bsp_dk_bcreg_3201.h

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00001 /**************************************************************************/
00035 #ifndef __BSP_DK_BCREG_3201_H
00036 #define __BSP_DK_BCREG_3201_H
00037 
00038 #include <stdint.h>
00039 
00040 /***************************************************************************/
00045 /***************************************************************************/
00050 #ifdef __cplusplus
00051 extern "C" {
00052 #endif
00053 
00054 /**************************************************************************/
00058 #define BC_REGISTER_BASE    0x80000000  
00059 #define BC_SSD2119_BASE     0x84000000  
00060 #define BC_PSRAM_BASE       0x88000000  
00061 #define BC_FLASH_BASE       0x8C000000  
00064 /**************************************************************************/
00068 /* Define registers in a similar manner to CMSIS standards */
00069 
00070 #define __IO    volatile
00071 
00073 typedef struct
00074 {
00075   __IO uint16_t RESERVERD0;        
00076   __IO uint16_t EM;                
00077   __IO uint16_t MAGIC;             
00079   __IO uint16_t UIF_LEDS;          
00080   __IO uint16_t UIF_PB;            
00081   __IO uint16_t UIF_DIP;           
00082   __IO uint16_t UIF_JOYSTICK;      
00083   __IO uint16_t UIF_AEM;           
00084   __IO uint16_t UIF_CTRL;          
00085   __IO uint16_t DISPLAY_CTRL;      
00086   __IO uint16_t EBI_CTRL;          
00087   __IO uint16_t ARB_CTRL;          
00088   __IO uint16_t PERICON;           
00089   __IO uint16_t SPI_DEMUX;         
00090   __IO uint16_t RESERVERD1[0x02];  
00092   __IO uint16_t ADC_WRITE;         
00093   __IO uint16_t ADC_STATUS;        
00094   __IO uint16_t ADC_READ;          
00096   __IO uint16_t CLKRST;            
00098   __IO uint16_t HW_VERSION;        
00099   __IO uint16_t FW_BUILDNO;        
00100   __IO uint16_t FW_VERSION;        
00102   __IO uint16_t SCRATCH_COMMON;    
00104   __IO uint16_t SCRATCH_EFM0;      
00105   __IO uint16_t SCRATCH_EFM1;      
00106   __IO uint16_t SCRATCH_EFM2;      
00107   __IO uint16_t SCRATCH_EFM3;      
00109   __IO uint16_t SCRATCH_BC0;       
00110   __IO uint16_t SCRATCH_BC1;       
00111   __IO uint16_t SCRATCH_BC2;       
00112   __IO uint16_t SCRATCH_BC3;       
00114   __IO uint16_t INTFLAG;           
00115   __IO uint16_t INTEN;             
00117   __IO uint16_t RESERVERD3[0x1e];  
00119   __IO uint16_t BC_MBOX_TXCTRL;    
00120   __IO uint16_t BC_MBOX_TXDATA;    
00121   __IO uint16_t BC_MBOX_TXSTATUS0; 
00122   __IO uint16_t BC_MBOX_TXSTATUS1; 
00124   __IO uint16_t RESERVED4[0x0d];   
00126   __IO uint16_t MBOX_TXCTRL;       
00127   __IO uint16_t MBOX_TXDATA;       
00128   __IO uint16_t MBOX_TXSTATUS0;    
00129   __IO uint16_t MBOX_TXSTATUS1;    
00131   __IO uint16_t RESERVED5[0x0b];   
00133   __IO uint16_t BUF_CTRL;          
00134 } BC_TypeDef;
00135 
00136 /* Cast into register structure */
00137 #define BC_REGISTER                         ((BC_TypeDef *) BC_REGISTER_BASE) 
00139 /* Energy Mode indicator */
00140 #define BC_EM_EM0                           (0)  
00141 #define BC_EM_EM1                           (1)  
00142 #define BC_EM_EM2                           (2)  
00143 #define BC_EM_EM3                           (3)  
00144 #define BC_EM_EM4                           (4)  
00146 /* Magic value */
00147 #define BC_MAGIC_VALUE                      (0xef32)  
00149 /* Push buttons, PB1-PB4 */
00150 #define BC_UIF_PB_MASK                      (0x000f) 
00151 #define BC_UIF_PB1                          (1 << 0) 
00152 #define BC_UIF_PB2                          (1 << 1) 
00153 #define BC_UIF_PB3                          (1 << 2) 
00154 #define BC_UIF_PB4                          (1 << 3) 
00156 /* Dip switch */
00157 #define BC_DIPSWITCH_MASK                   (0x000f)  
00159 /* Joystick directions */
00160 #define BC_UIF_JOYSTICK_MASK                (0x001f)      
00161 #define BC_UIF_JOYSTICK_DOWN                (1 << 0)      
00162 #define BC_UIF_JOYSTICK_RIGHT               (1 << 1)      
00163 #define BC_UIF_JOYSTICK_UP                  (1 << 2)      
00164 #define BC_UIF_JOYSTICK_LEFT                (1 << 3)      
00165 #define BC_UIF_JOYSTICK_CENTER              (1 << 4)      
00167 /* AEM state */
00168 #define BC_UIF_AEM_BC                       (0) 
00169 #define BC_UIF_AEM_EFM                      (1) 
00171 /* Display control */
00172 #define BC_DISPLAY_CTRL_RESET               (1 << 1)                          
00173 #define BC_DISPLAY_CTRL_POWER_ENABLE        (1 << 0)                          
00174 #define BC_DISPLAY_CTRL_MODE_SHIFT          2                                 
00175 #define BC_DISPLAY_CTRL_MODE_8080           (0 << BC_DISPLAY_CTRL_MODE_SHIFT) 
00176 #define BC_DISPLAY_CTRL_MODE_GENERIC        (1 << BC_DISPLAY_CTRL_MODE_SHIFT) 
00178 /* EBI control - extended address range enable bit  */
00179 #define BC_EBI_CTRL_EXTADDR_MASK            (0x0001) 
00181 /* Arbiter control - directs access to display controller  */
00182 #define BC_ARB_CTRL_SHIFT                   0                        
00183 #define BC_ARB_CTRL_BC                      (0 << BC_ARB_CTRL_SHIFT) 
00184 #define BC_ARB_CTRL_EBI                     (1 << BC_ARB_CTRL_SHIFT) 
00185 #define BC_ARB_CTRL_SPI                     (2 << BC_ARB_CTRL_SHIFT) 
00187 /* Interrupt flag registers, INTEN and INTFLAG */
00188 #define BC_INTEN_MASK                       (0x000f)  
00189 #define BC_INTEN_PB                         (1 << 0)  
00190 #define BC_INTEN_DIP                        (1 << 1)  
00191 #define BC_INTEN_JOYSTICK                   (1 << 2)  
00192 #define BC_INTEN_AEM                        (1 << 3)  
00193 #define BC_INTEN_ETH                        (1 << 4)  
00195 #define BC_INTFLAG_MASK                     (0x000f)  
00196 #define BC_INTFLAG_PB                       (1 << 0)  
00197 #define BC_INTFLAG_DIP                      (1 << 1)  
00198 #define BC_INTFLAG_JOYSTICK                 (1 << 2)  
00199 #define BC_INTFLAG_AEM                      (1 << 3)  
00200 #define BC_INTFLAG_ETH                      (1 << 4)  
00202 /* Peripheral control registers */
00203 #define BC_PERICON_RS232_SHUTDOWN_SHIFT     13 
00204 #define BC_PERICON_RS232_UART_SHIFT         12 
00205 #define BC_PERICON_RS232_LEUART_SHIFT       11 
00206 #define BC_PERICON_I2C_SHIFT                10 
00207 #define BC_PERICON_I2S_ETH_SEL_SHIFT        9  
00208 #define BC_PERICON_I2S_ETH_SHIFT            8  
00209 #define BC_PERICON_TRACE_SHIFT              7  
00210 #define BC_PERICON_TOUCH_SHIFT              6  
00211 #define BC_PERICON_AUDIO_IN_SHIFT           5  
00212 #define BC_PERICON_AUDIO_OUT_SEL_SHIFT      4  
00213 #define BC_PERICON_AUDIO_OUT_SHIFT          3  
00214 #define BC_PERICON_ANALOG_DIFF_SHIFT        2  
00215 #define BC_PERICON_ANALOG_SE_SHIFT          1  
00216 #define BC_PERICON_SPI_SHIFT                0  
00218 /* SPI DEMUX control */
00219 #define BC_SPI_DEMUX_SLAVE_MASK             (0x0003) 
00220 #define BC_SPI_DEMUX_SLAVE_AUDIO            (0)      
00221 #define BC_SPI_DEMUX_SLAVE_ETHERNET         (1)      
00222 #define BC_SPI_DEMUX_SLAVE_DISPLAY          (2)      
00224 /* ADC */
00225 #define BC_ADC_STATUS_DONE                  (0)  
00226 #define BC_ADC_STATUS_BUSY                  (1)  
00228 /* Clock and Reset Control */
00229 #define BC_CLKRST_FLASH_SHIFT               (1 << 1) 
00230 #define BC_CLKRST_ETH_SHIFT                 (1 << 2) 
00232 /* Hardware version information */
00233 #define BC_HW_VERSION_PCB_MASK              (0x07f0)  
00234 #define BC_HW_VERSION_PCB_SHIFT             (4)       
00235 #define BC_HW_VERSION_BOARD_MASK            (0x000f)  
00236 #define BC_HW_VERSION_BOARD_SHIFT           (0)       
00238 /* Firmware version information */
00239 #define BC_FW_VERSION_MAJOR_MASK            (0xf000) 
00240 #define BC_FW_VERSION_MAJOR_SHIFT           (12)     
00241 #define BC_FW_VERSION_MINOR_MASK            (0x0f00) 
00242 #define BC_FW_VERSION_MINOR_SHIFT           (8)      
00243 #define BC_FW_VERSION_PATCHLEVEL_MASK       (0x00ff) 
00244 #define BC_FW_VERSION_PATCHLEVEL_SHIFT      (0)      
00246 /* MBOX - BC <-> EFM32 communication */
00247 #define BC_MBOX_TXSTATUS0_FIFOEMPTY         (1 << 0) 
00248 #define BC_MBOX_TXSTATUS0_FIFOFULL          (1 << 1) 
00249 #define BC_MBOX_TXSTATUS0_FIFOUNDERFLOW     (1 << 4) 
00250 #define BC_MBOX_TXSTATUS0_FIFOOVERFLOW      (1 << 5) 
00252 #define BC_MBOX_TXSTATUS1_WORDCOUNT_MASK    (0x07FF) 
00254 /* Buffer Controller */
00255 #define BC_BUF_CTRL_CS_ENABLE               (1 << 0) 
00257 #ifdef __cplusplus
00258 }
00259 #endif
00260 
00264 #endif  /* __BSP_DK_BCREG_3201_H */