ksz8851snl.h
Go to the documentation of this file.00001
00035 #ifndef _ksz8851snl_H_
00036 #define _ksz8851snl_H_
00037
00038
00043
00052 #include <stdint.h>
00053 #include <stdbool.h>
00054
00055 #ifdef __cplusplus
00056 extern "C" {
00057 #endif
00058
00060 #define KSZ8851SNL_DEBUG 0
00061 #if KSZ8851SNL_DEBUG
00062
00063 #define DEBUG_PRINT(...) printf(__VA_ARGS__)
00064 #define DIGITAL_PHY_LOOPBACK
00065 #define DUMP_REGS
00066 #else
00067
00068 #define DEBUG_PRINT(...) (void)0
00069 #endif
00070
00071
00072 #define LOW_QMU_MAC_REG 0x10
00073 #define MID_QMU_MAC_REG 0x12
00074 #define HIGH_QMU_MAC_REG 0x14
00075 #define OBC_REG 0x20
00076 #define GLOBAL_RESET_REG 0x26
00077 #define TX_FLOW_CTRL_REG 0x70
00078 #define RX_FLOW_CTRL1_REG 0x74
00079 #define RX_FLOW_CTRL2_REG 0x76
00080 #define TX_MEM_INFO_REG 0x78
00081 #define RX_FRH_STAT_REG 0x7C
00082 #define RX_FRH_BC_REG 0x7E
00083 #define TXQ_CMD_REG 0x80
00084 #define RXQ_CMD_REG 0x82
00085 #define TX_FD_PTR_REG 0x84
00086 #define RX_FD_PTR_REG 0x86
00087 #define INT_ENABLE_REG 0x90
00088 #define INT_STATUS_REG 0x92
00089 #define RX_FRAME_THRES_REG 0x9C
00090 #define TX_NEXT_FRS_REG 0x9E
00091 #define FLOW_CTRL_LOW_WATERMARK 0xB0
00092 #define FLOW_CTRL_HIGH_WATERMARK 0xB2
00093 #define CIDER_REG 0xC0
00094 #define IND_ACC_CTRL_REG 0xC8
00095 #define IND_ACC_DATA_LOW_REG 0xD0
00096 #define IND_ACC_DATA_HIGH_REG 0xD2
00097 #define PHY_RST_REG 0xD8
00098 #define PHY1_CTRL_REG 0xE4
00099 #define PORT1_CTRL_REG 0xF6
00101
00102 #define KSZ8851SNL_CHIP_ID 0x8870
00103 #define CHIP_ID_MASK 0xFFF0
00104 #define ONE_FRAME_THRES 0x0001
00105 #define FD_PTR_AUTO_INC 0x4000
00106 #define CLEAR_INT 0xFFFF
00107 #define NO_INT 0x0000
00108 #define TX_MEM_AVAIL_MASK 0x1FFF
00109 #define frameId_MASK 0x003F
00110 #define RECEIVE_VALID_FRAME_MASK 0x3C17
00113 #define RECEIVED_FRAME_VALID_POS 0x0010
00114 #define RX_BYTE_CNT_MASK 0x0FFF
00115 #define LSB_MASK 0x00FF
00116 #define MSB_POS 0x0008
00117 #define TX_INT_on_COMPLETION 0x8000
00118 #define WORD_SIZE 0x0004
00119 #define EXTRA_SIZE 0x0008
00120 #define BLOCKING_RECEIVE 0
00121 #define WATERMARK_6KB 0x0600
00122 #define WATERMARK_4KB 0x0400
00123
00124 #define HIGH_QMU_MAC_H 0xD0
00125 #define HIGH_QMU_MAC_L 0xCF
00126 #define MID_QMU_MAC_H 0x5E
00127 #define MID_QMU_MAC_L 0x00
00128 #define LOW_QMU_MAC_H 0x00
00129 #define LOW_QMU_MAC_L 0x00
00130 #define BYTE_MASK 0x00FF
00131 #define BYTE_SIZE 0x0008
00133
00134
00136 #define TX_FLOW_CTRL_ICMP_CHECKSUM 0x0100
00137
00138 #define TX_FLOW_CTRL_UDP_CHECKSUM 0x0080
00139
00140 #define TX_FLOW_CTRL_TCP_CHECKSUM 0x0040
00141
00142 #define TX_FLOW_CTRL_IP_CHECKSUM 0x0020
00143
00144 #define TX_FLOW_CTRL_FLUSH_QUEUE 0x0010
00145
00146 #define TX_FLOW_CTRL_FLOW_ENABLE 0x0008
00147
00148 #define TX_FLOW_CTRL_PAD_ENABLE 0x0004
00149
00150 #define TX_FLOW_CTRL_CRC_ENABLE 0x0002
00151
00152 #define TX_FLOW_CTRL_ENABLE 0x0001
00153
00155 #define TX_FLOW_CTRL_EXAMPLE (TX_FLOW_CTRL_ICMP_CHECKSUM | \
00156 TX_FLOW_CTRL_UDP_CHECKSUM | \
00157 TX_FLOW_CTRL_TCP_CHECKSUM | \
00158 TX_FLOW_CTRL_IP_CHECKSUM | \
00159 TX_FLOW_CTRL_FLOW_ENABLE | \
00160 TX_FLOW_CTRL_PAD_ENABLE | \
00161 TX_FLOW_CTRL_CRC_ENABLE)
00162
00163
00165 #define TXQ_AUTO_ENQUEUE 0x0004
00166
00167 #define TXQ_MEM_AVAILABLE_INT 0x0002
00168
00169 #define TXQ_ENQUEUE 0x0001
00170
00171
00172
00174 #define RX_FLOW_CTRL_FLUSH_QUEUE 0x8000
00175
00176 #define RX_FLOW_CTRL_UDP_CHECKSUM 0x4000
00177
00178 #define RX_FLOW_CTRL_TCP_CHECKSUM 0x2000
00179
00180 #define RX_FLOW_CTRL_IP_CHECKSUM 0x1000
00181
00182 #define RX_FLOW_CTRL_MAC_FILTER 0x0800
00183
00184 #define RX_FLOW_CTRL_FLOW_ENABLE 0x0400
00185
00186 #define RX_FLOW_CTRL_BAD_PACKET 0x0200
00187
00188 #define RX_FLOW_CTRL_MULTICAST 0x0100
00189
00190 #define RX_FLOW_CTRL_BROADCAST 0x0080
00191
00192 #define RX_FLOW_CTRL_ALL_MULTICAST 0x0040
00193
00194 #define RX_FLOW_CTRL_UNICAST 0x0020
00195
00196 #define RX_FLOW_CTRL_PROMISCUOUS 0x0012
00197
00198 #define RX_FLOW_CTRL_INVERSE_FILTER 0x0002
00199
00200 #define RX_FLOW_CTRL_ENABLE 0x0001
00201
00203 #define RX_FLOW_CTRL1_EXAMPLE (RX_FLOW_CTRL_UDP_CHECKSUM | \
00204 RX_FLOW_CTRL_TCP_CHECKSUM | \
00205 RX_FLOW_CTRL_IP_CHECKSUM | \
00206 RX_FLOW_CTRL_MAC_FILTER | \
00207 RX_FLOW_CTRL_FLOW_ENABLE | \
00208 RX_FLOW_CTRL_BROADCAST | \
00209 RX_FLOW_CTRL_ALL_MULTICAST | \
00210 RX_FLOW_CTRL_UNICAST)
00211
00212
00213
00215 #define RX_FLOW_CTRL_BURST_LEN_MASK 0x00E0
00216
00217 #define RX_FLOW_CTRL_BURST_LEN_4 0x0000
00218
00219 #define RX_FLOW_CTRL_BURST_LEN_8 0x0020
00220
00221 #define RX_FLOW_CTRL_BURST_LEN_16 0x0040
00222
00223 #define RX_FLOW_CTRL_BURST_LEN_32 0x0060
00224
00225 #define RX_FLOW_CTRL_BURST_LEN_FRAME 0x0080
00226
00227 #define RX_FLOW_CTRL_IPV6_UDP_FRAG_PASS 0x0010
00228
00229 #define RX_FLOW_CTRL_IPV6_UDP_ZERO_PASS 0x0008
00230
00231 #define RX_FLOW_CTRL_UDP_LITE_CHECKSUM 0x0004
00232
00233 #define RX_FLOW_CTRL_ICMP_CHECKSUM 0x0002
00234
00235 #define RX_FLOW_CTRL_BLOCK_MAC 0x0001
00236
00238 #define RX_FLOW_CTRL2_EXAMPLE (RX_FLOW_CTRL_IPV6_UDP_FRAG_PASS | \
00239 RX_FLOW_CTRL_UDP_LITE_CHECKSUM | \
00240 RX_FLOW_CTRL_ICMP_CHECKSUM | \
00241 RX_FLOW_CTRL_BURST_LEN_FRAME)
00242
00243
00245 #define RXQ_ON_TIME_INT 0x1000
00246
00247 #define RXQ_ON_BYTE_CNT_INT 0x0800
00248
00249 #define RXQ_ON_FRAME_CNT_INT 0x0400
00250
00251 #define RXQ_TWOBYTE_OFFSET 0x0200
00252
00253 #define RXQ_EN_ON_TIME_INT 0x0080
00254
00255 #define RXQ_EN_ON_BYTE_CNT_INT 0x0040
00256
00257 #define RXQ_EN_ON_FRAME_CNT_INT 0x0020
00258
00259 #define RXQ_AUTO_DEQUEUE 0x0010
00260
00261 #define RXQ_START 0x0008
00262
00263 #define RXQ_RELEASE_CUR_FR 0x0001
00264
00266 #define RXQ_CMD_EXAMPLE (RXQ_EN_ON_FRAME_CNT_INT | \
00267 RXQ_TWOBYTE_OFFSET | \
00268 RXQ_AUTO_DEQUEUE)
00269
00270
00272 #define PORT1_LED_OFF 0x8000
00273
00274 #define PORT1_TX_DISABLE 0x4000
00275
00276 #define PORT1_AUTO_NEG_RESTART 0x2000
00277
00278 #define PORT1_POWER_DOWN 0x0800
00279
00280 #define PORT1_AUTO_MDIX_DISABLE 0x0400
00281
00282 #define PORT1_FORCE_MDIX 0x0200
00283
00284 #define PORT1_AUTO_NEG_ENABLE 0x0080
00285
00286 #define PORT1_FORCE_100_MBIT 0x0040
00287
00288 #define PORT1_FORCE_FULL_DUPLEX 0x0020
00289
00290 #define PORT1_AUTO_NEG_SYM_PAUSE 0x0010
00291
00292 #define PORT1_AUTO_NEG_100BTX_FD 0x0008
00293
00294 #define PORT1_AUTO_NEG_100BTX 0x0004
00295
00296 #define PORT1_AUTO_NEG_10BT_FD 0x0002
00297
00298 #define PORT1_AUTO_NEG_10BT 0x0001
00299
00300
00302 #define INT_LINK_CHANGE 0x8000
00303
00304 #define INT_TX_DONE 0x4000
00305
00306 #define INT_RX_DONE 0x2000
00307
00308 #define INT_RX_OVERRUN 0x0800
00309
00310 #define INT_TX_STOPPED 0x0200
00311
00312 #define INT_RX_STOPPED 0x0100
00313
00314 #define INT_TX_SPACE 0x0040
00315
00316 #define INT_RX_WOL_FRAME 0x0020
00317
00318 #define INT_MAGIC 0x0010
00319
00320 #define INT_LINKUP 0x0008
00321
00322 #define INT_ENERGY 0x0004
00323
00324 #define INT_SPI_ERROR 0x0002
00325
00327 #define INT_MASK_EXAMPLE (INT_RX_DONE | \
00328 INT_RX_OVERRUN | \
00329 INT_TX_STOPPED | \
00330 INT_RX_STOPPED | \
00331 INT_TX_DONE | \
00332 INT_LINK_CHANGE)
00333
00334
00336 #define QMU_MODULE_SOFT_RESET 0x0002
00337
00338 #define GLOBAL_SOFT_RESET 0x0001
00339
00341 #define PHY_RESET 0x0001
00342
00343
00345 #define DIGITAL_LOOPBACK 0x4000
00346
00347 #define FORCE_100 0x2000
00348
00349 #define AUTO_NEG 0x1000
00350
00351 #define RESTART_AUTO_NEG 0x0200
00352
00353 #define FORCE_FULL_DUPLEX 0x0100
00354
00355
00356 #define MIB_MASK 0x1C00
00357 #define MIB_RxByte 0x00
00358 #define MIB_XXX 0x01
00359 #define MIB_RxUndersizePkt 0x02
00360 #define MIB_RxFragments 0x03
00361 #define MIB_RxOversize 0x04
00362 #define MIB_RxJabbers 0x05
00363 #define MIB_RxSynbolError 0x06
00364 #define MIB_RxCRCError 0x07
00365 #define MIB_RxAlignmentError 0x08
00366 #define MIB_RxControl8808Pkts 0x09
00367 #define MIB_RxPausePkts 0x0A
00368 #define MIB_RxBroadcast 0x0B
00369 #define MIB_RxMulticast 0x0C
00370 #define MIB_RxUnicast 0x0D
00371 #define MIB_Rx64Octets 0x0E
00372 #define MIB_Rx65to127Octets 0x0F
00373 #define MIB_Rx128to255Octets 0x10
00374 #define MIB_Rx256to511Octets 0x11
00375 #define MIB_Rx512to1023Octets 0x12
00376 #define MIB_Rx1024to1521Octets 0x13
00377 #define MIB_Rx1522to2000Octets 0x14
00378 #define MIB_TxByte 0x15
00379 #define MIB_TxLateCollision 0x16
00380 #define MIB_TxPausePkts 0x17
00381 #define MIB_TxBroadcastPkts 0x18
00382 #define MIB_TxMulticastPkts 0x19
00383 #define MIB_TxUnicastPkts 0x1A
00384 #define MIB_TxDeferred 0x1B
00385 #define MIB_TxTotalCollision 0x1C
00386 #define MIB_TxExcessiveCollision 0x1D
00387 #define MIB_TxSingleCollision 0x1E
00388 #define MIB_TxMultipleCollision 0x1F
00391 enum exceptionType_e
00392 {
00393 ERROR,
00394 INFO
00395 };
00396
00397 void KSZ8851SNL_Init(void);
00398 void KSZ8851SNL_Send(uint16_t packetLength, uint8_t *packetData);
00399 uint16_t KSZ8851SNL_Receive(uint8_t *pRXData, uint16_t *pRXLength);
00400 void KSZ8851SNL_GetMacAddress(uint8_t *macAddress);
00401 void KSZ8851SNL_ReadMIBCounters(char* param);
00402 uint16_t KSZ8851SNL_CheckIrqStat(void);
00403 uint16_t KSZ8851SNL_CurrFrameSize(void);
00404 void KSZ8851SNL_TerminateLongTransmit(uint16_t pTXLength, uint8_t *pTXData);
00405 void KSZ8851SNL_InitiateLongTransmit(uint16_t pTXLength);
00406 void KSZ8851SNL_LongTransmit(uint16_t pTXLength, uint8_t *pTXData);
00407 void KSZ8851SNL_EnableInterupts(void);
00408
00409
00410 #ifdef __cplusplus
00411 }
00412 #endif
00413
00417 #endif