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Defines | |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 3 |
#define | __Vendor_SysTickConfig 0 |
#define | _EFM32_GIANT_FAMILY 1 |
#define | _EFM_DEVICE |
#define | EFM32GG995F1024 1 |
#define | PART_NUMBER "EFM32GG995F1024" |
#define | FLASH_MEM_BASE ((uint32_t) 0x0UL) |
#define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) |
#define | FLASH_MEM_BITS ((uint32_t) 0x28UL) |
#define | AES_MEM_BASE ((uint32_t) 0x400E0000UL) |
#define | AES_MEM_SIZE ((uint32_t) 0x400UL) |
#define | AES_MEM_END ((uint32_t) 0x400E03FFUL) |
#define | AES_MEM_BITS ((uint32_t) 0x10UL) |
#define | USBC_MEM_BASE ((uint32_t) 0x40100000UL) |
#define | USBC_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | USBC_MEM_END ((uint32_t) 0x4013FFFFUL) |
#define | USBC_MEM_BITS ((uint32_t) 0x18UL) |
#define | EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) |
#define | EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) |
#define | EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) |
#define | EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) |
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
#define | PER_MEM_SIZE ((uint32_t) 0xE0000UL) |
#define | PER_MEM_END ((uint32_t) 0x400DFFFFUL) |
#define | PER_MEM_BITS ((uint32_t) 0x20UL) |
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | RAM_MEM_END ((uint32_t) 0x2003FFFFUL) |
#define | RAM_MEM_BITS ((uint32_t) 0x18UL) |
#define | RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
#define | RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
#define | RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) |
#define | RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) |
#define | EBI_MEM_BASE ((uint32_t) 0x80000000UL) |
#define | EBI_MEM_SIZE ((uint32_t) 0x40000000UL) |
#define | EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) |
#define | EBI_MEM_BITS ((uint32_t) 0x30UL) |
#define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
#define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
#define | FLASH_BASE (0x00000000UL) |
#define | FLASH_SIZE (0x00100000UL) |
#define | FLASH_PAGE_SIZE 4096 |
#define | SRAM_BASE (0x20000000UL) |
#define | SRAM_SIZE (0x00020000UL) |
#define | __CM3_REV 0x201 |
#define | PRS_CHAN_COUNT 12 |
#define | DMA_CHAN_COUNT 12 |
#define | AFCHAN_MAX 163 |
#define | AFCHANLOC_MAX 7 |
#define | AFACHAN_MAX 53 |
#define | LETIMER_PRESENT |
#define | LETIMER_COUNT 1 |
#define | USART_PRESENT |
#define | USART_COUNT 3 |
#define | UART_PRESENT |
#define | UART_COUNT 2 |
#define | TIMER_PRESENT |
#define | TIMER_COUNT 4 |
#define | ACMP_PRESENT |
#define | ACMP_COUNT 2 |
#define | I2C_PRESENT |
#define | I2C_COUNT 2 |
#define | LEUART_PRESENT |
#define | LEUART_COUNT 2 |
#define | PCNT_PRESENT |
#define | PCNT_COUNT 3 |
#define | ADC_PRESENT |
#define | ADC_COUNT 1 |
#define | DAC_PRESENT |
#define | DAC_COUNT 1 |
#define | DMA_PRESENT |
#define | DMA_COUNT 1 |
#define | AES_PRESENT |
#define | AES_COUNT 1 |
#define | USBC_PRESENT |
#define | USBC_COUNT 1 |
#define | USB_PRESENT |
#define | USB_COUNT 1 |
#define | LE_PRESENT |
#define | LE_COUNT 1 |
#define | MSC_PRESENT |
#define | MSC_COUNT 1 |
#define | EMU_PRESENT |
#define | EMU_COUNT 1 |
#define | RMU_PRESENT |
#define | RMU_COUNT 1 |
#define | CMU_PRESENT |
#define | CMU_COUNT 1 |
#define | LESENSE_PRESENT |
#define | LESENSE_COUNT 1 |
#define | RTC_PRESENT |
#define | RTC_COUNT 1 |
#define | EBI_PRESENT |
#define | EBI_COUNT 1 |
#define | GPIO_PRESENT |
#define | GPIO_COUNT 1 |
#define | VCMP_PRESENT |
#define | VCMP_COUNT 1 |
#define | PRS_PRESENT |
#define | PRS_COUNT 1 |
#define | OPAMP_PRESENT |
#define | OPAMP_COUNT 1 |
#define | BU_PRESENT |
#define | BU_COUNT 1 |
#define | LCD_PRESENT |
#define | LCD_COUNT 1 |
#define | BURTC_PRESENT |
#define | BURTC_COUNT 1 |
#define | HFXTAL_PRESENT |
#define | HFXTAL_COUNT 1 |
#define | LFXTAL_PRESENT |
#define | LFXTAL_COUNT 1 |
#define | WDOG_PRESENT |
#define | WDOG_COUNT 1 |
#define | DBG_PRESENT |
#define | DBG_COUNT 1 |
#define | ETM_PRESENT |
#define | ETM_COUNT 1 |
#define | BOOTLOADER_PRESENT |
#define | BOOTLOADER_COUNT 1 |
#define | ANALOG_PRESENT |
#define | ANALOG_COUNT 1 |
#define | DMA_BASE (0x400C2000UL) |
#define | AES_BASE (0x400E0000UL) |
#define | USB_BASE (0x400C4000UL) |
#define | MSC_BASE (0x400C0000UL) |
#define | EMU_BASE (0x400C6000UL) |
#define | RMU_BASE (0x400CA000UL) |
#define | CMU_BASE (0x400C8000UL) |
#define | LESENSE_BASE (0x4008C000UL) |
#define | RTC_BASE (0x40080000UL) |
#define | LETIMER0_BASE (0x40082000UL) |
#define | EBI_BASE (0x40008000UL) |
#define | USART0_BASE (0x4000C000UL) |
#define | USART1_BASE (0x4000C400UL) |
#define | USART2_BASE (0x4000C800UL) |
#define | UART0_BASE (0x4000E000UL) |
#define | UART1_BASE (0x4000E400UL) |
#define | TIMER0_BASE (0x40010000UL) |
#define | TIMER1_BASE (0x40010400UL) |
#define | TIMER2_BASE (0x40010800UL) |
#define | TIMER3_BASE (0x40010C00UL) |
#define | ACMP0_BASE (0x40001000UL) |
#define | ACMP1_BASE (0x40001400UL) |
#define | I2C0_BASE (0x4000A000UL) |
#define | I2C1_BASE (0x4000A400UL) |
#define | GPIO_BASE (0x40006000UL) |
#define | VCMP_BASE (0x40000000UL) |
#define | PRS_BASE (0x400CC000UL) |
#define | LEUART0_BASE (0x40084000UL) |
#define | LEUART1_BASE (0x40084400UL) |
#define | PCNT0_BASE (0x40086000UL) |
#define | PCNT1_BASE (0x40086400UL) |
#define | PCNT2_BASE (0x40086800UL) |
#define | ADC0_BASE (0x40002000UL) |
#define | DAC0_BASE (0x40004000UL) |
#define | LCD_BASE (0x4008A000UL) |
#define | BURTC_BASE (0x40081000UL) |
#define | WDOG_BASE (0x40088000UL) |
#define | ETM_BASE (0xE0041000UL) |
#define | CALIBRATE_BASE (0x0FE08000UL) |
#define | DEVINFO_BASE (0x0FE081B0UL) |
#define | ROMTABLE_BASE (0xE00FFFD0UL) |
#define | LOCKBITS_BASE (0x0FE04000UL) |
#define | USERDATA_BASE (0x0FE00000UL) |
#define | DMA ((DMA_TypeDef *) DMA_BASE) |
#define | AES ((AES_TypeDef *) AES_BASE) |
#define | USB ((USB_TypeDef *) USB_BASE) |
#define | MSC ((MSC_TypeDef *) MSC_BASE) |
#define | EMU ((EMU_TypeDef *) EMU_BASE) |
#define | RMU ((RMU_TypeDef *) RMU_BASE) |
#define | CMU ((CMU_TypeDef *) CMU_BASE) |
#define | LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) |
#define | EBI ((EBI_TypeDef *) EBI_BASE) |
#define | USART0 ((USART_TypeDef *) USART0_BASE) |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | USART2 ((USART_TypeDef *) USART2_BASE) |
#define | UART0 ((USART_TypeDef *) UART0_BASE) |
#define | UART1 ((USART_TypeDef *) UART1_BASE) |
#define | TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) |
#define | TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) |
#define | TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) |
#define | TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) |
#define | ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) |
#define | ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) |
#define | I2C0 ((I2C_TypeDef *) I2C0_BASE) |
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define | GPIO ((GPIO_TypeDef *) GPIO_BASE) |
#define | VCMP ((VCMP_TypeDef *) VCMP_BASE) |
#define | PRS ((PRS_TypeDef *) PRS_BASE) |
#define | LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) |
#define | LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) |
#define | PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) |
#define | PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) |
#define | PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) |
#define | ADC0 ((ADC_TypeDef *) ADC0_BASE) |
#define | DAC0 ((DAC_TypeDef *) DAC0_BASE) |
#define | LCD ((LCD_TypeDef *) LCD_BASE) |
#define | BURTC ((BURTC_TypeDef *) BURTC_BASE) |
#define | WDOG ((WDOG_TypeDef *) WDOG_BASE) |
#define | ETM ((ETM_TypeDef *) ETM_BASE) |
#define | CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) |
#define | DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) |
#define | ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) |
#define | MSC_UNLOCK_CODE 0x1B71 |
#define | EMU_UNLOCK_CODE 0xADE8 |
#define | CMU_UNLOCK_CODE 0x580E |
#define | TIMER_UNLOCK_CODE 0xCE80 |
#define | GPIO_UNLOCK_CODE 0xA534 |
#define | BURTC_UNLOCK_CODE 0xAEE8 |
#define | SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register. | |
Typedefs | |
typedef enum IRQn | IRQn_Type |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, USART0_RX_IRQn = 3, USART0_TX_IRQn = 4, USB_IRQn = 5, ACMP0_IRQn = 6, ADC0_IRQn = 7, DAC0_IRQn = 8, I2C0_IRQn = 9, I2C1_IRQn = 10, GPIO_ODD_IRQn = 11, TIMER1_IRQn = 12, TIMER2_IRQn = 13, TIMER3_IRQn = 14, USART1_RX_IRQn = 15, USART1_TX_IRQn = 16, LESENSE_IRQn = 17, USART2_RX_IRQn = 18, USART2_TX_IRQn = 19, UART0_RX_IRQn = 20, UART0_TX_IRQn = 21, UART1_RX_IRQn = 22, UART1_TX_IRQn = 23, LEUART0_IRQn = 24, LEUART1_IRQn = 25, LETIMER0_IRQn = 26, PCNT0_IRQn = 27, PCNT1_IRQn = 28, PCNT2_IRQn = 29, RTC_IRQn = 30, BURTC_IRQn = 31, CMU_IRQn = 32, VCMP_IRQn = 33, LCD_IRQn = 34, MSC_IRQn = 35, AES_IRQn = 36, EBI_IRQn = 37, EMU_IRQn = 38 } |
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file efm32gg995f1024.h.