em_emu.h
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00034 #ifndef __EM_EMU_H
00035 #define __EM_EMU_H
00036
00037 #include "em_device.h"
00038 #if defined( EMU_PRESENT )
00039
00040 #include <stdbool.h>
00041 #include "em_bitband.h"
00042
00043 #ifdef __cplusplus
00044 extern "C" {
00045 #endif
00046
00047
00052
00057
00058
00059
00060
00061 #if defined( _EMU_EM4CONF_MASK )
00062
00063 typedef enum
00064 {
00066 emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
00068 emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
00070 emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
00071 } EMU_EM4Osc_TypeDef;
00072
00074 typedef enum
00075 {
00077 emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
00079 emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
00081 emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN,
00083 emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT
00084 } EMU_Probe_TypeDef;
00085
00087 typedef enum
00088 {
00090 emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
00092 emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
00094 emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
00096 emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
00097 } EMU_Resistor_TypeDef;
00098
00100 typedef enum
00101 {
00103 emuPower_None = EMU_BUINACT_PWRCON_NONE,
00106 emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
00109 emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
00111 emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
00112 } EMU_Power_TypeDef;
00113
00115 typedef enum
00116 {
00118 emuBODMode_Active,
00120 emuBODMode_Inactive,
00121 } EMU_BODMode_TypeDef;
00122
00123
00124
00125
00126
00128 typedef struct
00129 {
00131 bool lockConfig;
00133 EMU_EM4Osc_TypeDef osc;
00135 bool buRtcWakeup;
00137 bool vreg;
00138 } EMU_EM4Init_TypeDef;
00139
00141 #define EMU_EM4INIT_DEFAULT \
00142 { false, \
00143 emuEM4Osc_ULFRCO, \
00144 true, \
00145 true, \
00146 }
00147
00149 typedef struct
00150 {
00151
00152
00154 EMU_Probe_TypeDef probe;
00156 bool bodCal;
00158 bool statusPinEnable;
00159
00160
00162 EMU_Resistor_TypeDef resistor;
00164 bool voutStrong;
00166 bool voutMed;
00168 bool voutWeak;
00170 EMU_Power_TypeDef inactivePower;
00172 EMU_Power_TypeDef activePower;
00174 bool enable;
00175 } EMU_BUPDInit_TypeDef;
00176
00178 #define EMU_BUPDINIT_DEFAULT \
00179 { emuProbe_Disable, \
00180 false, \
00181 false, \
00182 \
00183 emuRes_Res0, \
00184 false, \
00185 false, \
00186 false, \
00187 \
00188 emuPower_None, \
00189 emuPower_None, \
00190 true \
00191 }
00192 #endif
00193
00194
00195
00196
00197
00198
00202 __STATIC_INLINE void EMU_EnterEM1(void)
00203 {
00204
00205 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
00206 __WFI();
00207 }
00208
00209
00210 void EMU_EnterEM2(bool restore);
00211 void EMU_EnterEM3(bool restore);
00212 void EMU_EnterEM4(void);
00213 void EMU_MemPwrDown(uint32_t blocks);
00214 void EMU_UpdateOscConfig(void);
00215 #if defined( _EMU_EM4CONF_MASK )
00216 void EMU_EM4Init(EMU_EM4Init_TypeDef *em4init);
00217 void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit);
00218 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
00219 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
00220
00221
00227 __STATIC_INLINE void EMU_EM4Lock(bool enable)
00228 {
00229 BITBAND_Peripheral(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
00230 }
00231
00232
00236 __STATIC_INLINE void EMU_BUReady(void)
00237 {
00238 while(!(EMU->STATUS & EMU_STATUS_BURDY));
00239 }
00240
00241
00247 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
00248 {
00249 BITBAND_Peripheral(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
00250 }
00251 #endif
00252
00253
00264 __STATIC_INLINE void EMU_Lock(void)
00265 {
00266 EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK;
00267 }
00268
00269
00270
00274 __STATIC_INLINE void EMU_Unlock(void)
00275 {
00276 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
00277 }
00278
00279
00283 __STATIC_INLINE void EMU_EM2Block(void)
00284 {
00285 BITBAND_Peripheral(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
00286 }
00287
00288
00292 __STATIC_INLINE void EMU_EM2UnBlock(void)
00293 {
00294 BITBAND_Peripheral(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
00295 }
00296
00297
00301 #ifdef __cplusplus
00302 }
00303 #endif
00304
00305 #endif
00306 #endif