release/EM_CMSIS_3.20.6/Device/SiliconLabs/EFM32GG/Include/efm32gg_cmu.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __IO uint32_t CTRL;         
00040   __IO uint32_t HFCORECLKDIV; 
00041   __IO uint32_t HFPERCLKDIV;  
00042   __IO uint32_t HFRCOCTRL;    
00043   __IO uint32_t LFRCOCTRL;    
00044   __IO uint32_t AUXHFRCOCTRL; 
00045   __IO uint32_t CALCTRL;      
00046   __IO uint32_t CALCNT;       
00047   __IO uint32_t OSCENCMD;     
00048   __IO uint32_t CMD;          
00049   __IO uint32_t LFCLKSEL;     
00050   __I uint32_t  STATUS;       
00051   __I uint32_t  IF;           
00052   __IO uint32_t IFS;          
00053   __IO uint32_t IFC;          
00054   __IO uint32_t IEN;          
00055   __IO uint32_t HFCORECLKEN0; 
00056   __IO uint32_t HFPERCLKEN0;  
00057   uint32_t      RESERVED0[2]; 
00058   __I uint32_t  SYNCBUSY;     
00059   __IO uint32_t FREEZE;       
00060   __IO uint32_t LFACLKEN0;    
00061   uint32_t      RESERVED1[1]; 
00062   __IO uint32_t LFBCLKEN0;    
00063   uint32_t      RESERVED2[1]; 
00064   __IO uint32_t LFAPRESC0;    
00065   uint32_t      RESERVED3[1]; 
00066   __IO uint32_t LFBPRESC0;    
00067   uint32_t      RESERVED4[1]; 
00068   __IO uint32_t PCNTCTRL;     
00069   __IO uint32_t LCDCTRL;      
00070   __IO uint32_t ROUTE;        
00071   __IO uint32_t LOCK;         
00072 } CMU_TypeDef;                
00074 /**************************************************************************/
00079 /* Bit fields for CMU CTRL */
00080 #define _CMU_CTRL_RESETVALUE                        0x000C062CUL                                
00081 #define _CMU_CTRL_MASK                              0x53FFFEEFUL                                
00082 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           
00083 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       
00084 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                
00085 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                                
00086 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                                
00087 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                                
00088 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)           
00089 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)              
00090 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)         
00091 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)         
00092 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                           
00093 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                       
00094 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                                
00095 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                                
00096 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                                
00097 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                                
00098 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                                
00099 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)          
00100 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)          
00101 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)          
00102 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)          
00103 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)         
00104 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                           
00105 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                      
00106 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                                
00107 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ         0x00000001UL                                
00108 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ        0x00000003UL                                
00109 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)         
00110 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ          (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)  
00111 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ         (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) 
00112 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                                
00113 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                           
00114 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                      
00115 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                                
00116 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)    
00117 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                           
00118 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                     
00119 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                                
00120 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                                
00121 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                                
00122 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                                
00123 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                                
00124 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)        
00125 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)      
00126 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)       
00127 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)        
00128 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)      
00129 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                          
00130 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                    
00131 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                                
00132 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                                
00133 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                                
00134 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                                
00135 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)          
00136 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)             
00137 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)        
00138 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)        
00139 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                               
00140 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                          
00141 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                    
00142 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                                
00143 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                                
00144 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                                
00145 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)         
00146 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)         
00147 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)        
00148 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                          
00149 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                   
00150 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                                
00151 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)          
00152 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                               
00153 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                          
00154 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                   
00155 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                                
00156 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)        
00157 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                          
00158 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                   
00159 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                                
00160 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                                
00161 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                                
00162 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                                
00163 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                                
00164 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)       
00165 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)      
00166 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)     
00167 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)       
00168 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)     
00169 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                          
00170 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                                  
00171 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                                
00172 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                                
00173 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                                
00174 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                                
00175 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                                
00176 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                                
00177 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                                
00178 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                                
00179 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                                
00180 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)        
00181 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)          
00182 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)           
00183 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)         
00184 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)         
00185 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)         
00186 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)        
00187 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         
00188 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       
00189 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          
00190 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 
00191 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                
00192 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                
00193 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                
00194 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                                
00195 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                                
00196 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                                
00197 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                                
00198 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                                
00199 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                                
00200 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)        
00201 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)          
00202 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)           
00203 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)          
00204 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)          
00205 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)          
00206 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)         
00207 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)         
00208 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)      
00209 #define CMU_CTRL_DBGCLK                             (0x1UL << 28)                               
00210 #define _CMU_CTRL_DBGCLK_SHIFT                      28                                          
00211 #define _CMU_CTRL_DBGCLK_MASK                       0x10000000UL                                
00212 #define _CMU_CTRL_DBGCLK_DEFAULT                    0x00000000UL                                
00213 #define _CMU_CTRL_DBGCLK_AUXHFRCO                   0x00000000UL                                
00214 #define _CMU_CTRL_DBGCLK_HFCLK                      0x00000001UL                                
00215 #define CMU_CTRL_DBGCLK_DEFAULT                     (_CMU_CTRL_DBGCLK_DEFAULT << 28)            
00216 #define CMU_CTRL_DBGCLK_AUXHFRCO                    (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)           
00217 #define CMU_CTRL_DBGCLK_HFCLK                       (_CMU_CTRL_DBGCLK_HFCLK << 28)              
00218 #define CMU_CTRL_HFLE                               (0x1UL << 30)                               
00219 #define _CMU_CTRL_HFLE_SHIFT                        30                                          
00220 #define _CMU_CTRL_HFLE_MASK                         0x40000000UL                                
00221 #define _CMU_CTRL_HFLE_DEFAULT                      0x00000000UL                                
00222 #define CMU_CTRL_HFLE_DEFAULT                       (_CMU_CTRL_HFLE_DEFAULT << 30)              
00224 /* Bit fields for CMU HFCORECLKDIV */
00225 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
00226 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
00227 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
00228 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
00229 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
00230 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
00231 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
00232 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
00233 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
00234 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
00235 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
00236 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
00237 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
00238 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
00239 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
00240 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
00241 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
00242 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
00243 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
00244 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
00245 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
00246 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
00247 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
00248 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
00249 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
00250 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
00251 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
00252 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
00253 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
00254 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
00255 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
00256 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
00257 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
00258 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
00259 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
00261 /* Bit fields for CMU HFPERCLKDIV */
00262 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
00263 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
00264 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
00265 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
00266 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
00267 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
00268 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
00269 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
00270 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
00271 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
00272 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
00273 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
00274 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
00275 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
00276 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
00277 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
00278 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
00279 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
00280 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
00281 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
00282 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
00283 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
00284 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
00285 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
00286 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
00287 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
00288 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
00289 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
00290 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
00291 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
00292 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
00294 /* Bit fields for CMU HFRCOCTRL */
00295 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
00296 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
00297 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
00298 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
00299 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
00300 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
00301 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
00302 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
00303 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
00304 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
00305 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
00306 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
00307 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
00308 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
00309 #define _CMU_HFRCOCTRL_BAND_28MHZ                   0x00000005UL                           
00310 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
00311 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
00312 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
00313 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
00314 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
00315 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
00316 #define CMU_HFRCOCTRL_BAND_28MHZ                    (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       
00317 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
00318 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
00319 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
00320 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
00322 /* Bit fields for CMU LFRCOCTRL */
00323 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
00324 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
00325 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
00326 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
00327 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
00328 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
00330 /* Bit fields for CMU AUXHFRCOCTRL */
00331 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
00332 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
00333 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
00334 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
00335 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
00336 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
00337 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
00338 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
00339 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
00340 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
00341 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
00342 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
00343 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
00344 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ                0x00000006UL                            
00345 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
00346 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
00347 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
00348 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
00349 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
00350 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
00351 #define CMU_AUXHFRCOCTRL_BAND_28MHZ                 (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)     
00352 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
00354 /* Bit fields for CMU CALCTRL */
00355 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
00356 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
00357 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
00358 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
00359 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
00360 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
00361 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
00362 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
00363 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
00364 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
00365 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
00366 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
00367 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
00368 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
00369 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
00370 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
00371 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
00372 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
00373 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
00374 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
00375 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
00376 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
00377 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
00378 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
00379 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
00380 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
00381 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
00382 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
00383 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
00384 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
00385 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
00386 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
00387 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
00388 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
00389 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
00390 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
00391 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
00393 /* Bit fields for CMU CALCNT */
00394 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
00395 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
00396 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
00397 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
00398 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
00399 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
00401 /* Bit fields for CMU OSCENCMD */
00402 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
00403 #define _CMU_OSCENCMD_MASK                          0x000003FFUL                             
00404 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
00405 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
00406 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
00407 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
00408 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
00409 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
00410 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
00411 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
00412 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
00413 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
00414 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
00415 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
00416 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
00417 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
00418 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
00419 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
00420 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
00421 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
00422 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
00423 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
00424 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
00425 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
00426 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
00427 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
00428 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
00429 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
00430 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
00431 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
00432 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
00433 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
00434 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
00435 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
00436 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
00437 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
00438 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
00439 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
00440 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
00441 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
00442 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
00443 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
00444 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
00445 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
00446 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
00447 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
00448 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
00449 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
00450 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
00451 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
00452 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
00453 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
00455 /* Bit fields for CMU CMD */
00456 #define _CMU_CMD_RESETVALUE                         0x00000000UL                          
00457 #define _CMU_CMD_MASK                               0x0000007FUL                          
00458 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                     
00459 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                 
00460 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                          
00461 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                          
00462 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                          
00463 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                          
00464 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                          
00465 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0)      
00466 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)        
00467 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)         
00468 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)        
00469 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)         
00470 #define CMU_CMD_CALSTART                            (0x1UL << 3)                          
00471 #define _CMU_CMD_CALSTART_SHIFT                     3                                     
00472 #define _CMU_CMD_CALSTART_MASK                      0x8UL                                 
00473 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                          
00474 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3)      
00475 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                          
00476 #define _CMU_CMD_CALSTOP_SHIFT                      4                                     
00477 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                                
00478 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                          
00479 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)       
00480 #define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                     
00481 #define _CMU_CMD_USBCCLKSEL_MASK                    0x60UL                                
00482 #define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                          
00483 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV              0x00000001UL                          
00484 #define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                          
00485 #define _CMU_CMD_USBCCLKSEL_LFRCO                   0x00000003UL                          
00486 #define CMU_CMD_USBCCLKSEL_DEFAULT                  (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)    
00487 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV               (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) 
00488 #define CMU_CMD_USBCCLKSEL_LFXO                     (_CMU_CMD_USBCCLKSEL_LFXO << 5)       
00489 #define CMU_CMD_USBCCLKSEL_LFRCO                    (_CMU_CMD_USBCCLKSEL_LFRCO << 5)      
00491 /* Bit fields for CMU LFCLKSEL */
00492 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             
00493 #define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             
00494 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
00495 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
00496 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
00497 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
00498 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
00499 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
00500 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
00501 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
00502 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
00503 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
00504 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
00505 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
00506 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
00507 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
00508 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
00509 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
00510 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
00511 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
00512 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
00513 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
00514 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
00515 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
00516 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
00517 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
00518 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
00519 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
00520 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
00521 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
00522 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
00523 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
00524 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
00525 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
00526 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
00527 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
00528 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
00529 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
00530 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
00531 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
00532 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
00533 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
00534 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
00535 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
00537 /* Bit fields for CMU STATUS */
00538 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                             
00539 #define _CMU_STATUS_MASK                            0x0003FFFFUL                             
00540 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                             
00541 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                        
00542 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                    
00543 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                             
00544 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)      
00545 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                             
00546 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                        
00547 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                    
00548 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                             
00549 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)      
00550 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                             
00551 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                        
00552 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                    
00553 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                             
00554 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)       
00555 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                             
00556 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                        
00557 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                    
00558 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                             
00559 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)       
00560 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                             
00561 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                        
00562 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                   
00563 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                             
00564 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)   
00565 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                             
00566 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                        
00567 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                   
00568 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                             
00569 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)   
00570 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                             
00571 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                        
00572 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                   
00573 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                             
00574 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)      
00575 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                             
00576 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                        
00577 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                   
00578 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                             
00579 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)      
00580 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                             
00581 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                        
00582 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                  
00583 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                             
00584 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)       
00585 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                             
00586 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                        
00587 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                  
00588 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                             
00589 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)       
00590 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                            
00591 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                       
00592 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                  
00593 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                             
00594 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)     
00595 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                            
00596 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                       
00597 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                  
00598 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                             
00599 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)      
00600 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                            
00601 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                       
00602 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                                 
00603 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                             
00604 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)     
00605 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                            
00606 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                       
00607 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                                 
00608 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                             
00609 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)      
00610 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                            
00611 #define _CMU_STATUS_CALBSY_SHIFT                    14                                       
00612 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                                 
00613 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                             
00614 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)       
00615 #define CMU_STATUS_USBCHFCLKSEL                     (0x1UL << 15)                            
00616 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT              15                                       
00617 #define _CMU_STATUS_USBCHFCLKSEL_MASK               0x8000UL                                 
00618 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT            0x00000000UL                             
00619 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT             (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) 
00620 #define CMU_STATUS_USBCLFXOSEL                      (0x1UL << 16)                            
00621 #define _CMU_STATUS_USBCLFXOSEL_SHIFT               16                                       
00622 #define _CMU_STATUS_USBCLFXOSEL_MASK                0x10000UL                                
00623 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT             0x00000000UL                             
00624 #define CMU_STATUS_USBCLFXOSEL_DEFAULT              (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)  
00625 #define CMU_STATUS_USBCLFRCOSEL                     (0x1UL << 17)                            
00626 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT              17                                       
00627 #define _CMU_STATUS_USBCLFRCOSEL_MASK               0x20000UL                                
00628 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT            0x00000000UL                             
00629 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT             (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) 
00631 /* Bit fields for CMU IF */
00632 #define _CMU_IF_RESETVALUE                          0x00000001UL                        
00633 #define _CMU_IF_MASK                                0x000000FFUL                        
00634 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                        
00635 #define _CMU_IF_HFRCORDY_SHIFT                      0                                   
00636 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                               
00637 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                        
00638 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)     
00639 #define CMU_IF_HFXORDY                              (0x1UL << 1)                        
00640 #define _CMU_IF_HFXORDY_SHIFT                       1                                   
00641 #define _CMU_IF_HFXORDY_MASK                        0x2UL                               
00642 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                        
00643 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)      
00644 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                        
00645 #define _CMU_IF_LFRCORDY_SHIFT                      2                                   
00646 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                               
00647 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                        
00648 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)     
00649 #define CMU_IF_LFXORDY                              (0x1UL << 3)                        
00650 #define _CMU_IF_LFXORDY_SHIFT                       3                                   
00651 #define _CMU_IF_LFXORDY_MASK                        0x8UL                               
00652 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                        
00653 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)      
00654 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                        
00655 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                   
00656 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                              
00657 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                        
00658 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)  
00659 #define CMU_IF_CALRDY                               (0x1UL << 5)                        
00660 #define _CMU_IF_CALRDY_SHIFT                        5                                   
00661 #define _CMU_IF_CALRDY_MASK                         0x20UL                              
00662 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                        
00663 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)       
00664 #define CMU_IF_CALOF                                (0x1UL << 6)                        
00665 #define _CMU_IF_CALOF_SHIFT                         6                                   
00666 #define _CMU_IF_CALOF_MASK                          0x40UL                              
00667 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                        
00668 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)        
00669 #define CMU_IF_USBCHFCLKSEL                         (0x1UL << 7)                        
00670 #define _CMU_IF_USBCHFCLKSEL_SHIFT                  7                                   
00671 #define _CMU_IF_USBCHFCLKSEL_MASK                   0x80UL                              
00672 #define _CMU_IF_USBCHFCLKSEL_DEFAULT                0x00000000UL                        
00673 #define CMU_IF_USBCHFCLKSEL_DEFAULT                 (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) 
00675 /* Bit fields for CMU IFS */
00676 #define _CMU_IFS_RESETVALUE                         0x00000000UL                         
00677 #define _CMU_IFS_MASK                               0x000000FFUL                         
00678 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                         
00679 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                    
00680 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                                
00681 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                         
00682 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)     
00683 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                         
00684 #define _CMU_IFS_HFXORDY_SHIFT                      1                                    
00685 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                                
00686 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                         
00687 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)      
00688 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                         
00689 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                    
00690 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                                
00691 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                         
00692 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)     
00693 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                         
00694 #define _CMU_IFS_LFXORDY_SHIFT                      3                                    
00695 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                                
00696 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                         
00697 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)      
00698 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                         
00699 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                    
00700 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                               
00701 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                         
00702 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)  
00703 #define CMU_IFS_CALRDY                              (0x1UL << 5)                         
00704 #define _CMU_IFS_CALRDY_SHIFT                       5                                    
00705 #define _CMU_IFS_CALRDY_MASK                        0x20UL                               
00706 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                         
00707 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)       
00708 #define CMU_IFS_CALOF                               (0x1UL << 6)                         
00709 #define _CMU_IFS_CALOF_SHIFT                        6                                    
00710 #define _CMU_IFS_CALOF_MASK                         0x40UL                               
00711 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                         
00712 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)        
00713 #define CMU_IFS_USBCHFCLKSEL                        (0x1UL << 7)                         
00714 #define _CMU_IFS_USBCHFCLKSEL_SHIFT                 7                                    
00715 #define _CMU_IFS_USBCHFCLKSEL_MASK                  0x80UL                               
00716 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT               0x00000000UL                         
00717 #define CMU_IFS_USBCHFCLKSEL_DEFAULT                (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) 
00719 /* Bit fields for CMU IFC */
00720 #define _CMU_IFC_RESETVALUE                         0x00000000UL                         
00721 #define _CMU_IFC_MASK                               0x000000FFUL                         
00722 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                         
00723 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                    
00724 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                                
00725 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                         
00726 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)     
00727 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                         
00728 #define _CMU_IFC_HFXORDY_SHIFT                      1                                    
00729 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                                
00730 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                         
00731 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)      
00732 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                         
00733 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                    
00734 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                                
00735 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                         
00736 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)     
00737 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                         
00738 #define _CMU_IFC_LFXORDY_SHIFT                      3                                    
00739 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                                
00740 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                         
00741 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)      
00742 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                         
00743 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                    
00744 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                               
00745 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                         
00746 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)  
00747 #define CMU_IFC_CALRDY                              (0x1UL << 5)                         
00748 #define _CMU_IFC_CALRDY_SHIFT                       5                                    
00749 #define _CMU_IFC_CALRDY_MASK                        0x20UL                               
00750 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                         
00751 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)       
00752 #define CMU_IFC_CALOF                               (0x1UL << 6)                         
00753 #define _CMU_IFC_CALOF_SHIFT                        6                                    
00754 #define _CMU_IFC_CALOF_MASK                         0x40UL                               
00755 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                         
00756 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)        
00757 #define CMU_IFC_USBCHFCLKSEL                        (0x1UL << 7)                         
00758 #define _CMU_IFC_USBCHFCLKSEL_SHIFT                 7                                    
00759 #define _CMU_IFC_USBCHFCLKSEL_MASK                  0x80UL                               
00760 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT               0x00000000UL                         
00761 #define CMU_IFC_USBCHFCLKSEL_DEFAULT                (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) 
00763 /* Bit fields for CMU IEN */
00764 #define _CMU_IEN_RESETVALUE                         0x00000000UL                         
00765 #define _CMU_IEN_MASK                               0x000000FFUL                         
00766 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                         
00767 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                    
00768 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                                
00769 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                         
00770 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)     
00771 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                         
00772 #define _CMU_IEN_HFXORDY_SHIFT                      1                                    
00773 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                                
00774 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                         
00775 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)      
00776 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                         
00777 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                    
00778 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                                
00779 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                         
00780 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)     
00781 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                         
00782 #define _CMU_IEN_LFXORDY_SHIFT                      3                                    
00783 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                                
00784 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                         
00785 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)      
00786 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                         
00787 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                    
00788 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                               
00789 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                         
00790 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)  
00791 #define CMU_IEN_CALRDY                              (0x1UL << 5)                         
00792 #define _CMU_IEN_CALRDY_SHIFT                       5                                    
00793 #define _CMU_IEN_CALRDY_MASK                        0x20UL                               
00794 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                         
00795 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)       
00796 #define CMU_IEN_CALOF                               (0x1UL << 6)                         
00797 #define _CMU_IEN_CALOF_SHIFT                        6                                    
00798 #define _CMU_IEN_CALOF_MASK                         0x40UL                               
00799 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                         
00800 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)        
00801 #define CMU_IEN_USBCHFCLKSEL                        (0x1UL << 7)                         
00802 #define _CMU_IEN_USBCHFCLKSEL_SHIFT                 7                                    
00803 #define _CMU_IEN_USBCHFCLKSEL_MASK                  0x80UL                               
00804 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT               0x00000000UL                         
00805 #define CMU_IEN_USBCHFCLKSEL_DEFAULT                (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) 
00807 /* Bit fields for CMU HFCORECLKEN0 */
00808 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                          
00809 #define _CMU_HFCORECLKEN0_MASK                      0x0000003FUL                          
00810 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 0)                          
00811 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 0                                     
00812 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x1UL                                 
00813 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                          
00814 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)  
00815 #define CMU_HFCORECLKEN0_AES                        (0x1UL << 1)                          
00816 #define _CMU_HFCORECLKEN0_AES_SHIFT                 1                                     
00817 #define _CMU_HFCORECLKEN0_AES_MASK                  0x2UL                                 
00818 #define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                          
00819 #define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)  
00820 #define CMU_HFCORECLKEN0_USBC                       (0x1UL << 2)                          
00821 #define _CMU_HFCORECLKEN0_USBC_SHIFT                2                                     
00822 #define _CMU_HFCORECLKEN0_USBC_MASK                 0x4UL                                 
00823 #define _CMU_HFCORECLKEN0_USBC_DEFAULT              0x00000000UL                          
00824 #define CMU_HFCORECLKEN0_USBC_DEFAULT               (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) 
00825 #define CMU_HFCORECLKEN0_USB                        (0x1UL << 3)                          
00826 #define _CMU_HFCORECLKEN0_USB_SHIFT                 3                                     
00827 #define _CMU_HFCORECLKEN0_USB_MASK                  0x8UL                                 
00828 #define _CMU_HFCORECLKEN0_USB_DEFAULT               0x00000000UL                          
00829 #define CMU_HFCORECLKEN0_USB_DEFAULT                (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)  
00830 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 4)                          
00831 #define _CMU_HFCORECLKEN0_LE_SHIFT                  4                                     
00832 #define _CMU_HFCORECLKEN0_LE_MASK                   0x10UL                                
00833 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                          
00834 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)   
00835 #define CMU_HFCORECLKEN0_EBI                        (0x1UL << 5)                          
00836 #define _CMU_HFCORECLKEN0_EBI_SHIFT                 5                                     
00837 #define _CMU_HFCORECLKEN0_EBI_MASK                  0x20UL                                
00838 #define _CMU_HFCORECLKEN0_EBI_DEFAULT               0x00000000UL                          
00839 #define CMU_HFCORECLKEN0_EBI_DEFAULT                (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5)  
00841 /* Bit fields for CMU HFPERCLKEN0 */
00842 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
00843 #define _CMU_HFPERCLKEN0_MASK                       0x0003FFFFUL                           
00844 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 0)                           
00845 #define _CMU_HFPERCLKEN0_USART0_SHIFT               0                                      
00846 #define _CMU_HFPERCLKEN0_USART0_MASK                0x1UL                                  
00847 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
00848 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) 
00849 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 1)                           
00850 #define _CMU_HFPERCLKEN0_USART1_SHIFT               1                                      
00851 #define _CMU_HFPERCLKEN0_USART1_MASK                0x2UL                                  
00852 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
00853 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) 
00854 #define CMU_HFPERCLKEN0_USART2                      (0x1UL << 2)                           
00855 #define _CMU_HFPERCLKEN0_USART2_SHIFT               2                                      
00856 #define _CMU_HFPERCLKEN0_USART2_MASK                0x4UL                                  
00857 #define _CMU_HFPERCLKEN0_USART2_DEFAULT             0x00000000UL                           
00858 #define CMU_HFPERCLKEN0_USART2_DEFAULT              (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) 
00859 #define CMU_HFPERCLKEN0_UART0                       (0x1UL << 3)                           
00860 #define _CMU_HFPERCLKEN0_UART0_SHIFT                3                                      
00861 #define _CMU_HFPERCLKEN0_UART0_MASK                 0x8UL                                  
00862 #define _CMU_HFPERCLKEN0_UART0_DEFAULT              0x00000000UL                           
00863 #define CMU_HFPERCLKEN0_UART0_DEFAULT               (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)  
00864 #define CMU_HFPERCLKEN0_UART1                       (0x1UL << 4)                           
00865 #define _CMU_HFPERCLKEN0_UART1_SHIFT                4                                      
00866 #define _CMU_HFPERCLKEN0_UART1_MASK                 0x10UL                                 
00867 #define _CMU_HFPERCLKEN0_UART1_DEFAULT              0x00000000UL                           
00868 #define CMU_HFPERCLKEN0_UART1_DEFAULT               (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4)  
00869 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 5)                           
00870 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               5                                      
00871 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x20UL                                 
00872 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
00873 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) 
00874 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 6)                           
00875 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               6                                      
00876 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x40UL                                 
00877 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
00878 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) 
00879 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 7)                           
00880 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               7                                      
00881 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x80UL                                 
00882 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
00883 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) 
00884 #define CMU_HFPERCLKEN0_TIMER3                      (0x1UL << 8)                           
00885 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT               8                                      
00886 #define _CMU_HFPERCLKEN0_TIMER3_MASK                0x100UL                                
00887 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT             0x00000000UL                           
00888 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT              (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) 
00889 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 9)                           
00890 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                9                                      
00891 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x200UL                                
00892 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
00893 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)  
00894 #define CMU_HFPERCLKEN0_ACMP1                       (0x1UL << 10)                          
00895 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT                10                                     
00896 #define _CMU_HFPERCLKEN0_ACMP1_MASK                 0x400UL                                
00897 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT              0x00000000UL                           
00898 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT               (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) 
00899 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
00900 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
00901 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
00902 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
00903 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
00904 #define CMU_HFPERCLKEN0_I2C1                        (0x1UL << 12)                          
00905 #define _CMU_HFPERCLKEN0_I2C1_SHIFT                 12                                     
00906 #define _CMU_HFPERCLKEN0_I2C1_MASK                  0x1000UL                               
00907 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT               0x00000000UL                           
00908 #define CMU_HFPERCLKEN0_I2C1_DEFAULT                (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)  
00909 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 13)                          
00910 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 13                                     
00911 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x2000UL                               
00912 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
00913 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)  
00914 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 14)                          
00915 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 14                                     
00916 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x4000UL                               
00917 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
00918 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)  
00919 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 15)                          
00920 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  15                                     
00921 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x8000UL                               
00922 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
00923 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)   
00924 #define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 16)                          
00925 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                 16                                     
00926 #define _CMU_HFPERCLKEN0_ADC0_MASK                  0x10000UL                              
00927 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           
00928 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)  
00929 #define CMU_HFPERCLKEN0_DAC0                        (0x1UL << 17)                          
00930 #define _CMU_HFPERCLKEN0_DAC0_SHIFT                 17                                     
00931 #define _CMU_HFPERCLKEN0_DAC0_MASK                  0x20000UL                              
00932 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT               0x00000000UL                           
00933 #define CMU_HFPERCLKEN0_DAC0_DEFAULT                (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)  
00935 /* Bit fields for CMU SYNCBUSY */
00936 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
00937 #define _CMU_SYNCBUSY_MASK                          0x00000055UL                           
00938 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
00939 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
00940 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
00941 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
00942 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
00943 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
00944 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
00945 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
00946 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
00947 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
00948 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
00949 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
00950 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
00951 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
00952 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
00953 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
00954 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
00955 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
00956 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
00957 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
00959 /* Bit fields for CMU FREEZE */
00960 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
00961 #define _CMU_FREEZE_MASK                            0x00000001UL                         
00962 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
00963 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
00964 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
00965 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
00966 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
00967 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
00968 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
00969 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
00970 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
00972 /* Bit fields for CMU LFACLKEN0 */
00973 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                           
00974 #define _CMU_LFACLKEN0_MASK                         0x0000000FUL                           
00975 #define CMU_LFACLKEN0_LESENSE                       (0x1UL << 0)                           
00976 #define _CMU_LFACLKEN0_LESENSE_SHIFT                0                                      
00977 #define _CMU_LFACLKEN0_LESENSE_MASK                 0x1UL                                  
00978 #define _CMU_LFACLKEN0_LESENSE_DEFAULT              0x00000000UL                           
00979 #define CMU_LFACLKEN0_LESENSE_DEFAULT               (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)  
00980 #define CMU_LFACLKEN0_RTC                           (0x1UL << 1)                           
00981 #define _CMU_LFACLKEN0_RTC_SHIFT                    1                                      
00982 #define _CMU_LFACLKEN0_RTC_MASK                     0x2UL                                  
00983 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                           
00984 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)      
00985 #define CMU_LFACLKEN0_LETIMER0                      (0x1UL << 2)                           
00986 #define _CMU_LFACLKEN0_LETIMER0_SHIFT               2                                      
00987 #define _CMU_LFACLKEN0_LETIMER0_MASK                0x4UL                                  
00988 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT             0x00000000UL                           
00989 #define CMU_LFACLKEN0_LETIMER0_DEFAULT              (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) 
00990 #define CMU_LFACLKEN0_LCD                           (0x1UL << 3)                           
00991 #define _CMU_LFACLKEN0_LCD_SHIFT                    3                                      
00992 #define _CMU_LFACLKEN0_LCD_MASK                     0x8UL                                  
00993 #define _CMU_LFACLKEN0_LCD_DEFAULT                  0x00000000UL                           
00994 #define CMU_LFACLKEN0_LCD_DEFAULT                   (_CMU_LFACLKEN0_LCD_DEFAULT << 3)      
00996 /* Bit fields for CMU LFBCLKEN0 */
00997 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
00998 #define _CMU_LFBCLKEN0_MASK                         0x00000003UL                          
00999 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
01000 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
01001 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
01002 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
01003 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
01004 #define CMU_LFBCLKEN0_LEUART1                       (0x1UL << 1)                          
01005 #define _CMU_LFBCLKEN0_LEUART1_SHIFT                1                                     
01006 #define _CMU_LFBCLKEN0_LEUART1_MASK                 0x2UL                                 
01007 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT              0x00000000UL                          
01008 #define CMU_LFBCLKEN0_LEUART1_DEFAULT               (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) 
01010 /* Bit fields for CMU LFAPRESC0 */
01011 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                            
01012 #define _CMU_LFAPRESC0_MASK                         0x00003FF3UL                            
01013 #define _CMU_LFAPRESC0_LESENSE_SHIFT                0                                       
01014 #define _CMU_LFAPRESC0_LESENSE_MASK                 0x3UL                                   
01015 #define _CMU_LFAPRESC0_LESENSE_DIV1                 0x00000000UL                            
01016 #define _CMU_LFAPRESC0_LESENSE_DIV2                 0x00000001UL                            
01017 #define _CMU_LFAPRESC0_LESENSE_DIV4                 0x00000002UL                            
01018 #define _CMU_LFAPRESC0_LESENSE_DIV8                 0x00000003UL                            
01019 #define CMU_LFAPRESC0_LESENSE_DIV1                  (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)      
01020 #define CMU_LFAPRESC0_LESENSE_DIV2                  (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)      
01021 #define CMU_LFAPRESC0_LESENSE_DIV4                  (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)      
01022 #define CMU_LFAPRESC0_LESENSE_DIV8                  (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)      
01023 #define _CMU_LFAPRESC0_RTC_SHIFT                    4                                       
01024 #define _CMU_LFAPRESC0_RTC_MASK                     0xF0UL                                  
01025 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                            
01026 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                            
01027 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                            
01028 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                            
01029 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                            
01030 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                            
01031 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                            
01032 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                            
01033 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                            
01034 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                            
01035 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                            
01036 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                            
01037 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                            
01038 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                            
01039 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                            
01040 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                            
01041 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 4)          
01042 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 4)          
01043 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 4)          
01044 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 4)          
01045 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 4)         
01046 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 4)         
01047 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 4)         
01048 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 4)        
01049 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 4)        
01050 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 4)        
01051 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)       
01052 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)       
01053 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)       
01054 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)       
01055 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 4)      
01056 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 4)      
01057 #define _CMU_LFAPRESC0_LETIMER0_SHIFT               8                                       
01058 #define _CMU_LFAPRESC0_LETIMER0_MASK                0xF00UL                                 
01059 #define _CMU_LFAPRESC0_LETIMER0_DIV1                0x00000000UL                            
01060 #define _CMU_LFAPRESC0_LETIMER0_DIV2                0x00000001UL                            
01061 #define _CMU_LFAPRESC0_LETIMER0_DIV4                0x00000002UL                            
01062 #define _CMU_LFAPRESC0_LETIMER0_DIV8                0x00000003UL                            
01063 #define _CMU_LFAPRESC0_LETIMER0_DIV16               0x00000004UL                            
01064 #define _CMU_LFAPRESC0_LETIMER0_DIV32               0x00000005UL                            
01065 #define _CMU_LFAPRESC0_LETIMER0_DIV64               0x00000006UL                            
01066 #define _CMU_LFAPRESC0_LETIMER0_DIV128              0x00000007UL                            
01067 #define _CMU_LFAPRESC0_LETIMER0_DIV256              0x00000008UL                            
01068 #define _CMU_LFAPRESC0_LETIMER0_DIV512              0x00000009UL                            
01069 #define _CMU_LFAPRESC0_LETIMER0_DIV1024             0x0000000AUL                            
01070 #define _CMU_LFAPRESC0_LETIMER0_DIV2048             0x0000000BUL                            
01071 #define _CMU_LFAPRESC0_LETIMER0_DIV4096             0x0000000CUL                            
01072 #define _CMU_LFAPRESC0_LETIMER0_DIV8192             0x0000000DUL                            
01073 #define _CMU_LFAPRESC0_LETIMER0_DIV16384            0x0000000EUL                            
01074 #define _CMU_LFAPRESC0_LETIMER0_DIV32768            0x0000000FUL                            
01075 #define CMU_LFAPRESC0_LETIMER0_DIV1                 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)     
01076 #define CMU_LFAPRESC0_LETIMER0_DIV2                 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)     
01077 #define CMU_LFAPRESC0_LETIMER0_DIV4                 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)     
01078 #define CMU_LFAPRESC0_LETIMER0_DIV8                 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)     
01079 #define CMU_LFAPRESC0_LETIMER0_DIV16                (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)    
01080 #define CMU_LFAPRESC0_LETIMER0_DIV32                (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)    
01081 #define CMU_LFAPRESC0_LETIMER0_DIV64                (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)    
01082 #define CMU_LFAPRESC0_LETIMER0_DIV128               (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)   
01083 #define CMU_LFAPRESC0_LETIMER0_DIV256               (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)   
01084 #define CMU_LFAPRESC0_LETIMER0_DIV512               (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)   
01085 #define CMU_LFAPRESC0_LETIMER0_DIV1024              (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)  
01086 #define CMU_LFAPRESC0_LETIMER0_DIV2048              (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)  
01087 #define CMU_LFAPRESC0_LETIMER0_DIV4096              (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)  
01088 #define CMU_LFAPRESC0_LETIMER0_DIV8192              (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)  
01089 #define CMU_LFAPRESC0_LETIMER0_DIV16384             (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) 
01090 #define CMU_LFAPRESC0_LETIMER0_DIV32768             (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) 
01091 #define _CMU_LFAPRESC0_LCD_SHIFT                    12                                      
01092 #define _CMU_LFAPRESC0_LCD_MASK                     0x3000UL                                
01093 #define _CMU_LFAPRESC0_LCD_DIV16                    0x00000000UL                            
01094 #define _CMU_LFAPRESC0_LCD_DIV32                    0x00000001UL                            
01095 #define _CMU_LFAPRESC0_LCD_DIV64                    0x00000002UL                            
01096 #define _CMU_LFAPRESC0_LCD_DIV128                   0x00000003UL                            
01097 #define CMU_LFAPRESC0_LCD_DIV16                     (_CMU_LFAPRESC0_LCD_DIV16 << 12)        
01098 #define CMU_LFAPRESC0_LCD_DIV32                     (_CMU_LFAPRESC0_LCD_DIV32 << 12)        
01099 #define CMU_LFAPRESC0_LCD_DIV64                     (_CMU_LFAPRESC0_LCD_DIV64 << 12)        
01100 #define CMU_LFAPRESC0_LCD_DIV128                    (_CMU_LFAPRESC0_LCD_DIV128 << 12)       
01102 /* Bit fields for CMU LFBPRESC0 */
01103 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
01104 #define _CMU_LFBPRESC0_MASK                         0x00000033UL                       
01105 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
01106 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
01107 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
01108 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
01109 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
01110 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
01111 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
01112 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
01113 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
01114 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
01115 #define _CMU_LFBPRESC0_LEUART1_SHIFT                4                                  
01116 #define _CMU_LFBPRESC0_LEUART1_MASK                 0x30UL                             
01117 #define _CMU_LFBPRESC0_LEUART1_DIV1                 0x00000000UL                       
01118 #define _CMU_LFBPRESC0_LEUART1_DIV2                 0x00000001UL                       
01119 #define _CMU_LFBPRESC0_LEUART1_DIV4                 0x00000002UL                       
01120 #define _CMU_LFBPRESC0_LEUART1_DIV8                 0x00000003UL                       
01121 #define CMU_LFBPRESC0_LEUART1_DIV1                  (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) 
01122 #define CMU_LFBPRESC0_LEUART1_DIV2                  (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) 
01123 #define CMU_LFBPRESC0_LEUART1_DIV4                  (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) 
01124 #define CMU_LFBPRESC0_LEUART1_DIV8                  (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) 
01126 /* Bit fields for CMU PCNTCTRL */
01127 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
01128 #define _CMU_PCNTCTRL_MASK                          0x0000003FUL                             
01129 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
01130 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
01131 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
01132 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
01133 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
01134 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
01135 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
01136 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
01137 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
01138 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
01139 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
01140 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
01141 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
01142 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
01143 #define CMU_PCNTCTRL_PCNT1CLKEN                     (0x1UL << 2)                             
01144 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT              2                                        
01145 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK               0x4UL                                    
01146 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT            0x00000000UL                             
01147 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  
01148 #define CMU_PCNTCTRL_PCNT1CLKSEL                    (0x1UL << 3)                             
01149 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT             3                                        
01150 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK              0x8UL                                    
01151 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT           0x00000000UL                             
01152 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK            0x00000000UL                             
01153 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0           0x00000001UL                             
01154 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) 
01155 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  
01156 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0            (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) 
01157 #define CMU_PCNTCTRL_PCNT2CLKEN                     (0x1UL << 4)                             
01158 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT              4                                        
01159 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK               0x10UL                                   
01160 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT            0x00000000UL                             
01161 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  
01162 #define CMU_PCNTCTRL_PCNT2CLKSEL                    (0x1UL << 5)                             
01163 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT             5                                        
01164 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK              0x20UL                                   
01165 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT           0x00000000UL                             
01166 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK            0x00000000UL                             
01167 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0           0x00000001UL                             
01168 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) 
01169 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  
01170 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0            (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) 
01172 /* Bit fields for CMU LCDCTRL */
01173 #define _CMU_LCDCTRL_RESETVALUE                     0x00000020UL                         
01174 #define _CMU_LCDCTRL_MASK                           0x0000007FUL                         
01175 #define _CMU_LCDCTRL_FDIV_SHIFT                     0                                    
01176 #define _CMU_LCDCTRL_FDIV_MASK                      0x7UL                                
01177 #define _CMU_LCDCTRL_FDIV_DEFAULT                   0x00000000UL                         
01178 #define CMU_LCDCTRL_FDIV_DEFAULT                    (_CMU_LCDCTRL_FDIV_DEFAULT << 0)     
01179 #define CMU_LCDCTRL_VBOOSTEN                        (0x1UL << 3)                         
01180 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT                 3                                    
01181 #define _CMU_LCDCTRL_VBOOSTEN_MASK                  0x8UL                                
01182 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT               0x00000000UL                         
01183 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT                (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) 
01184 #define _CMU_LCDCTRL_VBFDIV_SHIFT                   4                                    
01185 #define _CMU_LCDCTRL_VBFDIV_MASK                    0x70UL                               
01186 #define _CMU_LCDCTRL_VBFDIV_DIV1                    0x00000000UL                         
01187 #define _CMU_LCDCTRL_VBFDIV_DIV2                    0x00000001UL                         
01188 #define _CMU_LCDCTRL_VBFDIV_DEFAULT                 0x00000002UL                         
01189 #define _CMU_LCDCTRL_VBFDIV_DIV4                    0x00000002UL                         
01190 #define _CMU_LCDCTRL_VBFDIV_DIV8                    0x00000003UL                         
01191 #define _CMU_LCDCTRL_VBFDIV_DIV16                   0x00000004UL                         
01192 #define _CMU_LCDCTRL_VBFDIV_DIV32                   0x00000005UL                         
01193 #define _CMU_LCDCTRL_VBFDIV_DIV64                   0x00000006UL                         
01194 #define _CMU_LCDCTRL_VBFDIV_DIV128                  0x00000007UL                         
01195 #define CMU_LCDCTRL_VBFDIV_DIV1                     (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)      
01196 #define CMU_LCDCTRL_VBFDIV_DIV2                     (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)      
01197 #define CMU_LCDCTRL_VBFDIV_DEFAULT                  (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)   
01198 #define CMU_LCDCTRL_VBFDIV_DIV4                     (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)      
01199 #define CMU_LCDCTRL_VBFDIV_DIV8                     (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)      
01200 #define CMU_LCDCTRL_VBFDIV_DIV16                    (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)     
01201 #define CMU_LCDCTRL_VBFDIV_DIV32                    (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)     
01202 #define CMU_LCDCTRL_VBFDIV_DIV64                    (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)     
01203 #define CMU_LCDCTRL_VBFDIV_DIV128                   (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)    
01205 /* Bit fields for CMU ROUTE */
01206 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
01207 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
01208 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
01209 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
01210 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
01211 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
01212 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
01213 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
01214 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
01215 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
01216 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
01217 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
01218 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
01219 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
01220 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
01221 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
01222 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
01223 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
01224 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
01225 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
01226 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
01227 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
01229 /* Bit fields for CMU LOCK */
01230 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
01231 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
01232 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
01233 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
01234 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
01235 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
01236 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
01237 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
01238 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
01239 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
01240 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
01241 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
01242 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
01243 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)