EFM32LG330F256_CMU Bit Fields
[EFM32LG330F256 Bit Fields]


Defines

#define _CMU_CTRL_RESETVALUE   0x000C262CUL
#define _CMU_CTRL_MASK   0x53FFFEEFUL
#define _CMU_CTRL_HFXOMODE_SHIFT   0
#define _CMU_CTRL_HFXOMODE_MASK   0x3UL
#define _CMU_CTRL_HFXOMODE_DEFAULT   0x00000000UL
#define _CMU_CTRL_HFXOMODE_XTAL   0x00000000UL
#define _CMU_CTRL_HFXOMODE_BUFEXTCLK   0x00000001UL
#define _CMU_CTRL_HFXOMODE_DIGEXTCLK   0x00000002UL
#define CMU_CTRL_HFXOMODE_DEFAULT   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
#define CMU_CTRL_HFXOMODE_XTAL   (_CMU_CTRL_HFXOMODE_XTAL << 0)
#define CMU_CTRL_HFXOMODE_BUFEXTCLK   (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
#define CMU_CTRL_HFXOMODE_DIGEXTCLK   (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
#define _CMU_CTRL_HFXOBOOST_SHIFT   2
#define _CMU_CTRL_HFXOBOOST_MASK   0xCUL
#define _CMU_CTRL_HFXOBOOST_50PCENT   0x00000000UL
#define _CMU_CTRL_HFXOBOOST_70PCENT   0x00000001UL
#define _CMU_CTRL_HFXOBOOST_80PCENT   0x00000002UL
#define _CMU_CTRL_HFXOBOOST_DEFAULT   0x00000003UL
#define _CMU_CTRL_HFXOBOOST_100PCENT   0x00000003UL
#define CMU_CTRL_HFXOBOOST_50PCENT   (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
#define CMU_CTRL_HFXOBOOST_70PCENT   (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
#define CMU_CTRL_HFXOBOOST_80PCENT   (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
#define CMU_CTRL_HFXOBOOST_DEFAULT   (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
#define CMU_CTRL_HFXOBOOST_100PCENT   (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
#define _CMU_CTRL_HFXOBUFCUR_SHIFT   5
#define _CMU_CTRL_HFXOBUFCUR_MASK   0x60UL
#define _CMU_CTRL_HFXOBUFCUR_DEFAULT   0x00000001UL
#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ   0x00000001UL
#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ   0x00000003UL
#define CMU_CTRL_HFXOBUFCUR_DEFAULT   (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ   (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)
#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ   (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5)
#define CMU_CTRL_HFXOGLITCHDETEN   (0x1UL << 7)
#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT   7
#define _CMU_CTRL_HFXOGLITCHDETEN_MASK   0x80UL
#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT   0x00000000UL
#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT   (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
#define _CMU_CTRL_HFXOTIMEOUT_SHIFT   9
#define _CMU_CTRL_HFXOTIMEOUT_MASK   0x600UL
#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES   0x00000000UL
#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES   0x00000001UL
#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES   0x00000002UL
#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT   0x00000003UL
#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES   0x00000003UL
#define CMU_CTRL_HFXOTIMEOUT_8CYCLES   (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
#define CMU_CTRL_HFXOTIMEOUT_256CYCLES   (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES   (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
#define CMU_CTRL_HFXOTIMEOUT_DEFAULT   (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES   (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
#define _CMU_CTRL_LFXOMODE_SHIFT   11
#define _CMU_CTRL_LFXOMODE_MASK   0x1800UL
#define _CMU_CTRL_LFXOMODE_DEFAULT   0x00000000UL
#define _CMU_CTRL_LFXOMODE_XTAL   0x00000000UL
#define _CMU_CTRL_LFXOMODE_BUFEXTCLK   0x00000001UL
#define _CMU_CTRL_LFXOMODE_DIGEXTCLK   0x00000002UL
#define CMU_CTRL_LFXOMODE_DEFAULT   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
#define CMU_CTRL_LFXOMODE_XTAL   (_CMU_CTRL_LFXOMODE_XTAL << 11)
#define CMU_CTRL_LFXOMODE_BUFEXTCLK   (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
#define CMU_CTRL_LFXOMODE_DIGEXTCLK   (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
#define CMU_CTRL_LFXOBOOST   (0x1UL << 13)
#define _CMU_CTRL_LFXOBOOST_SHIFT   13
#define _CMU_CTRL_LFXOBOOST_MASK   0x2000UL
#define _CMU_CTRL_LFXOBOOST_70PCENT   0x00000000UL
#define _CMU_CTRL_LFXOBOOST_DEFAULT   0x00000001UL
#define _CMU_CTRL_LFXOBOOST_100PCENT   0x00000001UL
#define CMU_CTRL_LFXOBOOST_70PCENT   (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
#define CMU_CTRL_LFXOBOOST_DEFAULT   (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
#define CMU_CTRL_LFXOBOOST_100PCENT   (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
#define _CMU_CTRL_HFCLKDIV_SHIFT   14
#define _CMU_CTRL_HFCLKDIV_MASK   0x1C000UL
#define _CMU_CTRL_HFCLKDIV_DEFAULT   0x00000000UL
#define CMU_CTRL_HFCLKDIV_DEFAULT   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)
#define CMU_CTRL_LFXOBUFCUR   (0x1UL << 17)
#define _CMU_CTRL_LFXOBUFCUR_SHIFT   17
#define _CMU_CTRL_LFXOBUFCUR_MASK   0x20000UL
#define _CMU_CTRL_LFXOBUFCUR_DEFAULT   0x00000000UL
#define CMU_CTRL_LFXOBUFCUR_DEFAULT   (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
#define _CMU_CTRL_LFXOTIMEOUT_SHIFT   18
#define _CMU_CTRL_LFXOTIMEOUT_MASK   0xC0000UL
#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES   0x00000000UL
#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES   0x00000001UL
#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES   0x00000002UL
#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT   0x00000003UL
#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES   0x00000003UL
#define CMU_CTRL_LFXOTIMEOUT_8CYCLES   (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES   (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES   (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
#define CMU_CTRL_LFXOTIMEOUT_DEFAULT   (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES   (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
#define _CMU_CTRL_CLKOUTSEL0_SHIFT   20
#define _CMU_CTRL_CLKOUTSEL0_MASK   0x700000UL
#define _CMU_CTRL_CLKOUTSEL0_DEFAULT   0x00000000UL
#define _CMU_CTRL_CLKOUTSEL0_HFRCO   0x00000000UL
#define _CMU_CTRL_CLKOUTSEL0_HFXO   0x00000001UL
#define _CMU_CTRL_CLKOUTSEL0_HFCLK2   0x00000002UL
#define _CMU_CTRL_CLKOUTSEL0_HFCLK4   0x00000003UL
#define _CMU_CTRL_CLKOUTSEL0_HFCLK8   0x00000004UL
#define _CMU_CTRL_CLKOUTSEL0_HFCLK16   0x00000005UL
#define _CMU_CTRL_CLKOUTSEL0_ULFRCO   0x00000006UL
#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO   0x00000007UL
#define CMU_CTRL_CLKOUTSEL0_DEFAULT   (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
#define CMU_CTRL_CLKOUTSEL0_HFRCO   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
#define CMU_CTRL_CLKOUTSEL0_HFXO   (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
#define CMU_CTRL_CLKOUTSEL0_HFCLK2   (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
#define CMU_CTRL_CLKOUTSEL0_HFCLK4   (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
#define CMU_CTRL_CLKOUTSEL0_HFCLK8   (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
#define CMU_CTRL_CLKOUTSEL0_HFCLK16   (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
#define CMU_CTRL_CLKOUTSEL0_ULFRCO   (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO   (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
#define _CMU_CTRL_CLKOUTSEL1_SHIFT   23
#define _CMU_CTRL_CLKOUTSEL1_MASK   0x3800000UL
#define _CMU_CTRL_CLKOUTSEL1_DEFAULT   0x00000000UL
#define _CMU_CTRL_CLKOUTSEL1_LFRCO   0x00000000UL
#define _CMU_CTRL_CLKOUTSEL1_LFXO   0x00000001UL
#define _CMU_CTRL_CLKOUTSEL1_HFCLK   0x00000002UL
#define _CMU_CTRL_CLKOUTSEL1_LFXOQ   0x00000003UL
#define _CMU_CTRL_CLKOUTSEL1_HFXOQ   0x00000004UL
#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ   0x00000005UL
#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ   0x00000006UL
#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   0x00000007UL
#define CMU_CTRL_CLKOUTSEL1_DEFAULT   (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
#define CMU_CTRL_CLKOUTSEL1_LFRCO   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
#define CMU_CTRL_CLKOUTSEL1_LFXO   (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
#define CMU_CTRL_CLKOUTSEL1_HFCLK   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
#define CMU_CTRL_CLKOUTSEL1_LFXOQ   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
#define CMU_CTRL_CLKOUTSEL1_HFXOQ   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
#define CMU_CTRL_CLKOUTSEL1_LFRCOQ   (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
#define CMU_CTRL_CLKOUTSEL1_HFRCOQ   (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
#define CMU_CTRL_DBGCLK   (0x1UL << 28)
#define _CMU_CTRL_DBGCLK_SHIFT   28
#define _CMU_CTRL_DBGCLK_MASK   0x10000000UL
#define _CMU_CTRL_DBGCLK_DEFAULT   0x00000000UL
#define _CMU_CTRL_DBGCLK_AUXHFRCO   0x00000000UL
#define _CMU_CTRL_DBGCLK_HFCLK   0x00000001UL
#define CMU_CTRL_DBGCLK_DEFAULT   (_CMU_CTRL_DBGCLK_DEFAULT << 28)
#define CMU_CTRL_DBGCLK_AUXHFRCO   (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)
#define CMU_CTRL_DBGCLK_HFCLK   (_CMU_CTRL_DBGCLK_HFCLK << 28)
#define CMU_CTRL_HFLE   (0x1UL << 30)
#define _CMU_CTRL_HFLE_SHIFT   30
#define _CMU_CTRL_HFLE_MASK   0x40000000UL
#define _CMU_CTRL_HFLE_DEFAULT   0x00000000UL
#define CMU_CTRL_HFLE_DEFAULT   (_CMU_CTRL_HFLE_DEFAULT << 30)
#define _CMU_HFCORECLKDIV_RESETVALUE   0x00000000UL
#define _CMU_HFCORECLKDIV_MASK   0x0000010FUL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT   0
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK   0xFUL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT   0x00000000UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK   0x00000000UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2   0x00000001UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4   0x00000002UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8   0x00000003UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16   0x00000004UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32   0x00000005UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64   0x00000006UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128   0x00000007UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256   0x00000008UL
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512   0x00000009UL
#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT   (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
#define CMU_HFCORECLKDIV_HFCORECLKLEDIV   (0x1UL << 8)
#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT   8
#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK   0x100UL
#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT   0x00000000UL
#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2   0x00000000UL
#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4   0x00000001UL
#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT   (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)
#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2   (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)
#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4   (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)
#define _CMU_HFPERCLKDIV_RESETVALUE   0x00000100UL
#define _CMU_HFPERCLKDIV_MASK   0x0000010FUL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT   0
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK   0xFUL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT   0x00000000UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK   0x00000000UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2   0x00000001UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4   0x00000002UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8   0x00000003UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16   0x00000004UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32   0x00000005UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64   0x00000006UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128   0x00000007UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256   0x00000008UL
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512   0x00000009UL
#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT   (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
#define CMU_HFPERCLKDIV_HFPERCLKEN   (0x1UL << 8)
#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT   8
#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK   0x100UL
#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT   0x00000001UL
#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT   (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
#define _CMU_HFRCOCTRL_RESETVALUE   0x00000380UL
#define _CMU_HFRCOCTRL_MASK   0x0001F7FFUL
#define _CMU_HFRCOCTRL_TUNING_SHIFT   0
#define _CMU_HFRCOCTRL_TUNING_MASK   0xFFUL
#define _CMU_HFRCOCTRL_TUNING_DEFAULT   0x00000080UL
#define CMU_HFRCOCTRL_TUNING_DEFAULT   (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
#define _CMU_HFRCOCTRL_BAND_SHIFT   8
#define _CMU_HFRCOCTRL_BAND_MASK   0x700UL
#define _CMU_HFRCOCTRL_BAND_1MHZ   0x00000000UL
#define _CMU_HFRCOCTRL_BAND_7MHZ   0x00000001UL
#define _CMU_HFRCOCTRL_BAND_11MHZ   0x00000002UL
#define _CMU_HFRCOCTRL_BAND_DEFAULT   0x00000003UL
#define _CMU_HFRCOCTRL_BAND_14MHZ   0x00000003UL
#define _CMU_HFRCOCTRL_BAND_21MHZ   0x00000004UL
#define _CMU_HFRCOCTRL_BAND_28MHZ   0x00000005UL
#define CMU_HFRCOCTRL_BAND_1MHZ   (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
#define CMU_HFRCOCTRL_BAND_7MHZ   (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
#define CMU_HFRCOCTRL_BAND_11MHZ   (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
#define CMU_HFRCOCTRL_BAND_DEFAULT   (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
#define CMU_HFRCOCTRL_BAND_14MHZ   (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
#define CMU_HFRCOCTRL_BAND_21MHZ   (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
#define CMU_HFRCOCTRL_BAND_28MHZ   (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
#define _CMU_HFRCOCTRL_SUDELAY_SHIFT   12
#define _CMU_HFRCOCTRL_SUDELAY_MASK   0x1F000UL
#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT   0x00000000UL
#define CMU_HFRCOCTRL_SUDELAY_DEFAULT   (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
#define _CMU_LFRCOCTRL_RESETVALUE   0x00000040UL
#define _CMU_LFRCOCTRL_MASK   0x0000007FUL
#define _CMU_LFRCOCTRL_TUNING_SHIFT   0
#define _CMU_LFRCOCTRL_TUNING_MASK   0x7FUL
#define _CMU_LFRCOCTRL_TUNING_DEFAULT   0x00000040UL
#define CMU_LFRCOCTRL_TUNING_DEFAULT   (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
#define _CMU_AUXHFRCOCTRL_RESETVALUE   0x00000080UL
#define _CMU_AUXHFRCOCTRL_MASK   0x000007FFUL
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT   0
#define _CMU_AUXHFRCOCTRL_TUNING_MASK   0xFFUL
#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT   0x00000080UL
#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT   (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
#define _CMU_AUXHFRCOCTRL_BAND_SHIFT   8
#define _CMU_AUXHFRCOCTRL_BAND_MASK   0x700UL
#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT   0x00000000UL
#define _CMU_AUXHFRCOCTRL_BAND_14MHZ   0x00000000UL
#define _CMU_AUXHFRCOCTRL_BAND_11MHZ   0x00000001UL
#define _CMU_AUXHFRCOCTRL_BAND_7MHZ   0x00000002UL
#define _CMU_AUXHFRCOCTRL_BAND_1MHZ   0x00000003UL
#define _CMU_AUXHFRCOCTRL_BAND_28MHZ   0x00000006UL
#define _CMU_AUXHFRCOCTRL_BAND_21MHZ   0x00000007UL
#define CMU_AUXHFRCOCTRL_BAND_DEFAULT   (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
#define CMU_AUXHFRCOCTRL_BAND_14MHZ   (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
#define CMU_AUXHFRCOCTRL_BAND_11MHZ   (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
#define CMU_AUXHFRCOCTRL_BAND_7MHZ   (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
#define CMU_AUXHFRCOCTRL_BAND_1MHZ   (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
#define CMU_AUXHFRCOCTRL_BAND_28MHZ   (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)
#define CMU_AUXHFRCOCTRL_BAND_21MHZ   (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
#define _CMU_CALCTRL_RESETVALUE   0x00000000UL
#define _CMU_CALCTRL_MASK   0x0000007FUL
#define _CMU_CALCTRL_UPSEL_SHIFT   0
#define _CMU_CALCTRL_UPSEL_MASK   0x7UL
#define _CMU_CALCTRL_UPSEL_DEFAULT   0x00000000UL
#define _CMU_CALCTRL_UPSEL_HFXO   0x00000000UL
#define _CMU_CALCTRL_UPSEL_LFXO   0x00000001UL
#define _CMU_CALCTRL_UPSEL_HFRCO   0x00000002UL
#define _CMU_CALCTRL_UPSEL_LFRCO   0x00000003UL
#define _CMU_CALCTRL_UPSEL_AUXHFRCO   0x00000004UL
#define CMU_CALCTRL_UPSEL_DEFAULT   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
#define CMU_CALCTRL_UPSEL_HFXO   (_CMU_CALCTRL_UPSEL_HFXO << 0)
#define CMU_CALCTRL_UPSEL_LFXO   (_CMU_CALCTRL_UPSEL_LFXO << 0)
#define CMU_CALCTRL_UPSEL_HFRCO   (_CMU_CALCTRL_UPSEL_HFRCO << 0)
#define CMU_CALCTRL_UPSEL_LFRCO   (_CMU_CALCTRL_UPSEL_LFRCO << 0)
#define CMU_CALCTRL_UPSEL_AUXHFRCO   (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
#define _CMU_CALCTRL_DOWNSEL_SHIFT   3
#define _CMU_CALCTRL_DOWNSEL_MASK   0x38UL
#define _CMU_CALCTRL_DOWNSEL_DEFAULT   0x00000000UL
#define _CMU_CALCTRL_DOWNSEL_HFCLK   0x00000000UL
#define _CMU_CALCTRL_DOWNSEL_HFXO   0x00000001UL
#define _CMU_CALCTRL_DOWNSEL_LFXO   0x00000002UL
#define _CMU_CALCTRL_DOWNSEL_HFRCO   0x00000003UL
#define _CMU_CALCTRL_DOWNSEL_LFRCO   0x00000004UL
#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO   0x00000005UL
#define CMU_CALCTRL_DOWNSEL_DEFAULT   (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
#define CMU_CALCTRL_DOWNSEL_HFCLK   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
#define CMU_CALCTRL_DOWNSEL_HFXO   (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
#define CMU_CALCTRL_DOWNSEL_LFXO   (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
#define CMU_CALCTRL_DOWNSEL_HFRCO   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
#define CMU_CALCTRL_DOWNSEL_LFRCO   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO   (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
#define CMU_CALCTRL_CONT   (0x1UL << 6)
#define _CMU_CALCTRL_CONT_SHIFT   6
#define _CMU_CALCTRL_CONT_MASK   0x40UL
#define _CMU_CALCTRL_CONT_DEFAULT   0x00000000UL
#define CMU_CALCTRL_CONT_DEFAULT   (_CMU_CALCTRL_CONT_DEFAULT << 6)
#define _CMU_CALCNT_RESETVALUE   0x00000000UL
#define _CMU_CALCNT_MASK   0x000FFFFFUL
#define _CMU_CALCNT_CALCNT_SHIFT   0
#define _CMU_CALCNT_CALCNT_MASK   0xFFFFFUL
#define _CMU_CALCNT_CALCNT_DEFAULT   0x00000000UL
#define CMU_CALCNT_CALCNT_DEFAULT   (_CMU_CALCNT_CALCNT_DEFAULT << 0)
#define _CMU_OSCENCMD_RESETVALUE   0x00000000UL
#define _CMU_OSCENCMD_MASK   0x000003FFUL
#define CMU_OSCENCMD_HFRCOEN   (0x1UL << 0)
#define _CMU_OSCENCMD_HFRCOEN_SHIFT   0
#define _CMU_OSCENCMD_HFRCOEN_MASK   0x1UL
#define _CMU_OSCENCMD_HFRCOEN_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_HFRCOEN_DEFAULT   (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
#define CMU_OSCENCMD_HFRCODIS   (0x1UL << 1)
#define _CMU_OSCENCMD_HFRCODIS_SHIFT   1
#define _CMU_OSCENCMD_HFRCODIS_MASK   0x2UL
#define _CMU_OSCENCMD_HFRCODIS_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_HFRCODIS_DEFAULT   (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
#define CMU_OSCENCMD_HFXOEN   (0x1UL << 2)
#define _CMU_OSCENCMD_HFXOEN_SHIFT   2
#define _CMU_OSCENCMD_HFXOEN_MASK   0x4UL
#define _CMU_OSCENCMD_HFXOEN_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_HFXOEN_DEFAULT   (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
#define CMU_OSCENCMD_HFXODIS   (0x1UL << 3)
#define _CMU_OSCENCMD_HFXODIS_SHIFT   3
#define _CMU_OSCENCMD_HFXODIS_MASK   0x8UL
#define _CMU_OSCENCMD_HFXODIS_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_HFXODIS_DEFAULT   (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
#define CMU_OSCENCMD_AUXHFRCOEN   (0x1UL << 4)
#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT   4
#define _CMU_OSCENCMD_AUXHFRCOEN_MASK   0x10UL
#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
#define CMU_OSCENCMD_AUXHFRCODIS   (0x1UL << 5)
#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT   5
#define _CMU_OSCENCMD_AUXHFRCODIS_MASK   0x20UL
#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
#define CMU_OSCENCMD_LFRCOEN   (0x1UL << 6)
#define _CMU_OSCENCMD_LFRCOEN_SHIFT   6
#define _CMU_OSCENCMD_LFRCOEN_MASK   0x40UL
#define _CMU_OSCENCMD_LFRCOEN_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_LFRCOEN_DEFAULT   (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
#define CMU_OSCENCMD_LFRCODIS   (0x1UL << 7)
#define _CMU_OSCENCMD_LFRCODIS_SHIFT   7
#define _CMU_OSCENCMD_LFRCODIS_MASK   0x80UL
#define _CMU_OSCENCMD_LFRCODIS_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_LFRCODIS_DEFAULT   (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
#define CMU_OSCENCMD_LFXOEN   (0x1UL << 8)
#define _CMU_OSCENCMD_LFXOEN_SHIFT   8
#define _CMU_OSCENCMD_LFXOEN_MASK   0x100UL
#define _CMU_OSCENCMD_LFXOEN_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_LFXOEN_DEFAULT   (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
#define CMU_OSCENCMD_LFXODIS   (0x1UL << 9)
#define _CMU_OSCENCMD_LFXODIS_SHIFT   9
#define _CMU_OSCENCMD_LFXODIS_MASK   0x200UL
#define _CMU_OSCENCMD_LFXODIS_DEFAULT   0x00000000UL
#define CMU_OSCENCMD_LFXODIS_DEFAULT   (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
#define _CMU_CMD_RESETVALUE   0x00000000UL
#define _CMU_CMD_MASK   0x0000007FUL
#define _CMU_CMD_HFCLKSEL_SHIFT   0
#define _CMU_CMD_HFCLKSEL_MASK   0x7UL
#define _CMU_CMD_HFCLKSEL_DEFAULT   0x00000000UL
#define _CMU_CMD_HFCLKSEL_HFRCO   0x00000001UL
#define _CMU_CMD_HFCLKSEL_HFXO   0x00000002UL
#define _CMU_CMD_HFCLKSEL_LFRCO   0x00000003UL
#define _CMU_CMD_HFCLKSEL_LFXO   0x00000004UL
#define CMU_CMD_HFCLKSEL_DEFAULT   (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
#define CMU_CMD_HFCLKSEL_HFRCO   (_CMU_CMD_HFCLKSEL_HFRCO << 0)
#define CMU_CMD_HFCLKSEL_HFXO   (_CMU_CMD_HFCLKSEL_HFXO << 0)
#define CMU_CMD_HFCLKSEL_LFRCO   (_CMU_CMD_HFCLKSEL_LFRCO << 0)
#define CMU_CMD_HFCLKSEL_LFXO   (_CMU_CMD_HFCLKSEL_LFXO << 0)
#define CMU_CMD_CALSTART   (0x1UL << 3)
#define _CMU_CMD_CALSTART_SHIFT   3
#define _CMU_CMD_CALSTART_MASK   0x8UL
#define _CMU_CMD_CALSTART_DEFAULT   0x00000000UL
#define CMU_CMD_CALSTART_DEFAULT   (_CMU_CMD_CALSTART_DEFAULT << 3)
#define CMU_CMD_CALSTOP   (0x1UL << 4)
#define _CMU_CMD_CALSTOP_SHIFT   4
#define _CMU_CMD_CALSTOP_MASK   0x10UL
#define _CMU_CMD_CALSTOP_DEFAULT   0x00000000UL
#define CMU_CMD_CALSTOP_DEFAULT   (_CMU_CMD_CALSTOP_DEFAULT << 4)
#define _CMU_CMD_USBCCLKSEL_SHIFT   5
#define _CMU_CMD_USBCCLKSEL_MASK   0x60UL
#define _CMU_CMD_USBCCLKSEL_DEFAULT   0x00000000UL
#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV   0x00000001UL
#define _CMU_CMD_USBCCLKSEL_LFXO   0x00000002UL
#define _CMU_CMD_USBCCLKSEL_LFRCO   0x00000003UL
#define CMU_CMD_USBCCLKSEL_DEFAULT   (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)
#define CMU_CMD_USBCCLKSEL_HFCLKNODIV   (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5)
#define CMU_CMD_USBCCLKSEL_LFXO   (_CMU_CMD_USBCCLKSEL_LFXO << 5)
#define CMU_CMD_USBCCLKSEL_LFRCO   (_CMU_CMD_USBCCLKSEL_LFRCO << 5)
#define _CMU_LFCLKSEL_RESETVALUE   0x00000005UL
#define _CMU_LFCLKSEL_MASK   0x0011000FUL
#define _CMU_LFCLKSEL_LFA_SHIFT   0
#define _CMU_LFCLKSEL_LFA_MASK   0x3UL
#define _CMU_LFCLKSEL_LFA_DISABLED   0x00000000UL
#define _CMU_LFCLKSEL_LFA_DEFAULT   0x00000001UL
#define _CMU_LFCLKSEL_LFA_LFRCO   0x00000001UL
#define _CMU_LFCLKSEL_LFA_LFXO   0x00000002UL
#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2   0x00000003UL
#define CMU_LFCLKSEL_LFA_DISABLED   (_CMU_LFCLKSEL_LFA_DISABLED << 0)
#define CMU_LFCLKSEL_LFA_DEFAULT   (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
#define CMU_LFCLKSEL_LFA_LFRCO   (_CMU_LFCLKSEL_LFA_LFRCO << 0)
#define CMU_LFCLKSEL_LFA_LFXO   (_CMU_LFCLKSEL_LFA_LFXO << 0)
#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2   (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
#define _CMU_LFCLKSEL_LFB_SHIFT   2
#define _CMU_LFCLKSEL_LFB_MASK   0xCUL
#define _CMU_LFCLKSEL_LFB_DISABLED   0x00000000UL
#define _CMU_LFCLKSEL_LFB_DEFAULT   0x00000001UL
#define _CMU_LFCLKSEL_LFB_LFRCO   0x00000001UL
#define _CMU_LFCLKSEL_LFB_LFXO   0x00000002UL
#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2   0x00000003UL
#define CMU_LFCLKSEL_LFB_DISABLED   (_CMU_LFCLKSEL_LFB_DISABLED << 2)
#define CMU_LFCLKSEL_LFB_DEFAULT   (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
#define CMU_LFCLKSEL_LFB_LFRCO   (_CMU_LFCLKSEL_LFB_LFRCO << 2)
#define CMU_LFCLKSEL_LFB_LFXO   (_CMU_LFCLKSEL_LFB_LFXO << 2)
#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2   (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
#define CMU_LFCLKSEL_LFAE   (0x1UL << 16)
#define _CMU_LFCLKSEL_LFAE_SHIFT   16
#define _CMU_LFCLKSEL_LFAE_MASK   0x10000UL
#define _CMU_LFCLKSEL_LFAE_DEFAULT   0x00000000UL
#define _CMU_LFCLKSEL_LFAE_DISABLED   0x00000000UL
#define _CMU_LFCLKSEL_LFAE_ULFRCO   0x00000001UL
#define CMU_LFCLKSEL_LFAE_DEFAULT   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
#define CMU_LFCLKSEL_LFAE_DISABLED   (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
#define CMU_LFCLKSEL_LFAE_ULFRCO   (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
#define CMU_LFCLKSEL_LFBE   (0x1UL << 20)
#define _CMU_LFCLKSEL_LFBE_SHIFT   20
#define _CMU_LFCLKSEL_LFBE_MASK   0x100000UL
#define _CMU_LFCLKSEL_LFBE_DEFAULT   0x00000000UL
#define _CMU_LFCLKSEL_LFBE_DISABLED   0x00000000UL
#define _CMU_LFCLKSEL_LFBE_ULFRCO   0x00000001UL
#define CMU_LFCLKSEL_LFBE_DEFAULT   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
#define CMU_LFCLKSEL_LFBE_DISABLED   (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
#define CMU_LFCLKSEL_LFBE_ULFRCO   (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
#define _CMU_STATUS_RESETVALUE   0x00000403UL
#define _CMU_STATUS_MASK   0x0003FFFFUL
#define CMU_STATUS_HFRCOENS   (0x1UL << 0)
#define _CMU_STATUS_HFRCOENS_SHIFT   0
#define _CMU_STATUS_HFRCOENS_MASK   0x1UL
#define _CMU_STATUS_HFRCOENS_DEFAULT   0x00000001UL
#define CMU_STATUS_HFRCOENS_DEFAULT   (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
#define CMU_STATUS_HFRCORDY   (0x1UL << 1)
#define _CMU_STATUS_HFRCORDY_SHIFT   1
#define _CMU_STATUS_HFRCORDY_MASK   0x2UL
#define _CMU_STATUS_HFRCORDY_DEFAULT   0x00000001UL
#define CMU_STATUS_HFRCORDY_DEFAULT   (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
#define CMU_STATUS_HFXOENS   (0x1UL << 2)
#define _CMU_STATUS_HFXOENS_SHIFT   2
#define _CMU_STATUS_HFXOENS_MASK   0x4UL
#define _CMU_STATUS_HFXOENS_DEFAULT   0x00000000UL
#define CMU_STATUS_HFXOENS_DEFAULT   (_CMU_STATUS_HFXOENS_DEFAULT << 2)
#define CMU_STATUS_HFXORDY   (0x1UL << 3)
#define _CMU_STATUS_HFXORDY_SHIFT   3
#define _CMU_STATUS_HFXORDY_MASK   0x8UL
#define _CMU_STATUS_HFXORDY_DEFAULT   0x00000000UL
#define CMU_STATUS_HFXORDY_DEFAULT   (_CMU_STATUS_HFXORDY_DEFAULT << 3)
#define CMU_STATUS_AUXHFRCOENS   (0x1UL << 4)
#define _CMU_STATUS_AUXHFRCOENS_SHIFT   4
#define _CMU_STATUS_AUXHFRCOENS_MASK   0x10UL
#define _CMU_STATUS_AUXHFRCOENS_DEFAULT   0x00000000UL
#define CMU_STATUS_AUXHFRCOENS_DEFAULT   (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
#define CMU_STATUS_AUXHFRCORDY   (0x1UL << 5)
#define _CMU_STATUS_AUXHFRCORDY_SHIFT   5
#define _CMU_STATUS_AUXHFRCORDY_MASK   0x20UL
#define _CMU_STATUS_AUXHFRCORDY_DEFAULT   0x00000000UL
#define CMU_STATUS_AUXHFRCORDY_DEFAULT   (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
#define CMU_STATUS_LFRCOENS   (0x1UL << 6)
#define _CMU_STATUS_LFRCOENS_SHIFT   6
#define _CMU_STATUS_LFRCOENS_MASK   0x40UL
#define _CMU_STATUS_LFRCOENS_DEFAULT   0x00000000UL
#define CMU_STATUS_LFRCOENS_DEFAULT   (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
#define CMU_STATUS_LFRCORDY   (0x1UL << 7)
#define _CMU_STATUS_LFRCORDY_SHIFT   7
#define _CMU_STATUS_LFRCORDY_MASK   0x80UL
#define _CMU_STATUS_LFRCORDY_DEFAULT   0x00000000UL
#define CMU_STATUS_LFRCORDY_DEFAULT   (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
#define CMU_STATUS_LFXOENS   (0x1UL << 8)
#define _CMU_STATUS_LFXOENS_SHIFT   8
#define _CMU_STATUS_LFXOENS_MASK   0x100UL
#define _CMU_STATUS_LFXOENS_DEFAULT   0x00000000UL
#define CMU_STATUS_LFXOENS_DEFAULT   (_CMU_STATUS_LFXOENS_DEFAULT << 8)
#define CMU_STATUS_LFXORDY   (0x1UL << 9)
#define _CMU_STATUS_LFXORDY_SHIFT   9
#define _CMU_STATUS_LFXORDY_MASK   0x200UL
#define _CMU_STATUS_LFXORDY_DEFAULT   0x00000000UL
#define CMU_STATUS_LFXORDY_DEFAULT   (_CMU_STATUS_LFXORDY_DEFAULT << 9)
#define CMU_STATUS_HFRCOSEL   (0x1UL << 10)
#define _CMU_STATUS_HFRCOSEL_SHIFT   10
#define _CMU_STATUS_HFRCOSEL_MASK   0x400UL
#define _CMU_STATUS_HFRCOSEL_DEFAULT   0x00000001UL
#define CMU_STATUS_HFRCOSEL_DEFAULT   (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
#define CMU_STATUS_HFXOSEL   (0x1UL << 11)
#define _CMU_STATUS_HFXOSEL_SHIFT   11
#define _CMU_STATUS_HFXOSEL_MASK   0x800UL
#define _CMU_STATUS_HFXOSEL_DEFAULT   0x00000000UL
#define CMU_STATUS_HFXOSEL_DEFAULT   (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
#define CMU_STATUS_LFRCOSEL   (0x1UL << 12)
#define _CMU_STATUS_LFRCOSEL_SHIFT   12
#define _CMU_STATUS_LFRCOSEL_MASK   0x1000UL
#define _CMU_STATUS_LFRCOSEL_DEFAULT   0x00000000UL
#define CMU_STATUS_LFRCOSEL_DEFAULT   (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
#define CMU_STATUS_LFXOSEL   (0x1UL << 13)
#define _CMU_STATUS_LFXOSEL_SHIFT   13
#define _CMU_STATUS_LFXOSEL_MASK   0x2000UL
#define _CMU_STATUS_LFXOSEL_DEFAULT   0x00000000UL
#define CMU_STATUS_LFXOSEL_DEFAULT   (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
#define CMU_STATUS_CALBSY   (0x1UL << 14)
#define _CMU_STATUS_CALBSY_SHIFT   14
#define _CMU_STATUS_CALBSY_MASK   0x4000UL
#define _CMU_STATUS_CALBSY_DEFAULT   0x00000000UL
#define CMU_STATUS_CALBSY_DEFAULT   (_CMU_STATUS_CALBSY_DEFAULT << 14)
#define CMU_STATUS_USBCHFCLKSEL   (0x1UL << 15)
#define _CMU_STATUS_USBCHFCLKSEL_SHIFT   15
#define _CMU_STATUS_USBCHFCLKSEL_MASK   0x8000UL
#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT   0x00000000UL
#define CMU_STATUS_USBCHFCLKSEL_DEFAULT   (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15)
#define CMU_STATUS_USBCLFXOSEL   (0x1UL << 16)
#define _CMU_STATUS_USBCLFXOSEL_SHIFT   16
#define _CMU_STATUS_USBCLFXOSEL_MASK   0x10000UL
#define _CMU_STATUS_USBCLFXOSEL_DEFAULT   0x00000000UL
#define CMU_STATUS_USBCLFXOSEL_DEFAULT   (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)
#define CMU_STATUS_USBCLFRCOSEL   (0x1UL << 17)
#define _CMU_STATUS_USBCLFRCOSEL_SHIFT   17
#define _CMU_STATUS_USBCLFRCOSEL_MASK   0x20000UL
#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT   0x00000000UL
#define CMU_STATUS_USBCLFRCOSEL_DEFAULT   (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)
#define _CMU_IF_RESETVALUE   0x00000001UL
#define _CMU_IF_MASK   0x000000FFUL
#define CMU_IF_HFRCORDY   (0x1UL << 0)
#define _CMU_IF_HFRCORDY_SHIFT   0
#define _CMU_IF_HFRCORDY_MASK   0x1UL
#define _CMU_IF_HFRCORDY_DEFAULT   0x00000001UL
#define CMU_IF_HFRCORDY_DEFAULT   (_CMU_IF_HFRCORDY_DEFAULT << 0)
#define CMU_IF_HFXORDY   (0x1UL << 1)
#define _CMU_IF_HFXORDY_SHIFT   1
#define _CMU_IF_HFXORDY_MASK   0x2UL
#define _CMU_IF_HFXORDY_DEFAULT   0x00000000UL
#define CMU_IF_HFXORDY_DEFAULT   (_CMU_IF_HFXORDY_DEFAULT << 1)
#define CMU_IF_LFRCORDY   (0x1UL << 2)
#define _CMU_IF_LFRCORDY_SHIFT   2
#define _CMU_IF_LFRCORDY_MASK   0x4UL
#define _CMU_IF_LFRCORDY_DEFAULT   0x00000000UL
#define CMU_IF_LFRCORDY_DEFAULT   (_CMU_IF_LFRCORDY_DEFAULT << 2)
#define CMU_IF_LFXORDY   (0x1UL << 3)
#define _CMU_IF_LFXORDY_SHIFT   3
#define _CMU_IF_LFXORDY_MASK   0x8UL
#define _CMU_IF_LFXORDY_DEFAULT   0x00000000UL
#define CMU_IF_LFXORDY_DEFAULT   (_CMU_IF_LFXORDY_DEFAULT << 3)
#define CMU_IF_AUXHFRCORDY   (0x1UL << 4)
#define _CMU_IF_AUXHFRCORDY_SHIFT   4
#define _CMU_IF_AUXHFRCORDY_MASK   0x10UL
#define _CMU_IF_AUXHFRCORDY_DEFAULT   0x00000000UL
#define CMU_IF_AUXHFRCORDY_DEFAULT   (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
#define CMU_IF_CALRDY   (0x1UL << 5)
#define _CMU_IF_CALRDY_SHIFT   5
#define _CMU_IF_CALRDY_MASK   0x20UL
#define _CMU_IF_CALRDY_DEFAULT   0x00000000UL
#define CMU_IF_CALRDY_DEFAULT   (_CMU_IF_CALRDY_DEFAULT << 5)
#define CMU_IF_CALOF   (0x1UL << 6)
#define _CMU_IF_CALOF_SHIFT   6
#define _CMU_IF_CALOF_MASK   0x40UL
#define _CMU_IF_CALOF_DEFAULT   0x00000000UL
#define CMU_IF_CALOF_DEFAULT   (_CMU_IF_CALOF_DEFAULT << 6)
#define CMU_IF_USBCHFCLKSEL   (0x1UL << 7)
#define _CMU_IF_USBCHFCLKSEL_SHIFT   7
#define _CMU_IF_USBCHFCLKSEL_MASK   0x80UL
#define _CMU_IF_USBCHFCLKSEL_DEFAULT   0x00000000UL
#define CMU_IF_USBCHFCLKSEL_DEFAULT   (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7)
#define _CMU_IFS_RESETVALUE   0x00000000UL
#define _CMU_IFS_MASK   0x000000FFUL
#define CMU_IFS_HFRCORDY   (0x1UL << 0)
#define _CMU_IFS_HFRCORDY_SHIFT   0
#define _CMU_IFS_HFRCORDY_MASK   0x1UL
#define _CMU_IFS_HFRCORDY_DEFAULT   0x00000000UL
#define CMU_IFS_HFRCORDY_DEFAULT   (_CMU_IFS_HFRCORDY_DEFAULT << 0)
#define CMU_IFS_HFXORDY   (0x1UL << 1)
#define _CMU_IFS_HFXORDY_SHIFT   1
#define _CMU_IFS_HFXORDY_MASK   0x2UL
#define _CMU_IFS_HFXORDY_DEFAULT   0x00000000UL
#define CMU_IFS_HFXORDY_DEFAULT   (_CMU_IFS_HFXORDY_DEFAULT << 1)
#define CMU_IFS_LFRCORDY   (0x1UL << 2)
#define _CMU_IFS_LFRCORDY_SHIFT   2
#define _CMU_IFS_LFRCORDY_MASK   0x4UL
#define _CMU_IFS_LFRCORDY_DEFAULT   0x00000000UL
#define CMU_IFS_LFRCORDY_DEFAULT   (_CMU_IFS_LFRCORDY_DEFAULT << 2)
#define CMU_IFS_LFXORDY   (0x1UL << 3)
#define _CMU_IFS_LFXORDY_SHIFT   3
#define _CMU_IFS_LFXORDY_MASK   0x8UL
#define _CMU_IFS_LFXORDY_DEFAULT   0x00000000UL
#define CMU_IFS_LFXORDY_DEFAULT   (_CMU_IFS_LFXORDY_DEFAULT << 3)
#define CMU_IFS_AUXHFRCORDY   (0x1UL << 4)
#define _CMU_IFS_AUXHFRCORDY_SHIFT   4
#define _CMU_IFS_AUXHFRCORDY_MASK   0x10UL
#define _CMU_IFS_AUXHFRCORDY_DEFAULT   0x00000000UL
#define CMU_IFS_AUXHFRCORDY_DEFAULT   (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
#define CMU_IFS_CALRDY   (0x1UL << 5)
#define _CMU_IFS_CALRDY_SHIFT   5
#define _CMU_IFS_CALRDY_MASK   0x20UL
#define _CMU_IFS_CALRDY_DEFAULT   0x00000000UL
#define CMU_IFS_CALRDY_DEFAULT   (_CMU_IFS_CALRDY_DEFAULT << 5)
#define CMU_IFS_CALOF   (0x1UL << 6)
#define _CMU_IFS_CALOF_SHIFT   6
#define _CMU_IFS_CALOF_MASK   0x40UL
#define _CMU_IFS_CALOF_DEFAULT   0x00000000UL
#define CMU_IFS_CALOF_DEFAULT   (_CMU_IFS_CALOF_DEFAULT << 6)
#define CMU_IFS_USBCHFCLKSEL   (0x1UL << 7)
#define _CMU_IFS_USBCHFCLKSEL_SHIFT   7
#define _CMU_IFS_USBCHFCLKSEL_MASK   0x80UL
#define _CMU_IFS_USBCHFCLKSEL_DEFAULT   0x00000000UL
#define CMU_IFS_USBCHFCLKSEL_DEFAULT   (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7)
#define _CMU_IFC_RESETVALUE   0x00000000UL
#define _CMU_IFC_MASK   0x000000FFUL
#define CMU_IFC_HFRCORDY   (0x1UL << 0)
#define _CMU_IFC_HFRCORDY_SHIFT   0
#define _CMU_IFC_HFRCORDY_MASK   0x1UL
#define _CMU_IFC_HFRCORDY_DEFAULT   0x00000000UL
#define CMU_IFC_HFRCORDY_DEFAULT   (_CMU_IFC_HFRCORDY_DEFAULT << 0)
#define CMU_IFC_HFXORDY   (0x1UL << 1)
#define _CMU_IFC_HFXORDY_SHIFT   1
#define _CMU_IFC_HFXORDY_MASK   0x2UL
#define _CMU_IFC_HFXORDY_DEFAULT   0x00000000UL
#define CMU_IFC_HFXORDY_DEFAULT   (_CMU_IFC_HFXORDY_DEFAULT << 1)
#define CMU_IFC_LFRCORDY   (0x1UL << 2)
#define _CMU_IFC_LFRCORDY_SHIFT   2
#define _CMU_IFC_LFRCORDY_MASK   0x4UL
#define _CMU_IFC_LFRCORDY_DEFAULT   0x00000000UL
#define CMU_IFC_LFRCORDY_DEFAULT   (_CMU_IFC_LFRCORDY_DEFAULT << 2)
#define CMU_IFC_LFXORDY   (0x1UL << 3)
#define _CMU_IFC_LFXORDY_SHIFT   3
#define _CMU_IFC_LFXORDY_MASK   0x8UL
#define _CMU_IFC_LFXORDY_DEFAULT   0x00000000UL
#define CMU_IFC_LFXORDY_DEFAULT   (_CMU_IFC_LFXORDY_DEFAULT << 3)
#define CMU_IFC_AUXHFRCORDY   (0x1UL << 4)
#define _CMU_IFC_AUXHFRCORDY_SHIFT   4
#define _CMU_IFC_AUXHFRCORDY_MASK   0x10UL
#define _CMU_IFC_AUXHFRCORDY_DEFAULT   0x00000000UL
#define CMU_IFC_AUXHFRCORDY_DEFAULT   (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
#define CMU_IFC_CALRDY   (0x1UL << 5)
#define _CMU_IFC_CALRDY_SHIFT   5
#define _CMU_IFC_CALRDY_MASK   0x20UL
#define _CMU_IFC_CALRDY_DEFAULT   0x00000000UL
#define CMU_IFC_CALRDY_DEFAULT   (_CMU_IFC_CALRDY_DEFAULT << 5)
#define CMU_IFC_CALOF   (0x1UL << 6)
#define _CMU_IFC_CALOF_SHIFT   6
#define _CMU_IFC_CALOF_MASK   0x40UL
#define _CMU_IFC_CALOF_DEFAULT   0x00000000UL
#define CMU_IFC_CALOF_DEFAULT   (_CMU_IFC_CALOF_DEFAULT << 6)
#define CMU_IFC_USBCHFCLKSEL   (0x1UL << 7)
#define _CMU_IFC_USBCHFCLKSEL_SHIFT   7
#define _CMU_IFC_USBCHFCLKSEL_MASK   0x80UL
#define _CMU_IFC_USBCHFCLKSEL_DEFAULT   0x00000000UL
#define CMU_IFC_USBCHFCLKSEL_DEFAULT   (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7)
#define _CMU_IEN_RESETVALUE   0x00000000UL
#define _CMU_IEN_MASK   0x000000FFUL
#define CMU_IEN_HFRCORDY   (0x1UL << 0)
#define _CMU_IEN_HFRCORDY_SHIFT   0
#define _CMU_IEN_HFRCORDY_MASK   0x1UL
#define _CMU_IEN_HFRCORDY_DEFAULT   0x00000000UL
#define CMU_IEN_HFRCORDY_DEFAULT   (_CMU_IEN_HFRCORDY_DEFAULT << 0)
#define CMU_IEN_HFXORDY   (0x1UL << 1)
#define _CMU_IEN_HFXORDY_SHIFT   1
#define _CMU_IEN_HFXORDY_MASK   0x2UL
#define _CMU_IEN_HFXORDY_DEFAULT   0x00000000UL
#define CMU_IEN_HFXORDY_DEFAULT   (_CMU_IEN_HFXORDY_DEFAULT << 1)
#define CMU_IEN_LFRCORDY   (0x1UL << 2)
#define _CMU_IEN_LFRCORDY_SHIFT   2
#define _CMU_IEN_LFRCORDY_MASK   0x4UL
#define _CMU_IEN_LFRCORDY_DEFAULT   0x00000000UL
#define CMU_IEN_LFRCORDY_DEFAULT   (_CMU_IEN_LFRCORDY_DEFAULT << 2)
#define CMU_IEN_LFXORDY   (0x1UL << 3)
#define _CMU_IEN_LFXORDY_SHIFT   3
#define _CMU_IEN_LFXORDY_MASK   0x8UL
#define _CMU_IEN_LFXORDY_DEFAULT   0x00000000UL
#define CMU_IEN_LFXORDY_DEFAULT   (_CMU_IEN_LFXORDY_DEFAULT << 3)
#define CMU_IEN_AUXHFRCORDY   (0x1UL << 4)
#define _CMU_IEN_AUXHFRCORDY_SHIFT   4
#define _CMU_IEN_AUXHFRCORDY_MASK   0x10UL
#define _CMU_IEN_AUXHFRCORDY_DEFAULT   0x00000000UL
#define CMU_IEN_AUXHFRCORDY_DEFAULT   (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
#define CMU_IEN_CALRDY   (0x1UL << 5)
#define _CMU_IEN_CALRDY_SHIFT   5
#define _CMU_IEN_CALRDY_MASK   0x20UL
#define _CMU_IEN_CALRDY_DEFAULT   0x00000000UL
#define CMU_IEN_CALRDY_DEFAULT   (_CMU_IEN_CALRDY_DEFAULT << 5)
#define CMU_IEN_CALOF   (0x1UL << 6)
#define _CMU_IEN_CALOF_SHIFT   6
#define _CMU_IEN_CALOF_MASK   0x40UL
#define _CMU_IEN_CALOF_DEFAULT   0x00000000UL
#define CMU_IEN_CALOF_DEFAULT   (_CMU_IEN_CALOF_DEFAULT << 6)
#define CMU_IEN_USBCHFCLKSEL   (0x1UL << 7)
#define _CMU_IEN_USBCHFCLKSEL_SHIFT   7
#define _CMU_IEN_USBCHFCLKSEL_MASK   0x80UL
#define _CMU_IEN_USBCHFCLKSEL_DEFAULT   0x00000000UL
#define CMU_IEN_USBCHFCLKSEL_DEFAULT   (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7)
#define _CMU_HFCORECLKEN0_RESETVALUE   0x00000000UL
#define _CMU_HFCORECLKEN0_MASK   0x0000001FUL
#define CMU_HFCORECLKEN0_DMA   (0x1UL << 0)
#define _CMU_HFCORECLKEN0_DMA_SHIFT   0
#define _CMU_HFCORECLKEN0_DMA_MASK   0x1UL
#define _CMU_HFCORECLKEN0_DMA_DEFAULT   0x00000000UL
#define CMU_HFCORECLKEN0_DMA_DEFAULT   (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)
#define CMU_HFCORECLKEN0_AES   (0x1UL << 1)
#define _CMU_HFCORECLKEN0_AES_SHIFT   1
#define _CMU_HFCORECLKEN0_AES_MASK   0x2UL
#define _CMU_HFCORECLKEN0_AES_DEFAULT   0x00000000UL
#define CMU_HFCORECLKEN0_AES_DEFAULT   (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)
#define CMU_HFCORECLKEN0_USBC   (0x1UL << 2)
#define _CMU_HFCORECLKEN0_USBC_SHIFT   2
#define _CMU_HFCORECLKEN0_USBC_MASK   0x4UL
#define _CMU_HFCORECLKEN0_USBC_DEFAULT   0x00000000UL
#define CMU_HFCORECLKEN0_USBC_DEFAULT   (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2)
#define CMU_HFCORECLKEN0_USB   (0x1UL << 3)
#define _CMU_HFCORECLKEN0_USB_SHIFT   3
#define _CMU_HFCORECLKEN0_USB_MASK   0x8UL
#define _CMU_HFCORECLKEN0_USB_DEFAULT   0x00000000UL
#define CMU_HFCORECLKEN0_USB_DEFAULT   (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)
#define CMU_HFCORECLKEN0_LE   (0x1UL << 4)
#define _CMU_HFCORECLKEN0_LE_SHIFT   4
#define _CMU_HFCORECLKEN0_LE_MASK   0x10UL
#define _CMU_HFCORECLKEN0_LE_DEFAULT   0x00000000UL
#define CMU_HFCORECLKEN0_LE_DEFAULT   (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)
#define _CMU_HFPERCLKEN0_RESETVALUE   0x00000000UL
#define _CMU_HFPERCLKEN0_MASK   0x0003FFE7UL
#define CMU_HFPERCLKEN0_USART0   (0x1UL << 0)
#define _CMU_HFPERCLKEN0_USART0_SHIFT   0
#define _CMU_HFPERCLKEN0_USART0_MASK   0x1UL
#define _CMU_HFPERCLKEN0_USART0_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_USART0_DEFAULT   (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
#define CMU_HFPERCLKEN0_USART1   (0x1UL << 1)
#define _CMU_HFPERCLKEN0_USART1_SHIFT   1
#define _CMU_HFPERCLKEN0_USART1_MASK   0x2UL
#define _CMU_HFPERCLKEN0_USART1_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_USART1_DEFAULT   (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
#define CMU_HFPERCLKEN0_USART2   (0x1UL << 2)
#define _CMU_HFPERCLKEN0_USART2_SHIFT   2
#define _CMU_HFPERCLKEN0_USART2_MASK   0x4UL
#define _CMU_HFPERCLKEN0_USART2_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_USART2_DEFAULT   (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
#define CMU_HFPERCLKEN0_TIMER0   (0x1UL << 5)
#define _CMU_HFPERCLKEN0_TIMER0_SHIFT   5
#define _CMU_HFPERCLKEN0_TIMER0_MASK   0x20UL
#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_TIMER0_DEFAULT   (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5)
#define CMU_HFPERCLKEN0_TIMER1   (0x1UL << 6)
#define _CMU_HFPERCLKEN0_TIMER1_SHIFT   6
#define _CMU_HFPERCLKEN0_TIMER1_MASK   0x40UL
#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_TIMER1_DEFAULT   (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6)
#define CMU_HFPERCLKEN0_TIMER2   (0x1UL << 7)
#define _CMU_HFPERCLKEN0_TIMER2_SHIFT   7
#define _CMU_HFPERCLKEN0_TIMER2_MASK   0x80UL
#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_TIMER2_DEFAULT   (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7)
#define CMU_HFPERCLKEN0_TIMER3   (0x1UL << 8)
#define _CMU_HFPERCLKEN0_TIMER3_SHIFT   8
#define _CMU_HFPERCLKEN0_TIMER3_MASK   0x100UL
#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_TIMER3_DEFAULT   (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8)
#define CMU_HFPERCLKEN0_ACMP0   (0x1UL << 9)
#define _CMU_HFPERCLKEN0_ACMP0_SHIFT   9
#define _CMU_HFPERCLKEN0_ACMP0_MASK   0x200UL
#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_ACMP0_DEFAULT   (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)
#define CMU_HFPERCLKEN0_ACMP1   (0x1UL << 10)
#define _CMU_HFPERCLKEN0_ACMP1_SHIFT   10
#define _CMU_HFPERCLKEN0_ACMP1_MASK   0x400UL
#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_ACMP1_DEFAULT   (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10)
#define CMU_HFPERCLKEN0_I2C0   (0x1UL << 11)
#define _CMU_HFPERCLKEN0_I2C0_SHIFT   11
#define _CMU_HFPERCLKEN0_I2C0_MASK   0x800UL
#define _CMU_HFPERCLKEN0_I2C0_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_I2C0_DEFAULT   (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
#define CMU_HFPERCLKEN0_I2C1   (0x1UL << 12)
#define _CMU_HFPERCLKEN0_I2C1_SHIFT   12
#define _CMU_HFPERCLKEN0_I2C1_MASK   0x1000UL
#define _CMU_HFPERCLKEN0_I2C1_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_I2C1_DEFAULT   (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)
#define CMU_HFPERCLKEN0_GPIO   (0x1UL << 13)
#define _CMU_HFPERCLKEN0_GPIO_SHIFT   13
#define _CMU_HFPERCLKEN0_GPIO_MASK   0x2000UL
#define _CMU_HFPERCLKEN0_GPIO_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_GPIO_DEFAULT   (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)
#define CMU_HFPERCLKEN0_VCMP   (0x1UL << 14)
#define _CMU_HFPERCLKEN0_VCMP_SHIFT   14
#define _CMU_HFPERCLKEN0_VCMP_MASK   0x4000UL
#define _CMU_HFPERCLKEN0_VCMP_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_VCMP_DEFAULT   (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)
#define CMU_HFPERCLKEN0_PRS   (0x1UL << 15)
#define _CMU_HFPERCLKEN0_PRS_SHIFT   15
#define _CMU_HFPERCLKEN0_PRS_MASK   0x8000UL
#define _CMU_HFPERCLKEN0_PRS_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_PRS_DEFAULT   (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)
#define CMU_HFPERCLKEN0_ADC0   (0x1UL << 16)
#define _CMU_HFPERCLKEN0_ADC0_SHIFT   16
#define _CMU_HFPERCLKEN0_ADC0_MASK   0x10000UL
#define _CMU_HFPERCLKEN0_ADC0_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_ADC0_DEFAULT   (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)
#define CMU_HFPERCLKEN0_DAC0   (0x1UL << 17)
#define _CMU_HFPERCLKEN0_DAC0_SHIFT   17
#define _CMU_HFPERCLKEN0_DAC0_MASK   0x20000UL
#define _CMU_HFPERCLKEN0_DAC0_DEFAULT   0x00000000UL
#define CMU_HFPERCLKEN0_DAC0_DEFAULT   (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)
#define _CMU_SYNCBUSY_RESETVALUE   0x00000000UL
#define _CMU_SYNCBUSY_MASK   0x00000055UL
#define CMU_SYNCBUSY_LFACLKEN0   (0x1UL << 0)
#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT   0
#define _CMU_SYNCBUSY_LFACLKEN0_MASK   0x1UL
#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT   0x00000000UL
#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
#define CMU_SYNCBUSY_LFAPRESC0   (0x1UL << 2)
#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT   2
#define _CMU_SYNCBUSY_LFAPRESC0_MASK   0x4UL
#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT   0x00000000UL
#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
#define CMU_SYNCBUSY_LFBCLKEN0   (0x1UL << 4)
#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT   4
#define _CMU_SYNCBUSY_LFBCLKEN0_MASK   0x10UL
#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   0x00000000UL
#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
#define CMU_SYNCBUSY_LFBPRESC0   (0x1UL << 6)
#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT   6
#define _CMU_SYNCBUSY_LFBPRESC0_MASK   0x40UL
#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT   0x00000000UL
#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
#define _CMU_FREEZE_RESETVALUE   0x00000000UL
#define _CMU_FREEZE_MASK   0x00000001UL
#define CMU_FREEZE_REGFREEZE   (0x1UL << 0)
#define _CMU_FREEZE_REGFREEZE_SHIFT   0
#define _CMU_FREEZE_REGFREEZE_MASK   0x1UL
#define _CMU_FREEZE_REGFREEZE_DEFAULT   0x00000000UL
#define _CMU_FREEZE_REGFREEZE_UPDATE   0x00000000UL
#define _CMU_FREEZE_REGFREEZE_FREEZE   0x00000001UL
#define CMU_FREEZE_REGFREEZE_DEFAULT   (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
#define CMU_FREEZE_REGFREEZE_UPDATE   (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
#define CMU_FREEZE_REGFREEZE_FREEZE   (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
#define _CMU_LFACLKEN0_RESETVALUE   0x00000000UL
#define _CMU_LFACLKEN0_MASK   0x00000007UL
#define CMU_LFACLKEN0_LESENSE   (0x1UL << 0)
#define _CMU_LFACLKEN0_LESENSE_SHIFT   0
#define _CMU_LFACLKEN0_LESENSE_MASK   0x1UL
#define _CMU_LFACLKEN0_LESENSE_DEFAULT   0x00000000UL
#define CMU_LFACLKEN0_LESENSE_DEFAULT   (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)
#define CMU_LFACLKEN0_RTC   (0x1UL << 1)
#define _CMU_LFACLKEN0_RTC_SHIFT   1
#define _CMU_LFACLKEN0_RTC_MASK   0x2UL
#define _CMU_LFACLKEN0_RTC_DEFAULT   0x00000000UL
#define CMU_LFACLKEN0_RTC_DEFAULT   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)
#define CMU_LFACLKEN0_LETIMER0   (0x1UL << 2)
#define _CMU_LFACLKEN0_LETIMER0_SHIFT   2
#define _CMU_LFACLKEN0_LETIMER0_MASK   0x4UL
#define _CMU_LFACLKEN0_LETIMER0_DEFAULT   0x00000000UL
#define CMU_LFACLKEN0_LETIMER0_DEFAULT   (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)
#define _CMU_LFBCLKEN0_RESETVALUE   0x00000000UL
#define _CMU_LFBCLKEN0_MASK   0x00000003UL
#define CMU_LFBCLKEN0_LEUART0   (0x1UL << 0)
#define _CMU_LFBCLKEN0_LEUART0_SHIFT   0
#define _CMU_LFBCLKEN0_LEUART0_MASK   0x1UL
#define _CMU_LFBCLKEN0_LEUART0_DEFAULT   0x00000000UL
#define CMU_LFBCLKEN0_LEUART0_DEFAULT   (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
#define CMU_LFBCLKEN0_LEUART1   (0x1UL << 1)
#define _CMU_LFBCLKEN0_LEUART1_SHIFT   1
#define _CMU_LFBCLKEN0_LEUART1_MASK   0x2UL
#define _CMU_LFBCLKEN0_LEUART1_DEFAULT   0x00000000UL
#define CMU_LFBCLKEN0_LEUART1_DEFAULT   (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)
#define _CMU_LFAPRESC0_RESETVALUE   0x00000000UL
#define _CMU_LFAPRESC0_MASK   0x00000FF3UL
#define _CMU_LFAPRESC0_LESENSE_SHIFT   0
#define _CMU_LFAPRESC0_LESENSE_MASK   0x3UL
#define _CMU_LFAPRESC0_LESENSE_DIV1   0x00000000UL
#define _CMU_LFAPRESC0_LESENSE_DIV2   0x00000001UL
#define _CMU_LFAPRESC0_LESENSE_DIV4   0x00000002UL
#define _CMU_LFAPRESC0_LESENSE_DIV8   0x00000003UL
#define CMU_LFAPRESC0_LESENSE_DIV1   (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)
#define CMU_LFAPRESC0_LESENSE_DIV2   (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)
#define CMU_LFAPRESC0_LESENSE_DIV4   (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)
#define CMU_LFAPRESC0_LESENSE_DIV8   (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)
#define _CMU_LFAPRESC0_RTC_SHIFT   4
#define _CMU_LFAPRESC0_RTC_MASK   0xF0UL
#define _CMU_LFAPRESC0_RTC_DIV1   0x00000000UL
#define _CMU_LFAPRESC0_RTC_DIV2   0x00000001UL
#define _CMU_LFAPRESC0_RTC_DIV4   0x00000002UL
#define _CMU_LFAPRESC0_RTC_DIV8   0x00000003UL
#define _CMU_LFAPRESC0_RTC_DIV16   0x00000004UL
#define _CMU_LFAPRESC0_RTC_DIV32   0x00000005UL
#define _CMU_LFAPRESC0_RTC_DIV64   0x00000006UL
#define _CMU_LFAPRESC0_RTC_DIV128   0x00000007UL
#define _CMU_LFAPRESC0_RTC_DIV256   0x00000008UL
#define _CMU_LFAPRESC0_RTC_DIV512   0x00000009UL
#define _CMU_LFAPRESC0_RTC_DIV1024   0x0000000AUL
#define _CMU_LFAPRESC0_RTC_DIV2048   0x0000000BUL
#define _CMU_LFAPRESC0_RTC_DIV4096   0x0000000CUL
#define _CMU_LFAPRESC0_RTC_DIV8192   0x0000000DUL
#define _CMU_LFAPRESC0_RTC_DIV16384   0x0000000EUL
#define _CMU_LFAPRESC0_RTC_DIV32768   0x0000000FUL
#define CMU_LFAPRESC0_RTC_DIV1   (_CMU_LFAPRESC0_RTC_DIV1 << 4)
#define CMU_LFAPRESC0_RTC_DIV2   (_CMU_LFAPRESC0_RTC_DIV2 << 4)
#define CMU_LFAPRESC0_RTC_DIV4   (_CMU_LFAPRESC0_RTC_DIV4 << 4)
#define CMU_LFAPRESC0_RTC_DIV8   (_CMU_LFAPRESC0_RTC_DIV8 << 4)
#define CMU_LFAPRESC0_RTC_DIV16   (_CMU_LFAPRESC0_RTC_DIV16 << 4)
#define CMU_LFAPRESC0_RTC_DIV32   (_CMU_LFAPRESC0_RTC_DIV32 << 4)
#define CMU_LFAPRESC0_RTC_DIV64   (_CMU_LFAPRESC0_RTC_DIV64 << 4)
#define CMU_LFAPRESC0_RTC_DIV128   (_CMU_LFAPRESC0_RTC_DIV128 << 4)
#define CMU_LFAPRESC0_RTC_DIV256   (_CMU_LFAPRESC0_RTC_DIV256 << 4)
#define CMU_LFAPRESC0_RTC_DIV512   (_CMU_LFAPRESC0_RTC_DIV512 << 4)
#define CMU_LFAPRESC0_RTC_DIV1024   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)
#define CMU_LFAPRESC0_RTC_DIV2048   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)
#define CMU_LFAPRESC0_RTC_DIV4096   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)
#define CMU_LFAPRESC0_RTC_DIV8192   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)
#define CMU_LFAPRESC0_RTC_DIV16384   (_CMU_LFAPRESC0_RTC_DIV16384 << 4)
#define CMU_LFAPRESC0_RTC_DIV32768   (_CMU_LFAPRESC0_RTC_DIV32768 << 4)
#define _CMU_LFAPRESC0_LETIMER0_SHIFT   8
#define _CMU_LFAPRESC0_LETIMER0_MASK   0xF00UL
#define _CMU_LFAPRESC0_LETIMER0_DIV1   0x00000000UL
#define _CMU_LFAPRESC0_LETIMER0_DIV2   0x00000001UL
#define _CMU_LFAPRESC0_LETIMER0_DIV4   0x00000002UL
#define _CMU_LFAPRESC0_LETIMER0_DIV8   0x00000003UL
#define _CMU_LFAPRESC0_LETIMER0_DIV16   0x00000004UL
#define _CMU_LFAPRESC0_LETIMER0_DIV32   0x00000005UL
#define _CMU_LFAPRESC0_LETIMER0_DIV64   0x00000006UL
#define _CMU_LFAPRESC0_LETIMER0_DIV128   0x00000007UL
#define _CMU_LFAPRESC0_LETIMER0_DIV256   0x00000008UL
#define _CMU_LFAPRESC0_LETIMER0_DIV512   0x00000009UL
#define _CMU_LFAPRESC0_LETIMER0_DIV1024   0x0000000AUL
#define _CMU_LFAPRESC0_LETIMER0_DIV2048   0x0000000BUL
#define _CMU_LFAPRESC0_LETIMER0_DIV4096   0x0000000CUL
#define _CMU_LFAPRESC0_LETIMER0_DIV8192   0x0000000DUL
#define _CMU_LFAPRESC0_LETIMER0_DIV16384   0x0000000EUL
#define _CMU_LFAPRESC0_LETIMER0_DIV32768   0x0000000FUL
#define CMU_LFAPRESC0_LETIMER0_DIV1   (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV2   (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV4   (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV8   (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV16   (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV32   (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV64   (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV128   (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV256   (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV512   (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV1024   (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV2048   (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV4096   (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV8192   (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV16384   (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)
#define CMU_LFAPRESC0_LETIMER0_DIV32768   (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)
#define _CMU_LFBPRESC0_RESETVALUE   0x00000000UL
#define _CMU_LFBPRESC0_MASK   0x00000033UL
#define _CMU_LFBPRESC0_LEUART0_SHIFT   0
#define _CMU_LFBPRESC0_LEUART0_MASK   0x3UL
#define _CMU_LFBPRESC0_LEUART0_DIV1   0x00000000UL
#define _CMU_LFBPRESC0_LEUART0_DIV2   0x00000001UL
#define _CMU_LFBPRESC0_LEUART0_DIV4   0x00000002UL
#define _CMU_LFBPRESC0_LEUART0_DIV8   0x00000003UL
#define CMU_LFBPRESC0_LEUART0_DIV1   (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
#define CMU_LFBPRESC0_LEUART0_DIV2   (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
#define CMU_LFBPRESC0_LEUART0_DIV4   (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
#define CMU_LFBPRESC0_LEUART0_DIV8   (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
#define _CMU_LFBPRESC0_LEUART1_SHIFT   4
#define _CMU_LFBPRESC0_LEUART1_MASK   0x30UL
#define _CMU_LFBPRESC0_LEUART1_DIV1   0x00000000UL
#define _CMU_LFBPRESC0_LEUART1_DIV2   0x00000001UL
#define _CMU_LFBPRESC0_LEUART1_DIV4   0x00000002UL
#define _CMU_LFBPRESC0_LEUART1_DIV8   0x00000003UL
#define CMU_LFBPRESC0_LEUART1_DIV1   (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)
#define CMU_LFBPRESC0_LEUART1_DIV2   (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)
#define CMU_LFBPRESC0_LEUART1_DIV4   (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)
#define CMU_LFBPRESC0_LEUART1_DIV8   (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)
#define _CMU_PCNTCTRL_RESETVALUE   0x00000000UL
#define _CMU_PCNTCTRL_MASK   0x0000003FUL
#define CMU_PCNTCTRL_PCNT0CLKEN   (0x1UL << 0)
#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT   0
#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK   0x1UL
#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   0x00000000UL
#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
#define CMU_PCNTCTRL_PCNT0CLKSEL   (0x1UL << 1)
#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT   1
#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK   0x2UL
#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   0x00000000UL
#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   0x00000000UL
#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   0x00000001UL
#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
#define CMU_PCNTCTRL_PCNT1CLKEN   (0x1UL << 2)
#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT   2
#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK   0x4UL
#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT   0x00000000UL
#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)
#define CMU_PCNTCTRL_PCNT1CLKSEL   (0x1UL << 3)
#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT   3
#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK   0x8UL
#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT   0x00000000UL
#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK   0x00000000UL
#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0   0x00000001UL
#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)
#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)
#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0   (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)
#define CMU_PCNTCTRL_PCNT2CLKEN   (0x1UL << 4)
#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT   4
#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK   0x10UL
#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT   0x00000000UL
#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)
#define CMU_PCNTCTRL_PCNT2CLKSEL   (0x1UL << 5)
#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT   5
#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK   0x20UL
#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT   0x00000000UL
#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK   0x00000000UL
#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0   0x00000001UL
#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)
#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)
#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0   (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)
#define _CMU_ROUTE_RESETVALUE   0x00000000UL
#define _CMU_ROUTE_MASK   0x0000001FUL
#define CMU_ROUTE_CLKOUT0PEN   (0x1UL << 0)
#define _CMU_ROUTE_CLKOUT0PEN_SHIFT   0
#define _CMU_ROUTE_CLKOUT0PEN_MASK   0x1UL
#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT   0x00000000UL
#define CMU_ROUTE_CLKOUT0PEN_DEFAULT   (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
#define CMU_ROUTE_CLKOUT1PEN   (0x1UL << 1)
#define _CMU_ROUTE_CLKOUT1PEN_SHIFT   1
#define _CMU_ROUTE_CLKOUT1PEN_MASK   0x2UL
#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT   0x00000000UL
#define CMU_ROUTE_CLKOUT1PEN_DEFAULT   (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
#define _CMU_ROUTE_LOCATION_SHIFT   2
#define _CMU_ROUTE_LOCATION_MASK   0x1CUL
#define _CMU_ROUTE_LOCATION_LOC0   0x00000000UL
#define _CMU_ROUTE_LOCATION_DEFAULT   0x00000000UL
#define _CMU_ROUTE_LOCATION_LOC1   0x00000001UL
#define _CMU_ROUTE_LOCATION_LOC2   0x00000002UL
#define CMU_ROUTE_LOCATION_LOC0   (_CMU_ROUTE_LOCATION_LOC0 << 2)
#define CMU_ROUTE_LOCATION_DEFAULT   (_CMU_ROUTE_LOCATION_DEFAULT << 2)
#define CMU_ROUTE_LOCATION_LOC1   (_CMU_ROUTE_LOCATION_LOC1 << 2)
#define CMU_ROUTE_LOCATION_LOC2   (_CMU_ROUTE_LOCATION_LOC2 << 2)
#define _CMU_LOCK_RESETVALUE   0x00000000UL
#define _CMU_LOCK_MASK   0x0000FFFFUL
#define _CMU_LOCK_LOCKKEY_SHIFT   0
#define _CMU_LOCK_LOCKKEY_MASK   0xFFFFUL
#define _CMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL
#define _CMU_LOCK_LOCKKEY_LOCK   0x00000000UL
#define _CMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL
#define _CMU_LOCK_LOCKKEY_LOCKED   0x00000001UL
#define _CMU_LOCK_LOCKKEY_UNLOCK   0x0000580EUL
#define CMU_LOCK_LOCKKEY_DEFAULT   (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
#define CMU_LOCK_LOCKKEY_LOCK   (_CMU_LOCK_LOCKKEY_LOCK << 0)
#define CMU_LOCK_LOCKKEY_UNLOCKED   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
#define CMU_LOCK_LOCKKEY_LOCKED   (_CMU_LOCK_LOCKKEY_LOCKED << 0)
#define CMU_LOCK_LOCKKEY_UNLOCK   (_CMU_LOCK_LOCKKEY_UNLOCK << 0)

Define Documentation

#define _CMU_AUXHFRCOCTRL_BAND_11MHZ   0x00000001UL

Mode 11MHZ for CMU_AUXHFRCOCTRL

Definition at line 2391 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_14MHZ   0x00000000UL

Mode 14MHZ for CMU_AUXHFRCOCTRL

Definition at line 2390 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_1MHZ   0x00000003UL

Mode 1MHZ for CMU_AUXHFRCOCTRL

Definition at line 2393 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_21MHZ   0x00000007UL

Mode 21MHZ for CMU_AUXHFRCOCTRL

Definition at line 2395 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_28MHZ   0x00000006UL

Mode 28MHZ for CMU_AUXHFRCOCTRL

Definition at line 2394 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_7MHZ   0x00000002UL

Mode 7MHZ for CMU_AUXHFRCOCTRL

Definition at line 2392 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 2389 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_MASK   0x700UL

Bit mask for CMU_BAND

Definition at line 2388 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_BAND_SHIFT   8

Shift value for CMU_BAND

Definition at line 2387 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_MASK   0x000007FFUL

Mask for CMU_AUXHFRCOCTRL

Definition at line 2382 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_RESETVALUE   0x00000080UL

Default value for CMU_AUXHFRCOCTRL

Definition at line 2381 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT   0x00000080UL

Mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 2385 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_TUNING_MASK   0xFFUL

Bit mask for CMU_TUNING

Definition at line 2384 of file efm32lg330f256.h.

#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 2383 of file efm32lg330f256.h.

#define _CMU_CALCNT_CALCNT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCNT

Definition at line 2448 of file efm32lg330f256.h.

#define _CMU_CALCNT_CALCNT_MASK   0xFFFFFUL

Bit mask for CMU_CALCNT

Definition at line 2447 of file efm32lg330f256.h.

#define _CMU_CALCNT_CALCNT_SHIFT   0

Shift value for CMU_CALCNT

Definition at line 2446 of file efm32lg330f256.h.

#define _CMU_CALCNT_MASK   0x000FFFFFUL

Mask for CMU_CALCNT

Definition at line 2445 of file efm32lg330f256.h.

#define _CMU_CALCNT_RESETVALUE   0x00000000UL

Default value for CMU_CALCNT

Definition at line 2444 of file efm32lg330f256.h.

#define _CMU_CALCTRL_CONT_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 2440 of file efm32lg330f256.h.

#define _CMU_CALCTRL_CONT_MASK   0x40UL

Bit mask for CMU_CONT

Definition at line 2439 of file efm32lg330f256.h.

#define _CMU_CALCTRL_CONT_SHIFT   6

Shift value for CMU_CONT

Definition at line 2438 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_AUXHFRCO   0x00000005UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 2429 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 2423 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_HFCLK   0x00000000UL

Mode HFCLK for CMU_CALCTRL

Definition at line 2424 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_HFRCO   0x00000003UL

Mode HFRCO for CMU_CALCTRL

Definition at line 2427 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_HFXO   0x00000001UL

Mode HFXO for CMU_CALCTRL

Definition at line 2425 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_LFRCO   0x00000004UL

Mode LFRCO for CMU_CALCTRL

Definition at line 2428 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_LFXO   0x00000002UL

Mode LFXO for CMU_CALCTRL

Definition at line 2426 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_MASK   0x38UL

Bit mask for CMU_DOWNSEL

Definition at line 2422 of file efm32lg330f256.h.

#define _CMU_CALCTRL_DOWNSEL_SHIFT   3

Shift value for CMU_DOWNSEL

Definition at line 2421 of file efm32lg330f256.h.

#define _CMU_CALCTRL_MASK   0x0000007FUL

Mask for CMU_CALCTRL

Definition at line 2406 of file efm32lg330f256.h.

#define _CMU_CALCTRL_RESETVALUE   0x00000000UL

Default value for CMU_CALCTRL

Definition at line 2405 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_AUXHFRCO   0x00000004UL

Mode AUXHFRCO for CMU_CALCTRL

Definition at line 2414 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CALCTRL

Definition at line 2409 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_HFRCO   0x00000002UL

Mode HFRCO for CMU_CALCTRL

Definition at line 2412 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_HFXO   0x00000000UL

Mode HFXO for CMU_CALCTRL

Definition at line 2410 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_LFRCO   0x00000003UL

Mode LFRCO for CMU_CALCTRL

Definition at line 2413 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_LFXO   0x00000001UL

Mode LFXO for CMU_CALCTRL

Definition at line 2411 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_MASK   0x7UL

Bit mask for CMU_UPSEL

Definition at line 2408 of file efm32lg330f256.h.

#define _CMU_CALCTRL_UPSEL_SHIFT   0

Shift value for CMU_UPSEL

Definition at line 2407 of file efm32lg330f256.h.

#define _CMU_CMD_CALSTART_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 2523 of file efm32lg330f256.h.

#define _CMU_CMD_CALSTART_MASK   0x8UL

Bit mask for CMU_CALSTART

Definition at line 2522 of file efm32lg330f256.h.

#define _CMU_CMD_CALSTART_SHIFT   3

Shift value for CMU_CALSTART

Definition at line 2521 of file efm32lg330f256.h.

#define _CMU_CMD_CALSTOP_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 2528 of file efm32lg330f256.h.

#define _CMU_CMD_CALSTOP_MASK   0x10UL

Bit mask for CMU_CALSTOP

Definition at line 2527 of file efm32lg330f256.h.

#define _CMU_CMD_CALSTOP_SHIFT   4

Shift value for CMU_CALSTOP

Definition at line 2526 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 2510 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_HFRCO   0x00000001UL

Mode HFRCO for CMU_CMD

Definition at line 2511 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_HFXO   0x00000002UL

Mode HFXO for CMU_CMD

Definition at line 2512 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_LFRCO   0x00000003UL

Mode LFRCO for CMU_CMD

Definition at line 2513 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_LFXO   0x00000004UL

Mode LFXO for CMU_CMD

Definition at line 2514 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_MASK   0x7UL

Bit mask for CMU_HFCLKSEL

Definition at line 2509 of file efm32lg330f256.h.

#define _CMU_CMD_HFCLKSEL_SHIFT   0

Shift value for CMU_HFCLKSEL

Definition at line 2508 of file efm32lg330f256.h.

#define _CMU_CMD_MASK   0x0000007FUL

Mask for CMU_CMD

Definition at line 2507 of file efm32lg330f256.h.

#define _CMU_CMD_RESETVALUE   0x00000000UL

Default value for CMU_CMD

Definition at line 2506 of file efm32lg330f256.h.

#define _CMU_CMD_USBCCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CMD

Definition at line 2532 of file efm32lg330f256.h.

#define _CMU_CMD_USBCCLKSEL_HFCLKNODIV   0x00000001UL

Mode HFCLKNODIV for CMU_CMD

Definition at line 2533 of file efm32lg330f256.h.

#define _CMU_CMD_USBCCLKSEL_LFRCO   0x00000003UL

Mode LFRCO for CMU_CMD

Definition at line 2535 of file efm32lg330f256.h.

#define _CMU_CMD_USBCCLKSEL_LFXO   0x00000002UL

Mode LFXO for CMU_CMD

Definition at line 2534 of file efm32lg330f256.h.

#define _CMU_CMD_USBCCLKSEL_MASK   0x60UL

Bit mask for CMU_USBCCLKSEL

Definition at line 2531 of file efm32lg330f256.h.

#define _CMU_CMD_USBCCLKSEL_SHIFT   5

Shift value for CMU_USBCCLKSEL

Definition at line 2530 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO   0x00000007UL

Mode AUXHFRCO for CMU_CTRL

Definition at line 2229 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2221 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK16   0x00000005UL

Mode HFCLK16 for CMU_CTRL

Definition at line 2227 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK2   0x00000002UL

Mode HFCLK2 for CMU_CTRL

Definition at line 2224 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK4   0x00000003UL

Mode HFCLK4 for CMU_CTRL

Definition at line 2225 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_HFCLK8   0x00000004UL

Mode HFCLK8 for CMU_CTRL

Definition at line 2226 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_HFRCO   0x00000000UL

Mode HFRCO for CMU_CTRL

Definition at line 2222 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_HFXO   0x00000001UL

Mode HFXO for CMU_CTRL

Definition at line 2223 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_MASK   0x700000UL

Bit mask for CMU_CLKOUTSEL0

Definition at line 2220 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_SHIFT   20

Shift value for CMU_CLKOUTSEL0

Definition at line 2219 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL0_ULFRCO   0x00000006UL

Mode ULFRCO for CMU_CTRL

Definition at line 2228 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   0x00000007UL

Mode AUXHFRCOQ for CMU_CTRL

Definition at line 2249 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2241 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_HFCLK   0x00000002UL

Mode HFCLK for CMU_CTRL

Definition at line 2244 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_HFRCOQ   0x00000006UL

Mode HFRCOQ for CMU_CTRL

Definition at line 2248 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_HFXOQ   0x00000004UL

Mode HFXOQ for CMU_CTRL

Definition at line 2246 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCO   0x00000000UL

Mode LFRCO for CMU_CTRL

Definition at line 2242 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_LFRCOQ   0x00000005UL

Mode LFRCOQ for CMU_CTRL

Definition at line 2247 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXO   0x00000001UL

Mode LFXO for CMU_CTRL

Definition at line 2243 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_LFXOQ   0x00000003UL

Mode LFXOQ for CMU_CTRL

Definition at line 2245 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_MASK   0x3800000UL

Bit mask for CMU_CLKOUTSEL1

Definition at line 2240 of file efm32lg330f256.h.

#define _CMU_CTRL_CLKOUTSEL1_SHIFT   23

Shift value for CMU_CLKOUTSEL1

Definition at line 2239 of file efm32lg330f256.h.

#define _CMU_CTRL_DBGCLK_AUXHFRCO   0x00000000UL

Mode AUXHFRCO for CMU_CTRL

Definition at line 2263 of file efm32lg330f256.h.

#define _CMU_CTRL_DBGCLK_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2262 of file efm32lg330f256.h.

#define _CMU_CTRL_DBGCLK_HFCLK   0x00000001UL

Mode HFCLK for CMU_CTRL

Definition at line 2264 of file efm32lg330f256.h.

#define _CMU_CTRL_DBGCLK_MASK   0x10000000UL

Bit mask for CMU_DBGCLK

Definition at line 2261 of file efm32lg330f256.h.

#define _CMU_CTRL_DBGCLK_SHIFT   28

Shift value for CMU_DBGCLK

Definition at line 2260 of file efm32lg330f256.h.

#define _CMU_CTRL_HFCLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2200 of file efm32lg330f256.h.

#define _CMU_CTRL_HFCLKDIV_MASK   0x1C000UL

Bit mask for CMU_HFCLKDIV

Definition at line 2199 of file efm32lg330f256.h.

#define _CMU_CTRL_HFCLKDIV_SHIFT   14

Shift value for CMU_HFCLKDIV

Definition at line 2198 of file efm32lg330f256.h.

#define _CMU_CTRL_HFLE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2271 of file efm32lg330f256.h.

#define _CMU_CTRL_HFLE_MASK   0x40000000UL

Bit mask for CMU_HFLE

Definition at line 2270 of file efm32lg330f256.h.

#define _CMU_CTRL_HFLE_SHIFT   30

Shift value for CMU_HFLE

Definition at line 2269 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_100PCENT   0x00000003UL

Mode 100PCENT for CMU_CTRL

Definition at line 2148 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_50PCENT   0x00000000UL

Mode 50PCENT for CMU_CTRL

Definition at line 2144 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_70PCENT   0x00000001UL

Mode 70PCENT for CMU_CTRL

Definition at line 2145 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_80PCENT   0x00000002UL

Mode 80PCENT for CMU_CTRL

Definition at line 2146 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_DEFAULT   0x00000003UL

Mode DEFAULT for CMU_CTRL

Definition at line 2147 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_MASK   0xCUL

Bit mask for CMU_HFXOBOOST

Definition at line 2143 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBOOST_SHIFT   2

Shift value for CMU_HFXOBOOST

Definition at line 2142 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ   0x00000003UL

Mode BOOSTABOVE32MHZ for CMU_CTRL

Definition at line 2158 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ   0x00000001UL

Mode BOOSTUPTO32MHZ for CMU_CTRL

Definition at line 2157 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBUFCUR_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_CTRL

Definition at line 2156 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBUFCUR_MASK   0x60UL

Bit mask for CMU_HFXOBUFCUR

Definition at line 2155 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOBUFCUR_SHIFT   5

Shift value for CMU_HFXOBUFCUR

Definition at line 2154 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2165 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOGLITCHDETEN_MASK   0x80UL

Bit mask for CMU_HFXOGLITCHDETEN

Definition at line 2164 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT   7

Shift value for CMU_HFXOGLITCHDETEN

Definition at line 2163 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOMODE_BUFEXTCLK   0x00000001UL

Mode BUFEXTCLK for CMU_CTRL

Definition at line 2136 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOMODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2134 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOMODE_DIGEXTCLK   0x00000002UL

Mode DIGEXTCLK for CMU_CTRL

Definition at line 2137 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOMODE_MASK   0x3UL

Bit mask for CMU_HFXOMODE

Definition at line 2133 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOMODE_SHIFT   0

Shift value for CMU_HFXOMODE

Definition at line 2132 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOMODE_XTAL   0x00000000UL

Mode XTAL for CMU_CTRL

Definition at line 2135 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES   0x00000003UL

Mode 16KCYCLES for CMU_CTRL

Definition at line 2173 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES   0x00000002UL

Mode 1KCYCLES for CMU_CTRL

Definition at line 2171 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_256CYCLES   0x00000001UL

Mode 256CYCLES for CMU_CTRL

Definition at line 2170 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_8CYCLES   0x00000000UL

Mode 8CYCLES for CMU_CTRL

Definition at line 2169 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_DEFAULT   0x00000003UL

Mode DEFAULT for CMU_CTRL

Definition at line 2172 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_MASK   0x600UL

Bit mask for CMU_HFXOTIMEOUT

Definition at line 2168 of file efm32lg330f256.h.

#define _CMU_CTRL_HFXOTIMEOUT_SHIFT   9

Shift value for CMU_HFXOTIMEOUT

Definition at line 2167 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBOOST_100PCENT   0x00000001UL

Mode 100PCENT for CMU_CTRL

Definition at line 2194 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBOOST_70PCENT   0x00000000UL

Mode 70PCENT for CMU_CTRL

Definition at line 2192 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBOOST_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_CTRL

Definition at line 2193 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBOOST_MASK   0x2000UL

Bit mask for CMU_LFXOBOOST

Definition at line 2191 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBOOST_SHIFT   13

Shift value for CMU_LFXOBOOST

Definition at line 2190 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBUFCUR_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2205 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBUFCUR_MASK   0x20000UL

Bit mask for CMU_LFXOBUFCUR

Definition at line 2204 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOBUFCUR_SHIFT   17

Shift value for CMU_LFXOBUFCUR

Definition at line 2203 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOMODE_BUFEXTCLK   0x00000001UL

Mode BUFEXTCLK for CMU_CTRL

Definition at line 2183 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOMODE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_CTRL

Definition at line 2181 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOMODE_DIGEXTCLK   0x00000002UL

Mode DIGEXTCLK for CMU_CTRL

Definition at line 2184 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOMODE_MASK   0x1800UL

Bit mask for CMU_LFXOMODE

Definition at line 2180 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOMODE_SHIFT   11

Shift value for CMU_LFXOMODE

Definition at line 2179 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOMODE_XTAL   0x00000000UL

Mode XTAL for CMU_CTRL

Definition at line 2182 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES   0x00000002UL

Mode 16KCYCLES for CMU_CTRL

Definition at line 2211 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES   0x00000001UL

Mode 1KCYCLES for CMU_CTRL

Definition at line 2210 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES   0x00000003UL

Mode 32KCYCLES for CMU_CTRL

Definition at line 2213 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_8CYCLES   0x00000000UL

Mode 8CYCLES for CMU_CTRL

Definition at line 2209 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_DEFAULT   0x00000003UL

Mode DEFAULT for CMU_CTRL

Definition at line 2212 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_MASK   0xC0000UL

Bit mask for CMU_LFXOTIMEOUT

Definition at line 2208 of file efm32lg330f256.h.

#define _CMU_CTRL_LFXOTIMEOUT_SHIFT   18

Shift value for CMU_LFXOTIMEOUT

Definition at line 2207 of file efm32lg330f256.h.

#define _CMU_CTRL_MASK   0x53FFFEEFUL

Mask for CMU_CTRL

Definition at line 2131 of file efm32lg330f256.h.

#define _CMU_CTRL_RESETVALUE   0x000C262CUL

Default value for CMU_CTRL

Definition at line 2130 of file efm32lg330f256.h.

#define _CMU_FREEZE_MASK   0x00000001UL

Mask for CMU_FREEZE

Definition at line 2997 of file efm32lg330f256.h.

#define _CMU_FREEZE_REGFREEZE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_FREEZE

Definition at line 3001 of file efm32lg330f256.h.

#define _CMU_FREEZE_REGFREEZE_FREEZE   0x00000001UL

Mode FREEZE for CMU_FREEZE

Definition at line 3003 of file efm32lg330f256.h.

#define _CMU_FREEZE_REGFREEZE_MASK   0x1UL

Bit mask for CMU_REGFREEZE

Definition at line 3000 of file efm32lg330f256.h.

#define _CMU_FREEZE_REGFREEZE_SHIFT   0

Shift value for CMU_REGFREEZE

Definition at line 2999 of file efm32lg330f256.h.

#define _CMU_FREEZE_REGFREEZE_UPDATE   0x00000000UL

Mode UPDATE for CMU_FREEZE

Definition at line 3002 of file efm32lg330f256.h.

#define _CMU_FREEZE_RESETVALUE   0x00000000UL

Default value for CMU_FREEZE

Definition at line 2996 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 2279 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK   0x00000000UL

Mode HFCLK for CMU_HFCORECLKDIV

Definition at line 2280 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128   0x00000007UL

Mode HFCLK128 for CMU_HFCORECLKDIV

Definition at line 2287 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16   0x00000004UL

Mode HFCLK16 for CMU_HFCORECLKDIV

Definition at line 2284 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2   0x00000001UL

Mode HFCLK2 for CMU_HFCORECLKDIV

Definition at line 2281 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256   0x00000008UL

Mode HFCLK256 for CMU_HFCORECLKDIV

Definition at line 2288 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32   0x00000005UL

Mode HFCLK32 for CMU_HFCORECLKDIV

Definition at line 2285 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4   0x00000002UL

Mode HFCLK4 for CMU_HFCORECLKDIV

Definition at line 2282 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512   0x00000009UL

Mode HFCLK512 for CMU_HFCORECLKDIV

Definition at line 2289 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64   0x00000006UL

Mode HFCLK64 for CMU_HFCORECLKDIV

Definition at line 2286 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8   0x00000003UL

Mode HFCLK8 for CMU_HFCORECLKDIV

Definition at line 2283 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK   0xFUL

Bit mask for CMU_HFCORECLKDIV

Definition at line 2278 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT   0

Shift value for CMU_HFCORECLKDIV

Definition at line 2277 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 2304 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2   0x00000000UL

Mode DIV2 for CMU_HFCORECLKDIV

Definition at line 2305 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4   0x00000001UL

Mode DIV4 for CMU_HFCORECLKDIV

Definition at line 2306 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK   0x100UL

Bit mask for CMU_HFCORECLKLEDIV

Definition at line 2303 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT   8

Shift value for CMU_HFCORECLKLEDIV

Definition at line 2302 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_MASK   0x0000010FUL

Mask for CMU_HFCORECLKDIV

Definition at line 2276 of file efm32lg330f256.h.

#define _CMU_HFCORECLKDIV_RESETVALUE   0x00000000UL

Default value for CMU_HFCORECLKDIV

Definition at line 2275 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_AES_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2869 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_AES_MASK   0x2UL

Bit mask for CMU_AES

Definition at line 2868 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_AES_SHIFT   1

Shift value for CMU_AES

Definition at line 2867 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_DMA_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2864 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_DMA_MASK   0x1UL

Bit mask for CMU_DMA

Definition at line 2863 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_DMA_SHIFT   0

Shift value for CMU_DMA

Definition at line 2862 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_LE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2884 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_LE_MASK   0x10UL

Bit mask for CMU_LE

Definition at line 2883 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_LE_SHIFT   4

Shift value for CMU_LE

Definition at line 2882 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_MASK   0x0000001FUL

Mask for CMU_HFCORECLKEN0

Definition at line 2860 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_HFCORECLKEN0

Definition at line 2859 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_USB_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2879 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_USB_MASK   0x8UL

Bit mask for CMU_USB

Definition at line 2878 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_USB_SHIFT   3

Shift value for CMU_USB

Definition at line 2877 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_USBC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2874 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_USBC_MASK   0x4UL

Bit mask for CMU_USBC

Definition at line 2873 of file efm32lg330f256.h.

#define _CMU_HFCORECLKEN0_USBC_SHIFT   2

Shift value for CMU_USBC

Definition at line 2872 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 2316 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK   0x00000000UL

Mode HFCLK for CMU_HFPERCLKDIV

Definition at line 2317 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128   0x00000007UL

Mode HFCLK128 for CMU_HFPERCLKDIV

Definition at line 2324 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16   0x00000004UL

Mode HFCLK16 for CMU_HFPERCLKDIV

Definition at line 2321 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2   0x00000001UL

Mode HFCLK2 for CMU_HFPERCLKDIV

Definition at line 2318 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256   0x00000008UL

Mode HFCLK256 for CMU_HFPERCLKDIV

Definition at line 2325 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32   0x00000005UL

Mode HFCLK32 for CMU_HFPERCLKDIV

Definition at line 2322 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4   0x00000002UL

Mode HFCLK4 for CMU_HFPERCLKDIV

Definition at line 2319 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512   0x00000009UL

Mode HFCLK512 for CMU_HFPERCLKDIV

Definition at line 2326 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64   0x00000006UL

Mode HFCLK64 for CMU_HFPERCLKDIV

Definition at line 2323 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8   0x00000003UL

Mode HFCLK8 for CMU_HFPERCLKDIV

Definition at line 2320 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK   0xFUL

Bit mask for CMU_HFPERCLKDIV

Definition at line 2315 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT   0

Shift value for CMU_HFPERCLKDIV

Definition at line 2314 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 2341 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK   0x100UL

Bit mask for CMU_HFPERCLKEN

Definition at line 2340 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT   8

Shift value for CMU_HFPERCLKEN

Definition at line 2339 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_MASK   0x0000010FUL

Mask for CMU_HFPERCLKDIV

Definition at line 2313 of file efm32lg330f256.h.

#define _CMU_HFPERCLKDIV_RESETVALUE   0x00000100UL

Default value for CMU_HFPERCLKDIV

Definition at line 2312 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ACMP0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2928 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ACMP0_MASK   0x200UL

Bit mask for CMU_ACMP0

Definition at line 2927 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ACMP0_SHIFT   9

Shift value for CMU_ACMP0

Definition at line 2926 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ACMP1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2933 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ACMP1_MASK   0x400UL

Bit mask for CMU_ACMP1

Definition at line 2932 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ACMP1_SHIFT   10

Shift value for CMU_ACMP1

Definition at line 2931 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ADC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2963 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ADC0_MASK   0x10000UL

Bit mask for CMU_ADC0

Definition at line 2962 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_ADC0_SHIFT   16

Shift value for CMU_ADC0

Definition at line 2961 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_DAC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2968 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_DAC0_MASK   0x20000UL

Bit mask for CMU_DAC0

Definition at line 2967 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_DAC0_SHIFT   17

Shift value for CMU_DAC0

Definition at line 2966 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_GPIO_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2948 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_GPIO_MASK   0x2000UL

Bit mask for CMU_GPIO

Definition at line 2947 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_GPIO_SHIFT   13

Shift value for CMU_GPIO

Definition at line 2946 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_I2C0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2938 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_I2C0_MASK   0x800UL

Bit mask for CMU_I2C0

Definition at line 2937 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_I2C0_SHIFT   11

Shift value for CMU_I2C0

Definition at line 2936 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_I2C1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2943 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_I2C1_MASK   0x1000UL

Bit mask for CMU_I2C1

Definition at line 2942 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_I2C1_SHIFT   12

Shift value for CMU_I2C1

Definition at line 2941 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_MASK   0x0003FFE7UL

Mask for CMU_HFPERCLKEN0

Definition at line 2889 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_PRS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2958 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_PRS_MASK   0x8000UL

Bit mask for CMU_PRS

Definition at line 2957 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_PRS_SHIFT   15

Shift value for CMU_PRS

Definition at line 2956 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_HFPERCLKEN0

Definition at line 2888 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2908 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER0_MASK   0x20UL

Bit mask for CMU_TIMER0

Definition at line 2907 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER0_SHIFT   5

Shift value for CMU_TIMER0

Definition at line 2906 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2913 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER1_MASK   0x40UL

Bit mask for CMU_TIMER1

Definition at line 2912 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER1_SHIFT   6

Shift value for CMU_TIMER1

Definition at line 2911 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER2_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2918 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER2_MASK   0x80UL

Bit mask for CMU_TIMER2

Definition at line 2917 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER2_SHIFT   7

Shift value for CMU_TIMER2

Definition at line 2916 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER3_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2923 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER3_MASK   0x100UL

Bit mask for CMU_TIMER3

Definition at line 2922 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_TIMER3_SHIFT   8

Shift value for CMU_TIMER3

Definition at line 2921 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2893 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART0_MASK   0x1UL

Bit mask for CMU_USART0

Definition at line 2892 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART0_SHIFT   0

Shift value for CMU_USART0

Definition at line 2891 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2898 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART1_MASK   0x2UL

Bit mask for CMU_USART1

Definition at line 2897 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART1_SHIFT   1

Shift value for CMU_USART1

Definition at line 2896 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART2_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2903 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART2_MASK   0x4UL

Bit mask for CMU_USART2

Definition at line 2902 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_USART2_SHIFT   2

Shift value for CMU_USART2

Definition at line 2901 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_VCMP_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2953 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_VCMP_MASK   0x4000UL

Bit mask for CMU_VCMP

Definition at line 2952 of file efm32lg330f256.h.

#define _CMU_HFPERCLKEN0_VCMP_SHIFT   14

Shift value for CMU_VCMP

Definition at line 2951 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_11MHZ   0x00000002UL

Mode 11MHZ for CMU_HFRCOCTRL

Definition at line 2355 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_14MHZ   0x00000003UL

Mode 14MHZ for CMU_HFRCOCTRL

Definition at line 2357 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_1MHZ   0x00000000UL

Mode 1MHZ for CMU_HFRCOCTRL

Definition at line 2353 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_21MHZ   0x00000004UL

Mode 21MHZ for CMU_HFRCOCTRL

Definition at line 2358 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_28MHZ   0x00000005UL

Mode 28MHZ for CMU_HFRCOCTRL

Definition at line 2359 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_7MHZ   0x00000001UL

Mode 7MHZ for CMU_HFRCOCTRL

Definition at line 2354 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_DEFAULT   0x00000003UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 2356 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_MASK   0x700UL

Bit mask for CMU_BAND

Definition at line 2352 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_BAND_SHIFT   8

Shift value for CMU_BAND

Definition at line 2351 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_MASK   0x0001F7FFUL

Mask for CMU_HFRCOCTRL

Definition at line 2346 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_RESETVALUE   0x00000380UL

Default value for CMU_HFRCOCTRL

Definition at line 2345 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_SUDELAY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 2369 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_SUDELAY_MASK   0x1F000UL

Bit mask for CMU_SUDELAY

Definition at line 2368 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_SUDELAY_SHIFT   12

Shift value for CMU_SUDELAY

Definition at line 2367 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_TUNING_DEFAULT   0x00000080UL

Mode DEFAULT for CMU_HFRCOCTRL

Definition at line 2349 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_TUNING_MASK   0xFFUL

Bit mask for CMU_TUNING

Definition at line 2348 of file efm32lg330f256.h.

#define _CMU_HFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 2347 of file efm32lg330f256.h.

#define _CMU_IEN_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2840 of file efm32lg330f256.h.

#define _CMU_IEN_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 2839 of file efm32lg330f256.h.

#define _CMU_IEN_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 2838 of file efm32lg330f256.h.

#define _CMU_IEN_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2850 of file efm32lg330f256.h.

#define _CMU_IEN_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 2849 of file efm32lg330f256.h.

#define _CMU_IEN_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 2848 of file efm32lg330f256.h.

#define _CMU_IEN_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2845 of file efm32lg330f256.h.

#define _CMU_IEN_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 2844 of file efm32lg330f256.h.

#define _CMU_IEN_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 2843 of file efm32lg330f256.h.

#define _CMU_IEN_HFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2820 of file efm32lg330f256.h.

#define _CMU_IEN_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 2819 of file efm32lg330f256.h.

#define _CMU_IEN_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 2818 of file efm32lg330f256.h.

#define _CMU_IEN_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2825 of file efm32lg330f256.h.

#define _CMU_IEN_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 2824 of file efm32lg330f256.h.

#define _CMU_IEN_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 2823 of file efm32lg330f256.h.

#define _CMU_IEN_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2830 of file efm32lg330f256.h.

#define _CMU_IEN_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 2829 of file efm32lg330f256.h.

#define _CMU_IEN_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 2828 of file efm32lg330f256.h.

#define _CMU_IEN_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2835 of file efm32lg330f256.h.

#define _CMU_IEN_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 2834 of file efm32lg330f256.h.

#define _CMU_IEN_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 2833 of file efm32lg330f256.h.

#define _CMU_IEN_MASK   0x000000FFUL

Mask for CMU_IEN

Definition at line 2816 of file efm32lg330f256.h.

#define _CMU_IEN_RESETVALUE   0x00000000UL

Default value for CMU_IEN

Definition at line 2815 of file efm32lg330f256.h.

#define _CMU_IEN_USBCHFCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IEN

Definition at line 2855 of file efm32lg330f256.h.

#define _CMU_IEN_USBCHFCLKSEL_MASK   0x80UL

Bit mask for CMU_USBCHFCLKSEL

Definition at line 2854 of file efm32lg330f256.h.

#define _CMU_IEN_USBCHFCLKSEL_SHIFT   7

Shift value for CMU_USBCHFCLKSEL

Definition at line 2853 of file efm32lg330f256.h.

#define _CMU_IF_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2707 of file efm32lg330f256.h.

#define _CMU_IF_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 2706 of file efm32lg330f256.h.

#define _CMU_IF_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 2705 of file efm32lg330f256.h.

#define _CMU_IF_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2717 of file efm32lg330f256.h.

#define _CMU_IF_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 2716 of file efm32lg330f256.h.

#define _CMU_IF_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 2715 of file efm32lg330f256.h.

#define _CMU_IF_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2712 of file efm32lg330f256.h.

#define _CMU_IF_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 2711 of file efm32lg330f256.h.

#define _CMU_IF_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 2710 of file efm32lg330f256.h.

#define _CMU_IF_HFRCORDY_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_IF

Definition at line 2687 of file efm32lg330f256.h.

#define _CMU_IF_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 2686 of file efm32lg330f256.h.

#define _CMU_IF_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 2685 of file efm32lg330f256.h.

#define _CMU_IF_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2692 of file efm32lg330f256.h.

#define _CMU_IF_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 2691 of file efm32lg330f256.h.

#define _CMU_IF_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 2690 of file efm32lg330f256.h.

#define _CMU_IF_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2697 of file efm32lg330f256.h.

#define _CMU_IF_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 2696 of file efm32lg330f256.h.

#define _CMU_IF_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 2695 of file efm32lg330f256.h.

#define _CMU_IF_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2702 of file efm32lg330f256.h.

#define _CMU_IF_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 2701 of file efm32lg330f256.h.

#define _CMU_IF_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 2700 of file efm32lg330f256.h.

#define _CMU_IF_MASK   0x000000FFUL

Mask for CMU_IF

Definition at line 2683 of file efm32lg330f256.h.

#define _CMU_IF_RESETVALUE   0x00000001UL

Default value for CMU_IF

Definition at line 2682 of file efm32lg330f256.h.

#define _CMU_IF_USBCHFCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IF

Definition at line 2722 of file efm32lg330f256.h.

#define _CMU_IF_USBCHFCLKSEL_MASK   0x80UL

Bit mask for CMU_USBCHFCLKSEL

Definition at line 2721 of file efm32lg330f256.h.

#define _CMU_IF_USBCHFCLKSEL_SHIFT   7

Shift value for CMU_USBCHFCLKSEL

Definition at line 2720 of file efm32lg330f256.h.

#define _CMU_IFC_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2796 of file efm32lg330f256.h.

#define _CMU_IFC_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 2795 of file efm32lg330f256.h.

#define _CMU_IFC_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 2794 of file efm32lg330f256.h.

#define _CMU_IFC_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2806 of file efm32lg330f256.h.

#define _CMU_IFC_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 2805 of file efm32lg330f256.h.

#define _CMU_IFC_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 2804 of file efm32lg330f256.h.

#define _CMU_IFC_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2801 of file efm32lg330f256.h.

#define _CMU_IFC_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 2800 of file efm32lg330f256.h.

#define _CMU_IFC_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 2799 of file efm32lg330f256.h.

#define _CMU_IFC_HFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2776 of file efm32lg330f256.h.

#define _CMU_IFC_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 2775 of file efm32lg330f256.h.

#define _CMU_IFC_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 2774 of file efm32lg330f256.h.

#define _CMU_IFC_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2781 of file efm32lg330f256.h.

#define _CMU_IFC_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 2780 of file efm32lg330f256.h.

#define _CMU_IFC_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 2779 of file efm32lg330f256.h.

#define _CMU_IFC_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2786 of file efm32lg330f256.h.

#define _CMU_IFC_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 2785 of file efm32lg330f256.h.

#define _CMU_IFC_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 2784 of file efm32lg330f256.h.

#define _CMU_IFC_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2791 of file efm32lg330f256.h.

#define _CMU_IFC_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 2790 of file efm32lg330f256.h.

#define _CMU_IFC_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 2789 of file efm32lg330f256.h.

#define _CMU_IFC_MASK   0x000000FFUL

Mask for CMU_IFC

Definition at line 2772 of file efm32lg330f256.h.

#define _CMU_IFC_RESETVALUE   0x00000000UL

Default value for CMU_IFC

Definition at line 2771 of file efm32lg330f256.h.

#define _CMU_IFC_USBCHFCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFC

Definition at line 2811 of file efm32lg330f256.h.

#define _CMU_IFC_USBCHFCLKSEL_MASK   0x80UL

Bit mask for CMU_USBCHFCLKSEL

Definition at line 2810 of file efm32lg330f256.h.

#define _CMU_IFC_USBCHFCLKSEL_SHIFT   7

Shift value for CMU_USBCHFCLKSEL

Definition at line 2809 of file efm32lg330f256.h.

#define _CMU_IFS_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2752 of file efm32lg330f256.h.

#define _CMU_IFS_AUXHFRCORDY_MASK   0x10UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 2751 of file efm32lg330f256.h.

#define _CMU_IFS_AUXHFRCORDY_SHIFT   4

Shift value for CMU_AUXHFRCORDY

Definition at line 2750 of file efm32lg330f256.h.

#define _CMU_IFS_CALOF_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2762 of file efm32lg330f256.h.

#define _CMU_IFS_CALOF_MASK   0x40UL

Bit mask for CMU_CALOF

Definition at line 2761 of file efm32lg330f256.h.

#define _CMU_IFS_CALOF_SHIFT   6

Shift value for CMU_CALOF

Definition at line 2760 of file efm32lg330f256.h.

#define _CMU_IFS_CALRDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2757 of file efm32lg330f256.h.

#define _CMU_IFS_CALRDY_MASK   0x20UL

Bit mask for CMU_CALRDY

Definition at line 2756 of file efm32lg330f256.h.

#define _CMU_IFS_CALRDY_SHIFT   5

Shift value for CMU_CALRDY

Definition at line 2755 of file efm32lg330f256.h.

#define _CMU_IFS_HFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2731 of file efm32lg330f256.h.

#define _CMU_IFS_HFRCORDY_MASK   0x1UL

Bit mask for CMU_HFRCORDY

Definition at line 2730 of file efm32lg330f256.h.

#define _CMU_IFS_HFRCORDY_SHIFT   0

Shift value for CMU_HFRCORDY

Definition at line 2729 of file efm32lg330f256.h.

#define _CMU_IFS_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2737 of file efm32lg330f256.h.

#define _CMU_IFS_HFXORDY_MASK   0x2UL

Bit mask for CMU_HFXORDY

Definition at line 2735 of file efm32lg330f256.h.

#define _CMU_IFS_HFXORDY_SHIFT   1

Shift value for CMU_HFXORDY

Definition at line 2734 of file efm32lg330f256.h.

#define _CMU_IFS_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2742 of file efm32lg330f256.h.

#define _CMU_IFS_LFRCORDY_MASK   0x4UL

Bit mask for CMU_LFRCORDY

Definition at line 2741 of file efm32lg330f256.h.

#define _CMU_IFS_LFRCORDY_SHIFT   2

Shift value for CMU_LFRCORDY

Definition at line 2740 of file efm32lg330f256.h.

#define _CMU_IFS_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2747 of file efm32lg330f256.h.

#define _CMU_IFS_LFXORDY_MASK   0x8UL

Bit mask for CMU_LFXORDY

Definition at line 2746 of file efm32lg330f256.h.

#define _CMU_IFS_LFXORDY_SHIFT   3

Shift value for CMU_LFXORDY

Definition at line 2745 of file efm32lg330f256.h.

#define _CMU_IFS_MASK   0x000000FFUL

Mask for CMU_IFS

Definition at line 2727 of file efm32lg330f256.h.

#define _CMU_IFS_RESETVALUE   0x00000000UL

Default value for CMU_IFS

Definition at line 2726 of file efm32lg330f256.h.

#define _CMU_IFS_USBCHFCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_IFS

Definition at line 2767 of file efm32lg330f256.h.

#define _CMU_IFS_USBCHFCLKSEL_MASK   0x80UL

Bit mask for CMU_USBCHFCLKSEL

Definition at line 2766 of file efm32lg330f256.h.

#define _CMU_IFS_USBCHFCLKSEL_SHIFT   7

Shift value for CMU_USBCHFCLKSEL

Definition at line 2765 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_LESENSE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFACLKEN0

Definition at line 3014 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_LESENSE_MASK   0x1UL

Bit mask for CMU_LESENSE

Definition at line 3013 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_LESENSE_SHIFT   0

Shift value for CMU_LESENSE

Definition at line 3012 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_LETIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFACLKEN0

Definition at line 3024 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_LETIMER0_MASK   0x4UL

Bit mask for CMU_LETIMER0

Definition at line 3023 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_LETIMER0_SHIFT   2

Shift value for CMU_LETIMER0

Definition at line 3022 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_MASK   0x00000007UL

Mask for CMU_LFACLKEN0

Definition at line 3010 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_LFACLKEN0

Definition at line 3009 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_RTC_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFACLKEN0

Definition at line 3019 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_RTC_MASK   0x2UL

Bit mask for CMU_RTC

Definition at line 3018 of file efm32lg330f256.h.

#define _CMU_LFACLKEN0_RTC_SHIFT   1

Shift value for CMU_RTC

Definition at line 3017 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LESENSE_DIV1   0x00000000UL

Mode DIV1 for CMU_LFAPRESC0

Definition at line 3046 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LESENSE_DIV2   0x00000001UL

Mode DIV2 for CMU_LFAPRESC0

Definition at line 3047 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LESENSE_DIV4   0x00000002UL

Mode DIV4 for CMU_LFAPRESC0

Definition at line 3048 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LESENSE_DIV8   0x00000003UL

Mode DIV8 for CMU_LFAPRESC0

Definition at line 3049 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LESENSE_MASK   0x3UL

Bit mask for CMU_LESENSE

Definition at line 3045 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LESENSE_SHIFT   0

Shift value for CMU_LESENSE

Definition at line 3044 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV1   0x00000000UL

Mode DIV1 for CMU_LFAPRESC0

Definition at line 3090 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV1024   0x0000000AUL

Mode DIV1024 for CMU_LFAPRESC0

Definition at line 3100 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV128   0x00000007UL

Mode DIV128 for CMU_LFAPRESC0

Definition at line 3097 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV16   0x00000004UL

Mode DIV16 for CMU_LFAPRESC0

Definition at line 3094 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV16384   0x0000000EUL

Mode DIV16384 for CMU_LFAPRESC0

Definition at line 3104 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV2   0x00000001UL

Mode DIV2 for CMU_LFAPRESC0

Definition at line 3091 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV2048   0x0000000BUL

Mode DIV2048 for CMU_LFAPRESC0

Definition at line 3101 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV256   0x00000008UL

Mode DIV256 for CMU_LFAPRESC0

Definition at line 3098 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV32   0x00000005UL

Mode DIV32 for CMU_LFAPRESC0

Definition at line 3095 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV32768   0x0000000FUL

Mode DIV32768 for CMU_LFAPRESC0

Definition at line 3105 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV4   0x00000002UL

Mode DIV4 for CMU_LFAPRESC0

Definition at line 3092 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV4096   0x0000000CUL

Mode DIV4096 for CMU_LFAPRESC0

Definition at line 3102 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV512   0x00000009UL

Mode DIV512 for CMU_LFAPRESC0

Definition at line 3099 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV64   0x00000006UL

Mode DIV64 for CMU_LFAPRESC0

Definition at line 3096 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV8   0x00000003UL

Mode DIV8 for CMU_LFAPRESC0

Definition at line 3093 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_DIV8192   0x0000000DUL

Mode DIV8192 for CMU_LFAPRESC0

Definition at line 3103 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_MASK   0xF00UL

Bit mask for CMU_LETIMER0

Definition at line 3089 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_LETIMER0_SHIFT   8

Shift value for CMU_LETIMER0

Definition at line 3088 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_MASK   0x00000FF3UL

Mask for CMU_LFAPRESC0

Definition at line 3043 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RESETVALUE   0x00000000UL

Default value for CMU_LFAPRESC0

Definition at line 3042 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV1   0x00000000UL

Mode DIV1 for CMU_LFAPRESC0

Definition at line 3056 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV1024   0x0000000AUL

Mode DIV1024 for CMU_LFAPRESC0

Definition at line 3066 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV128   0x00000007UL

Mode DIV128 for CMU_LFAPRESC0

Definition at line 3063 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV16   0x00000004UL

Mode DIV16 for CMU_LFAPRESC0

Definition at line 3060 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV16384   0x0000000EUL

Mode DIV16384 for CMU_LFAPRESC0

Definition at line 3070 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV2   0x00000001UL

Mode DIV2 for CMU_LFAPRESC0

Definition at line 3057 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV2048   0x0000000BUL

Mode DIV2048 for CMU_LFAPRESC0

Definition at line 3067 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV256   0x00000008UL

Mode DIV256 for CMU_LFAPRESC0

Definition at line 3064 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV32   0x00000005UL

Mode DIV32 for CMU_LFAPRESC0

Definition at line 3061 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV32768   0x0000000FUL

Mode DIV32768 for CMU_LFAPRESC0

Definition at line 3071 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV4   0x00000002UL

Mode DIV4 for CMU_LFAPRESC0

Definition at line 3058 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV4096   0x0000000CUL

Mode DIV4096 for CMU_LFAPRESC0

Definition at line 3068 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV512   0x00000009UL

Mode DIV512 for CMU_LFAPRESC0

Definition at line 3065 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV64   0x00000006UL

Mode DIV64 for CMU_LFAPRESC0

Definition at line 3062 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV8   0x00000003UL

Mode DIV8 for CMU_LFAPRESC0

Definition at line 3059 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_DIV8192   0x0000000DUL

Mode DIV8192 for CMU_LFAPRESC0

Definition at line 3069 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_MASK   0xF0UL

Bit mask for CMU_RTC

Definition at line 3055 of file efm32lg330f256.h.

#define _CMU_LFAPRESC0_RTC_SHIFT   4

Shift value for CMU_RTC

Definition at line 3054 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_LEUART0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFBCLKEN0

Definition at line 3033 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_LEUART0_MASK   0x1UL

Bit mask for CMU_LEUART0

Definition at line 3032 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_LEUART0_SHIFT   0

Shift value for CMU_LEUART0

Definition at line 3031 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_LEUART1_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFBCLKEN0

Definition at line 3038 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_LEUART1_MASK   0x2UL

Bit mask for CMU_LEUART1

Definition at line 3037 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_LEUART1_SHIFT   1

Shift value for CMU_LEUART1

Definition at line 3036 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_MASK   0x00000003UL

Mask for CMU_LFBCLKEN0

Definition at line 3029 of file efm32lg330f256.h.

#define _CMU_LFBCLKEN0_RESETVALUE   0x00000000UL

Default value for CMU_LFBCLKEN0

Definition at line 3028 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART0_DIV1   0x00000000UL

Mode DIV1 for CMU_LFBPRESC0

Definition at line 3128 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART0_DIV2   0x00000001UL

Mode DIV2 for CMU_LFBPRESC0

Definition at line 3129 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART0_DIV4   0x00000002UL

Mode DIV4 for CMU_LFBPRESC0

Definition at line 3130 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART0_DIV8   0x00000003UL

Mode DIV8 for CMU_LFBPRESC0

Definition at line 3131 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART0_MASK   0x3UL

Bit mask for CMU_LEUART0

Definition at line 3127 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART0_SHIFT   0

Shift value for CMU_LEUART0

Definition at line 3126 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART1_DIV1   0x00000000UL

Mode DIV1 for CMU_LFBPRESC0

Definition at line 3138 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART1_DIV2   0x00000001UL

Mode DIV2 for CMU_LFBPRESC0

Definition at line 3139 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART1_DIV4   0x00000002UL

Mode DIV4 for CMU_LFBPRESC0

Definition at line 3140 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART1_DIV8   0x00000003UL

Mode DIV8 for CMU_LFBPRESC0

Definition at line 3141 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART1_MASK   0x30UL

Bit mask for CMU_LEUART1

Definition at line 3137 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_LEUART1_SHIFT   4

Shift value for CMU_LEUART1

Definition at line 3136 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_MASK   0x00000033UL

Mask for CMU_LFBPRESC0

Definition at line 3125 of file efm32lg330f256.h.

#define _CMU_LFBPRESC0_RESETVALUE   0x00000000UL

Default value for CMU_LFBPRESC0

Definition at line 3124 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 2547 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 2546 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2   0x00000003UL

Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 2550 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_LFRCO   0x00000001UL

Mode LFRCO for CMU_LFCLKSEL

Definition at line 2548 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_LFXO   0x00000002UL

Mode LFXO for CMU_LFCLKSEL

Definition at line 2549 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_MASK   0x3UL

Bit mask for CMU_LFA

Definition at line 2545 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFA_SHIFT   0

Shift value for CMU_LFA

Definition at line 2544 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFAE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 2571 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFAE_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 2572 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFAE_MASK   0x10000UL

Bit mask for CMU_LFAE

Definition at line 2570 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFAE_SHIFT   16

Shift value for CMU_LFAE

Definition at line 2569 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFAE_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_LFCLKSEL

Definition at line 2573 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 2559 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 2558 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2   0x00000003UL

Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 2562 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_LFRCO   0x00000001UL

Mode LFRCO for CMU_LFCLKSEL

Definition at line 2560 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_LFXO   0x00000002UL

Mode LFXO for CMU_LFCLKSEL

Definition at line 2561 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_MASK   0xCUL

Bit mask for CMU_LFB

Definition at line 2557 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFB_SHIFT   2

Shift value for CMU_LFB

Definition at line 2556 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFBE_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LFCLKSEL

Definition at line 2580 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFBE_DISABLED   0x00000000UL

Mode DISABLED for CMU_LFCLKSEL

Definition at line 2581 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFBE_MASK   0x100000UL

Bit mask for CMU_LFBE

Definition at line 2579 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFBE_SHIFT   20

Shift value for CMU_LFBE

Definition at line 2578 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_LFBE_ULFRCO   0x00000001UL

Mode ULFRCO for CMU_LFCLKSEL

Definition at line 2582 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_MASK   0x0011000FUL

Mask for CMU_LFCLKSEL

Definition at line 2543 of file efm32lg330f256.h.

#define _CMU_LFCLKSEL_RESETVALUE   0x00000005UL

Default value for CMU_LFCLKSEL

Definition at line 2542 of file efm32lg330f256.h.

#define _CMU_LFRCOCTRL_MASK   0x0000007FUL

Mask for CMU_LFRCOCTRL

Definition at line 2374 of file efm32lg330f256.h.

#define _CMU_LFRCOCTRL_RESETVALUE   0x00000040UL

Default value for CMU_LFRCOCTRL

Definition at line 2373 of file efm32lg330f256.h.

#define _CMU_LFRCOCTRL_TUNING_DEFAULT   0x00000040UL

Mode DEFAULT for CMU_LFRCOCTRL

Definition at line 2377 of file efm32lg330f256.h.

#define _CMU_LFRCOCTRL_TUNING_MASK   0x7FUL

Bit mask for CMU_TUNING

Definition at line 2376 of file efm32lg330f256.h.

#define _CMU_LFRCOCTRL_TUNING_SHIFT   0

Shift value for CMU_TUNING

Definition at line 2375 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_LOCK

Definition at line 3222 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_LOCK   0x00000000UL

Mode LOCK for CMU_LOCK

Definition at line 3223 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_LOCKED   0x00000001UL

Mode LOCKED for CMU_LOCK

Definition at line 3225 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_MASK   0xFFFFUL

Bit mask for CMU_LOCKKEY

Definition at line 3221 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_SHIFT   0

Shift value for CMU_LOCKKEY

Definition at line 3220 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_UNLOCK   0x0000580EUL

Mode UNLOCK for CMU_LOCK

Definition at line 3226 of file efm32lg330f256.h.

#define _CMU_LOCK_LOCKKEY_UNLOCKED   0x00000000UL

Mode UNLOCKED for CMU_LOCK

Definition at line 3224 of file efm32lg330f256.h.

#define _CMU_LOCK_MASK   0x0000FFFFUL

Mask for CMU_LOCK

Definition at line 3219 of file efm32lg330f256.h.

#define _CMU_LOCK_RESETVALUE   0x00000000UL

Default value for CMU_LOCK

Definition at line 3218 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2482 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_AUXHFRCODIS_MASK   0x20UL

Bit mask for CMU_AUXHFRCODIS

Definition at line 2481 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT   5

Shift value for CMU_AUXHFRCODIS

Definition at line 2480 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2477 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_AUXHFRCOEN_MASK   0x10UL

Bit mask for CMU_AUXHFRCOEN

Definition at line 2476 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT   4

Shift value for CMU_AUXHFRCOEN

Definition at line 2475 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2462 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFRCODIS_MASK   0x2UL

Bit mask for CMU_HFRCODIS

Definition at line 2461 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFRCODIS_SHIFT   1

Shift value for CMU_HFRCODIS

Definition at line 2460 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFRCOEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2457 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFRCOEN_MASK   0x1UL

Bit mask for CMU_HFRCOEN

Definition at line 2456 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFRCOEN_SHIFT   0

Shift value for CMU_HFRCOEN

Definition at line 2455 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFXODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2472 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFXODIS_MASK   0x8UL

Bit mask for CMU_HFXODIS

Definition at line 2471 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFXODIS_SHIFT   3

Shift value for CMU_HFXODIS

Definition at line 2470 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFXOEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2467 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFXOEN_MASK   0x4UL

Bit mask for CMU_HFXOEN

Definition at line 2466 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_HFXOEN_SHIFT   2

Shift value for CMU_HFXOEN

Definition at line 2465 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFRCODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2492 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFRCODIS_MASK   0x80UL

Bit mask for CMU_LFRCODIS

Definition at line 2491 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFRCODIS_SHIFT   7

Shift value for CMU_LFRCODIS

Definition at line 2490 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFRCOEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2487 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFRCOEN_MASK   0x40UL

Bit mask for CMU_LFRCOEN

Definition at line 2486 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFRCOEN_SHIFT   6

Shift value for CMU_LFRCOEN

Definition at line 2485 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFXODIS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2502 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFXODIS_MASK   0x200UL

Bit mask for CMU_LFXODIS

Definition at line 2501 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFXODIS_SHIFT   9

Shift value for CMU_LFXODIS

Definition at line 2500 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFXOEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_OSCENCMD

Definition at line 2497 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFXOEN_MASK   0x100UL

Bit mask for CMU_LFXOEN

Definition at line 2496 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_LFXOEN_SHIFT   8

Shift value for CMU_LFXOEN

Definition at line 2495 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_MASK   0x000003FFUL

Mask for CMU_OSCENCMD

Definition at line 2453 of file efm32lg330f256.h.

#define _CMU_OSCENCMD_RESETVALUE   0x00000000UL

Default value for CMU_OSCENCMD

Definition at line 2452 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_MASK   0x0000003FUL

Mask for CMU_PCNTCTRL

Definition at line 3149 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 3153 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKEN_MASK   0x1UL

Bit mask for CMU_PCNT0CLKEN

Definition at line 3152 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT   0

Shift value for CMU_PCNT0CLKEN

Definition at line 3151 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 3158 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   0x00000000UL

Mode LFACLK for CMU_PCNTCTRL

Definition at line 3159 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK   0x2UL

Bit mask for CMU_PCNT0CLKSEL

Definition at line 3157 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   0x00000001UL

Mode PCNT0S0 for CMU_PCNTCTRL

Definition at line 3160 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT   1

Shift value for CMU_PCNT0CLKSEL

Definition at line 3156 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 3167 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKEN_MASK   0x4UL

Bit mask for CMU_PCNT1CLKEN

Definition at line 3166 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT   2

Shift value for CMU_PCNT1CLKEN

Definition at line 3165 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 3172 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK   0x00000000UL

Mode LFACLK for CMU_PCNTCTRL

Definition at line 3173 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK   0x8UL

Bit mask for CMU_PCNT1CLKSEL

Definition at line 3171 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0   0x00000001UL

Mode PCNT1S0 for CMU_PCNTCTRL

Definition at line 3174 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT   3

Shift value for CMU_PCNT1CLKSEL

Definition at line 3170 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 3181 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKEN_MASK   0x10UL

Bit mask for CMU_PCNT2CLKEN

Definition at line 3180 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT   4

Shift value for CMU_PCNT2CLKEN

Definition at line 3179 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_PCNTCTRL

Definition at line 3186 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK   0x00000000UL

Mode LFACLK for CMU_PCNTCTRL

Definition at line 3187 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK   0x20UL

Bit mask for CMU_PCNT2CLKSEL

Definition at line 3185 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0   0x00000001UL

Mode PCNT2S0 for CMU_PCNTCTRL

Definition at line 3188 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT   5

Shift value for CMU_PCNT2CLKSEL

Definition at line 3184 of file efm32lg330f256.h.

#define _CMU_PCNTCTRL_RESETVALUE   0x00000000UL

Default value for CMU_PCNTCTRL

Definition at line 3148 of file efm32lg330f256.h.

#define _CMU_ROUTE_CLKOUT0PEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ROUTE

Definition at line 3199 of file efm32lg330f256.h.

#define _CMU_ROUTE_CLKOUT0PEN_MASK   0x1UL

Bit mask for CMU_CLKOUT0PEN

Definition at line 3198 of file efm32lg330f256.h.

#define _CMU_ROUTE_CLKOUT0PEN_SHIFT   0

Shift value for CMU_CLKOUT0PEN

Definition at line 3197 of file efm32lg330f256.h.

#define _CMU_ROUTE_CLKOUT1PEN_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ROUTE

Definition at line 3204 of file efm32lg330f256.h.

#define _CMU_ROUTE_CLKOUT1PEN_MASK   0x2UL

Bit mask for CMU_CLKOUT1PEN

Definition at line 3203 of file efm32lg330f256.h.

#define _CMU_ROUTE_CLKOUT1PEN_SHIFT   1

Shift value for CMU_CLKOUT1PEN

Definition at line 3202 of file efm32lg330f256.h.

#define _CMU_ROUTE_LOCATION_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_ROUTE

Definition at line 3209 of file efm32lg330f256.h.

#define _CMU_ROUTE_LOCATION_LOC0   0x00000000UL

Mode LOC0 for CMU_ROUTE

Definition at line 3208 of file efm32lg330f256.h.

#define _CMU_ROUTE_LOCATION_LOC1   0x00000001UL

Mode LOC1 for CMU_ROUTE

Definition at line 3210 of file efm32lg330f256.h.

#define _CMU_ROUTE_LOCATION_LOC2   0x00000002UL

Mode LOC2 for CMU_ROUTE

Definition at line 3211 of file efm32lg330f256.h.

#define _CMU_ROUTE_LOCATION_MASK   0x1CUL

Bit mask for CMU_LOCATION

Definition at line 3207 of file efm32lg330f256.h.

#define _CMU_ROUTE_LOCATION_SHIFT   2

Shift value for CMU_LOCATION

Definition at line 3206 of file efm32lg330f256.h.

#define _CMU_ROUTE_MASK   0x0000001FUL

Mask for CMU_ROUTE

Definition at line 3195 of file efm32lg330f256.h.

#define _CMU_ROUTE_RESETVALUE   0x00000000UL

Default value for CMU_ROUTE

Definition at line 3194 of file efm32lg330f256.h.

#define _CMU_STATUS_AUXHFRCOENS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2613 of file efm32lg330f256.h.

#define _CMU_STATUS_AUXHFRCOENS_MASK   0x10UL

Bit mask for CMU_AUXHFRCOENS

Definition at line 2612 of file efm32lg330f256.h.

#define _CMU_STATUS_AUXHFRCOENS_SHIFT   4

Shift value for CMU_AUXHFRCOENS

Definition at line 2611 of file efm32lg330f256.h.

#define _CMU_STATUS_AUXHFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2618 of file efm32lg330f256.h.

#define _CMU_STATUS_AUXHFRCORDY_MASK   0x20UL

Bit mask for CMU_AUXHFRCORDY

Definition at line 2617 of file efm32lg330f256.h.

#define _CMU_STATUS_AUXHFRCORDY_SHIFT   5

Shift value for CMU_AUXHFRCORDY

Definition at line 2616 of file efm32lg330f256.h.

#define _CMU_STATUS_CALBSY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2663 of file efm32lg330f256.h.

#define _CMU_STATUS_CALBSY_MASK   0x4000UL

Bit mask for CMU_CALBSY

Definition at line 2662 of file efm32lg330f256.h.

#define _CMU_STATUS_CALBSY_SHIFT   14

Shift value for CMU_CALBSY

Definition at line 2661 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCOENS_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_STATUS

Definition at line 2593 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCOENS_MASK   0x1UL

Bit mask for CMU_HFRCOENS

Definition at line 2592 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCOENS_SHIFT   0

Shift value for CMU_HFRCOENS

Definition at line 2591 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCORDY_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_STATUS

Definition at line 2598 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCORDY_MASK   0x2UL

Bit mask for CMU_HFRCORDY

Definition at line 2597 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCORDY_SHIFT   1

Shift value for CMU_HFRCORDY

Definition at line 2596 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCOSEL_DEFAULT   0x00000001UL

Mode DEFAULT for CMU_STATUS

Definition at line 2643 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCOSEL_MASK   0x400UL

Bit mask for CMU_HFRCOSEL

Definition at line 2642 of file efm32lg330f256.h.

#define _CMU_STATUS_HFRCOSEL_SHIFT   10

Shift value for CMU_HFRCOSEL

Definition at line 2641 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXOENS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2603 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXOENS_MASK   0x4UL

Bit mask for CMU_HFXOENS

Definition at line 2602 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXOENS_SHIFT   2

Shift value for CMU_HFXOENS

Definition at line 2601 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2608 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXORDY_MASK   0x8UL

Bit mask for CMU_HFXORDY

Definition at line 2607 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXORDY_SHIFT   3

Shift value for CMU_HFXORDY

Definition at line 2606 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXOSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2648 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXOSEL_MASK   0x800UL

Bit mask for CMU_HFXOSEL

Definition at line 2647 of file efm32lg330f256.h.

#define _CMU_STATUS_HFXOSEL_SHIFT   11

Shift value for CMU_HFXOSEL

Definition at line 2646 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCOENS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2623 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCOENS_MASK   0x40UL

Bit mask for CMU_LFRCOENS

Definition at line 2622 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCOENS_SHIFT   6

Shift value for CMU_LFRCOENS

Definition at line 2621 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2628 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCORDY_MASK   0x80UL

Bit mask for CMU_LFRCORDY

Definition at line 2627 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCORDY_SHIFT   7

Shift value for CMU_LFRCORDY

Definition at line 2626 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCOSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2653 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCOSEL_MASK   0x1000UL

Bit mask for CMU_LFRCOSEL

Definition at line 2652 of file efm32lg330f256.h.

#define _CMU_STATUS_LFRCOSEL_SHIFT   12

Shift value for CMU_LFRCOSEL

Definition at line 2651 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXOENS_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2633 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXOENS_MASK   0x100UL

Bit mask for CMU_LFXOENS

Definition at line 2632 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXOENS_SHIFT   8

Shift value for CMU_LFXOENS

Definition at line 2631 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXORDY_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2638 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXORDY_MASK   0x200UL

Bit mask for CMU_LFXORDY

Definition at line 2637 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXORDY_SHIFT   9

Shift value for CMU_LFXORDY

Definition at line 2636 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXOSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2658 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXOSEL_MASK   0x2000UL

Bit mask for CMU_LFXOSEL

Definition at line 2657 of file efm32lg330f256.h.

#define _CMU_STATUS_LFXOSEL_SHIFT   13

Shift value for CMU_LFXOSEL

Definition at line 2656 of file efm32lg330f256.h.

#define _CMU_STATUS_MASK   0x0003FFFFUL

Mask for CMU_STATUS

Definition at line 2589 of file efm32lg330f256.h.

#define _CMU_STATUS_RESETVALUE   0x00000403UL

Default value for CMU_STATUS

Definition at line 2588 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCHFCLKSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2668 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCHFCLKSEL_MASK   0x8000UL

Bit mask for CMU_USBCHFCLKSEL

Definition at line 2667 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCHFCLKSEL_SHIFT   15

Shift value for CMU_USBCHFCLKSEL

Definition at line 2666 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCLFRCOSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2678 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCLFRCOSEL_MASK   0x20000UL

Bit mask for CMU_USBCLFRCOSEL

Definition at line 2677 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCLFRCOSEL_SHIFT   17

Shift value for CMU_USBCLFRCOSEL

Definition at line 2676 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCLFXOSEL_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_STATUS

Definition at line 2673 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCLFXOSEL_MASK   0x10000UL

Bit mask for CMU_USBCLFXOSEL

Definition at line 2672 of file efm32lg330f256.h.

#define _CMU_STATUS_USBCLFXOSEL_SHIFT   16

Shift value for CMU_USBCLFXOSEL

Definition at line 2671 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 2977 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFACLKEN0_MASK   0x1UL

Bit mask for CMU_LFACLKEN0

Definition at line 2976 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFACLKEN0_SHIFT   0

Shift value for CMU_LFACLKEN0

Definition at line 2975 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 2982 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFAPRESC0_MASK   0x4UL

Bit mask for CMU_LFAPRESC0

Definition at line 2981 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFAPRESC0_SHIFT   2

Shift value for CMU_LFAPRESC0

Definition at line 2980 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 2987 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFBCLKEN0_MASK   0x10UL

Bit mask for CMU_LFBCLKEN0

Definition at line 2986 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT   4

Shift value for CMU_LFBCLKEN0

Definition at line 2985 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT   0x00000000UL

Mode DEFAULT for CMU_SYNCBUSY

Definition at line 2992 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFBPRESC0_MASK   0x40UL

Bit mask for CMU_LFBPRESC0

Definition at line 2991 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_LFBPRESC0_SHIFT   6

Shift value for CMU_LFBPRESC0

Definition at line 2990 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_MASK   0x00000055UL

Mask for CMU_SYNCBUSY

Definition at line 2973 of file efm32lg330f256.h.

#define _CMU_SYNCBUSY_RESETVALUE   0x00000000UL

Default value for CMU_SYNCBUSY

Definition at line 2972 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_11MHZ   (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)

Shifted mode 11MHZ for CMU_AUXHFRCOCTRL

Definition at line 2398 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_14MHZ   (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)

Shifted mode 14MHZ for CMU_AUXHFRCOCTRL

Definition at line 2397 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_1MHZ   (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)

Shifted mode 1MHZ for CMU_AUXHFRCOCTRL

Definition at line 2400 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_21MHZ   (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)

Shifted mode 21MHZ for CMU_AUXHFRCOCTRL

Definition at line 2402 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_28MHZ   (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)

Shifted mode 28MHZ for CMU_AUXHFRCOCTRL

Definition at line 2401 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_7MHZ   (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)

Shifted mode 7MHZ for CMU_AUXHFRCOCTRL

Definition at line 2399 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_BAND_DEFAULT   (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)

Shifted mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 2396 of file efm32lg330f256.h.

#define CMU_AUXHFRCOCTRL_TUNING_DEFAULT   (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)

Shifted mode DEFAULT for CMU_AUXHFRCOCTRL

Definition at line 2386 of file efm32lg330f256.h.

#define CMU_CALCNT_CALCNT_DEFAULT   (_CMU_CALCNT_CALCNT_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CALCNT

Definition at line 2449 of file efm32lg330f256.h.

#define CMU_CALCTRL_CONT   (0x1UL << 6)

Continuous Calibration

Definition at line 2437 of file efm32lg330f256.h.

#define CMU_CALCTRL_CONT_DEFAULT   (_CMU_CALCTRL_CONT_DEFAULT << 6)

Shifted mode DEFAULT for CMU_CALCTRL

Definition at line 2441 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_AUXHFRCO   (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)

Shifted mode AUXHFRCO for CMU_CALCTRL

Definition at line 2436 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_DEFAULT   (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)

Shifted mode DEFAULT for CMU_CALCTRL

Definition at line 2430 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_HFCLK   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)

Shifted mode HFCLK for CMU_CALCTRL

Definition at line 2431 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_HFRCO   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)

Shifted mode HFRCO for CMU_CALCTRL

Definition at line 2434 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_HFXO   (_CMU_CALCTRL_DOWNSEL_HFXO << 3)

Shifted mode HFXO for CMU_CALCTRL

Definition at line 2432 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_LFRCO   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)

Shifted mode LFRCO for CMU_CALCTRL

Definition at line 2435 of file efm32lg330f256.h.

#define CMU_CALCTRL_DOWNSEL_LFXO   (_CMU_CALCTRL_DOWNSEL_LFXO << 3)

Shifted mode LFXO for CMU_CALCTRL

Definition at line 2433 of file efm32lg330f256.h.

#define CMU_CALCTRL_UPSEL_AUXHFRCO   (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)

Shifted mode AUXHFRCO for CMU_CALCTRL

Definition at line 2420 of file efm32lg330f256.h.

#define CMU_CALCTRL_UPSEL_DEFAULT   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CALCTRL

Definition at line 2415 of file efm32lg330f256.h.

#define CMU_CALCTRL_UPSEL_HFRCO   (_CMU_CALCTRL_UPSEL_HFRCO << 0)

Shifted mode HFRCO for CMU_CALCTRL

Definition at line 2418 of file efm32lg330f256.h.

#define CMU_CALCTRL_UPSEL_HFXO   (_CMU_CALCTRL_UPSEL_HFXO << 0)

Shifted mode HFXO for CMU_CALCTRL

Definition at line 2416 of file efm32lg330f256.h.

#define CMU_CALCTRL_UPSEL_LFRCO   (_CMU_CALCTRL_UPSEL_LFRCO << 0)

Shifted mode LFRCO for CMU_CALCTRL

Definition at line 2419 of file efm32lg330f256.h.

#define CMU_CALCTRL_UPSEL_LFXO   (_CMU_CALCTRL_UPSEL_LFXO << 0)

Shifted mode LFXO for CMU_CALCTRL

Definition at line 2417 of file efm32lg330f256.h.

#define CMU_CMD_CALSTART   (0x1UL << 3)

Calibration Start

Definition at line 2520 of file efm32lg330f256.h.

#define CMU_CMD_CALSTART_DEFAULT   (_CMU_CMD_CALSTART_DEFAULT << 3)

Shifted mode DEFAULT for CMU_CMD

Definition at line 2524 of file efm32lg330f256.h.

#define CMU_CMD_CALSTOP   (0x1UL << 4)

Calibration Stop

Definition at line 2525 of file efm32lg330f256.h.

#define CMU_CMD_CALSTOP_DEFAULT   (_CMU_CMD_CALSTOP_DEFAULT << 4)

Shifted mode DEFAULT for CMU_CMD

Definition at line 2529 of file efm32lg330f256.h.

#define CMU_CMD_HFCLKSEL_DEFAULT   (_CMU_CMD_HFCLKSEL_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CMD

Definition at line 2515 of file efm32lg330f256.h.

#define CMU_CMD_HFCLKSEL_HFRCO   (_CMU_CMD_HFCLKSEL_HFRCO << 0)

Shifted mode HFRCO for CMU_CMD

Definition at line 2516 of file efm32lg330f256.h.

#define CMU_CMD_HFCLKSEL_HFXO   (_CMU_CMD_HFCLKSEL_HFXO << 0)

Shifted mode HFXO for CMU_CMD

Definition at line 2517 of file efm32lg330f256.h.

#define CMU_CMD_HFCLKSEL_LFRCO   (_CMU_CMD_HFCLKSEL_LFRCO << 0)

Shifted mode LFRCO for CMU_CMD

Definition at line 2518 of file efm32lg330f256.h.

#define CMU_CMD_HFCLKSEL_LFXO   (_CMU_CMD_HFCLKSEL_LFXO << 0)

Shifted mode LFXO for CMU_CMD

Definition at line 2519 of file efm32lg330f256.h.

#define CMU_CMD_USBCCLKSEL_DEFAULT   (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)

Shifted mode DEFAULT for CMU_CMD

Definition at line 2536 of file efm32lg330f256.h.

#define CMU_CMD_USBCCLKSEL_HFCLKNODIV   (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5)

Shifted mode HFCLKNODIV for CMU_CMD

Definition at line 2537 of file efm32lg330f256.h.

#define CMU_CMD_USBCCLKSEL_LFRCO   (_CMU_CMD_USBCCLKSEL_LFRCO << 5)

Shifted mode LFRCO for CMU_CMD

Definition at line 2539 of file efm32lg330f256.h.

#define CMU_CMD_USBCCLKSEL_LFXO   (_CMU_CMD_USBCCLKSEL_LFXO << 5)

Shifted mode LFXO for CMU_CMD

Definition at line 2538 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO   (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)

Shifted mode AUXHFRCO for CMU_CTRL

Definition at line 2238 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_DEFAULT   (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2230 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK16   (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)

Shifted mode HFCLK16 for CMU_CTRL

Definition at line 2236 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK2   (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)

Shifted mode HFCLK2 for CMU_CTRL

Definition at line 2233 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK4   (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)

Shifted mode HFCLK4 for CMU_CTRL

Definition at line 2234 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_HFCLK8   (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)

Shifted mode HFCLK8 for CMU_CTRL

Definition at line 2235 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_HFRCO   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)

Shifted mode HFRCO for CMU_CTRL

Definition at line 2231 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_HFXO   (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)

Shifted mode HFXO for CMU_CTRL

Definition at line 2232 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL0_ULFRCO   (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)

Shifted mode ULFRCO for CMU_CTRL

Definition at line 2237 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ   (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)

Shifted mode AUXHFRCOQ for CMU_CTRL

Definition at line 2258 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_DEFAULT   (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2250 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_HFCLK   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)

Shifted mode HFCLK for CMU_CTRL

Definition at line 2253 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_HFRCOQ   (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)

Shifted mode HFRCOQ for CMU_CTRL

Definition at line 2257 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_HFXOQ   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)

Shifted mode HFXOQ for CMU_CTRL

Definition at line 2255 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_LFRCO   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)

Shifted mode LFRCO for CMU_CTRL

Definition at line 2251 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_LFRCOQ   (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)

Shifted mode LFRCOQ for CMU_CTRL

Definition at line 2256 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_LFXO   (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)

Shifted mode LFXO for CMU_CTRL

Definition at line 2252 of file efm32lg330f256.h.

#define CMU_CTRL_CLKOUTSEL1_LFXOQ   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)

Shifted mode LFXOQ for CMU_CTRL

Definition at line 2254 of file efm32lg330f256.h.

#define CMU_CTRL_DBGCLK   (0x1UL << 28)

Debug Clock

Definition at line 2259 of file efm32lg330f256.h.

#define CMU_CTRL_DBGCLK_AUXHFRCO   (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)

Shifted mode AUXHFRCO for CMU_CTRL

Definition at line 2266 of file efm32lg330f256.h.

#define CMU_CTRL_DBGCLK_DEFAULT   (_CMU_CTRL_DBGCLK_DEFAULT << 28)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2265 of file efm32lg330f256.h.

#define CMU_CTRL_DBGCLK_HFCLK   (_CMU_CTRL_DBGCLK_HFCLK << 28)

Shifted mode HFCLK for CMU_CTRL

Definition at line 2267 of file efm32lg330f256.h.

#define CMU_CTRL_HFCLKDIV_DEFAULT   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2201 of file efm32lg330f256.h.

#define CMU_CTRL_HFLE   (0x1UL << 30)

High-Frequency LE Interface

Definition at line 2268 of file efm32lg330f256.h.

#define CMU_CTRL_HFLE_DEFAULT   (_CMU_CTRL_HFLE_DEFAULT << 30)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2272 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBOOST_100PCENT   (_CMU_CTRL_HFXOBOOST_100PCENT << 2)

Shifted mode 100PCENT for CMU_CTRL

Definition at line 2153 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBOOST_50PCENT   (_CMU_CTRL_HFXOBOOST_50PCENT << 2)

Shifted mode 50PCENT for CMU_CTRL

Definition at line 2149 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBOOST_70PCENT   (_CMU_CTRL_HFXOBOOST_70PCENT << 2)

Shifted mode 70PCENT for CMU_CTRL

Definition at line 2150 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBOOST_80PCENT   (_CMU_CTRL_HFXOBOOST_80PCENT << 2)

Shifted mode 80PCENT for CMU_CTRL

Definition at line 2151 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBOOST_DEFAULT   (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2152 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ   (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5)

Shifted mode BOOSTABOVE32MHZ for CMU_CTRL

Definition at line 2161 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ   (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)

Shifted mode BOOSTUPTO32MHZ for CMU_CTRL

Definition at line 2160 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOBUFCUR_DEFAULT   (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2159 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOGLITCHDETEN   (0x1UL << 7)

HFXO Glitch Detector Enable

Definition at line 2162 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT   (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2166 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOMODE_BUFEXTCLK   (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)

Shifted mode BUFEXTCLK for CMU_CTRL

Definition at line 2140 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOMODE_DEFAULT   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2138 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOMODE_DIGEXTCLK   (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)

Shifted mode DIGEXTCLK for CMU_CTRL

Definition at line 2141 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOMODE_XTAL   (_CMU_CTRL_HFXOMODE_XTAL << 0)

Shifted mode XTAL for CMU_CTRL

Definition at line 2139 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES   (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)

Shifted mode 16KCYCLES for CMU_CTRL

Definition at line 2178 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES   (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)

Shifted mode 1KCYCLES for CMU_CTRL

Definition at line 2176 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOTIMEOUT_256CYCLES   (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)

Shifted mode 256CYCLES for CMU_CTRL

Definition at line 2175 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOTIMEOUT_8CYCLES   (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)

Shifted mode 8CYCLES for CMU_CTRL

Definition at line 2174 of file efm32lg330f256.h.

#define CMU_CTRL_HFXOTIMEOUT_DEFAULT   (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2177 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOBOOST   (0x1UL << 13)

LFXO Start-up Boost Current

Definition at line 2189 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOBOOST_100PCENT   (_CMU_CTRL_LFXOBOOST_100PCENT << 13)

Shifted mode 100PCENT for CMU_CTRL

Definition at line 2197 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOBOOST_70PCENT   (_CMU_CTRL_LFXOBOOST_70PCENT << 13)

Shifted mode 70PCENT for CMU_CTRL

Definition at line 2195 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOBOOST_DEFAULT   (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2196 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOBUFCUR   (0x1UL << 17)

LFXO Boost Buffer Current

Definition at line 2202 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOBUFCUR_DEFAULT   (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2206 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOMODE_BUFEXTCLK   (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)

Shifted mode BUFEXTCLK for CMU_CTRL

Definition at line 2187 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOMODE_DEFAULT   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2185 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOMODE_DIGEXTCLK   (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)

Shifted mode DIGEXTCLK for CMU_CTRL

Definition at line 2188 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOMODE_XTAL   (_CMU_CTRL_LFXOMODE_XTAL << 11)

Shifted mode XTAL for CMU_CTRL

Definition at line 2186 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES   (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)

Shifted mode 16KCYCLES for CMU_CTRL

Definition at line 2216 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES   (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)

Shifted mode 1KCYCLES for CMU_CTRL

Definition at line 2215 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES   (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)

Shifted mode 32KCYCLES for CMU_CTRL

Definition at line 2218 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOTIMEOUT_8CYCLES   (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)

Shifted mode 8CYCLES for CMU_CTRL

Definition at line 2214 of file efm32lg330f256.h.

#define CMU_CTRL_LFXOTIMEOUT_DEFAULT   (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)

Shifted mode DEFAULT for CMU_CTRL

Definition at line 2217 of file efm32lg330f256.h.

#define CMU_FREEZE_REGFREEZE   (0x1UL << 0)

Register Update Freeze

Definition at line 2998 of file efm32lg330f256.h.

#define CMU_FREEZE_REGFREEZE_DEFAULT   (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)

Shifted mode DEFAULT for CMU_FREEZE

Definition at line 3004 of file efm32lg330f256.h.

#define CMU_FREEZE_REGFREEZE_FREEZE   (_CMU_FREEZE_REGFREEZE_FREEZE << 0)

Shifted mode FREEZE for CMU_FREEZE

Definition at line 3006 of file efm32lg330f256.h.

#define CMU_FREEZE_REGFREEZE_UPDATE   (_CMU_FREEZE_REGFREEZE_UPDATE << 0)

Shifted mode UPDATE for CMU_FREEZE

Definition at line 3005 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT   (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 2290 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)

Shifted mode HFCLK for CMU_HFCORECLKDIV

Definition at line 2291 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)

Shifted mode HFCLK128 for CMU_HFCORECLKDIV

Definition at line 2298 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)

Shifted mode HFCLK16 for CMU_HFCORECLKDIV

Definition at line 2295 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)

Shifted mode HFCLK2 for CMU_HFCORECLKDIV

Definition at line 2292 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)

Shifted mode HFCLK256 for CMU_HFCORECLKDIV

Definition at line 2299 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)

Shifted mode HFCLK32 for CMU_HFCORECLKDIV

Definition at line 2296 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)

Shifted mode HFCLK4 for CMU_HFCORECLKDIV

Definition at line 2293 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)

Shifted mode HFCLK512 for CMU_HFCORECLKDIV

Definition at line 2300 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)

Shifted mode HFCLK64 for CMU_HFCORECLKDIV

Definition at line 2297 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8   (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)

Shifted mode HFCLK8 for CMU_HFCORECLKDIV

Definition at line 2294 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV   (0x1UL << 8)

Additional Division Factor For HFCORECLKLE

Definition at line 2301 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT   (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFCORECLKDIV

Definition at line 2307 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2   (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)

Shifted mode DIV2 for CMU_HFCORECLKDIV

Definition at line 2308 of file efm32lg330f256.h.

#define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4   (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)

Shifted mode DIV4 for CMU_HFCORECLKDIV

Definition at line 2309 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_AES   (0x1UL << 1)

Advanced Encryption Standard Accelerator Clock Enable

Definition at line 2866 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_AES_DEFAULT   (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2870 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_DMA   (0x1UL << 0)

Direct Memory Access Controller Clock Enable

Definition at line 2861 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_DMA_DEFAULT   (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2865 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_LE   (0x1UL << 4)

Low Energy Peripheral Interface Clock Enable

Definition at line 2881 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_LE_DEFAULT   (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2885 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_USB   (0x1UL << 3)

Universal Serial Bus Interface Clock Enable

Definition at line 2876 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_USB_DEFAULT   (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2880 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_USBC   (0x1UL << 2)

Universal Serial Bus Interface Core Clock Enable

Definition at line 2871 of file efm32lg330f256.h.

#define CMU_HFCORECLKEN0_USBC_DEFAULT   (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2)

Shifted mode DEFAULT for CMU_HFCORECLKEN0

Definition at line 2875 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT   (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 2327 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)

Shifted mode HFCLK for CMU_HFPERCLKDIV

Definition at line 2328 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)

Shifted mode HFCLK128 for CMU_HFPERCLKDIV

Definition at line 2335 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)

Shifted mode HFCLK16 for CMU_HFPERCLKDIV

Definition at line 2332 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)

Shifted mode HFCLK2 for CMU_HFPERCLKDIV

Definition at line 2329 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)

Shifted mode HFCLK256 for CMU_HFPERCLKDIV

Definition at line 2336 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)

Shifted mode HFCLK32 for CMU_HFPERCLKDIV

Definition at line 2333 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)

Shifted mode HFCLK4 for CMU_HFPERCLKDIV

Definition at line 2330 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)

Shifted mode HFCLK512 for CMU_HFPERCLKDIV

Definition at line 2337 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)

Shifted mode HFCLK64 for CMU_HFPERCLKDIV

Definition at line 2334 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8   (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)

Shifted mode HFCLK8 for CMU_HFPERCLKDIV

Definition at line 2331 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKEN   (0x1UL << 8)

HFPERCLK Enable

Definition at line 2338 of file efm32lg330f256.h.

#define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT   (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFPERCLKDIV

Definition at line 2342 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_ACMP0   (0x1UL << 9)

Analog Comparator 0 Clock Enable

Definition at line 2925 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_ACMP0_DEFAULT   (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2929 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_ACMP1   (0x1UL << 10)

Analog Comparator 1 Clock Enable

Definition at line 2930 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_ACMP1_DEFAULT   (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2934 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_ADC0   (0x1UL << 16)

Analog to Digital Converter 0 Clock Enable

Definition at line 2960 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_ADC0_DEFAULT   (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2964 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_DAC0   (0x1UL << 17)

Digital to Analog Converter 0 Clock Enable

Definition at line 2965 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_DAC0_DEFAULT   (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2969 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_GPIO   (0x1UL << 13)

General purpose Input/Output Clock Enable

Definition at line 2945 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_GPIO_DEFAULT   (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2949 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_I2C0   (0x1UL << 11)

I2C 0 Clock Enable

Definition at line 2935 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_I2C0_DEFAULT   (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2939 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_I2C1   (0x1UL << 12)

I2C 1 Clock Enable

Definition at line 2940 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_I2C1_DEFAULT   (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2944 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_PRS   (0x1UL << 15)

Peripheral Reflex System Clock Enable

Definition at line 2955 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_PRS_DEFAULT   (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2959 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER0   (0x1UL << 5)

Timer 0 Clock Enable

Definition at line 2905 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER0_DEFAULT   (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2909 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER1   (0x1UL << 6)

Timer 1 Clock Enable

Definition at line 2910 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER1_DEFAULT   (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2914 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER2   (0x1UL << 7)

Timer 2 Clock Enable

Definition at line 2915 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER2_DEFAULT   (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2919 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER3   (0x1UL << 8)

Timer 3 Clock Enable

Definition at line 2920 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_TIMER3_DEFAULT   (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2924 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_USART0   (0x1UL << 0)

Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable

Definition at line 2890 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_USART0_DEFAULT   (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2894 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_USART1   (0x1UL << 1)

Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable

Definition at line 2895 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_USART1_DEFAULT   (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2899 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_USART2   (0x1UL << 2)

Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable

Definition at line 2900 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_USART2_DEFAULT   (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2904 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_VCMP   (0x1UL << 14)

Voltage Comparator Clock Enable

Definition at line 2950 of file efm32lg330f256.h.

#define CMU_HFPERCLKEN0_VCMP_DEFAULT   (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)

Shifted mode DEFAULT for CMU_HFPERCLKEN0

Definition at line 2954 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_11MHZ   (_CMU_HFRCOCTRL_BAND_11MHZ << 8)

Shifted mode 11MHZ for CMU_HFRCOCTRL

Definition at line 2362 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_14MHZ   (_CMU_HFRCOCTRL_BAND_14MHZ << 8)

Shifted mode 14MHZ for CMU_HFRCOCTRL

Definition at line 2364 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_1MHZ   (_CMU_HFRCOCTRL_BAND_1MHZ << 8)

Shifted mode 1MHZ for CMU_HFRCOCTRL

Definition at line 2360 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_21MHZ   (_CMU_HFRCOCTRL_BAND_21MHZ << 8)

Shifted mode 21MHZ for CMU_HFRCOCTRL

Definition at line 2365 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_28MHZ   (_CMU_HFRCOCTRL_BAND_28MHZ << 8)

Shifted mode 28MHZ for CMU_HFRCOCTRL

Definition at line 2366 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_7MHZ   (_CMU_HFRCOCTRL_BAND_7MHZ << 8)

Shifted mode 7MHZ for CMU_HFRCOCTRL

Definition at line 2361 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_BAND_DEFAULT   (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)

Shifted mode DEFAULT for CMU_HFRCOCTRL

Definition at line 2363 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_SUDELAY_DEFAULT   (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)

Shifted mode DEFAULT for CMU_HFRCOCTRL

Definition at line 2370 of file efm32lg330f256.h.

#define CMU_HFRCOCTRL_TUNING_DEFAULT   (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)

Shifted mode DEFAULT for CMU_HFRCOCTRL

Definition at line 2350 of file efm32lg330f256.h.

#define CMU_IEN_AUXHFRCORDY   (0x1UL << 4)

AUXHFRCO Ready Interrupt Enable

Definition at line 2837 of file efm32lg330f256.h.

#define CMU_IEN_AUXHFRCORDY_DEFAULT   (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2841 of file efm32lg330f256.h.

#define CMU_IEN_CALOF   (0x1UL << 6)

Calibration Overflow Interrupt Enable

Definition at line 2847 of file efm32lg330f256.h.

#define CMU_IEN_CALOF_DEFAULT   (_CMU_IEN_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2851 of file efm32lg330f256.h.

#define CMU_IEN_CALRDY   (0x1UL << 5)

Calibration Ready Interrupt Enable

Definition at line 2842 of file efm32lg330f256.h.

#define CMU_IEN_CALRDY_DEFAULT   (_CMU_IEN_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2846 of file efm32lg330f256.h.

#define CMU_IEN_HFRCORDY   (0x1UL << 0)

HFRCO Ready Interrupt Enable

Definition at line 2817 of file efm32lg330f256.h.

#define CMU_IEN_HFRCORDY_DEFAULT   (_CMU_IEN_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2821 of file efm32lg330f256.h.

#define CMU_IEN_HFXORDY   (0x1UL << 1)

HFXO Ready Interrupt Enable

Definition at line 2822 of file efm32lg330f256.h.

#define CMU_IEN_HFXORDY_DEFAULT   (_CMU_IEN_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2826 of file efm32lg330f256.h.

#define CMU_IEN_LFRCORDY   (0x1UL << 2)

LFRCO Ready Interrupt Enable

Definition at line 2827 of file efm32lg330f256.h.

#define CMU_IEN_LFRCORDY_DEFAULT   (_CMU_IEN_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2831 of file efm32lg330f256.h.

#define CMU_IEN_LFXORDY   (0x1UL << 3)

LFXO Ready Interrupt Enable

Definition at line 2832 of file efm32lg330f256.h.

#define CMU_IEN_LFXORDY_DEFAULT   (_CMU_IEN_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2836 of file efm32lg330f256.h.

#define CMU_IEN_USBCHFCLKSEL   (0x1UL << 7)

USBC HFCLK Selected Interrupt Enable

Definition at line 2852 of file efm32lg330f256.h.

#define CMU_IEN_USBCHFCLKSEL_DEFAULT   (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7)

Shifted mode DEFAULT for CMU_IEN

Definition at line 2856 of file efm32lg330f256.h.

#define CMU_IF_AUXHFRCORDY   (0x1UL << 4)

AUXHFRCO Ready Interrupt Flag

Definition at line 2704 of file efm32lg330f256.h.

#define CMU_IF_AUXHFRCORDY_DEFAULT   (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IF

Definition at line 2708 of file efm32lg330f256.h.

#define CMU_IF_CALOF   (0x1UL << 6)

Calibration Overflow Interrupt Flag

Definition at line 2714 of file efm32lg330f256.h.

#define CMU_IF_CALOF_DEFAULT   (_CMU_IF_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IF

Definition at line 2718 of file efm32lg330f256.h.

#define CMU_IF_CALRDY   (0x1UL << 5)

Calibration Ready Interrupt Flag

Definition at line 2709 of file efm32lg330f256.h.

#define CMU_IF_CALRDY_DEFAULT   (_CMU_IF_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IF

Definition at line 2713 of file efm32lg330f256.h.

#define CMU_IF_HFRCORDY   (0x1UL << 0)

HFRCO Ready Interrupt Flag

Definition at line 2684 of file efm32lg330f256.h.

#define CMU_IF_HFRCORDY_DEFAULT   (_CMU_IF_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IF

Definition at line 2688 of file efm32lg330f256.h.

#define CMU_IF_HFXORDY   (0x1UL << 1)

HFXO Ready Interrupt Flag

Definition at line 2689 of file efm32lg330f256.h.

#define CMU_IF_HFXORDY_DEFAULT   (_CMU_IF_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IF

Definition at line 2693 of file efm32lg330f256.h.

#define CMU_IF_LFRCORDY   (0x1UL << 2)

LFRCO Ready Interrupt Flag

Definition at line 2694 of file efm32lg330f256.h.

#define CMU_IF_LFRCORDY_DEFAULT   (_CMU_IF_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IF

Definition at line 2698 of file efm32lg330f256.h.

#define CMU_IF_LFXORDY   (0x1UL << 3)

LFXO Ready Interrupt Flag

Definition at line 2699 of file efm32lg330f256.h.

#define CMU_IF_LFXORDY_DEFAULT   (_CMU_IF_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IF

Definition at line 2703 of file efm32lg330f256.h.

#define CMU_IF_USBCHFCLKSEL   (0x1UL << 7)

USBC HFCLK Selected Interrupt Flag

Definition at line 2719 of file efm32lg330f256.h.

#define CMU_IF_USBCHFCLKSEL_DEFAULT   (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7)

Shifted mode DEFAULT for CMU_IF

Definition at line 2723 of file efm32lg330f256.h.

#define CMU_IFC_AUXHFRCORDY   (0x1UL << 4)

AUXHFRCO Ready Interrupt Flag Clear

Definition at line 2793 of file efm32lg330f256.h.

#define CMU_IFC_AUXHFRCORDY_DEFAULT   (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2797 of file efm32lg330f256.h.

#define CMU_IFC_CALOF   (0x1UL << 6)

Calibration Overflow Interrupt Flag Clear

Definition at line 2803 of file efm32lg330f256.h.

#define CMU_IFC_CALOF_DEFAULT   (_CMU_IFC_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2807 of file efm32lg330f256.h.

#define CMU_IFC_CALRDY   (0x1UL << 5)

Calibration Ready Interrupt Flag Clear

Definition at line 2798 of file efm32lg330f256.h.

#define CMU_IFC_CALRDY_DEFAULT   (_CMU_IFC_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2802 of file efm32lg330f256.h.

#define CMU_IFC_HFRCORDY   (0x1UL << 0)

HFRCO Ready Interrupt Flag Clear

Definition at line 2773 of file efm32lg330f256.h.

#define CMU_IFC_HFRCORDY_DEFAULT   (_CMU_IFC_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2777 of file efm32lg330f256.h.

#define CMU_IFC_HFXORDY   (0x1UL << 1)

HFXO Ready Interrupt Flag Clear

Definition at line 2778 of file efm32lg330f256.h.

#define CMU_IFC_HFXORDY_DEFAULT   (_CMU_IFC_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2782 of file efm32lg330f256.h.

#define CMU_IFC_LFRCORDY   (0x1UL << 2)

LFRCO Ready Interrupt Flag Clear

Definition at line 2783 of file efm32lg330f256.h.

#define CMU_IFC_LFRCORDY_DEFAULT   (_CMU_IFC_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2787 of file efm32lg330f256.h.

#define CMU_IFC_LFXORDY   (0x1UL << 3)

LFXO Ready Interrupt Flag Clear

Definition at line 2788 of file efm32lg330f256.h.

#define CMU_IFC_LFXORDY_DEFAULT   (_CMU_IFC_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2792 of file efm32lg330f256.h.

#define CMU_IFC_USBCHFCLKSEL   (0x1UL << 7)

USBC HFCLK Selected Interrupt Flag Clear

Definition at line 2808 of file efm32lg330f256.h.

#define CMU_IFC_USBCHFCLKSEL_DEFAULT   (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7)

Shifted mode DEFAULT for CMU_IFC

Definition at line 2812 of file efm32lg330f256.h.

#define CMU_IFS_AUXHFRCORDY   (0x1UL << 4)

AUXHFRCO Ready Interrupt Flag Set

Definition at line 2749 of file efm32lg330f256.h.

#define CMU_IFS_AUXHFRCORDY_DEFAULT   (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2753 of file efm32lg330f256.h.

#define CMU_IFS_CALOF   (0x1UL << 6)

Calibration Overflow Interrupt Flag Set

Definition at line 2759 of file efm32lg330f256.h.

#define CMU_IFS_CALOF_DEFAULT   (_CMU_IFS_CALOF_DEFAULT << 6)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2763 of file efm32lg330f256.h.

#define CMU_IFS_CALRDY   (0x1UL << 5)

Calibration Ready Interrupt Flag Set

Definition at line 2754 of file efm32lg330f256.h.

#define CMU_IFS_CALRDY_DEFAULT   (_CMU_IFS_CALRDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2758 of file efm32lg330f256.h.

#define CMU_IFS_HFRCORDY   (0x1UL << 0)

HFRCO Ready Interrupt Flag Set

Definition at line 2728 of file efm32lg330f256.h.

#define CMU_IFS_HFRCORDY_DEFAULT   (_CMU_IFS_HFRCORDY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2732 of file efm32lg330f256.h.

#define CMU_IFS_HFXORDY   (0x1UL << 1)

HFXO Ready Interrupt Flag Set

Definition at line 2733 of file efm32lg330f256.h.

#define CMU_IFS_HFXORDY_DEFAULT   (_CMU_IFS_HFXORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2738 of file efm32lg330f256.h.

#define CMU_IFS_LFRCORDY   (0x1UL << 2)

LFRCO Ready Interrupt Flag Set

Definition at line 2739 of file efm32lg330f256.h.

#define CMU_IFS_LFRCORDY_DEFAULT   (_CMU_IFS_LFRCORDY_DEFAULT << 2)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2743 of file efm32lg330f256.h.

#define CMU_IFS_LFXORDY   (0x1UL << 3)

LFXO Ready Interrupt Flag Set

Definition at line 2744 of file efm32lg330f256.h.

#define CMU_IFS_LFXORDY_DEFAULT   (_CMU_IFS_LFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2748 of file efm32lg330f256.h.

#define CMU_IFS_USBCHFCLKSEL   (0x1UL << 7)

USBC HFCLK Selected Interrupt Flag Set

Definition at line 2764 of file efm32lg330f256.h.

#define CMU_IFS_USBCHFCLKSEL_DEFAULT   (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7)

Shifted mode DEFAULT for CMU_IFS

Definition at line 2768 of file efm32lg330f256.h.

#define CMU_LFACLKEN0_LESENSE   (0x1UL << 0)

Low Energy Sensor Interface Clock Enable

Definition at line 3011 of file efm32lg330f256.h.

#define CMU_LFACLKEN0_LESENSE_DEFAULT   (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFACLKEN0

Definition at line 3015 of file efm32lg330f256.h.

#define CMU_LFACLKEN0_LETIMER0   (0x1UL << 2)

Low Energy Timer 0 Clock Enable

Definition at line 3021 of file efm32lg330f256.h.

#define CMU_LFACLKEN0_LETIMER0_DEFAULT   (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)

Shifted mode DEFAULT for CMU_LFACLKEN0

Definition at line 3025 of file efm32lg330f256.h.

#define CMU_LFACLKEN0_RTC   (0x1UL << 1)

Real-Time Counter Clock Enable

Definition at line 3016 of file efm32lg330f256.h.

#define CMU_LFACLKEN0_RTC_DEFAULT   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)

Shifted mode DEFAULT for CMU_LFACLKEN0

Definition at line 3020 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LESENSE_DIV1   (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)

Shifted mode DIV1 for CMU_LFAPRESC0

Definition at line 3050 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LESENSE_DIV2   (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)

Shifted mode DIV2 for CMU_LFAPRESC0

Definition at line 3051 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LESENSE_DIV4   (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)

Shifted mode DIV4 for CMU_LFAPRESC0

Definition at line 3052 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LESENSE_DIV8   (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)

Shifted mode DIV8 for CMU_LFAPRESC0

Definition at line 3053 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV1   (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)

Shifted mode DIV1 for CMU_LFAPRESC0

Definition at line 3106 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV1024   (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)

Shifted mode DIV1024 for CMU_LFAPRESC0

Definition at line 3116 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV128   (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)

Shifted mode DIV128 for CMU_LFAPRESC0

Definition at line 3113 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV16   (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)

Shifted mode DIV16 for CMU_LFAPRESC0

Definition at line 3110 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV16384   (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)

Shifted mode DIV16384 for CMU_LFAPRESC0

Definition at line 3120 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV2   (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)

Shifted mode DIV2 for CMU_LFAPRESC0

Definition at line 3107 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV2048   (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)

Shifted mode DIV2048 for CMU_LFAPRESC0

Definition at line 3117 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV256   (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)

Shifted mode DIV256 for CMU_LFAPRESC0

Definition at line 3114 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV32   (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)

Shifted mode DIV32 for CMU_LFAPRESC0

Definition at line 3111 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV32768   (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)

Shifted mode DIV32768 for CMU_LFAPRESC0

Definition at line 3121 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV4   (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)

Shifted mode DIV4 for CMU_LFAPRESC0

Definition at line 3108 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV4096   (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)

Shifted mode DIV4096 for CMU_LFAPRESC0

Definition at line 3118 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV512   (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)

Shifted mode DIV512 for CMU_LFAPRESC0

Definition at line 3115 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV64   (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)

Shifted mode DIV64 for CMU_LFAPRESC0

Definition at line 3112 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV8   (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)

Shifted mode DIV8 for CMU_LFAPRESC0

Definition at line 3109 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_LETIMER0_DIV8192   (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)

Shifted mode DIV8192 for CMU_LFAPRESC0

Definition at line 3119 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV1   (_CMU_LFAPRESC0_RTC_DIV1 << 4)

Shifted mode DIV1 for CMU_LFAPRESC0

Definition at line 3072 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV1024   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)

Shifted mode DIV1024 for CMU_LFAPRESC0

Definition at line 3082 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV128   (_CMU_LFAPRESC0_RTC_DIV128 << 4)

Shifted mode DIV128 for CMU_LFAPRESC0

Definition at line 3079 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV16   (_CMU_LFAPRESC0_RTC_DIV16 << 4)

Shifted mode DIV16 for CMU_LFAPRESC0

Definition at line 3076 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV16384   (_CMU_LFAPRESC0_RTC_DIV16384 << 4)

Shifted mode DIV16384 for CMU_LFAPRESC0

Definition at line 3086 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV2   (_CMU_LFAPRESC0_RTC_DIV2 << 4)

Shifted mode DIV2 for CMU_LFAPRESC0

Definition at line 3073 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV2048   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)

Shifted mode DIV2048 for CMU_LFAPRESC0

Definition at line 3083 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV256   (_CMU_LFAPRESC0_RTC_DIV256 << 4)

Shifted mode DIV256 for CMU_LFAPRESC0

Definition at line 3080 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV32   (_CMU_LFAPRESC0_RTC_DIV32 << 4)

Shifted mode DIV32 for CMU_LFAPRESC0

Definition at line 3077 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV32768   (_CMU_LFAPRESC0_RTC_DIV32768 << 4)

Shifted mode DIV32768 for CMU_LFAPRESC0

Definition at line 3087 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV4   (_CMU_LFAPRESC0_RTC_DIV4 << 4)

Shifted mode DIV4 for CMU_LFAPRESC0

Definition at line 3074 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV4096   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)

Shifted mode DIV4096 for CMU_LFAPRESC0

Definition at line 3084 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV512   (_CMU_LFAPRESC0_RTC_DIV512 << 4)

Shifted mode DIV512 for CMU_LFAPRESC0

Definition at line 3081 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV64   (_CMU_LFAPRESC0_RTC_DIV64 << 4)

Shifted mode DIV64 for CMU_LFAPRESC0

Definition at line 3078 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV8   (_CMU_LFAPRESC0_RTC_DIV8 << 4)

Shifted mode DIV8 for CMU_LFAPRESC0

Definition at line 3075 of file efm32lg330f256.h.

#define CMU_LFAPRESC0_RTC_DIV8192   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)

Shifted mode DIV8192 for CMU_LFAPRESC0

Definition at line 3085 of file efm32lg330f256.h.

#define CMU_LFBCLKEN0_LEUART0   (0x1UL << 0)

Low Energy UART 0 Clock Enable

Definition at line 3030 of file efm32lg330f256.h.

#define CMU_LFBCLKEN0_LEUART0_DEFAULT   (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFBCLKEN0

Definition at line 3034 of file efm32lg330f256.h.

#define CMU_LFBCLKEN0_LEUART1   (0x1UL << 1)

Low Energy UART 1 Clock Enable

Definition at line 3035 of file efm32lg330f256.h.

#define CMU_LFBCLKEN0_LEUART1_DEFAULT   (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)

Shifted mode DEFAULT for CMU_LFBCLKEN0

Definition at line 3039 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART0_DIV1   (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)

Shifted mode DIV1 for CMU_LFBPRESC0

Definition at line 3132 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART0_DIV2   (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)

Shifted mode DIV2 for CMU_LFBPRESC0

Definition at line 3133 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART0_DIV4   (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)

Shifted mode DIV4 for CMU_LFBPRESC0

Definition at line 3134 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART0_DIV8   (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)

Shifted mode DIV8 for CMU_LFBPRESC0

Definition at line 3135 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART1_DIV1   (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)

Shifted mode DIV1 for CMU_LFBPRESC0

Definition at line 3142 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART1_DIV2   (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)

Shifted mode DIV2 for CMU_LFBPRESC0

Definition at line 3143 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART1_DIV4   (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)

Shifted mode DIV4 for CMU_LFBPRESC0

Definition at line 3144 of file efm32lg330f256.h.

#define CMU_LFBPRESC0_LEUART1_DIV8   (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)

Shifted mode DIV8 for CMU_LFBPRESC0

Definition at line 3145 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFA_DEFAULT   (_CMU_LFCLKSEL_LFA_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 2552 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFA_DISABLED   (_CMU_LFCLKSEL_LFA_DISABLED << 0)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 2551 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2   (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)

Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 2555 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFA_LFRCO   (_CMU_LFCLKSEL_LFA_LFRCO << 0)

Shifted mode LFRCO for CMU_LFCLKSEL

Definition at line 2553 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFA_LFXO   (_CMU_LFCLKSEL_LFA_LFXO << 0)

Shifted mode LFXO for CMU_LFCLKSEL

Definition at line 2554 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFAE   (0x1UL << 16)

Clock Select for LFA Extended

Definition at line 2568 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFAE_DEFAULT   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 2574 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFAE_DISABLED   (_CMU_LFCLKSEL_LFAE_DISABLED << 16)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 2575 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFAE_ULFRCO   (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)

Shifted mode ULFRCO for CMU_LFCLKSEL

Definition at line 2576 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFB_DEFAULT   (_CMU_LFCLKSEL_LFB_DEFAULT << 2)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 2564 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFB_DISABLED   (_CMU_LFCLKSEL_LFB_DISABLED << 2)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 2563 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2   (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)

Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL

Definition at line 2567 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFB_LFRCO   (_CMU_LFCLKSEL_LFB_LFRCO << 2)

Shifted mode LFRCO for CMU_LFCLKSEL

Definition at line 2565 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFB_LFXO   (_CMU_LFCLKSEL_LFB_LFXO << 2)

Shifted mode LFXO for CMU_LFCLKSEL

Definition at line 2566 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFBE   (0x1UL << 20)

Clock Select for LFB Extended

Definition at line 2577 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFBE_DEFAULT   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)

Shifted mode DEFAULT for CMU_LFCLKSEL

Definition at line 2583 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFBE_DISABLED   (_CMU_LFCLKSEL_LFBE_DISABLED << 20)

Shifted mode DISABLED for CMU_LFCLKSEL

Definition at line 2584 of file efm32lg330f256.h.

#define CMU_LFCLKSEL_LFBE_ULFRCO   (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)

Shifted mode ULFRCO for CMU_LFCLKSEL

Definition at line 2585 of file efm32lg330f256.h.

#define CMU_LFRCOCTRL_TUNING_DEFAULT   (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LFRCOCTRL

Definition at line 2378 of file efm32lg330f256.h.

#define CMU_LOCK_LOCKKEY_DEFAULT   (_CMU_LOCK_LOCKKEY_DEFAULT << 0)

Shifted mode DEFAULT for CMU_LOCK

Definition at line 3227 of file efm32lg330f256.h.

#define CMU_LOCK_LOCKKEY_LOCK   (_CMU_LOCK_LOCKKEY_LOCK << 0)

Shifted mode LOCK for CMU_LOCK

Definition at line 3228 of file efm32lg330f256.h.

#define CMU_LOCK_LOCKKEY_LOCKED   (_CMU_LOCK_LOCKKEY_LOCKED << 0)

Shifted mode LOCKED for CMU_LOCK

Definition at line 3230 of file efm32lg330f256.h.

#define CMU_LOCK_LOCKKEY_UNLOCK   (_CMU_LOCK_LOCKKEY_UNLOCK << 0)

Shifted mode UNLOCK for CMU_LOCK

Definition at line 3231 of file efm32lg330f256.h.

#define CMU_LOCK_LOCKKEY_UNLOCKED   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)

Shifted mode UNLOCKED for CMU_LOCK

Definition at line 3229 of file efm32lg330f256.h.

#define CMU_OSCENCMD_AUXHFRCODIS   (0x1UL << 5)

AUXHFRCO Disable

Definition at line 2479 of file efm32lg330f256.h.

#define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT   (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2483 of file efm32lg330f256.h.

#define CMU_OSCENCMD_AUXHFRCOEN   (0x1UL << 4)

AUXHFRCO Enable

Definition at line 2474 of file efm32lg330f256.h.

#define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT   (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2478 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFRCODIS   (0x1UL << 1)

HFRCO Disable

Definition at line 2459 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFRCODIS_DEFAULT   (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2463 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFRCOEN   (0x1UL << 0)

HFRCO Enable

Definition at line 2454 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFRCOEN_DEFAULT   (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2458 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFXODIS   (0x1UL << 3)

HFXO Disable

Definition at line 2469 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFXODIS_DEFAULT   (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2473 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFXOEN   (0x1UL << 2)

HFXO Enable

Definition at line 2464 of file efm32lg330f256.h.

#define CMU_OSCENCMD_HFXOEN_DEFAULT   (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2468 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFRCODIS   (0x1UL << 7)

LFRCO Disable

Definition at line 2489 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFRCODIS_DEFAULT   (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2493 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFRCOEN   (0x1UL << 6)

LFRCO Enable

Definition at line 2484 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFRCOEN_DEFAULT   (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2488 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFXODIS   (0x1UL << 9)

LFXO Disable

Definition at line 2499 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFXODIS_DEFAULT   (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2503 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFXOEN   (0x1UL << 8)

LFXO Enable

Definition at line 2494 of file efm32lg330f256.h.

#define CMU_OSCENCMD_LFXOEN_DEFAULT   (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)

Shifted mode DEFAULT for CMU_OSCENCMD

Definition at line 2498 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT0CLKEN   (0x1UL << 0)

PCNT0 Clock Enable

Definition at line 3150 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 3154 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL   (0x1UL << 1)

PCNT0 Clock Select

Definition at line 3155 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 3161 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)

Shifted mode LFACLK for CMU_PCNTCTRL

Definition at line 3162 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0   (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)

Shifted mode PCNT0S0 for CMU_PCNTCTRL

Definition at line 3163 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT1CLKEN   (0x1UL << 2)

PCNT1 Clock Enable

Definition at line 3164 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 3168 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT1CLKSEL   (0x1UL << 3)

PCNT1 Clock Select

Definition at line 3169 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 3175 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)

Shifted mode LFACLK for CMU_PCNTCTRL

Definition at line 3176 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0   (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)

Shifted mode PCNT1S0 for CMU_PCNTCTRL

Definition at line 3177 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT2CLKEN   (0x1UL << 4)

PCNT2 Clock Enable

Definition at line 3178 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT   (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 3182 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT2CLKSEL   (0x1UL << 5)

PCNT2 Clock Select

Definition at line 3183 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT   (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)

Shifted mode DEFAULT for CMU_PCNTCTRL

Definition at line 3189 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK   (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)

Shifted mode LFACLK for CMU_PCNTCTRL

Definition at line 3190 of file efm32lg330f256.h.

#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0   (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)

Shifted mode PCNT2S0 for CMU_PCNTCTRL

Definition at line 3191 of file efm32lg330f256.h.

#define CMU_ROUTE_CLKOUT0PEN   (0x1UL << 0)

CLKOUT0 Pin Enable

Definition at line 3196 of file efm32lg330f256.h.

#define CMU_ROUTE_CLKOUT0PEN_DEFAULT   (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)

Shifted mode DEFAULT for CMU_ROUTE

Definition at line 3200 of file efm32lg330f256.h.

#define CMU_ROUTE_CLKOUT1PEN   (0x1UL << 1)

CLKOUT1 Pin Enable

Definition at line 3201 of file efm32lg330f256.h.

#define CMU_ROUTE_CLKOUT1PEN_DEFAULT   (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)

Shifted mode DEFAULT for CMU_ROUTE

Definition at line 3205 of file efm32lg330f256.h.

#define CMU_ROUTE_LOCATION_DEFAULT   (_CMU_ROUTE_LOCATION_DEFAULT << 2)

Shifted mode DEFAULT for CMU_ROUTE

Definition at line 3213 of file efm32lg330f256.h.

#define CMU_ROUTE_LOCATION_LOC0   (_CMU_ROUTE_LOCATION_LOC0 << 2)

Shifted mode LOC0 for CMU_ROUTE

Definition at line 3212 of file efm32lg330f256.h.

#define CMU_ROUTE_LOCATION_LOC1   (_CMU_ROUTE_LOCATION_LOC1 << 2)

Shifted mode LOC1 for CMU_ROUTE

Definition at line 3214 of file efm32lg330f256.h.

#define CMU_ROUTE_LOCATION_LOC2   (_CMU_ROUTE_LOCATION_LOC2 << 2)

Shifted mode LOC2 for CMU_ROUTE

Definition at line 3215 of file efm32lg330f256.h.

#define CMU_STATUS_AUXHFRCOENS   (0x1UL << 4)

AUXHFRCO Enable Status

Definition at line 2610 of file efm32lg330f256.h.

#define CMU_STATUS_AUXHFRCOENS_DEFAULT   (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2614 of file efm32lg330f256.h.

#define CMU_STATUS_AUXHFRCORDY   (0x1UL << 5)

AUXHFRCO Ready

Definition at line 2615 of file efm32lg330f256.h.

#define CMU_STATUS_AUXHFRCORDY_DEFAULT   (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2619 of file efm32lg330f256.h.

#define CMU_STATUS_CALBSY   (0x1UL << 14)

Calibration Busy

Definition at line 2660 of file efm32lg330f256.h.

#define CMU_STATUS_CALBSY_DEFAULT   (_CMU_STATUS_CALBSY_DEFAULT << 14)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2664 of file efm32lg330f256.h.

#define CMU_STATUS_HFRCOENS   (0x1UL << 0)

HFRCO Enable Status

Definition at line 2590 of file efm32lg330f256.h.

#define CMU_STATUS_HFRCOENS_DEFAULT   (_CMU_STATUS_HFRCOENS_DEFAULT << 0)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2594 of file efm32lg330f256.h.

#define CMU_STATUS_HFRCORDY   (0x1UL << 1)

HFRCO Ready

Definition at line 2595 of file efm32lg330f256.h.

#define CMU_STATUS_HFRCORDY_DEFAULT   (_CMU_STATUS_HFRCORDY_DEFAULT << 1)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2599 of file efm32lg330f256.h.

#define CMU_STATUS_HFRCOSEL   (0x1UL << 10)

HFRCO Selected

Definition at line 2640 of file efm32lg330f256.h.

#define CMU_STATUS_HFRCOSEL_DEFAULT   (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2644 of file efm32lg330f256.h.

#define CMU_STATUS_HFXOENS   (0x1UL << 2)

HFXO Enable Status

Definition at line 2600 of file efm32lg330f256.h.

#define CMU_STATUS_HFXOENS_DEFAULT   (_CMU_STATUS_HFXOENS_DEFAULT << 2)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2604 of file efm32lg330f256.h.

#define CMU_STATUS_HFXORDY   (0x1UL << 3)

HFXO Ready

Definition at line 2605 of file efm32lg330f256.h.

#define CMU_STATUS_HFXORDY_DEFAULT   (_CMU_STATUS_HFXORDY_DEFAULT << 3)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2609 of file efm32lg330f256.h.

#define CMU_STATUS_HFXOSEL   (0x1UL << 11)

HFXO Selected

Definition at line 2645 of file efm32lg330f256.h.

#define CMU_STATUS_HFXOSEL_DEFAULT   (_CMU_STATUS_HFXOSEL_DEFAULT << 11)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2649 of file efm32lg330f256.h.

#define CMU_STATUS_LFRCOENS   (0x1UL << 6)

LFRCO Enable Status

Definition at line 2620 of file efm32lg330f256.h.

#define CMU_STATUS_LFRCOENS_DEFAULT   (_CMU_STATUS_LFRCOENS_DEFAULT << 6)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2624 of file efm32lg330f256.h.

#define CMU_STATUS_LFRCORDY   (0x1UL << 7)

LFRCO Ready

Definition at line 2625 of file efm32lg330f256.h.

#define CMU_STATUS_LFRCORDY_DEFAULT   (_CMU_STATUS_LFRCORDY_DEFAULT << 7)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2629 of file efm32lg330f256.h.

#define CMU_STATUS_LFRCOSEL   (0x1UL << 12)

LFRCO Selected

Definition at line 2650 of file efm32lg330f256.h.

#define CMU_STATUS_LFRCOSEL_DEFAULT   (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2654 of file efm32lg330f256.h.

#define CMU_STATUS_LFXOENS   (0x1UL << 8)

LFXO Enable Status

Definition at line 2630 of file efm32lg330f256.h.

#define CMU_STATUS_LFXOENS_DEFAULT   (_CMU_STATUS_LFXOENS_DEFAULT << 8)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2634 of file efm32lg330f256.h.

#define CMU_STATUS_LFXORDY   (0x1UL << 9)

LFXO Ready

Definition at line 2635 of file efm32lg330f256.h.

#define CMU_STATUS_LFXORDY_DEFAULT   (_CMU_STATUS_LFXORDY_DEFAULT << 9)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2639 of file efm32lg330f256.h.

#define CMU_STATUS_LFXOSEL   (0x1UL << 13)

LFXO Selected

Definition at line 2655 of file efm32lg330f256.h.

#define CMU_STATUS_LFXOSEL_DEFAULT   (_CMU_STATUS_LFXOSEL_DEFAULT << 13)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2659 of file efm32lg330f256.h.

#define CMU_STATUS_USBCHFCLKSEL   (0x1UL << 15)

USBC HFCLK Selected

Definition at line 2665 of file efm32lg330f256.h.

#define CMU_STATUS_USBCHFCLKSEL_DEFAULT   (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2669 of file efm32lg330f256.h.

#define CMU_STATUS_USBCLFRCOSEL   (0x1UL << 17)

USBC LFRCO Selected

Definition at line 2675 of file efm32lg330f256.h.

#define CMU_STATUS_USBCLFRCOSEL_DEFAULT   (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2679 of file efm32lg330f256.h.

#define CMU_STATUS_USBCLFXOSEL   (0x1UL << 16)

USBC LFXO Selected

Definition at line 2670 of file efm32lg330f256.h.

#define CMU_STATUS_USBCLFXOSEL_DEFAULT   (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)

Shifted mode DEFAULT for CMU_STATUS

Definition at line 2674 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFACLKEN0   (0x1UL << 0)

Low Frequency A Clock Enable 0 Busy

Definition at line 2974 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFACLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 2978 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFAPRESC0   (0x1UL << 2)

Low Frequency A Prescaler 0 Busy

Definition at line 2979 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFAPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 2983 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFBCLKEN0   (0x1UL << 4)

Low Frequency B Clock Enable 0 Busy

Definition at line 2984 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT   (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 2988 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFBPRESC0   (0x1UL << 6)

Low Frequency B Prescaler 0 Busy

Definition at line 2989 of file efm32lg330f256.h.

#define CMU_SYNCBUSY_LFBPRESC0_DEFAULT   (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)

Shifted mode DEFAULT for CMU_SYNCBUSY

Definition at line 2993 of file efm32lg330f256.h.