EFM32GG940F1024
[Parts]


Modules

 EFM32GG940F1024 Core
 Processor and Core Peripheral Section.
 EFM32GG940F1024 Part
 EFM32GG940F1024 Peripheral TypeDefs
 Device Specific Peripheral Register Structures.
 EFM32GG940F1024 Peripheral Memory Map
 EFM32GG940F1024 Peripheral Declarations
 EFM32GG940F1024 Bit Fields
 EFM32GG940F1024 Alternate Function

Defines

#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
 Set the value of a bit field within a register.

Typedefs

typedef enum IRQn IRQn_Type

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11,
  UsageFault_IRQn = -10,
  SVCall_IRQn = -5,
  DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  DMA_IRQn = 0,
  GPIO_EVEN_IRQn = 1,
  TIMER0_IRQn = 2,
  USART0_RX_IRQn = 3,
  USART0_TX_IRQn = 4,
  USB_IRQn = 5,
  ACMP0_IRQn = 6,
  ADC0_IRQn = 7,
  DAC0_IRQn = 8,
  I2C0_IRQn = 9,
  I2C1_IRQn = 10,
  GPIO_ODD_IRQn = 11,
  TIMER1_IRQn = 12,
  TIMER2_IRQn = 13,
  TIMER3_IRQn = 14,
  USART1_RX_IRQn = 15,
  USART1_TX_IRQn = 16,
  LESENSE_IRQn = 17,
  USART2_RX_IRQn = 18,
  USART2_TX_IRQn = 19,
  LEUART0_IRQn = 24,
  LEUART1_IRQn = 25,
  LETIMER0_IRQn = 26,
  PCNT0_IRQn = 27,
  PCNT1_IRQn = 28,
  PCNT2_IRQn = 29,
  RTC_IRQn = 30,
  BURTC_IRQn = 31,
  CMU_IRQn = 32,
  VCMP_IRQn = 33,
  LCD_IRQn = 34,
  MSC_IRQn = 35,
  AES_IRQn = 36,
  EMU_IRQn = 38
}

Define Documentation

#define SET_BIT_FIELD ( REG,
MASK,
VALUE,
OFFSET   )     REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters:
REG The register to update
MASK The mask for the bit field to update
VALUE The value to write to the bit field
OFFSET The number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 3721 of file efm32gg940f1024.h.


Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition


Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator:
NonMaskableInt_IRQn  2 Non Maskable Interrupt
HardFault_IRQn  3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn  4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn  5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn  6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn  11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn  12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn  14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn  15 Cortex-M3 System Tick Interrupt
DMA_IRQn  16+0 EFM32 DMA Interrupt
GPIO_EVEN_IRQn  16+1 EFM32 GPIO_EVEN Interrupt
TIMER0_IRQn  16+2 EFM32 TIMER0 Interrupt
USART0_RX_IRQn  16+3 EFM32 USART0_RX Interrupt
USART0_TX_IRQn  16+4 EFM32 USART0_TX Interrupt
USB_IRQn  16+5 EFM32 USB Interrupt
ACMP0_IRQn  16+6 EFM32 ACMP0 Interrupt
ADC0_IRQn  16+7 EFM32 ADC0 Interrupt
DAC0_IRQn  16+8 EFM32 DAC0 Interrupt
I2C0_IRQn  16+9 EFM32 I2C0 Interrupt
I2C1_IRQn  16+10 EFM32 I2C1 Interrupt
GPIO_ODD_IRQn  16+11 EFM32 GPIO_ODD Interrupt
TIMER1_IRQn  16+12 EFM32 TIMER1 Interrupt
TIMER2_IRQn  16+13 EFM32 TIMER2 Interrupt
TIMER3_IRQn  16+14 EFM32 TIMER3 Interrupt
USART1_RX_IRQn  16+15 EFM32 USART1_RX Interrupt
USART1_TX_IRQn  16+16 EFM32 USART1_TX Interrupt
LESENSE_IRQn  16+17 EFM32 LESENSE Interrupt
USART2_RX_IRQn  16+18 EFM32 USART2_RX Interrupt
USART2_TX_IRQn  16+19 EFM32 USART2_TX Interrupt
LEUART0_IRQn  16+24 EFM32 LEUART0 Interrupt
LEUART1_IRQn  16+25 EFM32 LEUART1 Interrupt
LETIMER0_IRQn  16+26 EFM32 LETIMER0 Interrupt
PCNT0_IRQn  16+27 EFM32 PCNT0 Interrupt
PCNT1_IRQn  16+28 EFM32 PCNT1 Interrupt
PCNT2_IRQn  16+29 EFM32 PCNT2 Interrupt
RTC_IRQn  16+30 EFM32 RTC Interrupt
BURTC_IRQn  16+31 EFM32 BURTC Interrupt
CMU_IRQn  16+32 EFM32 CMU Interrupt
VCMP_IRQn  16+33 EFM32 VCMP Interrupt
LCD_IRQn  16+34 EFM32 LCD Interrupt
MSC_IRQn  16+35 EFM32 MSC Interrupt
AES_IRQn  16+36 EFM32 AES Interrupt
EMU_IRQn  16+38 EFM32 EMU Interrupt

Definition at line 52 of file efm32gg940f1024.h.