release/EM_CMSIS_3.20.6/Device/SiliconLabs/EFM32GG/Include/efm32gg230f1024.h

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00001 /**************************************************************************/
00034 #ifndef __EFM32GG230F1024_H
00035 #define __EFM32GG230F1024_H
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M3 Processor Exceptions Numbers *******************************************/
00055   NonMaskableInt_IRQn   = -14,              
00056   HardFault_IRQn        = -13,              
00057   MemoryManagement_IRQn = -12,              
00058   BusFault_IRQn         = -11,              
00059   UsageFault_IRQn       = -10,              
00060   SVCall_IRQn           = -5,               
00061   DebugMonitor_IRQn     = -4,               
00062   PendSV_IRQn           = -2,               
00063   SysTick_IRQn          = -1,               
00065 /******  EFM32G Peripheral Interrupt Numbers **********************************************/
00066   DMA_IRQn              = 0,  
00067   GPIO_EVEN_IRQn        = 1,  
00068   TIMER0_IRQn           = 2,  
00069   USART0_RX_IRQn        = 3,  
00070   USART0_TX_IRQn        = 4,  
00071   ACMP0_IRQn            = 6,  
00072   ADC0_IRQn             = 7,  
00073   DAC0_IRQn             = 8,  
00074   I2C0_IRQn             = 9,  
00075   I2C1_IRQn             = 10, 
00076   GPIO_ODD_IRQn         = 11, 
00077   TIMER1_IRQn           = 12, 
00078   TIMER2_IRQn           = 13, 
00079   TIMER3_IRQn           = 14, 
00080   USART1_RX_IRQn        = 15, 
00081   USART1_TX_IRQn        = 16, 
00082   LESENSE_IRQn          = 17, 
00083   USART2_RX_IRQn        = 18, 
00084   USART2_TX_IRQn        = 19, 
00085   LEUART0_IRQn          = 24, 
00086   LEUART1_IRQn          = 25, 
00087   LETIMER0_IRQn         = 26, 
00088   PCNT0_IRQn            = 27, 
00089   PCNT1_IRQn            = 28, 
00090   PCNT2_IRQn            = 29, 
00091   RTC_IRQn              = 30, 
00092   BURTC_IRQn            = 31, 
00093   CMU_IRQn              = 32, 
00094   VCMP_IRQn             = 33, 
00095   MSC_IRQn              = 35, 
00096   AES_IRQn              = 36, 
00097   EMU_IRQn              = 38, 
00098 } IRQn_Type;
00099 
00100 /**************************************************************************/
00105 #define __MPU_PRESENT             1 
00106 #define __NVIC_PRIO_BITS          3 
00107 #define __Vendor_SysTickConfig    0 
00111 /**************************************************************************/
00117 #define _EFM32_GIANT_FAMILY    1 
00118 #define _EFM_DEVICE              
00120 /* If part number is not defined as compiler option, define it */
00121 #if !defined(EFM32GG230F1024)
00122 #define EFM32GG230F1024    1 
00123 #endif
00124 
00126 #define PART_NUMBER          "EFM32GG230F1024" 
00129 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00130 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00131 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00132 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00133 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00134 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00135 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00136 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00137 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL) 
00138 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)    
00139 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL) 
00140 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)       
00141 #define EBI_CODE_MEM_BASE    ((uint32_t) 0x12000000UL) 
00142 #define EBI_CODE_MEM_SIZE    ((uint32_t) 0xE000000UL)  
00143 #define EBI_CODE_MEM_END     ((uint32_t) 0x1FFFFFFFUL) 
00144 #define EBI_CODE_MEM_BITS    ((uint32_t) 0x28UL)       
00145 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00146 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00147 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00148 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00149 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00150 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00151 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00152 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00153 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00154 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00155 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00156 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00157 #define EBI_MEM_BASE         ((uint32_t) 0x80000000UL) 
00158 #define EBI_MEM_SIZE         ((uint32_t) 0x40000000UL) 
00159 #define EBI_MEM_END          ((uint32_t) 0xBFFFFFFFUL) 
00160 #define EBI_MEM_BITS         ((uint32_t) 0x30UL)       
00163 #define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL) 
00164 #define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL) 
00167 #define FLASH_BASE           (0x00000000UL) 
00168 #define FLASH_SIZE           (0x00100000UL) 
00169 #define FLASH_PAGE_SIZE      4096           
00170 #define SRAM_BASE            (0x20000000UL) 
00171 #define SRAM_SIZE            (0x00020000UL) 
00172 #define __CM3_REV            0x201          
00173 #define PRS_CHAN_COUNT       12             
00174 #define DMA_CHAN_COUNT       12             
00177 #define AFCHAN_MAX           163
00178 #define AFCHANLOC_MAX        7
00179 
00180 #define AFACHAN_MAX          53
00181 
00182 /* Part number capabilities */
00183 
00184 #define LETIMER_PRESENT       
00185 #define LETIMER_COUNT       1 
00186 #define USART_PRESENT         
00187 #define USART_COUNT         3 
00188 #define TIMER_PRESENT         
00189 #define TIMER_COUNT         4 
00190 #define ACMP_PRESENT          
00191 #define ACMP_COUNT          2 
00192 #define I2C_PRESENT           
00193 #define I2C_COUNT           2 
00194 #define LEUART_PRESENT        
00195 #define LEUART_COUNT        2 
00196 #define PCNT_PRESENT          
00197 #define PCNT_COUNT          3 
00198 #define ADC_PRESENT           
00199 #define ADC_COUNT           1 
00200 #define DAC_PRESENT           
00201 #define DAC_COUNT           1 
00202 #define DMA_PRESENT
00203 #define DMA_COUNT           1
00204 #define AES_PRESENT
00205 #define AES_COUNT           1
00206 #define LE_PRESENT
00207 #define LE_COUNT            1
00208 #define MSC_PRESENT
00209 #define MSC_COUNT           1
00210 #define EMU_PRESENT
00211 #define EMU_COUNT           1
00212 #define RMU_PRESENT
00213 #define RMU_COUNT           1
00214 #define CMU_PRESENT
00215 #define CMU_COUNT           1
00216 #define LESENSE_PRESENT
00217 #define LESENSE_COUNT       1
00218 #define RTC_PRESENT
00219 #define RTC_COUNT           1
00220 #define GPIO_PRESENT
00221 #define GPIO_COUNT          1
00222 #define VCMP_PRESENT
00223 #define VCMP_COUNT          1
00224 #define PRS_PRESENT
00225 #define PRS_COUNT           1
00226 #define OPAMP_PRESENT
00227 #define OPAMP_COUNT         1
00228 #define BU_PRESENT
00229 #define BU_COUNT            1
00230 #define BURTC_PRESENT
00231 #define BURTC_COUNT         1
00232 #define HFXTAL_PRESENT
00233 #define HFXTAL_COUNT        1
00234 #define LFXTAL_PRESENT
00235 #define LFXTAL_COUNT        1
00236 #define WDOG_PRESENT
00237 #define WDOG_COUNT          1
00238 #define DBG_PRESENT
00239 #define DBG_COUNT           1
00240 #define ETM_PRESENT
00241 #define ETM_COUNT           1
00242 #define BOOTLOADER_PRESENT
00243 #define BOOTLOADER_COUNT    1
00244 #define ANALOG_PRESENT
00245 #define ANALOG_COUNT        1
00246 
00247 #include "core_cm3.h"       /* Cortex-M3 processor and core peripherals */
00248 #include "system_efm32gg.h" /* System Header */
00249 
00252 /**************************************************************************/
00258 #include "efm32gg_dma_ch.h"
00259 
00260 /**************************************************************************/
00265 typedef struct
00266 {
00267   __I uint32_t   STATUS;         
00268   __O uint32_t   CONFIG;         
00269   __IO uint32_t  CTRLBASE;       
00270   __I uint32_t   ALTCTRLBASE;    
00271   __I uint32_t   CHWAITSTATUS;   
00272   __O uint32_t   CHSWREQ;        
00273   __IO uint32_t  CHUSEBURSTS;    
00274   __O uint32_t   CHUSEBURSTC;    
00275   __IO uint32_t  CHREQMASKS;     
00276   __O uint32_t   CHREQMASKC;     
00277   __IO uint32_t  CHENS;          
00278   __O uint32_t   CHENC;          
00279   __IO uint32_t  CHALTS;         
00280   __O uint32_t   CHALTC;         
00281   __IO uint32_t  CHPRIS;         
00282   __O uint32_t   CHPRIC;         
00283   uint32_t       RESERVED0[3];   
00284   __IO uint32_t  ERRORC;         
00286   uint32_t       RESERVED1[880]; 
00287   __I uint32_t   CHREQSTATUS;    
00288   uint32_t       RESERVED2[1];   
00289   __I uint32_t   CHSREQSTATUS;   
00291   uint32_t       RESERVED3[121]; 
00292   __I uint32_t   IF;             
00293   __IO uint32_t  IFS;            
00294   __IO uint32_t  IFC;            
00295   __IO uint32_t  IEN;            
00296   __IO uint32_t  CTRL;           
00297   __IO uint32_t  RDS;            
00299   uint32_t       RESERVED4[2];   
00300   __IO uint32_t  LOOP0;          
00301   __IO uint32_t  LOOP1;          
00302   uint32_t       RESERVED5[14];  
00303   __IO uint32_t  RECT0;          
00305   uint32_t       RESERVED6[39];  
00307   DMA_CH_TypeDef CH[12];         
00308 } DMA_TypeDef;                   
00310 #include "efm32gg_aes.h"
00311 #include "efm32gg_msc.h"
00312 #include "efm32gg_emu.h"
00313 #include "efm32gg_rmu.h"
00314 
00315 /**************************************************************************/
00320 typedef struct
00321 {
00322   __IO uint32_t CTRL;         
00323   __IO uint32_t HFCORECLKDIV; 
00324   __IO uint32_t HFPERCLKDIV;  
00325   __IO uint32_t HFRCOCTRL;    
00326   __IO uint32_t LFRCOCTRL;    
00327   __IO uint32_t AUXHFRCOCTRL; 
00328   __IO uint32_t CALCTRL;      
00329   __IO uint32_t CALCNT;       
00330   __IO uint32_t OSCENCMD;     
00331   __IO uint32_t CMD;          
00332   __IO uint32_t LFCLKSEL;     
00333   __I uint32_t  STATUS;       
00334   __I uint32_t  IF;           
00335   __IO uint32_t IFS;          
00336   __IO uint32_t IFC;          
00337   __IO uint32_t IEN;          
00338   __IO uint32_t HFCORECLKEN0; 
00339   __IO uint32_t HFPERCLKEN0;  
00340   uint32_t      RESERVED0[2]; 
00341   __I uint32_t  SYNCBUSY;     
00342   __IO uint32_t FREEZE;       
00343   __IO uint32_t LFACLKEN0;    
00344   uint32_t      RESERVED1[1]; 
00345   __IO uint32_t LFBCLKEN0;    
00346   uint32_t      RESERVED2[1]; 
00347   __IO uint32_t LFAPRESC0;    
00348   uint32_t      RESERVED3[1]; 
00349   __IO uint32_t LFBPRESC0;    
00350   uint32_t      RESERVED4[1]; 
00351   __IO uint32_t PCNTCTRL;     
00353   uint32_t      RESERVED5[1]; 
00354   __IO uint32_t ROUTE;        
00355   __IO uint32_t LOCK;         
00356 } CMU_TypeDef;                
00358 #include "efm32gg_lesense_st.h"
00359 #include "efm32gg_lesense_buf.h"
00360 #include "efm32gg_lesense_ch.h"
00361 #include "efm32gg_lesense.h"
00362 #include "efm32gg_rtc.h"
00363 #include "efm32gg_letimer.h"
00364 #include "efm32gg_usart.h"
00365 #include "efm32gg_timer_cc.h"
00366 #include "efm32gg_timer.h"
00367 #include "efm32gg_acmp.h"
00368 #include "efm32gg_i2c.h"
00369 #include "efm32gg_gpio_p.h"
00370 #include "efm32gg_gpio.h"
00371 #include "efm32gg_vcmp.h"
00372 #include "efm32gg_prs_ch.h"
00373 
00374 /**************************************************************************/
00379 typedef struct
00380 {
00381   __IO uint32_t  SWPULSE;      
00382   __IO uint32_t  SWLEVEL;      
00383   __IO uint32_t  ROUTE;        
00385   uint32_t       RESERVED0[1]; 
00387   PRS_CH_TypeDef CH[12];       
00388 } PRS_TypeDef;                 
00390 #include "efm32gg_leuart.h"
00391 #include "efm32gg_pcnt.h"
00392 #include "efm32gg_adc.h"
00393 #include "efm32gg_dac.h"
00394 #include "efm32gg_burtc_ret.h"
00395 #include "efm32gg_burtc.h"
00396 #include "efm32gg_wdog.h"
00397 #include "efm32gg_etm.h"
00398 #include "efm32gg_dma_descriptor.h"
00399 #include "efm32gg_devinfo.h"
00400 #include "efm32gg_romtable.h"
00401 #include "efm32gg_calibrate.h"
00402 
00405 /**************************************************************************/
00410 #define DMA_BASE          (0x400C2000UL) 
00411 #define AES_BASE          (0x400E0000UL) 
00412 #define MSC_BASE          (0x400C0000UL) 
00413 #define EMU_BASE          (0x400C6000UL) 
00414 #define RMU_BASE          (0x400CA000UL) 
00415 #define CMU_BASE          (0x400C8000UL) 
00416 #define LESENSE_BASE      (0x4008C000UL) 
00417 #define RTC_BASE          (0x40080000UL) 
00418 #define LETIMER0_BASE     (0x40082000UL) 
00419 #define USART0_BASE       (0x4000C000UL) 
00420 #define USART1_BASE       (0x4000C400UL) 
00421 #define USART2_BASE       (0x4000C800UL) 
00422 #define TIMER0_BASE       (0x40010000UL) 
00423 #define TIMER1_BASE       (0x40010400UL) 
00424 #define TIMER2_BASE       (0x40010800UL) 
00425 #define TIMER3_BASE       (0x40010C00UL) 
00426 #define ACMP0_BASE        (0x40001000UL) 
00427 #define ACMP1_BASE        (0x40001400UL) 
00428 #define I2C0_BASE         (0x4000A000UL) 
00429 #define I2C1_BASE         (0x4000A400UL) 
00430 #define GPIO_BASE         (0x40006000UL) 
00431 #define VCMP_BASE         (0x40000000UL) 
00432 #define PRS_BASE          (0x400CC000UL) 
00433 #define LEUART0_BASE      (0x40084000UL) 
00434 #define LEUART1_BASE      (0x40084400UL) 
00435 #define PCNT0_BASE        (0x40086000UL) 
00436 #define PCNT1_BASE        (0x40086400UL) 
00437 #define PCNT2_BASE        (0x40086800UL) 
00438 #define ADC0_BASE         (0x40002000UL) 
00439 #define DAC0_BASE         (0x40004000UL) 
00440 #define BURTC_BASE        (0x40081000UL) 
00441 #define WDOG_BASE         (0x40088000UL) 
00442 #define ETM_BASE          (0xE0041000UL) 
00443 #define CALIBRATE_BASE    (0x0FE08000UL) 
00444 #define DEVINFO_BASE      (0x0FE081B0UL) 
00445 #define ROMTABLE_BASE     (0xE00FFFD0UL) 
00446 #define LOCKBITS_BASE     (0x0FE04000UL) 
00447 #define USERDATA_BASE     (0x0FE00000UL) 
00451 /**************************************************************************/
00456 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00457 #define AES          ((AES_TypeDef *) AES_BASE)             
00458 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00459 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00460 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00461 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00462 #define LESENSE      ((LESENSE_TypeDef *) LESENSE_BASE)     
00463 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00464 #define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    
00465 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00466 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00467 #define USART2       ((USART_TypeDef *) USART2_BASE)        
00468 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00469 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00470 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        
00471 #define TIMER3       ((TIMER_TypeDef *) TIMER3_BASE)        
00472 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00473 #define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          
00474 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00475 #define I2C1         ((I2C_TypeDef *) I2C1_BASE)            
00476 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00477 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00478 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00479 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00480 #define LEUART1      ((LEUART_TypeDef *) LEUART1_BASE)      
00481 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00482 #define PCNT1        ((PCNT_TypeDef *) PCNT1_BASE)          
00483 #define PCNT2        ((PCNT_TypeDef *) PCNT2_BASE)          
00484 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
00485 #define DAC0         ((DAC_TypeDef *) DAC0_BASE)            
00486 #define BURTC        ((BURTC_TypeDef *) BURTC_BASE)         
00487 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00488 #define ETM          ((ETM_TypeDef *) ETM_BASE)             
00489 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00490 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00491 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00495 /**************************************************************************/
00500 /**************************************************************************/
00506 #define PRS_VCMP_OUT             ((1 << 16) + 0)  
00507 #define PRS_ACMP0_OUT            ((2 << 16) + 0)  
00508 #define PRS_ACMP1_OUT            ((3 << 16) + 0)  
00509 #define PRS_DAC0_CH0             ((6 << 16) + 0)  
00510 #define PRS_DAC0_CH1             ((6 << 16) + 1)  
00511 #define PRS_ADC0_SINGLE          ((8 << 16) + 0)  
00512 #define PRS_ADC0_SCAN            ((8 << 16) + 1)  
00513 #define PRS_USART0_IRTX          ((16 << 16) + 0) 
00514 #define PRS_USART0_TXC           ((16 << 16) + 1) 
00515 #define PRS_USART0_RXDATAV       ((16 << 16) + 2) 
00516 #define PRS_USART1_TXC           ((17 << 16) + 1) 
00517 #define PRS_USART1_RXDATAV       ((17 << 16) + 2) 
00518 #define PRS_USART2_TXC           ((18 << 16) + 1) 
00519 #define PRS_USART2_RXDATAV       ((18 << 16) + 2) 
00520 #define PRS_TIMER0_UF            ((28 << 16) + 0) 
00521 #define PRS_TIMER0_OF            ((28 << 16) + 1) 
00522 #define PRS_TIMER0_CC0           ((28 << 16) + 2) 
00523 #define PRS_TIMER0_CC1           ((28 << 16) + 3) 
00524 #define PRS_TIMER0_CC2           ((28 << 16) + 4) 
00525 #define PRS_TIMER1_UF            ((29 << 16) + 0) 
00526 #define PRS_TIMER1_OF            ((29 << 16) + 1) 
00527 #define PRS_TIMER1_CC0           ((29 << 16) + 2) 
00528 #define PRS_TIMER1_CC1           ((29 << 16) + 3) 
00529 #define PRS_TIMER1_CC2           ((29 << 16) + 4) 
00530 #define PRS_TIMER2_UF            ((30 << 16) + 0) 
00531 #define PRS_TIMER2_OF            ((30 << 16) + 1) 
00532 #define PRS_TIMER2_CC0           ((30 << 16) + 2) 
00533 #define PRS_TIMER2_CC1           ((30 << 16) + 3) 
00534 #define PRS_TIMER2_CC2           ((30 << 16) + 4) 
00535 #define PRS_TIMER3_UF            ((31 << 16) + 0) 
00536 #define PRS_TIMER3_OF            ((31 << 16) + 1) 
00537 #define PRS_TIMER3_CC0           ((31 << 16) + 2) 
00538 #define PRS_TIMER3_CC1           ((31 << 16) + 3) 
00539 #define PRS_TIMER3_CC2           ((31 << 16) + 4) 
00540 #define PRS_RTC_OF               ((40 << 16) + 0) 
00541 #define PRS_RTC_COMP0            ((40 << 16) + 1) 
00542 #define PRS_RTC_COMP1            ((40 << 16) + 2) 
00543 #define PRS_GPIO_PIN0            ((48 << 16) + 0) 
00544 #define PRS_GPIO_PIN1            ((48 << 16) + 1) 
00545 #define PRS_GPIO_PIN2            ((48 << 16) + 2) 
00546 #define PRS_GPIO_PIN3            ((48 << 16) + 3) 
00547 #define PRS_GPIO_PIN4            ((48 << 16) + 4) 
00548 #define PRS_GPIO_PIN5            ((48 << 16) + 5) 
00549 #define PRS_GPIO_PIN6            ((48 << 16) + 6) 
00550 #define PRS_GPIO_PIN7            ((48 << 16) + 7) 
00551 #define PRS_GPIO_PIN8            ((49 << 16) + 0) 
00552 #define PRS_GPIO_PIN9            ((49 << 16) + 1) 
00553 #define PRS_GPIO_PIN10           ((49 << 16) + 2) 
00554 #define PRS_GPIO_PIN11           ((49 << 16) + 3) 
00555 #define PRS_GPIO_PIN12           ((49 << 16) + 4) 
00556 #define PRS_GPIO_PIN13           ((49 << 16) + 5) 
00557 #define PRS_GPIO_PIN14           ((49 << 16) + 6) 
00558 #define PRS_GPIO_PIN15           ((49 << 16) + 7) 
00559 #define PRS_LETIMER0_CH0         ((52 << 16) + 0) 
00560 #define PRS_LETIMER0_CH1         ((52 << 16) + 1) 
00561 #define PRS_BURTC_OF             ((55 << 16) + 0) 
00562 #define PRS_BURTC_COMP0          ((55 << 16) + 1) 
00563 #define PRS_LESENSE_SCANRES0     ((57 << 16) + 0) 
00564 #define PRS_LESENSE_SCANRES1     ((57 << 16) + 1) 
00565 #define PRS_LESENSE_SCANRES2     ((57 << 16) + 2) 
00566 #define PRS_LESENSE_SCANRES3     ((57 << 16) + 3) 
00567 #define PRS_LESENSE_SCANRES4     ((57 << 16) + 4) 
00568 #define PRS_LESENSE_SCANRES5     ((57 << 16) + 5) 
00569 #define PRS_LESENSE_SCANRES6     ((57 << 16) + 6) 
00570 #define PRS_LESENSE_SCANRES7     ((57 << 16) + 7) 
00571 #define PRS_LESENSE_SCANRES8     ((58 << 16) + 0) 
00572 #define PRS_LESENSE_SCANRES9     ((58 << 16) + 1) 
00573 #define PRS_LESENSE_SCANRES10    ((58 << 16) + 2) 
00574 #define PRS_LESENSE_SCANRES11    ((58 << 16) + 3) 
00575 #define PRS_LESENSE_SCANRES12    ((58 << 16) + 4) 
00576 #define PRS_LESENSE_SCANRES13    ((58 << 16) + 5) 
00577 #define PRS_LESENSE_SCANRES14    ((58 << 16) + 6) 
00578 #define PRS_LESENSE_SCANRES15    ((58 << 16) + 7) 
00579 #define PRS_LESENSE_DEC0         ((59 << 16) + 0) 
00580 #define PRS_LESENSE_DEC1         ((59 << 16) + 1) 
00581 #define PRS_LESENSE_DEC2         ((59 << 16) + 2) 
00585 #include "efm32gg_dmareq.h"
00586 #include "efm32gg_dmactrl.h"
00587 
00588 /**************************************************************************/
00593 /* Bit fields for DMA STATUS */
00594 #define _DMA_STATUS_RESETVALUE                          0x100B0000UL                          
00595 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00596 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00597 #define _DMA_STATUS_EN_SHIFT                            0                                     
00598 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00599 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00600 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00601 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00602 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00603 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00604 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00605 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00606 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00607 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00608 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00609 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00610 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00611 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00612 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00613 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00614 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00615 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00616 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00617 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00618 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00619 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00620 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00621 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00622 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00623 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00624 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00625 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00626 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00627 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00628 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00629 #define _DMA_STATUS_CHNUM_DEFAULT                       0x0000000BUL                          
00630 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00632 /* Bit fields for DMA CONFIG */
00633 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00634 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00635 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00636 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00637 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00638 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00639 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00640 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00641 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00642 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00643 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00644 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00646 /* Bit fields for DMA CTRLBASE */
00647 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00648 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00649 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00650 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00651 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00652 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00654 /* Bit fields for DMA ALTCTRLBASE */
00655 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000100UL                                
00656 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00657 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00658 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00659 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000100UL                                
00660 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00662 /* Bit fields for DMA CHWAITSTATUS */
00663 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x00000FFFUL                                     
00664 #define _DMA_CHWAITSTATUS_MASK                          0x00000FFFUL                                     
00665 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                     
00666 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                                
00667 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                            
00668 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                     
00669 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)   
00670 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                     
00671 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                                
00672 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                            
00673 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                     
00674 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)   
00675 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                     
00676 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                                
00677 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                            
00678 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                     
00679 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)   
00680 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                     
00681 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                                
00682 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                            
00683 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                     
00684 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)   
00685 #define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                     
00686 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                                
00687 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                           
00688 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                     
00689 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)   
00690 #define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                     
00691 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                                
00692 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                           
00693 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                     
00694 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)   
00695 #define DMA_CHWAITSTATUS_CH6WAITSTATUS                  (0x1UL << 6)                                     
00696 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT           6                                                
00697 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK            0x40UL                                           
00698 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT         0x00000001UL                                     
00699 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)   
00700 #define DMA_CHWAITSTATUS_CH7WAITSTATUS                  (0x1UL << 7)                                     
00701 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT           7                                                
00702 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK            0x80UL                                           
00703 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT         0x00000001UL                                     
00704 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)   
00705 #define DMA_CHWAITSTATUS_CH8WAITSTATUS                  (0x1UL << 8)                                     
00706 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT           8                                                
00707 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK            0x100UL                                          
00708 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT         0x00000001UL                                     
00709 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8)   
00710 #define DMA_CHWAITSTATUS_CH9WAITSTATUS                  (0x1UL << 9)                                     
00711 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT           9                                                
00712 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK            0x200UL                                          
00713 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT         0x00000001UL                                     
00714 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9)   
00715 #define DMA_CHWAITSTATUS_CH10WAITSTATUS                 (0x1UL << 10)                                    
00716 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT          10                                               
00717 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK           0x400UL                                          
00718 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT        0x00000001UL                                     
00719 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT         (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) 
00720 #define DMA_CHWAITSTATUS_CH11WAITSTATUS                 (0x1UL << 11)                                    
00721 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT          11                                               
00722 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK           0x800UL                                          
00723 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT        0x00000001UL                                     
00724 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT         (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) 
00726 /* Bit fields for DMA CHSWREQ */
00727 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                           
00728 #define _DMA_CHSWREQ_MASK                               0x00000FFFUL                           
00729 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                           
00730 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                      
00731 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                  
00732 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                           
00733 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)   
00734 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                           
00735 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                      
00736 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                  
00737 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                           
00738 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)   
00739 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                           
00740 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                      
00741 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                  
00742 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                           
00743 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)   
00744 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                           
00745 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                      
00746 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                  
00747 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                           
00748 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)   
00749 #define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                           
00750 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                      
00751 #define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                                 
00752 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                           
00753 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)   
00754 #define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                           
00755 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                      
00756 #define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                                 
00757 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                           
00758 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)   
00759 #define DMA_CHSWREQ_CH6SWREQ                            (0x1UL << 6)                           
00760 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT                     6                                      
00761 #define _DMA_CHSWREQ_CH6SWREQ_MASK                      0x40UL                                 
00762 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT                   0x00000000UL                           
00763 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)   
00764 #define DMA_CHSWREQ_CH7SWREQ                            (0x1UL << 7)                           
00765 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT                     7                                      
00766 #define _DMA_CHSWREQ_CH7SWREQ_MASK                      0x80UL                                 
00767 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT                   0x00000000UL                           
00768 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)   
00769 #define DMA_CHSWREQ_CH8SWREQ                            (0x1UL << 8)                           
00770 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT                     8                                      
00771 #define _DMA_CHSWREQ_CH8SWREQ_MASK                      0x100UL                                
00772 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT                   0x00000000UL                           
00773 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8)   
00774 #define DMA_CHSWREQ_CH9SWREQ                            (0x1UL << 9)                           
00775 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT                     9                                      
00776 #define _DMA_CHSWREQ_CH9SWREQ_MASK                      0x200UL                                
00777 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT                   0x00000000UL                           
00778 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9)   
00779 #define DMA_CHSWREQ_CH10SWREQ                           (0x1UL << 10)                          
00780 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT                    10                                     
00781 #define _DMA_CHSWREQ_CH10SWREQ_MASK                     0x400UL                                
00782 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT                  0x00000000UL                           
00783 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT                   (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) 
00784 #define DMA_CHSWREQ_CH11SWREQ                           (0x1UL << 11)                          
00785 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT                    11                                     
00786 #define _DMA_CHSWREQ_CH11SWREQ_MASK                     0x800UL                                
00787 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT                  0x00000000UL                           
00788 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT                   (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) 
00790 /* Bit fields for DMA CHUSEBURSTS */
00791 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00792 #define _DMA_CHUSEBURSTS_MASK                           0x00000FFFUL                                        
00793 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00794 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00795 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00796 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00797 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00798 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00799 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00800 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00801 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00802 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00803 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00804 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00805 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00806 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00807 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00808 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00809 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00810 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00811 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00812 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00813 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00814 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00815 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00816 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00817 #define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        
00818 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   
00819 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              
00820 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        
00821 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        
00822 #define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        
00823 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   
00824 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              
00825 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        
00826 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        
00827 #define DMA_CHUSEBURSTS_CH6USEBURSTS                    (0x1UL << 6)                                        
00828 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT             6                                                   
00829 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK              0x40UL                                              
00830 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT           0x00000000UL                                        
00831 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)        
00832 #define DMA_CHUSEBURSTS_CH7USEBURSTS                    (0x1UL << 7)                                        
00833 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT             7                                                   
00834 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK              0x80UL                                              
00835 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT           0x00000000UL                                        
00836 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)        
00837 #define DMA_CHUSEBURSTS_CH8USEBURSTS                    (0x1UL << 8)                                        
00838 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT             8                                                   
00839 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK              0x100UL                                             
00840 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT           0x00000000UL                                        
00841 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8)        
00842 #define DMA_CHUSEBURSTS_CH9USEBURSTS                    (0x1UL << 9)                                        
00843 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT             9                                                   
00844 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK              0x200UL                                             
00845 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT           0x00000000UL                                        
00846 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9)        
00847 #define DMA_CHUSEBURSTS_CH10USEBURSTS                   (0x1UL << 10)                                       
00848 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT            10                                                  
00849 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK             0x400UL                                             
00850 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT          0x00000000UL                                        
00851 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT           (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10)      
00852 #define DMA_CHUSEBURSTS_CH11USEBURSTS                   (0x1UL << 11)                                       
00853 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT            11                                                  
00854 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK             0x800UL                                             
00855 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT          0x00000000UL                                        
00856 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT           (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11)      
00858 /* Bit fields for DMA CHUSEBURSTC */
00859 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                   
00860 #define _DMA_CHUSEBURSTC_MASK                           0x00000FFFUL                                   
00861 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                   
00862 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                              
00863 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                          
00864 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                   
00865 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)   
00866 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                   
00867 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                              
00868 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                          
00869 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                   
00870 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)   
00871 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                   
00872 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                              
00873 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                          
00874 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                   
00875 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)   
00876 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                   
00877 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                              
00878 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                          
00879 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                   
00880 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)   
00881 #define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                   
00882 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                              
00883 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                         
00884 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                   
00885 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)   
00886 #define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                   
00887 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                              
00888 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                         
00889 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                   
00890 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)   
00891 #define DMA_CHUSEBURSTC_CH6USEBURSTC                    (0x1UL << 6)                                   
00892 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT             6                                              
00893 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK              0x40UL                                         
00894 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT           0x00000000UL                                   
00895 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)   
00896 #define DMA_CHUSEBURSTC_CH7USEBURSTC                    (0x1UL << 7)                                   
00897 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT             7                                              
00898 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK              0x80UL                                         
00899 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT           0x00000000UL                                   
00900 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)   
00901 #define DMA_CHUSEBURSTC_CH08USEBURSTC                   (0x1UL << 8)                                   
00902 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT            8                                              
00903 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK             0x100UL                                        
00904 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT          0x00000000UL                                   
00905 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT           (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8)  
00906 #define DMA_CHUSEBURSTC_CH9USEBURSTC                    (0x1UL << 9)                                   
00907 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT             9                                              
00908 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK              0x200UL                                        
00909 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT           0x00000000UL                                   
00910 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9)   
00911 #define DMA_CHUSEBURSTC_CH10USEBURSTC                   (0x1UL << 10)                                  
00912 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT            10                                             
00913 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK             0x400UL                                        
00914 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT          0x00000000UL                                   
00915 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT           (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) 
00916 #define DMA_CHUSEBURSTC_CH11USEBURSTC                   (0x1UL << 11)                                  
00917 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT            11                                             
00918 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK             0x800UL                                        
00919 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT          0x00000000UL                                   
00920 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT           (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) 
00922 /* Bit fields for DMA CHREQMASKS */
00923 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                                 
00924 #define _DMA_CHREQMASKS_MASK                            0x00000FFFUL                                 
00925 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                                 
00926 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                            
00927 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                        
00928 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                                 
00929 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)   
00930 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                                 
00931 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                            
00932 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                        
00933 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                                 
00934 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)   
00935 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                                 
00936 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                            
00937 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                        
00938 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                                 
00939 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)   
00940 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                                 
00941 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                            
00942 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                        
00943 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                                 
00944 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)   
00945 #define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                                 
00946 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                            
00947 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                       
00948 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                                 
00949 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)   
00950 #define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                                 
00951 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                            
00952 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                       
00953 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                                 
00954 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)   
00955 #define DMA_CHREQMASKS_CH6REQMASKS                      (0x1UL << 6)                                 
00956 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT               6                                            
00957 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK                0x40UL                                       
00958 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT             0x00000000UL                                 
00959 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)   
00960 #define DMA_CHREQMASKS_CH7REQMASKS                      (0x1UL << 7)                                 
00961 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT               7                                            
00962 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK                0x80UL                                       
00963 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT             0x00000000UL                                 
00964 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)   
00965 #define DMA_CHREQMASKS_CH8REQMASKS                      (0x1UL << 8)                                 
00966 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT               8                                            
00967 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK                0x100UL                                      
00968 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT             0x00000000UL                                 
00969 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8)   
00970 #define DMA_CHREQMASKS_CH9REQMASKS                      (0x1UL << 9)                                 
00971 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT               9                                            
00972 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK                0x200UL                                      
00973 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT             0x00000000UL                                 
00974 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9)   
00975 #define DMA_CHREQMASKS_CH10REQMASKS                     (0x1UL << 10)                                
00976 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT              10                                           
00977 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK               0x400UL                                      
00978 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT            0x00000000UL                                 
00979 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT             (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) 
00980 #define DMA_CHREQMASKS_CH11REQMASKS                     (0x1UL << 11)                                
00981 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT              11                                           
00982 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK               0x800UL                                      
00983 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT            0x00000000UL                                 
00984 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT             (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) 
00986 /* Bit fields for DMA CHREQMASKC */
00987 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                                 
00988 #define _DMA_CHREQMASKC_MASK                            0x00000FFFUL                                 
00989 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                                 
00990 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                            
00991 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                        
00992 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                                 
00993 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)   
00994 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                                 
00995 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                            
00996 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                        
00997 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                                 
00998 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)   
00999 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                                 
01000 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                            
01001 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                        
01002 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                                 
01003 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)   
01004 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                                 
01005 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                            
01006 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                        
01007 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                                 
01008 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)   
01009 #define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                                 
01010 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                            
01011 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                       
01012 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                                 
01013 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)   
01014 #define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                                 
01015 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                            
01016 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                       
01017 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                                 
01018 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)   
01019 #define DMA_CHREQMASKC_CH6REQMASKC                      (0x1UL << 6)                                 
01020 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT               6                                            
01021 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK                0x40UL                                       
01022 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT             0x00000000UL                                 
01023 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)   
01024 #define DMA_CHREQMASKC_CH7REQMASKC                      (0x1UL << 7)                                 
01025 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT               7                                            
01026 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK                0x80UL                                       
01027 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT             0x00000000UL                                 
01028 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)   
01029 #define DMA_CHREQMASKC_CH8REQMASKC                      (0x1UL << 8)                                 
01030 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT               8                                            
01031 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK                0x100UL                                      
01032 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT             0x00000000UL                                 
01033 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8)   
01034 #define DMA_CHREQMASKC_CH9REQMASKC                      (0x1UL << 9)                                 
01035 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT               9                                            
01036 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK                0x200UL                                      
01037 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT             0x00000000UL                                 
01038 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9)   
01039 #define DMA_CHREQMASKC_CH10REQMASKC                     (0x1UL << 10)                                
01040 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT              10                                           
01041 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK               0x400UL                                      
01042 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT            0x00000000UL                                 
01043 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT             (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) 
01044 #define DMA_CHREQMASKC_CH11REQMASKC                     (0x1UL << 11)                                
01045 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT              11                                           
01046 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK               0x800UL                                      
01047 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT            0x00000000UL                                 
01048 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT             (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) 
01050 /* Bit fields for DMA CHENS */
01051 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                       
01052 #define _DMA_CHENS_MASK                                 0x00000FFFUL                       
01053 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                       
01054 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                  
01055 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                              
01056 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                       
01057 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0)   
01058 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                       
01059 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                  
01060 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                              
01061 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                       
01062 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1)   
01063 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                       
01064 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                  
01065 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                              
01066 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                       
01067 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2)   
01068 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                       
01069 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                  
01070 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                              
01071 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                       
01072 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3)   
01073 #define DMA_CHENS_CH4ENS                                (0x1UL << 4)                       
01074 #define _DMA_CHENS_CH4ENS_SHIFT                         4                                  
01075 #define _DMA_CHENS_CH4ENS_MASK                          0x10UL                             
01076 #define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                       
01077 #define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4)   
01078 #define DMA_CHENS_CH5ENS                                (0x1UL << 5)                       
01079 #define _DMA_CHENS_CH5ENS_SHIFT                         5                                  
01080 #define _DMA_CHENS_CH5ENS_MASK                          0x20UL                             
01081 #define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                       
01082 #define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5)   
01083 #define DMA_CHENS_CH6ENS                                (0x1UL << 6)                       
01084 #define _DMA_CHENS_CH6ENS_SHIFT                         6                                  
01085 #define _DMA_CHENS_CH6ENS_MASK                          0x40UL                             
01086 #define _DMA_CHENS_CH6ENS_DEFAULT                       0x00000000UL                       
01087 #define DMA_CHENS_CH6ENS_DEFAULT                        (_DMA_CHENS_CH6ENS_DEFAULT << 6)   
01088 #define DMA_CHENS_CH7ENS                                (0x1UL << 7)                       
01089 #define _DMA_CHENS_CH7ENS_SHIFT                         7                                  
01090 #define _DMA_CHENS_CH7ENS_MASK                          0x80UL                             
01091 #define _DMA_CHENS_CH7ENS_DEFAULT                       0x00000000UL                       
01092 #define DMA_CHENS_CH7ENS_DEFAULT                        (_DMA_CHENS_CH7ENS_DEFAULT << 7)   
01093 #define DMA_CHENS_CH8ENS                                (0x1UL << 8)                       
01094 #define _DMA_CHENS_CH8ENS_SHIFT                         8                                  
01095 #define _DMA_CHENS_CH8ENS_MASK                          0x100UL                            
01096 #define _DMA_CHENS_CH8ENS_DEFAULT                       0x00000000UL                       
01097 #define DMA_CHENS_CH8ENS_DEFAULT                        (_DMA_CHENS_CH8ENS_DEFAULT << 8)   
01098 #define DMA_CHENS_CH9ENS                                (0x1UL << 9)                       
01099 #define _DMA_CHENS_CH9ENS_SHIFT                         9                                  
01100 #define _DMA_CHENS_CH9ENS_MASK                          0x200UL                            
01101 #define _DMA_CHENS_CH9ENS_DEFAULT                       0x00000000UL                       
01102 #define DMA_CHENS_CH9ENS_DEFAULT                        (_DMA_CHENS_CH9ENS_DEFAULT << 9)   
01103 #define DMA_CHENS_CH10ENS                               (0x1UL << 10)                      
01104 #define _DMA_CHENS_CH10ENS_SHIFT                        10                                 
01105 #define _DMA_CHENS_CH10ENS_MASK                         0x400UL                            
01106 #define _DMA_CHENS_CH10ENS_DEFAULT                      0x00000000UL                       
01107 #define DMA_CHENS_CH10ENS_DEFAULT                       (_DMA_CHENS_CH10ENS_DEFAULT << 10) 
01108 #define DMA_CHENS_CH11ENS                               (0x1UL << 11)                      
01109 #define _DMA_CHENS_CH11ENS_SHIFT                        11                                 
01110 #define _DMA_CHENS_CH11ENS_MASK                         0x800UL                            
01111 #define _DMA_CHENS_CH11ENS_DEFAULT                      0x00000000UL                       
01112 #define DMA_CHENS_CH11ENS_DEFAULT                       (_DMA_CHENS_CH11ENS_DEFAULT << 11) 
01114 /* Bit fields for DMA CHENC */
01115 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                       
01116 #define _DMA_CHENC_MASK                                 0x00000FFFUL                       
01117 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                       
01118 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                  
01119 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                              
01120 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                       
01121 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0)   
01122 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                       
01123 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                  
01124 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                              
01125 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                       
01126 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1)   
01127 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                       
01128 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                  
01129 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                              
01130 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                       
01131 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2)   
01132 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                       
01133 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                  
01134 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                              
01135 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                       
01136 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3)   
01137 #define DMA_CHENC_CH4ENC                                (0x1UL << 4)                       
01138 #define _DMA_CHENC_CH4ENC_SHIFT                         4                                  
01139 #define _DMA_CHENC_CH4ENC_MASK                          0x10UL                             
01140 #define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                       
01141 #define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4)   
01142 #define DMA_CHENC_CH5ENC                                (0x1UL << 5)                       
01143 #define _DMA_CHENC_CH5ENC_SHIFT                         5                                  
01144 #define _DMA_CHENC_CH5ENC_MASK                          0x20UL                             
01145 #define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                       
01146 #define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5)   
01147 #define DMA_CHENC_CH6ENC                                (0x1UL << 6)                       
01148 #define _DMA_CHENC_CH6ENC_SHIFT                         6                                  
01149 #define _DMA_CHENC_CH6ENC_MASK                          0x40UL                             
01150 #define _DMA_CHENC_CH6ENC_DEFAULT                       0x00000000UL                       
01151 #define DMA_CHENC_CH6ENC_DEFAULT                        (_DMA_CHENC_CH6ENC_DEFAULT << 6)   
01152 #define DMA_CHENC_CH7ENC                                (0x1UL << 7)                       
01153 #define _DMA_CHENC_CH7ENC_SHIFT                         7                                  
01154 #define _DMA_CHENC_CH7ENC_MASK                          0x80UL                             
01155 #define _DMA_CHENC_CH7ENC_DEFAULT                       0x00000000UL                       
01156 #define DMA_CHENC_CH7ENC_DEFAULT                        (_DMA_CHENC_CH7ENC_DEFAULT << 7)   
01157 #define DMA_CHENC_CH8ENC                                (0x1UL << 8)                       
01158 #define _DMA_CHENC_CH8ENC_SHIFT                         8                                  
01159 #define _DMA_CHENC_CH8ENC_MASK                          0x100UL                            
01160 #define _DMA_CHENC_CH8ENC_DEFAULT                       0x00000000UL                       
01161 #define DMA_CHENC_CH8ENC_DEFAULT                        (_DMA_CHENC_CH8ENC_DEFAULT << 8)   
01162 #define DMA_CHENC_CH9ENC                                (0x1UL << 9)                       
01163 #define _DMA_CHENC_CH9ENC_SHIFT                         9                                  
01164 #define _DMA_CHENC_CH9ENC_MASK                          0x200UL                            
01165 #define _DMA_CHENC_CH9ENC_DEFAULT                       0x00000000UL                       
01166 #define DMA_CHENC_CH9ENC_DEFAULT                        (_DMA_CHENC_CH9ENC_DEFAULT << 9)   
01167 #define DMA_CHENC_CH10ENC                               (0x1UL << 10)                      
01168 #define _DMA_CHENC_CH10ENC_SHIFT                        10                                 
01169 #define _DMA_CHENC_CH10ENC_MASK                         0x400UL                            
01170 #define _DMA_CHENC_CH10ENC_DEFAULT                      0x00000000UL                       
01171 #define DMA_CHENC_CH10ENC_DEFAULT                       (_DMA_CHENC_CH10ENC_DEFAULT << 10) 
01172 #define DMA_CHENC_CH11ENC                               (0x1UL << 11)                      
01173 #define _DMA_CHENC_CH11ENC_SHIFT                        11                                 
01174 #define _DMA_CHENC_CH11ENC_MASK                         0x800UL                            
01175 #define _DMA_CHENC_CH11ENC_DEFAULT                      0x00000000UL                       
01176 #define DMA_CHENC_CH11ENC_DEFAULT                       (_DMA_CHENC_CH11ENC_DEFAULT << 11) 
01178 /* Bit fields for DMA CHALTS */
01179 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                         
01180 #define _DMA_CHALTS_MASK                                0x00000FFFUL                         
01181 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                         
01182 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                    
01183 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                                
01184 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                         
01185 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)   
01186 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                         
01187 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                    
01188 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                                
01189 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                         
01190 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)   
01191 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                         
01192 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                    
01193 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                                
01194 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                         
01195 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)   
01196 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                         
01197 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                    
01198 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                                
01199 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                         
01200 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)   
01201 #define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                         
01202 #define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                    
01203 #define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                               
01204 #define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                         
01205 #define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)   
01206 #define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                         
01207 #define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                    
01208 #define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                               
01209 #define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                         
01210 #define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)   
01211 #define DMA_CHALTS_CH6ALTS                              (0x1UL << 6)                         
01212 #define _DMA_CHALTS_CH6ALTS_SHIFT                       6                                    
01213 #define _DMA_CHALTS_CH6ALTS_MASK                        0x40UL                               
01214 #define _DMA_CHALTS_CH6ALTS_DEFAULT                     0x00000000UL                         
01215 #define DMA_CHALTS_CH6ALTS_DEFAULT                      (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)   
01216 #define DMA_CHALTS_CH7ALTS                              (0x1UL << 7)                         
01217 #define _DMA_CHALTS_CH7ALTS_SHIFT                       7                                    
01218 #define _DMA_CHALTS_CH7ALTS_MASK                        0x80UL                               
01219 #define _DMA_CHALTS_CH7ALTS_DEFAULT                     0x00000000UL                         
01220 #define DMA_CHALTS_CH7ALTS_DEFAULT                      (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)   
01221 #define DMA_CHALTS_CH8ALTS                              (0x1UL << 8)                         
01222 #define _DMA_CHALTS_CH8ALTS_SHIFT                       8                                    
01223 #define _DMA_CHALTS_CH8ALTS_MASK                        0x100UL                              
01224 #define _DMA_CHALTS_CH8ALTS_DEFAULT                     0x00000000UL                         
01225 #define DMA_CHALTS_CH8ALTS_DEFAULT                      (_DMA_CHALTS_CH8ALTS_DEFAULT << 8)   
01226 #define DMA_CHALTS_CH9ALTS                              (0x1UL << 9)                         
01227 #define _DMA_CHALTS_CH9ALTS_SHIFT                       9                                    
01228 #define _DMA_CHALTS_CH9ALTS_MASK                        0x200UL                              
01229 #define _DMA_CHALTS_CH9ALTS_DEFAULT                     0x00000000UL                         
01230 #define DMA_CHALTS_CH9ALTS_DEFAULT                      (_DMA_CHALTS_CH9ALTS_DEFAULT << 9)   
01231 #define DMA_CHALTS_CH10ALTS                             (0x1UL << 10)                        
01232 #define _DMA_CHALTS_CH10ALTS_SHIFT                      10                                   
01233 #define _DMA_CHALTS_CH10ALTS_MASK                       0x400UL                              
01234 #define _DMA_CHALTS_CH10ALTS_DEFAULT                    0x00000000UL                         
01235 #define DMA_CHALTS_CH10ALTS_DEFAULT                     (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) 
01236 #define DMA_CHALTS_CH11ALTS                             (0x1UL << 11)                        
01237 #define _DMA_CHALTS_CH11ALTS_SHIFT                      11                                   
01238 #define _DMA_CHALTS_CH11ALTS_MASK                       0x800UL                              
01239 #define _DMA_CHALTS_CH11ALTS_DEFAULT                    0x00000000UL                         
01240 #define DMA_CHALTS_CH11ALTS_DEFAULT                     (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) 
01242 /* Bit fields for DMA CHALTC */
01243 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                         
01244 #define _DMA_CHALTC_MASK                                0x00000FFFUL                         
01245 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                         
01246 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                    
01247 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                                
01248 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                         
01249 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)   
01250 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                         
01251 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                    
01252 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                                
01253 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                         
01254 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)   
01255 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                         
01256 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                    
01257 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                                
01258 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                         
01259 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)   
01260 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                         
01261 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                    
01262 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                                
01263 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                         
01264 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)   
01265 #define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                         
01266 #define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                    
01267 #define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                               
01268 #define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                         
01269 #define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)   
01270 #define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                         
01271 #define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                    
01272 #define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                               
01273 #define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                         
01274 #define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)   
01275 #define DMA_CHALTC_CH6ALTC                              (0x1UL << 6)                         
01276 #define _DMA_CHALTC_CH6ALTC_SHIFT                       6                                    
01277 #define _DMA_CHALTC_CH6ALTC_MASK                        0x40UL                               
01278 #define _DMA_CHALTC_CH6ALTC_DEFAULT                     0x00000000UL                         
01279 #define DMA_CHALTC_CH6ALTC_DEFAULT                      (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)   
01280 #define DMA_CHALTC_CH7ALTC                              (0x1UL << 7)                         
01281 #define _DMA_CHALTC_CH7ALTC_SHIFT                       7                                    
01282 #define _DMA_CHALTC_CH7ALTC_MASK                        0x80UL                               
01283 #define _DMA_CHALTC_CH7ALTC_DEFAULT                     0x00000000UL                         
01284 #define DMA_CHALTC_CH7ALTC_DEFAULT                      (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)   
01285 #define DMA_CHALTC_CH8ALTC                              (0x1UL << 8)                         
01286 #define _DMA_CHALTC_CH8ALTC_SHIFT                       8                                    
01287 #define _DMA_CHALTC_CH8ALTC_MASK                        0x100UL                              
01288 #define _DMA_CHALTC_CH8ALTC_DEFAULT                     0x00000000UL                         
01289 #define DMA_CHALTC_CH8ALTC_DEFAULT                      (_DMA_CHALTC_CH8ALTC_DEFAULT << 8)   
01290 #define DMA_CHALTC_CH9ALTC                              (0x1UL << 9)                         
01291 #define _DMA_CHALTC_CH9ALTC_SHIFT                       9                                    
01292 #define _DMA_CHALTC_CH9ALTC_MASK                        0x200UL                              
01293 #define _DMA_CHALTC_CH9ALTC_DEFAULT                     0x00000000UL                         
01294 #define DMA_CHALTC_CH9ALTC_DEFAULT                      (_DMA_CHALTC_CH9ALTC_DEFAULT << 9)   
01295 #define DMA_CHALTC_CH10ALTC                             (0x1UL << 10)                        
01296 #define _DMA_CHALTC_CH10ALTC_SHIFT                      10                                   
01297 #define _DMA_CHALTC_CH10ALTC_MASK                       0x400UL                              
01298 #define _DMA_CHALTC_CH10ALTC_DEFAULT                    0x00000000UL                         
01299 #define DMA_CHALTC_CH10ALTC_DEFAULT                     (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) 
01300 #define DMA_CHALTC_CH11ALTC                             (0x1UL << 11)                        
01301 #define _DMA_CHALTC_CH11ALTC_SHIFT                      11                                   
01302 #define _DMA_CHALTC_CH11ALTC_MASK                       0x800UL                              
01303 #define _DMA_CHALTC_CH11ALTC_DEFAULT                    0x00000000UL                         
01304 #define DMA_CHALTC_CH11ALTC_DEFAULT                     (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) 
01306 /* Bit fields for DMA CHPRIS */
01307 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                         
01308 #define _DMA_CHPRIS_MASK                                0x00000FFFUL                         
01309 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                         
01310 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                    
01311 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                                
01312 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                         
01313 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)   
01314 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                         
01315 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                    
01316 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                                
01317 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                         
01318 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)   
01319 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                         
01320 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                    
01321 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                                
01322 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                         
01323 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)   
01324 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                         
01325 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                    
01326 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                                
01327 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                         
01328 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)   
01329 #define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                         
01330 #define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                    
01331 #define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                               
01332 #define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                         
01333 #define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)   
01334 #define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                         
01335 #define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                    
01336 #define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                               
01337 #define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                         
01338 #define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)   
01339 #define DMA_CHPRIS_CH6PRIS                              (0x1UL << 6)                         
01340 #define _DMA_CHPRIS_CH6PRIS_SHIFT                       6                                    
01341 #define _DMA_CHPRIS_CH6PRIS_MASK                        0x40UL                               
01342 #define _DMA_CHPRIS_CH6PRIS_DEFAULT                     0x00000000UL                         
01343 #define DMA_CHPRIS_CH6PRIS_DEFAULT                      (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)   
01344 #define DMA_CHPRIS_CH7PRIS                              (0x1UL << 7)                         
01345 #define _DMA_CHPRIS_CH7PRIS_SHIFT                       7                                    
01346 #define _DMA_CHPRIS_CH7PRIS_MASK                        0x80UL                               
01347 #define _DMA_CHPRIS_CH7PRIS_DEFAULT                     0x00000000UL                         
01348 #define DMA_CHPRIS_CH7PRIS_DEFAULT                      (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)   
01349 #define DMA_CHPRIS_CH8PRIS                              (0x1UL << 8)                         
01350 #define _DMA_CHPRIS_CH8PRIS_SHIFT                       8                                    
01351 #define _DMA_CHPRIS_CH8PRIS_MASK                        0x100UL                              
01352 #define _DMA_CHPRIS_CH8PRIS_DEFAULT                     0x00000000UL                         
01353 #define DMA_CHPRIS_CH8PRIS_DEFAULT                      (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8)   
01354 #define DMA_CHPRIS_CH9PRIS                              (0x1UL << 9)                         
01355 #define _DMA_CHPRIS_CH9PRIS_SHIFT                       9                                    
01356 #define _DMA_CHPRIS_CH9PRIS_MASK                        0x200UL                              
01357 #define _DMA_CHPRIS_CH9PRIS_DEFAULT                     0x00000000UL                         
01358 #define DMA_CHPRIS_CH9PRIS_DEFAULT                      (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9)   
01359 #define DMA_CHPRIS_CH10PRIS                             (0x1UL << 10)                        
01360 #define _DMA_CHPRIS_CH10PRIS_SHIFT                      10                                   
01361 #define _DMA_CHPRIS_CH10PRIS_MASK                       0x400UL                              
01362 #define _DMA_CHPRIS_CH10PRIS_DEFAULT                    0x00000000UL                         
01363 #define DMA_CHPRIS_CH10PRIS_DEFAULT                     (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) 
01364 #define DMA_CHPRIS_CH11PRIS                             (0x1UL << 11)                        
01365 #define _DMA_CHPRIS_CH11PRIS_SHIFT                      11                                   
01366 #define _DMA_CHPRIS_CH11PRIS_MASK                       0x800UL                              
01367 #define _DMA_CHPRIS_CH11PRIS_DEFAULT                    0x00000000UL                         
01368 #define DMA_CHPRIS_CH11PRIS_DEFAULT                     (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) 
01370 /* Bit fields for DMA CHPRIC */
01371 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                         
01372 #define _DMA_CHPRIC_MASK                                0x00000FFFUL                         
01373 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                         
01374 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                    
01375 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                                
01376 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                         
01377 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)   
01378 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                         
01379 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                    
01380 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                                
01381 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                         
01382 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)   
01383 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                         
01384 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                    
01385 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                                
01386 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                         
01387 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)   
01388 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                         
01389 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                    
01390 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                                
01391 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                         
01392 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)   
01393 #define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                         
01394 #define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                    
01395 #define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                               
01396 #define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                         
01397 #define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)   
01398 #define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                         
01399 #define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                    
01400 #define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                               
01401 #define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                         
01402 #define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)   
01403 #define DMA_CHPRIC_CH6PRIC                              (0x1UL << 6)                         
01404 #define _DMA_CHPRIC_CH6PRIC_SHIFT                       6                                    
01405 #define _DMA_CHPRIC_CH6PRIC_MASK                        0x40UL                               
01406 #define _DMA_CHPRIC_CH6PRIC_DEFAULT                     0x00000000UL                         
01407 #define DMA_CHPRIC_CH6PRIC_DEFAULT                      (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)   
01408 #define DMA_CHPRIC_CH7PRIC                              (0x1UL << 7)                         
01409 #define _DMA_CHPRIC_CH7PRIC_SHIFT                       7                                    
01410 #define _DMA_CHPRIC_CH7PRIC_MASK                        0x80UL                               
01411 #define _DMA_CHPRIC_CH7PRIC_DEFAULT                     0x00000000UL                         
01412 #define DMA_CHPRIC_CH7PRIC_DEFAULT                      (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)   
01413 #define DMA_CHPRIC_CH8PRIC                              (0x1UL << 8)                         
01414 #define _DMA_CHPRIC_CH8PRIC_SHIFT                       8                                    
01415 #define _DMA_CHPRIC_CH8PRIC_MASK                        0x100UL                              
01416 #define _DMA_CHPRIC_CH8PRIC_DEFAULT                     0x00000000UL                         
01417 #define DMA_CHPRIC_CH8PRIC_DEFAULT                      (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8)   
01418 #define DMA_CHPRIC_CH9PRIC                              (0x1UL << 9)                         
01419 #define _DMA_CHPRIC_CH9PRIC_SHIFT                       9                                    
01420 #define _DMA_CHPRIC_CH9PRIC_MASK                        0x200UL                              
01421 #define _DMA_CHPRIC_CH9PRIC_DEFAULT                     0x00000000UL                         
01422 #define DMA_CHPRIC_CH9PRIC_DEFAULT                      (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9)   
01423 #define DMA_CHPRIC_CH10PRIC                             (0x1UL << 10)                        
01424 #define _DMA_CHPRIC_CH10PRIC_SHIFT                      10                                   
01425 #define _DMA_CHPRIC_CH10PRIC_MASK                       0x400UL                              
01426 #define _DMA_CHPRIC_CH10PRIC_DEFAULT                    0x00000000UL                         
01427 #define DMA_CHPRIC_CH10PRIC_DEFAULT                     (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) 
01428 #define DMA_CHPRIC_CH11PRIC                             (0x1UL << 11)                        
01429 #define _DMA_CHPRIC_CH11PRIC_SHIFT                      11                                   
01430 #define _DMA_CHPRIC_CH11PRIC_MASK                       0x800UL                              
01431 #define _DMA_CHPRIC_CH11PRIC_DEFAULT                    0x00000000UL                         
01432 #define DMA_CHPRIC_CH11PRIC_DEFAULT                     (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) 
01434 /* Bit fields for DMA ERRORC */
01435 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
01436 #define _DMA_ERRORC_MASK                                0x00000001UL                      
01437 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
01438 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
01439 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
01440 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
01441 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
01443 /* Bit fields for DMA CHREQSTATUS */
01444 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                   
01445 #define _DMA_CHREQSTATUS_MASK                           0x00000FFFUL                                   
01446 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                   
01447 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                              
01448 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                          
01449 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                   
01450 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)   
01451 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                   
01452 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                              
01453 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                          
01454 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                   
01455 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)   
01456 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                   
01457 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                              
01458 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                          
01459 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                   
01460 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)   
01461 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                   
01462 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                              
01463 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                          
01464 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                   
01465 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)   
01466 #define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                   
01467 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                              
01468 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                         
01469 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                   
01470 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)   
01471 #define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                   
01472 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                              
01473 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                         
01474 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                   
01475 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)   
01476 #define DMA_CHREQSTATUS_CH6REQSTATUS                    (0x1UL << 6)                                   
01477 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT             6                                              
01478 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK              0x40UL                                         
01479 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT           0x00000000UL                                   
01480 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)   
01481 #define DMA_CHREQSTATUS_CH7REQSTATUS                    (0x1UL << 7)                                   
01482 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT             7                                              
01483 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK              0x80UL                                         
01484 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT           0x00000000UL                                   
01485 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)   
01486 #define DMA_CHREQSTATUS_CH8REQSTATUS                    (0x1UL << 8)                                   
01487 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT             8                                              
01488 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK              0x100UL                                        
01489 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT           0x00000000UL                                   
01490 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8)   
01491 #define DMA_CHREQSTATUS_CH9REQSTATUS                    (0x1UL << 9)                                   
01492 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT             9                                              
01493 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK              0x200UL                                        
01494 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT           0x00000000UL                                   
01495 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9)   
01496 #define DMA_CHREQSTATUS_CH10REQSTATUS                   (0x1UL << 10)                                  
01497 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT            10                                             
01498 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK             0x400UL                                        
01499 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT          0x00000000UL                                   
01500 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT           (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) 
01501 #define DMA_CHREQSTATUS_CH11REQSTATUS                   (0x1UL << 11)                                  
01502 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT            11                                             
01503 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK             0x800UL                                        
01504 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT          0x00000000UL                                   
01505 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT           (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) 
01507 /* Bit fields for DMA CHSREQSTATUS */
01508 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                     
01509 #define _DMA_CHSREQSTATUS_MASK                          0x00000FFFUL                                     
01510 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                     
01511 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                                
01512 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                            
01513 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                     
01514 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)   
01515 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                     
01516 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                                
01517 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                            
01518 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                     
01519 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)   
01520 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                     
01521 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                                
01522 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                            
01523 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                     
01524 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)   
01525 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                     
01526 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                                
01527 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                            
01528 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                     
01529 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)   
01530 #define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                     
01531 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                                
01532 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                           
01533 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                     
01534 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)   
01535 #define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                     
01536 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                                
01537 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                           
01538 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                     
01539 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)   
01540 #define DMA_CHSREQSTATUS_CH6SREQSTATUS                  (0x1UL << 6)                                     
01541 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT           6                                                
01542 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK            0x40UL                                           
01543 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT         0x00000000UL                                     
01544 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)   
01545 #define DMA_CHSREQSTATUS_CH7SREQSTATUS                  (0x1UL << 7)                                     
01546 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT           7                                                
01547 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK            0x80UL                                           
01548 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT         0x00000000UL                                     
01549 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)   
01550 #define DMA_CHSREQSTATUS_CH8SREQSTATUS                  (0x1UL << 8)                                     
01551 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT           8                                                
01552 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK            0x100UL                                          
01553 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT         0x00000000UL                                     
01554 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8)   
01555 #define DMA_CHSREQSTATUS_CH9SREQSTATUS                  (0x1UL << 9)                                     
01556 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT           9                                                
01557 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK            0x200UL                                          
01558 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT         0x00000000UL                                     
01559 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9)   
01560 #define DMA_CHSREQSTATUS_CH10SREQSTATUS                 (0x1UL << 10)                                    
01561 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT          10                                               
01562 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK           0x400UL                                          
01563 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT        0x00000000UL                                     
01564 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT         (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) 
01565 #define DMA_CHSREQSTATUS_CH11SREQSTATUS                 (0x1UL << 11)                                    
01566 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT          11                                               
01567 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK           0x800UL                                          
01568 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT        0x00000000UL                                     
01569 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT         (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) 
01571 /* Bit fields for DMA IF */
01572 #define _DMA_IF_RESETVALUE                              0x00000000UL                     
01573 #define _DMA_IF_MASK                                    0x80000FFFUL                     
01574 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                     
01575 #define _DMA_IF_CH0DONE_SHIFT                           0                                
01576 #define _DMA_IF_CH0DONE_MASK                            0x1UL                            
01577 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                     
01578 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0)   
01579 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                     
01580 #define _DMA_IF_CH1DONE_SHIFT                           1                                
01581 #define _DMA_IF_CH1DONE_MASK                            0x2UL                            
01582 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                     
01583 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1)   
01584 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                     
01585 #define _DMA_IF_CH2DONE_SHIFT                           2                                
01586 #define _DMA_IF_CH2DONE_MASK                            0x4UL                            
01587 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                     
01588 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2)   
01589 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                     
01590 #define _DMA_IF_CH3DONE_SHIFT                           3                                
01591 #define _DMA_IF_CH3DONE_MASK                            0x8UL                            
01592 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                     
01593 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3)   
01594 #define DMA_IF_CH4DONE                                  (0x1UL << 4)                     
01595 #define _DMA_IF_CH4DONE_SHIFT                           4                                
01596 #define _DMA_IF_CH4DONE_MASK                            0x10UL                           
01597 #define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                     
01598 #define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4)   
01599 #define DMA_IF_CH5DONE                                  (0x1UL << 5)                     
01600 #define _DMA_IF_CH5DONE_SHIFT                           5                                
01601 #define _DMA_IF_CH5DONE_MASK                            0x20UL                           
01602 #define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                     
01603 #define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5)   
01604 #define DMA_IF_CH6DONE                                  (0x1UL << 6)                     
01605 #define _DMA_IF_CH6DONE_SHIFT                           6                                
01606 #define _DMA_IF_CH6DONE_MASK                            0x40UL                           
01607 #define _DMA_IF_CH6DONE_DEFAULT                         0x00000000UL                     
01608 #define DMA_IF_CH6DONE_DEFAULT                          (_DMA_IF_CH6DONE_DEFAULT << 6)   
01609 #define DMA_IF_CH7DONE                                  (0x1UL << 7)                     
01610 #define _DMA_IF_CH7DONE_SHIFT                           7                                
01611 #define _DMA_IF_CH7DONE_MASK                            0x80UL                           
01612 #define _DMA_IF_CH7DONE_DEFAULT                         0x00000000UL                     
01613 #define DMA_IF_CH7DONE_DEFAULT                          (_DMA_IF_CH7DONE_DEFAULT << 7)   
01614 #define DMA_IF_CH8DONE                                  (0x1UL << 8)                     
01615 #define _DMA_IF_CH8DONE_SHIFT                           8                                
01616 #define _DMA_IF_CH8DONE_MASK                            0x100UL                          
01617 #define _DMA_IF_CH8DONE_DEFAULT                         0x00000000UL                     
01618 #define DMA_IF_CH8DONE_DEFAULT                          (_DMA_IF_CH8DONE_DEFAULT << 8)   
01619 #define DMA_IF_CH9DONE                                  (0x1UL << 9)                     
01620 #define _DMA_IF_CH9DONE_SHIFT                           9                                
01621 #define _DMA_IF_CH9DONE_MASK                            0x200UL                          
01622 #define _DMA_IF_CH9DONE_DEFAULT                         0x00000000UL                     
01623 #define DMA_IF_CH9DONE_DEFAULT                          (_DMA_IF_CH9DONE_DEFAULT << 9)   
01624 #define DMA_IF_CH10DONE                                 (0x1UL << 10)                    
01625 #define _DMA_IF_CH10DONE_SHIFT                          10                               
01626 #define _DMA_IF_CH10DONE_MASK                           0x400UL                          
01627 #define _DMA_IF_CH10DONE_DEFAULT                        0x00000000UL                     
01628 #define DMA_IF_CH10DONE_DEFAULT                         (_DMA_IF_CH10DONE_DEFAULT << 10) 
01629 #define DMA_IF_CH11DONE                                 (0x1UL << 11)                    
01630 #define _DMA_IF_CH11DONE_SHIFT                          11                               
01631 #define _DMA_IF_CH11DONE_MASK                           0x800UL                          
01632 #define _DMA_IF_CH11DONE_DEFAULT                        0x00000000UL                     
01633 #define DMA_IF_CH11DONE_DEFAULT                         (_DMA_IF_CH11DONE_DEFAULT << 11) 
01634 #define DMA_IF_ERR                                      (0x1UL << 31)                    
01635 #define _DMA_IF_ERR_SHIFT                               31                               
01636 #define _DMA_IF_ERR_MASK                                0x80000000UL                     
01637 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                     
01638 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)      
01640 /* Bit fields for DMA IFS */
01641 #define _DMA_IFS_RESETVALUE                             0x00000000UL                      
01642 #define _DMA_IFS_MASK                                   0x80000FFFUL                      
01643 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                      
01644 #define _DMA_IFS_CH0DONE_SHIFT                          0                                 
01645 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                             
01646 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                      
01647 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0)   
01648 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                      
01649 #define _DMA_IFS_CH1DONE_SHIFT                          1                                 
01650 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                             
01651 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                      
01652 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1)   
01653 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                      
01654 #define _DMA_IFS_CH2DONE_SHIFT                          2                                 
01655 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                             
01656 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                      
01657 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2)   
01658 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                      
01659 #define _DMA_IFS_CH3DONE_SHIFT                          3                                 
01660 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                             
01661 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                      
01662 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3)   
01663 #define DMA_IFS_CH4DONE                                 (0x1UL << 4)                      
01664 #define _DMA_IFS_CH4DONE_SHIFT                          4                                 
01665 #define _DMA_IFS_CH4DONE_MASK                           0x10UL                            
01666 #define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                      
01667 #define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4)   
01668 #define DMA_IFS_CH5DONE                                 (0x1UL << 5)                      
01669 #define _DMA_IFS_CH5DONE_SHIFT                          5                                 
01670 #define _DMA_IFS_CH5DONE_MASK                           0x20UL                            
01671 #define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                      
01672 #define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5)   
01673 #define DMA_IFS_CH6DONE                                 (0x1UL << 6)                      
01674 #define _DMA_IFS_CH6DONE_SHIFT                          6                                 
01675 #define _DMA_IFS_CH6DONE_MASK                           0x40UL                            
01676 #define _DMA_IFS_CH6DONE_DEFAULT                        0x00000000UL                      
01677 #define DMA_IFS_CH6DONE_DEFAULT                         (_DMA_IFS_CH6DONE_DEFAULT << 6)   
01678 #define DMA_IFS_CH7DONE                                 (0x1UL << 7)                      
01679 #define _DMA_IFS_CH7DONE_SHIFT                          7                                 
01680 #define _DMA_IFS_CH7DONE_MASK                           0x80UL                            
01681 #define _DMA_IFS_CH7DONE_DEFAULT                        0x00000000UL                      
01682 #define DMA_IFS_CH7DONE_DEFAULT                         (_DMA_IFS_CH7DONE_DEFAULT << 7)   
01683 #define DMA_IFS_CH8DONE                                 (0x1UL << 8)                      
01684 #define _DMA_IFS_CH8DONE_SHIFT                          8                                 
01685 #define _DMA_IFS_CH8DONE_MASK                           0x100UL                           
01686 #define _DMA_IFS_CH8DONE_DEFAULT                        0x00000000UL                      
01687 #define DMA_IFS_CH8DONE_DEFAULT                         (_DMA_IFS_CH8DONE_DEFAULT << 8)   
01688 #define DMA_IFS_CH9DONE                                 (0x1UL << 9)                      
01689 #define _DMA_IFS_CH9DONE_SHIFT                          9                                 
01690 #define _DMA_IFS_CH9DONE_MASK                           0x200UL                           
01691 #define _DMA_IFS_CH9DONE_DEFAULT                        0x00000000UL                      
01692 #define DMA_IFS_CH9DONE_DEFAULT                         (_DMA_IFS_CH9DONE_DEFAULT << 9)   
01693 #define DMA_IFS_CH10DONE                                (0x1UL << 10)                     
01694 #define _DMA_IFS_CH10DONE_SHIFT                         10                                
01695 #define _DMA_IFS_CH10DONE_MASK                          0x400UL                           
01696 #define _DMA_IFS_CH10DONE_DEFAULT                       0x00000000UL                      
01697 #define DMA_IFS_CH10DONE_DEFAULT                        (_DMA_IFS_CH10DONE_DEFAULT << 10) 
01698 #define DMA_IFS_CH11DONE                                (0x1UL << 11)                     
01699 #define _DMA_IFS_CH11DONE_SHIFT                         11                                
01700 #define _DMA_IFS_CH11DONE_MASK                          0x800UL                           
01701 #define _DMA_IFS_CH11DONE_DEFAULT                       0x00000000UL                      
01702 #define DMA_IFS_CH11DONE_DEFAULT                        (_DMA_IFS_CH11DONE_DEFAULT << 11) 
01703 #define DMA_IFS_ERR                                     (0x1UL << 31)                     
01704 #define _DMA_IFS_ERR_SHIFT                              31                                
01705 #define _DMA_IFS_ERR_MASK                               0x80000000UL                      
01706 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                      
01707 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)      
01709 /* Bit fields for DMA IFC */
01710 #define _DMA_IFC_RESETVALUE                             0x00000000UL                      
01711 #define _DMA_IFC_MASK                                   0x80000FFFUL                      
01712 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                      
01713 #define _DMA_IFC_CH0DONE_SHIFT                          0                                 
01714 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                             
01715 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                      
01716 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0)   
01717 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                      
01718 #define _DMA_IFC_CH1DONE_SHIFT                          1                                 
01719 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                             
01720 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                      
01721 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1)   
01722 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                      
01723 #define _DMA_IFC_CH2DONE_SHIFT                          2                                 
01724 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                             
01725 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                      
01726 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2)   
01727 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                      
01728 #define _DMA_IFC_CH3DONE_SHIFT                          3                                 
01729 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                             
01730 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                      
01731 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3)   
01732 #define DMA_IFC_CH4DONE                                 (0x1UL << 4)                      
01733 #define _DMA_IFC_CH4DONE_SHIFT                          4                                 
01734 #define _DMA_IFC_CH4DONE_MASK                           0x10UL                            
01735 #define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                      
01736 #define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4)   
01737 #define DMA_IFC_CH5DONE                                 (0x1UL << 5)                      
01738 #define _DMA_IFC_CH5DONE_SHIFT                          5                                 
01739 #define _DMA_IFC_CH5DONE_MASK                           0x20UL                            
01740 #define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                      
01741 #define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5)   
01742 #define DMA_IFC_CH6DONE                                 (0x1UL << 6)                      
01743 #define _DMA_IFC_CH6DONE_SHIFT                          6                                 
01744 #define _DMA_IFC_CH6DONE_MASK                           0x40UL                            
01745 #define _DMA_IFC_CH6DONE_DEFAULT                        0x00000000UL                      
01746 #define DMA_IFC_CH6DONE_DEFAULT                         (_DMA_IFC_CH6DONE_DEFAULT << 6)   
01747 #define DMA_IFC_CH7DONE                                 (0x1UL << 7)                      
01748 #define _DMA_IFC_CH7DONE_SHIFT                          7                                 
01749 #define _DMA_IFC_CH7DONE_MASK                           0x80UL                            
01750 #define _DMA_IFC_CH7DONE_DEFAULT                        0x00000000UL                      
01751 #define DMA_IFC_CH7DONE_DEFAULT                         (_DMA_IFC_CH7DONE_DEFAULT << 7)   
01752 #define DMA_IFC_CH8DONE                                 (0x1UL << 8)                      
01753 #define _DMA_IFC_CH8DONE_SHIFT                          8                                 
01754 #define _DMA_IFC_CH8DONE_MASK                           0x100UL                           
01755 #define _DMA_IFC_CH8DONE_DEFAULT                        0x00000000UL                      
01756 #define DMA_IFC_CH8DONE_DEFAULT                         (_DMA_IFC_CH8DONE_DEFAULT << 8)   
01757 #define DMA_IFC_CH9DONE                                 (0x1UL << 9)                      
01758 #define _DMA_IFC_CH9DONE_SHIFT                          9                                 
01759 #define _DMA_IFC_CH9DONE_MASK                           0x200UL                           
01760 #define _DMA_IFC_CH9DONE_DEFAULT                        0x00000000UL                      
01761 #define DMA_IFC_CH9DONE_DEFAULT                         (_DMA_IFC_CH9DONE_DEFAULT << 9)   
01762 #define DMA_IFC_CH10DONE                                (0x1UL << 10)                     
01763 #define _DMA_IFC_CH10DONE_SHIFT                         10                                
01764 #define _DMA_IFC_CH10DONE_MASK                          0x400UL                           
01765 #define _DMA_IFC_CH10DONE_DEFAULT                       0x00000000UL                      
01766 #define DMA_IFC_CH10DONE_DEFAULT                        (_DMA_IFC_CH10DONE_DEFAULT << 10) 
01767 #define DMA_IFC_CH11DONE                                (0x1UL << 11)                     
01768 #define _DMA_IFC_CH11DONE_SHIFT                         11                                
01769 #define _DMA_IFC_CH11DONE_MASK                          0x800UL                           
01770 #define _DMA_IFC_CH11DONE_DEFAULT                       0x00000000UL                      
01771 #define DMA_IFC_CH11DONE_DEFAULT                        (_DMA_IFC_CH11DONE_DEFAULT << 11) 
01772 #define DMA_IFC_ERR                                     (0x1UL << 31)                     
01773 #define _DMA_IFC_ERR_SHIFT                              31                                
01774 #define _DMA_IFC_ERR_MASK                               0x80000000UL                      
01775 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                      
01776 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)      
01778 /* Bit fields for DMA IEN */
01779 #define _DMA_IEN_RESETVALUE                             0x00000000UL                      
01780 #define _DMA_IEN_MASK                                   0x80000FFFUL                      
01781 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                      
01782 #define _DMA_IEN_CH0DONE_SHIFT                          0                                 
01783 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                             
01784 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                      
01785 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0)   
01786 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                      
01787 #define _DMA_IEN_CH1DONE_SHIFT                          1                                 
01788 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                             
01789 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                      
01790 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1)   
01791 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                      
01792 #define _DMA_IEN_CH2DONE_SHIFT                          2                                 
01793 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                             
01794 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                      
01795 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2)   
01796 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                      
01797 #define _DMA_IEN_CH3DONE_SHIFT                          3                                 
01798 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                             
01799 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                      
01800 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3)   
01801 #define DMA_IEN_CH4DONE                                 (0x1UL << 4)                      
01802 #define _DMA_IEN_CH4DONE_SHIFT                          4                                 
01803 #define _DMA_IEN_CH4DONE_MASK                           0x10UL                            
01804 #define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                      
01805 #define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4)   
01806 #define DMA_IEN_CH5DONE                                 (0x1UL << 5)                      
01807 #define _DMA_IEN_CH5DONE_SHIFT                          5                                 
01808 #define _DMA_IEN_CH5DONE_MASK                           0x20UL                            
01809 #define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                      
01810 #define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5)   
01811 #define DMA_IEN_CH6DONE                                 (0x1UL << 6)                      
01812 #define _DMA_IEN_CH6DONE_SHIFT                          6                                 
01813 #define _DMA_IEN_CH6DONE_MASK                           0x40UL                            
01814 #define _DMA_IEN_CH6DONE_DEFAULT                        0x00000000UL                      
01815 #define DMA_IEN_CH6DONE_DEFAULT                         (_DMA_IEN_CH6DONE_DEFAULT << 6)   
01816 #define DMA_IEN_CH7DONE                                 (0x1UL << 7)                      
01817 #define _DMA_IEN_CH7DONE_SHIFT                          7                                 
01818 #define _DMA_IEN_CH7DONE_MASK                           0x80UL                            
01819 #define _DMA_IEN_CH7DONE_DEFAULT                        0x00000000UL                      
01820 #define DMA_IEN_CH7DONE_DEFAULT                         (_DMA_IEN_CH7DONE_DEFAULT << 7)   
01821 #define DMA_IEN_CH8DONE                                 (0x1UL << 8)                      
01822 #define _DMA_IEN_CH8DONE_SHIFT                          8                                 
01823 #define _DMA_IEN_CH8DONE_MASK                           0x100UL                           
01824 #define _DMA_IEN_CH8DONE_DEFAULT                        0x00000000UL                      
01825 #define DMA_IEN_CH8DONE_DEFAULT                         (_DMA_IEN_CH8DONE_DEFAULT << 8)   
01826 #define DMA_IEN_CH9DONE                                 (0x1UL << 9)                      
01827 #define _DMA_IEN_CH9DONE_SHIFT                          9                                 
01828 #define _DMA_IEN_CH9DONE_MASK                           0x200UL                           
01829 #define _DMA_IEN_CH9DONE_DEFAULT                        0x00000000UL                      
01830 #define DMA_IEN_CH9DONE_DEFAULT                         (_DMA_IEN_CH9DONE_DEFAULT << 9)   
01831 #define DMA_IEN_CH10DONE                                (0x1UL << 10)                     
01832 #define _DMA_IEN_CH10DONE_SHIFT                         10                                
01833 #define _DMA_IEN_CH10DONE_MASK                          0x400UL                           
01834 #define _DMA_IEN_CH10DONE_DEFAULT                       0x00000000UL                      
01835 #define DMA_IEN_CH10DONE_DEFAULT                        (_DMA_IEN_CH10DONE_DEFAULT << 10) 
01836 #define DMA_IEN_CH11DONE                                (0x1UL << 11)                     
01837 #define _DMA_IEN_CH11DONE_SHIFT                         11                                
01838 #define _DMA_IEN_CH11DONE_MASK                          0x800UL                           
01839 #define _DMA_IEN_CH11DONE_DEFAULT                       0x00000000UL                      
01840 #define DMA_IEN_CH11DONE_DEFAULT                        (_DMA_IEN_CH11DONE_DEFAULT << 11) 
01841 #define DMA_IEN_ERR                                     (0x1UL << 31)                     
01842 #define _DMA_IEN_ERR_SHIFT                              31                                
01843 #define _DMA_IEN_ERR_MASK                               0x80000000UL                      
01844 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                      
01845 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)      
01847 /* Bit fields for DMA CTRL */
01848 #define _DMA_CTRL_RESETVALUE                            0x00000000UL                      
01849 #define _DMA_CTRL_MASK                                  0x00000003UL                      
01850 #define DMA_CTRL_DESCRECT                               (0x1UL << 0)                      
01851 #define _DMA_CTRL_DESCRECT_SHIFT                        0                                 
01852 #define _DMA_CTRL_DESCRECT_MASK                         0x1UL                             
01853 #define _DMA_CTRL_DESCRECT_DEFAULT                      0x00000000UL                      
01854 #define DMA_CTRL_DESCRECT_DEFAULT                       (_DMA_CTRL_DESCRECT_DEFAULT << 0) 
01855 #define DMA_CTRL_PRDU                                   (0x1UL << 1)                      
01856 #define _DMA_CTRL_PRDU_SHIFT                            1                                 
01857 #define _DMA_CTRL_PRDU_MASK                             0x2UL                             
01858 #define _DMA_CTRL_PRDU_DEFAULT                          0x00000000UL                      
01859 #define DMA_CTRL_PRDU_DEFAULT                           (_DMA_CTRL_PRDU_DEFAULT << 1)     
01861 /* Bit fields for DMA RDS */
01862 #define _DMA_RDS_RESETVALUE                             0x00000000UL                     
01863 #define _DMA_RDS_MASK                                   0x00000FFFUL                     
01864 #define DMA_RDS_RDSCH0                                  (0x1UL << 0)                     
01865 #define _DMA_RDS_RDSCH0_SHIFT                           0                                
01866 #define _DMA_RDS_RDSCH0_MASK                            0x1UL                            
01867 #define _DMA_RDS_RDSCH0_DEFAULT                         0x00000000UL                     
01868 #define DMA_RDS_RDSCH0_DEFAULT                          (_DMA_RDS_RDSCH0_DEFAULT << 0)   
01869 #define DMA_RDS_RDSCH1                                  (0x1UL << 1)                     
01870 #define _DMA_RDS_RDSCH1_SHIFT                           1                                
01871 #define _DMA_RDS_RDSCH1_MASK                            0x2UL                            
01872 #define _DMA_RDS_RDSCH1_DEFAULT                         0x00000000UL                     
01873 #define DMA_RDS_RDSCH1_DEFAULT                          (_DMA_RDS_RDSCH1_DEFAULT << 1)   
01874 #define DMA_RDS_RDSCH2                                  (0x1UL << 2)                     
01875 #define _DMA_RDS_RDSCH2_SHIFT                           2                                
01876 #define _DMA_RDS_RDSCH2_MASK                            0x4UL                            
01877 #define _DMA_RDS_RDSCH2_DEFAULT                         0x00000000UL                     
01878 #define DMA_RDS_RDSCH2_DEFAULT                          (_DMA_RDS_RDSCH2_DEFAULT << 2)   
01879 #define DMA_RDS_RDSCH3                                  (0x1UL << 3)                     
01880 #define _DMA_RDS_RDSCH3_SHIFT                           3                                
01881 #define _DMA_RDS_RDSCH3_MASK                            0x8UL                            
01882 #define _DMA_RDS_RDSCH3_DEFAULT                         0x00000000UL                     
01883 #define DMA_RDS_RDSCH3_DEFAULT                          (_DMA_RDS_RDSCH3_DEFAULT << 3)   
01884 #define DMA_RDS_RDSCH4                                  (0x1UL << 4)                     
01885 #define _DMA_RDS_RDSCH4_SHIFT                           4                                
01886 #define _DMA_RDS_RDSCH4_MASK                            0x10UL                           
01887 #define _DMA_RDS_RDSCH4_DEFAULT                         0x00000000UL                     
01888 #define DMA_RDS_RDSCH4_DEFAULT                          (_DMA_RDS_RDSCH4_DEFAULT << 4)   
01889 #define DMA_RDS_RDSCH5                                  (0x1UL << 5)                     
01890 #define _DMA_RDS_RDSCH5_SHIFT                           5                                
01891 #define _DMA_RDS_RDSCH5_MASK                            0x20UL                           
01892 #define _DMA_RDS_RDSCH5_DEFAULT                         0x00000000UL                     
01893 #define DMA_RDS_RDSCH5_DEFAULT                          (_DMA_RDS_RDSCH5_DEFAULT << 5)   
01894 #define DMA_RDS_RDSCH6                                  (0x1UL << 6)                     
01895 #define _DMA_RDS_RDSCH6_SHIFT                           6                                
01896 #define _DMA_RDS_RDSCH6_MASK                            0x40UL                           
01897 #define _DMA_RDS_RDSCH6_DEFAULT                         0x00000000UL                     
01898 #define DMA_RDS_RDSCH6_DEFAULT                          (_DMA_RDS_RDSCH6_DEFAULT << 6)   
01899 #define DMA_RDS_RDSCH7                                  (0x1UL << 7)                     
01900 #define _DMA_RDS_RDSCH7_SHIFT                           7                                
01901 #define _DMA_RDS_RDSCH7_MASK                            0x80UL                           
01902 #define _DMA_RDS_RDSCH7_DEFAULT                         0x00000000UL                     
01903 #define DMA_RDS_RDSCH7_DEFAULT                          (_DMA_RDS_RDSCH7_DEFAULT << 7)   
01904 #define DMA_RDS_RDSCH8                                  (0x1UL << 8)                     
01905 #define _DMA_RDS_RDSCH8_SHIFT                           8                                
01906 #define _DMA_RDS_RDSCH8_MASK                            0x100UL                          
01907 #define _DMA_RDS_RDSCH8_DEFAULT                         0x00000000UL                     
01908 #define DMA_RDS_RDSCH8_DEFAULT                          (_DMA_RDS_RDSCH8_DEFAULT << 8)   
01909 #define DMA_RDS_RDSCH9                                  (0x1UL << 9)                     
01910 #define _DMA_RDS_RDSCH9_SHIFT                           9                                
01911 #define _DMA_RDS_RDSCH9_MASK                            0x200UL                          
01912 #define _DMA_RDS_RDSCH9_DEFAULT                         0x00000000UL                     
01913 #define DMA_RDS_RDSCH9_DEFAULT                          (_DMA_RDS_RDSCH9_DEFAULT << 9)   
01914 #define DMA_RDS_RDSCH10                                 (0x1UL << 10)                    
01915 #define _DMA_RDS_RDSCH10_SHIFT                          10                               
01916 #define _DMA_RDS_RDSCH10_MASK                           0x400UL                          
01917 #define _DMA_RDS_RDSCH10_DEFAULT                        0x00000000UL                     
01918 #define DMA_RDS_RDSCH10_DEFAULT                         (_DMA_RDS_RDSCH10_DEFAULT << 10) 
01919 #define DMA_RDS_RDSCH11                                 (0x1UL << 11)                    
01920 #define _DMA_RDS_RDSCH11_SHIFT                          11                               
01921 #define _DMA_RDS_RDSCH11_MASK                           0x800UL                          
01922 #define _DMA_RDS_RDSCH11_DEFAULT                        0x00000000UL                     
01923 #define DMA_RDS_RDSCH11_DEFAULT                         (_DMA_RDS_RDSCH11_DEFAULT << 11) 
01925 /* Bit fields for DMA LOOP0 */
01926 #define _DMA_LOOP0_RESETVALUE                           0x00000000UL                    
01927 #define _DMA_LOOP0_MASK                                 0x000103FFUL                    
01928 #define _DMA_LOOP0_WIDTH_SHIFT                          0                               
01929 #define _DMA_LOOP0_WIDTH_MASK                           0x3FFUL                         
01930 #define _DMA_LOOP0_WIDTH_DEFAULT                        0x00000000UL                    
01931 #define DMA_LOOP0_WIDTH_DEFAULT                         (_DMA_LOOP0_WIDTH_DEFAULT << 0) 
01932 #define DMA_LOOP0_EN                                    (0x1UL << 16)                   
01933 #define _DMA_LOOP0_EN_SHIFT                             16                              
01934 #define _DMA_LOOP0_EN_MASK                              0x10000UL                       
01935 #define _DMA_LOOP0_EN_DEFAULT                           0x00000000UL                    
01936 #define DMA_LOOP0_EN_DEFAULT                            (_DMA_LOOP0_EN_DEFAULT << 16)   
01938 /* Bit fields for DMA LOOP1 */
01939 #define _DMA_LOOP1_RESETVALUE                           0x00000000UL                    
01940 #define _DMA_LOOP1_MASK                                 0x000103FFUL                    
01941 #define _DMA_LOOP1_WIDTH_SHIFT                          0                               
01942 #define _DMA_LOOP1_WIDTH_MASK                           0x3FFUL                         
01943 #define _DMA_LOOP1_WIDTH_DEFAULT                        0x00000000UL                    
01944 #define DMA_LOOP1_WIDTH_DEFAULT                         (_DMA_LOOP1_WIDTH_DEFAULT << 0) 
01945 #define DMA_LOOP1_EN                                    (0x1UL << 16)                   
01946 #define _DMA_LOOP1_EN_SHIFT                             16                              
01947 #define _DMA_LOOP1_EN_MASK                              0x10000UL                       
01948 #define _DMA_LOOP1_EN_DEFAULT                           0x00000000UL                    
01949 #define DMA_LOOP1_EN_DEFAULT                            (_DMA_LOOP1_EN_DEFAULT << 16)   
01951 /* Bit fields for DMA RECT0 */
01952 #define _DMA_RECT0_RESETVALUE                           0x00000000UL                         
01953 #define _DMA_RECT0_MASK                                 0xFFFFFFFFUL                         
01954 #define _DMA_RECT0_HEIGHT_SHIFT                         0                                    
01955 #define _DMA_RECT0_HEIGHT_MASK                          0x3FFUL                              
01956 #define _DMA_RECT0_HEIGHT_DEFAULT                       0x00000000UL                         
01957 #define DMA_RECT0_HEIGHT_DEFAULT                        (_DMA_RECT0_HEIGHT_DEFAULT << 0)     
01958 #define _DMA_RECT0_SRCSTRIDE_SHIFT                      10                                   
01959 #define _DMA_RECT0_SRCSTRIDE_MASK                       0x1FFC00UL                           
01960 #define _DMA_RECT0_SRCSTRIDE_DEFAULT                    0x00000000UL                         
01961 #define DMA_RECT0_SRCSTRIDE_DEFAULT                     (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) 
01962 #define _DMA_RECT0_DSTSTRIDE_SHIFT                      21                                   
01963 #define _DMA_RECT0_DSTSTRIDE_MASK                       0xFFE00000UL                         
01964 #define _DMA_RECT0_DSTSTRIDE_DEFAULT                    0x00000000UL                         
01965 #define DMA_RECT0_DSTSTRIDE_DEFAULT                     (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) 
01967 /* Bit fields for DMA CH_CTRL */
01968 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                                  
01969 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                                  
01970 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                             
01971 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                         
01972 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE                  0x00000000UL                                  
01973 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0                     0x00000000UL                                  
01974 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                                  
01975 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                                  
01976 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV               0x00000000UL                                  
01977 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                                  
01978 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV              0x00000000UL                                  
01979 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                                  
01980 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV                 0x00000000UL                                  
01981 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                                  
01982 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                                  
01983 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF                  0x00000000UL                                  
01984 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF                  0x00000000UL                                  
01985 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                                  
01986 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR                   0x00000000UL                                  
01987 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV             0x00000000UL                                  
01988 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN                    0x00000001UL                                  
01989 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1                     0x00000001UL                                  
01990 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                                  
01991 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                                  
01992 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL                  0x00000001UL                                  
01993 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                                  
01994 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL                 0x00000001UL                                  
01995 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                                  
01996 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL                    0x00000001UL                                  
01997 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                                  
01998 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                                  
01999 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0                   0x00000001UL                                  
02000 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0                   0x00000001UL                                  
02001 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR                0x00000001UL                                  
02002 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                                  
02003 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                                  
02004 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY               0x00000002UL                                  
02005 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                                  
02006 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY              0x00000002UL                                  
02007 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                                  
02008 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                                  
02009 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1                   0x00000002UL                                  
02010 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1                   0x00000002UL                                  
02011 #define _DMA_CH_CTRL_SIGSEL_AESDATARD                   0x00000002UL                                  
02012 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT          0x00000003UL                                  
02013 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT          0x00000003UL                                  
02014 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                                  
02015 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                                  
02016 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2                   0x00000003UL                                  
02017 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2                   0x00000003UL                                  
02018 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR                    0x00000003UL                                  
02019 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT             0x00000004UL                                  
02020 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT             0x00000004UL                                  
02021 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE                   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)         
02022 #define DMA_CH_CTRL_SIGSEL_DAC0CH0                      (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)            
02023 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)      
02024 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)      
02025 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)      
02026 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)     
02027 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)     
02028 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)        
02029 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0)        
02030 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)         
02031 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)         
02032 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)         
02033 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0)         
02034 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)           
02035 #define DMA_CH_CTRL_SIGSEL_AESDATAWR                    (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)          
02036 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV              (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0)    
02037 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN                     (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)           
02038 #define DMA_CH_CTRL_SIGSEL_DAC0CH1                      (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)            
02039 #define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)         
02040 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)         
02041 #define DMA_CH_CTRL_SIGSEL_USART2TXBL                   (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)         
02042 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)        
02043 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)        
02044 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)           
02045 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0)           
02046 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)          
02047 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)          
02048 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)          
02049 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0)          
02050 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR                 (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)       
02051 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)      
02052 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)      
02053 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)      
02054 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)     
02055 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)     
02056 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)          
02057 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)          
02058 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)          
02059 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0)          
02060 #define DMA_CH_CTRL_SIGSEL_AESDATARD                    (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)          
02061 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) 
02062 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) 
02063 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)          
02064 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)          
02065 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)          
02066 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0)          
02067 #define DMA_CH_CTRL_SIGSEL_AESKEYWR                     (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)           
02068 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)    
02069 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0)    
02070 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                            
02071 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                    
02072 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                                  
02073 #define _DMA_CH_CTRL_SOURCESEL_ADC0                     0x00000008UL                                  
02074 #define _DMA_CH_CTRL_SOURCESEL_DAC0                     0x0000000AUL                                  
02075 #define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                                  
02076 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                                  
02077 #define _DMA_CH_CTRL_SOURCESEL_USART2                   0x0000000EUL                                  
02078 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                                  
02079 #define _DMA_CH_CTRL_SOURCESEL_LEUART1                  0x00000011UL                                  
02080 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                                  
02081 #define _DMA_CH_CTRL_SOURCESEL_I2C1                     0x00000015UL                                  
02082 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                                  
02083 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                                  
02084 #define _DMA_CH_CTRL_SOURCESEL_TIMER2                   0x0000001AUL                                  
02085 #define _DMA_CH_CTRL_SOURCESEL_TIMER3                   0x0000001BUL                                  
02086 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                                  
02087 #define _DMA_CH_CTRL_SOURCESEL_AES                      0x00000031UL                                  
02088 #define _DMA_CH_CTRL_SOURCESEL_LESENSE                  0x00000032UL                                  
02089 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)           
02090 #define DMA_CH_CTRL_SOURCESEL_ADC0                      (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)           
02091 #define DMA_CH_CTRL_SOURCESEL_DAC0                      (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)           
02092 #define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)         
02093 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)         
02094 #define DMA_CH_CTRL_SOURCESEL_USART2                    (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)         
02095 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)        
02096 #define DMA_CH_CTRL_SOURCESEL_LEUART1                   (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)        
02097 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)           
02098 #define DMA_CH_CTRL_SOURCESEL_I2C1                      (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16)           
02099 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)         
02100 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)         
02101 #define DMA_CH_CTRL_SOURCESEL_TIMER2                    (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)         
02102 #define DMA_CH_CTRL_SOURCESEL_TIMER3                    (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16)         
02103 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)            
02104 #define DMA_CH_CTRL_SOURCESEL_AES                       (_DMA_CH_CTRL_SOURCESEL_AES << 16)            
02105 #define DMA_CH_CTRL_SOURCESEL_LESENSE                   (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16)        
02111 /**************************************************************************/
02116 /* Bit fields for CMU CTRL */
02117 #define _CMU_CTRL_RESETVALUE                        0x000C062CUL                                
02118 #define _CMU_CTRL_MASK                              0x53FFFEEFUL                                
02119 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           
02120 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       
02121 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                
02122 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                                
02123 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                                
02124 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                                
02125 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)           
02126 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)              
02127 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)         
02128 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)         
02129 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                           
02130 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                       
02131 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                                
02132 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                                
02133 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                                
02134 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                                
02135 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                                
02136 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)          
02137 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)          
02138 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)          
02139 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)          
02140 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)         
02141 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                           
02142 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                      
02143 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                                
02144 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ         0x00000001UL                                
02145 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ        0x00000003UL                                
02146 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)         
02147 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ          (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)  
02148 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ         (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) 
02149 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                                
02150 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                           
02151 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                      
02152 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                                
02153 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)    
02154 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                           
02155 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                     
02156 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                                
02157 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                                
02158 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                                
02159 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                                
02160 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                                
02161 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)        
02162 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)      
02163 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)       
02164 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)        
02165 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)      
02166 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                          
02167 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                    
02168 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                                
02169 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                                
02170 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                                
02171 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                                
02172 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)          
02173 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)             
02174 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)        
02175 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)        
02176 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                               
02177 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                          
02178 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                    
02179 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                                
02180 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                                
02181 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                                
02182 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)         
02183 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)         
02184 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)        
02185 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                          
02186 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                   
02187 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                                
02188 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)          
02189 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                               
02190 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                          
02191 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                   
02192 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                                
02193 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)        
02194 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                          
02195 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                   
02196 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                                
02197 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                                
02198 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                                
02199 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                                
02200 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                                
02201 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)       
02202 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)      
02203 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)     
02204 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)       
02205 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)     
02206 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                          
02207 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                                  
02208 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                                
02209 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                                
02210 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                                
02211 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                                
02212 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                                
02213 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                                
02214 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                                
02215 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                                
02216 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                                
02217 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)        
02218 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)          
02219 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)           
02220 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)         
02221 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)         
02222 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)         
02223 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)        
02224 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         
02225 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       
02226 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          
02227 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 
02228 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                
02229 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                
02230 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                
02231 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                                
02232 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                                
02233 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                                
02234 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                                
02235 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                                
02236 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                                
02237 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)        
02238 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)          
02239 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)           
02240 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)          
02241 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)          
02242 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)          
02243 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)         
02244 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)         
02245 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)      
02246 #define CMU_CTRL_DBGCLK                             (0x1UL << 28)                               
02247 #define _CMU_CTRL_DBGCLK_SHIFT                      28                                          
02248 #define _CMU_CTRL_DBGCLK_MASK                       0x10000000UL                                
02249 #define _CMU_CTRL_DBGCLK_DEFAULT                    0x00000000UL                                
02250 #define _CMU_CTRL_DBGCLK_AUXHFRCO                   0x00000000UL                                
02251 #define _CMU_CTRL_DBGCLK_HFCLK                      0x00000001UL                                
02252 #define CMU_CTRL_DBGCLK_DEFAULT                     (_CMU_CTRL_DBGCLK_DEFAULT << 28)            
02253 #define CMU_CTRL_DBGCLK_AUXHFRCO                    (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)           
02254 #define CMU_CTRL_DBGCLK_HFCLK                       (_CMU_CTRL_DBGCLK_HFCLK << 28)              
02255 #define CMU_CTRL_HFLE                               (0x1UL << 30)                               
02256 #define _CMU_CTRL_HFLE_SHIFT                        30                                          
02257 #define _CMU_CTRL_HFLE_MASK                         0x40000000UL                                
02258 #define _CMU_CTRL_HFLE_DEFAULT                      0x00000000UL                                
02259 #define CMU_CTRL_HFLE_DEFAULT                       (_CMU_CTRL_HFLE_DEFAULT << 30)              
02261 /* Bit fields for CMU HFCORECLKDIV */
02262 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
02263 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
02264 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
02265 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
02266 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
02267 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
02268 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
02269 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
02270 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
02271 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
02272 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
02273 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
02274 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
02275 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
02276 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
02277 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
02278 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
02279 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
02280 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
02281 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
02282 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
02283 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
02284 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
02285 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
02286 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
02287 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
02288 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
02289 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
02290 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
02291 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
02292 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
02293 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
02294 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
02295 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
02296 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
02298 /* Bit fields for CMU HFPERCLKDIV */
02299 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
02300 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
02301 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
02302 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
02303 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
02304 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
02305 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
02306 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
02307 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
02308 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
02309 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
02310 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
02311 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
02312 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
02313 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
02314 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
02315 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
02316 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
02317 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
02318 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
02319 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
02320 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
02321 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
02322 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
02323 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
02324 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
02325 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
02326 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
02327 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
02328 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
02329 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
02331 /* Bit fields for CMU HFRCOCTRL */
02332 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
02333 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
02334 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
02335 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
02336 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
02337 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
02338 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
02339 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
02340 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
02341 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
02342 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
02343 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
02344 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
02345 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
02346 #define _CMU_HFRCOCTRL_BAND_28MHZ                   0x00000005UL                           
02347 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
02348 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
02349 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
02350 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
02351 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
02352 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
02353 #define CMU_HFRCOCTRL_BAND_28MHZ                    (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       
02354 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
02355 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
02356 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
02357 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
02359 /* Bit fields for CMU LFRCOCTRL */
02360 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
02361 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
02362 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
02363 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
02364 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
02365 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
02367 /* Bit fields for CMU AUXHFRCOCTRL */
02368 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
02369 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
02370 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
02371 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
02372 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
02373 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
02374 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
02375 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
02376 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
02377 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
02378 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
02379 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
02380 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
02381 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ                0x00000006UL                            
02382 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
02383 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
02384 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
02385 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
02386 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
02387 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
02388 #define CMU_AUXHFRCOCTRL_BAND_28MHZ                 (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)     
02389 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
02391 /* Bit fields for CMU CALCTRL */
02392 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
02393 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
02394 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
02395 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
02396 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
02397 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
02398 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
02399 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
02400 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
02401 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
02402 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
02403 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
02404 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
02405 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
02406 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
02407 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
02408 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
02409 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
02410 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
02411 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
02412 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
02413 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
02414 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
02415 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
02416 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
02417 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
02418 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
02419 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
02420 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
02421 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
02422 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
02423 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
02424 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
02425 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
02426 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
02427 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
02428 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
02430 /* Bit fields for CMU CALCNT */
02431 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
02432 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
02433 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
02434 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
02435 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
02436 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
02438 /* Bit fields for CMU OSCENCMD */
02439 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
02440 #define _CMU_OSCENCMD_MASK                          0x000003FFUL                             
02441 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
02442 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
02443 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
02444 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
02445 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
02446 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
02447 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
02448 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
02449 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
02450 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
02451 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
02452 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
02453 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
02454 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
02455 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
02456 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
02457 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
02458 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
02459 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
02460 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
02461 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
02462 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
02463 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
02464 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
02465 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
02466 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
02467 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
02468 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
02469 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
02470 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
02471 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
02472 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
02473 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
02474 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
02475 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
02476 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
02477 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
02478 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
02479 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
02480 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
02481 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
02482 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
02483 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
02484 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
02485 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
02486 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
02487 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
02488 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
02489 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
02490 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
02492 /* Bit fields for CMU CMD */
02493 #define _CMU_CMD_RESETVALUE                         0x00000000UL                     
02494 #define _CMU_CMD_MASK                               0x0000001FUL                     
02495 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                
02496 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                            
02497 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                     
02498 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                     
02499 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                     
02500 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                     
02501 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                     
02502 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0) 
02503 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)   
02504 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)    
02505 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)   
02506 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)    
02507 #define CMU_CMD_CALSTART                            (0x1UL << 3)                     
02508 #define _CMU_CMD_CALSTART_SHIFT                     3                                
02509 #define _CMU_CMD_CALSTART_MASK                      0x8UL                            
02510 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                     
02511 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3) 
02512 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                     
02513 #define _CMU_CMD_CALSTOP_SHIFT                      4                                
02514 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                           
02515 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                     
02516 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)  
02518 /* Bit fields for CMU LFCLKSEL */
02519 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             
02520 #define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             
02521 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
02522 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
02523 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
02524 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
02525 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
02526 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
02527 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
02528 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
02529 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
02530 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
02531 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
02532 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
02533 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
02534 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
02535 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
02536 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
02537 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
02538 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
02539 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
02540 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
02541 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
02542 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
02543 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
02544 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
02545 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
02546 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
02547 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
02548 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
02549 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
02550 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
02551 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
02552 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
02553 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
02554 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
02555 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
02556 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
02557 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
02558 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
02559 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
02560 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
02561 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
02562 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
02564 /* Bit fields for CMU STATUS */
02565 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                           
02566 #define _CMU_STATUS_MASK                            0x00007FFFUL                           
02567 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                           
02568 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                      
02569 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                  
02570 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                           
02571 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)    
02572 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                           
02573 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                      
02574 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                  
02575 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                           
02576 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)    
02577 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                           
02578 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                      
02579 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                  
02580 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                           
02581 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)     
02582 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                           
02583 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                      
02584 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                  
02585 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                           
02586 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)     
02587 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                           
02588 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                      
02589 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                 
02590 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                           
02591 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) 
02592 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                           
02593 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                      
02594 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                 
02595 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                           
02596 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) 
02597 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                           
02598 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                      
02599 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                 
02600 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                           
02601 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)    
02602 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                           
02603 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                      
02604 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                 
02605 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                           
02606 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)    
02607 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                           
02608 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                      
02609 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                
02610 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                           
02611 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)     
02612 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                           
02613 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                      
02614 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                
02615 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                           
02616 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)     
02617 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                          
02618 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                     
02619 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                
02620 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                           
02621 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)   
02622 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                          
02623 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                     
02624 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                
02625 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                           
02626 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)    
02627 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                          
02628 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                     
02629 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                               
02630 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                           
02631 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)   
02632 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                          
02633 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                     
02634 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                               
02635 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                           
02636 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)    
02637 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                          
02638 #define _CMU_STATUS_CALBSY_SHIFT                    14                                     
02639 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                               
02640 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                           
02641 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)     
02643 /* Bit fields for CMU IF */
02644 #define _CMU_IF_RESETVALUE                          0x00000001UL                       
02645 #define _CMU_IF_MASK                                0x0000007FUL                       
02646 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                       
02647 #define _CMU_IF_HFRCORDY_SHIFT                      0                                  
02648 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                              
02649 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                       
02650 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)    
02651 #define CMU_IF_HFXORDY                              (0x1UL << 1)                       
02652 #define _CMU_IF_HFXORDY_SHIFT                       1                                  
02653 #define _CMU_IF_HFXORDY_MASK                        0x2UL                              
02654 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                       
02655 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)     
02656 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                       
02657 #define _CMU_IF_LFRCORDY_SHIFT                      2                                  
02658 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                              
02659 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                       
02660 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)    
02661 #define CMU_IF_LFXORDY                              (0x1UL << 3)                       
02662 #define _CMU_IF_LFXORDY_SHIFT                       3                                  
02663 #define _CMU_IF_LFXORDY_MASK                        0x8UL                              
02664 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                       
02665 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)     
02666 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                       
02667 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                  
02668 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                             
02669 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                       
02670 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
02671 #define CMU_IF_CALRDY                               (0x1UL << 5)                       
02672 #define _CMU_IF_CALRDY_SHIFT                        5                                  
02673 #define _CMU_IF_CALRDY_MASK                         0x20UL                             
02674 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                       
02675 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)      
02676 #define CMU_IF_CALOF                                (0x1UL << 6)                       
02677 #define _CMU_IF_CALOF_SHIFT                         6                                  
02678 #define _CMU_IF_CALOF_MASK                          0x40UL                             
02679 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                       
02680 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)       
02682 /* Bit fields for CMU IFS */
02683 #define _CMU_IFS_RESETVALUE                         0x00000000UL                        
02684 #define _CMU_IFS_MASK                               0x0000007FUL                        
02685 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                        
02686 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                   
02687 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                               
02688 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                        
02689 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
02690 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                        
02691 #define _CMU_IFS_HFXORDY_SHIFT                      1                                   
02692 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                               
02693 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                        
02694 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)     
02695 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                        
02696 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                   
02697 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                               
02698 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                        
02699 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
02700 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                        
02701 #define _CMU_IFS_LFXORDY_SHIFT                      3                                   
02702 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                               
02703 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                        
02704 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)     
02705 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                        
02706 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                   
02707 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                              
02708 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                        
02709 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
02710 #define CMU_IFS_CALRDY                              (0x1UL << 5)                        
02711 #define _CMU_IFS_CALRDY_SHIFT                       5                                   
02712 #define _CMU_IFS_CALRDY_MASK                        0x20UL                              
02713 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                        
02714 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)      
02715 #define CMU_IFS_CALOF                               (0x1UL << 6)                        
02716 #define _CMU_IFS_CALOF_SHIFT                        6                                   
02717 #define _CMU_IFS_CALOF_MASK                         0x40UL                              
02718 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                        
02719 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)       
02721 /* Bit fields for CMU IFC */
02722 #define _CMU_IFC_RESETVALUE                         0x00000000UL                        
02723 #define _CMU_IFC_MASK                               0x0000007FUL                        
02724 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                        
02725 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                   
02726 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                               
02727 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                        
02728 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
02729 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                        
02730 #define _CMU_IFC_HFXORDY_SHIFT                      1                                   
02731 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                               
02732 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                        
02733 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)     
02734 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                        
02735 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                   
02736 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                               
02737 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                        
02738 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
02739 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                        
02740 #define _CMU_IFC_LFXORDY_SHIFT                      3                                   
02741 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                               
02742 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                        
02743 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)     
02744 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                        
02745 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                   
02746 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                              
02747 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                        
02748 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
02749 #define CMU_IFC_CALRDY                              (0x1UL << 5)                        
02750 #define _CMU_IFC_CALRDY_SHIFT                       5                                   
02751 #define _CMU_IFC_CALRDY_MASK                        0x20UL                              
02752 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                        
02753 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)      
02754 #define CMU_IFC_CALOF                               (0x1UL << 6)                        
02755 #define _CMU_IFC_CALOF_SHIFT                        6                                   
02756 #define _CMU_IFC_CALOF_MASK                         0x40UL                              
02757 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                        
02758 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)       
02760 /* Bit fields for CMU IEN */
02761 #define _CMU_IEN_RESETVALUE                         0x00000000UL                        
02762 #define _CMU_IEN_MASK                               0x0000007FUL                        
02763 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                        
02764 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                   
02765 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                               
02766 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                        
02767 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
02768 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                        
02769 #define _CMU_IEN_HFXORDY_SHIFT                      1                                   
02770 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                               
02771 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                        
02772 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)     
02773 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                        
02774 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                   
02775 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                               
02776 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                        
02777 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
02778 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                        
02779 #define _CMU_IEN_LFXORDY_SHIFT                      3                                   
02780 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                               
02781 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                        
02782 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)     
02783 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                        
02784 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                   
02785 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                              
02786 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                        
02787 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
02788 #define CMU_IEN_CALRDY                              (0x1UL << 5)                        
02789 #define _CMU_IEN_CALRDY_SHIFT                       5                                   
02790 #define _CMU_IEN_CALRDY_MASK                        0x20UL                              
02791 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                        
02792 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)      
02793 #define CMU_IEN_CALOF                               (0x1UL << 6)                        
02794 #define _CMU_IEN_CALOF_SHIFT                        6                                   
02795 #define _CMU_IEN_CALOF_MASK                         0x40UL                              
02796 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                        
02797 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)       
02799 /* Bit fields for CMU HFCORECLKEN0 */
02800 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                         
02801 #define _CMU_HFCORECLKEN0_MASK                      0x00000013UL                         
02802 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 0)                         
02803 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 0                                    
02804 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x1UL                                
02805 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                         
02806 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) 
02807 #define CMU_HFCORECLKEN0_AES                        (0x1UL << 1)                         
02808 #define _CMU_HFCORECLKEN0_AES_SHIFT                 1                                    
02809 #define _CMU_HFCORECLKEN0_AES_MASK                  0x2UL                                
02810 #define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                         
02811 #define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) 
02812 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 4)                         
02813 #define _CMU_HFCORECLKEN0_LE_SHIFT                  4                                    
02814 #define _CMU_HFCORECLKEN0_LE_MASK                   0x10UL                               
02815 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                         
02816 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)  
02818 /* Bit fields for CMU HFPERCLKEN0 */
02819 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
02820 #define _CMU_HFPERCLKEN0_MASK                       0x0003FFE7UL                           
02821 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 0)                           
02822 #define _CMU_HFPERCLKEN0_USART0_SHIFT               0                                      
02823 #define _CMU_HFPERCLKEN0_USART0_MASK                0x1UL                                  
02824 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
02825 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) 
02826 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 1)                           
02827 #define _CMU_HFPERCLKEN0_USART1_SHIFT               1                                      
02828 #define _CMU_HFPERCLKEN0_USART1_MASK                0x2UL                                  
02829 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
02830 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) 
02831 #define CMU_HFPERCLKEN0_USART2                      (0x1UL << 2)                           
02832 #define _CMU_HFPERCLKEN0_USART2_SHIFT               2                                      
02833 #define _CMU_HFPERCLKEN0_USART2_MASK                0x4UL                                  
02834 #define _CMU_HFPERCLKEN0_USART2_DEFAULT             0x00000000UL                           
02835 #define CMU_HFPERCLKEN0_USART2_DEFAULT              (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) 
02836 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 5)                           
02837 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               5                                      
02838 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x20UL                                 
02839 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
02840 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) 
02841 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 6)                           
02842 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               6                                      
02843 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x40UL                                 
02844 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
02845 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) 
02846 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 7)                           
02847 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               7                                      
02848 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x80UL                                 
02849 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
02850 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) 
02851 #define CMU_HFPERCLKEN0_TIMER3                      (0x1UL << 8)                           
02852 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT               8                                      
02853 #define _CMU_HFPERCLKEN0_TIMER3_MASK                0x100UL                                
02854 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT             0x00000000UL                           
02855 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT              (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) 
02856 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 9)                           
02857 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                9                                      
02858 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x200UL                                
02859 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
02860 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)  
02861 #define CMU_HFPERCLKEN0_ACMP1                       (0x1UL << 10)                          
02862 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT                10                                     
02863 #define _CMU_HFPERCLKEN0_ACMP1_MASK                 0x400UL                                
02864 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT              0x00000000UL                           
02865 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT               (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) 
02866 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
02867 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
02868 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
02869 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
02870 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
02871 #define CMU_HFPERCLKEN0_I2C1                        (0x1UL << 12)                          
02872 #define _CMU_HFPERCLKEN0_I2C1_SHIFT                 12                                     
02873 #define _CMU_HFPERCLKEN0_I2C1_MASK                  0x1000UL                               
02874 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT               0x00000000UL                           
02875 #define CMU_HFPERCLKEN0_I2C1_DEFAULT                (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)  
02876 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 13)                          
02877 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 13                                     
02878 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x2000UL                               
02879 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
02880 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)  
02881 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 14)                          
02882 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 14                                     
02883 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x4000UL                               
02884 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
02885 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)  
02886 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 15)                          
02887 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  15                                     
02888 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x8000UL                               
02889 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
02890 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)   
02891 #define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 16)                          
02892 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                 16                                     
02893 #define _CMU_HFPERCLKEN0_ADC0_MASK                  0x10000UL                              
02894 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           
02895 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)  
02896 #define CMU_HFPERCLKEN0_DAC0                        (0x1UL << 17)                          
02897 #define _CMU_HFPERCLKEN0_DAC0_SHIFT                 17                                     
02898 #define _CMU_HFPERCLKEN0_DAC0_MASK                  0x20000UL                              
02899 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT               0x00000000UL                           
02900 #define CMU_HFPERCLKEN0_DAC0_DEFAULT                (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)  
02902 /* Bit fields for CMU SYNCBUSY */
02903 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
02904 #define _CMU_SYNCBUSY_MASK                          0x00000055UL                           
02905 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
02906 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
02907 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
02908 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
02909 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
02910 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
02911 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
02912 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
02913 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
02914 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
02915 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
02916 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
02917 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
02918 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
02919 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
02920 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
02921 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
02922 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
02923 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
02924 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
02926 /* Bit fields for CMU FREEZE */
02927 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
02928 #define _CMU_FREEZE_MASK                            0x00000001UL                         
02929 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
02930 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
02931 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
02932 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
02933 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
02934 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
02935 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
02936 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
02937 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
02939 /* Bit fields for CMU LFACLKEN0 */
02940 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                           
02941 #define _CMU_LFACLKEN0_MASK                         0x00000007UL                           
02942 #define CMU_LFACLKEN0_LESENSE                       (0x1UL << 0)                           
02943 #define _CMU_LFACLKEN0_LESENSE_SHIFT                0                                      
02944 #define _CMU_LFACLKEN0_LESENSE_MASK                 0x1UL                                  
02945 #define _CMU_LFACLKEN0_LESENSE_DEFAULT              0x00000000UL                           
02946 #define CMU_LFACLKEN0_LESENSE_DEFAULT               (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)  
02947 #define CMU_LFACLKEN0_RTC                           (0x1UL << 1)                           
02948 #define _CMU_LFACLKEN0_RTC_SHIFT                    1                                      
02949 #define _CMU_LFACLKEN0_RTC_MASK                     0x2UL                                  
02950 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                           
02951 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)      
02952 #define CMU_LFACLKEN0_LETIMER0                      (0x1UL << 2)                           
02953 #define _CMU_LFACLKEN0_LETIMER0_SHIFT               2                                      
02954 #define _CMU_LFACLKEN0_LETIMER0_MASK                0x4UL                                  
02955 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT             0x00000000UL                           
02956 #define CMU_LFACLKEN0_LETIMER0_DEFAULT              (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) 
02958 /* Bit fields for CMU LFBCLKEN0 */
02959 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
02960 #define _CMU_LFBCLKEN0_MASK                         0x00000003UL                          
02961 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
02962 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
02963 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
02964 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
02965 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
02966 #define CMU_LFBCLKEN0_LEUART1                       (0x1UL << 1)                          
02967 #define _CMU_LFBCLKEN0_LEUART1_SHIFT                1                                     
02968 #define _CMU_LFBCLKEN0_LEUART1_MASK                 0x2UL                                 
02969 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT              0x00000000UL                          
02970 #define CMU_LFBCLKEN0_LEUART1_DEFAULT               (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) 
02972 /* Bit fields for CMU LFAPRESC0 */
02973 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                            
02974 #define _CMU_LFAPRESC0_MASK                         0x00000FF3UL                            
02975 #define _CMU_LFAPRESC0_LESENSE_SHIFT                0                                       
02976 #define _CMU_LFAPRESC0_LESENSE_MASK                 0x3UL                                   
02977 #define _CMU_LFAPRESC0_LESENSE_DIV1                 0x00000000UL                            
02978 #define _CMU_LFAPRESC0_LESENSE_DIV2                 0x00000001UL                            
02979 #define _CMU_LFAPRESC0_LESENSE_DIV4                 0x00000002UL                            
02980 #define _CMU_LFAPRESC0_LESENSE_DIV8                 0x00000003UL                            
02981 #define CMU_LFAPRESC0_LESENSE_DIV1                  (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)      
02982 #define CMU_LFAPRESC0_LESENSE_DIV2                  (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)      
02983 #define CMU_LFAPRESC0_LESENSE_DIV4                  (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)      
02984 #define CMU_LFAPRESC0_LESENSE_DIV8                  (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)      
02985 #define _CMU_LFAPRESC0_RTC_SHIFT                    4                                       
02986 #define _CMU_LFAPRESC0_RTC_MASK                     0xF0UL                                  
02987 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                            
02988 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                            
02989 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                            
02990 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                            
02991 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                            
02992 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                            
02993 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                            
02994 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                            
02995 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                            
02996 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                            
02997 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                            
02998 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                            
02999 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                            
03000 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                            
03001 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                            
03002 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                            
03003 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 4)          
03004 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 4)          
03005 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 4)          
03006 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 4)          
03007 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 4)         
03008 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 4)         
03009 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 4)         
03010 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 4)        
03011 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 4)        
03012 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 4)        
03013 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)       
03014 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)       
03015 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)       
03016 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)       
03017 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 4)      
03018 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 4)      
03019 #define _CMU_LFAPRESC0_LETIMER0_SHIFT               8                                       
03020 #define _CMU_LFAPRESC0_LETIMER0_MASK                0xF00UL                                 
03021 #define _CMU_LFAPRESC0_LETIMER0_DIV1                0x00000000UL                            
03022 #define _CMU_LFAPRESC0_LETIMER0_DIV2                0x00000001UL                            
03023 #define _CMU_LFAPRESC0_LETIMER0_DIV4                0x00000002UL                            
03024 #define _CMU_LFAPRESC0_LETIMER0_DIV8                0x00000003UL                            
03025 #define _CMU_LFAPRESC0_LETIMER0_DIV16               0x00000004UL                            
03026 #define _CMU_LFAPRESC0_LETIMER0_DIV32               0x00000005UL                            
03027 #define _CMU_LFAPRESC0_LETIMER0_DIV64               0x00000006UL                            
03028 #define _CMU_LFAPRESC0_LETIMER0_DIV128              0x00000007UL                            
03029 #define _CMU_LFAPRESC0_LETIMER0_DIV256              0x00000008UL                            
03030 #define _CMU_LFAPRESC0_LETIMER0_DIV512              0x00000009UL                            
03031 #define _CMU_LFAPRESC0_LETIMER0_DIV1024             0x0000000AUL                            
03032 #define _CMU_LFAPRESC0_LETIMER0_DIV2048             0x0000000BUL                            
03033 #define _CMU_LFAPRESC0_LETIMER0_DIV4096             0x0000000CUL                            
03034 #define _CMU_LFAPRESC0_LETIMER0_DIV8192             0x0000000DUL                            
03035 #define _CMU_LFAPRESC0_LETIMER0_DIV16384            0x0000000EUL                            
03036 #define _CMU_LFAPRESC0_LETIMER0_DIV32768            0x0000000FUL                            
03037 #define CMU_LFAPRESC0_LETIMER0_DIV1                 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)     
03038 #define CMU_LFAPRESC0_LETIMER0_DIV2                 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)     
03039 #define CMU_LFAPRESC0_LETIMER0_DIV4                 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)     
03040 #define CMU_LFAPRESC0_LETIMER0_DIV8                 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)     
03041 #define CMU_LFAPRESC0_LETIMER0_DIV16                (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)    
03042 #define CMU_LFAPRESC0_LETIMER0_DIV32                (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)    
03043 #define CMU_LFAPRESC0_LETIMER0_DIV64                (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)    
03044 #define CMU_LFAPRESC0_LETIMER0_DIV128               (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)   
03045 #define CMU_LFAPRESC0_LETIMER0_DIV256               (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)   
03046 #define CMU_LFAPRESC0_LETIMER0_DIV512               (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)   
03047 #define CMU_LFAPRESC0_LETIMER0_DIV1024              (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)  
03048 #define CMU_LFAPRESC0_LETIMER0_DIV2048              (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)  
03049 #define CMU_LFAPRESC0_LETIMER0_DIV4096              (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)  
03050 #define CMU_LFAPRESC0_LETIMER0_DIV8192              (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)  
03051 #define CMU_LFAPRESC0_LETIMER0_DIV16384             (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) 
03052 #define CMU_LFAPRESC0_LETIMER0_DIV32768             (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) 
03054 /* Bit fields for CMU LFBPRESC0 */
03055 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
03056 #define _CMU_LFBPRESC0_MASK                         0x00000033UL                       
03057 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
03058 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
03059 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
03060 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
03061 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
03062 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
03063 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
03064 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
03065 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
03066 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
03067 #define _CMU_LFBPRESC0_LEUART1_SHIFT                4                                  
03068 #define _CMU_LFBPRESC0_LEUART1_MASK                 0x30UL                             
03069 #define _CMU_LFBPRESC0_LEUART1_DIV1                 0x00000000UL                       
03070 #define _CMU_LFBPRESC0_LEUART1_DIV2                 0x00000001UL                       
03071 #define _CMU_LFBPRESC0_LEUART1_DIV4                 0x00000002UL                       
03072 #define _CMU_LFBPRESC0_LEUART1_DIV8                 0x00000003UL                       
03073 #define CMU_LFBPRESC0_LEUART1_DIV1                  (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) 
03074 #define CMU_LFBPRESC0_LEUART1_DIV2                  (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) 
03075 #define CMU_LFBPRESC0_LEUART1_DIV4                  (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) 
03076 #define CMU_LFBPRESC0_LEUART1_DIV8                  (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) 
03078 /* Bit fields for CMU PCNTCTRL */
03079 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
03080 #define _CMU_PCNTCTRL_MASK                          0x0000003FUL                             
03081 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
03082 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
03083 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
03084 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
03085 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
03086 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
03087 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
03088 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
03089 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
03090 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
03091 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
03092 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
03093 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
03094 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
03095 #define CMU_PCNTCTRL_PCNT1CLKEN                     (0x1UL << 2)                             
03096 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT              2                                        
03097 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK               0x4UL                                    
03098 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT            0x00000000UL                             
03099 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  
03100 #define CMU_PCNTCTRL_PCNT1CLKSEL                    (0x1UL << 3)                             
03101 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT             3                                        
03102 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK              0x8UL                                    
03103 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT           0x00000000UL                             
03104 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK            0x00000000UL                             
03105 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0           0x00000001UL                             
03106 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) 
03107 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  
03108 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0            (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) 
03109 #define CMU_PCNTCTRL_PCNT2CLKEN                     (0x1UL << 4)                             
03110 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT              4                                        
03111 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK               0x10UL                                   
03112 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT            0x00000000UL                             
03113 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  
03114 #define CMU_PCNTCTRL_PCNT2CLKSEL                    (0x1UL << 5)                             
03115 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT             5                                        
03116 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK              0x20UL                                   
03117 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT           0x00000000UL                             
03118 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK            0x00000000UL                             
03119 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0           0x00000001UL                             
03120 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) 
03121 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  
03122 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0            (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) 
03124 /* Bit fields for CMU ROUTE */
03125 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
03126 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
03127 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
03128 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
03129 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
03130 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
03131 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
03132 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
03133 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
03134 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
03135 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
03136 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
03137 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
03138 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
03139 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
03140 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
03141 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
03142 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
03143 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
03144 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
03145 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
03146 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
03148 /* Bit fields for CMU LOCK */
03149 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
03150 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
03151 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
03152 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
03153 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
03154 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
03155 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
03156 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
03157 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
03158 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
03159 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
03160 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
03161 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
03162 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
03168 /**************************************************************************/
03173 /* Bit fields for PRS SWPULSE */
03174 #define _PRS_SWPULSE_RESETVALUE                 0x00000000UL                           
03175 #define _PRS_SWPULSE_MASK                       0x00000FFFUL                           
03176 #define PRS_SWPULSE_CH0PULSE                    (0x1UL << 0)                           
03177 #define _PRS_SWPULSE_CH0PULSE_SHIFT             0                                      
03178 #define _PRS_SWPULSE_CH0PULSE_MASK              0x1UL                                  
03179 #define _PRS_SWPULSE_CH0PULSE_DEFAULT           0x00000000UL                           
03180 #define PRS_SWPULSE_CH0PULSE_DEFAULT            (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)   
03181 #define PRS_SWPULSE_CH1PULSE                    (0x1UL << 1)                           
03182 #define _PRS_SWPULSE_CH1PULSE_SHIFT             1                                      
03183 #define _PRS_SWPULSE_CH1PULSE_MASK              0x2UL                                  
03184 #define _PRS_SWPULSE_CH1PULSE_DEFAULT           0x00000000UL                           
03185 #define PRS_SWPULSE_CH1PULSE_DEFAULT            (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)   
03186 #define PRS_SWPULSE_CH2PULSE                    (0x1UL << 2)                           
03187 #define _PRS_SWPULSE_CH2PULSE_SHIFT             2                                      
03188 #define _PRS_SWPULSE_CH2PULSE_MASK              0x4UL                                  
03189 #define _PRS_SWPULSE_CH2PULSE_DEFAULT           0x00000000UL                           
03190 #define PRS_SWPULSE_CH2PULSE_DEFAULT            (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)   
03191 #define PRS_SWPULSE_CH3PULSE                    (0x1UL << 3)                           
03192 #define _PRS_SWPULSE_CH3PULSE_SHIFT             3                                      
03193 #define _PRS_SWPULSE_CH3PULSE_MASK              0x8UL                                  
03194 #define _PRS_SWPULSE_CH3PULSE_DEFAULT           0x00000000UL                           
03195 #define PRS_SWPULSE_CH3PULSE_DEFAULT            (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)   
03196 #define PRS_SWPULSE_CH4PULSE                    (0x1UL << 4)                           
03197 #define _PRS_SWPULSE_CH4PULSE_SHIFT             4                                      
03198 #define _PRS_SWPULSE_CH4PULSE_MASK              0x10UL                                 
03199 #define _PRS_SWPULSE_CH4PULSE_DEFAULT           0x00000000UL                           
03200 #define PRS_SWPULSE_CH4PULSE_DEFAULT            (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)   
03201 #define PRS_SWPULSE_CH5PULSE                    (0x1UL << 5)                           
03202 #define _PRS_SWPULSE_CH5PULSE_SHIFT             5                                      
03203 #define _PRS_SWPULSE_CH5PULSE_MASK              0x20UL                                 
03204 #define _PRS_SWPULSE_CH5PULSE_DEFAULT           0x00000000UL                           
03205 #define PRS_SWPULSE_CH5PULSE_DEFAULT            (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)   
03206 #define PRS_SWPULSE_CH6PULSE                    (0x1UL << 6)                           
03207 #define _PRS_SWPULSE_CH6PULSE_SHIFT             6                                      
03208 #define _PRS_SWPULSE_CH6PULSE_MASK              0x40UL                                 
03209 #define _PRS_SWPULSE_CH6PULSE_DEFAULT           0x00000000UL                           
03210 #define PRS_SWPULSE_CH6PULSE_DEFAULT            (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)   
03211 #define PRS_SWPULSE_CH7PULSE                    (0x1UL << 7)                           
03212 #define _PRS_SWPULSE_CH7PULSE_SHIFT             7                                      
03213 #define _PRS_SWPULSE_CH7PULSE_MASK              0x80UL                                 
03214 #define _PRS_SWPULSE_CH7PULSE_DEFAULT           0x00000000UL                           
03215 #define PRS_SWPULSE_CH7PULSE_DEFAULT            (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)   
03216 #define PRS_SWPULSE_CH8PULSE                    (0x1UL << 8)                           
03217 #define _PRS_SWPULSE_CH8PULSE_SHIFT             8                                      
03218 #define _PRS_SWPULSE_CH8PULSE_MASK              0x100UL                                
03219 #define _PRS_SWPULSE_CH8PULSE_DEFAULT           0x00000000UL                           
03220 #define PRS_SWPULSE_CH8PULSE_DEFAULT            (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8)   
03221 #define PRS_SWPULSE_CH9PULSE                    (0x1UL << 9)                           
03222 #define _PRS_SWPULSE_CH9PULSE_SHIFT             9                                      
03223 #define _PRS_SWPULSE_CH9PULSE_MASK              0x200UL                                
03224 #define _PRS_SWPULSE_CH9PULSE_DEFAULT           0x00000000UL                           
03225 #define PRS_SWPULSE_CH9PULSE_DEFAULT            (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9)   
03226 #define PRS_SWPULSE_CH10PULSE                   (0x1UL << 10)                          
03227 #define _PRS_SWPULSE_CH10PULSE_SHIFT            10                                     
03228 #define _PRS_SWPULSE_CH10PULSE_MASK             0x400UL                                
03229 #define _PRS_SWPULSE_CH10PULSE_DEFAULT          0x00000000UL                           
03230 #define PRS_SWPULSE_CH10PULSE_DEFAULT           (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) 
03231 #define PRS_SWPULSE_CH11PULSE                   (0x1UL << 11)                          
03232 #define _PRS_SWPULSE_CH11PULSE_SHIFT            11                                     
03233 #define _PRS_SWPULSE_CH11PULSE_MASK             0x800UL                                
03234 #define _PRS_SWPULSE_CH11PULSE_DEFAULT          0x00000000UL                           
03235 #define PRS_SWPULSE_CH11PULSE_DEFAULT           (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) 
03237 /* Bit fields for PRS SWLEVEL */
03238 #define _PRS_SWLEVEL_RESETVALUE                 0x00000000UL                           
03239 #define _PRS_SWLEVEL_MASK                       0x00000FFFUL                           
03240 #define PRS_SWLEVEL_CH0LEVEL                    (0x1UL << 0)                           
03241 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT             0                                      
03242 #define _PRS_SWLEVEL_CH0LEVEL_MASK              0x1UL                                  
03243 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT           0x00000000UL                           
03244 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT            (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)   
03245 #define PRS_SWLEVEL_CH1LEVEL                    (0x1UL << 1)                           
03246 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT             1                                      
03247 #define _PRS_SWLEVEL_CH1LEVEL_MASK              0x2UL                                  
03248 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT           0x00000000UL                           
03249 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT            (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)   
03250 #define PRS_SWLEVEL_CH2LEVEL                    (0x1UL << 2)                           
03251 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT             2                                      
03252 #define _PRS_SWLEVEL_CH2LEVEL_MASK              0x4UL                                  
03253 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT           0x00000000UL                           
03254 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT            (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)   
03255 #define PRS_SWLEVEL_CH3LEVEL                    (0x1UL << 3)                           
03256 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT             3                                      
03257 #define _PRS_SWLEVEL_CH3LEVEL_MASK              0x8UL                                  
03258 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT           0x00000000UL                           
03259 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT            (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)   
03260 #define PRS_SWLEVEL_CH4LEVEL                    (0x1UL << 4)                           
03261 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT             4                                      
03262 #define _PRS_SWLEVEL_CH4LEVEL_MASK              0x10UL                                 
03263 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT           0x00000000UL                           
03264 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT            (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)   
03265 #define PRS_SWLEVEL_CH5LEVEL                    (0x1UL << 5)                           
03266 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT             5                                      
03267 #define _PRS_SWLEVEL_CH5LEVEL_MASK              0x20UL                                 
03268 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT           0x00000000UL                           
03269 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT            (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)   
03270 #define PRS_SWLEVEL_CH6LEVEL                    (0x1UL << 6)                           
03271 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT             6                                      
03272 #define _PRS_SWLEVEL_CH6LEVEL_MASK              0x40UL                                 
03273 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT           0x00000000UL                           
03274 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT            (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)   
03275 #define PRS_SWLEVEL_CH7LEVEL                    (0x1UL << 7)                           
03276 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT             7                                      
03277 #define _PRS_SWLEVEL_CH7LEVEL_MASK              0x80UL                                 
03278 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT           0x00000000UL                           
03279 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT            (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)   
03280 #define PRS_SWLEVEL_CH8LEVEL                    (0x1UL << 8)                           
03281 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT             8                                      
03282 #define _PRS_SWLEVEL_CH8LEVEL_MASK              0x100UL                                
03283 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT           0x00000000UL                           
03284 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT            (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8)   
03285 #define PRS_SWLEVEL_CH9LEVEL                    (0x1UL << 9)                           
03286 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT             9                                      
03287 #define _PRS_SWLEVEL_CH9LEVEL_MASK              0x200UL                                
03288 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT           0x00000000UL                           
03289 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT            (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9)   
03290 #define PRS_SWLEVEL_CH10LEVEL                   (0x1UL << 10)                          
03291 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT            10                                     
03292 #define _PRS_SWLEVEL_CH10LEVEL_MASK             0x400UL                                
03293 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT          0x00000000UL                           
03294 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT           (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) 
03295 #define PRS_SWLEVEL_CH11LEVEL                   (0x1UL << 11)                          
03296 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT            11                                     
03297 #define _PRS_SWLEVEL_CH11LEVEL_MASK             0x800UL                                
03298 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT          0x00000000UL                           
03299 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT           (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) 
03301 /* Bit fields for PRS ROUTE */
03302 #define _PRS_ROUTE_RESETVALUE                   0x00000000UL                       
03303 #define _PRS_ROUTE_MASK                         0x0000070FUL                       
03304 #define PRS_ROUTE_CH0PEN                        (0x1UL << 0)                       
03305 #define _PRS_ROUTE_CH0PEN_SHIFT                 0                                  
03306 #define _PRS_ROUTE_CH0PEN_MASK                  0x1UL                              
03307 #define _PRS_ROUTE_CH0PEN_DEFAULT               0x00000000UL                       
03308 #define PRS_ROUTE_CH0PEN_DEFAULT                (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   
03309 #define PRS_ROUTE_CH1PEN                        (0x1UL << 1)                       
03310 #define _PRS_ROUTE_CH1PEN_SHIFT                 1                                  
03311 #define _PRS_ROUTE_CH1PEN_MASK                  0x2UL                              
03312 #define _PRS_ROUTE_CH1PEN_DEFAULT               0x00000000UL                       
03313 #define PRS_ROUTE_CH1PEN_DEFAULT                (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   
03314 #define PRS_ROUTE_CH2PEN                        (0x1UL << 2)                       
03315 #define _PRS_ROUTE_CH2PEN_SHIFT                 2                                  
03316 #define _PRS_ROUTE_CH2PEN_MASK                  0x4UL                              
03317 #define _PRS_ROUTE_CH2PEN_DEFAULT               0x00000000UL                       
03318 #define PRS_ROUTE_CH2PEN_DEFAULT                (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   
03319 #define PRS_ROUTE_CH3PEN                        (0x1UL << 3)                       
03320 #define _PRS_ROUTE_CH3PEN_SHIFT                 3                                  
03321 #define _PRS_ROUTE_CH3PEN_MASK                  0x8UL                              
03322 #define _PRS_ROUTE_CH3PEN_DEFAULT               0x00000000UL                       
03323 #define PRS_ROUTE_CH3PEN_DEFAULT                (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   
03324 #define _PRS_ROUTE_LOCATION_SHIFT               8                                  
03325 #define _PRS_ROUTE_LOCATION_MASK                0x700UL                            
03326 #define _PRS_ROUTE_LOCATION_LOC0                0x00000000UL                       
03327 #define _PRS_ROUTE_LOCATION_DEFAULT             0x00000000UL                       
03328 #define _PRS_ROUTE_LOCATION_LOC1                0x00000001UL                       
03329 #define PRS_ROUTE_LOCATION_LOC0                 (_PRS_ROUTE_LOCATION_LOC0 << 8)    
03330 #define PRS_ROUTE_LOCATION_DEFAULT              (_PRS_ROUTE_LOCATION_DEFAULT << 8) 
03331 #define PRS_ROUTE_LOCATION_LOC1                 (_PRS_ROUTE_LOCATION_LOC1 << 8)    
03333 /* Bit fields for PRS CH_CTRL */
03334 #define _PRS_CH_CTRL_RESETVALUE                 0x00000000UL                                
03335 #define _PRS_CH_CTRL_MASK                       0x133F0007UL                                
03336 #define _PRS_CH_CTRL_SIGSEL_SHIFT               0                                           
03337 #define _PRS_CH_CTRL_SIGSEL_MASK                0x7UL                                       
03338 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT             0x00000000UL                                
03339 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT            0x00000000UL                                
03340 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT            0x00000000UL                                
03341 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0             0x00000000UL                                
03342 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE          0x00000000UL                                
03343 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX          0x00000000UL                                
03344 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF            0x00000000UL                                
03345 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF            0x00000000UL                                
03346 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF            0x00000000UL                                
03347 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF            0x00000000UL                                
03348 #define _PRS_CH_CTRL_SIGSEL_RTCOF               0x00000000UL                                
03349 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0            0x00000000UL                                
03350 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8            0x00000000UL                                
03351 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0         0x00000000UL                                
03352 #define _PRS_CH_CTRL_SIGSEL_BURTCOF             0x00000000UL                                
03353 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0     0x00000000UL                                
03354 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8     0x00000000UL                                
03355 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0         0x00000000UL                                
03356 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1             0x00000001UL                                
03357 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN            0x00000001UL                                
03358 #define _PRS_CH_CTRL_SIGSEL_USART0TXC           0x00000001UL                                
03359 #define _PRS_CH_CTRL_SIGSEL_USART1TXC           0x00000001UL                                
03360 #define _PRS_CH_CTRL_SIGSEL_USART2TXC           0x00000001UL                                
03361 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF            0x00000001UL                                
03362 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF            0x00000001UL                                
03363 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF            0x00000001UL                                
03364 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF            0x00000001UL                                
03365 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0            0x00000001UL                                
03366 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1            0x00000001UL                                
03367 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9            0x00000001UL                                
03368 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1         0x00000001UL                                
03369 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0          0x00000001UL                                
03370 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1     0x00000001UL                                
03371 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9     0x00000001UL                                
03372 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1         0x00000001UL                                
03373 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV       0x00000002UL                                
03374 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV       0x00000002UL                                
03375 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV       0x00000002UL                                
03376 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0           0x00000002UL                                
03377 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0           0x00000002UL                                
03378 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0           0x00000002UL                                
03379 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0           0x00000002UL                                
03380 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1            0x00000002UL                                
03381 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2            0x00000002UL                                
03382 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10           0x00000002UL                                
03383 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2     0x00000002UL                                
03384 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10    0x00000002UL                                
03385 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2         0x00000002UL                                
03386 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1           0x00000003UL                                
03387 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1           0x00000003UL                                
03388 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1           0x00000003UL                                
03389 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1           0x00000003UL                                
03390 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3            0x00000003UL                                
03391 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11           0x00000003UL                                
03392 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3     0x00000003UL                                
03393 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11    0x00000003UL                                
03394 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2           0x00000004UL                                
03395 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2           0x00000004UL                                
03396 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2           0x00000004UL                                
03397 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2           0x00000004UL                                
03398 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4            0x00000004UL                                
03399 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12           0x00000004UL                                
03400 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4     0x00000004UL                                
03401 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12    0x00000004UL                                
03402 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5            0x00000005UL                                
03403 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13           0x00000005UL                                
03404 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5     0x00000005UL                                
03405 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13    0x00000005UL                                
03406 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6            0x00000006UL                                
03407 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14           0x00000006UL                                
03408 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6     0x00000006UL                                
03409 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14    0x00000006UL                                
03410 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7            0x00000007UL                                
03411 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15           0x00000007UL                                
03412 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7     0x00000007UL                                
03413 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15    0x00000007UL                                
03414 #define PRS_CH_CTRL_SIGSEL_VCMPOUT              (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)          
03415 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT             (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)         
03416 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT             (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)         
03417 #define PRS_CH_CTRL_SIGSEL_DAC0CH0              (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)          
03418 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE           (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)       
03419 #define PRS_CH_CTRL_SIGSEL_USART0IRTX           (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)       
03420 #define PRS_CH_CTRL_SIGSEL_TIMER0UF             (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)         
03421 #define PRS_CH_CTRL_SIGSEL_TIMER1UF             (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)         
03422 #define PRS_CH_CTRL_SIGSEL_TIMER2UF             (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)         
03423 #define PRS_CH_CTRL_SIGSEL_TIMER3UF             (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0)         
03424 #define PRS_CH_CTRL_SIGSEL_RTCOF                (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)            
03425 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0             (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)         
03426 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8             (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)         
03427 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0          (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)      
03428 #define PRS_CH_CTRL_SIGSEL_BURTCOF              (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0)          
03429 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0)  
03430 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0)  
03431 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0)      
03432 #define PRS_CH_CTRL_SIGSEL_DAC0CH1              (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)          
03433 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN             (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)         
03434 #define PRS_CH_CTRL_SIGSEL_USART0TXC            (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)        
03435 #define PRS_CH_CTRL_SIGSEL_USART1TXC            (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)        
03436 #define PRS_CH_CTRL_SIGSEL_USART2TXC            (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0)        
03437 #define PRS_CH_CTRL_SIGSEL_TIMER0OF             (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)         
03438 #define PRS_CH_CTRL_SIGSEL_TIMER1OF             (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)         
03439 #define PRS_CH_CTRL_SIGSEL_TIMER2OF             (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)         
03440 #define PRS_CH_CTRL_SIGSEL_TIMER3OF             (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0)         
03441 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0             (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)         
03442 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1             (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)         
03443 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9             (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)         
03444 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1          (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)      
03445 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0           (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0)       
03446 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0)  
03447 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0)  
03448 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0)      
03449 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)    
03450 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)    
03451 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0)    
03452 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0            (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)        
03453 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0            (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)        
03454 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0            (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)        
03455 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0            (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0)        
03456 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1             (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)         
03457 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2             (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)         
03458 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10            (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)        
03459 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0)  
03460 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) 
03461 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0)      
03462 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1            (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)        
03463 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1            (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)        
03464 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1            (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)        
03465 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1            (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0)        
03466 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3             (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)         
03467 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11            (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)        
03468 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0)  
03469 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) 
03470 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2            (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)        
03471 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2            (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)        
03472 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2            (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)        
03473 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2            (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0)        
03474 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4             (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)         
03475 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12            (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)        
03476 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0)  
03477 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) 
03478 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5             (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)         
03479 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13            (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)        
03480 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0)  
03481 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) 
03482 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6             (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)         
03483 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14            (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)        
03484 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0)  
03485 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) 
03486 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7             (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)         
03487 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15            (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)        
03488 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0)  
03489 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) 
03490 #define _PRS_CH_CTRL_SOURCESEL_SHIFT            16                                          
03491 #define _PRS_CH_CTRL_SOURCESEL_MASK             0x3F0000UL                                  
03492 #define _PRS_CH_CTRL_SOURCESEL_NONE             0x00000000UL                                
03493 #define _PRS_CH_CTRL_SOURCESEL_VCMP             0x00000001UL                                
03494 #define _PRS_CH_CTRL_SOURCESEL_ACMP0            0x00000002UL                                
03495 #define _PRS_CH_CTRL_SOURCESEL_ACMP1            0x00000003UL                                
03496 #define _PRS_CH_CTRL_SOURCESEL_DAC0             0x00000006UL                                
03497 #define _PRS_CH_CTRL_SOURCESEL_ADC0             0x00000008UL                                
03498 #define _PRS_CH_CTRL_SOURCESEL_USART0           0x00000010UL                                
03499 #define _PRS_CH_CTRL_SOURCESEL_USART1           0x00000011UL                                
03500 #define _PRS_CH_CTRL_SOURCESEL_USART2           0x00000012UL                                
03501 #define _PRS_CH_CTRL_SOURCESEL_TIMER0           0x0000001CUL                                
03502 #define _PRS_CH_CTRL_SOURCESEL_TIMER1           0x0000001DUL                                
03503 #define _PRS_CH_CTRL_SOURCESEL_TIMER2           0x0000001EUL                                
03504 #define _PRS_CH_CTRL_SOURCESEL_TIMER3           0x0000001FUL                                
03505 #define _PRS_CH_CTRL_SOURCESEL_RTC              0x00000028UL                                
03506 #define _PRS_CH_CTRL_SOURCESEL_GPIOL            0x00000030UL                                
03507 #define _PRS_CH_CTRL_SOURCESEL_GPIOH            0x00000031UL                                
03508 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0         0x00000034UL                                
03509 #define _PRS_CH_CTRL_SOURCESEL_BURTC            0x00000037UL                                
03510 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL         0x00000039UL                                
03511 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH         0x0000003AUL                                
03512 #define _PRS_CH_CTRL_SOURCESEL_LESENSED         0x0000003BUL                                
03513 #define PRS_CH_CTRL_SOURCESEL_NONE              (_PRS_CH_CTRL_SOURCESEL_NONE << 16)         
03514 #define PRS_CH_CTRL_SOURCESEL_VCMP              (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)         
03515 #define PRS_CH_CTRL_SOURCESEL_ACMP0             (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)        
03516 #define PRS_CH_CTRL_SOURCESEL_ACMP1             (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)        
03517 #define PRS_CH_CTRL_SOURCESEL_DAC0              (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)         
03518 #define PRS_CH_CTRL_SOURCESEL_ADC0              (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)         
03519 #define PRS_CH_CTRL_SOURCESEL_USART0            (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)       
03520 #define PRS_CH_CTRL_SOURCESEL_USART1            (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)       
03521 #define PRS_CH_CTRL_SOURCESEL_USART2            (_PRS_CH_CTRL_SOURCESEL_USART2 << 16)       
03522 #define PRS_CH_CTRL_SOURCESEL_TIMER0            (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)       
03523 #define PRS_CH_CTRL_SOURCESEL_TIMER1            (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)       
03524 #define PRS_CH_CTRL_SOURCESEL_TIMER2            (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)       
03525 #define PRS_CH_CTRL_SOURCESEL_TIMER3            (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16)       
03526 #define PRS_CH_CTRL_SOURCESEL_RTC               (_PRS_CH_CTRL_SOURCESEL_RTC << 16)          
03527 #define PRS_CH_CTRL_SOURCESEL_GPIOL             (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)        
03528 #define PRS_CH_CTRL_SOURCESEL_GPIOH             (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)        
03529 #define PRS_CH_CTRL_SOURCESEL_LETIMER0          (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16)     
03530 #define PRS_CH_CTRL_SOURCESEL_BURTC             (_PRS_CH_CTRL_SOURCESEL_BURTC << 16)        
03531 #define PRS_CH_CTRL_SOURCESEL_LESENSEL          (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16)     
03532 #define PRS_CH_CTRL_SOURCESEL_LESENSEH          (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16)     
03533 #define PRS_CH_CTRL_SOURCESEL_LESENSED          (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16)     
03534 #define _PRS_CH_CTRL_EDSEL_SHIFT                24                                          
03535 #define _PRS_CH_CTRL_EDSEL_MASK                 0x3000000UL                                 
03536 #define _PRS_CH_CTRL_EDSEL_DEFAULT              0x00000000UL                                
03537 #define _PRS_CH_CTRL_EDSEL_OFF                  0x00000000UL                                
03538 #define _PRS_CH_CTRL_EDSEL_POSEDGE              0x00000001UL                                
03539 #define _PRS_CH_CTRL_EDSEL_NEGEDGE              0x00000002UL                                
03540 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES            0x00000003UL                                
03541 #define PRS_CH_CTRL_EDSEL_DEFAULT               (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)          
03542 #define PRS_CH_CTRL_EDSEL_OFF                   (_PRS_CH_CTRL_EDSEL_OFF << 24)              
03543 #define PRS_CH_CTRL_EDSEL_POSEDGE               (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)          
03544 #define PRS_CH_CTRL_EDSEL_NEGEDGE               (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)          
03545 #define PRS_CH_CTRL_EDSEL_BOTHEDGES             (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)        
03546 #define PRS_CH_CTRL_ASYNC                       (0x1UL << 28)                               
03547 #define _PRS_CH_CTRL_ASYNC_SHIFT                28                                          
03548 #define _PRS_CH_CTRL_ASYNC_MASK                 0x10000000UL                                
03549 #define _PRS_CH_CTRL_ASYNC_DEFAULT              0x00000000UL                                
03550 #define PRS_CH_CTRL_ASYNC_DEFAULT               (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)          
03556 /**************************************************************************/
03560 #define MSC_UNLOCK_CODE      0x1B71 
03561 #define EMU_UNLOCK_CODE      0xADE8 
03562 #define CMU_UNLOCK_CODE      0x580E 
03563 #define TIMER_UNLOCK_CODE    0xCE80 
03564 #define GPIO_UNLOCK_CODE     0xA534 
03565 #define BURTC_UNLOCK_CODE    0xAEE8 
03571 /**************************************************************************/
03576 #include "efm32gg_af_ports.h"
03577 #include "efm32gg_af_pins.h"
03578 
03581 /**************************************************************************/
03594 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
03595   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
03596 
03601 #ifdef __cplusplus
03602 }
03603 #endif
03604 #endif /* __EFM32GG230F1024_H */