release/EM_CMSIS_3.20.6/Device/SiliconLabs/EFM32GG/Include/efm32gg890f1024.h

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00001 /**************************************************************************/
00034 #ifndef __EFM32GG890F1024_H
00035 #define __EFM32GG890F1024_H
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M3 Processor Exceptions Numbers *******************************************/
00055   NonMaskableInt_IRQn   = -14,              
00056   HardFault_IRQn        = -13,              
00057   MemoryManagement_IRQn = -12,              
00058   BusFault_IRQn         = -11,              
00059   UsageFault_IRQn       = -10,              
00060   SVCall_IRQn           = -5,               
00061   DebugMonitor_IRQn     = -4,               
00062   PendSV_IRQn           = -2,               
00063   SysTick_IRQn          = -1,               
00065 /******  EFM32G Peripheral Interrupt Numbers **********************************************/
00066   DMA_IRQn              = 0,  
00067   GPIO_EVEN_IRQn        = 1,  
00068   TIMER0_IRQn           = 2,  
00069   USART0_RX_IRQn        = 3,  
00070   USART0_TX_IRQn        = 4,  
00071   ACMP0_IRQn            = 6,  
00072   ADC0_IRQn             = 7,  
00073   DAC0_IRQn             = 8,  
00074   I2C0_IRQn             = 9,  
00075   I2C1_IRQn             = 10, 
00076   GPIO_ODD_IRQn         = 11, 
00077   TIMER1_IRQn           = 12, 
00078   TIMER2_IRQn           = 13, 
00079   TIMER3_IRQn           = 14, 
00080   USART1_RX_IRQn        = 15, 
00081   USART1_TX_IRQn        = 16, 
00082   LESENSE_IRQn          = 17, 
00083   USART2_RX_IRQn        = 18, 
00084   USART2_TX_IRQn        = 19, 
00085   UART0_RX_IRQn         = 20, 
00086   UART0_TX_IRQn         = 21, 
00087   UART1_RX_IRQn         = 22, 
00088   UART1_TX_IRQn         = 23, 
00089   LEUART0_IRQn          = 24, 
00090   LEUART1_IRQn          = 25, 
00091   LETIMER0_IRQn         = 26, 
00092   PCNT0_IRQn            = 27, 
00093   PCNT1_IRQn            = 28, 
00094   PCNT2_IRQn            = 29, 
00095   RTC_IRQn              = 30, 
00096   BURTC_IRQn            = 31, 
00097   CMU_IRQn              = 32, 
00098   VCMP_IRQn             = 33, 
00099   LCD_IRQn              = 34, 
00100   MSC_IRQn              = 35, 
00101   AES_IRQn              = 36, 
00102   EBI_IRQn              = 37, 
00103   EMU_IRQn              = 38, 
00104 } IRQn_Type;
00105 
00106 /**************************************************************************/
00111 #define __MPU_PRESENT             1 
00112 #define __NVIC_PRIO_BITS          3 
00113 #define __Vendor_SysTickConfig    0 
00117 /**************************************************************************/
00123 #define _EFM32_GIANT_FAMILY    1 
00124 #define _EFM_DEVICE              
00126 /* If part number is not defined as compiler option, define it */
00127 #if !defined(EFM32GG890F1024)
00128 #define EFM32GG890F1024    1 
00129 #endif
00130 
00132 #define PART_NUMBER          "EFM32GG890F1024" 
00135 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00136 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00137 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00138 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00139 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00140 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00141 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00142 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00143 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL) 
00144 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)    
00145 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL) 
00146 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)       
00147 #define EBI_CODE_MEM_BASE    ((uint32_t) 0x12000000UL) 
00148 #define EBI_CODE_MEM_SIZE    ((uint32_t) 0xE000000UL)  
00149 #define EBI_CODE_MEM_END     ((uint32_t) 0x1FFFFFFFUL) 
00150 #define EBI_CODE_MEM_BITS    ((uint32_t) 0x28UL)       
00151 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00152 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00153 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00154 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00155 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00156 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00157 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00158 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00159 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00160 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00161 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00162 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00163 #define EBI_MEM_BASE         ((uint32_t) 0x80000000UL) 
00164 #define EBI_MEM_SIZE         ((uint32_t) 0x40000000UL) 
00165 #define EBI_MEM_END          ((uint32_t) 0xBFFFFFFFUL) 
00166 #define EBI_MEM_BITS         ((uint32_t) 0x30UL)       
00169 #define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL) 
00170 #define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL) 
00173 #define FLASH_BASE           (0x00000000UL) 
00174 #define FLASH_SIZE           (0x00100000UL) 
00175 #define FLASH_PAGE_SIZE      4096           
00176 #define SRAM_BASE            (0x20000000UL) 
00177 #define SRAM_SIZE            (0x00020000UL) 
00178 #define __CM3_REV            0x201          
00179 #define PRS_CHAN_COUNT       12             
00180 #define DMA_CHAN_COUNT       12             
00183 #define AFCHAN_MAX           163
00184 #define AFCHANLOC_MAX        7
00185 
00186 #define AFACHAN_MAX          53
00187 
00188 /* Part number capabilities */
00189 
00190 #define LETIMER_PRESENT       
00191 #define LETIMER_COUNT       1 
00192 #define USART_PRESENT         
00193 #define USART_COUNT         3 
00194 #define UART_PRESENT          
00195 #define UART_COUNT          2 
00196 #define TIMER_PRESENT         
00197 #define TIMER_COUNT         4 
00198 #define ACMP_PRESENT          
00199 #define ACMP_COUNT          2 
00200 #define I2C_PRESENT           
00201 #define I2C_COUNT           2 
00202 #define LEUART_PRESENT        
00203 #define LEUART_COUNT        2 
00204 #define PCNT_PRESENT          
00205 #define PCNT_COUNT          3 
00206 #define ADC_PRESENT           
00207 #define ADC_COUNT           1 
00208 #define DAC_PRESENT           
00209 #define DAC_COUNT           1 
00210 #define DMA_PRESENT
00211 #define DMA_COUNT           1
00212 #define AES_PRESENT
00213 #define AES_COUNT           1
00214 #define LE_PRESENT
00215 #define LE_COUNT            1
00216 #define MSC_PRESENT
00217 #define MSC_COUNT           1
00218 #define EMU_PRESENT
00219 #define EMU_COUNT           1
00220 #define RMU_PRESENT
00221 #define RMU_COUNT           1
00222 #define CMU_PRESENT
00223 #define CMU_COUNT           1
00224 #define LESENSE_PRESENT
00225 #define LESENSE_COUNT       1
00226 #define RTC_PRESENT
00227 #define RTC_COUNT           1
00228 #define EBI_PRESENT
00229 #define EBI_COUNT           1
00230 #define GPIO_PRESENT
00231 #define GPIO_COUNT          1
00232 #define VCMP_PRESENT
00233 #define VCMP_COUNT          1
00234 #define PRS_PRESENT
00235 #define PRS_COUNT           1
00236 #define OPAMP_PRESENT
00237 #define OPAMP_COUNT         1
00238 #define BU_PRESENT
00239 #define BU_COUNT            1
00240 #define LCD_PRESENT
00241 #define LCD_COUNT           1
00242 #define BURTC_PRESENT
00243 #define BURTC_COUNT         1
00244 #define HFXTAL_PRESENT
00245 #define HFXTAL_COUNT        1
00246 #define LFXTAL_PRESENT
00247 #define LFXTAL_COUNT        1
00248 #define WDOG_PRESENT
00249 #define WDOG_COUNT          1
00250 #define DBG_PRESENT
00251 #define DBG_COUNT           1
00252 #define ETM_PRESENT
00253 #define ETM_COUNT           1
00254 #define BOOTLOADER_PRESENT
00255 #define BOOTLOADER_COUNT    1
00256 #define ANALOG_PRESENT
00257 #define ANALOG_COUNT        1
00258 
00259 #include "core_cm3.h"       /* Cortex-M3 processor and core peripherals */
00260 #include "system_efm32gg.h" /* System Header */
00261 
00264 /**************************************************************************/
00270 #include "efm32gg_dma_ch.h"
00271 #include "efm32gg_dma.h"
00272 #include "efm32gg_aes.h"
00273 #include "efm32gg_msc.h"
00274 #include "efm32gg_emu.h"
00275 #include "efm32gg_rmu.h"
00276 
00277 /**************************************************************************/
00282 typedef struct
00283 {
00284   __IO uint32_t CTRL;         
00285   __IO uint32_t HFCORECLKDIV; 
00286   __IO uint32_t HFPERCLKDIV;  
00287   __IO uint32_t HFRCOCTRL;    
00288   __IO uint32_t LFRCOCTRL;    
00289   __IO uint32_t AUXHFRCOCTRL; 
00290   __IO uint32_t CALCTRL;      
00291   __IO uint32_t CALCNT;       
00292   __IO uint32_t OSCENCMD;     
00293   __IO uint32_t CMD;          
00294   __IO uint32_t LFCLKSEL;     
00295   __I uint32_t  STATUS;       
00296   __I uint32_t  IF;           
00297   __IO uint32_t IFS;          
00298   __IO uint32_t IFC;          
00299   __IO uint32_t IEN;          
00300   __IO uint32_t HFCORECLKEN0; 
00301   __IO uint32_t HFPERCLKEN0;  
00302   uint32_t      RESERVED0[2]; 
00303   __I uint32_t  SYNCBUSY;     
00304   __IO uint32_t FREEZE;       
00305   __IO uint32_t LFACLKEN0;    
00306   uint32_t      RESERVED1[1]; 
00307   __IO uint32_t LFBCLKEN0;    
00308   uint32_t      RESERVED2[1]; 
00309   __IO uint32_t LFAPRESC0;    
00310   uint32_t      RESERVED3[1]; 
00311   __IO uint32_t LFBPRESC0;    
00312   uint32_t      RESERVED4[1]; 
00313   __IO uint32_t PCNTCTRL;     
00314   __IO uint32_t LCDCTRL;      
00315   __IO uint32_t ROUTE;        
00316   __IO uint32_t LOCK;         
00317 } CMU_TypeDef;                
00319 #include "efm32gg_lesense_st.h"
00320 #include "efm32gg_lesense_buf.h"
00321 #include "efm32gg_lesense_ch.h"
00322 #include "efm32gg_lesense.h"
00323 #include "efm32gg_rtc.h"
00324 #include "efm32gg_letimer.h"
00325 #include "efm32gg_ebi.h"
00326 #include "efm32gg_usart.h"
00327 #include "efm32gg_timer_cc.h"
00328 #include "efm32gg_timer.h"
00329 #include "efm32gg_acmp.h"
00330 #include "efm32gg_i2c.h"
00331 #include "efm32gg_gpio_p.h"
00332 #include "efm32gg_gpio.h"
00333 #include "efm32gg_vcmp.h"
00334 #include "efm32gg_prs_ch.h"
00335 
00336 /**************************************************************************/
00341 typedef struct
00342 {
00343   __IO uint32_t  SWPULSE;      
00344   __IO uint32_t  SWLEVEL;      
00345   __IO uint32_t  ROUTE;        
00347   uint32_t       RESERVED0[1]; 
00349   PRS_CH_TypeDef CH[12];       
00350 } PRS_TypeDef;                 
00352 #include "efm32gg_leuart.h"
00353 #include "efm32gg_pcnt.h"
00354 #include "efm32gg_adc.h"
00355 #include "efm32gg_dac.h"
00356 #include "efm32gg_lcd.h"
00357 #include "efm32gg_burtc_ret.h"
00358 #include "efm32gg_burtc.h"
00359 #include "efm32gg_wdog.h"
00360 #include "efm32gg_etm.h"
00361 #include "efm32gg_dma_descriptor.h"
00362 #include "efm32gg_devinfo.h"
00363 #include "efm32gg_romtable.h"
00364 #include "efm32gg_calibrate.h"
00365 
00368 /**************************************************************************/
00373 #define DMA_BASE          (0x400C2000UL) 
00374 #define AES_BASE          (0x400E0000UL) 
00375 #define MSC_BASE          (0x400C0000UL) 
00376 #define EMU_BASE          (0x400C6000UL) 
00377 #define RMU_BASE          (0x400CA000UL) 
00378 #define CMU_BASE          (0x400C8000UL) 
00379 #define LESENSE_BASE      (0x4008C000UL) 
00380 #define RTC_BASE          (0x40080000UL) 
00381 #define LETIMER0_BASE     (0x40082000UL) 
00382 #define EBI_BASE          (0x40008000UL) 
00383 #define USART0_BASE       (0x4000C000UL) 
00384 #define USART1_BASE       (0x4000C400UL) 
00385 #define USART2_BASE       (0x4000C800UL) 
00386 #define UART0_BASE        (0x4000E000UL) 
00387 #define UART1_BASE        (0x4000E400UL) 
00388 #define TIMER0_BASE       (0x40010000UL) 
00389 #define TIMER1_BASE       (0x40010400UL) 
00390 #define TIMER2_BASE       (0x40010800UL) 
00391 #define TIMER3_BASE       (0x40010C00UL) 
00392 #define ACMP0_BASE        (0x40001000UL) 
00393 #define ACMP1_BASE        (0x40001400UL) 
00394 #define I2C0_BASE         (0x4000A000UL) 
00395 #define I2C1_BASE         (0x4000A400UL) 
00396 #define GPIO_BASE         (0x40006000UL) 
00397 #define VCMP_BASE         (0x40000000UL) 
00398 #define PRS_BASE          (0x400CC000UL) 
00399 #define LEUART0_BASE      (0x40084000UL) 
00400 #define LEUART1_BASE      (0x40084400UL) 
00401 #define PCNT0_BASE        (0x40086000UL) 
00402 #define PCNT1_BASE        (0x40086400UL) 
00403 #define PCNT2_BASE        (0x40086800UL) 
00404 #define ADC0_BASE         (0x40002000UL) 
00405 #define DAC0_BASE         (0x40004000UL) 
00406 #define LCD_BASE          (0x4008A000UL) 
00407 #define BURTC_BASE        (0x40081000UL) 
00408 #define WDOG_BASE         (0x40088000UL) 
00409 #define ETM_BASE          (0xE0041000UL) 
00410 #define CALIBRATE_BASE    (0x0FE08000UL) 
00411 #define DEVINFO_BASE      (0x0FE081B0UL) 
00412 #define ROMTABLE_BASE     (0xE00FFFD0UL) 
00413 #define LOCKBITS_BASE     (0x0FE04000UL) 
00414 #define USERDATA_BASE     (0x0FE00000UL) 
00418 /**************************************************************************/
00423 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00424 #define AES          ((AES_TypeDef *) AES_BASE)             
00425 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00426 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00427 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00428 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00429 #define LESENSE      ((LESENSE_TypeDef *) LESENSE_BASE)     
00430 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00431 #define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    
00432 #define EBI          ((EBI_TypeDef *) EBI_BASE)             
00433 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00434 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00435 #define USART2       ((USART_TypeDef *) USART2_BASE)        
00436 #define UART0        ((USART_TypeDef *) UART0_BASE)         
00437 #define UART1        ((USART_TypeDef *) UART1_BASE)         
00438 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00439 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00440 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        
00441 #define TIMER3       ((TIMER_TypeDef *) TIMER3_BASE)        
00442 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00443 #define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          
00444 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00445 #define I2C1         ((I2C_TypeDef *) I2C1_BASE)            
00446 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00447 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00448 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00449 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00450 #define LEUART1      ((LEUART_TypeDef *) LEUART1_BASE)      
00451 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00452 #define PCNT1        ((PCNT_TypeDef *) PCNT1_BASE)          
00453 #define PCNT2        ((PCNT_TypeDef *) PCNT2_BASE)          
00454 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
00455 #define DAC0         ((DAC_TypeDef *) DAC0_BASE)            
00456 #define LCD          ((LCD_TypeDef *) LCD_BASE)             
00457 #define BURTC        ((BURTC_TypeDef *) BURTC_BASE)         
00458 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00459 #define ETM          ((ETM_TypeDef *) ETM_BASE)             
00460 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00461 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00462 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00466 /**************************************************************************/
00471 /**************************************************************************/
00477 #define PRS_VCMP_OUT             ((1 << 16) + 0)  
00478 #define PRS_ACMP0_OUT            ((2 << 16) + 0)  
00479 #define PRS_ACMP1_OUT            ((3 << 16) + 0)  
00480 #define PRS_DAC0_CH0             ((6 << 16) + 0)  
00481 #define PRS_DAC0_CH1             ((6 << 16) + 1)  
00482 #define PRS_ADC0_SINGLE          ((8 << 16) + 0)  
00483 #define PRS_ADC0_SCAN            ((8 << 16) + 1)  
00484 #define PRS_USART0_IRTX          ((16 << 16) + 0) 
00485 #define PRS_USART0_TXC           ((16 << 16) + 1) 
00486 #define PRS_USART0_RXDATAV       ((16 << 16) + 2) 
00487 #define PRS_USART1_TXC           ((17 << 16) + 1) 
00488 #define PRS_USART1_RXDATAV       ((17 << 16) + 2) 
00489 #define PRS_USART2_TXC           ((18 << 16) + 1) 
00490 #define PRS_USART2_RXDATAV       ((18 << 16) + 2) 
00491 #define PRS_TIMER0_UF            ((28 << 16) + 0) 
00492 #define PRS_TIMER0_OF            ((28 << 16) + 1) 
00493 #define PRS_TIMER0_CC0           ((28 << 16) + 2) 
00494 #define PRS_TIMER0_CC1           ((28 << 16) + 3) 
00495 #define PRS_TIMER0_CC2           ((28 << 16) + 4) 
00496 #define PRS_TIMER1_UF            ((29 << 16) + 0) 
00497 #define PRS_TIMER1_OF            ((29 << 16) + 1) 
00498 #define PRS_TIMER1_CC0           ((29 << 16) + 2) 
00499 #define PRS_TIMER1_CC1           ((29 << 16) + 3) 
00500 #define PRS_TIMER1_CC2           ((29 << 16) + 4) 
00501 #define PRS_TIMER2_UF            ((30 << 16) + 0) 
00502 #define PRS_TIMER2_OF            ((30 << 16) + 1) 
00503 #define PRS_TIMER2_CC0           ((30 << 16) + 2) 
00504 #define PRS_TIMER2_CC1           ((30 << 16) + 3) 
00505 #define PRS_TIMER2_CC2           ((30 << 16) + 4) 
00506 #define PRS_TIMER3_UF            ((31 << 16) + 0) 
00507 #define PRS_TIMER3_OF            ((31 << 16) + 1) 
00508 #define PRS_TIMER3_CC0           ((31 << 16) + 2) 
00509 #define PRS_TIMER3_CC1           ((31 << 16) + 3) 
00510 #define PRS_TIMER3_CC2           ((31 << 16) + 4) 
00511 #define PRS_RTC_OF               ((40 << 16) + 0) 
00512 #define PRS_RTC_COMP0            ((40 << 16) + 1) 
00513 #define PRS_RTC_COMP1            ((40 << 16) + 2) 
00514 #define PRS_UART0_TXC            ((41 << 16) + 1) 
00515 #define PRS_UART0_RXDATAV        ((41 << 16) + 2) 
00516 #define PRS_UART1_TXC            ((42 << 16) + 1) 
00517 #define PRS_UART1_RXDATAV        ((42 << 16) + 2) 
00518 #define PRS_GPIO_PIN0            ((48 << 16) + 0) 
00519 #define PRS_GPIO_PIN1            ((48 << 16) + 1) 
00520 #define PRS_GPIO_PIN2            ((48 << 16) + 2) 
00521 #define PRS_GPIO_PIN3            ((48 << 16) + 3) 
00522 #define PRS_GPIO_PIN4            ((48 << 16) + 4) 
00523 #define PRS_GPIO_PIN5            ((48 << 16) + 5) 
00524 #define PRS_GPIO_PIN6            ((48 << 16) + 6) 
00525 #define PRS_GPIO_PIN7            ((48 << 16) + 7) 
00526 #define PRS_GPIO_PIN8            ((49 << 16) + 0) 
00527 #define PRS_GPIO_PIN9            ((49 << 16) + 1) 
00528 #define PRS_GPIO_PIN10           ((49 << 16) + 2) 
00529 #define PRS_GPIO_PIN11           ((49 << 16) + 3) 
00530 #define PRS_GPIO_PIN12           ((49 << 16) + 4) 
00531 #define PRS_GPIO_PIN13           ((49 << 16) + 5) 
00532 #define PRS_GPIO_PIN14           ((49 << 16) + 6) 
00533 #define PRS_GPIO_PIN15           ((49 << 16) + 7) 
00534 #define PRS_LETIMER0_CH0         ((52 << 16) + 0) 
00535 #define PRS_LETIMER0_CH1         ((52 << 16) + 1) 
00536 #define PRS_BURTC_OF             ((55 << 16) + 0) 
00537 #define PRS_BURTC_COMP0          ((55 << 16) + 1) 
00538 #define PRS_LESENSE_SCANRES0     ((57 << 16) + 0) 
00539 #define PRS_LESENSE_SCANRES1     ((57 << 16) + 1) 
00540 #define PRS_LESENSE_SCANRES2     ((57 << 16) + 2) 
00541 #define PRS_LESENSE_SCANRES3     ((57 << 16) + 3) 
00542 #define PRS_LESENSE_SCANRES4     ((57 << 16) + 4) 
00543 #define PRS_LESENSE_SCANRES5     ((57 << 16) + 5) 
00544 #define PRS_LESENSE_SCANRES6     ((57 << 16) + 6) 
00545 #define PRS_LESENSE_SCANRES7     ((57 << 16) + 7) 
00546 #define PRS_LESENSE_SCANRES8     ((58 << 16) + 0) 
00547 #define PRS_LESENSE_SCANRES9     ((58 << 16) + 1) 
00548 #define PRS_LESENSE_SCANRES10    ((58 << 16) + 2) 
00549 #define PRS_LESENSE_SCANRES11    ((58 << 16) + 3) 
00550 #define PRS_LESENSE_SCANRES12    ((58 << 16) + 4) 
00551 #define PRS_LESENSE_SCANRES13    ((58 << 16) + 5) 
00552 #define PRS_LESENSE_SCANRES14    ((58 << 16) + 6) 
00553 #define PRS_LESENSE_SCANRES15    ((58 << 16) + 7) 
00554 #define PRS_LESENSE_DEC0         ((59 << 16) + 0) 
00555 #define PRS_LESENSE_DEC1         ((59 << 16) + 1) 
00556 #define PRS_LESENSE_DEC2         ((59 << 16) + 2) 
00560 #include "efm32gg_dmareq.h"
00561 #include "efm32gg_dmactrl.h"
00562 #include "efm32gg_uart.h"
00563 
00564 /**************************************************************************/
00569 /* Bit fields for CMU CTRL */
00570 #define _CMU_CTRL_RESETVALUE                        0x000C062CUL                                
00571 #define _CMU_CTRL_MASK                              0x53FFFEEFUL                                
00572 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           
00573 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       
00574 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                
00575 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                                
00576 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                                
00577 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                                
00578 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)           
00579 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)              
00580 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)         
00581 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)         
00582 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                           
00583 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                       
00584 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                                
00585 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                                
00586 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                                
00587 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                                
00588 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                                
00589 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)          
00590 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)          
00591 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)          
00592 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)          
00593 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)         
00594 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                           
00595 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                      
00596 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                                
00597 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ         0x00000001UL                                
00598 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ        0x00000003UL                                
00599 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)         
00600 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ          (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)  
00601 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ         (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) 
00602 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                                
00603 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                           
00604 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                      
00605 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                                
00606 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)    
00607 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                           
00608 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                     
00609 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                                
00610 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                                
00611 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                                
00612 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                                
00613 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                                
00614 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)        
00615 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)      
00616 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)       
00617 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)        
00618 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)      
00619 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                          
00620 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                    
00621 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                                
00622 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                                
00623 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                                
00624 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                                
00625 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)          
00626 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)             
00627 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)        
00628 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)        
00629 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                               
00630 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                          
00631 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                    
00632 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                                
00633 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                                
00634 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                                
00635 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)         
00636 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)         
00637 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)        
00638 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                          
00639 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                   
00640 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                                
00641 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)          
00642 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                               
00643 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                          
00644 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                   
00645 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                                
00646 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)        
00647 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                          
00648 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                   
00649 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                                
00650 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                                
00651 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                                
00652 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                                
00653 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                                
00654 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)       
00655 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)      
00656 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)     
00657 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)       
00658 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)     
00659 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                          
00660 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                                  
00661 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                                
00662 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                                
00663 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                                
00664 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                                
00665 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                                
00666 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                                
00667 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                                
00668 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                                
00669 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                                
00670 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)        
00671 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)          
00672 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)           
00673 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)         
00674 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)         
00675 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)         
00676 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)        
00677 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         
00678 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       
00679 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          
00680 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 
00681 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                
00682 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                
00683 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                
00684 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                                
00685 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                                
00686 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                                
00687 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                                
00688 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                                
00689 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                                
00690 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)        
00691 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)          
00692 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)           
00693 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)          
00694 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)          
00695 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)          
00696 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)         
00697 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)         
00698 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)      
00699 #define CMU_CTRL_DBGCLK                             (0x1UL << 28)                               
00700 #define _CMU_CTRL_DBGCLK_SHIFT                      28                                          
00701 #define _CMU_CTRL_DBGCLK_MASK                       0x10000000UL                                
00702 #define _CMU_CTRL_DBGCLK_DEFAULT                    0x00000000UL                                
00703 #define _CMU_CTRL_DBGCLK_AUXHFRCO                   0x00000000UL                                
00704 #define _CMU_CTRL_DBGCLK_HFCLK                      0x00000001UL                                
00705 #define CMU_CTRL_DBGCLK_DEFAULT                     (_CMU_CTRL_DBGCLK_DEFAULT << 28)            
00706 #define CMU_CTRL_DBGCLK_AUXHFRCO                    (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)           
00707 #define CMU_CTRL_DBGCLK_HFCLK                       (_CMU_CTRL_DBGCLK_HFCLK << 28)              
00708 #define CMU_CTRL_HFLE                               (0x1UL << 30)                               
00709 #define _CMU_CTRL_HFLE_SHIFT                        30                                          
00710 #define _CMU_CTRL_HFLE_MASK                         0x40000000UL                                
00711 #define _CMU_CTRL_HFLE_DEFAULT                      0x00000000UL                                
00712 #define CMU_CTRL_HFLE_DEFAULT                       (_CMU_CTRL_HFLE_DEFAULT << 30)              
00714 /* Bit fields for CMU HFCORECLKDIV */
00715 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
00716 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
00717 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
00718 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
00719 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
00720 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
00721 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
00722 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
00723 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
00724 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
00725 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
00726 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
00727 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
00728 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
00729 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
00730 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
00731 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
00732 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
00733 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
00734 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
00735 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
00736 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
00737 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
00738 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
00739 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
00740 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
00741 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
00742 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
00743 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
00744 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
00745 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
00746 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
00747 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
00748 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
00749 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
00751 /* Bit fields for CMU HFPERCLKDIV */
00752 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
00753 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
00754 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
00755 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
00756 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
00757 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
00758 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
00759 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
00760 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
00761 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
00762 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
00763 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
00764 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
00765 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
00766 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
00767 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
00768 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
00769 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
00770 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
00771 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
00772 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
00773 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
00774 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
00775 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
00776 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
00777 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
00778 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
00779 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
00780 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
00781 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
00782 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
00784 /* Bit fields for CMU HFRCOCTRL */
00785 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
00786 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
00787 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
00788 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
00789 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
00790 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
00791 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
00792 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
00793 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
00794 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
00795 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
00796 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
00797 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
00798 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
00799 #define _CMU_HFRCOCTRL_BAND_28MHZ                   0x00000005UL                           
00800 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
00801 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
00802 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
00803 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
00804 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
00805 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
00806 #define CMU_HFRCOCTRL_BAND_28MHZ                    (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       
00807 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
00808 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
00809 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
00810 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
00812 /* Bit fields for CMU LFRCOCTRL */
00813 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
00814 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
00815 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
00816 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
00817 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
00818 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
00820 /* Bit fields for CMU AUXHFRCOCTRL */
00821 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
00822 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
00823 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
00824 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
00825 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
00826 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
00827 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
00828 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
00829 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
00830 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
00831 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
00832 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
00833 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
00834 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ                0x00000006UL                            
00835 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
00836 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
00837 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
00838 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
00839 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
00840 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
00841 #define CMU_AUXHFRCOCTRL_BAND_28MHZ                 (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)     
00842 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
00844 /* Bit fields for CMU CALCTRL */
00845 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
00846 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
00847 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
00848 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
00849 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
00850 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
00851 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
00852 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
00853 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
00854 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
00855 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
00856 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
00857 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
00858 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
00859 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
00860 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
00861 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
00862 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
00863 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
00864 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
00865 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
00866 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
00867 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
00868 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
00869 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
00870 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
00871 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
00872 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
00873 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
00874 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
00875 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
00876 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
00877 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
00878 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
00879 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
00880 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
00881 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
00883 /* Bit fields for CMU CALCNT */
00884 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
00885 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
00886 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
00887 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
00888 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
00889 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
00891 /* Bit fields for CMU OSCENCMD */
00892 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
00893 #define _CMU_OSCENCMD_MASK                          0x000003FFUL                             
00894 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
00895 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
00896 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
00897 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
00898 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
00899 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
00900 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
00901 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
00902 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
00903 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
00904 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
00905 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
00906 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
00907 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
00908 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
00909 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
00910 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
00911 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
00912 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
00913 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
00914 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
00915 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
00916 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
00917 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
00918 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
00919 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
00920 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
00921 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
00922 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
00923 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
00924 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
00925 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
00926 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
00927 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
00928 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
00929 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
00930 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
00931 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
00932 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
00933 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
00934 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
00935 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
00936 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
00937 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
00938 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
00939 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
00940 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
00941 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
00942 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
00943 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
00945 /* Bit fields for CMU CMD */
00946 #define _CMU_CMD_RESETVALUE                         0x00000000UL                     
00947 #define _CMU_CMD_MASK                               0x0000001FUL                     
00948 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                
00949 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                            
00950 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                     
00951 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                     
00952 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                     
00953 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                     
00954 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                     
00955 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0) 
00956 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)   
00957 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)    
00958 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)   
00959 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)    
00960 #define CMU_CMD_CALSTART                            (0x1UL << 3)                     
00961 #define _CMU_CMD_CALSTART_SHIFT                     3                                
00962 #define _CMU_CMD_CALSTART_MASK                      0x8UL                            
00963 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                     
00964 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3) 
00965 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                     
00966 #define _CMU_CMD_CALSTOP_SHIFT                      4                                
00967 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                           
00968 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                     
00969 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)  
00971 /* Bit fields for CMU LFCLKSEL */
00972 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             
00973 #define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             
00974 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
00975 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
00976 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
00977 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
00978 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
00979 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
00980 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
00981 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
00982 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
00983 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
00984 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
00985 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
00986 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
00987 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
00988 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
00989 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
00990 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
00991 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
00992 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
00993 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
00994 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
00995 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
00996 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
00997 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
00998 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
00999 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
01000 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
01001 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
01002 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
01003 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
01004 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
01005 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
01006 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
01007 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
01008 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
01009 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
01010 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
01011 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
01012 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
01013 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
01014 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
01015 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
01017 /* Bit fields for CMU STATUS */
01018 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                           
01019 #define _CMU_STATUS_MASK                            0x00007FFFUL                           
01020 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                           
01021 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                      
01022 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                  
01023 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                           
01024 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)    
01025 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                           
01026 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                      
01027 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                  
01028 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                           
01029 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)    
01030 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                           
01031 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                      
01032 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                  
01033 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                           
01034 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)     
01035 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                           
01036 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                      
01037 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                  
01038 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                           
01039 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)     
01040 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                           
01041 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                      
01042 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                 
01043 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                           
01044 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) 
01045 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                           
01046 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                      
01047 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                 
01048 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                           
01049 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) 
01050 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                           
01051 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                      
01052 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                 
01053 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                           
01054 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)    
01055 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                           
01056 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                      
01057 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                 
01058 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                           
01059 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)    
01060 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                           
01061 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                      
01062 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                
01063 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                           
01064 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)     
01065 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                           
01066 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                      
01067 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                
01068 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                           
01069 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)     
01070 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                          
01071 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                     
01072 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                
01073 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                           
01074 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)   
01075 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                          
01076 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                     
01077 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                
01078 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                           
01079 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)    
01080 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                          
01081 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                     
01082 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                               
01083 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                           
01084 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)   
01085 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                          
01086 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                     
01087 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                               
01088 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                           
01089 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)    
01090 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                          
01091 #define _CMU_STATUS_CALBSY_SHIFT                    14                                     
01092 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                               
01093 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                           
01094 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)     
01096 /* Bit fields for CMU IF */
01097 #define _CMU_IF_RESETVALUE                          0x00000001UL                       
01098 #define _CMU_IF_MASK                                0x0000007FUL                       
01099 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                       
01100 #define _CMU_IF_HFRCORDY_SHIFT                      0                                  
01101 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                              
01102 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                       
01103 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)    
01104 #define CMU_IF_HFXORDY                              (0x1UL << 1)                       
01105 #define _CMU_IF_HFXORDY_SHIFT                       1                                  
01106 #define _CMU_IF_HFXORDY_MASK                        0x2UL                              
01107 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                       
01108 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)     
01109 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                       
01110 #define _CMU_IF_LFRCORDY_SHIFT                      2                                  
01111 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                              
01112 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                       
01113 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)    
01114 #define CMU_IF_LFXORDY                              (0x1UL << 3)                       
01115 #define _CMU_IF_LFXORDY_SHIFT                       3                                  
01116 #define _CMU_IF_LFXORDY_MASK                        0x8UL                              
01117 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                       
01118 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)     
01119 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                       
01120 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                  
01121 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                             
01122 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                       
01123 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
01124 #define CMU_IF_CALRDY                               (0x1UL << 5)                       
01125 #define _CMU_IF_CALRDY_SHIFT                        5                                  
01126 #define _CMU_IF_CALRDY_MASK                         0x20UL                             
01127 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                       
01128 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)      
01129 #define CMU_IF_CALOF                                (0x1UL << 6)                       
01130 #define _CMU_IF_CALOF_SHIFT                         6                                  
01131 #define _CMU_IF_CALOF_MASK                          0x40UL                             
01132 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                       
01133 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)       
01135 /* Bit fields for CMU IFS */
01136 #define _CMU_IFS_RESETVALUE                         0x00000000UL                        
01137 #define _CMU_IFS_MASK                               0x0000007FUL                        
01138 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                        
01139 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                   
01140 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                               
01141 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                        
01142 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
01143 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                        
01144 #define _CMU_IFS_HFXORDY_SHIFT                      1                                   
01145 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                               
01146 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                        
01147 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)     
01148 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                        
01149 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                   
01150 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                               
01151 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                        
01152 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
01153 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                        
01154 #define _CMU_IFS_LFXORDY_SHIFT                      3                                   
01155 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                               
01156 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                        
01157 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)     
01158 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                        
01159 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                   
01160 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                              
01161 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01162 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
01163 #define CMU_IFS_CALRDY                              (0x1UL << 5)                        
01164 #define _CMU_IFS_CALRDY_SHIFT                       5                                   
01165 #define _CMU_IFS_CALRDY_MASK                        0x20UL                              
01166 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                        
01167 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)      
01168 #define CMU_IFS_CALOF                               (0x1UL << 6)                        
01169 #define _CMU_IFS_CALOF_SHIFT                        6                                   
01170 #define _CMU_IFS_CALOF_MASK                         0x40UL                              
01171 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                        
01172 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)       
01174 /* Bit fields for CMU IFC */
01175 #define _CMU_IFC_RESETVALUE                         0x00000000UL                        
01176 #define _CMU_IFC_MASK                               0x0000007FUL                        
01177 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                        
01178 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                   
01179 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                               
01180 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                        
01181 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
01182 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                        
01183 #define _CMU_IFC_HFXORDY_SHIFT                      1                                   
01184 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                               
01185 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                        
01186 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)     
01187 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                        
01188 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                   
01189 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                               
01190 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                        
01191 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
01192 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                        
01193 #define _CMU_IFC_LFXORDY_SHIFT                      3                                   
01194 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                               
01195 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                        
01196 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)     
01197 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                        
01198 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                   
01199 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                              
01200 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01201 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
01202 #define CMU_IFC_CALRDY                              (0x1UL << 5)                        
01203 #define _CMU_IFC_CALRDY_SHIFT                       5                                   
01204 #define _CMU_IFC_CALRDY_MASK                        0x20UL                              
01205 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                        
01206 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)      
01207 #define CMU_IFC_CALOF                               (0x1UL << 6)                        
01208 #define _CMU_IFC_CALOF_SHIFT                        6                                   
01209 #define _CMU_IFC_CALOF_MASK                         0x40UL                              
01210 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                        
01211 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)       
01213 /* Bit fields for CMU IEN */
01214 #define _CMU_IEN_RESETVALUE                         0x00000000UL                        
01215 #define _CMU_IEN_MASK                               0x0000007FUL                        
01216 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                        
01217 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                   
01218 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                               
01219 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                        
01220 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
01221 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                        
01222 #define _CMU_IEN_HFXORDY_SHIFT                      1                                   
01223 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                               
01224 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                        
01225 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)     
01226 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                        
01227 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                   
01228 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                               
01229 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                        
01230 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
01231 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                        
01232 #define _CMU_IEN_LFXORDY_SHIFT                      3                                   
01233 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                               
01234 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                        
01235 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)     
01236 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                        
01237 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                   
01238 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                              
01239 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01240 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
01241 #define CMU_IEN_CALRDY                              (0x1UL << 5)                        
01242 #define _CMU_IEN_CALRDY_SHIFT                       5                                   
01243 #define _CMU_IEN_CALRDY_MASK                        0x20UL                              
01244 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                        
01245 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)      
01246 #define CMU_IEN_CALOF                               (0x1UL << 6)                        
01247 #define _CMU_IEN_CALOF_SHIFT                        6                                   
01248 #define _CMU_IEN_CALOF_MASK                         0x40UL                              
01249 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                        
01250 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)       
01252 /* Bit fields for CMU HFCORECLKEN0 */
01253 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                         
01254 #define _CMU_HFCORECLKEN0_MASK                      0x00000033UL                         
01255 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 0)                         
01256 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 0                                    
01257 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x1UL                                
01258 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                         
01259 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) 
01260 #define CMU_HFCORECLKEN0_AES                        (0x1UL << 1)                         
01261 #define _CMU_HFCORECLKEN0_AES_SHIFT                 1                                    
01262 #define _CMU_HFCORECLKEN0_AES_MASK                  0x2UL                                
01263 #define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                         
01264 #define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) 
01265 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 4)                         
01266 #define _CMU_HFCORECLKEN0_LE_SHIFT                  4                                    
01267 #define _CMU_HFCORECLKEN0_LE_MASK                   0x10UL                               
01268 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                         
01269 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)  
01270 #define CMU_HFCORECLKEN0_EBI                        (0x1UL << 5)                         
01271 #define _CMU_HFCORECLKEN0_EBI_SHIFT                 5                                    
01272 #define _CMU_HFCORECLKEN0_EBI_MASK                  0x20UL                               
01273 #define _CMU_HFCORECLKEN0_EBI_DEFAULT               0x00000000UL                         
01274 #define CMU_HFCORECLKEN0_EBI_DEFAULT                (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) 
01276 /* Bit fields for CMU HFPERCLKEN0 */
01277 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
01278 #define _CMU_HFPERCLKEN0_MASK                       0x0003FFFFUL                           
01279 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 0)                           
01280 #define _CMU_HFPERCLKEN0_USART0_SHIFT               0                                      
01281 #define _CMU_HFPERCLKEN0_USART0_MASK                0x1UL                                  
01282 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
01283 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) 
01284 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 1)                           
01285 #define _CMU_HFPERCLKEN0_USART1_SHIFT               1                                      
01286 #define _CMU_HFPERCLKEN0_USART1_MASK                0x2UL                                  
01287 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
01288 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) 
01289 #define CMU_HFPERCLKEN0_USART2                      (0x1UL << 2)                           
01290 #define _CMU_HFPERCLKEN0_USART2_SHIFT               2                                      
01291 #define _CMU_HFPERCLKEN0_USART2_MASK                0x4UL                                  
01292 #define _CMU_HFPERCLKEN0_USART2_DEFAULT             0x00000000UL                           
01293 #define CMU_HFPERCLKEN0_USART2_DEFAULT              (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) 
01294 #define CMU_HFPERCLKEN0_UART0                       (0x1UL << 3)                           
01295 #define _CMU_HFPERCLKEN0_UART0_SHIFT                3                                      
01296 #define _CMU_HFPERCLKEN0_UART0_MASK                 0x8UL                                  
01297 #define _CMU_HFPERCLKEN0_UART0_DEFAULT              0x00000000UL                           
01298 #define CMU_HFPERCLKEN0_UART0_DEFAULT               (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)  
01299 #define CMU_HFPERCLKEN0_UART1                       (0x1UL << 4)                           
01300 #define _CMU_HFPERCLKEN0_UART1_SHIFT                4                                      
01301 #define _CMU_HFPERCLKEN0_UART1_MASK                 0x10UL                                 
01302 #define _CMU_HFPERCLKEN0_UART1_DEFAULT              0x00000000UL                           
01303 #define CMU_HFPERCLKEN0_UART1_DEFAULT               (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4)  
01304 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 5)                           
01305 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               5                                      
01306 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x20UL                                 
01307 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
01308 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) 
01309 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 6)                           
01310 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               6                                      
01311 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x40UL                                 
01312 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
01313 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) 
01314 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 7)                           
01315 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               7                                      
01316 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x80UL                                 
01317 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
01318 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) 
01319 #define CMU_HFPERCLKEN0_TIMER3                      (0x1UL << 8)                           
01320 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT               8                                      
01321 #define _CMU_HFPERCLKEN0_TIMER3_MASK                0x100UL                                
01322 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT             0x00000000UL                           
01323 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT              (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) 
01324 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 9)                           
01325 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                9                                      
01326 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x200UL                                
01327 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
01328 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)  
01329 #define CMU_HFPERCLKEN0_ACMP1                       (0x1UL << 10)                          
01330 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT                10                                     
01331 #define _CMU_HFPERCLKEN0_ACMP1_MASK                 0x400UL                                
01332 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT              0x00000000UL                           
01333 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT               (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) 
01334 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
01335 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
01336 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
01337 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
01338 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
01339 #define CMU_HFPERCLKEN0_I2C1                        (0x1UL << 12)                          
01340 #define _CMU_HFPERCLKEN0_I2C1_SHIFT                 12                                     
01341 #define _CMU_HFPERCLKEN0_I2C1_MASK                  0x1000UL                               
01342 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT               0x00000000UL                           
01343 #define CMU_HFPERCLKEN0_I2C1_DEFAULT                (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)  
01344 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 13)                          
01345 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 13                                     
01346 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x2000UL                               
01347 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
01348 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)  
01349 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 14)                          
01350 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 14                                     
01351 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x4000UL                               
01352 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
01353 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)  
01354 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 15)                          
01355 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  15                                     
01356 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x8000UL                               
01357 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
01358 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)   
01359 #define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 16)                          
01360 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                 16                                     
01361 #define _CMU_HFPERCLKEN0_ADC0_MASK                  0x10000UL                              
01362 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           
01363 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)  
01364 #define CMU_HFPERCLKEN0_DAC0                        (0x1UL << 17)                          
01365 #define _CMU_HFPERCLKEN0_DAC0_SHIFT                 17                                     
01366 #define _CMU_HFPERCLKEN0_DAC0_MASK                  0x20000UL                              
01367 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT               0x00000000UL                           
01368 #define CMU_HFPERCLKEN0_DAC0_DEFAULT                (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)  
01370 /* Bit fields for CMU SYNCBUSY */
01371 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
01372 #define _CMU_SYNCBUSY_MASK                          0x00000055UL                           
01373 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
01374 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
01375 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
01376 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
01377 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
01378 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
01379 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
01380 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
01381 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
01382 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
01383 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
01384 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
01385 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
01386 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
01387 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
01388 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
01389 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
01390 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
01391 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
01392 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
01394 /* Bit fields for CMU FREEZE */
01395 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
01396 #define _CMU_FREEZE_MASK                            0x00000001UL                         
01397 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
01398 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
01399 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
01400 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
01401 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
01402 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
01403 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
01404 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
01405 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
01407 /* Bit fields for CMU LFACLKEN0 */
01408 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                           
01409 #define _CMU_LFACLKEN0_MASK                         0x0000000FUL                           
01410 #define CMU_LFACLKEN0_LESENSE                       (0x1UL << 0)                           
01411 #define _CMU_LFACLKEN0_LESENSE_SHIFT                0                                      
01412 #define _CMU_LFACLKEN0_LESENSE_MASK                 0x1UL                                  
01413 #define _CMU_LFACLKEN0_LESENSE_DEFAULT              0x00000000UL                           
01414 #define CMU_LFACLKEN0_LESENSE_DEFAULT               (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)  
01415 #define CMU_LFACLKEN0_RTC                           (0x1UL << 1)                           
01416 #define _CMU_LFACLKEN0_RTC_SHIFT                    1                                      
01417 #define _CMU_LFACLKEN0_RTC_MASK                     0x2UL                                  
01418 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                           
01419 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)      
01420 #define CMU_LFACLKEN0_LETIMER0                      (0x1UL << 2)                           
01421 #define _CMU_LFACLKEN0_LETIMER0_SHIFT               2                                      
01422 #define _CMU_LFACLKEN0_LETIMER0_MASK                0x4UL                                  
01423 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT             0x00000000UL                           
01424 #define CMU_LFACLKEN0_LETIMER0_DEFAULT              (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) 
01425 #define CMU_LFACLKEN0_LCD                           (0x1UL << 3)                           
01426 #define _CMU_LFACLKEN0_LCD_SHIFT                    3                                      
01427 #define _CMU_LFACLKEN0_LCD_MASK                     0x8UL                                  
01428 #define _CMU_LFACLKEN0_LCD_DEFAULT                  0x00000000UL                           
01429 #define CMU_LFACLKEN0_LCD_DEFAULT                   (_CMU_LFACLKEN0_LCD_DEFAULT << 3)      
01431 /* Bit fields for CMU LFBCLKEN0 */
01432 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
01433 #define _CMU_LFBCLKEN0_MASK                         0x00000003UL                          
01434 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
01435 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
01436 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
01437 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
01438 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
01439 #define CMU_LFBCLKEN0_LEUART1                       (0x1UL << 1)                          
01440 #define _CMU_LFBCLKEN0_LEUART1_SHIFT                1                                     
01441 #define _CMU_LFBCLKEN0_LEUART1_MASK                 0x2UL                                 
01442 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT              0x00000000UL                          
01443 #define CMU_LFBCLKEN0_LEUART1_DEFAULT               (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) 
01445 /* Bit fields for CMU LFAPRESC0 */
01446 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                            
01447 #define _CMU_LFAPRESC0_MASK                         0x00003FF3UL                            
01448 #define _CMU_LFAPRESC0_LESENSE_SHIFT                0                                       
01449 #define _CMU_LFAPRESC0_LESENSE_MASK                 0x3UL                                   
01450 #define _CMU_LFAPRESC0_LESENSE_DIV1                 0x00000000UL                            
01451 #define _CMU_LFAPRESC0_LESENSE_DIV2                 0x00000001UL                            
01452 #define _CMU_LFAPRESC0_LESENSE_DIV4                 0x00000002UL                            
01453 #define _CMU_LFAPRESC0_LESENSE_DIV8                 0x00000003UL                            
01454 #define CMU_LFAPRESC0_LESENSE_DIV1                  (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)      
01455 #define CMU_LFAPRESC0_LESENSE_DIV2                  (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)      
01456 #define CMU_LFAPRESC0_LESENSE_DIV4                  (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)      
01457 #define CMU_LFAPRESC0_LESENSE_DIV8                  (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)      
01458 #define _CMU_LFAPRESC0_RTC_SHIFT                    4                                       
01459 #define _CMU_LFAPRESC0_RTC_MASK                     0xF0UL                                  
01460 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                            
01461 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                            
01462 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                            
01463 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                            
01464 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                            
01465 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                            
01466 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                            
01467 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                            
01468 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                            
01469 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                            
01470 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                            
01471 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                            
01472 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                            
01473 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                            
01474 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                            
01475 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                            
01476 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 4)          
01477 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 4)          
01478 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 4)          
01479 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 4)          
01480 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 4)         
01481 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 4)         
01482 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 4)         
01483 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 4)        
01484 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 4)        
01485 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 4)        
01486 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)       
01487 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)       
01488 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)       
01489 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)       
01490 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 4)      
01491 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 4)      
01492 #define _CMU_LFAPRESC0_LETIMER0_SHIFT               8                                       
01493 #define _CMU_LFAPRESC0_LETIMER0_MASK                0xF00UL                                 
01494 #define _CMU_LFAPRESC0_LETIMER0_DIV1                0x00000000UL                            
01495 #define _CMU_LFAPRESC0_LETIMER0_DIV2                0x00000001UL                            
01496 #define _CMU_LFAPRESC0_LETIMER0_DIV4                0x00000002UL                            
01497 #define _CMU_LFAPRESC0_LETIMER0_DIV8                0x00000003UL                            
01498 #define _CMU_LFAPRESC0_LETIMER0_DIV16               0x00000004UL                            
01499 #define _CMU_LFAPRESC0_LETIMER0_DIV32               0x00000005UL                            
01500 #define _CMU_LFAPRESC0_LETIMER0_DIV64               0x00000006UL                            
01501 #define _CMU_LFAPRESC0_LETIMER0_DIV128              0x00000007UL                            
01502 #define _CMU_LFAPRESC0_LETIMER0_DIV256              0x00000008UL                            
01503 #define _CMU_LFAPRESC0_LETIMER0_DIV512              0x00000009UL                            
01504 #define _CMU_LFAPRESC0_LETIMER0_DIV1024             0x0000000AUL                            
01505 #define _CMU_LFAPRESC0_LETIMER0_DIV2048             0x0000000BUL                            
01506 #define _CMU_LFAPRESC0_LETIMER0_DIV4096             0x0000000CUL                            
01507 #define _CMU_LFAPRESC0_LETIMER0_DIV8192             0x0000000DUL                            
01508 #define _CMU_LFAPRESC0_LETIMER0_DIV16384            0x0000000EUL                            
01509 #define _CMU_LFAPRESC0_LETIMER0_DIV32768            0x0000000FUL                            
01510 #define CMU_LFAPRESC0_LETIMER0_DIV1                 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)     
01511 #define CMU_LFAPRESC0_LETIMER0_DIV2                 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)     
01512 #define CMU_LFAPRESC0_LETIMER0_DIV4                 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)     
01513 #define CMU_LFAPRESC0_LETIMER0_DIV8                 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)     
01514 #define CMU_LFAPRESC0_LETIMER0_DIV16                (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)    
01515 #define CMU_LFAPRESC0_LETIMER0_DIV32                (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)    
01516 #define CMU_LFAPRESC0_LETIMER0_DIV64                (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)    
01517 #define CMU_LFAPRESC0_LETIMER0_DIV128               (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)   
01518 #define CMU_LFAPRESC0_LETIMER0_DIV256               (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)   
01519 #define CMU_LFAPRESC0_LETIMER0_DIV512               (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)   
01520 #define CMU_LFAPRESC0_LETIMER0_DIV1024              (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)  
01521 #define CMU_LFAPRESC0_LETIMER0_DIV2048              (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)  
01522 #define CMU_LFAPRESC0_LETIMER0_DIV4096              (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)  
01523 #define CMU_LFAPRESC0_LETIMER0_DIV8192              (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)  
01524 #define CMU_LFAPRESC0_LETIMER0_DIV16384             (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) 
01525 #define CMU_LFAPRESC0_LETIMER0_DIV32768             (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) 
01526 #define _CMU_LFAPRESC0_LCD_SHIFT                    12                                      
01527 #define _CMU_LFAPRESC0_LCD_MASK                     0x3000UL                                
01528 #define _CMU_LFAPRESC0_LCD_DIV16                    0x00000000UL                            
01529 #define _CMU_LFAPRESC0_LCD_DIV32                    0x00000001UL                            
01530 #define _CMU_LFAPRESC0_LCD_DIV64                    0x00000002UL                            
01531 #define _CMU_LFAPRESC0_LCD_DIV128                   0x00000003UL                            
01532 #define CMU_LFAPRESC0_LCD_DIV16                     (_CMU_LFAPRESC0_LCD_DIV16 << 12)        
01533 #define CMU_LFAPRESC0_LCD_DIV32                     (_CMU_LFAPRESC0_LCD_DIV32 << 12)        
01534 #define CMU_LFAPRESC0_LCD_DIV64                     (_CMU_LFAPRESC0_LCD_DIV64 << 12)        
01535 #define CMU_LFAPRESC0_LCD_DIV128                    (_CMU_LFAPRESC0_LCD_DIV128 << 12)       
01537 /* Bit fields for CMU LFBPRESC0 */
01538 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
01539 #define _CMU_LFBPRESC0_MASK                         0x00000033UL                       
01540 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
01541 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
01542 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
01543 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
01544 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
01545 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
01546 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
01547 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
01548 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
01549 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
01550 #define _CMU_LFBPRESC0_LEUART1_SHIFT                4                                  
01551 #define _CMU_LFBPRESC0_LEUART1_MASK                 0x30UL                             
01552 #define _CMU_LFBPRESC0_LEUART1_DIV1                 0x00000000UL                       
01553 #define _CMU_LFBPRESC0_LEUART1_DIV2                 0x00000001UL                       
01554 #define _CMU_LFBPRESC0_LEUART1_DIV4                 0x00000002UL                       
01555 #define _CMU_LFBPRESC0_LEUART1_DIV8                 0x00000003UL                       
01556 #define CMU_LFBPRESC0_LEUART1_DIV1                  (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) 
01557 #define CMU_LFBPRESC0_LEUART1_DIV2                  (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) 
01558 #define CMU_LFBPRESC0_LEUART1_DIV4                  (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) 
01559 #define CMU_LFBPRESC0_LEUART1_DIV8                  (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) 
01561 /* Bit fields for CMU PCNTCTRL */
01562 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
01563 #define _CMU_PCNTCTRL_MASK                          0x0000003FUL                             
01564 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
01565 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
01566 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
01567 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
01568 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
01569 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
01570 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
01571 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
01572 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
01573 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
01574 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
01575 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
01576 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
01577 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
01578 #define CMU_PCNTCTRL_PCNT1CLKEN                     (0x1UL << 2)                             
01579 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT              2                                        
01580 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK               0x4UL                                    
01581 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT            0x00000000UL                             
01582 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  
01583 #define CMU_PCNTCTRL_PCNT1CLKSEL                    (0x1UL << 3)                             
01584 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT             3                                        
01585 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK              0x8UL                                    
01586 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT           0x00000000UL                             
01587 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK            0x00000000UL                             
01588 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0           0x00000001UL                             
01589 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) 
01590 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  
01591 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0            (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) 
01592 #define CMU_PCNTCTRL_PCNT2CLKEN                     (0x1UL << 4)                             
01593 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT              4                                        
01594 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK               0x10UL                                   
01595 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT            0x00000000UL                             
01596 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  
01597 #define CMU_PCNTCTRL_PCNT2CLKSEL                    (0x1UL << 5)                             
01598 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT             5                                        
01599 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK              0x20UL                                   
01600 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT           0x00000000UL                             
01601 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK            0x00000000UL                             
01602 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0           0x00000001UL                             
01603 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) 
01604 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  
01605 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0            (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) 
01607 /* Bit fields for CMU LCDCTRL */
01608 #define _CMU_LCDCTRL_RESETVALUE                     0x00000020UL                         
01609 #define _CMU_LCDCTRL_MASK                           0x0000007FUL                         
01610 #define _CMU_LCDCTRL_FDIV_SHIFT                     0                                    
01611 #define _CMU_LCDCTRL_FDIV_MASK                      0x7UL                                
01612 #define _CMU_LCDCTRL_FDIV_DEFAULT                   0x00000000UL                         
01613 #define CMU_LCDCTRL_FDIV_DEFAULT                    (_CMU_LCDCTRL_FDIV_DEFAULT << 0)     
01614 #define CMU_LCDCTRL_VBOOSTEN                        (0x1UL << 3)                         
01615 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT                 3                                    
01616 #define _CMU_LCDCTRL_VBOOSTEN_MASK                  0x8UL                                
01617 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT               0x00000000UL                         
01618 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT                (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) 
01619 #define _CMU_LCDCTRL_VBFDIV_SHIFT                   4                                    
01620 #define _CMU_LCDCTRL_VBFDIV_MASK                    0x70UL                               
01621 #define _CMU_LCDCTRL_VBFDIV_DIV1                    0x00000000UL                         
01622 #define _CMU_LCDCTRL_VBFDIV_DIV2                    0x00000001UL                         
01623 #define _CMU_LCDCTRL_VBFDIV_DEFAULT                 0x00000002UL                         
01624 #define _CMU_LCDCTRL_VBFDIV_DIV4                    0x00000002UL                         
01625 #define _CMU_LCDCTRL_VBFDIV_DIV8                    0x00000003UL                         
01626 #define _CMU_LCDCTRL_VBFDIV_DIV16                   0x00000004UL                         
01627 #define _CMU_LCDCTRL_VBFDIV_DIV32                   0x00000005UL                         
01628 #define _CMU_LCDCTRL_VBFDIV_DIV64                   0x00000006UL                         
01629 #define _CMU_LCDCTRL_VBFDIV_DIV128                  0x00000007UL                         
01630 #define CMU_LCDCTRL_VBFDIV_DIV1                     (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)      
01631 #define CMU_LCDCTRL_VBFDIV_DIV2                     (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)      
01632 #define CMU_LCDCTRL_VBFDIV_DEFAULT                  (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)   
01633 #define CMU_LCDCTRL_VBFDIV_DIV4                     (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)      
01634 #define CMU_LCDCTRL_VBFDIV_DIV8                     (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)      
01635 #define CMU_LCDCTRL_VBFDIV_DIV16                    (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)     
01636 #define CMU_LCDCTRL_VBFDIV_DIV32                    (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)     
01637 #define CMU_LCDCTRL_VBFDIV_DIV64                    (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)     
01638 #define CMU_LCDCTRL_VBFDIV_DIV128                   (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)    
01640 /* Bit fields for CMU ROUTE */
01641 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
01642 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
01643 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
01644 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
01645 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
01646 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
01647 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
01648 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
01649 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
01650 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
01651 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
01652 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
01653 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
01654 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
01655 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
01656 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
01657 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
01658 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
01659 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
01660 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
01661 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
01662 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
01664 /* Bit fields for CMU LOCK */
01665 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
01666 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
01667 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
01668 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
01669 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
01670 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
01671 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
01672 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
01673 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
01674 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
01675 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
01676 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
01677 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
01678 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
01684 /**************************************************************************/
01689 /* Bit fields for PRS SWPULSE */
01690 #define _PRS_SWPULSE_RESETVALUE                 0x00000000UL                           
01691 #define _PRS_SWPULSE_MASK                       0x00000FFFUL                           
01692 #define PRS_SWPULSE_CH0PULSE                    (0x1UL << 0)                           
01693 #define _PRS_SWPULSE_CH0PULSE_SHIFT             0                                      
01694 #define _PRS_SWPULSE_CH0PULSE_MASK              0x1UL                                  
01695 #define _PRS_SWPULSE_CH0PULSE_DEFAULT           0x00000000UL                           
01696 #define PRS_SWPULSE_CH0PULSE_DEFAULT            (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)   
01697 #define PRS_SWPULSE_CH1PULSE                    (0x1UL << 1)                           
01698 #define _PRS_SWPULSE_CH1PULSE_SHIFT             1                                      
01699 #define _PRS_SWPULSE_CH1PULSE_MASK              0x2UL                                  
01700 #define _PRS_SWPULSE_CH1PULSE_DEFAULT           0x00000000UL                           
01701 #define PRS_SWPULSE_CH1PULSE_DEFAULT            (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)   
01702 #define PRS_SWPULSE_CH2PULSE                    (0x1UL << 2)                           
01703 #define _PRS_SWPULSE_CH2PULSE_SHIFT             2                                      
01704 #define _PRS_SWPULSE_CH2PULSE_MASK              0x4UL                                  
01705 #define _PRS_SWPULSE_CH2PULSE_DEFAULT           0x00000000UL                           
01706 #define PRS_SWPULSE_CH2PULSE_DEFAULT            (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)   
01707 #define PRS_SWPULSE_CH3PULSE                    (0x1UL << 3)                           
01708 #define _PRS_SWPULSE_CH3PULSE_SHIFT             3                                      
01709 #define _PRS_SWPULSE_CH3PULSE_MASK              0x8UL                                  
01710 #define _PRS_SWPULSE_CH3PULSE_DEFAULT           0x00000000UL                           
01711 #define PRS_SWPULSE_CH3PULSE_DEFAULT            (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)   
01712 #define PRS_SWPULSE_CH4PULSE                    (0x1UL << 4)                           
01713 #define _PRS_SWPULSE_CH4PULSE_SHIFT             4                                      
01714 #define _PRS_SWPULSE_CH4PULSE_MASK              0x10UL                                 
01715 #define _PRS_SWPULSE_CH4PULSE_DEFAULT           0x00000000UL                           
01716 #define PRS_SWPULSE_CH4PULSE_DEFAULT            (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)   
01717 #define PRS_SWPULSE_CH5PULSE                    (0x1UL << 5)                           
01718 #define _PRS_SWPULSE_CH5PULSE_SHIFT             5                                      
01719 #define _PRS_SWPULSE_CH5PULSE_MASK              0x20UL                                 
01720 #define _PRS_SWPULSE_CH5PULSE_DEFAULT           0x00000000UL                           
01721 #define PRS_SWPULSE_CH5PULSE_DEFAULT            (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)   
01722 #define PRS_SWPULSE_CH6PULSE                    (0x1UL << 6)                           
01723 #define _PRS_SWPULSE_CH6PULSE_SHIFT             6                                      
01724 #define _PRS_SWPULSE_CH6PULSE_MASK              0x40UL                                 
01725 #define _PRS_SWPULSE_CH6PULSE_DEFAULT           0x00000000UL                           
01726 #define PRS_SWPULSE_CH6PULSE_DEFAULT            (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)   
01727 #define PRS_SWPULSE_CH7PULSE                    (0x1UL << 7)                           
01728 #define _PRS_SWPULSE_CH7PULSE_SHIFT             7                                      
01729 #define _PRS_SWPULSE_CH7PULSE_MASK              0x80UL                                 
01730 #define _PRS_SWPULSE_CH7PULSE_DEFAULT           0x00000000UL                           
01731 #define PRS_SWPULSE_CH7PULSE_DEFAULT            (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)   
01732 #define PRS_SWPULSE_CH8PULSE                    (0x1UL << 8)                           
01733 #define _PRS_SWPULSE_CH8PULSE_SHIFT             8                                      
01734 #define _PRS_SWPULSE_CH8PULSE_MASK              0x100UL                                
01735 #define _PRS_SWPULSE_CH8PULSE_DEFAULT           0x00000000UL                           
01736 #define PRS_SWPULSE_CH8PULSE_DEFAULT            (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8)   
01737 #define PRS_SWPULSE_CH9PULSE                    (0x1UL << 9)                           
01738 #define _PRS_SWPULSE_CH9PULSE_SHIFT             9                                      
01739 #define _PRS_SWPULSE_CH9PULSE_MASK              0x200UL                                
01740 #define _PRS_SWPULSE_CH9PULSE_DEFAULT           0x00000000UL                           
01741 #define PRS_SWPULSE_CH9PULSE_DEFAULT            (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9)   
01742 #define PRS_SWPULSE_CH10PULSE                   (0x1UL << 10)                          
01743 #define _PRS_SWPULSE_CH10PULSE_SHIFT            10                                     
01744 #define _PRS_SWPULSE_CH10PULSE_MASK             0x400UL                                
01745 #define _PRS_SWPULSE_CH10PULSE_DEFAULT          0x00000000UL                           
01746 #define PRS_SWPULSE_CH10PULSE_DEFAULT           (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) 
01747 #define PRS_SWPULSE_CH11PULSE                   (0x1UL << 11)                          
01748 #define _PRS_SWPULSE_CH11PULSE_SHIFT            11                                     
01749 #define _PRS_SWPULSE_CH11PULSE_MASK             0x800UL                                
01750 #define _PRS_SWPULSE_CH11PULSE_DEFAULT          0x00000000UL                           
01751 #define PRS_SWPULSE_CH11PULSE_DEFAULT           (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) 
01753 /* Bit fields for PRS SWLEVEL */
01754 #define _PRS_SWLEVEL_RESETVALUE                 0x00000000UL                           
01755 #define _PRS_SWLEVEL_MASK                       0x00000FFFUL                           
01756 #define PRS_SWLEVEL_CH0LEVEL                    (0x1UL << 0)                           
01757 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT             0                                      
01758 #define _PRS_SWLEVEL_CH0LEVEL_MASK              0x1UL                                  
01759 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT           0x00000000UL                           
01760 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT            (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)   
01761 #define PRS_SWLEVEL_CH1LEVEL                    (0x1UL << 1)                           
01762 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT             1                                      
01763 #define _PRS_SWLEVEL_CH1LEVEL_MASK              0x2UL                                  
01764 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT           0x00000000UL                           
01765 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT            (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)   
01766 #define PRS_SWLEVEL_CH2LEVEL                    (0x1UL << 2)                           
01767 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT             2                                      
01768 #define _PRS_SWLEVEL_CH2LEVEL_MASK              0x4UL                                  
01769 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT           0x00000000UL                           
01770 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT            (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)   
01771 #define PRS_SWLEVEL_CH3LEVEL                    (0x1UL << 3)                           
01772 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT             3                                      
01773 #define _PRS_SWLEVEL_CH3LEVEL_MASK              0x8UL                                  
01774 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT           0x00000000UL                           
01775 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT            (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)   
01776 #define PRS_SWLEVEL_CH4LEVEL                    (0x1UL << 4)                           
01777 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT             4                                      
01778 #define _PRS_SWLEVEL_CH4LEVEL_MASK              0x10UL                                 
01779 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT           0x00000000UL                           
01780 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT            (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)   
01781 #define PRS_SWLEVEL_CH5LEVEL                    (0x1UL << 5)                           
01782 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT             5                                      
01783 #define _PRS_SWLEVEL_CH5LEVEL_MASK              0x20UL                                 
01784 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT           0x00000000UL                           
01785 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT            (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)   
01786 #define PRS_SWLEVEL_CH6LEVEL                    (0x1UL << 6)                           
01787 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT             6                                      
01788 #define _PRS_SWLEVEL_CH6LEVEL_MASK              0x40UL                                 
01789 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT           0x00000000UL                           
01790 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT            (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)   
01791 #define PRS_SWLEVEL_CH7LEVEL                    (0x1UL << 7)                           
01792 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT             7                                      
01793 #define _PRS_SWLEVEL_CH7LEVEL_MASK              0x80UL                                 
01794 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT           0x00000000UL                           
01795 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT            (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)   
01796 #define PRS_SWLEVEL_CH8LEVEL                    (0x1UL << 8)                           
01797 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT             8                                      
01798 #define _PRS_SWLEVEL_CH8LEVEL_MASK              0x100UL                                
01799 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT           0x00000000UL                           
01800 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT            (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8)   
01801 #define PRS_SWLEVEL_CH9LEVEL                    (0x1UL << 9)                           
01802 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT             9                                      
01803 #define _PRS_SWLEVEL_CH9LEVEL_MASK              0x200UL                                
01804 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT           0x00000000UL                           
01805 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT            (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9)   
01806 #define PRS_SWLEVEL_CH10LEVEL                   (0x1UL << 10)                          
01807 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT            10                                     
01808 #define _PRS_SWLEVEL_CH10LEVEL_MASK             0x400UL                                
01809 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT          0x00000000UL                           
01810 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT           (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) 
01811 #define PRS_SWLEVEL_CH11LEVEL                   (0x1UL << 11)                          
01812 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT            11                                     
01813 #define _PRS_SWLEVEL_CH11LEVEL_MASK             0x800UL                                
01814 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT          0x00000000UL                           
01815 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT           (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) 
01817 /* Bit fields for PRS ROUTE */
01818 #define _PRS_ROUTE_RESETVALUE                   0x00000000UL                       
01819 #define _PRS_ROUTE_MASK                         0x0000070FUL                       
01820 #define PRS_ROUTE_CH0PEN                        (0x1UL << 0)                       
01821 #define _PRS_ROUTE_CH0PEN_SHIFT                 0                                  
01822 #define _PRS_ROUTE_CH0PEN_MASK                  0x1UL                              
01823 #define _PRS_ROUTE_CH0PEN_DEFAULT               0x00000000UL                       
01824 #define PRS_ROUTE_CH0PEN_DEFAULT                (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   
01825 #define PRS_ROUTE_CH1PEN                        (0x1UL << 1)                       
01826 #define _PRS_ROUTE_CH1PEN_SHIFT                 1                                  
01827 #define _PRS_ROUTE_CH1PEN_MASK                  0x2UL                              
01828 #define _PRS_ROUTE_CH1PEN_DEFAULT               0x00000000UL                       
01829 #define PRS_ROUTE_CH1PEN_DEFAULT                (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   
01830 #define PRS_ROUTE_CH2PEN                        (0x1UL << 2)                       
01831 #define _PRS_ROUTE_CH2PEN_SHIFT                 2                                  
01832 #define _PRS_ROUTE_CH2PEN_MASK                  0x4UL                              
01833 #define _PRS_ROUTE_CH2PEN_DEFAULT               0x00000000UL                       
01834 #define PRS_ROUTE_CH2PEN_DEFAULT                (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   
01835 #define PRS_ROUTE_CH3PEN                        (0x1UL << 3)                       
01836 #define _PRS_ROUTE_CH3PEN_SHIFT                 3                                  
01837 #define _PRS_ROUTE_CH3PEN_MASK                  0x8UL                              
01838 #define _PRS_ROUTE_CH3PEN_DEFAULT               0x00000000UL                       
01839 #define PRS_ROUTE_CH3PEN_DEFAULT                (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   
01840 #define _PRS_ROUTE_LOCATION_SHIFT               8                                  
01841 #define _PRS_ROUTE_LOCATION_MASK                0x700UL                            
01842 #define _PRS_ROUTE_LOCATION_LOC0                0x00000000UL                       
01843 #define _PRS_ROUTE_LOCATION_DEFAULT             0x00000000UL                       
01844 #define _PRS_ROUTE_LOCATION_LOC1                0x00000001UL                       
01845 #define PRS_ROUTE_LOCATION_LOC0                 (_PRS_ROUTE_LOCATION_LOC0 << 8)    
01846 #define PRS_ROUTE_LOCATION_DEFAULT              (_PRS_ROUTE_LOCATION_DEFAULT << 8) 
01847 #define PRS_ROUTE_LOCATION_LOC1                 (_PRS_ROUTE_LOCATION_LOC1 << 8)    
01849 /* Bit fields for PRS CH_CTRL */
01850 #define _PRS_CH_CTRL_RESETVALUE                 0x00000000UL                                
01851 #define _PRS_CH_CTRL_MASK                       0x133F0007UL                                
01852 #define _PRS_CH_CTRL_SIGSEL_SHIFT               0                                           
01853 #define _PRS_CH_CTRL_SIGSEL_MASK                0x7UL                                       
01854 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT             0x00000000UL                                
01855 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT            0x00000000UL                                
01856 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT            0x00000000UL                                
01857 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0             0x00000000UL                                
01858 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE          0x00000000UL                                
01859 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX          0x00000000UL                                
01860 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF            0x00000000UL                                
01861 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF            0x00000000UL                                
01862 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF            0x00000000UL                                
01863 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF            0x00000000UL                                
01864 #define _PRS_CH_CTRL_SIGSEL_RTCOF               0x00000000UL                                
01865 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0            0x00000000UL                                
01866 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8            0x00000000UL                                
01867 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0         0x00000000UL                                
01868 #define _PRS_CH_CTRL_SIGSEL_BURTCOF             0x00000000UL                                
01869 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0     0x00000000UL                                
01870 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8     0x00000000UL                                
01871 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0         0x00000000UL                                
01872 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1             0x00000001UL                                
01873 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN            0x00000001UL                                
01874 #define _PRS_CH_CTRL_SIGSEL_USART0TXC           0x00000001UL                                
01875 #define _PRS_CH_CTRL_SIGSEL_USART1TXC           0x00000001UL                                
01876 #define _PRS_CH_CTRL_SIGSEL_USART2TXC           0x00000001UL                                
01877 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF            0x00000001UL                                
01878 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF            0x00000001UL                                
01879 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF            0x00000001UL                                
01880 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF            0x00000001UL                                
01881 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0            0x00000001UL                                
01882 #define _PRS_CH_CTRL_SIGSEL_UART0TXC            0x00000001UL                                
01883 #define _PRS_CH_CTRL_SIGSEL_UART1TXC            0x00000001UL                                
01884 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1            0x00000001UL                                
01885 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9            0x00000001UL                                
01886 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1         0x00000001UL                                
01887 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0          0x00000001UL                                
01888 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1     0x00000001UL                                
01889 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9     0x00000001UL                                
01890 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1         0x00000001UL                                
01891 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV       0x00000002UL                                
01892 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV       0x00000002UL                                
01893 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV       0x00000002UL                                
01894 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0           0x00000002UL                                
01895 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0           0x00000002UL                                
01896 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0           0x00000002UL                                
01897 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0           0x00000002UL                                
01898 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1            0x00000002UL                                
01899 #define _PRS_CH_CTRL_SIGSEL_UART0RXDATAV        0x00000002UL                                
01900 #define _PRS_CH_CTRL_SIGSEL_UART1RXDATAV        0x00000002UL                                
01901 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2            0x00000002UL                                
01902 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10           0x00000002UL                                
01903 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2     0x00000002UL                                
01904 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10    0x00000002UL                                
01905 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2         0x00000002UL                                
01906 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1           0x00000003UL                                
01907 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1           0x00000003UL                                
01908 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1           0x00000003UL                                
01909 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1           0x00000003UL                                
01910 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3            0x00000003UL                                
01911 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11           0x00000003UL                                
01912 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3     0x00000003UL                                
01913 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11    0x00000003UL                                
01914 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2           0x00000004UL                                
01915 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2           0x00000004UL                                
01916 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2           0x00000004UL                                
01917 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2           0x00000004UL                                
01918 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4            0x00000004UL                                
01919 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12           0x00000004UL                                
01920 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4     0x00000004UL                                
01921 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12    0x00000004UL                                
01922 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5            0x00000005UL                                
01923 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13           0x00000005UL                                
01924 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5     0x00000005UL                                
01925 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13    0x00000005UL                                
01926 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6            0x00000006UL                                
01927 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14           0x00000006UL                                
01928 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6     0x00000006UL                                
01929 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14    0x00000006UL                                
01930 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7            0x00000007UL                                
01931 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15           0x00000007UL                                
01932 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7     0x00000007UL                                
01933 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15    0x00000007UL                                
01934 #define PRS_CH_CTRL_SIGSEL_VCMPOUT              (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)          
01935 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT             (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)         
01936 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT             (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)         
01937 #define PRS_CH_CTRL_SIGSEL_DAC0CH0              (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)          
01938 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE           (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)       
01939 #define PRS_CH_CTRL_SIGSEL_USART0IRTX           (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)       
01940 #define PRS_CH_CTRL_SIGSEL_TIMER0UF             (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)         
01941 #define PRS_CH_CTRL_SIGSEL_TIMER1UF             (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)         
01942 #define PRS_CH_CTRL_SIGSEL_TIMER2UF             (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)         
01943 #define PRS_CH_CTRL_SIGSEL_TIMER3UF             (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0)         
01944 #define PRS_CH_CTRL_SIGSEL_RTCOF                (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)            
01945 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0             (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)         
01946 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8             (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)         
01947 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0          (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)      
01948 #define PRS_CH_CTRL_SIGSEL_BURTCOF              (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0)          
01949 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0)  
01950 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0)  
01951 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0)      
01952 #define PRS_CH_CTRL_SIGSEL_DAC0CH1              (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)          
01953 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN             (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)         
01954 #define PRS_CH_CTRL_SIGSEL_USART0TXC            (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)        
01955 #define PRS_CH_CTRL_SIGSEL_USART1TXC            (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)        
01956 #define PRS_CH_CTRL_SIGSEL_USART2TXC            (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0)        
01957 #define PRS_CH_CTRL_SIGSEL_TIMER0OF             (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)         
01958 #define PRS_CH_CTRL_SIGSEL_TIMER1OF             (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)         
01959 #define PRS_CH_CTRL_SIGSEL_TIMER2OF             (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)         
01960 #define PRS_CH_CTRL_SIGSEL_TIMER3OF             (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0)         
01961 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0             (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)         
01962 #define PRS_CH_CTRL_SIGSEL_UART0TXC             (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0)         
01963 #define PRS_CH_CTRL_SIGSEL_UART1TXC             (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0)         
01964 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1             (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)         
01965 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9             (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)         
01966 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1          (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)      
01967 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0           (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0)       
01968 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0)  
01969 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0)  
01970 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0)      
01971 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)    
01972 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)    
01973 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV        (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0)    
01974 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0            (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)        
01975 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0            (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)        
01976 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0            (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)        
01977 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0            (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0)        
01978 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1             (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)         
01979 #define PRS_CH_CTRL_SIGSEL_UART0RXDATAV         (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0)     
01980 #define PRS_CH_CTRL_SIGSEL_UART1RXDATAV         (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0)     
01981 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2             (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)         
01982 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10            (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)        
01983 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0)  
01984 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) 
01985 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2          (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0)      
01986 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1            (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)        
01987 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1            (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)        
01988 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1            (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)        
01989 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1            (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0)        
01990 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3             (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)         
01991 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11            (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)        
01992 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0)  
01993 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) 
01994 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2            (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)        
01995 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2            (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)        
01996 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2            (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)        
01997 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2            (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0)        
01998 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4             (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)         
01999 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12            (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)        
02000 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0)  
02001 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) 
02002 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5             (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)         
02003 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13            (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)        
02004 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0)  
02005 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) 
02006 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6             (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)         
02007 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14            (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)        
02008 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0)  
02009 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) 
02010 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7             (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)         
02011 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15            (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)        
02012 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7      (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0)  
02013 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15     (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) 
02014 #define _PRS_CH_CTRL_SOURCESEL_SHIFT            16                                          
02015 #define _PRS_CH_CTRL_SOURCESEL_MASK             0x3F0000UL                                  
02016 #define _PRS_CH_CTRL_SOURCESEL_NONE             0x00000000UL                                
02017 #define _PRS_CH_CTRL_SOURCESEL_VCMP             0x00000001UL                                
02018 #define _PRS_CH_CTRL_SOURCESEL_ACMP0            0x00000002UL                                
02019 #define _PRS_CH_CTRL_SOURCESEL_ACMP1            0x00000003UL                                
02020 #define _PRS_CH_CTRL_SOURCESEL_DAC0             0x00000006UL                                
02021 #define _PRS_CH_CTRL_SOURCESEL_ADC0             0x00000008UL                                
02022 #define _PRS_CH_CTRL_SOURCESEL_USART0           0x00000010UL                                
02023 #define _PRS_CH_CTRL_SOURCESEL_USART1           0x00000011UL                                
02024 #define _PRS_CH_CTRL_SOURCESEL_USART2           0x00000012UL                                
02025 #define _PRS_CH_CTRL_SOURCESEL_TIMER0           0x0000001CUL                                
02026 #define _PRS_CH_CTRL_SOURCESEL_TIMER1           0x0000001DUL                                
02027 #define _PRS_CH_CTRL_SOURCESEL_TIMER2           0x0000001EUL                                
02028 #define _PRS_CH_CTRL_SOURCESEL_TIMER3           0x0000001FUL                                
02029 #define _PRS_CH_CTRL_SOURCESEL_RTC              0x00000028UL                                
02030 #define _PRS_CH_CTRL_SOURCESEL_UART0            0x00000029UL                                
02031 #define _PRS_CH_CTRL_SOURCESEL_UART1            0x0000002AUL                                
02032 #define _PRS_CH_CTRL_SOURCESEL_GPIOL            0x00000030UL                                
02033 #define _PRS_CH_CTRL_SOURCESEL_GPIOH            0x00000031UL                                
02034 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0         0x00000034UL                                
02035 #define _PRS_CH_CTRL_SOURCESEL_BURTC            0x00000037UL                                
02036 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL         0x00000039UL                                
02037 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH         0x0000003AUL                                
02038 #define _PRS_CH_CTRL_SOURCESEL_LESENSED         0x0000003BUL                                
02039 #define PRS_CH_CTRL_SOURCESEL_NONE              (_PRS_CH_CTRL_SOURCESEL_NONE << 16)         
02040 #define PRS_CH_CTRL_SOURCESEL_VCMP              (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)         
02041 #define PRS_CH_CTRL_SOURCESEL_ACMP0             (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)        
02042 #define PRS_CH_CTRL_SOURCESEL_ACMP1             (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)        
02043 #define PRS_CH_CTRL_SOURCESEL_DAC0              (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)         
02044 #define PRS_CH_CTRL_SOURCESEL_ADC0              (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)         
02045 #define PRS_CH_CTRL_SOURCESEL_USART0            (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)       
02046 #define PRS_CH_CTRL_SOURCESEL_USART1            (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)       
02047 #define PRS_CH_CTRL_SOURCESEL_USART2            (_PRS_CH_CTRL_SOURCESEL_USART2 << 16)       
02048 #define PRS_CH_CTRL_SOURCESEL_TIMER0            (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)       
02049 #define PRS_CH_CTRL_SOURCESEL_TIMER1            (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)       
02050 #define PRS_CH_CTRL_SOURCESEL_TIMER2            (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)       
02051 #define PRS_CH_CTRL_SOURCESEL_TIMER3            (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16)       
02052 #define PRS_CH_CTRL_SOURCESEL_RTC               (_PRS_CH_CTRL_SOURCESEL_RTC << 16)          
02053 #define PRS_CH_CTRL_SOURCESEL_UART0             (_PRS_CH_CTRL_SOURCESEL_UART0 << 16)        
02054 #define PRS_CH_CTRL_SOURCESEL_UART1             (_PRS_CH_CTRL_SOURCESEL_UART1 << 16)        
02055 #define PRS_CH_CTRL_SOURCESEL_GPIOL             (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)        
02056 #define PRS_CH_CTRL_SOURCESEL_GPIOH             (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)        
02057 #define PRS_CH_CTRL_SOURCESEL_LETIMER0          (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16)     
02058 #define PRS_CH_CTRL_SOURCESEL_BURTC             (_PRS_CH_CTRL_SOURCESEL_BURTC << 16)        
02059 #define PRS_CH_CTRL_SOURCESEL_LESENSEL          (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16)     
02060 #define PRS_CH_CTRL_SOURCESEL_LESENSEH          (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16)     
02061 #define PRS_CH_CTRL_SOURCESEL_LESENSED          (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16)     
02062 #define _PRS_CH_CTRL_EDSEL_SHIFT                24                                          
02063 #define _PRS_CH_CTRL_EDSEL_MASK                 0x3000000UL                                 
02064 #define _PRS_CH_CTRL_EDSEL_DEFAULT              0x00000000UL                                
02065 #define _PRS_CH_CTRL_EDSEL_OFF                  0x00000000UL                                
02066 #define _PRS_CH_CTRL_EDSEL_POSEDGE              0x00000001UL                                
02067 #define _PRS_CH_CTRL_EDSEL_NEGEDGE              0x00000002UL                                
02068 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES            0x00000003UL                                
02069 #define PRS_CH_CTRL_EDSEL_DEFAULT               (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)          
02070 #define PRS_CH_CTRL_EDSEL_OFF                   (_PRS_CH_CTRL_EDSEL_OFF << 24)              
02071 #define PRS_CH_CTRL_EDSEL_POSEDGE               (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)          
02072 #define PRS_CH_CTRL_EDSEL_NEGEDGE               (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)          
02073 #define PRS_CH_CTRL_EDSEL_BOTHEDGES             (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)        
02074 #define PRS_CH_CTRL_ASYNC                       (0x1UL << 28)                               
02075 #define _PRS_CH_CTRL_ASYNC_SHIFT                28                                          
02076 #define _PRS_CH_CTRL_ASYNC_MASK                 0x10000000UL                                
02077 #define _PRS_CH_CTRL_ASYNC_DEFAULT              0x00000000UL                                
02078 #define PRS_CH_CTRL_ASYNC_DEFAULT               (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)          
02084 /**************************************************************************/
02088 #define MSC_UNLOCK_CODE      0x1B71 
02089 #define EMU_UNLOCK_CODE      0xADE8 
02090 #define CMU_UNLOCK_CODE      0x580E 
02091 #define TIMER_UNLOCK_CODE    0xCE80 
02092 #define GPIO_UNLOCK_CODE     0xA534 
02093 #define BURTC_UNLOCK_CODE    0xAEE8 
02099 /**************************************************************************/
02104 #include "efm32gg_af_ports.h"
02105 #include "efm32gg_af_pins.h"
02106 
02109 /**************************************************************************/
02122 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02123   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02124 
02129 #ifdef __cplusplus
02130 }
02131 #endif
02132 #endif /* __EFM32GG890F1024_H */