em_cmu.c
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00034 #include "em_cmu.h"
00035 #if defined( CMU_PRESENT )
00036
00037 #include "em_assert.h"
00038 #include "em_bitband.h"
00039 #include "em_emu.h"
00040
00041
00046
00052
00053
00054
00055
00059 #define CMU_MAX_FREQ_0WS 16000000
00060
00061 #define CMU_MAX_FREQ_1WS 32000000
00062
00063 #define CMU_MAX_FREQ_HFLE 32000000
00064
00066 #define CMU_LFA 0
00067
00069 #define CMU_LFB 1
00070
00073
00074
00075
00076
00079
00084 static void CMU_FlashWaitStateMax(void)
00085 {
00086 uint32_t cfg;
00087
00088 cfg = MSC->READCTRL;
00089
00090 switch(cfg & _MSC_READCTRL_MODE_MASK)
00091 {
00092 case MSC_READCTRL_MODE_WS1:
00093 case MSC_READCTRL_MODE_WS0:
00094
00095 #if defined( MSC_READCTRL_MODE_WS2 )
00096 case MSC_READCTRL_MODE_WS2:
00097 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS2;
00098 #else
00099 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS1;
00100 #endif
00101 break;
00102
00103 #if defined( MSC_READCTRL_MODE_WS1SCBTP )
00104 case MSC_READCTRL_MODE_WS1SCBTP:
00105 #endif
00106 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
00107 case MSC_READCTRL_MODE_WS0SCBTP:
00108 #endif
00109
00110 #if defined( MSC_READCTRL_MODE_WS2SCBTP )
00111 case MSC_READCTRL_MODE_WS2SCBTP:
00112 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS2SCBTP;
00113 #elif defined( MSC_READCTRL_MODE_WS1SCBTP )
00114 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS1SCBTP;
00115 #endif
00116 #if defined( MSC_READCTRL_MODE_WS2SCBTP ) || \
00117 defined( MSC_READCTRL_MODE_WS1SCBTP ) || defined( MSC_READCTRL_MODE_WS0SCBTP )
00118 break;
00119 #endif
00120 }
00121 MSC->READCTRL = cfg;
00122 }
00123
00124
00125
00131 __STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
00132 {
00133 uint32_t log2;
00134
00135
00136 EFM_ASSERT((div>0) && (div <= 32768));
00137
00138
00139 log2 = (31 - __CLZ(div));
00140
00141 return log2;
00142 }
00143
00144
00145
00150 __STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
00151 {
00152 return 1<<log2;
00153 }
00154
00155
00156
00164 static void CMU_FlashWaitStateControl(uint32_t hfcoreclk)
00165 {
00166 uint32_t cfg;
00167
00168 cfg = MSC->READCTRL;
00169
00170 #if defined( MSC_READCTRL_MODE_WS2 )
00171 if (hfcoreclk > CMU_MAX_FREQ_1WS)
00172 {
00173 switch(cfg & _MSC_READCTRL_MODE_MASK)
00174 {
00175 case MSC_READCTRL_MODE_WS0SCBTP:
00176 case MSC_READCTRL_MODE_WS1SCBTP:
00177 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS2SCBTP;
00178 break;
00179 case MSC_READCTRL_MODE_WS0:
00180 case MSC_READCTRL_MODE_WS1:
00181 default:
00182 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS2;
00183 break;
00184 }
00185 }
00186 #endif
00187
00188 if ((hfcoreclk > CMU_MAX_FREQ_0WS) && (hfcoreclk <= CMU_MAX_FREQ_1WS))
00189 {
00190 switch (cfg & _MSC_READCTRL_MODE_MASK)
00191 {
00192 #if defined( MSC_READCTRL_MODE_WS2SCBTP )
00193 case MSC_READCTRL_MODE_WS2SCBTP:
00194 #endif
00195 #if defined( MSC_READCTRL_MODE_WS1SCBTP ) && defined( MSC_READCTRL_MODE_WS0SCBTP )
00196 case MSC_READCTRL_MODE_WS0SCBTP:
00197 case MSC_READCTRL_MODE_WS1SCBTP:
00198 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS1SCBTP;
00199 #endif
00200 #if defined( MSC_READCTRL_MODE_WS2SCBTP ) || \
00201 defined( MSC_READCTRL_MODE_WS1SCBTP ) || defined( MSC_READCTRL_MODE_WS0SCBTP )
00202 break;
00203 #endif
00204
00205 default:
00206 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS1;
00207 break;
00208 }
00209 }
00210
00211 if (hfcoreclk <= CMU_MAX_FREQ_0WS)
00212 {
00213 switch (cfg & _MSC_READCTRL_MODE_MASK)
00214 {
00215 #if defined( MSC_READCTRL_MODE_WS2SCBTP )
00216 case MSC_READCTRL_MODE_WS2SCBTP:
00217 #endif
00218 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
00219 case MSC_READCTRL_MODE_WS1SCBTP:
00220 case MSC_READCTRL_MODE_WS0SCBTP:
00221 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS0SCBTP;
00222 #endif
00223 #if defined( MSC_READCTRL_MODE_WS2SCBTP ) || \
00224 defined( MSC_READCTRL_MODE_WS1SCBTP ) || defined( MSC_READCTRL_MODE_WS0SCBTP )
00225 break;
00226 #endif
00227
00228 default:
00229 cfg = (cfg & ~_MSC_READCTRL_MODE_MASK) | MSC_READCTRL_MODE_WS0;
00230 break;
00231 }
00232 }
00233
00234 MSC->READCTRL = cfg;
00235 }
00236
00237
00238 #if defined(USB_PRESENT)
00239
00246 static uint32_t CMU_USBCClkGet(void)
00247 {
00248 uint32_t ret;
00249 CMU_Select_TypeDef clk;
00250
00251
00252 clk = CMU_ClockSelectGet(cmuClock_USBC);
00253
00254 switch(clk)
00255 {
00256 case cmuSelect_LFXO:
00257 ret = SystemLFXOClockGet();
00258 break;
00259 case cmuSelect_LFRCO:
00260 ret = SystemLFRCOClockGet();
00261 break;
00262 case cmuSelect_HFCLK:
00263 ret = SystemHFClockGet();
00264 break;
00265 default:
00266
00267 ret = 0;
00268 break;
00269 }
00270 return ret;
00271 }
00272 #endif
00273
00274
00275
00283 static uint32_t CMU_AUXClkGet(void)
00284 {
00285 uint32_t ret;
00286
00287 #if defined(_EFM32_GECKO_FAMILY)
00288
00289 ret = 14000000;
00290 #else
00291 switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
00292 {
00293 case CMU_AUXHFRCOCTRL_BAND_1MHZ:
00294 ret = 1000000;
00295 break;
00296 case CMU_AUXHFRCOCTRL_BAND_7MHZ:
00297 ret = 7000000;
00298 break;
00299 case CMU_AUXHFRCOCTRL_BAND_11MHZ:
00300 ret = 11000000;
00301 break;
00302 case CMU_AUXHFRCOCTRL_BAND_14MHZ:
00303 ret = 14000000;
00304 break;
00305 case CMU_AUXHFRCOCTRL_BAND_21MHZ:
00306 ret = 21000000;
00307 break;
00308 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
00309 case CMU_AUXHFRCOCTRL_BAND_28MHZ:
00310 ret = 28000000;
00311 break;
00312 #endif
00313 default:
00314 ret = 0;
00315 break;
00316 }
00317 #endif
00318 return ret;
00319 }
00320
00321
00322
00329 static uint32_t CMU_DBGClkGet(void)
00330 {
00331 uint32_t ret;
00332 CMU_Select_TypeDef clk;
00333
00334
00335 clk = CMU_ClockSelectGet(cmuClock_DBG);
00336
00337 switch(clk)
00338 {
00339 case cmuSelect_HFCLK:
00340 ret = SystemHFClockGet();
00341 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00342
00343 ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
00344 _CMU_CTRL_HFCLKDIV_SHIFT));
00345 #endif
00346 break;
00347
00348 case cmuSelect_AUXHFRCO:
00349 ret = CMU_AUXClkGet();
00350 break;
00351
00352 default:
00353 EFM_ASSERT(0);
00354 ret = 0;
00355 break;
00356 }
00357 return ret;
00358 }
00359
00360
00361
00372 static uint32_t CMU_LFClkGet(unsigned int lfClkBranch)
00373 {
00374 uint32_t ret;
00375
00376 EFM_ASSERT(lfClkBranch == CMU_LFA || lfClkBranch == CMU_LFB);
00377
00378 switch ((CMU->LFCLKSEL >> (lfClkBranch * 2)) & 0x3)
00379 {
00380 case _CMU_LFCLKSEL_LFA_LFRCO:
00381 ret = SystemLFRCOClockGet();
00382 break;
00383
00384 case _CMU_LFCLKSEL_LFA_LFXO:
00385 ret = SystemLFXOClockGet();
00386 break;
00387
00388 case _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
00389 #if defined( CMU_CTRL_HFLE )
00390
00391 if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK) == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)||
00392 (CMU->CTRL & CMU_CTRL_HFLE))
00393 {
00394 ret = SystemCoreClockGet() / 4;
00395 }
00396 else
00397 {
00398 ret = SystemCoreClockGet() / 2;
00399 }
00400 #else
00401 ret = SystemCoreClockGet() / 2;
00402 #endif
00403 break;
00404
00405 case _CMU_LFCLKSEL_LFA_DISABLED:
00406 #if defined( CMU_LFCLKSEL_LFAE )
00407
00408 if(CMU->LFCLKSEL >> (_CMU_LFCLKSEL_LFAE_SHIFT + lfClkBranch * 4))
00409 {
00410 ret = SystemULFRCOClockGet();
00411 }
00412 else
00413 {
00414 ret = 0;
00415 }
00416 #else
00417 ret = 0;
00418 #endif
00419 break;
00420
00421 default:
00422 ret = 0;
00423 break;
00424 }
00425
00426 return ret;
00427 }
00428
00429
00430
00438 __STATIC_INLINE void CMU_Sync(uint32_t mask)
00439 {
00440
00441
00442 if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
00443 return;
00444
00445
00446
00447 while (CMU->SYNCBUSY & mask)
00448 ;
00449 }
00450
00451
00454
00455
00456
00457
00458
00480 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef ref)
00481 {
00482 EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
00483
00484
00485 switch (ref)
00486 {
00487 case cmuOsc_LFXO:
00488 CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
00489 break;
00490
00491 case cmuOsc_LFRCO:
00492 CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
00493 break;
00494
00495 case cmuOsc_HFXO:
00496 CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
00497 break;
00498
00499 case cmuOsc_HFRCO:
00500 CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
00501 break;
00502
00503 case cmuOsc_AUXHFRCO:
00504 CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
00505 break;
00506
00507 default:
00508 EFM_ASSERT(0);
00509 return 0;
00510 }
00511
00512
00513 CMU->CALCNT = HFCycles;
00514
00515
00516 CMU->CMD = CMU_CMD_CALSTART;
00517
00518
00519 while (CMU->STATUS & CMU_STATUS_CALBSY)
00520 ;
00521
00522 return CMU->CALCNT;
00523 }
00524
00525
00526 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
00527
00553 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
00554 CMU_Osc_TypeDef upSel)
00555 {
00556
00557 uint32_t calCtrl = CMU->CALCTRL & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);
00558
00559
00560 EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
00561
00562
00563 switch (downSel)
00564 {
00565 case cmuOsc_LFXO:
00566 calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
00567 break;
00568
00569 case cmuOsc_LFRCO:
00570 calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;
00571 break;
00572
00573 case cmuOsc_HFXO:
00574 calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;
00575 break;
00576
00577 case cmuOsc_HFRCO:
00578 calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;
00579 break;
00580
00581 case cmuOsc_AUXHFRCO:
00582 calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
00583 break;
00584
00585 default:
00586 EFM_ASSERT(0);
00587 break;
00588 }
00589
00590
00591 CMU->CALCNT = downCycles;
00592
00593
00594 switch (upSel)
00595 {
00596 case cmuOsc_LFXO:
00597 calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
00598 break;
00599
00600 case cmuOsc_LFRCO:
00601 calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;
00602 break;
00603
00604 case cmuOsc_HFXO:
00605 calCtrl |= CMU_CALCTRL_UPSEL_HFXO;
00606 break;
00607
00608 case cmuOsc_HFRCO:
00609 calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;
00610 break;
00611
00612 case cmuOsc_AUXHFRCO:
00613 calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
00614 break;
00615
00616 default:
00617 EFM_ASSERT(0);
00618 break;
00619 }
00620
00621 CMU->CALCTRL = calCtrl;
00622 }
00623 #endif
00624
00625
00626
00638 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
00639 {
00640 uint32_t divReg;
00641 CMU_ClkDiv_TypeDef ret;
00642
00643
00644 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
00645
00646 switch (divReg)
00647 {
00648 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00649 case CMU_HFCLKDIV_REG:
00650 ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
00651 _CMU_CTRL_HFCLKDIV_SHIFT);
00652 break;
00653 #endif
00654
00655 case CMU_HFPERCLKDIV_REG:
00656 ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV &
00657 _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>
00658 _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
00659 ret = CMU_Log2ToDiv(ret);
00660 break;
00661
00662 case CMU_HFCORECLKDIV_REG:
00663 ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV &
00664 _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >>
00665 _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
00666 ret = CMU_Log2ToDiv(ret);
00667 break;
00668
00669 case CMU_LFAPRESC0_REG:
00670 switch (clock)
00671 {
00672 case cmuClock_RTC:
00673 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >>
00674 _CMU_LFAPRESC0_RTC_SHIFT));
00675 ret = CMU_Log2ToDiv(ret);
00676 break;
00677
00678 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
00679 case cmuClock_LETIMER0:
00680 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >>
00681 _CMU_LFAPRESC0_LETIMER0_SHIFT));
00682 ret = CMU_Log2ToDiv(ret);
00683 break;
00684 #endif
00685
00686 #if defined(_CMU_LFAPRESC0_LCD_MASK)
00687 case cmuClock_LCDpre:
00688 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>
00689 _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16));
00690 ret = CMU_Log2ToDiv(ret);
00691 break;
00692 #endif
00693
00694 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
00695 case cmuClock_LESENSE:
00696 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >>
00697 _CMU_LFAPRESC0_LESENSE_SHIFT));
00698 ret = CMU_Log2ToDiv(ret);
00699 break;
00700 #endif
00701
00702 default:
00703 EFM_ASSERT(0);
00704 ret = cmuClkDiv_1;
00705 break;
00706 }
00707 break;
00708
00709 case CMU_LFBPRESC0_REG:
00710 switch (clock)
00711 {
00712 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
00713 case cmuClock_LEUART0:
00714 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >>
00715 _CMU_LFBPRESC0_LEUART0_SHIFT));
00716 ret = CMU_Log2ToDiv(ret);
00717 break;
00718 #endif
00719
00720 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
00721 case cmuClock_LEUART1:
00722 ret = (CMU_ClkDiv_TypeDef)(((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >>
00723 _CMU_LFBPRESC0_LEUART1_SHIFT));
00724 ret = CMU_Log2ToDiv(ret);
00725 break;
00726 #endif
00727
00728 default:
00729 EFM_ASSERT(0);
00730 ret = cmuClkDiv_1;
00731 break;
00732 }
00733 break;
00734
00735 default:
00736 EFM_ASSERT(0);
00737 ret = cmuClkDiv_1;
00738 break;
00739 }
00740
00741 return(ret);
00742 }
00743
00744
00745
00764 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
00765 {
00766 uint32_t freq;
00767 uint32_t divReg;
00768
00769
00770 divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
00771
00772 switch (divReg)
00773 {
00774 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00775 case CMU_HFCLKDIV_REG:
00776 EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
00777
00778
00779 CMU_FlashWaitStateMax();
00780
00781
00782 CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK) |
00783 ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
00784
00785
00786
00787 freq = SystemCoreClockGet();
00788
00789
00790 CMU_FlashWaitStateControl(freq);
00791 break;
00792 #endif
00793
00794 case CMU_HFPERCLKDIV_REG:
00795 EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
00796
00797 div = CMU_DivToLog2(div);
00798 CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) |
00799 (div << _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT);
00800 break;
00801
00802 case CMU_HFCORECLKDIV_REG:
00803 EFM_ASSERT(div <= cmuClkDiv_512);
00804
00805
00806 CMU_FlashWaitStateMax();
00807
00808 #if defined( CMU_CTRL_HFLE )
00809
00810
00811 if ( (cmuSelect_HFXO != CMU_ClockSelectGet(cmuClock_HF)) ||
00812 ((SystemHFXOClockGet()/div) <= CMU_MAX_FREQ_HFLE) )
00813 {
00814
00815 BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 0);
00816
00817
00818 BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
00819 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);
00820 }
00821 else
00822 {
00823
00824 BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
00825
00826
00827 BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
00828 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
00829 }
00830 #endif
00831
00832
00833 div = CMU_DivToLog2(div);
00834
00835 CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV & ~_CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) |
00836 (div << _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT);
00837
00838
00839
00840 freq = SystemCoreClockGet();
00841
00842
00843 CMU_FlashWaitStateControl(freq);
00844 break;
00845
00846 case CMU_LFAPRESC0_REG:
00847 switch (clock)
00848 {
00849 case cmuClock_RTC:
00850 EFM_ASSERT(div <= cmuClkDiv_32768);
00851
00852
00853 CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
00854
00855
00856 div = CMU_DivToLog2(div);
00857
00858 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK) |
00859 (div << _CMU_LFAPRESC0_RTC_SHIFT);
00860 break;
00861
00862 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
00863 case cmuClock_LETIMER0:
00864 EFM_ASSERT(div <= cmuClkDiv_32768);
00865
00866
00867 CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
00868
00869
00870 div = CMU_DivToLog2(div);
00871
00872 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK) |
00873 (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
00874 break;
00875 #endif
00876
00877 #if defined(LCD_PRESENT)
00878 case cmuClock_LCDpre:
00879 EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
00880
00881
00882 CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
00883
00884
00885 div = CMU_DivToLog2(div);
00886
00887 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK) |
00888 ((div - CMU_DivToLog2(cmuClkDiv_16)) << _CMU_LFAPRESC0_LCD_SHIFT);
00889 break;
00890 #endif
00891
00892 #if defined(LESENSE_PRESENT)
00893 case cmuClock_LESENSE:
00894 EFM_ASSERT(div <= cmuClkDiv_8);
00895
00896
00897 CMU_Sync(CMU_SYNCBUSY_LFAPRESC0);
00898
00899
00900 div = CMU_DivToLog2(div);
00901
00902 CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK) |
00903 (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
00904 break;
00905 #endif
00906
00907 default:
00908 EFM_ASSERT(0);
00909 break;
00910 }
00911 break;
00912
00913 case CMU_LFBPRESC0_REG:
00914 switch (clock)
00915 {
00916 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
00917 case cmuClock_LEUART0:
00918 EFM_ASSERT(div <= cmuClkDiv_8);
00919
00920
00921 CMU_Sync(CMU_SYNCBUSY_LFBPRESC0);
00922
00923
00924 div = CMU_DivToLog2(div);
00925
00926 CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK) |
00927 (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
00928 break;
00929 #endif
00930
00931 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
00932 case cmuClock_LEUART1:
00933 EFM_ASSERT(div <= cmuClkDiv_8);
00934
00935
00936 CMU_Sync(CMU_SYNCBUSY_LFBPRESC0);
00937
00938
00939 div = CMU_DivToLog2(div);
00940
00941 CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK) |
00942 (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
00943 break;
00944 #endif
00945
00946 default:
00947 EFM_ASSERT(0);
00948 break;
00949 }
00950 break;
00951
00952 default:
00953 EFM_ASSERT(0);
00954 break;
00955 }
00956 }
00957
00958
00959
00986 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
00987 {
00988 volatile uint32_t *reg;
00989 uint32_t bit;
00990 uint32_t sync = 0;
00991
00992
00993 switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
00994 {
00995 case CMU_HFPERCLKDIV_EN_REG:
00996 reg = &(CMU->HFPERCLKDIV);
00997 break;
00998
00999 case CMU_HFPERCLKEN0_EN_REG:
01000 reg = &(CMU->HFPERCLKEN0);
01001 break;
01002
01003 case CMU_HFCORECLKEN0_EN_REG:
01004 reg = &(CMU->HFCORECLKEN0);
01005
01006 #if defined( CMU_CTRL_HFLE )
01007
01008
01009 if ( (cmuSelect_HFXO == CMU_ClockSelectGet(cmuClock_HF)) &&
01010 ((SystemHFXOClockGet()/CMU_ClockDivGet(cmuClock_CORE)) >
01011 CMU_MAX_FREQ_HFLE) )
01012 {
01013
01014 BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
01015
01016
01017 BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
01018 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
01019 }
01020 #endif
01021 break;
01022
01023 case CMU_LFACLKEN0_EN_REG:
01024 reg = &(CMU->LFACLKEN0);
01025 sync = CMU_SYNCBUSY_LFACLKEN0;
01026 break;
01027
01028 case CMU_LFBCLKEN0_EN_REG:
01029 reg = &(CMU->LFBCLKEN0);
01030 sync = CMU_SYNCBUSY_LFBCLKEN0;
01031 break;
01032
01033 case CMU_PCNT_EN_REG:
01034 reg = &(CMU->PCNTCTRL);
01035 break;
01036
01037 default:
01038 EFM_ASSERT(0);
01039 return;
01040 }
01041
01042
01043 bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
01044
01045
01046 if (sync)
01047 {
01048 CMU_Sync(sync);
01049 }
01050
01051
01052 BITBAND_Peripheral(reg, bit, (unsigned int)enable);
01053 }
01054
01055
01056
01066 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
01067 {
01068 uint32_t ret;
01069
01070 switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
01071 {
01072 case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01073 {
01074 ret = SystemHFClockGet();
01075 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
01076
01077 ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
01078 _CMU_CTRL_HFCLKDIV_SHIFT));
01079 #endif
01080 } break;
01081
01082 #if defined(_CMU_HFPERCLKEN0_USART0_MASK) || \
01083 defined(_CMU_HFPERCLKEN0_USART1_MASK) || \
01084 defined(_CMU_HFPERCLKEN0_USART2_MASK) || \
01085 defined(_CMU_HFPERCLKEN0_UART0_MASK) || \
01086 defined(_CMU_HFPERCLKEN0_UART1_MASK) || \
01087 defined(_CMU_HFPERCLKEN0_TIMER0_MASK) || \
01088 defined(_CMU_HFPERCLKEN0_TIMER1_MASK) || \
01089 defined(_CMU_HFPERCLKEN0_TIMER2_MASK) || \
01090 defined(_CMU_HFPERCLKEN0_TIMER3_MASK) || \
01091 defined(_CMU_HFPERCLKEN0_ACMP0_MASK) || \
01092 defined(_CMU_HFPERCLKEN0_ACMP1_MASK) || \
01093 defined(_CMU_HFPERCLKEN0_DAC0_MASK) || \
01094 defined(_CMU_HFPERCLKEN0_IDAC0_MASK) || \
01095 defined(_CMU_HFPERCLKEN0_ADC0_MASK) || \
01096 defined(_CMU_HFPERCLKEN0_I2C0_MASK) || \
01097 defined(_CMU_HFPERCLKEN0_I2C1_MASK) || \
01098 defined(PRS_PRESENT) || \
01099 defined(VCMP_PRESENT)|| \
01100 defined(GPIO_PRESENT)
01101 case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01102 {
01103 ret = SystemHFClockGet();
01104 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
01105
01106 ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK) >>
01107 _CMU_CTRL_HFCLKDIV_SHIFT));
01108 #endif
01109 ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) >>
01110 _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT;
01111 } break;
01112 #endif
01113
01114 #if defined(AES_PRESENT) || \
01115 defined(DMA_PRESENT) || \
01116 defined(EBI_PRESENT) || \
01117 defined(USB_PRESENT)
01118 case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01119 {
01120 ret = SystemCoreClockGet();
01121 } break;
01122 #endif
01123
01124 case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01125 {
01126 ret = CMU_LFClkGet(CMU_LFA);
01127 } break;
01128 #if defined(_CMU_LFACLKEN0_RTC_MASK)
01129 case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01130 {
01131 ret = CMU_LFClkGet(CMU_LFA);
01132 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK) >>
01133 _CMU_LFAPRESC0_RTC_SHIFT;
01134 } break;
01135 #endif
01136 #if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
01137 case (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01138 {
01139 ret = CMU_LFClkGet(CMU_LFA);
01140 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK) >>
01141 _CMU_LFAPRESC0_LETIMER0_SHIFT;
01142 } break;
01143 #endif
01144 #if defined(_CMU_LFACLKEN0_LCD_MASK)
01145 case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01146 {
01147 ret = CMU_LFClkGet(CMU_LFA);
01148 ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>
01149 _CMU_LFAPRESC0_LCD_SHIFT) + CMU_DivToLog2(cmuClkDiv_16);
01150 } break;
01151
01152 case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01153 {
01154 ret = CMU_LFClkGet(CMU_LFA);
01155 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK) >>
01156 _CMU_LFAPRESC0_LCD_SHIFT;
01157 ret /= (1 + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >>
01158 _CMU_LCDCTRL_FDIV_SHIFT));
01159 } break;
01160 #endif
01161 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
01162 case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01163 {
01164 ret = CMU_LFClkGet(CMU_LFA);
01165 ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK) >>
01166 _CMU_LFAPRESC0_LESENSE_SHIFT;
01167 } break;
01168 #endif
01169 case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01170 {
01171 ret = CMU_LFClkGet(CMU_LFB);
01172 } break;
01173 #if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
01174 case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01175 {
01176 ret = CMU_LFClkGet(CMU_LFB);
01177 ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK) >>
01178 _CMU_LFBPRESC0_LEUART0_SHIFT;
01179 } break;
01180 #endif
01181 #if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
01182 case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01183 {
01184 ret = CMU_LFClkGet(CMU_LFB);
01185 ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK) >>
01186 _CMU_LFBPRESC0_LEUART1_SHIFT;
01187 } break;
01188 #endif
01189
01190 case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01191 {
01192 ret = CMU_DBGClkGet();
01193 } break;
01194
01195 case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01196 {
01197 ret = CMU_AUXClkGet();
01198 } break;
01199
01200 #if defined(USB_PRESENT)
01201 case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
01202 {
01203 ret = CMU_USBCClkGet();
01204 } break;
01205 #endif
01206 default:
01207 {
01208 EFM_ASSERT(0);
01209 ret = 0;
01210 } break;
01211 }
01212 return ret;
01213 }
01214
01215
01216
01233 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
01234 {
01235 CMU_Select_TypeDef ret = cmuSelect_Disabled;
01236 uint32_t selReg;
01237
01238 selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
01239
01240 switch (selReg)
01241 {
01242 case CMU_HFCLKSEL_REG:
01243 switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL |
01244 CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL))
01245 {
01246 case CMU_STATUS_LFXOSEL:
01247 ret = cmuSelect_LFXO;
01248 break;
01249
01250 case CMU_STATUS_LFRCOSEL:
01251 ret = cmuSelect_LFRCO;
01252 break;
01253
01254 case CMU_STATUS_HFXOSEL:
01255 ret = cmuSelect_HFXO;
01256 break;
01257
01258 default:
01259 ret = cmuSelect_HFRCO;
01260 break;
01261 }
01262 break;
01263
01264 case CMU_LFACLKSEL_REG:
01265 switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
01266 {
01267 case CMU_LFCLKSEL_LFA_LFRCO:
01268 ret = cmuSelect_LFRCO;
01269 break;
01270
01271 case CMU_LFCLKSEL_LFA_LFXO:
01272 ret = cmuSelect_LFXO;
01273 break;
01274
01275 case CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2:
01276 ret = cmuSelect_CORELEDIV2;
01277 break;
01278
01279 default:
01280 #if defined( CMU_LFCLKSEL_LFAE )
01281 if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
01282 {
01283 ret = cmuSelect_ULFRCO;
01284 break;
01285 }
01286 #else
01287 ret = cmuSelect_Disabled;
01288 #endif
01289 break;
01290 }
01291 break;
01292
01293 case CMU_LFBCLKSEL_REG:
01294 switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
01295 {
01296 case CMU_LFCLKSEL_LFB_LFRCO:
01297 ret = cmuSelect_LFRCO;
01298 break;
01299
01300 case CMU_LFCLKSEL_LFB_LFXO:
01301 ret = cmuSelect_LFXO;
01302 break;
01303
01304 case CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2:
01305 ret = cmuSelect_CORELEDIV2;
01306 break;
01307
01308 default:
01309 #if defined( CMU_LFCLKSEL_LFBE )
01310 if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
01311 {
01312 ret = cmuSelect_ULFRCO;
01313 break;
01314 }
01315 #else
01316 ret = cmuSelect_Disabled;
01317 #endif
01318 break;
01319 }
01320 break;
01321
01322 case CMU_DBGCLKSEL_REG:
01323 #if defined( CMU_CTRL_DBGCLK )
01324 switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
01325 {
01326 case CMU_CTRL_DBGCLK_AUXHFRCO:
01327 ret = cmuSelect_AUXHFRCO;
01328 break;
01329
01330 case CMU_CTRL_DBGCLK_HFCLK:
01331 ret = cmuSelect_HFCLK;
01332 break;
01333 }
01334 #endif
01335 #if defined(_EFM32_GECKO_FAMILY)
01336 ret = cmuSelect_AUXHFRCO;
01337 #endif
01338 break;
01339
01340
01341 #if defined(USB_PRESENT)
01342 case CMU_USBCCLKSEL_REG:
01343 switch(CMU->STATUS & (CMU_STATUS_USBCHFCLKSEL |
01344 CMU_STATUS_USBCLFXOSEL |
01345 CMU_STATUS_USBCLFRCOSEL))
01346 {
01347 case CMU_STATUS_USBCHFCLKSEL:
01348 ret = cmuSelect_HFCLK;
01349 break;
01350
01351 case CMU_STATUS_USBCLFXOSEL:
01352 ret = cmuSelect_LFXO;
01353 break;
01354
01355 case CMU_STATUS_USBCLFRCOSEL:
01356 ret = cmuSelect_LFRCO;
01357 break;
01358
01359 default:
01360 ret = cmuSelect_Disabled;
01361 break;
01362 }
01363 break;
01364 #endif
01365
01366 default:
01367 EFM_ASSERT(0);
01368 ret = cmuSelect_Error;
01369 break;
01370 }
01371
01372 return ret;
01373 }
01374
01375
01376
01412 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
01413 {
01414 uint32_t select = cmuOsc_HFRCO;
01415 CMU_Osc_TypeDef osc = cmuOsc_HFRCO;
01416 uint32_t freq;
01417 uint32_t selReg;
01418 #if !defined(_EFM32_GECKO_FAMILY)
01419 uint32_t lfExtended = 0;
01420 #endif
01421 uint32_t tmp;
01422
01423 selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
01424
01425 switch (selReg)
01426 {
01427 case CMU_HFCLKSEL_REG:
01428 switch (ref)
01429 {
01430 case cmuSelect_LFXO:
01431 select = CMU_CMD_HFCLKSEL_LFXO;
01432 osc = cmuOsc_LFXO;
01433 break;
01434
01435 case cmuSelect_LFRCO:
01436 select = CMU_CMD_HFCLKSEL_LFRCO;
01437 osc = cmuOsc_LFRCO;
01438 break;
01439
01440 case cmuSelect_HFXO:
01441 select = CMU_CMD_HFCLKSEL_HFXO;
01442 osc = cmuOsc_HFXO;
01443 #if defined( CMU_CTRL_HFLE )
01444
01445
01446 if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE)
01447 {
01448 CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
01449 CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ |
01450
01451 CMU_CTRL_HFLE;
01452
01453
01454
01455 if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)
01456 {
01457 BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
01458 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
01459 }
01460 } else {
01461
01462
01463 CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK) |
01464 CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
01465 }
01466 #endif
01467 break;
01468
01469 case cmuSelect_HFRCO:
01470 select = CMU_CMD_HFCLKSEL_HFRCO;
01471 osc = cmuOsc_HFRCO;
01472 break;
01473
01474 #if !defined(_EFM32_GECKO_FAMILY)
01475 case cmuSelect_ULFRCO:
01476
01477 EFM_ASSERT(0);
01478 break;
01479 #endif
01480
01481 default:
01482 EFM_ASSERT(0);
01483 return;
01484 }
01485
01486
01487 CMU_OscillatorEnable(osc, true, true);
01488
01489
01490 CMU_FlashWaitStateMax();
01491
01492
01493 CMU->CMD = select;
01494
01495
01496 EMU_UpdateOscConfig();
01497
01498
01499
01500 freq = SystemCoreClockGet();
01501
01502
01503 CMU_FlashWaitStateControl(freq);
01504 break;
01505
01506 case CMU_LFACLKSEL_REG:
01507 case CMU_LFBCLKSEL_REG:
01508
01509 switch (ref)
01510 {
01511 case cmuSelect_Disabled:
01512 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
01513 break;
01514
01515 case cmuSelect_LFXO:
01516
01517 CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
01518 tmp = _CMU_LFCLKSEL_LFA_LFXO;
01519 break;
01520
01521 case cmuSelect_LFRCO:
01522
01523 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
01524 tmp = _CMU_LFCLKSEL_LFA_LFRCO;
01525 break;
01526
01527 case cmuSelect_CORELEDIV2:
01528
01529 BITBAND_Peripheral(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);
01530 tmp = _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2;
01531 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
01532
01533 freq = SystemCoreClockGet();
01534 if(freq > CMU_MAX_FREQ_HFLE)
01535 {
01536
01537 BITBAND_Peripheral(&(CMU->CTRL), _CMU_CTRL_HFLE_SHIFT, 1);
01538
01539
01540 BITBAND_Peripheral(&(CMU->HFCORECLKDIV),
01541 _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
01542 }
01543 #endif
01544 break;
01545
01546 #if !defined(_EFM32_GECKO_FAMILY)
01547 case cmuSelect_ULFRCO:
01548
01549 tmp = _CMU_LFCLKSEL_LFA_DISABLED;
01550 lfExtended = 1;
01551 break;
01552 #endif
01553
01554 default:
01555
01556 EFM_ASSERT(0);
01557 return;
01558 }
01559
01560
01561 if (selReg == CMU_LFACLKSEL_REG)
01562 {
01563 #if !defined(_EFM32_GECKO_FAMILY)
01564 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK) ) |
01565 (tmp << _CMU_LFCLKSEL_LFA_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
01566 #else
01567 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK) |
01568 (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
01569 #endif
01570 }
01571 else
01572 {
01573 #if !defined(_EFM32_GECKO_FAMILY)
01574 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK) ) |
01575 (tmp << _CMU_LFCLKSEL_LFB_SHIFT) | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
01576 #else
01577 CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK) |
01578 (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
01579 #endif
01580 }
01581 break;
01582
01583 #if defined( CMU_CTRL_DBGCLK )
01584 case CMU_DBGCLKSEL_REG:
01585 switch(ref)
01586 {
01587 case cmuSelect_AUXHFRCO:
01588
01589 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))| CMU_CTRL_DBGCLK_AUXHFRCO;
01590 break;
01591
01592 case cmuSelect_HFCLK:
01593
01594 CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))| CMU_CTRL_DBGCLK_HFCLK;
01595 break;
01596
01597 default:
01598
01599 EFM_ASSERT(0);
01600 return;
01601 }
01602 break;
01603 #endif
01604
01605 #if defined(USB_PRESENT)
01606 case CMU_USBCCLKSEL_REG:
01607 switch(ref)
01608 {
01609
01610 case cmuSelect_HFCLK:
01611
01612
01613 CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
01614
01615 while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0);
01616 break;
01617
01618 case cmuSelect_LFXO:
01619
01620
01621
01622 CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
01623
01624
01625 CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
01626
01627
01628 while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0);
01629 break;
01630
01631 case cmuSelect_LFRCO:
01632
01633
01634
01635 CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
01636
01637
01638 CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
01639
01640
01641 while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0);
01642 break;
01643
01644 default:
01645
01646 EFM_ASSERT(0);
01647 return;
01648 }
01649
01650 break;
01651 #endif
01652
01653 default:
01654 EFM_ASSERT(0);
01655 break;
01656 }
01657 }
01658
01659
01660
01689 void CMU_FreezeEnable(bool enable)
01690 {
01691 if (enable)
01692 {
01693
01694
01695
01696
01697
01698
01699
01700 while (CMU->SYNCBUSY)
01701 ;
01702
01703 CMU->FREEZE = CMU_FREEZE_REGFREEZE;
01704 }
01705 else
01706 {
01707 CMU->FREEZE = 0;
01708 }
01709 }
01710
01711
01712 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
01713
01720 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
01721 {
01722 return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK) >>
01723 _CMU_AUXHFRCOCTRL_BAND_SHIFT);
01724 }
01725
01726
01734 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
01735 {
01736 uint32_t tuning;
01737
01738
01739 switch (band)
01740 {
01741 case cmuAUXHFRCOBand_1MHz:
01742 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK) >>
01743 _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
01744 break;
01745
01746 case cmuAUXHFRCOBand_7MHz:
01747 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK) >>
01748 _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
01749 break;
01750
01751 case cmuAUXHFRCOBand_11MHz:
01752 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK) >>
01753 _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
01754 break;
01755
01756 case cmuAUXHFRCOBand_14MHz:
01757 tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK) >>
01758 _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
01759 break;
01760
01761 case cmuAUXHFRCOBand_21MHz:
01762 tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK) >>
01763 _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
01764 break;
01765
01766 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
01767 case cmuAUXHFRCOBand_28MHz:
01768 tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK) >>
01769 _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
01770 break;
01771 #endif
01772
01773 default:
01774 EFM_ASSERT(0);
01775 return;
01776 }
01777
01778
01779 CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
01780 ~(_CMU_AUXHFRCOCTRL_BAND_MASK | _CMU_AUXHFRCOCTRL_TUNING_MASK)) |
01781 (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT) |
01782 (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
01783
01784 }
01785 #endif
01786
01787
01788
01795 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
01796 {
01797 return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) >>
01798 _CMU_HFRCOCTRL_BAND_SHIFT);
01799 }
01800
01801
01802
01810 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
01811 {
01812 uint32_t tuning;
01813 uint32_t freq;
01814 CMU_Select_TypeDef osc;
01815
01816
01817 switch (band)
01818 {
01819 case cmuHFRCOBand_1MHz:
01820 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK) >>
01821 _DEVINFO_HFRCOCAL0_BAND1_SHIFT;
01822 break;
01823
01824 case cmuHFRCOBand_7MHz:
01825 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK) >>
01826 _DEVINFO_HFRCOCAL0_BAND7_SHIFT;
01827 break;
01828
01829 case cmuHFRCOBand_11MHz:
01830 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK) >>
01831 _DEVINFO_HFRCOCAL0_BAND11_SHIFT;
01832 break;
01833
01834 case cmuHFRCOBand_14MHz:
01835 tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK) >>
01836 _DEVINFO_HFRCOCAL0_BAND14_SHIFT;
01837 break;
01838
01839 case cmuHFRCOBand_21MHz:
01840 tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK) >>
01841 _DEVINFO_HFRCOCAL1_BAND21_SHIFT;
01842 break;
01843
01844 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
01845 case cmuHFRCOBand_28MHz:
01846 tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK) >>
01847 _DEVINFO_HFRCOCAL1_BAND28_SHIFT;
01848 break;
01849 #endif
01850
01851 default:
01852 EFM_ASSERT(0);
01853 return;
01854 }
01855
01856
01857 osc = CMU_ClockSelectGet(cmuClock_HF);
01858 if (osc == cmuSelect_HFRCO)
01859 {
01860
01861 CMU_FlashWaitStateMax();
01862 }
01863
01864
01865 CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
01866 ~(_CMU_HFRCOCTRL_BAND_MASK | _CMU_HFRCOCTRL_TUNING_MASK)) |
01867 (band << _CMU_HFRCOCTRL_BAND_SHIFT) |
01868 (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
01869
01870
01871 if (osc == cmuSelect_HFRCO)
01872 {
01873
01874
01875
01876
01877 freq = SystemCoreClockGet();
01878
01879
01880 CMU_FlashWaitStateControl(freq);
01881 }
01882 }
01883
01884
01885
01895 uint32_t CMU_HFRCOStartupDelayGet(void)
01896 {
01897 return((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK) >>
01898 _CMU_HFRCOCTRL_SUDELAY_SHIFT);
01899 }
01900
01901
01902
01912 void CMU_HFRCOStartupDelaySet(uint32_t delay)
01913 {
01914 EFM_ASSERT(delay <= 31);
01915
01916 delay &= (_CMU_HFRCOCTRL_SUDELAY_MASK >> _CMU_HFRCOCTRL_SUDELAY_SHIFT);
01917 CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK)) |
01918 (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
01919 }
01920
01921
01922
01929 uint32_t CMU_LCDClkFDIVGet(void)
01930 {
01931 #if defined(LCD_PRESENT)
01932 return((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT);
01933 #else
01934 return 0;
01935 #endif
01936 }
01937
01938
01939
01952 void CMU_LCDClkFDIVSet(uint32_t div)
01953 {
01954 #if defined(LCD_PRESENT)
01955 EFM_ASSERT(div <= cmuClkDiv_128);
01956
01957
01958 if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
01959 {
01960 return;
01961 }
01962
01963 div <<= _CMU_LCDCTRL_FDIV_SHIFT;
01964 div &= _CMU_LCDCTRL_FDIV_MASK;
01965 CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div;
01966 #else
01967 (void)div;
01968 #endif
01969 }
01970
01971
01972
01996 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
01997 {
01998 uint32_t status;
01999 uint32_t enBit;
02000 uint32_t disBit;
02001
02002 switch (osc)
02003 {
02004 case cmuOsc_HFRCO:
02005 enBit = CMU_OSCENCMD_HFRCOEN;
02006 disBit = CMU_OSCENCMD_HFRCODIS;
02007 status = CMU_STATUS_HFRCORDY;
02008 break;
02009
02010 case cmuOsc_HFXO:
02011 enBit = CMU_OSCENCMD_HFXOEN;
02012 disBit = CMU_OSCENCMD_HFXODIS;
02013 status = CMU_STATUS_HFXORDY;
02014 break;
02015
02016 case cmuOsc_AUXHFRCO:
02017 enBit = CMU_OSCENCMD_AUXHFRCOEN;
02018 disBit = CMU_OSCENCMD_AUXHFRCODIS;
02019 status = CMU_STATUS_AUXHFRCORDY;
02020 break;
02021
02022 case cmuOsc_LFRCO:
02023 enBit = CMU_OSCENCMD_LFRCOEN;
02024 disBit = CMU_OSCENCMD_LFRCODIS;
02025 status = CMU_STATUS_LFRCORDY;
02026 break;
02027
02028 case cmuOsc_LFXO:
02029 enBit = CMU_OSCENCMD_LFXOEN;
02030 disBit = CMU_OSCENCMD_LFXODIS;
02031 status = CMU_STATUS_LFXORDY;
02032 break;
02033
02034 #if defined _CMU_LFCLKSEL_LFAE_ULFRCO
02035 case cmuOsc_ULFRCO:
02036
02037 return;
02038 #endif
02039
02040 default:
02041
02042 EFM_ASSERT(0);
02043 return;
02044 }
02045
02046 if (enable)
02047 {
02048 CMU->OSCENCMD = enBit;
02049
02050
02051 if (wait)
02052 {
02053 while (!(CMU->STATUS & status))
02054 ;
02055 }
02056 }
02057 else
02058 {
02059 CMU->OSCENCMD = disBit;
02060 }
02061
02062
02063 EMU_UpdateOscConfig();
02064 }
02065
02066
02067
02080 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
02081 {
02082 uint32_t ret;
02083
02084 switch (osc)
02085 {
02086 case cmuOsc_LFRCO:
02087 ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK) >>
02088 _CMU_LFRCOCTRL_TUNING_SHIFT;
02089 break;
02090
02091 case cmuOsc_HFRCO:
02092 ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK) >>
02093 _CMU_HFRCOCTRL_TUNING_SHIFT;
02094 break;
02095
02096 case cmuOsc_AUXHFRCO:
02097 ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK) >>
02098 _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
02099 break;
02100
02101 default:
02102 EFM_ASSERT(0);
02103 ret = 0;
02104 break;
02105 }
02106
02107 return(ret);
02108 }
02109
02110
02111
02129 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
02130 {
02131 switch (osc)
02132 {
02133 case cmuOsc_LFRCO:
02134 EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT));
02135
02136 val &= (_CMU_LFRCOCTRL_TUNING_MASK >> _CMU_LFRCOCTRL_TUNING_SHIFT);
02137 CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK)) |
02138 (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
02139 break;
02140
02141 case cmuOsc_HFRCO:
02142 EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT));
02143
02144 val &= (_CMU_HFRCOCTRL_TUNING_MASK >> _CMU_HFRCOCTRL_TUNING_SHIFT);
02145 CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK)) |
02146 (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
02147 break;
02148
02149 case cmuOsc_AUXHFRCO:
02150 EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK >> _CMU_AUXHFRCOCTRL_TUNING_SHIFT));
02151
02152 val <<= _CMU_AUXHFRCOCTRL_TUNING_SHIFT;
02153 val &= _CMU_AUXHFRCOCTRL_TUNING_MASK;
02154 CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK)) | val;
02155 break;
02156
02157 default:
02158 EFM_ASSERT(0);
02159 break;
02160 }
02161 }
02162
02163
02164
02175 bool CMU_PCNTClockExternalGet(unsigned int inst)
02176 {
02177 bool ret;
02178 uint32_t setting;
02179
02180 switch (inst)
02181 {
02182 #if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
02183 case 0:
02184 setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
02185 break;
02186
02187 #if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
02188 case 1:
02189 setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
02190 break;
02191
02192 #if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
02193 case 2:
02194 setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
02195 break;
02196 #endif
02197 #endif
02198 #endif
02199
02200 default:
02201 setting = 0;
02202 break;
02203 }
02204
02205 if (setting)
02206 {
02207 ret = true;
02208 }
02209 else
02210 {
02211 ret = false;
02212 }
02213 return ret;
02214 }
02215
02216
02217
02227 void CMU_PCNTClockExternalSet(unsigned int inst, bool external)
02228 {
02229 #if defined(PCNT_PRESENT)
02230 uint32_t setting = 0;
02231
02232 EFM_ASSERT(inst < PCNT_COUNT);
02233
02234 if (external)
02235 {
02236 setting = 1;
02237 }
02238
02239 BITBAND_Peripheral(&(CMU->PCNTCTRL), (inst * 2) + 1, setting);
02240
02241 #else
02242 (void)inst;
02243 (void)external;
02244 #endif
02245 }
02246
02247
02250 #endif