em_usart.h

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00001 /***************************************************************************/
00035 #ifndef __EM_USART_H
00036 #define __EM_USART_H
00037 
00038 #include "em_device.h"
00039 #if defined(USART_COUNT) && (USART_COUNT > 0)
00040 
00041 #include <stdbool.h>
00042 
00043 #ifdef __cplusplus
00044 extern "C" {
00045 #endif
00046 
00047 /***************************************************************************/
00052 /***************************************************************************/
00058 /*******************************************************************************
00059  ********************************   ENUMS   ************************************
00060  ******************************************************************************/
00061 
00063 typedef enum
00064 {
00065   usartDatabits4  = USART_FRAME_DATABITS_FOUR,     
00066   usartDatabits5  = USART_FRAME_DATABITS_FIVE,     
00067   usartDatabits6  = USART_FRAME_DATABITS_SIX,      
00068   usartDatabits7  = USART_FRAME_DATABITS_SEVEN,    
00069   usartDatabits8  = USART_FRAME_DATABITS_EIGHT,    
00070   usartDatabits9  = USART_FRAME_DATABITS_NINE,     
00071   usartDatabits10 = USART_FRAME_DATABITS_TEN,      
00072   usartDatabits11 = USART_FRAME_DATABITS_ELEVEN,   
00073   usartDatabits12 = USART_FRAME_DATABITS_TWELVE,   
00074   usartDatabits13 = USART_FRAME_DATABITS_THIRTEEN, 
00075   usartDatabits14 = USART_FRAME_DATABITS_FOURTEEN, 
00076   usartDatabits15 = USART_FRAME_DATABITS_FIFTEEN,  
00077   usartDatabits16 = USART_FRAME_DATABITS_SIXTEEN   
00078 } USART_Databits_TypeDef;
00079 
00080 
00082 typedef enum
00083 {
00085   usartDisable  = 0x0,
00086 
00088   usartEnableRx = USART_CMD_RXEN,
00089 
00091   usartEnableTx = USART_CMD_TXEN,
00092 
00094   usartEnable   = (USART_CMD_RXEN | USART_CMD_TXEN)
00095 } USART_Enable_TypeDef;
00096 
00097 
00099 typedef enum
00100 {
00101   usartOVS16 = USART_CTRL_OVS_X16,     
00102   usartOVS8  = USART_CTRL_OVS_X8,      
00103   usartOVS6  = USART_CTRL_OVS_X6,      
00104   usartOVS4  = USART_CTRL_OVS_X4       
00105 } USART_OVS_TypeDef;
00106 
00107 
00109 typedef enum
00110 {
00111   usartNoParity   = USART_FRAME_PARITY_NONE,    
00112   usartEvenParity = USART_FRAME_PARITY_EVEN,    
00113   usartOddParity  = USART_FRAME_PARITY_ODD      
00114 } USART_Parity_TypeDef;
00115 
00116 
00118 typedef enum
00119 {
00120   usartStopbits0p5 = USART_FRAME_STOPBITS_HALF,        
00121   usartStopbits1   = USART_FRAME_STOPBITS_ONE,         
00122   usartStopbits1p5 = USART_FRAME_STOPBITS_ONEANDAHALF, 
00123   usartStopbits2   = USART_FRAME_STOPBITS_TWO          
00124 } USART_Stopbits_TypeDef;
00125 
00126 
00128 typedef enum
00129 {
00131   usartClockMode0 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLELEADING,
00132 
00134   usartClockMode1 = USART_CTRL_CLKPOL_IDLELOW | USART_CTRL_CLKPHA_SAMPLETRAILING,
00135 
00137   usartClockMode2 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLELEADING,
00138 
00140   usartClockMode3 = USART_CTRL_CLKPOL_IDLEHIGH | USART_CTRL_CLKPHA_SAMPLETRAILING
00141 } USART_ClockMode_TypeDef;
00142 
00143 
00145 typedef enum
00146 {
00148   usartIrDAPwONE   = USART_IRCTRL_IRPW_ONE,
00149 
00151   usartIrDAPwTWO   = USART_IRCTRL_IRPW_TWO,
00152 
00154   usartIrDAPwTHREE = USART_IRCTRL_IRPW_THREE,
00155 
00157   usartIrDAPwFOUR  = USART_IRCTRL_IRPW_FOUR
00158 } USART_IrDAPw_Typedef;
00159 
00160 
00162 typedef enum
00163 {
00164   usartIrDAPrsCh0 = USART_IRCTRL_IRPRSSEL_PRSCH0, 
00165   usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, 
00166   usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, 
00167   usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3, 
00168 #if defined( USART_IRCTRL_IRPRSSEL_PRSCH7 )
00169   usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4, 
00170   usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5, 
00171   usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6, 
00172   usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7  
00173 #endif
00174 } USART_IrDAPrsSel_Typedef;
00175 
00176 #if defined( _USART_I2SCTRL_MASK )
00177 
00178 typedef enum
00179 {
00180   usartI2sFormatW32D32  = USART_I2SCTRL_FORMAT_W32D32,   
00181   usartI2sFormatW32D24M = USART_I2SCTRL_FORMAT_W32D24M,  
00182   usartI2sFormatW32D24  = USART_I2SCTRL_FORMAT_W32D24,   
00183   usartI2sFormatW32D16  = USART_I2SCTRL_FORMAT_W32D16,   
00184   usartI2sFormatW32D8   = USART_I2SCTRL_FORMAT_W32D8,    
00185   usartI2sFormatW16D16  = USART_I2SCTRL_FORMAT_W16D16,   
00186   usartI2sFormatW16D8   = USART_I2SCTRL_FORMAT_W16D8,    
00187   usartI2sFormatW8D8    = USART_I2SCTRL_FORMAT_W8D8      
00188 } USART_I2sFormat_TypeDef;
00189 
00191 typedef enum
00192 {
00193   usartI2sJustifyLeft  = USART_I2SCTRL_JUSTIFY_LEFT,  
00194   usartI2sJustifyRight = USART_I2SCTRL_JUSTIFY_RIGHT  
00195 } USART_I2sJustify_TypeDef;
00196 #endif
00197 
00198 #if defined( _USART_INPUT_MASK )
00199 
00200 typedef enum
00201 {
00202   usartPrsRxCh0  = USART_INPUT_RXPRSSEL_PRSCH0,    
00203   usartPrsRxCh1  = USART_INPUT_RXPRSSEL_PRSCH1,    
00204   usartPrsRxCh2  = USART_INPUT_RXPRSSEL_PRSCH2,    
00205   usartPrsRxCh3  = USART_INPUT_RXPRSSEL_PRSCH3,    
00207 #if defined( USART_INPUT_RXPRSSEL_PRSCH7 )
00208   usartPrsRxCh4  = USART_INPUT_RXPRSSEL_PRSCH4,    
00209   usartPrsRxCh5  = USART_INPUT_RXPRSSEL_PRSCH5,    
00210   usartPrsRxCh6  = USART_INPUT_RXPRSSEL_PRSCH6,    
00211   usartPrsRxCh7  = USART_INPUT_RXPRSSEL_PRSCH7,    
00212 #endif
00213 
00214 #if defined( USART_INPUT_RXPRSSEL_PRSCH11 )
00215   usartPrsRxCh8  = USART_INPUT_RXPRSSEL_PRSCH8,    
00216   usartPrsRxCh9  = USART_INPUT_RXPRSSEL_PRSCH9,    
00217   usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10,   
00218   usartPrsRxCh11 = USART_INPUT_RXPRSSEL_PRSCH11    
00219 #endif
00220 } USART_PrsRxCh_TypeDef;
00221 #endif
00222 
00224 typedef enum
00225 {
00226   usartPrsTriggerCh0 = USART_TRIGCTRL_TSEL_PRSCH0, 
00227   usartPrsTriggerCh1 = USART_TRIGCTRL_TSEL_PRSCH1, 
00228   usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, 
00229   usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, 
00231 #if defined( USART_TRIGCTRL_TSEL_PRSCH7 )
00232   usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, 
00233   usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, 
00234   usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, 
00235   usartPrsTriggerCh7 = USART_TRIGCTRL_TSEL_PRSCH7, 
00236 #endif
00237 } USART_PrsTriggerCh_TypeDef;
00238 
00239 /*******************************************************************************
00240  *******************************   STRUCTS   ***********************************
00241  ******************************************************************************/
00242 
00244 typedef struct
00245 {
00247   USART_Enable_TypeDef   enable;
00248 
00253   uint32_t               refFreq;
00254 
00256   uint32_t               baudrate;
00257 
00259   USART_OVS_TypeDef      oversampling;
00260 
00263   USART_Databits_TypeDef databits;
00264 
00266   USART_Parity_TypeDef   parity;
00267 
00269   USART_Stopbits_TypeDef stopbits;
00270 
00271 #if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )
00272 
00273   bool                   mvdis;
00274 
00276   bool                   prsRxEnable;
00277 
00279   USART_PrsRxCh_TypeDef  prsRxCh;
00280 #endif
00281 } USART_InitAsync_TypeDef;
00282 
00284 typedef struct
00285 {
00286 #if defined( USART_TRIGCTRL_AUTOTXTEN )
00287 
00288   bool autoTxTriggerEnable;
00289 #endif
00290 
00291   bool rxTriggerEnable;
00293   bool txTriggerEnable;
00295   USART_PrsTriggerCh_TypeDef prsTriggerChannel;
00296 } USART_PrsTriggerInit_TypeDef;
00297 
00299 #if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )
00300 #define USART_INITASYNC_DEFAULT                                                              \
00301   { usartEnable,      /* Enable RX/TX when init completed. */                                \
00302     0,                /* Use current configured reference clock for configuring baudrate. */ \
00303     115200,           /* 115200 bits/s. */                                                   \
00304     usartOVS16,       /* 16x oversampling. */                                                \
00305     usartDatabits8,   /* 8 databits. */                                                      \
00306     usartNoParity,    /* No parity. */                                                       \
00307     usartStopbits1,   /* 1 stopbit. */                                                       \
00308     false,            /* Do not disable majority vote. */                                    \
00309     false,            /* Not USART PRS input mode. */                                        \
00310     usartPrsRxCh0     /* PRS channel 0. */                                                   \
00311   }
00312 #else
00313 #define USART_INITASYNC_DEFAULT                                                              \
00314   { usartEnable,      /* Enable RX/TX when init completed. */                                \
00315     0,                /* Use current configured reference clock for configuring baudrate. */ \
00316     115200,           /* 115200 bits/s. */                                                   \
00317     usartOVS16,       /* 16x oversampling. */                                                \
00318     usartDatabits8,   /* 8 databits. */                                                      \
00319     usartNoParity,    /* No parity. */                                                       \
00320     usartStopbits1    /* 1 stopbit. */                                                       \
00321   }
00322 #endif
00323 
00325 typedef struct
00326 {
00328   USART_Enable_TypeDef    enable;
00329 
00334   uint32_t                refFreq;
00335 
00337   uint32_t                baudrate;
00338 
00340   USART_Databits_TypeDef  databits;
00341 
00343   bool                    master;
00344 
00346   bool                    msbf;
00347 
00349   USART_ClockMode_TypeDef clockMode;
00350 
00351 #if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )
00352 
00353   bool                    prsRxEnable;
00354 
00356   USART_PrsRxCh_TypeDef   prsRxCh;
00357 
00360   bool                    autoTx;
00361 #endif
00362 } USART_InitSync_TypeDef;
00363 
00365 #if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )
00366 #define USART_INITSYNC_DEFAULT                                                                \
00367   { usartEnable,       /* Enable RX/TX when init completed. */                                \
00368     0,                 /* Use current configured reference clock for configuring baudrate. */ \
00369     1000000,           /* 1 Mbits/s. */                                                       \
00370     usartDatabits8,    /* 8 databits. */                                                      \
00371     true,              /* Master mode. */                                                     \
00372     false,             /* Send least significant bit first. */                                \
00373     usartClockMode0,   /* Clock idle low, sample on rising edge. */                           \
00374     false,             /* Not USART PRS input mode. */                                        \
00375     usartPrsRxCh0,     /* PRS channel 0. */                                                   \
00376     false              /* No AUTOTX mode. */                                                  \
00377   }
00378 #else
00379 #define USART_INITSYNC_DEFAULT                                                                \
00380   { usartEnable,       /* Enable RX/TX when init completed. */                                \
00381     0,                 /* Use current configured reference clock for configuring baudrate. */ \
00382     1000000,           /* 1 Mbits/s. */                                                       \
00383     usartDatabits8,    /* 8 databits. */                                                      \
00384     true,              /* Master mode. */                                                     \
00385     false,             /* Send least significant bit first. */                                \
00386     usartClockMode0    /* Clock idle low, sample on rising edge. */                           \
00387   }
00388 #endif
00389 
00390 
00392 typedef struct
00393 {
00395   USART_InitAsync_TypeDef  async;
00396 
00398   bool                     irRxInv;
00399 
00401   bool                     irFilt;
00402 
00405   USART_IrDAPw_Typedef     irPw;
00406 
00409   bool                     irPrsEn;
00410 
00413   USART_IrDAPrsSel_Typedef irPrsSel;
00414 } USART_InitIrDA_TypeDef;
00415 
00416 
00418 #define USART_INITIRDA_DEFAULT                                                                \
00419   {                                                                                           \
00420     { usartEnable,     /* Enable RX/TX when init completed. */                                \
00421       0,               /* Use current configured reference clock for configuring baudrate. */ \
00422       115200,          /* 115200 bits/s. */                                                   \
00423       usartOVS16,      /* 16x oversampling. */                                                \
00424       usartDatabits8,  /* 8 databits. */                                                      \
00425       usartEvenParity, /* Even parity. */                                                     \
00426       usartStopbits1   /* 1 stopbit. */                                                       \
00427     },                                                                                        \
00428     false,             /* Rx invert disabled. */                                              \
00429     false,             /* Filtering disabled. */                                              \
00430     usartIrDAPwTHREE,  /* Pulse width is set to ONE. */                                       \
00431     false,             /* Routing to PRS is disabled. */                                      \
00432     usartIrDAPrsCh0    /* PRS channel 0. */                                                   \
00433   }
00434 
00435 
00436 #if defined( _USART_I2SCTRL_MASK )
00437 
00438 typedef struct
00439 {
00441   USART_InitSync_TypeDef   sync;
00442 
00444   USART_I2sFormat_TypeDef  format;
00445 
00449   bool                     delay;
00450 
00452   bool                     dmaSplit;
00453 
00455   USART_I2sJustify_TypeDef justify;
00456 
00458   bool                     mono;
00459 } USART_InitI2s_TypeDef;
00460 
00461 
00463 #define USART_INITI2S_DEFAULT                                                                    \
00464   {                                                                                              \
00465     { usartEnableTx,      /* Enable TX when init completed. */                                   \
00466       0,                  /* Use current configured reference clock for configuring baudrate. */ \
00467       1000000,            /* Baudrate 1M bits/s. */                                              \
00468       usartDatabits16,    /* 16 databits. */                                                     \
00469       true,               /* Operate as I2S master. */                                           \
00470       true,               /* Most significant bit first. */                                      \
00471       usartClockMode0,    /* Clock idle low, sample on rising edge. */                           \
00472       false,              /* Don't enable USARTRx via PRS. */                                    \
00473       usartPrsRxCh0,      /* PRS channel selection (dummy). */                                   \
00474       false               /* Disable AUTOTX mode. */                                             \
00475     },                                                                                           \
00476     usartI2sFormatW16D16, /* 16-bit word, 16-bit data */                                         \
00477     true,                 /* Delay on I2S data. */                                               \
00478     false,                /* No DMA split. */                                                    \
00479     usartI2sJustifyLeft,  /* Data is left-justified within the frame */                          \
00480     false                 /* Stereo mode. */                                                     \
00481   }
00482 #endif
00483 
00484 /*******************************************************************************
00485  *****************************   PROTOTYPES   **********************************
00486  ******************************************************************************/
00487 
00488 void USART_BaudrateAsyncSet(USART_TypeDef *usart,
00489                             uint32_t refFreq,
00490                             uint32_t baudrate,
00491                             USART_OVS_TypeDef ovs);
00492 uint32_t USART_BaudrateCalc(uint32_t refFreq,
00493                             uint32_t clkdiv,
00494                             bool syncmode,
00495                             USART_OVS_TypeDef ovs);
00496 uint32_t USART_BaudrateGet(USART_TypeDef *usart);
00497 void USART_BaudrateSyncSet(USART_TypeDef *usart,
00498                            uint32_t refFreq,
00499                            uint32_t baudrate);
00500 void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable);
00501 
00502 void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
00503 void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
00504 #if defined(USART0) || ( (USART_COUNT == 1) && defined( USART1 ) )
00505 void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);
00506 #endif
00507 
00508 #if defined( _USART_I2SCTRL_MASK )
00509 void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
00510 #endif
00511 void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
00512 
00513 
00514 /***************************************************************************/
00525 __STATIC_INLINE void USART_IntClear(USART_TypeDef *usart, uint32_t flags)
00526 {
00527   usart->IFC = flags;
00528 }
00529 
00530 
00531 /***************************************************************************/
00542 __STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
00543 {
00544   usart->IEN &= ~(flags);
00545 }
00546 
00547 
00548 /***************************************************************************/
00564 __STATIC_INLINE void USART_IntEnable(USART_TypeDef *usart, uint32_t flags)
00565 {
00566   usart->IEN |= flags;
00567 }
00568 
00569 
00570 /***************************************************************************/
00584 __STATIC_INLINE uint32_t USART_IntGet(USART_TypeDef *usart)
00585 {
00586   return usart->IF;
00587 }
00588 
00589 
00590 /***************************************************************************/
00609 __STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
00610 {
00611   uint32_t tmp;
00612 
00613   /* Store USARTx->IEN in temporary variable in order to define explicit order
00614    * of volatile accesses. */
00615   tmp = usart->IEN;
00616 
00617   /* Bitwise AND of pending and enabled interrupts */
00618   return usart->IF & tmp;
00619 }
00620 
00621 
00622 /***************************************************************************/
00633 __STATIC_INLINE void USART_IntSet(USART_TypeDef *usart, uint32_t flags)
00634 {
00635   usart->IFS = flags;
00636 }
00637 
00638 
00639 /***************************************************************************/
00650 static __INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
00651 {
00652   return usart->STATUS;
00653 }
00654 
00655 void USART_Reset(USART_TypeDef *usart);
00656 uint8_t USART_Rx(USART_TypeDef *usart);
00657 uint16_t USART_RxDouble(USART_TypeDef *usart);
00658 uint32_t USART_RxDoubleExt(USART_TypeDef *usart);
00659 uint16_t USART_RxExt(USART_TypeDef *usart);
00660 
00661 
00662 /***************************************************************************/
00690 static __INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
00691 {
00692   return (uint8_t) (usart->RXDATA);
00693 }
00694 
00695 
00696 /***************************************************************************/
00728 static __INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
00729 {
00730   return (uint16_t) (usart->RXDOUBLE);
00731 }
00732 
00733 
00734 /***************************************************************************/
00764 static __INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
00765 {
00766   return usart->RXDOUBLEX;
00767 }
00768 
00769 
00770 /***************************************************************************/
00799 static __INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
00800 {
00801   return (uint16_t) (usart->RXDATAX);
00802 }
00803 
00804 uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);
00805 void USART_Tx(USART_TypeDef *usart, uint8_t data);
00806 void USART_TxDouble(USART_TypeDef *usart, uint16_t data);
00807 void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data);
00808 void USART_TxExt(USART_TypeDef *usart, uint16_t data);
00809 
00810 
00814 #ifdef __cplusplus
00815 }
00816 #endif
00817 
00818 #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
00819 #endif /* __EM_USART_H */