em_cmu.h

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00001 /***************************************************************************/
00034 #ifndef __EM_CMU_H
00035 #define __EM_CMU_H
00036 
00037 #include "em_device.h"
00038 #if defined( CMU_PRESENT )
00039 
00040 #include <stdbool.h>
00041 #include "em_bitband.h"
00042 
00043 #ifdef __cplusplus
00044 extern "C" {
00045 #endif
00046 
00047 /***************************************************************************/
00052 /***************************************************************************/
00059 /* Select register ids, for internal use */
00060 #define CMU_NOSEL_REG              0
00061 #define CMU_HFCLKSEL_REG           1
00062 #define CMU_LFACLKSEL_REG          2
00063 #define CMU_LFBCLKSEL_REG          3
00064 #define CMU_DBGCLKSEL_REG          4
00065 #if defined( USB_PRESENT )
00066 #define CMU_USBCCLKSEL_REG         5
00067 #endif
00068 
00069 #define CMU_SEL_REG_POS            0
00070 #define CMU_SEL_REG_MASK           0xf
00071 
00072 /* Divisor register ids, for internal use */
00073 #define CMU_NODIV_REG              0
00074 #define CMU_HFPERCLKDIV_REG        1
00075 #define CMU_HFCORECLKDIV_REG       2
00076 #define CMU_LFAPRESC0_REG          3
00077 #define CMU_LFBPRESC0_REG          4
00078 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00079 #define CMU_HFCLKDIV_REG           5
00080 #endif
00081 #define CMU_DIV_REG_POS            4
00082 #define CMU_DIV_REG_MASK           0xf
00083 
00084 /* Enable register ids, for internal use */
00085 #define CMU_NO_EN_REG              0
00086 #define CMU_HFPERCLKDIV_EN_REG     1
00087 #define CMU_HFPERCLKEN0_EN_REG     2
00088 #define CMU_HFCORECLKEN0_EN_REG    3
00089 #define CMU_LFACLKEN0_EN_REG       4
00090 #define CMU_LFBCLKEN0_EN_REG       5
00091 #define CMU_PCNT_EN_REG            6
00092 
00093 #define CMU_EN_REG_POS             8
00094 #define CMU_EN_REG_MASK            0xf
00095 
00096 /* Enable register bit position, for internal use */
00097 #define CMU_EN_BIT_POS             12
00098 #define CMU_EN_BIT_MASK            0x1f
00099 
00100 /* Clock branch bitfield position, for internal use */
00101 #define CMU_HF_CLK_BRANCH          0
00102 #define CMU_HFPER_CLK_BRANCH       1
00103 #define CMU_HFCORE_CLK_BRANCH      2
00104 #define CMU_LFA_CLK_BRANCH         3
00105 #define CMU_RTC_CLK_BRANCH         4
00106 #define CMU_LETIMER_CLK_BRANCH     5
00107 #define CMU_LCDPRE_CLK_BRANCH      6
00108 #define CMU_LCD_CLK_BRANCH         7
00109 #define CMU_LESENSE_CLK_BRANCH     8
00110 #define CMU_LFB_CLK_BRANCH         9
00111 #define CMU_LEUART0_CLK_BRANCH     10
00112 #define CMU_LEUART1_CLK_BRANCH     11
00113 #define CMU_DBG_CLK_BRANCH         12
00114 #define CMU_AUX_CLK_BRANCH         13
00115 #define CMU_USBC_CLK_BRANCH        14
00116 
00117 #define CMU_CLK_BRANCH_POS         17
00118 #define CMU_CLK_BRANCH_MASK        0x1f
00119 
00122 /*******************************************************************************
00123  ********************************   ENUMS   ************************************
00124  ******************************************************************************/
00125 
00127 #define cmuClkDiv_1     1     
00128 #define cmuClkDiv_2     2     
00129 #define cmuClkDiv_4     4     
00130 #define cmuClkDiv_8     8     
00131 #define cmuClkDiv_16    16    
00132 #define cmuClkDiv_32    32    
00133 #define cmuClkDiv_64    64    
00134 #define cmuClkDiv_128   128   
00135 #define cmuClkDiv_256   256   
00136 #define cmuClkDiv_512   512   
00137 #define cmuClkDiv_1024  1024  
00138 #define cmuClkDiv_2048  2048  
00139 #define cmuClkDiv_4096  4096  
00140 #define cmuClkDiv_8192  8192  
00141 #define cmuClkDiv_16384 16384 
00142 #define cmuClkDiv_32768 32768 
00145 typedef uint32_t CMU_ClkDiv_TypeDef;
00146 
00148 typedef enum
00149 {
00151   cmuHFRCOBand_1MHz  = _CMU_HFRCOCTRL_BAND_1MHZ,
00153   cmuHFRCOBand_7MHz  = _CMU_HFRCOCTRL_BAND_7MHZ,
00155   cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
00157   cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
00159   cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
00160 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
00161 
00162   cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ
00163 #endif
00164 } CMU_HFRCOBand_TypeDef;
00165 
00166 
00167 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
00168 
00169 typedef enum
00170 {
00172   cmuAUXHFRCOBand_1MHz  = _CMU_AUXHFRCOCTRL_BAND_1MHZ,
00174   cmuAUXHFRCOBand_7MHz  = _CMU_AUXHFRCOCTRL_BAND_7MHZ,
00176   cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,
00178   cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,
00180   cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,
00181 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
00182 
00183   cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ
00184 #endif
00185 } CMU_AUXHFRCOBand_TypeDef;
00186 #endif
00187 
00189 typedef enum
00190 {
00191   /*******************/
00192   /* HF clock branch */
00193   /*******************/
00194 
00196 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00197   cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) |
00198                 (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
00199                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00200                 (0 << CMU_EN_BIT_POS) |
00201                 (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00202 #else
00203   cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00204                 (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
00205                 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00206                 (0 << CMU_EN_BIT_POS) |
00207                 (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00208 #endif
00209 
00211   cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00212                  (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) |
00213                  (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00214                  (0 << CMU_EN_BIT_POS) |
00215                  (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00216 
00218   cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00219                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00220                  (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00221                  (0 << CMU_EN_BIT_POS) |
00222                  (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00223 
00224   /**********************************/
00225   /* HF peripheral clock sub-branch */
00226   /**********************************/
00227 
00229   cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |
00230                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00231                    (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |
00232                    (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) |
00233                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00234 
00235 #if defined(_CMU_HFPERCLKEN0_USART0_MASK)
00237   cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00238                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00239                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00240                     (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) |
00241                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00242 #endif
00243 
00244 #if defined(_CMU_HFPERCLKEN0_USART1_MASK)
00246   cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00247                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00248                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00249                     (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) |
00250                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00251 #endif
00252 
00253 #if defined(_CMU_HFPERCLKEN0_USART2_MASK)
00255   cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00256                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00257                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00258                     (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) |
00259                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00260 #endif
00261 
00262 #if defined(_CMU_HFPERCLKEN0_UART0_MASK)
00264   cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00265                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00266                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00267                    (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) |
00268                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00269 #endif
00270 
00271 #if defined(_CMU_HFPERCLKEN0_UART1_MASK)
00273   cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00274                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00275                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00276                    (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) |
00277                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00278 #endif
00279 
00280 #if defined(_CMU_HFPERCLKEN0_TIMER0_MASK)
00282   cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00283                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00284                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00285                     (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) |
00286                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00287 #endif
00288 
00289 #if defined(_CMU_HFPERCLKEN0_TIMER1_MASK)
00291   cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00292                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00293                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00294                     (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) |
00295                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00296 #endif
00297 
00298 #if defined(_CMU_HFPERCLKEN0_TIMER2_MASK)
00300   cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00301                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00302                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00303                     (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) |
00304                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00305 #endif
00306 
00307 #if defined(_CMU_HFPERCLKEN0_TIMER3_MASK)
00309   cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00310                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00311                     (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00312                     (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) |
00313                     (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00314 #endif
00315 
00316 #if defined(_CMU_HFPERCLKEN0_ACMP0_MASK)
00318   cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00319                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00320                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00321                    (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) |
00322                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00323 #endif
00324 
00325 #if defined(_CMU_HFPERCLKEN0_ACMP1_MASK)
00327   cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00328                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00329                    (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00330                    (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) |
00331                    (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00332 #endif
00333 
00334 #if defined(_CMU_HFPERCLKEN0_PRS_MASK)
00336   cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00337                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00338                  (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00339                  (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) |
00340                  (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00341 #endif
00342 
00343 #if defined(_CMU_HFPERCLKEN0_DAC0_MASK)
00345   cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00346                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00347                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00348                   (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) |
00349                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00350 #endif
00351 
00352 #if defined(_CMU_HFPERCLKEN0_IDAC0_MASK)
00354   cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00355                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00356                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00357                   (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) |
00358                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00359 #endif
00360 
00361 #if defined(GPIO_PRESENT)
00363   cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00364                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00365                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00366                   (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) |
00367                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00368 #endif
00369 
00370 #if defined(VCMP_PRESENT)
00372   cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00373                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00374                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00375                   (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) |
00376                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00377 #endif
00378 
00379 #if defined(_CMU_HFPERCLKEN0_ADC0_MASK)
00381   cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00382                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00383                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00384                   (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) |
00385                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00386 #endif
00387 
00388 #if defined(_CMU_HFPERCLKEN0_I2C0_MASK)
00390   cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00391                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00392                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00393                   (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) |
00394                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00395 #endif
00396 
00397 #if defined(_CMU_HFPERCLKEN0_I2C1_MASK)
00399   cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00400                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00401                   (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00402                   (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) |
00403                   (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00404 #endif
00405 
00406   /**********************/
00407   /* HF core sub-branch */
00408   /**********************/
00409 
00411   cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |
00412                   (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00413                   (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00414                   (0 << CMU_EN_BIT_POS) |
00415                   (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00416 
00417 #if defined(AES_PRESENT)
00418 
00419   cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00420                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00421                  (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00422                  (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) |
00423                  (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00424 #endif
00425 
00426 #if defined(DMA_PRESENT)
00428   cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00429                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00430                  (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00431                  (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) |
00432                  (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00433 #endif
00435   cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00436                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00437                     (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00438                     (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) |
00439                     (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00440 
00441 #if defined(EBI_PRESENT)
00442 
00443   cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00444                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00445                  (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00446                  (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) |
00447                  (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00448 #endif
00449 
00450 #if defined(USB_PRESENT)
00452   cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00453                   (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
00454                   (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00455                   (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
00456                   (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00457 
00458 #endif
00459 
00460 #if defined(USB_PRESENT)
00462   cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00463                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00464                  (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00465                  (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |
00466                  (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00467 #endif
00468 
00469   /***************/
00470   /* LF A branch */
00471   /***************/
00472 
00474   cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00475                  (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |
00476                  (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00477                  (0 << CMU_EN_BIT_POS) |
00478                  (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00479 
00480 #if defined(RTC_PRESENT)
00481 
00482   cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00483                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00484                  (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00485                  (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) |
00486                  (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00487 #endif
00488 
00489 #if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
00491   cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00492                       (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00493                       (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00494                       (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) |
00495                       (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00496 #endif
00497 
00498 #if defined(_CMU_LFACLKEN0_LCD_MASK)
00500   cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00501                     (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00502                     (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00503                     (0 << CMU_EN_BIT_POS) |
00504                     (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00505 
00508   cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00509                  (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00510                  (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00511                  (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) |
00512                  (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00513 #endif
00514 
00515 #if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
00516 
00517   cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00518                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00519                    (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
00520                    (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) |
00521                    (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00522 #endif
00523 
00524 #if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
00526   cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00527                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00528                    (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
00529                    (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) |
00530                    (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00531 #endif
00532 
00533 #if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
00535   cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00536                    (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00537                    (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
00538                    (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) |
00539                    (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00540 #endif
00541 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
00543   cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00544                      (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00545                      (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00546                      (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) |
00547                      (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00548 #endif
00549 
00550   /***************/
00551   /* LF B branch */
00552   /***************/
00553 
00555   cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00556                  (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |
00557                  (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00558                  (0 << CMU_EN_BIT_POS) |
00559                  (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00560 
00561 #if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
00562 
00563   cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
00564                      (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00565                      (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
00566                      (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) |
00567                      (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00568 #endif
00569 
00570 #if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
00572   cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
00573                      (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00574                      (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
00575                      (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) |
00576                      (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00577 #endif
00578 } CMU_Clock_TypeDef;
00579 
00580 
00582 typedef enum
00583 {
00584   cmuOsc_LFXO,     
00585   cmuOsc_LFRCO,    
00586   cmuOsc_HFXO,     
00587   cmuOsc_HFRCO,    
00588   cmuOsc_AUXHFRCO, 
00589 #if !defined(_EFM32_GECKO_FAMILY)
00590   cmuOsc_ULFRCO    
00591 #endif
00592 } CMU_Osc_TypeDef;
00593 
00594 
00596 typedef enum
00597 {
00598   cmuSelect_Error,      
00599   cmuSelect_Disabled,   
00600   cmuSelect_LFXO,       
00601   cmuSelect_LFRCO,      
00602   cmuSelect_HFXO,       
00603   cmuSelect_HFRCO,      
00604   cmuSelect_CORELEDIV2, 
00605   cmuSelect_AUXHFRCO,   
00606   cmuSelect_HFCLK,      
00607 #if !defined(_EFM32_GECKO_FAMILY)
00608   cmuSelect_ULFRCO,     
00609 #endif
00610 } CMU_Select_TypeDef;
00611 
00612 
00613 /*******************************************************************************
00614  *****************************   PROTOTYPES   **********************************
00615  ******************************************************************************/
00616 
00617 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
00618 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
00619 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
00620 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
00621 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
00622 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
00623 
00624 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
00625 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
00626 
00627 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
00628 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
00629 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
00630 #endif
00631 
00632 void CMU_HFRCOStartupDelaySet(uint32_t delay);
00633 uint32_t CMU_HFRCOStartupDelayGet(void);
00634 
00635 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
00636 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
00637 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
00638 
00639 bool CMU_PCNTClockExternalGet(unsigned int inst);
00640 void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
00641 
00642 uint32_t CMU_LCDClkFDIVGet(void);
00643 void CMU_LCDClkFDIVSet(uint32_t div);
00644 
00645 void CMU_FreezeEnable(bool enable);
00646 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
00647 
00648 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
00649 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
00650                          CMU_Osc_TypeDef upSel);
00651 #endif
00652 
00653 /***************************************************************************/
00660 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
00661 {
00662   CMU->IFC = flags;
00663 }
00664 
00665 
00666 /***************************************************************************/
00673 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
00674 {
00675   CMU->IEN &= ~flags;
00676 }
00677 
00678 
00679 /***************************************************************************/
00691 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
00692 {
00693   CMU->IEN |= flags;
00694 }
00695 
00696 
00697 /***************************************************************************/
00704 __STATIC_INLINE uint32_t CMU_IntGet(void)
00705 {
00706   return CMU->IF;
00707 }
00708 
00709 
00710 /***************************************************************************/
00728 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
00729 {
00730   uint32_t tmp = 0U;
00731 
00732 
00733   /* Store LESENSE->IEN in temporary variable in order to define explicit order
00734    * of volatile accesses. */
00735   tmp = CMU->IEN;
00736 
00737   /* Bitwise AND of pending and enabled interrupts */
00738   return CMU->IF & tmp;
00739 }
00740 
00741 
00742 /**************************************************************************/
00749 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
00750 {
00751   CMU->IFS = flags;
00752 }
00753 
00754 
00755 /***************************************************************************/
00768 __STATIC_INLINE void CMU_Lock(void)
00769 {
00770   CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
00771 }
00772 
00773 
00774 /***************************************************************************/
00778 __STATIC_INLINE void CMU_Unlock(void)
00779 {
00780   CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
00781 }
00782 
00783 
00784 /***************************************************************************/
00797 __STATIC_INLINE uint32_t CMU_CalibrateCountGet(void)
00798 {
00799   /* Wait until calibration completes, UNLESS continuous calibration mode is  */
00800   /* active */
00801 #if defined( CMU_CALCTRL_CONT )
00802   if (!(CMU->CALCTRL & CMU_CALCTRL_CONT))
00803   {
00804     while (CMU->STATUS & CMU_STATUS_CALBSY)
00805       ;
00806   }
00807 #else
00808   while (CMU->STATUS & CMU_STATUS_CALBSY)
00809       ;
00810 #endif
00811   return CMU->CALCNT;
00812 }
00813 
00814 
00815 /***************************************************************************/
00822 __STATIC_INLINE void CMU_CalibrateStart(void)
00823 {
00824   CMU->CMD = CMU_CMD_CALSTART;
00825 }
00826 
00827 
00828 #if defined( CMU_CMD_CALSTOP )
00829 /***************************************************************************/
00833 __STATIC_INLINE void CMU_CalibrateStop(void)
00834 {
00835   CMU->CMD = CMU_CMD_CALSTOP;
00836 }
00837 #endif
00838 
00839 
00840 #if defined( CMU_CALCTRL_CONT )
00841 /***************************************************************************/
00848 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
00849 {
00850   BITBAND_Peripheral(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
00851 }
00852 #endif
00853 
00857 #ifdef __cplusplus
00858 }
00859 #endif
00860 
00861 #endif /* defined( CMU_PRESENT ) */
00862 #endif /* __EM_CMU_H */