00001
00032
00037 typedef struct
00038 {
00039 __I uint32_t STATUS;
00040 __O uint32_t CONFIG;
00041 __IO uint32_t CTRLBASE;
00042 __I uint32_t ALTCTRLBASE;
00043 __I uint32_t CHWAITSTATUS;
00044 __O uint32_t CHSWREQ;
00045 __IO uint32_t CHUSEBURSTS;
00046 __O uint32_t CHUSEBURSTC;
00047 __IO uint32_t CHREQMASKS;
00048 __O uint32_t CHREQMASKC;
00049 __IO uint32_t CHENS;
00050 __O uint32_t CHENC;
00051 __IO uint32_t CHALTS;
00052 __O uint32_t CHALTC;
00053 __IO uint32_t CHPRIS;
00054 __O uint32_t CHPRIC;
00055 uint32_t RESERVED0[3];
00056 __IO uint32_t ERRORC;
00058 uint32_t RESERVED1[880];
00059 __I uint32_t CHREQSTATUS;
00060 uint32_t RESERVED2[1];
00061 __I uint32_t CHSREQSTATUS;
00063 uint32_t RESERVED3[121];
00064 __I uint32_t IF;
00065 __IO uint32_t IFS;
00066 __IO uint32_t IFC;
00067 __IO uint32_t IEN;
00068 __IO uint32_t CTRL;
00069 __IO uint32_t RDS;
00071 uint32_t RESERVED4[2];
00072 __IO uint32_t LOOP0;
00073 __IO uint32_t LOOP1;
00074 uint32_t RESERVED5[14];
00075 __IO uint32_t RECT0;
00077 uint32_t RESERVED6[39];
00079 DMA_CH_TypeDef CH[12];
00080 } DMA_TypeDef;
00082
00087
00088 #define _DMA_STATUS_RESETVALUE 0x100B0000UL
00089 #define _DMA_STATUS_MASK 0x001F00F1UL
00090 #define DMA_STATUS_EN (0x1UL << 0)
00091 #define _DMA_STATUS_EN_SHIFT 0
00092 #define _DMA_STATUS_EN_MASK 0x1UL
00093 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL
00094 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
00095 #define _DMA_STATUS_STATE_SHIFT 4
00096 #define _DMA_STATUS_STATE_MASK 0xF0UL
00097 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL
00098 #define _DMA_STATUS_STATE_IDLE 0x00000000UL
00099 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
00100 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
00101 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
00102 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
00103 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
00104 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
00105 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
00106 #define _DMA_STATUS_STATE_STALLED 0x00000008UL
00107 #define _DMA_STATUS_STATE_DONE 0x00000009UL
00108 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
00109 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
00110 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
00111 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
00112 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
00113 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
00114 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
00115 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
00116 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
00117 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
00118 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
00119 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
00120 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
00121 #define _DMA_STATUS_CHNUM_SHIFT 16
00122 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL
00123 #define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL
00124 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
00126
00127 #define _DMA_CONFIG_RESETVALUE 0x00000000UL
00128 #define _DMA_CONFIG_MASK 0x00000021UL
00129 #define DMA_CONFIG_EN (0x1UL << 0)
00130 #define _DMA_CONFIG_EN_SHIFT 0
00131 #define _DMA_CONFIG_EN_MASK 0x1UL
00132 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL
00133 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
00134 #define DMA_CONFIG_CHPROT (0x1UL << 5)
00135 #define _DMA_CONFIG_CHPROT_SHIFT 5
00136 #define _DMA_CONFIG_CHPROT_MASK 0x20UL
00137 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
00138 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
00140
00141 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL
00142 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL
00143 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0
00144 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
00145 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
00146 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
00148
00149 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL
00150 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00151 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
00152 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00153 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL
00154 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
00156
00157 #define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL
00158 #define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL
00159 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
00160 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
00161 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
00162 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
00163 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
00164 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
00165 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
00166 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
00167 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
00168 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
00169 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
00170 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
00171 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
00172 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
00173 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
00174 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
00175 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
00176 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
00177 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
00178 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
00179 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)
00180 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4
00181 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL
00182 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL
00183 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
00184 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)
00185 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5
00186 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL
00187 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL
00188 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
00189 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6)
00190 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6
00191 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL
00192 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL
00193 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
00194 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7)
00195 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7
00196 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL
00197 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL
00198 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
00199 #define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8)
00200 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8
00201 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL
00202 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL
00203 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8)
00204 #define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9)
00205 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9
00206 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL
00207 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL
00208 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9)
00209 #define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10)
00210 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10
00211 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL
00212 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL
00213 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10)
00214 #define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11)
00215 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11
00216 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL
00217 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL
00218 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11)
00220
00221 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL
00222 #define _DMA_CHSWREQ_MASK 0x00000FFFUL
00223 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
00224 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0
00225 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
00226 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
00227 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
00228 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
00229 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1
00230 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
00231 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
00232 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
00233 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
00234 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2
00235 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
00236 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
00237 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
00238 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
00239 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3
00240 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
00241 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
00242 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
00243 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)
00244 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4
00245 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL
00246 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL
00247 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
00248 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)
00249 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5
00250 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL
00251 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL
00252 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
00253 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6)
00254 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6
00255 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL
00256 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL
00257 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
00258 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7)
00259 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7
00260 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL
00261 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL
00262 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
00263 #define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8)
00264 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8
00265 #define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL
00266 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL
00267 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8)
00268 #define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9)
00269 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9
00270 #define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL
00271 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL
00272 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9)
00273 #define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10)
00274 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10
00275 #define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL
00276 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL
00277 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10)
00278 #define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11)
00279 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11
00280 #define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL
00281 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL
00282 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11)
00284
00285 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
00286 #define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL
00287 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
00288 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
00289 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
00290 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
00291 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
00292 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
00293 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
00294 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
00295 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
00296 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
00297 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
00298 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
00299 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
00300 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
00301 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
00302 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
00303 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
00304 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
00305 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
00306 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
00307 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
00308 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
00309 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
00310 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
00311 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)
00312 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4
00313 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL
00314 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL
00315 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
00316 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)
00317 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5
00318 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL
00319 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL
00320 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
00321 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6)
00322 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6
00323 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL
00324 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL
00325 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
00326 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7)
00327 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7
00328 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL
00329 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL
00330 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
00331 #define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8)
00332 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8
00333 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL
00334 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL
00335 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8)
00336 #define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9)
00337 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9
00338 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL
00339 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL
00340 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9)
00341 #define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10)
00342 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10
00343 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL
00344 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL
00345 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10)
00346 #define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11)
00347 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11
00348 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL
00349 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL
00350 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11)
00352
00353 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
00354 #define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL
00355 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
00356 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
00357 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
00358 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
00359 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
00360 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
00361 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
00362 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
00363 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
00364 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
00365 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
00366 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
00367 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
00368 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
00369 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
00370 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
00371 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
00372 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
00373 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
00374 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
00375 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)
00376 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4
00377 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL
00378 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL
00379 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
00380 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)
00381 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5
00382 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL
00383 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL
00384 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
00385 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6)
00386 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6
00387 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL
00388 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL
00389 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
00390 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7)
00391 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7
00392 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL
00393 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL
00394 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
00395 #define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8)
00396 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8
00397 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL
00398 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL
00399 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8)
00400 #define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9)
00401 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9
00402 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL
00403 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL
00404 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9)
00405 #define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10)
00406 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10
00407 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL
00408 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL
00409 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10)
00410 #define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11)
00411 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11
00412 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL
00413 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL
00414 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11)
00416
00417 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
00418 #define _DMA_CHREQMASKS_MASK 0x00000FFFUL
00419 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
00420 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
00421 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
00422 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
00423 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
00424 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
00425 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
00426 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
00427 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
00428 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
00429 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
00430 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
00431 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
00432 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
00433 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
00434 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
00435 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
00436 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
00437 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
00438 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
00439 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)
00440 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
00441 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
00442 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
00443 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
00444 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)
00445 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
00446 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
00447 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
00448 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
00449 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6)
00450 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6
00451 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL
00452 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL
00453 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
00454 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7)
00455 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7
00456 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL
00457 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL
00458 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
00459 #define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8)
00460 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8
00461 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL
00462 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL
00463 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8)
00464 #define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9)
00465 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9
00466 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL
00467 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL
00468 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9)
00469 #define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10)
00470 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10
00471 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL
00472 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL
00473 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10)
00474 #define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11)
00475 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11
00476 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL
00477 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL
00478 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11)
00480
00481 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
00482 #define _DMA_CHREQMASKC_MASK 0x00000FFFUL
00483 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
00484 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
00485 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
00486 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
00487 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
00488 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
00489 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
00490 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
00491 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
00492 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
00493 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
00494 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
00495 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
00496 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
00497 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
00498 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
00499 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
00500 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
00501 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
00502 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
00503 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)
00504 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
00505 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
00506 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
00507 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
00508 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)
00509 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
00510 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
00511 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
00512 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
00513 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6)
00514 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6
00515 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL
00516 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL
00517 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
00518 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7)
00519 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7
00520 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL
00521 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL
00522 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
00523 #define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8)
00524 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8
00525 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL
00526 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL
00527 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8)
00528 #define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9)
00529 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9
00530 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL
00531 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL
00532 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9)
00533 #define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10)
00534 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10
00535 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL
00536 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL
00537 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10)
00538 #define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11)
00539 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11
00540 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL
00541 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL
00542 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11)
00544
00545 #define _DMA_CHENS_RESETVALUE 0x00000000UL
00546 #define _DMA_CHENS_MASK 0x00000FFFUL
00547 #define DMA_CHENS_CH0ENS (0x1UL << 0)
00548 #define _DMA_CHENS_CH0ENS_SHIFT 0
00549 #define _DMA_CHENS_CH0ENS_MASK 0x1UL
00550 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
00551 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
00552 #define DMA_CHENS_CH1ENS (0x1UL << 1)
00553 #define _DMA_CHENS_CH1ENS_SHIFT 1
00554 #define _DMA_CHENS_CH1ENS_MASK 0x2UL
00555 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
00556 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
00557 #define DMA_CHENS_CH2ENS (0x1UL << 2)
00558 #define _DMA_CHENS_CH2ENS_SHIFT 2
00559 #define _DMA_CHENS_CH2ENS_MASK 0x4UL
00560 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
00561 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
00562 #define DMA_CHENS_CH3ENS (0x1UL << 3)
00563 #define _DMA_CHENS_CH3ENS_SHIFT 3
00564 #define _DMA_CHENS_CH3ENS_MASK 0x8UL
00565 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
00566 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
00567 #define DMA_CHENS_CH4ENS (0x1UL << 4)
00568 #define _DMA_CHENS_CH4ENS_SHIFT 4
00569 #define _DMA_CHENS_CH4ENS_MASK 0x10UL
00570 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
00571 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)
00572 #define DMA_CHENS_CH5ENS (0x1UL << 5)
00573 #define _DMA_CHENS_CH5ENS_SHIFT 5
00574 #define _DMA_CHENS_CH5ENS_MASK 0x20UL
00575 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
00576 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)
00577 #define DMA_CHENS_CH6ENS (0x1UL << 6)
00578 #define _DMA_CHENS_CH6ENS_SHIFT 6
00579 #define _DMA_CHENS_CH6ENS_MASK 0x40UL
00580 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL
00581 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6)
00582 #define DMA_CHENS_CH7ENS (0x1UL << 7)
00583 #define _DMA_CHENS_CH7ENS_SHIFT 7
00584 #define _DMA_CHENS_CH7ENS_MASK 0x80UL
00585 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL
00586 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7)
00587 #define DMA_CHENS_CH8ENS (0x1UL << 8)
00588 #define _DMA_CHENS_CH8ENS_SHIFT 8
00589 #define _DMA_CHENS_CH8ENS_MASK 0x100UL
00590 #define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL
00591 #define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8)
00592 #define DMA_CHENS_CH9ENS (0x1UL << 9)
00593 #define _DMA_CHENS_CH9ENS_SHIFT 9
00594 #define _DMA_CHENS_CH9ENS_MASK 0x200UL
00595 #define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL
00596 #define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9)
00597 #define DMA_CHENS_CH10ENS (0x1UL << 10)
00598 #define _DMA_CHENS_CH10ENS_SHIFT 10
00599 #define _DMA_CHENS_CH10ENS_MASK 0x400UL
00600 #define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL
00601 #define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10)
00602 #define DMA_CHENS_CH11ENS (0x1UL << 11)
00603 #define _DMA_CHENS_CH11ENS_SHIFT 11
00604 #define _DMA_CHENS_CH11ENS_MASK 0x800UL
00605 #define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL
00606 #define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11)
00608
00609 #define _DMA_CHENC_RESETVALUE 0x00000000UL
00610 #define _DMA_CHENC_MASK 0x00000FFFUL
00611 #define DMA_CHENC_CH0ENC (0x1UL << 0)
00612 #define _DMA_CHENC_CH0ENC_SHIFT 0
00613 #define _DMA_CHENC_CH0ENC_MASK 0x1UL
00614 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
00615 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
00616 #define DMA_CHENC_CH1ENC (0x1UL << 1)
00617 #define _DMA_CHENC_CH1ENC_SHIFT 1
00618 #define _DMA_CHENC_CH1ENC_MASK 0x2UL
00619 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
00620 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
00621 #define DMA_CHENC_CH2ENC (0x1UL << 2)
00622 #define _DMA_CHENC_CH2ENC_SHIFT 2
00623 #define _DMA_CHENC_CH2ENC_MASK 0x4UL
00624 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
00625 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
00626 #define DMA_CHENC_CH3ENC (0x1UL << 3)
00627 #define _DMA_CHENC_CH3ENC_SHIFT 3
00628 #define _DMA_CHENC_CH3ENC_MASK 0x8UL
00629 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
00630 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
00631 #define DMA_CHENC_CH4ENC (0x1UL << 4)
00632 #define _DMA_CHENC_CH4ENC_SHIFT 4
00633 #define _DMA_CHENC_CH4ENC_MASK 0x10UL
00634 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
00635 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)
00636 #define DMA_CHENC_CH5ENC (0x1UL << 5)
00637 #define _DMA_CHENC_CH5ENC_SHIFT 5
00638 #define _DMA_CHENC_CH5ENC_MASK 0x20UL
00639 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
00640 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)
00641 #define DMA_CHENC_CH6ENC (0x1UL << 6)
00642 #define _DMA_CHENC_CH6ENC_SHIFT 6
00643 #define _DMA_CHENC_CH6ENC_MASK 0x40UL
00644 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL
00645 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6)
00646 #define DMA_CHENC_CH7ENC (0x1UL << 7)
00647 #define _DMA_CHENC_CH7ENC_SHIFT 7
00648 #define _DMA_CHENC_CH7ENC_MASK 0x80UL
00649 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL
00650 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7)
00651 #define DMA_CHENC_CH8ENC (0x1UL << 8)
00652 #define _DMA_CHENC_CH8ENC_SHIFT 8
00653 #define _DMA_CHENC_CH8ENC_MASK 0x100UL
00654 #define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL
00655 #define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8)
00656 #define DMA_CHENC_CH9ENC (0x1UL << 9)
00657 #define _DMA_CHENC_CH9ENC_SHIFT 9
00658 #define _DMA_CHENC_CH9ENC_MASK 0x200UL
00659 #define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL
00660 #define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9)
00661 #define DMA_CHENC_CH10ENC (0x1UL << 10)
00662 #define _DMA_CHENC_CH10ENC_SHIFT 10
00663 #define _DMA_CHENC_CH10ENC_MASK 0x400UL
00664 #define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL
00665 #define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10)
00666 #define DMA_CHENC_CH11ENC (0x1UL << 11)
00667 #define _DMA_CHENC_CH11ENC_SHIFT 11
00668 #define _DMA_CHENC_CH11ENC_MASK 0x800UL
00669 #define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL
00670 #define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11)
00672
00673 #define _DMA_CHALTS_RESETVALUE 0x00000000UL
00674 #define _DMA_CHALTS_MASK 0x00000FFFUL
00675 #define DMA_CHALTS_CH0ALTS (0x1UL << 0)
00676 #define _DMA_CHALTS_CH0ALTS_SHIFT 0
00677 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
00678 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
00679 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
00680 #define DMA_CHALTS_CH1ALTS (0x1UL << 1)
00681 #define _DMA_CHALTS_CH1ALTS_SHIFT 1
00682 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
00683 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
00684 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
00685 #define DMA_CHALTS_CH2ALTS (0x1UL << 2)
00686 #define _DMA_CHALTS_CH2ALTS_SHIFT 2
00687 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
00688 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
00689 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
00690 #define DMA_CHALTS_CH3ALTS (0x1UL << 3)
00691 #define _DMA_CHALTS_CH3ALTS_SHIFT 3
00692 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
00693 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
00694 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
00695 #define DMA_CHALTS_CH4ALTS (0x1UL << 4)
00696 #define _DMA_CHALTS_CH4ALTS_SHIFT 4
00697 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL
00698 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
00699 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
00700 #define DMA_CHALTS_CH5ALTS (0x1UL << 5)
00701 #define _DMA_CHALTS_CH5ALTS_SHIFT 5
00702 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL
00703 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
00704 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
00705 #define DMA_CHALTS_CH6ALTS (0x1UL << 6)
00706 #define _DMA_CHALTS_CH6ALTS_SHIFT 6
00707 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL
00708 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL
00709 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
00710 #define DMA_CHALTS_CH7ALTS (0x1UL << 7)
00711 #define _DMA_CHALTS_CH7ALTS_SHIFT 7
00712 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL
00713 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL
00714 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
00715 #define DMA_CHALTS_CH8ALTS (0x1UL << 8)
00716 #define _DMA_CHALTS_CH8ALTS_SHIFT 8
00717 #define _DMA_CHALTS_CH8ALTS_MASK 0x100UL
00718 #define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL
00719 #define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8)
00720 #define DMA_CHALTS_CH9ALTS (0x1UL << 9)
00721 #define _DMA_CHALTS_CH9ALTS_SHIFT 9
00722 #define _DMA_CHALTS_CH9ALTS_MASK 0x200UL
00723 #define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL
00724 #define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9)
00725 #define DMA_CHALTS_CH10ALTS (0x1UL << 10)
00726 #define _DMA_CHALTS_CH10ALTS_SHIFT 10
00727 #define _DMA_CHALTS_CH10ALTS_MASK 0x400UL
00728 #define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL
00729 #define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10)
00730 #define DMA_CHALTS_CH11ALTS (0x1UL << 11)
00731 #define _DMA_CHALTS_CH11ALTS_SHIFT 11
00732 #define _DMA_CHALTS_CH11ALTS_MASK 0x800UL
00733 #define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL
00734 #define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11)
00736
00737 #define _DMA_CHALTC_RESETVALUE 0x00000000UL
00738 #define _DMA_CHALTC_MASK 0x00000FFFUL
00739 #define DMA_CHALTC_CH0ALTC (0x1UL << 0)
00740 #define _DMA_CHALTC_CH0ALTC_SHIFT 0
00741 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
00742 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
00743 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
00744 #define DMA_CHALTC_CH1ALTC (0x1UL << 1)
00745 #define _DMA_CHALTC_CH1ALTC_SHIFT 1
00746 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
00747 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
00748 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
00749 #define DMA_CHALTC_CH2ALTC (0x1UL << 2)
00750 #define _DMA_CHALTC_CH2ALTC_SHIFT 2
00751 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
00752 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
00753 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
00754 #define DMA_CHALTC_CH3ALTC (0x1UL << 3)
00755 #define _DMA_CHALTC_CH3ALTC_SHIFT 3
00756 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
00757 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
00758 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
00759 #define DMA_CHALTC_CH4ALTC (0x1UL << 4)
00760 #define _DMA_CHALTC_CH4ALTC_SHIFT 4
00761 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL
00762 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
00763 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
00764 #define DMA_CHALTC_CH5ALTC (0x1UL << 5)
00765 #define _DMA_CHALTC_CH5ALTC_SHIFT 5
00766 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL
00767 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
00768 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
00769 #define DMA_CHALTC_CH6ALTC (0x1UL << 6)
00770 #define _DMA_CHALTC_CH6ALTC_SHIFT 6
00771 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL
00772 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL
00773 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
00774 #define DMA_CHALTC_CH7ALTC (0x1UL << 7)
00775 #define _DMA_CHALTC_CH7ALTC_SHIFT 7
00776 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL
00777 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL
00778 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
00779 #define DMA_CHALTC_CH8ALTC (0x1UL << 8)
00780 #define _DMA_CHALTC_CH8ALTC_SHIFT 8
00781 #define _DMA_CHALTC_CH8ALTC_MASK 0x100UL
00782 #define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL
00783 #define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8)
00784 #define DMA_CHALTC_CH9ALTC (0x1UL << 9)
00785 #define _DMA_CHALTC_CH9ALTC_SHIFT 9
00786 #define _DMA_CHALTC_CH9ALTC_MASK 0x200UL
00787 #define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL
00788 #define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9)
00789 #define DMA_CHALTC_CH10ALTC (0x1UL << 10)
00790 #define _DMA_CHALTC_CH10ALTC_SHIFT 10
00791 #define _DMA_CHALTC_CH10ALTC_MASK 0x400UL
00792 #define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL
00793 #define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10)
00794 #define DMA_CHALTC_CH11ALTC (0x1UL << 11)
00795 #define _DMA_CHALTC_CH11ALTC_SHIFT 11
00796 #define _DMA_CHALTC_CH11ALTC_MASK 0x800UL
00797 #define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL
00798 #define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11)
00800
00801 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL
00802 #define _DMA_CHPRIS_MASK 0x00000FFFUL
00803 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0)
00804 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0
00805 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
00806 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
00807 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
00808 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1)
00809 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1
00810 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
00811 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
00812 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
00813 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2)
00814 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2
00815 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
00816 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
00817 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
00818 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3)
00819 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3
00820 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
00821 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
00822 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
00823 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4)
00824 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4
00825 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL
00826 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
00827 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
00828 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5)
00829 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5
00830 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL
00831 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
00832 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
00833 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6)
00834 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6
00835 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL
00836 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL
00837 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
00838 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7)
00839 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7
00840 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL
00841 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL
00842 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
00843 #define DMA_CHPRIS_CH8PRIS (0x1UL << 8)
00844 #define _DMA_CHPRIS_CH8PRIS_SHIFT 8
00845 #define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL
00846 #define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL
00847 #define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8)
00848 #define DMA_CHPRIS_CH9PRIS (0x1UL << 9)
00849 #define _DMA_CHPRIS_CH9PRIS_SHIFT 9
00850 #define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL
00851 #define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL
00852 #define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9)
00853 #define DMA_CHPRIS_CH10PRIS (0x1UL << 10)
00854 #define _DMA_CHPRIS_CH10PRIS_SHIFT 10
00855 #define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL
00856 #define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL
00857 #define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10)
00858 #define DMA_CHPRIS_CH11PRIS (0x1UL << 11)
00859 #define _DMA_CHPRIS_CH11PRIS_SHIFT 11
00860 #define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL
00861 #define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL
00862 #define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11)
00864
00865 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL
00866 #define _DMA_CHPRIC_MASK 0x00000FFFUL
00867 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0)
00868 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0
00869 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
00870 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
00871 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
00872 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1)
00873 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1
00874 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
00875 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
00876 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
00877 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2)
00878 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2
00879 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
00880 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
00881 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
00882 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3)
00883 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3
00884 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
00885 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
00886 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
00887 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4)
00888 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4
00889 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL
00890 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
00891 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
00892 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5)
00893 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5
00894 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL
00895 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
00896 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
00897 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6)
00898 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6
00899 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL
00900 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL
00901 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
00902 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7)
00903 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7
00904 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL
00905 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL
00906 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
00907 #define DMA_CHPRIC_CH8PRIC (0x1UL << 8)
00908 #define _DMA_CHPRIC_CH8PRIC_SHIFT 8
00909 #define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL
00910 #define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL
00911 #define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8)
00912 #define DMA_CHPRIC_CH9PRIC (0x1UL << 9)
00913 #define _DMA_CHPRIC_CH9PRIC_SHIFT 9
00914 #define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL
00915 #define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL
00916 #define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9)
00917 #define DMA_CHPRIC_CH10PRIC (0x1UL << 10)
00918 #define _DMA_CHPRIC_CH10PRIC_SHIFT 10
00919 #define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL
00920 #define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL
00921 #define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10)
00922 #define DMA_CHPRIC_CH11PRIC (0x1UL << 11)
00923 #define _DMA_CHPRIC_CH11PRIC_SHIFT 11
00924 #define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL
00925 #define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL
00926 #define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11)
00928
00929 #define _DMA_ERRORC_RESETVALUE 0x00000000UL
00930 #define _DMA_ERRORC_MASK 0x00000001UL
00931 #define DMA_ERRORC_ERRORC (0x1UL << 0)
00932 #define _DMA_ERRORC_ERRORC_SHIFT 0
00933 #define _DMA_ERRORC_ERRORC_MASK 0x1UL
00934 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
00935 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
00937
00938 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
00939 #define _DMA_CHREQSTATUS_MASK 0x00000FFFUL
00940 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
00941 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
00942 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
00943 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
00944 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
00945 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
00946 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
00947 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
00948 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
00949 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
00950 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
00951 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
00952 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
00953 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
00954 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
00955 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
00956 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
00957 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
00958 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
00959 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
00960 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)
00961 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
00962 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
00963 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
00964 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
00965 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)
00966 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
00967 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
00968 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
00969 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
00970 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6)
00971 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6
00972 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL
00973 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL
00974 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
00975 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7)
00976 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7
00977 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL
00978 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL
00979 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
00980 #define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8)
00981 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8
00982 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL
00983 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL
00984 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8)
00985 #define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9)
00986 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9
00987 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL
00988 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL
00989 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9)
00990 #define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10)
00991 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10
00992 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL
00993 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL
00994 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10)
00995 #define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11)
00996 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11
00997 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL
00998 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL
00999 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11)
01001
01002 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
01003 #define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL
01004 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
01005 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
01006 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
01007 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
01008 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
01009 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
01010 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
01011 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
01012 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
01013 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
01014 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
01015 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
01016 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
01017 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
01018 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
01019 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
01020 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
01021 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
01022 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
01023 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
01024 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)
01025 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
01026 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
01027 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
01028 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
01029 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)
01030 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
01031 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
01032 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
01033 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
01034 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6)
01035 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6
01036 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL
01037 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL
01038 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
01039 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7)
01040 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7
01041 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL
01042 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL
01043 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
01044 #define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8)
01045 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8
01046 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL
01047 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL
01048 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8)
01049 #define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9)
01050 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9
01051 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL
01052 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL
01053 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9)
01054 #define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10)
01055 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10
01056 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL
01057 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL
01058 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10)
01059 #define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11)
01060 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11
01061 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL
01062 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL
01063 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11)
01065
01066 #define _DMA_IF_RESETVALUE 0x00000000UL
01067 #define _DMA_IF_MASK 0x80000FFFUL
01068 #define DMA_IF_CH0DONE (0x1UL << 0)
01069 #define _DMA_IF_CH0DONE_SHIFT 0
01070 #define _DMA_IF_CH0DONE_MASK 0x1UL
01071 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL
01072 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
01073 #define DMA_IF_CH1DONE (0x1UL << 1)
01074 #define _DMA_IF_CH1DONE_SHIFT 1
01075 #define _DMA_IF_CH1DONE_MASK 0x2UL
01076 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL
01077 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
01078 #define DMA_IF_CH2DONE (0x1UL << 2)
01079 #define _DMA_IF_CH2DONE_SHIFT 2
01080 #define _DMA_IF_CH2DONE_MASK 0x4UL
01081 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL
01082 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
01083 #define DMA_IF_CH3DONE (0x1UL << 3)
01084 #define _DMA_IF_CH3DONE_SHIFT 3
01085 #define _DMA_IF_CH3DONE_MASK 0x8UL
01086 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL
01087 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
01088 #define DMA_IF_CH4DONE (0x1UL << 4)
01089 #define _DMA_IF_CH4DONE_SHIFT 4
01090 #define _DMA_IF_CH4DONE_MASK 0x10UL
01091 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL
01092 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)
01093 #define DMA_IF_CH5DONE (0x1UL << 5)
01094 #define _DMA_IF_CH5DONE_SHIFT 5
01095 #define _DMA_IF_CH5DONE_MASK 0x20UL
01096 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL
01097 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)
01098 #define DMA_IF_CH6DONE (0x1UL << 6)
01099 #define _DMA_IF_CH6DONE_SHIFT 6
01100 #define _DMA_IF_CH6DONE_MASK 0x40UL
01101 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL
01102 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6)
01103 #define DMA_IF_CH7DONE (0x1UL << 7)
01104 #define _DMA_IF_CH7DONE_SHIFT 7
01105 #define _DMA_IF_CH7DONE_MASK 0x80UL
01106 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL
01107 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7)
01108 #define DMA_IF_CH8DONE (0x1UL << 8)
01109 #define _DMA_IF_CH8DONE_SHIFT 8
01110 #define _DMA_IF_CH8DONE_MASK 0x100UL
01111 #define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL
01112 #define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8)
01113 #define DMA_IF_CH9DONE (0x1UL << 9)
01114 #define _DMA_IF_CH9DONE_SHIFT 9
01115 #define _DMA_IF_CH9DONE_MASK 0x200UL
01116 #define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL
01117 #define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9)
01118 #define DMA_IF_CH10DONE (0x1UL << 10)
01119 #define _DMA_IF_CH10DONE_SHIFT 10
01120 #define _DMA_IF_CH10DONE_MASK 0x400UL
01121 #define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL
01122 #define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10)
01123 #define DMA_IF_CH11DONE (0x1UL << 11)
01124 #define _DMA_IF_CH11DONE_SHIFT 11
01125 #define _DMA_IF_CH11DONE_MASK 0x800UL
01126 #define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL
01127 #define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11)
01128 #define DMA_IF_ERR (0x1UL << 31)
01129 #define _DMA_IF_ERR_SHIFT 31
01130 #define _DMA_IF_ERR_MASK 0x80000000UL
01131 #define _DMA_IF_ERR_DEFAULT 0x00000000UL
01132 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
01134
01135 #define _DMA_IFS_RESETVALUE 0x00000000UL
01136 #define _DMA_IFS_MASK 0x80000FFFUL
01137 #define DMA_IFS_CH0DONE (0x1UL << 0)
01138 #define _DMA_IFS_CH0DONE_SHIFT 0
01139 #define _DMA_IFS_CH0DONE_MASK 0x1UL
01140 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
01141 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
01142 #define DMA_IFS_CH1DONE (0x1UL << 1)
01143 #define _DMA_IFS_CH1DONE_SHIFT 1
01144 #define _DMA_IFS_CH1DONE_MASK 0x2UL
01145 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
01146 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
01147 #define DMA_IFS_CH2DONE (0x1UL << 2)
01148 #define _DMA_IFS_CH2DONE_SHIFT 2
01149 #define _DMA_IFS_CH2DONE_MASK 0x4UL
01150 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
01151 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
01152 #define DMA_IFS_CH3DONE (0x1UL << 3)
01153 #define _DMA_IFS_CH3DONE_SHIFT 3
01154 #define _DMA_IFS_CH3DONE_MASK 0x8UL
01155 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
01156 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
01157 #define DMA_IFS_CH4DONE (0x1UL << 4)
01158 #define _DMA_IFS_CH4DONE_SHIFT 4
01159 #define _DMA_IFS_CH4DONE_MASK 0x10UL
01160 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL
01161 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)
01162 #define DMA_IFS_CH5DONE (0x1UL << 5)
01163 #define _DMA_IFS_CH5DONE_SHIFT 5
01164 #define _DMA_IFS_CH5DONE_MASK 0x20UL
01165 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL
01166 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)
01167 #define DMA_IFS_CH6DONE (0x1UL << 6)
01168 #define _DMA_IFS_CH6DONE_SHIFT 6
01169 #define _DMA_IFS_CH6DONE_MASK 0x40UL
01170 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL
01171 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6)
01172 #define DMA_IFS_CH7DONE (0x1UL << 7)
01173 #define _DMA_IFS_CH7DONE_SHIFT 7
01174 #define _DMA_IFS_CH7DONE_MASK 0x80UL
01175 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL
01176 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7)
01177 #define DMA_IFS_CH8DONE (0x1UL << 8)
01178 #define _DMA_IFS_CH8DONE_SHIFT 8
01179 #define _DMA_IFS_CH8DONE_MASK 0x100UL
01180 #define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL
01181 #define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8)
01182 #define DMA_IFS_CH9DONE (0x1UL << 9)
01183 #define _DMA_IFS_CH9DONE_SHIFT 9
01184 #define _DMA_IFS_CH9DONE_MASK 0x200UL
01185 #define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL
01186 #define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9)
01187 #define DMA_IFS_CH10DONE (0x1UL << 10)
01188 #define _DMA_IFS_CH10DONE_SHIFT 10
01189 #define _DMA_IFS_CH10DONE_MASK 0x400UL
01190 #define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL
01191 #define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10)
01192 #define DMA_IFS_CH11DONE (0x1UL << 11)
01193 #define _DMA_IFS_CH11DONE_SHIFT 11
01194 #define _DMA_IFS_CH11DONE_MASK 0x800UL
01195 #define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL
01196 #define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11)
01197 #define DMA_IFS_ERR (0x1UL << 31)
01198 #define _DMA_IFS_ERR_SHIFT 31
01199 #define _DMA_IFS_ERR_MASK 0x80000000UL
01200 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL
01201 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
01203
01204 #define _DMA_IFC_RESETVALUE 0x00000000UL
01205 #define _DMA_IFC_MASK 0x80000FFFUL
01206 #define DMA_IFC_CH0DONE (0x1UL << 0)
01207 #define _DMA_IFC_CH0DONE_SHIFT 0
01208 #define _DMA_IFC_CH0DONE_MASK 0x1UL
01209 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
01210 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
01211 #define DMA_IFC_CH1DONE (0x1UL << 1)
01212 #define _DMA_IFC_CH1DONE_SHIFT 1
01213 #define _DMA_IFC_CH1DONE_MASK 0x2UL
01214 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
01215 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
01216 #define DMA_IFC_CH2DONE (0x1UL << 2)
01217 #define _DMA_IFC_CH2DONE_SHIFT 2
01218 #define _DMA_IFC_CH2DONE_MASK 0x4UL
01219 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
01220 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
01221 #define DMA_IFC_CH3DONE (0x1UL << 3)
01222 #define _DMA_IFC_CH3DONE_SHIFT 3
01223 #define _DMA_IFC_CH3DONE_MASK 0x8UL
01224 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
01225 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
01226 #define DMA_IFC_CH4DONE (0x1UL << 4)
01227 #define _DMA_IFC_CH4DONE_SHIFT 4
01228 #define _DMA_IFC_CH4DONE_MASK 0x10UL
01229 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL
01230 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)
01231 #define DMA_IFC_CH5DONE (0x1UL << 5)
01232 #define _DMA_IFC_CH5DONE_SHIFT 5
01233 #define _DMA_IFC_CH5DONE_MASK 0x20UL
01234 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL
01235 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)
01236 #define DMA_IFC_CH6DONE (0x1UL << 6)
01237 #define _DMA_IFC_CH6DONE_SHIFT 6
01238 #define _DMA_IFC_CH6DONE_MASK 0x40UL
01239 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL
01240 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6)
01241 #define DMA_IFC_CH7DONE (0x1UL << 7)
01242 #define _DMA_IFC_CH7DONE_SHIFT 7
01243 #define _DMA_IFC_CH7DONE_MASK 0x80UL
01244 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL
01245 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7)
01246 #define DMA_IFC_CH8DONE (0x1UL << 8)
01247 #define _DMA_IFC_CH8DONE_SHIFT 8
01248 #define _DMA_IFC_CH8DONE_MASK 0x100UL
01249 #define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL
01250 #define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8)
01251 #define DMA_IFC_CH9DONE (0x1UL << 9)
01252 #define _DMA_IFC_CH9DONE_SHIFT 9
01253 #define _DMA_IFC_CH9DONE_MASK 0x200UL
01254 #define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL
01255 #define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9)
01256 #define DMA_IFC_CH10DONE (0x1UL << 10)
01257 #define _DMA_IFC_CH10DONE_SHIFT 10
01258 #define _DMA_IFC_CH10DONE_MASK 0x400UL
01259 #define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL
01260 #define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10)
01261 #define DMA_IFC_CH11DONE (0x1UL << 11)
01262 #define _DMA_IFC_CH11DONE_SHIFT 11
01263 #define _DMA_IFC_CH11DONE_MASK 0x800UL
01264 #define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL
01265 #define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11)
01266 #define DMA_IFC_ERR (0x1UL << 31)
01267 #define _DMA_IFC_ERR_SHIFT 31
01268 #define _DMA_IFC_ERR_MASK 0x80000000UL
01269 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL
01270 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
01272
01273 #define _DMA_IEN_RESETVALUE 0x00000000UL
01274 #define _DMA_IEN_MASK 0x80000FFFUL
01275 #define DMA_IEN_CH0DONE (0x1UL << 0)
01276 #define _DMA_IEN_CH0DONE_SHIFT 0
01277 #define _DMA_IEN_CH0DONE_MASK 0x1UL
01278 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
01279 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
01280 #define DMA_IEN_CH1DONE (0x1UL << 1)
01281 #define _DMA_IEN_CH1DONE_SHIFT 1
01282 #define _DMA_IEN_CH1DONE_MASK 0x2UL
01283 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
01284 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
01285 #define DMA_IEN_CH2DONE (0x1UL << 2)
01286 #define _DMA_IEN_CH2DONE_SHIFT 2
01287 #define _DMA_IEN_CH2DONE_MASK 0x4UL
01288 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
01289 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
01290 #define DMA_IEN_CH3DONE (0x1UL << 3)
01291 #define _DMA_IEN_CH3DONE_SHIFT 3
01292 #define _DMA_IEN_CH3DONE_MASK 0x8UL
01293 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
01294 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
01295 #define DMA_IEN_CH4DONE (0x1UL << 4)
01296 #define _DMA_IEN_CH4DONE_SHIFT 4
01297 #define _DMA_IEN_CH4DONE_MASK 0x10UL
01298 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL
01299 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)
01300 #define DMA_IEN_CH5DONE (0x1UL << 5)
01301 #define _DMA_IEN_CH5DONE_SHIFT 5
01302 #define _DMA_IEN_CH5DONE_MASK 0x20UL
01303 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL
01304 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)
01305 #define DMA_IEN_CH6DONE (0x1UL << 6)
01306 #define _DMA_IEN_CH6DONE_SHIFT 6
01307 #define _DMA_IEN_CH6DONE_MASK 0x40UL
01308 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL
01309 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6)
01310 #define DMA_IEN_CH7DONE (0x1UL << 7)
01311 #define _DMA_IEN_CH7DONE_SHIFT 7
01312 #define _DMA_IEN_CH7DONE_MASK 0x80UL
01313 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL
01314 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7)
01315 #define DMA_IEN_CH8DONE (0x1UL << 8)
01316 #define _DMA_IEN_CH8DONE_SHIFT 8
01317 #define _DMA_IEN_CH8DONE_MASK 0x100UL
01318 #define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL
01319 #define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8)
01320 #define DMA_IEN_CH9DONE (0x1UL << 9)
01321 #define _DMA_IEN_CH9DONE_SHIFT 9
01322 #define _DMA_IEN_CH9DONE_MASK 0x200UL
01323 #define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL
01324 #define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9)
01325 #define DMA_IEN_CH10DONE (0x1UL << 10)
01326 #define _DMA_IEN_CH10DONE_SHIFT 10
01327 #define _DMA_IEN_CH10DONE_MASK 0x400UL
01328 #define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL
01329 #define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10)
01330 #define DMA_IEN_CH11DONE (0x1UL << 11)
01331 #define _DMA_IEN_CH11DONE_SHIFT 11
01332 #define _DMA_IEN_CH11DONE_MASK 0x800UL
01333 #define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL
01334 #define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11)
01335 #define DMA_IEN_ERR (0x1UL << 31)
01336 #define _DMA_IEN_ERR_SHIFT 31
01337 #define _DMA_IEN_ERR_MASK 0x80000000UL
01338 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL
01339 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
01341
01342 #define _DMA_CTRL_RESETVALUE 0x00000000UL
01343 #define _DMA_CTRL_MASK 0x00000003UL
01344 #define DMA_CTRL_DESCRECT (0x1UL << 0)
01345 #define _DMA_CTRL_DESCRECT_SHIFT 0
01346 #define _DMA_CTRL_DESCRECT_MASK 0x1UL
01347 #define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL
01348 #define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0)
01349 #define DMA_CTRL_PRDU (0x1UL << 1)
01350 #define _DMA_CTRL_PRDU_SHIFT 1
01351 #define _DMA_CTRL_PRDU_MASK 0x2UL
01352 #define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL
01353 #define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1)
01355
01356 #define _DMA_RDS_RESETVALUE 0x00000000UL
01357 #define _DMA_RDS_MASK 0x00000FFFUL
01358 #define DMA_RDS_RDSCH0 (0x1UL << 0)
01359 #define _DMA_RDS_RDSCH0_SHIFT 0
01360 #define _DMA_RDS_RDSCH0_MASK 0x1UL
01361 #define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL
01362 #define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0)
01363 #define DMA_RDS_RDSCH1 (0x1UL << 1)
01364 #define _DMA_RDS_RDSCH1_SHIFT 1
01365 #define _DMA_RDS_RDSCH1_MASK 0x2UL
01366 #define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL
01367 #define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1)
01368 #define DMA_RDS_RDSCH2 (0x1UL << 2)
01369 #define _DMA_RDS_RDSCH2_SHIFT 2
01370 #define _DMA_RDS_RDSCH2_MASK 0x4UL
01371 #define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL
01372 #define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2)
01373 #define DMA_RDS_RDSCH3 (0x1UL << 3)
01374 #define _DMA_RDS_RDSCH3_SHIFT 3
01375 #define _DMA_RDS_RDSCH3_MASK 0x8UL
01376 #define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL
01377 #define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3)
01378 #define DMA_RDS_RDSCH4 (0x1UL << 4)
01379 #define _DMA_RDS_RDSCH4_SHIFT 4
01380 #define _DMA_RDS_RDSCH4_MASK 0x10UL
01381 #define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL
01382 #define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4)
01383 #define DMA_RDS_RDSCH5 (0x1UL << 5)
01384 #define _DMA_RDS_RDSCH5_SHIFT 5
01385 #define _DMA_RDS_RDSCH5_MASK 0x20UL
01386 #define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL
01387 #define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5)
01388 #define DMA_RDS_RDSCH6 (0x1UL << 6)
01389 #define _DMA_RDS_RDSCH6_SHIFT 6
01390 #define _DMA_RDS_RDSCH6_MASK 0x40UL
01391 #define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL
01392 #define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6)
01393 #define DMA_RDS_RDSCH7 (0x1UL << 7)
01394 #define _DMA_RDS_RDSCH7_SHIFT 7
01395 #define _DMA_RDS_RDSCH7_MASK 0x80UL
01396 #define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL
01397 #define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7)
01398 #define DMA_RDS_RDSCH8 (0x1UL << 8)
01399 #define _DMA_RDS_RDSCH8_SHIFT 8
01400 #define _DMA_RDS_RDSCH8_MASK 0x100UL
01401 #define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL
01402 #define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8)
01403 #define DMA_RDS_RDSCH9 (0x1UL << 9)
01404 #define _DMA_RDS_RDSCH9_SHIFT 9
01405 #define _DMA_RDS_RDSCH9_MASK 0x200UL
01406 #define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL
01407 #define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9)
01408 #define DMA_RDS_RDSCH10 (0x1UL << 10)
01409 #define _DMA_RDS_RDSCH10_SHIFT 10
01410 #define _DMA_RDS_RDSCH10_MASK 0x400UL
01411 #define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL
01412 #define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10)
01413 #define DMA_RDS_RDSCH11 (0x1UL << 11)
01414 #define _DMA_RDS_RDSCH11_SHIFT 11
01415 #define _DMA_RDS_RDSCH11_MASK 0x800UL
01416 #define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL
01417 #define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11)
01419
01420 #define _DMA_LOOP0_RESETVALUE 0x00000000UL
01421 #define _DMA_LOOP0_MASK 0x000103FFUL
01422 #define _DMA_LOOP0_WIDTH_SHIFT 0
01423 #define _DMA_LOOP0_WIDTH_MASK 0x3FFUL
01424 #define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL
01425 #define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0)
01426 #define DMA_LOOP0_EN (0x1UL << 16)
01427 #define _DMA_LOOP0_EN_SHIFT 16
01428 #define _DMA_LOOP0_EN_MASK 0x10000UL
01429 #define _DMA_LOOP0_EN_DEFAULT 0x00000000UL
01430 #define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16)
01432
01433 #define _DMA_LOOP1_RESETVALUE 0x00000000UL
01434 #define _DMA_LOOP1_MASK 0x000103FFUL
01435 #define _DMA_LOOP1_WIDTH_SHIFT 0
01436 #define _DMA_LOOP1_WIDTH_MASK 0x3FFUL
01437 #define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL
01438 #define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0)
01439 #define DMA_LOOP1_EN (0x1UL << 16)
01440 #define _DMA_LOOP1_EN_SHIFT 16
01441 #define _DMA_LOOP1_EN_MASK 0x10000UL
01442 #define _DMA_LOOP1_EN_DEFAULT 0x00000000UL
01443 #define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16)
01445
01446 #define _DMA_RECT0_RESETVALUE 0x00000000UL
01447 #define _DMA_RECT0_MASK 0xFFFFFFFFUL
01448 #define _DMA_RECT0_HEIGHT_SHIFT 0
01449 #define _DMA_RECT0_HEIGHT_MASK 0x3FFUL
01450 #define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL
01451 #define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0)
01452 #define _DMA_RECT0_SRCSTRIDE_SHIFT 10
01453 #define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL
01454 #define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL
01455 #define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10)
01456 #define _DMA_RECT0_DSTSTRIDE_SHIFT 21
01457 #define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL
01458 #define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL
01459 #define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21)
01461
01462 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
01463 #define _DMA_CH_CTRL_MASK 0x003F000FUL
01464 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0
01465 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
01466 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
01467 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
01468 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL
01469 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
01470 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL
01471 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
01472 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL
01473 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
01474 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL
01475 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
01476 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
01477 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL
01478 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL
01479 #define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000000UL
01480 #define _DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000000UL
01481 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
01482 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL
01483 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL
01484 #define _DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0x00000000UL
01485 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
01486 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
01487 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL
01488 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
01489 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL
01490 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
01491 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL
01492 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
01493 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL
01494 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
01495 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
01496 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL
01497 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL
01498 #define _DMA_CH_CTRL_SIGSEL_UART0TXBL 0x00000001UL
01499 #define _DMA_CH_CTRL_SIGSEL_UART1TXBL 0x00000001UL
01500 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL
01501 #define _DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 0x00000001UL
01502 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL
01503 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
01504 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL
01505 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
01506 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL
01507 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
01508 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
01509 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL
01510 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL
01511 #define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 0x00000002UL
01512 #define _DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 0x00000002UL
01513 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL
01514 #define _DMA_CH_CTRL_SIGSEL_EBIPXLFULL 0x00000002UL
01515 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL
01516 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL
01517 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
01518 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
01519 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL
01520 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL
01521 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL
01522 #define _DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 0x00000003UL
01523 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL
01524 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL
01525 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
01526 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)
01527 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
01528 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
01529 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
01530 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
01531 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)
01532 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
01533 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0)
01534 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
01535 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
01536 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)
01537 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0)
01538 #define DMA_CH_CTRL_SIGSEL_UART0RXDATAV (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)
01539 #define DMA_CH_CTRL_SIGSEL_UART1RXDATAV (_DMA_CH_CTRL_SIGSEL_UART1RXDATAV << 0)
01540 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
01541 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
01542 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0)
01543 #define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY << 0)
01544 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
01545 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)
01546 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)
01547 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
01548 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)
01549 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
01550 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)
01551 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
01552 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0)
01553 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
01554 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
01555 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
01556 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0)
01557 #define DMA_CH_CTRL_SIGSEL_UART0TXBL (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)
01558 #define DMA_CH_CTRL_SIGSEL_UART1TXBL (_DMA_CH_CTRL_SIGSEL_UART1TXBL << 0)
01559 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
01560 #define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY (_DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY << 0)
01561 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)
01562 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
01563 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)
01564 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
01565 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)
01566 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
01567 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
01568 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
01569 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0)
01570 #define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)
01571 #define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_UART1TXEMPTY << 0)
01572 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
01573 #define DMA_CH_CTRL_SIGSEL_EBIPXLFULL (_DMA_CH_CTRL_SIGSEL_EBIPXLFULL << 0)
01574 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)
01575 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0)
01576 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
01577 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
01578 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
01579 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0)
01580 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
01581 #define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY (_DMA_CH_CTRL_SIGSEL_EBIDDEMPTY << 0)
01582 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)
01583 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0)
01584 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
01585 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
01586 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
01587 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
01588 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL
01589 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL
01590 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
01591 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL
01592 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
01593 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL
01594 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
01595 #define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL
01596 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
01597 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
01598 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL
01599 #define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL
01600 #define _DMA_CH_CTRL_SOURCESEL_UART0 0x0000002CUL
01601 #define _DMA_CH_CTRL_SOURCESEL_UART1 0x0000002DUL
01602 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
01603 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL
01604 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL
01605 #define _DMA_CH_CTRL_SOURCESEL_EBI 0x00000033UL
01606 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
01607 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
01608 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)
01609 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)
01610 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
01611 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)
01612 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
01613 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)
01614 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
01615 #define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16)
01616 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
01617 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
01618 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)
01619 #define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16)
01620 #define DMA_CH_CTRL_SOURCESEL_UART0 (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)
01621 #define DMA_CH_CTRL_SOURCESEL_UART1 (_DMA_CH_CTRL_SOURCESEL_UART1 << 16)
01622 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
01623 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)
01624 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16)
01625 #define DMA_CH_CTRL_SOURCESEL_EBI (_DMA_CH_CTRL_SOURCESEL_EBI << 16)