release/EM_CMSIS_3.20.6/Device/SiliconLabs/EFM32GG/Include/efm32gg390f1024.h

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00001 /**************************************************************************/
00034 #ifndef __EFM32GG390F1024_H
00035 #define __EFM32GG390F1024_H
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M3 Processor Exceptions Numbers *******************************************/
00055   NonMaskableInt_IRQn   = -14,              
00056   HardFault_IRQn        = -13,              
00057   MemoryManagement_IRQn = -12,              
00058   BusFault_IRQn         = -11,              
00059   UsageFault_IRQn       = -10,              
00060   SVCall_IRQn           = -5,               
00061   DebugMonitor_IRQn     = -4,               
00062   PendSV_IRQn           = -2,               
00063   SysTick_IRQn          = -1,               
00065 /******  EFM32G Peripheral Interrupt Numbers **********************************************/
00066   DMA_IRQn              = 0,  
00067   GPIO_EVEN_IRQn        = 1,  
00068   TIMER0_IRQn           = 2,  
00069   USART0_RX_IRQn        = 3,  
00070   USART0_TX_IRQn        = 4,  
00071   USB_IRQn              = 5,  
00072   ACMP0_IRQn            = 6,  
00073   ADC0_IRQn             = 7,  
00074   DAC0_IRQn             = 8,  
00075   I2C0_IRQn             = 9,  
00076   I2C1_IRQn             = 10, 
00077   GPIO_ODD_IRQn         = 11, 
00078   TIMER1_IRQn           = 12, 
00079   TIMER2_IRQn           = 13, 
00080   TIMER3_IRQn           = 14, 
00081   USART1_RX_IRQn        = 15, 
00082   USART1_TX_IRQn        = 16, 
00083   LESENSE_IRQn          = 17, 
00084   USART2_RX_IRQn        = 18, 
00085   USART2_TX_IRQn        = 19, 
00086   UART0_RX_IRQn         = 20, 
00087   UART0_TX_IRQn         = 21, 
00088   UART1_RX_IRQn         = 22, 
00089   UART1_TX_IRQn         = 23, 
00090   LEUART0_IRQn          = 24, 
00091   LEUART1_IRQn          = 25, 
00092   LETIMER0_IRQn         = 26, 
00093   PCNT0_IRQn            = 27, 
00094   PCNT1_IRQn            = 28, 
00095   PCNT2_IRQn            = 29, 
00096   RTC_IRQn              = 30, 
00097   BURTC_IRQn            = 31, 
00098   CMU_IRQn              = 32, 
00099   VCMP_IRQn             = 33, 
00100   MSC_IRQn              = 35, 
00101   AES_IRQn              = 36, 
00102   EBI_IRQn              = 37, 
00103   EMU_IRQn              = 38, 
00104 } IRQn_Type;
00105 
00106 /**************************************************************************/
00111 #define __MPU_PRESENT             1 
00112 #define __NVIC_PRIO_BITS          3 
00113 #define __Vendor_SysTickConfig    0 
00117 /**************************************************************************/
00123 #define _EFM32_GIANT_FAMILY    1 
00124 #define _EFM_DEVICE              
00126 /* If part number is not defined as compiler option, define it */
00127 #if !defined(EFM32GG390F1024)
00128 #define EFM32GG390F1024    1 
00129 #endif
00130 
00132 #define PART_NUMBER          "EFM32GG390F1024" 
00135 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00136 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00137 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00138 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00139 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00140 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00141 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00142 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00143 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL) 
00144 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)    
00145 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL) 
00146 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)       
00147 #define EBI_CODE_MEM_BASE    ((uint32_t) 0x12000000UL) 
00148 #define EBI_CODE_MEM_SIZE    ((uint32_t) 0xE000000UL)  
00149 #define EBI_CODE_MEM_END     ((uint32_t) 0x1FFFFFFFUL) 
00150 #define EBI_CODE_MEM_BITS    ((uint32_t) 0x28UL)       
00151 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00152 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00153 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00154 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00155 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00156 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00157 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00158 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00159 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00160 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00161 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00162 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00163 #define EBI_MEM_BASE         ((uint32_t) 0x80000000UL) 
00164 #define EBI_MEM_SIZE         ((uint32_t) 0x40000000UL) 
00165 #define EBI_MEM_END          ((uint32_t) 0xBFFFFFFFUL) 
00166 #define EBI_MEM_BITS         ((uint32_t) 0x30UL)       
00169 #define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL) 
00170 #define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL) 
00173 #define FLASH_BASE           (0x00000000UL) 
00174 #define FLASH_SIZE           (0x00100000UL) 
00175 #define FLASH_PAGE_SIZE      4096           
00176 #define SRAM_BASE            (0x20000000UL) 
00177 #define SRAM_SIZE            (0x00020000UL) 
00178 #define __CM3_REV            0x201          
00179 #define PRS_CHAN_COUNT       12             
00180 #define DMA_CHAN_COUNT       12             
00183 #define AFCHAN_MAX           163
00184 #define AFCHANLOC_MAX        7
00185 
00186 #define AFACHAN_MAX          53
00187 
00188 /* Part number capabilities */
00189 
00190 #define LETIMER_PRESENT       
00191 #define LETIMER_COUNT       1 
00192 #define USART_PRESENT         
00193 #define USART_COUNT         3 
00194 #define UART_PRESENT          
00195 #define UART_COUNT          2 
00196 #define TIMER_PRESENT         
00197 #define TIMER_COUNT         4 
00198 #define ACMP_PRESENT          
00199 #define ACMP_COUNT          2 
00200 #define I2C_PRESENT           
00201 #define I2C_COUNT           2 
00202 #define LEUART_PRESENT        
00203 #define LEUART_COUNT        2 
00204 #define PCNT_PRESENT          
00205 #define PCNT_COUNT          3 
00206 #define ADC_PRESENT           
00207 #define ADC_COUNT           1 
00208 #define DAC_PRESENT           
00209 #define DAC_COUNT           1 
00210 #define DMA_PRESENT
00211 #define DMA_COUNT           1
00212 #define AES_PRESENT
00213 #define AES_COUNT           1
00214 #define USBC_PRESENT
00215 #define USBC_COUNT          1
00216 #define USB_PRESENT
00217 #define USB_COUNT           1
00218 #define LE_PRESENT
00219 #define LE_COUNT            1
00220 #define MSC_PRESENT
00221 #define MSC_COUNT           1
00222 #define EMU_PRESENT
00223 #define EMU_COUNT           1
00224 #define RMU_PRESENT
00225 #define RMU_COUNT           1
00226 #define CMU_PRESENT
00227 #define CMU_COUNT           1
00228 #define LESENSE_PRESENT
00229 #define LESENSE_COUNT       1
00230 #define RTC_PRESENT
00231 #define RTC_COUNT           1
00232 #define EBI_PRESENT
00233 #define EBI_COUNT           1
00234 #define GPIO_PRESENT
00235 #define GPIO_COUNT          1
00236 #define VCMP_PRESENT
00237 #define VCMP_COUNT          1
00238 #define PRS_PRESENT
00239 #define PRS_COUNT           1
00240 #define OPAMP_PRESENT
00241 #define OPAMP_COUNT         1
00242 #define BU_PRESENT
00243 #define BU_COUNT            1
00244 #define BURTC_PRESENT
00245 #define BURTC_COUNT         1
00246 #define HFXTAL_PRESENT
00247 #define HFXTAL_COUNT        1
00248 #define LFXTAL_PRESENT
00249 #define LFXTAL_COUNT        1
00250 #define WDOG_PRESENT
00251 #define WDOG_COUNT          1
00252 #define DBG_PRESENT
00253 #define DBG_COUNT           1
00254 #define ETM_PRESENT
00255 #define ETM_COUNT           1
00256 #define BOOTLOADER_PRESENT
00257 #define BOOTLOADER_COUNT    1
00258 #define ANALOG_PRESENT
00259 #define ANALOG_COUNT        1
00260 
00261 #include "core_cm3.h"       /* Cortex-M3 processor and core peripherals */
00262 #include "system_efm32gg.h" /* System Header */
00263 
00266 /**************************************************************************/
00272 #include "efm32gg_dma_ch.h"
00273 #include "efm32gg_dma.h"
00274 #include "efm32gg_aes.h"
00275 #include "efm32gg_usb_hc.h"
00276 #include "efm32gg_usb_diep.h"
00277 #include "efm32gg_usb_doep.h"
00278 #include "efm32gg_usb.h"
00279 #include "efm32gg_msc.h"
00280 #include "efm32gg_emu.h"
00281 #include "efm32gg_rmu.h"
00282 
00283 /**************************************************************************/
00288 typedef struct
00289 {
00290   __IO uint32_t CTRL;         
00291   __IO uint32_t HFCORECLKDIV; 
00292   __IO uint32_t HFPERCLKDIV;  
00293   __IO uint32_t HFRCOCTRL;    
00294   __IO uint32_t LFRCOCTRL;    
00295   __IO uint32_t AUXHFRCOCTRL; 
00296   __IO uint32_t CALCTRL;      
00297   __IO uint32_t CALCNT;       
00298   __IO uint32_t OSCENCMD;     
00299   __IO uint32_t CMD;          
00300   __IO uint32_t LFCLKSEL;     
00301   __I uint32_t  STATUS;       
00302   __I uint32_t  IF;           
00303   __IO uint32_t IFS;          
00304   __IO uint32_t IFC;          
00305   __IO uint32_t IEN;          
00306   __IO uint32_t HFCORECLKEN0; 
00307   __IO uint32_t HFPERCLKEN0;  
00308   uint32_t      RESERVED0[2]; 
00309   __I uint32_t  SYNCBUSY;     
00310   __IO uint32_t FREEZE;       
00311   __IO uint32_t LFACLKEN0;    
00312   uint32_t      RESERVED1[1]; 
00313   __IO uint32_t LFBCLKEN0;    
00314   uint32_t      RESERVED2[1]; 
00315   __IO uint32_t LFAPRESC0;    
00316   uint32_t      RESERVED3[1]; 
00317   __IO uint32_t LFBPRESC0;    
00318   uint32_t      RESERVED4[1]; 
00319   __IO uint32_t PCNTCTRL;     
00321   uint32_t      RESERVED5[1]; 
00322   __IO uint32_t ROUTE;        
00323   __IO uint32_t LOCK;         
00324 } CMU_TypeDef;                
00326 #include "efm32gg_lesense_st.h"
00327 #include "efm32gg_lesense_buf.h"
00328 #include "efm32gg_lesense_ch.h"
00329 #include "efm32gg_lesense.h"
00330 #include "efm32gg_rtc.h"
00331 #include "efm32gg_letimer.h"
00332 #include "efm32gg_ebi.h"
00333 #include "efm32gg_usart.h"
00334 #include "efm32gg_timer_cc.h"
00335 #include "efm32gg_timer.h"
00336 #include "efm32gg_acmp.h"
00337 #include "efm32gg_i2c.h"
00338 #include "efm32gg_gpio_p.h"
00339 #include "efm32gg_gpio.h"
00340 #include "efm32gg_vcmp.h"
00341 #include "efm32gg_prs_ch.h"
00342 #include "efm32gg_prs.h"
00343 #include "efm32gg_leuart.h"
00344 #include "efm32gg_pcnt.h"
00345 #include "efm32gg_adc.h"
00346 #include "efm32gg_dac.h"
00347 #include "efm32gg_burtc_ret.h"
00348 #include "efm32gg_burtc.h"
00349 #include "efm32gg_wdog.h"
00350 #include "efm32gg_etm.h"
00351 #include "efm32gg_dma_descriptor.h"
00352 #include "efm32gg_devinfo.h"
00353 #include "efm32gg_romtable.h"
00354 #include "efm32gg_calibrate.h"
00355 
00358 /**************************************************************************/
00363 #define DMA_BASE          (0x400C2000UL) 
00364 #define AES_BASE          (0x400E0000UL) 
00365 #define USB_BASE          (0x400C4000UL) 
00366 #define MSC_BASE          (0x400C0000UL) 
00367 #define EMU_BASE          (0x400C6000UL) 
00368 #define RMU_BASE          (0x400CA000UL) 
00369 #define CMU_BASE          (0x400C8000UL) 
00370 #define LESENSE_BASE      (0x4008C000UL) 
00371 #define RTC_BASE          (0x40080000UL) 
00372 #define LETIMER0_BASE     (0x40082000UL) 
00373 #define EBI_BASE          (0x40008000UL) 
00374 #define USART0_BASE       (0x4000C000UL) 
00375 #define USART1_BASE       (0x4000C400UL) 
00376 #define USART2_BASE       (0x4000C800UL) 
00377 #define UART0_BASE        (0x4000E000UL) 
00378 #define UART1_BASE        (0x4000E400UL) 
00379 #define TIMER0_BASE       (0x40010000UL) 
00380 #define TIMER1_BASE       (0x40010400UL) 
00381 #define TIMER2_BASE       (0x40010800UL) 
00382 #define TIMER3_BASE       (0x40010C00UL) 
00383 #define ACMP0_BASE        (0x40001000UL) 
00384 #define ACMP1_BASE        (0x40001400UL) 
00385 #define I2C0_BASE         (0x4000A000UL) 
00386 #define I2C1_BASE         (0x4000A400UL) 
00387 #define GPIO_BASE         (0x40006000UL) 
00388 #define VCMP_BASE         (0x40000000UL) 
00389 #define PRS_BASE          (0x400CC000UL) 
00390 #define LEUART0_BASE      (0x40084000UL) 
00391 #define LEUART1_BASE      (0x40084400UL) 
00392 #define PCNT0_BASE        (0x40086000UL) 
00393 #define PCNT1_BASE        (0x40086400UL) 
00394 #define PCNT2_BASE        (0x40086800UL) 
00395 #define ADC0_BASE         (0x40002000UL) 
00396 #define DAC0_BASE         (0x40004000UL) 
00397 #define BURTC_BASE        (0x40081000UL) 
00398 #define WDOG_BASE         (0x40088000UL) 
00399 #define ETM_BASE          (0xE0041000UL) 
00400 #define CALIBRATE_BASE    (0x0FE08000UL) 
00401 #define DEVINFO_BASE      (0x0FE081B0UL) 
00402 #define ROMTABLE_BASE     (0xE00FFFD0UL) 
00403 #define LOCKBITS_BASE     (0x0FE04000UL) 
00404 #define USERDATA_BASE     (0x0FE00000UL) 
00408 /**************************************************************************/
00413 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00414 #define AES          ((AES_TypeDef *) AES_BASE)             
00415 #define USB          ((USB_TypeDef *) USB_BASE)             
00416 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00417 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00418 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00419 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00420 #define LESENSE      ((LESENSE_TypeDef *) LESENSE_BASE)     
00421 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00422 #define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    
00423 #define EBI          ((EBI_TypeDef *) EBI_BASE)             
00424 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00425 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00426 #define USART2       ((USART_TypeDef *) USART2_BASE)        
00427 #define UART0        ((USART_TypeDef *) UART0_BASE)         
00428 #define UART1        ((USART_TypeDef *) UART1_BASE)         
00429 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00430 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00431 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        
00432 #define TIMER3       ((TIMER_TypeDef *) TIMER3_BASE)        
00433 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00434 #define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          
00435 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00436 #define I2C1         ((I2C_TypeDef *) I2C1_BASE)            
00437 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00438 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00439 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00440 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00441 #define LEUART1      ((LEUART_TypeDef *) LEUART1_BASE)      
00442 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00443 #define PCNT1        ((PCNT_TypeDef *) PCNT1_BASE)          
00444 #define PCNT2        ((PCNT_TypeDef *) PCNT2_BASE)          
00445 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
00446 #define DAC0         ((DAC_TypeDef *) DAC0_BASE)            
00447 #define BURTC        ((BURTC_TypeDef *) BURTC_BASE)         
00448 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00449 #define ETM          ((ETM_TypeDef *) ETM_BASE)             
00450 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00451 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00452 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00456 /**************************************************************************/
00461 #include "efm32gg_prs_signals.h"
00462 #include "efm32gg_dmareq.h"
00463 #include "efm32gg_dmactrl.h"
00464 #include "efm32gg_uart.h"
00465 
00466 /**************************************************************************/
00471 /* Bit fields for CMU CTRL */
00472 #define _CMU_CTRL_RESETVALUE                        0x000C062CUL                                
00473 #define _CMU_CTRL_MASK                              0x53FFFEEFUL                                
00474 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                           
00475 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                       
00476 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                                
00477 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                                
00478 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                                
00479 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                                
00480 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)           
00481 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)              
00482 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)         
00483 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)         
00484 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                           
00485 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                       
00486 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                                
00487 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                                
00488 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                                
00489 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                                
00490 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                                
00491 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)          
00492 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)          
00493 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)          
00494 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)          
00495 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)         
00496 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                           
00497 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                      
00498 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                                
00499 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ         0x00000001UL                                
00500 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ        0x00000003UL                                
00501 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)         
00502 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ          (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)  
00503 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ         (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) 
00504 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                                
00505 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                           
00506 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                      
00507 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                                
00508 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)    
00509 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                           
00510 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                     
00511 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                                
00512 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                                
00513 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                                
00514 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                                
00515 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                                
00516 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)        
00517 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)      
00518 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)       
00519 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)        
00520 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)      
00521 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                          
00522 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                    
00523 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                                
00524 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                                
00525 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                                
00526 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                                
00527 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)          
00528 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)             
00529 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)        
00530 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)        
00531 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                               
00532 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                          
00533 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                    
00534 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                                
00535 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                                
00536 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                                
00537 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)         
00538 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)         
00539 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)        
00540 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                          
00541 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                   
00542 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                                
00543 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)          
00544 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                               
00545 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                          
00546 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                   
00547 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                                
00548 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)        
00549 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                          
00550 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                   
00551 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                                
00552 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                                
00553 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                                
00554 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                                
00555 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                                
00556 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)       
00557 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)      
00558 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)     
00559 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)       
00560 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)     
00561 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                          
00562 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                                  
00563 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                                
00564 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                                
00565 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                                
00566 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                                
00567 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                                
00568 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                                
00569 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                                
00570 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                                
00571 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                                
00572 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)        
00573 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)          
00574 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)           
00575 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)         
00576 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)         
00577 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)         
00578 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)        
00579 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)         
00580 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)       
00581 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                          
00582 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x3800000UL                                 
00583 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                                
00584 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                                
00585 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                                
00586 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                                
00587 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                                
00588 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                                
00589 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                                
00590 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                                
00591 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                                
00592 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)        
00593 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)          
00594 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)           
00595 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)          
00596 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)          
00597 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)          
00598 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)         
00599 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)         
00600 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)      
00601 #define CMU_CTRL_DBGCLK                             (0x1UL << 28)                               
00602 #define _CMU_CTRL_DBGCLK_SHIFT                      28                                          
00603 #define _CMU_CTRL_DBGCLK_MASK                       0x10000000UL                                
00604 #define _CMU_CTRL_DBGCLK_DEFAULT                    0x00000000UL                                
00605 #define _CMU_CTRL_DBGCLK_AUXHFRCO                   0x00000000UL                                
00606 #define _CMU_CTRL_DBGCLK_HFCLK                      0x00000001UL                                
00607 #define CMU_CTRL_DBGCLK_DEFAULT                     (_CMU_CTRL_DBGCLK_DEFAULT << 28)            
00608 #define CMU_CTRL_DBGCLK_AUXHFRCO                    (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)           
00609 #define CMU_CTRL_DBGCLK_HFCLK                       (_CMU_CTRL_DBGCLK_HFCLK << 28)              
00610 #define CMU_CTRL_HFLE                               (0x1UL << 30)                               
00611 #define _CMU_CTRL_HFLE_SHIFT                        30                                          
00612 #define _CMU_CTRL_HFLE_MASK                         0x40000000UL                                
00613 #define _CMU_CTRL_HFLE_DEFAULT                      0x00000000UL                                
00614 #define CMU_CTRL_HFLE_DEFAULT                       (_CMU_CTRL_HFLE_DEFAULT << 30)              
00616 /* Bit fields for CMU HFCORECLKDIV */
00617 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
00618 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
00619 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
00620 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
00621 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
00622 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
00623 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
00624 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
00625 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
00626 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
00627 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
00628 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
00629 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
00630 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
00631 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
00632 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
00633 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
00634 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
00635 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
00636 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
00637 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
00638 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
00639 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
00640 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
00641 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
00642 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
00643 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
00644 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
00645 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
00646 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
00647 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
00648 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
00649 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
00650 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
00651 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
00653 /* Bit fields for CMU HFPERCLKDIV */
00654 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
00655 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
00656 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
00657 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
00658 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
00659 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
00660 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
00661 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
00662 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
00663 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
00664 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
00665 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
00666 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
00667 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
00668 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
00669 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
00670 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
00671 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
00672 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
00673 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
00674 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
00675 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
00676 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
00677 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
00678 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
00679 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
00680 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
00681 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
00682 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
00683 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
00684 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
00686 /* Bit fields for CMU HFRCOCTRL */
00687 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
00688 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
00689 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
00690 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
00691 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
00692 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
00693 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
00694 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
00695 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
00696 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
00697 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
00698 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
00699 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
00700 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
00701 #define _CMU_HFRCOCTRL_BAND_28MHZ                   0x00000005UL                           
00702 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
00703 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
00704 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
00705 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
00706 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
00707 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
00708 #define CMU_HFRCOCTRL_BAND_28MHZ                    (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       
00709 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
00710 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
00711 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
00712 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
00714 /* Bit fields for CMU LFRCOCTRL */
00715 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
00716 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
00717 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
00718 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
00719 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
00720 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
00722 /* Bit fields for CMU AUXHFRCOCTRL */
00723 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
00724 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
00725 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
00726 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
00727 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
00728 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
00729 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
00730 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
00731 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
00732 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
00733 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
00734 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
00735 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
00736 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ                0x00000006UL                            
00737 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
00738 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
00739 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
00740 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
00741 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
00742 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
00743 #define CMU_AUXHFRCOCTRL_BAND_28MHZ                 (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)     
00744 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
00746 /* Bit fields for CMU CALCTRL */
00747 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
00748 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
00749 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
00750 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
00751 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
00752 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
00753 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
00754 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
00755 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
00756 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
00757 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
00758 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
00759 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
00760 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
00761 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
00762 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
00763 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
00764 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
00765 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
00766 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
00767 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
00768 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
00769 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
00770 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
00771 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
00772 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
00773 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
00774 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
00775 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
00776 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
00777 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
00778 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
00779 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
00780 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
00781 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
00782 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
00783 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
00785 /* Bit fields for CMU CALCNT */
00786 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
00787 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
00788 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
00789 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
00790 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
00791 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
00793 /* Bit fields for CMU OSCENCMD */
00794 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
00795 #define _CMU_OSCENCMD_MASK                          0x000003FFUL                             
00796 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
00797 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
00798 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
00799 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
00800 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
00801 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
00802 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
00803 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
00804 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
00805 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
00806 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
00807 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
00808 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
00809 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
00810 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
00811 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
00812 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
00813 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
00814 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
00815 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
00816 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
00817 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
00818 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
00819 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
00820 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
00821 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
00822 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
00823 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
00824 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
00825 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
00826 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
00827 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
00828 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
00829 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
00830 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
00831 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
00832 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
00833 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
00834 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
00835 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
00836 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
00837 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
00838 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
00839 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
00840 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
00841 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
00842 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
00843 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
00844 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
00845 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
00847 /* Bit fields for CMU CMD */
00848 #define _CMU_CMD_RESETVALUE                         0x00000000UL                          
00849 #define _CMU_CMD_MASK                               0x0000007FUL                          
00850 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                     
00851 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                 
00852 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                          
00853 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                          
00854 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                          
00855 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                          
00856 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                          
00857 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0)      
00858 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)        
00859 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)         
00860 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)        
00861 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)         
00862 #define CMU_CMD_CALSTART                            (0x1UL << 3)                          
00863 #define _CMU_CMD_CALSTART_SHIFT                     3                                     
00864 #define _CMU_CMD_CALSTART_MASK                      0x8UL                                 
00865 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                          
00866 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3)      
00867 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                          
00868 #define _CMU_CMD_CALSTOP_SHIFT                      4                                     
00869 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                                
00870 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                          
00871 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)       
00872 #define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                     
00873 #define _CMU_CMD_USBCCLKSEL_MASK                    0x60UL                                
00874 #define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                          
00875 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV              0x00000001UL                          
00876 #define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                          
00877 #define _CMU_CMD_USBCCLKSEL_LFRCO                   0x00000003UL                          
00878 #define CMU_CMD_USBCCLKSEL_DEFAULT                  (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)    
00879 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV               (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5) 
00880 #define CMU_CMD_USBCCLKSEL_LFXO                     (_CMU_CMD_USBCCLKSEL_LFXO << 5)       
00881 #define CMU_CMD_USBCCLKSEL_LFRCO                    (_CMU_CMD_USBCCLKSEL_LFRCO << 5)      
00883 /* Bit fields for CMU LFCLKSEL */
00884 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             
00885 #define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             
00886 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
00887 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
00888 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
00889 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
00890 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
00891 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
00892 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
00893 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
00894 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
00895 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
00896 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
00897 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
00898 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
00899 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
00900 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
00901 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
00902 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
00903 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
00904 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
00905 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
00906 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
00907 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
00908 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
00909 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
00910 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
00911 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
00912 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
00913 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
00914 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
00915 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
00916 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
00917 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
00918 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
00919 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
00920 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
00921 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
00922 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
00923 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
00924 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
00925 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
00926 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
00927 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
00929 /* Bit fields for CMU STATUS */
00930 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                             
00931 #define _CMU_STATUS_MASK                            0x0003FFFFUL                             
00932 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                             
00933 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                        
00934 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                    
00935 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                             
00936 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)      
00937 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                             
00938 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                        
00939 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                    
00940 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                             
00941 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)      
00942 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                             
00943 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                        
00944 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                    
00945 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                             
00946 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)       
00947 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                             
00948 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                        
00949 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                    
00950 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                             
00951 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)       
00952 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                             
00953 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                        
00954 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                   
00955 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                             
00956 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)   
00957 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                             
00958 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                        
00959 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                   
00960 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                             
00961 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)   
00962 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                             
00963 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                        
00964 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                   
00965 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                             
00966 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)      
00967 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                             
00968 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                        
00969 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                   
00970 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                             
00971 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)      
00972 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                             
00973 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                        
00974 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                  
00975 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                             
00976 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)       
00977 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                             
00978 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                        
00979 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                  
00980 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                             
00981 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)       
00982 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                            
00983 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                       
00984 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                  
00985 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                             
00986 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)     
00987 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                            
00988 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                       
00989 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                  
00990 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                             
00991 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)      
00992 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                            
00993 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                       
00994 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                                 
00995 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                             
00996 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)     
00997 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                            
00998 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                       
00999 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                                 
01000 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                             
01001 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)      
01002 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                            
01003 #define _CMU_STATUS_CALBSY_SHIFT                    14                                       
01004 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                                 
01005 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                             
01006 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)       
01007 #define CMU_STATUS_USBCHFCLKSEL                     (0x1UL << 15)                            
01008 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT              15                                       
01009 #define _CMU_STATUS_USBCHFCLKSEL_MASK               0x8000UL                                 
01010 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT            0x00000000UL                             
01011 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT             (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15) 
01012 #define CMU_STATUS_USBCLFXOSEL                      (0x1UL << 16)                            
01013 #define _CMU_STATUS_USBCLFXOSEL_SHIFT               16                                       
01014 #define _CMU_STATUS_USBCLFXOSEL_MASK                0x10000UL                                
01015 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT             0x00000000UL                             
01016 #define CMU_STATUS_USBCLFXOSEL_DEFAULT              (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)  
01017 #define CMU_STATUS_USBCLFRCOSEL                     (0x1UL << 17)                            
01018 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT              17                                       
01019 #define _CMU_STATUS_USBCLFRCOSEL_MASK               0x20000UL                                
01020 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT            0x00000000UL                             
01021 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT             (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17) 
01023 /* Bit fields for CMU IF */
01024 #define _CMU_IF_RESETVALUE                          0x00000001UL                        
01025 #define _CMU_IF_MASK                                0x000000FFUL                        
01026 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                        
01027 #define _CMU_IF_HFRCORDY_SHIFT                      0                                   
01028 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                               
01029 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                        
01030 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)     
01031 #define CMU_IF_HFXORDY                              (0x1UL << 1)                        
01032 #define _CMU_IF_HFXORDY_SHIFT                       1                                   
01033 #define _CMU_IF_HFXORDY_MASK                        0x2UL                               
01034 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                        
01035 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)      
01036 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                        
01037 #define _CMU_IF_LFRCORDY_SHIFT                      2                                   
01038 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                               
01039 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                        
01040 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)     
01041 #define CMU_IF_LFXORDY                              (0x1UL << 3)                        
01042 #define _CMU_IF_LFXORDY_SHIFT                       3                                   
01043 #define _CMU_IF_LFXORDY_MASK                        0x8UL                               
01044 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                        
01045 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)      
01046 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                        
01047 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                   
01048 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                              
01049 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                        
01050 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)  
01051 #define CMU_IF_CALRDY                               (0x1UL << 5)                        
01052 #define _CMU_IF_CALRDY_SHIFT                        5                                   
01053 #define _CMU_IF_CALRDY_MASK                         0x20UL                              
01054 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                        
01055 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)       
01056 #define CMU_IF_CALOF                                (0x1UL << 6)                        
01057 #define _CMU_IF_CALOF_SHIFT                         6                                   
01058 #define _CMU_IF_CALOF_MASK                          0x40UL                              
01059 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                        
01060 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)        
01061 #define CMU_IF_USBCHFCLKSEL                         (0x1UL << 7)                        
01062 #define _CMU_IF_USBCHFCLKSEL_SHIFT                  7                                   
01063 #define _CMU_IF_USBCHFCLKSEL_MASK                   0x80UL                              
01064 #define _CMU_IF_USBCHFCLKSEL_DEFAULT                0x00000000UL                        
01065 #define CMU_IF_USBCHFCLKSEL_DEFAULT                 (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7) 
01067 /* Bit fields for CMU IFS */
01068 #define _CMU_IFS_RESETVALUE                         0x00000000UL                         
01069 #define _CMU_IFS_MASK                               0x000000FFUL                         
01070 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                         
01071 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                    
01072 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                                
01073 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                         
01074 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)     
01075 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                         
01076 #define _CMU_IFS_HFXORDY_SHIFT                      1                                    
01077 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                                
01078 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                         
01079 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)      
01080 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                         
01081 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                    
01082 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                                
01083 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                         
01084 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)     
01085 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                         
01086 #define _CMU_IFS_LFXORDY_SHIFT                      3                                    
01087 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                                
01088 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                         
01089 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)      
01090 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                         
01091 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                    
01092 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                               
01093 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                         
01094 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)  
01095 #define CMU_IFS_CALRDY                              (0x1UL << 5)                         
01096 #define _CMU_IFS_CALRDY_SHIFT                       5                                    
01097 #define _CMU_IFS_CALRDY_MASK                        0x20UL                               
01098 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                         
01099 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)       
01100 #define CMU_IFS_CALOF                               (0x1UL << 6)                         
01101 #define _CMU_IFS_CALOF_SHIFT                        6                                    
01102 #define _CMU_IFS_CALOF_MASK                         0x40UL                               
01103 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                         
01104 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)        
01105 #define CMU_IFS_USBCHFCLKSEL                        (0x1UL << 7)                         
01106 #define _CMU_IFS_USBCHFCLKSEL_SHIFT                 7                                    
01107 #define _CMU_IFS_USBCHFCLKSEL_MASK                  0x80UL                               
01108 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT               0x00000000UL                         
01109 #define CMU_IFS_USBCHFCLKSEL_DEFAULT                (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7) 
01111 /* Bit fields for CMU IFC */
01112 #define _CMU_IFC_RESETVALUE                         0x00000000UL                         
01113 #define _CMU_IFC_MASK                               0x000000FFUL                         
01114 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                         
01115 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                    
01116 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                                
01117 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                         
01118 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)     
01119 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                         
01120 #define _CMU_IFC_HFXORDY_SHIFT                      1                                    
01121 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                                
01122 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                         
01123 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)      
01124 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                         
01125 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                    
01126 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                                
01127 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                         
01128 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)     
01129 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                         
01130 #define _CMU_IFC_LFXORDY_SHIFT                      3                                    
01131 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                                
01132 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                         
01133 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)      
01134 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                         
01135 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                    
01136 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                               
01137 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                         
01138 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)  
01139 #define CMU_IFC_CALRDY                              (0x1UL << 5)                         
01140 #define _CMU_IFC_CALRDY_SHIFT                       5                                    
01141 #define _CMU_IFC_CALRDY_MASK                        0x20UL                               
01142 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                         
01143 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)       
01144 #define CMU_IFC_CALOF                               (0x1UL << 6)                         
01145 #define _CMU_IFC_CALOF_SHIFT                        6                                    
01146 #define _CMU_IFC_CALOF_MASK                         0x40UL                               
01147 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                         
01148 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)        
01149 #define CMU_IFC_USBCHFCLKSEL                        (0x1UL << 7)                         
01150 #define _CMU_IFC_USBCHFCLKSEL_SHIFT                 7                                    
01151 #define _CMU_IFC_USBCHFCLKSEL_MASK                  0x80UL                               
01152 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT               0x00000000UL                         
01153 #define CMU_IFC_USBCHFCLKSEL_DEFAULT                (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7) 
01155 /* Bit fields for CMU IEN */
01156 #define _CMU_IEN_RESETVALUE                         0x00000000UL                         
01157 #define _CMU_IEN_MASK                               0x000000FFUL                         
01158 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                         
01159 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                    
01160 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                                
01161 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                         
01162 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)     
01163 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                         
01164 #define _CMU_IEN_HFXORDY_SHIFT                      1                                    
01165 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                                
01166 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                         
01167 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)      
01168 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                         
01169 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                    
01170 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                                
01171 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                         
01172 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)     
01173 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                         
01174 #define _CMU_IEN_LFXORDY_SHIFT                      3                                    
01175 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                                
01176 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                         
01177 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)      
01178 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                         
01179 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                    
01180 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                               
01181 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                         
01182 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)  
01183 #define CMU_IEN_CALRDY                              (0x1UL << 5)                         
01184 #define _CMU_IEN_CALRDY_SHIFT                       5                                    
01185 #define _CMU_IEN_CALRDY_MASK                        0x20UL                               
01186 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                         
01187 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)       
01188 #define CMU_IEN_CALOF                               (0x1UL << 6)                         
01189 #define _CMU_IEN_CALOF_SHIFT                        6                                    
01190 #define _CMU_IEN_CALOF_MASK                         0x40UL                               
01191 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                         
01192 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)        
01193 #define CMU_IEN_USBCHFCLKSEL                        (0x1UL << 7)                         
01194 #define _CMU_IEN_USBCHFCLKSEL_SHIFT                 7                                    
01195 #define _CMU_IEN_USBCHFCLKSEL_MASK                  0x80UL                               
01196 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT               0x00000000UL                         
01197 #define CMU_IEN_USBCHFCLKSEL_DEFAULT                (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7) 
01199 /* Bit fields for CMU HFCORECLKEN0 */
01200 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                          
01201 #define _CMU_HFCORECLKEN0_MASK                      0x0000003FUL                          
01202 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 0)                          
01203 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 0                                     
01204 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x1UL                                 
01205 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                          
01206 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)  
01207 #define CMU_HFCORECLKEN0_AES                        (0x1UL << 1)                          
01208 #define _CMU_HFCORECLKEN0_AES_SHIFT                 1                                     
01209 #define _CMU_HFCORECLKEN0_AES_MASK                  0x2UL                                 
01210 #define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                          
01211 #define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)  
01212 #define CMU_HFCORECLKEN0_USBC                       (0x1UL << 2)                          
01213 #define _CMU_HFCORECLKEN0_USBC_SHIFT                2                                     
01214 #define _CMU_HFCORECLKEN0_USBC_MASK                 0x4UL                                 
01215 #define _CMU_HFCORECLKEN0_USBC_DEFAULT              0x00000000UL                          
01216 #define CMU_HFCORECLKEN0_USBC_DEFAULT               (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2) 
01217 #define CMU_HFCORECLKEN0_USB                        (0x1UL << 3)                          
01218 #define _CMU_HFCORECLKEN0_USB_SHIFT                 3                                     
01219 #define _CMU_HFCORECLKEN0_USB_MASK                  0x8UL                                 
01220 #define _CMU_HFCORECLKEN0_USB_DEFAULT               0x00000000UL                          
01221 #define CMU_HFCORECLKEN0_USB_DEFAULT                (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)  
01222 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 4)                          
01223 #define _CMU_HFCORECLKEN0_LE_SHIFT                  4                                     
01224 #define _CMU_HFCORECLKEN0_LE_MASK                   0x10UL                                
01225 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                          
01226 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)   
01227 #define CMU_HFCORECLKEN0_EBI                        (0x1UL << 5)                          
01228 #define _CMU_HFCORECLKEN0_EBI_SHIFT                 5                                     
01229 #define _CMU_HFCORECLKEN0_EBI_MASK                  0x20UL                                
01230 #define _CMU_HFCORECLKEN0_EBI_DEFAULT               0x00000000UL                          
01231 #define CMU_HFCORECLKEN0_EBI_DEFAULT                (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5)  
01233 /* Bit fields for CMU HFPERCLKEN0 */
01234 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
01235 #define _CMU_HFPERCLKEN0_MASK                       0x0003FFFFUL                           
01236 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 0)                           
01237 #define _CMU_HFPERCLKEN0_USART0_SHIFT               0                                      
01238 #define _CMU_HFPERCLKEN0_USART0_MASK                0x1UL                                  
01239 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
01240 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) 
01241 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 1)                           
01242 #define _CMU_HFPERCLKEN0_USART1_SHIFT               1                                      
01243 #define _CMU_HFPERCLKEN0_USART1_MASK                0x2UL                                  
01244 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
01245 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) 
01246 #define CMU_HFPERCLKEN0_USART2                      (0x1UL << 2)                           
01247 #define _CMU_HFPERCLKEN0_USART2_SHIFT               2                                      
01248 #define _CMU_HFPERCLKEN0_USART2_MASK                0x4UL                                  
01249 #define _CMU_HFPERCLKEN0_USART2_DEFAULT             0x00000000UL                           
01250 #define CMU_HFPERCLKEN0_USART2_DEFAULT              (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) 
01251 #define CMU_HFPERCLKEN0_UART0                       (0x1UL << 3)                           
01252 #define _CMU_HFPERCLKEN0_UART0_SHIFT                3                                      
01253 #define _CMU_HFPERCLKEN0_UART0_MASK                 0x8UL                                  
01254 #define _CMU_HFPERCLKEN0_UART0_DEFAULT              0x00000000UL                           
01255 #define CMU_HFPERCLKEN0_UART0_DEFAULT               (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)  
01256 #define CMU_HFPERCLKEN0_UART1                       (0x1UL << 4)                           
01257 #define _CMU_HFPERCLKEN0_UART1_SHIFT                4                                      
01258 #define _CMU_HFPERCLKEN0_UART1_MASK                 0x10UL                                 
01259 #define _CMU_HFPERCLKEN0_UART1_DEFAULT              0x00000000UL                           
01260 #define CMU_HFPERCLKEN0_UART1_DEFAULT               (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4)  
01261 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 5)                           
01262 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               5                                      
01263 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x20UL                                 
01264 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
01265 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) 
01266 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 6)                           
01267 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               6                                      
01268 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x40UL                                 
01269 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
01270 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) 
01271 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 7)                           
01272 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               7                                      
01273 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x80UL                                 
01274 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
01275 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) 
01276 #define CMU_HFPERCLKEN0_TIMER3                      (0x1UL << 8)                           
01277 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT               8                                      
01278 #define _CMU_HFPERCLKEN0_TIMER3_MASK                0x100UL                                
01279 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT             0x00000000UL                           
01280 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT              (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) 
01281 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 9)                           
01282 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                9                                      
01283 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x200UL                                
01284 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
01285 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)  
01286 #define CMU_HFPERCLKEN0_ACMP1                       (0x1UL << 10)                          
01287 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT                10                                     
01288 #define _CMU_HFPERCLKEN0_ACMP1_MASK                 0x400UL                                
01289 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT              0x00000000UL                           
01290 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT               (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) 
01291 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
01292 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
01293 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
01294 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
01295 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
01296 #define CMU_HFPERCLKEN0_I2C1                        (0x1UL << 12)                          
01297 #define _CMU_HFPERCLKEN0_I2C1_SHIFT                 12                                     
01298 #define _CMU_HFPERCLKEN0_I2C1_MASK                  0x1000UL                               
01299 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT               0x00000000UL                           
01300 #define CMU_HFPERCLKEN0_I2C1_DEFAULT                (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)  
01301 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 13)                          
01302 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 13                                     
01303 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x2000UL                               
01304 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
01305 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)  
01306 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 14)                          
01307 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 14                                     
01308 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x4000UL                               
01309 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
01310 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)  
01311 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 15)                          
01312 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  15                                     
01313 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x8000UL                               
01314 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
01315 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)   
01316 #define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 16)                          
01317 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                 16                                     
01318 #define _CMU_HFPERCLKEN0_ADC0_MASK                  0x10000UL                              
01319 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           
01320 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)  
01321 #define CMU_HFPERCLKEN0_DAC0                        (0x1UL << 17)                          
01322 #define _CMU_HFPERCLKEN0_DAC0_SHIFT                 17                                     
01323 #define _CMU_HFPERCLKEN0_DAC0_MASK                  0x20000UL                              
01324 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT               0x00000000UL                           
01325 #define CMU_HFPERCLKEN0_DAC0_DEFAULT                (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)  
01327 /* Bit fields for CMU SYNCBUSY */
01328 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
01329 #define _CMU_SYNCBUSY_MASK                          0x00000055UL                           
01330 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
01331 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
01332 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
01333 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
01334 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
01335 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
01336 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
01337 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
01338 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
01339 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
01340 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
01341 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
01342 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
01343 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
01344 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
01345 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
01346 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
01347 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
01348 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
01349 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
01351 /* Bit fields for CMU FREEZE */
01352 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
01353 #define _CMU_FREEZE_MASK                            0x00000001UL                         
01354 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
01355 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
01356 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
01357 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
01358 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
01359 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
01360 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
01361 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
01362 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
01364 /* Bit fields for CMU LFACLKEN0 */
01365 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                           
01366 #define _CMU_LFACLKEN0_MASK                         0x00000007UL                           
01367 #define CMU_LFACLKEN0_LESENSE                       (0x1UL << 0)                           
01368 #define _CMU_LFACLKEN0_LESENSE_SHIFT                0                                      
01369 #define _CMU_LFACLKEN0_LESENSE_MASK                 0x1UL                                  
01370 #define _CMU_LFACLKEN0_LESENSE_DEFAULT              0x00000000UL                           
01371 #define CMU_LFACLKEN0_LESENSE_DEFAULT               (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)  
01372 #define CMU_LFACLKEN0_RTC                           (0x1UL << 1)                           
01373 #define _CMU_LFACLKEN0_RTC_SHIFT                    1                                      
01374 #define _CMU_LFACLKEN0_RTC_MASK                     0x2UL                                  
01375 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                           
01376 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 1)      
01377 #define CMU_LFACLKEN0_LETIMER0                      (0x1UL << 2)                           
01378 #define _CMU_LFACLKEN0_LETIMER0_SHIFT               2                                      
01379 #define _CMU_LFACLKEN0_LETIMER0_MASK                0x4UL                                  
01380 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT             0x00000000UL                           
01381 #define CMU_LFACLKEN0_LETIMER0_DEFAULT              (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) 
01383 /* Bit fields for CMU LFBCLKEN0 */
01384 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
01385 #define _CMU_LFBCLKEN0_MASK                         0x00000003UL                          
01386 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
01387 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
01388 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
01389 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
01390 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
01391 #define CMU_LFBCLKEN0_LEUART1                       (0x1UL << 1)                          
01392 #define _CMU_LFBCLKEN0_LEUART1_SHIFT                1                                     
01393 #define _CMU_LFBCLKEN0_LEUART1_MASK                 0x2UL                                 
01394 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT              0x00000000UL                          
01395 #define CMU_LFBCLKEN0_LEUART1_DEFAULT               (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) 
01397 /* Bit fields for CMU LFAPRESC0 */
01398 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                            
01399 #define _CMU_LFAPRESC0_MASK                         0x00000FF3UL                            
01400 #define _CMU_LFAPRESC0_LESENSE_SHIFT                0                                       
01401 #define _CMU_LFAPRESC0_LESENSE_MASK                 0x3UL                                   
01402 #define _CMU_LFAPRESC0_LESENSE_DIV1                 0x00000000UL                            
01403 #define _CMU_LFAPRESC0_LESENSE_DIV2                 0x00000001UL                            
01404 #define _CMU_LFAPRESC0_LESENSE_DIV4                 0x00000002UL                            
01405 #define _CMU_LFAPRESC0_LESENSE_DIV8                 0x00000003UL                            
01406 #define CMU_LFAPRESC0_LESENSE_DIV1                  (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)      
01407 #define CMU_LFAPRESC0_LESENSE_DIV2                  (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)      
01408 #define CMU_LFAPRESC0_LESENSE_DIV4                  (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)      
01409 #define CMU_LFAPRESC0_LESENSE_DIV8                  (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)      
01410 #define _CMU_LFAPRESC0_RTC_SHIFT                    4                                       
01411 #define _CMU_LFAPRESC0_RTC_MASK                     0xF0UL                                  
01412 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                            
01413 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                            
01414 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                            
01415 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                            
01416 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                            
01417 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                            
01418 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                            
01419 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                            
01420 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                            
01421 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                            
01422 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                            
01423 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                            
01424 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                            
01425 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                            
01426 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                            
01427 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                            
01428 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 4)          
01429 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 4)          
01430 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 4)          
01431 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 4)          
01432 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 4)         
01433 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 4)         
01434 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 4)         
01435 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 4)        
01436 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 4)        
01437 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 4)        
01438 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 4)       
01439 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 4)       
01440 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 4)       
01441 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 4)       
01442 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 4)      
01443 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 4)      
01444 #define _CMU_LFAPRESC0_LETIMER0_SHIFT               8                                       
01445 #define _CMU_LFAPRESC0_LETIMER0_MASK                0xF00UL                                 
01446 #define _CMU_LFAPRESC0_LETIMER0_DIV1                0x00000000UL                            
01447 #define _CMU_LFAPRESC0_LETIMER0_DIV2                0x00000001UL                            
01448 #define _CMU_LFAPRESC0_LETIMER0_DIV4                0x00000002UL                            
01449 #define _CMU_LFAPRESC0_LETIMER0_DIV8                0x00000003UL                            
01450 #define _CMU_LFAPRESC0_LETIMER0_DIV16               0x00000004UL                            
01451 #define _CMU_LFAPRESC0_LETIMER0_DIV32               0x00000005UL                            
01452 #define _CMU_LFAPRESC0_LETIMER0_DIV64               0x00000006UL                            
01453 #define _CMU_LFAPRESC0_LETIMER0_DIV128              0x00000007UL                            
01454 #define _CMU_LFAPRESC0_LETIMER0_DIV256              0x00000008UL                            
01455 #define _CMU_LFAPRESC0_LETIMER0_DIV512              0x00000009UL                            
01456 #define _CMU_LFAPRESC0_LETIMER0_DIV1024             0x0000000AUL                            
01457 #define _CMU_LFAPRESC0_LETIMER0_DIV2048             0x0000000BUL                            
01458 #define _CMU_LFAPRESC0_LETIMER0_DIV4096             0x0000000CUL                            
01459 #define _CMU_LFAPRESC0_LETIMER0_DIV8192             0x0000000DUL                            
01460 #define _CMU_LFAPRESC0_LETIMER0_DIV16384            0x0000000EUL                            
01461 #define _CMU_LFAPRESC0_LETIMER0_DIV32768            0x0000000FUL                            
01462 #define CMU_LFAPRESC0_LETIMER0_DIV1                 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)     
01463 #define CMU_LFAPRESC0_LETIMER0_DIV2                 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)     
01464 #define CMU_LFAPRESC0_LETIMER0_DIV4                 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)     
01465 #define CMU_LFAPRESC0_LETIMER0_DIV8                 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)     
01466 #define CMU_LFAPRESC0_LETIMER0_DIV16                (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)    
01467 #define CMU_LFAPRESC0_LETIMER0_DIV32                (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)    
01468 #define CMU_LFAPRESC0_LETIMER0_DIV64                (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)    
01469 #define CMU_LFAPRESC0_LETIMER0_DIV128               (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)   
01470 #define CMU_LFAPRESC0_LETIMER0_DIV256               (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)   
01471 #define CMU_LFAPRESC0_LETIMER0_DIV512               (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)   
01472 #define CMU_LFAPRESC0_LETIMER0_DIV1024              (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)  
01473 #define CMU_LFAPRESC0_LETIMER0_DIV2048              (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)  
01474 #define CMU_LFAPRESC0_LETIMER0_DIV4096              (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)  
01475 #define CMU_LFAPRESC0_LETIMER0_DIV8192              (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)  
01476 #define CMU_LFAPRESC0_LETIMER0_DIV16384             (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) 
01477 #define CMU_LFAPRESC0_LETIMER0_DIV32768             (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) 
01479 /* Bit fields for CMU LFBPRESC0 */
01480 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
01481 #define _CMU_LFBPRESC0_MASK                         0x00000033UL                       
01482 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
01483 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
01484 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
01485 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
01486 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
01487 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
01488 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
01489 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
01490 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
01491 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
01492 #define _CMU_LFBPRESC0_LEUART1_SHIFT                4                                  
01493 #define _CMU_LFBPRESC0_LEUART1_MASK                 0x30UL                             
01494 #define _CMU_LFBPRESC0_LEUART1_DIV1                 0x00000000UL                       
01495 #define _CMU_LFBPRESC0_LEUART1_DIV2                 0x00000001UL                       
01496 #define _CMU_LFBPRESC0_LEUART1_DIV4                 0x00000002UL                       
01497 #define _CMU_LFBPRESC0_LEUART1_DIV8                 0x00000003UL                       
01498 #define CMU_LFBPRESC0_LEUART1_DIV1                  (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) 
01499 #define CMU_LFBPRESC0_LEUART1_DIV2                  (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) 
01500 #define CMU_LFBPRESC0_LEUART1_DIV4                  (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) 
01501 #define CMU_LFBPRESC0_LEUART1_DIV8                  (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) 
01503 /* Bit fields for CMU PCNTCTRL */
01504 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
01505 #define _CMU_PCNTCTRL_MASK                          0x0000003FUL                             
01506 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
01507 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
01508 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
01509 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
01510 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
01511 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
01512 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
01513 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
01514 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
01515 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
01516 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
01517 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
01518 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
01519 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
01520 #define CMU_PCNTCTRL_PCNT1CLKEN                     (0x1UL << 2)                             
01521 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT              2                                        
01522 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK               0x4UL                                    
01523 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT            0x00000000UL                             
01524 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)  
01525 #define CMU_PCNTCTRL_PCNT1CLKSEL                    (0x1UL << 3)                             
01526 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT             3                                        
01527 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK              0x8UL                                    
01528 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT           0x00000000UL                             
01529 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK            0x00000000UL                             
01530 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0           0x00000001UL                             
01531 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) 
01532 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)  
01533 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0            (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) 
01534 #define CMU_PCNTCTRL_PCNT2CLKEN                     (0x1UL << 4)                             
01535 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT              4                                        
01536 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK               0x10UL                                   
01537 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT            0x00000000UL                             
01538 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)  
01539 #define CMU_PCNTCTRL_PCNT2CLKSEL                    (0x1UL << 5)                             
01540 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT             5                                        
01541 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK              0x20UL                                   
01542 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT           0x00000000UL                             
01543 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK            0x00000000UL                             
01544 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0           0x00000001UL                             
01545 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) 
01546 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)  
01547 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0            (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) 
01549 /* Bit fields for CMU ROUTE */
01550 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
01551 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
01552 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
01553 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
01554 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
01555 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
01556 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
01557 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
01558 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
01559 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
01560 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
01561 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
01562 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
01563 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
01564 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
01565 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
01566 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
01567 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
01568 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
01569 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
01570 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
01571 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
01573 /* Bit fields for CMU LOCK */
01574 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
01575 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
01576 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
01577 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
01578 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
01579 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
01580 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
01581 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
01582 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
01583 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
01584 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
01585 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
01586 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
01587 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
01593 /**************************************************************************/
01597 #define MSC_UNLOCK_CODE      0x1B71 
01598 #define EMU_UNLOCK_CODE      0xADE8 
01599 #define CMU_UNLOCK_CODE      0x580E 
01600 #define TIMER_UNLOCK_CODE    0xCE80 
01601 #define GPIO_UNLOCK_CODE     0xA534 
01602 #define BURTC_UNLOCK_CODE    0xAEE8 
01608 /**************************************************************************/
01613 #include "efm32gg_af_ports.h"
01614 #include "efm32gg_af_pins.h"
01615 
01618 /**************************************************************************/
01631 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
01632   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
01633 
01638 #ifdef __cplusplus
01639 }
01640 #endif
01641 #endif /* __EFM32GG390F1024_H */