Go to the source code of this file.
Defines | |
#define | _UART_CTRL_RESETVALUE 0x00000000UL |
#define | _UART_CTRL_MASK 0x7DFFFF7FUL |
#define | UART_CTRL_SYNC (0x1UL << 0) |
#define | _UART_CTRL_SYNC_SHIFT 0 |
#define | _UART_CTRL_SYNC_MASK 0x1UL |
#define | _UART_CTRL_SYNC_DEFAULT 0x00000000UL |
#define | UART_CTRL_SYNC_DEFAULT (_UART_CTRL_SYNC_DEFAULT << 0) |
#define | UART_CTRL_LOOPBK (0x1UL << 1) |
#define | _UART_CTRL_LOOPBK_SHIFT 1 |
#define | _UART_CTRL_LOOPBK_MASK 0x2UL |
#define | _UART_CTRL_LOOPBK_DEFAULT 0x00000000UL |
#define | UART_CTRL_LOOPBK_DEFAULT (_UART_CTRL_LOOPBK_DEFAULT << 1) |
#define | UART_CTRL_CCEN (0x1UL << 2) |
#define | _UART_CTRL_CCEN_SHIFT 2 |
#define | _UART_CTRL_CCEN_MASK 0x4UL |
#define | _UART_CTRL_CCEN_DEFAULT 0x00000000UL |
#define | UART_CTRL_CCEN_DEFAULT (_UART_CTRL_CCEN_DEFAULT << 2) |
#define | UART_CTRL_MPM (0x1UL << 3) |
#define | _UART_CTRL_MPM_SHIFT 3 |
#define | _UART_CTRL_MPM_MASK 0x8UL |
#define | _UART_CTRL_MPM_DEFAULT 0x00000000UL |
#define | UART_CTRL_MPM_DEFAULT (_UART_CTRL_MPM_DEFAULT << 3) |
#define | UART_CTRL_MPAB (0x1UL << 4) |
#define | _UART_CTRL_MPAB_SHIFT 4 |
#define | _UART_CTRL_MPAB_MASK 0x10UL |
#define | _UART_CTRL_MPAB_DEFAULT 0x00000000UL |
#define | UART_CTRL_MPAB_DEFAULT (_UART_CTRL_MPAB_DEFAULT << 4) |
#define | _UART_CTRL_OVS_SHIFT 5 |
#define | _UART_CTRL_OVS_MASK 0x60UL |
#define | _UART_CTRL_OVS_DEFAULT 0x00000000UL |
#define | _UART_CTRL_OVS_X16 0x00000000UL |
#define | _UART_CTRL_OVS_X8 0x00000001UL |
#define | _UART_CTRL_OVS_X6 0x00000002UL |
#define | _UART_CTRL_OVS_X4 0x00000003UL |
#define | UART_CTRL_OVS_DEFAULT (_UART_CTRL_OVS_DEFAULT << 5) |
#define | UART_CTRL_OVS_X16 (_UART_CTRL_OVS_X16 << 5) |
#define | UART_CTRL_OVS_X8 (_UART_CTRL_OVS_X8 << 5) |
#define | UART_CTRL_OVS_X6 (_UART_CTRL_OVS_X6 << 5) |
#define | UART_CTRL_OVS_X4 (_UART_CTRL_OVS_X4 << 5) |
#define | UART_CTRL_CLKPOL (0x1UL << 8) |
#define | _UART_CTRL_CLKPOL_SHIFT 8 |
#define | _UART_CTRL_CLKPOL_MASK 0x100UL |
#define | _UART_CTRL_CLKPOL_DEFAULT 0x00000000UL |
#define | _UART_CTRL_CLKPOL_IDLELOW 0x00000000UL |
#define | _UART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL |
#define | UART_CTRL_CLKPOL_DEFAULT (_UART_CTRL_CLKPOL_DEFAULT << 8) |
#define | UART_CTRL_CLKPOL_IDLELOW (_UART_CTRL_CLKPOL_IDLELOW << 8) |
#define | UART_CTRL_CLKPOL_IDLEHIGH (_UART_CTRL_CLKPOL_IDLEHIGH << 8) |
#define | UART_CTRL_CLKPHA (0x1UL << 9) |
#define | _UART_CTRL_CLKPHA_SHIFT 9 |
#define | _UART_CTRL_CLKPHA_MASK 0x200UL |
#define | _UART_CTRL_CLKPHA_DEFAULT 0x00000000UL |
#define | _UART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL |
#define | _UART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL |
#define | UART_CTRL_CLKPHA_DEFAULT (_UART_CTRL_CLKPHA_DEFAULT << 9) |
#define | UART_CTRL_CLKPHA_SAMPLELEADING (_UART_CTRL_CLKPHA_SAMPLELEADING << 9) |
#define | UART_CTRL_CLKPHA_SAMPLETRAILING (_UART_CTRL_CLKPHA_SAMPLETRAILING << 9) |
#define | UART_CTRL_MSBF (0x1UL << 10) |
#define | _UART_CTRL_MSBF_SHIFT 10 |
#define | _UART_CTRL_MSBF_MASK 0x400UL |
#define | _UART_CTRL_MSBF_DEFAULT 0x00000000UL |
#define | UART_CTRL_MSBF_DEFAULT (_UART_CTRL_MSBF_DEFAULT << 10) |
#define | UART_CTRL_CSMA (0x1UL << 11) |
#define | _UART_CTRL_CSMA_SHIFT 11 |
#define | _UART_CTRL_CSMA_MASK 0x800UL |
#define | _UART_CTRL_CSMA_DEFAULT 0x00000000UL |
#define | _UART_CTRL_CSMA_NOACTION 0x00000000UL |
#define | _UART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL |
#define | UART_CTRL_CSMA_DEFAULT (_UART_CTRL_CSMA_DEFAULT << 11) |
#define | UART_CTRL_CSMA_NOACTION (_UART_CTRL_CSMA_NOACTION << 11) |
#define | UART_CTRL_CSMA_GOTOSLAVEMODE (_UART_CTRL_CSMA_GOTOSLAVEMODE << 11) |
#define | UART_CTRL_TXBIL (0x1UL << 12) |
#define | _UART_CTRL_TXBIL_SHIFT 12 |
#define | _UART_CTRL_TXBIL_MASK 0x1000UL |
#define | _UART_CTRL_TXBIL_DEFAULT 0x00000000UL |
#define | _UART_CTRL_TXBIL_EMPTY 0x00000000UL |
#define | _UART_CTRL_TXBIL_HALFFULL 0x00000001UL |
#define | UART_CTRL_TXBIL_DEFAULT (_UART_CTRL_TXBIL_DEFAULT << 12) |
#define | UART_CTRL_TXBIL_EMPTY (_UART_CTRL_TXBIL_EMPTY << 12) |
#define | UART_CTRL_TXBIL_HALFFULL (_UART_CTRL_TXBIL_HALFFULL << 12) |
#define | UART_CTRL_RXINV (0x1UL << 13) |
#define | _UART_CTRL_RXINV_SHIFT 13 |
#define | _UART_CTRL_RXINV_MASK 0x2000UL |
#define | _UART_CTRL_RXINV_DEFAULT 0x00000000UL |
#define | UART_CTRL_RXINV_DEFAULT (_UART_CTRL_RXINV_DEFAULT << 13) |
#define | UART_CTRL_TXINV (0x1UL << 14) |
#define | _UART_CTRL_TXINV_SHIFT 14 |
#define | _UART_CTRL_TXINV_MASK 0x4000UL |
#define | _UART_CTRL_TXINV_DEFAULT 0x00000000UL |
#define | UART_CTRL_TXINV_DEFAULT (_UART_CTRL_TXINV_DEFAULT << 14) |
#define | UART_CTRL_CSINV (0x1UL << 15) |
#define | _UART_CTRL_CSINV_SHIFT 15 |
#define | _UART_CTRL_CSINV_MASK 0x8000UL |
#define | _UART_CTRL_CSINV_DEFAULT 0x00000000UL |
#define | UART_CTRL_CSINV_DEFAULT (_UART_CTRL_CSINV_DEFAULT << 15) |
#define | UART_CTRL_AUTOCS (0x1UL << 16) |
#define | _UART_CTRL_AUTOCS_SHIFT 16 |
#define | _UART_CTRL_AUTOCS_MASK 0x10000UL |
#define | _UART_CTRL_AUTOCS_DEFAULT 0x00000000UL |
#define | UART_CTRL_AUTOCS_DEFAULT (_UART_CTRL_AUTOCS_DEFAULT << 16) |
#define | UART_CTRL_AUTOTRI (0x1UL << 17) |
#define | _UART_CTRL_AUTOTRI_SHIFT 17 |
#define | _UART_CTRL_AUTOTRI_MASK 0x20000UL |
#define | _UART_CTRL_AUTOTRI_DEFAULT 0x00000000UL |
#define | UART_CTRL_AUTOTRI_DEFAULT (_UART_CTRL_AUTOTRI_DEFAULT << 17) |
#define | UART_CTRL_SCMODE (0x1UL << 18) |
#define | _UART_CTRL_SCMODE_SHIFT 18 |
#define | _UART_CTRL_SCMODE_MASK 0x40000UL |
#define | _UART_CTRL_SCMODE_DEFAULT 0x00000000UL |
#define | UART_CTRL_SCMODE_DEFAULT (_UART_CTRL_SCMODE_DEFAULT << 18) |
#define | UART_CTRL_SCRETRANS (0x1UL << 19) |
#define | _UART_CTRL_SCRETRANS_SHIFT 19 |
#define | _UART_CTRL_SCRETRANS_MASK 0x80000UL |
#define | _UART_CTRL_SCRETRANS_DEFAULT 0x00000000UL |
#define | UART_CTRL_SCRETRANS_DEFAULT (_UART_CTRL_SCRETRANS_DEFAULT << 19) |
#define | UART_CTRL_SKIPPERRF (0x1UL << 20) |
#define | _UART_CTRL_SKIPPERRF_SHIFT 20 |
#define | _UART_CTRL_SKIPPERRF_MASK 0x100000UL |
#define | _UART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL |
#define | UART_CTRL_SKIPPERRF_DEFAULT (_UART_CTRL_SKIPPERRF_DEFAULT << 20) |
#define | UART_CTRL_BIT8DV (0x1UL << 21) |
#define | _UART_CTRL_BIT8DV_SHIFT 21 |
#define | _UART_CTRL_BIT8DV_MASK 0x200000UL |
#define | _UART_CTRL_BIT8DV_DEFAULT 0x00000000UL |
#define | UART_CTRL_BIT8DV_DEFAULT (_UART_CTRL_BIT8DV_DEFAULT << 21) |
#define | UART_CTRL_ERRSDMA (0x1UL << 22) |
#define | _UART_CTRL_ERRSDMA_SHIFT 22 |
#define | _UART_CTRL_ERRSDMA_MASK 0x400000UL |
#define | _UART_CTRL_ERRSDMA_DEFAULT 0x00000000UL |
#define | UART_CTRL_ERRSDMA_DEFAULT (_UART_CTRL_ERRSDMA_DEFAULT << 22) |
#define | UART_CTRL_ERRSRX (0x1UL << 23) |
#define | _UART_CTRL_ERRSRX_SHIFT 23 |
#define | _UART_CTRL_ERRSRX_MASK 0x800000UL |
#define | _UART_CTRL_ERRSRX_DEFAULT 0x00000000UL |
#define | UART_CTRL_ERRSRX_DEFAULT (_UART_CTRL_ERRSRX_DEFAULT << 23) |
#define | UART_CTRL_ERRSTX (0x1UL << 24) |
#define | _UART_CTRL_ERRSTX_SHIFT 24 |
#define | _UART_CTRL_ERRSTX_MASK 0x1000000UL |
#define | _UART_CTRL_ERRSTX_DEFAULT 0x00000000UL |
#define | UART_CTRL_ERRSTX_DEFAULT (_UART_CTRL_ERRSTX_DEFAULT << 24) |
#define | _UART_CTRL_TXDELAY_SHIFT 26 |
#define | _UART_CTRL_TXDELAY_MASK 0xC000000UL |
#define | _UART_CTRL_TXDELAY_DEFAULT 0x00000000UL |
#define | _UART_CTRL_TXDELAY_NONE 0x00000000UL |
#define | _UART_CTRL_TXDELAY_SINGLE 0x00000001UL |
#define | _UART_CTRL_TXDELAY_DOUBLE 0x00000002UL |
#define | _UART_CTRL_TXDELAY_TRIPLE 0x00000003UL |
#define | UART_CTRL_TXDELAY_DEFAULT (_UART_CTRL_TXDELAY_DEFAULT << 26) |
#define | UART_CTRL_TXDELAY_NONE (_UART_CTRL_TXDELAY_NONE << 26) |
#define | UART_CTRL_TXDELAY_SINGLE (_UART_CTRL_TXDELAY_SINGLE << 26) |
#define | UART_CTRL_TXDELAY_DOUBLE (_UART_CTRL_TXDELAY_DOUBLE << 26) |
#define | UART_CTRL_TXDELAY_TRIPLE (_UART_CTRL_TXDELAY_TRIPLE << 26) |
#define | UART_CTRL_BYTESWAP (0x1UL << 28) |
#define | _UART_CTRL_BYTESWAP_SHIFT 28 |
#define | _UART_CTRL_BYTESWAP_MASK 0x10000000UL |
#define | _UART_CTRL_BYTESWAP_DEFAULT 0x00000000UL |
#define | UART_CTRL_BYTESWAP_DEFAULT (_UART_CTRL_BYTESWAP_DEFAULT << 28) |
#define | UART_CTRL_AUTOTX (0x1UL << 29) |
#define | _UART_CTRL_AUTOTX_SHIFT 29 |
#define | _UART_CTRL_AUTOTX_MASK 0x20000000UL |
#define | _UART_CTRL_AUTOTX_DEFAULT 0x00000000UL |
#define | UART_CTRL_AUTOTX_DEFAULT (_UART_CTRL_AUTOTX_DEFAULT << 29) |
#define | UART_CTRL_MVDIS (0x1UL << 30) |
#define | _UART_CTRL_MVDIS_SHIFT 30 |
#define | _UART_CTRL_MVDIS_MASK 0x40000000UL |
#define | _UART_CTRL_MVDIS_DEFAULT 0x00000000UL |
#define | UART_CTRL_MVDIS_DEFAULT (_UART_CTRL_MVDIS_DEFAULT << 30) |
#define | _UART_FRAME_RESETVALUE 0x00001005UL |
#define | _UART_FRAME_MASK 0x0000330FUL |
#define | _UART_FRAME_DATABITS_SHIFT 0 |
#define | _UART_FRAME_DATABITS_MASK 0xFUL |
#define | _UART_FRAME_DATABITS_FOUR 0x00000001UL |
#define | _UART_FRAME_DATABITS_FIVE 0x00000002UL |
#define | _UART_FRAME_DATABITS_SIX 0x00000003UL |
#define | _UART_FRAME_DATABITS_SEVEN 0x00000004UL |
#define | _UART_FRAME_DATABITS_DEFAULT 0x00000005UL |
#define | _UART_FRAME_DATABITS_EIGHT 0x00000005UL |
#define | _UART_FRAME_DATABITS_NINE 0x00000006UL |
#define | _UART_FRAME_DATABITS_TEN 0x00000007UL |
#define | _UART_FRAME_DATABITS_ELEVEN 0x00000008UL |
#define | _UART_FRAME_DATABITS_TWELVE 0x00000009UL |
#define | _UART_FRAME_DATABITS_THIRTEEN 0x0000000AUL |
#define | _UART_FRAME_DATABITS_FOURTEEN 0x0000000BUL |
#define | _UART_FRAME_DATABITS_FIFTEEN 0x0000000CUL |
#define | _UART_FRAME_DATABITS_SIXTEEN 0x0000000DUL |
#define | UART_FRAME_DATABITS_FOUR (_UART_FRAME_DATABITS_FOUR << 0) |
#define | UART_FRAME_DATABITS_FIVE (_UART_FRAME_DATABITS_FIVE << 0) |
#define | UART_FRAME_DATABITS_SIX (_UART_FRAME_DATABITS_SIX << 0) |
#define | UART_FRAME_DATABITS_SEVEN (_UART_FRAME_DATABITS_SEVEN << 0) |
#define | UART_FRAME_DATABITS_DEFAULT (_UART_FRAME_DATABITS_DEFAULT << 0) |
#define | UART_FRAME_DATABITS_EIGHT (_UART_FRAME_DATABITS_EIGHT << 0) |
#define | UART_FRAME_DATABITS_NINE (_UART_FRAME_DATABITS_NINE << 0) |
#define | UART_FRAME_DATABITS_TEN (_UART_FRAME_DATABITS_TEN << 0) |
#define | UART_FRAME_DATABITS_ELEVEN (_UART_FRAME_DATABITS_ELEVEN << 0) |
#define | UART_FRAME_DATABITS_TWELVE (_UART_FRAME_DATABITS_TWELVE << 0) |
#define | UART_FRAME_DATABITS_THIRTEEN (_UART_FRAME_DATABITS_THIRTEEN << 0) |
#define | UART_FRAME_DATABITS_FOURTEEN (_UART_FRAME_DATABITS_FOURTEEN << 0) |
#define | UART_FRAME_DATABITS_FIFTEEN (_UART_FRAME_DATABITS_FIFTEEN << 0) |
#define | UART_FRAME_DATABITS_SIXTEEN (_UART_FRAME_DATABITS_SIXTEEN << 0) |
#define | _UART_FRAME_PARITY_SHIFT 8 |
#define | _UART_FRAME_PARITY_MASK 0x300UL |
#define | _UART_FRAME_PARITY_DEFAULT 0x00000000UL |
#define | _UART_FRAME_PARITY_NONE 0x00000000UL |
#define | _UART_FRAME_PARITY_EVEN 0x00000002UL |
#define | _UART_FRAME_PARITY_ODD 0x00000003UL |
#define | UART_FRAME_PARITY_DEFAULT (_UART_FRAME_PARITY_DEFAULT << 8) |
#define | UART_FRAME_PARITY_NONE (_UART_FRAME_PARITY_NONE << 8) |
#define | UART_FRAME_PARITY_EVEN (_UART_FRAME_PARITY_EVEN << 8) |
#define | UART_FRAME_PARITY_ODD (_UART_FRAME_PARITY_ODD << 8) |
#define | _UART_FRAME_STOPBITS_SHIFT 12 |
#define | _UART_FRAME_STOPBITS_MASK 0x3000UL |
#define | _UART_FRAME_STOPBITS_HALF 0x00000000UL |
#define | _UART_FRAME_STOPBITS_DEFAULT 0x00000001UL |
#define | _UART_FRAME_STOPBITS_ONE 0x00000001UL |
#define | _UART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL |
#define | _UART_FRAME_STOPBITS_TWO 0x00000003UL |
#define | UART_FRAME_STOPBITS_HALF (_UART_FRAME_STOPBITS_HALF << 12) |
#define | UART_FRAME_STOPBITS_DEFAULT (_UART_FRAME_STOPBITS_DEFAULT << 12) |
#define | UART_FRAME_STOPBITS_ONE (_UART_FRAME_STOPBITS_ONE << 12) |
#define | UART_FRAME_STOPBITS_ONEANDAHALF (_UART_FRAME_STOPBITS_ONEANDAHALF << 12) |
#define | UART_FRAME_STOPBITS_TWO (_UART_FRAME_STOPBITS_TWO << 12) |
#define | _UART_TRIGCTRL_RESETVALUE 0x00000000UL |
#define | _UART_TRIGCTRL_MASK 0x00000077UL |
#define | _UART_TRIGCTRL_TSEL_SHIFT 0 |
#define | _UART_TRIGCTRL_TSEL_MASK 0x7UL |
#define | _UART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL |
#define | _UART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL |
#define | UART_TRIGCTRL_TSEL_DEFAULT (_UART_TRIGCTRL_TSEL_DEFAULT << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH0 (_UART_TRIGCTRL_TSEL_PRSCH0 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH1 (_UART_TRIGCTRL_TSEL_PRSCH1 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH2 (_UART_TRIGCTRL_TSEL_PRSCH2 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH3 (_UART_TRIGCTRL_TSEL_PRSCH3 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH4 (_UART_TRIGCTRL_TSEL_PRSCH4 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH5 (_UART_TRIGCTRL_TSEL_PRSCH5 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH6 (_UART_TRIGCTRL_TSEL_PRSCH6 << 0) |
#define | UART_TRIGCTRL_TSEL_PRSCH7 (_UART_TRIGCTRL_TSEL_PRSCH7 << 0) |
#define | UART_TRIGCTRL_RXTEN (0x1UL << 4) |
#define | _UART_TRIGCTRL_RXTEN_SHIFT 4 |
#define | _UART_TRIGCTRL_RXTEN_MASK 0x10UL |
#define | _UART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL |
#define | UART_TRIGCTRL_RXTEN_DEFAULT (_UART_TRIGCTRL_RXTEN_DEFAULT << 4) |
#define | UART_TRIGCTRL_TXTEN (0x1UL << 5) |
#define | _UART_TRIGCTRL_TXTEN_SHIFT 5 |
#define | _UART_TRIGCTRL_TXTEN_MASK 0x20UL |
#define | _UART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL |
#define | UART_TRIGCTRL_TXTEN_DEFAULT (_UART_TRIGCTRL_TXTEN_DEFAULT << 5) |
#define | UART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) |
#define | _UART_TRIGCTRL_AUTOTXTEN_SHIFT 6 |
#define | _UART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL |
#define | _UART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL |
#define | UART_TRIGCTRL_AUTOTXTEN_DEFAULT (_UART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) |
#define | _UART_CMD_RESETVALUE 0x00000000UL |
#define | _UART_CMD_MASK 0x00000FFFUL |
#define | UART_CMD_RXEN (0x1UL << 0) |
#define | _UART_CMD_RXEN_SHIFT 0 |
#define | _UART_CMD_RXEN_MASK 0x1UL |
#define | _UART_CMD_RXEN_DEFAULT 0x00000000UL |
#define | UART_CMD_RXEN_DEFAULT (_UART_CMD_RXEN_DEFAULT << 0) |
#define | UART_CMD_RXDIS (0x1UL << 1) |
#define | _UART_CMD_RXDIS_SHIFT 1 |
#define | _UART_CMD_RXDIS_MASK 0x2UL |
#define | _UART_CMD_RXDIS_DEFAULT 0x00000000UL |
#define | UART_CMD_RXDIS_DEFAULT (_UART_CMD_RXDIS_DEFAULT << 1) |
#define | UART_CMD_TXEN (0x1UL << 2) |
#define | _UART_CMD_TXEN_SHIFT 2 |
#define | _UART_CMD_TXEN_MASK 0x4UL |
#define | _UART_CMD_TXEN_DEFAULT 0x00000000UL |
#define | UART_CMD_TXEN_DEFAULT (_UART_CMD_TXEN_DEFAULT << 2) |
#define | UART_CMD_TXDIS (0x1UL << 3) |
#define | _UART_CMD_TXDIS_SHIFT 3 |
#define | _UART_CMD_TXDIS_MASK 0x8UL |
#define | _UART_CMD_TXDIS_DEFAULT 0x00000000UL |
#define | UART_CMD_TXDIS_DEFAULT (_UART_CMD_TXDIS_DEFAULT << 3) |
#define | UART_CMD_MASTEREN (0x1UL << 4) |
#define | _UART_CMD_MASTEREN_SHIFT 4 |
#define | _UART_CMD_MASTEREN_MASK 0x10UL |
#define | _UART_CMD_MASTEREN_DEFAULT 0x00000000UL |
#define | UART_CMD_MASTEREN_DEFAULT (_UART_CMD_MASTEREN_DEFAULT << 4) |
#define | UART_CMD_MASTERDIS (0x1UL << 5) |
#define | _UART_CMD_MASTERDIS_SHIFT 5 |
#define | _UART_CMD_MASTERDIS_MASK 0x20UL |
#define | _UART_CMD_MASTERDIS_DEFAULT 0x00000000UL |
#define | UART_CMD_MASTERDIS_DEFAULT (_UART_CMD_MASTERDIS_DEFAULT << 5) |
#define | UART_CMD_RXBLOCKEN (0x1UL << 6) |
#define | _UART_CMD_RXBLOCKEN_SHIFT 6 |
#define | _UART_CMD_RXBLOCKEN_MASK 0x40UL |
#define | _UART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL |
#define | UART_CMD_RXBLOCKEN_DEFAULT (_UART_CMD_RXBLOCKEN_DEFAULT << 6) |
#define | UART_CMD_RXBLOCKDIS (0x1UL << 7) |
#define | _UART_CMD_RXBLOCKDIS_SHIFT 7 |
#define | _UART_CMD_RXBLOCKDIS_MASK 0x80UL |
#define | _UART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL |
#define | UART_CMD_RXBLOCKDIS_DEFAULT (_UART_CMD_RXBLOCKDIS_DEFAULT << 7) |
#define | UART_CMD_TXTRIEN (0x1UL << 8) |
#define | _UART_CMD_TXTRIEN_SHIFT 8 |
#define | _UART_CMD_TXTRIEN_MASK 0x100UL |
#define | _UART_CMD_TXTRIEN_DEFAULT 0x00000000UL |
#define | UART_CMD_TXTRIEN_DEFAULT (_UART_CMD_TXTRIEN_DEFAULT << 8) |
#define | UART_CMD_TXTRIDIS (0x1UL << 9) |
#define | _UART_CMD_TXTRIDIS_SHIFT 9 |
#define | _UART_CMD_TXTRIDIS_MASK 0x200UL |
#define | _UART_CMD_TXTRIDIS_DEFAULT 0x00000000UL |
#define | UART_CMD_TXTRIDIS_DEFAULT (_UART_CMD_TXTRIDIS_DEFAULT << 9) |
#define | UART_CMD_CLEARTX (0x1UL << 10) |
#define | _UART_CMD_CLEARTX_SHIFT 10 |
#define | _UART_CMD_CLEARTX_MASK 0x400UL |
#define | _UART_CMD_CLEARTX_DEFAULT 0x00000000UL |
#define | UART_CMD_CLEARTX_DEFAULT (_UART_CMD_CLEARTX_DEFAULT << 10) |
#define | UART_CMD_CLEARRX (0x1UL << 11) |
#define | _UART_CMD_CLEARRX_SHIFT 11 |
#define | _UART_CMD_CLEARRX_MASK 0x800UL |
#define | _UART_CMD_CLEARRX_DEFAULT 0x00000000UL |
#define | UART_CMD_CLEARRX_DEFAULT (_UART_CMD_CLEARRX_DEFAULT << 11) |
#define | _UART_STATUS_RESETVALUE 0x00000040UL |
#define | _UART_STATUS_MASK 0x00001FFFUL |
#define | UART_STATUS_RXENS (0x1UL << 0) |
#define | _UART_STATUS_RXENS_SHIFT 0 |
#define | _UART_STATUS_RXENS_MASK 0x1UL |
#define | _UART_STATUS_RXENS_DEFAULT 0x00000000UL |
#define | UART_STATUS_RXENS_DEFAULT (_UART_STATUS_RXENS_DEFAULT << 0) |
#define | UART_STATUS_TXENS (0x1UL << 1) |
#define | _UART_STATUS_TXENS_SHIFT 1 |
#define | _UART_STATUS_TXENS_MASK 0x2UL |
#define | _UART_STATUS_TXENS_DEFAULT 0x00000000UL |
#define | UART_STATUS_TXENS_DEFAULT (_UART_STATUS_TXENS_DEFAULT << 1) |
#define | UART_STATUS_MASTER (0x1UL << 2) |
#define | _UART_STATUS_MASTER_SHIFT 2 |
#define | _UART_STATUS_MASTER_MASK 0x4UL |
#define | _UART_STATUS_MASTER_DEFAULT 0x00000000UL |
#define | UART_STATUS_MASTER_DEFAULT (_UART_STATUS_MASTER_DEFAULT << 2) |
#define | UART_STATUS_RXBLOCK (0x1UL << 3) |
#define | _UART_STATUS_RXBLOCK_SHIFT 3 |
#define | _UART_STATUS_RXBLOCK_MASK 0x8UL |
#define | _UART_STATUS_RXBLOCK_DEFAULT 0x00000000UL |
#define | UART_STATUS_RXBLOCK_DEFAULT (_UART_STATUS_RXBLOCK_DEFAULT << 3) |
#define | UART_STATUS_TXTRI (0x1UL << 4) |
#define | _UART_STATUS_TXTRI_SHIFT 4 |
#define | _UART_STATUS_TXTRI_MASK 0x10UL |
#define | _UART_STATUS_TXTRI_DEFAULT 0x00000000UL |
#define | UART_STATUS_TXTRI_DEFAULT (_UART_STATUS_TXTRI_DEFAULT << 4) |
#define | UART_STATUS_TXC (0x1UL << 5) |
#define | _UART_STATUS_TXC_SHIFT 5 |
#define | _UART_STATUS_TXC_MASK 0x20UL |
#define | _UART_STATUS_TXC_DEFAULT 0x00000000UL |
#define | UART_STATUS_TXC_DEFAULT (_UART_STATUS_TXC_DEFAULT << 5) |
#define | UART_STATUS_TXBL (0x1UL << 6) |
#define | _UART_STATUS_TXBL_SHIFT 6 |
#define | _UART_STATUS_TXBL_MASK 0x40UL |
#define | _UART_STATUS_TXBL_DEFAULT 0x00000001UL |
#define | UART_STATUS_TXBL_DEFAULT (_UART_STATUS_TXBL_DEFAULT << 6) |
#define | UART_STATUS_RXDATAV (0x1UL << 7) |
#define | _UART_STATUS_RXDATAV_SHIFT 7 |
#define | _UART_STATUS_RXDATAV_MASK 0x80UL |
#define | _UART_STATUS_RXDATAV_DEFAULT 0x00000000UL |
#define | UART_STATUS_RXDATAV_DEFAULT (_UART_STATUS_RXDATAV_DEFAULT << 7) |
#define | UART_STATUS_RXFULL (0x1UL << 8) |
#define | _UART_STATUS_RXFULL_SHIFT 8 |
#define | _UART_STATUS_RXFULL_MASK 0x100UL |
#define | _UART_STATUS_RXFULL_DEFAULT 0x00000000UL |
#define | UART_STATUS_RXFULL_DEFAULT (_UART_STATUS_RXFULL_DEFAULT << 8) |
#define | UART_STATUS_TXBDRIGHT (0x1UL << 9) |
#define | _UART_STATUS_TXBDRIGHT_SHIFT 9 |
#define | _UART_STATUS_TXBDRIGHT_MASK 0x200UL |
#define | _UART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL |
#define | UART_STATUS_TXBDRIGHT_DEFAULT (_UART_STATUS_TXBDRIGHT_DEFAULT << 9) |
#define | UART_STATUS_TXBSRIGHT (0x1UL << 10) |
#define | _UART_STATUS_TXBSRIGHT_SHIFT 10 |
#define | _UART_STATUS_TXBSRIGHT_MASK 0x400UL |
#define | _UART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL |
#define | UART_STATUS_TXBSRIGHT_DEFAULT (_UART_STATUS_TXBSRIGHT_DEFAULT << 10) |
#define | UART_STATUS_RXDATAVRIGHT (0x1UL << 11) |
#define | _UART_STATUS_RXDATAVRIGHT_SHIFT 11 |
#define | _UART_STATUS_RXDATAVRIGHT_MASK 0x800UL |
#define | _UART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL |
#define | UART_STATUS_RXDATAVRIGHT_DEFAULT (_UART_STATUS_RXDATAVRIGHT_DEFAULT << 11) |
#define | UART_STATUS_RXFULLRIGHT (0x1UL << 12) |
#define | _UART_STATUS_RXFULLRIGHT_SHIFT 12 |
#define | _UART_STATUS_RXFULLRIGHT_MASK 0x1000UL |
#define | _UART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL |
#define | UART_STATUS_RXFULLRIGHT_DEFAULT (_UART_STATUS_RXFULLRIGHT_DEFAULT << 12) |
#define | _UART_CLKDIV_RESETVALUE 0x00000000UL |
#define | _UART_CLKDIV_MASK 0x001FFFC0UL |
#define | _UART_CLKDIV_DIV_SHIFT 6 |
#define | _UART_CLKDIV_DIV_MASK 0x1FFFC0UL |
#define | _UART_CLKDIV_DIV_DEFAULT 0x00000000UL |
#define | UART_CLKDIV_DIV_DEFAULT (_UART_CLKDIV_DIV_DEFAULT << 6) |
#define | _UART_RXDATAX_RESETVALUE 0x00000000UL |
#define | _UART_RXDATAX_MASK 0x0000C1FFUL |
#define | _UART_RXDATAX_RXDATA_SHIFT 0 |
#define | _UART_RXDATAX_RXDATA_MASK 0x1FFUL |
#define | _UART_RXDATAX_RXDATA_DEFAULT 0x00000000UL |
#define | UART_RXDATAX_RXDATA_DEFAULT (_UART_RXDATAX_RXDATA_DEFAULT << 0) |
#define | UART_RXDATAX_PERR (0x1UL << 14) |
#define | _UART_RXDATAX_PERR_SHIFT 14 |
#define | _UART_RXDATAX_PERR_MASK 0x4000UL |
#define | _UART_RXDATAX_PERR_DEFAULT 0x00000000UL |
#define | UART_RXDATAX_PERR_DEFAULT (_UART_RXDATAX_PERR_DEFAULT << 14) |
#define | UART_RXDATAX_FERR (0x1UL << 15) |
#define | _UART_RXDATAX_FERR_SHIFT 15 |
#define | _UART_RXDATAX_FERR_MASK 0x8000UL |
#define | _UART_RXDATAX_FERR_DEFAULT 0x00000000UL |
#define | UART_RXDATAX_FERR_DEFAULT (_UART_RXDATAX_FERR_DEFAULT << 15) |
#define | _UART_RXDATA_RESETVALUE 0x00000000UL |
#define | _UART_RXDATA_MASK 0x000000FFUL |
#define | _UART_RXDATA_RXDATA_SHIFT 0 |
#define | _UART_RXDATA_RXDATA_MASK 0xFFUL |
#define | _UART_RXDATA_RXDATA_DEFAULT 0x00000000UL |
#define | UART_RXDATA_RXDATA_DEFAULT (_UART_RXDATA_RXDATA_DEFAULT << 0) |
#define | _UART_RXDOUBLEX_RESETVALUE 0x00000000UL |
#define | _UART_RXDOUBLEX_MASK 0xC1FFC1FFUL |
#define | _UART_RXDOUBLEX_RXDATA0_SHIFT 0 |
#define | _UART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL |
#define | _UART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEX_RXDATA0_DEFAULT (_UART_RXDOUBLEX_RXDATA0_DEFAULT << 0) |
#define | UART_RXDOUBLEX_PERR0 (0x1UL << 14) |
#define | _UART_RXDOUBLEX_PERR0_SHIFT 14 |
#define | _UART_RXDOUBLEX_PERR0_MASK 0x4000UL |
#define | _UART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEX_PERR0_DEFAULT (_UART_RXDOUBLEX_PERR0_DEFAULT << 14) |
#define | UART_RXDOUBLEX_FERR0 (0x1UL << 15) |
#define | _UART_RXDOUBLEX_FERR0_SHIFT 15 |
#define | _UART_RXDOUBLEX_FERR0_MASK 0x8000UL |
#define | _UART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEX_FERR0_DEFAULT (_UART_RXDOUBLEX_FERR0_DEFAULT << 15) |
#define | _UART_RXDOUBLEX_RXDATA1_SHIFT 16 |
#define | _UART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL |
#define | _UART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEX_RXDATA1_DEFAULT (_UART_RXDOUBLEX_RXDATA1_DEFAULT << 16) |
#define | UART_RXDOUBLEX_PERR1 (0x1UL << 30) |
#define | _UART_RXDOUBLEX_PERR1_SHIFT 30 |
#define | _UART_RXDOUBLEX_PERR1_MASK 0x40000000UL |
#define | _UART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEX_PERR1_DEFAULT (_UART_RXDOUBLEX_PERR1_DEFAULT << 30) |
#define | UART_RXDOUBLEX_FERR1 (0x1UL << 31) |
#define | _UART_RXDOUBLEX_FERR1_SHIFT 31 |
#define | _UART_RXDOUBLEX_FERR1_MASK 0x80000000UL |
#define | _UART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEX_FERR1_DEFAULT (_UART_RXDOUBLEX_FERR1_DEFAULT << 31) |
#define | _UART_RXDOUBLE_RESETVALUE 0x00000000UL |
#define | _UART_RXDOUBLE_MASK 0x0000FFFFUL |
#define | _UART_RXDOUBLE_RXDATA0_SHIFT 0 |
#define | _UART_RXDOUBLE_RXDATA0_MASK 0xFFUL |
#define | _UART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLE_RXDATA0_DEFAULT (_UART_RXDOUBLE_RXDATA0_DEFAULT << 0) |
#define | _UART_RXDOUBLE_RXDATA1_SHIFT 8 |
#define | _UART_RXDOUBLE_RXDATA1_MASK 0xFF00UL |
#define | _UART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLE_RXDATA1_DEFAULT (_UART_RXDOUBLE_RXDATA1_DEFAULT << 8) |
#define | _UART_RXDATAXP_RESETVALUE 0x00000000UL |
#define | _UART_RXDATAXP_MASK 0x0000C1FFUL |
#define | _UART_RXDATAXP_RXDATAP_SHIFT 0 |
#define | _UART_RXDATAXP_RXDATAP_MASK 0x1FFUL |
#define | _UART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL |
#define | UART_RXDATAXP_RXDATAP_DEFAULT (_UART_RXDATAXP_RXDATAP_DEFAULT << 0) |
#define | UART_RXDATAXP_PERRP (0x1UL << 14) |
#define | _UART_RXDATAXP_PERRP_SHIFT 14 |
#define | _UART_RXDATAXP_PERRP_MASK 0x4000UL |
#define | _UART_RXDATAXP_PERRP_DEFAULT 0x00000000UL |
#define | UART_RXDATAXP_PERRP_DEFAULT (_UART_RXDATAXP_PERRP_DEFAULT << 14) |
#define | UART_RXDATAXP_FERRP (0x1UL << 15) |
#define | _UART_RXDATAXP_FERRP_SHIFT 15 |
#define | _UART_RXDATAXP_FERRP_MASK 0x8000UL |
#define | _UART_RXDATAXP_FERRP_DEFAULT 0x00000000UL |
#define | UART_RXDATAXP_FERRP_DEFAULT (_UART_RXDATAXP_FERRP_DEFAULT << 15) |
#define | _UART_RXDOUBLEXP_RESETVALUE 0x00000000UL |
#define | _UART_RXDOUBLEXP_MASK 0xC1FFC1FFUL |
#define | _UART_RXDOUBLEXP_RXDATAP0_SHIFT 0 |
#define | _UART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL |
#define | _UART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEXP_RXDATAP0_DEFAULT (_UART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) |
#define | UART_RXDOUBLEXP_PERRP0 (0x1UL << 14) |
#define | _UART_RXDOUBLEXP_PERRP0_SHIFT 14 |
#define | _UART_RXDOUBLEXP_PERRP0_MASK 0x4000UL |
#define | _UART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEXP_PERRP0_DEFAULT (_UART_RXDOUBLEXP_PERRP0_DEFAULT << 14) |
#define | UART_RXDOUBLEXP_FERRP0 (0x1UL << 15) |
#define | _UART_RXDOUBLEXP_FERRP0_SHIFT 15 |
#define | _UART_RXDOUBLEXP_FERRP0_MASK 0x8000UL |
#define | _UART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEXP_FERRP0_DEFAULT (_UART_RXDOUBLEXP_FERRP0_DEFAULT << 15) |
#define | _UART_RXDOUBLEXP_RXDATAP1_SHIFT 16 |
#define | _UART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL |
#define | _UART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEXP_RXDATAP1_DEFAULT (_UART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) |
#define | UART_RXDOUBLEXP_PERRP1 (0x1UL << 30) |
#define | _UART_RXDOUBLEXP_PERRP1_SHIFT 30 |
#define | _UART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL |
#define | _UART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEXP_PERRP1_DEFAULT (_UART_RXDOUBLEXP_PERRP1_DEFAULT << 30) |
#define | UART_RXDOUBLEXP_FERRP1 (0x1UL << 31) |
#define | _UART_RXDOUBLEXP_FERRP1_SHIFT 31 |
#define | _UART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL |
#define | _UART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL |
#define | UART_RXDOUBLEXP_FERRP1_DEFAULT (_UART_RXDOUBLEXP_FERRP1_DEFAULT << 31) |
#define | _UART_TXDATAX_RESETVALUE 0x00000000UL |
#define | _UART_TXDATAX_MASK 0x0000F9FFUL |
#define | _UART_TXDATAX_TXDATAX_SHIFT 0 |
#define | _UART_TXDATAX_TXDATAX_MASK 0x1FFUL |
#define | _UART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL |
#define | UART_TXDATAX_TXDATAX_DEFAULT (_UART_TXDATAX_TXDATAX_DEFAULT << 0) |
#define | UART_TXDATAX_UBRXAT (0x1UL << 11) |
#define | _UART_TXDATAX_UBRXAT_SHIFT 11 |
#define | _UART_TXDATAX_UBRXAT_MASK 0x800UL |
#define | _UART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL |
#define | UART_TXDATAX_UBRXAT_DEFAULT (_UART_TXDATAX_UBRXAT_DEFAULT << 11) |
#define | UART_TXDATAX_TXTRIAT (0x1UL << 12) |
#define | _UART_TXDATAX_TXTRIAT_SHIFT 12 |
#define | _UART_TXDATAX_TXTRIAT_MASK 0x1000UL |
#define | _UART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL |
#define | UART_TXDATAX_TXTRIAT_DEFAULT (_UART_TXDATAX_TXTRIAT_DEFAULT << 12) |
#define | UART_TXDATAX_TXBREAK (0x1UL << 13) |
#define | _UART_TXDATAX_TXBREAK_SHIFT 13 |
#define | _UART_TXDATAX_TXBREAK_MASK 0x2000UL |
#define | _UART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL |
#define | UART_TXDATAX_TXBREAK_DEFAULT (_UART_TXDATAX_TXBREAK_DEFAULT << 13) |
#define | UART_TXDATAX_TXDISAT (0x1UL << 14) |
#define | _UART_TXDATAX_TXDISAT_SHIFT 14 |
#define | _UART_TXDATAX_TXDISAT_MASK 0x4000UL |
#define | _UART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL |
#define | UART_TXDATAX_TXDISAT_DEFAULT (_UART_TXDATAX_TXDISAT_DEFAULT << 14) |
#define | UART_TXDATAX_RXENAT (0x1UL << 15) |
#define | _UART_TXDATAX_RXENAT_SHIFT 15 |
#define | _UART_TXDATAX_RXENAT_MASK 0x8000UL |
#define | _UART_TXDATAX_RXENAT_DEFAULT 0x00000000UL |
#define | UART_TXDATAX_RXENAT_DEFAULT (_UART_TXDATAX_RXENAT_DEFAULT << 15) |
#define | _UART_TXDATA_RESETVALUE 0x00000000UL |
#define | _UART_TXDATA_MASK 0x000000FFUL |
#define | _UART_TXDATA_TXDATA_SHIFT 0 |
#define | _UART_TXDATA_TXDATA_MASK 0xFFUL |
#define | _UART_TXDATA_TXDATA_DEFAULT 0x00000000UL |
#define | UART_TXDATA_TXDATA_DEFAULT (_UART_TXDATA_TXDATA_DEFAULT << 0) |
#define | _UART_TXDOUBLEX_RESETVALUE 0x00000000UL |
#define | _UART_TXDOUBLEX_MASK 0xF9FFF9FFUL |
#define | _UART_TXDOUBLEX_TXDATA0_SHIFT 0 |
#define | _UART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL |
#define | _UART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXDATA0_DEFAULT (_UART_TXDOUBLEX_TXDATA0_DEFAULT << 0) |
#define | UART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) |
#define | _UART_TXDOUBLEX_UBRXAT0_SHIFT 11 |
#define | _UART_TXDOUBLEX_UBRXAT0_MASK 0x800UL |
#define | _UART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_UBRXAT0_DEFAULT (_UART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) |
#define | UART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) |
#define | _UART_TXDOUBLEX_TXTRIAT0_SHIFT 12 |
#define | _UART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL |
#define | _UART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXTRIAT0_DEFAULT (_UART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) |
#define | UART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) |
#define | _UART_TXDOUBLEX_TXBREAK0_SHIFT 13 |
#define | _UART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL |
#define | _UART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXBREAK0_DEFAULT (_UART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) |
#define | UART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) |
#define | _UART_TXDOUBLEX_TXDISAT0_SHIFT 14 |
#define | _UART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL |
#define | _UART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXDISAT0_DEFAULT (_UART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) |
#define | UART_TXDOUBLEX_RXENAT0 (0x1UL << 15) |
#define | _UART_TXDOUBLEX_RXENAT0_SHIFT 15 |
#define | _UART_TXDOUBLEX_RXENAT0_MASK 0x8000UL |
#define | _UART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_RXENAT0_DEFAULT (_UART_TXDOUBLEX_RXENAT0_DEFAULT << 15) |
#define | _UART_TXDOUBLEX_TXDATA1_SHIFT 16 |
#define | _UART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL |
#define | _UART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXDATA1_DEFAULT (_UART_TXDOUBLEX_TXDATA1_DEFAULT << 16) |
#define | UART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) |
#define | _UART_TXDOUBLEX_UBRXAT1_SHIFT 27 |
#define | _UART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL |
#define | _UART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_UBRXAT1_DEFAULT (_UART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) |
#define | UART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) |
#define | _UART_TXDOUBLEX_TXTRIAT1_SHIFT 28 |
#define | _UART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL |
#define | _UART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXTRIAT1_DEFAULT (_UART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) |
#define | UART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) |
#define | _UART_TXDOUBLEX_TXBREAK1_SHIFT 29 |
#define | _UART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL |
#define | _UART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXBREAK1_DEFAULT (_UART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) |
#define | UART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) |
#define | _UART_TXDOUBLEX_TXDISAT1_SHIFT 30 |
#define | _UART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL |
#define | _UART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_TXDISAT1_DEFAULT (_UART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) |
#define | UART_TXDOUBLEX_RXENAT1 (0x1UL << 31) |
#define | _UART_TXDOUBLEX_RXENAT1_SHIFT 31 |
#define | _UART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL |
#define | _UART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLEX_RXENAT1_DEFAULT (_UART_TXDOUBLEX_RXENAT1_DEFAULT << 31) |
#define | _UART_TXDOUBLE_RESETVALUE 0x00000000UL |
#define | _UART_TXDOUBLE_MASK 0x0000FFFFUL |
#define | _UART_TXDOUBLE_TXDATA0_SHIFT 0 |
#define | _UART_TXDOUBLE_TXDATA0_MASK 0xFFUL |
#define | _UART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLE_TXDATA0_DEFAULT (_UART_TXDOUBLE_TXDATA0_DEFAULT << 0) |
#define | _UART_TXDOUBLE_TXDATA1_SHIFT 8 |
#define | _UART_TXDOUBLE_TXDATA1_MASK 0xFF00UL |
#define | _UART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL |
#define | UART_TXDOUBLE_TXDATA1_DEFAULT (_UART_TXDOUBLE_TXDATA1_DEFAULT << 8) |
#define | _UART_IF_RESETVALUE 0x00000002UL |
#define | _UART_IF_MASK 0x00001FFFUL |
#define | UART_IF_TXC (0x1UL << 0) |
#define | _UART_IF_TXC_SHIFT 0 |
#define | _UART_IF_TXC_MASK 0x1UL |
#define | _UART_IF_TXC_DEFAULT 0x00000000UL |
#define | UART_IF_TXC_DEFAULT (_UART_IF_TXC_DEFAULT << 0) |
#define | UART_IF_TXBL (0x1UL << 1) |
#define | _UART_IF_TXBL_SHIFT 1 |
#define | _UART_IF_TXBL_MASK 0x2UL |
#define | _UART_IF_TXBL_DEFAULT 0x00000001UL |
#define | UART_IF_TXBL_DEFAULT (_UART_IF_TXBL_DEFAULT << 1) |
#define | UART_IF_RXDATAV (0x1UL << 2) |
#define | _UART_IF_RXDATAV_SHIFT 2 |
#define | _UART_IF_RXDATAV_MASK 0x4UL |
#define | _UART_IF_RXDATAV_DEFAULT 0x00000000UL |
#define | UART_IF_RXDATAV_DEFAULT (_UART_IF_RXDATAV_DEFAULT << 2) |
#define | UART_IF_RXFULL (0x1UL << 3) |
#define | _UART_IF_RXFULL_SHIFT 3 |
#define | _UART_IF_RXFULL_MASK 0x8UL |
#define | _UART_IF_RXFULL_DEFAULT 0x00000000UL |
#define | UART_IF_RXFULL_DEFAULT (_UART_IF_RXFULL_DEFAULT << 3) |
#define | UART_IF_RXOF (0x1UL << 4) |
#define | _UART_IF_RXOF_SHIFT 4 |
#define | _UART_IF_RXOF_MASK 0x10UL |
#define | _UART_IF_RXOF_DEFAULT 0x00000000UL |
#define | UART_IF_RXOF_DEFAULT (_UART_IF_RXOF_DEFAULT << 4) |
#define | UART_IF_RXUF (0x1UL << 5) |
#define | _UART_IF_RXUF_SHIFT 5 |
#define | _UART_IF_RXUF_MASK 0x20UL |
#define | _UART_IF_RXUF_DEFAULT 0x00000000UL |
#define | UART_IF_RXUF_DEFAULT (_UART_IF_RXUF_DEFAULT << 5) |
#define | UART_IF_TXOF (0x1UL << 6) |
#define | _UART_IF_TXOF_SHIFT 6 |
#define | _UART_IF_TXOF_MASK 0x40UL |
#define | _UART_IF_TXOF_DEFAULT 0x00000000UL |
#define | UART_IF_TXOF_DEFAULT (_UART_IF_TXOF_DEFAULT << 6) |
#define | UART_IF_TXUF (0x1UL << 7) |
#define | _UART_IF_TXUF_SHIFT 7 |
#define | _UART_IF_TXUF_MASK 0x80UL |
#define | _UART_IF_TXUF_DEFAULT 0x00000000UL |
#define | UART_IF_TXUF_DEFAULT (_UART_IF_TXUF_DEFAULT << 7) |
#define | UART_IF_PERR (0x1UL << 8) |
#define | _UART_IF_PERR_SHIFT 8 |
#define | _UART_IF_PERR_MASK 0x100UL |
#define | _UART_IF_PERR_DEFAULT 0x00000000UL |
#define | UART_IF_PERR_DEFAULT (_UART_IF_PERR_DEFAULT << 8) |
#define | UART_IF_FERR (0x1UL << 9) |
#define | _UART_IF_FERR_SHIFT 9 |
#define | _UART_IF_FERR_MASK 0x200UL |
#define | _UART_IF_FERR_DEFAULT 0x00000000UL |
#define | UART_IF_FERR_DEFAULT (_UART_IF_FERR_DEFAULT << 9) |
#define | UART_IF_MPAF (0x1UL << 10) |
#define | _UART_IF_MPAF_SHIFT 10 |
#define | _UART_IF_MPAF_MASK 0x400UL |
#define | _UART_IF_MPAF_DEFAULT 0x00000000UL |
#define | UART_IF_MPAF_DEFAULT (_UART_IF_MPAF_DEFAULT << 10) |
#define | UART_IF_SSM (0x1UL << 11) |
#define | _UART_IF_SSM_SHIFT 11 |
#define | _UART_IF_SSM_MASK 0x800UL |
#define | _UART_IF_SSM_DEFAULT 0x00000000UL |
#define | UART_IF_SSM_DEFAULT (_UART_IF_SSM_DEFAULT << 11) |
#define | UART_IF_CCF (0x1UL << 12) |
#define | _UART_IF_CCF_SHIFT 12 |
#define | _UART_IF_CCF_MASK 0x1000UL |
#define | _UART_IF_CCF_DEFAULT 0x00000000UL |
#define | UART_IF_CCF_DEFAULT (_UART_IF_CCF_DEFAULT << 12) |
#define | _UART_IFS_RESETVALUE 0x00000000UL |
#define | _UART_IFS_MASK 0x00001FF9UL |
#define | UART_IFS_TXC (0x1UL << 0) |
#define | _UART_IFS_TXC_SHIFT 0 |
#define | _UART_IFS_TXC_MASK 0x1UL |
#define | _UART_IFS_TXC_DEFAULT 0x00000000UL |
#define | UART_IFS_TXC_DEFAULT (_UART_IFS_TXC_DEFAULT << 0) |
#define | UART_IFS_RXFULL (0x1UL << 3) |
#define | _UART_IFS_RXFULL_SHIFT 3 |
#define | _UART_IFS_RXFULL_MASK 0x8UL |
#define | _UART_IFS_RXFULL_DEFAULT 0x00000000UL |
#define | UART_IFS_RXFULL_DEFAULT (_UART_IFS_RXFULL_DEFAULT << 3) |
#define | UART_IFS_RXOF (0x1UL << 4) |
#define | _UART_IFS_RXOF_SHIFT 4 |
#define | _UART_IFS_RXOF_MASK 0x10UL |
#define | _UART_IFS_RXOF_DEFAULT 0x00000000UL |
#define | UART_IFS_RXOF_DEFAULT (_UART_IFS_RXOF_DEFAULT << 4) |
#define | UART_IFS_RXUF (0x1UL << 5) |
#define | _UART_IFS_RXUF_SHIFT 5 |
#define | _UART_IFS_RXUF_MASK 0x20UL |
#define | _UART_IFS_RXUF_DEFAULT 0x00000000UL |
#define | UART_IFS_RXUF_DEFAULT (_UART_IFS_RXUF_DEFAULT << 5) |
#define | UART_IFS_TXOF (0x1UL << 6) |
#define | _UART_IFS_TXOF_SHIFT 6 |
#define | _UART_IFS_TXOF_MASK 0x40UL |
#define | _UART_IFS_TXOF_DEFAULT 0x00000000UL |
#define | UART_IFS_TXOF_DEFAULT (_UART_IFS_TXOF_DEFAULT << 6) |
#define | UART_IFS_TXUF (0x1UL << 7) |
#define | _UART_IFS_TXUF_SHIFT 7 |
#define | _UART_IFS_TXUF_MASK 0x80UL |
#define | _UART_IFS_TXUF_DEFAULT 0x00000000UL |
#define | UART_IFS_TXUF_DEFAULT (_UART_IFS_TXUF_DEFAULT << 7) |
#define | UART_IFS_PERR (0x1UL << 8) |
#define | _UART_IFS_PERR_SHIFT 8 |
#define | _UART_IFS_PERR_MASK 0x100UL |
#define | _UART_IFS_PERR_DEFAULT 0x00000000UL |
#define | UART_IFS_PERR_DEFAULT (_UART_IFS_PERR_DEFAULT << 8) |
#define | UART_IFS_FERR (0x1UL << 9) |
#define | _UART_IFS_FERR_SHIFT 9 |
#define | _UART_IFS_FERR_MASK 0x200UL |
#define | _UART_IFS_FERR_DEFAULT 0x00000000UL |
#define | UART_IFS_FERR_DEFAULT (_UART_IFS_FERR_DEFAULT << 9) |
#define | UART_IFS_MPAF (0x1UL << 10) |
#define | _UART_IFS_MPAF_SHIFT 10 |
#define | _UART_IFS_MPAF_MASK 0x400UL |
#define | _UART_IFS_MPAF_DEFAULT 0x00000000UL |
#define | UART_IFS_MPAF_DEFAULT (_UART_IFS_MPAF_DEFAULT << 10) |
#define | UART_IFS_SSM (0x1UL << 11) |
#define | _UART_IFS_SSM_SHIFT 11 |
#define | _UART_IFS_SSM_MASK 0x800UL |
#define | _UART_IFS_SSM_DEFAULT 0x00000000UL |
#define | UART_IFS_SSM_DEFAULT (_UART_IFS_SSM_DEFAULT << 11) |
#define | UART_IFS_CCF (0x1UL << 12) |
#define | _UART_IFS_CCF_SHIFT 12 |
#define | _UART_IFS_CCF_MASK 0x1000UL |
#define | _UART_IFS_CCF_DEFAULT 0x00000000UL |
#define | UART_IFS_CCF_DEFAULT (_UART_IFS_CCF_DEFAULT << 12) |
#define | _UART_IFC_RESETVALUE 0x00000000UL |
#define | _UART_IFC_MASK 0x00001FF9UL |
#define | UART_IFC_TXC (0x1UL << 0) |
#define | _UART_IFC_TXC_SHIFT 0 |
#define | _UART_IFC_TXC_MASK 0x1UL |
#define | _UART_IFC_TXC_DEFAULT 0x00000000UL |
#define | UART_IFC_TXC_DEFAULT (_UART_IFC_TXC_DEFAULT << 0) |
#define | UART_IFC_RXFULL (0x1UL << 3) |
#define | _UART_IFC_RXFULL_SHIFT 3 |
#define | _UART_IFC_RXFULL_MASK 0x8UL |
#define | _UART_IFC_RXFULL_DEFAULT 0x00000000UL |
#define | UART_IFC_RXFULL_DEFAULT (_UART_IFC_RXFULL_DEFAULT << 3) |
#define | UART_IFC_RXOF (0x1UL << 4) |
#define | _UART_IFC_RXOF_SHIFT 4 |
#define | _UART_IFC_RXOF_MASK 0x10UL |
#define | _UART_IFC_RXOF_DEFAULT 0x00000000UL |
#define | UART_IFC_RXOF_DEFAULT (_UART_IFC_RXOF_DEFAULT << 4) |
#define | UART_IFC_RXUF (0x1UL << 5) |
#define | _UART_IFC_RXUF_SHIFT 5 |
#define | _UART_IFC_RXUF_MASK 0x20UL |
#define | _UART_IFC_RXUF_DEFAULT 0x00000000UL |
#define | UART_IFC_RXUF_DEFAULT (_UART_IFC_RXUF_DEFAULT << 5) |
#define | UART_IFC_TXOF (0x1UL << 6) |
#define | _UART_IFC_TXOF_SHIFT 6 |
#define | _UART_IFC_TXOF_MASK 0x40UL |
#define | _UART_IFC_TXOF_DEFAULT 0x00000000UL |
#define | UART_IFC_TXOF_DEFAULT (_UART_IFC_TXOF_DEFAULT << 6) |
#define | UART_IFC_TXUF (0x1UL << 7) |
#define | _UART_IFC_TXUF_SHIFT 7 |
#define | _UART_IFC_TXUF_MASK 0x80UL |
#define | _UART_IFC_TXUF_DEFAULT 0x00000000UL |
#define | UART_IFC_TXUF_DEFAULT (_UART_IFC_TXUF_DEFAULT << 7) |
#define | UART_IFC_PERR (0x1UL << 8) |
#define | _UART_IFC_PERR_SHIFT 8 |
#define | _UART_IFC_PERR_MASK 0x100UL |
#define | _UART_IFC_PERR_DEFAULT 0x00000000UL |
#define | UART_IFC_PERR_DEFAULT (_UART_IFC_PERR_DEFAULT << 8) |
#define | UART_IFC_FERR (0x1UL << 9) |
#define | _UART_IFC_FERR_SHIFT 9 |
#define | _UART_IFC_FERR_MASK 0x200UL |
#define | _UART_IFC_FERR_DEFAULT 0x00000000UL |
#define | UART_IFC_FERR_DEFAULT (_UART_IFC_FERR_DEFAULT << 9) |
#define | UART_IFC_MPAF (0x1UL << 10) |
#define | _UART_IFC_MPAF_SHIFT 10 |
#define | _UART_IFC_MPAF_MASK 0x400UL |
#define | _UART_IFC_MPAF_DEFAULT 0x00000000UL |
#define | UART_IFC_MPAF_DEFAULT (_UART_IFC_MPAF_DEFAULT << 10) |
#define | UART_IFC_SSM (0x1UL << 11) |
#define | _UART_IFC_SSM_SHIFT 11 |
#define | _UART_IFC_SSM_MASK 0x800UL |
#define | _UART_IFC_SSM_DEFAULT 0x00000000UL |
#define | UART_IFC_SSM_DEFAULT (_UART_IFC_SSM_DEFAULT << 11) |
#define | UART_IFC_CCF (0x1UL << 12) |
#define | _UART_IFC_CCF_SHIFT 12 |
#define | _UART_IFC_CCF_MASK 0x1000UL |
#define | _UART_IFC_CCF_DEFAULT 0x00000000UL |
#define | UART_IFC_CCF_DEFAULT (_UART_IFC_CCF_DEFAULT << 12) |
#define | _UART_IEN_RESETVALUE 0x00000000UL |
#define | _UART_IEN_MASK 0x00001FFFUL |
#define | UART_IEN_TXC (0x1UL << 0) |
#define | _UART_IEN_TXC_SHIFT 0 |
#define | _UART_IEN_TXC_MASK 0x1UL |
#define | _UART_IEN_TXC_DEFAULT 0x00000000UL |
#define | UART_IEN_TXC_DEFAULT (_UART_IEN_TXC_DEFAULT << 0) |
#define | UART_IEN_TXBL (0x1UL << 1) |
#define | _UART_IEN_TXBL_SHIFT 1 |
#define | _UART_IEN_TXBL_MASK 0x2UL |
#define | _UART_IEN_TXBL_DEFAULT 0x00000000UL |
#define | UART_IEN_TXBL_DEFAULT (_UART_IEN_TXBL_DEFAULT << 1) |
#define | UART_IEN_RXDATAV (0x1UL << 2) |
#define | _UART_IEN_RXDATAV_SHIFT 2 |
#define | _UART_IEN_RXDATAV_MASK 0x4UL |
#define | _UART_IEN_RXDATAV_DEFAULT 0x00000000UL |
#define | UART_IEN_RXDATAV_DEFAULT (_UART_IEN_RXDATAV_DEFAULT << 2) |
#define | UART_IEN_RXFULL (0x1UL << 3) |
#define | _UART_IEN_RXFULL_SHIFT 3 |
#define | _UART_IEN_RXFULL_MASK 0x8UL |
#define | _UART_IEN_RXFULL_DEFAULT 0x00000000UL |
#define | UART_IEN_RXFULL_DEFAULT (_UART_IEN_RXFULL_DEFAULT << 3) |
#define | UART_IEN_RXOF (0x1UL << 4) |
#define | _UART_IEN_RXOF_SHIFT 4 |
#define | _UART_IEN_RXOF_MASK 0x10UL |
#define | _UART_IEN_RXOF_DEFAULT 0x00000000UL |
#define | UART_IEN_RXOF_DEFAULT (_UART_IEN_RXOF_DEFAULT << 4) |
#define | UART_IEN_RXUF (0x1UL << 5) |
#define | _UART_IEN_RXUF_SHIFT 5 |
#define | _UART_IEN_RXUF_MASK 0x20UL |
#define | _UART_IEN_RXUF_DEFAULT 0x00000000UL |
#define | UART_IEN_RXUF_DEFAULT (_UART_IEN_RXUF_DEFAULT << 5) |
#define | UART_IEN_TXOF (0x1UL << 6) |
#define | _UART_IEN_TXOF_SHIFT 6 |
#define | _UART_IEN_TXOF_MASK 0x40UL |
#define | _UART_IEN_TXOF_DEFAULT 0x00000000UL |
#define | UART_IEN_TXOF_DEFAULT (_UART_IEN_TXOF_DEFAULT << 6) |
#define | UART_IEN_TXUF (0x1UL << 7) |
#define | _UART_IEN_TXUF_SHIFT 7 |
#define | _UART_IEN_TXUF_MASK 0x80UL |
#define | _UART_IEN_TXUF_DEFAULT 0x00000000UL |
#define | UART_IEN_TXUF_DEFAULT (_UART_IEN_TXUF_DEFAULT << 7) |
#define | UART_IEN_PERR (0x1UL << 8) |
#define | _UART_IEN_PERR_SHIFT 8 |
#define | _UART_IEN_PERR_MASK 0x100UL |
#define | _UART_IEN_PERR_DEFAULT 0x00000000UL |
#define | UART_IEN_PERR_DEFAULT (_UART_IEN_PERR_DEFAULT << 8) |
#define | UART_IEN_FERR (0x1UL << 9) |
#define | _UART_IEN_FERR_SHIFT 9 |
#define | _UART_IEN_FERR_MASK 0x200UL |
#define | _UART_IEN_FERR_DEFAULT 0x00000000UL |
#define | UART_IEN_FERR_DEFAULT (_UART_IEN_FERR_DEFAULT << 9) |
#define | UART_IEN_MPAF (0x1UL << 10) |
#define | _UART_IEN_MPAF_SHIFT 10 |
#define | _UART_IEN_MPAF_MASK 0x400UL |
#define | _UART_IEN_MPAF_DEFAULT 0x00000000UL |
#define | UART_IEN_MPAF_DEFAULT (_UART_IEN_MPAF_DEFAULT << 10) |
#define | UART_IEN_SSM (0x1UL << 11) |
#define | _UART_IEN_SSM_SHIFT 11 |
#define | _UART_IEN_SSM_MASK 0x800UL |
#define | _UART_IEN_SSM_DEFAULT 0x00000000UL |
#define | UART_IEN_SSM_DEFAULT (_UART_IEN_SSM_DEFAULT << 11) |
#define | UART_IEN_CCF (0x1UL << 12) |
#define | _UART_IEN_CCF_SHIFT 12 |
#define | _UART_IEN_CCF_MASK 0x1000UL |
#define | _UART_IEN_CCF_DEFAULT 0x00000000UL |
#define | UART_IEN_CCF_DEFAULT (_UART_IEN_CCF_DEFAULT << 12) |
#define | _UART_IRCTRL_RESETVALUE 0x00000000UL |
#define | _UART_IRCTRL_MASK 0x000000FFUL |
#define | UART_IRCTRL_IREN (0x1UL << 0) |
#define | _UART_IRCTRL_IREN_SHIFT 0 |
#define | _UART_IRCTRL_IREN_MASK 0x1UL |
#define | _UART_IRCTRL_IREN_DEFAULT 0x00000000UL |
#define | UART_IRCTRL_IREN_DEFAULT (_UART_IRCTRL_IREN_DEFAULT << 0) |
#define | _UART_IRCTRL_IRPW_SHIFT 1 |
#define | _UART_IRCTRL_IRPW_MASK 0x6UL |
#define | _UART_IRCTRL_IRPW_DEFAULT 0x00000000UL |
#define | _UART_IRCTRL_IRPW_ONE 0x00000000UL |
#define | _UART_IRCTRL_IRPW_TWO 0x00000001UL |
#define | _UART_IRCTRL_IRPW_THREE 0x00000002UL |
#define | _UART_IRCTRL_IRPW_FOUR 0x00000003UL |
#define | UART_IRCTRL_IRPW_DEFAULT (_UART_IRCTRL_IRPW_DEFAULT << 1) |
#define | UART_IRCTRL_IRPW_ONE (_UART_IRCTRL_IRPW_ONE << 1) |
#define | UART_IRCTRL_IRPW_TWO (_UART_IRCTRL_IRPW_TWO << 1) |
#define | UART_IRCTRL_IRPW_THREE (_UART_IRCTRL_IRPW_THREE << 1) |
#define | UART_IRCTRL_IRPW_FOUR (_UART_IRCTRL_IRPW_FOUR << 1) |
#define | UART_IRCTRL_IRFILT (0x1UL << 3) |
#define | _UART_IRCTRL_IRFILT_SHIFT 3 |
#define | _UART_IRCTRL_IRFILT_MASK 0x8UL |
#define | _UART_IRCTRL_IRFILT_DEFAULT 0x00000000UL |
#define | UART_IRCTRL_IRFILT_DEFAULT (_UART_IRCTRL_IRFILT_DEFAULT << 3) |
#define | _UART_IRCTRL_IRPRSSEL_SHIFT 4 |
#define | _UART_IRCTRL_IRPRSSEL_MASK 0x70UL |
#define | _UART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL |
#define | _UART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL |
#define | UART_IRCTRL_IRPRSSEL_DEFAULT (_UART_IRCTRL_IRPRSSEL_DEFAULT << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH0 (_UART_IRCTRL_IRPRSSEL_PRSCH0 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH1 (_UART_IRCTRL_IRPRSSEL_PRSCH1 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH2 (_UART_IRCTRL_IRPRSSEL_PRSCH2 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH3 (_UART_IRCTRL_IRPRSSEL_PRSCH3 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH4 (_UART_IRCTRL_IRPRSSEL_PRSCH4 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH5 (_UART_IRCTRL_IRPRSSEL_PRSCH5 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH6 (_UART_IRCTRL_IRPRSSEL_PRSCH6 << 4) |
#define | UART_IRCTRL_IRPRSSEL_PRSCH7 (_UART_IRCTRL_IRPRSSEL_PRSCH7 << 4) |
#define | UART_IRCTRL_IRPRSEN (0x1UL << 7) |
#define | _UART_IRCTRL_IRPRSEN_SHIFT 7 |
#define | _UART_IRCTRL_IRPRSEN_MASK 0x80UL |
#define | _UART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL |
#define | UART_IRCTRL_IRPRSEN_DEFAULT (_UART_IRCTRL_IRPRSEN_DEFAULT << 7) |
#define | _UART_ROUTE_RESETVALUE 0x00000000UL |
#define | _UART_ROUTE_MASK 0x0000070FUL |
#define | UART_ROUTE_RXPEN (0x1UL << 0) |
#define | _UART_ROUTE_RXPEN_SHIFT 0 |
#define | _UART_ROUTE_RXPEN_MASK 0x1UL |
#define | _UART_ROUTE_RXPEN_DEFAULT 0x00000000UL |
#define | UART_ROUTE_RXPEN_DEFAULT (_UART_ROUTE_RXPEN_DEFAULT << 0) |
#define | UART_ROUTE_TXPEN (0x1UL << 1) |
#define | _UART_ROUTE_TXPEN_SHIFT 1 |
#define | _UART_ROUTE_TXPEN_MASK 0x2UL |
#define | _UART_ROUTE_TXPEN_DEFAULT 0x00000000UL |
#define | UART_ROUTE_TXPEN_DEFAULT (_UART_ROUTE_TXPEN_DEFAULT << 1) |
#define | UART_ROUTE_CSPEN (0x1UL << 2) |
#define | _UART_ROUTE_CSPEN_SHIFT 2 |
#define | _UART_ROUTE_CSPEN_MASK 0x4UL |
#define | _UART_ROUTE_CSPEN_DEFAULT 0x00000000UL |
#define | UART_ROUTE_CSPEN_DEFAULT (_UART_ROUTE_CSPEN_DEFAULT << 2) |
#define | UART_ROUTE_CLKPEN (0x1UL << 3) |
#define | _UART_ROUTE_CLKPEN_SHIFT 3 |
#define | _UART_ROUTE_CLKPEN_MASK 0x8UL |
#define | _UART_ROUTE_CLKPEN_DEFAULT 0x00000000UL |
#define | UART_ROUTE_CLKPEN_DEFAULT (_UART_ROUTE_CLKPEN_DEFAULT << 3) |
#define | _UART_ROUTE_LOCATION_SHIFT 8 |
#define | _UART_ROUTE_LOCATION_MASK 0x700UL |
#define | _UART_ROUTE_LOCATION_LOC0 0x00000000UL |
#define | _UART_ROUTE_LOCATION_DEFAULT 0x00000000UL |
#define | _UART_ROUTE_LOCATION_LOC1 0x00000001UL |
#define | _UART_ROUTE_LOCATION_LOC2 0x00000002UL |
#define | _UART_ROUTE_LOCATION_LOC3 0x00000003UL |
#define | _UART_ROUTE_LOCATION_LOC4 0x00000004UL |
#define | _UART_ROUTE_LOCATION_LOC5 0x00000005UL |
#define | UART_ROUTE_LOCATION_LOC0 (_UART_ROUTE_LOCATION_LOC0 << 8) |
#define | UART_ROUTE_LOCATION_DEFAULT (_UART_ROUTE_LOCATION_DEFAULT << 8) |
#define | UART_ROUTE_LOCATION_LOC1 (_UART_ROUTE_LOCATION_LOC1 << 8) |
#define | UART_ROUTE_LOCATION_LOC2 (_UART_ROUTE_LOCATION_LOC2 << 8) |
#define | UART_ROUTE_LOCATION_LOC3 (_UART_ROUTE_LOCATION_LOC3 << 8) |
#define | UART_ROUTE_LOCATION_LOC4 (_UART_ROUTE_LOCATION_LOC4 << 8) |
#define | UART_ROUTE_LOCATION_LOC5 (_UART_ROUTE_LOCATION_LOC5 << 8) |
#define | _UART_INPUT_RESETVALUE 0x00000000UL |
#define | _UART_INPUT_MASK 0x0000001FUL |
#define | _UART_INPUT_RXPRSSEL_SHIFT 0 |
#define | _UART_INPUT_RXPRSSEL_MASK 0xFUL |
#define | _UART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL |
#define | _UART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL |
#define | _UART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL |
#define | UART_INPUT_RXPRSSEL_DEFAULT (_UART_INPUT_RXPRSSEL_DEFAULT << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH0 (_UART_INPUT_RXPRSSEL_PRSCH0 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH1 (_UART_INPUT_RXPRSSEL_PRSCH1 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH2 (_UART_INPUT_RXPRSSEL_PRSCH2 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH3 (_UART_INPUT_RXPRSSEL_PRSCH3 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH4 (_UART_INPUT_RXPRSSEL_PRSCH4 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH5 (_UART_INPUT_RXPRSSEL_PRSCH5 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH6 (_UART_INPUT_RXPRSSEL_PRSCH6 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH7 (_UART_INPUT_RXPRSSEL_PRSCH7 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH8 (_UART_INPUT_RXPRSSEL_PRSCH8 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH9 (_UART_INPUT_RXPRSSEL_PRSCH9 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH10 (_UART_INPUT_RXPRSSEL_PRSCH10 << 0) |
#define | UART_INPUT_RXPRSSEL_PRSCH11 (_UART_INPUT_RXPRSSEL_PRSCH11 << 0) |
#define | UART_INPUT_RXPRS (0x1UL << 4) |
#define | _UART_INPUT_RXPRS_SHIFT 4 |
#define | _UART_INPUT_RXPRS_MASK 0x10UL |
#define | _UART_INPUT_RXPRS_DEFAULT 0x00000000UL |
#define | UART_INPUT_RXPRS_DEFAULT (_UART_INPUT_RXPRS_DEFAULT << 4) |
#define | _UART_I2SCTRL_RESETVALUE 0x00000000UL |
#define | _UART_I2SCTRL_MASK 0x0000071FUL |
#define | UART_I2SCTRL_EN (0x1UL << 0) |
#define | _UART_I2SCTRL_EN_SHIFT 0 |
#define | _UART_I2SCTRL_EN_MASK 0x1UL |
#define | _UART_I2SCTRL_EN_DEFAULT 0x00000000UL |
#define | UART_I2SCTRL_EN_DEFAULT (_UART_I2SCTRL_EN_DEFAULT << 0) |
#define | UART_I2SCTRL_MONO (0x1UL << 1) |
#define | _UART_I2SCTRL_MONO_SHIFT 1 |
#define | _UART_I2SCTRL_MONO_MASK 0x2UL |
#define | _UART_I2SCTRL_MONO_DEFAULT 0x00000000UL |
#define | UART_I2SCTRL_MONO_DEFAULT (_UART_I2SCTRL_MONO_DEFAULT << 1) |
#define | UART_I2SCTRL_JUSTIFY (0x1UL << 2) |
#define | _UART_I2SCTRL_JUSTIFY_SHIFT 2 |
#define | _UART_I2SCTRL_JUSTIFY_MASK 0x4UL |
#define | _UART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL |
#define | _UART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL |
#define | _UART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL |
#define | UART_I2SCTRL_JUSTIFY_DEFAULT (_UART_I2SCTRL_JUSTIFY_DEFAULT << 2) |
#define | UART_I2SCTRL_JUSTIFY_LEFT (_UART_I2SCTRL_JUSTIFY_LEFT << 2) |
#define | UART_I2SCTRL_JUSTIFY_RIGHT (_UART_I2SCTRL_JUSTIFY_RIGHT << 2) |
#define | UART_I2SCTRL_DMASPLIT (0x1UL << 3) |
#define | _UART_I2SCTRL_DMASPLIT_SHIFT 3 |
#define | _UART_I2SCTRL_DMASPLIT_MASK 0x8UL |
#define | _UART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL |
#define | UART_I2SCTRL_DMASPLIT_DEFAULT (_UART_I2SCTRL_DMASPLIT_DEFAULT << 3) |
#define | UART_I2SCTRL_DELAY (0x1UL << 4) |
#define | _UART_I2SCTRL_DELAY_SHIFT 4 |
#define | _UART_I2SCTRL_DELAY_MASK 0x10UL |
#define | _UART_I2SCTRL_DELAY_DEFAULT 0x00000000UL |
#define | UART_I2SCTRL_DELAY_DEFAULT (_UART_I2SCTRL_DELAY_DEFAULT << 4) |
#define | _UART_I2SCTRL_FORMAT_SHIFT 8 |
#define | _UART_I2SCTRL_FORMAT_MASK 0x700UL |
#define | _UART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL |
#define | _UART_I2SCTRL_FORMAT_W32D32 0x00000000UL |
#define | _UART_I2SCTRL_FORMAT_W32D24M 0x00000001UL |
#define | _UART_I2SCTRL_FORMAT_W32D24 0x00000002UL |
#define | _UART_I2SCTRL_FORMAT_W32D16 0x00000003UL |
#define | _UART_I2SCTRL_FORMAT_W32D8 0x00000004UL |
#define | _UART_I2SCTRL_FORMAT_W16D16 0x00000005UL |
#define | _UART_I2SCTRL_FORMAT_W16D8 0x00000006UL |
#define | _UART_I2SCTRL_FORMAT_W8D8 0x00000007UL |
#define | UART_I2SCTRL_FORMAT_DEFAULT (_UART_I2SCTRL_FORMAT_DEFAULT << 8) |
#define | UART_I2SCTRL_FORMAT_W32D32 (_UART_I2SCTRL_FORMAT_W32D32 << 8) |
#define | UART_I2SCTRL_FORMAT_W32D24M (_UART_I2SCTRL_FORMAT_W32D24M << 8) |
#define | UART_I2SCTRL_FORMAT_W32D24 (_UART_I2SCTRL_FORMAT_W32D24 << 8) |
#define | UART_I2SCTRL_FORMAT_W32D16 (_UART_I2SCTRL_FORMAT_W32D16 << 8) |
#define | UART_I2SCTRL_FORMAT_W32D8 (_UART_I2SCTRL_FORMAT_W32D8 << 8) |
#define | UART_I2SCTRL_FORMAT_W16D16 (_UART_I2SCTRL_FORMAT_W16D16 << 8) |
#define | UART_I2SCTRL_FORMAT_W16D8 (_UART_I2SCTRL_FORMAT_W16D8 << 8) |
#define | UART_I2SCTRL_FORMAT_W8D8 (_UART_I2SCTRL_FORMAT_W8D8 << 8) |
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file efm32gg_uart.h.