ksz8851snl.h

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00001 /***************************************************************************/
00017 #ifndef _ksz8851snl_H_
00018 #define _ksz8851snl_H_
00019 
00020 /**************************************************************************/
00025 /**************************************************************************/
00034 #include <stdint.h>
00035 #include <stdbool.h>
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00042 #define KSZ8851SNL_DEBUG    0
00043 #if KSZ8851SNL_DEBUG
00044 
00045 #define DEBUG_PRINT(...)    printf(__VA_ARGS__)
00046 #define DIGITAL_PHY_LOOPBACK
00047 #define DUMP_REGS
00048 #else
00049 
00050 #define DEBUG_PRINT(...)    (void)0
00051 #endif /* KSZ8851SNL_DEBUG */
00052 
00053 /* Register definitions */
00054 #define LOW_QMU_MAC_REG             0x10 
00055 #define MID_QMU_MAC_REG             0x12 
00056 #define HIGH_QMU_MAC_REG            0x14 
00057 #define OBC_REG                     0x20 
00058 #define GLOBAL_RESET_REG            0x26 
00059 #define TX_FLOW_CTRL_REG            0x70 
00060 #define RX_FLOW_CTRL1_REG           0x74 
00061 #define RX_FLOW_CTRL2_REG           0x76 
00062 #define TX_MEM_INFO_REG             0x78 
00063 #define RX_FRH_STAT_REG             0x7C 
00064 #define RX_FRH_BC_REG               0x7E 
00065 #define TXQ_CMD_REG                 0x80 
00066 #define RXQ_CMD_REG                 0x82 
00067 #define TX_FD_PTR_REG               0x84 
00068 #define RX_FD_PTR_REG               0x86 
00069 #define INT_ENABLE_REG              0x90 
00070 #define INT_STATUS_REG              0x92 
00071 #define RX_FRAME_THRES_REG          0x9C 
00072 #define TX_NEXT_FRS_REG             0x9E 
00073 #define FLOW_CTRL_LOW_WATERMARK     0xB0 
00074 #define FLOW_CTRL_HIGH_WATERMARK    0xB2 
00075 #define CIDER_REG                   0xC0 
00076 #define IND_ACC_CTRL_REG            0xC8 
00077 #define IND_ACC_DATA_LOW_REG        0xD0 
00078 #define IND_ACC_DATA_HIGH_REG       0xD2 
00079 #define PHY_RST_REG                 0xD8 
00080 #define PHY1_CTRL_REG               0xE4 
00081 #define PORT1_CTRL_REG              0xF6 
00083 /* Magic numbers */
00084 #define KSZ8851SNL_CHIP_ID          0x8870 
00085 #define CHIP_ID_MASK                0xFFF0 
00086 #define ONE_FRAME_THRES             0x0001 
00087 #define FD_PTR_AUTO_INC             0x4000 
00088 #define CLEAR_INT                   0xFFFF 
00089 #define NO_INT                      0x0000 
00090 #define TX_MEM_AVAIL_MASK           0x1FFF 
00091 #define frameId_MASK                0x003F 
00092 #define RECEIVE_VALID_FRAME_MASK    0x3C17 
00095 #define RECEIVED_FRAME_VALID_POS    0x0010 
00096 #define RX_BYTE_CNT_MASK            0x0FFF 
00097 #define LSB_MASK                    0x00FF 
00098 #define MSB_POS                     0x0008 
00099 #define TX_INT_on_COMPLETION        0x8000 
00100 #define WORD_SIZE                   0x0004 
00101 #define EXTRA_SIZE                  0x0008 
00102 #define BLOCKING_RECEIVE            0      
00103 #define WATERMARK_6KB               0x0600 
00104 #define WATERMARK_4KB               0x0400 
00105 /* Energy Micro's MAC address space */
00106 #define HIGH_QMU_MAC_H              0xD0   
00107 #define HIGH_QMU_MAC_L              0xCF   
00108 #define MID_QMU_MAC_H               0x5E   
00109 #define MID_QMU_MAC_L               0x00   
00110 #define LOW_QMU_MAC_H               0x00   
00111 #define LOW_QMU_MAC_L               0x00   
00112 #define BYTE_MASK                   0x00FF 
00113 #define BYTE_SIZE                   0x0008 
00115 /* TX Flow Control Register Options */
00116 
00118 #define   TX_FLOW_CTRL_ICMP_CHECKSUM    0x0100
00119 
00120 #define   TX_FLOW_CTRL_UDP_CHECKSUM     0x0080
00121 
00122 #define   TX_FLOW_CTRL_TCP_CHECKSUM     0x0040
00123 
00124 #define   TX_FLOW_CTRL_IP_CHECKSUM      0x0020
00125 
00126 #define   TX_FLOW_CTRL_FLUSH_QUEUE      0x0010
00127 
00128 #define   TX_FLOW_CTRL_FLOW_ENABLE      0x0008
00129 
00130 #define   TX_FLOW_CTRL_PAD_ENABLE       0x0004
00131 
00132 #define   TX_FLOW_CTRL_CRC_ENABLE       0x0002
00133 
00134 #define   TX_FLOW_CTRL_ENABLE           0x0001
00135 
00137 #define   TX_FLOW_CTRL_EXAMPLE          (TX_FLOW_CTRL_ICMP_CHECKSUM | \
00138                                          TX_FLOW_CTRL_UDP_CHECKSUM |  \
00139                                          TX_FLOW_CTRL_TCP_CHECKSUM |  \
00140                                          TX_FLOW_CTRL_IP_CHECKSUM |   \
00141                                          TX_FLOW_CTRL_FLOW_ENABLE |   \
00142                                          TX_FLOW_CTRL_PAD_ENABLE |    \
00143                                          TX_FLOW_CTRL_CRC_ENABLE)
00144 
00145 /* TXQ Command Register Options */
00147 #define   TXQ_AUTO_ENQUEUE         0x0004
00148 
00149 #define   TXQ_MEM_AVAILABLE_INT    0x0002
00150 
00151 #define   TXQ_ENQUEUE              0x0001
00152 
00153 
00154 /* RX Flow Control Register 1 Options */
00156 #define   RX_FLOW_CTRL_FLUSH_QUEUE       0x8000
00157 
00158 #define   RX_FLOW_CTRL_UDP_CHECKSUM      0x4000
00159 
00160 #define   RX_FLOW_CTRL_TCP_CHECKSUM      0x2000
00161 
00162 #define   RX_FLOW_CTRL_IP_CHECKSUM       0x1000
00163 
00164 #define   RX_FLOW_CTRL_MAC_FILTER        0x0800
00165 
00166 #define   RX_FLOW_CTRL_FLOW_ENABLE       0x0400
00167 
00168 #define   RX_FLOW_CTRL_BAD_PACKET        0x0200
00169 
00170 #define   RX_FLOW_CTRL_MULTICAST         0x0100
00171 
00172 #define   RX_FLOW_CTRL_BROADCAST         0x0080
00173 
00174 #define   RX_FLOW_CTRL_ALL_MULTICAST     0x0040
00175 
00176 #define   RX_FLOW_CTRL_UNICAST           0x0020
00177 
00178 #define   RX_FLOW_CTRL_PROMISCUOUS       0x0012
00179 
00180 #define   RX_FLOW_CTRL_INVERSE_FILTER    0x0002
00181 
00182 #define   RX_FLOW_CTRL_ENABLE            0x0001
00183 
00185 #define   RX_FLOW_CTRL1_EXAMPLE          (RX_FLOW_CTRL_UDP_CHECKSUM |  \
00186                                           RX_FLOW_CTRL_TCP_CHECKSUM |  \
00187                                           RX_FLOW_CTRL_IP_CHECKSUM |   \
00188                                           RX_FLOW_CTRL_MAC_FILTER |    \
00189                                           RX_FLOW_CTRL_FLOW_ENABLE |   \
00190                                           RX_FLOW_CTRL_BROADCAST |     \
00191                                           RX_FLOW_CTRL_ALL_MULTICAST | \
00192                                           RX_FLOW_CTRL_UNICAST)
00193 
00194 /* RX Flow Control Register 2 Options */
00195 /* SPI Receive Data Burst Length */
00197 #define   RX_FLOW_CTRL_BURST_LEN_MASK        0x00E0
00198 
00199 #define   RX_FLOW_CTRL_BURST_LEN_4           0x0000
00200 
00201 #define   RX_FLOW_CTRL_BURST_LEN_8           0x0020
00202 
00203 #define   RX_FLOW_CTRL_BURST_LEN_16          0x0040
00204 
00205 #define   RX_FLOW_CTRL_BURST_LEN_32          0x0060
00206 
00207 #define   RX_FLOW_CTRL_BURST_LEN_FRAME       0x0080
00208 
00209 #define   RX_FLOW_CTRL_IPV6_UDP_FRAG_PASS    0x0010
00210 
00211 #define   RX_FLOW_CTRL_IPV6_UDP_ZERO_PASS    0x0008
00212 
00213 #define   RX_FLOW_CTRL_UDP_LITE_CHECKSUM     0x0004
00214 
00215 #define   RX_FLOW_CTRL_ICMP_CHECKSUM         0x0002
00216 
00217 #define   RX_FLOW_CTRL_BLOCK_MAC             0x0001
00218 
00220 #define   RX_FLOW_CTRL2_EXAMPLE              (RX_FLOW_CTRL_IPV6_UDP_FRAG_PASS | \
00221                                               RX_FLOW_CTRL_UDP_LITE_CHECKSUM |  \
00222                                               RX_FLOW_CTRL_ICMP_CHECKSUM |      \
00223                                               RX_FLOW_CTRL_BURST_LEN_FRAME)
00224 
00225 /* RXQ Command Register Options */
00227 #define   RXQ_ON_TIME_INT            0x1000
00228 
00229 #define   RXQ_ON_BYTE_CNT_INT        0x0800
00230 
00231 #define   RXQ_ON_FRAME_CNT_INT       0x0400
00232 
00233 #define   RXQ_TWOBYTE_OFFSET         0x0200
00234 
00235 #define   RXQ_EN_ON_TIME_INT         0x0080
00236 
00237 #define   RXQ_EN_ON_BYTE_CNT_INT     0x0040
00238 
00239 #define   RXQ_EN_ON_FRAME_CNT_INT    0x0020
00240 
00241 #define   RXQ_AUTO_DEQUEUE           0x0010
00242 
00243 #define   RXQ_START                  0x0008
00244 
00245 #define   RXQ_RELEASE_CUR_FR         0x0001
00246 
00248 #define   RXQ_CMD_EXAMPLE            (RXQ_EN_ON_FRAME_CNT_INT | \
00249                                       RXQ_TWOBYTE_OFFSET |      \
00250                                       RXQ_AUTO_DEQUEUE)
00251 
00252 /* Port 1 Control Register Options */
00254 #define   PORT1_LED_OFF               0x8000
00255 
00256 #define   PORT1_TX_DISABLE            0x4000
00257 
00258 #define   PORT1_AUTO_NEG_RESTART      0x2000
00259 
00260 #define   PORT1_POWER_DOWN            0x0800
00261 
00262 #define   PORT1_AUTO_MDIX_DISABLE     0x0400
00263 
00264 #define   PORT1_FORCE_MDIX            0x0200
00265 
00266 #define   PORT1_AUTO_NEG_ENABLE       0x0080
00267 
00268 #define   PORT1_FORCE_100_MBIT        0x0040
00269 
00270 #define   PORT1_FORCE_FULL_DUPLEX     0x0020
00271 
00272 #define   PORT1_AUTO_NEG_SYM_PAUSE    0x0010
00273 
00274 #define   PORT1_AUTO_NEG_100BTX_FD    0x0008
00275 
00276 #define   PORT1_AUTO_NEG_100BTX       0x0004
00277 
00278 #define   PORT1_AUTO_NEG_10BT_FD      0x0002
00279 
00280 #define   PORT1_AUTO_NEG_10BT         0x0001
00281 
00282 /* Interrupt Enable Register Options */
00284 #define   INT_LINK_CHANGE     0x8000
00285 
00286 #define   INT_TX_DONE         0x4000
00287 
00288 #define   INT_RX_DONE         0x2000
00289 
00290 #define   INT_RX_OVERRUN      0x0800
00291 
00292 #define   INT_TX_STOPPED      0x0200
00293 
00294 #define   INT_RX_STOPPED      0x0100
00295 
00296 #define   INT_TX_SPACE        0x0040
00297 
00298 #define   INT_RX_WOL_FRAME    0x0020
00299 
00300 #define   INT_MAGIC           0x0010
00301 
00302 #define   INT_LINKUP          0x0008
00303 
00304 #define   INT_ENERGY          0x0004
00305 
00306 #define   INT_SPI_ERROR       0x0002
00307 
00309 #define   INT_MASK_EXAMPLE    (INT_RX_DONE |    \
00310                                INT_RX_OVERRUN | \
00311                                INT_TX_STOPPED | \
00312                                INT_RX_STOPPED | \
00313                                INT_TX_DONE |    \
00314                                INT_LINK_CHANGE)
00315 
00316 /* Global Reset Register Options */
00318 #define QMU_MODULE_SOFT_RESET    0x0002
00319 
00320 #define GLOBAL_SOFT_RESET        0x0001
00321 
00323 #define PHY_RESET                0x0001
00324 
00325 /* Global Reset Register Options */
00327 #define DIGITAL_LOOPBACK            0x4000
00328 
00329 #define FORCE_100                   0x2000
00330 
00331 #define AUTO_NEG                    0x1000
00332 
00333 #define RESTART_AUTO_NEG            0x0200
00334 
00335 #define FORCE_FULL_DUPLEX           0x0100
00336 
00337 /* Management information base registers */
00338 #define MIB_MASK                    0x1C00       
00339 #define MIB_RxByte                  0x00         
00340 #define MIB_XXX                     0x01         
00341 #define MIB_RxUndersizePkt          0x02         
00342 #define MIB_RxFragments             0x03         
00343 #define MIB_RxOversize              0x04         
00344 #define MIB_RxJabbers               0x05         
00345 #define MIB_RxSynbolError           0x06         
00346 #define MIB_RxCRCError              0x07         
00347 #define MIB_RxAlignmentError        0x08         
00348 #define MIB_RxControl8808Pkts       0x09         
00349 #define MIB_RxPausePkts             0x0A         
00350 #define MIB_RxBroadcast             0x0B         
00351 #define MIB_RxMulticast             0x0C         
00352 #define MIB_RxUnicast               0x0D         
00353 #define MIB_Rx64Octets              0x0E         
00354 #define MIB_Rx65to127Octets         0x0F         
00355 #define MIB_Rx128to255Octets        0x10         
00356 #define MIB_Rx256to511Octets        0x11         
00357 #define MIB_Rx512to1023Octets       0x12         
00358 #define MIB_Rx1024to1521Octets      0x13         
00359 #define MIB_Rx1522to2000Octets      0x14         
00360 #define MIB_TxByte                  0x15         
00361 #define MIB_TxLateCollision         0x16         
00362 #define MIB_TxPausePkts             0x17         
00363 #define MIB_TxBroadcastPkts         0x18         
00364 #define MIB_TxMulticastPkts         0x19         
00365 #define MIB_TxUnicastPkts           0x1A         
00366 #define MIB_TxDeferred              0x1B         
00367 #define MIB_TxTotalCollision        0x1C         
00368 #define MIB_TxExcessiveCollision    0x1D         
00369 #define MIB_TxSingleCollision       0x1E         
00370 #define MIB_TxMultipleCollision     0x1F         
00373 enum exceptionType_e
00374 {
00375   ERROR,
00376   INFO
00377 };
00378 
00379 void     KSZ8851SNL_Init(void);
00380 void     KSZ8851SNL_Send(uint16_t packetLength, uint8_t *packetData);
00381 uint16_t KSZ8851SNL_Receive(uint8_t *pRXData, uint16_t *pRXLength);
00382 void     KSZ8851SNL_GetMacAddress(uint8_t *macAddress);
00383 void     KSZ8851SNL_ReadMIBCounters(char* param);
00384 uint16_t KSZ8851SNL_CheckIrqStat(void);
00385 uint16_t KSZ8851SNL_CurrFrameSize(void);
00386 void     KSZ8851SNL_TerminateLongTransmit(uint16_t pTXLength, uint8_t *pTXData);
00387 void     KSZ8851SNL_InitiateLongTransmit(uint16_t pTXLength);
00388 void     KSZ8851SNL_LongTransmit(uint16_t pTXLength, uint8_t *pTXData);
00389 void     KSZ8851SNL_EnableInterupts(void);
00390 
00391 
00392 #ifdef __cplusplus
00393 }
00394 #endif
00395 
00399 #endif