00001
00032
00037 typedef struct
00038 {
00039 __IO uint32_t ETMCR;
00040 __I uint32_t ETMCCR;
00041 __IO uint32_t ETMTRIGGER;
00042 uint32_t RESERVED0[1];
00043 __IO uint32_t ETMSR;
00044 __I uint32_t ETMSCR;
00045 uint32_t RESERVED1[2];
00046 __IO uint32_t ETMTEEVR;
00047 __IO uint32_t ETMTECR1;
00048 uint32_t RESERVED2[1];
00049 __IO uint32_t ETMFFLR;
00050 uint32_t RESERVED3[68];
00051 __IO uint32_t ETMCNTRLDVR1;
00052 uint32_t RESERVED4[39];
00053 __IO uint32_t ETMSYNCFR;
00054 __I uint32_t ETMIDR;
00055 __I uint32_t ETMCCER;
00056 uint32_t RESERVED5[1];
00057 __IO uint32_t ETMTESSEICR;
00058 uint32_t RESERVED6[1];
00059 __IO uint32_t ETMTSEVR;
00060 uint32_t RESERVED7[1];
00061 __IO uint32_t ETMTRACEIDR;
00062 uint32_t RESERVED8[1];
00063 __I uint32_t ETMIDR2;
00064 uint32_t RESERVED9[66];
00065 __I uint32_t ETMPDSR;
00066 uint32_t RESERVED10[754];
00067 __IO uint32_t ETMISCIN;
00068 uint32_t RESERVED11[1];
00069 __O uint32_t ITTRIGOUT;
00070 uint32_t RESERVED12[1];
00071 __I uint32_t ETMITATBCTR2;
00072 uint32_t RESERVED13[1];
00073 __O uint32_t ETMITATBCTR0;
00074 uint32_t RESERVED14[1];
00075 __IO uint32_t ETMITCTRL;
00076 uint32_t RESERVED15[39];
00077 __IO uint32_t ETMCLAIMSET;
00078 __IO uint32_t ETMCLAIMCLR;
00079 uint32_t RESERVED16[2];
00080 __IO uint32_t ETMLAR;
00081 __I uint32_t ETMLSR;
00082 __I uint32_t ETMAUTHSTATUS;
00083 uint32_t RESERVED17[4];
00084 __I uint32_t ETMDEVTYPE;
00085 __I uint32_t ETMPIDR4;
00086 __O uint32_t ETMPIDR5;
00087 __O uint32_t ETMPIDR6;
00088 __O uint32_t ETMPIDR7;
00089 __I uint32_t ETMPIDR0;
00090 __I uint32_t ETMPIDR1;
00091 __I uint32_t ETMPIDR2;
00092 __I uint32_t ETMPIDR3;
00093 __I uint32_t ETMCIDR0;
00094 __I uint32_t ETMCIDR1;
00095 __I uint32_t ETMCIDR2;
00096 __I uint32_t ETMCIDR3;
00097 } ETM_TypeDef;
00099
00104
00105 #define _ETM_ETMCR_RESETVALUE 0x00000411UL
00106 #define _ETM_ETMCR_MASK 0x10632FF1UL
00107 #define ETM_ETMCR_POWERDWN (0x1UL << 0)
00108 #define _ETM_ETMCR_POWERDWN_SHIFT 0
00109 #define _ETM_ETMCR_POWERDWN_MASK 0x1UL
00110 #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL
00111 #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0)
00112 #define _ETM_ETMCR_PORTSIZE_SHIFT 4
00113 #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL
00114 #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL
00115 #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4)
00116 #define ETM_ETMCR_STALL (0x1UL << 7)
00117 #define _ETM_ETMCR_STALL_SHIFT 7
00118 #define _ETM_ETMCR_STALL_MASK 0x80UL
00119 #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL
00120 #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7)
00121 #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8)
00122 #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8
00123 #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL
00124 #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL
00125 #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8)
00126 #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9)
00127 #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9
00128 #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL
00129 #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL
00130 #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9)
00131 #define ETM_ETMCR_ETMPROG (0x1UL << 10)
00132 #define _ETM_ETMCR_ETMPROG_SHIFT 10
00133 #define _ETM_ETMCR_ETMPROG_MASK 0x400UL
00134 #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL
00135 #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10)
00136 #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11)
00137 #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11
00138 #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL
00139 #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL
00140 #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL
00141 #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL
00142 #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11)
00143 #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11)
00144 #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11)
00145 #define ETM_ETMCR_PORTMODE2 (0x1UL << 13)
00146 #define _ETM_ETMCR_PORTMODE2_SHIFT 13
00147 #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL
00148 #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL
00149 #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13)
00150 #define _ETM_ETMCR_PORTMODE_SHIFT 16
00151 #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL
00152 #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL
00153 #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16)
00154 #define _ETM_ETMCR_EPORTSIZE_SHIFT 21
00155 #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL
00156 #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL
00157 #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21)
00158 #define ETM_ETMCR_TSTAMPEN (0x1UL << 28)
00159 #define _ETM_ETMCR_TSTAMPEN_SHIFT 28
00160 #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL
00161 #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL
00162 #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28)
00164
00165 #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL
00166 #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL
00167 #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0
00168 #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL
00169 #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL
00170 #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0)
00171 #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4
00172 #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL
00173 #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL
00174 #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4)
00175 #define _ETM_ETMCCR_MMDECCNT_SHIFT 8
00176 #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL
00177 #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL
00178 #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8)
00179 #define _ETM_ETMCCR_COUNTNUM_SHIFT 13
00180 #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL
00181 #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL
00182 #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13)
00183 #define ETM_ETMCCR_SEQPRES (0x1UL << 16)
00184 #define _ETM_ETMCCR_SEQPRES_SHIFT 16
00185 #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL
00186 #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL
00187 #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16)
00188 #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17
00189 #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL
00190 #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL
00191 #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL
00192 #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL
00193 #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL
00194 #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17)
00195 #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17)
00196 #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17)
00197 #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17)
00198 #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20
00199 #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL
00200 #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL
00201 #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20)
00202 #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23)
00203 #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23
00204 #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL
00205 #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL
00206 #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23)
00207 #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24
00208 #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL
00209 #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL
00210 #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24)
00211 #define ETM_ETMCCR_TRACESS (0x1UL << 26)
00212 #define _ETM_ETMCCR_TRACESS_SHIFT 26
00213 #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL
00214 #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL
00215 #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26)
00216 #define ETM_ETMCCR_MMACCESS (0x1UL << 27)
00217 #define _ETM_ETMCCR_MMACCESS_SHIFT 27
00218 #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL
00219 #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL
00220 #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27)
00221 #define ETM_ETMCCR_ETMID (0x1UL << 31)
00222 #define _ETM_ETMCCR_ETMID_SHIFT 31
00223 #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL
00224 #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL
00225 #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31)
00227
00228 #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL
00229 #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL
00230 #define _ETM_ETMTRIGGER_RESA_SHIFT 0
00231 #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL
00232 #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL
00233 #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0)
00234 #define _ETM_ETMTRIGGER_RESB_SHIFT 7
00235 #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL
00236 #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL
00237 #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7)
00238 #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14
00239 #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL
00240 #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL
00241 #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14)
00243
00244 #define _ETM_ETMSR_RESETVALUE 0x00000002UL
00245 #define _ETM_ETMSR_MASK 0x0000000FUL
00246 #define ETM_ETMSR_ETHOF (0x1UL << 0)
00247 #define _ETM_ETMSR_ETHOF_SHIFT 0
00248 #define _ETM_ETMSR_ETHOF_MASK 0x1UL
00249 #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL
00250 #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0)
00251 #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1)
00252 #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1
00253 #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL
00254 #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL
00255 #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1)
00256 #define ETM_ETMSR_TRACESTAT (0x1UL << 2)
00257 #define _ETM_ETMSR_TRACESTAT_SHIFT 2
00258 #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL
00259 #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL
00260 #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2)
00261 #define ETM_ETMSR_TRIGBIT (0x1UL << 3)
00262 #define _ETM_ETMSR_TRIGBIT_SHIFT 3
00263 #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL
00264 #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL
00265 #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3)
00267
00268 #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL
00269 #define _ETM_ETMSCR_MASK 0x00027F0FUL
00270 #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0
00271 #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL
00272 #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL
00273 #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0)
00274 #define ETM_ETMSCR_Reserved (0x1UL << 3)
00275 #define _ETM_ETMSCR_Reserved_SHIFT 3
00276 #define _ETM_ETMSCR_Reserved_MASK 0x8UL
00277 #define _ETM_ETMSCR_Reserved_DEFAULT 0x00000001UL
00278 #define ETM_ETMSCR_Reserved_DEFAULT (_ETM_ETMSCR_Reserved_DEFAULT << 3)
00279 #define ETM_ETMSCR_FIFOFULL (0x1UL << 8)
00280 #define _ETM_ETMSCR_FIFOFULL_SHIFT 8
00281 #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL
00282 #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL
00283 #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8)
00284 #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9)
00285 #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9
00286 #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL
00287 #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL
00288 #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9)
00289 #define ETM_ETMSCR_PORTSIZE (0x1UL << 10)
00290 #define _ETM_ETMSCR_PORTSIZE_SHIFT 10
00291 #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL
00292 #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL
00293 #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10)
00294 #define ETM_ETMSCR_PORTMODE (0x1UL << 11)
00295 #define _ETM_ETMSCR_PORTMODE_SHIFT 11
00296 #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL
00297 #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL
00298 #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11)
00299 #define _ETM_ETMSCR_PROCNUM_SHIFT 12
00300 #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL
00301 #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL
00302 #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12)
00303 #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17)
00304 #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17
00305 #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL
00306 #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL
00307 #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17)
00309
00310 #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL
00311 #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL
00312 #define _ETM_ETMTEEVR_RESA_SHIFT 0
00313 #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL
00314 #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL
00315 #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0)
00316 #define _ETM_ETMTEEVR_RESB_SHIFT 7
00317 #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL
00318 #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL
00319 #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7)
00320 #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14
00321 #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL
00322 #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL
00323 #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14)
00325
00326 #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL
00327 #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL
00328 #define _ETM_ETMTECR1_ADRCMP_SHIFT 0
00329 #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL
00330 #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL
00331 #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0)
00332 #define _ETM_ETMTECR1_MEMMAP_SHIFT 8
00333 #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL
00334 #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL
00335 #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8)
00336 #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24)
00337 #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24
00338 #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL
00339 #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL
00340 #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL
00341 #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL
00342 #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24)
00343 #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24)
00344 #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24)
00345 #define ETM_ETMTECR1_TCE (0x1UL << 25)
00346 #define _ETM_ETMTECR1_TCE_SHIFT 25
00347 #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL
00348 #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL
00349 #define _ETM_ETMTECR1_TCE_EN 0x00000000UL
00350 #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL
00351 #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25)
00352 #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25)
00353 #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25)
00355
00356 #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL
00357 #define _ETM_ETMFFLR_MASK 0x000000FFUL
00358 #define _ETM_ETMFFLR_BYTENUM_SHIFT 0
00359 #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL
00360 #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL
00361 #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0)
00363
00364 #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL
00365 #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL
00366 #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0
00367 #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL
00368 #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL
00369 #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0)
00371
00372 #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL
00373 #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL
00374 #define _ETM_ETMSYNCFR_FREQ_SHIFT 0
00375 #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL
00376 #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL
00377 #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0)
00379
00380 #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL
00381 #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL
00382 #define _ETM_ETMIDR_IMPVER_SHIFT 0
00383 #define _ETM_ETMIDR_IMPVER_MASK 0xFUL
00384 #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL
00385 #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0)
00386 #define _ETM_ETMIDR_ETMMINVER_SHIFT 4
00387 #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL
00388 #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL
00389 #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4)
00390 #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8
00391 #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL
00392 #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL
00393 #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8)
00394 #define _ETM_ETMIDR_PROCFAM_SHIFT 12
00395 #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL
00396 #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL
00397 #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12)
00398 #define ETM_ETMIDR_LPCF (0x1UL << 16)
00399 #define _ETM_ETMIDR_LPCF_SHIFT 16
00400 #define _ETM_ETMIDR_LPCF_MASK 0x10000UL
00401 #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL
00402 #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16)
00403 #define ETM_ETMIDR_THUMBT (0x1UL << 18)
00404 #define _ETM_ETMIDR_THUMBT_SHIFT 18
00405 #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL
00406 #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL
00407 #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18)
00408 #define ETM_ETMIDR_SECEXT (0x1UL << 19)
00409 #define _ETM_ETMIDR_SECEXT_SHIFT 19
00410 #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL
00411 #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL
00412 #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19)
00413 #define ETM_ETMIDR_BPE (0x1UL << 20)
00414 #define _ETM_ETMIDR_BPE_SHIFT 20
00415 #define _ETM_ETMIDR_BPE_MASK 0x100000UL
00416 #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL
00417 #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20)
00418 #define _ETM_ETMIDR_IMPCODE_SHIFT 24
00419 #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL
00420 #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL
00421 #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24)
00423
00424 #define _ETM_ETMCCER_RESETVALUE 0x18541800UL
00425 #define _ETM_ETMCCER_MASK 0x387FFFFBUL
00426 #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0
00427 #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL
00428 #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL
00429 #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0)
00430 #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3
00431 #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL
00432 #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL
00433 #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3)
00434 #define ETM_ETMCCER_READREGS (0x1UL << 11)
00435 #define _ETM_ETMCCER_READREGS_SHIFT 11
00436 #define _ETM_ETMCCER_READREGS_MASK 0x800UL
00437 #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL
00438 #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11)
00439 #define ETM_ETMCCER_DADDRCMP (0x1UL << 12)
00440 #define _ETM_ETMCCER_DADDRCMP_SHIFT 12
00441 #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL
00442 #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL
00443 #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12)
00444 #define _ETM_ETMCCER_INSTRES_SHIFT 13
00445 #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL
00446 #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL
00447 #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13)
00448 #define _ETM_ETMCCER_EICEWPNT_SHIFT 16
00449 #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL
00450 #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL
00451 #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16)
00452 #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20)
00453 #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20
00454 #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL
00455 #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL
00456 #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20)
00457 #define ETM_ETMCCER_EICEIMP (0x1UL << 21)
00458 #define _ETM_ETMCCER_EICEIMP_SHIFT 21
00459 #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL
00460 #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL
00461 #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21)
00462 #define ETM_ETMCCER_TIMP (0x1UL << 22)
00463 #define _ETM_ETMCCER_TIMP_SHIFT 22
00464 #define _ETM_ETMCCER_TIMP_MASK 0x400000UL
00465 #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL
00466 #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22)
00467 #define ETM_ETMCCER_RFCNT (0x1UL << 27)
00468 #define _ETM_ETMCCER_RFCNT_SHIFT 27
00469 #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL
00470 #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL
00471 #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27)
00472 #define ETM_ETMCCER_TENC (0x1UL << 28)
00473 #define _ETM_ETMCCER_TENC_SHIFT 28
00474 #define _ETM_ETMCCER_TENC_MASK 0x10000000UL
00475 #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL
00476 #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28)
00477 #define ETM_ETMCCER_TSIZE (0x1UL << 29)
00478 #define _ETM_ETMCCER_TSIZE_SHIFT 29
00479 #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL
00480 #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL
00481 #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29)
00483
00484 #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL
00485 #define _ETM_ETMTESSEICR_MASK 0x000F000FUL
00486 #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0
00487 #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL
00488 #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL
00489 #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0)
00490 #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16
00491 #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL
00492 #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL
00493 #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16)
00495
00496 #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL
00497 #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL
00498 #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0
00499 #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL
00500 #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL
00501 #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0)
00502 #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7
00503 #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL
00504 #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL
00505 #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7)
00506 #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14
00507 #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL
00508 #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL
00509 #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14)
00511
00512 #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL
00513 #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL
00514 #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0
00515 #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL
00516 #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL
00517 #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0)
00519
00520 #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL
00521 #define _ETM_ETMIDR2_MASK 0x00000003UL
00522 #define ETM_ETMIDR2_RFE (0x1UL << 0)
00523 #define _ETM_ETMIDR2_RFE_SHIFT 0
00524 #define _ETM_ETMIDR2_RFE_MASK 0x1UL
00525 #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL
00526 #define _ETM_ETMIDR2_RFE_PC 0x00000000UL
00527 #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL
00528 #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0)
00529 #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0)
00530 #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0)
00531 #define ETM_ETMIDR2_SWP (0x1UL << 1)
00532 #define _ETM_ETMIDR2_SWP_SHIFT 1
00533 #define _ETM_ETMIDR2_SWP_MASK 0x2UL
00534 #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL
00535 #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL
00536 #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL
00537 #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1)
00538 #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1)
00539 #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1)
00541
00542 #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL
00543 #define _ETM_ETMPDSR_MASK 0x00000001UL
00544 #define ETM_ETMPDSR_ETMUP (0x1UL << 0)
00545 #define _ETM_ETMPDSR_ETMUP_SHIFT 0
00546 #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL
00547 #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL
00548 #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0)
00550
00551 #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL
00552 #define _ETM_ETMISCIN_MASK 0x00000013UL
00553 #define _ETM_ETMISCIN_EXTIN_SHIFT 0
00554 #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL
00555 #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL
00556 #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0)
00557 #define ETM_ETMISCIN_COREHALT (0x1UL << 4)
00558 #define _ETM_ETMISCIN_COREHALT_SHIFT 4
00559 #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL
00560 #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL
00561 #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4)
00563
00564 #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL
00565 #define _ETM_ITTRIGOUT_MASK 0x00000001UL
00566 #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0)
00567 #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0
00568 #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL
00569 #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL
00570 #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0)
00572
00573 #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL
00574 #define _ETM_ETMITATBCTR2_MASK 0x00000001UL
00575 #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0)
00576 #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0
00577 #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL
00578 #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL
00579 #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0)
00581
00582 #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL
00583 #define _ETM_ETMITATBCTR0_MASK 0x00000001UL
00584 #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0)
00585 #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0
00586 #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL
00587 #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL
00588 #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0)
00590
00591 #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL
00592 #define _ETM_ETMITCTRL_MASK 0x00000001UL
00593 #define ETM_ETMITCTRL_ITEN (0x1UL << 0)
00594 #define _ETM_ETMITCTRL_ITEN_SHIFT 0
00595 #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL
00596 #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL
00597 #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0)
00599
00600 #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL
00601 #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL
00602 #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0
00603 #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL
00604 #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL
00605 #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0)
00607
00608 #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL
00609 #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL
00610 #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0)
00611 #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0
00612 #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL
00613 #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL
00614 #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0)
00616
00617 #define _ETM_ETMLAR_RESETVALUE 0x00000000UL
00618 #define _ETM_ETMLAR_MASK 0x00000001UL
00619 #define ETM_ETMLAR_KEY (0x1UL << 0)
00620 #define _ETM_ETMLAR_KEY_SHIFT 0
00621 #define _ETM_ETMLAR_KEY_MASK 0x1UL
00622 #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL
00623 #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0)
00625
00626 #define _ETM_ETMLSR_RESETVALUE 0x00000003UL
00627 #define _ETM_ETMLSR_MASK 0x00000003UL
00628 #define ETM_ETMLSR_LOCKIMP (0x1UL << 0)
00629 #define _ETM_ETMLSR_LOCKIMP_SHIFT 0
00630 #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL
00631 #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL
00632 #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0)
00633 #define ETM_ETMLSR_LOCKED (0x1UL << 1)
00634 #define _ETM_ETMLSR_LOCKED_SHIFT 1
00635 #define _ETM_ETMLSR_LOCKED_MASK 0x2UL
00636 #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL
00637 #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1)
00639
00640 #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL
00641 #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL
00642 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0
00643 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL
00644 #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL
00645 #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0)
00646 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2
00647 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL
00648 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL
00649 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL
00650 #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL
00651 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2)
00652 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2)
00653 #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2)
00654 #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4
00655 #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL
00656 #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL
00657 #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4)
00658 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6
00659 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL
00660 #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL
00661 #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6)
00663
00664 #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL
00665 #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL
00666 #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0
00667 #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL
00668 #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL
00669 #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0)
00670 #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4
00671 #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL
00672 #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL
00673 #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4)
00675
00676 #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL
00677 #define _ETM_ETMPIDR4_MASK 0x000000FFUL
00678 #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0
00679 #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL
00680 #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL
00681 #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0)
00682 #define _ETM_ETMPIDR4_COUNT_SHIFT 4
00683 #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL
00684 #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL
00685 #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4)
00687
00688 #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL
00689 #define _ETM_ETMPIDR5_MASK 0x00000000UL
00691
00692 #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL
00693 #define _ETM_ETMPIDR6_MASK 0x00000000UL
00695
00696 #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL
00697 #define _ETM_ETMPIDR7_MASK 0x00000000UL
00699
00700 #define _ETM_ETMPIDR0_RESETVALUE 0x00000024UL
00701 #define _ETM_ETMPIDR0_MASK 0x000000FFUL
00702 #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0
00703 #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL
00704 #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000024UL
00705 #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0)
00707
00708 #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL
00709 #define _ETM_ETMPIDR1_MASK 0x000000FFUL
00710 #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0
00711 #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL
00712 #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL
00713 #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0)
00714 #define _ETM_ETMPIDR1_IDCODE_SHIFT 4
00715 #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL
00716 #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL
00717 #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4)
00719
00720 #define _ETM_ETMPIDR2_RESETVALUE 0x0000003BUL
00721 #define _ETM_ETMPIDR2_MASK 0x000000FFUL
00722 #define _ETM_ETMPIDR2_IDCODE_SHIFT 0
00723 #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL
00724 #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL
00725 #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0)
00726 #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3)
00727 #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3
00728 #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL
00729 #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL
00730 #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3)
00731 #define _ETM_ETMPIDR2_REV_SHIFT 4
00732 #define _ETM_ETMPIDR2_REV_MASK 0xF0UL
00733 #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000003UL
00734 #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4)
00736
00737 #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL
00738 #define _ETM_ETMPIDR3_MASK 0x000000FFUL
00739 #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0
00740 #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL
00741 #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL
00742 #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0)
00743 #define _ETM_ETMPIDR3_REVAND_SHIFT 4
00744 #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL
00745 #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL
00746 #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4)
00748
00749 #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL
00750 #define _ETM_ETMCIDR0_MASK 0x000000FFUL
00751 #define _ETM_ETMCIDR0_PREAMB_SHIFT 0
00752 #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL
00753 #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL
00754 #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0)
00756
00757 #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL
00758 #define _ETM_ETMCIDR1_MASK 0x000000FFUL
00759 #define _ETM_ETMCIDR1_PREAMB_SHIFT 0
00760 #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL
00761 #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL
00762 #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0)
00764
00765 #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL
00766 #define _ETM_ETMCIDR2_MASK 0x000000FFUL
00767 #define _ETM_ETMCIDR2_PREAMB_SHIFT 0
00768 #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL
00769 #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL
00770 #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0)
00772
00773 #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL
00774 #define _ETM_ETMCIDR3_MASK 0x000000FFUL
00775 #define _ETM_ETMCIDR3_PREAMB_SHIFT 0
00776 #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL
00777 #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL
00778 #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0)