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Data Structures | |
struct | CMU_TypeDef |
struct | PRS_TypeDef |
Defines | |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 3 |
#define | __Vendor_SysTickConfig 0 |
#define | _EFM32_GIANT_FAMILY 1 |
#define | _EFM_DEVICE |
#define | EFM32LG295F256 1 |
#define | PART_NUMBER "EFM32LG295F256" |
#define | FLASH_MEM_BASE ((uint32_t) 0x0UL) |
#define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) |
#define | FLASH_MEM_BITS ((uint32_t) 0x28UL) |
#define | AES_MEM_BASE ((uint32_t) 0x400E0000UL) |
#define | AES_MEM_SIZE ((uint32_t) 0x400UL) |
#define | AES_MEM_END ((uint32_t) 0x400E03FFUL) |
#define | AES_MEM_BITS ((uint32_t) 0x10UL) |
#define | USBC_MEM_BASE ((uint32_t) 0x40100000UL) |
#define | USBC_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | USBC_MEM_END ((uint32_t) 0x4013FFFFUL) |
#define | USBC_MEM_BITS ((uint32_t) 0x18UL) |
#define | EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) |
#define | EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) |
#define | EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) |
#define | EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) |
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
#define | PER_MEM_SIZE ((uint32_t) 0xE0000UL) |
#define | PER_MEM_END ((uint32_t) 0x400DFFFFUL) |
#define | PER_MEM_BITS ((uint32_t) 0x20UL) |
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM_MEM_SIZE ((uint32_t) 0x40000UL) |
#define | RAM_MEM_END ((uint32_t) 0x2003FFFFUL) |
#define | RAM_MEM_BITS ((uint32_t) 0x18UL) |
#define | RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
#define | RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) |
#define | RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) |
#define | RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) |
#define | EBI_MEM_BASE ((uint32_t) 0x80000000UL) |
#define | EBI_MEM_SIZE ((uint32_t) 0x40000000UL) |
#define | EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) |
#define | EBI_MEM_BITS ((uint32_t) 0x30UL) |
#define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
#define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
#define | FLASH_BASE (0x00000000UL) |
#define | FLASH_SIZE (0x00040000UL) |
#define | FLASH_PAGE_SIZE 2048 |
#define | SRAM_BASE (0x20000000UL) |
#define | SRAM_SIZE (0x00008000UL) |
#define | __CM3_REV 0x201 |
#define | PRS_CHAN_COUNT 12 |
#define | DMA_CHAN_COUNT 12 |
#define | AFCHAN_MAX 163 |
#define | AFCHANLOC_MAX 7 |
#define | AFACHAN_MAX 53 |
#define | USART_PRESENT |
#define | USART_COUNT 3 |
#define | UART_PRESENT |
#define | UART_COUNT 2 |
#define | TIMER_PRESENT |
#define | TIMER_COUNT 4 |
#define | ACMP_PRESENT |
#define | ACMP_COUNT 2 |
#define | LEUART_PRESENT |
#define | LEUART_COUNT 2 |
#define | LETIMER_PRESENT |
#define | LETIMER_COUNT 1 |
#define | PCNT_PRESENT |
#define | PCNT_COUNT 3 |
#define | I2C_PRESENT |
#define | I2C_COUNT 2 |
#define | ADC_PRESENT |
#define | ADC_COUNT 1 |
#define | DAC_PRESENT |
#define | DAC_COUNT 1 |
#define | DMA_PRESENT |
#define | DMA_COUNT 1 |
#define | AES_PRESENT |
#define | AES_COUNT 1 |
#define | LE_PRESENT |
#define | LE_COUNT 1 |
#define | MSC_PRESENT |
#define | MSC_COUNT 1 |
#define | EMU_PRESENT |
#define | EMU_COUNT 1 |
#define | RMU_PRESENT |
#define | RMU_COUNT 1 |
#define | CMU_PRESENT |
#define | CMU_COUNT 1 |
#define | LESENSE_PRESENT |
#define | LESENSE_COUNT 1 |
#define | EBI_PRESENT |
#define | EBI_COUNT 1 |
#define | RTC_PRESENT |
#define | RTC_COUNT 1 |
#define | GPIO_PRESENT |
#define | GPIO_COUNT 1 |
#define | VCMP_PRESENT |
#define | VCMP_COUNT 1 |
#define | PRS_PRESENT |
#define | PRS_COUNT 1 |
#define | OPAMP_PRESENT |
#define | OPAMP_COUNT 1 |
#define | BU_PRESENT |
#define | BU_COUNT 1 |
#define | BURTC_PRESENT |
#define | BURTC_COUNT 1 |
#define | HFXTAL_PRESENT |
#define | HFXTAL_COUNT 1 |
#define | LFXTAL_PRESENT |
#define | LFXTAL_COUNT 1 |
#define | WDOG_PRESENT |
#define | WDOG_COUNT 1 |
#define | DBG_PRESENT |
#define | DBG_COUNT 1 |
#define | ETM_PRESENT |
#define | ETM_COUNT 1 |
#define | BOOTLOADER_PRESENT |
#define | BOOTLOADER_COUNT 1 |
#define | ANALOG_PRESENT |
#define | ANALOG_COUNT 1 |
#define | DMA_BASE (0x400C2000UL) |
#define | AES_BASE (0x400E0000UL) |
#define | MSC_BASE (0x400C0000UL) |
#define | EMU_BASE (0x400C6000UL) |
#define | RMU_BASE (0x400CA000UL) |
#define | CMU_BASE (0x400C8000UL) |
#define | LESENSE_BASE (0x4008C000UL) |
#define | EBI_BASE (0x40008000UL) |
#define | USART0_BASE (0x4000C000UL) |
#define | USART1_BASE (0x4000C400UL) |
#define | USART2_BASE (0x4000C800UL) |
#define | UART0_BASE (0x4000E000UL) |
#define | UART1_BASE (0x4000E400UL) |
#define | TIMER0_BASE (0x40010000UL) |
#define | TIMER1_BASE (0x40010400UL) |
#define | TIMER2_BASE (0x40010800UL) |
#define | TIMER3_BASE (0x40010C00UL) |
#define | ACMP0_BASE (0x40001000UL) |
#define | ACMP1_BASE (0x40001400UL) |
#define | LEUART0_BASE (0x40084000UL) |
#define | LEUART1_BASE (0x40084400UL) |
#define | RTC_BASE (0x40080000UL) |
#define | LETIMER0_BASE (0x40082000UL) |
#define | PCNT0_BASE (0x40086000UL) |
#define | PCNT1_BASE (0x40086400UL) |
#define | PCNT2_BASE (0x40086800UL) |
#define | I2C0_BASE (0x4000A000UL) |
#define | I2C1_BASE (0x4000A400UL) |
#define | GPIO_BASE (0x40006000UL) |
#define | VCMP_BASE (0x40000000UL) |
#define | PRS_BASE (0x400CC000UL) |
#define | ADC0_BASE (0x40002000UL) |
#define | DAC0_BASE (0x40004000UL) |
#define | BURTC_BASE (0x40081000UL) |
#define | WDOG_BASE (0x40088000UL) |
#define | ETM_BASE (0xE0041000UL) |
#define | CALIBRATE_BASE (0x0FE08000UL) |
#define | DEVINFO_BASE (0x0FE081B0UL) |
#define | ROMTABLE_BASE (0xE00FFFD0UL) |
#define | LOCKBITS_BASE (0x0FE04000UL) |
#define | USERDATA_BASE (0x0FE00000UL) |
#define | DMA ((DMA_TypeDef *) DMA_BASE) |
#define | AES ((AES_TypeDef *) AES_BASE) |
#define | MSC ((MSC_TypeDef *) MSC_BASE) |
#define | EMU ((EMU_TypeDef *) EMU_BASE) |
#define | RMU ((RMU_TypeDef *) RMU_BASE) |
#define | CMU ((CMU_TypeDef *) CMU_BASE) |
#define | LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) |
#define | EBI ((EBI_TypeDef *) EBI_BASE) |
#define | USART0 ((USART_TypeDef *) USART0_BASE) |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | USART2 ((USART_TypeDef *) USART2_BASE) |
#define | UART0 ((USART_TypeDef *) UART0_BASE) |
#define | UART1 ((USART_TypeDef *) UART1_BASE) |
#define | TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) |
#define | TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) |
#define | TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) |
#define | TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) |
#define | ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) |
#define | ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) |
#define | LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) |
#define | LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) |
#define | PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) |
#define | PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) |
#define | PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) |
#define | I2C0 ((I2C_TypeDef *) I2C0_BASE) |
#define | I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define | GPIO ((GPIO_TypeDef *) GPIO_BASE) |
#define | VCMP ((VCMP_TypeDef *) VCMP_BASE) |
#define | PRS ((PRS_TypeDef *) PRS_BASE) |
#define | ADC0 ((ADC_TypeDef *) ADC0_BASE) |
#define | DAC0 ((DAC_TypeDef *) DAC0_BASE) |
#define | BURTC ((BURTC_TypeDef *) BURTC_BASE) |
#define | WDOG ((WDOG_TypeDef *) WDOG_BASE) |
#define | ETM ((ETM_TypeDef *) ETM_BASE) |
#define | CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) |
#define | DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) |
#define | ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) |
#define | PRS_VCMP_OUT ((1 << 16) + 0) |
#define | PRS_ACMP0_OUT ((2 << 16) + 0) |
#define | PRS_ACMP1_OUT ((3 << 16) + 0) |
#define | PRS_DAC0_CH0 ((6 << 16) + 0) |
#define | PRS_DAC0_CH1 ((6 << 16) + 1) |
#define | PRS_ADC0_SINGLE ((8 << 16) + 0) |
#define | PRS_ADC0_SCAN ((8 << 16) + 1) |
#define | PRS_USART0_IRTX ((16 << 16) + 0) |
#define | PRS_USART0_TXC ((16 << 16) + 1) |
#define | PRS_USART0_RXDATAV ((16 << 16) + 2) |
#define | PRS_USART1_TXC ((17 << 16) + 1) |
#define | PRS_USART1_RXDATAV ((17 << 16) + 2) |
#define | PRS_USART2_TXC ((18 << 16) + 1) |
#define | PRS_USART2_RXDATAV ((18 << 16) + 2) |
#define | PRS_TIMER0_UF ((28 << 16) + 0) |
#define | PRS_TIMER0_OF ((28 << 16) + 1) |
#define | PRS_TIMER0_CC0 ((28 << 16) + 2) |
#define | PRS_TIMER0_CC1 ((28 << 16) + 3) |
#define | PRS_TIMER0_CC2 ((28 << 16) + 4) |
#define | PRS_TIMER1_UF ((29 << 16) + 0) |
#define | PRS_TIMER1_OF ((29 << 16) + 1) |
#define | PRS_TIMER1_CC0 ((29 << 16) + 2) |
#define | PRS_TIMER1_CC1 ((29 << 16) + 3) |
#define | PRS_TIMER1_CC2 ((29 << 16) + 4) |
#define | PRS_TIMER2_UF ((30 << 16) + 0) |
#define | PRS_TIMER2_OF ((30 << 16) + 1) |
#define | PRS_TIMER2_CC0 ((30 << 16) + 2) |
#define | PRS_TIMER2_CC1 ((30 << 16) + 3) |
#define | PRS_TIMER2_CC2 ((30 << 16) + 4) |
#define | PRS_TIMER3_UF ((31 << 16) + 0) |
#define | PRS_TIMER3_OF ((31 << 16) + 1) |
#define | PRS_TIMER3_CC0 ((31 << 16) + 2) |
#define | PRS_TIMER3_CC1 ((31 << 16) + 3) |
#define | PRS_TIMER3_CC2 ((31 << 16) + 4) |
#define | PRS_RTC_OF ((40 << 16) + 0) |
#define | PRS_RTC_COMP0 ((40 << 16) + 1) |
#define | PRS_RTC_COMP1 ((40 << 16) + 2) |
#define | PRS_UART0_TXC ((41 << 16) + 1) |
#define | PRS_UART0_RXDATAV ((41 << 16) + 2) |
#define | PRS_UART1_TXC ((42 << 16) + 1) |
#define | PRS_UART1_RXDATAV ((42 << 16) + 2) |
#define | PRS_GPIO_PIN0 ((48 << 16) + 0) |
#define | PRS_GPIO_PIN1 ((48 << 16) + 1) |
#define | PRS_GPIO_PIN2 ((48 << 16) + 2) |
#define | PRS_GPIO_PIN3 ((48 << 16) + 3) |
#define | PRS_GPIO_PIN4 ((48 << 16) + 4) |
#define | PRS_GPIO_PIN5 ((48 << 16) + 5) |
#define | PRS_GPIO_PIN6 ((48 << 16) + 6) |
#define | PRS_GPIO_PIN7 ((48 << 16) + 7) |
#define | PRS_GPIO_PIN8 ((49 << 16) + 0) |
#define | PRS_GPIO_PIN9 ((49 << 16) + 1) |
#define | PRS_GPIO_PIN10 ((49 << 16) + 2) |
#define | PRS_GPIO_PIN11 ((49 << 16) + 3) |
#define | PRS_GPIO_PIN12 ((49 << 16) + 4) |
#define | PRS_GPIO_PIN13 ((49 << 16) + 5) |
#define | PRS_GPIO_PIN14 ((49 << 16) + 6) |
#define | PRS_GPIO_PIN15 ((49 << 16) + 7) |
#define | PRS_LETIMER0_CH0 ((52 << 16) + 0) |
#define | PRS_LETIMER0_CH1 ((52 << 16) + 1) |
#define | PRS_BURTC_OF ((55 << 16) + 0) |
#define | PRS_BURTC_COMP0 ((55 << 16) + 1) |
#define | PRS_LESENSE_SCANRES0 ((57 << 16) + 0) |
#define | PRS_LESENSE_SCANRES1 ((57 << 16) + 1) |
#define | PRS_LESENSE_SCANRES2 ((57 << 16) + 2) |
#define | PRS_LESENSE_SCANRES3 ((57 << 16) + 3) |
#define | PRS_LESENSE_SCANRES4 ((57 << 16) + 4) |
#define | PRS_LESENSE_SCANRES5 ((57 << 16) + 5) |
#define | PRS_LESENSE_SCANRES6 ((57 << 16) + 6) |
#define | PRS_LESENSE_SCANRES7 ((57 << 16) + 7) |
#define | PRS_LESENSE_SCANRES8 ((58 << 16) + 0) |
#define | PRS_LESENSE_SCANRES9 ((58 << 16) + 1) |
#define | PRS_LESENSE_SCANRES10 ((58 << 16) + 2) |
#define | PRS_LESENSE_SCANRES11 ((58 << 16) + 3) |
#define | PRS_LESENSE_SCANRES12 ((58 << 16) + 4) |
#define | PRS_LESENSE_SCANRES13 ((58 << 16) + 5) |
#define | PRS_LESENSE_SCANRES14 ((58 << 16) + 6) |
#define | PRS_LESENSE_SCANRES15 ((58 << 16) + 7) |
#define | PRS_LESENSE_DEC0 ((59 << 16) + 0) |
#define | PRS_LESENSE_DEC1 ((59 << 16) + 1) |
#define | PRS_LESENSE_DEC2 ((59 << 16) + 2) |
#define | _CMU_CTRL_RESETVALUE 0x000C262CUL |
#define | _CMU_CTRL_MASK 0x53FFFEEFUL |
#define | _CMU_CTRL_HFXOMODE_SHIFT 0 |
#define | _CMU_CTRL_HFXOMODE_MASK 0x3UL |
#define | _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL |
#define | _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL |
#define | _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL |
#define | CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) |
#define | CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) |
#define | CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) |
#define | CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) |
#define | _CMU_CTRL_HFXOBOOST_SHIFT 2 |
#define | _CMU_CTRL_HFXOBOOST_MASK 0xCUL |
#define | _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL |
#define | _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL |
#define | _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL |
#define | _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL |
#define | _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL |
#define | CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) |
#define | CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) |
#define | CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) |
#define | CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) |
#define | CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) |
#define | _CMU_CTRL_HFXOBUFCUR_SHIFT 5 |
#define | _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL |
#define | _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL |
#define | _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL |
#define | _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL |
#define | CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) |
#define | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) |
#define | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) |
#define | CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) |
#define | _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 |
#define | _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL |
#define | _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL |
#define | CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) |
#define | _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 |
#define | _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL |
#define | _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL |
#define | _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL |
#define | _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL |
#define | _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL |
#define | _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL |
#define | CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) |
#define | _CMU_CTRL_LFXOMODE_SHIFT 11 |
#define | _CMU_CTRL_LFXOMODE_MASK 0x1800UL |
#define | _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL |
#define | _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL |
#define | _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL |
#define | CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) |
#define | CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) |
#define | CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) |
#define | CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) |
#define | CMU_CTRL_LFXOBOOST (0x1UL << 13) |
#define | _CMU_CTRL_LFXOBOOST_SHIFT 13 |
#define | _CMU_CTRL_LFXOBOOST_MASK 0x2000UL |
#define | _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL |
#define | _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL |
#define | _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL |
#define | CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) |
#define | CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) |
#define | CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) |
#define | _CMU_CTRL_HFCLKDIV_SHIFT 14 |
#define | _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL |
#define | _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL |
#define | CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) |
#define | CMU_CTRL_LFXOBUFCUR (0x1UL << 17) |
#define | _CMU_CTRL_LFXOBUFCUR_SHIFT 17 |
#define | _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL |
#define | _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL |
#define | CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) |
#define | _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 |
#define | _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL |
#define | _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL |
#define | _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL |
#define | _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL |
#define | _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL |
#define | _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL |
#define | CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) |
#define | _CMU_CTRL_CLKOUTSEL0_SHIFT 20 |
#define | _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL |
#define | _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL |
#define | _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL |
#define | _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL |
#define | CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) |
#define | CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) |
#define | _CMU_CTRL_CLKOUTSEL1_SHIFT 23 |
#define | _CMU_CTRL_CLKOUTSEL1_MASK 0x3800000UL |
#define | _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL |
#define | _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL |
#define | _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL |
#define | _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL |
#define | _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL |
#define | _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL |
#define | _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL |
#define | CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) |
#define | CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) |
#define | CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) |
#define | CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) |
#define | CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) |
#define | CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) |
#define | CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) |
#define | CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) |
#define | CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) |
#define | CMU_CTRL_DBGCLK (0x1UL << 28) |
#define | _CMU_CTRL_DBGCLK_SHIFT 28 |
#define | _CMU_CTRL_DBGCLK_MASK 0x10000000UL |
#define | _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL |
#define | _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL |
#define | CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) |
#define | CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) |
#define | CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) |
#define | CMU_CTRL_HFLE (0x1UL << 30) |
#define | _CMU_CTRL_HFLE_SHIFT 30 |
#define | _CMU_CTRL_HFLE_MASK 0x40000000UL |
#define | _CMU_CTRL_HFLE_DEFAULT 0x00000000UL |
#define | CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) |
#define | _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL |
#define | _CMU_HFCORECLKDIV_MASK 0x0000010FUL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) |
#define | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 |
#define | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL |
#define | CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) |
#define | CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) |
#define | CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) |
#define | _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL |
#define | _CMU_HFPERCLKDIV_MASK 0x0000010FUL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) |
#define | _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 |
#define | _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL |
#define | CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) |
#define | _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL |
#define | _CMU_HFRCOCTRL_MASK 0x0001F7FFUL |
#define | _CMU_HFRCOCTRL_TUNING_SHIFT 0 |
#define | _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL |
#define | _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL |
#define | CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) |
#define | _CMU_HFRCOCTRL_BAND_SHIFT 8 |
#define | _CMU_HFRCOCTRL_BAND_MASK 0x700UL |
#define | _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL |
#define | _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL |
#define | _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL |
#define | _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL |
#define | _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL |
#define | _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL |
#define | _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL |
#define | CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) |
#define | CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) |
#define | _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 |
#define | _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL |
#define | _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL |
#define | CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) |
#define | _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL |
#define | _CMU_LFRCOCTRL_MASK 0x0000007FUL |
#define | _CMU_LFRCOCTRL_TUNING_SHIFT 0 |
#define | _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL |
#define | _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL |
#define | CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) |
#define | _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL |
#define | _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL |
#define | _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 |
#define | _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL |
#define | _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL |
#define | CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) |
#define | _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 |
#define | _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL |
#define | _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL |
#define | _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL |
#define | _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL |
#define | _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL |
#define | _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL |
#define | _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL |
#define | _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL |
#define | CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) |
#define | CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) |
#define | CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) |
#define | CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) |
#define | CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) |
#define | CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) |
#define | CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) |
#define | _CMU_CALCTRL_RESETVALUE 0x00000000UL |
#define | _CMU_CALCTRL_MASK 0x0000007FUL |
#define | _CMU_CALCTRL_UPSEL_SHIFT 0 |
#define | _CMU_CALCTRL_UPSEL_MASK 0x7UL |
#define | _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL |
#define | _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL |
#define | _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL |
#define | _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL |
#define | _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL |
#define | _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL |
#define | CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) |
#define | CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) |
#define | CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) |
#define | CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) |
#define | CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) |
#define | CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) |
#define | _CMU_CALCTRL_DOWNSEL_SHIFT 3 |
#define | _CMU_CALCTRL_DOWNSEL_MASK 0x38UL |
#define | _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL |
#define | _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL |
#define | _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL |
#define | _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL |
#define | _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL |
#define | _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL |
#define | _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL |
#define | CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) |
#define | CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) |
#define | CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) |
#define | CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) |
#define | CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) |
#define | CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) |
#define | CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) |
#define | CMU_CALCTRL_CONT (0x1UL << 6) |
#define | _CMU_CALCTRL_CONT_SHIFT 6 |
#define | _CMU_CALCTRL_CONT_MASK 0x40UL |
#define | _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL |
#define | CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) |
#define | _CMU_CALCNT_RESETVALUE 0x00000000UL |
#define | _CMU_CALCNT_MASK 0x000FFFFFUL |
#define | _CMU_CALCNT_CALCNT_SHIFT 0 |
#define | _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL |
#define | _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL |
#define | CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) |
#define | _CMU_OSCENCMD_RESETVALUE 0x00000000UL |
#define | _CMU_OSCENCMD_MASK 0x000003FFUL |
#define | CMU_OSCENCMD_HFRCOEN (0x1UL << 0) |
#define | _CMU_OSCENCMD_HFRCOEN_SHIFT 0 |
#define | _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL |
#define | _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) |
#define | CMU_OSCENCMD_HFRCODIS (0x1UL << 1) |
#define | _CMU_OSCENCMD_HFRCODIS_SHIFT 1 |
#define | _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL |
#define | _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) |
#define | CMU_OSCENCMD_HFXOEN (0x1UL << 2) |
#define | _CMU_OSCENCMD_HFXOEN_SHIFT 2 |
#define | _CMU_OSCENCMD_HFXOEN_MASK 0x4UL |
#define | _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) |
#define | CMU_OSCENCMD_HFXODIS (0x1UL << 3) |
#define | _CMU_OSCENCMD_HFXODIS_SHIFT 3 |
#define | _CMU_OSCENCMD_HFXODIS_MASK 0x8UL |
#define | _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) |
#define | CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) |
#define | _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 |
#define | _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL |
#define | _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) |
#define | CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) |
#define | _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 |
#define | _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL |
#define | _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) |
#define | CMU_OSCENCMD_LFRCOEN (0x1UL << 6) |
#define | _CMU_OSCENCMD_LFRCOEN_SHIFT 6 |
#define | _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL |
#define | _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) |
#define | CMU_OSCENCMD_LFRCODIS (0x1UL << 7) |
#define | _CMU_OSCENCMD_LFRCODIS_SHIFT 7 |
#define | _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL |
#define | _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) |
#define | CMU_OSCENCMD_LFXOEN (0x1UL << 8) |
#define | _CMU_OSCENCMD_LFXOEN_SHIFT 8 |
#define | _CMU_OSCENCMD_LFXOEN_MASK 0x100UL |
#define | _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) |
#define | CMU_OSCENCMD_LFXODIS (0x1UL << 9) |
#define | _CMU_OSCENCMD_LFXODIS_SHIFT 9 |
#define | _CMU_OSCENCMD_LFXODIS_MASK 0x200UL |
#define | _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) |
#define | _CMU_CMD_RESETVALUE 0x00000000UL |
#define | _CMU_CMD_MASK 0x0000001FUL |
#define | _CMU_CMD_HFCLKSEL_SHIFT 0 |
#define | _CMU_CMD_HFCLKSEL_MASK 0x7UL |
#define | _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL |
#define | _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL |
#define | _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL |
#define | _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL |
#define | _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL |
#define | CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) |
#define | CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) |
#define | CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) |
#define | CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) |
#define | CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) |
#define | CMU_CMD_CALSTART (0x1UL << 3) |
#define | _CMU_CMD_CALSTART_SHIFT 3 |
#define | _CMU_CMD_CALSTART_MASK 0x8UL |
#define | _CMU_CMD_CALSTART_DEFAULT 0x00000000UL |
#define | CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) |
#define | CMU_CMD_CALSTOP (0x1UL << 4) |
#define | _CMU_CMD_CALSTOP_SHIFT 4 |
#define | _CMU_CMD_CALSTOP_MASK 0x10UL |
#define | _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL |
#define | CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) |
#define | _CMU_LFCLKSEL_RESETVALUE 0x00000005UL |
#define | _CMU_LFCLKSEL_MASK 0x0011000FUL |
#define | _CMU_LFCLKSEL_LFA_SHIFT 0 |
#define | _CMU_LFCLKSEL_LFA_MASK 0x3UL |
#define | _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL |
#define | _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL |
#define | _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL |
#define | _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL |
#define | _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL |
#define | CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) |
#define | CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) |
#define | CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) |
#define | CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) |
#define | CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) |
#define | _CMU_LFCLKSEL_LFB_SHIFT 2 |
#define | _CMU_LFCLKSEL_LFB_MASK 0xCUL |
#define | _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL |
#define | _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL |
#define | _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL |
#define | _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL |
#define | _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL |
#define | CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) |
#define | CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) |
#define | CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) |
#define | CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) |
#define | CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) |
#define | CMU_LFCLKSEL_LFAE (0x1UL << 16) |
#define | _CMU_LFCLKSEL_LFAE_SHIFT 16 |
#define | _CMU_LFCLKSEL_LFAE_MASK 0x10000UL |
#define | _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL |
#define | _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL |
#define | _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL |
#define | CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) |
#define | CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) |
#define | CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) |
#define | CMU_LFCLKSEL_LFBE (0x1UL << 20) |
#define | _CMU_LFCLKSEL_LFBE_SHIFT 20 |
#define | _CMU_LFCLKSEL_LFBE_MASK 0x100000UL |
#define | _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL |
#define | _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL |
#define | _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL |
#define | CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) |
#define | CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) |
#define | CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) |
#define | _CMU_STATUS_RESETVALUE 0x00000403UL |
#define | _CMU_STATUS_MASK 0x00007FFFUL |
#define | CMU_STATUS_HFRCOENS (0x1UL << 0) |
#define | _CMU_STATUS_HFRCOENS_SHIFT 0 |
#define | _CMU_STATUS_HFRCOENS_MASK 0x1UL |
#define | _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL |
#define | CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) |
#define | CMU_STATUS_HFRCORDY (0x1UL << 1) |
#define | _CMU_STATUS_HFRCORDY_SHIFT 1 |
#define | _CMU_STATUS_HFRCORDY_MASK 0x2UL |
#define | _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL |
#define | CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) |
#define | CMU_STATUS_HFXOENS (0x1UL << 2) |
#define | _CMU_STATUS_HFXOENS_SHIFT 2 |
#define | _CMU_STATUS_HFXOENS_MASK 0x4UL |
#define | _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) |
#define | CMU_STATUS_HFXORDY (0x1UL << 3) |
#define | _CMU_STATUS_HFXORDY_SHIFT 3 |
#define | _CMU_STATUS_HFXORDY_MASK 0x8UL |
#define | _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) |
#define | CMU_STATUS_AUXHFRCOENS (0x1UL << 4) |
#define | _CMU_STATUS_AUXHFRCOENS_SHIFT 4 |
#define | _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL |
#define | _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) |
#define | CMU_STATUS_AUXHFRCORDY (0x1UL << 5) |
#define | _CMU_STATUS_AUXHFRCORDY_SHIFT 5 |
#define | _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL |
#define | _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) |
#define | CMU_STATUS_LFRCOENS (0x1UL << 6) |
#define | _CMU_STATUS_LFRCOENS_SHIFT 6 |
#define | _CMU_STATUS_LFRCOENS_MASK 0x40UL |
#define | _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) |
#define | CMU_STATUS_LFRCORDY (0x1UL << 7) |
#define | _CMU_STATUS_LFRCORDY_SHIFT 7 |
#define | _CMU_STATUS_LFRCORDY_MASK 0x80UL |
#define | _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) |
#define | CMU_STATUS_LFXOENS (0x1UL << 8) |
#define | _CMU_STATUS_LFXOENS_SHIFT 8 |
#define | _CMU_STATUS_LFXOENS_MASK 0x100UL |
#define | _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) |
#define | CMU_STATUS_LFXORDY (0x1UL << 9) |
#define | _CMU_STATUS_LFXORDY_SHIFT 9 |
#define | _CMU_STATUS_LFXORDY_MASK 0x200UL |
#define | _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) |
#define | CMU_STATUS_HFRCOSEL (0x1UL << 10) |
#define | _CMU_STATUS_HFRCOSEL_SHIFT 10 |
#define | _CMU_STATUS_HFRCOSEL_MASK 0x400UL |
#define | _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL |
#define | CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) |
#define | CMU_STATUS_HFXOSEL (0x1UL << 11) |
#define | _CMU_STATUS_HFXOSEL_SHIFT 11 |
#define | _CMU_STATUS_HFXOSEL_MASK 0x800UL |
#define | _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL |
#define | CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) |
#define | CMU_STATUS_LFRCOSEL (0x1UL << 12) |
#define | _CMU_STATUS_LFRCOSEL_SHIFT 12 |
#define | _CMU_STATUS_LFRCOSEL_MASK 0x1000UL |
#define | _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) |
#define | CMU_STATUS_LFXOSEL (0x1UL << 13) |
#define | _CMU_STATUS_LFXOSEL_SHIFT 13 |
#define | _CMU_STATUS_LFXOSEL_MASK 0x2000UL |
#define | _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) |
#define | CMU_STATUS_CALBSY (0x1UL << 14) |
#define | _CMU_STATUS_CALBSY_SHIFT 14 |
#define | _CMU_STATUS_CALBSY_MASK 0x4000UL |
#define | _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) |
#define | _CMU_IF_RESETVALUE 0x00000001UL |
#define | _CMU_IF_MASK 0x0000007FUL |
#define | CMU_IF_HFRCORDY (0x1UL << 0) |
#define | _CMU_IF_HFRCORDY_SHIFT 0 |
#define | _CMU_IF_HFRCORDY_MASK 0x1UL |
#define | _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL |
#define | CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) |
#define | CMU_IF_HFXORDY (0x1UL << 1) |
#define | _CMU_IF_HFXORDY_SHIFT 1 |
#define | _CMU_IF_HFXORDY_MASK 0x2UL |
#define | _CMU_IF_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) |
#define | CMU_IF_LFRCORDY (0x1UL << 2) |
#define | _CMU_IF_LFRCORDY_SHIFT 2 |
#define | _CMU_IF_LFRCORDY_MASK 0x4UL |
#define | _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) |
#define | CMU_IF_LFXORDY (0x1UL << 3) |
#define | _CMU_IF_LFXORDY_SHIFT 3 |
#define | _CMU_IF_LFXORDY_MASK 0x8UL |
#define | _CMU_IF_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) |
#define | CMU_IF_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IF_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IF_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IF_CALRDY (0x1UL << 5) |
#define | _CMU_IF_CALRDY_SHIFT 5 |
#define | _CMU_IF_CALRDY_MASK 0x20UL |
#define | _CMU_IF_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) |
#define | CMU_IF_CALOF (0x1UL << 6) |
#define | _CMU_IF_CALOF_SHIFT 6 |
#define | _CMU_IF_CALOF_MASK 0x40UL |
#define | _CMU_IF_CALOF_DEFAULT 0x00000000UL |
#define | CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) |
#define | _CMU_IFS_RESETVALUE 0x00000000UL |
#define | _CMU_IFS_MASK 0x0000007FUL |
#define | CMU_IFS_HFRCORDY (0x1UL << 0) |
#define | _CMU_IFS_HFRCORDY_SHIFT 0 |
#define | _CMU_IFS_HFRCORDY_MASK 0x1UL |
#define | _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) |
#define | CMU_IFS_HFXORDY (0x1UL << 1) |
#define | _CMU_IFS_HFXORDY_SHIFT 1 |
#define | _CMU_IFS_HFXORDY_MASK 0x2UL |
#define | _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) |
#define | CMU_IFS_LFRCORDY (0x1UL << 2) |
#define | _CMU_IFS_LFRCORDY_SHIFT 2 |
#define | _CMU_IFS_LFRCORDY_MASK 0x4UL |
#define | _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) |
#define | CMU_IFS_LFXORDY (0x1UL << 3) |
#define | _CMU_IFS_LFXORDY_SHIFT 3 |
#define | _CMU_IFS_LFXORDY_MASK 0x8UL |
#define | _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) |
#define | CMU_IFS_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IFS_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IFS_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IFS_CALRDY (0x1UL << 5) |
#define | _CMU_IFS_CALRDY_SHIFT 5 |
#define | _CMU_IFS_CALRDY_MASK 0x20UL |
#define | _CMU_IFS_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) |
#define | CMU_IFS_CALOF (0x1UL << 6) |
#define | _CMU_IFS_CALOF_SHIFT 6 |
#define | _CMU_IFS_CALOF_MASK 0x40UL |
#define | _CMU_IFS_CALOF_DEFAULT 0x00000000UL |
#define | CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) |
#define | _CMU_IFC_RESETVALUE 0x00000000UL |
#define | _CMU_IFC_MASK 0x0000007FUL |
#define | CMU_IFC_HFRCORDY (0x1UL << 0) |
#define | _CMU_IFC_HFRCORDY_SHIFT 0 |
#define | _CMU_IFC_HFRCORDY_MASK 0x1UL |
#define | _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) |
#define | CMU_IFC_HFXORDY (0x1UL << 1) |
#define | _CMU_IFC_HFXORDY_SHIFT 1 |
#define | _CMU_IFC_HFXORDY_MASK 0x2UL |
#define | _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) |
#define | CMU_IFC_LFRCORDY (0x1UL << 2) |
#define | _CMU_IFC_LFRCORDY_SHIFT 2 |
#define | _CMU_IFC_LFRCORDY_MASK 0x4UL |
#define | _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) |
#define | CMU_IFC_LFXORDY (0x1UL << 3) |
#define | _CMU_IFC_LFXORDY_SHIFT 3 |
#define | _CMU_IFC_LFXORDY_MASK 0x8UL |
#define | _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) |
#define | CMU_IFC_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IFC_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IFC_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IFC_CALRDY (0x1UL << 5) |
#define | _CMU_IFC_CALRDY_SHIFT 5 |
#define | _CMU_IFC_CALRDY_MASK 0x20UL |
#define | _CMU_IFC_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) |
#define | CMU_IFC_CALOF (0x1UL << 6) |
#define | _CMU_IFC_CALOF_SHIFT 6 |
#define | _CMU_IFC_CALOF_MASK 0x40UL |
#define | _CMU_IFC_CALOF_DEFAULT 0x00000000UL |
#define | CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) |
#define | _CMU_IEN_RESETVALUE 0x00000000UL |
#define | _CMU_IEN_MASK 0x0000007FUL |
#define | CMU_IEN_HFRCORDY (0x1UL << 0) |
#define | _CMU_IEN_HFRCORDY_SHIFT 0 |
#define | _CMU_IEN_HFRCORDY_MASK 0x1UL |
#define | _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) |
#define | CMU_IEN_HFXORDY (0x1UL << 1) |
#define | _CMU_IEN_HFXORDY_SHIFT 1 |
#define | _CMU_IEN_HFXORDY_MASK 0x2UL |
#define | _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) |
#define | CMU_IEN_LFRCORDY (0x1UL << 2) |
#define | _CMU_IEN_LFRCORDY_SHIFT 2 |
#define | _CMU_IEN_LFRCORDY_MASK 0x4UL |
#define | _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) |
#define | CMU_IEN_LFXORDY (0x1UL << 3) |
#define | _CMU_IEN_LFXORDY_SHIFT 3 |
#define | _CMU_IEN_LFXORDY_MASK 0x8UL |
#define | _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) |
#define | CMU_IEN_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IEN_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IEN_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IEN_CALRDY (0x1UL << 5) |
#define | _CMU_IEN_CALRDY_SHIFT 5 |
#define | _CMU_IEN_CALRDY_MASK 0x20UL |
#define | _CMU_IEN_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) |
#define | CMU_IEN_CALOF (0x1UL << 6) |
#define | _CMU_IEN_CALOF_SHIFT 6 |
#define | _CMU_IEN_CALOF_MASK 0x40UL |
#define | _CMU_IEN_CALOF_DEFAULT 0x00000000UL |
#define | CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) |
#define | _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_HFCORECLKEN0_MASK 0x00000033UL |
#define | CMU_HFCORECLKEN0_DMA (0x1UL << 0) |
#define | _CMU_HFCORECLKEN0_DMA_SHIFT 0 |
#define | _CMU_HFCORECLKEN0_DMA_MASK 0x1UL |
#define | _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL |
#define | CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) |
#define | CMU_HFCORECLKEN0_AES (0x1UL << 1) |
#define | _CMU_HFCORECLKEN0_AES_SHIFT 1 |
#define | _CMU_HFCORECLKEN0_AES_MASK 0x2UL |
#define | _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL |
#define | CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) |
#define | CMU_HFCORECLKEN0_LE (0x1UL << 4) |
#define | _CMU_HFCORECLKEN0_LE_SHIFT 4 |
#define | _CMU_HFCORECLKEN0_LE_MASK 0x10UL |
#define | _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL |
#define | CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) |
#define | CMU_HFCORECLKEN0_EBI (0x1UL << 5) |
#define | _CMU_HFCORECLKEN0_EBI_SHIFT 5 |
#define | _CMU_HFCORECLKEN0_EBI_MASK 0x20UL |
#define | _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL |
#define | CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5) |
#define | _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL |
#define | CMU_HFPERCLKEN0_USART0 (0x1UL << 0) |
#define | _CMU_HFPERCLKEN0_USART0_SHIFT 0 |
#define | _CMU_HFPERCLKEN0_USART0_MASK 0x1UL |
#define | _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) |
#define | CMU_HFPERCLKEN0_USART1 (0x1UL << 1) |
#define | _CMU_HFPERCLKEN0_USART1_SHIFT 1 |
#define | _CMU_HFPERCLKEN0_USART1_MASK 0x2UL |
#define | _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) |
#define | CMU_HFPERCLKEN0_USART2 (0x1UL << 2) |
#define | _CMU_HFPERCLKEN0_USART2_SHIFT 2 |
#define | _CMU_HFPERCLKEN0_USART2_MASK 0x4UL |
#define | _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) |
#define | CMU_HFPERCLKEN0_UART0 (0x1UL << 3) |
#define | _CMU_HFPERCLKEN0_UART0_SHIFT 3 |
#define | _CMU_HFPERCLKEN0_UART0_MASK 0x8UL |
#define | _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3) |
#define | CMU_HFPERCLKEN0_UART1 (0x1UL << 4) |
#define | _CMU_HFPERCLKEN0_UART1_SHIFT 4 |
#define | _CMU_HFPERCLKEN0_UART1_MASK 0x10UL |
#define | _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4) |
#define | CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) |
#define | _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 |
#define | _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL |
#define | _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) |
#define | CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) |
#define | _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 |
#define | _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL |
#define | _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) |
#define | CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) |
#define | _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 |
#define | _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL |
#define | _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) |
#define | CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) |
#define | _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 |
#define | _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL |
#define | _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) |
#define | CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) |
#define | _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 |
#define | _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL |
#define | _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) |
#define | CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) |
#define | _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 |
#define | _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL |
#define | _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) |
#define | CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) |
#define | _CMU_HFPERCLKEN0_I2C0_SHIFT 11 |
#define | _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL |
#define | _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) |
#define | CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) |
#define | _CMU_HFPERCLKEN0_I2C1_SHIFT 12 |
#define | _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL |
#define | _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) |
#define | CMU_HFPERCLKEN0_GPIO (0x1UL << 13) |
#define | _CMU_HFPERCLKEN0_GPIO_SHIFT 13 |
#define | _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL |
#define | _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) |
#define | CMU_HFPERCLKEN0_VCMP (0x1UL << 14) |
#define | _CMU_HFPERCLKEN0_VCMP_SHIFT 14 |
#define | _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL |
#define | _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) |
#define | CMU_HFPERCLKEN0_PRS (0x1UL << 15) |
#define | _CMU_HFPERCLKEN0_PRS_SHIFT 15 |
#define | _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL |
#define | _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) |
#define | CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) |
#define | _CMU_HFPERCLKEN0_ADC0_SHIFT 16 |
#define | _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL |
#define | _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) |
#define | CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) |
#define | _CMU_HFPERCLKEN0_DAC0_SHIFT 17 |
#define | _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL |
#define | _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) |
#define | _CMU_SYNCBUSY_RESETVALUE 0x00000000UL |
#define | _CMU_SYNCBUSY_MASK 0x00000055UL |
#define | CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) |
#define | _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 |
#define | _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL |
#define | _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) |
#define | CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) |
#define | _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 |
#define | _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL |
#define | _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) |
#define | CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) |
#define | _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 |
#define | _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL |
#define | _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) |
#define | CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) |
#define | _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 |
#define | _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL |
#define | _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) |
#define | _CMU_FREEZE_RESETVALUE 0x00000000UL |
#define | _CMU_FREEZE_MASK 0x00000001UL |
#define | CMU_FREEZE_REGFREEZE (0x1UL << 0) |
#define | _CMU_FREEZE_REGFREEZE_SHIFT 0 |
#define | _CMU_FREEZE_REGFREEZE_MASK 0x1UL |
#define | _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL |
#define | _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL |
#define | _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL |
#define | CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) |
#define | CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) |
#define | CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) |
#define | _CMU_LFACLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_LFACLKEN0_MASK 0x00000007UL |
#define | CMU_LFACLKEN0_LESENSE (0x1UL << 0) |
#define | _CMU_LFACLKEN0_LESENSE_SHIFT 0 |
#define | _CMU_LFACLKEN0_LESENSE_MASK 0x1UL |
#define | _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL |
#define | CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) |
#define | CMU_LFACLKEN0_RTC (0x1UL << 1) |
#define | _CMU_LFACLKEN0_RTC_SHIFT 1 |
#define | _CMU_LFACLKEN0_RTC_MASK 0x2UL |
#define | _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL |
#define | CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) |
#define | CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) |
#define | _CMU_LFACLKEN0_LETIMER0_SHIFT 2 |
#define | _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL |
#define | _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL |
#define | CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) |
#define | _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_LFBCLKEN0_MASK 0x00000003UL |
#define | CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) |
#define | _CMU_LFBCLKEN0_LEUART0_SHIFT 0 |
#define | _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL |
#define | _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL |
#define | CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) |
#define | CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) |
#define | _CMU_LFBCLKEN0_LEUART1_SHIFT 1 |
#define | _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL |
#define | _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL |
#define | CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) |
#define | _CMU_LFAPRESC0_RESETVALUE 0x00000000UL |
#define | _CMU_LFAPRESC0_MASK 0x00000FF3UL |
#define | _CMU_LFAPRESC0_LESENSE_SHIFT 0 |
#define | _CMU_LFAPRESC0_LESENSE_MASK 0x3UL |
#define | _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL |
#define | _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL |
#define | _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL |
#define | _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL |
#define | CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) |
#define | CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) |
#define | CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) |
#define | CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) |
#define | _CMU_LFAPRESC0_RTC_SHIFT 4 |
#define | _CMU_LFAPRESC0_RTC_MASK 0xF0UL |
#define | _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL |
#define | _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL |
#define | _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL |
#define | _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL |
#define | _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL |
#define | _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL |
#define | _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL |
#define | _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL |
#define | _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL |
#define | _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL |
#define | _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL |
#define | _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL |
#define | _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL |
#define | _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL |
#define | _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL |
#define | _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL |
#define | CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) |
#define | CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) |
#define | _CMU_LFAPRESC0_LETIMER0_SHIFT 8 |
#define | _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL |
#define | CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) |
#define | CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) |
#define | _CMU_LFBPRESC0_RESETVALUE 0x00000000UL |
#define | _CMU_LFBPRESC0_MASK 0x00000033UL |
#define | _CMU_LFBPRESC0_LEUART0_SHIFT 0 |
#define | _CMU_LFBPRESC0_LEUART0_MASK 0x3UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL |
#define | CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) |
#define | CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) |
#define | CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) |
#define | CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) |
#define | _CMU_LFBPRESC0_LEUART1_SHIFT 4 |
#define | _CMU_LFBPRESC0_LEUART1_MASK 0x30UL |
#define | _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL |
#define | _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL |
#define | _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL |
#define | _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL |
#define | CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) |
#define | CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) |
#define | CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) |
#define | CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) |
#define | _CMU_PCNTCTRL_RESETVALUE 0x00000000UL |
#define | _CMU_PCNTCTRL_MASK 0x0000003FUL |
#define | CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) |
#define | _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 |
#define | _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL |
#define | _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL |
#define | CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) |
#define | CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL |
#define | CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) |
#define | CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) |
#define | CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) |
#define | CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) |
#define | _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 |
#define | _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL |
#define | _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL |
#define | CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) |
#define | CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) |
#define | _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 |
#define | _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL |
#define | _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL |
#define | CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) |
#define | CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) |
#define | CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) |
#define | CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) |
#define | _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 |
#define | _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL |
#define | _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL |
#define | CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) |
#define | CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) |
#define | _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 |
#define | _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL |
#define | _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL |
#define | CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) |
#define | CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) |
#define | CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) |
#define | _CMU_ROUTE_RESETVALUE 0x00000000UL |
#define | _CMU_ROUTE_MASK 0x0000001FUL |
#define | CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) |
#define | _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 |
#define | _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL |
#define | _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL |
#define | CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) |
#define | CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) |
#define | _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 |
#define | _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL |
#define | _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL |
#define | CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) |
#define | _CMU_ROUTE_LOCATION_SHIFT 2 |
#define | _CMU_ROUTE_LOCATION_MASK 0x1CUL |
#define | _CMU_ROUTE_LOCATION_LOC0 0x00000000UL |
#define | _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL |
#define | _CMU_ROUTE_LOCATION_LOC1 0x00000001UL |
#define | _CMU_ROUTE_LOCATION_LOC2 0x00000002UL |
#define | CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) |
#define | CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) |
#define | CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) |
#define | CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) |
#define | _CMU_LOCK_RESETVALUE 0x00000000UL |
#define | _CMU_LOCK_MASK 0x0000FFFFUL |
#define | _CMU_LOCK_LOCKKEY_SHIFT 0 |
#define | _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL |
#define | _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL |
#define | _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL |
#define | _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL |
#define | _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL |
#define | _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL |
#define | CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) |
#define | CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) |
#define | CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) |
#define | CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) |
#define | CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) |
#define | _PRS_SWPULSE_RESETVALUE 0x00000000UL |
#define | _PRS_SWPULSE_MASK 0x00000FFFUL |
#define | PRS_SWPULSE_CH0PULSE (0x1UL << 0) |
#define | _PRS_SWPULSE_CH0PULSE_SHIFT 0 |
#define | _PRS_SWPULSE_CH0PULSE_MASK 0x1UL |
#define | _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) |
#define | PRS_SWPULSE_CH1PULSE (0x1UL << 1) |
#define | _PRS_SWPULSE_CH1PULSE_SHIFT 1 |
#define | _PRS_SWPULSE_CH1PULSE_MASK 0x2UL |
#define | _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) |
#define | PRS_SWPULSE_CH2PULSE (0x1UL << 2) |
#define | _PRS_SWPULSE_CH2PULSE_SHIFT 2 |
#define | _PRS_SWPULSE_CH2PULSE_MASK 0x4UL |
#define | _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) |
#define | PRS_SWPULSE_CH3PULSE (0x1UL << 3) |
#define | _PRS_SWPULSE_CH3PULSE_SHIFT 3 |
#define | _PRS_SWPULSE_CH3PULSE_MASK 0x8UL |
#define | _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) |
#define | PRS_SWPULSE_CH4PULSE (0x1UL << 4) |
#define | _PRS_SWPULSE_CH4PULSE_SHIFT 4 |
#define | _PRS_SWPULSE_CH4PULSE_MASK 0x10UL |
#define | _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) |
#define | PRS_SWPULSE_CH5PULSE (0x1UL << 5) |
#define | _PRS_SWPULSE_CH5PULSE_SHIFT 5 |
#define | _PRS_SWPULSE_CH5PULSE_MASK 0x20UL |
#define | _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) |
#define | PRS_SWPULSE_CH6PULSE (0x1UL << 6) |
#define | _PRS_SWPULSE_CH6PULSE_SHIFT 6 |
#define | _PRS_SWPULSE_CH6PULSE_MASK 0x40UL |
#define | _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) |
#define | PRS_SWPULSE_CH7PULSE (0x1UL << 7) |
#define | _PRS_SWPULSE_CH7PULSE_SHIFT 7 |
#define | _PRS_SWPULSE_CH7PULSE_MASK 0x80UL |
#define | _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) |
#define | PRS_SWPULSE_CH8PULSE (0x1UL << 8) |
#define | _PRS_SWPULSE_CH8PULSE_SHIFT 8 |
#define | _PRS_SWPULSE_CH8PULSE_MASK 0x100UL |
#define | _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) |
#define | PRS_SWPULSE_CH9PULSE (0x1UL << 9) |
#define | _PRS_SWPULSE_CH9PULSE_SHIFT 9 |
#define | _PRS_SWPULSE_CH9PULSE_MASK 0x200UL |
#define | _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) |
#define | PRS_SWPULSE_CH10PULSE (0x1UL << 10) |
#define | _PRS_SWPULSE_CH10PULSE_SHIFT 10 |
#define | _PRS_SWPULSE_CH10PULSE_MASK 0x400UL |
#define | _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) |
#define | PRS_SWPULSE_CH11PULSE (0x1UL << 11) |
#define | _PRS_SWPULSE_CH11PULSE_SHIFT 11 |
#define | _PRS_SWPULSE_CH11PULSE_MASK 0x800UL |
#define | _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) |
#define | _PRS_SWLEVEL_RESETVALUE 0x00000000UL |
#define | _PRS_SWLEVEL_MASK 0x00000FFFUL |
#define | PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) |
#define | _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 |
#define | _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL |
#define | _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) |
#define | PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) |
#define | _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 |
#define | _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL |
#define | _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) |
#define | PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) |
#define | _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 |
#define | _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL |
#define | _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) |
#define | PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) |
#define | _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 |
#define | _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL |
#define | _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) |
#define | PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) |
#define | _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 |
#define | _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL |
#define | _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) |
#define | PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) |
#define | _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 |
#define | _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL |
#define | _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) |
#define | PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) |
#define | _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 |
#define | _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL |
#define | _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) |
#define | PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) |
#define | _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 |
#define | _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL |
#define | _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) |
#define | PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) |
#define | _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 |
#define | _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL |
#define | _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) |
#define | PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) |
#define | _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 |
#define | _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL |
#define | _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) |
#define | PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) |
#define | _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 |
#define | _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL |
#define | _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) |
#define | PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) |
#define | _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 |
#define | _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL |
#define | _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) |
#define | _PRS_ROUTE_RESETVALUE 0x00000000UL |
#define | _PRS_ROUTE_MASK 0x0000070FUL |
#define | PRS_ROUTE_CH0PEN (0x1UL << 0) |
#define | _PRS_ROUTE_CH0PEN_SHIFT 0 |
#define | _PRS_ROUTE_CH0PEN_MASK 0x1UL |
#define | _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL |
#define | PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) |
#define | PRS_ROUTE_CH1PEN (0x1UL << 1) |
#define | _PRS_ROUTE_CH1PEN_SHIFT 1 |
#define | _PRS_ROUTE_CH1PEN_MASK 0x2UL |
#define | _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL |
#define | PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) |
#define | PRS_ROUTE_CH2PEN (0x1UL << 2) |
#define | _PRS_ROUTE_CH2PEN_SHIFT 2 |
#define | _PRS_ROUTE_CH2PEN_MASK 0x4UL |
#define | _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL |
#define | PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) |
#define | PRS_ROUTE_CH3PEN (0x1UL << 3) |
#define | _PRS_ROUTE_CH3PEN_SHIFT 3 |
#define | _PRS_ROUTE_CH3PEN_MASK 0x8UL |
#define | _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL |
#define | PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) |
#define | _PRS_ROUTE_LOCATION_SHIFT 8 |
#define | _PRS_ROUTE_LOCATION_MASK 0x700UL |
#define | _PRS_ROUTE_LOCATION_LOC0 0x00000000UL |
#define | _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL |
#define | _PRS_ROUTE_LOCATION_LOC1 0x00000001UL |
#define | PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) |
#define | PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) |
#define | PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) |
#define | _PRS_CH_CTRL_RESETVALUE 0x00000000UL |
#define | _PRS_CH_CTRL_MASK 0x133F0007UL |
#define | _PRS_CH_CTRL_SIGSEL_SHIFT 0 |
#define | _PRS_CH_CTRL_SIGSEL_MASK 0x7UL |
#define | _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_UART0TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_UART1TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_UART0RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_UART1RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL |
#define | _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL |
#define | PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_UART0TXC (_PRS_CH_CTRL_SIGSEL_UART0TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_UART1TXC (_PRS_CH_CTRL_SIGSEL_UART1TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_UART0RXDATAV (_PRS_CH_CTRL_SIGSEL_UART0RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_UART1RXDATAV (_PRS_CH_CTRL_SIGSEL_UART1RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) |
#define | PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) |
#define | _PRS_CH_CTRL_SOURCESEL_SHIFT 16 |
#define | _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL |
#define | _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL |
#define | _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL |
#define | _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL |
#define | _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL |
#define | _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL |
#define | _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL |
#define | _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL |
#define | _PRS_CH_CTRL_SOURCESEL_UART0 0x00000029UL |
#define | _PRS_CH_CTRL_SOURCESEL_UART1 0x0000002AUL |
#define | _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL |
#define | _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL |
#define | _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL |
#define | _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL |
#define | _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL |
#define | _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL |
#define | _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL |
#define | PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) |
#define | PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) |
#define | PRS_CH_CTRL_SOURCESEL_UART0 (_PRS_CH_CTRL_SOURCESEL_UART0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_UART1 (_PRS_CH_CTRL_SOURCESEL_UART1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) |
#define | PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) |
#define | PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) |
#define | PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) |
#define | PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) |
#define | PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) |
#define | _PRS_CH_CTRL_EDSEL_SHIFT 24 |
#define | _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL |
#define | _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL |
#define | _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL |
#define | _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL |
#define | _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL |
#define | _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL |
#define | PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) |
#define | PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) |
#define | PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) |
#define | PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) |
#define | PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) |
#define | PRS_CH_CTRL_ASYNC (0x1UL << 28) |
#define | _PRS_CH_CTRL_ASYNC_SHIFT 28 |
#define | _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL |
#define | _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL |
#define | PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) |
#define | MSC_UNLOCK_CODE 0x1B71 |
#define | EMU_UNLOCK_CODE 0xADE8 |
#define | CMU_UNLOCK_CODE 0x580E |
#define | TIMER_UNLOCK_CODE 0xCE80 |
#define | GPIO_UNLOCK_CODE 0xA534 |
#define | BURTC_UNLOCK_CODE 0xAEE8 |
#define | SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register. | |
Typedefs | |
typedef enum IRQn | IRQn_Type |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, USART0_RX_IRQn = 3, USART0_TX_IRQn = 4, ACMP0_IRQn = 6, ADC0_IRQn = 7, DAC0_IRQn = 8, I2C0_IRQn = 9, I2C1_IRQn = 10, GPIO_ODD_IRQn = 11, TIMER1_IRQn = 12, TIMER2_IRQn = 13, TIMER3_IRQn = 14, USART1_RX_IRQn = 15, USART1_TX_IRQn = 16, LESENSE_IRQn = 17, USART2_RX_IRQn = 18, USART2_TX_IRQn = 19, UART0_RX_IRQn = 20, UART0_TX_IRQn = 21, UART1_RX_IRQn = 22, UART1_TX_IRQn = 23, LEUART0_IRQn = 24, LEUART1_IRQn = 25, LETIMER0_IRQn = 26, PCNT0_IRQn = 27, PCNT1_IRQn = 28, PCNT2_IRQn = 29, RTC_IRQn = 30, BURTC_IRQn = 31, CMU_IRQn = 32, VCMP_IRQn = 33, MSC_IRQn = 35, AES_IRQn = 36, EBI_IRQn = 37, EMU_IRQn = 38 } |
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file efm32lg295f256.h.