The actual communication between the EFM32 chips and the ethernet controller is done via SPI using the driver from this file. More...
![]() |
Defines | |
#define | BAUDRATE_100K 100000 |
Baudrate 100.000. | |
#define | ETH_USART_USED USART1 |
The used USART. | |
#define | ETH_USART_CLK cmuClock_USART1 |
The used USART clock. | |
#define | BOGUS_BYTE 0xFF |
Bogus byte used for receiving via SPI. | |
#define | REG_MASK 0x03 |
Register mask. | |
#define | OPCODE_REG_READ 0x00 |
Opcode for reading a register. | |
#define | OPCODE_REG_WRITE 0x40 |
Opcode for writing a register. | |
#define | OPCODE_FIFO_READ 0x80 |
Opcode for reading from FIFO. | |
#define | OPCODE_FIFO_WRITE 0xC0 |
Opcode for writing to FIFO. | |
#define | SHIFT_VAL 0x02 |
Shift value - 2 bits. | |
#define | ADDRESS_MS2B_MASK 0xC0 |
Most semnificative 2 Bytes of the address mask. | |
#define | ADDRESS_MS2B_POS 0x06 |
Most semnificative 2 Bytes of the address position. | |
#define | SPI_MOSI_PIN 0 |
SPI MOSI Pin. | |
#define | SPI_MOSI_PORT gpioPortD |
SPI MOSI Port. | |
#define | SPI_MISO_PIN 1 |
SPI MISO Pin. | |
#define | SPI_MISO_PORT gpioPortD |
SPI MISO Port. | |
#define | SPI_CLK_PIN 2 |
SPI CLOCK Pin. | |
#define | SPI_CLK_PORT gpioPortD |
SPI CLOCK Port. | |
#define | SPI_CS_PIN 3 |
SPI CHIP SELECT Pin. | |
#define | SPI_CS_PORT gpioPortD |
SPI CHIP SELECT Port. | |
Functions | |
void | ETHSPI_Init (void) |
ETHSPI_Init Initialize SPI interface to Ethernet controller. | |
void | ETHSPI_ReadRegister (uint8_t reg, int numBytes, void *data) |
Read ethernet controller register. | |
void | ETHSPI_WriteRegister (uint8_t reg, int numBytes, void *data) |
Write ethernet controller register. | |
void | ETHSPI_StartWriteFIFO (void) |
Start writing to the ethernet controller FIFO. | |
void | ETHSPI_StartReadFIFO (void) |
Start reading from the ethernet controller FIFO. | |
void | ETHSPI_StopFIFO (void) |
Stop read/write the ethernet controller FIFO. | |
void | ETHSPI_ReadFifoContinue (int numBytes, uint8_t *data) |
Continue reading ethernet controller FIFO. | |
void | ETHSPI_WriteFifoContinue (int numBytes, uint8_t *data) |
Continue writing ethernet controller FIFO. |
The actual communication between the EFM32 chips and the ethernet controller is done via SPI using the driver from this file.
#define ADDRESS_MS2B_MASK 0xC0 |
Most semnificative 2 Bytes of the address mask.
Definition at line 46 of file ethspi.h.
Referenced by ETHSPI_ReadRegister(), and ETHSPI_WriteRegister().
#define ADDRESS_MS2B_POS 0x06 |
Most semnificative 2 Bytes of the address position.
Definition at line 47 of file ethspi.h.
Referenced by ETHSPI_ReadRegister(), and ETHSPI_WriteRegister().
#define BOGUS_BYTE 0xFF |
Bogus byte used for receiving via SPI.
Definition at line 39 of file ethspi.h.
Referenced by ETHSPI_ReadFifoContinue(), and ETHSPI_ReadRegister().
#define ETH_USART_CLK cmuClock_USART1 |
#define ETH_USART_USED USART1 |
#define OPCODE_FIFO_READ 0x80 |
Opcode for reading from FIFO.
Definition at line 43 of file ethspi.h.
Referenced by ETHSPI_StartReadFIFO().
#define OPCODE_FIFO_WRITE 0xC0 |
Opcode for writing to FIFO.
Definition at line 44 of file ethspi.h.
Referenced by ETHSPI_StartWriteFIFO().
#define OPCODE_REG_WRITE 0x40 |
Opcode for writing a register.
Definition at line 42 of file ethspi.h.
Referenced by ETHSPI_WriteRegister().
#define REG_MASK 0x03 |
Register mask.
Definition at line 40 of file ethspi.h.
Referenced by ETHSPI_ReadRegister(), and ETHSPI_WriteRegister().
#define SHIFT_VAL 0x02 |
Shift value - 2 bits.
Definition at line 45 of file ethspi.h.
Referenced by ETHSPI_ReadRegister(), and ETHSPI_WriteRegister().
#define SPI_CLK_PIN 2 |
#define SPI_CLK_PORT gpioPortD |
#define SPI_CS_PIN 3 |
SPI CHIP SELECT Pin.
Definition at line 57 of file ethspi.h.
Referenced by ETHSPI_Init(), and ETHSPI_SetChipSelect().
#define SPI_CS_PORT gpioPortD |
SPI CHIP SELECT Port.
Definition at line 58 of file ethspi.h.
Referenced by ETHSPI_Init(), and ETHSPI_SetChipSelect().
#define SPI_MISO_PIN 1 |
#define SPI_MISO_PORT gpioPortD |
#define SPI_MOSI_PIN 0 |
#define SPI_MOSI_PORT gpioPortD |
void ETHSPI_Init | ( | void | ) |
ETHSPI_Init Initialize SPI interface to Ethernet controller.
Definition at line 55 of file ethspi.c.
References ETH_USART_CLK, ETH_USART_USED, SPI_CLK_PIN, SPI_CLK_PORT, SPI_CS_PIN, SPI_CS_PORT, SPI_MISO_PIN, SPI_MISO_PORT, SPI_MOSI_PIN, and SPI_MOSI_PORT.
Referenced by KSZ8851SNL_Init().
void ETHSPI_ReadFifoContinue | ( | int | numBytes, | |
uint8_t * | data | |||
) |
Continue reading ethernet controller FIFO.
[in] | numBytes | Number of bytes to read, 1-12K |
[out] | data | Actual bytes to read |
Definition at line 236 of file ethspi.c.
References BOGUS_BYTE, ETHSPI_XferSpi(), and rxBuffer.
Referenced by KSZ8851SNL_Receive().
void ETHSPI_ReadRegister | ( | uint8_t | reg, | |
int | numBytes, | |||
void * | data | |||
) |
Read ethernet controller register.
[in] | reg | Register to read |
[in] | numBytes | Number of bytes to read, should be 1-4 |
[out] | data | Pointer to element where data should be put |
Definition at line 129 of file ethspi.c.
References ADDRESS_MS2B_MASK, ADDRESS_MS2B_POS, BOGUS_BYTE, ETHSPI_SetChipSelect(), ETHSPI_XferSpi(), REG_MASK, rxBuffer, and SHIFT_VAL.
Referenced by KSZ8851SNL_CheckIrqStat(), KSZ8851SNL_CurrFrameSize(), KSZ8851SNL_Init(), KSZ8851SNL_InitiateLongTransmit(), KSZ8851SNL_ReadMIBCounters(), KSZ8851SNL_Receive(), KSZ8851SNL_ReleaseIncosistentFrame(), KSZ8851SNL_Send(), and KSZ8851SNL_TerminateLongTransmit().
void ETHSPI_StartReadFIFO | ( | void | ) |
Start reading from the ethernet controller FIFO.
Definition at line 200 of file ethspi.c.
References ETHSPI_SetChipSelect(), ETHSPI_XferSpi(), and OPCODE_FIFO_READ.
Referenced by KSZ8851SNL_Receive().
void ETHSPI_StartWriteFIFO | ( | void | ) |
Start writing to the ethernet controller FIFO.
Definition at line 212 of file ethspi.c.
References ETHSPI_SetChipSelect(), ETHSPI_XferSpi(), and OPCODE_FIFO_WRITE.
Referenced by KSZ8851SNL_InitiateLongTransmit(), and KSZ8851SNL_Send().
void ETHSPI_StopFIFO | ( | void | ) |
Stop read/write the ethernet controller FIFO.
Definition at line 224 of file ethspi.c.
References ETHSPI_SetChipSelect().
Referenced by KSZ8851SNL_Receive(), KSZ8851SNL_Send(), and KSZ8851SNL_TerminateLongTransmit().
void ETHSPI_WriteFifoContinue | ( | int | numBytes, | |
uint8_t * | data | |||
) |
Continue writing ethernet controller FIFO.
[in] | numBytes | Number of bytes to write, 1-12K |
[in] | data | Actual bytes to write |
Definition at line 254 of file ethspi.c.
References ETHSPI_XferSpi().
Referenced by KSZ8851SNL_InitiateLongTransmit(), KSZ8851SNL_LongTransmit(), KSZ8851SNL_Send(), and KSZ8851SNL_TerminateLongTransmit().
void ETHSPI_WriteRegister | ( | uint8_t | reg, | |
int | numBytes, | |||
void * | data | |||
) |
Write ethernet controller register.
[in] | reg | Register to read |
[in] | numBytes | Number of bytes to read, should be 1-4 |
[out] | data | Pointer to element where data should be put |
Definition at line 167 of file ethspi.c.
References ADDRESS_MS2B_MASK, ADDRESS_MS2B_POS, ETHSPI_SetChipSelect(), ETHSPI_XferSpi(), OPCODE_REG_WRITE, REG_MASK, and SHIFT_VAL.
Referenced by KSZ8851SNL_CheckIrqStat(), KSZ8851SNL_EnableInterupts(), KSZ8851SNL_ExceptionHandler(), KSZ8851SNL_Init(), KSZ8851SNL_InitiateLongTransmit(), KSZ8851SNL_ReadMIBCounters(), KSZ8851SNL_Receive(), KSZ8851SNL_ReleaseIncosistentFrame(), KSZ8851SNL_Send(), and KSZ8851SNL_TerminateLongTransmit().