release/EM_CMSIS_3.20.6/Device/SiliconLabs/EFM32LG/Include/efm32lg_dmareq.h

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00001 /**************************************************************************/
00033 /**************************************************************************/
00037 #define DMAREQ_ADC0_SINGLE            ((8 << 16) + 0)  
00038 #define DMAREQ_ADC0_SCAN              ((8 << 16) + 1)  
00039 #define DMAREQ_DAC0_CH0               ((10 << 16) + 0) 
00040 #define DMAREQ_DAC0_CH1               ((10 << 16) + 1) 
00041 #define DMAREQ_USART0_RXDATAV         ((12 << 16) + 0) 
00042 #define DMAREQ_USART0_TXBL            ((12 << 16) + 1) 
00043 #define DMAREQ_USART0_TXEMPTY         ((12 << 16) + 2) 
00044 #define DMAREQ_USART1_RXDATAV         ((13 << 16) + 0) 
00045 #define DMAREQ_USART1_TXBL            ((13 << 16) + 1) 
00046 #define DMAREQ_USART1_TXEMPTY         ((13 << 16) + 2) 
00047 #define DMAREQ_USART1_RXDATAVRIGHT    ((13 << 16) + 3) 
00048 #define DMAREQ_USART1_TXBLRIGHT       ((13 << 16) + 4) 
00049 #define DMAREQ_USART2_RXDATAV         ((14 << 16) + 0) 
00050 #define DMAREQ_USART2_TXBL            ((14 << 16) + 1) 
00051 #define DMAREQ_USART2_TXEMPTY         ((14 << 16) + 2) 
00052 #define DMAREQ_USART2_RXDATAVRIGHT    ((14 << 16) + 3) 
00053 #define DMAREQ_USART2_TXBLRIGHT       ((14 << 16) + 4) 
00054 #define DMAREQ_LEUART0_RXDATAV        ((16 << 16) + 0) 
00055 #define DMAREQ_LEUART0_TXBL           ((16 << 16) + 1) 
00056 #define DMAREQ_LEUART0_TXEMPTY        ((16 << 16) + 2) 
00057 #define DMAREQ_LEUART1_RXDATAV        ((17 << 16) + 0) 
00058 #define DMAREQ_LEUART1_TXBL           ((17 << 16) + 1) 
00059 #define DMAREQ_LEUART1_TXEMPTY        ((17 << 16) + 2) 
00060 #define DMAREQ_I2C0_RXDATAV           ((20 << 16) + 0) 
00061 #define DMAREQ_I2C0_TXBL              ((20 << 16) + 1) 
00062 #define DMAREQ_I2C1_RXDATAV           ((21 << 16) + 0) 
00063 #define DMAREQ_I2C1_TXBL              ((21 << 16) + 1) 
00064 #define DMAREQ_TIMER0_UFOF            ((24 << 16) + 0) 
00065 #define DMAREQ_TIMER0_CC0             ((24 << 16) + 1) 
00066 #define DMAREQ_TIMER0_CC1             ((24 << 16) + 2) 
00067 #define DMAREQ_TIMER0_CC2             ((24 << 16) + 3) 
00068 #define DMAREQ_TIMER1_UFOF            ((25 << 16) + 0) 
00069 #define DMAREQ_TIMER1_CC0             ((25 << 16) + 1) 
00070 #define DMAREQ_TIMER1_CC1             ((25 << 16) + 2) 
00071 #define DMAREQ_TIMER1_CC2             ((25 << 16) + 3) 
00072 #define DMAREQ_TIMER2_UFOF            ((26 << 16) + 0) 
00073 #define DMAREQ_TIMER2_CC0             ((26 << 16) + 1) 
00074 #define DMAREQ_TIMER2_CC1             ((26 << 16) + 2) 
00075 #define DMAREQ_TIMER2_CC2             ((26 << 16) + 3) 
00076 #define DMAREQ_TIMER3_UFOF            ((27 << 16) + 0) 
00077 #define DMAREQ_TIMER3_CC0             ((27 << 16) + 1) 
00078 #define DMAREQ_TIMER3_CC1             ((27 << 16) + 2) 
00079 #define DMAREQ_TIMER3_CC2             ((27 << 16) + 3) 
00080 #define DMAREQ_UART0_RXDATAV          ((44 << 16) + 0) 
00081 #define DMAREQ_UART0_TXBL             ((44 << 16) + 1) 
00082 #define DMAREQ_UART0_TXEMPTY          ((44 << 16) + 2) 
00083 #define DMAREQ_UART1_RXDATAV          ((45 << 16) + 0) 
00084 #define DMAREQ_UART1_TXBL             ((45 << 16) + 1) 
00085 #define DMAREQ_UART1_TXEMPTY          ((45 << 16) + 2) 
00086 #define DMAREQ_MSC_WDATA              ((48 << 16) + 0) 
00087 #define DMAREQ_AES_DATAWR             ((49 << 16) + 0) 
00088 #define DMAREQ_AES_XORDATAWR          ((49 << 16) + 1) 
00089 #define DMAREQ_AES_DATARD             ((49 << 16) + 2) 
00090 #define DMAREQ_AES_KEYWR              ((49 << 16) + 3) 
00091 #define DMAREQ_LESENSE_BUFDATAV       ((50 << 16) + 0) 
00092 #define DMAREQ_EBI_PXL0EMPTY          ((51 << 16) + 0) 
00093 #define DMAREQ_EBI_PXL1EMPTY          ((51 << 16) + 1) 
00094 #define DMAREQ_EBI_PXLFULL            ((51 << 16) + 2) 
00095 #define DMAREQ_EBI_DDEMPTY            ((51 << 16) + 3)