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Data Structures | |
struct | EBI_TypeDef |
Defines | |
#define | _EBI_CTRL_RESETVALUE 0x00000000UL |
#define | _EBI_CTRL_MASK 0xCFFFFFFFUL |
#define | _EBI_CTRL_MODE_SHIFT 0 |
#define | _EBI_CTRL_MODE_MASK 0x3UL |
#define | _EBI_CTRL_MODE_DEFAULT 0x00000000UL |
#define | _EBI_CTRL_MODE_D8A8 0x00000000UL |
#define | _EBI_CTRL_MODE_D16A16ALE 0x00000001UL |
#define | _EBI_CTRL_MODE_D8A24ALE 0x00000002UL |
#define | _EBI_CTRL_MODE_D16 0x00000003UL |
#define | EBI_CTRL_MODE_DEFAULT (_EBI_CTRL_MODE_DEFAULT << 0) |
#define | EBI_CTRL_MODE_D8A8 (_EBI_CTRL_MODE_D8A8 << 0) |
#define | EBI_CTRL_MODE_D16A16ALE (_EBI_CTRL_MODE_D16A16ALE << 0) |
#define | EBI_CTRL_MODE_D8A24ALE (_EBI_CTRL_MODE_D8A24ALE << 0) |
#define | EBI_CTRL_MODE_D16 (_EBI_CTRL_MODE_D16 << 0) |
#define | _EBI_CTRL_MODE1_SHIFT 2 |
#define | _EBI_CTRL_MODE1_MASK 0xCUL |
#define | _EBI_CTRL_MODE1_DEFAULT 0x00000000UL |
#define | _EBI_CTRL_MODE1_D8A8 0x00000000UL |
#define | _EBI_CTRL_MODE1_D16A16ALE 0x00000001UL |
#define | _EBI_CTRL_MODE1_D8A24ALE 0x00000002UL |
#define | _EBI_CTRL_MODE1_D16 0x00000003UL |
#define | EBI_CTRL_MODE1_DEFAULT (_EBI_CTRL_MODE1_DEFAULT << 2) |
#define | EBI_CTRL_MODE1_D8A8 (_EBI_CTRL_MODE1_D8A8 << 2) |
#define | EBI_CTRL_MODE1_D16A16ALE (_EBI_CTRL_MODE1_D16A16ALE << 2) |
#define | EBI_CTRL_MODE1_D8A24ALE (_EBI_CTRL_MODE1_D8A24ALE << 2) |
#define | EBI_CTRL_MODE1_D16 (_EBI_CTRL_MODE1_D16 << 2) |
#define | _EBI_CTRL_MODE2_SHIFT 4 |
#define | _EBI_CTRL_MODE2_MASK 0x30UL |
#define | _EBI_CTRL_MODE2_DEFAULT 0x00000000UL |
#define | _EBI_CTRL_MODE2_D8A8 0x00000000UL |
#define | _EBI_CTRL_MODE2_D16A16ALE 0x00000001UL |
#define | _EBI_CTRL_MODE2_D8A24ALE 0x00000002UL |
#define | _EBI_CTRL_MODE2_D16 0x00000003UL |
#define | EBI_CTRL_MODE2_DEFAULT (_EBI_CTRL_MODE2_DEFAULT << 4) |
#define | EBI_CTRL_MODE2_D8A8 (_EBI_CTRL_MODE2_D8A8 << 4) |
#define | EBI_CTRL_MODE2_D16A16ALE (_EBI_CTRL_MODE2_D16A16ALE << 4) |
#define | EBI_CTRL_MODE2_D8A24ALE (_EBI_CTRL_MODE2_D8A24ALE << 4) |
#define | EBI_CTRL_MODE2_D16 (_EBI_CTRL_MODE2_D16 << 4) |
#define | _EBI_CTRL_MODE3_SHIFT 6 |
#define | _EBI_CTRL_MODE3_MASK 0xC0UL |
#define | _EBI_CTRL_MODE3_DEFAULT 0x00000000UL |
#define | _EBI_CTRL_MODE3_D8A8 0x00000000UL |
#define | _EBI_CTRL_MODE3_D16A16ALE 0x00000001UL |
#define | _EBI_CTRL_MODE3_D8A24ALE 0x00000002UL |
#define | _EBI_CTRL_MODE3_D16 0x00000003UL |
#define | EBI_CTRL_MODE3_DEFAULT (_EBI_CTRL_MODE3_DEFAULT << 6) |
#define | EBI_CTRL_MODE3_D8A8 (_EBI_CTRL_MODE3_D8A8 << 6) |
#define | EBI_CTRL_MODE3_D16A16ALE (_EBI_CTRL_MODE3_D16A16ALE << 6) |
#define | EBI_CTRL_MODE3_D8A24ALE (_EBI_CTRL_MODE3_D8A24ALE << 6) |
#define | EBI_CTRL_MODE3_D16 (_EBI_CTRL_MODE3_D16 << 6) |
#define | EBI_CTRL_BANK0EN (0x1UL << 8) |
#define | _EBI_CTRL_BANK0EN_SHIFT 8 |
#define | _EBI_CTRL_BANK0EN_MASK 0x100UL |
#define | _EBI_CTRL_BANK0EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BANK0EN_DEFAULT (_EBI_CTRL_BANK0EN_DEFAULT << 8) |
#define | EBI_CTRL_BANK1EN (0x1UL << 9) |
#define | _EBI_CTRL_BANK1EN_SHIFT 9 |
#define | _EBI_CTRL_BANK1EN_MASK 0x200UL |
#define | _EBI_CTRL_BANK1EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BANK1EN_DEFAULT (_EBI_CTRL_BANK1EN_DEFAULT << 9) |
#define | EBI_CTRL_BANK2EN (0x1UL << 10) |
#define | _EBI_CTRL_BANK2EN_SHIFT 10 |
#define | _EBI_CTRL_BANK2EN_MASK 0x400UL |
#define | _EBI_CTRL_BANK2EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BANK2EN_DEFAULT (_EBI_CTRL_BANK2EN_DEFAULT << 10) |
#define | EBI_CTRL_BANK3EN (0x1UL << 11) |
#define | _EBI_CTRL_BANK3EN_SHIFT 11 |
#define | _EBI_CTRL_BANK3EN_MASK 0x800UL |
#define | _EBI_CTRL_BANK3EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BANK3EN_DEFAULT (_EBI_CTRL_BANK3EN_DEFAULT << 11) |
#define | EBI_CTRL_NOIDLE (0x1UL << 12) |
#define | _EBI_CTRL_NOIDLE_SHIFT 12 |
#define | _EBI_CTRL_NOIDLE_MASK 0x1000UL |
#define | _EBI_CTRL_NOIDLE_DEFAULT 0x00000000UL |
#define | EBI_CTRL_NOIDLE_DEFAULT (_EBI_CTRL_NOIDLE_DEFAULT << 12) |
#define | EBI_CTRL_NOIDLE1 (0x1UL << 13) |
#define | _EBI_CTRL_NOIDLE1_SHIFT 13 |
#define | _EBI_CTRL_NOIDLE1_MASK 0x2000UL |
#define | _EBI_CTRL_NOIDLE1_DEFAULT 0x00000000UL |
#define | EBI_CTRL_NOIDLE1_DEFAULT (_EBI_CTRL_NOIDLE1_DEFAULT << 13) |
#define | EBI_CTRL_NOIDLE2 (0x1UL << 14) |
#define | _EBI_CTRL_NOIDLE2_SHIFT 14 |
#define | _EBI_CTRL_NOIDLE2_MASK 0x4000UL |
#define | _EBI_CTRL_NOIDLE2_DEFAULT 0x00000000UL |
#define | EBI_CTRL_NOIDLE2_DEFAULT (_EBI_CTRL_NOIDLE2_DEFAULT << 14) |
#define | EBI_CTRL_NOIDLE3 (0x1UL << 15) |
#define | _EBI_CTRL_NOIDLE3_SHIFT 15 |
#define | _EBI_CTRL_NOIDLE3_MASK 0x8000UL |
#define | _EBI_CTRL_NOIDLE3_DEFAULT 0x00000000UL |
#define | EBI_CTRL_NOIDLE3_DEFAULT (_EBI_CTRL_NOIDLE3_DEFAULT << 15) |
#define | EBI_CTRL_ARDYEN (0x1UL << 16) |
#define | _EBI_CTRL_ARDYEN_SHIFT 16 |
#define | _EBI_CTRL_ARDYEN_MASK 0x10000UL |
#define | _EBI_CTRL_ARDYEN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDYEN_DEFAULT (_EBI_CTRL_ARDYEN_DEFAULT << 16) |
#define | EBI_CTRL_ARDYTODIS (0x1UL << 17) |
#define | _EBI_CTRL_ARDYTODIS_SHIFT 17 |
#define | _EBI_CTRL_ARDYTODIS_MASK 0x20000UL |
#define | _EBI_CTRL_ARDYTODIS_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDYTODIS_DEFAULT (_EBI_CTRL_ARDYTODIS_DEFAULT << 17) |
#define | EBI_CTRL_ARDY1EN (0x1UL << 18) |
#define | _EBI_CTRL_ARDY1EN_SHIFT 18 |
#define | _EBI_CTRL_ARDY1EN_MASK 0x40000UL |
#define | _EBI_CTRL_ARDY1EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDY1EN_DEFAULT (_EBI_CTRL_ARDY1EN_DEFAULT << 18) |
#define | EBI_CTRL_ARDYTO1DIS (0x1UL << 19) |
#define | _EBI_CTRL_ARDYTO1DIS_SHIFT 19 |
#define | _EBI_CTRL_ARDYTO1DIS_MASK 0x80000UL |
#define | _EBI_CTRL_ARDYTO1DIS_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDYTO1DIS_DEFAULT (_EBI_CTRL_ARDYTO1DIS_DEFAULT << 19) |
#define | EBI_CTRL_ARDY2EN (0x1UL << 20) |
#define | _EBI_CTRL_ARDY2EN_SHIFT 20 |
#define | _EBI_CTRL_ARDY2EN_MASK 0x100000UL |
#define | _EBI_CTRL_ARDY2EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDY2EN_DEFAULT (_EBI_CTRL_ARDY2EN_DEFAULT << 20) |
#define | EBI_CTRL_ARDYTO2DIS (0x1UL << 21) |
#define | _EBI_CTRL_ARDYTO2DIS_SHIFT 21 |
#define | _EBI_CTRL_ARDYTO2DIS_MASK 0x200000UL |
#define | _EBI_CTRL_ARDYTO2DIS_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDYTO2DIS_DEFAULT (_EBI_CTRL_ARDYTO2DIS_DEFAULT << 21) |
#define | EBI_CTRL_ARDY3EN (0x1UL << 22) |
#define | _EBI_CTRL_ARDY3EN_SHIFT 22 |
#define | _EBI_CTRL_ARDY3EN_MASK 0x400000UL |
#define | _EBI_CTRL_ARDY3EN_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDY3EN_DEFAULT (_EBI_CTRL_ARDY3EN_DEFAULT << 22) |
#define | EBI_CTRL_ARDYTO3DIS (0x1UL << 23) |
#define | _EBI_CTRL_ARDYTO3DIS_SHIFT 23 |
#define | _EBI_CTRL_ARDYTO3DIS_MASK 0x800000UL |
#define | _EBI_CTRL_ARDYTO3DIS_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ARDYTO3DIS_DEFAULT (_EBI_CTRL_ARDYTO3DIS_DEFAULT << 23) |
#define | EBI_CTRL_BL (0x1UL << 24) |
#define | _EBI_CTRL_BL_SHIFT 24 |
#define | _EBI_CTRL_BL_MASK 0x1000000UL |
#define | _EBI_CTRL_BL_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BL_DEFAULT (_EBI_CTRL_BL_DEFAULT << 24) |
#define | EBI_CTRL_BL1 (0x1UL << 25) |
#define | _EBI_CTRL_BL1_SHIFT 25 |
#define | _EBI_CTRL_BL1_MASK 0x2000000UL |
#define | _EBI_CTRL_BL1_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BL1_DEFAULT (_EBI_CTRL_BL1_DEFAULT << 25) |
#define | EBI_CTRL_BL2 (0x1UL << 26) |
#define | _EBI_CTRL_BL2_SHIFT 26 |
#define | _EBI_CTRL_BL2_MASK 0x4000000UL |
#define | _EBI_CTRL_BL2_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BL2_DEFAULT (_EBI_CTRL_BL2_DEFAULT << 26) |
#define | EBI_CTRL_BL3 (0x1UL << 27) |
#define | _EBI_CTRL_BL3_SHIFT 27 |
#define | _EBI_CTRL_BL3_MASK 0x8000000UL |
#define | _EBI_CTRL_BL3_DEFAULT 0x00000000UL |
#define | EBI_CTRL_BL3_DEFAULT (_EBI_CTRL_BL3_DEFAULT << 27) |
#define | EBI_CTRL_ITS (0x1UL << 30) |
#define | _EBI_CTRL_ITS_SHIFT 30 |
#define | _EBI_CTRL_ITS_MASK 0x40000000UL |
#define | _EBI_CTRL_ITS_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ITS_DEFAULT (_EBI_CTRL_ITS_DEFAULT << 30) |
#define | EBI_CTRL_ALTMAP (0x1UL << 31) |
#define | _EBI_CTRL_ALTMAP_SHIFT 31 |
#define | _EBI_CTRL_ALTMAP_MASK 0x80000000UL |
#define | _EBI_CTRL_ALTMAP_DEFAULT 0x00000000UL |
#define | EBI_CTRL_ALTMAP_DEFAULT (_EBI_CTRL_ALTMAP_DEFAULT << 31) |
#define | _EBI_ADDRTIMING_RESETVALUE 0x00000303UL |
#define | _EBI_ADDRTIMING_MASK 0x10000303UL |
#define | _EBI_ADDRTIMING_ADDRSETUP_SHIFT 0 |
#define | _EBI_ADDRTIMING_ADDRSETUP_MASK 0x3UL |
#define | _EBI_ADDRTIMING_ADDRSETUP_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING_ADDRSETUP_DEFAULT << 0) |
#define | _EBI_ADDRTIMING_ADDRHOLD_SHIFT 8 |
#define | _EBI_ADDRTIMING_ADDRHOLD_MASK 0x300UL |
#define | _EBI_ADDRTIMING_ADDRHOLD_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING_ADDRHOLD_DEFAULT << 8) |
#define | EBI_ADDRTIMING_HALFALE (0x1UL << 28) |
#define | _EBI_ADDRTIMING_HALFALE_SHIFT 28 |
#define | _EBI_ADDRTIMING_HALFALE_MASK 0x10000000UL |
#define | _EBI_ADDRTIMING_HALFALE_DEFAULT 0x00000000UL |
#define | EBI_ADDRTIMING_HALFALE_DEFAULT (_EBI_ADDRTIMING_HALFALE_DEFAULT << 28) |
#define | _EBI_RDTIMING_RESETVALUE 0x00033F03UL |
#define | _EBI_RDTIMING_MASK 0x70033F03UL |
#define | _EBI_RDTIMING_RDSETUP_SHIFT 0 |
#define | _EBI_RDTIMING_RDSETUP_MASK 0x3UL |
#define | _EBI_RDTIMING_RDSETUP_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING_RDSETUP_DEFAULT (_EBI_RDTIMING_RDSETUP_DEFAULT << 0) |
#define | _EBI_RDTIMING_RDSTRB_SHIFT 8 |
#define | _EBI_RDTIMING_RDSTRB_MASK 0x3F00UL |
#define | _EBI_RDTIMING_RDSTRB_DEFAULT 0x0000003FUL |
#define | EBI_RDTIMING_RDSTRB_DEFAULT (_EBI_RDTIMING_RDSTRB_DEFAULT << 8) |
#define | _EBI_RDTIMING_RDHOLD_SHIFT 16 |
#define | _EBI_RDTIMING_RDHOLD_MASK 0x30000UL |
#define | _EBI_RDTIMING_RDHOLD_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING_RDHOLD_DEFAULT (_EBI_RDTIMING_RDHOLD_DEFAULT << 16) |
#define | EBI_RDTIMING_HALFRE (0x1UL << 28) |
#define | _EBI_RDTIMING_HALFRE_SHIFT 28 |
#define | _EBI_RDTIMING_HALFRE_MASK 0x10000000UL |
#define | _EBI_RDTIMING_HALFRE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING_HALFRE_DEFAULT (_EBI_RDTIMING_HALFRE_DEFAULT << 28) |
#define | EBI_RDTIMING_PREFETCH (0x1UL << 29) |
#define | _EBI_RDTIMING_PREFETCH_SHIFT 29 |
#define | _EBI_RDTIMING_PREFETCH_MASK 0x20000000UL |
#define | _EBI_RDTIMING_PREFETCH_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING_PREFETCH_DEFAULT (_EBI_RDTIMING_PREFETCH_DEFAULT << 29) |
#define | EBI_RDTIMING_PAGEMODE (0x1UL << 30) |
#define | _EBI_RDTIMING_PAGEMODE_SHIFT 30 |
#define | _EBI_RDTIMING_PAGEMODE_MASK 0x40000000UL |
#define | _EBI_RDTIMING_PAGEMODE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING_PAGEMODE_DEFAULT (_EBI_RDTIMING_PAGEMODE_DEFAULT << 30) |
#define | _EBI_WRTIMING_RESETVALUE 0x00033F03UL |
#define | _EBI_WRTIMING_MASK 0x30033F03UL |
#define | _EBI_WRTIMING_WRSETUP_SHIFT 0 |
#define | _EBI_WRTIMING_WRSETUP_MASK 0x3UL |
#define | _EBI_WRTIMING_WRSETUP_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING_WRSETUP_DEFAULT (_EBI_WRTIMING_WRSETUP_DEFAULT << 0) |
#define | _EBI_WRTIMING_WRSTRB_SHIFT 8 |
#define | _EBI_WRTIMING_WRSTRB_MASK 0x3F00UL |
#define | _EBI_WRTIMING_WRSTRB_DEFAULT 0x0000003FUL |
#define | EBI_WRTIMING_WRSTRB_DEFAULT (_EBI_WRTIMING_WRSTRB_DEFAULT << 8) |
#define | _EBI_WRTIMING_WRHOLD_SHIFT 16 |
#define | _EBI_WRTIMING_WRHOLD_MASK 0x30000UL |
#define | _EBI_WRTIMING_WRHOLD_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING_WRHOLD_DEFAULT (_EBI_WRTIMING_WRHOLD_DEFAULT << 16) |
#define | EBI_WRTIMING_HALFWE (0x1UL << 28) |
#define | _EBI_WRTIMING_HALFWE_SHIFT 28 |
#define | _EBI_WRTIMING_HALFWE_MASK 0x10000000UL |
#define | _EBI_WRTIMING_HALFWE_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING_HALFWE_DEFAULT (_EBI_WRTIMING_HALFWE_DEFAULT << 28) |
#define | EBI_WRTIMING_WBUFDIS (0x1UL << 29) |
#define | _EBI_WRTIMING_WBUFDIS_SHIFT 29 |
#define | _EBI_WRTIMING_WBUFDIS_MASK 0x20000000UL |
#define | _EBI_WRTIMING_WBUFDIS_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING_WBUFDIS_DEFAULT (_EBI_WRTIMING_WBUFDIS_DEFAULT << 29) |
#define | _EBI_POLARITY_RESETVALUE 0x00000000UL |
#define | _EBI_POLARITY_MASK 0x0000003FUL |
#define | EBI_POLARITY_CSPOL (0x1UL << 0) |
#define | _EBI_POLARITY_CSPOL_SHIFT 0 |
#define | _EBI_POLARITY_CSPOL_MASK 0x1UL |
#define | _EBI_POLARITY_CSPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY_CSPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY_CSPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY_CSPOL_DEFAULT (_EBI_POLARITY_CSPOL_DEFAULT << 0) |
#define | EBI_POLARITY_CSPOL_ACTIVELOW (_EBI_POLARITY_CSPOL_ACTIVELOW << 0) |
#define | EBI_POLARITY_CSPOL_ACTIVEHIGH (_EBI_POLARITY_CSPOL_ACTIVEHIGH << 0) |
#define | EBI_POLARITY_REPOL (0x1UL << 1) |
#define | _EBI_POLARITY_REPOL_SHIFT 1 |
#define | _EBI_POLARITY_REPOL_MASK 0x2UL |
#define | _EBI_POLARITY_REPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY_REPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY_REPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY_REPOL_DEFAULT (_EBI_POLARITY_REPOL_DEFAULT << 1) |
#define | EBI_POLARITY_REPOL_ACTIVELOW (_EBI_POLARITY_REPOL_ACTIVELOW << 1) |
#define | EBI_POLARITY_REPOL_ACTIVEHIGH (_EBI_POLARITY_REPOL_ACTIVEHIGH << 1) |
#define | EBI_POLARITY_WEPOL (0x1UL << 2) |
#define | _EBI_POLARITY_WEPOL_SHIFT 2 |
#define | _EBI_POLARITY_WEPOL_MASK 0x4UL |
#define | _EBI_POLARITY_WEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY_WEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY_WEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY_WEPOL_DEFAULT (_EBI_POLARITY_WEPOL_DEFAULT << 2) |
#define | EBI_POLARITY_WEPOL_ACTIVELOW (_EBI_POLARITY_WEPOL_ACTIVELOW << 2) |
#define | EBI_POLARITY_WEPOL_ACTIVEHIGH (_EBI_POLARITY_WEPOL_ACTIVEHIGH << 2) |
#define | EBI_POLARITY_ALEPOL (0x1UL << 3) |
#define | _EBI_POLARITY_ALEPOL_SHIFT 3 |
#define | _EBI_POLARITY_ALEPOL_MASK 0x8UL |
#define | _EBI_POLARITY_ALEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY_ALEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY_ALEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY_ALEPOL_DEFAULT (_EBI_POLARITY_ALEPOL_DEFAULT << 3) |
#define | EBI_POLARITY_ALEPOL_ACTIVELOW (_EBI_POLARITY_ALEPOL_ACTIVELOW << 3) |
#define | EBI_POLARITY_ALEPOL_ACTIVEHIGH (_EBI_POLARITY_ALEPOL_ACTIVEHIGH << 3) |
#define | EBI_POLARITY_ARDYPOL (0x1UL << 4) |
#define | _EBI_POLARITY_ARDYPOL_SHIFT 4 |
#define | _EBI_POLARITY_ARDYPOL_MASK 0x10UL |
#define | _EBI_POLARITY_ARDYPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY_ARDYPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY_ARDYPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY_ARDYPOL_DEFAULT (_EBI_POLARITY_ARDYPOL_DEFAULT << 4) |
#define | EBI_POLARITY_ARDYPOL_ACTIVELOW (_EBI_POLARITY_ARDYPOL_ACTIVELOW << 4) |
#define | EBI_POLARITY_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY_ARDYPOL_ACTIVEHIGH << 4) |
#define | EBI_POLARITY_BLPOL (0x1UL << 5) |
#define | _EBI_POLARITY_BLPOL_SHIFT 5 |
#define | _EBI_POLARITY_BLPOL_MASK 0x20UL |
#define | _EBI_POLARITY_BLPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY_BLPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY_BLPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY_BLPOL_DEFAULT (_EBI_POLARITY_BLPOL_DEFAULT << 5) |
#define | EBI_POLARITY_BLPOL_ACTIVELOW (_EBI_POLARITY_BLPOL_ACTIVELOW << 5) |
#define | EBI_POLARITY_BLPOL_ACTIVEHIGH (_EBI_POLARITY_BLPOL_ACTIVEHIGH << 5) |
#define | _EBI_ROUTE_RESETVALUE 0x00000000UL |
#define | _EBI_ROUTE_MASK 0x777F10FFUL |
#define | EBI_ROUTE_EBIPEN (0x1UL << 0) |
#define | _EBI_ROUTE_EBIPEN_SHIFT 0 |
#define | _EBI_ROUTE_EBIPEN_MASK 0x1UL |
#define | _EBI_ROUTE_EBIPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_EBIPEN_DEFAULT (_EBI_ROUTE_EBIPEN_DEFAULT << 0) |
#define | EBI_ROUTE_CS0PEN (0x1UL << 1) |
#define | _EBI_ROUTE_CS0PEN_SHIFT 1 |
#define | _EBI_ROUTE_CS0PEN_MASK 0x2UL |
#define | _EBI_ROUTE_CS0PEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_CS0PEN_DEFAULT (_EBI_ROUTE_CS0PEN_DEFAULT << 1) |
#define | EBI_ROUTE_CS1PEN (0x1UL << 2) |
#define | _EBI_ROUTE_CS1PEN_SHIFT 2 |
#define | _EBI_ROUTE_CS1PEN_MASK 0x4UL |
#define | _EBI_ROUTE_CS1PEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_CS1PEN_DEFAULT (_EBI_ROUTE_CS1PEN_DEFAULT << 2) |
#define | EBI_ROUTE_CS2PEN (0x1UL << 3) |
#define | _EBI_ROUTE_CS2PEN_SHIFT 3 |
#define | _EBI_ROUTE_CS2PEN_MASK 0x8UL |
#define | _EBI_ROUTE_CS2PEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_CS2PEN_DEFAULT (_EBI_ROUTE_CS2PEN_DEFAULT << 3) |
#define | EBI_ROUTE_CS3PEN (0x1UL << 4) |
#define | _EBI_ROUTE_CS3PEN_SHIFT 4 |
#define | _EBI_ROUTE_CS3PEN_MASK 0x10UL |
#define | _EBI_ROUTE_CS3PEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_CS3PEN_DEFAULT (_EBI_ROUTE_CS3PEN_DEFAULT << 4) |
#define | EBI_ROUTE_ALEPEN (0x1UL << 5) |
#define | _EBI_ROUTE_ALEPEN_SHIFT 5 |
#define | _EBI_ROUTE_ALEPEN_MASK 0x20UL |
#define | _EBI_ROUTE_ALEPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_ALEPEN_DEFAULT (_EBI_ROUTE_ALEPEN_DEFAULT << 5) |
#define | EBI_ROUTE_ARDYPEN (0x1UL << 6) |
#define | _EBI_ROUTE_ARDYPEN_SHIFT 6 |
#define | _EBI_ROUTE_ARDYPEN_MASK 0x40UL |
#define | _EBI_ROUTE_ARDYPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_ARDYPEN_DEFAULT (_EBI_ROUTE_ARDYPEN_DEFAULT << 6) |
#define | EBI_ROUTE_BLPEN (0x1UL << 7) |
#define | _EBI_ROUTE_BLPEN_SHIFT 7 |
#define | _EBI_ROUTE_BLPEN_MASK 0x80UL |
#define | _EBI_ROUTE_BLPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_BLPEN_DEFAULT (_EBI_ROUTE_BLPEN_DEFAULT << 7) |
#define | EBI_ROUTE_NANDPEN (0x1UL << 12) |
#define | _EBI_ROUTE_NANDPEN_SHIFT 12 |
#define | _EBI_ROUTE_NANDPEN_MASK 0x1000UL |
#define | _EBI_ROUTE_NANDPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_NANDPEN_DEFAULT (_EBI_ROUTE_NANDPEN_DEFAULT << 12) |
#define | _EBI_ROUTE_ALB_SHIFT 16 |
#define | _EBI_ROUTE_ALB_MASK 0x30000UL |
#define | _EBI_ROUTE_ALB_DEFAULT 0x00000000UL |
#define | _EBI_ROUTE_ALB_A0 0x00000000UL |
#define | _EBI_ROUTE_ALB_A8 0x00000001UL |
#define | _EBI_ROUTE_ALB_A16 0x00000002UL |
#define | _EBI_ROUTE_ALB_A24 0x00000003UL |
#define | EBI_ROUTE_ALB_DEFAULT (_EBI_ROUTE_ALB_DEFAULT << 16) |
#define | EBI_ROUTE_ALB_A0 (_EBI_ROUTE_ALB_A0 << 16) |
#define | EBI_ROUTE_ALB_A8 (_EBI_ROUTE_ALB_A8 << 16) |
#define | EBI_ROUTE_ALB_A16 (_EBI_ROUTE_ALB_A16 << 16) |
#define | EBI_ROUTE_ALB_A24 (_EBI_ROUTE_ALB_A24 << 16) |
#define | _EBI_ROUTE_APEN_SHIFT 18 |
#define | _EBI_ROUTE_APEN_MASK 0x7C0000UL |
#define | _EBI_ROUTE_APEN_DEFAULT 0x00000000UL |
#define | _EBI_ROUTE_APEN_A0 0x00000000UL |
#define | _EBI_ROUTE_APEN_A5 0x00000005UL |
#define | _EBI_ROUTE_APEN_A6 0x00000006UL |
#define | _EBI_ROUTE_APEN_A7 0x00000007UL |
#define | _EBI_ROUTE_APEN_A8 0x00000008UL |
#define | _EBI_ROUTE_APEN_A9 0x00000009UL |
#define | _EBI_ROUTE_APEN_A10 0x0000000AUL |
#define | _EBI_ROUTE_APEN_A11 0x0000000BUL |
#define | _EBI_ROUTE_APEN_A12 0x0000000CUL |
#define | _EBI_ROUTE_APEN_A13 0x0000000DUL |
#define | _EBI_ROUTE_APEN_A14 0x0000000EUL |
#define | _EBI_ROUTE_APEN_A15 0x0000000FUL |
#define | _EBI_ROUTE_APEN_A16 0x00000010UL |
#define | _EBI_ROUTE_APEN_A17 0x00000011UL |
#define | _EBI_ROUTE_APEN_A18 0x00000012UL |
#define | _EBI_ROUTE_APEN_A19 0x00000013UL |
#define | _EBI_ROUTE_APEN_A20 0x00000014UL |
#define | _EBI_ROUTE_APEN_A21 0x00000015UL |
#define | _EBI_ROUTE_APEN_A22 0x00000016UL |
#define | _EBI_ROUTE_APEN_A23 0x00000017UL |
#define | _EBI_ROUTE_APEN_A24 0x00000018UL |
#define | _EBI_ROUTE_APEN_A25 0x00000019UL |
#define | _EBI_ROUTE_APEN_A26 0x0000001AUL |
#define | _EBI_ROUTE_APEN_A27 0x0000001BUL |
#define | _EBI_ROUTE_APEN_A28 0x0000001CUL |
#define | EBI_ROUTE_APEN_DEFAULT (_EBI_ROUTE_APEN_DEFAULT << 18) |
#define | EBI_ROUTE_APEN_A0 (_EBI_ROUTE_APEN_A0 << 18) |
#define | EBI_ROUTE_APEN_A5 (_EBI_ROUTE_APEN_A5 << 18) |
#define | EBI_ROUTE_APEN_A6 (_EBI_ROUTE_APEN_A6 << 18) |
#define | EBI_ROUTE_APEN_A7 (_EBI_ROUTE_APEN_A7 << 18) |
#define | EBI_ROUTE_APEN_A8 (_EBI_ROUTE_APEN_A8 << 18) |
#define | EBI_ROUTE_APEN_A9 (_EBI_ROUTE_APEN_A9 << 18) |
#define | EBI_ROUTE_APEN_A10 (_EBI_ROUTE_APEN_A10 << 18) |
#define | EBI_ROUTE_APEN_A11 (_EBI_ROUTE_APEN_A11 << 18) |
#define | EBI_ROUTE_APEN_A12 (_EBI_ROUTE_APEN_A12 << 18) |
#define | EBI_ROUTE_APEN_A13 (_EBI_ROUTE_APEN_A13 << 18) |
#define | EBI_ROUTE_APEN_A14 (_EBI_ROUTE_APEN_A14 << 18) |
#define | EBI_ROUTE_APEN_A15 (_EBI_ROUTE_APEN_A15 << 18) |
#define | EBI_ROUTE_APEN_A16 (_EBI_ROUTE_APEN_A16 << 18) |
#define | EBI_ROUTE_APEN_A17 (_EBI_ROUTE_APEN_A17 << 18) |
#define | EBI_ROUTE_APEN_A18 (_EBI_ROUTE_APEN_A18 << 18) |
#define | EBI_ROUTE_APEN_A19 (_EBI_ROUTE_APEN_A19 << 18) |
#define | EBI_ROUTE_APEN_A20 (_EBI_ROUTE_APEN_A20 << 18) |
#define | EBI_ROUTE_APEN_A21 (_EBI_ROUTE_APEN_A21 << 18) |
#define | EBI_ROUTE_APEN_A22 (_EBI_ROUTE_APEN_A22 << 18) |
#define | EBI_ROUTE_APEN_A23 (_EBI_ROUTE_APEN_A23 << 18) |
#define | EBI_ROUTE_APEN_A24 (_EBI_ROUTE_APEN_A24 << 18) |
#define | EBI_ROUTE_APEN_A25 (_EBI_ROUTE_APEN_A25 << 18) |
#define | EBI_ROUTE_APEN_A26 (_EBI_ROUTE_APEN_A26 << 18) |
#define | EBI_ROUTE_APEN_A27 (_EBI_ROUTE_APEN_A27 << 18) |
#define | EBI_ROUTE_APEN_A28 (_EBI_ROUTE_APEN_A28 << 18) |
#define | EBI_ROUTE_TFTPEN (0x1UL << 24) |
#define | _EBI_ROUTE_TFTPEN_SHIFT 24 |
#define | _EBI_ROUTE_TFTPEN_MASK 0x1000000UL |
#define | _EBI_ROUTE_TFTPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_TFTPEN_DEFAULT (_EBI_ROUTE_TFTPEN_DEFAULT << 24) |
#define | EBI_ROUTE_DATAENPEN (0x1UL << 25) |
#define | _EBI_ROUTE_DATAENPEN_SHIFT 25 |
#define | _EBI_ROUTE_DATAENPEN_MASK 0x2000000UL |
#define | _EBI_ROUTE_DATAENPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_DATAENPEN_DEFAULT (_EBI_ROUTE_DATAENPEN_DEFAULT << 25) |
#define | EBI_ROUTE_CSTFTPEN (0x1UL << 26) |
#define | _EBI_ROUTE_CSTFTPEN_SHIFT 26 |
#define | _EBI_ROUTE_CSTFTPEN_MASK 0x4000000UL |
#define | _EBI_ROUTE_CSTFTPEN_DEFAULT 0x00000000UL |
#define | EBI_ROUTE_CSTFTPEN_DEFAULT (_EBI_ROUTE_CSTFTPEN_DEFAULT << 26) |
#define | _EBI_ROUTE_LOCATION_SHIFT 28 |
#define | _EBI_ROUTE_LOCATION_MASK 0x70000000UL |
#define | _EBI_ROUTE_LOCATION_LOC0 0x00000000UL |
#define | _EBI_ROUTE_LOCATION_DEFAULT 0x00000000UL |
#define | _EBI_ROUTE_LOCATION_LOC1 0x00000001UL |
#define | _EBI_ROUTE_LOCATION_LOC2 0x00000002UL |
#define | EBI_ROUTE_LOCATION_LOC0 (_EBI_ROUTE_LOCATION_LOC0 << 28) |
#define | EBI_ROUTE_LOCATION_DEFAULT (_EBI_ROUTE_LOCATION_DEFAULT << 28) |
#define | EBI_ROUTE_LOCATION_LOC1 (_EBI_ROUTE_LOCATION_LOC1 << 28) |
#define | EBI_ROUTE_LOCATION_LOC2 (_EBI_ROUTE_LOCATION_LOC2 << 28) |
#define | _EBI_ADDRTIMING1_RESETVALUE 0x00000303UL |
#define | _EBI_ADDRTIMING1_MASK 0x10000303UL |
#define | _EBI_ADDRTIMING1_ADDRSETUP_SHIFT 0 |
#define | _EBI_ADDRTIMING1_ADDRSETUP_MASK 0x3UL |
#define | _EBI_ADDRTIMING1_ADDRSETUP_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING1_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING1_ADDRSETUP_DEFAULT << 0) |
#define | _EBI_ADDRTIMING1_ADDRHOLD_SHIFT 8 |
#define | _EBI_ADDRTIMING1_ADDRHOLD_MASK 0x300UL |
#define | _EBI_ADDRTIMING1_ADDRHOLD_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING1_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING1_ADDRHOLD_DEFAULT << 8) |
#define | EBI_ADDRTIMING1_HALFALE (0x1UL << 28) |
#define | _EBI_ADDRTIMING1_HALFALE_SHIFT 28 |
#define | _EBI_ADDRTIMING1_HALFALE_MASK 0x10000000UL |
#define | _EBI_ADDRTIMING1_HALFALE_DEFAULT 0x00000000UL |
#define | EBI_ADDRTIMING1_HALFALE_DEFAULT (_EBI_ADDRTIMING1_HALFALE_DEFAULT << 28) |
#define | _EBI_RDTIMING1_RESETVALUE 0x00033F03UL |
#define | _EBI_RDTIMING1_MASK 0x70033F03UL |
#define | _EBI_RDTIMING1_RDSETUP_SHIFT 0 |
#define | _EBI_RDTIMING1_RDSETUP_MASK 0x3UL |
#define | _EBI_RDTIMING1_RDSETUP_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING1_RDSETUP_DEFAULT (_EBI_RDTIMING1_RDSETUP_DEFAULT << 0) |
#define | _EBI_RDTIMING1_RDSTRB_SHIFT 8 |
#define | _EBI_RDTIMING1_RDSTRB_MASK 0x3F00UL |
#define | _EBI_RDTIMING1_RDSTRB_DEFAULT 0x0000003FUL |
#define | EBI_RDTIMING1_RDSTRB_DEFAULT (_EBI_RDTIMING1_RDSTRB_DEFAULT << 8) |
#define | _EBI_RDTIMING1_RDHOLD_SHIFT 16 |
#define | _EBI_RDTIMING1_RDHOLD_MASK 0x30000UL |
#define | _EBI_RDTIMING1_RDHOLD_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING1_RDHOLD_DEFAULT (_EBI_RDTIMING1_RDHOLD_DEFAULT << 16) |
#define | EBI_RDTIMING1_HALFRE (0x1UL << 28) |
#define | _EBI_RDTIMING1_HALFRE_SHIFT 28 |
#define | _EBI_RDTIMING1_HALFRE_MASK 0x10000000UL |
#define | _EBI_RDTIMING1_HALFRE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING1_HALFRE_DEFAULT (_EBI_RDTIMING1_HALFRE_DEFAULT << 28) |
#define | EBI_RDTIMING1_PREFETCH (0x1UL << 29) |
#define | _EBI_RDTIMING1_PREFETCH_SHIFT 29 |
#define | _EBI_RDTIMING1_PREFETCH_MASK 0x20000000UL |
#define | _EBI_RDTIMING1_PREFETCH_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING1_PREFETCH_DEFAULT (_EBI_RDTIMING1_PREFETCH_DEFAULT << 29) |
#define | EBI_RDTIMING1_PAGEMODE (0x1UL << 30) |
#define | _EBI_RDTIMING1_PAGEMODE_SHIFT 30 |
#define | _EBI_RDTIMING1_PAGEMODE_MASK 0x40000000UL |
#define | _EBI_RDTIMING1_PAGEMODE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING1_PAGEMODE_DEFAULT (_EBI_RDTIMING1_PAGEMODE_DEFAULT << 30) |
#define | _EBI_WRTIMING1_RESETVALUE 0x00033F03UL |
#define | _EBI_WRTIMING1_MASK 0x30033F03UL |
#define | _EBI_WRTIMING1_WRSETUP_SHIFT 0 |
#define | _EBI_WRTIMING1_WRSETUP_MASK 0x3UL |
#define | _EBI_WRTIMING1_WRSETUP_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING1_WRSETUP_DEFAULT (_EBI_WRTIMING1_WRSETUP_DEFAULT << 0) |
#define | _EBI_WRTIMING1_WRSTRB_SHIFT 8 |
#define | _EBI_WRTIMING1_WRSTRB_MASK 0x3F00UL |
#define | _EBI_WRTIMING1_WRSTRB_DEFAULT 0x0000003FUL |
#define | EBI_WRTIMING1_WRSTRB_DEFAULT (_EBI_WRTIMING1_WRSTRB_DEFAULT << 8) |
#define | _EBI_WRTIMING1_WRHOLD_SHIFT 16 |
#define | _EBI_WRTIMING1_WRHOLD_MASK 0x30000UL |
#define | _EBI_WRTIMING1_WRHOLD_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING1_WRHOLD_DEFAULT (_EBI_WRTIMING1_WRHOLD_DEFAULT << 16) |
#define | EBI_WRTIMING1_HALFWE (0x1UL << 28) |
#define | _EBI_WRTIMING1_HALFWE_SHIFT 28 |
#define | _EBI_WRTIMING1_HALFWE_MASK 0x10000000UL |
#define | _EBI_WRTIMING1_HALFWE_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING1_HALFWE_DEFAULT (_EBI_WRTIMING1_HALFWE_DEFAULT << 28) |
#define | EBI_WRTIMING1_WBUFDIS (0x1UL << 29) |
#define | _EBI_WRTIMING1_WBUFDIS_SHIFT 29 |
#define | _EBI_WRTIMING1_WBUFDIS_MASK 0x20000000UL |
#define | _EBI_WRTIMING1_WBUFDIS_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING1_WBUFDIS_DEFAULT (_EBI_WRTIMING1_WBUFDIS_DEFAULT << 29) |
#define | _EBI_POLARITY1_RESETVALUE 0x00000000UL |
#define | _EBI_POLARITY1_MASK 0x0000003FUL |
#define | EBI_POLARITY1_CSPOL (0x1UL << 0) |
#define | _EBI_POLARITY1_CSPOL_SHIFT 0 |
#define | _EBI_POLARITY1_CSPOL_MASK 0x1UL |
#define | _EBI_POLARITY1_CSPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY1_CSPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY1_CSPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY1_CSPOL_DEFAULT (_EBI_POLARITY1_CSPOL_DEFAULT << 0) |
#define | EBI_POLARITY1_CSPOL_ACTIVELOW (_EBI_POLARITY1_CSPOL_ACTIVELOW << 0) |
#define | EBI_POLARITY1_CSPOL_ACTIVEHIGH (_EBI_POLARITY1_CSPOL_ACTIVEHIGH << 0) |
#define | EBI_POLARITY1_REPOL (0x1UL << 1) |
#define | _EBI_POLARITY1_REPOL_SHIFT 1 |
#define | _EBI_POLARITY1_REPOL_MASK 0x2UL |
#define | _EBI_POLARITY1_REPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY1_REPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY1_REPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY1_REPOL_DEFAULT (_EBI_POLARITY1_REPOL_DEFAULT << 1) |
#define | EBI_POLARITY1_REPOL_ACTIVELOW (_EBI_POLARITY1_REPOL_ACTIVELOW << 1) |
#define | EBI_POLARITY1_REPOL_ACTIVEHIGH (_EBI_POLARITY1_REPOL_ACTIVEHIGH << 1) |
#define | EBI_POLARITY1_WEPOL (0x1UL << 2) |
#define | _EBI_POLARITY1_WEPOL_SHIFT 2 |
#define | _EBI_POLARITY1_WEPOL_MASK 0x4UL |
#define | _EBI_POLARITY1_WEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY1_WEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY1_WEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY1_WEPOL_DEFAULT (_EBI_POLARITY1_WEPOL_DEFAULT << 2) |
#define | EBI_POLARITY1_WEPOL_ACTIVELOW (_EBI_POLARITY1_WEPOL_ACTIVELOW << 2) |
#define | EBI_POLARITY1_WEPOL_ACTIVEHIGH (_EBI_POLARITY1_WEPOL_ACTIVEHIGH << 2) |
#define | EBI_POLARITY1_ALEPOL (0x1UL << 3) |
#define | _EBI_POLARITY1_ALEPOL_SHIFT 3 |
#define | _EBI_POLARITY1_ALEPOL_MASK 0x8UL |
#define | _EBI_POLARITY1_ALEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY1_ALEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY1_ALEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY1_ALEPOL_DEFAULT (_EBI_POLARITY1_ALEPOL_DEFAULT << 3) |
#define | EBI_POLARITY1_ALEPOL_ACTIVELOW (_EBI_POLARITY1_ALEPOL_ACTIVELOW << 3) |
#define | EBI_POLARITY1_ALEPOL_ACTIVEHIGH (_EBI_POLARITY1_ALEPOL_ACTIVEHIGH << 3) |
#define | EBI_POLARITY1_ARDYPOL (0x1UL << 4) |
#define | _EBI_POLARITY1_ARDYPOL_SHIFT 4 |
#define | _EBI_POLARITY1_ARDYPOL_MASK 0x10UL |
#define | _EBI_POLARITY1_ARDYPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY1_ARDYPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY1_ARDYPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY1_ARDYPOL_DEFAULT (_EBI_POLARITY1_ARDYPOL_DEFAULT << 4) |
#define | EBI_POLARITY1_ARDYPOL_ACTIVELOW (_EBI_POLARITY1_ARDYPOL_ACTIVELOW << 4) |
#define | EBI_POLARITY1_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY1_ARDYPOL_ACTIVEHIGH << 4) |
#define | EBI_POLARITY1_BLPOL (0x1UL << 5) |
#define | _EBI_POLARITY1_BLPOL_SHIFT 5 |
#define | _EBI_POLARITY1_BLPOL_MASK 0x20UL |
#define | _EBI_POLARITY1_BLPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY1_BLPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY1_BLPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY1_BLPOL_DEFAULT (_EBI_POLARITY1_BLPOL_DEFAULT << 5) |
#define | EBI_POLARITY1_BLPOL_ACTIVELOW (_EBI_POLARITY1_BLPOL_ACTIVELOW << 5) |
#define | EBI_POLARITY1_BLPOL_ACTIVEHIGH (_EBI_POLARITY1_BLPOL_ACTIVEHIGH << 5) |
#define | _EBI_ADDRTIMING2_RESETVALUE 0x00000303UL |
#define | _EBI_ADDRTIMING2_MASK 0x10000303UL |
#define | _EBI_ADDRTIMING2_ADDRSETUP_SHIFT 0 |
#define | _EBI_ADDRTIMING2_ADDRSETUP_MASK 0x3UL |
#define | _EBI_ADDRTIMING2_ADDRSETUP_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING2_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING2_ADDRSETUP_DEFAULT << 0) |
#define | _EBI_ADDRTIMING2_ADDRHOLD_SHIFT 8 |
#define | _EBI_ADDRTIMING2_ADDRHOLD_MASK 0x300UL |
#define | _EBI_ADDRTIMING2_ADDRHOLD_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING2_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING2_ADDRHOLD_DEFAULT << 8) |
#define | EBI_ADDRTIMING2_HALFALE (0x1UL << 28) |
#define | _EBI_ADDRTIMING2_HALFALE_SHIFT 28 |
#define | _EBI_ADDRTIMING2_HALFALE_MASK 0x10000000UL |
#define | _EBI_ADDRTIMING2_HALFALE_DEFAULT 0x00000000UL |
#define | EBI_ADDRTIMING2_HALFALE_DEFAULT (_EBI_ADDRTIMING2_HALFALE_DEFAULT << 28) |
#define | _EBI_RDTIMING2_RESETVALUE 0x00033F03UL |
#define | _EBI_RDTIMING2_MASK 0x70033F03UL |
#define | _EBI_RDTIMING2_RDSETUP_SHIFT 0 |
#define | _EBI_RDTIMING2_RDSETUP_MASK 0x3UL |
#define | _EBI_RDTIMING2_RDSETUP_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING2_RDSETUP_DEFAULT (_EBI_RDTIMING2_RDSETUP_DEFAULT << 0) |
#define | _EBI_RDTIMING2_RDSTRB_SHIFT 8 |
#define | _EBI_RDTIMING2_RDSTRB_MASK 0x3F00UL |
#define | _EBI_RDTIMING2_RDSTRB_DEFAULT 0x0000003FUL |
#define | EBI_RDTIMING2_RDSTRB_DEFAULT (_EBI_RDTIMING2_RDSTRB_DEFAULT << 8) |
#define | _EBI_RDTIMING2_RDHOLD_SHIFT 16 |
#define | _EBI_RDTIMING2_RDHOLD_MASK 0x30000UL |
#define | _EBI_RDTIMING2_RDHOLD_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING2_RDHOLD_DEFAULT (_EBI_RDTIMING2_RDHOLD_DEFAULT << 16) |
#define | EBI_RDTIMING2_HALFRE (0x1UL << 28) |
#define | _EBI_RDTIMING2_HALFRE_SHIFT 28 |
#define | _EBI_RDTIMING2_HALFRE_MASK 0x10000000UL |
#define | _EBI_RDTIMING2_HALFRE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING2_HALFRE_DEFAULT (_EBI_RDTIMING2_HALFRE_DEFAULT << 28) |
#define | EBI_RDTIMING2_PREFETCH (0x1UL << 29) |
#define | _EBI_RDTIMING2_PREFETCH_SHIFT 29 |
#define | _EBI_RDTIMING2_PREFETCH_MASK 0x20000000UL |
#define | _EBI_RDTIMING2_PREFETCH_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING2_PREFETCH_DEFAULT (_EBI_RDTIMING2_PREFETCH_DEFAULT << 29) |
#define | EBI_RDTIMING2_PAGEMODE (0x1UL << 30) |
#define | _EBI_RDTIMING2_PAGEMODE_SHIFT 30 |
#define | _EBI_RDTIMING2_PAGEMODE_MASK 0x40000000UL |
#define | _EBI_RDTIMING2_PAGEMODE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING2_PAGEMODE_DEFAULT (_EBI_RDTIMING2_PAGEMODE_DEFAULT << 30) |
#define | _EBI_WRTIMING2_RESETVALUE 0x00033F03UL |
#define | _EBI_WRTIMING2_MASK 0x30033F03UL |
#define | _EBI_WRTIMING2_WRSETUP_SHIFT 0 |
#define | _EBI_WRTIMING2_WRSETUP_MASK 0x3UL |
#define | _EBI_WRTIMING2_WRSETUP_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING2_WRSETUP_DEFAULT (_EBI_WRTIMING2_WRSETUP_DEFAULT << 0) |
#define | _EBI_WRTIMING2_WRSTRB_SHIFT 8 |
#define | _EBI_WRTIMING2_WRSTRB_MASK 0x3F00UL |
#define | _EBI_WRTIMING2_WRSTRB_DEFAULT 0x0000003FUL |
#define | EBI_WRTIMING2_WRSTRB_DEFAULT (_EBI_WRTIMING2_WRSTRB_DEFAULT << 8) |
#define | _EBI_WRTIMING2_WRHOLD_SHIFT 16 |
#define | _EBI_WRTIMING2_WRHOLD_MASK 0x30000UL |
#define | _EBI_WRTIMING2_WRHOLD_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING2_WRHOLD_DEFAULT (_EBI_WRTIMING2_WRHOLD_DEFAULT << 16) |
#define | EBI_WRTIMING2_HALFWE (0x1UL << 28) |
#define | _EBI_WRTIMING2_HALFWE_SHIFT 28 |
#define | _EBI_WRTIMING2_HALFWE_MASK 0x10000000UL |
#define | _EBI_WRTIMING2_HALFWE_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING2_HALFWE_DEFAULT (_EBI_WRTIMING2_HALFWE_DEFAULT << 28) |
#define | EBI_WRTIMING2_WBUFDIS (0x1UL << 29) |
#define | _EBI_WRTIMING2_WBUFDIS_SHIFT 29 |
#define | _EBI_WRTIMING2_WBUFDIS_MASK 0x20000000UL |
#define | _EBI_WRTIMING2_WBUFDIS_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING2_WBUFDIS_DEFAULT (_EBI_WRTIMING2_WBUFDIS_DEFAULT << 29) |
#define | _EBI_POLARITY2_RESETVALUE 0x00000000UL |
#define | _EBI_POLARITY2_MASK 0x0000003FUL |
#define | EBI_POLARITY2_CSPOL (0x1UL << 0) |
#define | _EBI_POLARITY2_CSPOL_SHIFT 0 |
#define | _EBI_POLARITY2_CSPOL_MASK 0x1UL |
#define | _EBI_POLARITY2_CSPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY2_CSPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY2_CSPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY2_CSPOL_DEFAULT (_EBI_POLARITY2_CSPOL_DEFAULT << 0) |
#define | EBI_POLARITY2_CSPOL_ACTIVELOW (_EBI_POLARITY2_CSPOL_ACTIVELOW << 0) |
#define | EBI_POLARITY2_CSPOL_ACTIVEHIGH (_EBI_POLARITY2_CSPOL_ACTIVEHIGH << 0) |
#define | EBI_POLARITY2_REPOL (0x1UL << 1) |
#define | _EBI_POLARITY2_REPOL_SHIFT 1 |
#define | _EBI_POLARITY2_REPOL_MASK 0x2UL |
#define | _EBI_POLARITY2_REPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY2_REPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY2_REPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY2_REPOL_DEFAULT (_EBI_POLARITY2_REPOL_DEFAULT << 1) |
#define | EBI_POLARITY2_REPOL_ACTIVELOW (_EBI_POLARITY2_REPOL_ACTIVELOW << 1) |
#define | EBI_POLARITY2_REPOL_ACTIVEHIGH (_EBI_POLARITY2_REPOL_ACTIVEHIGH << 1) |
#define | EBI_POLARITY2_WEPOL (0x1UL << 2) |
#define | _EBI_POLARITY2_WEPOL_SHIFT 2 |
#define | _EBI_POLARITY2_WEPOL_MASK 0x4UL |
#define | _EBI_POLARITY2_WEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY2_WEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY2_WEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY2_WEPOL_DEFAULT (_EBI_POLARITY2_WEPOL_DEFAULT << 2) |
#define | EBI_POLARITY2_WEPOL_ACTIVELOW (_EBI_POLARITY2_WEPOL_ACTIVELOW << 2) |
#define | EBI_POLARITY2_WEPOL_ACTIVEHIGH (_EBI_POLARITY2_WEPOL_ACTIVEHIGH << 2) |
#define | EBI_POLARITY2_ALEPOL (0x1UL << 3) |
#define | _EBI_POLARITY2_ALEPOL_SHIFT 3 |
#define | _EBI_POLARITY2_ALEPOL_MASK 0x8UL |
#define | _EBI_POLARITY2_ALEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY2_ALEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY2_ALEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY2_ALEPOL_DEFAULT (_EBI_POLARITY2_ALEPOL_DEFAULT << 3) |
#define | EBI_POLARITY2_ALEPOL_ACTIVELOW (_EBI_POLARITY2_ALEPOL_ACTIVELOW << 3) |
#define | EBI_POLARITY2_ALEPOL_ACTIVEHIGH (_EBI_POLARITY2_ALEPOL_ACTIVEHIGH << 3) |
#define | EBI_POLARITY2_ARDYPOL (0x1UL << 4) |
#define | _EBI_POLARITY2_ARDYPOL_SHIFT 4 |
#define | _EBI_POLARITY2_ARDYPOL_MASK 0x10UL |
#define | _EBI_POLARITY2_ARDYPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY2_ARDYPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY2_ARDYPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY2_ARDYPOL_DEFAULT (_EBI_POLARITY2_ARDYPOL_DEFAULT << 4) |
#define | EBI_POLARITY2_ARDYPOL_ACTIVELOW (_EBI_POLARITY2_ARDYPOL_ACTIVELOW << 4) |
#define | EBI_POLARITY2_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY2_ARDYPOL_ACTIVEHIGH << 4) |
#define | EBI_POLARITY2_BLPOL (0x1UL << 5) |
#define | _EBI_POLARITY2_BLPOL_SHIFT 5 |
#define | _EBI_POLARITY2_BLPOL_MASK 0x20UL |
#define | _EBI_POLARITY2_BLPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY2_BLPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY2_BLPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY2_BLPOL_DEFAULT (_EBI_POLARITY2_BLPOL_DEFAULT << 5) |
#define | EBI_POLARITY2_BLPOL_ACTIVELOW (_EBI_POLARITY2_BLPOL_ACTIVELOW << 5) |
#define | EBI_POLARITY2_BLPOL_ACTIVEHIGH (_EBI_POLARITY2_BLPOL_ACTIVEHIGH << 5) |
#define | _EBI_ADDRTIMING3_RESETVALUE 0x00000303UL |
#define | _EBI_ADDRTIMING3_MASK 0x10000303UL |
#define | _EBI_ADDRTIMING3_ADDRSETUP_SHIFT 0 |
#define | _EBI_ADDRTIMING3_ADDRSETUP_MASK 0x3UL |
#define | _EBI_ADDRTIMING3_ADDRSETUP_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING3_ADDRSETUP_DEFAULT (_EBI_ADDRTIMING3_ADDRSETUP_DEFAULT << 0) |
#define | _EBI_ADDRTIMING3_ADDRHOLD_SHIFT 8 |
#define | _EBI_ADDRTIMING3_ADDRHOLD_MASK 0x300UL |
#define | _EBI_ADDRTIMING3_ADDRHOLD_DEFAULT 0x00000003UL |
#define | EBI_ADDRTIMING3_ADDRHOLD_DEFAULT (_EBI_ADDRTIMING3_ADDRHOLD_DEFAULT << 8) |
#define | EBI_ADDRTIMING3_HALFALE (0x1UL << 28) |
#define | _EBI_ADDRTIMING3_HALFALE_SHIFT 28 |
#define | _EBI_ADDRTIMING3_HALFALE_MASK 0x10000000UL |
#define | _EBI_ADDRTIMING3_HALFALE_DEFAULT 0x00000000UL |
#define | EBI_ADDRTIMING3_HALFALE_DEFAULT (_EBI_ADDRTIMING3_HALFALE_DEFAULT << 28) |
#define | _EBI_RDTIMING3_RESETVALUE 0x00033F03UL |
#define | _EBI_RDTIMING3_MASK 0x70033F03UL |
#define | _EBI_RDTIMING3_RDSETUP_SHIFT 0 |
#define | _EBI_RDTIMING3_RDSETUP_MASK 0x3UL |
#define | _EBI_RDTIMING3_RDSETUP_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING3_RDSETUP_DEFAULT (_EBI_RDTIMING3_RDSETUP_DEFAULT << 0) |
#define | _EBI_RDTIMING3_RDSTRB_SHIFT 8 |
#define | _EBI_RDTIMING3_RDSTRB_MASK 0x3F00UL |
#define | _EBI_RDTIMING3_RDSTRB_DEFAULT 0x0000003FUL |
#define | EBI_RDTIMING3_RDSTRB_DEFAULT (_EBI_RDTIMING3_RDSTRB_DEFAULT << 8) |
#define | _EBI_RDTIMING3_RDHOLD_SHIFT 16 |
#define | _EBI_RDTIMING3_RDHOLD_MASK 0x30000UL |
#define | _EBI_RDTIMING3_RDHOLD_DEFAULT 0x00000003UL |
#define | EBI_RDTIMING3_RDHOLD_DEFAULT (_EBI_RDTIMING3_RDHOLD_DEFAULT << 16) |
#define | EBI_RDTIMING3_HALFRE (0x1UL << 28) |
#define | _EBI_RDTIMING3_HALFRE_SHIFT 28 |
#define | _EBI_RDTIMING3_HALFRE_MASK 0x10000000UL |
#define | _EBI_RDTIMING3_HALFRE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING3_HALFRE_DEFAULT (_EBI_RDTIMING3_HALFRE_DEFAULT << 28) |
#define | EBI_RDTIMING3_PREFETCH (0x1UL << 29) |
#define | _EBI_RDTIMING3_PREFETCH_SHIFT 29 |
#define | _EBI_RDTIMING3_PREFETCH_MASK 0x20000000UL |
#define | _EBI_RDTIMING3_PREFETCH_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING3_PREFETCH_DEFAULT (_EBI_RDTIMING3_PREFETCH_DEFAULT << 29) |
#define | EBI_RDTIMING3_PAGEMODE (0x1UL << 30) |
#define | _EBI_RDTIMING3_PAGEMODE_SHIFT 30 |
#define | _EBI_RDTIMING3_PAGEMODE_MASK 0x40000000UL |
#define | _EBI_RDTIMING3_PAGEMODE_DEFAULT 0x00000000UL |
#define | EBI_RDTIMING3_PAGEMODE_DEFAULT (_EBI_RDTIMING3_PAGEMODE_DEFAULT << 30) |
#define | _EBI_WRTIMING3_RESETVALUE 0x00033F03UL |
#define | _EBI_WRTIMING3_MASK 0x30033F03UL |
#define | _EBI_WRTIMING3_WRSETUP_SHIFT 0 |
#define | _EBI_WRTIMING3_WRSETUP_MASK 0x3UL |
#define | _EBI_WRTIMING3_WRSETUP_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING3_WRSETUP_DEFAULT (_EBI_WRTIMING3_WRSETUP_DEFAULT << 0) |
#define | _EBI_WRTIMING3_WRSTRB_SHIFT 8 |
#define | _EBI_WRTIMING3_WRSTRB_MASK 0x3F00UL |
#define | _EBI_WRTIMING3_WRSTRB_DEFAULT 0x0000003FUL |
#define | EBI_WRTIMING3_WRSTRB_DEFAULT (_EBI_WRTIMING3_WRSTRB_DEFAULT << 8) |
#define | _EBI_WRTIMING3_WRHOLD_SHIFT 16 |
#define | _EBI_WRTIMING3_WRHOLD_MASK 0x30000UL |
#define | _EBI_WRTIMING3_WRHOLD_DEFAULT 0x00000003UL |
#define | EBI_WRTIMING3_WRHOLD_DEFAULT (_EBI_WRTIMING3_WRHOLD_DEFAULT << 16) |
#define | EBI_WRTIMING3_HALFWE (0x1UL << 28) |
#define | _EBI_WRTIMING3_HALFWE_SHIFT 28 |
#define | _EBI_WRTIMING3_HALFWE_MASK 0x10000000UL |
#define | _EBI_WRTIMING3_HALFWE_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING3_HALFWE_DEFAULT (_EBI_WRTIMING3_HALFWE_DEFAULT << 28) |
#define | EBI_WRTIMING3_WBUFDIS (0x1UL << 29) |
#define | _EBI_WRTIMING3_WBUFDIS_SHIFT 29 |
#define | _EBI_WRTIMING3_WBUFDIS_MASK 0x20000000UL |
#define | _EBI_WRTIMING3_WBUFDIS_DEFAULT 0x00000000UL |
#define | EBI_WRTIMING3_WBUFDIS_DEFAULT (_EBI_WRTIMING3_WBUFDIS_DEFAULT << 29) |
#define | _EBI_POLARITY3_RESETVALUE 0x00000000UL |
#define | _EBI_POLARITY3_MASK 0x0000003FUL |
#define | EBI_POLARITY3_CSPOL (0x1UL << 0) |
#define | _EBI_POLARITY3_CSPOL_SHIFT 0 |
#define | _EBI_POLARITY3_CSPOL_MASK 0x1UL |
#define | _EBI_POLARITY3_CSPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY3_CSPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY3_CSPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY3_CSPOL_DEFAULT (_EBI_POLARITY3_CSPOL_DEFAULT << 0) |
#define | EBI_POLARITY3_CSPOL_ACTIVELOW (_EBI_POLARITY3_CSPOL_ACTIVELOW << 0) |
#define | EBI_POLARITY3_CSPOL_ACTIVEHIGH (_EBI_POLARITY3_CSPOL_ACTIVEHIGH << 0) |
#define | EBI_POLARITY3_REPOL (0x1UL << 1) |
#define | _EBI_POLARITY3_REPOL_SHIFT 1 |
#define | _EBI_POLARITY3_REPOL_MASK 0x2UL |
#define | _EBI_POLARITY3_REPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY3_REPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY3_REPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY3_REPOL_DEFAULT (_EBI_POLARITY3_REPOL_DEFAULT << 1) |
#define | EBI_POLARITY3_REPOL_ACTIVELOW (_EBI_POLARITY3_REPOL_ACTIVELOW << 1) |
#define | EBI_POLARITY3_REPOL_ACTIVEHIGH (_EBI_POLARITY3_REPOL_ACTIVEHIGH << 1) |
#define | EBI_POLARITY3_WEPOL (0x1UL << 2) |
#define | _EBI_POLARITY3_WEPOL_SHIFT 2 |
#define | _EBI_POLARITY3_WEPOL_MASK 0x4UL |
#define | _EBI_POLARITY3_WEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY3_WEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY3_WEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY3_WEPOL_DEFAULT (_EBI_POLARITY3_WEPOL_DEFAULT << 2) |
#define | EBI_POLARITY3_WEPOL_ACTIVELOW (_EBI_POLARITY3_WEPOL_ACTIVELOW << 2) |
#define | EBI_POLARITY3_WEPOL_ACTIVEHIGH (_EBI_POLARITY3_WEPOL_ACTIVEHIGH << 2) |
#define | EBI_POLARITY3_ALEPOL (0x1UL << 3) |
#define | _EBI_POLARITY3_ALEPOL_SHIFT 3 |
#define | _EBI_POLARITY3_ALEPOL_MASK 0x8UL |
#define | _EBI_POLARITY3_ALEPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY3_ALEPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY3_ALEPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY3_ALEPOL_DEFAULT (_EBI_POLARITY3_ALEPOL_DEFAULT << 3) |
#define | EBI_POLARITY3_ALEPOL_ACTIVELOW (_EBI_POLARITY3_ALEPOL_ACTIVELOW << 3) |
#define | EBI_POLARITY3_ALEPOL_ACTIVEHIGH (_EBI_POLARITY3_ALEPOL_ACTIVEHIGH << 3) |
#define | EBI_POLARITY3_ARDYPOL (0x1UL << 4) |
#define | _EBI_POLARITY3_ARDYPOL_SHIFT 4 |
#define | _EBI_POLARITY3_ARDYPOL_MASK 0x10UL |
#define | _EBI_POLARITY3_ARDYPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY3_ARDYPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY3_ARDYPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY3_ARDYPOL_DEFAULT (_EBI_POLARITY3_ARDYPOL_DEFAULT << 4) |
#define | EBI_POLARITY3_ARDYPOL_ACTIVELOW (_EBI_POLARITY3_ARDYPOL_ACTIVELOW << 4) |
#define | EBI_POLARITY3_ARDYPOL_ACTIVEHIGH (_EBI_POLARITY3_ARDYPOL_ACTIVEHIGH << 4) |
#define | EBI_POLARITY3_BLPOL (0x1UL << 5) |
#define | _EBI_POLARITY3_BLPOL_SHIFT 5 |
#define | _EBI_POLARITY3_BLPOL_MASK 0x20UL |
#define | _EBI_POLARITY3_BLPOL_DEFAULT 0x00000000UL |
#define | _EBI_POLARITY3_BLPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_POLARITY3_BLPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_POLARITY3_BLPOL_DEFAULT (_EBI_POLARITY3_BLPOL_DEFAULT << 5) |
#define | EBI_POLARITY3_BLPOL_ACTIVELOW (_EBI_POLARITY3_BLPOL_ACTIVELOW << 5) |
#define | EBI_POLARITY3_BLPOL_ACTIVEHIGH (_EBI_POLARITY3_BLPOL_ACTIVEHIGH << 5) |
#define | _EBI_PAGECTRL_RESETVALUE 0x00000700UL |
#define | _EBI_PAGECTRL_MASK 0x07F00713UL |
#define | _EBI_PAGECTRL_PAGELEN_SHIFT 0 |
#define | _EBI_PAGECTRL_PAGELEN_MASK 0x3UL |
#define | _EBI_PAGECTRL_PAGELEN_DEFAULT 0x00000000UL |
#define | _EBI_PAGECTRL_PAGELEN_MEMBER4 0x00000000UL |
#define | _EBI_PAGECTRL_PAGELEN_MEMBER8 0x00000001UL |
#define | _EBI_PAGECTRL_PAGELEN_MEMBER16 0x00000002UL |
#define | _EBI_PAGECTRL_PAGELEN_MEMBER32 0x00000003UL |
#define | EBI_PAGECTRL_PAGELEN_DEFAULT (_EBI_PAGECTRL_PAGELEN_DEFAULT << 0) |
#define | EBI_PAGECTRL_PAGELEN_MEMBER4 (_EBI_PAGECTRL_PAGELEN_MEMBER4 << 0) |
#define | EBI_PAGECTRL_PAGELEN_MEMBER8 (_EBI_PAGECTRL_PAGELEN_MEMBER8 << 0) |
#define | EBI_PAGECTRL_PAGELEN_MEMBER16 (_EBI_PAGECTRL_PAGELEN_MEMBER16 << 0) |
#define | EBI_PAGECTRL_PAGELEN_MEMBER32 (_EBI_PAGECTRL_PAGELEN_MEMBER32 << 0) |
#define | EBI_PAGECTRL_INCHIT (0x1UL << 4) |
#define | _EBI_PAGECTRL_INCHIT_SHIFT 4 |
#define | _EBI_PAGECTRL_INCHIT_MASK 0x10UL |
#define | _EBI_PAGECTRL_INCHIT_DEFAULT 0x00000000UL |
#define | EBI_PAGECTRL_INCHIT_DEFAULT (_EBI_PAGECTRL_INCHIT_DEFAULT << 4) |
#define | _EBI_PAGECTRL_RDPA_SHIFT 8 |
#define | _EBI_PAGECTRL_RDPA_MASK 0x700UL |
#define | _EBI_PAGECTRL_RDPA_DEFAULT 0x00000007UL |
#define | EBI_PAGECTRL_RDPA_DEFAULT (_EBI_PAGECTRL_RDPA_DEFAULT << 8) |
#define | _EBI_PAGECTRL_KEEPOPEN_SHIFT 20 |
#define | _EBI_PAGECTRL_KEEPOPEN_MASK 0x7F00000UL |
#define | _EBI_PAGECTRL_KEEPOPEN_DEFAULT 0x00000000UL |
#define | EBI_PAGECTRL_KEEPOPEN_DEFAULT (_EBI_PAGECTRL_KEEPOPEN_DEFAULT << 20) |
#define | _EBI_NANDCTRL_RESETVALUE 0x00000000UL |
#define | _EBI_NANDCTRL_MASK 0x00000031UL |
#define | EBI_NANDCTRL_EN (0x1UL << 0) |
#define | _EBI_NANDCTRL_EN_SHIFT 0 |
#define | _EBI_NANDCTRL_EN_MASK 0x1UL |
#define | _EBI_NANDCTRL_EN_DEFAULT 0x00000000UL |
#define | EBI_NANDCTRL_EN_DEFAULT (_EBI_NANDCTRL_EN_DEFAULT << 0) |
#define | _EBI_NANDCTRL_BANKSEL_SHIFT 4 |
#define | _EBI_NANDCTRL_BANKSEL_MASK 0x30UL |
#define | _EBI_NANDCTRL_BANKSEL_DEFAULT 0x00000000UL |
#define | _EBI_NANDCTRL_BANKSEL_BANK0 0x00000000UL |
#define | _EBI_NANDCTRL_BANKSEL_BANK1 0x00000001UL |
#define | _EBI_NANDCTRL_BANKSEL_BANK2 0x00000002UL |
#define | _EBI_NANDCTRL_BANKSEL_BANK3 0x00000003UL |
#define | EBI_NANDCTRL_BANKSEL_DEFAULT (_EBI_NANDCTRL_BANKSEL_DEFAULT << 4) |
#define | EBI_NANDCTRL_BANKSEL_BANK0 (_EBI_NANDCTRL_BANKSEL_BANK0 << 4) |
#define | EBI_NANDCTRL_BANKSEL_BANK1 (_EBI_NANDCTRL_BANKSEL_BANK1 << 4) |
#define | EBI_NANDCTRL_BANKSEL_BANK2 (_EBI_NANDCTRL_BANKSEL_BANK2 << 4) |
#define | EBI_NANDCTRL_BANKSEL_BANK3 (_EBI_NANDCTRL_BANKSEL_BANK3 << 4) |
#define | _EBI_CMD_RESETVALUE 0x00000000UL |
#define | _EBI_CMD_MASK 0x00000007UL |
#define | EBI_CMD_ECCSTART (0x1UL << 0) |
#define | _EBI_CMD_ECCSTART_SHIFT 0 |
#define | _EBI_CMD_ECCSTART_MASK 0x1UL |
#define | _EBI_CMD_ECCSTART_DEFAULT 0x00000000UL |
#define | EBI_CMD_ECCSTART_DEFAULT (_EBI_CMD_ECCSTART_DEFAULT << 0) |
#define | EBI_CMD_ECCSTOP (0x1UL << 1) |
#define | _EBI_CMD_ECCSTOP_SHIFT 1 |
#define | _EBI_CMD_ECCSTOP_MASK 0x2UL |
#define | _EBI_CMD_ECCSTOP_DEFAULT 0x00000000UL |
#define | EBI_CMD_ECCSTOP_DEFAULT (_EBI_CMD_ECCSTOP_DEFAULT << 1) |
#define | EBI_CMD_ECCCLEAR (0x1UL << 2) |
#define | _EBI_CMD_ECCCLEAR_SHIFT 2 |
#define | _EBI_CMD_ECCCLEAR_MASK 0x4UL |
#define | _EBI_CMD_ECCCLEAR_DEFAULT 0x00000000UL |
#define | EBI_CMD_ECCCLEAR_DEFAULT (_EBI_CMD_ECCCLEAR_DEFAULT << 2) |
#define | _EBI_STATUS_RESETVALUE 0x00000000UL |
#define | _EBI_STATUS_MASK 0x00003711UL |
#define | EBI_STATUS_AHBACT (0x1UL << 0) |
#define | _EBI_STATUS_AHBACT_SHIFT 0 |
#define | _EBI_STATUS_AHBACT_MASK 0x1UL |
#define | _EBI_STATUS_AHBACT_DEFAULT 0x00000000UL |
#define | EBI_STATUS_AHBACT_DEFAULT (_EBI_STATUS_AHBACT_DEFAULT << 0) |
#define | EBI_STATUS_ECCACT (0x1UL << 4) |
#define | _EBI_STATUS_ECCACT_SHIFT 4 |
#define | _EBI_STATUS_ECCACT_MASK 0x10UL |
#define | _EBI_STATUS_ECCACT_DEFAULT 0x00000000UL |
#define | EBI_STATUS_ECCACT_DEFAULT (_EBI_STATUS_ECCACT_DEFAULT << 4) |
#define | EBI_STATUS_TFTPIXEL0EMPTY (0x1UL << 8) |
#define | _EBI_STATUS_TFTPIXEL0EMPTY_SHIFT 8 |
#define | _EBI_STATUS_TFTPIXEL0EMPTY_MASK 0x100UL |
#define | _EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT 0x00000000UL |
#define | EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL0EMPTY_DEFAULT << 8) |
#define | EBI_STATUS_TFTPIXEL1EMPTY (0x1UL << 9) |
#define | _EBI_STATUS_TFTPIXEL1EMPTY_SHIFT 9 |
#define | _EBI_STATUS_TFTPIXEL1EMPTY_MASK 0x200UL |
#define | _EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT 0x00000000UL |
#define | EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT (_EBI_STATUS_TFTPIXEL1EMPTY_DEFAULT << 9) |
#define | EBI_STATUS_TFTPIXELFULL (0x1UL << 10) |
#define | _EBI_STATUS_TFTPIXELFULL_SHIFT 10 |
#define | _EBI_STATUS_TFTPIXELFULL_MASK 0x400UL |
#define | _EBI_STATUS_TFTPIXELFULL_DEFAULT 0x00000000UL |
#define | EBI_STATUS_TFTPIXELFULL_DEFAULT (_EBI_STATUS_TFTPIXELFULL_DEFAULT << 10) |
#define | EBI_STATUS_DDACT (0x1UL << 12) |
#define | _EBI_STATUS_DDACT_SHIFT 12 |
#define | _EBI_STATUS_DDACT_MASK 0x1000UL |
#define | _EBI_STATUS_DDACT_DEFAULT 0x00000000UL |
#define | EBI_STATUS_DDACT_DEFAULT (_EBI_STATUS_DDACT_DEFAULT << 12) |
#define | EBI_STATUS_TFTDDEMPTY (0x1UL << 13) |
#define | _EBI_STATUS_TFTDDEMPTY_SHIFT 13 |
#define | _EBI_STATUS_TFTDDEMPTY_MASK 0x2000UL |
#define | _EBI_STATUS_TFTDDEMPTY_DEFAULT 0x00000000UL |
#define | EBI_STATUS_TFTDDEMPTY_DEFAULT (_EBI_STATUS_TFTDDEMPTY_DEFAULT << 13) |
#define | _EBI_ECCPARITY_RESETVALUE 0x00000000UL |
#define | _EBI_ECCPARITY_MASK 0xFFFFFFFFUL |
#define | _EBI_ECCPARITY_ECCPARITY_SHIFT 0 |
#define | _EBI_ECCPARITY_ECCPARITY_MASK 0xFFFFFFFFUL |
#define | _EBI_ECCPARITY_ECCPARITY_DEFAULT 0x00000000UL |
#define | EBI_ECCPARITY_ECCPARITY_DEFAULT (_EBI_ECCPARITY_ECCPARITY_DEFAULT << 0) |
#define | _EBI_TFTCTRL_RESETVALUE 0x00000000UL |
#define | _EBI_TFTCTRL_MASK 0x01311F1FUL |
#define | _EBI_TFTCTRL_DD_SHIFT 0 |
#define | _EBI_TFTCTRL_DD_MASK 0x3UL |
#define | _EBI_TFTCTRL_DD_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_DD_DISABLED 0x00000000UL |
#define | _EBI_TFTCTRL_DD_INTERNAL 0x00000001UL |
#define | _EBI_TFTCTRL_DD_EXTERNAL 0x00000002UL |
#define | EBI_TFTCTRL_DD_DEFAULT (_EBI_TFTCTRL_DD_DEFAULT << 0) |
#define | EBI_TFTCTRL_DD_DISABLED (_EBI_TFTCTRL_DD_DISABLED << 0) |
#define | EBI_TFTCTRL_DD_INTERNAL (_EBI_TFTCTRL_DD_INTERNAL << 0) |
#define | EBI_TFTCTRL_DD_EXTERNAL (_EBI_TFTCTRL_DD_EXTERNAL << 0) |
#define | _EBI_TFTCTRL_MASKBLEND_SHIFT 2 |
#define | _EBI_TFTCTRL_MASKBLEND_MASK 0x1CUL |
#define | _EBI_TFTCTRL_MASKBLEND_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_MASKBLEND_DISABLED 0x00000000UL |
#define | _EBI_TFTCTRL_MASKBLEND_IMASK 0x00000001UL |
#define | _EBI_TFTCTRL_MASKBLEND_IALPHA 0x00000002UL |
#define | _EBI_TFTCTRL_MASKBLEND_IMASKIALPHA 0x00000003UL |
#define | _EBI_TFTCTRL_MASKBLEND_EMASK 0x00000005UL |
#define | _EBI_TFTCTRL_MASKBLEND_EALPHA 0x00000006UL |
#define | _EBI_TFTCTRL_MASKBLEND_EMASKEALPHA 0x00000007UL |
#define | EBI_TFTCTRL_MASKBLEND_DEFAULT (_EBI_TFTCTRL_MASKBLEND_DEFAULT << 2) |
#define | EBI_TFTCTRL_MASKBLEND_DISABLED (_EBI_TFTCTRL_MASKBLEND_DISABLED << 2) |
#define | EBI_TFTCTRL_MASKBLEND_IMASK (_EBI_TFTCTRL_MASKBLEND_IMASK << 2) |
#define | EBI_TFTCTRL_MASKBLEND_IALPHA (_EBI_TFTCTRL_MASKBLEND_IALPHA << 2) |
#define | EBI_TFTCTRL_MASKBLEND_IMASKIALPHA (_EBI_TFTCTRL_MASKBLEND_IMASKIALPHA << 2) |
#define | EBI_TFTCTRL_MASKBLEND_EMASK (_EBI_TFTCTRL_MASKBLEND_EMASK << 2) |
#define | EBI_TFTCTRL_MASKBLEND_EALPHA (_EBI_TFTCTRL_MASKBLEND_EALPHA << 2) |
#define | EBI_TFTCTRL_MASKBLEND_EMASKEALPHA (_EBI_TFTCTRL_MASKBLEND_EMASKEALPHA << 2) |
#define | EBI_TFTCTRL_SHIFTDCLKEN (0x1UL << 8) |
#define | _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT 8 |
#define | _EBI_TFTCTRL_SHIFTDCLKEN_MASK 0x100UL |
#define | _EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT 0x00000000UL |
#define | EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT (_EBI_TFTCTRL_SHIFTDCLKEN_DEFAULT << 8) |
#define | EBI_TFTCTRL_FBCTRIG (0x1UL << 9) |
#define | _EBI_TFTCTRL_FBCTRIG_SHIFT 9 |
#define | _EBI_TFTCTRL_FBCTRIG_MASK 0x200UL |
#define | _EBI_TFTCTRL_FBCTRIG_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_FBCTRIG_VSYNC 0x00000000UL |
#define | _EBI_TFTCTRL_FBCTRIG_HSYNC 0x00000001UL |
#define | EBI_TFTCTRL_FBCTRIG_DEFAULT (_EBI_TFTCTRL_FBCTRIG_DEFAULT << 9) |
#define | EBI_TFTCTRL_FBCTRIG_VSYNC (_EBI_TFTCTRL_FBCTRIG_VSYNC << 9) |
#define | EBI_TFTCTRL_FBCTRIG_HSYNC (_EBI_TFTCTRL_FBCTRIG_HSYNC << 9) |
#define | _EBI_TFTCTRL_INTERLEAVE_SHIFT 10 |
#define | _EBI_TFTCTRL_INTERLEAVE_MASK 0xC00UL |
#define | _EBI_TFTCTRL_INTERLEAVE_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_INTERLEAVE_UNLIMITED 0x00000000UL |
#define | _EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK 0x00000001UL |
#define | _EBI_TFTCTRL_INTERLEAVE_PORCH 0x00000002UL |
#define | EBI_TFTCTRL_INTERLEAVE_DEFAULT (_EBI_TFTCTRL_INTERLEAVE_DEFAULT << 10) |
#define | EBI_TFTCTRL_INTERLEAVE_UNLIMITED (_EBI_TFTCTRL_INTERLEAVE_UNLIMITED << 10) |
#define | EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK (_EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK << 10) |
#define | EBI_TFTCTRL_INTERLEAVE_PORCH (_EBI_TFTCTRL_INTERLEAVE_PORCH << 10) |
#define | EBI_TFTCTRL_COLOR1SRC (0x1UL << 12) |
#define | _EBI_TFTCTRL_COLOR1SRC_SHIFT 12 |
#define | _EBI_TFTCTRL_COLOR1SRC_MASK 0x1000UL |
#define | _EBI_TFTCTRL_COLOR1SRC_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_COLOR1SRC_MEM 0x00000000UL |
#define | _EBI_TFTCTRL_COLOR1SRC_PIXEL1 0x00000001UL |
#define | EBI_TFTCTRL_COLOR1SRC_DEFAULT (_EBI_TFTCTRL_COLOR1SRC_DEFAULT << 12) |
#define | EBI_TFTCTRL_COLOR1SRC_MEM (_EBI_TFTCTRL_COLOR1SRC_MEM << 12) |
#define | EBI_TFTCTRL_COLOR1SRC_PIXEL1 (_EBI_TFTCTRL_COLOR1SRC_PIXEL1 << 12) |
#define | EBI_TFTCTRL_WIDTH (0x1UL << 16) |
#define | _EBI_TFTCTRL_WIDTH_SHIFT 16 |
#define | _EBI_TFTCTRL_WIDTH_MASK 0x10000UL |
#define | _EBI_TFTCTRL_WIDTH_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_WIDTH_BYTE 0x00000000UL |
#define | _EBI_TFTCTRL_WIDTH_HALFWORD 0x00000001UL |
#define | EBI_TFTCTRL_WIDTH_DEFAULT (_EBI_TFTCTRL_WIDTH_DEFAULT << 16) |
#define | EBI_TFTCTRL_WIDTH_BYTE (_EBI_TFTCTRL_WIDTH_BYTE << 16) |
#define | EBI_TFTCTRL_WIDTH_HALFWORD (_EBI_TFTCTRL_WIDTH_HALFWORD << 16) |
#define | _EBI_TFTCTRL_BANKSEL_SHIFT 20 |
#define | _EBI_TFTCTRL_BANKSEL_MASK 0x300000UL |
#define | _EBI_TFTCTRL_BANKSEL_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_BANKSEL_BANK0 0x00000000UL |
#define | _EBI_TFTCTRL_BANKSEL_BANK1 0x00000001UL |
#define | _EBI_TFTCTRL_BANKSEL_BANK2 0x00000002UL |
#define | _EBI_TFTCTRL_BANKSEL_BANK3 0x00000003UL |
#define | EBI_TFTCTRL_BANKSEL_DEFAULT (_EBI_TFTCTRL_BANKSEL_DEFAULT << 20) |
#define | EBI_TFTCTRL_BANKSEL_BANK0 (_EBI_TFTCTRL_BANKSEL_BANK0 << 20) |
#define | EBI_TFTCTRL_BANKSEL_BANK1 (_EBI_TFTCTRL_BANKSEL_BANK1 << 20) |
#define | EBI_TFTCTRL_BANKSEL_BANK2 (_EBI_TFTCTRL_BANKSEL_BANK2 << 20) |
#define | EBI_TFTCTRL_BANKSEL_BANK3 (_EBI_TFTCTRL_BANKSEL_BANK3 << 20) |
#define | EBI_TFTCTRL_RGBMODE (0x1UL << 24) |
#define | _EBI_TFTCTRL_RGBMODE_SHIFT 24 |
#define | _EBI_TFTCTRL_RGBMODE_MASK 0x1000000UL |
#define | _EBI_TFTCTRL_RGBMODE_DEFAULT 0x00000000UL |
#define | _EBI_TFTCTRL_RGBMODE_RGB565 0x00000000UL |
#define | _EBI_TFTCTRL_RGBMODE_RGB555 0x00000001UL |
#define | EBI_TFTCTRL_RGBMODE_DEFAULT (_EBI_TFTCTRL_RGBMODE_DEFAULT << 24) |
#define | EBI_TFTCTRL_RGBMODE_RGB565 (_EBI_TFTCTRL_RGBMODE_RGB565 << 24) |
#define | EBI_TFTCTRL_RGBMODE_RGB555 (_EBI_TFTCTRL_RGBMODE_RGB555 << 24) |
#define | _EBI_TFTSTATUS_RESETVALUE 0x00000000UL |
#define | _EBI_TFTSTATUS_MASK 0x07FF07FFUL |
#define | _EBI_TFTSTATUS_HCNT_SHIFT 0 |
#define | _EBI_TFTSTATUS_HCNT_MASK 0x7FFUL |
#define | _EBI_TFTSTATUS_HCNT_DEFAULT 0x00000000UL |
#define | EBI_TFTSTATUS_HCNT_DEFAULT (_EBI_TFTSTATUS_HCNT_DEFAULT << 0) |
#define | _EBI_TFTSTATUS_VCNT_SHIFT 16 |
#define | _EBI_TFTSTATUS_VCNT_MASK 0x7FF0000UL |
#define | _EBI_TFTSTATUS_VCNT_DEFAULT 0x00000000UL |
#define | EBI_TFTSTATUS_VCNT_DEFAULT (_EBI_TFTSTATUS_VCNT_DEFAULT << 16) |
#define | _EBI_TFTFRAMEBASE_RESETVALUE 0x00000000UL |
#define | _EBI_TFTFRAMEBASE_MASK 0x0FFFFFFFUL |
#define | _EBI_TFTFRAMEBASE_FRAMEBASE_SHIFT 0 |
#define | _EBI_TFTFRAMEBASE_FRAMEBASE_MASK 0xFFFFFFFUL |
#define | _EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT 0x00000000UL |
#define | EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT (_EBI_TFTFRAMEBASE_FRAMEBASE_DEFAULT << 0) |
#define | _EBI_TFTSTRIDE_RESETVALUE 0x00000000UL |
#define | _EBI_TFTSTRIDE_MASK 0x00000FFFUL |
#define | _EBI_TFTSTRIDE_HSTRIDE_SHIFT 0 |
#define | _EBI_TFTSTRIDE_HSTRIDE_MASK 0xFFFUL |
#define | _EBI_TFTSTRIDE_HSTRIDE_DEFAULT 0x00000000UL |
#define | EBI_TFTSTRIDE_HSTRIDE_DEFAULT (_EBI_TFTSTRIDE_HSTRIDE_DEFAULT << 0) |
#define | _EBI_TFTSIZE_RESETVALUE 0x00000000UL |
#define | _EBI_TFTSIZE_MASK 0x03FF03FFUL |
#define | _EBI_TFTSIZE_HSZ_SHIFT 0 |
#define | _EBI_TFTSIZE_HSZ_MASK 0x3FFUL |
#define | _EBI_TFTSIZE_HSZ_DEFAULT 0x00000000UL |
#define | EBI_TFTSIZE_HSZ_DEFAULT (_EBI_TFTSIZE_HSZ_DEFAULT << 0) |
#define | _EBI_TFTSIZE_VSZ_SHIFT 16 |
#define | _EBI_TFTSIZE_VSZ_MASK 0x3FF0000UL |
#define | _EBI_TFTSIZE_VSZ_DEFAULT 0x00000000UL |
#define | EBI_TFTSIZE_VSZ_DEFAULT (_EBI_TFTSIZE_VSZ_DEFAULT << 16) |
#define | _EBI_TFTHPORCH_RESETVALUE 0x00000000UL |
#define | _EBI_TFTHPORCH_MASK 0x33FCFF7FUL |
#define | _EBI_TFTHPORCH_HSYNC_SHIFT 0 |
#define | _EBI_TFTHPORCH_HSYNC_MASK 0x7FUL |
#define | _EBI_TFTHPORCH_HSYNC_DEFAULT 0x00000000UL |
#define | EBI_TFTHPORCH_HSYNC_DEFAULT (_EBI_TFTHPORCH_HSYNC_DEFAULT << 0) |
#define | _EBI_TFTHPORCH_HFPORCH_SHIFT 8 |
#define | _EBI_TFTHPORCH_HFPORCH_MASK 0xFF00UL |
#define | _EBI_TFTHPORCH_HFPORCH_DEFAULT 0x00000000UL |
#define | EBI_TFTHPORCH_HFPORCH_DEFAULT (_EBI_TFTHPORCH_HFPORCH_DEFAULT << 8) |
#define | _EBI_TFTHPORCH_HBPORCH_SHIFT 18 |
#define | _EBI_TFTHPORCH_HBPORCH_MASK 0x3FC0000UL |
#define | _EBI_TFTHPORCH_HBPORCH_DEFAULT 0x00000000UL |
#define | EBI_TFTHPORCH_HBPORCH_DEFAULT (_EBI_TFTHPORCH_HBPORCH_DEFAULT << 18) |
#define | _EBI_TFTHPORCH_HSYNCSTART_SHIFT 28 |
#define | _EBI_TFTHPORCH_HSYNCSTART_MASK 0x30000000UL |
#define | _EBI_TFTHPORCH_HSYNCSTART_DEFAULT 0x00000000UL |
#define | EBI_TFTHPORCH_HSYNCSTART_DEFAULT (_EBI_TFTHPORCH_HSYNCSTART_DEFAULT << 28) |
#define | _EBI_TFTVPORCH_RESETVALUE 0x00000000UL |
#define | _EBI_TFTVPORCH_MASK 0x03FCFF7FUL |
#define | _EBI_TFTVPORCH_VSYNC_SHIFT 0 |
#define | _EBI_TFTVPORCH_VSYNC_MASK 0x7FUL |
#define | _EBI_TFTVPORCH_VSYNC_DEFAULT 0x00000000UL |
#define | EBI_TFTVPORCH_VSYNC_DEFAULT (_EBI_TFTVPORCH_VSYNC_DEFAULT << 0) |
#define | _EBI_TFTVPORCH_VFPORCH_SHIFT 8 |
#define | _EBI_TFTVPORCH_VFPORCH_MASK 0xFF00UL |
#define | _EBI_TFTVPORCH_VFPORCH_DEFAULT 0x00000000UL |
#define | EBI_TFTVPORCH_VFPORCH_DEFAULT (_EBI_TFTVPORCH_VFPORCH_DEFAULT << 8) |
#define | _EBI_TFTVPORCH_VBPORCH_SHIFT 18 |
#define | _EBI_TFTVPORCH_VBPORCH_MASK 0x3FC0000UL |
#define | _EBI_TFTVPORCH_VBPORCH_DEFAULT 0x00000000UL |
#define | EBI_TFTVPORCH_VBPORCH_DEFAULT (_EBI_TFTVPORCH_VBPORCH_DEFAULT << 18) |
#define | _EBI_TFTTIMING_RESETVALUE 0x00000000UL |
#define | _EBI_TFTTIMING_MASK 0x337FF7FFUL |
#define | _EBI_TFTTIMING_DCLKPERIOD_SHIFT 0 |
#define | _EBI_TFTTIMING_DCLKPERIOD_MASK 0x7FFUL |
#define | _EBI_TFTTIMING_DCLKPERIOD_DEFAULT 0x00000000UL |
#define | EBI_TFTTIMING_DCLKPERIOD_DEFAULT (_EBI_TFTTIMING_DCLKPERIOD_DEFAULT << 0) |
#define | _EBI_TFTTIMING_TFTSTART_SHIFT 12 |
#define | _EBI_TFTTIMING_TFTSTART_MASK 0x7FF000UL |
#define | _EBI_TFTTIMING_TFTSTART_DEFAULT 0x00000000UL |
#define | EBI_TFTTIMING_TFTSTART_DEFAULT (_EBI_TFTTIMING_TFTSTART_DEFAULT << 12) |
#define | _EBI_TFTTIMING_TFTSETUP_SHIFT 24 |
#define | _EBI_TFTTIMING_TFTSETUP_MASK 0x3000000UL |
#define | _EBI_TFTTIMING_TFTSETUP_DEFAULT 0x00000000UL |
#define | EBI_TFTTIMING_TFTSETUP_DEFAULT (_EBI_TFTTIMING_TFTSETUP_DEFAULT << 24) |
#define | _EBI_TFTTIMING_TFTHOLD_SHIFT 28 |
#define | _EBI_TFTTIMING_TFTHOLD_MASK 0x30000000UL |
#define | _EBI_TFTTIMING_TFTHOLD_DEFAULT 0x00000000UL |
#define | EBI_TFTTIMING_TFTHOLD_DEFAULT (_EBI_TFTTIMING_TFTHOLD_DEFAULT << 28) |
#define | _EBI_TFTPOLARITY_RESETVALUE 0x00000000UL |
#define | _EBI_TFTPOLARITY_MASK 0x0000001FUL |
#define | EBI_TFTPOLARITY_CSPOL (0x1UL << 0) |
#define | _EBI_TFTPOLARITY_CSPOL_SHIFT 0 |
#define | _EBI_TFTPOLARITY_CSPOL_MASK 0x1UL |
#define | _EBI_TFTPOLARITY_CSPOL_DEFAULT 0x00000000UL |
#define | _EBI_TFTPOLARITY_CSPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_TFTPOLARITY_CSPOL_DEFAULT (_EBI_TFTPOLARITY_CSPOL_DEFAULT << 0) |
#define | EBI_TFTPOLARITY_CSPOL_ACTIVELOW (_EBI_TFTPOLARITY_CSPOL_ACTIVELOW << 0) |
#define | EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_CSPOL_ACTIVEHIGH << 0) |
#define | EBI_TFTPOLARITY_DCLKPOL (0x1UL << 1) |
#define | _EBI_TFTPOLARITY_DCLKPOL_SHIFT 1 |
#define | _EBI_TFTPOLARITY_DCLKPOL_MASK 0x2UL |
#define | _EBI_TFTPOLARITY_DCLKPOL_DEFAULT 0x00000000UL |
#define | _EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING 0x00000000UL |
#define | _EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING 0x00000001UL |
#define | EBI_TFTPOLARITY_DCLKPOL_DEFAULT (_EBI_TFTPOLARITY_DCLKPOL_DEFAULT << 1) |
#define | EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVEFALLING << 1) |
#define | EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING (_EBI_TFTPOLARITY_DCLKPOL_ACTIVERISING << 1) |
#define | EBI_TFTPOLARITY_DATAENPOL (0x1UL << 2) |
#define | _EBI_TFTPOLARITY_DATAENPOL_SHIFT 2 |
#define | _EBI_TFTPOLARITY_DATAENPOL_MASK 0x4UL |
#define | _EBI_TFTPOLARITY_DATAENPOL_DEFAULT 0x00000000UL |
#define | _EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_TFTPOLARITY_DATAENPOL_DEFAULT (_EBI_TFTPOLARITY_DATAENPOL_DEFAULT << 2) |
#define | EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW (_EBI_TFTPOLARITY_DATAENPOL_ACTIVELOW << 2) |
#define | EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_DATAENPOL_ACTIVEHIGH << 2) |
#define | EBI_TFTPOLARITY_HSYNCPOL (0x1UL << 3) |
#define | _EBI_TFTPOLARITY_HSYNCPOL_SHIFT 3 |
#define | _EBI_TFTPOLARITY_HSYNCPOL_MASK 0x8UL |
#define | _EBI_TFTPOLARITY_HSYNCPOL_DEFAULT 0x00000000UL |
#define | _EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_TFTPOLARITY_HSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_HSYNCPOL_DEFAULT << 3) |
#define | EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVELOW << 3) |
#define | EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_HSYNCPOL_ACTIVEHIGH << 3) |
#define | EBI_TFTPOLARITY_VSYNCPOL (0x1UL << 4) |
#define | _EBI_TFTPOLARITY_VSYNCPOL_SHIFT 4 |
#define | _EBI_TFTPOLARITY_VSYNCPOL_MASK 0x10UL |
#define | _EBI_TFTPOLARITY_VSYNCPOL_DEFAULT 0x00000000UL |
#define | _EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW 0x00000000UL |
#define | _EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH 0x00000001UL |
#define | EBI_TFTPOLARITY_VSYNCPOL_DEFAULT (_EBI_TFTPOLARITY_VSYNCPOL_DEFAULT << 4) |
#define | EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVELOW << 4) |
#define | EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH (_EBI_TFTPOLARITY_VSYNCPOL_ACTIVEHIGH << 4) |
#define | _EBI_TFTDD_RESETVALUE 0x00000000UL |
#define | _EBI_TFTDD_MASK 0x0000FFFFUL |
#define | _EBI_TFTDD_DATA_SHIFT 0 |
#define | _EBI_TFTDD_DATA_MASK 0xFFFFUL |
#define | _EBI_TFTDD_DATA_DEFAULT 0x00000000UL |
#define | EBI_TFTDD_DATA_DEFAULT (_EBI_TFTDD_DATA_DEFAULT << 0) |
#define | _EBI_TFTALPHA_RESETVALUE 0x00000000UL |
#define | _EBI_TFTALPHA_MASK 0x000001FFUL |
#define | _EBI_TFTALPHA_ALPHA_SHIFT 0 |
#define | _EBI_TFTALPHA_ALPHA_MASK 0x1FFUL |
#define | _EBI_TFTALPHA_ALPHA_DEFAULT 0x00000000UL |
#define | EBI_TFTALPHA_ALPHA_DEFAULT (_EBI_TFTALPHA_ALPHA_DEFAULT << 0) |
#define | _EBI_TFTPIXEL0_RESETVALUE 0x00000000UL |
#define | _EBI_TFTPIXEL0_MASK 0x0000FFFFUL |
#define | _EBI_TFTPIXEL0_DATA_SHIFT 0 |
#define | _EBI_TFTPIXEL0_DATA_MASK 0xFFFFUL |
#define | _EBI_TFTPIXEL0_DATA_DEFAULT 0x00000000UL |
#define | EBI_TFTPIXEL0_DATA_DEFAULT (_EBI_TFTPIXEL0_DATA_DEFAULT << 0) |
#define | _EBI_TFTPIXEL1_RESETVALUE 0x00000000UL |
#define | _EBI_TFTPIXEL1_MASK 0x0000FFFFUL |
#define | _EBI_TFTPIXEL1_DATA_SHIFT 0 |
#define | _EBI_TFTPIXEL1_DATA_MASK 0xFFFFUL |
#define | _EBI_TFTPIXEL1_DATA_DEFAULT 0x00000000UL |
#define | EBI_TFTPIXEL1_DATA_DEFAULT (_EBI_TFTPIXEL1_DATA_DEFAULT << 0) |
#define | _EBI_TFTPIXEL_RESETVALUE 0x00000000UL |
#define | _EBI_TFTPIXEL_MASK 0x0000FFFFUL |
#define | _EBI_TFTPIXEL_DATA_SHIFT 0 |
#define | _EBI_TFTPIXEL_DATA_MASK 0xFFFFUL |
#define | _EBI_TFTPIXEL_DATA_DEFAULT 0x00000000UL |
#define | EBI_TFTPIXEL_DATA_DEFAULT (_EBI_TFTPIXEL_DATA_DEFAULT << 0) |
#define | _EBI_TFTMASK_RESETVALUE 0x00000000UL |
#define | _EBI_TFTMASK_MASK 0x0000FFFFUL |
#define | _EBI_TFTMASK_TFTMASK_SHIFT 0 |
#define | _EBI_TFTMASK_TFTMASK_MASK 0xFFFFUL |
#define | _EBI_TFTMASK_TFTMASK_DEFAULT 0x00000000UL |
#define | EBI_TFTMASK_TFTMASK_DEFAULT (_EBI_TFTMASK_TFTMASK_DEFAULT << 0) |
#define | _EBI_IF_RESETVALUE 0x00000000UL |
#define | _EBI_IF_MASK 0x0000003FUL |
#define | EBI_IF_VSYNC (0x1UL << 0) |
#define | _EBI_IF_VSYNC_SHIFT 0 |
#define | _EBI_IF_VSYNC_MASK 0x1UL |
#define | _EBI_IF_VSYNC_DEFAULT 0x00000000UL |
#define | EBI_IF_VSYNC_DEFAULT (_EBI_IF_VSYNC_DEFAULT << 0) |
#define | EBI_IF_HSYNC (0x1UL << 1) |
#define | _EBI_IF_HSYNC_SHIFT 1 |
#define | _EBI_IF_HSYNC_MASK 0x2UL |
#define | _EBI_IF_HSYNC_DEFAULT 0x00000000UL |
#define | EBI_IF_HSYNC_DEFAULT (_EBI_IF_HSYNC_DEFAULT << 1) |
#define | EBI_IF_VBPORCH (0x1UL << 2) |
#define | _EBI_IF_VBPORCH_SHIFT 2 |
#define | _EBI_IF_VBPORCH_MASK 0x4UL |
#define | _EBI_IF_VBPORCH_DEFAULT 0x00000000UL |
#define | EBI_IF_VBPORCH_DEFAULT (_EBI_IF_VBPORCH_DEFAULT << 2) |
#define | EBI_IF_VFPORCH (0x1UL << 3) |
#define | _EBI_IF_VFPORCH_SHIFT 3 |
#define | _EBI_IF_VFPORCH_MASK 0x8UL |
#define | _EBI_IF_VFPORCH_DEFAULT 0x00000000UL |
#define | EBI_IF_VFPORCH_DEFAULT (_EBI_IF_VFPORCH_DEFAULT << 3) |
#define | EBI_IF_DDEMPTY (0x1UL << 4) |
#define | _EBI_IF_DDEMPTY_SHIFT 4 |
#define | _EBI_IF_DDEMPTY_MASK 0x10UL |
#define | _EBI_IF_DDEMPTY_DEFAULT 0x00000000UL |
#define | EBI_IF_DDEMPTY_DEFAULT (_EBI_IF_DDEMPTY_DEFAULT << 4) |
#define | EBI_IF_DDJIT (0x1UL << 5) |
#define | _EBI_IF_DDJIT_SHIFT 5 |
#define | _EBI_IF_DDJIT_MASK 0x20UL |
#define | _EBI_IF_DDJIT_DEFAULT 0x00000000UL |
#define | EBI_IF_DDJIT_DEFAULT (_EBI_IF_DDJIT_DEFAULT << 5) |
#define | _EBI_IFS_RESETVALUE 0x00000000UL |
#define | _EBI_IFS_MASK 0x0000003FUL |
#define | EBI_IFS_VSYNC (0x1UL << 0) |
#define | _EBI_IFS_VSYNC_SHIFT 0 |
#define | _EBI_IFS_VSYNC_MASK 0x1UL |
#define | _EBI_IFS_VSYNC_DEFAULT 0x00000000UL |
#define | EBI_IFS_VSYNC_DEFAULT (_EBI_IFS_VSYNC_DEFAULT << 0) |
#define | EBI_IFS_HSYNC (0x1UL << 1) |
#define | _EBI_IFS_HSYNC_SHIFT 1 |
#define | _EBI_IFS_HSYNC_MASK 0x2UL |
#define | _EBI_IFS_HSYNC_DEFAULT 0x00000000UL |
#define | EBI_IFS_HSYNC_DEFAULT (_EBI_IFS_HSYNC_DEFAULT << 1) |
#define | EBI_IFS_VBPORCH (0x1UL << 2) |
#define | _EBI_IFS_VBPORCH_SHIFT 2 |
#define | _EBI_IFS_VBPORCH_MASK 0x4UL |
#define | _EBI_IFS_VBPORCH_DEFAULT 0x00000000UL |
#define | EBI_IFS_VBPORCH_DEFAULT (_EBI_IFS_VBPORCH_DEFAULT << 2) |
#define | EBI_IFS_VFPORCH (0x1UL << 3) |
#define | _EBI_IFS_VFPORCH_SHIFT 3 |
#define | _EBI_IFS_VFPORCH_MASK 0x8UL |
#define | _EBI_IFS_VFPORCH_DEFAULT 0x00000000UL |
#define | EBI_IFS_VFPORCH_DEFAULT (_EBI_IFS_VFPORCH_DEFAULT << 3) |
#define | EBI_IFS_DDEMPTY (0x1UL << 4) |
#define | _EBI_IFS_DDEMPTY_SHIFT 4 |
#define | _EBI_IFS_DDEMPTY_MASK 0x10UL |
#define | _EBI_IFS_DDEMPTY_DEFAULT 0x00000000UL |
#define | EBI_IFS_DDEMPTY_DEFAULT (_EBI_IFS_DDEMPTY_DEFAULT << 4) |
#define | EBI_IFS_DDJIT (0x1UL << 5) |
#define | _EBI_IFS_DDJIT_SHIFT 5 |
#define | _EBI_IFS_DDJIT_MASK 0x20UL |
#define | _EBI_IFS_DDJIT_DEFAULT 0x00000000UL |
#define | EBI_IFS_DDJIT_DEFAULT (_EBI_IFS_DDJIT_DEFAULT << 5) |
#define | _EBI_IFC_RESETVALUE 0x00000000UL |
#define | _EBI_IFC_MASK 0x0000003FUL |
#define | EBI_IFC_VSYNC (0x1UL << 0) |
#define | _EBI_IFC_VSYNC_SHIFT 0 |
#define | _EBI_IFC_VSYNC_MASK 0x1UL |
#define | _EBI_IFC_VSYNC_DEFAULT 0x00000000UL |
#define | EBI_IFC_VSYNC_DEFAULT (_EBI_IFC_VSYNC_DEFAULT << 0) |
#define | EBI_IFC_HSYNC (0x1UL << 1) |
#define | _EBI_IFC_HSYNC_SHIFT 1 |
#define | _EBI_IFC_HSYNC_MASK 0x2UL |
#define | _EBI_IFC_HSYNC_DEFAULT 0x00000000UL |
#define | EBI_IFC_HSYNC_DEFAULT (_EBI_IFC_HSYNC_DEFAULT << 1) |
#define | EBI_IFC_VBPORCH (0x1UL << 2) |
#define | _EBI_IFC_VBPORCH_SHIFT 2 |
#define | _EBI_IFC_VBPORCH_MASK 0x4UL |
#define | _EBI_IFC_VBPORCH_DEFAULT 0x00000000UL |
#define | EBI_IFC_VBPORCH_DEFAULT (_EBI_IFC_VBPORCH_DEFAULT << 2) |
#define | EBI_IFC_VFPORCH (0x1UL << 3) |
#define | _EBI_IFC_VFPORCH_SHIFT 3 |
#define | _EBI_IFC_VFPORCH_MASK 0x8UL |
#define | _EBI_IFC_VFPORCH_DEFAULT 0x00000000UL |
#define | EBI_IFC_VFPORCH_DEFAULT (_EBI_IFC_VFPORCH_DEFAULT << 3) |
#define | EBI_IFC_DDEMPTY (0x1UL << 4) |
#define | _EBI_IFC_DDEMPTY_SHIFT 4 |
#define | _EBI_IFC_DDEMPTY_MASK 0x10UL |
#define | _EBI_IFC_DDEMPTY_DEFAULT 0x00000000UL |
#define | EBI_IFC_DDEMPTY_DEFAULT (_EBI_IFC_DDEMPTY_DEFAULT << 4) |
#define | EBI_IFC_DDJIT (0x1UL << 5) |
#define | _EBI_IFC_DDJIT_SHIFT 5 |
#define | _EBI_IFC_DDJIT_MASK 0x20UL |
#define | _EBI_IFC_DDJIT_DEFAULT 0x00000000UL |
#define | EBI_IFC_DDJIT_DEFAULT (_EBI_IFC_DDJIT_DEFAULT << 5) |
#define | _EBI_IEN_RESETVALUE 0x00000000UL |
#define | _EBI_IEN_MASK 0x0000003FUL |
#define | EBI_IEN_VSYNC (0x1UL << 0) |
#define | _EBI_IEN_VSYNC_SHIFT 0 |
#define | _EBI_IEN_VSYNC_MASK 0x1UL |
#define | _EBI_IEN_VSYNC_DEFAULT 0x00000000UL |
#define | EBI_IEN_VSYNC_DEFAULT (_EBI_IEN_VSYNC_DEFAULT << 0) |
#define | EBI_IEN_HSYNC (0x1UL << 1) |
#define | _EBI_IEN_HSYNC_SHIFT 1 |
#define | _EBI_IEN_HSYNC_MASK 0x2UL |
#define | _EBI_IEN_HSYNC_DEFAULT 0x00000000UL |
#define | EBI_IEN_HSYNC_DEFAULT (_EBI_IEN_HSYNC_DEFAULT << 1) |
#define | EBI_IEN_VBPORCH (0x1UL << 2) |
#define | _EBI_IEN_VBPORCH_SHIFT 2 |
#define | _EBI_IEN_VBPORCH_MASK 0x4UL |
#define | _EBI_IEN_VBPORCH_DEFAULT 0x00000000UL |
#define | EBI_IEN_VBPORCH_DEFAULT (_EBI_IEN_VBPORCH_DEFAULT << 2) |
#define | EBI_IEN_VFPORCH (0x1UL << 3) |
#define | _EBI_IEN_VFPORCH_SHIFT 3 |
#define | _EBI_IEN_VFPORCH_MASK 0x8UL |
#define | _EBI_IEN_VFPORCH_DEFAULT 0x00000000UL |
#define | EBI_IEN_VFPORCH_DEFAULT (_EBI_IEN_VFPORCH_DEFAULT << 3) |
#define | EBI_IEN_DDEMPTY (0x1UL << 4) |
#define | _EBI_IEN_DDEMPTY_SHIFT 4 |
#define | _EBI_IEN_DDEMPTY_MASK 0x10UL |
#define | _EBI_IEN_DDEMPTY_DEFAULT 0x00000000UL |
#define | EBI_IEN_DDEMPTY_DEFAULT (_EBI_IEN_DDEMPTY_DEFAULT << 4) |
#define | EBI_IEN_DDJIT (0x1UL << 5) |
#define | _EBI_IEN_DDJIT_SHIFT 5 |
#define | _EBI_IEN_DDJIT_MASK 0x20UL |
#define | _EBI_IEN_DDJIT_DEFAULT 0x00000000UL |
#define | EBI_IEN_DDJIT_DEFAULT (_EBI_IEN_DDJIT_DEFAULT << 5) |
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file efm32gg_ebi.h.