00001
00034 #ifndef __EFM32LG990F256_H
00035 #define __EFM32LG990F256_H
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 MemoryManagement_IRQn = -12,
00058 BusFault_IRQn = -11,
00059 UsageFault_IRQn = -10,
00060 SVCall_IRQn = -5,
00061 DebugMonitor_IRQn = -4,
00062 PendSV_IRQn = -2,
00063 SysTick_IRQn = -1,
00065
00066 DMA_IRQn = 0,
00067 GPIO_EVEN_IRQn = 1,
00068 TIMER0_IRQn = 2,
00069 USART0_RX_IRQn = 3,
00070 USART0_TX_IRQn = 4,
00071 USB_IRQn = 5,
00072 ACMP0_IRQn = 6,
00073 ADC0_IRQn = 7,
00074 DAC0_IRQn = 8,
00075 I2C0_IRQn = 9,
00076 I2C1_IRQn = 10,
00077 GPIO_ODD_IRQn = 11,
00078 TIMER1_IRQn = 12,
00079 TIMER2_IRQn = 13,
00080 TIMER3_IRQn = 14,
00081 USART1_RX_IRQn = 15,
00082 USART1_TX_IRQn = 16,
00083 LESENSE_IRQn = 17,
00084 USART2_RX_IRQn = 18,
00085 USART2_TX_IRQn = 19,
00086 UART0_RX_IRQn = 20,
00087 UART0_TX_IRQn = 21,
00088 UART1_RX_IRQn = 22,
00089 UART1_TX_IRQn = 23,
00090 LEUART0_IRQn = 24,
00091 LEUART1_IRQn = 25,
00092 LETIMER0_IRQn = 26,
00093 PCNT0_IRQn = 27,
00094 PCNT1_IRQn = 28,
00095 PCNT2_IRQn = 29,
00096 RTC_IRQn = 30,
00097 BURTC_IRQn = 31,
00098 CMU_IRQn = 32,
00099 VCMP_IRQn = 33,
00100 LCD_IRQn = 34,
00101 MSC_IRQn = 35,
00102 AES_IRQn = 36,
00103 EBI_IRQn = 37,
00104 EMU_IRQn = 38,
00105 } IRQn_Type;
00106
00107
00112 #define __MPU_PRESENT 1
00113 #define __NVIC_PRIO_BITS 3
00114 #define __Vendor_SysTickConfig 0
00118
00124 #define _EFM32_GIANT_FAMILY 1
00125 #define _EFM_DEVICE
00127
00128 #if !defined(EFM32LG990F256)
00129 #define EFM32LG990F256 1
00130 #endif
00131
00133 #define PART_NUMBER "EFM32LG990F256"
00136 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00137 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00138 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00139 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00140 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00141 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00142 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00143 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00144 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
00145 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
00146 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
00147 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
00148 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL)
00149 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL)
00150 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL)
00151 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL)
00152 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00153 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00154 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00155 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00156 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00157 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
00158 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
00159 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
00160 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00161 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
00162 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
00163 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
00164 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
00165 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL)
00166 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL)
00167 #define EBI_MEM_BITS ((uint32_t) 0x30UL)
00170 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
00171 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
00174 #define FLASH_BASE (0x00000000UL)
00175 #define FLASH_SIZE (0x00040000UL)
00176 #define FLASH_PAGE_SIZE 2048
00177 #define SRAM_BASE (0x20000000UL)
00178 #define SRAM_SIZE (0x00008000UL)
00179 #define __CM3_REV 0x201
00180 #define PRS_CHAN_COUNT 12
00181 #define DMA_CHAN_COUNT 12
00184 #define AFCHAN_MAX 163
00185 #define AFCHANLOC_MAX 7
00186
00187 #define AFACHAN_MAX 53
00188
00189
00190
00191 #define USART_PRESENT
00192 #define USART_COUNT 3
00193 #define UART_PRESENT
00194 #define UART_COUNT 2
00195 #define TIMER_PRESENT
00196 #define TIMER_COUNT 4
00197 #define ACMP_PRESENT
00198 #define ACMP_COUNT 2
00199 #define LEUART_PRESENT
00200 #define LEUART_COUNT 2
00201 #define LETIMER_PRESENT
00202 #define LETIMER_COUNT 1
00203 #define PCNT_PRESENT
00204 #define PCNT_COUNT 3
00205 #define I2C_PRESENT
00206 #define I2C_COUNT 2
00207 #define ADC_PRESENT
00208 #define ADC_COUNT 1
00209 #define DAC_PRESENT
00210 #define DAC_COUNT 1
00211 #define DMA_PRESENT
00212 #define DMA_COUNT 1
00213 #define AES_PRESENT
00214 #define AES_COUNT 1
00215 #define USBC_PRESENT
00216 #define USBC_COUNT 1
00217 #define USB_PRESENT
00218 #define USB_COUNT 1
00219 #define LE_PRESENT
00220 #define LE_COUNT 1
00221 #define MSC_PRESENT
00222 #define MSC_COUNT 1
00223 #define EMU_PRESENT
00224 #define EMU_COUNT 1
00225 #define RMU_PRESENT
00226 #define RMU_COUNT 1
00227 #define CMU_PRESENT
00228 #define CMU_COUNT 1
00229 #define LESENSE_PRESENT
00230 #define LESENSE_COUNT 1
00231 #define EBI_PRESENT
00232 #define EBI_COUNT 1
00233 #define RTC_PRESENT
00234 #define RTC_COUNT 1
00235 #define GPIO_PRESENT
00236 #define GPIO_COUNT 1
00237 #define VCMP_PRESENT
00238 #define VCMP_COUNT 1
00239 #define PRS_PRESENT
00240 #define PRS_COUNT 1
00241 #define OPAMP_PRESENT
00242 #define OPAMP_COUNT 1
00243 #define BU_PRESENT
00244 #define BU_COUNT 1
00245 #define LCD_PRESENT
00246 #define LCD_COUNT 1
00247 #define BURTC_PRESENT
00248 #define BURTC_COUNT 1
00249 #define HFXTAL_PRESENT
00250 #define HFXTAL_COUNT 1
00251 #define LFXTAL_PRESENT
00252 #define LFXTAL_COUNT 1
00253 #define WDOG_PRESENT
00254 #define WDOG_COUNT 1
00255 #define DBG_PRESENT
00256 #define DBG_COUNT 1
00257 #define ETM_PRESENT
00258 #define ETM_COUNT 1
00259 #define BOOTLOADER_PRESENT
00260 #define BOOTLOADER_COUNT 1
00261 #define ANALOG_PRESENT
00262 #define ANALOG_COUNT 1
00263
00264 #include "core_cm3.h"
00265 #include "system_efm32lg.h"
00266
00269
00275 #include "efm32lg_dma_ch.h"
00276 #include "efm32lg_dma.h"
00277 #include "efm32lg_aes.h"
00278 #include "efm32lg_usb_hc.h"
00279 #include "efm32lg_usb_diep.h"
00280 #include "efm32lg_usb_doep.h"
00281 #include "efm32lg_usb.h"
00282 #include "efm32lg_msc.h"
00283 #include "efm32lg_emu.h"
00284 #include "efm32lg_rmu.h"
00285
00286
00291 typedef struct
00292 {
00293 __IO uint32_t CTRL;
00294 __IO uint32_t HFCORECLKDIV;
00295 __IO uint32_t HFPERCLKDIV;
00296 __IO uint32_t HFRCOCTRL;
00297 __IO uint32_t LFRCOCTRL;
00298 __IO uint32_t AUXHFRCOCTRL;
00299 __IO uint32_t CALCTRL;
00300 __IO uint32_t CALCNT;
00301 __IO uint32_t OSCENCMD;
00302 __IO uint32_t CMD;
00303 __IO uint32_t LFCLKSEL;
00304 __I uint32_t STATUS;
00305 __I uint32_t IF;
00306 __IO uint32_t IFS;
00307 __IO uint32_t IFC;
00308 __IO uint32_t IEN;
00309 __IO uint32_t HFCORECLKEN0;
00310 __IO uint32_t HFPERCLKEN0;
00311 uint32_t RESERVED0[2];
00312 __I uint32_t SYNCBUSY;
00313 __IO uint32_t FREEZE;
00314 __IO uint32_t LFACLKEN0;
00315 uint32_t RESERVED1[1];
00316 __IO uint32_t LFBCLKEN0;
00317 uint32_t RESERVED2[1];
00318 __IO uint32_t LFAPRESC0;
00319 uint32_t RESERVED3[1];
00320 __IO uint32_t LFBPRESC0;
00321 uint32_t RESERVED4[1];
00322 __IO uint32_t PCNTCTRL;
00323 __IO uint32_t LCDCTRL;
00324 __IO uint32_t ROUTE;
00325 __IO uint32_t LOCK;
00326 } CMU_TypeDef;
00328 #include "efm32lg_lesense_st.h"
00329 #include "efm32lg_lesense_buf.h"
00330 #include "efm32lg_lesense_ch.h"
00331 #include "efm32lg_lesense.h"
00332 #include "efm32lg_ebi.h"
00333 #include "efm32lg_usart.h"
00334 #include "efm32lg_timer_cc.h"
00335 #include "efm32lg_timer.h"
00336 #include "efm32lg_acmp.h"
00337 #include "efm32lg_leuart.h"
00338 #include "efm32lg_rtc.h"
00339 #include "efm32lg_letimer.h"
00340 #include "efm32lg_pcnt.h"
00341 #include "efm32lg_i2c.h"
00342 #include "efm32lg_gpio_p.h"
00343 #include "efm32lg_gpio.h"
00344 #include "efm32lg_vcmp.h"
00345 #include "efm32lg_prs_ch.h"
00346 #include "efm32lg_prs.h"
00347 #include "efm32lg_adc.h"
00348 #include "efm32lg_dac.h"
00349 #include "efm32lg_lcd.h"
00350 #include "efm32lg_burtc_ret.h"
00351 #include "efm32lg_burtc.h"
00352 #include "efm32lg_wdog.h"
00353 #include "efm32lg_etm.h"
00354 #include "efm32lg_dma_descriptor.h"
00355 #include "efm32lg_devinfo.h"
00356 #include "efm32lg_romtable.h"
00357 #include "efm32lg_calibrate.h"
00358
00361
00366 #define DMA_BASE (0x400C2000UL)
00367 #define AES_BASE (0x400E0000UL)
00368 #define USB_BASE (0x400C4000UL)
00369 #define MSC_BASE (0x400C0000UL)
00370 #define EMU_BASE (0x400C6000UL)
00371 #define RMU_BASE (0x400CA000UL)
00372 #define CMU_BASE (0x400C8000UL)
00373 #define LESENSE_BASE (0x4008C000UL)
00374 #define EBI_BASE (0x40008000UL)
00375 #define USART0_BASE (0x4000C000UL)
00376 #define USART1_BASE (0x4000C400UL)
00377 #define USART2_BASE (0x4000C800UL)
00378 #define UART0_BASE (0x4000E000UL)
00379 #define UART1_BASE (0x4000E400UL)
00380 #define TIMER0_BASE (0x40010000UL)
00381 #define TIMER1_BASE (0x40010400UL)
00382 #define TIMER2_BASE (0x40010800UL)
00383 #define TIMER3_BASE (0x40010C00UL)
00384 #define ACMP0_BASE (0x40001000UL)
00385 #define ACMP1_BASE (0x40001400UL)
00386 #define LEUART0_BASE (0x40084000UL)
00387 #define LEUART1_BASE (0x40084400UL)
00388 #define RTC_BASE (0x40080000UL)
00389 #define LETIMER0_BASE (0x40082000UL)
00390 #define PCNT0_BASE (0x40086000UL)
00391 #define PCNT1_BASE (0x40086400UL)
00392 #define PCNT2_BASE (0x40086800UL)
00393 #define I2C0_BASE (0x4000A000UL)
00394 #define I2C1_BASE (0x4000A400UL)
00395 #define GPIO_BASE (0x40006000UL)
00396 #define VCMP_BASE (0x40000000UL)
00397 #define PRS_BASE (0x400CC000UL)
00398 #define ADC0_BASE (0x40002000UL)
00399 #define DAC0_BASE (0x40004000UL)
00400 #define LCD_BASE (0x4008A000UL)
00401 #define BURTC_BASE (0x40081000UL)
00402 #define WDOG_BASE (0x40088000UL)
00403 #define ETM_BASE (0xE0041000UL)
00404 #define CALIBRATE_BASE (0x0FE08000UL)
00405 #define DEVINFO_BASE (0x0FE081B0UL)
00406 #define ROMTABLE_BASE (0xE00FFFD0UL)
00407 #define LOCKBITS_BASE (0x0FE04000UL)
00408 #define USERDATA_BASE (0x0FE00000UL)
00412
00417 #define DMA ((DMA_TypeDef *) DMA_BASE)
00418 #define AES ((AES_TypeDef *) AES_BASE)
00419 #define USB ((USB_TypeDef *) USB_BASE)
00420 #define MSC ((MSC_TypeDef *) MSC_BASE)
00421 #define EMU ((EMU_TypeDef *) EMU_BASE)
00422 #define RMU ((RMU_TypeDef *) RMU_BASE)
00423 #define CMU ((CMU_TypeDef *) CMU_BASE)
00424 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE)
00425 #define EBI ((EBI_TypeDef *) EBI_BASE)
00426 #define USART0 ((USART_TypeDef *) USART0_BASE)
00427 #define USART1 ((USART_TypeDef *) USART1_BASE)
00428 #define USART2 ((USART_TypeDef *) USART2_BASE)
00429 #define UART0 ((USART_TypeDef *) UART0_BASE)
00430 #define UART1 ((USART_TypeDef *) UART1_BASE)
00431 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00432 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00433 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
00434 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE)
00435 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00436 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
00437 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00438 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
00439 #define RTC ((RTC_TypeDef *) RTC_BASE)
00440 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
00441 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00442 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
00443 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
00444 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00445 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
00446 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00447 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00448 #define PRS ((PRS_TypeDef *) PRS_BASE)
00449 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00450 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
00451 #define LCD ((LCD_TypeDef *) LCD_BASE)
00452 #define BURTC ((BURTC_TypeDef *) BURTC_BASE)
00453 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00454 #define ETM ((ETM_TypeDef *) ETM_BASE)
00455 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00456 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00457 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00461
00466 #include "efm32lg_prs_signals.h"
00467 #include "efm32lg_dmareq.h"
00468 #include "efm32lg_dmactrl.h"
00469 #include "efm32lg_uart.h"
00470
00471
00476
00477 #define _CMU_CTRL_RESETVALUE 0x000C062CUL
00478 #define _CMU_CTRL_MASK 0x53FFFEEFUL
00479 #define _CMU_CTRL_HFXOMODE_SHIFT 0
00480 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
00481 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
00482 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
00483 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
00484 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
00485 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
00486 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
00487 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
00488 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
00489 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
00490 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
00491 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
00492 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
00493 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
00494 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
00495 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
00496 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
00497 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
00498 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
00499 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
00500 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
00501 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
00502 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
00503 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
00504 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL
00505 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL
00506 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
00507 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5)
00508 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5)
00509 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
00510 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
00511 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
00512 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
00513 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
00514 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
00515 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
00516 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
00517 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
00518 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
00519 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
00520 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
00521 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
00522 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
00523 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
00524 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
00525 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
00526 #define _CMU_CTRL_LFXOMODE_SHIFT 11
00527 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
00528 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
00529 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
00530 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
00531 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
00532 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
00533 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
00534 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
00535 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
00536 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
00537 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
00538 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
00539 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
00540 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
00541 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
00542 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
00543 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
00544 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
00545 #define _CMU_CTRL_HFCLKDIV_SHIFT 14
00546 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL
00547 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL
00548 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)
00549 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
00550 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
00551 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
00552 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
00553 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
00554 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
00555 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
00556 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
00557 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
00558 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
00559 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
00560 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
00561 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
00562 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
00563 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
00564 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
00565 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
00566 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
00567 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
00568 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
00569 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
00570 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
00571 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
00572 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
00573 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
00574 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
00575 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
00576 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL
00577 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
00578 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
00579 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
00580 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
00581 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
00582 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
00583 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
00584 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
00585 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
00586 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
00587 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x3800000UL
00588 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
00589 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
00590 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
00591 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL
00592 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL
00593 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL
00594 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL
00595 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL
00596 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL
00597 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
00598 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
00599 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
00600 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
00601 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
00602 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
00603 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
00604 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
00605 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
00606 #define CMU_CTRL_DBGCLK (0x1UL << 28)
00607 #define _CMU_CTRL_DBGCLK_SHIFT 28
00608 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL
00609 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL
00610 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL
00611 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL
00612 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28)
00613 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)
00614 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28)
00615 #define CMU_CTRL_HFLE (0x1UL << 30)
00616 #define _CMU_CTRL_HFLE_SHIFT 30
00617 #define _CMU_CTRL_HFLE_MASK 0x40000000UL
00618 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL
00619 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30)
00621
00622 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
00623 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL
00624 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
00625 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
00626 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
00627 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
00628 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
00629 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
00630 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
00631 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
00632 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
00633 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
00634 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
00635 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
00636 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
00637 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
00638 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
00639 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
00640 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
00641 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
00642 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
00643 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
00644 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
00645 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
00646 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
00647 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
00648 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8)
00649 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8
00650 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL
00651 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL
00652 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL
00653 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL
00654 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)
00655 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)
00656 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)
00658
00659 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
00660 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
00661 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
00662 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
00663 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
00664 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
00665 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
00666 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
00667 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
00668 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
00669 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
00670 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
00671 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
00672 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
00673 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
00674 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
00675 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
00676 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
00677 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
00678 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
00679 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
00680 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
00681 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
00682 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
00683 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
00684 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
00685 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
00686 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
00687 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
00688 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
00689 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
00691
00692 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
00693 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
00694 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
00695 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
00696 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00697 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
00698 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
00699 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
00700 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
00701 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
00702 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
00703 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
00704 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
00705 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
00706 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
00707 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
00708 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
00709 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
00710 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
00711 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
00712 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
00713 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
00714 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
00715 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
00716 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
00717 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
00719
00720 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
00721 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
00722 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
00723 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
00724 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
00725 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
00727
00728 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
00729 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL
00730 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
00731 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
00732 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00733 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
00734 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8
00735 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL
00736 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL
00737 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL
00738 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL
00739 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL
00740 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL
00741 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL
00742 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL
00743 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
00744 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
00745 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
00746 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
00747 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
00748 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)
00749 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
00751
00752 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
00753 #define _CMU_CALCTRL_MASK 0x0000007FUL
00754 #define _CMU_CALCTRL_UPSEL_SHIFT 0
00755 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
00756 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
00757 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
00758 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
00759 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
00760 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
00761 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
00762 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
00763 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
00764 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
00765 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
00766 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
00767 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
00768 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3
00769 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL
00770 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
00771 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
00772 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
00773 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
00774 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
00775 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
00776 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
00777 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
00778 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
00779 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
00780 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
00781 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
00782 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
00783 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
00784 #define CMU_CALCTRL_CONT (0x1UL << 6)
00785 #define _CMU_CALCTRL_CONT_SHIFT 6
00786 #define _CMU_CALCTRL_CONT_MASK 0x40UL
00787 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
00788 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)
00790
00791 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
00792 #define _CMU_CALCNT_MASK 0x000FFFFFUL
00793 #define _CMU_CALCNT_CALCNT_SHIFT 0
00794 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
00795 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
00796 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
00798
00799 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
00800 #define _CMU_OSCENCMD_MASK 0x000003FFUL
00801 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
00802 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
00803 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
00804 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
00805 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
00806 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
00807 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
00808 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
00809 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
00810 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
00811 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
00812 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
00813 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
00814 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
00815 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
00816 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
00817 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
00818 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
00819 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
00820 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
00821 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
00822 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
00823 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
00824 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
00825 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
00826 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
00827 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
00828 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
00829 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
00830 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
00831 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
00832 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
00833 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
00834 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
00835 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
00836 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
00837 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
00838 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
00839 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
00840 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
00841 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
00842 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
00843 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
00844 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
00845 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
00846 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
00847 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
00848 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
00849 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
00850 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
00852
00853 #define _CMU_CMD_RESETVALUE 0x00000000UL
00854 #define _CMU_CMD_MASK 0x0000007FUL
00855 #define _CMU_CMD_HFCLKSEL_SHIFT 0
00856 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
00857 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
00858 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
00859 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
00860 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
00861 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
00862 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
00863 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
00864 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
00865 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
00866 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
00867 #define CMU_CMD_CALSTART (0x1UL << 3)
00868 #define _CMU_CMD_CALSTART_SHIFT 3
00869 #define _CMU_CMD_CALSTART_MASK 0x8UL
00870 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
00871 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
00872 #define CMU_CMD_CALSTOP (0x1UL << 4)
00873 #define _CMU_CMD_CALSTOP_SHIFT 4
00874 #define _CMU_CMD_CALSTOP_MASK 0x10UL
00875 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
00876 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)
00877 #define _CMU_CMD_USBCCLKSEL_SHIFT 5
00878 #define _CMU_CMD_USBCCLKSEL_MASK 0x60UL
00879 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL
00880 #define _CMU_CMD_USBCCLKSEL_HFCLKNODIV 0x00000001UL
00881 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL
00882 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL
00883 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)
00884 #define CMU_CMD_USBCCLKSEL_HFCLKNODIV (_CMU_CMD_USBCCLKSEL_HFCLKNODIV << 5)
00885 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5)
00886 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5)
00888
00889 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
00890 #define _CMU_LFCLKSEL_MASK 0x0011000FUL
00891 #define _CMU_LFCLKSEL_LFA_SHIFT 0
00892 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
00893 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
00894 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
00895 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
00896 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
00897 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
00898 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
00899 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
00900 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
00901 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
00902 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
00903 #define _CMU_LFCLKSEL_LFB_SHIFT 2
00904 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
00905 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
00906 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
00907 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
00908 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
00909 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
00910 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
00911 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
00912 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
00913 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
00914 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
00915 #define CMU_LFCLKSEL_LFAE (0x1UL << 16)
00916 #define _CMU_LFCLKSEL_LFAE_SHIFT 16
00917 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL
00918 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL
00919 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL
00920 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL
00921 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
00922 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
00923 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
00924 #define CMU_LFCLKSEL_LFBE (0x1UL << 20)
00925 #define _CMU_LFCLKSEL_LFBE_SHIFT 20
00926 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL
00927 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL
00928 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL
00929 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL
00930 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
00931 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
00932 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
00934
00935 #define _CMU_STATUS_RESETVALUE 0x00000403UL
00936 #define _CMU_STATUS_MASK 0x0003FFFFUL
00937 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
00938 #define _CMU_STATUS_HFRCOENS_SHIFT 0
00939 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
00940 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
00941 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
00942 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
00943 #define _CMU_STATUS_HFRCORDY_SHIFT 1
00944 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
00945 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
00946 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
00947 #define CMU_STATUS_HFXOENS (0x1UL << 2)
00948 #define _CMU_STATUS_HFXOENS_SHIFT 2
00949 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
00950 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
00951 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
00952 #define CMU_STATUS_HFXORDY (0x1UL << 3)
00953 #define _CMU_STATUS_HFXORDY_SHIFT 3
00954 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
00955 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
00956 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
00957 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
00958 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
00959 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
00960 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
00961 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
00962 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
00963 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
00964 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
00965 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
00966 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
00967 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
00968 #define _CMU_STATUS_LFRCOENS_SHIFT 6
00969 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
00970 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
00971 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
00972 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
00973 #define _CMU_STATUS_LFRCORDY_SHIFT 7
00974 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
00975 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
00976 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
00977 #define CMU_STATUS_LFXOENS (0x1UL << 8)
00978 #define _CMU_STATUS_LFXOENS_SHIFT 8
00979 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
00980 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
00981 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
00982 #define CMU_STATUS_LFXORDY (0x1UL << 9)
00983 #define _CMU_STATUS_LFXORDY_SHIFT 9
00984 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
00985 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
00986 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
00987 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
00988 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
00989 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
00990 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
00991 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
00992 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
00993 #define _CMU_STATUS_HFXOSEL_SHIFT 11
00994 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
00995 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
00996 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
00997 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
00998 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
00999 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
01000 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
01001 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
01002 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
01003 #define _CMU_STATUS_LFXOSEL_SHIFT 13
01004 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
01005 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
01006 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
01007 #define CMU_STATUS_CALBSY (0x1UL << 14)
01008 #define _CMU_STATUS_CALBSY_SHIFT 14
01009 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
01010 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
01011 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
01012 #define CMU_STATUS_USBCHFCLKSEL (0x1UL << 15)
01013 #define _CMU_STATUS_USBCHFCLKSEL_SHIFT 15
01014 #define _CMU_STATUS_USBCHFCLKSEL_MASK 0x8000UL
01015 #define _CMU_STATUS_USBCHFCLKSEL_DEFAULT 0x00000000UL
01016 #define CMU_STATUS_USBCHFCLKSEL_DEFAULT (_CMU_STATUS_USBCHFCLKSEL_DEFAULT << 15)
01017 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16)
01018 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16
01019 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL
01020 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL
01021 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)
01022 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17)
01023 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17
01024 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL
01025 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL
01026 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)
01028
01029 #define _CMU_IF_RESETVALUE 0x00000001UL
01030 #define _CMU_IF_MASK 0x000000FFUL
01031 #define CMU_IF_HFRCORDY (0x1UL << 0)
01032 #define _CMU_IF_HFRCORDY_SHIFT 0
01033 #define _CMU_IF_HFRCORDY_MASK 0x1UL
01034 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
01035 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
01036 #define CMU_IF_HFXORDY (0x1UL << 1)
01037 #define _CMU_IF_HFXORDY_SHIFT 1
01038 #define _CMU_IF_HFXORDY_MASK 0x2UL
01039 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
01040 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
01041 #define CMU_IF_LFRCORDY (0x1UL << 2)
01042 #define _CMU_IF_LFRCORDY_SHIFT 2
01043 #define _CMU_IF_LFRCORDY_MASK 0x4UL
01044 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
01045 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
01046 #define CMU_IF_LFXORDY (0x1UL << 3)
01047 #define _CMU_IF_LFXORDY_SHIFT 3
01048 #define _CMU_IF_LFXORDY_MASK 0x8UL
01049 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
01050 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
01051 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
01052 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
01053 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
01054 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
01055 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
01056 #define CMU_IF_CALRDY (0x1UL << 5)
01057 #define _CMU_IF_CALRDY_SHIFT 5
01058 #define _CMU_IF_CALRDY_MASK 0x20UL
01059 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
01060 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
01061 #define CMU_IF_CALOF (0x1UL << 6)
01062 #define _CMU_IF_CALOF_SHIFT 6
01063 #define _CMU_IF_CALOF_MASK 0x40UL
01064 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
01065 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
01066 #define CMU_IF_USBCHFCLKSEL (0x1UL << 7)
01067 #define _CMU_IF_USBCHFCLKSEL_SHIFT 7
01068 #define _CMU_IF_USBCHFCLKSEL_MASK 0x80UL
01069 #define _CMU_IF_USBCHFCLKSEL_DEFAULT 0x00000000UL
01070 #define CMU_IF_USBCHFCLKSEL_DEFAULT (_CMU_IF_USBCHFCLKSEL_DEFAULT << 7)
01072
01073 #define _CMU_IFS_RESETVALUE 0x00000000UL
01074 #define _CMU_IFS_MASK 0x000000FFUL
01075 #define CMU_IFS_HFRCORDY (0x1UL << 0)
01076 #define _CMU_IFS_HFRCORDY_SHIFT 0
01077 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
01078 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
01079 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
01080 #define CMU_IFS_HFXORDY (0x1UL << 1)
01081 #define _CMU_IFS_HFXORDY_SHIFT 1
01082 #define _CMU_IFS_HFXORDY_MASK 0x2UL
01083 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
01084 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
01085 #define CMU_IFS_LFRCORDY (0x1UL << 2)
01086 #define _CMU_IFS_LFRCORDY_SHIFT 2
01087 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
01088 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
01089 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
01090 #define CMU_IFS_LFXORDY (0x1UL << 3)
01091 #define _CMU_IFS_LFXORDY_SHIFT 3
01092 #define _CMU_IFS_LFXORDY_MASK 0x8UL
01093 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
01094 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
01095 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
01096 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
01097 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
01098 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
01099 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
01100 #define CMU_IFS_CALRDY (0x1UL << 5)
01101 #define _CMU_IFS_CALRDY_SHIFT 5
01102 #define _CMU_IFS_CALRDY_MASK 0x20UL
01103 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
01104 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
01105 #define CMU_IFS_CALOF (0x1UL << 6)
01106 #define _CMU_IFS_CALOF_SHIFT 6
01107 #define _CMU_IFS_CALOF_MASK 0x40UL
01108 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
01109 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
01110 #define CMU_IFS_USBCHFCLKSEL (0x1UL << 7)
01111 #define _CMU_IFS_USBCHFCLKSEL_SHIFT 7
01112 #define _CMU_IFS_USBCHFCLKSEL_MASK 0x80UL
01113 #define _CMU_IFS_USBCHFCLKSEL_DEFAULT 0x00000000UL
01114 #define CMU_IFS_USBCHFCLKSEL_DEFAULT (_CMU_IFS_USBCHFCLKSEL_DEFAULT << 7)
01116
01117 #define _CMU_IFC_RESETVALUE 0x00000000UL
01118 #define _CMU_IFC_MASK 0x000000FFUL
01119 #define CMU_IFC_HFRCORDY (0x1UL << 0)
01120 #define _CMU_IFC_HFRCORDY_SHIFT 0
01121 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
01122 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
01123 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
01124 #define CMU_IFC_HFXORDY (0x1UL << 1)
01125 #define _CMU_IFC_HFXORDY_SHIFT 1
01126 #define _CMU_IFC_HFXORDY_MASK 0x2UL
01127 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
01128 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
01129 #define CMU_IFC_LFRCORDY (0x1UL << 2)
01130 #define _CMU_IFC_LFRCORDY_SHIFT 2
01131 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
01132 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
01133 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
01134 #define CMU_IFC_LFXORDY (0x1UL << 3)
01135 #define _CMU_IFC_LFXORDY_SHIFT 3
01136 #define _CMU_IFC_LFXORDY_MASK 0x8UL
01137 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
01138 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
01139 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
01140 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
01141 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
01142 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
01143 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
01144 #define CMU_IFC_CALRDY (0x1UL << 5)
01145 #define _CMU_IFC_CALRDY_SHIFT 5
01146 #define _CMU_IFC_CALRDY_MASK 0x20UL
01147 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
01148 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
01149 #define CMU_IFC_CALOF (0x1UL << 6)
01150 #define _CMU_IFC_CALOF_SHIFT 6
01151 #define _CMU_IFC_CALOF_MASK 0x40UL
01152 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
01153 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
01154 #define CMU_IFC_USBCHFCLKSEL (0x1UL << 7)
01155 #define _CMU_IFC_USBCHFCLKSEL_SHIFT 7
01156 #define _CMU_IFC_USBCHFCLKSEL_MASK 0x80UL
01157 #define _CMU_IFC_USBCHFCLKSEL_DEFAULT 0x00000000UL
01158 #define CMU_IFC_USBCHFCLKSEL_DEFAULT (_CMU_IFC_USBCHFCLKSEL_DEFAULT << 7)
01160
01161 #define _CMU_IEN_RESETVALUE 0x00000000UL
01162 #define _CMU_IEN_MASK 0x000000FFUL
01163 #define CMU_IEN_HFRCORDY (0x1UL << 0)
01164 #define _CMU_IEN_HFRCORDY_SHIFT 0
01165 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
01166 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
01167 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
01168 #define CMU_IEN_HFXORDY (0x1UL << 1)
01169 #define _CMU_IEN_HFXORDY_SHIFT 1
01170 #define _CMU_IEN_HFXORDY_MASK 0x2UL
01171 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
01172 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
01173 #define CMU_IEN_LFRCORDY (0x1UL << 2)
01174 #define _CMU_IEN_LFRCORDY_SHIFT 2
01175 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
01176 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
01177 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
01178 #define CMU_IEN_LFXORDY (0x1UL << 3)
01179 #define _CMU_IEN_LFXORDY_SHIFT 3
01180 #define _CMU_IEN_LFXORDY_MASK 0x8UL
01181 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
01182 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
01183 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
01184 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
01185 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
01186 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
01187 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
01188 #define CMU_IEN_CALRDY (0x1UL << 5)
01189 #define _CMU_IEN_CALRDY_SHIFT 5
01190 #define _CMU_IEN_CALRDY_MASK 0x20UL
01191 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
01192 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
01193 #define CMU_IEN_CALOF (0x1UL << 6)
01194 #define _CMU_IEN_CALOF_SHIFT 6
01195 #define _CMU_IEN_CALOF_MASK 0x40UL
01196 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
01197 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
01198 #define CMU_IEN_USBCHFCLKSEL (0x1UL << 7)
01199 #define _CMU_IEN_USBCHFCLKSEL_SHIFT 7
01200 #define _CMU_IEN_USBCHFCLKSEL_MASK 0x80UL
01201 #define _CMU_IEN_USBCHFCLKSEL_DEFAULT 0x00000000UL
01202 #define CMU_IEN_USBCHFCLKSEL_DEFAULT (_CMU_IEN_USBCHFCLKSEL_DEFAULT << 7)
01204
01205 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
01206 #define _CMU_HFCORECLKEN0_MASK 0x0000003FUL
01207 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0)
01208 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0
01209 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL
01210 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
01211 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0)
01212 #define CMU_HFCORECLKEN0_AES (0x1UL << 1)
01213 #define _CMU_HFCORECLKEN0_AES_SHIFT 1
01214 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL
01215 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
01216 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1)
01217 #define CMU_HFCORECLKEN0_USBC (0x1UL << 2)
01218 #define _CMU_HFCORECLKEN0_USBC_SHIFT 2
01219 #define _CMU_HFCORECLKEN0_USBC_MASK 0x4UL
01220 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL
01221 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 2)
01222 #define CMU_HFCORECLKEN0_USB (0x1UL << 3)
01223 #define _CMU_HFCORECLKEN0_USB_SHIFT 3
01224 #define _CMU_HFCORECLKEN0_USB_MASK 0x8UL
01225 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL
01226 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 3)
01227 #define CMU_HFCORECLKEN0_LE (0x1UL << 4)
01228 #define _CMU_HFCORECLKEN0_LE_SHIFT 4
01229 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL
01230 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
01231 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4)
01232 #define CMU_HFCORECLKEN0_EBI (0x1UL << 5)
01233 #define _CMU_HFCORECLKEN0_EBI_SHIFT 5
01234 #define _CMU_HFCORECLKEN0_EBI_MASK 0x20UL
01235 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL
01236 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 5)
01238
01239 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
01240 #define _CMU_HFPERCLKEN0_MASK 0x0003FFFFUL
01241 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0)
01242 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0
01243 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL
01244 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
01245 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
01246 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1)
01247 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1
01248 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL
01249 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
01250 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
01251 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2)
01252 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2
01253 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL
01254 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL
01255 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
01256 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3)
01257 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3
01258 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL
01259 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL
01260 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)
01261 #define CMU_HFPERCLKEN0_UART1 (0x1UL << 4)
01262 #define _CMU_HFPERCLKEN0_UART1_SHIFT 4
01263 #define _CMU_HFPERCLKEN0_UART1_MASK 0x10UL
01264 #define _CMU_HFPERCLKEN0_UART1_DEFAULT 0x00000000UL
01265 #define CMU_HFPERCLKEN0_UART1_DEFAULT (_CMU_HFPERCLKEN0_UART1_DEFAULT << 4)
01266 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5)
01267 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5
01268 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL
01269 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
01270 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5)
01271 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6)
01272 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6
01273 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL
01274 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
01275 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6)
01276 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7)
01277 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7
01278 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL
01279 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
01280 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7)
01281 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8)
01282 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8
01283 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL
01284 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL
01285 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8)
01286 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9)
01287 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9
01288 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL
01289 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
01290 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9)
01291 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10)
01292 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10
01293 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL
01294 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
01295 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10)
01296 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)
01297 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11
01298 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL
01299 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
01300 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
01301 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12)
01302 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12
01303 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL
01304 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL
01305 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12)
01306 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13)
01307 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13
01308 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL
01309 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
01310 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13)
01311 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14)
01312 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14
01313 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL
01314 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
01315 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14)
01316 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15)
01317 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15
01318 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL
01319 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
01320 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15)
01321 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16)
01322 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16
01323 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL
01324 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
01325 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16)
01326 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17)
01327 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17
01328 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL
01329 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
01330 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17)
01332
01333 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
01334 #define _CMU_SYNCBUSY_MASK 0x00000055UL
01335 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
01336 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
01337 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
01338 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
01339 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
01340 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
01341 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
01342 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
01343 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
01344 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
01345 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
01346 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
01347 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
01348 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
01349 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
01350 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
01351 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
01352 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
01353 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
01354 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
01356
01357 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
01358 #define _CMU_FREEZE_MASK 0x00000001UL
01359 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
01360 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
01361 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
01362 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
01363 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
01364 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
01365 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
01366 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
01367 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
01369
01370 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
01371 #define _CMU_LFACLKEN0_MASK 0x0000000FUL
01372 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0)
01373 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0
01374 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL
01375 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL
01376 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)
01377 #define CMU_LFACLKEN0_RTC (0x1UL << 1)
01378 #define _CMU_LFACLKEN0_RTC_SHIFT 1
01379 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL
01380 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
01381 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1)
01382 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2)
01383 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2
01384 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL
01385 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
01386 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)
01387 #define CMU_LFACLKEN0_LCD (0x1UL << 3)
01388 #define _CMU_LFACLKEN0_LCD_SHIFT 3
01389 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL
01390 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL
01391 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3)
01393
01394 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
01395 #define _CMU_LFBCLKEN0_MASK 0x00000003UL
01396 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
01397 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
01398 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
01399 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
01400 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
01401 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1)
01402 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1
01403 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL
01404 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL
01405 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)
01407
01408 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
01409 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL
01410 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0
01411 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL
01412 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL
01413 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL
01414 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL
01415 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL
01416 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)
01417 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)
01418 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)
01419 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)
01420 #define _CMU_LFAPRESC0_RTC_SHIFT 4
01421 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL
01422 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
01423 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
01424 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
01425 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
01426 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
01427 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
01428 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
01429 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
01430 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
01431 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
01432 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
01433 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
01434 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
01435 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
01436 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
01437 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
01438 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4)
01439 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4)
01440 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4)
01441 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4)
01442 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4)
01443 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4)
01444 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4)
01445 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4)
01446 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4)
01447 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4)
01448 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4)
01449 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4)
01450 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4)
01451 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4)
01452 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4)
01453 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4)
01454 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8
01455 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL
01456 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
01457 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
01458 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
01459 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
01460 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
01461 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
01462 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
01463 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
01464 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
01465 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
01466 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
01467 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
01468 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
01469 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
01470 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
01471 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
01472 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)
01473 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)
01474 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)
01475 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)
01476 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)
01477 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)
01478 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)
01479 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)
01480 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)
01481 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)
01482 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)
01483 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)
01484 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)
01485 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)
01486 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)
01487 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)
01488 #define _CMU_LFAPRESC0_LCD_SHIFT 12
01489 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL
01490 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL
01491 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL
01492 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL
01493 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL
01494 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12)
01495 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12)
01496 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12)
01497 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12)
01499
01500 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
01501 #define _CMU_LFBPRESC0_MASK 0x00000033UL
01502 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
01503 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
01504 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
01505 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
01506 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
01507 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
01508 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
01509 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
01510 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
01511 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
01512 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4
01513 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL
01514 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL
01515 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL
01516 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL
01517 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL
01518 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)
01519 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)
01520 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)
01521 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)
01523
01524 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
01525 #define _CMU_PCNTCTRL_MASK 0x0000003FUL
01526 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
01527 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
01528 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
01529 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
01530 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
01531 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
01532 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
01533 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
01534 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
01535 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
01536 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
01537 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
01538 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
01539 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
01540 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2)
01541 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2
01542 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL
01543 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL
01544 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)
01545 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3)
01546 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3
01547 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL
01548 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL
01549 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL
01550 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL
01551 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)
01552 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)
01553 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)
01554 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4)
01555 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4
01556 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL
01557 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL
01558 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)
01559 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5)
01560 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5
01561 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL
01562 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL
01563 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL
01564 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL
01565 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)
01566 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)
01567 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)
01569
01570 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL
01571 #define _CMU_LCDCTRL_MASK 0x0000007FUL
01572 #define _CMU_LCDCTRL_FDIV_SHIFT 0
01573 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL
01574 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL
01575 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0)
01576 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3)
01577 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3
01578 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL
01579 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL
01580 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3)
01581 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4
01582 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL
01583 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL
01584 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL
01585 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL
01586 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL
01587 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL
01588 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL
01589 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL
01590 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL
01591 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL
01592 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)
01593 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)
01594 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)
01595 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)
01596 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)
01597 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)
01598 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)
01599 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)
01600 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)
01602
01603 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
01604 #define _CMU_ROUTE_MASK 0x0000001FUL
01605 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
01606 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
01607 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
01608 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
01609 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
01610 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
01611 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
01612 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
01613 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
01614 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
01615 #define _CMU_ROUTE_LOCATION_SHIFT 2
01616 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL
01617 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
01618 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
01619 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
01620 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL
01621 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
01622 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
01623 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
01624 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)
01626
01627 #define _CMU_LOCK_RESETVALUE 0x00000000UL
01628 #define _CMU_LOCK_MASK 0x0000FFFFUL
01629 #define _CMU_LOCK_LOCKKEY_SHIFT 0
01630 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
01631 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
01632 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
01633 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
01634 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
01635 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
01636 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
01637 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
01638 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
01639 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
01640 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
01646
01650 #define MSC_UNLOCK_CODE 0x1B71
01651 #define EMU_UNLOCK_CODE 0xADE8
01652 #define CMU_UNLOCK_CODE 0x580E
01653 #define TIMER_UNLOCK_CODE 0xCE80
01654 #define GPIO_UNLOCK_CODE 0xA534
01655 #define BURTC_UNLOCK_CODE 0xAEE8
01661
01666 #include "efm32lg_af_ports.h"
01667 #include "efm32lg_af_pins.h"
01668
01671
01684 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
01685 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
01686
01691 #ifdef __cplusplus
01692 }
01693 #endif
01694 #endif