EFM32 Giant Gecko Software Documentation  efm32gg-doc-4.2.1
efm32gg_emu.h
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1 /**************************************************************************/
32 /**************************************************************************/
36 /**************************************************************************/
41 typedef struct
42 {
43  __IO uint32_t CTRL;
44  __IO uint32_t MEMCTRL;
45  __IO uint32_t LOCK;
47  uint32_t RESERVED0[6];
48  __IO uint32_t AUXCTRL;
50  uint32_t RESERVED1[1];
51  __IO uint32_t EM4CONF;
52  __IO uint32_t BUCTRL;
53  __IO uint32_t PWRCONF;
54  __IO uint32_t BUINACT;
55  __IO uint32_t BUACT;
56  __I uint32_t STATUS;
57  __IO uint32_t ROUTE;
58  __I uint32_t IF;
59  __IO uint32_t IFS;
60  __IO uint32_t IFC;
61  __IO uint32_t IEN;
62  __IO uint32_t BUBODBUVINCAL;
63  __IO uint32_t BUBODUNREGCAL;
64 } EMU_TypeDef;
66 /**************************************************************************/
71 /* Bit fields for EMU CTRL */
72 #define _EMU_CTRL_RESETVALUE 0x00000000UL
73 #define _EMU_CTRL_MASK 0x0000000FUL
74 #define EMU_CTRL_EMVREG (0x1UL << 0)
75 #define _EMU_CTRL_EMVREG_SHIFT 0
76 #define _EMU_CTRL_EMVREG_MASK 0x1UL
77 #define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL
78 #define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL
79 #define _EMU_CTRL_EMVREG_FULL 0x00000001UL
80 #define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0)
81 #define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0)
82 #define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0)
83 #define EMU_CTRL_EM2BLOCK (0x1UL << 1)
84 #define _EMU_CTRL_EM2BLOCK_SHIFT 1
85 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL
86 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL
87 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1)
88 #define _EMU_CTRL_EM4CTRL_SHIFT 2
89 #define _EMU_CTRL_EM4CTRL_MASK 0xCUL
90 #define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL
91 #define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2)
93 /* Bit fields for EMU MEMCTRL */
94 #define _EMU_MEMCTRL_RESETVALUE 0x00000000UL
95 #define _EMU_MEMCTRL_MASK 0x00000007UL
96 #define _EMU_MEMCTRL_POWERDOWN_SHIFT 0
97 #define _EMU_MEMCTRL_POWERDOWN_MASK 0x7UL
98 #define _EMU_MEMCTRL_POWERDOWN_DEFAULT 0x00000000UL
99 #define _EMU_MEMCTRL_POWERDOWN_BLK3 0x00000004UL
100 #define _EMU_MEMCTRL_POWERDOWN_BLK23 0x00000006UL
101 #define _EMU_MEMCTRL_POWERDOWN_BLK123 0x00000007UL
102 #define EMU_MEMCTRL_POWERDOWN_DEFAULT (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0)
103 #define EMU_MEMCTRL_POWERDOWN_BLK3 (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0)
104 #define EMU_MEMCTRL_POWERDOWN_BLK23 (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0)
105 #define EMU_MEMCTRL_POWERDOWN_BLK123 (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0)
107 /* Bit fields for EMU LOCK */
108 #define _EMU_LOCK_RESETVALUE 0x00000000UL
109 #define _EMU_LOCK_MASK 0x0000FFFFUL
110 #define _EMU_LOCK_LOCKKEY_SHIFT 0
111 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL
112 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
113 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL
114 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
115 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
116 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL
117 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0)
118 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0)
119 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0)
120 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0)
121 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0)
123 /* Bit fields for EMU AUXCTRL */
124 #define _EMU_AUXCTRL_RESETVALUE 0x00000000UL
125 #define _EMU_AUXCTRL_MASK 0x00000101UL
126 #define EMU_AUXCTRL_HRCCLR (0x1UL << 0)
127 #define _EMU_AUXCTRL_HRCCLR_SHIFT 0
128 #define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL
129 #define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL
130 #define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)
131 #define EMU_AUXCTRL_REDLFXOBOOST (0x1UL << 8)
132 #define _EMU_AUXCTRL_REDLFXOBOOST_SHIFT 8
133 #define _EMU_AUXCTRL_REDLFXOBOOST_MASK 0x100UL
134 #define _EMU_AUXCTRL_REDLFXOBOOST_DEFAULT 0x00000000UL
135 #define EMU_AUXCTRL_REDLFXOBOOST_DEFAULT (_EMU_AUXCTRL_REDLFXOBOOST_DEFAULT << 8)
137 /* Bit fields for EMU EM4CONF */
138 #define _EMU_EM4CONF_RESETVALUE 0x00000000UL
139 #define _EMU_EM4CONF_MASK 0x0001001FUL
140 #define EMU_EM4CONF_VREGEN (0x1UL << 0)
141 #define _EMU_EM4CONF_VREGEN_SHIFT 0
142 #define _EMU_EM4CONF_VREGEN_MASK 0x1UL
143 #define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL
144 #define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0)
145 #define EMU_EM4CONF_BURTCWU (0x1UL << 1)
146 #define _EMU_EM4CONF_BURTCWU_SHIFT 1
147 #define _EMU_EM4CONF_BURTCWU_MASK 0x2UL
148 #define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL
149 #define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1)
150 #define _EMU_EM4CONF_OSC_SHIFT 2
151 #define _EMU_EM4CONF_OSC_MASK 0xCUL
152 #define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL
153 #define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL
154 #define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL
155 #define _EMU_EM4CONF_OSC_LFXO 0x00000002UL
156 #define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2)
157 #define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2)
158 #define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2)
159 #define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2)
160 #define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4)
161 #define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4
162 #define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL
163 #define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL
164 #define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4)
165 #define EMU_EM4CONF_LOCKCONF (0x1UL << 16)
166 #define _EMU_EM4CONF_LOCKCONF_SHIFT 16
167 #define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL
168 #define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL
169 #define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16)
171 /* Bit fields for EMU BUCTRL */
172 #define _EMU_BUCTRL_RESETVALUE 0x00000000UL
173 #define _EMU_BUCTRL_MASK 0x00000067UL
174 #define EMU_BUCTRL_EN (0x1UL << 0)
175 #define _EMU_BUCTRL_EN_SHIFT 0
176 #define _EMU_BUCTRL_EN_MASK 0x1UL
177 #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL
178 #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0)
179 #define EMU_BUCTRL_STATEN (0x1UL << 1)
180 #define _EMU_BUCTRL_STATEN_SHIFT 1
181 #define _EMU_BUCTRL_STATEN_MASK 0x2UL
182 #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL
183 #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1)
184 #define EMU_BUCTRL_BODCAL (0x1UL << 2)
185 #define _EMU_BUCTRL_BODCAL_SHIFT 2
186 #define _EMU_BUCTRL_BODCAL_MASK 0x4UL
187 #define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL
188 #define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2)
189 #define _EMU_BUCTRL_PROBE_SHIFT 5
190 #define _EMU_BUCTRL_PROBE_MASK 0x60UL
191 #define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL
192 #define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL
193 #define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL
194 #define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL
195 #define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL
196 #define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5)
197 #define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5)
198 #define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5)
199 #define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5)
200 #define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5)
202 /* Bit fields for EMU PWRCONF */
203 #define _EMU_PWRCONF_RESETVALUE 0x00000000UL
204 #define _EMU_PWRCONF_MASK 0x0000001FUL
205 #define EMU_PWRCONF_VOUTWEAK (0x1UL << 0)
206 #define _EMU_PWRCONF_VOUTWEAK_SHIFT 0
207 #define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL
208 #define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL
209 #define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0)
210 #define EMU_PWRCONF_VOUTMED (0x1UL << 1)
211 #define _EMU_PWRCONF_VOUTMED_SHIFT 1
212 #define _EMU_PWRCONF_VOUTMED_MASK 0x2UL
213 #define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL
214 #define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1)
215 #define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2)
216 #define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2
217 #define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL
218 #define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL
219 #define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2)
220 #define _EMU_PWRCONF_PWRRES_SHIFT 3
221 #define _EMU_PWRCONF_PWRRES_MASK 0x18UL
222 #define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL
223 #define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL
224 #define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL
225 #define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL
226 #define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL
227 #define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3)
228 #define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3)
229 #define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3)
230 #define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3)
231 #define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3)
233 /* Bit fields for EMU BUINACT */
234 #define _EMU_BUINACT_RESETVALUE 0x0000000BUL
235 #define _EMU_BUINACT_MASK 0x0000007FUL
236 #define _EMU_BUINACT_BUENTHRES_SHIFT 0
237 #define _EMU_BUINACT_BUENTHRES_MASK 0x7UL
238 #define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL
239 #define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0)
240 #define _EMU_BUINACT_BUENRANGE_SHIFT 3
241 #define _EMU_BUINACT_BUENRANGE_MASK 0x18UL
242 #define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL
243 #define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3)
244 #define _EMU_BUINACT_PWRCON_SHIFT 5
245 #define _EMU_BUINACT_PWRCON_MASK 0x60UL
246 #define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL
247 #define _EMU_BUINACT_PWRCON_NONE 0x00000000UL
248 #define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL
249 #define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL
250 #define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL
251 #define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5)
252 #define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5)
253 #define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5)
254 #define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5)
255 #define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5)
257 /* Bit fields for EMU BUACT */
258 #define _EMU_BUACT_RESETVALUE 0x0000000BUL
259 #define _EMU_BUACT_MASK 0x0000007FUL
260 #define _EMU_BUACT_BUEXTHRES_SHIFT 0
261 #define _EMU_BUACT_BUEXTHRES_MASK 0x7UL
262 #define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL
263 #define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0)
264 #define _EMU_BUACT_BUEXRANGE_SHIFT 3
265 #define _EMU_BUACT_BUEXRANGE_MASK 0x18UL
266 #define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL
267 #define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3)
268 #define _EMU_BUACT_PWRCON_SHIFT 5
269 #define _EMU_BUACT_PWRCON_MASK 0x60UL
270 #define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL
271 #define _EMU_BUACT_PWRCON_NONE 0x00000000UL
272 #define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL
273 #define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL
274 #define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL
275 #define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5)
276 #define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5)
277 #define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5)
278 #define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5)
279 #define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5)
281 /* Bit fields for EMU STATUS */
282 #define _EMU_STATUS_RESETVALUE 0x00000000UL
283 #define _EMU_STATUS_MASK 0x00000001UL
284 #define EMU_STATUS_BURDY (0x1UL << 0)
285 #define _EMU_STATUS_BURDY_SHIFT 0
286 #define _EMU_STATUS_BURDY_MASK 0x1UL
287 #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL
288 #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0)
290 /* Bit fields for EMU ROUTE */
291 #define _EMU_ROUTE_RESETVALUE 0x00000001UL
292 #define _EMU_ROUTE_MASK 0x00000001UL
293 #define EMU_ROUTE_BUVINPEN (0x1UL << 0)
294 #define _EMU_ROUTE_BUVINPEN_SHIFT 0
295 #define _EMU_ROUTE_BUVINPEN_MASK 0x1UL
296 #define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL
297 #define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0)
299 /* Bit fields for EMU IF */
300 #define _EMU_IF_RESETVALUE 0x00000000UL
301 #define _EMU_IF_MASK 0x00000001UL
302 #define EMU_IF_BURDY (0x1UL << 0)
303 #define _EMU_IF_BURDY_SHIFT 0
304 #define _EMU_IF_BURDY_MASK 0x1UL
305 #define _EMU_IF_BURDY_DEFAULT 0x00000000UL
306 #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0)
308 /* Bit fields for EMU IFS */
309 #define _EMU_IFS_RESETVALUE 0x00000000UL
310 #define _EMU_IFS_MASK 0x00000001UL
311 #define EMU_IFS_BURDY (0x1UL << 0)
312 #define _EMU_IFS_BURDY_SHIFT 0
313 #define _EMU_IFS_BURDY_MASK 0x1UL
314 #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL
315 #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0)
317 /* Bit fields for EMU IFC */
318 #define _EMU_IFC_RESETVALUE 0x00000000UL
319 #define _EMU_IFC_MASK 0x00000001UL
320 #define EMU_IFC_BURDY (0x1UL << 0)
321 #define _EMU_IFC_BURDY_SHIFT 0
322 #define _EMU_IFC_BURDY_MASK 0x1UL
323 #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL
324 #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0)
326 /* Bit fields for EMU IEN */
327 #define _EMU_IEN_RESETVALUE 0x00000000UL
328 #define _EMU_IEN_MASK 0x00000001UL
329 #define EMU_IEN_BURDY (0x1UL << 0)
330 #define _EMU_IEN_BURDY_SHIFT 0
331 #define _EMU_IEN_BURDY_MASK 0x1UL
332 #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL
333 #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0)
335 /* Bit fields for EMU BUBODBUVINCAL */
336 #define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL
337 #define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL
338 #define _EMU_BUBODBUVINCAL_THRES_SHIFT 0
339 #define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL
340 #define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL
341 #define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0)
342 #define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3
343 #define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL
344 #define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL
345 #define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3)
347 /* Bit fields for EMU BUBODUNREGCAL */
348 #define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL
349 #define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL
350 #define _EMU_BUBODUNREGCAL_THRES_SHIFT 0
351 #define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL
352 #define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL
353 #define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0)
354 #define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3
355 #define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL
356 #define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL
357 #define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3)
__IO uint32_t CTRL
Definition: efm32gg_emu.h:43
#define __IO
__IO uint32_t IEN
Definition: efm32gg_emu.h:61
__IO uint32_t BUBODUNREGCAL
Definition: efm32gg_emu.h:63
__I uint32_t STATUS
Definition: efm32gg_emu.h:56
__IO uint32_t BUACT
Definition: efm32gg_emu.h:55
__IO uint32_t IFC
Definition: efm32gg_emu.h:60
__IO uint32_t BUCTRL
Definition: efm32gg_emu.h:52
__IO uint32_t IFS
Definition: efm32gg_emu.h:59
__IO uint32_t AUXCTRL
Definition: efm32gg_emu.h:48
__IO uint32_t ROUTE
Definition: efm32gg_emu.h:57
__IO uint32_t LOCK
Definition: efm32gg_emu.h:45
__IO uint32_t BUINACT
Definition: efm32gg_emu.h:54
__IO uint32_t EM4CONF
Definition: efm32gg_emu.h:51
__IO uint32_t BUBODBUVINCAL
Definition: efm32gg_emu.h:62
__IO uint32_t MEMCTRL
Definition: efm32gg_emu.h:44
__I uint32_t IF
Definition: efm32gg_emu.h:58
__IO uint32_t PWRCONF
Definition: efm32gg_emu.h:53