release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32G/Include/efm32g_dmareq.h

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00001 /**************************************************************************/
00033 /**************************************************************************/
00037 #define DMAREQ_ADC0_SINGLE        ((8 << 16) + 0)  
00038 #define DMAREQ_ADC0_SCAN          ((8 << 16) + 1)  
00039 #define DMAREQ_DAC0_CH0           ((10 << 16) + 0) 
00040 #define DMAREQ_DAC0_CH1           ((10 << 16) + 1) 
00041 #define DMAREQ_USART0_RXDATAV     ((12 << 16) + 0) 
00042 #define DMAREQ_USART0_TXBL        ((12 << 16) + 1) 
00043 #define DMAREQ_USART0_TXEMPTY     ((12 << 16) + 2) 
00044 #define DMAREQ_USART1_RXDATAV     ((13 << 16) + 0) 
00045 #define DMAREQ_USART1_TXBL        ((13 << 16) + 1) 
00046 #define DMAREQ_USART1_TXEMPTY     ((13 << 16) + 2) 
00047 #define DMAREQ_USART2_RXDATAV     ((14 << 16) + 0) 
00048 #define DMAREQ_USART2_TXBL        ((14 << 16) + 1) 
00049 #define DMAREQ_USART2_TXEMPTY     ((14 << 16) + 2) 
00050 #define DMAREQ_LEUART0_RXDATAV    ((16 << 16) + 0) 
00051 #define DMAREQ_LEUART0_TXBL       ((16 << 16) + 1) 
00052 #define DMAREQ_LEUART0_TXEMPTY    ((16 << 16) + 2) 
00053 #define DMAREQ_LEUART1_RXDATAV    ((17 << 16) + 0) 
00054 #define DMAREQ_LEUART1_TXBL       ((17 << 16) + 1) 
00055 #define DMAREQ_LEUART1_TXEMPTY    ((17 << 16) + 2) 
00056 #define DMAREQ_I2C0_RXDATAV       ((20 << 16) + 0) 
00057 #define DMAREQ_I2C0_TXBL          ((20 << 16) + 1) 
00058 #define DMAREQ_TIMER0_UFOF        ((24 << 16) + 0) 
00059 #define DMAREQ_TIMER0_CC0         ((24 << 16) + 1) 
00060 #define DMAREQ_TIMER0_CC1         ((24 << 16) + 2) 
00061 #define DMAREQ_TIMER0_CC2         ((24 << 16) + 3) 
00062 #define DMAREQ_TIMER1_UFOF        ((25 << 16) + 0) 
00063 #define DMAREQ_TIMER1_CC0         ((25 << 16) + 1) 
00064 #define DMAREQ_TIMER1_CC1         ((25 << 16) + 2) 
00065 #define DMAREQ_TIMER1_CC2         ((25 << 16) + 3) 
00066 #define DMAREQ_TIMER2_UFOF        ((26 << 16) + 0) 
00067 #define DMAREQ_TIMER2_CC0         ((26 << 16) + 1) 
00068 #define DMAREQ_TIMER2_CC1         ((26 << 16) + 2) 
00069 #define DMAREQ_TIMER2_CC2         ((26 << 16) + 3) 
00070 #define DMAREQ_UART0_RXDATAV      ((44 << 16) + 0) 
00071 #define DMAREQ_UART0_TXBL         ((44 << 16) + 1) 
00072 #define DMAREQ_UART0_TXEMPTY      ((44 << 16) + 2) 
00073 #define DMAREQ_MSC_WDATA          ((48 << 16) + 0) 
00074 #define DMAREQ_AES_DATAWR         ((49 << 16) + 0) 
00075 #define DMAREQ_AES_XORDATAWR      ((49 << 16) + 1) 
00076 #define DMAREQ_AES_DATARD         ((49 << 16) + 2) 
00077 #define DMAREQ_AES_KEYWR          ((49 << 16) + 3)