release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32G/Include/efm32g_dma.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __I uint32_t   STATUS;         
00040   __O uint32_t   CONFIG;         
00041   __IO uint32_t  CTRLBASE;       
00042   __I uint32_t   ALTCTRLBASE;    
00043   __I uint32_t   CHWAITSTATUS;   
00044   __O uint32_t   CHSWREQ;        
00045   __IO uint32_t  CHUSEBURSTS;    
00046   __O uint32_t   CHUSEBURSTC;    
00047   __IO uint32_t  CHREQMASKS;     
00048   __O uint32_t   CHREQMASKC;     
00049   __IO uint32_t  CHENS;          
00050   __O uint32_t   CHENC;          
00051   __IO uint32_t  CHALTS;         
00052   __O uint32_t   CHALTC;         
00053   __IO uint32_t  CHPRIS;         
00054   __O uint32_t   CHPRIC;         
00055   uint32_t       RESERVED0[3];   
00056   __IO uint32_t  ERRORC;         
00057   uint32_t       RESERVED1[880]; 
00058   __I uint32_t   CHREQSTATUS;    
00059   uint32_t       RESERVED2[1];   
00060   __I uint32_t   CHSREQSTATUS;   
00062   uint32_t       RESERVED3[121]; 
00063   __I uint32_t   IF;             
00064   __IO uint32_t  IFS;            
00065   __IO uint32_t  IFC;            
00066   __IO uint32_t  IEN;            
00068   uint32_t       RESERVED4[60];  
00070   DMA_CH_TypeDef CH[8];          
00071 } DMA_TypeDef;                   
00073 /**************************************************************************/
00078 /* Bit fields for DMA STATUS */
00079 #define _DMA_STATUS_RESETVALUE                          0x10070000UL                          
00080 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00081 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00082 #define _DMA_STATUS_EN_SHIFT                            0                                     
00083 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00084 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00085 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00086 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00087 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00088 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00089 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00090 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00091 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00092 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00093 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00094 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00095 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00096 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00097 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00098 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00099 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00100 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00101 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00102 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00103 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00104 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00105 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00106 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00107 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00108 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00109 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00110 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00111 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00112 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00113 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00114 #define _DMA_STATUS_CHNUM_DEFAULT                       0x00000007UL                          
00115 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00117 /* Bit fields for DMA CONFIG */
00118 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00119 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00120 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00121 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00122 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00123 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00124 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00125 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00126 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00127 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00128 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00129 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00131 /* Bit fields for DMA CTRLBASE */
00132 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00133 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00134 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00135 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00136 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00137 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00139 /* Bit fields for DMA ALTCTRLBASE */
00140 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000080UL                                
00141 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00142 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00143 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00144 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000080UL                                
00145 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00147 /* Bit fields for DMA CHWAITSTATUS */
00148 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x000000FFUL                                   
00149 #define _DMA_CHWAITSTATUS_MASK                          0x000000FFUL                                   
00150 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   
00151 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              
00152 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          
00153 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   
00154 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 
00155 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   
00156 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              
00157 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          
00158 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   
00159 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 
00160 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   
00161 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              
00162 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          
00163 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   
00164 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 
00165 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   
00166 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              
00167 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          
00168 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   
00169 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 
00170 #define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                   
00171 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                              
00172 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                         
00173 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                   
00174 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) 
00175 #define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                   
00176 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                              
00177 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                         
00178 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                   
00179 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) 
00180 #define DMA_CHWAITSTATUS_CH6WAITSTATUS                  (0x1UL << 6)                                   
00181 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT           6                                              
00182 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK            0x40UL                                         
00183 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT         0x00000001UL                                   
00184 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) 
00185 #define DMA_CHWAITSTATUS_CH7WAITSTATUS                  (0x1UL << 7)                                   
00186 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT           7                                              
00187 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK            0x80UL                                         
00188 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT         0x00000001UL                                   
00189 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) 
00191 /* Bit fields for DMA CHSWREQ */
00192 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         
00193 #define _DMA_CHSWREQ_MASK                               0x000000FFUL                         
00194 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         
00195 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    
00196 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                
00197 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         
00198 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 
00199 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         
00200 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    
00201 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                
00202 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         
00203 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 
00204 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         
00205 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    
00206 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                
00207 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         
00208 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 
00209 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         
00210 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    
00211 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                
00212 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         
00213 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 
00214 #define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                         
00215 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                    
00216 #define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                               
00217 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                         
00218 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) 
00219 #define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                         
00220 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                    
00221 #define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                               
00222 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                         
00223 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) 
00224 #define DMA_CHSWREQ_CH6SWREQ                            (0x1UL << 6)                         
00225 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT                     6                                    
00226 #define _DMA_CHSWREQ_CH6SWREQ_MASK                      0x40UL                               
00227 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT                   0x00000000UL                         
00228 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) 
00229 #define DMA_CHSWREQ_CH7SWREQ                            (0x1UL << 7)                         
00230 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT                     7                                    
00231 #define _DMA_CHSWREQ_CH7SWREQ_MASK                      0x80UL                               
00232 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT                   0x00000000UL                         
00233 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) 
00235 /* Bit fields for DMA CHUSEBURSTS */
00236 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00237 #define _DMA_CHUSEBURSTS_MASK                           0x000000FFUL                                        
00238 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00239 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00240 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00241 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00242 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00243 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00244 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00245 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00246 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00247 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00248 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00249 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00250 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00251 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00252 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00253 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00254 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00255 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00256 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00257 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00258 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00259 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00260 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00261 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00262 #define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        
00263 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   
00264 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              
00265 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        
00266 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        
00267 #define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        
00268 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   
00269 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              
00270 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        
00271 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        
00272 #define DMA_CHUSEBURSTS_CH6USEBURSTS                    (0x1UL << 6)                                        
00273 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT             6                                                   
00274 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK              0x40UL                                              
00275 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT           0x00000000UL                                        
00276 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)        
00277 #define DMA_CHUSEBURSTS_CH7USEBURSTS                    (0x1UL << 7)                                        
00278 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT             7                                                   
00279 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK              0x80UL                                              
00280 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT           0x00000000UL                                        
00281 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)        
00283 /* Bit fields for DMA CHUSEBURSTC */
00284 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 
00285 #define _DMA_CHUSEBURSTC_MASK                           0x000000FFUL                                 
00286 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 
00287 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            
00288 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        
00289 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 
00290 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 
00291 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 
00292 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            
00293 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        
00294 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 
00295 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 
00296 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 
00297 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            
00298 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        
00299 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 
00300 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 
00301 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 
00302 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            
00303 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        
00304 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 
00305 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 
00306 #define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                 
00307 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                            
00308 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                       
00309 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                 
00310 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) 
00311 #define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                 
00312 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                            
00313 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                       
00314 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                 
00315 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) 
00316 #define DMA_CHUSEBURSTC_CH6USEBURSTC                    (0x1UL << 6)                                 
00317 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT             6                                            
00318 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK              0x40UL                                       
00319 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT           0x00000000UL                                 
00320 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) 
00321 #define DMA_CHUSEBURSTC_CH7USEBURSTC                    (0x1UL << 7)                                 
00322 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT             7                                            
00323 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK              0x80UL                                       
00324 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT           0x00000000UL                                 
00325 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) 
00327 /* Bit fields for DMA CHREQMASKS */
00328 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               
00329 #define _DMA_CHREQMASKS_MASK                            0x000000FFUL                               
00330 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               
00331 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          
00332 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      
00333 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               
00334 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 
00335 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               
00336 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          
00337 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      
00338 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               
00339 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 
00340 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               
00341 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          
00342 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      
00343 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               
00344 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 
00345 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               
00346 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          
00347 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      
00348 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               
00349 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 
00350 #define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                               
00351 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                          
00352 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                     
00353 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                               
00354 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) 
00355 #define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                               
00356 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                          
00357 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                     
00358 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                               
00359 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) 
00360 #define DMA_CHREQMASKS_CH6REQMASKS                      (0x1UL << 6)                               
00361 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT               6                                          
00362 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK                0x40UL                                     
00363 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT             0x00000000UL                               
00364 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) 
00365 #define DMA_CHREQMASKS_CH7REQMASKS                      (0x1UL << 7)                               
00366 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT               7                                          
00367 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK                0x80UL                                     
00368 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT             0x00000000UL                               
00369 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) 
00371 /* Bit fields for DMA CHREQMASKC */
00372 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               
00373 #define _DMA_CHREQMASKC_MASK                            0x000000FFUL                               
00374 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               
00375 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          
00376 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      
00377 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               
00378 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 
00379 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               
00380 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          
00381 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      
00382 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               
00383 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 
00384 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               
00385 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          
00386 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      
00387 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               
00388 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 
00389 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               
00390 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          
00391 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      
00392 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               
00393 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 
00394 #define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                               
00395 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                          
00396 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                     
00397 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                               
00398 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) 
00399 #define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                               
00400 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                          
00401 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                     
00402 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                               
00403 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) 
00404 #define DMA_CHREQMASKC_CH6REQMASKC                      (0x1UL << 6)                               
00405 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT               6                                          
00406 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK                0x40UL                                     
00407 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT             0x00000000UL                               
00408 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) 
00409 #define DMA_CHREQMASKC_CH7REQMASKC                      (0x1UL << 7)                               
00410 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT               7                                          
00411 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK                0x80UL                                     
00412 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT             0x00000000UL                               
00413 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) 
00415 /* Bit fields for DMA CHENS */
00416 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                     
00417 #define _DMA_CHENS_MASK                                 0x000000FFUL                     
00418 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     
00419 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                
00420 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            
00421 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     
00422 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) 
00423 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     
00424 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                
00425 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            
00426 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     
00427 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) 
00428 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     
00429 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                
00430 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            
00431 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     
00432 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) 
00433 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     
00434 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                
00435 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            
00436 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     
00437 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) 
00438 #define DMA_CHENS_CH4ENS                                (0x1UL << 4)                     
00439 #define _DMA_CHENS_CH4ENS_SHIFT                         4                                
00440 #define _DMA_CHENS_CH4ENS_MASK                          0x10UL                           
00441 #define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                     
00442 #define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4) 
00443 #define DMA_CHENS_CH5ENS                                (0x1UL << 5)                     
00444 #define _DMA_CHENS_CH5ENS_SHIFT                         5                                
00445 #define _DMA_CHENS_CH5ENS_MASK                          0x20UL                           
00446 #define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                     
00447 #define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5) 
00448 #define DMA_CHENS_CH6ENS                                (0x1UL << 6)                     
00449 #define _DMA_CHENS_CH6ENS_SHIFT                         6                                
00450 #define _DMA_CHENS_CH6ENS_MASK                          0x40UL                           
00451 #define _DMA_CHENS_CH6ENS_DEFAULT                       0x00000000UL                     
00452 #define DMA_CHENS_CH6ENS_DEFAULT                        (_DMA_CHENS_CH6ENS_DEFAULT << 6) 
00453 #define DMA_CHENS_CH7ENS                                (0x1UL << 7)                     
00454 #define _DMA_CHENS_CH7ENS_SHIFT                         7                                
00455 #define _DMA_CHENS_CH7ENS_MASK                          0x80UL                           
00456 #define _DMA_CHENS_CH7ENS_DEFAULT                       0x00000000UL                     
00457 #define DMA_CHENS_CH7ENS_DEFAULT                        (_DMA_CHENS_CH7ENS_DEFAULT << 7) 
00459 /* Bit fields for DMA CHENC */
00460 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                     
00461 #define _DMA_CHENC_MASK                                 0x000000FFUL                     
00462 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     
00463 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                
00464 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            
00465 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     
00466 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) 
00467 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     
00468 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                
00469 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            
00470 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     
00471 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) 
00472 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     
00473 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                
00474 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            
00475 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     
00476 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) 
00477 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     
00478 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                
00479 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            
00480 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     
00481 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) 
00482 #define DMA_CHENC_CH4ENC                                (0x1UL << 4)                     
00483 #define _DMA_CHENC_CH4ENC_SHIFT                         4                                
00484 #define _DMA_CHENC_CH4ENC_MASK                          0x10UL                           
00485 #define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                     
00486 #define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4) 
00487 #define DMA_CHENC_CH5ENC                                (0x1UL << 5)                     
00488 #define _DMA_CHENC_CH5ENC_SHIFT                         5                                
00489 #define _DMA_CHENC_CH5ENC_MASK                          0x20UL                           
00490 #define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                     
00491 #define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5) 
00492 #define DMA_CHENC_CH6ENC                                (0x1UL << 6)                     
00493 #define _DMA_CHENC_CH6ENC_SHIFT                         6                                
00494 #define _DMA_CHENC_CH6ENC_MASK                          0x40UL                           
00495 #define _DMA_CHENC_CH6ENC_DEFAULT                       0x00000000UL                     
00496 #define DMA_CHENC_CH6ENC_DEFAULT                        (_DMA_CHENC_CH6ENC_DEFAULT << 6) 
00497 #define DMA_CHENC_CH7ENC                                (0x1UL << 7)                     
00498 #define _DMA_CHENC_CH7ENC_SHIFT                         7                                
00499 #define _DMA_CHENC_CH7ENC_MASK                          0x80UL                           
00500 #define _DMA_CHENC_CH7ENC_DEFAULT                       0x00000000UL                     
00501 #define DMA_CHENC_CH7ENC_DEFAULT                        (_DMA_CHENC_CH7ENC_DEFAULT << 7) 
00503 /* Bit fields for DMA CHALTS */
00504 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       
00505 #define _DMA_CHALTS_MASK                                0x000000FFUL                       
00506 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       
00507 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  
00508 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              
00509 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       
00510 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 
00511 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       
00512 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  
00513 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              
00514 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       
00515 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 
00516 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       
00517 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  
00518 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              
00519 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       
00520 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 
00521 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       
00522 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  
00523 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              
00524 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       
00525 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 
00526 #define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                       
00527 #define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                  
00528 #define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                             
00529 #define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                       
00530 #define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) 
00531 #define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                       
00532 #define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                  
00533 #define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                             
00534 #define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                       
00535 #define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) 
00536 #define DMA_CHALTS_CH6ALTS                              (0x1UL << 6)                       
00537 #define _DMA_CHALTS_CH6ALTS_SHIFT                       6                                  
00538 #define _DMA_CHALTS_CH6ALTS_MASK                        0x40UL                             
00539 #define _DMA_CHALTS_CH6ALTS_DEFAULT                     0x00000000UL                       
00540 #define DMA_CHALTS_CH6ALTS_DEFAULT                      (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) 
00541 #define DMA_CHALTS_CH7ALTS                              (0x1UL << 7)                       
00542 #define _DMA_CHALTS_CH7ALTS_SHIFT                       7                                  
00543 #define _DMA_CHALTS_CH7ALTS_MASK                        0x80UL                             
00544 #define _DMA_CHALTS_CH7ALTS_DEFAULT                     0x00000000UL                       
00545 #define DMA_CHALTS_CH7ALTS_DEFAULT                      (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) 
00547 /* Bit fields for DMA CHALTC */
00548 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       
00549 #define _DMA_CHALTC_MASK                                0x000000FFUL                       
00550 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       
00551 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  
00552 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              
00553 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       
00554 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 
00555 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       
00556 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  
00557 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              
00558 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       
00559 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 
00560 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       
00561 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  
00562 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              
00563 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       
00564 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 
00565 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       
00566 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  
00567 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              
00568 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       
00569 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 
00570 #define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                       
00571 #define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                  
00572 #define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                             
00573 #define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                       
00574 #define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) 
00575 #define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                       
00576 #define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                  
00577 #define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                             
00578 #define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                       
00579 #define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) 
00580 #define DMA_CHALTC_CH6ALTC                              (0x1UL << 6)                       
00581 #define _DMA_CHALTC_CH6ALTC_SHIFT                       6                                  
00582 #define _DMA_CHALTC_CH6ALTC_MASK                        0x40UL                             
00583 #define _DMA_CHALTC_CH6ALTC_DEFAULT                     0x00000000UL                       
00584 #define DMA_CHALTC_CH6ALTC_DEFAULT                      (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) 
00585 #define DMA_CHALTC_CH7ALTC                              (0x1UL << 7)                       
00586 #define _DMA_CHALTC_CH7ALTC_SHIFT                       7                                  
00587 #define _DMA_CHALTC_CH7ALTC_MASK                        0x80UL                             
00588 #define _DMA_CHALTC_CH7ALTC_DEFAULT                     0x00000000UL                       
00589 #define DMA_CHALTC_CH7ALTC_DEFAULT                      (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) 
00591 /* Bit fields for DMA CHPRIS */
00592 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       
00593 #define _DMA_CHPRIS_MASK                                0x000000FFUL                       
00594 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       
00595 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  
00596 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              
00597 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       
00598 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 
00599 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       
00600 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  
00601 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              
00602 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       
00603 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 
00604 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       
00605 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  
00606 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              
00607 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       
00608 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 
00609 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       
00610 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  
00611 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              
00612 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       
00613 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 
00614 #define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                       
00615 #define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                  
00616 #define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                             
00617 #define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                       
00618 #define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) 
00619 #define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                       
00620 #define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                  
00621 #define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                             
00622 #define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                       
00623 #define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) 
00624 #define DMA_CHPRIS_CH6PRIS                              (0x1UL << 6)                       
00625 #define _DMA_CHPRIS_CH6PRIS_SHIFT                       6                                  
00626 #define _DMA_CHPRIS_CH6PRIS_MASK                        0x40UL                             
00627 #define _DMA_CHPRIS_CH6PRIS_DEFAULT                     0x00000000UL                       
00628 #define DMA_CHPRIS_CH6PRIS_DEFAULT                      (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) 
00629 #define DMA_CHPRIS_CH7PRIS                              (0x1UL << 7)                       
00630 #define _DMA_CHPRIS_CH7PRIS_SHIFT                       7                                  
00631 #define _DMA_CHPRIS_CH7PRIS_MASK                        0x80UL                             
00632 #define _DMA_CHPRIS_CH7PRIS_DEFAULT                     0x00000000UL                       
00633 #define DMA_CHPRIS_CH7PRIS_DEFAULT                      (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) 
00635 /* Bit fields for DMA CHPRIC */
00636 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       
00637 #define _DMA_CHPRIC_MASK                                0x000000FFUL                       
00638 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       
00639 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  
00640 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              
00641 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       
00642 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 
00643 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       
00644 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  
00645 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              
00646 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       
00647 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 
00648 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       
00649 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  
00650 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              
00651 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       
00652 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 
00653 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       
00654 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  
00655 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              
00656 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       
00657 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 
00658 #define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                       
00659 #define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                  
00660 #define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                             
00661 #define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                       
00662 #define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) 
00663 #define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                       
00664 #define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                  
00665 #define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                             
00666 #define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                       
00667 #define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) 
00668 #define DMA_CHPRIC_CH6PRIC                              (0x1UL << 6)                       
00669 #define _DMA_CHPRIC_CH6PRIC_SHIFT                       6                                  
00670 #define _DMA_CHPRIC_CH6PRIC_MASK                        0x40UL                             
00671 #define _DMA_CHPRIC_CH6PRIC_DEFAULT                     0x00000000UL                       
00672 #define DMA_CHPRIC_CH6PRIC_DEFAULT                      (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) 
00673 #define DMA_CHPRIC_CH7PRIC                              (0x1UL << 7)                       
00674 #define _DMA_CHPRIC_CH7PRIC_SHIFT                       7                                  
00675 #define _DMA_CHPRIC_CH7PRIC_MASK                        0x80UL                             
00676 #define _DMA_CHPRIC_CH7PRIC_DEFAULT                     0x00000000UL                       
00677 #define DMA_CHPRIC_CH7PRIC_DEFAULT                      (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) 
00679 /* Bit fields for DMA ERRORC */
00680 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
00681 #define _DMA_ERRORC_MASK                                0x00000001UL                      
00682 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
00683 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
00684 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
00685 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
00686 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
00688 /* Bit fields for DMA CHREQSTATUS */
00689 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 
00690 #define _DMA_CHREQSTATUS_MASK                           0x000000FFUL                                 
00691 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 
00692 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            
00693 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        
00694 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 
00695 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 
00696 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 
00697 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            
00698 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        
00699 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 
00700 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 
00701 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 
00702 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            
00703 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        
00704 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 
00705 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 
00706 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 
00707 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            
00708 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        
00709 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 
00710 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 
00711 #define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                 
00712 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                            
00713 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                       
00714 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                 
00715 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) 
00716 #define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                 
00717 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                            
00718 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                       
00719 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                 
00720 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) 
00721 #define DMA_CHREQSTATUS_CH6REQSTATUS                    (0x1UL << 6)                                 
00722 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT             6                                            
00723 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK              0x40UL                                       
00724 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT           0x00000000UL                                 
00725 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) 
00726 #define DMA_CHREQSTATUS_CH7REQSTATUS                    (0x1UL << 7)                                 
00727 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT             7                                            
00728 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK              0x80UL                                       
00729 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT           0x00000000UL                                 
00730 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) 
00732 /* Bit fields for DMA CHSREQSTATUS */
00733 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   
00734 #define _DMA_CHSREQSTATUS_MASK                          0x000000FFUL                                   
00735 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   
00736 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              
00737 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          
00738 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   
00739 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 
00740 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   
00741 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              
00742 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          
00743 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   
00744 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 
00745 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   
00746 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              
00747 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          
00748 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   
00749 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 
00750 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   
00751 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              
00752 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          
00753 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   
00754 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 
00755 #define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                   
00756 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                              
00757 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                         
00758 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                   
00759 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) 
00760 #define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                   
00761 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                              
00762 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                         
00763 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                   
00764 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) 
00765 #define DMA_CHSREQSTATUS_CH6SREQSTATUS                  (0x1UL << 6)                                   
00766 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT           6                                              
00767 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK            0x40UL                                         
00768 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT         0x00000000UL                                   
00769 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) 
00770 #define DMA_CHSREQSTATUS_CH7SREQSTATUS                  (0x1UL << 7)                                   
00771 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT           7                                              
00772 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK            0x80UL                                         
00773 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT         0x00000000UL                                   
00774 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) 
00776 /* Bit fields for DMA IF */
00777 #define _DMA_IF_RESETVALUE                              0x00000000UL                   
00778 #define _DMA_IF_MASK                                    0x800000FFUL                   
00779 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                   
00780 #define _DMA_IF_CH0DONE_SHIFT                           0                              
00781 #define _DMA_IF_CH0DONE_MASK                            0x1UL                          
00782 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   
00783 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) 
00784 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                   
00785 #define _DMA_IF_CH1DONE_SHIFT                           1                              
00786 #define _DMA_IF_CH1DONE_MASK                            0x2UL                          
00787 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   
00788 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) 
00789 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                   
00790 #define _DMA_IF_CH2DONE_SHIFT                           2                              
00791 #define _DMA_IF_CH2DONE_MASK                            0x4UL                          
00792 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   
00793 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) 
00794 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                   
00795 #define _DMA_IF_CH3DONE_SHIFT                           3                              
00796 #define _DMA_IF_CH3DONE_MASK                            0x8UL                          
00797 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   
00798 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) 
00799 #define DMA_IF_CH4DONE                                  (0x1UL << 4)                   
00800 #define _DMA_IF_CH4DONE_SHIFT                           4                              
00801 #define _DMA_IF_CH4DONE_MASK                            0x10UL                         
00802 #define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                   
00803 #define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4) 
00804 #define DMA_IF_CH5DONE                                  (0x1UL << 5)                   
00805 #define _DMA_IF_CH5DONE_SHIFT                           5                              
00806 #define _DMA_IF_CH5DONE_MASK                            0x20UL                         
00807 #define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                   
00808 #define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5) 
00809 #define DMA_IF_CH6DONE                                  (0x1UL << 6)                   
00810 #define _DMA_IF_CH6DONE_SHIFT                           6                              
00811 #define _DMA_IF_CH6DONE_MASK                            0x40UL                         
00812 #define _DMA_IF_CH6DONE_DEFAULT                         0x00000000UL                   
00813 #define DMA_IF_CH6DONE_DEFAULT                          (_DMA_IF_CH6DONE_DEFAULT << 6) 
00814 #define DMA_IF_CH7DONE                                  (0x1UL << 7)                   
00815 #define _DMA_IF_CH7DONE_SHIFT                           7                              
00816 #define _DMA_IF_CH7DONE_MASK                            0x80UL                         
00817 #define _DMA_IF_CH7DONE_DEFAULT                         0x00000000UL                   
00818 #define DMA_IF_CH7DONE_DEFAULT                          (_DMA_IF_CH7DONE_DEFAULT << 7) 
00819 #define DMA_IF_ERR                                      (0x1UL << 31)                  
00820 #define _DMA_IF_ERR_SHIFT                               31                             
00821 #define _DMA_IF_ERR_MASK                                0x80000000UL                   
00822 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   
00823 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    
00825 /* Bit fields for DMA IFS */
00826 #define _DMA_IFS_RESETVALUE                             0x00000000UL                    
00827 #define _DMA_IFS_MASK                                   0x800000FFUL                    
00828 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    
00829 #define _DMA_IFS_CH0DONE_SHIFT                          0                               
00830 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                           
00831 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    
00832 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) 
00833 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    
00834 #define _DMA_IFS_CH1DONE_SHIFT                          1                               
00835 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                           
00836 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    
00837 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) 
00838 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    
00839 #define _DMA_IFS_CH2DONE_SHIFT                          2                               
00840 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                           
00841 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    
00842 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) 
00843 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    
00844 #define _DMA_IFS_CH3DONE_SHIFT                          3                               
00845 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                           
00846 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    
00847 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) 
00848 #define DMA_IFS_CH4DONE                                 (0x1UL << 4)                    
00849 #define _DMA_IFS_CH4DONE_SHIFT                          4                               
00850 #define _DMA_IFS_CH4DONE_MASK                           0x10UL                          
00851 #define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                    
00852 #define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4) 
00853 #define DMA_IFS_CH5DONE                                 (0x1UL << 5)                    
00854 #define _DMA_IFS_CH5DONE_SHIFT                          5                               
00855 #define _DMA_IFS_CH5DONE_MASK                           0x20UL                          
00856 #define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                    
00857 #define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5) 
00858 #define DMA_IFS_CH6DONE                                 (0x1UL << 6)                    
00859 #define _DMA_IFS_CH6DONE_SHIFT                          6                               
00860 #define _DMA_IFS_CH6DONE_MASK                           0x40UL                          
00861 #define _DMA_IFS_CH6DONE_DEFAULT                        0x00000000UL                    
00862 #define DMA_IFS_CH6DONE_DEFAULT                         (_DMA_IFS_CH6DONE_DEFAULT << 6) 
00863 #define DMA_IFS_CH7DONE                                 (0x1UL << 7)                    
00864 #define _DMA_IFS_CH7DONE_SHIFT                          7                               
00865 #define _DMA_IFS_CH7DONE_MASK                           0x80UL                          
00866 #define _DMA_IFS_CH7DONE_DEFAULT                        0x00000000UL                    
00867 #define DMA_IFS_CH7DONE_DEFAULT                         (_DMA_IFS_CH7DONE_DEFAULT << 7) 
00868 #define DMA_IFS_ERR                                     (0x1UL << 31)                   
00869 #define _DMA_IFS_ERR_SHIFT                              31                              
00870 #define _DMA_IFS_ERR_MASK                               0x80000000UL                    
00871 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    
00872 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    
00874 /* Bit fields for DMA IFC */
00875 #define _DMA_IFC_RESETVALUE                             0x00000000UL                    
00876 #define _DMA_IFC_MASK                                   0x800000FFUL                    
00877 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    
00878 #define _DMA_IFC_CH0DONE_SHIFT                          0                               
00879 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                           
00880 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    
00881 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) 
00882 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    
00883 #define _DMA_IFC_CH1DONE_SHIFT                          1                               
00884 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                           
00885 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    
00886 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) 
00887 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    
00888 #define _DMA_IFC_CH2DONE_SHIFT                          2                               
00889 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                           
00890 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    
00891 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) 
00892 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    
00893 #define _DMA_IFC_CH3DONE_SHIFT                          3                               
00894 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                           
00895 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    
00896 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) 
00897 #define DMA_IFC_CH4DONE                                 (0x1UL << 4)                    
00898 #define _DMA_IFC_CH4DONE_SHIFT                          4                               
00899 #define _DMA_IFC_CH4DONE_MASK                           0x10UL                          
00900 #define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                    
00901 #define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4) 
00902 #define DMA_IFC_CH5DONE                                 (0x1UL << 5)                    
00903 #define _DMA_IFC_CH5DONE_SHIFT                          5                               
00904 #define _DMA_IFC_CH5DONE_MASK                           0x20UL                          
00905 #define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                    
00906 #define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5) 
00907 #define DMA_IFC_CH6DONE                                 (0x1UL << 6)                    
00908 #define _DMA_IFC_CH6DONE_SHIFT                          6                               
00909 #define _DMA_IFC_CH6DONE_MASK                           0x40UL                          
00910 #define _DMA_IFC_CH6DONE_DEFAULT                        0x00000000UL                    
00911 #define DMA_IFC_CH6DONE_DEFAULT                         (_DMA_IFC_CH6DONE_DEFAULT << 6) 
00912 #define DMA_IFC_CH7DONE                                 (0x1UL << 7)                    
00913 #define _DMA_IFC_CH7DONE_SHIFT                          7                               
00914 #define _DMA_IFC_CH7DONE_MASK                           0x80UL                          
00915 #define _DMA_IFC_CH7DONE_DEFAULT                        0x00000000UL                    
00916 #define DMA_IFC_CH7DONE_DEFAULT                         (_DMA_IFC_CH7DONE_DEFAULT << 7) 
00917 #define DMA_IFC_ERR                                     (0x1UL << 31)                   
00918 #define _DMA_IFC_ERR_SHIFT                              31                              
00919 #define _DMA_IFC_ERR_MASK                               0x80000000UL                    
00920 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    
00921 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    
00923 /* Bit fields for DMA IEN */
00924 #define _DMA_IEN_RESETVALUE                             0x00000000UL                    
00925 #define _DMA_IEN_MASK                                   0x800000FFUL                    
00926 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    
00927 #define _DMA_IEN_CH0DONE_SHIFT                          0                               
00928 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                           
00929 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    
00930 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) 
00931 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    
00932 #define _DMA_IEN_CH1DONE_SHIFT                          1                               
00933 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                           
00934 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    
00935 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) 
00936 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    
00937 #define _DMA_IEN_CH2DONE_SHIFT                          2                               
00938 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                           
00939 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    
00940 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) 
00941 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    
00942 #define _DMA_IEN_CH3DONE_SHIFT                          3                               
00943 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                           
00944 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    
00945 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) 
00946 #define DMA_IEN_CH4DONE                                 (0x1UL << 4)                    
00947 #define _DMA_IEN_CH4DONE_SHIFT                          4                               
00948 #define _DMA_IEN_CH4DONE_MASK                           0x10UL                          
00949 #define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                    
00950 #define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4) 
00951 #define DMA_IEN_CH5DONE                                 (0x1UL << 5)                    
00952 #define _DMA_IEN_CH5DONE_SHIFT                          5                               
00953 #define _DMA_IEN_CH5DONE_MASK                           0x20UL                          
00954 #define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                    
00955 #define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5) 
00956 #define DMA_IEN_CH6DONE                                 (0x1UL << 6)                    
00957 #define _DMA_IEN_CH6DONE_SHIFT                          6                               
00958 #define _DMA_IEN_CH6DONE_MASK                           0x40UL                          
00959 #define _DMA_IEN_CH6DONE_DEFAULT                        0x00000000UL                    
00960 #define DMA_IEN_CH6DONE_DEFAULT                         (_DMA_IEN_CH6DONE_DEFAULT << 6) 
00961 #define DMA_IEN_CH7DONE                                 (0x1UL << 7)                    
00962 #define _DMA_IEN_CH7DONE_SHIFT                          7                               
00963 #define _DMA_IEN_CH7DONE_MASK                           0x80UL                          
00964 #define _DMA_IEN_CH7DONE_DEFAULT                        0x00000000UL                    
00965 #define DMA_IEN_CH7DONE_DEFAULT                         (_DMA_IEN_CH7DONE_DEFAULT << 7) 
00966 #define DMA_IEN_ERR                                     (0x1UL << 31)                   
00967 #define _DMA_IEN_ERR_SHIFT                              31                              
00968 #define _DMA_IEN_ERR_MASK                               0x80000000UL                    
00969 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    
00970 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    
00972 /* Bit fields for DMA CH_CTRL */
00973 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                              
00974 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                              
00975 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                         
00976 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                     
00977 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE                  0x00000000UL                              
00978 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0                     0x00000000UL                              
00979 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                              
00980 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                              
00981 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV               0x00000000UL                              
00982 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                              
00983 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV              0x00000000UL                              
00984 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                              
00985 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                              
00986 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                              
00987 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF                  0x00000000UL                              
00988 #define _DMA_CH_CTRL_SIGSEL_UART0RXDATAV                0x00000000UL                              
00989 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                              
00990 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR                   0x00000000UL                              
00991 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN                    0x00000001UL                              
00992 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1                     0x00000001UL                              
00993 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                              
00994 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                              
00995 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL                  0x00000001UL                              
00996 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                              
00997 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL                 0x00000001UL                              
00998 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                              
00999 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                              
01000 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                              
01001 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0                   0x00000001UL                              
01002 #define _DMA_CH_CTRL_SIGSEL_UART0TXBL                   0x00000001UL                              
01003 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR                0x00000001UL                              
01004 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                              
01005 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                              
01006 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY               0x00000002UL                              
01007 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                              
01008 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY              0x00000002UL                              
01009 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                              
01010 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                              
01011 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1                   0x00000002UL                              
01012 #define _DMA_CH_CTRL_SIGSEL_UART0TXEMPTY                0x00000002UL                              
01013 #define _DMA_CH_CTRL_SIGSEL_AESDATARD                   0x00000002UL                              
01014 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                              
01015 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                              
01016 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2                   0x00000003UL                              
01017 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR                    0x00000003UL                              
01018 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE                   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)     
01019 #define DMA_CH_CTRL_SIGSEL_DAC0CH0                      (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)        
01020 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)  
01021 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)  
01022 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)  
01023 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) 
01024 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) 
01025 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)    
01026 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)     
01027 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)     
01028 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)     
01029 #define DMA_CH_CTRL_SIGSEL_UART0RXDATAV                 (_DMA_CH_CTRL_SIGSEL_UART0RXDATAV << 0)   
01030 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)       
01031 #define DMA_CH_CTRL_SIGSEL_AESDATAWR                    (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)      
01032 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN                     (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)       
01033 #define DMA_CH_CTRL_SIGSEL_DAC0CH1                      (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)        
01034 #define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)     
01035 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)     
01036 #define DMA_CH_CTRL_SIGSEL_USART2TXBL                   (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)     
01037 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)    
01038 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)    
01039 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)       
01040 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)      
01041 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)      
01042 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)      
01043 #define DMA_CH_CTRL_SIGSEL_UART0TXBL                    (_DMA_CH_CTRL_SIGSEL_UART0TXBL << 0)      
01044 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR                 (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)   
01045 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)  
01046 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)  
01047 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)  
01048 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) 
01049 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) 
01050 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)      
01051 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)      
01052 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)      
01053 #define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY                 (_DMA_CH_CTRL_SIGSEL_UART0TXEMPTY << 0)   
01054 #define DMA_CH_CTRL_SIGSEL_AESDATARD                    (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)      
01055 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)      
01056 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)      
01057 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)      
01058 #define DMA_CH_CTRL_SIGSEL_AESKEYWR                     (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)       
01059 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                        
01060 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                
01061 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                              
01062 #define _DMA_CH_CTRL_SOURCESEL_ADC0                     0x00000008UL                              
01063 #define _DMA_CH_CTRL_SOURCESEL_DAC0                     0x0000000AUL                              
01064 #define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                              
01065 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                              
01066 #define _DMA_CH_CTRL_SOURCESEL_USART2                   0x0000000EUL                              
01067 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                              
01068 #define _DMA_CH_CTRL_SOURCESEL_LEUART1                  0x00000011UL                              
01069 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                              
01070 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                              
01071 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                              
01072 #define _DMA_CH_CTRL_SOURCESEL_TIMER2                   0x0000001AUL                              
01073 #define _DMA_CH_CTRL_SOURCESEL_UART0                    0x0000002CUL                              
01074 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                              
01075 #define _DMA_CH_CTRL_SOURCESEL_AES                      0x00000031UL                              
01076 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)       
01077 #define DMA_CH_CTRL_SOURCESEL_ADC0                      (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)       
01078 #define DMA_CH_CTRL_SOURCESEL_DAC0                      (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)       
01079 #define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)     
01080 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)     
01081 #define DMA_CH_CTRL_SOURCESEL_USART2                    (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)     
01082 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)    
01083 #define DMA_CH_CTRL_SOURCESEL_LEUART1                   (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)    
01084 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)       
01085 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)     
01086 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)     
01087 #define DMA_CH_CTRL_SOURCESEL_TIMER2                    (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)     
01088 #define DMA_CH_CTRL_SOURCESEL_UART0                     (_DMA_CH_CTRL_SOURCESEL_UART0 << 16)      
01089 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)        
01090 #define DMA_CH_CTRL_SOURCESEL_AES                       (_DMA_CH_CTRL_SOURCESEL_AES << 16)