release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32G/Include/efm32g200f16.h

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00001 /**************************************************************************/
00034 #ifndef __SILICON_LABS_EFM32G200F16_H__
00035 #define __SILICON_LABS_EFM32G200F16_H__
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M3 Processor Exceptions Numbers *******************************************/
00055   NonMaskableInt_IRQn   = -14,              
00056   HardFault_IRQn        = -13,              
00057   MemoryManagement_IRQn = -12,              
00058   BusFault_IRQn         = -11,              
00059   UsageFault_IRQn       = -10,              
00060   SVCall_IRQn           = -5,               
00061   DebugMonitor_IRQn     = -4,               
00062   PendSV_IRQn           = -2,               
00063   SysTick_IRQn          = -1,               
00065 /******  EFM32G Peripheral Interrupt Numbers **********************************************/
00066   DMA_IRQn              = 0,  
00067   GPIO_EVEN_IRQn        = 1,  
00068   TIMER0_IRQn           = 2,  
00069   USART0_RX_IRQn        = 3,  
00070   USART0_TX_IRQn        = 4,  
00071   ACMP0_IRQn            = 5,  
00072   ADC0_IRQn             = 6,  
00073   DAC0_IRQn             = 7,  
00074   I2C0_IRQn             = 8,  
00075   GPIO_ODD_IRQn         = 9,  
00076   TIMER1_IRQn           = 10, 
00077   USART1_RX_IRQn        = 12, 
00078   USART1_TX_IRQn        = 13, 
00079   LEUART0_IRQn          = 18, 
00080   LETIMER0_IRQn         = 20, 
00081   PCNT0_IRQn            = 21, 
00082   RTC_IRQn              = 24, 
00083   CMU_IRQn              = 25, 
00084   VCMP_IRQn             = 26, 
00085   MSC_IRQn              = 28, 
00086 } IRQn_Type;
00087 
00088 /**************************************************************************/
00093 #define __MPU_PRESENT             1 
00094 #define __NVIC_PRIO_BITS          3 
00095 #define __Vendor_SysTickConfig    0 
00099 /**************************************************************************/
00105 #define _EFM32_GECKO_FAMILY             1 
00106 #define _EFM_DEVICE                       
00107 #define _SILICON_LABS_32B_PLATFORM_1      
00108 #define _SILICON_LABS_32B_PLATFORM      1 
00110 /* If part number is not defined as compiler option, define it */
00111 #if !defined(EFM32G200F16)
00112 #define EFM32G200F16    1 
00113 #endif
00114 
00116 #define PART_NUMBER          "EFM32G200F16" 
00119 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00120 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00121 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00122 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00123 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00124 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00125 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00126 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00127 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00128 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00129 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00130 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00131 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00132 #define RAM_MEM_SIZE         ((uint32_t) 0x8000UL)     
00133 #define RAM_MEM_END          ((uint32_t) 0x20007FFFUL) 
00134 #define RAM_MEM_BITS         ((uint32_t) 0x15UL)       
00135 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00136 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x4000UL)     
00137 #define RAM_CODE_MEM_END     ((uint32_t) 0x10003FFFUL) 
00138 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x14UL)       
00139 #define EBI_MEM_BASE         ((uint32_t) 0x80000000UL) 
00140 #define EBI_MEM_SIZE         ((uint32_t) 0x10000000UL) 
00141 #define EBI_MEM_END          ((uint32_t) 0x8FFFFFFFUL) 
00142 #define EBI_MEM_BITS         ((uint32_t) 0x28UL)       
00145 #define BITBAND_PER_BASE     ((uint32_t) 0x42000000UL) 
00146 #define BITBAND_RAM_BASE     ((uint32_t) 0x22000000UL) 
00149 #define FLASH_BASE           (0x00000000UL) 
00150 #define FLASH_SIZE           (0x00004000UL) 
00151 #define FLASH_PAGE_SIZE      512            
00152 #define SRAM_BASE            (0x20000000UL) 
00153 #define SRAM_SIZE            (0x00002000UL) 
00154 #define __CM3_REV            0x200          
00155 #define PRS_CHAN_COUNT       8              
00156 #define DMA_CHAN_COUNT       8              
00159 #define AFCHAN_MAX           79
00160 #define AFCHANLOC_MAX        4
00161 
00162 #define AFACHAN_MAX          37
00163 
00164 /* Part number capabilities */
00165 
00166 #define TIMER_PRESENT         
00167 #define TIMER_COUNT         2 
00168 #define USART_PRESENT         
00169 #define USART_COUNT         2 
00170 #define LEUART_PRESENT        
00171 #define LEUART_COUNT        1 
00172 #define LETIMER_PRESENT       
00173 #define LETIMER_COUNT       1 
00174 #define PCNT_PRESENT          
00175 #define PCNT_COUNT          1 
00176 #define ACMP_PRESENT          
00177 #define ACMP_COUNT          2 
00178 #define DAC_PRESENT           
00179 #define DAC_COUNT           1 
00180 #define ADC_PRESENT           
00181 #define ADC_COUNT           1 
00182 #define I2C_PRESENT           
00183 #define I2C_COUNT           1 
00184 #define DMA_PRESENT
00185 #define DMA_COUNT           1
00186 #define LE_PRESENT
00187 #define LE_COUNT            1
00188 #define MSC_PRESENT
00189 #define MSC_COUNT           1
00190 #define EMU_PRESENT
00191 #define EMU_COUNT           1
00192 #define RMU_PRESENT
00193 #define RMU_COUNT           1
00194 #define CMU_PRESENT
00195 #define CMU_COUNT           1
00196 #define RTC_PRESENT
00197 #define RTC_COUNT           1
00198 #define PRS_PRESENT
00199 #define PRS_COUNT           1
00200 #define GPIO_PRESENT
00201 #define GPIO_COUNT          1
00202 #define VCMP_PRESENT
00203 #define VCMP_COUNT          1
00204 #define HFXTAL_PRESENT
00205 #define HFXTAL_COUNT        1
00206 #define LFXTAL_PRESENT
00207 #define LFXTAL_COUNT        1
00208 #define WDOG_PRESENT
00209 #define WDOG_COUNT          1
00210 #define DBG_PRESENT
00211 #define DBG_COUNT           1
00212 #define BOOTLOADER_PRESENT
00213 #define BOOTLOADER_COUNT    1
00214 #define ANALOG_PRESENT
00215 #define ANALOG_COUNT        1
00216 
00217 #include "core_cm3.h"      /* Cortex-M3 processor and core peripherals */
00218 #include "system_efm32g.h" /* System Header */
00219 
00222 /**************************************************************************/
00228 #include "efm32g_dma_ch.h"
00229 
00230 /**************************************************************************/
00235 typedef struct
00236 {
00237   __I uint32_t   STATUS;         
00238   __O uint32_t   CONFIG;         
00239   __IO uint32_t  CTRLBASE;       
00240   __I uint32_t   ALTCTRLBASE;    
00241   __I uint32_t   CHWAITSTATUS;   
00242   __O uint32_t   CHSWREQ;        
00243   __IO uint32_t  CHUSEBURSTS;    
00244   __O uint32_t   CHUSEBURSTC;    
00245   __IO uint32_t  CHREQMASKS;     
00246   __O uint32_t   CHREQMASKC;     
00247   __IO uint32_t  CHENS;          
00248   __O uint32_t   CHENC;          
00249   __IO uint32_t  CHALTS;         
00250   __O uint32_t   CHALTC;         
00251   __IO uint32_t  CHPRIS;         
00252   __O uint32_t   CHPRIC;         
00253   uint32_t       RESERVED0[3];   
00254   __IO uint32_t  ERRORC;         
00255   uint32_t       RESERVED1[880]; 
00256   __I uint32_t   CHREQSTATUS;    
00257   uint32_t       RESERVED2[1];   
00258   __I uint32_t   CHSREQSTATUS;   
00260   uint32_t       RESERVED3[121]; 
00261   __I uint32_t   IF;             
00262   __IO uint32_t  IFS;            
00263   __IO uint32_t  IFC;            
00264   __IO uint32_t  IEN;            
00266   uint32_t       RESERVED4[60];  
00268   DMA_CH_TypeDef CH[8];          
00269 } DMA_TypeDef;                   
00271 #include "efm32g_msc.h"
00272 #include "efm32g_emu.h"
00273 #include "efm32g_rmu.h"
00274 
00275 /**************************************************************************/
00280 typedef struct
00281 {
00282   __IO uint32_t CTRL;         
00283   __IO uint32_t HFCORECLKDIV; 
00284   __IO uint32_t HFPERCLKDIV;  
00285   __IO uint32_t HFRCOCTRL;    
00286   __IO uint32_t LFRCOCTRL;    
00287   __IO uint32_t AUXHFRCOCTRL; 
00288   __IO uint32_t CALCTRL;      
00289   __IO uint32_t CALCNT;       
00290   __IO uint32_t OSCENCMD;     
00291   __IO uint32_t CMD;          
00292   __IO uint32_t LFCLKSEL;     
00293   __I uint32_t  STATUS;       
00294   __I uint32_t  IF;           
00295   __IO uint32_t IFS;          
00296   __IO uint32_t IFC;          
00297   __IO uint32_t IEN;          
00298   __IO uint32_t HFCORECLKEN0; 
00299   __IO uint32_t HFPERCLKEN0;  
00300   uint32_t      RESERVED0[2]; 
00301   __I uint32_t  SYNCBUSY;     
00302   __IO uint32_t FREEZE;       
00303   __IO uint32_t LFACLKEN0;    
00304   uint32_t      RESERVED1[1]; 
00305   __IO uint32_t LFBCLKEN0;    
00306   uint32_t      RESERVED2[1]; 
00307   __IO uint32_t LFAPRESC0;    
00308   uint32_t      RESERVED3[1]; 
00309   __IO uint32_t LFBPRESC0;    
00310   uint32_t      RESERVED4[1]; 
00311   __IO uint32_t PCNTCTRL;     
00312   uint32_t      RESERVED5[1]; 
00313   __IO uint32_t ROUTE;        
00314   __IO uint32_t LOCK;         
00315 } CMU_TypeDef;                
00317 #include "efm32g_timer_cc.h"
00318 #include "efm32g_timer.h"
00319 #include "efm32g_usart.h"
00320 #include "efm32g_leuart.h"
00321 #include "efm32g_rtc.h"
00322 #include "efm32g_letimer.h"
00323 #include "efm32g_pcnt.h"
00324 #include "efm32g_acmp.h"
00325 #include "efm32g_prs_ch.h"
00326 
00327 /**************************************************************************/
00332 typedef struct
00333 {
00334   __IO uint32_t  SWPULSE;      
00335   __IO uint32_t  SWLEVEL;      
00337   uint32_t       RESERVED0[2]; 
00339   PRS_CH_TypeDef CH[8];        
00340 } PRS_TypeDef;                 
00342 #include "efm32g_dac.h"
00343 #include "efm32g_gpio_p.h"
00344 #include "efm32g_gpio.h"
00345 #include "efm32g_vcmp.h"
00346 #include "efm32g_adc.h"
00347 #include "efm32g_i2c.h"
00348 #include "efm32g_wdog.h"
00349 #include "efm32g_dma_descriptor.h"
00350 #include "efm32g_devinfo.h"
00351 #include "efm32g_romtable.h"
00352 #include "efm32g_calibrate.h"
00353 
00356 /**************************************************************************/
00361 #define DMA_BASE          (0x400C2000UL) 
00362 #define MSC_BASE          (0x400C0000UL) 
00363 #define EMU_BASE          (0x400C6000UL) 
00364 #define RMU_BASE          (0x400CA000UL) 
00365 #define CMU_BASE          (0x400C8000UL) 
00366 #define TIMER0_BASE       (0x40010000UL) 
00367 #define TIMER1_BASE       (0x40010400UL) 
00368 #define USART0_BASE       (0x4000C000UL) 
00369 #define USART1_BASE       (0x4000C400UL) 
00370 #define LEUART0_BASE      (0x40084000UL) 
00371 #define RTC_BASE          (0x40080000UL) 
00372 #define LETIMER0_BASE     (0x40082000UL) 
00373 #define PCNT0_BASE        (0x40086000UL) 
00374 #define ACMP0_BASE        (0x40001000UL) 
00375 #define ACMP1_BASE        (0x40001400UL) 
00376 #define PRS_BASE          (0x400CC000UL) 
00377 #define DAC0_BASE         (0x40004000UL) 
00378 #define GPIO_BASE         (0x40006000UL) 
00379 #define VCMP_BASE         (0x40000000UL) 
00380 #define ADC0_BASE         (0x40002000UL) 
00381 #define I2C0_BASE         (0x4000A000UL) 
00382 #define WDOG_BASE         (0x40088000UL) 
00383 #define CALIBRATE_BASE    (0x0FE08000UL) 
00384 #define DEVINFO_BASE      (0x0FE081B0UL) 
00385 #define ROMTABLE_BASE     (0xE00FFFD0UL) 
00386 #define LOCKBITS_BASE     (0x0FE04000UL) 
00387 #define USERDATA_BASE     (0x0FE00000UL) 
00391 /**************************************************************************/
00396 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00397 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00398 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00399 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00400 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00401 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00402 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00403 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00404 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00405 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00406 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00407 #define LETIMER0     ((LETIMER_TypeDef *) LETIMER0_BASE)    
00408 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00409 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00410 #define ACMP1        ((ACMP_TypeDef *) ACMP1_BASE)          
00411 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00412 #define DAC0         ((DAC_TypeDef *) DAC0_BASE)            
00413 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00414 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00415 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
00416 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00417 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00418 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00419 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00420 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00424 /**************************************************************************/
00429 /**************************************************************************/
00435 #define PRS_VCMP_OUT          ((1 << 16) + 0)  
00436 #define PRS_ACMP0_OUT         ((2 << 16) + 0)  
00437 #define PRS_ACMP1_OUT         ((3 << 16) + 0)  
00438 #define PRS_DAC0_CH0          ((6 << 16) + 0)  
00439 #define PRS_DAC0_CH1          ((6 << 16) + 1)  
00440 #define PRS_ADC0_SINGLE       ((8 << 16) + 0)  
00441 #define PRS_ADC0_SCAN         ((8 << 16) + 1)  
00442 #define PRS_USART0_IRTX       ((16 << 16) + 0) 
00443 #define PRS_USART0_TXC        ((16 << 16) + 1) 
00444 #define PRS_USART0_RXDATAV    ((16 << 16) + 2) 
00445 #define PRS_USART1_IRTX       ((17 << 16) + 0) 
00446 #define PRS_USART1_TXC        ((17 << 16) + 1) 
00447 #define PRS_USART1_RXDATAV    ((17 << 16) + 2) 
00448 #define PRS_TIMER0_UF         ((28 << 16) + 0) 
00449 #define PRS_TIMER0_OF         ((28 << 16) + 1) 
00450 #define PRS_TIMER0_CC0        ((28 << 16) + 2) 
00451 #define PRS_TIMER0_CC1        ((28 << 16) + 3) 
00452 #define PRS_TIMER0_CC2        ((28 << 16) + 4) 
00453 #define PRS_TIMER1_UF         ((29 << 16) + 0) 
00454 #define PRS_TIMER1_OF         ((29 << 16) + 1) 
00455 #define PRS_TIMER1_CC0        ((29 << 16) + 2) 
00456 #define PRS_TIMER1_CC1        ((29 << 16) + 3) 
00457 #define PRS_TIMER1_CC2        ((29 << 16) + 4) 
00458 #define PRS_RTC_OF            ((40 << 16) + 0) 
00459 #define PRS_RTC_COMP0         ((40 << 16) + 1) 
00460 #define PRS_RTC_COMP1         ((40 << 16) + 2) 
00461 #define PRS_GPIO_PIN0         ((48 << 16) + 0) 
00462 #define PRS_GPIO_PIN1         ((48 << 16) + 1) 
00463 #define PRS_GPIO_PIN2         ((48 << 16) + 2) 
00464 #define PRS_GPIO_PIN3         ((48 << 16) + 3) 
00465 #define PRS_GPIO_PIN4         ((48 << 16) + 4) 
00466 #define PRS_GPIO_PIN5         ((48 << 16) + 5) 
00467 #define PRS_GPIO_PIN6         ((48 << 16) + 6) 
00468 #define PRS_GPIO_PIN7         ((48 << 16) + 7) 
00469 #define PRS_GPIO_PIN8         ((49 << 16) + 0) 
00470 #define PRS_GPIO_PIN9         ((49 << 16) + 1) 
00471 #define PRS_GPIO_PIN10        ((49 << 16) + 2) 
00472 #define PRS_GPIO_PIN11        ((49 << 16) + 3) 
00473 #define PRS_GPIO_PIN12        ((49 << 16) + 4) 
00474 #define PRS_GPIO_PIN13        ((49 << 16) + 5) 
00475 #define PRS_GPIO_PIN14        ((49 << 16) + 6) 
00476 #define PRS_GPIO_PIN15        ((49 << 16) + 7) 
00480 #include "efm32g_dmareq.h"
00481 #include "efm32g_dmactrl.h"
00482 
00483 /**************************************************************************/
00488 /* Bit fields for DMA STATUS */
00489 #define _DMA_STATUS_RESETVALUE                          0x10070000UL                          
00490 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00491 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00492 #define _DMA_STATUS_EN_SHIFT                            0                                     
00493 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00494 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00495 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00496 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00497 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00498 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00499 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00500 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00501 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00502 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00503 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00504 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00505 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00506 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00507 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00508 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00509 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00510 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00511 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00512 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00513 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00514 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00515 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00516 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00517 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00518 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00519 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00520 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00521 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00522 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00523 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00524 #define _DMA_STATUS_CHNUM_DEFAULT                       0x00000007UL                          
00525 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00527 /* Bit fields for DMA CONFIG */
00528 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00529 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00530 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00531 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00532 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00533 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00534 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00535 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00536 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00537 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00538 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00539 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00541 /* Bit fields for DMA CTRLBASE */
00542 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00543 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00544 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00545 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00546 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00547 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00549 /* Bit fields for DMA ALTCTRLBASE */
00550 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000080UL                                
00551 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00552 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00553 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00554 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000080UL                                
00555 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00557 /* Bit fields for DMA CHWAITSTATUS */
00558 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x000000FFUL                                   
00559 #define _DMA_CHWAITSTATUS_MASK                          0x000000FFUL                                   
00560 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   
00561 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              
00562 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          
00563 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   
00564 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 
00565 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   
00566 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              
00567 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          
00568 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   
00569 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 
00570 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   
00571 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              
00572 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          
00573 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   
00574 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 
00575 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   
00576 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              
00577 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          
00578 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   
00579 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 
00580 #define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                   
00581 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                              
00582 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                         
00583 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                   
00584 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) 
00585 #define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                   
00586 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                              
00587 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                         
00588 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                   
00589 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) 
00590 #define DMA_CHWAITSTATUS_CH6WAITSTATUS                  (0x1UL << 6)                                   
00591 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT           6                                              
00592 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK            0x40UL                                         
00593 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT         0x00000001UL                                   
00594 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) 
00595 #define DMA_CHWAITSTATUS_CH7WAITSTATUS                  (0x1UL << 7)                                   
00596 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT           7                                              
00597 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK            0x80UL                                         
00598 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT         0x00000001UL                                   
00599 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) 
00601 /* Bit fields for DMA CHSWREQ */
00602 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         
00603 #define _DMA_CHSWREQ_MASK                               0x000000FFUL                         
00604 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         
00605 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    
00606 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                
00607 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         
00608 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 
00609 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         
00610 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    
00611 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                
00612 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         
00613 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 
00614 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         
00615 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    
00616 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                
00617 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         
00618 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 
00619 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         
00620 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    
00621 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                
00622 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         
00623 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 
00624 #define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                         
00625 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                    
00626 #define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                               
00627 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                         
00628 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) 
00629 #define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                         
00630 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                    
00631 #define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                               
00632 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                         
00633 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) 
00634 #define DMA_CHSWREQ_CH6SWREQ                            (0x1UL << 6)                         
00635 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT                     6                                    
00636 #define _DMA_CHSWREQ_CH6SWREQ_MASK                      0x40UL                               
00637 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT                   0x00000000UL                         
00638 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) 
00639 #define DMA_CHSWREQ_CH7SWREQ                            (0x1UL << 7)                         
00640 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT                     7                                    
00641 #define _DMA_CHSWREQ_CH7SWREQ_MASK                      0x80UL                               
00642 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT                   0x00000000UL                         
00643 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) 
00645 /* Bit fields for DMA CHUSEBURSTS */
00646 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00647 #define _DMA_CHUSEBURSTS_MASK                           0x000000FFUL                                        
00648 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00649 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00650 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00651 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00652 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00653 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00654 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00655 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00656 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00657 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00658 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00659 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00660 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00661 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00662 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00663 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00664 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00665 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00666 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00667 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00668 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00669 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00670 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00671 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00672 #define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        
00673 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   
00674 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              
00675 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        
00676 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        
00677 #define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        
00678 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   
00679 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              
00680 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        
00681 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        
00682 #define DMA_CHUSEBURSTS_CH6USEBURSTS                    (0x1UL << 6)                                        
00683 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT             6                                                   
00684 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK              0x40UL                                              
00685 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT           0x00000000UL                                        
00686 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)        
00687 #define DMA_CHUSEBURSTS_CH7USEBURSTS                    (0x1UL << 7)                                        
00688 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT             7                                                   
00689 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK              0x80UL                                              
00690 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT           0x00000000UL                                        
00691 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)        
00693 /* Bit fields for DMA CHUSEBURSTC */
00694 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 
00695 #define _DMA_CHUSEBURSTC_MASK                           0x000000FFUL                                 
00696 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 
00697 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            
00698 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        
00699 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 
00700 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 
00701 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 
00702 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            
00703 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        
00704 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 
00705 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 
00706 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 
00707 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            
00708 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        
00709 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 
00710 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 
00711 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 
00712 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            
00713 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        
00714 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 
00715 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 
00716 #define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                 
00717 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                            
00718 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                       
00719 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                 
00720 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) 
00721 #define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                 
00722 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                            
00723 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                       
00724 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                 
00725 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) 
00726 #define DMA_CHUSEBURSTC_CH6USEBURSTC                    (0x1UL << 6)                                 
00727 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT             6                                            
00728 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK              0x40UL                                       
00729 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT           0x00000000UL                                 
00730 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) 
00731 #define DMA_CHUSEBURSTC_CH7USEBURSTC                    (0x1UL << 7)                                 
00732 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT             7                                            
00733 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK              0x80UL                                       
00734 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT           0x00000000UL                                 
00735 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) 
00737 /* Bit fields for DMA CHREQMASKS */
00738 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               
00739 #define _DMA_CHREQMASKS_MASK                            0x000000FFUL                               
00740 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               
00741 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          
00742 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      
00743 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               
00744 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 
00745 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               
00746 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          
00747 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      
00748 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               
00749 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 
00750 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               
00751 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          
00752 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      
00753 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               
00754 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 
00755 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               
00756 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          
00757 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      
00758 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               
00759 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 
00760 #define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                               
00761 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                          
00762 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                     
00763 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                               
00764 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) 
00765 #define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                               
00766 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                          
00767 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                     
00768 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                               
00769 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) 
00770 #define DMA_CHREQMASKS_CH6REQMASKS                      (0x1UL << 6)                               
00771 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT               6                                          
00772 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK                0x40UL                                     
00773 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT             0x00000000UL                               
00774 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) 
00775 #define DMA_CHREQMASKS_CH7REQMASKS                      (0x1UL << 7)                               
00776 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT               7                                          
00777 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK                0x80UL                                     
00778 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT             0x00000000UL                               
00779 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) 
00781 /* Bit fields for DMA CHREQMASKC */
00782 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               
00783 #define _DMA_CHREQMASKC_MASK                            0x000000FFUL                               
00784 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               
00785 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          
00786 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      
00787 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               
00788 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 
00789 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               
00790 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          
00791 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      
00792 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               
00793 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 
00794 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               
00795 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          
00796 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      
00797 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               
00798 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 
00799 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               
00800 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          
00801 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      
00802 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               
00803 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 
00804 #define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                               
00805 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                          
00806 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                     
00807 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                               
00808 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) 
00809 #define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                               
00810 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                          
00811 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                     
00812 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                               
00813 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) 
00814 #define DMA_CHREQMASKC_CH6REQMASKC                      (0x1UL << 6)                               
00815 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT               6                                          
00816 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK                0x40UL                                     
00817 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT             0x00000000UL                               
00818 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) 
00819 #define DMA_CHREQMASKC_CH7REQMASKC                      (0x1UL << 7)                               
00820 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT               7                                          
00821 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK                0x80UL                                     
00822 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT             0x00000000UL                               
00823 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) 
00825 /* Bit fields for DMA CHENS */
00826 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                     
00827 #define _DMA_CHENS_MASK                                 0x000000FFUL                     
00828 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     
00829 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                
00830 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            
00831 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     
00832 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) 
00833 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     
00834 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                
00835 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            
00836 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     
00837 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) 
00838 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     
00839 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                
00840 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            
00841 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     
00842 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) 
00843 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     
00844 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                
00845 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            
00846 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     
00847 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) 
00848 #define DMA_CHENS_CH4ENS                                (0x1UL << 4)                     
00849 #define _DMA_CHENS_CH4ENS_SHIFT                         4                                
00850 #define _DMA_CHENS_CH4ENS_MASK                          0x10UL                           
00851 #define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                     
00852 #define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4) 
00853 #define DMA_CHENS_CH5ENS                                (0x1UL << 5)                     
00854 #define _DMA_CHENS_CH5ENS_SHIFT                         5                                
00855 #define _DMA_CHENS_CH5ENS_MASK                          0x20UL                           
00856 #define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                     
00857 #define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5) 
00858 #define DMA_CHENS_CH6ENS                                (0x1UL << 6)                     
00859 #define _DMA_CHENS_CH6ENS_SHIFT                         6                                
00860 #define _DMA_CHENS_CH6ENS_MASK                          0x40UL                           
00861 #define _DMA_CHENS_CH6ENS_DEFAULT                       0x00000000UL                     
00862 #define DMA_CHENS_CH6ENS_DEFAULT                        (_DMA_CHENS_CH6ENS_DEFAULT << 6) 
00863 #define DMA_CHENS_CH7ENS                                (0x1UL << 7)                     
00864 #define _DMA_CHENS_CH7ENS_SHIFT                         7                                
00865 #define _DMA_CHENS_CH7ENS_MASK                          0x80UL                           
00866 #define _DMA_CHENS_CH7ENS_DEFAULT                       0x00000000UL                     
00867 #define DMA_CHENS_CH7ENS_DEFAULT                        (_DMA_CHENS_CH7ENS_DEFAULT << 7) 
00869 /* Bit fields for DMA CHENC */
00870 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                     
00871 #define _DMA_CHENC_MASK                                 0x000000FFUL                     
00872 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     
00873 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                
00874 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            
00875 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     
00876 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) 
00877 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     
00878 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                
00879 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            
00880 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     
00881 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) 
00882 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     
00883 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                
00884 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            
00885 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     
00886 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) 
00887 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     
00888 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                
00889 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            
00890 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     
00891 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) 
00892 #define DMA_CHENC_CH4ENC                                (0x1UL << 4)                     
00893 #define _DMA_CHENC_CH4ENC_SHIFT                         4                                
00894 #define _DMA_CHENC_CH4ENC_MASK                          0x10UL                           
00895 #define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                     
00896 #define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4) 
00897 #define DMA_CHENC_CH5ENC                                (0x1UL << 5)                     
00898 #define _DMA_CHENC_CH5ENC_SHIFT                         5                                
00899 #define _DMA_CHENC_CH5ENC_MASK                          0x20UL                           
00900 #define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                     
00901 #define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5) 
00902 #define DMA_CHENC_CH6ENC                                (0x1UL << 6)                     
00903 #define _DMA_CHENC_CH6ENC_SHIFT                         6                                
00904 #define _DMA_CHENC_CH6ENC_MASK                          0x40UL                           
00905 #define _DMA_CHENC_CH6ENC_DEFAULT                       0x00000000UL                     
00906 #define DMA_CHENC_CH6ENC_DEFAULT                        (_DMA_CHENC_CH6ENC_DEFAULT << 6) 
00907 #define DMA_CHENC_CH7ENC                                (0x1UL << 7)                     
00908 #define _DMA_CHENC_CH7ENC_SHIFT                         7                                
00909 #define _DMA_CHENC_CH7ENC_MASK                          0x80UL                           
00910 #define _DMA_CHENC_CH7ENC_DEFAULT                       0x00000000UL                     
00911 #define DMA_CHENC_CH7ENC_DEFAULT                        (_DMA_CHENC_CH7ENC_DEFAULT << 7) 
00913 /* Bit fields for DMA CHALTS */
00914 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       
00915 #define _DMA_CHALTS_MASK                                0x000000FFUL                       
00916 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       
00917 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  
00918 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              
00919 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       
00920 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 
00921 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       
00922 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  
00923 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              
00924 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       
00925 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 
00926 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       
00927 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  
00928 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              
00929 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       
00930 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 
00931 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       
00932 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  
00933 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              
00934 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       
00935 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 
00936 #define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                       
00937 #define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                  
00938 #define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                             
00939 #define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                       
00940 #define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) 
00941 #define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                       
00942 #define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                  
00943 #define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                             
00944 #define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                       
00945 #define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) 
00946 #define DMA_CHALTS_CH6ALTS                              (0x1UL << 6)                       
00947 #define _DMA_CHALTS_CH6ALTS_SHIFT                       6                                  
00948 #define _DMA_CHALTS_CH6ALTS_MASK                        0x40UL                             
00949 #define _DMA_CHALTS_CH6ALTS_DEFAULT                     0x00000000UL                       
00950 #define DMA_CHALTS_CH6ALTS_DEFAULT                      (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) 
00951 #define DMA_CHALTS_CH7ALTS                              (0x1UL << 7)                       
00952 #define _DMA_CHALTS_CH7ALTS_SHIFT                       7                                  
00953 #define _DMA_CHALTS_CH7ALTS_MASK                        0x80UL                             
00954 #define _DMA_CHALTS_CH7ALTS_DEFAULT                     0x00000000UL                       
00955 #define DMA_CHALTS_CH7ALTS_DEFAULT                      (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) 
00957 /* Bit fields for DMA CHALTC */
00958 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       
00959 #define _DMA_CHALTC_MASK                                0x000000FFUL                       
00960 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       
00961 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  
00962 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              
00963 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       
00964 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 
00965 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       
00966 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  
00967 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              
00968 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       
00969 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 
00970 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       
00971 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  
00972 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              
00973 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       
00974 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 
00975 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       
00976 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  
00977 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              
00978 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       
00979 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 
00980 #define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                       
00981 #define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                  
00982 #define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                             
00983 #define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                       
00984 #define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) 
00985 #define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                       
00986 #define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                  
00987 #define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                             
00988 #define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                       
00989 #define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) 
00990 #define DMA_CHALTC_CH6ALTC                              (0x1UL << 6)                       
00991 #define _DMA_CHALTC_CH6ALTC_SHIFT                       6                                  
00992 #define _DMA_CHALTC_CH6ALTC_MASK                        0x40UL                             
00993 #define _DMA_CHALTC_CH6ALTC_DEFAULT                     0x00000000UL                       
00994 #define DMA_CHALTC_CH6ALTC_DEFAULT                      (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) 
00995 #define DMA_CHALTC_CH7ALTC                              (0x1UL << 7)                       
00996 #define _DMA_CHALTC_CH7ALTC_SHIFT                       7                                  
00997 #define _DMA_CHALTC_CH7ALTC_MASK                        0x80UL                             
00998 #define _DMA_CHALTC_CH7ALTC_DEFAULT                     0x00000000UL                       
00999 #define DMA_CHALTC_CH7ALTC_DEFAULT                      (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) 
01001 /* Bit fields for DMA CHPRIS */
01002 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       
01003 #define _DMA_CHPRIS_MASK                                0x000000FFUL                       
01004 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       
01005 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  
01006 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              
01007 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       
01008 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 
01009 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       
01010 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  
01011 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              
01012 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       
01013 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 
01014 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       
01015 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  
01016 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              
01017 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       
01018 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 
01019 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       
01020 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  
01021 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              
01022 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       
01023 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 
01024 #define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                       
01025 #define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                  
01026 #define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                             
01027 #define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                       
01028 #define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) 
01029 #define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                       
01030 #define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                  
01031 #define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                             
01032 #define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                       
01033 #define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) 
01034 #define DMA_CHPRIS_CH6PRIS                              (0x1UL << 6)                       
01035 #define _DMA_CHPRIS_CH6PRIS_SHIFT                       6                                  
01036 #define _DMA_CHPRIS_CH6PRIS_MASK                        0x40UL                             
01037 #define _DMA_CHPRIS_CH6PRIS_DEFAULT                     0x00000000UL                       
01038 #define DMA_CHPRIS_CH6PRIS_DEFAULT                      (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) 
01039 #define DMA_CHPRIS_CH7PRIS                              (0x1UL << 7)                       
01040 #define _DMA_CHPRIS_CH7PRIS_SHIFT                       7                                  
01041 #define _DMA_CHPRIS_CH7PRIS_MASK                        0x80UL                             
01042 #define _DMA_CHPRIS_CH7PRIS_DEFAULT                     0x00000000UL                       
01043 #define DMA_CHPRIS_CH7PRIS_DEFAULT                      (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) 
01045 /* Bit fields for DMA CHPRIC */
01046 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       
01047 #define _DMA_CHPRIC_MASK                                0x000000FFUL                       
01048 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       
01049 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  
01050 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              
01051 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       
01052 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 
01053 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       
01054 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  
01055 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              
01056 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       
01057 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 
01058 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       
01059 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  
01060 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              
01061 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       
01062 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 
01063 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       
01064 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  
01065 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              
01066 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       
01067 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 
01068 #define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                       
01069 #define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                  
01070 #define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                             
01071 #define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                       
01072 #define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) 
01073 #define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                       
01074 #define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                  
01075 #define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                             
01076 #define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                       
01077 #define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) 
01078 #define DMA_CHPRIC_CH6PRIC                              (0x1UL << 6)                       
01079 #define _DMA_CHPRIC_CH6PRIC_SHIFT                       6                                  
01080 #define _DMA_CHPRIC_CH6PRIC_MASK                        0x40UL                             
01081 #define _DMA_CHPRIC_CH6PRIC_DEFAULT                     0x00000000UL                       
01082 #define DMA_CHPRIC_CH6PRIC_DEFAULT                      (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) 
01083 #define DMA_CHPRIC_CH7PRIC                              (0x1UL << 7)                       
01084 #define _DMA_CHPRIC_CH7PRIC_SHIFT                       7                                  
01085 #define _DMA_CHPRIC_CH7PRIC_MASK                        0x80UL                             
01086 #define _DMA_CHPRIC_CH7PRIC_DEFAULT                     0x00000000UL                       
01087 #define DMA_CHPRIC_CH7PRIC_DEFAULT                      (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) 
01089 /* Bit fields for DMA ERRORC */
01090 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
01091 #define _DMA_ERRORC_MASK                                0x00000001UL                      
01092 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
01093 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
01094 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
01095 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
01096 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
01098 /* Bit fields for DMA CHREQSTATUS */
01099 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 
01100 #define _DMA_CHREQSTATUS_MASK                           0x000000FFUL                                 
01101 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 
01102 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            
01103 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        
01104 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 
01105 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 
01106 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 
01107 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            
01108 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        
01109 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 
01110 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 
01111 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 
01112 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            
01113 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        
01114 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 
01115 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 
01116 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 
01117 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            
01118 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        
01119 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 
01120 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 
01121 #define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                 
01122 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                            
01123 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                       
01124 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                 
01125 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) 
01126 #define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                 
01127 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                            
01128 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                       
01129 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                 
01130 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) 
01131 #define DMA_CHREQSTATUS_CH6REQSTATUS                    (0x1UL << 6)                                 
01132 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT             6                                            
01133 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK              0x40UL                                       
01134 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT           0x00000000UL                                 
01135 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) 
01136 #define DMA_CHREQSTATUS_CH7REQSTATUS                    (0x1UL << 7)                                 
01137 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT             7                                            
01138 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK              0x80UL                                       
01139 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT           0x00000000UL                                 
01140 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) 
01142 /* Bit fields for DMA CHSREQSTATUS */
01143 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   
01144 #define _DMA_CHSREQSTATUS_MASK                          0x000000FFUL                                   
01145 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   
01146 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              
01147 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          
01148 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   
01149 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 
01150 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   
01151 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              
01152 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          
01153 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   
01154 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 
01155 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   
01156 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              
01157 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          
01158 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   
01159 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 
01160 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   
01161 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              
01162 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          
01163 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   
01164 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 
01165 #define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                   
01166 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                              
01167 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                         
01168 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                   
01169 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) 
01170 #define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                   
01171 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                              
01172 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                         
01173 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                   
01174 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) 
01175 #define DMA_CHSREQSTATUS_CH6SREQSTATUS                  (0x1UL << 6)                                   
01176 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT           6                                              
01177 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK            0x40UL                                         
01178 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT         0x00000000UL                                   
01179 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) 
01180 #define DMA_CHSREQSTATUS_CH7SREQSTATUS                  (0x1UL << 7)                                   
01181 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT           7                                              
01182 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK            0x80UL                                         
01183 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT         0x00000000UL                                   
01184 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) 
01186 /* Bit fields for DMA IF */
01187 #define _DMA_IF_RESETVALUE                              0x00000000UL                   
01188 #define _DMA_IF_MASK                                    0x800000FFUL                   
01189 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                   
01190 #define _DMA_IF_CH0DONE_SHIFT                           0                              
01191 #define _DMA_IF_CH0DONE_MASK                            0x1UL                          
01192 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   
01193 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) 
01194 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                   
01195 #define _DMA_IF_CH1DONE_SHIFT                           1                              
01196 #define _DMA_IF_CH1DONE_MASK                            0x2UL                          
01197 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   
01198 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) 
01199 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                   
01200 #define _DMA_IF_CH2DONE_SHIFT                           2                              
01201 #define _DMA_IF_CH2DONE_MASK                            0x4UL                          
01202 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   
01203 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) 
01204 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                   
01205 #define _DMA_IF_CH3DONE_SHIFT                           3                              
01206 #define _DMA_IF_CH3DONE_MASK                            0x8UL                          
01207 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   
01208 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) 
01209 #define DMA_IF_CH4DONE                                  (0x1UL << 4)                   
01210 #define _DMA_IF_CH4DONE_SHIFT                           4                              
01211 #define _DMA_IF_CH4DONE_MASK                            0x10UL                         
01212 #define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                   
01213 #define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4) 
01214 #define DMA_IF_CH5DONE                                  (0x1UL << 5)                   
01215 #define _DMA_IF_CH5DONE_SHIFT                           5                              
01216 #define _DMA_IF_CH5DONE_MASK                            0x20UL                         
01217 #define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                   
01218 #define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5) 
01219 #define DMA_IF_CH6DONE                                  (0x1UL << 6)                   
01220 #define _DMA_IF_CH6DONE_SHIFT                           6                              
01221 #define _DMA_IF_CH6DONE_MASK                            0x40UL                         
01222 #define _DMA_IF_CH6DONE_DEFAULT                         0x00000000UL                   
01223 #define DMA_IF_CH6DONE_DEFAULT                          (_DMA_IF_CH6DONE_DEFAULT << 6) 
01224 #define DMA_IF_CH7DONE                                  (0x1UL << 7)                   
01225 #define _DMA_IF_CH7DONE_SHIFT                           7                              
01226 #define _DMA_IF_CH7DONE_MASK                            0x80UL                         
01227 #define _DMA_IF_CH7DONE_DEFAULT                         0x00000000UL                   
01228 #define DMA_IF_CH7DONE_DEFAULT                          (_DMA_IF_CH7DONE_DEFAULT << 7) 
01229 #define DMA_IF_ERR                                      (0x1UL << 31)                  
01230 #define _DMA_IF_ERR_SHIFT                               31                             
01231 #define _DMA_IF_ERR_MASK                                0x80000000UL                   
01232 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   
01233 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    
01235 /* Bit fields for DMA IFS */
01236 #define _DMA_IFS_RESETVALUE                             0x00000000UL                    
01237 #define _DMA_IFS_MASK                                   0x800000FFUL                    
01238 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    
01239 #define _DMA_IFS_CH0DONE_SHIFT                          0                               
01240 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                           
01241 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    
01242 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) 
01243 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    
01244 #define _DMA_IFS_CH1DONE_SHIFT                          1                               
01245 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                           
01246 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    
01247 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) 
01248 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    
01249 #define _DMA_IFS_CH2DONE_SHIFT                          2                               
01250 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                           
01251 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    
01252 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) 
01253 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    
01254 #define _DMA_IFS_CH3DONE_SHIFT                          3                               
01255 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                           
01256 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    
01257 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) 
01258 #define DMA_IFS_CH4DONE                                 (0x1UL << 4)                    
01259 #define _DMA_IFS_CH4DONE_SHIFT                          4                               
01260 #define _DMA_IFS_CH4DONE_MASK                           0x10UL                          
01261 #define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                    
01262 #define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4) 
01263 #define DMA_IFS_CH5DONE                                 (0x1UL << 5)                    
01264 #define _DMA_IFS_CH5DONE_SHIFT                          5                               
01265 #define _DMA_IFS_CH5DONE_MASK                           0x20UL                          
01266 #define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                    
01267 #define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5) 
01268 #define DMA_IFS_CH6DONE                                 (0x1UL << 6)                    
01269 #define _DMA_IFS_CH6DONE_SHIFT                          6                               
01270 #define _DMA_IFS_CH6DONE_MASK                           0x40UL                          
01271 #define _DMA_IFS_CH6DONE_DEFAULT                        0x00000000UL                    
01272 #define DMA_IFS_CH6DONE_DEFAULT                         (_DMA_IFS_CH6DONE_DEFAULT << 6) 
01273 #define DMA_IFS_CH7DONE                                 (0x1UL << 7)                    
01274 #define _DMA_IFS_CH7DONE_SHIFT                          7                               
01275 #define _DMA_IFS_CH7DONE_MASK                           0x80UL                          
01276 #define _DMA_IFS_CH7DONE_DEFAULT                        0x00000000UL                    
01277 #define DMA_IFS_CH7DONE_DEFAULT                         (_DMA_IFS_CH7DONE_DEFAULT << 7) 
01278 #define DMA_IFS_ERR                                     (0x1UL << 31)                   
01279 #define _DMA_IFS_ERR_SHIFT                              31                              
01280 #define _DMA_IFS_ERR_MASK                               0x80000000UL                    
01281 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    
01282 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    
01284 /* Bit fields for DMA IFC */
01285 #define _DMA_IFC_RESETVALUE                             0x00000000UL                    
01286 #define _DMA_IFC_MASK                                   0x800000FFUL                    
01287 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    
01288 #define _DMA_IFC_CH0DONE_SHIFT                          0                               
01289 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                           
01290 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    
01291 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) 
01292 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    
01293 #define _DMA_IFC_CH1DONE_SHIFT                          1                               
01294 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                           
01295 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    
01296 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) 
01297 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    
01298 #define _DMA_IFC_CH2DONE_SHIFT                          2                               
01299 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                           
01300 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    
01301 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) 
01302 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    
01303 #define _DMA_IFC_CH3DONE_SHIFT                          3                               
01304 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                           
01305 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    
01306 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) 
01307 #define DMA_IFC_CH4DONE                                 (0x1UL << 4)                    
01308 #define _DMA_IFC_CH4DONE_SHIFT                          4                               
01309 #define _DMA_IFC_CH4DONE_MASK                           0x10UL                          
01310 #define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                    
01311 #define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4) 
01312 #define DMA_IFC_CH5DONE                                 (0x1UL << 5)                    
01313 #define _DMA_IFC_CH5DONE_SHIFT                          5                               
01314 #define _DMA_IFC_CH5DONE_MASK                           0x20UL                          
01315 #define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                    
01316 #define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5) 
01317 #define DMA_IFC_CH6DONE                                 (0x1UL << 6)                    
01318 #define _DMA_IFC_CH6DONE_SHIFT                          6                               
01319 #define _DMA_IFC_CH6DONE_MASK                           0x40UL                          
01320 #define _DMA_IFC_CH6DONE_DEFAULT                        0x00000000UL                    
01321 #define DMA_IFC_CH6DONE_DEFAULT                         (_DMA_IFC_CH6DONE_DEFAULT << 6) 
01322 #define DMA_IFC_CH7DONE                                 (0x1UL << 7)                    
01323 #define _DMA_IFC_CH7DONE_SHIFT                          7                               
01324 #define _DMA_IFC_CH7DONE_MASK                           0x80UL                          
01325 #define _DMA_IFC_CH7DONE_DEFAULT                        0x00000000UL                    
01326 #define DMA_IFC_CH7DONE_DEFAULT                         (_DMA_IFC_CH7DONE_DEFAULT << 7) 
01327 #define DMA_IFC_ERR                                     (0x1UL << 31)                   
01328 #define _DMA_IFC_ERR_SHIFT                              31                              
01329 #define _DMA_IFC_ERR_MASK                               0x80000000UL                    
01330 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    
01331 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    
01333 /* Bit fields for DMA IEN */
01334 #define _DMA_IEN_RESETVALUE                             0x00000000UL                    
01335 #define _DMA_IEN_MASK                                   0x800000FFUL                    
01336 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    
01337 #define _DMA_IEN_CH0DONE_SHIFT                          0                               
01338 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                           
01339 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    
01340 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) 
01341 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    
01342 #define _DMA_IEN_CH1DONE_SHIFT                          1                               
01343 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                           
01344 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    
01345 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) 
01346 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    
01347 #define _DMA_IEN_CH2DONE_SHIFT                          2                               
01348 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                           
01349 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    
01350 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) 
01351 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    
01352 #define _DMA_IEN_CH3DONE_SHIFT                          3                               
01353 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                           
01354 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    
01355 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) 
01356 #define DMA_IEN_CH4DONE                                 (0x1UL << 4)                    
01357 #define _DMA_IEN_CH4DONE_SHIFT                          4                               
01358 #define _DMA_IEN_CH4DONE_MASK                           0x10UL                          
01359 #define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                    
01360 #define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4) 
01361 #define DMA_IEN_CH5DONE                                 (0x1UL << 5)                    
01362 #define _DMA_IEN_CH5DONE_SHIFT                          5                               
01363 #define _DMA_IEN_CH5DONE_MASK                           0x20UL                          
01364 #define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                    
01365 #define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5) 
01366 #define DMA_IEN_CH6DONE                                 (0x1UL << 6)                    
01367 #define _DMA_IEN_CH6DONE_SHIFT                          6                               
01368 #define _DMA_IEN_CH6DONE_MASK                           0x40UL                          
01369 #define _DMA_IEN_CH6DONE_DEFAULT                        0x00000000UL                    
01370 #define DMA_IEN_CH6DONE_DEFAULT                         (_DMA_IEN_CH6DONE_DEFAULT << 6) 
01371 #define DMA_IEN_CH7DONE                                 (0x1UL << 7)                    
01372 #define _DMA_IEN_CH7DONE_SHIFT                          7                               
01373 #define _DMA_IEN_CH7DONE_MASK                           0x80UL                          
01374 #define _DMA_IEN_CH7DONE_DEFAULT                        0x00000000UL                    
01375 #define DMA_IEN_CH7DONE_DEFAULT                         (_DMA_IEN_CH7DONE_DEFAULT << 7) 
01376 #define DMA_IEN_ERR                                     (0x1UL << 31)                   
01377 #define _DMA_IEN_ERR_SHIFT                              31                              
01378 #define _DMA_IEN_ERR_MASK                               0x80000000UL                    
01379 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    
01380 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    
01382 /* Bit fields for DMA CH_CTRL */
01383 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                              
01384 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                              
01385 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                         
01386 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                     
01387 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE                  0x00000000UL                              
01388 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0                     0x00000000UL                              
01389 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                              
01390 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                              
01391 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                              
01392 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                              
01393 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                              
01394 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                              
01395 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                              
01396 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN                    0x00000001UL                              
01397 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1                     0x00000001UL                              
01398 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                              
01399 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                              
01400 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                              
01401 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                              
01402 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                              
01403 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                              
01404 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                              
01405 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                              
01406 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                              
01407 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                              
01408 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                              
01409 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                              
01410 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                              
01411 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE                   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)     
01412 #define DMA_CH_CTRL_SIGSEL_DAC0CH0                      (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)        
01413 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)  
01414 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)  
01415 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) 
01416 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)    
01417 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)     
01418 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)     
01419 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)       
01420 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN                     (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)       
01421 #define DMA_CH_CTRL_SIGSEL_DAC0CH1                      (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)        
01422 #define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)     
01423 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)     
01424 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)    
01425 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)       
01426 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)      
01427 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)      
01428 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)  
01429 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)  
01430 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) 
01431 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)      
01432 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)      
01433 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)      
01434 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)      
01435 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                        
01436 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                
01437 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                              
01438 #define _DMA_CH_CTRL_SOURCESEL_ADC0                     0x00000008UL                              
01439 #define _DMA_CH_CTRL_SOURCESEL_DAC0                     0x0000000AUL                              
01440 #define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                              
01441 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                              
01442 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                              
01443 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                              
01444 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                              
01445 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                              
01446 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                              
01447 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)       
01448 #define DMA_CH_CTRL_SOURCESEL_ADC0                      (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)       
01449 #define DMA_CH_CTRL_SOURCESEL_DAC0                      (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)       
01450 #define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)     
01451 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)     
01452 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)    
01453 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)       
01454 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)     
01455 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)     
01456 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)        
01462 /**************************************************************************/
01467 /* Bit fields for CMU CTRL */
01468 #define _CMU_CTRL_RESETVALUE                       0x000C262CUL                             
01469 #define _CMU_CTRL_MASK                             0x00FE3EEFUL                             
01470 #define _CMU_CTRL_HFXOMODE_SHIFT                   0                                        
01471 #define _CMU_CTRL_HFXOMODE_MASK                    0x3UL                                    
01472 #define _CMU_CTRL_HFXOMODE_DEFAULT                 0x00000000UL                             
01473 #define _CMU_CTRL_HFXOMODE_XTAL                    0x00000000UL                             
01474 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK               0x00000001UL                             
01475 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK               0x00000002UL                             
01476 #define CMU_CTRL_HFXOMODE_DEFAULT                  (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        
01477 #define CMU_CTRL_HFXOMODE_XTAL                     (_CMU_CTRL_HFXOMODE_XTAL << 0)           
01478 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      
01479 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      
01480 #define _CMU_CTRL_HFXOBOOST_SHIFT                  2                                        
01481 #define _CMU_CTRL_HFXOBOOST_MASK                   0xCUL                                    
01482 #define _CMU_CTRL_HFXOBOOST_50PCENT                0x00000000UL                             
01483 #define _CMU_CTRL_HFXOBOOST_70PCENT                0x00000001UL                             
01484 #define _CMU_CTRL_HFXOBOOST_80PCENT                0x00000002UL                             
01485 #define _CMU_CTRL_HFXOBOOST_DEFAULT                0x00000003UL                             
01486 #define _CMU_CTRL_HFXOBOOST_100PCENT               0x00000003UL                             
01487 #define CMU_CTRL_HFXOBOOST_50PCENT                 (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       
01488 #define CMU_CTRL_HFXOBOOST_70PCENT                 (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       
01489 #define CMU_CTRL_HFXOBOOST_80PCENT                 (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       
01490 #define CMU_CTRL_HFXOBOOST_DEFAULT                 (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       
01491 #define CMU_CTRL_HFXOBOOST_100PCENT                (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      
01492 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                 5                                        
01493 #define _CMU_CTRL_HFXOBUFCUR_MASK                  0x60UL                                   
01494 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT               0x00000001UL                             
01495 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      
01496 #define CMU_CTRL_HFXOGLITCHDETEN                   (0x1UL << 7)                             
01497 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT            7                                        
01498 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK             0x80UL                                   
01499 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT          0x00000000UL                             
01500 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 
01501 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                9                                        
01502 #define _CMU_CTRL_HFXOTIMEOUT_MASK                 0x600UL                                  
01503 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES              0x00000000UL                             
01504 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES            0x00000001UL                             
01505 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES             0x00000002UL                             
01506 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT              0x00000003UL                             
01507 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES            0x00000003UL                             
01508 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES               (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     
01509 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES             (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   
01510 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    
01511 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT               (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     
01512 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES             (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   
01513 #define _CMU_CTRL_LFXOMODE_SHIFT                   11                                       
01514 #define _CMU_CTRL_LFXOMODE_MASK                    0x1800UL                                 
01515 #define _CMU_CTRL_LFXOMODE_DEFAULT                 0x00000000UL                             
01516 #define _CMU_CTRL_LFXOMODE_XTAL                    0x00000000UL                             
01517 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK               0x00000001UL                             
01518 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK               0x00000002UL                             
01519 #define CMU_CTRL_LFXOMODE_DEFAULT                  (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       
01520 #define CMU_CTRL_LFXOMODE_XTAL                     (_CMU_CTRL_LFXOMODE_XTAL << 11)          
01521 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     
01522 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     
01523 #define CMU_CTRL_LFXOBOOST                         (0x1UL << 13)                            
01524 #define _CMU_CTRL_LFXOBOOST_SHIFT                  13                                       
01525 #define _CMU_CTRL_LFXOBOOST_MASK                   0x2000UL                                 
01526 #define _CMU_CTRL_LFXOBOOST_70PCENT                0x00000000UL                             
01527 #define _CMU_CTRL_LFXOBOOST_DEFAULT                0x00000001UL                             
01528 #define _CMU_CTRL_LFXOBOOST_100PCENT               0x00000001UL                             
01529 #define CMU_CTRL_LFXOBOOST_70PCENT                 (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      
01530 #define CMU_CTRL_LFXOBOOST_DEFAULT                 (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      
01531 #define CMU_CTRL_LFXOBOOST_100PCENT                (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     
01532 #define CMU_CTRL_LFXOBUFCUR                        (0x1UL << 17)                            
01533 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                 17                                       
01534 #define _CMU_CTRL_LFXOBUFCUR_MASK                  0x20000UL                                
01535 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT               0x00000000UL                             
01536 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     
01537 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                18                                       
01538 #define _CMU_CTRL_LFXOTIMEOUT_MASK                 0xC0000UL                                
01539 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES              0x00000000UL                             
01540 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES             0x00000001UL                             
01541 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES            0x00000002UL                             
01542 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT              0x00000003UL                             
01543 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES            0x00000003UL                             
01544 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES               (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    
01545 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   
01546 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES             (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  
01547 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT               (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    
01548 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES             (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  
01549 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                 20                                       
01550 #define _CMU_CTRL_CLKOUTSEL0_MASK                  0x700000UL                               
01551 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT               0x00000000UL                             
01552 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                 0x00000000UL                             
01553 #define _CMU_CTRL_CLKOUTSEL0_HFXO                  0x00000001UL                             
01554 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                0x00000002UL                             
01555 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                0x00000003UL                             
01556 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                0x00000004UL                             
01557 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16               0x00000005UL                             
01558 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                0x00000006UL                             
01559 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     
01560 #define CMU_CTRL_CLKOUTSEL0_HFRCO                  (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       
01561 #define CMU_CTRL_CLKOUTSEL0_HFXO                   (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        
01562 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      
01563 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      
01564 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      
01565 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     
01566 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                 (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      
01567 #define CMU_CTRL_CLKOUTSEL1                        (0x1UL << 23)                            
01568 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                 23                                       
01569 #define _CMU_CTRL_CLKOUTSEL1_MASK                  0x800000UL                               
01570 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT               0x00000000UL                             
01571 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                 0x00000000UL                             
01572 #define _CMU_CTRL_CLKOUTSEL1_LFXO                  0x00000001UL                             
01573 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     
01574 #define CMU_CTRL_CLKOUTSEL1_LFRCO                  (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       
01575 #define CMU_CTRL_CLKOUTSEL1_LFXO                   (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        
01577 /* Bit fields for CMU HFCORECLKDIV */
01578 #define _CMU_HFCORECLKDIV_RESETVALUE               0x00000000UL                                   
01579 #define _CMU_HFCORECLKDIV_MASK                     0x0000000FUL                                   
01580 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT       0                                              
01581 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK        0xFUL                                          
01582 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT     0x00000000UL                                   
01583 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK       0x00000000UL                                   
01584 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2      0x00000001UL                                   
01585 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4      0x00000002UL                                   
01586 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8      0x00000003UL                                   
01587 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16     0x00000004UL                                   
01588 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32     0x00000005UL                                   
01589 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64     0x00000006UL                                   
01590 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128    0x00000007UL                                   
01591 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256    0x00000008UL                                   
01592 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512    0x00000009UL                                   
01593 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)  
01594 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)    
01595 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)   
01596 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)   
01597 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)   
01598 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)  
01599 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)  
01600 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)  
01601 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) 
01602 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) 
01603 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) 
01605 /* Bit fields for CMU HFPERCLKDIV */
01606 #define _CMU_HFPERCLKDIV_RESETVALUE                0x00000100UL                                 
01607 #define _CMU_HFPERCLKDIV_MASK                      0x0000010FUL                                 
01608 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT         0                                            
01609 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK          0xFUL                                        
01610 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT       0x00000000UL                                 
01611 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK         0x00000000UL                                 
01612 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2        0x00000001UL                                 
01613 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4        0x00000002UL                                 
01614 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8        0x00000003UL                                 
01615 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16       0x00000004UL                                 
01616 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32       0x00000005UL                                 
01617 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64       0x00000006UL                                 
01618 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128      0x00000007UL                                 
01619 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256      0x00000008UL                                 
01620 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512      0x00000009UL                                 
01621 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
01622 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
01623 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
01624 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
01625 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
01626 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
01627 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
01628 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
01629 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
01630 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
01631 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
01632 #define CMU_HFPERCLKDIV_HFPERCLKEN                 (0x1UL << 8)                                 
01633 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT          8                                            
01634 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK           0x100UL                                      
01635 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT        0x00000001UL                                 
01636 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
01638 /* Bit fields for CMU HFRCOCTRL */
01639 #define _CMU_HFRCOCTRL_RESETVALUE                  0x00000380UL                           
01640 #define _CMU_HFRCOCTRL_MASK                        0x0001F7FFUL                           
01641 #define _CMU_HFRCOCTRL_TUNING_SHIFT                0                                      
01642 #define _CMU_HFRCOCTRL_TUNING_MASK                 0xFFUL                                 
01643 #define _CMU_HFRCOCTRL_TUNING_DEFAULT              0x00000080UL                           
01644 #define CMU_HFRCOCTRL_TUNING_DEFAULT               (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
01645 #define _CMU_HFRCOCTRL_BAND_SHIFT                  8                                      
01646 #define _CMU_HFRCOCTRL_BAND_MASK                   0x700UL                                
01647 #define _CMU_HFRCOCTRL_BAND_1MHZ                   0x00000000UL                           
01648 #define _CMU_HFRCOCTRL_BAND_7MHZ                   0x00000001UL                           
01649 #define _CMU_HFRCOCTRL_BAND_11MHZ                  0x00000002UL                           
01650 #define _CMU_HFRCOCTRL_BAND_DEFAULT                0x00000003UL                           
01651 #define _CMU_HFRCOCTRL_BAND_14MHZ                  0x00000003UL                           
01652 #define _CMU_HFRCOCTRL_BAND_21MHZ                  0x00000004UL                           
01653 #define _CMU_HFRCOCTRL_BAND_28MHZ                  0x00000005UL                           
01654 #define CMU_HFRCOCTRL_BAND_1MHZ                    (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
01655 #define CMU_HFRCOCTRL_BAND_7MHZ                    (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
01656 #define CMU_HFRCOCTRL_BAND_11MHZ                   (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
01657 #define CMU_HFRCOCTRL_BAND_DEFAULT                 (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
01658 #define CMU_HFRCOCTRL_BAND_14MHZ                   (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
01659 #define CMU_HFRCOCTRL_BAND_21MHZ                   (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
01660 #define CMU_HFRCOCTRL_BAND_28MHZ                   (_CMU_HFRCOCTRL_BAND_28MHZ << 8)       
01661 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT               12                                     
01662 #define _CMU_HFRCOCTRL_SUDELAY_MASK                0x1F000UL                              
01663 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT             0x00000000UL                           
01664 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT              (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
01666 /* Bit fields for CMU LFRCOCTRL */
01667 #define _CMU_LFRCOCTRL_RESETVALUE                  0x00000040UL                         
01668 #define _CMU_LFRCOCTRL_MASK                        0x0000007FUL                         
01669 #define _CMU_LFRCOCTRL_TUNING_SHIFT                0                                    
01670 #define _CMU_LFRCOCTRL_TUNING_MASK                 0x7FUL                               
01671 #define _CMU_LFRCOCTRL_TUNING_DEFAULT              0x00000040UL                         
01672 #define CMU_LFRCOCTRL_TUNING_DEFAULT               (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
01674 /* Bit fields for CMU AUXHFRCOCTRL */
01675 #define _CMU_AUXHFRCOCTRL_RESETVALUE               0x00000080UL                            
01676 #define _CMU_AUXHFRCOCTRL_MASK                     0x000000FFUL                            
01677 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT             0                                       
01678 #define _CMU_AUXHFRCOCTRL_TUNING_MASK              0xFFUL                                  
01679 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT           0x00000080UL                            
01680 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT            (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
01682 /* Bit fields for CMU CALCTRL */
01683 #define _CMU_CALCTRL_RESETVALUE                    0x00000000UL                       
01684 #define _CMU_CALCTRL_MASK                          0x00000007UL                       
01685 #define _CMU_CALCTRL_UPSEL_SHIFT                   0                                  
01686 #define _CMU_CALCTRL_UPSEL_MASK                    0x7UL                              
01687 #define _CMU_CALCTRL_UPSEL_DEFAULT                 0x00000000UL                       
01688 #define _CMU_CALCTRL_UPSEL_HFXO                    0x00000000UL                       
01689 #define _CMU_CALCTRL_UPSEL_LFXO                    0x00000001UL                       
01690 #define _CMU_CALCTRL_UPSEL_HFRCO                   0x00000002UL                       
01691 #define _CMU_CALCTRL_UPSEL_LFRCO                   0x00000003UL                       
01692 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                0x00000004UL                       
01693 #define CMU_CALCTRL_UPSEL_DEFAULT                  (_CMU_CALCTRL_UPSEL_DEFAULT << 0)  
01694 #define CMU_CALCTRL_UPSEL_HFXO                     (_CMU_CALCTRL_UPSEL_HFXO << 0)     
01695 #define CMU_CALCTRL_UPSEL_LFXO                     (_CMU_CALCTRL_UPSEL_LFXO << 0)     
01696 #define CMU_CALCTRL_UPSEL_HFRCO                    (_CMU_CALCTRL_UPSEL_HFRCO << 0)    
01697 #define CMU_CALCTRL_UPSEL_LFRCO                    (_CMU_CALCTRL_UPSEL_LFRCO << 0)    
01698 #define CMU_CALCTRL_UPSEL_AUXHFRCO                 (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) 
01700 /* Bit fields for CMU CALCNT */
01701 #define _CMU_CALCNT_RESETVALUE                     0x00000000UL                      
01702 #define _CMU_CALCNT_MASK                           0x000FFFFFUL                      
01703 #define _CMU_CALCNT_CALCNT_SHIFT                   0                                 
01704 #define _CMU_CALCNT_CALCNT_MASK                    0xFFFFFUL                         
01705 #define _CMU_CALCNT_CALCNT_DEFAULT                 0x00000000UL                      
01706 #define CMU_CALCNT_CALCNT_DEFAULT                  (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
01708 /* Bit fields for CMU OSCENCMD */
01709 #define _CMU_OSCENCMD_RESETVALUE                   0x00000000UL                             
01710 #define _CMU_OSCENCMD_MASK                         0x000003FFUL                             
01711 #define CMU_OSCENCMD_HFRCOEN                       (0x1UL << 0)                             
01712 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                0                                        
01713 #define _CMU_OSCENCMD_HFRCOEN_MASK                 0x1UL                                    
01714 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT              0x00000000UL                             
01715 #define CMU_OSCENCMD_HFRCOEN_DEFAULT               (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
01716 #define CMU_OSCENCMD_HFRCODIS                      (0x1UL << 1)                             
01717 #define _CMU_OSCENCMD_HFRCODIS_SHIFT               1                                        
01718 #define _CMU_OSCENCMD_HFRCODIS_MASK                0x2UL                                    
01719 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT             0x00000000UL                             
01720 #define CMU_OSCENCMD_HFRCODIS_DEFAULT              (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
01721 #define CMU_OSCENCMD_HFXOEN                        (0x1UL << 2)                             
01722 #define _CMU_OSCENCMD_HFXOEN_SHIFT                 2                                        
01723 #define _CMU_OSCENCMD_HFXOEN_MASK                  0x4UL                                    
01724 #define _CMU_OSCENCMD_HFXOEN_DEFAULT               0x00000000UL                             
01725 #define CMU_OSCENCMD_HFXOEN_DEFAULT                (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
01726 #define CMU_OSCENCMD_HFXODIS                       (0x1UL << 3)                             
01727 #define _CMU_OSCENCMD_HFXODIS_SHIFT                3                                        
01728 #define _CMU_OSCENCMD_HFXODIS_MASK                 0x8UL                                    
01729 #define _CMU_OSCENCMD_HFXODIS_DEFAULT              0x00000000UL                             
01730 #define CMU_OSCENCMD_HFXODIS_DEFAULT               (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
01731 #define CMU_OSCENCMD_AUXHFRCOEN                    (0x1UL << 4)                             
01732 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT             4                                        
01733 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK              0x10UL                                   
01734 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT           0x00000000UL                             
01735 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
01736 #define CMU_OSCENCMD_AUXHFRCODIS                   (0x1UL << 5)                             
01737 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT            5                                        
01738 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK             0x20UL                                   
01739 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT          0x00000000UL                             
01740 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
01741 #define CMU_OSCENCMD_LFRCOEN                       (0x1UL << 6)                             
01742 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                6                                        
01743 #define _CMU_OSCENCMD_LFRCOEN_MASK                 0x40UL                                   
01744 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT              0x00000000UL                             
01745 #define CMU_OSCENCMD_LFRCOEN_DEFAULT               (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
01746 #define CMU_OSCENCMD_LFRCODIS                      (0x1UL << 7)                             
01747 #define _CMU_OSCENCMD_LFRCODIS_SHIFT               7                                        
01748 #define _CMU_OSCENCMD_LFRCODIS_MASK                0x80UL                                   
01749 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT             0x00000000UL                             
01750 #define CMU_OSCENCMD_LFRCODIS_DEFAULT              (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
01751 #define CMU_OSCENCMD_LFXOEN                        (0x1UL << 8)                             
01752 #define _CMU_OSCENCMD_LFXOEN_SHIFT                 8                                        
01753 #define _CMU_OSCENCMD_LFXOEN_MASK                  0x100UL                                  
01754 #define _CMU_OSCENCMD_LFXOEN_DEFAULT               0x00000000UL                             
01755 #define CMU_OSCENCMD_LFXOEN_DEFAULT                (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
01756 #define CMU_OSCENCMD_LFXODIS                       (0x1UL << 9)                             
01757 #define _CMU_OSCENCMD_LFXODIS_SHIFT                9                                        
01758 #define _CMU_OSCENCMD_LFXODIS_MASK                 0x200UL                                  
01759 #define _CMU_OSCENCMD_LFXODIS_DEFAULT              0x00000000UL                             
01760 #define CMU_OSCENCMD_LFXODIS_DEFAULT               (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
01762 /* Bit fields for CMU CMD */
01763 #define _CMU_CMD_RESETVALUE                        0x00000000UL                     
01764 #define _CMU_CMD_MASK                              0x0000000FUL                     
01765 #define _CMU_CMD_HFCLKSEL_SHIFT                    0                                
01766 #define _CMU_CMD_HFCLKSEL_MASK                     0x7UL                            
01767 #define _CMU_CMD_HFCLKSEL_DEFAULT                  0x00000000UL                     
01768 #define _CMU_CMD_HFCLKSEL_HFRCO                    0x00000001UL                     
01769 #define _CMU_CMD_HFCLKSEL_HFXO                     0x00000002UL                     
01770 #define _CMU_CMD_HFCLKSEL_LFRCO                    0x00000003UL                     
01771 #define _CMU_CMD_HFCLKSEL_LFXO                     0x00000004UL                     
01772 #define CMU_CMD_HFCLKSEL_DEFAULT                   (_CMU_CMD_HFCLKSEL_DEFAULT << 0) 
01773 #define CMU_CMD_HFCLKSEL_HFRCO                     (_CMU_CMD_HFCLKSEL_HFRCO << 0)   
01774 #define CMU_CMD_HFCLKSEL_HFXO                      (_CMU_CMD_HFCLKSEL_HFXO << 0)    
01775 #define CMU_CMD_HFCLKSEL_LFRCO                     (_CMU_CMD_HFCLKSEL_LFRCO << 0)   
01776 #define CMU_CMD_HFCLKSEL_LFXO                      (_CMU_CMD_HFCLKSEL_LFXO << 0)    
01777 #define CMU_CMD_CALSTART                           (0x1UL << 3)                     
01778 #define _CMU_CMD_CALSTART_SHIFT                    3                                
01779 #define _CMU_CMD_CALSTART_MASK                     0x8UL                            
01780 #define _CMU_CMD_CALSTART_DEFAULT                  0x00000000UL                     
01781 #define CMU_CMD_CALSTART_DEFAULT                   (_CMU_CMD_CALSTART_DEFAULT << 3) 
01783 /* Bit fields for CMU LFCLKSEL */
01784 #define _CMU_LFCLKSEL_RESETVALUE                   0x00000005UL                             
01785 #define _CMU_LFCLKSEL_MASK                         0x0000000FUL                             
01786 #define _CMU_LFCLKSEL_LFA_SHIFT                    0                                        
01787 #define _CMU_LFCLKSEL_LFA_MASK                     0x3UL                                    
01788 #define _CMU_LFCLKSEL_LFA_DISABLED                 0x00000000UL                             
01789 #define _CMU_LFCLKSEL_LFA_DEFAULT                  0x00000001UL                             
01790 #define _CMU_LFCLKSEL_LFA_LFRCO                    0x00000001UL                             
01791 #define _CMU_LFCLKSEL_LFA_LFXO                     0x00000002UL                             
01792 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2          0x00000003UL                             
01793 #define CMU_LFCLKSEL_LFA_DISABLED                  (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
01794 #define CMU_LFCLKSEL_LFA_DEFAULT                   (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
01795 #define CMU_LFCLKSEL_LFA_LFRCO                     (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
01796 #define CMU_LFCLKSEL_LFA_LFXO                      (_CMU_LFCLKSEL_LFA_LFXO << 0)            
01797 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
01798 #define _CMU_LFCLKSEL_LFB_SHIFT                    2                                        
01799 #define _CMU_LFCLKSEL_LFB_MASK                     0xCUL                                    
01800 #define _CMU_LFCLKSEL_LFB_DISABLED                 0x00000000UL                             
01801 #define _CMU_LFCLKSEL_LFB_DEFAULT                  0x00000001UL                             
01802 #define _CMU_LFCLKSEL_LFB_LFRCO                    0x00000001UL                             
01803 #define _CMU_LFCLKSEL_LFB_LFXO                     0x00000002UL                             
01804 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2          0x00000003UL                             
01805 #define CMU_LFCLKSEL_LFB_DISABLED                  (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
01806 #define CMU_LFCLKSEL_LFB_DEFAULT                   (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
01807 #define CMU_LFCLKSEL_LFB_LFRCO                     (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
01808 #define CMU_LFCLKSEL_LFB_LFXO                      (_CMU_LFCLKSEL_LFB_LFXO << 2)            
01809 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
01811 /* Bit fields for CMU STATUS */
01812 #define _CMU_STATUS_RESETVALUE                     0x00000403UL                           
01813 #define _CMU_STATUS_MASK                           0x00007FFFUL                           
01814 #define CMU_STATUS_HFRCOENS                        (0x1UL << 0)                           
01815 #define _CMU_STATUS_HFRCOENS_SHIFT                 0                                      
01816 #define _CMU_STATUS_HFRCOENS_MASK                  0x1UL                                  
01817 #define _CMU_STATUS_HFRCOENS_DEFAULT               0x00000001UL                           
01818 #define CMU_STATUS_HFRCOENS_DEFAULT                (_CMU_STATUS_HFRCOENS_DEFAULT << 0)    
01819 #define CMU_STATUS_HFRCORDY                        (0x1UL << 1)                           
01820 #define _CMU_STATUS_HFRCORDY_SHIFT                 1                                      
01821 #define _CMU_STATUS_HFRCORDY_MASK                  0x2UL                                  
01822 #define _CMU_STATUS_HFRCORDY_DEFAULT               0x00000001UL                           
01823 #define CMU_STATUS_HFRCORDY_DEFAULT                (_CMU_STATUS_HFRCORDY_DEFAULT << 1)    
01824 #define CMU_STATUS_HFXOENS                         (0x1UL << 2)                           
01825 #define _CMU_STATUS_HFXOENS_SHIFT                  2                                      
01826 #define _CMU_STATUS_HFXOENS_MASK                   0x4UL                                  
01827 #define _CMU_STATUS_HFXOENS_DEFAULT                0x00000000UL                           
01828 #define CMU_STATUS_HFXOENS_DEFAULT                 (_CMU_STATUS_HFXOENS_DEFAULT << 2)     
01829 #define CMU_STATUS_HFXORDY                         (0x1UL << 3)                           
01830 #define _CMU_STATUS_HFXORDY_SHIFT                  3                                      
01831 #define _CMU_STATUS_HFXORDY_MASK                   0x8UL                                  
01832 #define _CMU_STATUS_HFXORDY_DEFAULT                0x00000000UL                           
01833 #define CMU_STATUS_HFXORDY_DEFAULT                 (_CMU_STATUS_HFXORDY_DEFAULT << 3)     
01834 #define CMU_STATUS_AUXHFRCOENS                     (0x1UL << 4)                           
01835 #define _CMU_STATUS_AUXHFRCOENS_SHIFT              4                                      
01836 #define _CMU_STATUS_AUXHFRCOENS_MASK               0x10UL                                 
01837 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT            0x00000000UL                           
01838 #define CMU_STATUS_AUXHFRCOENS_DEFAULT             (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) 
01839 #define CMU_STATUS_AUXHFRCORDY                     (0x1UL << 5)                           
01840 #define _CMU_STATUS_AUXHFRCORDY_SHIFT              5                                      
01841 #define _CMU_STATUS_AUXHFRCORDY_MASK               0x20UL                                 
01842 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT            0x00000000UL                           
01843 #define CMU_STATUS_AUXHFRCORDY_DEFAULT             (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) 
01844 #define CMU_STATUS_LFRCOENS                        (0x1UL << 6)                           
01845 #define _CMU_STATUS_LFRCOENS_SHIFT                 6                                      
01846 #define _CMU_STATUS_LFRCOENS_MASK                  0x40UL                                 
01847 #define _CMU_STATUS_LFRCOENS_DEFAULT               0x00000000UL                           
01848 #define CMU_STATUS_LFRCOENS_DEFAULT                (_CMU_STATUS_LFRCOENS_DEFAULT << 6)    
01849 #define CMU_STATUS_LFRCORDY                        (0x1UL << 7)                           
01850 #define _CMU_STATUS_LFRCORDY_SHIFT                 7                                      
01851 #define _CMU_STATUS_LFRCORDY_MASK                  0x80UL                                 
01852 #define _CMU_STATUS_LFRCORDY_DEFAULT               0x00000000UL                           
01853 #define CMU_STATUS_LFRCORDY_DEFAULT                (_CMU_STATUS_LFRCORDY_DEFAULT << 7)    
01854 #define CMU_STATUS_LFXOENS                         (0x1UL << 8)                           
01855 #define _CMU_STATUS_LFXOENS_SHIFT                  8                                      
01856 #define _CMU_STATUS_LFXOENS_MASK                   0x100UL                                
01857 #define _CMU_STATUS_LFXOENS_DEFAULT                0x00000000UL                           
01858 #define CMU_STATUS_LFXOENS_DEFAULT                 (_CMU_STATUS_LFXOENS_DEFAULT << 8)     
01859 #define CMU_STATUS_LFXORDY                         (0x1UL << 9)                           
01860 #define _CMU_STATUS_LFXORDY_SHIFT                  9                                      
01861 #define _CMU_STATUS_LFXORDY_MASK                   0x200UL                                
01862 #define _CMU_STATUS_LFXORDY_DEFAULT                0x00000000UL                           
01863 #define CMU_STATUS_LFXORDY_DEFAULT                 (_CMU_STATUS_LFXORDY_DEFAULT << 9)     
01864 #define CMU_STATUS_HFRCOSEL                        (0x1UL << 10)                          
01865 #define _CMU_STATUS_HFRCOSEL_SHIFT                 10                                     
01866 #define _CMU_STATUS_HFRCOSEL_MASK                  0x400UL                                
01867 #define _CMU_STATUS_HFRCOSEL_DEFAULT               0x00000001UL                           
01868 #define CMU_STATUS_HFRCOSEL_DEFAULT                (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)   
01869 #define CMU_STATUS_HFXOSEL                         (0x1UL << 11)                          
01870 #define _CMU_STATUS_HFXOSEL_SHIFT                  11                                     
01871 #define _CMU_STATUS_HFXOSEL_MASK                   0x800UL                                
01872 #define _CMU_STATUS_HFXOSEL_DEFAULT                0x00000000UL                           
01873 #define CMU_STATUS_HFXOSEL_DEFAULT                 (_CMU_STATUS_HFXOSEL_DEFAULT << 11)    
01874 #define CMU_STATUS_LFRCOSEL                        (0x1UL << 12)                          
01875 #define _CMU_STATUS_LFRCOSEL_SHIFT                 12                                     
01876 #define _CMU_STATUS_LFRCOSEL_MASK                  0x1000UL                               
01877 #define _CMU_STATUS_LFRCOSEL_DEFAULT               0x00000000UL                           
01878 #define CMU_STATUS_LFRCOSEL_DEFAULT                (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)   
01879 #define CMU_STATUS_LFXOSEL                         (0x1UL << 13)                          
01880 #define _CMU_STATUS_LFXOSEL_SHIFT                  13                                     
01881 #define _CMU_STATUS_LFXOSEL_MASK                   0x2000UL                               
01882 #define _CMU_STATUS_LFXOSEL_DEFAULT                0x00000000UL                           
01883 #define CMU_STATUS_LFXOSEL_DEFAULT                 (_CMU_STATUS_LFXOSEL_DEFAULT << 13)    
01884 #define CMU_STATUS_CALBSY                          (0x1UL << 14)                          
01885 #define _CMU_STATUS_CALBSY_SHIFT                   14                                     
01886 #define _CMU_STATUS_CALBSY_MASK                    0x4000UL                               
01887 #define _CMU_STATUS_CALBSY_DEFAULT                 0x00000000UL                           
01888 #define CMU_STATUS_CALBSY_DEFAULT                  (_CMU_STATUS_CALBSY_DEFAULT << 14)     
01890 /* Bit fields for CMU IF */
01891 #define _CMU_IF_RESETVALUE                         0x00000001UL                       
01892 #define _CMU_IF_MASK                               0x0000003FUL                       
01893 #define CMU_IF_HFRCORDY                            (0x1UL << 0)                       
01894 #define _CMU_IF_HFRCORDY_SHIFT                     0                                  
01895 #define _CMU_IF_HFRCORDY_MASK                      0x1UL                              
01896 #define _CMU_IF_HFRCORDY_DEFAULT                   0x00000001UL                       
01897 #define CMU_IF_HFRCORDY_DEFAULT                    (_CMU_IF_HFRCORDY_DEFAULT << 0)    
01898 #define CMU_IF_HFXORDY                             (0x1UL << 1)                       
01899 #define _CMU_IF_HFXORDY_SHIFT                      1                                  
01900 #define _CMU_IF_HFXORDY_MASK                       0x2UL                              
01901 #define _CMU_IF_HFXORDY_DEFAULT                    0x00000000UL                       
01902 #define CMU_IF_HFXORDY_DEFAULT                     (_CMU_IF_HFXORDY_DEFAULT << 1)     
01903 #define CMU_IF_LFRCORDY                            (0x1UL << 2)                       
01904 #define _CMU_IF_LFRCORDY_SHIFT                     2                                  
01905 #define _CMU_IF_LFRCORDY_MASK                      0x4UL                              
01906 #define _CMU_IF_LFRCORDY_DEFAULT                   0x00000000UL                       
01907 #define CMU_IF_LFRCORDY_DEFAULT                    (_CMU_IF_LFRCORDY_DEFAULT << 2)    
01908 #define CMU_IF_LFXORDY                             (0x1UL << 3)                       
01909 #define _CMU_IF_LFXORDY_SHIFT                      3                                  
01910 #define _CMU_IF_LFXORDY_MASK                       0x8UL                              
01911 #define _CMU_IF_LFXORDY_DEFAULT                    0x00000000UL                       
01912 #define CMU_IF_LFXORDY_DEFAULT                     (_CMU_IF_LFXORDY_DEFAULT << 3)     
01913 #define CMU_IF_AUXHFRCORDY                         (0x1UL << 4)                       
01914 #define _CMU_IF_AUXHFRCORDY_SHIFT                  4                                  
01915 #define _CMU_IF_AUXHFRCORDY_MASK                   0x10UL                             
01916 #define _CMU_IF_AUXHFRCORDY_DEFAULT                0x00000000UL                       
01917 #define CMU_IF_AUXHFRCORDY_DEFAULT                 (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
01918 #define CMU_IF_CALRDY                              (0x1UL << 5)                       
01919 #define _CMU_IF_CALRDY_SHIFT                       5                                  
01920 #define _CMU_IF_CALRDY_MASK                        0x20UL                             
01921 #define _CMU_IF_CALRDY_DEFAULT                     0x00000000UL                       
01922 #define CMU_IF_CALRDY_DEFAULT                      (_CMU_IF_CALRDY_DEFAULT << 5)      
01924 /* Bit fields for CMU IFS */
01925 #define _CMU_IFS_RESETVALUE                        0x00000000UL                        
01926 #define _CMU_IFS_MASK                              0x0000003FUL                        
01927 #define CMU_IFS_HFRCORDY                           (0x1UL << 0)                        
01928 #define _CMU_IFS_HFRCORDY_SHIFT                    0                                   
01929 #define _CMU_IFS_HFRCORDY_MASK                     0x1UL                               
01930 #define _CMU_IFS_HFRCORDY_DEFAULT                  0x00000000UL                        
01931 #define CMU_IFS_HFRCORDY_DEFAULT                   (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
01932 #define CMU_IFS_HFXORDY                            (0x1UL << 1)                        
01933 #define _CMU_IFS_HFXORDY_SHIFT                     1                                   
01934 #define _CMU_IFS_HFXORDY_MASK                      0x2UL                               
01935 #define _CMU_IFS_HFXORDY_DEFAULT                   0x00000000UL                        
01936 #define CMU_IFS_HFXORDY_DEFAULT                    (_CMU_IFS_HFXORDY_DEFAULT << 1)     
01937 #define CMU_IFS_LFRCORDY                           (0x1UL << 2)                        
01938 #define _CMU_IFS_LFRCORDY_SHIFT                    2                                   
01939 #define _CMU_IFS_LFRCORDY_MASK                     0x4UL                               
01940 #define _CMU_IFS_LFRCORDY_DEFAULT                  0x00000000UL                        
01941 #define CMU_IFS_LFRCORDY_DEFAULT                   (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
01942 #define CMU_IFS_LFXORDY                            (0x1UL << 3)                        
01943 #define _CMU_IFS_LFXORDY_SHIFT                     3                                   
01944 #define _CMU_IFS_LFXORDY_MASK                      0x8UL                               
01945 #define _CMU_IFS_LFXORDY_DEFAULT                   0x00000000UL                        
01946 #define CMU_IFS_LFXORDY_DEFAULT                    (_CMU_IFS_LFXORDY_DEFAULT << 3)     
01947 #define CMU_IFS_AUXHFRCORDY                        (0x1UL << 4)                        
01948 #define _CMU_IFS_AUXHFRCORDY_SHIFT                 4                                   
01949 #define _CMU_IFS_AUXHFRCORDY_MASK                  0x10UL                              
01950 #define _CMU_IFS_AUXHFRCORDY_DEFAULT               0x00000000UL                        
01951 #define CMU_IFS_AUXHFRCORDY_DEFAULT                (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
01952 #define CMU_IFS_CALRDY                             (0x1UL << 5)                        
01953 #define _CMU_IFS_CALRDY_SHIFT                      5                                   
01954 #define _CMU_IFS_CALRDY_MASK                       0x20UL                              
01955 #define _CMU_IFS_CALRDY_DEFAULT                    0x00000000UL                        
01956 #define CMU_IFS_CALRDY_DEFAULT                     (_CMU_IFS_CALRDY_DEFAULT << 5)      
01958 /* Bit fields for CMU IFC */
01959 #define _CMU_IFC_RESETVALUE                        0x00000000UL                        
01960 #define _CMU_IFC_MASK                              0x0000003FUL                        
01961 #define CMU_IFC_HFRCORDY                           (0x1UL << 0)                        
01962 #define _CMU_IFC_HFRCORDY_SHIFT                    0                                   
01963 #define _CMU_IFC_HFRCORDY_MASK                     0x1UL                               
01964 #define _CMU_IFC_HFRCORDY_DEFAULT                  0x00000000UL                        
01965 #define CMU_IFC_HFRCORDY_DEFAULT                   (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
01966 #define CMU_IFC_HFXORDY                            (0x1UL << 1)                        
01967 #define _CMU_IFC_HFXORDY_SHIFT                     1                                   
01968 #define _CMU_IFC_HFXORDY_MASK                      0x2UL                               
01969 #define _CMU_IFC_HFXORDY_DEFAULT                   0x00000000UL                        
01970 #define CMU_IFC_HFXORDY_DEFAULT                    (_CMU_IFC_HFXORDY_DEFAULT << 1)     
01971 #define CMU_IFC_LFRCORDY                           (0x1UL << 2)                        
01972 #define _CMU_IFC_LFRCORDY_SHIFT                    2                                   
01973 #define _CMU_IFC_LFRCORDY_MASK                     0x4UL                               
01974 #define _CMU_IFC_LFRCORDY_DEFAULT                  0x00000000UL                        
01975 #define CMU_IFC_LFRCORDY_DEFAULT                   (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
01976 #define CMU_IFC_LFXORDY                            (0x1UL << 3)                        
01977 #define _CMU_IFC_LFXORDY_SHIFT                     3                                   
01978 #define _CMU_IFC_LFXORDY_MASK                      0x8UL                               
01979 #define _CMU_IFC_LFXORDY_DEFAULT                   0x00000000UL                        
01980 #define CMU_IFC_LFXORDY_DEFAULT                    (_CMU_IFC_LFXORDY_DEFAULT << 3)     
01981 #define CMU_IFC_AUXHFRCORDY                        (0x1UL << 4)                        
01982 #define _CMU_IFC_AUXHFRCORDY_SHIFT                 4                                   
01983 #define _CMU_IFC_AUXHFRCORDY_MASK                  0x10UL                              
01984 #define _CMU_IFC_AUXHFRCORDY_DEFAULT               0x00000000UL                        
01985 #define CMU_IFC_AUXHFRCORDY_DEFAULT                (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
01986 #define CMU_IFC_CALRDY                             (0x1UL << 5)                        
01987 #define _CMU_IFC_CALRDY_SHIFT                      5                                   
01988 #define _CMU_IFC_CALRDY_MASK                       0x20UL                              
01989 #define _CMU_IFC_CALRDY_DEFAULT                    0x00000000UL                        
01990 #define CMU_IFC_CALRDY_DEFAULT                     (_CMU_IFC_CALRDY_DEFAULT << 5)      
01992 /* Bit fields for CMU IEN */
01993 #define _CMU_IEN_RESETVALUE                        0x00000000UL                        
01994 #define _CMU_IEN_MASK                              0x0000003FUL                        
01995 #define CMU_IEN_HFRCORDY                           (0x1UL << 0)                        
01996 #define _CMU_IEN_HFRCORDY_SHIFT                    0                                   
01997 #define _CMU_IEN_HFRCORDY_MASK                     0x1UL                               
01998 #define _CMU_IEN_HFRCORDY_DEFAULT                  0x00000000UL                        
01999 #define CMU_IEN_HFRCORDY_DEFAULT                   (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
02000 #define CMU_IEN_HFXORDY                            (0x1UL << 1)                        
02001 #define _CMU_IEN_HFXORDY_SHIFT                     1                                   
02002 #define _CMU_IEN_HFXORDY_MASK                      0x2UL                               
02003 #define _CMU_IEN_HFXORDY_DEFAULT                   0x00000000UL                        
02004 #define CMU_IEN_HFXORDY_DEFAULT                    (_CMU_IEN_HFXORDY_DEFAULT << 1)     
02005 #define CMU_IEN_LFRCORDY                           (0x1UL << 2)                        
02006 #define _CMU_IEN_LFRCORDY_SHIFT                    2                                   
02007 #define _CMU_IEN_LFRCORDY_MASK                     0x4UL                               
02008 #define _CMU_IEN_LFRCORDY_DEFAULT                  0x00000000UL                        
02009 #define CMU_IEN_LFRCORDY_DEFAULT                   (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
02010 #define CMU_IEN_LFXORDY                            (0x1UL << 3)                        
02011 #define _CMU_IEN_LFXORDY_SHIFT                     3                                   
02012 #define _CMU_IEN_LFXORDY_MASK                      0x8UL                               
02013 #define _CMU_IEN_LFXORDY_DEFAULT                   0x00000000UL                        
02014 #define CMU_IEN_LFXORDY_DEFAULT                    (_CMU_IEN_LFXORDY_DEFAULT << 3)     
02015 #define CMU_IEN_AUXHFRCORDY                        (0x1UL << 4)                        
02016 #define _CMU_IEN_AUXHFRCORDY_SHIFT                 4                                   
02017 #define _CMU_IEN_AUXHFRCORDY_MASK                  0x10UL                              
02018 #define _CMU_IEN_AUXHFRCORDY_DEFAULT               0x00000000UL                        
02019 #define CMU_IEN_AUXHFRCORDY_DEFAULT                (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
02020 #define CMU_IEN_CALRDY                             (0x1UL << 5)                        
02021 #define _CMU_IEN_CALRDY_SHIFT                      5                                   
02022 #define _CMU_IEN_CALRDY_MASK                       0x20UL                              
02023 #define _CMU_IEN_CALRDY_DEFAULT                    0x00000000UL                        
02024 #define CMU_IEN_CALRDY_DEFAULT                     (_CMU_IEN_CALRDY_DEFAULT << 5)      
02026 /* Bit fields for CMU HFCORECLKEN0 */
02027 #define _CMU_HFCORECLKEN0_RESETVALUE               0x00000000UL                         
02028 #define _CMU_HFCORECLKEN0_MASK                     0x00000006UL                         
02029 #define CMU_HFCORECLKEN0_DMA                       (0x1UL << 1)                         
02030 #define _CMU_HFCORECLKEN0_DMA_SHIFT                1                                    
02031 #define _CMU_HFCORECLKEN0_DMA_MASK                 0x2UL                                
02032 #define _CMU_HFCORECLKEN0_DMA_DEFAULT              0x00000000UL                         
02033 #define CMU_HFCORECLKEN0_DMA_DEFAULT               (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) 
02034 #define CMU_HFCORECLKEN0_LE                        (0x1UL << 2)                         
02035 #define _CMU_HFCORECLKEN0_LE_SHIFT                 2                                    
02036 #define _CMU_HFCORECLKEN0_LE_MASK                  0x4UL                                
02037 #define _CMU_HFCORECLKEN0_LE_DEFAULT               0x00000000UL                         
02038 #define CMU_HFCORECLKEN0_LE_DEFAULT                (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)  
02040 /* Bit fields for CMU HFPERCLKEN0 */
02041 #define _CMU_HFPERCLKEN0_RESETVALUE                0x00000000UL                           
02042 #define _CMU_HFPERCLKEN0_MASK                      0x0000FDB3UL                           
02043 #define CMU_HFPERCLKEN0_USART0                     (0x1UL << 0)                           
02044 #define _CMU_HFPERCLKEN0_USART0_SHIFT              0                                      
02045 #define _CMU_HFPERCLKEN0_USART0_MASK               0x1UL                                  
02046 #define _CMU_HFPERCLKEN0_USART0_DEFAULT            0x00000000UL                           
02047 #define CMU_HFPERCLKEN0_USART0_DEFAULT             (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) 
02048 #define CMU_HFPERCLKEN0_USART1                     (0x1UL << 1)                           
02049 #define _CMU_HFPERCLKEN0_USART1_SHIFT              1                                      
02050 #define _CMU_HFPERCLKEN0_USART1_MASK               0x2UL                                  
02051 #define _CMU_HFPERCLKEN0_USART1_DEFAULT            0x00000000UL                           
02052 #define CMU_HFPERCLKEN0_USART1_DEFAULT             (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) 
02053 #define CMU_HFPERCLKEN0_TIMER0                     (0x1UL << 4)                           
02054 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT              4                                      
02055 #define _CMU_HFPERCLKEN0_TIMER0_MASK               0x10UL                                 
02056 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT            0x00000000UL                           
02057 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT             (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4) 
02058 #define CMU_HFPERCLKEN0_TIMER1                     (0x1UL << 5)                           
02059 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT              5                                      
02060 #define _CMU_HFPERCLKEN0_TIMER1_MASK               0x20UL                                 
02061 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT            0x00000000UL                           
02062 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT             (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5) 
02063 #define CMU_HFPERCLKEN0_ACMP0                      (0x1UL << 7)                           
02064 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT               7                                      
02065 #define _CMU_HFPERCLKEN0_ACMP0_MASK                0x80UL                                 
02066 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT             0x00000000UL                           
02067 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT              (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)  
02068 #define CMU_HFPERCLKEN0_ACMP1                      (0x1UL << 8)                           
02069 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT               8                                      
02070 #define _CMU_HFPERCLKEN0_ACMP1_MASK                0x100UL                                
02071 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT             0x00000000UL                           
02072 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT              (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)  
02073 #define CMU_HFPERCLKEN0_PRS                        (0x1UL << 10)                          
02074 #define _CMU_HFPERCLKEN0_PRS_SHIFT                 10                                     
02075 #define _CMU_HFPERCLKEN0_PRS_MASK                  0x400UL                                
02076 #define _CMU_HFPERCLKEN0_PRS_DEFAULT               0x00000000UL                           
02077 #define CMU_HFPERCLKEN0_PRS_DEFAULT                (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)   
02078 #define CMU_HFPERCLKEN0_DAC0                       (0x1UL << 11)                          
02079 #define _CMU_HFPERCLKEN0_DAC0_SHIFT                11                                     
02080 #define _CMU_HFPERCLKEN0_DAC0_MASK                 0x800UL                                
02081 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT              0x00000000UL                           
02082 #define CMU_HFPERCLKEN0_DAC0_DEFAULT               (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)  
02083 #define CMU_HFPERCLKEN0_GPIO                       (0x1UL << 12)                          
02084 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                12                                     
02085 #define _CMU_HFPERCLKEN0_GPIO_MASK                 0x1000UL                               
02086 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT              0x00000000UL                           
02087 #define CMU_HFPERCLKEN0_GPIO_DEFAULT               (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)  
02088 #define CMU_HFPERCLKEN0_VCMP                       (0x1UL << 13)                          
02089 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                13                                     
02090 #define _CMU_HFPERCLKEN0_VCMP_MASK                 0x2000UL                               
02091 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT              0x00000000UL                           
02092 #define CMU_HFPERCLKEN0_VCMP_DEFAULT               (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)  
02093 #define CMU_HFPERCLKEN0_ADC0                       (0x1UL << 14)                          
02094 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                14                                     
02095 #define _CMU_HFPERCLKEN0_ADC0_MASK                 0x4000UL                               
02096 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT              0x00000000UL                           
02097 #define CMU_HFPERCLKEN0_ADC0_DEFAULT               (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)  
02098 #define CMU_HFPERCLKEN0_I2C0                       (0x1UL << 15)                          
02099 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                15                                     
02100 #define _CMU_HFPERCLKEN0_I2C0_MASK                 0x8000UL                               
02101 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT              0x00000000UL                           
02102 #define CMU_HFPERCLKEN0_I2C0_DEFAULT               (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)  
02104 /* Bit fields for CMU SYNCBUSY */
02105 #define _CMU_SYNCBUSY_RESETVALUE                   0x00000000UL                           
02106 #define _CMU_SYNCBUSY_MASK                         0x00000055UL                           
02107 #define CMU_SYNCBUSY_LFACLKEN0                     (0x1UL << 0)                           
02108 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT              0                                      
02109 #define _CMU_SYNCBUSY_LFACLKEN0_MASK               0x1UL                                  
02110 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT            0x00000000UL                           
02111 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT             (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
02112 #define CMU_SYNCBUSY_LFAPRESC0                     (0x1UL << 2)                           
02113 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT              2                                      
02114 #define _CMU_SYNCBUSY_LFAPRESC0_MASK               0x4UL                                  
02115 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT            0x00000000UL                           
02116 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT             (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
02117 #define CMU_SYNCBUSY_LFBCLKEN0                     (0x1UL << 4)                           
02118 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT              4                                      
02119 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK               0x10UL                                 
02120 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT            0x00000000UL                           
02121 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
02122 #define CMU_SYNCBUSY_LFBPRESC0                     (0x1UL << 6)                           
02123 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT              6                                      
02124 #define _CMU_SYNCBUSY_LFBPRESC0_MASK               0x40UL                                 
02125 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT            0x00000000UL                           
02126 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT             (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
02128 /* Bit fields for CMU FREEZE */
02129 #define _CMU_FREEZE_RESETVALUE                     0x00000000UL                         
02130 #define _CMU_FREEZE_MASK                           0x00000001UL                         
02131 #define CMU_FREEZE_REGFREEZE                       (0x1UL << 0)                         
02132 #define _CMU_FREEZE_REGFREEZE_SHIFT                0                                    
02133 #define _CMU_FREEZE_REGFREEZE_MASK                 0x1UL                                
02134 #define _CMU_FREEZE_REGFREEZE_DEFAULT              0x00000000UL                         
02135 #define _CMU_FREEZE_REGFREEZE_UPDATE               0x00000000UL                         
02136 #define _CMU_FREEZE_REGFREEZE_FREEZE               0x00000001UL                         
02137 #define CMU_FREEZE_REGFREEZE_DEFAULT               (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
02138 #define CMU_FREEZE_REGFREEZE_UPDATE                (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
02139 #define CMU_FREEZE_REGFREEZE_FREEZE                (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
02141 /* Bit fields for CMU LFACLKEN0 */
02142 #define _CMU_LFACLKEN0_RESETVALUE                  0x00000000UL                           
02143 #define _CMU_LFACLKEN0_MASK                        0x00000003UL                           
02144 #define CMU_LFACLKEN0_RTC                          (0x1UL << 0)                           
02145 #define _CMU_LFACLKEN0_RTC_SHIFT                   0                                      
02146 #define _CMU_LFACLKEN0_RTC_MASK                    0x1UL                                  
02147 #define _CMU_LFACLKEN0_RTC_DEFAULT                 0x00000000UL                           
02148 #define CMU_LFACLKEN0_RTC_DEFAULT                  (_CMU_LFACLKEN0_RTC_DEFAULT << 0)      
02149 #define CMU_LFACLKEN0_LETIMER0                     (0x1UL << 1)                           
02150 #define _CMU_LFACLKEN0_LETIMER0_SHIFT              1                                      
02151 #define _CMU_LFACLKEN0_LETIMER0_MASK               0x2UL                                  
02152 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT            0x00000000UL                           
02153 #define CMU_LFACLKEN0_LETIMER0_DEFAULT             (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1) 
02155 /* Bit fields for CMU LFBCLKEN0 */
02156 #define _CMU_LFBCLKEN0_RESETVALUE                  0x00000000UL                          
02157 #define _CMU_LFBCLKEN0_MASK                        0x00000001UL                          
02158 #define CMU_LFBCLKEN0_LEUART0                      (0x1UL << 0)                          
02159 #define _CMU_LFBCLKEN0_LEUART0_SHIFT               0                                     
02160 #define _CMU_LFBCLKEN0_LEUART0_MASK                0x1UL                                 
02161 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT             0x00000000UL                          
02162 #define CMU_LFBCLKEN0_LEUART0_DEFAULT              (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
02164 /* Bit fields for CMU LFAPRESC0 */
02165 #define _CMU_LFAPRESC0_RESETVALUE                  0x00000000UL                            
02166 #define _CMU_LFAPRESC0_MASK                        0x000000FFUL                            
02167 #define _CMU_LFAPRESC0_RTC_SHIFT                   0                                       
02168 #define _CMU_LFAPRESC0_RTC_MASK                    0xFUL                                   
02169 #define _CMU_LFAPRESC0_RTC_DIV1                    0x00000000UL                            
02170 #define _CMU_LFAPRESC0_RTC_DIV2                    0x00000001UL                            
02171 #define _CMU_LFAPRESC0_RTC_DIV4                    0x00000002UL                            
02172 #define _CMU_LFAPRESC0_RTC_DIV8                    0x00000003UL                            
02173 #define _CMU_LFAPRESC0_RTC_DIV16                   0x00000004UL                            
02174 #define _CMU_LFAPRESC0_RTC_DIV32                   0x00000005UL                            
02175 #define _CMU_LFAPRESC0_RTC_DIV64                   0x00000006UL                            
02176 #define _CMU_LFAPRESC0_RTC_DIV128                  0x00000007UL                            
02177 #define _CMU_LFAPRESC0_RTC_DIV256                  0x00000008UL                            
02178 #define _CMU_LFAPRESC0_RTC_DIV512                  0x00000009UL                            
02179 #define _CMU_LFAPRESC0_RTC_DIV1024                 0x0000000AUL                            
02180 #define _CMU_LFAPRESC0_RTC_DIV2048                 0x0000000BUL                            
02181 #define _CMU_LFAPRESC0_RTC_DIV4096                 0x0000000CUL                            
02182 #define _CMU_LFAPRESC0_RTC_DIV8192                 0x0000000DUL                            
02183 #define _CMU_LFAPRESC0_RTC_DIV16384                0x0000000EUL                            
02184 #define _CMU_LFAPRESC0_RTC_DIV32768                0x0000000FUL                            
02185 #define CMU_LFAPRESC0_RTC_DIV1                     (_CMU_LFAPRESC0_RTC_DIV1 << 0)          
02186 #define CMU_LFAPRESC0_RTC_DIV2                     (_CMU_LFAPRESC0_RTC_DIV2 << 0)          
02187 #define CMU_LFAPRESC0_RTC_DIV4                     (_CMU_LFAPRESC0_RTC_DIV4 << 0)          
02188 #define CMU_LFAPRESC0_RTC_DIV8                     (_CMU_LFAPRESC0_RTC_DIV8 << 0)          
02189 #define CMU_LFAPRESC0_RTC_DIV16                    (_CMU_LFAPRESC0_RTC_DIV16 << 0)         
02190 #define CMU_LFAPRESC0_RTC_DIV32                    (_CMU_LFAPRESC0_RTC_DIV32 << 0)         
02191 #define CMU_LFAPRESC0_RTC_DIV64                    (_CMU_LFAPRESC0_RTC_DIV64 << 0)         
02192 #define CMU_LFAPRESC0_RTC_DIV128                   (_CMU_LFAPRESC0_RTC_DIV128 << 0)        
02193 #define CMU_LFAPRESC0_RTC_DIV256                   (_CMU_LFAPRESC0_RTC_DIV256 << 0)        
02194 #define CMU_LFAPRESC0_RTC_DIV512                   (_CMU_LFAPRESC0_RTC_DIV512 << 0)        
02195 #define CMU_LFAPRESC0_RTC_DIV1024                  (_CMU_LFAPRESC0_RTC_DIV1024 << 0)       
02196 #define CMU_LFAPRESC0_RTC_DIV2048                  (_CMU_LFAPRESC0_RTC_DIV2048 << 0)       
02197 #define CMU_LFAPRESC0_RTC_DIV4096                  (_CMU_LFAPRESC0_RTC_DIV4096 << 0)       
02198 #define CMU_LFAPRESC0_RTC_DIV8192                  (_CMU_LFAPRESC0_RTC_DIV8192 << 0)       
02199 #define CMU_LFAPRESC0_RTC_DIV16384                 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)      
02200 #define CMU_LFAPRESC0_RTC_DIV32768                 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)      
02201 #define _CMU_LFAPRESC0_LETIMER0_SHIFT              4                                       
02202 #define _CMU_LFAPRESC0_LETIMER0_MASK               0xF0UL                                  
02203 #define _CMU_LFAPRESC0_LETIMER0_DIV1               0x00000000UL                            
02204 #define _CMU_LFAPRESC0_LETIMER0_DIV2               0x00000001UL                            
02205 #define _CMU_LFAPRESC0_LETIMER0_DIV4               0x00000002UL                            
02206 #define _CMU_LFAPRESC0_LETIMER0_DIV8               0x00000003UL                            
02207 #define _CMU_LFAPRESC0_LETIMER0_DIV16              0x00000004UL                            
02208 #define _CMU_LFAPRESC0_LETIMER0_DIV32              0x00000005UL                            
02209 #define _CMU_LFAPRESC0_LETIMER0_DIV64              0x00000006UL                            
02210 #define _CMU_LFAPRESC0_LETIMER0_DIV128             0x00000007UL                            
02211 #define _CMU_LFAPRESC0_LETIMER0_DIV256             0x00000008UL                            
02212 #define _CMU_LFAPRESC0_LETIMER0_DIV512             0x00000009UL                            
02213 #define _CMU_LFAPRESC0_LETIMER0_DIV1024            0x0000000AUL                            
02214 #define _CMU_LFAPRESC0_LETIMER0_DIV2048            0x0000000BUL                            
02215 #define _CMU_LFAPRESC0_LETIMER0_DIV4096            0x0000000CUL                            
02216 #define _CMU_LFAPRESC0_LETIMER0_DIV8192            0x0000000DUL                            
02217 #define _CMU_LFAPRESC0_LETIMER0_DIV16384           0x0000000EUL                            
02218 #define _CMU_LFAPRESC0_LETIMER0_DIV32768           0x0000000FUL                            
02219 #define CMU_LFAPRESC0_LETIMER0_DIV1                (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)     
02220 #define CMU_LFAPRESC0_LETIMER0_DIV2                (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)     
02221 #define CMU_LFAPRESC0_LETIMER0_DIV4                (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)     
02222 #define CMU_LFAPRESC0_LETIMER0_DIV8                (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)     
02223 #define CMU_LFAPRESC0_LETIMER0_DIV16               (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)    
02224 #define CMU_LFAPRESC0_LETIMER0_DIV32               (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)    
02225 #define CMU_LFAPRESC0_LETIMER0_DIV64               (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)    
02226 #define CMU_LFAPRESC0_LETIMER0_DIV128              (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)   
02227 #define CMU_LFAPRESC0_LETIMER0_DIV256              (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)   
02228 #define CMU_LFAPRESC0_LETIMER0_DIV512              (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)   
02229 #define CMU_LFAPRESC0_LETIMER0_DIV1024             (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)  
02230 #define CMU_LFAPRESC0_LETIMER0_DIV2048             (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)  
02231 #define CMU_LFAPRESC0_LETIMER0_DIV4096             (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)  
02232 #define CMU_LFAPRESC0_LETIMER0_DIV8192             (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)  
02233 #define CMU_LFAPRESC0_LETIMER0_DIV16384            (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4) 
02234 #define CMU_LFAPRESC0_LETIMER0_DIV32768            (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4) 
02236 /* Bit fields for CMU LFBPRESC0 */
02237 #define _CMU_LFBPRESC0_RESETVALUE                  0x00000000UL                       
02238 #define _CMU_LFBPRESC0_MASK                        0x00000003UL                       
02239 #define _CMU_LFBPRESC0_LEUART0_SHIFT               0                                  
02240 #define _CMU_LFBPRESC0_LEUART0_MASK                0x3UL                              
02241 #define _CMU_LFBPRESC0_LEUART0_DIV1                0x00000000UL                       
02242 #define _CMU_LFBPRESC0_LEUART0_DIV2                0x00000001UL                       
02243 #define _CMU_LFBPRESC0_LEUART0_DIV4                0x00000002UL                       
02244 #define _CMU_LFBPRESC0_LEUART0_DIV8                0x00000003UL                       
02245 #define CMU_LFBPRESC0_LEUART0_DIV1                 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
02246 #define CMU_LFBPRESC0_LEUART0_DIV2                 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
02247 #define CMU_LFBPRESC0_LEUART0_DIV4                 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
02248 #define CMU_LFBPRESC0_LEUART0_DIV8                 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
02250 /* Bit fields for CMU PCNTCTRL */
02251 #define _CMU_PCNTCTRL_RESETVALUE                   0x00000000UL                             
02252 #define _CMU_PCNTCTRL_MASK                         0x00000003UL                             
02253 #define CMU_PCNTCTRL_PCNT0CLKEN                    (0x1UL << 0)                             
02254 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT             0                                        
02255 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK              0x1UL                                    
02256 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT           0x00000000UL                             
02257 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
02258 #define CMU_PCNTCTRL_PCNT0CLKSEL                   (0x1UL << 1)                             
02259 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT            1                                        
02260 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK             0x2UL                                    
02261 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT          0x00000000UL                             
02262 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK           0x00000000UL                             
02263 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0          0x00000001UL                             
02264 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
02265 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
02266 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
02268 /* Bit fields for CMU ROUTE */
02269 #define _CMU_ROUTE_RESETVALUE                      0x00000000UL                         
02270 #define _CMU_ROUTE_MASK                            0x00000007UL                         
02271 #define CMU_ROUTE_CLKOUT0PEN                       (0x1UL << 0)                         
02272 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                0                                    
02273 #define _CMU_ROUTE_CLKOUT0PEN_MASK                 0x1UL                                
02274 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT              0x00000000UL                         
02275 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT               (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
02276 #define CMU_ROUTE_CLKOUT1PEN                       (0x1UL << 1)                         
02277 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                1                                    
02278 #define _CMU_ROUTE_CLKOUT1PEN_MASK                 0x2UL                                
02279 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT              0x00000000UL                         
02280 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT               (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
02281 #define CMU_ROUTE_LOCATION                         (0x1UL << 2)                         
02282 #define _CMU_ROUTE_LOCATION_SHIFT                  2                                    
02283 #define _CMU_ROUTE_LOCATION_MASK                   0x4UL                                
02284 #define _CMU_ROUTE_LOCATION_LOC0                   0x00000000UL                         
02285 #define _CMU_ROUTE_LOCATION_DEFAULT                0x00000000UL                         
02286 #define _CMU_ROUTE_LOCATION_LOC1                   0x00000001UL                         
02287 #define CMU_ROUTE_LOCATION_LOC0                    (_CMU_ROUTE_LOCATION_LOC0 << 2)      
02288 #define CMU_ROUTE_LOCATION_DEFAULT                 (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
02289 #define CMU_ROUTE_LOCATION_LOC1                    (_CMU_ROUTE_LOCATION_LOC1 << 2)      
02291 /* Bit fields for CMU LOCK */
02292 #define _CMU_LOCK_RESETVALUE                       0x00000000UL                      
02293 #define _CMU_LOCK_MASK                             0x0000FFFFUL                      
02294 #define _CMU_LOCK_LOCKKEY_SHIFT                    0                                 
02295 #define _CMU_LOCK_LOCKKEY_MASK                     0xFFFFUL                          
02296 #define _CMU_LOCK_LOCKKEY_DEFAULT                  0x00000000UL                      
02297 #define _CMU_LOCK_LOCKKEY_LOCK                     0x00000000UL                      
02298 #define _CMU_LOCK_LOCKKEY_UNLOCKED                 0x00000000UL                      
02299 #define _CMU_LOCK_LOCKKEY_LOCKED                   0x00000001UL                      
02300 #define _CMU_LOCK_LOCKKEY_UNLOCK                   0x0000580EUL                      
02301 #define CMU_LOCK_LOCKKEY_DEFAULT                   (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
02302 #define CMU_LOCK_LOCKKEY_LOCK                      (_CMU_LOCK_LOCKKEY_LOCK << 0)     
02303 #define CMU_LOCK_LOCKKEY_UNLOCKED                  (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
02304 #define CMU_LOCK_LOCKKEY_LOCKED                    (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
02305 #define CMU_LOCK_LOCKKEY_UNLOCK                    (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
02310 /**************************************************************************/
02315 /* Bit fields for PRS SWPULSE */
02316 #define _PRS_SWPULSE_RESETVALUE              0x00000000UL                         
02317 #define _PRS_SWPULSE_MASK                    0x000000FFUL                         
02318 #define PRS_SWPULSE_CH0PULSE                 (0x1UL << 0)                         
02319 #define _PRS_SWPULSE_CH0PULSE_SHIFT          0                                    
02320 #define _PRS_SWPULSE_CH0PULSE_MASK           0x1UL                                
02321 #define _PRS_SWPULSE_CH0PULSE_DEFAULT        0x00000000UL                         
02322 #define PRS_SWPULSE_CH0PULSE_DEFAULT         (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) 
02323 #define PRS_SWPULSE_CH1PULSE                 (0x1UL << 1)                         
02324 #define _PRS_SWPULSE_CH1PULSE_SHIFT          1                                    
02325 #define _PRS_SWPULSE_CH1PULSE_MASK           0x2UL                                
02326 #define _PRS_SWPULSE_CH1PULSE_DEFAULT        0x00000000UL                         
02327 #define PRS_SWPULSE_CH1PULSE_DEFAULT         (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) 
02328 #define PRS_SWPULSE_CH2PULSE                 (0x1UL << 2)                         
02329 #define _PRS_SWPULSE_CH2PULSE_SHIFT          2                                    
02330 #define _PRS_SWPULSE_CH2PULSE_MASK           0x4UL                                
02331 #define _PRS_SWPULSE_CH2PULSE_DEFAULT        0x00000000UL                         
02332 #define PRS_SWPULSE_CH2PULSE_DEFAULT         (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) 
02333 #define PRS_SWPULSE_CH3PULSE                 (0x1UL << 3)                         
02334 #define _PRS_SWPULSE_CH3PULSE_SHIFT          3                                    
02335 #define _PRS_SWPULSE_CH3PULSE_MASK           0x8UL                                
02336 #define _PRS_SWPULSE_CH3PULSE_DEFAULT        0x00000000UL                         
02337 #define PRS_SWPULSE_CH3PULSE_DEFAULT         (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) 
02338 #define PRS_SWPULSE_CH4PULSE                 (0x1UL << 4)                         
02339 #define _PRS_SWPULSE_CH4PULSE_SHIFT          4                                    
02340 #define _PRS_SWPULSE_CH4PULSE_MASK           0x10UL                               
02341 #define _PRS_SWPULSE_CH4PULSE_DEFAULT        0x00000000UL                         
02342 #define PRS_SWPULSE_CH4PULSE_DEFAULT         (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) 
02343 #define PRS_SWPULSE_CH5PULSE                 (0x1UL << 5)                         
02344 #define _PRS_SWPULSE_CH5PULSE_SHIFT          5                                    
02345 #define _PRS_SWPULSE_CH5PULSE_MASK           0x20UL                               
02346 #define _PRS_SWPULSE_CH5PULSE_DEFAULT        0x00000000UL                         
02347 #define PRS_SWPULSE_CH5PULSE_DEFAULT         (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) 
02348 #define PRS_SWPULSE_CH6PULSE                 (0x1UL << 6)                         
02349 #define _PRS_SWPULSE_CH6PULSE_SHIFT          6                                    
02350 #define _PRS_SWPULSE_CH6PULSE_MASK           0x40UL                               
02351 #define _PRS_SWPULSE_CH6PULSE_DEFAULT        0x00000000UL                         
02352 #define PRS_SWPULSE_CH6PULSE_DEFAULT         (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) 
02353 #define PRS_SWPULSE_CH7PULSE                 (0x1UL << 7)                         
02354 #define _PRS_SWPULSE_CH7PULSE_SHIFT          7                                    
02355 #define _PRS_SWPULSE_CH7PULSE_MASK           0x80UL                               
02356 #define _PRS_SWPULSE_CH7PULSE_DEFAULT        0x00000000UL                         
02357 #define PRS_SWPULSE_CH7PULSE_DEFAULT         (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) 
02359 /* Bit fields for PRS SWLEVEL */
02360 #define _PRS_SWLEVEL_RESETVALUE              0x00000000UL                         
02361 #define _PRS_SWLEVEL_MASK                    0x000000FFUL                         
02362 #define PRS_SWLEVEL_CH0LEVEL                 (0x1UL << 0)                         
02363 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT          0                                    
02364 #define _PRS_SWLEVEL_CH0LEVEL_MASK           0x1UL                                
02365 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT        0x00000000UL                         
02366 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT         (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) 
02367 #define PRS_SWLEVEL_CH1LEVEL                 (0x1UL << 1)                         
02368 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT          1                                    
02369 #define _PRS_SWLEVEL_CH1LEVEL_MASK           0x2UL                                
02370 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT        0x00000000UL                         
02371 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT         (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) 
02372 #define PRS_SWLEVEL_CH2LEVEL                 (0x1UL << 2)                         
02373 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT          2                                    
02374 #define _PRS_SWLEVEL_CH2LEVEL_MASK           0x4UL                                
02375 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT        0x00000000UL                         
02376 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT         (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) 
02377 #define PRS_SWLEVEL_CH3LEVEL                 (0x1UL << 3)                         
02378 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT          3                                    
02379 #define _PRS_SWLEVEL_CH3LEVEL_MASK           0x8UL                                
02380 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT        0x00000000UL                         
02381 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT         (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) 
02382 #define PRS_SWLEVEL_CH4LEVEL                 (0x1UL << 4)                         
02383 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT          4                                    
02384 #define _PRS_SWLEVEL_CH4LEVEL_MASK           0x10UL                               
02385 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT        0x00000000UL                         
02386 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT         (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) 
02387 #define PRS_SWLEVEL_CH5LEVEL                 (0x1UL << 5)                         
02388 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT          5                                    
02389 #define _PRS_SWLEVEL_CH5LEVEL_MASK           0x20UL                               
02390 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT        0x00000000UL                         
02391 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT         (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) 
02392 #define PRS_SWLEVEL_CH6LEVEL                 (0x1UL << 6)                         
02393 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT          6                                    
02394 #define _PRS_SWLEVEL_CH6LEVEL_MASK           0x40UL                               
02395 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT        0x00000000UL                         
02396 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT         (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) 
02397 #define PRS_SWLEVEL_CH7LEVEL                 (0x1UL << 7)                         
02398 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT          7                                    
02399 #define _PRS_SWLEVEL_CH7LEVEL_MASK           0x80UL                               
02400 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT        0x00000000UL                         
02401 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT         (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) 
02403 /* Bit fields for PRS CH_CTRL */
02404 #define _PRS_CH_CTRL_RESETVALUE              0x00000000UL                             
02405 #define _PRS_CH_CTRL_MASK                    0x033F0007UL                             
02406 #define _PRS_CH_CTRL_SIGSEL_SHIFT            0                                        
02407 #define _PRS_CH_CTRL_SIGSEL_MASK             0x7UL                                    
02408 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT          0x00000000UL                             
02409 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT         0x00000000UL                             
02410 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT         0x00000000UL                             
02411 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0          0x00000000UL                             
02412 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE       0x00000000UL                             
02413 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX       0x00000000UL                             
02414 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF         0x00000000UL                             
02415 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF         0x00000000UL                             
02416 #define _PRS_CH_CTRL_SIGSEL_RTCOF            0x00000000UL                             
02417 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0         0x00000000UL                             
02418 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8         0x00000000UL                             
02419 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1          0x00000001UL                             
02420 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN         0x00000001UL                             
02421 #define _PRS_CH_CTRL_SIGSEL_USART0TXC        0x00000001UL                             
02422 #define _PRS_CH_CTRL_SIGSEL_USART1TXC        0x00000001UL                             
02423 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF         0x00000001UL                             
02424 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF         0x00000001UL                             
02425 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0         0x00000001UL                             
02426 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1         0x00000001UL                             
02427 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9         0x00000001UL                             
02428 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV    0x00000002UL                             
02429 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV    0x00000002UL                             
02430 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0        0x00000002UL                             
02431 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0        0x00000002UL                             
02432 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1         0x00000002UL                             
02433 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2         0x00000002UL                             
02434 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10        0x00000002UL                             
02435 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1        0x00000003UL                             
02436 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1        0x00000003UL                             
02437 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3         0x00000003UL                             
02438 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11        0x00000003UL                             
02439 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2        0x00000004UL                             
02440 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2        0x00000004UL                             
02441 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4         0x00000004UL                             
02442 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12        0x00000004UL                             
02443 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5         0x00000005UL                             
02444 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13        0x00000005UL                             
02445 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6         0x00000006UL                             
02446 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14        0x00000006UL                             
02447 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7         0x00000007UL                             
02448 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15        0x00000007UL                             
02449 #define PRS_CH_CTRL_SIGSEL_VCMPOUT           (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)       
02450 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT          (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)      
02451 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT          (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)      
02452 #define PRS_CH_CTRL_SIGSEL_DAC0CH0           (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)       
02453 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE        (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)    
02454 #define PRS_CH_CTRL_SIGSEL_USART0IRTX        (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)    
02455 #define PRS_CH_CTRL_SIGSEL_TIMER0UF          (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)      
02456 #define PRS_CH_CTRL_SIGSEL_TIMER1UF          (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)      
02457 #define PRS_CH_CTRL_SIGSEL_RTCOF             (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)         
02458 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0          (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)      
02459 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8          (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)      
02460 #define PRS_CH_CTRL_SIGSEL_DAC0CH1           (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)       
02461 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN          (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)      
02462 #define PRS_CH_CTRL_SIGSEL_USART0TXC         (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)     
02463 #define PRS_CH_CTRL_SIGSEL_USART1TXC         (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)     
02464 #define PRS_CH_CTRL_SIGSEL_TIMER0OF          (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)      
02465 #define PRS_CH_CTRL_SIGSEL_TIMER1OF          (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)      
02466 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0          (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)      
02467 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1          (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)      
02468 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9          (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)      
02469 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) 
02470 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 
02471 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0         (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)     
02472 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0         (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)     
02473 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1          (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)      
02474 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2          (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)      
02475 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10         (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)     
02476 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1         (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)     
02477 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1         (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)     
02478 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3          (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)      
02479 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11         (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)     
02480 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2         (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)     
02481 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2         (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)     
02482 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4          (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)      
02483 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12         (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)     
02484 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5          (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)      
02485 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13         (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)     
02486 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6          (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)      
02487 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14         (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)     
02488 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7          (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)      
02489 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15         (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)     
02490 #define _PRS_CH_CTRL_SOURCESEL_SHIFT         16                                       
02491 #define _PRS_CH_CTRL_SOURCESEL_MASK          0x3F0000UL                               
02492 #define _PRS_CH_CTRL_SOURCESEL_NONE          0x00000000UL                             
02493 #define _PRS_CH_CTRL_SOURCESEL_VCMP          0x00000001UL                             
02494 #define _PRS_CH_CTRL_SOURCESEL_ACMP0         0x00000002UL                             
02495 #define _PRS_CH_CTRL_SOURCESEL_ACMP1         0x00000003UL                             
02496 #define _PRS_CH_CTRL_SOURCESEL_DAC0          0x00000006UL                             
02497 #define _PRS_CH_CTRL_SOURCESEL_ADC0          0x00000008UL                             
02498 #define _PRS_CH_CTRL_SOURCESEL_USART0        0x00000010UL                             
02499 #define _PRS_CH_CTRL_SOURCESEL_USART1        0x00000011UL                             
02500 #define _PRS_CH_CTRL_SOURCESEL_TIMER0        0x0000001CUL                             
02501 #define _PRS_CH_CTRL_SOURCESEL_TIMER1        0x0000001DUL                             
02502 #define _PRS_CH_CTRL_SOURCESEL_RTC           0x00000028UL                             
02503 #define _PRS_CH_CTRL_SOURCESEL_GPIOL         0x00000030UL                             
02504 #define _PRS_CH_CTRL_SOURCESEL_GPIOH         0x00000031UL                             
02505 #define PRS_CH_CTRL_SOURCESEL_NONE           (_PRS_CH_CTRL_SOURCESEL_NONE << 16)      
02506 #define PRS_CH_CTRL_SOURCESEL_VCMP           (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)      
02507 #define PRS_CH_CTRL_SOURCESEL_ACMP0          (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)     
02508 #define PRS_CH_CTRL_SOURCESEL_ACMP1          (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)     
02509 #define PRS_CH_CTRL_SOURCESEL_DAC0           (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)      
02510 #define PRS_CH_CTRL_SOURCESEL_ADC0           (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)      
02511 #define PRS_CH_CTRL_SOURCESEL_USART0         (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)    
02512 #define PRS_CH_CTRL_SOURCESEL_USART1         (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)    
02513 #define PRS_CH_CTRL_SOURCESEL_TIMER0         (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)    
02514 #define PRS_CH_CTRL_SOURCESEL_TIMER1         (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)    
02515 #define PRS_CH_CTRL_SOURCESEL_RTC            (_PRS_CH_CTRL_SOURCESEL_RTC << 16)       
02516 #define PRS_CH_CTRL_SOURCESEL_GPIOL          (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)     
02517 #define PRS_CH_CTRL_SOURCESEL_GPIOH          (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)     
02518 #define _PRS_CH_CTRL_EDSEL_SHIFT             24                                       
02519 #define _PRS_CH_CTRL_EDSEL_MASK              0x3000000UL                              
02520 #define _PRS_CH_CTRL_EDSEL_DEFAULT           0x00000000UL                             
02521 #define _PRS_CH_CTRL_EDSEL_OFF               0x00000000UL                             
02522 #define _PRS_CH_CTRL_EDSEL_POSEDGE           0x00000001UL                             
02523 #define _PRS_CH_CTRL_EDSEL_NEGEDGE           0x00000002UL                             
02524 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES         0x00000003UL                             
02525 #define PRS_CH_CTRL_EDSEL_DEFAULT            (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)       
02526 #define PRS_CH_CTRL_EDSEL_OFF                (_PRS_CH_CTRL_EDSEL_OFF << 24)           
02527 #define PRS_CH_CTRL_EDSEL_POSEDGE            (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)       
02528 #define PRS_CH_CTRL_EDSEL_NEGEDGE            (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)       
02529 #define PRS_CH_CTRL_EDSEL_BOTHEDGES          (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)     
02535 /**************************************************************************/
02539 #define MSC_UNLOCK_CODE      0x1B71 
02540 #define EMU_UNLOCK_CODE      0xADE8 
02541 #define CMU_UNLOCK_CODE      0x580E 
02542 #define TIMER_UNLOCK_CODE    0xCE80 
02543 #define GPIO_UNLOCK_CODE     0xA534 
02549 /**************************************************************************/
02554 #include "efm32g_af_ports.h"
02555 #include "efm32g_af_pins.h"
02556 
02559 /**************************************************************************/
02572 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02573   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02574 
02579 #ifdef __cplusplus
02580 }
02581 #endif
02582 #endif /* __SILICON_LABS_EFM32G200F16_H__ */