release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32G/Include/efm32g_emu.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __IO uint32_t CTRL;         
00040   __IO uint32_t MEMCTRL;      
00041   __IO uint32_t LOCK;         
00042   uint32_t      RESERVED0[6]; 
00043   __IO uint32_t AUXCTRL;      
00044 } EMU_TypeDef;                
00046 /**************************************************************************/
00051 /* Bit fields for EMU CTRL */
00052 #define _EMU_CTRL_RESETVALUE              0x00000000UL                      
00053 #define _EMU_CTRL_MASK                    0x0000000FUL                      
00054 #define EMU_CTRL_EMVREG                   (0x1UL << 0)                      
00055 #define _EMU_CTRL_EMVREG_SHIFT            0                                 
00056 #define _EMU_CTRL_EMVREG_MASK             0x1UL                             
00057 #define _EMU_CTRL_EMVREG_DEFAULT          0x00000000UL                      
00058 #define _EMU_CTRL_EMVREG_REDUCED          0x00000000UL                      
00059 #define _EMU_CTRL_EMVREG_FULL             0x00000001UL                      
00060 #define EMU_CTRL_EMVREG_DEFAULT           (_EMU_CTRL_EMVREG_DEFAULT << 0)   
00061 #define EMU_CTRL_EMVREG_REDUCED           (_EMU_CTRL_EMVREG_REDUCED << 0)   
00062 #define EMU_CTRL_EMVREG_FULL              (_EMU_CTRL_EMVREG_FULL << 0)      
00063 #define EMU_CTRL_EM2BLOCK                 (0x1UL << 1)                      
00064 #define _EMU_CTRL_EM2BLOCK_SHIFT          1                                 
00065 #define _EMU_CTRL_EM2BLOCK_MASK           0x2UL                             
00066 #define _EMU_CTRL_EM2BLOCK_DEFAULT        0x00000000UL                      
00067 #define EMU_CTRL_EM2BLOCK_DEFAULT         (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) 
00068 #define _EMU_CTRL_EM4CTRL_SHIFT           2                                 
00069 #define _EMU_CTRL_EM4CTRL_MASK            0xCUL                             
00070 #define _EMU_CTRL_EM4CTRL_DEFAULT         0x00000000UL                      
00071 #define EMU_CTRL_EM4CTRL_DEFAULT          (_EMU_CTRL_EM4CTRL_DEFAULT << 2)  
00073 /* Bit fields for EMU MEMCTRL */
00074 #define _EMU_MEMCTRL_RESETVALUE           0x00000000UL                          
00075 #define _EMU_MEMCTRL_MASK                 0x00000007UL                          
00076 #define _EMU_MEMCTRL_POWERDOWN_SHIFT      0                                     
00077 #define _EMU_MEMCTRL_POWERDOWN_MASK       0x7UL                                 
00078 #define _EMU_MEMCTRL_POWERDOWN_DEFAULT    0x00000000UL                          
00079 #define _EMU_MEMCTRL_POWERDOWN_BLK3       0x00000004UL                          
00080 #define _EMU_MEMCTRL_POWERDOWN_BLK23      0x00000006UL                          
00081 #define _EMU_MEMCTRL_POWERDOWN_BLK123     0x00000007UL                          
00082 #define EMU_MEMCTRL_POWERDOWN_DEFAULT     (_EMU_MEMCTRL_POWERDOWN_DEFAULT << 0) 
00083 #define EMU_MEMCTRL_POWERDOWN_BLK3        (_EMU_MEMCTRL_POWERDOWN_BLK3 << 0)    
00084 #define EMU_MEMCTRL_POWERDOWN_BLK23       (_EMU_MEMCTRL_POWERDOWN_BLK23 << 0)   
00085 #define EMU_MEMCTRL_POWERDOWN_BLK123      (_EMU_MEMCTRL_POWERDOWN_BLK123 << 0)  
00087 /* Bit fields for EMU LOCK */
00088 #define _EMU_LOCK_RESETVALUE              0x00000000UL                      
00089 #define _EMU_LOCK_MASK                    0x0000FFFFUL                      
00090 #define _EMU_LOCK_LOCKKEY_SHIFT           0                                 
00091 #define _EMU_LOCK_LOCKKEY_MASK            0xFFFFUL                          
00092 #define _EMU_LOCK_LOCKKEY_DEFAULT         0x00000000UL                      
00093 #define _EMU_LOCK_LOCKKEY_LOCK            0x00000000UL                      
00094 #define _EMU_LOCK_LOCKKEY_UNLOCKED        0x00000000UL                      
00095 #define _EMU_LOCK_LOCKKEY_LOCKED          0x00000001UL                      
00096 #define _EMU_LOCK_LOCKKEY_UNLOCK          0x0000ADE8UL                      
00097 #define EMU_LOCK_LOCKKEY_DEFAULT          (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  
00098 #define EMU_LOCK_LOCKKEY_LOCK             (_EMU_LOCK_LOCKKEY_LOCK << 0)     
00099 #define EMU_LOCK_LOCKKEY_UNLOCKED         (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) 
00100 #define EMU_LOCK_LOCKKEY_LOCKED           (_EMU_LOCK_LOCKKEY_LOCKED << 0)   
00101 #define EMU_LOCK_LOCKKEY_UNLOCK           (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   
00103 /* Bit fields for EMU AUXCTRL */
00104 #define _EMU_AUXCTRL_RESETVALUE           0x00000000UL                       
00105 #define _EMU_AUXCTRL_MASK                 0x00000001UL                       
00106 #define EMU_AUXCTRL_HRCCLR                (0x1UL << 0)                       
00107 #define _EMU_AUXCTRL_HRCCLR_SHIFT         0                                  
00108 #define _EMU_AUXCTRL_HRCCLR_MASK          0x1UL                              
00109 #define _EMU_AUXCTRL_HRCCLR_DEFAULT       0x00000000UL                       
00110 #define EMU_AUXCTRL_HRCCLR_DEFAULT        (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)