Defines | |
#define | _PRS_SWPULSE_RESETVALUE 0x00000000UL |
#define | _PRS_SWPULSE_MASK 0x000000FFUL |
#define | PRS_SWPULSE_CH0PULSE (0x1UL << 0) |
#define | _PRS_SWPULSE_CH0PULSE_SHIFT 0 |
#define | _PRS_SWPULSE_CH0PULSE_MASK 0x1UL |
#define | _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) |
#define | PRS_SWPULSE_CH1PULSE (0x1UL << 1) |
#define | _PRS_SWPULSE_CH1PULSE_SHIFT 1 |
#define | _PRS_SWPULSE_CH1PULSE_MASK 0x2UL |
#define | _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) |
#define | PRS_SWPULSE_CH2PULSE (0x1UL << 2) |
#define | _PRS_SWPULSE_CH2PULSE_SHIFT 2 |
#define | _PRS_SWPULSE_CH2PULSE_MASK 0x4UL |
#define | _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) |
#define | PRS_SWPULSE_CH3PULSE (0x1UL << 3) |
#define | _PRS_SWPULSE_CH3PULSE_SHIFT 3 |
#define | _PRS_SWPULSE_CH3PULSE_MASK 0x8UL |
#define | _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) |
#define | PRS_SWPULSE_CH4PULSE (0x1UL << 4) |
#define | _PRS_SWPULSE_CH4PULSE_SHIFT 4 |
#define | _PRS_SWPULSE_CH4PULSE_MASK 0x10UL |
#define | _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) |
#define | PRS_SWPULSE_CH5PULSE (0x1UL << 5) |
#define | _PRS_SWPULSE_CH5PULSE_SHIFT 5 |
#define | _PRS_SWPULSE_CH5PULSE_MASK 0x20UL |
#define | _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) |
#define | PRS_SWPULSE_CH6PULSE (0x1UL << 6) |
#define | _PRS_SWPULSE_CH6PULSE_SHIFT 6 |
#define | _PRS_SWPULSE_CH6PULSE_MASK 0x40UL |
#define | _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) |
#define | PRS_SWPULSE_CH7PULSE (0x1UL << 7) |
#define | _PRS_SWPULSE_CH7PULSE_SHIFT 7 |
#define | _PRS_SWPULSE_CH7PULSE_MASK 0x80UL |
#define | _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) |
#define | _PRS_SWLEVEL_RESETVALUE 0x00000000UL |
#define | _PRS_SWLEVEL_MASK 0x000000FFUL |
#define | PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) |
#define | _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 |
#define | _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL |
#define | _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) |
#define | PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) |
#define | _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 |
#define | _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL |
#define | _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) |
#define | PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) |
#define | _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 |
#define | _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL |
#define | _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) |
#define | PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) |
#define | _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 |
#define | _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL |
#define | _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) |
#define | PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) |
#define | _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 |
#define | _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL |
#define | _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) |
#define | PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) |
#define | _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 |
#define | _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL |
#define | _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) |
#define | PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) |
#define | _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 |
#define | _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL |
#define | _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) |
#define | PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) |
#define | _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 |
#define | _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL |
#define | _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) |
#define | _PRS_CH_CTRL_RESETVALUE 0x00000000UL |
#define | _PRS_CH_CTRL_MASK 0x033F0007UL |
#define | _PRS_CH_CTRL_SIGSEL_SHIFT 0 |
#define | _PRS_CH_CTRL_SIGSEL_MASK 0x7UL |
#define | _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL |
#define | PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) |
#define | PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) |
#define | _PRS_CH_CTRL_SOURCESEL_SHIFT 16 |
#define | _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL |
#define | _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL |
#define | _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL |
#define | _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL |
#define | _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL |
#define | _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL |
#define | _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL |
#define | _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL |
#define | _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL |
#define | _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL |
#define | PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) |
#define | PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) |
#define | PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) |
#define | PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) |
#define | _PRS_CH_CTRL_EDSEL_SHIFT 24 |
#define | _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL |
#define | _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL |
#define | _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL |
#define | _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL |
#define | _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL |
#define | _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL |
#define | PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) |
#define | PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) |
#define | PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) |
#define | PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) |
#define | PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) |
#define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL |
Mode BOTHEDGES for PRS_CH_CTRL
Definition at line 2720 of file efm32g842f128.h.
#define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_CH_CTRL
Definition at line 2716 of file efm32g842f128.h.
#define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL |
Bit mask for PRS_EDSEL
Definition at line 2715 of file efm32g842f128.h.
#define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL |
Mode NEGEDGE for PRS_CH_CTRL
Definition at line 2719 of file efm32g842f128.h.
#define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL |
Mode OFF for PRS_CH_CTRL
Definition at line 2717 of file efm32g842f128.h.
#define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL |
Mode POSEDGE for PRS_CH_CTRL
Definition at line 2718 of file efm32g842f128.h.
#define _PRS_CH_CTRL_EDSEL_SHIFT 24 |
Shift value for PRS_EDSEL
Definition at line 2714 of file efm32g842f128.h.
#define _PRS_CH_CTRL_MASK 0x033F0007UL |
Mask for PRS_CH_CTRL
Definition at line 2583 of file efm32g842f128.h.
#define _PRS_CH_CTRL_RESETVALUE 0x00000000UL |
Default value for PRS_CH_CTRL
Definition at line 2582 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL |
Mode ACMP0OUT for PRS_CH_CTRL
Definition at line 2587 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL |
Mode ACMP1OUT for PRS_CH_CTRL
Definition at line 2588 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL |
Mode ADC0SCAN for PRS_CH_CTRL
Definition at line 2599 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL |
Mode ADC0SINGLE for PRS_CH_CTRL
Definition at line 2590 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL |
Mode DAC0CH0 for PRS_CH_CTRL
Definition at line 2589 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL |
Mode DAC0CH1 for PRS_CH_CTRL
Definition at line 2598 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL |
Mode GPIOPIN0 for PRS_CH_CTRL
Definition at line 2596 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL |
Mode GPIOPIN1 for PRS_CH_CTRL
Definition at line 2607 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL |
Mode GPIOPIN10 for PRS_CH_CTRL
Definition at line 2617 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL |
Mode GPIOPIN11 for PRS_CH_CTRL
Definition at line 2622 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL |
Mode GPIOPIN12 for PRS_CH_CTRL
Definition at line 2627 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL |
Mode GPIOPIN13 for PRS_CH_CTRL
Definition at line 2629 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL |
Mode GPIOPIN14 for PRS_CH_CTRL
Definition at line 2631 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL |
Mode GPIOPIN15 for PRS_CH_CTRL
Definition at line 2633 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL |
Mode GPIOPIN2 for PRS_CH_CTRL
Definition at line 2616 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL |
Mode GPIOPIN3 for PRS_CH_CTRL
Definition at line 2621 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL |
Mode GPIOPIN4 for PRS_CH_CTRL
Definition at line 2626 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL |
Mode GPIOPIN5 for PRS_CH_CTRL
Definition at line 2628 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL |
Mode GPIOPIN6 for PRS_CH_CTRL
Definition at line 2630 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL |
Mode GPIOPIN7 for PRS_CH_CTRL
Definition at line 2632 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL |
Mode GPIOPIN8 for PRS_CH_CTRL
Definition at line 2597 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL |
Mode GPIOPIN9 for PRS_CH_CTRL
Definition at line 2608 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL |
Bit mask for PRS_SIGSEL
Definition at line 2585 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL |
Mode RTCCOMP0 for PRS_CH_CTRL
Definition at line 2606 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL |
Mode RTCCOMP1 for PRS_CH_CTRL
Definition at line 2615 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL |
Mode RTCOF for PRS_CH_CTRL
Definition at line 2595 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_SHIFT 0 |
Shift value for PRS_SIGSEL
Definition at line 2584 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL |
Mode TIMER0CC0 for PRS_CH_CTRL
Definition at line 2612 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL |
Mode TIMER0CC1 for PRS_CH_CTRL
Definition at line 2618 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL |
Mode TIMER0CC2 for PRS_CH_CTRL
Definition at line 2623 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL |
Mode TIMER0OF for PRS_CH_CTRL
Definition at line 2603 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL |
Mode TIMER0UF for PRS_CH_CTRL
Definition at line 2592 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL |
Mode TIMER1CC0 for PRS_CH_CTRL
Definition at line 2613 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL |
Mode TIMER1CC1 for PRS_CH_CTRL
Definition at line 2619 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL |
Mode TIMER1CC2 for PRS_CH_CTRL
Definition at line 2624 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL |
Mode TIMER1OF for PRS_CH_CTRL
Definition at line 2604 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL |
Mode TIMER1UF for PRS_CH_CTRL
Definition at line 2593 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL |
Mode TIMER2CC0 for PRS_CH_CTRL
Definition at line 2614 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL |
Mode TIMER2CC1 for PRS_CH_CTRL
Definition at line 2620 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL |
Mode TIMER2CC2 for PRS_CH_CTRL
Definition at line 2625 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL |
Mode TIMER2OF for PRS_CH_CTRL
Definition at line 2605 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL |
Mode TIMER2UF for PRS_CH_CTRL
Definition at line 2594 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL |
Mode USART0IRTX for PRS_CH_CTRL
Definition at line 2591 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL |
Mode USART0RXDATAV for PRS_CH_CTRL
Definition at line 2609 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL |
Mode USART0TXC for PRS_CH_CTRL
Definition at line 2600 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL |
Mode USART1RXDATAV for PRS_CH_CTRL
Definition at line 2610 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL |
Mode USART1TXC for PRS_CH_CTRL
Definition at line 2601 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL |
Mode USART2RXDATAV for PRS_CH_CTRL
Definition at line 2611 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL |
Mode USART2TXC for PRS_CH_CTRL
Definition at line 2602 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL |
Mode VCMPOUT for PRS_CH_CTRL
Definition at line 2586 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL |
Mode ACMP0 for PRS_CH_CTRL
Definition at line 2686 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL |
Mode ACMP1 for PRS_CH_CTRL
Definition at line 2687 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL |
Mode ADC0 for PRS_CH_CTRL
Definition at line 2689 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL |
Mode DAC0 for PRS_CH_CTRL
Definition at line 2688 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL |
Mode GPIOH for PRS_CH_CTRL
Definition at line 2698 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL |
Mode GPIOL for PRS_CH_CTRL
Definition at line 2697 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL |
Bit mask for PRS_SOURCESEL
Definition at line 2683 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL |
Mode NONE for PRS_CH_CTRL
Definition at line 2684 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL |
Mode RTC for PRS_CH_CTRL
Definition at line 2696 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 |
Shift value for PRS_SOURCESEL
Definition at line 2682 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL |
Mode TIMER0 for PRS_CH_CTRL
Definition at line 2693 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL |
Mode TIMER1 for PRS_CH_CTRL
Definition at line 2694 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL |
Mode TIMER2 for PRS_CH_CTRL
Definition at line 2695 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL |
Mode USART0 for PRS_CH_CTRL
Definition at line 2690 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL |
Mode USART1 for PRS_CH_CTRL
Definition at line 2691 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL |
Mode USART2 for PRS_CH_CTRL
Definition at line 2692 of file efm32g842f128.h.
#define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL |
Mode VCMP for PRS_CH_CTRL
Definition at line 2685 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2543 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL |
Bit mask for PRS_CH0LEVEL
Definition at line 2542 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 |
Shift value for PRS_CH0LEVEL
Definition at line 2541 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2548 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL |
Bit mask for PRS_CH1LEVEL
Definition at line 2547 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 |
Shift value for PRS_CH1LEVEL
Definition at line 2546 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2553 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL |
Bit mask for PRS_CH2LEVEL
Definition at line 2552 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 |
Shift value for PRS_CH2LEVEL
Definition at line 2551 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2558 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL |
Bit mask for PRS_CH3LEVEL
Definition at line 2557 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 |
Shift value for PRS_CH3LEVEL
Definition at line 2556 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2563 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL |
Bit mask for PRS_CH4LEVEL
Definition at line 2562 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 |
Shift value for PRS_CH4LEVEL
Definition at line 2561 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2568 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL |
Bit mask for PRS_CH5LEVEL
Definition at line 2567 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 |
Shift value for PRS_CH5LEVEL
Definition at line 2566 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2573 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL |
Bit mask for PRS_CH6LEVEL
Definition at line 2572 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 |
Shift value for PRS_CH6LEVEL
Definition at line 2571 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWLEVEL
Definition at line 2578 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL |
Bit mask for PRS_CH7LEVEL
Definition at line 2577 of file efm32g842f128.h.
#define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 |
Shift value for PRS_CH7LEVEL
Definition at line 2576 of file efm32g842f128.h.
#define _PRS_SWLEVEL_MASK 0x000000FFUL |
Mask for PRS_SWLEVEL
Definition at line 2539 of file efm32g842f128.h.
#define _PRS_SWLEVEL_RESETVALUE 0x00000000UL |
Default value for PRS_SWLEVEL
Definition at line 2538 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2499 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL |
Bit mask for PRS_CH0PULSE
Definition at line 2498 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH0PULSE_SHIFT 0 |
Shift value for PRS_CH0PULSE
Definition at line 2497 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2504 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL |
Bit mask for PRS_CH1PULSE
Definition at line 2503 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH1PULSE_SHIFT 1 |
Shift value for PRS_CH1PULSE
Definition at line 2502 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2509 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL |
Bit mask for PRS_CH2PULSE
Definition at line 2508 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH2PULSE_SHIFT 2 |
Shift value for PRS_CH2PULSE
Definition at line 2507 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2514 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL |
Bit mask for PRS_CH3PULSE
Definition at line 2513 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH3PULSE_SHIFT 3 |
Shift value for PRS_CH3PULSE
Definition at line 2512 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2519 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL |
Bit mask for PRS_CH4PULSE
Definition at line 2518 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH4PULSE_SHIFT 4 |
Shift value for PRS_CH4PULSE
Definition at line 2517 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2524 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL |
Bit mask for PRS_CH5PULSE
Definition at line 2523 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH5PULSE_SHIFT 5 |
Shift value for PRS_CH5PULSE
Definition at line 2522 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2529 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL |
Bit mask for PRS_CH6PULSE
Definition at line 2528 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH6PULSE_SHIFT 6 |
Shift value for PRS_CH6PULSE
Definition at line 2527 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL |
Mode DEFAULT for PRS_SWPULSE
Definition at line 2534 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL |
Bit mask for PRS_CH7PULSE
Definition at line 2533 of file efm32g842f128.h.
#define _PRS_SWPULSE_CH7PULSE_SHIFT 7 |
Shift value for PRS_CH7PULSE
Definition at line 2532 of file efm32g842f128.h.
#define _PRS_SWPULSE_MASK 0x000000FFUL |
Mask for PRS_SWPULSE
Definition at line 2495 of file efm32g842f128.h.
#define _PRS_SWPULSE_RESETVALUE 0x00000000UL |
Default value for PRS_SWPULSE
Definition at line 2494 of file efm32g842f128.h.
#define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) |
Shifted mode BOTHEDGES for PRS_CH_CTRL
Definition at line 2725 of file efm32g842f128.h.
#define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) |
Shifted mode DEFAULT for PRS_CH_CTRL
Definition at line 2721 of file efm32g842f128.h.
#define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) |
Shifted mode NEGEDGE for PRS_CH_CTRL
Definition at line 2724 of file efm32g842f128.h.
#define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) |
Shifted mode OFF for PRS_CH_CTRL
Definition at line 2722 of file efm32g842f128.h.
#define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) |
Shifted mode POSEDGE for PRS_CH_CTRL
Definition at line 2723 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) |
Shifted mode ACMP0OUT for PRS_CH_CTRL
Definition at line 2635 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) |
Shifted mode ACMP1OUT for PRS_CH_CTRL
Definition at line 2636 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) |
Shifted mode ADC0SCAN for PRS_CH_CTRL
Definition at line 2647 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) |
Shifted mode ADC0SINGLE for PRS_CH_CTRL
Definition at line 2638 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) |
Shifted mode DAC0CH0 for PRS_CH_CTRL
Definition at line 2637 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) |
Shifted mode DAC0CH1 for PRS_CH_CTRL
Definition at line 2646 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) |
Shifted mode GPIOPIN0 for PRS_CH_CTRL
Definition at line 2644 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) |
Shifted mode GPIOPIN1 for PRS_CH_CTRL
Definition at line 2655 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) |
Shifted mode GPIOPIN10 for PRS_CH_CTRL
Definition at line 2665 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) |
Shifted mode GPIOPIN11 for PRS_CH_CTRL
Definition at line 2670 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) |
Shifted mode GPIOPIN12 for PRS_CH_CTRL
Definition at line 2675 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) |
Shifted mode GPIOPIN13 for PRS_CH_CTRL
Definition at line 2677 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) |
Shifted mode GPIOPIN14 for PRS_CH_CTRL
Definition at line 2679 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) |
Shifted mode GPIOPIN15 for PRS_CH_CTRL
Definition at line 2681 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) |
Shifted mode GPIOPIN2 for PRS_CH_CTRL
Definition at line 2664 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) |
Shifted mode GPIOPIN3 for PRS_CH_CTRL
Definition at line 2669 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) |
Shifted mode GPIOPIN4 for PRS_CH_CTRL
Definition at line 2674 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) |
Shifted mode GPIOPIN5 for PRS_CH_CTRL
Definition at line 2676 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) |
Shifted mode GPIOPIN6 for PRS_CH_CTRL
Definition at line 2678 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) |
Shifted mode GPIOPIN7 for PRS_CH_CTRL
Definition at line 2680 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) |
Shifted mode GPIOPIN8 for PRS_CH_CTRL
Definition at line 2645 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) |
Shifted mode GPIOPIN9 for PRS_CH_CTRL
Definition at line 2656 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) |
Shifted mode RTCCOMP0 for PRS_CH_CTRL
Definition at line 2654 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) |
Shifted mode RTCCOMP1 for PRS_CH_CTRL
Definition at line 2663 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) |
Shifted mode RTCOF for PRS_CH_CTRL
Definition at line 2643 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) |
Shifted mode TIMER0CC0 for PRS_CH_CTRL
Definition at line 2660 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) |
Shifted mode TIMER0CC1 for PRS_CH_CTRL
Definition at line 2666 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) |
Shifted mode TIMER0CC2 for PRS_CH_CTRL
Definition at line 2671 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) |
Shifted mode TIMER0OF for PRS_CH_CTRL
Definition at line 2651 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) |
Shifted mode TIMER0UF for PRS_CH_CTRL
Definition at line 2640 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) |
Shifted mode TIMER1CC0 for PRS_CH_CTRL
Definition at line 2661 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) |
Shifted mode TIMER1CC1 for PRS_CH_CTRL
Definition at line 2667 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) |
Shifted mode TIMER1CC2 for PRS_CH_CTRL
Definition at line 2672 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) |
Shifted mode TIMER1OF for PRS_CH_CTRL
Definition at line 2652 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) |
Shifted mode TIMER1UF for PRS_CH_CTRL
Definition at line 2641 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) |
Shifted mode TIMER2CC0 for PRS_CH_CTRL
Definition at line 2662 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) |
Shifted mode TIMER2CC1 for PRS_CH_CTRL
Definition at line 2668 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) |
Shifted mode TIMER2CC2 for PRS_CH_CTRL
Definition at line 2673 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) |
Shifted mode TIMER2OF for PRS_CH_CTRL
Definition at line 2653 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) |
Shifted mode TIMER2UF for PRS_CH_CTRL
Definition at line 2642 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) |
Shifted mode USART0IRTX for PRS_CH_CTRL
Definition at line 2639 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) |
Shifted mode USART0RXDATAV for PRS_CH_CTRL
Definition at line 2657 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) |
Shifted mode USART0TXC for PRS_CH_CTRL
Definition at line 2648 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) |
Shifted mode USART1RXDATAV for PRS_CH_CTRL
Definition at line 2658 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) |
Shifted mode USART1TXC for PRS_CH_CTRL
Definition at line 2649 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) |
Shifted mode USART2RXDATAV for PRS_CH_CTRL
Definition at line 2659 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) |
Shifted mode USART2TXC for PRS_CH_CTRL
Definition at line 2650 of file efm32g842f128.h.
#define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) |
Shifted mode VCMPOUT for PRS_CH_CTRL
Definition at line 2634 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) |
Shifted mode ACMP0 for PRS_CH_CTRL
Definition at line 2701 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) |
Shifted mode ACMP1 for PRS_CH_CTRL
Definition at line 2702 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) |
Shifted mode ADC0 for PRS_CH_CTRL
Definition at line 2704 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) |
Shifted mode DAC0 for PRS_CH_CTRL
Definition at line 2703 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) |
Shifted mode GPIOH for PRS_CH_CTRL
Definition at line 2713 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) |
Shifted mode GPIOL for PRS_CH_CTRL
Definition at line 2712 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) |
Shifted mode NONE for PRS_CH_CTRL
Definition at line 2699 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) |
Shifted mode RTC for PRS_CH_CTRL
Definition at line 2711 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) |
Shifted mode TIMER0 for PRS_CH_CTRL
Definition at line 2708 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) |
Shifted mode TIMER1 for PRS_CH_CTRL
Definition at line 2709 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) |
Shifted mode TIMER2 for PRS_CH_CTRL
Definition at line 2710 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) |
Shifted mode USART0 for PRS_CH_CTRL
Definition at line 2705 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) |
Shifted mode USART1 for PRS_CH_CTRL
Definition at line 2706 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) |
Shifted mode USART2 for PRS_CH_CTRL
Definition at line 2707 of file efm32g842f128.h.
#define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) |
Shifted mode VCMP for PRS_CH_CTRL
Definition at line 2700 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) |
Channel 0 Software Level
Definition at line 2540 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2544 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) |
Channel 1 Software Level
Definition at line 2545 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2549 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) |
Channel 2 Software Level
Definition at line 2550 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2554 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) |
Channel 3 Software Level
Definition at line 2555 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2559 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) |
Channel 4 Software Level
Definition at line 2560 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2564 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) |
Channel 5 Software Level
Definition at line 2565 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2569 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) |
Channel 6 Software Level
Definition at line 2570 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2574 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) |
Channel 7 Software Level
Definition at line 2575 of file efm32g842f128.h.
#define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) |
Shifted mode DEFAULT for PRS_SWLEVEL
Definition at line 2579 of file efm32g842f128.h.
#define PRS_SWPULSE_CH0PULSE (0x1UL << 0) |
Channel 0 Pulse Generation
Definition at line 2496 of file efm32g842f128.h.
#define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2500 of file efm32g842f128.h.
#define PRS_SWPULSE_CH1PULSE (0x1UL << 1) |
Channel 1 Pulse Generation
Definition at line 2501 of file efm32g842f128.h.
#define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2505 of file efm32g842f128.h.
#define PRS_SWPULSE_CH2PULSE (0x1UL << 2) |
Channel 2 Pulse Generation
Definition at line 2506 of file efm32g842f128.h.
#define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2510 of file efm32g842f128.h.
#define PRS_SWPULSE_CH3PULSE (0x1UL << 3) |
Channel 3 Pulse Generation
Definition at line 2511 of file efm32g842f128.h.
#define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2515 of file efm32g842f128.h.
#define PRS_SWPULSE_CH4PULSE (0x1UL << 4) |
Channel 4 Pulse Generation
Definition at line 2516 of file efm32g842f128.h.
#define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2520 of file efm32g842f128.h.
#define PRS_SWPULSE_CH5PULSE (0x1UL << 5) |
Channel 5 Pulse Generation
Definition at line 2521 of file efm32g842f128.h.
#define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2525 of file efm32g842f128.h.
#define PRS_SWPULSE_CH6PULSE (0x1UL << 6) |
Channel 6 Pulse Generation
Definition at line 2526 of file efm32g842f128.h.
#define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2530 of file efm32g842f128.h.
#define PRS_SWPULSE_CH7PULSE (0x1UL << 7) |
Channel 7 Pulse Generation
Definition at line 2531 of file efm32g842f128.h.
#define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) |
Shifted mode DEFAULT for PRS_SWPULSE
Definition at line 2535 of file efm32g842f128.h.