00001
00034 #ifndef __SILICON_LABS_EFM32G840F128_H__
00035 #define __SILICON_LABS_EFM32G840F128_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 MemoryManagement_IRQn = -12,
00058 BusFault_IRQn = -11,
00059 UsageFault_IRQn = -10,
00060 SVCall_IRQn = -5,
00061 DebugMonitor_IRQn = -4,
00062 PendSV_IRQn = -2,
00063 SysTick_IRQn = -1,
00065
00066 DMA_IRQn = 0,
00067 GPIO_EVEN_IRQn = 1,
00068 TIMER0_IRQn = 2,
00069 USART0_RX_IRQn = 3,
00070 USART0_TX_IRQn = 4,
00071 ACMP0_IRQn = 5,
00072 ADC0_IRQn = 6,
00073 DAC0_IRQn = 7,
00074 I2C0_IRQn = 8,
00075 GPIO_ODD_IRQn = 9,
00076 TIMER1_IRQn = 10,
00077 TIMER2_IRQn = 11,
00078 USART1_RX_IRQn = 12,
00079 USART1_TX_IRQn = 13,
00080 USART2_RX_IRQn = 14,
00081 USART2_TX_IRQn = 15,
00082 LEUART0_IRQn = 18,
00083 LEUART1_IRQn = 19,
00084 LETIMER0_IRQn = 20,
00085 PCNT0_IRQn = 21,
00086 PCNT1_IRQn = 22,
00087 PCNT2_IRQn = 23,
00088 RTC_IRQn = 24,
00089 CMU_IRQn = 25,
00090 VCMP_IRQn = 26,
00091 LCD_IRQn = 27,
00092 MSC_IRQn = 28,
00093 AES_IRQn = 29,
00094 } IRQn_Type;
00095
00096
00101 #define __MPU_PRESENT 1
00102 #define __NVIC_PRIO_BITS 3
00103 #define __Vendor_SysTickConfig 0
00107
00113 #define _EFM32_GECKO_FAMILY 1
00114 #define _EFM_DEVICE
00115 #define _SILICON_LABS_32B_PLATFORM_1
00116 #define _SILICON_LABS_32B_PLATFORM 1
00118
00119 #if !defined(EFM32G840F128)
00120 #define EFM32G840F128 1
00121 #endif
00122
00124 #define PART_NUMBER "EFM32G840F128"
00127 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00128 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00129 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00130 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00131 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00132 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00133 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00134 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00135 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00136 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00137 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00138 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00139 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00140 #define RAM_MEM_SIZE ((uint32_t) 0x8000UL)
00141 #define RAM_MEM_END ((uint32_t) 0x20007FFFUL)
00142 #define RAM_MEM_BITS ((uint32_t) 0x15UL)
00143 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00144 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
00145 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
00146 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
00147 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
00148 #define EBI_MEM_SIZE ((uint32_t) 0x10000000UL)
00149 #define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL)
00150 #define EBI_MEM_BITS ((uint32_t) 0x28UL)
00153 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
00154 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
00157 #define FLASH_BASE (0x00000000UL)
00158 #define FLASH_SIZE (0x00020000UL)
00159 #define FLASH_PAGE_SIZE 512
00160 #define SRAM_BASE (0x20000000UL)
00161 #define SRAM_SIZE (0x00004000UL)
00162 #define __CM3_REV 0x200
00163 #define PRS_CHAN_COUNT 8
00164 #define DMA_CHAN_COUNT 8
00167 #define AFCHAN_MAX 79
00168 #define AFCHANLOC_MAX 4
00169
00170 #define AFACHAN_MAX 37
00171
00172
00173
00174 #define TIMER_PRESENT
00175 #define TIMER_COUNT 3
00176 #define USART_PRESENT
00177 #define USART_COUNT 3
00178 #define LEUART_PRESENT
00179 #define LEUART_COUNT 2
00180 #define LETIMER_PRESENT
00181 #define LETIMER_COUNT 1
00182 #define PCNT_PRESENT
00183 #define PCNT_COUNT 3
00184 #define ACMP_PRESENT
00185 #define ACMP_COUNT 2
00186 #define DAC_PRESENT
00187 #define DAC_COUNT 1
00188 #define ADC_PRESENT
00189 #define ADC_COUNT 1
00190 #define I2C_PRESENT
00191 #define I2C_COUNT 1
00192 #define AES_PRESENT
00193 #define AES_COUNT 1
00194 #define DMA_PRESENT
00195 #define DMA_COUNT 1
00196 #define LE_PRESENT
00197 #define LE_COUNT 1
00198 #define MSC_PRESENT
00199 #define MSC_COUNT 1
00200 #define EMU_PRESENT
00201 #define EMU_COUNT 1
00202 #define RMU_PRESENT
00203 #define RMU_COUNT 1
00204 #define CMU_PRESENT
00205 #define CMU_COUNT 1
00206 #define RTC_PRESENT
00207 #define RTC_COUNT 1
00208 #define PRS_PRESENT
00209 #define PRS_COUNT 1
00210 #define GPIO_PRESENT
00211 #define GPIO_COUNT 1
00212 #define VCMP_PRESENT
00213 #define VCMP_COUNT 1
00214 #define LCD_PRESENT
00215 #define LCD_COUNT 1
00216 #define HFXTAL_PRESENT
00217 #define HFXTAL_COUNT 1
00218 #define LFXTAL_PRESENT
00219 #define LFXTAL_COUNT 1
00220 #define WDOG_PRESENT
00221 #define WDOG_COUNT 1
00222 #define DBG_PRESENT
00223 #define DBG_COUNT 1
00224 #define BOOTLOADER_PRESENT
00225 #define BOOTLOADER_COUNT 1
00226 #define ANALOG_PRESENT
00227 #define ANALOG_COUNT 1
00228
00229 #include "core_cm3.h"
00230 #include "system_efm32g.h"
00231
00234
00240 #include "efm32g_aes.h"
00241 #include "efm32g_dma_ch.h"
00242
00243
00248 typedef struct
00249 {
00250 __I uint32_t STATUS;
00251 __O uint32_t CONFIG;
00252 __IO uint32_t CTRLBASE;
00253 __I uint32_t ALTCTRLBASE;
00254 __I uint32_t CHWAITSTATUS;
00255 __O uint32_t CHSWREQ;
00256 __IO uint32_t CHUSEBURSTS;
00257 __O uint32_t CHUSEBURSTC;
00258 __IO uint32_t CHREQMASKS;
00259 __O uint32_t CHREQMASKC;
00260 __IO uint32_t CHENS;
00261 __O uint32_t CHENC;
00262 __IO uint32_t CHALTS;
00263 __O uint32_t CHALTC;
00264 __IO uint32_t CHPRIS;
00265 __O uint32_t CHPRIC;
00266 uint32_t RESERVED0[3];
00267 __IO uint32_t ERRORC;
00268 uint32_t RESERVED1[880];
00269 __I uint32_t CHREQSTATUS;
00270 uint32_t RESERVED2[1];
00271 __I uint32_t CHSREQSTATUS;
00273 uint32_t RESERVED3[121];
00274 __I uint32_t IF;
00275 __IO uint32_t IFS;
00276 __IO uint32_t IFC;
00277 __IO uint32_t IEN;
00279 uint32_t RESERVED4[60];
00281 DMA_CH_TypeDef CH[8];
00282 } DMA_TypeDef;
00284 #include "efm32g_msc.h"
00285 #include "efm32g_emu.h"
00286 #include "efm32g_rmu.h"
00287
00288
00293 typedef struct
00294 {
00295 __IO uint32_t CTRL;
00296 __IO uint32_t HFCORECLKDIV;
00297 __IO uint32_t HFPERCLKDIV;
00298 __IO uint32_t HFRCOCTRL;
00299 __IO uint32_t LFRCOCTRL;
00300 __IO uint32_t AUXHFRCOCTRL;
00301 __IO uint32_t CALCTRL;
00302 __IO uint32_t CALCNT;
00303 __IO uint32_t OSCENCMD;
00304 __IO uint32_t CMD;
00305 __IO uint32_t LFCLKSEL;
00306 __I uint32_t STATUS;
00307 __I uint32_t IF;
00308 __IO uint32_t IFS;
00309 __IO uint32_t IFC;
00310 __IO uint32_t IEN;
00311 __IO uint32_t HFCORECLKEN0;
00312 __IO uint32_t HFPERCLKEN0;
00313 uint32_t RESERVED0[2];
00314 __I uint32_t SYNCBUSY;
00315 __IO uint32_t FREEZE;
00316 __IO uint32_t LFACLKEN0;
00317 uint32_t RESERVED1[1];
00318 __IO uint32_t LFBCLKEN0;
00319 uint32_t RESERVED2[1];
00320 __IO uint32_t LFAPRESC0;
00321 uint32_t RESERVED3[1];
00322 __IO uint32_t LFBPRESC0;
00323 uint32_t RESERVED4[1];
00324 __IO uint32_t PCNTCTRL;
00325 __IO uint32_t LCDCTRL;
00326 __IO uint32_t ROUTE;
00327 __IO uint32_t LOCK;
00328 } CMU_TypeDef;
00330 #include "efm32g_timer_cc.h"
00331 #include "efm32g_timer.h"
00332 #include "efm32g_usart.h"
00333 #include "efm32g_leuart.h"
00334 #include "efm32g_rtc.h"
00335 #include "efm32g_letimer.h"
00336 #include "efm32g_pcnt.h"
00337 #include "efm32g_acmp.h"
00338 #include "efm32g_prs_ch.h"
00339
00340
00345 typedef struct
00346 {
00347 __IO uint32_t SWPULSE;
00348 __IO uint32_t SWLEVEL;
00350 uint32_t RESERVED0[2];
00352 PRS_CH_TypeDef CH[8];
00353 } PRS_TypeDef;
00355 #include "efm32g_dac.h"
00356 #include "efm32g_gpio_p.h"
00357 #include "efm32g_gpio.h"
00358 #include "efm32g_vcmp.h"
00359 #include "efm32g_adc.h"
00360 #include "efm32g_i2c.h"
00361 #include "efm32g_lcd.h"
00362 #include "efm32g_wdog.h"
00363 #include "efm32g_dma_descriptor.h"
00364 #include "efm32g_devinfo.h"
00365 #include "efm32g_romtable.h"
00366 #include "efm32g_calibrate.h"
00367
00370
00375 #define AES_BASE (0x400E0000UL)
00376 #define DMA_BASE (0x400C2000UL)
00377 #define MSC_BASE (0x400C0000UL)
00378 #define EMU_BASE (0x400C6000UL)
00379 #define RMU_BASE (0x400CA000UL)
00380 #define CMU_BASE (0x400C8000UL)
00381 #define TIMER0_BASE (0x40010000UL)
00382 #define TIMER1_BASE (0x40010400UL)
00383 #define TIMER2_BASE (0x40010800UL)
00384 #define USART0_BASE (0x4000C000UL)
00385 #define USART1_BASE (0x4000C400UL)
00386 #define USART2_BASE (0x4000C800UL)
00387 #define LEUART0_BASE (0x40084000UL)
00388 #define LEUART1_BASE (0x40084400UL)
00389 #define RTC_BASE (0x40080000UL)
00390 #define LETIMER0_BASE (0x40082000UL)
00391 #define PCNT0_BASE (0x40086000UL)
00392 #define PCNT1_BASE (0x40086400UL)
00393 #define PCNT2_BASE (0x40086800UL)
00394 #define ACMP0_BASE (0x40001000UL)
00395 #define ACMP1_BASE (0x40001400UL)
00396 #define PRS_BASE (0x400CC000UL)
00397 #define DAC0_BASE (0x40004000UL)
00398 #define GPIO_BASE (0x40006000UL)
00399 #define VCMP_BASE (0x40000000UL)
00400 #define ADC0_BASE (0x40002000UL)
00401 #define I2C0_BASE (0x4000A000UL)
00402 #define LCD_BASE (0x4008A000UL)
00403 #define WDOG_BASE (0x40088000UL)
00404 #define CALIBRATE_BASE (0x0FE08000UL)
00405 #define DEVINFO_BASE (0x0FE081B0UL)
00406 #define ROMTABLE_BASE (0xE00FFFD0UL)
00407 #define LOCKBITS_BASE (0x0FE04000UL)
00408 #define USERDATA_BASE (0x0FE00000UL)
00412
00417 #define AES ((AES_TypeDef *) AES_BASE)
00418 #define DMA ((DMA_TypeDef *) DMA_BASE)
00419 #define MSC ((MSC_TypeDef *) MSC_BASE)
00420 #define EMU ((EMU_TypeDef *) EMU_BASE)
00421 #define RMU ((RMU_TypeDef *) RMU_BASE)
00422 #define CMU ((CMU_TypeDef *) CMU_BASE)
00423 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00424 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00425 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
00426 #define USART0 ((USART_TypeDef *) USART0_BASE)
00427 #define USART1 ((USART_TypeDef *) USART1_BASE)
00428 #define USART2 ((USART_TypeDef *) USART2_BASE)
00429 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00430 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
00431 #define RTC ((RTC_TypeDef *) RTC_BASE)
00432 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
00433 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00434 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
00435 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
00436 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00437 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
00438 #define PRS ((PRS_TypeDef *) PRS_BASE)
00439 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
00440 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00441 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00442 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00443 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00444 #define LCD ((LCD_TypeDef *) LCD_BASE)
00445 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00446 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00447 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00448 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00452
00457
00463 #define PRS_VCMP_OUT ((1 << 16) + 0)
00464 #define PRS_ACMP0_OUT ((2 << 16) + 0)
00465 #define PRS_ACMP1_OUT ((3 << 16) + 0)
00466 #define PRS_DAC0_CH0 ((6 << 16) + 0)
00467 #define PRS_DAC0_CH1 ((6 << 16) + 1)
00468 #define PRS_ADC0_SINGLE ((8 << 16) + 0)
00469 #define PRS_ADC0_SCAN ((8 << 16) + 1)
00470 #define PRS_USART0_IRTX ((16 << 16) + 0)
00471 #define PRS_USART0_TXC ((16 << 16) + 1)
00472 #define PRS_USART0_RXDATAV ((16 << 16) + 2)
00473 #define PRS_USART1_IRTX ((17 << 16) + 0)
00474 #define PRS_USART1_TXC ((17 << 16) + 1)
00475 #define PRS_USART1_RXDATAV ((17 << 16) + 2)
00476 #define PRS_USART2_IRTX ((18 << 16) + 0)
00477 #define PRS_USART2_TXC ((18 << 16) + 1)
00478 #define PRS_USART2_RXDATAV ((18 << 16) + 2)
00479 #define PRS_TIMER0_UF ((28 << 16) + 0)
00480 #define PRS_TIMER0_OF ((28 << 16) + 1)
00481 #define PRS_TIMER0_CC0 ((28 << 16) + 2)
00482 #define PRS_TIMER0_CC1 ((28 << 16) + 3)
00483 #define PRS_TIMER0_CC2 ((28 << 16) + 4)
00484 #define PRS_TIMER1_UF ((29 << 16) + 0)
00485 #define PRS_TIMER1_OF ((29 << 16) + 1)
00486 #define PRS_TIMER1_CC0 ((29 << 16) + 2)
00487 #define PRS_TIMER1_CC1 ((29 << 16) + 3)
00488 #define PRS_TIMER1_CC2 ((29 << 16) + 4)
00489 #define PRS_TIMER2_UF ((30 << 16) + 0)
00490 #define PRS_TIMER2_OF ((30 << 16) + 1)
00491 #define PRS_TIMER2_CC0 ((30 << 16) + 2)
00492 #define PRS_TIMER2_CC1 ((30 << 16) + 3)
00493 #define PRS_TIMER2_CC2 ((30 << 16) + 4)
00494 #define PRS_RTC_OF ((40 << 16) + 0)
00495 #define PRS_RTC_COMP0 ((40 << 16) + 1)
00496 #define PRS_RTC_COMP1 ((40 << 16) + 2)
00497 #define PRS_GPIO_PIN0 ((48 << 16) + 0)
00498 #define PRS_GPIO_PIN1 ((48 << 16) + 1)
00499 #define PRS_GPIO_PIN2 ((48 << 16) + 2)
00500 #define PRS_GPIO_PIN3 ((48 << 16) + 3)
00501 #define PRS_GPIO_PIN4 ((48 << 16) + 4)
00502 #define PRS_GPIO_PIN5 ((48 << 16) + 5)
00503 #define PRS_GPIO_PIN6 ((48 << 16) + 6)
00504 #define PRS_GPIO_PIN7 ((48 << 16) + 7)
00505 #define PRS_GPIO_PIN8 ((49 << 16) + 0)
00506 #define PRS_GPIO_PIN9 ((49 << 16) + 1)
00507 #define PRS_GPIO_PIN10 ((49 << 16) + 2)
00508 #define PRS_GPIO_PIN11 ((49 << 16) + 3)
00509 #define PRS_GPIO_PIN12 ((49 << 16) + 4)
00510 #define PRS_GPIO_PIN13 ((49 << 16) + 5)
00511 #define PRS_GPIO_PIN14 ((49 << 16) + 6)
00512 #define PRS_GPIO_PIN15 ((49 << 16) + 7)
00516 #include "efm32g_dmareq.h"
00517 #include "efm32g_dmactrl.h"
00518
00519
00524
00525 #define _DMA_STATUS_RESETVALUE 0x10070000UL
00526 #define _DMA_STATUS_MASK 0x001F00F1UL
00527 #define DMA_STATUS_EN (0x1UL << 0)
00528 #define _DMA_STATUS_EN_SHIFT 0
00529 #define _DMA_STATUS_EN_MASK 0x1UL
00530 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL
00531 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
00532 #define _DMA_STATUS_STATE_SHIFT 4
00533 #define _DMA_STATUS_STATE_MASK 0xF0UL
00534 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL
00535 #define _DMA_STATUS_STATE_IDLE 0x00000000UL
00536 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
00537 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
00538 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
00539 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
00540 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
00541 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
00542 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
00543 #define _DMA_STATUS_STATE_STALLED 0x00000008UL
00544 #define _DMA_STATUS_STATE_DONE 0x00000009UL
00545 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
00546 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
00547 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
00548 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
00549 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
00550 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
00551 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
00552 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
00553 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
00554 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
00555 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
00556 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
00557 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
00558 #define _DMA_STATUS_CHNUM_SHIFT 16
00559 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL
00560 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL
00561 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
00563
00564 #define _DMA_CONFIG_RESETVALUE 0x00000000UL
00565 #define _DMA_CONFIG_MASK 0x00000021UL
00566 #define DMA_CONFIG_EN (0x1UL << 0)
00567 #define _DMA_CONFIG_EN_SHIFT 0
00568 #define _DMA_CONFIG_EN_MASK 0x1UL
00569 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL
00570 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
00571 #define DMA_CONFIG_CHPROT (0x1UL << 5)
00572 #define _DMA_CONFIG_CHPROT_SHIFT 5
00573 #define _DMA_CONFIG_CHPROT_MASK 0x20UL
00574 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
00575 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
00577
00578 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL
00579 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL
00580 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0
00581 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
00582 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
00583 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
00585
00586 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL
00587 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00588 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
00589 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00590 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL
00591 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
00593
00594 #define _DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL
00595 #define _DMA_CHWAITSTATUS_MASK 0x000000FFUL
00596 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
00597 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
00598 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
00599 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
00600 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
00601 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
00602 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
00603 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
00604 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
00605 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
00606 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
00607 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
00608 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
00609 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
00610 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
00611 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
00612 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
00613 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
00614 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
00615 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
00616 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)
00617 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4
00618 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL
00619 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL
00620 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
00621 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)
00622 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5
00623 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL
00624 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL
00625 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
00626 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6)
00627 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6
00628 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL
00629 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL
00630 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
00631 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7)
00632 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7
00633 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL
00634 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL
00635 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
00637
00638 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL
00639 #define _DMA_CHSWREQ_MASK 0x000000FFUL
00640 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
00641 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0
00642 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
00643 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
00644 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
00645 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
00646 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1
00647 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
00648 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
00649 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
00650 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
00651 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2
00652 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
00653 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
00654 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
00655 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
00656 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3
00657 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
00658 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
00659 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
00660 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)
00661 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4
00662 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL
00663 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL
00664 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
00665 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)
00666 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5
00667 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL
00668 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL
00669 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
00670 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6)
00671 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6
00672 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL
00673 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL
00674 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
00675 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7)
00676 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7
00677 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL
00678 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL
00679 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
00681
00682 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
00683 #define _DMA_CHUSEBURSTS_MASK 0x000000FFUL
00684 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
00685 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
00686 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
00687 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
00688 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
00689 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
00690 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
00691 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
00692 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
00693 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
00694 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
00695 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
00696 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
00697 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
00698 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
00699 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
00700 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
00701 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
00702 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
00703 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
00704 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
00705 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
00706 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
00707 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
00708 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)
00709 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4
00710 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL
00711 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL
00712 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
00713 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)
00714 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5
00715 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL
00716 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL
00717 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
00718 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6)
00719 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6
00720 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL
00721 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL
00722 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
00723 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7)
00724 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7
00725 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL
00726 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL
00727 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
00729
00730 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
00731 #define _DMA_CHUSEBURSTC_MASK 0x000000FFUL
00732 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
00733 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
00734 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
00735 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
00736 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
00737 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
00738 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
00739 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
00740 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
00741 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
00742 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
00743 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
00744 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
00745 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
00746 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
00747 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
00748 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
00749 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
00750 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
00751 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
00752 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)
00753 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4
00754 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL
00755 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL
00756 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
00757 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)
00758 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5
00759 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL
00760 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL
00761 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
00762 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6)
00763 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6
00764 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL
00765 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL
00766 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
00767 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7)
00768 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7
00769 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL
00770 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL
00771 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
00773
00774 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
00775 #define _DMA_CHREQMASKS_MASK 0x000000FFUL
00776 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
00777 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
00778 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
00779 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
00780 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
00781 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
00782 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
00783 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
00784 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
00785 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
00786 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
00787 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
00788 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
00789 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
00790 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
00791 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
00792 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
00793 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
00794 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
00795 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
00796 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)
00797 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
00798 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
00799 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
00800 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
00801 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)
00802 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
00803 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
00804 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
00805 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
00806 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6)
00807 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6
00808 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL
00809 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL
00810 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
00811 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7)
00812 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7
00813 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL
00814 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL
00815 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
00817
00818 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
00819 #define _DMA_CHREQMASKC_MASK 0x000000FFUL
00820 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
00821 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
00822 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
00823 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
00824 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
00825 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
00826 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
00827 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
00828 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
00829 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
00830 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
00831 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
00832 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
00833 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
00834 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
00835 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
00836 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
00837 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
00838 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
00839 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
00840 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)
00841 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
00842 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
00843 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
00844 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
00845 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)
00846 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
00847 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
00848 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
00849 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
00850 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6)
00851 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6
00852 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL
00853 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL
00854 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
00855 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7)
00856 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7
00857 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL
00858 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL
00859 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
00861
00862 #define _DMA_CHENS_RESETVALUE 0x00000000UL
00863 #define _DMA_CHENS_MASK 0x000000FFUL
00864 #define DMA_CHENS_CH0ENS (0x1UL << 0)
00865 #define _DMA_CHENS_CH0ENS_SHIFT 0
00866 #define _DMA_CHENS_CH0ENS_MASK 0x1UL
00867 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
00868 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
00869 #define DMA_CHENS_CH1ENS (0x1UL << 1)
00870 #define _DMA_CHENS_CH1ENS_SHIFT 1
00871 #define _DMA_CHENS_CH1ENS_MASK 0x2UL
00872 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
00873 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
00874 #define DMA_CHENS_CH2ENS (0x1UL << 2)
00875 #define _DMA_CHENS_CH2ENS_SHIFT 2
00876 #define _DMA_CHENS_CH2ENS_MASK 0x4UL
00877 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
00878 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
00879 #define DMA_CHENS_CH3ENS (0x1UL << 3)
00880 #define _DMA_CHENS_CH3ENS_SHIFT 3
00881 #define _DMA_CHENS_CH3ENS_MASK 0x8UL
00882 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
00883 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
00884 #define DMA_CHENS_CH4ENS (0x1UL << 4)
00885 #define _DMA_CHENS_CH4ENS_SHIFT 4
00886 #define _DMA_CHENS_CH4ENS_MASK 0x10UL
00887 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
00888 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)
00889 #define DMA_CHENS_CH5ENS (0x1UL << 5)
00890 #define _DMA_CHENS_CH5ENS_SHIFT 5
00891 #define _DMA_CHENS_CH5ENS_MASK 0x20UL
00892 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
00893 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)
00894 #define DMA_CHENS_CH6ENS (0x1UL << 6)
00895 #define _DMA_CHENS_CH6ENS_SHIFT 6
00896 #define _DMA_CHENS_CH6ENS_MASK 0x40UL
00897 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL
00898 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6)
00899 #define DMA_CHENS_CH7ENS (0x1UL << 7)
00900 #define _DMA_CHENS_CH7ENS_SHIFT 7
00901 #define _DMA_CHENS_CH7ENS_MASK 0x80UL
00902 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL
00903 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7)
00905
00906 #define _DMA_CHENC_RESETVALUE 0x00000000UL
00907 #define _DMA_CHENC_MASK 0x000000FFUL
00908 #define DMA_CHENC_CH0ENC (0x1UL << 0)
00909 #define _DMA_CHENC_CH0ENC_SHIFT 0
00910 #define _DMA_CHENC_CH0ENC_MASK 0x1UL
00911 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
00912 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
00913 #define DMA_CHENC_CH1ENC (0x1UL << 1)
00914 #define _DMA_CHENC_CH1ENC_SHIFT 1
00915 #define _DMA_CHENC_CH1ENC_MASK 0x2UL
00916 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
00917 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
00918 #define DMA_CHENC_CH2ENC (0x1UL << 2)
00919 #define _DMA_CHENC_CH2ENC_SHIFT 2
00920 #define _DMA_CHENC_CH2ENC_MASK 0x4UL
00921 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
00922 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
00923 #define DMA_CHENC_CH3ENC (0x1UL << 3)
00924 #define _DMA_CHENC_CH3ENC_SHIFT 3
00925 #define _DMA_CHENC_CH3ENC_MASK 0x8UL
00926 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
00927 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
00928 #define DMA_CHENC_CH4ENC (0x1UL << 4)
00929 #define _DMA_CHENC_CH4ENC_SHIFT 4
00930 #define _DMA_CHENC_CH4ENC_MASK 0x10UL
00931 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
00932 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)
00933 #define DMA_CHENC_CH5ENC (0x1UL << 5)
00934 #define _DMA_CHENC_CH5ENC_SHIFT 5
00935 #define _DMA_CHENC_CH5ENC_MASK 0x20UL
00936 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
00937 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)
00938 #define DMA_CHENC_CH6ENC (0x1UL << 6)
00939 #define _DMA_CHENC_CH6ENC_SHIFT 6
00940 #define _DMA_CHENC_CH6ENC_MASK 0x40UL
00941 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL
00942 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6)
00943 #define DMA_CHENC_CH7ENC (0x1UL << 7)
00944 #define _DMA_CHENC_CH7ENC_SHIFT 7
00945 #define _DMA_CHENC_CH7ENC_MASK 0x80UL
00946 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL
00947 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7)
00949
00950 #define _DMA_CHALTS_RESETVALUE 0x00000000UL
00951 #define _DMA_CHALTS_MASK 0x000000FFUL
00952 #define DMA_CHALTS_CH0ALTS (0x1UL << 0)
00953 #define _DMA_CHALTS_CH0ALTS_SHIFT 0
00954 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
00955 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
00956 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
00957 #define DMA_CHALTS_CH1ALTS (0x1UL << 1)
00958 #define _DMA_CHALTS_CH1ALTS_SHIFT 1
00959 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
00960 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
00961 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
00962 #define DMA_CHALTS_CH2ALTS (0x1UL << 2)
00963 #define _DMA_CHALTS_CH2ALTS_SHIFT 2
00964 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
00965 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
00966 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
00967 #define DMA_CHALTS_CH3ALTS (0x1UL << 3)
00968 #define _DMA_CHALTS_CH3ALTS_SHIFT 3
00969 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
00970 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
00971 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
00972 #define DMA_CHALTS_CH4ALTS (0x1UL << 4)
00973 #define _DMA_CHALTS_CH4ALTS_SHIFT 4
00974 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL
00975 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
00976 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
00977 #define DMA_CHALTS_CH5ALTS (0x1UL << 5)
00978 #define _DMA_CHALTS_CH5ALTS_SHIFT 5
00979 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL
00980 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
00981 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
00982 #define DMA_CHALTS_CH6ALTS (0x1UL << 6)
00983 #define _DMA_CHALTS_CH6ALTS_SHIFT 6
00984 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL
00985 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL
00986 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
00987 #define DMA_CHALTS_CH7ALTS (0x1UL << 7)
00988 #define _DMA_CHALTS_CH7ALTS_SHIFT 7
00989 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL
00990 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL
00991 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
00993
00994 #define _DMA_CHALTC_RESETVALUE 0x00000000UL
00995 #define _DMA_CHALTC_MASK 0x000000FFUL
00996 #define DMA_CHALTC_CH0ALTC (0x1UL << 0)
00997 #define _DMA_CHALTC_CH0ALTC_SHIFT 0
00998 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
00999 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
01000 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
01001 #define DMA_CHALTC_CH1ALTC (0x1UL << 1)
01002 #define _DMA_CHALTC_CH1ALTC_SHIFT 1
01003 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
01004 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
01005 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
01006 #define DMA_CHALTC_CH2ALTC (0x1UL << 2)
01007 #define _DMA_CHALTC_CH2ALTC_SHIFT 2
01008 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
01009 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
01010 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
01011 #define DMA_CHALTC_CH3ALTC (0x1UL << 3)
01012 #define _DMA_CHALTC_CH3ALTC_SHIFT 3
01013 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
01014 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
01015 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
01016 #define DMA_CHALTC_CH4ALTC (0x1UL << 4)
01017 #define _DMA_CHALTC_CH4ALTC_SHIFT 4
01018 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL
01019 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
01020 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
01021 #define DMA_CHALTC_CH5ALTC (0x1UL << 5)
01022 #define _DMA_CHALTC_CH5ALTC_SHIFT 5
01023 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL
01024 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
01025 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
01026 #define DMA_CHALTC_CH6ALTC (0x1UL << 6)
01027 #define _DMA_CHALTC_CH6ALTC_SHIFT 6
01028 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL
01029 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL
01030 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
01031 #define DMA_CHALTC_CH7ALTC (0x1UL << 7)
01032 #define _DMA_CHALTC_CH7ALTC_SHIFT 7
01033 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL
01034 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL
01035 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
01037
01038 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL
01039 #define _DMA_CHPRIS_MASK 0x000000FFUL
01040 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0)
01041 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0
01042 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
01043 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
01044 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
01045 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1)
01046 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1
01047 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
01048 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
01049 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
01050 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2)
01051 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2
01052 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
01053 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
01054 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
01055 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3)
01056 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3
01057 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
01058 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
01059 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
01060 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4)
01061 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4
01062 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL
01063 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
01064 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
01065 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5)
01066 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5
01067 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL
01068 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
01069 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
01070 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6)
01071 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6
01072 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL
01073 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL
01074 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
01075 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7)
01076 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7
01077 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL
01078 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL
01079 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
01081
01082 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL
01083 #define _DMA_CHPRIC_MASK 0x000000FFUL
01084 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0)
01085 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0
01086 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
01087 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
01088 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
01089 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1)
01090 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1
01091 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
01092 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
01093 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
01094 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2)
01095 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2
01096 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
01097 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
01098 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
01099 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3)
01100 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3
01101 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
01102 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
01103 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
01104 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4)
01105 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4
01106 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL
01107 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
01108 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
01109 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5)
01110 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5
01111 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL
01112 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
01113 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
01114 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6)
01115 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6
01116 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL
01117 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL
01118 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
01119 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7)
01120 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7
01121 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL
01122 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL
01123 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
01125
01126 #define _DMA_ERRORC_RESETVALUE 0x00000000UL
01127 #define _DMA_ERRORC_MASK 0x00000001UL
01128 #define DMA_ERRORC_ERRORC (0x1UL << 0)
01129 #define _DMA_ERRORC_ERRORC_SHIFT 0
01130 #define _DMA_ERRORC_ERRORC_MASK 0x1UL
01131 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
01132 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
01134
01135 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
01136 #define _DMA_CHREQSTATUS_MASK 0x000000FFUL
01137 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
01138 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
01139 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
01140 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
01141 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
01142 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
01143 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
01144 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
01145 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
01146 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
01147 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
01148 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
01149 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
01150 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
01151 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
01152 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
01153 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
01154 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
01155 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
01156 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
01157 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)
01158 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
01159 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
01160 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
01161 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
01162 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)
01163 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
01164 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
01165 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
01166 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
01167 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6)
01168 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6
01169 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL
01170 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL
01171 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
01172 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7)
01173 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7
01174 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL
01175 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL
01176 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
01178
01179 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
01180 #define _DMA_CHSREQSTATUS_MASK 0x000000FFUL
01181 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
01182 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
01183 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
01184 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
01185 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
01186 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
01187 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
01188 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
01189 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
01190 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
01191 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
01192 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
01193 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
01194 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
01195 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
01196 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
01197 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
01198 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
01199 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
01200 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
01201 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)
01202 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
01203 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
01204 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
01205 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
01206 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)
01207 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
01208 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
01209 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
01210 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
01211 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6)
01212 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6
01213 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL
01214 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL
01215 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
01216 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7)
01217 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7
01218 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL
01219 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL
01220 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
01222
01223 #define _DMA_IF_RESETVALUE 0x00000000UL
01224 #define _DMA_IF_MASK 0x800000FFUL
01225 #define DMA_IF_CH0DONE (0x1UL << 0)
01226 #define _DMA_IF_CH0DONE_SHIFT 0
01227 #define _DMA_IF_CH0DONE_MASK 0x1UL
01228 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL
01229 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
01230 #define DMA_IF_CH1DONE (0x1UL << 1)
01231 #define _DMA_IF_CH1DONE_SHIFT 1
01232 #define _DMA_IF_CH1DONE_MASK 0x2UL
01233 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL
01234 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
01235 #define DMA_IF_CH2DONE (0x1UL << 2)
01236 #define _DMA_IF_CH2DONE_SHIFT 2
01237 #define _DMA_IF_CH2DONE_MASK 0x4UL
01238 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL
01239 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
01240 #define DMA_IF_CH3DONE (0x1UL << 3)
01241 #define _DMA_IF_CH3DONE_SHIFT 3
01242 #define _DMA_IF_CH3DONE_MASK 0x8UL
01243 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL
01244 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
01245 #define DMA_IF_CH4DONE (0x1UL << 4)
01246 #define _DMA_IF_CH4DONE_SHIFT 4
01247 #define _DMA_IF_CH4DONE_MASK 0x10UL
01248 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL
01249 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)
01250 #define DMA_IF_CH5DONE (0x1UL << 5)
01251 #define _DMA_IF_CH5DONE_SHIFT 5
01252 #define _DMA_IF_CH5DONE_MASK 0x20UL
01253 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL
01254 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)
01255 #define DMA_IF_CH6DONE (0x1UL << 6)
01256 #define _DMA_IF_CH6DONE_SHIFT 6
01257 #define _DMA_IF_CH6DONE_MASK 0x40UL
01258 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL
01259 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6)
01260 #define DMA_IF_CH7DONE (0x1UL << 7)
01261 #define _DMA_IF_CH7DONE_SHIFT 7
01262 #define _DMA_IF_CH7DONE_MASK 0x80UL
01263 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL
01264 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7)
01265 #define DMA_IF_ERR (0x1UL << 31)
01266 #define _DMA_IF_ERR_SHIFT 31
01267 #define _DMA_IF_ERR_MASK 0x80000000UL
01268 #define _DMA_IF_ERR_DEFAULT 0x00000000UL
01269 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
01271
01272 #define _DMA_IFS_RESETVALUE 0x00000000UL
01273 #define _DMA_IFS_MASK 0x800000FFUL
01274 #define DMA_IFS_CH0DONE (0x1UL << 0)
01275 #define _DMA_IFS_CH0DONE_SHIFT 0
01276 #define _DMA_IFS_CH0DONE_MASK 0x1UL
01277 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
01278 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
01279 #define DMA_IFS_CH1DONE (0x1UL << 1)
01280 #define _DMA_IFS_CH1DONE_SHIFT 1
01281 #define _DMA_IFS_CH1DONE_MASK 0x2UL
01282 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
01283 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
01284 #define DMA_IFS_CH2DONE (0x1UL << 2)
01285 #define _DMA_IFS_CH2DONE_SHIFT 2
01286 #define _DMA_IFS_CH2DONE_MASK 0x4UL
01287 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
01288 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
01289 #define DMA_IFS_CH3DONE (0x1UL << 3)
01290 #define _DMA_IFS_CH3DONE_SHIFT 3
01291 #define _DMA_IFS_CH3DONE_MASK 0x8UL
01292 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
01293 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
01294 #define DMA_IFS_CH4DONE (0x1UL << 4)
01295 #define _DMA_IFS_CH4DONE_SHIFT 4
01296 #define _DMA_IFS_CH4DONE_MASK 0x10UL
01297 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL
01298 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)
01299 #define DMA_IFS_CH5DONE (0x1UL << 5)
01300 #define _DMA_IFS_CH5DONE_SHIFT 5
01301 #define _DMA_IFS_CH5DONE_MASK 0x20UL
01302 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL
01303 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)
01304 #define DMA_IFS_CH6DONE (0x1UL << 6)
01305 #define _DMA_IFS_CH6DONE_SHIFT 6
01306 #define _DMA_IFS_CH6DONE_MASK 0x40UL
01307 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL
01308 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6)
01309 #define DMA_IFS_CH7DONE (0x1UL << 7)
01310 #define _DMA_IFS_CH7DONE_SHIFT 7
01311 #define _DMA_IFS_CH7DONE_MASK 0x80UL
01312 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL
01313 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7)
01314 #define DMA_IFS_ERR (0x1UL << 31)
01315 #define _DMA_IFS_ERR_SHIFT 31
01316 #define _DMA_IFS_ERR_MASK 0x80000000UL
01317 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL
01318 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
01320
01321 #define _DMA_IFC_RESETVALUE 0x00000000UL
01322 #define _DMA_IFC_MASK 0x800000FFUL
01323 #define DMA_IFC_CH0DONE (0x1UL << 0)
01324 #define _DMA_IFC_CH0DONE_SHIFT 0
01325 #define _DMA_IFC_CH0DONE_MASK 0x1UL
01326 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
01327 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
01328 #define DMA_IFC_CH1DONE (0x1UL << 1)
01329 #define _DMA_IFC_CH1DONE_SHIFT 1
01330 #define _DMA_IFC_CH1DONE_MASK 0x2UL
01331 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
01332 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
01333 #define DMA_IFC_CH2DONE (0x1UL << 2)
01334 #define _DMA_IFC_CH2DONE_SHIFT 2
01335 #define _DMA_IFC_CH2DONE_MASK 0x4UL
01336 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
01337 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
01338 #define DMA_IFC_CH3DONE (0x1UL << 3)
01339 #define _DMA_IFC_CH3DONE_SHIFT 3
01340 #define _DMA_IFC_CH3DONE_MASK 0x8UL
01341 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
01342 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
01343 #define DMA_IFC_CH4DONE (0x1UL << 4)
01344 #define _DMA_IFC_CH4DONE_SHIFT 4
01345 #define _DMA_IFC_CH4DONE_MASK 0x10UL
01346 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL
01347 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)
01348 #define DMA_IFC_CH5DONE (0x1UL << 5)
01349 #define _DMA_IFC_CH5DONE_SHIFT 5
01350 #define _DMA_IFC_CH5DONE_MASK 0x20UL
01351 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL
01352 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)
01353 #define DMA_IFC_CH6DONE (0x1UL << 6)
01354 #define _DMA_IFC_CH6DONE_SHIFT 6
01355 #define _DMA_IFC_CH6DONE_MASK 0x40UL
01356 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL
01357 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6)
01358 #define DMA_IFC_CH7DONE (0x1UL << 7)
01359 #define _DMA_IFC_CH7DONE_SHIFT 7
01360 #define _DMA_IFC_CH7DONE_MASK 0x80UL
01361 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL
01362 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7)
01363 #define DMA_IFC_ERR (0x1UL << 31)
01364 #define _DMA_IFC_ERR_SHIFT 31
01365 #define _DMA_IFC_ERR_MASK 0x80000000UL
01366 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL
01367 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
01369
01370 #define _DMA_IEN_RESETVALUE 0x00000000UL
01371 #define _DMA_IEN_MASK 0x800000FFUL
01372 #define DMA_IEN_CH0DONE (0x1UL << 0)
01373 #define _DMA_IEN_CH0DONE_SHIFT 0
01374 #define _DMA_IEN_CH0DONE_MASK 0x1UL
01375 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
01376 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
01377 #define DMA_IEN_CH1DONE (0x1UL << 1)
01378 #define _DMA_IEN_CH1DONE_SHIFT 1
01379 #define _DMA_IEN_CH1DONE_MASK 0x2UL
01380 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
01381 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
01382 #define DMA_IEN_CH2DONE (0x1UL << 2)
01383 #define _DMA_IEN_CH2DONE_SHIFT 2
01384 #define _DMA_IEN_CH2DONE_MASK 0x4UL
01385 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
01386 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
01387 #define DMA_IEN_CH3DONE (0x1UL << 3)
01388 #define _DMA_IEN_CH3DONE_SHIFT 3
01389 #define _DMA_IEN_CH3DONE_MASK 0x8UL
01390 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
01391 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
01392 #define DMA_IEN_CH4DONE (0x1UL << 4)
01393 #define _DMA_IEN_CH4DONE_SHIFT 4
01394 #define _DMA_IEN_CH4DONE_MASK 0x10UL
01395 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL
01396 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)
01397 #define DMA_IEN_CH5DONE (0x1UL << 5)
01398 #define _DMA_IEN_CH5DONE_SHIFT 5
01399 #define _DMA_IEN_CH5DONE_MASK 0x20UL
01400 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL
01401 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)
01402 #define DMA_IEN_CH6DONE (0x1UL << 6)
01403 #define _DMA_IEN_CH6DONE_SHIFT 6
01404 #define _DMA_IEN_CH6DONE_MASK 0x40UL
01405 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL
01406 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6)
01407 #define DMA_IEN_CH7DONE (0x1UL << 7)
01408 #define _DMA_IEN_CH7DONE_SHIFT 7
01409 #define _DMA_IEN_CH7DONE_MASK 0x80UL
01410 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL
01411 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7)
01412 #define DMA_IEN_ERR (0x1UL << 31)
01413 #define _DMA_IEN_ERR_SHIFT 31
01414 #define _DMA_IEN_ERR_MASK 0x80000000UL
01415 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL
01416 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
01418
01419 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
01420 #define _DMA_CH_CTRL_MASK 0x003F000FUL
01421 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0
01422 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
01423 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
01424 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
01425 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL
01426 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
01427 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL
01428 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
01429 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL
01430 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
01431 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
01432 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
01433 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL
01434 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
01435 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL
01436 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
01437 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
01438 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL
01439 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
01440 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL
01441 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
01442 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL
01443 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
01444 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
01445 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
01446 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL
01447 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL
01448 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL
01449 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
01450 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL
01451 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
01452 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL
01453 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
01454 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
01455 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL
01456 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL
01457 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
01458 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
01459 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL
01460 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL
01461 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
01462 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)
01463 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
01464 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
01465 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
01466 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
01467 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0)
01468 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
01469 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
01470 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
01471 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)
01472 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
01473 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
01474 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
01475 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)
01476 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)
01477 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
01478 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0)
01479 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
01480 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0)
01481 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
01482 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
01483 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
01484 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
01485 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
01486 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)
01487 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
01488 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0)
01489 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
01490 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0)
01491 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
01492 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
01493 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
01494 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
01495 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
01496 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
01497 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
01498 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
01499 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
01500 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
01501 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
01502 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
01503 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL
01504 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL
01505 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
01506 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL
01507 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
01508 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL
01509 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
01510 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
01511 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
01512 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL
01513 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
01514 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL
01515 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
01516 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
01517 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)
01518 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)
01519 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
01520 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16)
01521 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
01522 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16)
01523 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
01524 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
01525 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
01526 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)
01527 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
01528 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)
01534
01539
01540 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
01541 #define _CMU_CTRL_MASK 0x00FE3EEFUL
01542 #define _CMU_CTRL_HFXOMODE_SHIFT 0
01543 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
01544 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
01545 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
01546 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
01547 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
01548 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
01549 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
01550 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
01551 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
01552 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
01553 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
01554 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
01555 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
01556 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
01557 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
01558 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
01559 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
01560 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
01561 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
01562 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
01563 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
01564 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
01565 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
01566 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
01567 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
01568 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
01569 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
01570 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
01571 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
01572 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
01573 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
01574 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
01575 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
01576 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
01577 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
01578 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
01579 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
01580 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
01581 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
01582 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
01583 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
01584 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
01585 #define _CMU_CTRL_LFXOMODE_SHIFT 11
01586 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
01587 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
01588 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
01589 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
01590 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
01591 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
01592 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
01593 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
01594 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
01595 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
01596 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
01597 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
01598 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
01599 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
01600 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
01601 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
01602 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
01603 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
01604 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
01605 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
01606 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
01607 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
01608 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
01609 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
01610 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
01611 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
01612 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
01613 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
01614 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
01615 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
01616 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
01617 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
01618 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
01619 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
01620 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
01621 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
01622 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
01623 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
01624 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
01625 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
01626 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
01627 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
01628 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
01629 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
01630 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
01631 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
01632 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
01633 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
01634 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
01635 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
01636 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
01637 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
01638 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
01639 #define CMU_CTRL_CLKOUTSEL1 (0x1UL << 23)
01640 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
01641 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL
01642 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
01643 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
01644 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
01645 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
01646 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
01647 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
01649
01650 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
01651 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
01652 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
01653 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
01654 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
01655 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
01656 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
01657 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
01658 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
01659 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
01660 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
01661 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
01662 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
01663 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
01664 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
01665 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
01666 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
01667 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
01668 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
01669 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
01670 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
01671 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
01672 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
01673 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
01674 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
01675 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
01677
01678 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
01679 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
01680 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
01681 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
01682 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
01683 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
01684 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
01685 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
01686 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
01687 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
01688 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
01689 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
01690 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
01691 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
01692 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
01693 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
01694 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
01695 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
01696 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
01697 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
01698 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
01699 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
01700 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
01701 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
01702 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
01703 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
01704 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
01705 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
01706 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
01707 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
01708 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
01710
01711 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
01712 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
01713 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
01714 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
01715 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01716 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
01717 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
01718 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
01719 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
01720 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
01721 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
01722 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
01723 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
01724 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
01725 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
01726 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
01727 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
01728 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
01729 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
01730 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
01731 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
01732 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
01733 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
01734 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
01735 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
01736 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
01738
01739 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
01740 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
01741 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
01742 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
01743 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
01744 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
01746
01747 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
01748 #define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL
01749 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
01750 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
01751 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01752 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
01754
01755 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
01756 #define _CMU_CALCTRL_MASK 0x00000007UL
01757 #define _CMU_CALCTRL_UPSEL_SHIFT 0
01758 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
01759 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
01760 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
01761 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
01762 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
01763 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
01764 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
01765 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
01766 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
01767 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
01768 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
01769 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
01770 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
01772
01773 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
01774 #define _CMU_CALCNT_MASK 0x000FFFFFUL
01775 #define _CMU_CALCNT_CALCNT_SHIFT 0
01776 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
01777 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
01778 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
01780
01781 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
01782 #define _CMU_OSCENCMD_MASK 0x000003FFUL
01783 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
01784 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
01785 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
01786 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
01787 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
01788 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
01789 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
01790 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
01791 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
01792 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
01793 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
01794 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
01795 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
01796 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
01797 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
01798 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
01799 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
01800 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
01801 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
01802 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
01803 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
01804 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
01805 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
01806 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
01807 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
01808 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
01809 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
01810 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
01811 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
01812 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
01813 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
01814 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
01815 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
01816 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
01817 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
01818 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
01819 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
01820 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
01821 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
01822 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
01823 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
01824 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
01825 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
01826 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
01827 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
01828 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
01829 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
01830 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
01831 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
01832 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
01834
01835 #define _CMU_CMD_RESETVALUE 0x00000000UL
01836 #define _CMU_CMD_MASK 0x0000000FUL
01837 #define _CMU_CMD_HFCLKSEL_SHIFT 0
01838 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
01839 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
01840 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
01841 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
01842 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
01843 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
01844 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
01845 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
01846 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
01847 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
01848 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
01849 #define CMU_CMD_CALSTART (0x1UL << 3)
01850 #define _CMU_CMD_CALSTART_SHIFT 3
01851 #define _CMU_CMD_CALSTART_MASK 0x8UL
01852 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
01853 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
01855
01856 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
01857 #define _CMU_LFCLKSEL_MASK 0x0000000FUL
01858 #define _CMU_LFCLKSEL_LFA_SHIFT 0
01859 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
01860 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
01861 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
01862 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
01863 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
01864 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
01865 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
01866 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
01867 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
01868 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
01869 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
01870 #define _CMU_LFCLKSEL_LFB_SHIFT 2
01871 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
01872 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
01873 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
01874 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
01875 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
01876 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
01877 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
01878 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
01879 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
01880 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
01881 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
01883
01884 #define _CMU_STATUS_RESETVALUE 0x00000403UL
01885 #define _CMU_STATUS_MASK 0x00007FFFUL
01886 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
01887 #define _CMU_STATUS_HFRCOENS_SHIFT 0
01888 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
01889 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
01890 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
01891 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
01892 #define _CMU_STATUS_HFRCORDY_SHIFT 1
01893 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
01894 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
01895 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
01896 #define CMU_STATUS_HFXOENS (0x1UL << 2)
01897 #define _CMU_STATUS_HFXOENS_SHIFT 2
01898 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
01899 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
01900 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
01901 #define CMU_STATUS_HFXORDY (0x1UL << 3)
01902 #define _CMU_STATUS_HFXORDY_SHIFT 3
01903 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
01904 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
01905 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
01906 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
01907 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
01908 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
01909 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
01910 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
01911 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
01912 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
01913 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
01914 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
01915 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
01916 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
01917 #define _CMU_STATUS_LFRCOENS_SHIFT 6
01918 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
01919 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
01920 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
01921 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
01922 #define _CMU_STATUS_LFRCORDY_SHIFT 7
01923 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
01924 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
01925 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
01926 #define CMU_STATUS_LFXOENS (0x1UL << 8)
01927 #define _CMU_STATUS_LFXOENS_SHIFT 8
01928 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
01929 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
01930 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
01931 #define CMU_STATUS_LFXORDY (0x1UL << 9)
01932 #define _CMU_STATUS_LFXORDY_SHIFT 9
01933 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
01934 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
01935 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
01936 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
01937 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
01938 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
01939 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
01940 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
01941 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
01942 #define _CMU_STATUS_HFXOSEL_SHIFT 11
01943 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
01944 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
01945 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
01946 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
01947 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
01948 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
01949 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
01950 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
01951 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
01952 #define _CMU_STATUS_LFXOSEL_SHIFT 13
01953 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
01954 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
01955 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
01956 #define CMU_STATUS_CALBSY (0x1UL << 14)
01957 #define _CMU_STATUS_CALBSY_SHIFT 14
01958 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
01959 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
01960 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
01962
01963 #define _CMU_IF_RESETVALUE 0x00000001UL
01964 #define _CMU_IF_MASK 0x0000003FUL
01965 #define CMU_IF_HFRCORDY (0x1UL << 0)
01966 #define _CMU_IF_HFRCORDY_SHIFT 0
01967 #define _CMU_IF_HFRCORDY_MASK 0x1UL
01968 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
01969 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
01970 #define CMU_IF_HFXORDY (0x1UL << 1)
01971 #define _CMU_IF_HFXORDY_SHIFT 1
01972 #define _CMU_IF_HFXORDY_MASK 0x2UL
01973 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
01974 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
01975 #define CMU_IF_LFRCORDY (0x1UL << 2)
01976 #define _CMU_IF_LFRCORDY_SHIFT 2
01977 #define _CMU_IF_LFRCORDY_MASK 0x4UL
01978 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
01979 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
01980 #define CMU_IF_LFXORDY (0x1UL << 3)
01981 #define _CMU_IF_LFXORDY_SHIFT 3
01982 #define _CMU_IF_LFXORDY_MASK 0x8UL
01983 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
01984 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
01985 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
01986 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
01987 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
01988 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
01989 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
01990 #define CMU_IF_CALRDY (0x1UL << 5)
01991 #define _CMU_IF_CALRDY_SHIFT 5
01992 #define _CMU_IF_CALRDY_MASK 0x20UL
01993 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
01994 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
01996
01997 #define _CMU_IFS_RESETVALUE 0x00000000UL
01998 #define _CMU_IFS_MASK 0x0000003FUL
01999 #define CMU_IFS_HFRCORDY (0x1UL << 0)
02000 #define _CMU_IFS_HFRCORDY_SHIFT 0
02001 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
02002 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
02003 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
02004 #define CMU_IFS_HFXORDY (0x1UL << 1)
02005 #define _CMU_IFS_HFXORDY_SHIFT 1
02006 #define _CMU_IFS_HFXORDY_MASK 0x2UL
02007 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
02008 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
02009 #define CMU_IFS_LFRCORDY (0x1UL << 2)
02010 #define _CMU_IFS_LFRCORDY_SHIFT 2
02011 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
02012 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
02013 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
02014 #define CMU_IFS_LFXORDY (0x1UL << 3)
02015 #define _CMU_IFS_LFXORDY_SHIFT 3
02016 #define _CMU_IFS_LFXORDY_MASK 0x8UL
02017 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
02018 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
02019 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
02020 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
02021 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
02022 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
02023 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
02024 #define CMU_IFS_CALRDY (0x1UL << 5)
02025 #define _CMU_IFS_CALRDY_SHIFT 5
02026 #define _CMU_IFS_CALRDY_MASK 0x20UL
02027 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
02028 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
02030
02031 #define _CMU_IFC_RESETVALUE 0x00000000UL
02032 #define _CMU_IFC_MASK 0x0000003FUL
02033 #define CMU_IFC_HFRCORDY (0x1UL << 0)
02034 #define _CMU_IFC_HFRCORDY_SHIFT 0
02035 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
02036 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
02037 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
02038 #define CMU_IFC_HFXORDY (0x1UL << 1)
02039 #define _CMU_IFC_HFXORDY_SHIFT 1
02040 #define _CMU_IFC_HFXORDY_MASK 0x2UL
02041 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
02042 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
02043 #define CMU_IFC_LFRCORDY (0x1UL << 2)
02044 #define _CMU_IFC_LFRCORDY_SHIFT 2
02045 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
02046 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
02047 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
02048 #define CMU_IFC_LFXORDY (0x1UL << 3)
02049 #define _CMU_IFC_LFXORDY_SHIFT 3
02050 #define _CMU_IFC_LFXORDY_MASK 0x8UL
02051 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
02052 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
02053 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
02054 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
02055 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
02056 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
02057 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
02058 #define CMU_IFC_CALRDY (0x1UL << 5)
02059 #define _CMU_IFC_CALRDY_SHIFT 5
02060 #define _CMU_IFC_CALRDY_MASK 0x20UL
02061 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
02062 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
02064
02065 #define _CMU_IEN_RESETVALUE 0x00000000UL
02066 #define _CMU_IEN_MASK 0x0000003FUL
02067 #define CMU_IEN_HFRCORDY (0x1UL << 0)
02068 #define _CMU_IEN_HFRCORDY_SHIFT 0
02069 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
02070 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
02071 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
02072 #define CMU_IEN_HFXORDY (0x1UL << 1)
02073 #define _CMU_IEN_HFXORDY_SHIFT 1
02074 #define _CMU_IEN_HFXORDY_MASK 0x2UL
02075 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
02076 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
02077 #define CMU_IEN_LFRCORDY (0x1UL << 2)
02078 #define _CMU_IEN_LFRCORDY_SHIFT 2
02079 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
02080 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
02081 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
02082 #define CMU_IEN_LFXORDY (0x1UL << 3)
02083 #define _CMU_IEN_LFXORDY_SHIFT 3
02084 #define _CMU_IEN_LFXORDY_MASK 0x8UL
02085 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
02086 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
02087 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
02088 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
02089 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
02090 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
02091 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
02092 #define CMU_IEN_CALRDY (0x1UL << 5)
02093 #define _CMU_IEN_CALRDY_SHIFT 5
02094 #define _CMU_IEN_CALRDY_MASK 0x20UL
02095 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
02096 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
02098
02099 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
02100 #define _CMU_HFCORECLKEN0_MASK 0x00000007UL
02101 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
02102 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
02103 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
02104 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
02105 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
02106 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
02107 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
02108 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
02109 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
02110 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
02111 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
02112 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
02113 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
02114 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
02115 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
02117
02118 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
02119 #define _CMU_HFPERCLKEN0_MASK 0x0000FDF7UL
02120 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0)
02121 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0
02122 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL
02123 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
02124 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
02125 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1)
02126 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1
02127 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL
02128 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
02129 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
02130 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2)
02131 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2
02132 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL
02133 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL
02134 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
02135 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
02136 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
02137 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
02138 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
02139 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
02140 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
02141 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
02142 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
02143 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
02144 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
02145 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 6)
02146 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 6
02147 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL
02148 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
02149 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 6)
02150 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7)
02151 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7
02152 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL
02153 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
02154 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)
02155 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8)
02156 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8
02157 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL
02158 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
02159 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)
02160 #define CMU_HFPERCLKEN0_PRS (0x1UL << 10)
02161 #define _CMU_HFPERCLKEN0_PRS_SHIFT 10
02162 #define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL
02163 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
02164 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)
02165 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 11)
02166 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 11
02167 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL
02168 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
02169 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)
02170 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 12)
02171 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 12
02172 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL
02173 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
02174 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)
02175 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 13)
02176 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 13
02177 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL
02178 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
02179 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)
02180 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 14)
02181 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 14
02182 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL
02183 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
02184 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)
02185 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 15)
02186 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 15
02187 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL
02188 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
02189 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)
02191
02192 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
02193 #define _CMU_SYNCBUSY_MASK 0x00000055UL
02194 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
02195 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
02196 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
02197 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
02198 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
02199 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
02200 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
02201 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
02202 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
02203 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
02204 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
02205 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
02206 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
02207 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
02208 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
02209 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
02210 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
02211 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
02212 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
02213 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
02215
02216 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
02217 #define _CMU_FREEZE_MASK 0x00000001UL
02218 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
02219 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
02220 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
02221 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
02222 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
02223 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
02224 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
02225 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
02226 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
02228
02229 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
02230 #define _CMU_LFACLKEN0_MASK 0x00000007UL
02231 #define CMU_LFACLKEN0_RTC (0x1UL << 0)
02232 #define _CMU_LFACLKEN0_RTC_SHIFT 0
02233 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL
02234 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
02235 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
02236 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 1)
02237 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 1
02238 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL
02239 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
02240 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1)
02241 #define CMU_LFACLKEN0_LCD (0x1UL << 2)
02242 #define _CMU_LFACLKEN0_LCD_SHIFT 2
02243 #define _CMU_LFACLKEN0_LCD_MASK 0x4UL
02244 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL
02245 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 2)
02247
02248 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
02249 #define _CMU_LFBCLKEN0_MASK 0x00000003UL
02250 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
02251 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
02252 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
02253 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
02254 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
02255 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1)
02256 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1
02257 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL
02258 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL
02259 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)
02261
02262 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
02263 #define _CMU_LFAPRESC0_MASK 0x000003FFUL
02264 #define _CMU_LFAPRESC0_RTC_SHIFT 0
02265 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL
02266 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
02267 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
02268 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
02269 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
02270 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
02271 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
02272 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
02273 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
02274 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
02275 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
02276 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
02277 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
02278 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
02279 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
02280 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
02281 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
02282 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
02283 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
02284 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
02285 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
02286 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
02287 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
02288 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
02289 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
02290 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
02291 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
02292 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
02293 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
02294 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
02295 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
02296 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
02297 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
02298 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 4
02299 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL
02300 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
02301 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
02302 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
02303 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
02304 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
02305 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
02306 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
02307 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
02308 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
02309 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
02310 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
02311 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
02312 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
02313 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
02314 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
02315 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
02316 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)
02317 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)
02318 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)
02319 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)
02320 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)
02321 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)
02322 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)
02323 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)
02324 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)
02325 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)
02326 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)
02327 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)
02328 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)
02329 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)
02330 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4)
02331 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4)
02332 #define _CMU_LFAPRESC0_LCD_SHIFT 8
02333 #define _CMU_LFAPRESC0_LCD_MASK 0x300UL
02334 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL
02335 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL
02336 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL
02337 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL
02338 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 8)
02339 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 8)
02340 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 8)
02341 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 8)
02343
02344 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
02345 #define _CMU_LFBPRESC0_MASK 0x00000033UL
02346 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
02347 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
02348 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
02349 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
02350 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
02351 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
02352 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
02353 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
02354 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
02355 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
02356 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4
02357 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL
02358 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL
02359 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL
02360 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL
02361 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL
02362 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)
02363 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)
02364 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)
02365 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)
02367
02368 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
02369 #define _CMU_PCNTCTRL_MASK 0x0000003FUL
02370 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
02371 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
02372 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
02373 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
02374 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
02375 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
02376 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
02377 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
02378 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
02379 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
02380 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
02381 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
02382 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
02383 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
02384 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2)
02385 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2
02386 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL
02387 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL
02388 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)
02389 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3)
02390 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3
02391 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL
02392 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL
02393 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL
02394 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL
02395 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)
02396 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)
02397 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)
02398 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4)
02399 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4
02400 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL
02401 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL
02402 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)
02403 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5)
02404 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5
02405 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL
02406 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL
02407 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL
02408 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL
02409 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)
02410 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)
02411 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)
02413
02414 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL
02415 #define _CMU_LCDCTRL_MASK 0x0000007FUL
02416 #define _CMU_LCDCTRL_FDIV_SHIFT 0
02417 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL
02418 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL
02419 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0)
02420 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3)
02421 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3
02422 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL
02423 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL
02424 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3)
02425 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4
02426 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL
02427 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL
02428 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL
02429 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL
02430 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL
02431 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL
02432 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL
02433 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL
02434 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL
02435 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL
02436 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)
02437 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)
02438 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)
02439 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)
02440 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)
02441 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)
02442 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)
02443 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)
02444 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)
02446
02447 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
02448 #define _CMU_ROUTE_MASK 0x00000007UL
02449 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
02450 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
02451 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
02452 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
02453 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
02454 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
02455 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
02456 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
02457 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
02458 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
02459 #define CMU_ROUTE_LOCATION (0x1UL << 2)
02460 #define _CMU_ROUTE_LOCATION_SHIFT 2
02461 #define _CMU_ROUTE_LOCATION_MASK 0x4UL
02462 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
02463 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
02464 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
02465 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
02466 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
02467 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
02469
02470 #define _CMU_LOCK_RESETVALUE 0x00000000UL
02471 #define _CMU_LOCK_MASK 0x0000FFFFUL
02472 #define _CMU_LOCK_LOCKKEY_SHIFT 0
02473 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
02474 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
02475 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
02476 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
02477 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
02478 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
02479 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
02480 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
02481 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
02482 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
02483 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
02488
02493
02494 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL
02495 #define _PRS_SWPULSE_MASK 0x000000FFUL
02496 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0)
02497 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0
02498 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL
02499 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL
02500 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)
02501 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1)
02502 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1
02503 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL
02504 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL
02505 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)
02506 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2)
02507 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2
02508 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL
02509 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL
02510 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)
02511 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3)
02512 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3
02513 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL
02514 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL
02515 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)
02516 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4)
02517 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4
02518 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL
02519 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL
02520 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)
02521 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5)
02522 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5
02523 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL
02524 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL
02525 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)
02526 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6)
02527 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6
02528 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL
02529 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL
02530 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)
02531 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7)
02532 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7
02533 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL
02534 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL
02535 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)
02537
02538 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL
02539 #define _PRS_SWLEVEL_MASK 0x000000FFUL
02540 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0)
02541 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0
02542 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL
02543 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL
02544 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)
02545 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1)
02546 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1
02547 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL
02548 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL
02549 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)
02550 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2)
02551 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2
02552 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL
02553 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL
02554 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)
02555 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3)
02556 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3
02557 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL
02558 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL
02559 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)
02560 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4)
02561 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4
02562 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL
02563 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL
02564 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)
02565 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5)
02566 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5
02567 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL
02568 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL
02569 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)
02570 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6)
02571 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6
02572 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL
02573 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL
02574 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)
02575 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7)
02576 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7
02577 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL
02578 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL
02579 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)
02581
02582 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL
02583 #define _PRS_CH_CTRL_MASK 0x033F0007UL
02584 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0
02585 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL
02586 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL
02587 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL
02588 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL
02589 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
02590 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
02591 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL
02592 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL
02593 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL
02594 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL
02595 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL
02596 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL
02597 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL
02598 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
02599 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
02600 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL
02601 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL
02602 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL
02603 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL
02604 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL
02605 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL
02606 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL
02607 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL
02608 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL
02609 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL
02610 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL
02611 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL
02612 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL
02613 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL
02614 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL
02615 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL
02616 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL
02617 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL
02618 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL
02619 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL
02620 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL
02621 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL
02622 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL
02623 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL
02624 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL
02625 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL
02626 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL
02627 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL
02628 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL
02629 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL
02630 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL
02631 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL
02632 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL
02633 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL
02634 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)
02635 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)
02636 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)
02637 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)
02638 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
02639 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)
02640 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)
02641 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)
02642 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)
02643 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)
02644 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)
02645 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)
02646 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)
02647 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)
02648 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)
02649 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)
02650 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0)
02651 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)
02652 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)
02653 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)
02654 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)
02655 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)
02656 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)
02657 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
02658 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
02659 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0)
02660 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
02661 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
02662 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
02663 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)
02664 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)
02665 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)
02666 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
02667 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
02668 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
02669 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)
02670 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)
02671 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
02672 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
02673 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
02674 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)
02675 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)
02676 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)
02677 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)
02678 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)
02679 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)
02680 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)
02681 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)
02682 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16
02683 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
02684 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL
02685 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL
02686 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL
02687 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL
02688 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL
02689 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
02690 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL
02691 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL
02692 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL
02693 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL
02694 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL
02695 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL
02696 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL
02697 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL
02698 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL
02699 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16)
02700 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)
02701 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)
02702 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)
02703 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)
02704 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)
02705 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)
02706 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)
02707 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16)
02708 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)
02709 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)
02710 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)
02711 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16)
02712 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)
02713 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)
02714 #define _PRS_CH_CTRL_EDSEL_SHIFT 24
02715 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL
02716 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL
02717 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL
02718 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL
02719 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL
02720 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL
02721 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)
02722 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24)
02723 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)
02724 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)
02725 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)
02731
02735 #define MSC_UNLOCK_CODE 0x1B71
02736 #define EMU_UNLOCK_CODE 0xADE8
02737 #define CMU_UNLOCK_CODE 0x580E
02738 #define TIMER_UNLOCK_CODE 0xCE80
02739 #define GPIO_UNLOCK_CODE 0xA534
02745
02750 #include "efm32g_af_ports.h"
02751 #include "efm32g_af_pins.h"
02752
02755
02768 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02769 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02770
02775 #ifdef __cplusplus
02776 }
02777 #endif
02778 #endif