em_wdog.c

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00001 /***************************************************************************/
00035 #include "em_wdog.h"
00036 #if defined(WDOG_COUNT) && (WDOG_COUNT > 0)
00037 
00038 #include "em_bitband.h"
00039 
00040 /***************************************************************************/
00045 /***************************************************************************/
00051 /*******************************************************************************
00052  **************************   GLOBAL FUNCTIONS   *******************************
00053  ******************************************************************************/
00054 
00055 /***************************************************************************/
00069 void WDOG_Enable(bool enable)
00070 {
00071   if (!enable)
00072   {
00073     /* Wait for any pending previous write operation to have been completed in */
00074     /* low frequency domain */
00075     while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
00076       ;
00077   }
00078   BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_EN_SHIFT, (unsigned int)enable);
00079 }
00080 
00081 
00082 /***************************************************************************/
00091 void WDOG_Feed(void)
00092 {
00093   /* The watchdog should not be fed while it is disabled */
00094   if ( !(WDOG->CTRL & WDOG_CTRL_EN) )
00095   {
00096     return;
00097   }
00098 
00099   /* If a previous clearing is being synchronized to LF domain, then there */
00100   /* is no point in waiting for it to complete before clearing over again. */
00101   /* This avoids stalling the core in the typical use case where some idle loop */
00102   /* keeps clearing the watchdog. */
00103   if (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CMD)
00104   {
00105     return;
00106   }
00107   /* Before writing to the WDOG_CMD register we also need to make sure that 
00108    * any previous write to WDOG_CTRL is complete. */
00109   while ( WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL );
00110 
00111   WDOG->CMD = WDOG_CMD_CLEAR;
00112 }
00113 
00114 
00115 /***************************************************************************/
00130 void WDOG_Init(const WDOG_Init_TypeDef *init)
00131 {
00132   uint32_t setting;
00133 
00134   if (init->enable)
00135   {
00136     setting = WDOG_CTRL_EN;
00137   }
00138   else
00139   {
00140     setting = 0;
00141   }
00142 
00143   if (init->debugRun)
00144   {
00145     setting |= WDOG_CTRL_DEBUGRUN;
00146   }
00147 
00148   if (init->em2Run)
00149   {
00150     setting |= WDOG_CTRL_EM2RUN;
00151   }
00152 
00153   if (init->em3Run)
00154   {
00155     setting |= WDOG_CTRL_EM3RUN;
00156   }
00157 
00158   if (init->em4Block)
00159   {
00160     setting |= WDOG_CTRL_EM4BLOCK;
00161   }
00162 
00163   if (init->swoscBlock)
00164   {
00165     setting |= WDOG_CTRL_SWOSCBLOCK;
00166   }
00167 
00168   setting |= ((uint32_t)(init->clkSel) << _WDOG_CTRL_CLKSEL_SHIFT) |
00169              ((uint32_t)(init->perSel) << _WDOG_CTRL_PERSEL_SHIFT);
00170 
00171   /* Wait for any pending previous write operation to have been completed in */
00172   /* low frequency domain */
00173   while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
00174     ;
00175 
00176   WDOG->CTRL = setting;
00177 
00178   /* Optional register locking */
00179   if (init->lock)
00180   {
00181     if (init->enable)
00182     {
00183       WDOG_Lock();
00184     }
00185     else
00186     {
00187       BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
00188     }
00189   }
00190 }
00191 
00192 
00193 /***************************************************************************/
00211 void WDOG_Lock(void)
00212 {
00213   /* Wait for any pending previous write operation to have been completed in */
00214   /* low frequency domain */
00215   while (WDOG->SYNCBUSY & WDOG_SYNCBUSY_CTRL)
00216     ;
00217 
00218   /* Disable writing to the control register */
00219   BITBAND_Peripheral(&(WDOG->CTRL), _WDOG_CTRL_LOCK_SHIFT, 1);
00220 }
00221 
00222 
00225 #endif /* defined(WDOG_COUNT) && (WDOG_COUNT > 0) */