00001
00032
00037 typedef struct
00038 {
00039 __IO uint32_t CTRL;
00040 __IO uint32_t HFCORECLKDIV;
00041 __IO uint32_t HFPERCLKDIV;
00042 __IO uint32_t HFRCOCTRL;
00043 __IO uint32_t LFRCOCTRL;
00044 __IO uint32_t AUXHFRCOCTRL;
00045 __IO uint32_t CALCTRL;
00046 __IO uint32_t CALCNT;
00047 __IO uint32_t OSCENCMD;
00048 __IO uint32_t CMD;
00049 __IO uint32_t LFCLKSEL;
00050 __I uint32_t STATUS;
00051 __I uint32_t IF;
00052 __IO uint32_t IFS;
00053 __IO uint32_t IFC;
00054 __IO uint32_t IEN;
00055 __IO uint32_t HFCORECLKEN0;
00056 __IO uint32_t HFPERCLKEN0;
00057 uint32_t RESERVED0[2];
00058 __I uint32_t SYNCBUSY;
00059 __IO uint32_t FREEZE;
00060 __IO uint32_t LFACLKEN0;
00061 uint32_t RESERVED1[1];
00062 __IO uint32_t LFBCLKEN0;
00063 uint32_t RESERVED2[1];
00064 __IO uint32_t LFAPRESC0;
00065 uint32_t RESERVED3[1];
00066 __IO uint32_t LFBPRESC0;
00067 uint32_t RESERVED4[1];
00068 __IO uint32_t PCNTCTRL;
00069 __IO uint32_t LCDCTRL;
00070 __IO uint32_t ROUTE;
00071 __IO uint32_t LOCK;
00072 } CMU_TypeDef;
00074
00079
00080 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
00081 #define _CMU_CTRL_MASK 0x00FE3EEFUL
00082 #define _CMU_CTRL_HFXOMODE_SHIFT 0
00083 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
00084 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
00085 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
00086 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
00087 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
00088 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
00089 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
00090 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
00091 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
00092 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
00093 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
00094 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
00095 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
00096 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
00097 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
00098 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
00099 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
00100 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
00101 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
00102 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
00103 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
00104 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
00105 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
00106 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
00107 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
00108 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
00109 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
00110 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
00111 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
00112 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
00113 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
00114 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
00115 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
00116 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
00117 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
00118 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
00119 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
00120 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
00121 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
00122 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
00123 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
00124 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
00125 #define _CMU_CTRL_LFXOMODE_SHIFT 11
00126 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
00127 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
00128 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
00129 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
00130 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
00131 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
00132 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
00133 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
00134 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
00135 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
00136 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
00137 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
00138 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
00139 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
00140 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
00141 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
00142 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
00143 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
00144 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
00145 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
00146 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
00147 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
00148 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
00149 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
00150 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
00151 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
00152 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
00153 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
00154 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
00155 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
00156 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
00157 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
00158 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
00159 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
00160 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
00161 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
00162 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
00163 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
00164 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
00165 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
00166 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
00167 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
00168 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
00169 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
00170 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
00171 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
00172 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
00173 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
00174 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
00175 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
00176 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
00177 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
00178 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
00179 #define CMU_CTRL_CLKOUTSEL1 (0x1UL << 23)
00180 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
00181 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL
00182 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
00183 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
00184 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
00185 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
00186 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
00187 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
00189
00190 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
00191 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
00192 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
00193 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
00194 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
00195 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
00196 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
00197 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
00198 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
00199 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
00200 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
00201 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
00202 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
00203 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
00204 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
00205 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
00206 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
00207 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
00208 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
00209 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
00210 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
00211 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
00212 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
00213 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
00214 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
00215 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
00217
00218 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
00219 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
00220 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
00221 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
00222 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
00223 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
00224 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
00225 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
00226 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
00227 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
00228 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
00229 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
00230 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
00231 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
00232 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
00233 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
00234 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
00235 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
00236 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
00237 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
00238 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
00239 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
00240 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
00241 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
00242 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
00243 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
00244 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
00245 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
00246 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
00247 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
00248 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
00250
00251 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
00252 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
00253 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
00254 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
00255 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00256 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
00257 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
00258 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
00259 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
00260 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
00261 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
00262 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
00263 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
00264 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
00265 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
00266 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
00267 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
00268 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
00269 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
00270 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
00271 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
00272 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
00273 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
00274 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
00275 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
00276 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
00278
00279 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
00280 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
00281 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
00282 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
00283 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
00284 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
00286
00287 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
00288 #define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL
00289 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
00290 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
00291 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00292 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
00294
00295 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
00296 #define _CMU_CALCTRL_MASK 0x00000007UL
00297 #define _CMU_CALCTRL_UPSEL_SHIFT 0
00298 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
00299 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
00300 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
00301 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
00302 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
00303 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
00304 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
00305 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
00306 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
00307 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
00308 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
00309 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
00310 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
00312
00313 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
00314 #define _CMU_CALCNT_MASK 0x000FFFFFUL
00315 #define _CMU_CALCNT_CALCNT_SHIFT 0
00316 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
00317 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
00318 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
00320
00321 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
00322 #define _CMU_OSCENCMD_MASK 0x000003FFUL
00323 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
00324 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
00325 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
00326 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
00327 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
00328 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
00329 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
00330 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
00331 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
00332 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
00333 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
00334 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
00335 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
00336 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
00337 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
00338 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
00339 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
00340 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
00341 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
00342 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
00343 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
00344 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
00345 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
00346 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
00347 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
00348 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
00349 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
00350 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
00351 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
00352 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
00353 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
00354 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
00355 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
00356 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
00357 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
00358 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
00359 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
00360 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
00361 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
00362 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
00363 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
00364 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
00365 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
00366 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
00367 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
00368 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
00369 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
00370 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
00371 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
00372 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
00374
00375 #define _CMU_CMD_RESETVALUE 0x00000000UL
00376 #define _CMU_CMD_MASK 0x0000000FUL
00377 #define _CMU_CMD_HFCLKSEL_SHIFT 0
00378 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
00379 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
00380 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
00381 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
00382 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
00383 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
00384 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
00385 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
00386 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
00387 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
00388 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
00389 #define CMU_CMD_CALSTART (0x1UL << 3)
00390 #define _CMU_CMD_CALSTART_SHIFT 3
00391 #define _CMU_CMD_CALSTART_MASK 0x8UL
00392 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
00393 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
00395
00396 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
00397 #define _CMU_LFCLKSEL_MASK 0x0000000FUL
00398 #define _CMU_LFCLKSEL_LFA_SHIFT 0
00399 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
00400 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
00401 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
00402 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
00403 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
00404 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
00405 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
00406 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
00407 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
00408 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
00409 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
00410 #define _CMU_LFCLKSEL_LFB_SHIFT 2
00411 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
00412 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
00413 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
00414 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
00415 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
00416 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
00417 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
00418 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
00419 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
00420 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
00421 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
00423
00424 #define _CMU_STATUS_RESETVALUE 0x00000403UL
00425 #define _CMU_STATUS_MASK 0x00007FFFUL
00426 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
00427 #define _CMU_STATUS_HFRCOENS_SHIFT 0
00428 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
00429 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
00430 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
00431 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
00432 #define _CMU_STATUS_HFRCORDY_SHIFT 1
00433 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
00434 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
00435 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
00436 #define CMU_STATUS_HFXOENS (0x1UL << 2)
00437 #define _CMU_STATUS_HFXOENS_SHIFT 2
00438 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
00439 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
00440 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
00441 #define CMU_STATUS_HFXORDY (0x1UL << 3)
00442 #define _CMU_STATUS_HFXORDY_SHIFT 3
00443 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
00444 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
00445 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
00446 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
00447 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
00448 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
00449 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
00450 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
00451 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
00452 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
00453 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
00454 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
00455 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
00456 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
00457 #define _CMU_STATUS_LFRCOENS_SHIFT 6
00458 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
00459 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
00460 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
00461 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
00462 #define _CMU_STATUS_LFRCORDY_SHIFT 7
00463 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
00464 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
00465 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
00466 #define CMU_STATUS_LFXOENS (0x1UL << 8)
00467 #define _CMU_STATUS_LFXOENS_SHIFT 8
00468 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
00469 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
00470 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
00471 #define CMU_STATUS_LFXORDY (0x1UL << 9)
00472 #define _CMU_STATUS_LFXORDY_SHIFT 9
00473 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
00474 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
00475 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
00476 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
00477 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
00478 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
00479 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
00480 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
00481 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
00482 #define _CMU_STATUS_HFXOSEL_SHIFT 11
00483 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
00484 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
00485 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
00486 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
00487 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
00488 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
00489 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
00490 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
00491 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
00492 #define _CMU_STATUS_LFXOSEL_SHIFT 13
00493 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
00494 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
00495 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
00496 #define CMU_STATUS_CALBSY (0x1UL << 14)
00497 #define _CMU_STATUS_CALBSY_SHIFT 14
00498 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
00499 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
00500 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
00502
00503 #define _CMU_IF_RESETVALUE 0x00000001UL
00504 #define _CMU_IF_MASK 0x0000003FUL
00505 #define CMU_IF_HFRCORDY (0x1UL << 0)
00506 #define _CMU_IF_HFRCORDY_SHIFT 0
00507 #define _CMU_IF_HFRCORDY_MASK 0x1UL
00508 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
00509 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
00510 #define CMU_IF_HFXORDY (0x1UL << 1)
00511 #define _CMU_IF_HFXORDY_SHIFT 1
00512 #define _CMU_IF_HFXORDY_MASK 0x2UL
00513 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
00514 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
00515 #define CMU_IF_LFRCORDY (0x1UL << 2)
00516 #define _CMU_IF_LFRCORDY_SHIFT 2
00517 #define _CMU_IF_LFRCORDY_MASK 0x4UL
00518 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
00519 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
00520 #define CMU_IF_LFXORDY (0x1UL << 3)
00521 #define _CMU_IF_LFXORDY_SHIFT 3
00522 #define _CMU_IF_LFXORDY_MASK 0x8UL
00523 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
00524 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
00525 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
00526 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
00527 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
00528 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
00529 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
00530 #define CMU_IF_CALRDY (0x1UL << 5)
00531 #define _CMU_IF_CALRDY_SHIFT 5
00532 #define _CMU_IF_CALRDY_MASK 0x20UL
00533 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
00534 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
00536
00537 #define _CMU_IFS_RESETVALUE 0x00000000UL
00538 #define _CMU_IFS_MASK 0x0000003FUL
00539 #define CMU_IFS_HFRCORDY (0x1UL << 0)
00540 #define _CMU_IFS_HFRCORDY_SHIFT 0
00541 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
00542 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
00543 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
00544 #define CMU_IFS_HFXORDY (0x1UL << 1)
00545 #define _CMU_IFS_HFXORDY_SHIFT 1
00546 #define _CMU_IFS_HFXORDY_MASK 0x2UL
00547 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
00548 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
00549 #define CMU_IFS_LFRCORDY (0x1UL << 2)
00550 #define _CMU_IFS_LFRCORDY_SHIFT 2
00551 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
00552 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
00553 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
00554 #define CMU_IFS_LFXORDY (0x1UL << 3)
00555 #define _CMU_IFS_LFXORDY_SHIFT 3
00556 #define _CMU_IFS_LFXORDY_MASK 0x8UL
00557 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
00558 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
00559 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
00560 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
00561 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
00562 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
00563 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
00564 #define CMU_IFS_CALRDY (0x1UL << 5)
00565 #define _CMU_IFS_CALRDY_SHIFT 5
00566 #define _CMU_IFS_CALRDY_MASK 0x20UL
00567 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
00568 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
00570
00571 #define _CMU_IFC_RESETVALUE 0x00000000UL
00572 #define _CMU_IFC_MASK 0x0000003FUL
00573 #define CMU_IFC_HFRCORDY (0x1UL << 0)
00574 #define _CMU_IFC_HFRCORDY_SHIFT 0
00575 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
00576 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
00577 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
00578 #define CMU_IFC_HFXORDY (0x1UL << 1)
00579 #define _CMU_IFC_HFXORDY_SHIFT 1
00580 #define _CMU_IFC_HFXORDY_MASK 0x2UL
00581 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
00582 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
00583 #define CMU_IFC_LFRCORDY (0x1UL << 2)
00584 #define _CMU_IFC_LFRCORDY_SHIFT 2
00585 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
00586 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
00587 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
00588 #define CMU_IFC_LFXORDY (0x1UL << 3)
00589 #define _CMU_IFC_LFXORDY_SHIFT 3
00590 #define _CMU_IFC_LFXORDY_MASK 0x8UL
00591 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
00592 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
00593 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
00594 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
00595 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
00596 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
00597 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
00598 #define CMU_IFC_CALRDY (0x1UL << 5)
00599 #define _CMU_IFC_CALRDY_SHIFT 5
00600 #define _CMU_IFC_CALRDY_MASK 0x20UL
00601 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
00602 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
00604
00605 #define _CMU_IEN_RESETVALUE 0x00000000UL
00606 #define _CMU_IEN_MASK 0x0000003FUL
00607 #define CMU_IEN_HFRCORDY (0x1UL << 0)
00608 #define _CMU_IEN_HFRCORDY_SHIFT 0
00609 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
00610 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
00611 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
00612 #define CMU_IEN_HFXORDY (0x1UL << 1)
00613 #define _CMU_IEN_HFXORDY_SHIFT 1
00614 #define _CMU_IEN_HFXORDY_MASK 0x2UL
00615 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
00616 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
00617 #define CMU_IEN_LFRCORDY (0x1UL << 2)
00618 #define _CMU_IEN_LFRCORDY_SHIFT 2
00619 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
00620 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
00621 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
00622 #define CMU_IEN_LFXORDY (0x1UL << 3)
00623 #define _CMU_IEN_LFXORDY_SHIFT 3
00624 #define _CMU_IEN_LFXORDY_MASK 0x8UL
00625 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
00626 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
00627 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
00628 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
00629 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
00630 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
00631 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
00632 #define CMU_IEN_CALRDY (0x1UL << 5)
00633 #define _CMU_IEN_CALRDY_SHIFT 5
00634 #define _CMU_IEN_CALRDY_MASK 0x20UL
00635 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
00636 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
00638
00639 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
00640 #define _CMU_HFCORECLKEN0_MASK 0x0000000FUL
00641 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
00642 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
00643 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
00644 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
00645 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
00646 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
00647 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
00648 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
00649 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
00650 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
00651 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
00652 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
00653 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
00654 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
00655 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
00656 #define CMU_HFCORECLKEN0_EBI (0x1UL << 3)
00657 #define _CMU_HFCORECLKEN0_EBI_SHIFT 3
00658 #define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL
00659 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL
00660 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3)
00662
00663 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
00664 #define _CMU_HFPERCLKEN0_MASK 0x0000FDFFUL
00665 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0)
00666 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0
00667 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL
00668 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
00669 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
00670 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1)
00671 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1
00672 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL
00673 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
00674 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
00675 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2)
00676 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2
00677 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL
00678 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL
00679 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
00680 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3)
00681 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3
00682 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL
00683 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL
00684 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)
00685 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
00686 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
00687 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
00688 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
00689 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
00690 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
00691 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
00692 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
00693 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
00694 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
00695 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 6)
00696 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 6
00697 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL
00698 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
00699 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 6)
00700 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7)
00701 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7
00702 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL
00703 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
00704 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)
00705 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8)
00706 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8
00707 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL
00708 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
00709 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)
00710 #define CMU_HFPERCLKEN0_PRS (0x1UL << 10)
00711 #define _CMU_HFPERCLKEN0_PRS_SHIFT 10
00712 #define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL
00713 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
00714 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)
00715 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 11)
00716 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 11
00717 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL
00718 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
00719 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)
00720 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 12)
00721 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 12
00722 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL
00723 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
00724 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)
00725 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 13)
00726 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 13
00727 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL
00728 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
00729 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)
00730 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 14)
00731 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 14
00732 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL
00733 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
00734 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)
00735 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 15)
00736 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 15
00737 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL
00738 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
00739 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)
00741
00742 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
00743 #define _CMU_SYNCBUSY_MASK 0x00000055UL
00744 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
00745 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
00746 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
00747 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
00748 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
00749 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
00750 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
00751 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
00752 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
00753 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
00754 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
00755 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
00756 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
00757 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
00758 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
00759 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
00760 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
00761 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
00762 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
00763 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
00765
00766 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
00767 #define _CMU_FREEZE_MASK 0x00000001UL
00768 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
00769 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
00770 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
00771 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
00772 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
00773 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
00774 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
00775 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
00776 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
00778
00779 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
00780 #define _CMU_LFACLKEN0_MASK 0x00000007UL
00781 #define CMU_LFACLKEN0_RTC (0x1UL << 0)
00782 #define _CMU_LFACLKEN0_RTC_SHIFT 0
00783 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL
00784 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
00785 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
00786 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 1)
00787 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 1
00788 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL
00789 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
00790 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1)
00791 #define CMU_LFACLKEN0_LCD (0x1UL << 2)
00792 #define _CMU_LFACLKEN0_LCD_SHIFT 2
00793 #define _CMU_LFACLKEN0_LCD_MASK 0x4UL
00794 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL
00795 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 2)
00797
00798 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
00799 #define _CMU_LFBCLKEN0_MASK 0x00000003UL
00800 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
00801 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
00802 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
00803 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
00804 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
00805 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1)
00806 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1
00807 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL
00808 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL
00809 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)
00811
00812 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
00813 #define _CMU_LFAPRESC0_MASK 0x000003FFUL
00814 #define _CMU_LFAPRESC0_RTC_SHIFT 0
00815 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL
00816 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
00817 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
00818 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
00819 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
00820 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
00821 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
00822 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
00823 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
00824 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
00825 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
00826 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
00827 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
00828 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
00829 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
00830 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
00831 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
00832 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
00833 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
00834 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
00835 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
00836 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
00837 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
00838 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
00839 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
00840 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
00841 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
00842 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
00843 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
00844 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
00845 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
00846 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
00847 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
00848 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 4
00849 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL
00850 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
00851 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
00852 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
00853 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
00854 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
00855 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
00856 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
00857 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
00858 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
00859 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
00860 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
00861 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
00862 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
00863 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
00864 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
00865 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
00866 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)
00867 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)
00868 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)
00869 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)
00870 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)
00871 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)
00872 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)
00873 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)
00874 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)
00875 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)
00876 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)
00877 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)
00878 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)
00879 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)
00880 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4)
00881 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4)
00882 #define _CMU_LFAPRESC0_LCD_SHIFT 8
00883 #define _CMU_LFAPRESC0_LCD_MASK 0x300UL
00884 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL
00885 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL
00886 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL
00887 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL
00888 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 8)
00889 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 8)
00890 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 8)
00891 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 8)
00893
00894 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
00895 #define _CMU_LFBPRESC0_MASK 0x00000033UL
00896 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
00897 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
00898 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
00899 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
00900 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
00901 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
00902 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
00903 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
00904 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
00905 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
00906 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4
00907 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL
00908 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL
00909 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL
00910 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL
00911 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL
00912 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)
00913 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)
00914 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)
00915 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)
00917
00918 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
00919 #define _CMU_PCNTCTRL_MASK 0x0000003FUL
00920 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
00921 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
00922 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
00923 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
00924 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
00925 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
00926 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
00927 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
00928 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
00929 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
00930 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
00931 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
00932 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
00933 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
00934 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2)
00935 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2
00936 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL
00937 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL
00938 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)
00939 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3)
00940 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3
00941 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL
00942 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL
00943 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL
00944 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL
00945 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)
00946 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)
00947 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)
00948 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4)
00949 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4
00950 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL
00951 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL
00952 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)
00953 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5)
00954 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5
00955 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL
00956 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL
00957 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL
00958 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL
00959 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)
00960 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)
00961 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)
00963
00964 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL
00965 #define _CMU_LCDCTRL_MASK 0x0000007FUL
00966 #define _CMU_LCDCTRL_FDIV_SHIFT 0
00967 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL
00968 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL
00969 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0)
00970 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3)
00971 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3
00972 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL
00973 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL
00974 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3)
00975 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4
00976 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL
00977 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL
00978 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL
00979 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL
00980 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL
00981 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL
00982 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL
00983 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL
00984 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL
00985 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL
00986 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)
00987 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)
00988 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)
00989 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)
00990 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)
00991 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)
00992 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)
00993 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)
00994 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)
00996
00997 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
00998 #define _CMU_ROUTE_MASK 0x00000007UL
00999 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
01000 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
01001 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
01002 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
01003 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
01004 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
01005 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
01006 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
01007 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
01008 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
01009 #define CMU_ROUTE_LOCATION (0x1UL << 2)
01010 #define _CMU_ROUTE_LOCATION_SHIFT 2
01011 #define _CMU_ROUTE_LOCATION_MASK 0x4UL
01012 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
01013 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
01014 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
01015 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
01016 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
01017 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
01019
01020 #define _CMU_LOCK_RESETVALUE 0x00000000UL
01021 #define _CMU_LOCK_MASK 0x0000FFFFUL
01022 #define _CMU_LOCK_LOCKKEY_SHIFT 0
01023 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
01024 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
01025 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
01026 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
01027 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
01028 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
01029 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
01030 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
01031 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
01032 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
01033 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)