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Data Structures | |
struct | DMA_TypeDef |
struct | CMU_TypeDef |
struct | PRS_TypeDef |
Defines | |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 3 |
#define | __Vendor_SysTickConfig 0 |
#define | _EFM32_GECKO_FAMILY 1 |
#define | _EFM_DEVICE |
#define | _SILICON_LABS_32B_PLATFORM_1 |
#define | _SILICON_LABS_32B_PLATFORM 1 |
#define | EFM32G200F16 1 |
#define | PART_NUMBER "EFM32G200F16" |
#define | FLASH_MEM_BASE ((uint32_t) 0x0UL) |
#define | FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) |
#define | FLASH_MEM_BITS ((uint32_t) 0x28UL) |
#define | AES_MEM_BASE ((uint32_t) 0x400E0000UL) |
#define | AES_MEM_SIZE ((uint32_t) 0x400UL) |
#define | AES_MEM_END ((uint32_t) 0x400E03FFUL) |
#define | AES_MEM_BITS ((uint32_t) 0x10UL) |
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) |
#define | PER_MEM_SIZE ((uint32_t) 0xE0000UL) |
#define | PER_MEM_END ((uint32_t) 0x400DFFFFUL) |
#define | PER_MEM_BITS ((uint32_t) 0x20UL) |
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) |
#define | RAM_MEM_SIZE ((uint32_t) 0x8000UL) |
#define | RAM_MEM_END ((uint32_t) 0x20007FFFUL) |
#define | RAM_MEM_BITS ((uint32_t) 0x15UL) |
#define | RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) |
#define | RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL) |
#define | RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL) |
#define | RAM_CODE_MEM_BITS ((uint32_t) 0x14UL) |
#define | EBI_MEM_BASE ((uint32_t) 0x80000000UL) |
#define | EBI_MEM_SIZE ((uint32_t) 0x10000000UL) |
#define | EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL) |
#define | EBI_MEM_BITS ((uint32_t) 0x28UL) |
#define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) |
#define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) |
#define | FLASH_BASE (0x00000000UL) |
#define | FLASH_SIZE (0x00004000UL) |
#define | FLASH_PAGE_SIZE 512 |
#define | SRAM_BASE (0x20000000UL) |
#define | SRAM_SIZE (0x00002000UL) |
#define | __CM3_REV 0x200 |
#define | PRS_CHAN_COUNT 8 |
#define | DMA_CHAN_COUNT 8 |
#define | AFCHAN_MAX 79 |
#define | AFCHANLOC_MAX 4 |
#define | AFACHAN_MAX 37 |
#define | TIMER_PRESENT |
#define | TIMER_COUNT 2 |
#define | USART_PRESENT |
#define | USART_COUNT 2 |
#define | LEUART_PRESENT |
#define | LEUART_COUNT 1 |
#define | LETIMER_PRESENT |
#define | LETIMER_COUNT 1 |
#define | PCNT_PRESENT |
#define | PCNT_COUNT 1 |
#define | ACMP_PRESENT |
#define | ACMP_COUNT 2 |
#define | DAC_PRESENT |
#define | DAC_COUNT 1 |
#define | ADC_PRESENT |
#define | ADC_COUNT 1 |
#define | I2C_PRESENT |
#define | I2C_COUNT 1 |
#define | DMA_PRESENT |
#define | DMA_COUNT 1 |
#define | LE_PRESENT |
#define | LE_COUNT 1 |
#define | MSC_PRESENT |
#define | MSC_COUNT 1 |
#define | EMU_PRESENT |
#define | EMU_COUNT 1 |
#define | RMU_PRESENT |
#define | RMU_COUNT 1 |
#define | CMU_PRESENT |
#define | CMU_COUNT 1 |
#define | RTC_PRESENT |
#define | RTC_COUNT 1 |
#define | PRS_PRESENT |
#define | PRS_COUNT 1 |
#define | GPIO_PRESENT |
#define | GPIO_COUNT 1 |
#define | VCMP_PRESENT |
#define | VCMP_COUNT 1 |
#define | HFXTAL_PRESENT |
#define | HFXTAL_COUNT 1 |
#define | LFXTAL_PRESENT |
#define | LFXTAL_COUNT 1 |
#define | WDOG_PRESENT |
#define | WDOG_COUNT 1 |
#define | DBG_PRESENT |
#define | DBG_COUNT 1 |
#define | BOOTLOADER_PRESENT |
#define | BOOTLOADER_COUNT 1 |
#define | ANALOG_PRESENT |
#define | ANALOG_COUNT 1 |
#define | DMA_BASE (0x400C2000UL) |
#define | MSC_BASE (0x400C0000UL) |
#define | EMU_BASE (0x400C6000UL) |
#define | RMU_BASE (0x400CA000UL) |
#define | CMU_BASE (0x400C8000UL) |
#define | TIMER0_BASE (0x40010000UL) |
#define | TIMER1_BASE (0x40010400UL) |
#define | USART0_BASE (0x4000C000UL) |
#define | USART1_BASE (0x4000C400UL) |
#define | LEUART0_BASE (0x40084000UL) |
#define | RTC_BASE (0x40080000UL) |
#define | LETIMER0_BASE (0x40082000UL) |
#define | PCNT0_BASE (0x40086000UL) |
#define | ACMP0_BASE (0x40001000UL) |
#define | ACMP1_BASE (0x40001400UL) |
#define | PRS_BASE (0x400CC000UL) |
#define | DAC0_BASE (0x40004000UL) |
#define | GPIO_BASE (0x40006000UL) |
#define | VCMP_BASE (0x40000000UL) |
#define | ADC0_BASE (0x40002000UL) |
#define | I2C0_BASE (0x4000A000UL) |
#define | WDOG_BASE (0x40088000UL) |
#define | CALIBRATE_BASE (0x0FE08000UL) |
#define | DEVINFO_BASE (0x0FE081B0UL) |
#define | ROMTABLE_BASE (0xE00FFFD0UL) |
#define | LOCKBITS_BASE (0x0FE04000UL) |
#define | USERDATA_BASE (0x0FE00000UL) |
#define | DMA ((DMA_TypeDef *) DMA_BASE) |
#define | MSC ((MSC_TypeDef *) MSC_BASE) |
#define | EMU ((EMU_TypeDef *) EMU_BASE) |
#define | RMU ((RMU_TypeDef *) RMU_BASE) |
#define | CMU ((CMU_TypeDef *) CMU_BASE) |
#define | TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) |
#define | TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) |
#define | USART0 ((USART_TypeDef *) USART0_BASE) |
#define | USART1 ((USART_TypeDef *) USART1_BASE) |
#define | LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) |
#define | RTC ((RTC_TypeDef *) RTC_BASE) |
#define | LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) |
#define | PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) |
#define | ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) |
#define | ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) |
#define | PRS ((PRS_TypeDef *) PRS_BASE) |
#define | DAC0 ((DAC_TypeDef *) DAC0_BASE) |
#define | GPIO ((GPIO_TypeDef *) GPIO_BASE) |
#define | VCMP ((VCMP_TypeDef *) VCMP_BASE) |
#define | ADC0 ((ADC_TypeDef *) ADC0_BASE) |
#define | I2C0 ((I2C_TypeDef *) I2C0_BASE) |
#define | WDOG ((WDOG_TypeDef *) WDOG_BASE) |
#define | CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) |
#define | DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) |
#define | ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) |
#define | PRS_VCMP_OUT ((1 << 16) + 0) |
#define | PRS_ACMP0_OUT ((2 << 16) + 0) |
#define | PRS_ACMP1_OUT ((3 << 16) + 0) |
#define | PRS_DAC0_CH0 ((6 << 16) + 0) |
#define | PRS_DAC0_CH1 ((6 << 16) + 1) |
#define | PRS_ADC0_SINGLE ((8 << 16) + 0) |
#define | PRS_ADC0_SCAN ((8 << 16) + 1) |
#define | PRS_USART0_IRTX ((16 << 16) + 0) |
#define | PRS_USART0_TXC ((16 << 16) + 1) |
#define | PRS_USART0_RXDATAV ((16 << 16) + 2) |
#define | PRS_USART1_IRTX ((17 << 16) + 0) |
#define | PRS_USART1_TXC ((17 << 16) + 1) |
#define | PRS_USART1_RXDATAV ((17 << 16) + 2) |
#define | PRS_TIMER0_UF ((28 << 16) + 0) |
#define | PRS_TIMER0_OF ((28 << 16) + 1) |
#define | PRS_TIMER0_CC0 ((28 << 16) + 2) |
#define | PRS_TIMER0_CC1 ((28 << 16) + 3) |
#define | PRS_TIMER0_CC2 ((28 << 16) + 4) |
#define | PRS_TIMER1_UF ((29 << 16) + 0) |
#define | PRS_TIMER1_OF ((29 << 16) + 1) |
#define | PRS_TIMER1_CC0 ((29 << 16) + 2) |
#define | PRS_TIMER1_CC1 ((29 << 16) + 3) |
#define | PRS_TIMER1_CC2 ((29 << 16) + 4) |
#define | PRS_RTC_OF ((40 << 16) + 0) |
#define | PRS_RTC_COMP0 ((40 << 16) + 1) |
#define | PRS_RTC_COMP1 ((40 << 16) + 2) |
#define | PRS_GPIO_PIN0 ((48 << 16) + 0) |
#define | PRS_GPIO_PIN1 ((48 << 16) + 1) |
#define | PRS_GPIO_PIN2 ((48 << 16) + 2) |
#define | PRS_GPIO_PIN3 ((48 << 16) + 3) |
#define | PRS_GPIO_PIN4 ((48 << 16) + 4) |
#define | PRS_GPIO_PIN5 ((48 << 16) + 5) |
#define | PRS_GPIO_PIN6 ((48 << 16) + 6) |
#define | PRS_GPIO_PIN7 ((48 << 16) + 7) |
#define | PRS_GPIO_PIN8 ((49 << 16) + 0) |
#define | PRS_GPIO_PIN9 ((49 << 16) + 1) |
#define | PRS_GPIO_PIN10 ((49 << 16) + 2) |
#define | PRS_GPIO_PIN11 ((49 << 16) + 3) |
#define | PRS_GPIO_PIN12 ((49 << 16) + 4) |
#define | PRS_GPIO_PIN13 ((49 << 16) + 5) |
#define | PRS_GPIO_PIN14 ((49 << 16) + 6) |
#define | PRS_GPIO_PIN15 ((49 << 16) + 7) |
#define | _DMA_STATUS_RESETVALUE 0x10070000UL |
#define | _DMA_STATUS_MASK 0x001F00F1UL |
#define | DMA_STATUS_EN (0x1UL << 0) |
#define | _DMA_STATUS_EN_SHIFT 0 |
#define | _DMA_STATUS_EN_MASK 0x1UL |
#define | _DMA_STATUS_EN_DEFAULT 0x00000000UL |
#define | DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) |
#define | _DMA_STATUS_STATE_SHIFT 4 |
#define | _DMA_STATUS_STATE_MASK 0xF0UL |
#define | _DMA_STATUS_STATE_DEFAULT 0x00000000UL |
#define | _DMA_STATUS_STATE_IDLE 0x00000000UL |
#define | _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL |
#define | _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL |
#define | _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL |
#define | _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL |
#define | _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL |
#define | _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL |
#define | _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL |
#define | _DMA_STATUS_STATE_STALLED 0x00000008UL |
#define | _DMA_STATUS_STATE_DONE 0x00000009UL |
#define | _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL |
#define | DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) |
#define | DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) |
#define | DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) |
#define | DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) |
#define | DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) |
#define | DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) |
#define | DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) |
#define | DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) |
#define | DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) |
#define | DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) |
#define | DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) |
#define | DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) |
#define | _DMA_STATUS_CHNUM_SHIFT 16 |
#define | _DMA_STATUS_CHNUM_MASK 0x1F0000UL |
#define | _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL |
#define | DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) |
#define | _DMA_CONFIG_RESETVALUE 0x00000000UL |
#define | _DMA_CONFIG_MASK 0x00000021UL |
#define | DMA_CONFIG_EN (0x1UL << 0) |
#define | _DMA_CONFIG_EN_SHIFT 0 |
#define | _DMA_CONFIG_EN_MASK 0x1UL |
#define | _DMA_CONFIG_EN_DEFAULT 0x00000000UL |
#define | DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) |
#define | DMA_CONFIG_CHPROT (0x1UL << 5) |
#define | _DMA_CONFIG_CHPROT_SHIFT 5 |
#define | _DMA_CONFIG_CHPROT_MASK 0x20UL |
#define | _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL |
#define | DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) |
#define | _DMA_CTRLBASE_RESETVALUE 0x00000000UL |
#define | _DMA_CTRLBASE_MASK 0xFFFFFFFFUL |
#define | _DMA_CTRLBASE_CTRLBASE_SHIFT 0 |
#define | _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL |
#define | _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL |
#define | DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) |
#define | _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL |
#define | _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL |
#define | _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 |
#define | _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL |
#define | _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL |
#define | DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) |
#define | _DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL |
#define | _DMA_CHWAITSTATUS_MASK 0x000000FFUL |
#define | DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) |
#define | _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 |
#define | _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL |
#define | _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) |
#define | DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) |
#define | _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 |
#define | _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL |
#define | _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) |
#define | DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) |
#define | _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 |
#define | _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL |
#define | _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) |
#define | DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) |
#define | _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 |
#define | _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL |
#define | _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) |
#define | DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) |
#define | _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 |
#define | _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL |
#define | _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) |
#define | DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) |
#define | _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 |
#define | _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL |
#define | _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) |
#define | DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) |
#define | _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 |
#define | _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL |
#define | _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) |
#define | DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) |
#define | _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 |
#define | _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL |
#define | _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL |
#define | DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) |
#define | _DMA_CHSWREQ_RESETVALUE 0x00000000UL |
#define | _DMA_CHSWREQ_MASK 0x000000FFUL |
#define | DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) |
#define | _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 |
#define | _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL |
#define | _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) |
#define | DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) |
#define | _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 |
#define | _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL |
#define | _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) |
#define | DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) |
#define | _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 |
#define | _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL |
#define | _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) |
#define | DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) |
#define | _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 |
#define | _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL |
#define | _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) |
#define | DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) |
#define | _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 |
#define | _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL |
#define | _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) |
#define | DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) |
#define | _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 |
#define | _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL |
#define | _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) |
#define | DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) |
#define | _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 |
#define | _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL |
#define | _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) |
#define | DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) |
#define | _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 |
#define | _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL |
#define | _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL |
#define | DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) |
#define | _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL |
#define | _DMA_CHUSEBURSTS_MASK 0x000000FFUL |
#define | DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) |
#define | _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 |
#define | _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL |
#define | _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL |
#define | _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL |
#define | _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL |
#define | DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) |
#define | DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) |
#define | DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) |
#define | DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) |
#define | _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 |
#define | _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL |
#define | _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) |
#define | DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) |
#define | _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 |
#define | _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL |
#define | _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) |
#define | DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) |
#define | _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 |
#define | _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL |
#define | _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) |
#define | DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) |
#define | _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 |
#define | _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL |
#define | _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) |
#define | DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) |
#define | _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 |
#define | _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL |
#define | _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) |
#define | DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) |
#define | _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 |
#define | _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL |
#define | _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) |
#define | DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) |
#define | _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 |
#define | _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL |
#define | _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) |
#define | _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL |
#define | _DMA_CHUSEBURSTC_MASK 0x000000FFUL |
#define | DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) |
#define | _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 |
#define | _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL |
#define | _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) |
#define | DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) |
#define | _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 |
#define | _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL |
#define | _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) |
#define | DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) |
#define | _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 |
#define | _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL |
#define | _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) |
#define | DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) |
#define | _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 |
#define | _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL |
#define | _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) |
#define | DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) |
#define | _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 |
#define | _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL |
#define | _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) |
#define | DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) |
#define | _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 |
#define | _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL |
#define | _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) |
#define | DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) |
#define | _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 |
#define | _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL |
#define | _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) |
#define | DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) |
#define | _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 |
#define | _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL |
#define | _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL |
#define | DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) |
#define | _DMA_CHREQMASKS_RESETVALUE 0x00000000UL |
#define | _DMA_CHREQMASKS_MASK 0x000000FFUL |
#define | DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) |
#define | _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 |
#define | _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL |
#define | _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) |
#define | DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) |
#define | _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 |
#define | _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL |
#define | _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) |
#define | DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) |
#define | _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 |
#define | _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL |
#define | _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) |
#define | DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) |
#define | _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 |
#define | _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL |
#define | _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) |
#define | DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) |
#define | _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 |
#define | _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL |
#define | _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) |
#define | DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) |
#define | _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 |
#define | _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL |
#define | _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) |
#define | DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) |
#define | _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 |
#define | _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL |
#define | _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) |
#define | DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) |
#define | _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 |
#define | _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL |
#define | _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) |
#define | _DMA_CHREQMASKC_RESETVALUE 0x00000000UL |
#define | _DMA_CHREQMASKC_MASK 0x000000FFUL |
#define | DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) |
#define | _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 |
#define | _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL |
#define | _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) |
#define | DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) |
#define | _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 |
#define | _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL |
#define | _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) |
#define | DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) |
#define | _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 |
#define | _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL |
#define | _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) |
#define | DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) |
#define | _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 |
#define | _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL |
#define | _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) |
#define | DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) |
#define | _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 |
#define | _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL |
#define | _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) |
#define | DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) |
#define | _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 |
#define | _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL |
#define | _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) |
#define | DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) |
#define | _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 |
#define | _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL |
#define | _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) |
#define | DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) |
#define | _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 |
#define | _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL |
#define | _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL |
#define | DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) |
#define | _DMA_CHENS_RESETVALUE 0x00000000UL |
#define | _DMA_CHENS_MASK 0x000000FFUL |
#define | DMA_CHENS_CH0ENS (0x1UL << 0) |
#define | _DMA_CHENS_CH0ENS_SHIFT 0 |
#define | _DMA_CHENS_CH0ENS_MASK 0x1UL |
#define | _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) |
#define | DMA_CHENS_CH1ENS (0x1UL << 1) |
#define | _DMA_CHENS_CH1ENS_SHIFT 1 |
#define | _DMA_CHENS_CH1ENS_MASK 0x2UL |
#define | _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) |
#define | DMA_CHENS_CH2ENS (0x1UL << 2) |
#define | _DMA_CHENS_CH2ENS_SHIFT 2 |
#define | _DMA_CHENS_CH2ENS_MASK 0x4UL |
#define | _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) |
#define | DMA_CHENS_CH3ENS (0x1UL << 3) |
#define | _DMA_CHENS_CH3ENS_SHIFT 3 |
#define | _DMA_CHENS_CH3ENS_MASK 0x8UL |
#define | _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) |
#define | DMA_CHENS_CH4ENS (0x1UL << 4) |
#define | _DMA_CHENS_CH4ENS_SHIFT 4 |
#define | _DMA_CHENS_CH4ENS_MASK 0x10UL |
#define | _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) |
#define | DMA_CHENS_CH5ENS (0x1UL << 5) |
#define | _DMA_CHENS_CH5ENS_SHIFT 5 |
#define | _DMA_CHENS_CH5ENS_MASK 0x20UL |
#define | _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) |
#define | DMA_CHENS_CH6ENS (0x1UL << 6) |
#define | _DMA_CHENS_CH6ENS_SHIFT 6 |
#define | _DMA_CHENS_CH6ENS_MASK 0x40UL |
#define | _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) |
#define | DMA_CHENS_CH7ENS (0x1UL << 7) |
#define | _DMA_CHENS_CH7ENS_SHIFT 7 |
#define | _DMA_CHENS_CH7ENS_MASK 0x80UL |
#define | _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL |
#define | DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) |
#define | _DMA_CHENC_RESETVALUE 0x00000000UL |
#define | _DMA_CHENC_MASK 0x000000FFUL |
#define | DMA_CHENC_CH0ENC (0x1UL << 0) |
#define | _DMA_CHENC_CH0ENC_SHIFT 0 |
#define | _DMA_CHENC_CH0ENC_MASK 0x1UL |
#define | _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) |
#define | DMA_CHENC_CH1ENC (0x1UL << 1) |
#define | _DMA_CHENC_CH1ENC_SHIFT 1 |
#define | _DMA_CHENC_CH1ENC_MASK 0x2UL |
#define | _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) |
#define | DMA_CHENC_CH2ENC (0x1UL << 2) |
#define | _DMA_CHENC_CH2ENC_SHIFT 2 |
#define | _DMA_CHENC_CH2ENC_MASK 0x4UL |
#define | _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) |
#define | DMA_CHENC_CH3ENC (0x1UL << 3) |
#define | _DMA_CHENC_CH3ENC_SHIFT 3 |
#define | _DMA_CHENC_CH3ENC_MASK 0x8UL |
#define | _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) |
#define | DMA_CHENC_CH4ENC (0x1UL << 4) |
#define | _DMA_CHENC_CH4ENC_SHIFT 4 |
#define | _DMA_CHENC_CH4ENC_MASK 0x10UL |
#define | _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) |
#define | DMA_CHENC_CH5ENC (0x1UL << 5) |
#define | _DMA_CHENC_CH5ENC_SHIFT 5 |
#define | _DMA_CHENC_CH5ENC_MASK 0x20UL |
#define | _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) |
#define | DMA_CHENC_CH6ENC (0x1UL << 6) |
#define | _DMA_CHENC_CH6ENC_SHIFT 6 |
#define | _DMA_CHENC_CH6ENC_MASK 0x40UL |
#define | _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) |
#define | DMA_CHENC_CH7ENC (0x1UL << 7) |
#define | _DMA_CHENC_CH7ENC_SHIFT 7 |
#define | _DMA_CHENC_CH7ENC_MASK 0x80UL |
#define | _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL |
#define | DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) |
#define | _DMA_CHALTS_RESETVALUE 0x00000000UL |
#define | _DMA_CHALTS_MASK 0x000000FFUL |
#define | DMA_CHALTS_CH0ALTS (0x1UL << 0) |
#define | _DMA_CHALTS_CH0ALTS_SHIFT 0 |
#define | _DMA_CHALTS_CH0ALTS_MASK 0x1UL |
#define | _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) |
#define | DMA_CHALTS_CH1ALTS (0x1UL << 1) |
#define | _DMA_CHALTS_CH1ALTS_SHIFT 1 |
#define | _DMA_CHALTS_CH1ALTS_MASK 0x2UL |
#define | _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) |
#define | DMA_CHALTS_CH2ALTS (0x1UL << 2) |
#define | _DMA_CHALTS_CH2ALTS_SHIFT 2 |
#define | _DMA_CHALTS_CH2ALTS_MASK 0x4UL |
#define | _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) |
#define | DMA_CHALTS_CH3ALTS (0x1UL << 3) |
#define | _DMA_CHALTS_CH3ALTS_SHIFT 3 |
#define | _DMA_CHALTS_CH3ALTS_MASK 0x8UL |
#define | _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) |
#define | DMA_CHALTS_CH4ALTS (0x1UL << 4) |
#define | _DMA_CHALTS_CH4ALTS_SHIFT 4 |
#define | _DMA_CHALTS_CH4ALTS_MASK 0x10UL |
#define | _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) |
#define | DMA_CHALTS_CH5ALTS (0x1UL << 5) |
#define | _DMA_CHALTS_CH5ALTS_SHIFT 5 |
#define | _DMA_CHALTS_CH5ALTS_MASK 0x20UL |
#define | _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) |
#define | DMA_CHALTS_CH6ALTS (0x1UL << 6) |
#define | _DMA_CHALTS_CH6ALTS_SHIFT 6 |
#define | _DMA_CHALTS_CH6ALTS_MASK 0x40UL |
#define | _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) |
#define | DMA_CHALTS_CH7ALTS (0x1UL << 7) |
#define | _DMA_CHALTS_CH7ALTS_SHIFT 7 |
#define | _DMA_CHALTS_CH7ALTS_MASK 0x80UL |
#define | _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL |
#define | DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) |
#define | _DMA_CHALTC_RESETVALUE 0x00000000UL |
#define | _DMA_CHALTC_MASK 0x000000FFUL |
#define | DMA_CHALTC_CH0ALTC (0x1UL << 0) |
#define | _DMA_CHALTC_CH0ALTC_SHIFT 0 |
#define | _DMA_CHALTC_CH0ALTC_MASK 0x1UL |
#define | _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) |
#define | DMA_CHALTC_CH1ALTC (0x1UL << 1) |
#define | _DMA_CHALTC_CH1ALTC_SHIFT 1 |
#define | _DMA_CHALTC_CH1ALTC_MASK 0x2UL |
#define | _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) |
#define | DMA_CHALTC_CH2ALTC (0x1UL << 2) |
#define | _DMA_CHALTC_CH2ALTC_SHIFT 2 |
#define | _DMA_CHALTC_CH2ALTC_MASK 0x4UL |
#define | _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) |
#define | DMA_CHALTC_CH3ALTC (0x1UL << 3) |
#define | _DMA_CHALTC_CH3ALTC_SHIFT 3 |
#define | _DMA_CHALTC_CH3ALTC_MASK 0x8UL |
#define | _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) |
#define | DMA_CHALTC_CH4ALTC (0x1UL << 4) |
#define | _DMA_CHALTC_CH4ALTC_SHIFT 4 |
#define | _DMA_CHALTC_CH4ALTC_MASK 0x10UL |
#define | _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) |
#define | DMA_CHALTC_CH5ALTC (0x1UL << 5) |
#define | _DMA_CHALTC_CH5ALTC_SHIFT 5 |
#define | _DMA_CHALTC_CH5ALTC_MASK 0x20UL |
#define | _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) |
#define | DMA_CHALTC_CH6ALTC (0x1UL << 6) |
#define | _DMA_CHALTC_CH6ALTC_SHIFT 6 |
#define | _DMA_CHALTC_CH6ALTC_MASK 0x40UL |
#define | _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) |
#define | DMA_CHALTC_CH7ALTC (0x1UL << 7) |
#define | _DMA_CHALTC_CH7ALTC_SHIFT 7 |
#define | _DMA_CHALTC_CH7ALTC_MASK 0x80UL |
#define | _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL |
#define | DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) |
#define | _DMA_CHPRIS_RESETVALUE 0x00000000UL |
#define | _DMA_CHPRIS_MASK 0x000000FFUL |
#define | DMA_CHPRIS_CH0PRIS (0x1UL << 0) |
#define | _DMA_CHPRIS_CH0PRIS_SHIFT 0 |
#define | _DMA_CHPRIS_CH0PRIS_MASK 0x1UL |
#define | _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) |
#define | DMA_CHPRIS_CH1PRIS (0x1UL << 1) |
#define | _DMA_CHPRIS_CH1PRIS_SHIFT 1 |
#define | _DMA_CHPRIS_CH1PRIS_MASK 0x2UL |
#define | _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) |
#define | DMA_CHPRIS_CH2PRIS (0x1UL << 2) |
#define | _DMA_CHPRIS_CH2PRIS_SHIFT 2 |
#define | _DMA_CHPRIS_CH2PRIS_MASK 0x4UL |
#define | _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) |
#define | DMA_CHPRIS_CH3PRIS (0x1UL << 3) |
#define | _DMA_CHPRIS_CH3PRIS_SHIFT 3 |
#define | _DMA_CHPRIS_CH3PRIS_MASK 0x8UL |
#define | _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) |
#define | DMA_CHPRIS_CH4PRIS (0x1UL << 4) |
#define | _DMA_CHPRIS_CH4PRIS_SHIFT 4 |
#define | _DMA_CHPRIS_CH4PRIS_MASK 0x10UL |
#define | _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) |
#define | DMA_CHPRIS_CH5PRIS (0x1UL << 5) |
#define | _DMA_CHPRIS_CH5PRIS_SHIFT 5 |
#define | _DMA_CHPRIS_CH5PRIS_MASK 0x20UL |
#define | _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) |
#define | DMA_CHPRIS_CH6PRIS (0x1UL << 6) |
#define | _DMA_CHPRIS_CH6PRIS_SHIFT 6 |
#define | _DMA_CHPRIS_CH6PRIS_MASK 0x40UL |
#define | _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) |
#define | DMA_CHPRIS_CH7PRIS (0x1UL << 7) |
#define | _DMA_CHPRIS_CH7PRIS_SHIFT 7 |
#define | _DMA_CHPRIS_CH7PRIS_MASK 0x80UL |
#define | _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL |
#define | DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) |
#define | _DMA_CHPRIC_RESETVALUE 0x00000000UL |
#define | _DMA_CHPRIC_MASK 0x000000FFUL |
#define | DMA_CHPRIC_CH0PRIC (0x1UL << 0) |
#define | _DMA_CHPRIC_CH0PRIC_SHIFT 0 |
#define | _DMA_CHPRIC_CH0PRIC_MASK 0x1UL |
#define | _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) |
#define | DMA_CHPRIC_CH1PRIC (0x1UL << 1) |
#define | _DMA_CHPRIC_CH1PRIC_SHIFT 1 |
#define | _DMA_CHPRIC_CH1PRIC_MASK 0x2UL |
#define | _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) |
#define | DMA_CHPRIC_CH2PRIC (0x1UL << 2) |
#define | _DMA_CHPRIC_CH2PRIC_SHIFT 2 |
#define | _DMA_CHPRIC_CH2PRIC_MASK 0x4UL |
#define | _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) |
#define | DMA_CHPRIC_CH3PRIC (0x1UL << 3) |
#define | _DMA_CHPRIC_CH3PRIC_SHIFT 3 |
#define | _DMA_CHPRIC_CH3PRIC_MASK 0x8UL |
#define | _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) |
#define | DMA_CHPRIC_CH4PRIC (0x1UL << 4) |
#define | _DMA_CHPRIC_CH4PRIC_SHIFT 4 |
#define | _DMA_CHPRIC_CH4PRIC_MASK 0x10UL |
#define | _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) |
#define | DMA_CHPRIC_CH5PRIC (0x1UL << 5) |
#define | _DMA_CHPRIC_CH5PRIC_SHIFT 5 |
#define | _DMA_CHPRIC_CH5PRIC_MASK 0x20UL |
#define | _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) |
#define | DMA_CHPRIC_CH6PRIC (0x1UL << 6) |
#define | _DMA_CHPRIC_CH6PRIC_SHIFT 6 |
#define | _DMA_CHPRIC_CH6PRIC_MASK 0x40UL |
#define | _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) |
#define | DMA_CHPRIC_CH7PRIC (0x1UL << 7) |
#define | _DMA_CHPRIC_CH7PRIC_SHIFT 7 |
#define | _DMA_CHPRIC_CH7PRIC_MASK 0x80UL |
#define | _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL |
#define | DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) |
#define | _DMA_ERRORC_RESETVALUE 0x00000000UL |
#define | _DMA_ERRORC_MASK 0x00000001UL |
#define | DMA_ERRORC_ERRORC (0x1UL << 0) |
#define | _DMA_ERRORC_ERRORC_SHIFT 0 |
#define | _DMA_ERRORC_ERRORC_MASK 0x1UL |
#define | _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL |
#define | DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) |
#define | _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL |
#define | _DMA_CHREQSTATUS_MASK 0x000000FFUL |
#define | DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) |
#define | _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 |
#define | _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL |
#define | _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) |
#define | DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) |
#define | _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 |
#define | _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL |
#define | _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) |
#define | DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) |
#define | _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 |
#define | _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL |
#define | _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) |
#define | DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) |
#define | _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 |
#define | _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL |
#define | _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) |
#define | DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) |
#define | _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 |
#define | _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL |
#define | _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) |
#define | DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) |
#define | _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 |
#define | _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL |
#define | _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) |
#define | DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) |
#define | _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 |
#define | _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL |
#define | _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) |
#define | DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) |
#define | _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 |
#define | _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL |
#define | _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) |
#define | _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL |
#define | _DMA_CHSREQSTATUS_MASK 0x000000FFUL |
#define | DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) |
#define | _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 |
#define | _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL |
#define | _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) |
#define | DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) |
#define | _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 |
#define | _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL |
#define | _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) |
#define | DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) |
#define | _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 |
#define | _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL |
#define | _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) |
#define | DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) |
#define | _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 |
#define | _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL |
#define | _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) |
#define | DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) |
#define | _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 |
#define | _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL |
#define | _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) |
#define | DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) |
#define | _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 |
#define | _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL |
#define | _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) |
#define | DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) |
#define | _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 |
#define | _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL |
#define | _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) |
#define | DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) |
#define | _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 |
#define | _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL |
#define | _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL |
#define | DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) |
#define | _DMA_IF_RESETVALUE 0x00000000UL |
#define | _DMA_IF_MASK 0x800000FFUL |
#define | DMA_IF_CH0DONE (0x1UL << 0) |
#define | _DMA_IF_CH0DONE_SHIFT 0 |
#define | _DMA_IF_CH0DONE_MASK 0x1UL |
#define | _DMA_IF_CH0DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) |
#define | DMA_IF_CH1DONE (0x1UL << 1) |
#define | _DMA_IF_CH1DONE_SHIFT 1 |
#define | _DMA_IF_CH1DONE_MASK 0x2UL |
#define | _DMA_IF_CH1DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) |
#define | DMA_IF_CH2DONE (0x1UL << 2) |
#define | _DMA_IF_CH2DONE_SHIFT 2 |
#define | _DMA_IF_CH2DONE_MASK 0x4UL |
#define | _DMA_IF_CH2DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) |
#define | DMA_IF_CH3DONE (0x1UL << 3) |
#define | _DMA_IF_CH3DONE_SHIFT 3 |
#define | _DMA_IF_CH3DONE_MASK 0x8UL |
#define | _DMA_IF_CH3DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) |
#define | DMA_IF_CH4DONE (0x1UL << 4) |
#define | _DMA_IF_CH4DONE_SHIFT 4 |
#define | _DMA_IF_CH4DONE_MASK 0x10UL |
#define | _DMA_IF_CH4DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) |
#define | DMA_IF_CH5DONE (0x1UL << 5) |
#define | _DMA_IF_CH5DONE_SHIFT 5 |
#define | _DMA_IF_CH5DONE_MASK 0x20UL |
#define | _DMA_IF_CH5DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) |
#define | DMA_IF_CH6DONE (0x1UL << 6) |
#define | _DMA_IF_CH6DONE_SHIFT 6 |
#define | _DMA_IF_CH6DONE_MASK 0x40UL |
#define | _DMA_IF_CH6DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) |
#define | DMA_IF_CH7DONE (0x1UL << 7) |
#define | _DMA_IF_CH7DONE_SHIFT 7 |
#define | _DMA_IF_CH7DONE_MASK 0x80UL |
#define | _DMA_IF_CH7DONE_DEFAULT 0x00000000UL |
#define | DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) |
#define | DMA_IF_ERR (0x1UL << 31) |
#define | _DMA_IF_ERR_SHIFT 31 |
#define | _DMA_IF_ERR_MASK 0x80000000UL |
#define | _DMA_IF_ERR_DEFAULT 0x00000000UL |
#define | DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) |
#define | _DMA_IFS_RESETVALUE 0x00000000UL |
#define | _DMA_IFS_MASK 0x800000FFUL |
#define | DMA_IFS_CH0DONE (0x1UL << 0) |
#define | _DMA_IFS_CH0DONE_SHIFT 0 |
#define | _DMA_IFS_CH0DONE_MASK 0x1UL |
#define | _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) |
#define | DMA_IFS_CH1DONE (0x1UL << 1) |
#define | _DMA_IFS_CH1DONE_SHIFT 1 |
#define | _DMA_IFS_CH1DONE_MASK 0x2UL |
#define | _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) |
#define | DMA_IFS_CH2DONE (0x1UL << 2) |
#define | _DMA_IFS_CH2DONE_SHIFT 2 |
#define | _DMA_IFS_CH2DONE_MASK 0x4UL |
#define | _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) |
#define | DMA_IFS_CH3DONE (0x1UL << 3) |
#define | _DMA_IFS_CH3DONE_SHIFT 3 |
#define | _DMA_IFS_CH3DONE_MASK 0x8UL |
#define | _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) |
#define | DMA_IFS_CH4DONE (0x1UL << 4) |
#define | _DMA_IFS_CH4DONE_SHIFT 4 |
#define | _DMA_IFS_CH4DONE_MASK 0x10UL |
#define | _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) |
#define | DMA_IFS_CH5DONE (0x1UL << 5) |
#define | _DMA_IFS_CH5DONE_SHIFT 5 |
#define | _DMA_IFS_CH5DONE_MASK 0x20UL |
#define | _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) |
#define | DMA_IFS_CH6DONE (0x1UL << 6) |
#define | _DMA_IFS_CH6DONE_SHIFT 6 |
#define | _DMA_IFS_CH6DONE_MASK 0x40UL |
#define | _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) |
#define | DMA_IFS_CH7DONE (0x1UL << 7) |
#define | _DMA_IFS_CH7DONE_SHIFT 7 |
#define | _DMA_IFS_CH7DONE_MASK 0x80UL |
#define | _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL |
#define | DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) |
#define | DMA_IFS_ERR (0x1UL << 31) |
#define | _DMA_IFS_ERR_SHIFT 31 |
#define | _DMA_IFS_ERR_MASK 0x80000000UL |
#define | _DMA_IFS_ERR_DEFAULT 0x00000000UL |
#define | DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) |
#define | _DMA_IFC_RESETVALUE 0x00000000UL |
#define | _DMA_IFC_MASK 0x800000FFUL |
#define | DMA_IFC_CH0DONE (0x1UL << 0) |
#define | _DMA_IFC_CH0DONE_SHIFT 0 |
#define | _DMA_IFC_CH0DONE_MASK 0x1UL |
#define | _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) |
#define | DMA_IFC_CH1DONE (0x1UL << 1) |
#define | _DMA_IFC_CH1DONE_SHIFT 1 |
#define | _DMA_IFC_CH1DONE_MASK 0x2UL |
#define | _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) |
#define | DMA_IFC_CH2DONE (0x1UL << 2) |
#define | _DMA_IFC_CH2DONE_SHIFT 2 |
#define | _DMA_IFC_CH2DONE_MASK 0x4UL |
#define | _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) |
#define | DMA_IFC_CH3DONE (0x1UL << 3) |
#define | _DMA_IFC_CH3DONE_SHIFT 3 |
#define | _DMA_IFC_CH3DONE_MASK 0x8UL |
#define | _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) |
#define | DMA_IFC_CH4DONE (0x1UL << 4) |
#define | _DMA_IFC_CH4DONE_SHIFT 4 |
#define | _DMA_IFC_CH4DONE_MASK 0x10UL |
#define | _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) |
#define | DMA_IFC_CH5DONE (0x1UL << 5) |
#define | _DMA_IFC_CH5DONE_SHIFT 5 |
#define | _DMA_IFC_CH5DONE_MASK 0x20UL |
#define | _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) |
#define | DMA_IFC_CH6DONE (0x1UL << 6) |
#define | _DMA_IFC_CH6DONE_SHIFT 6 |
#define | _DMA_IFC_CH6DONE_MASK 0x40UL |
#define | _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) |
#define | DMA_IFC_CH7DONE (0x1UL << 7) |
#define | _DMA_IFC_CH7DONE_SHIFT 7 |
#define | _DMA_IFC_CH7DONE_MASK 0x80UL |
#define | _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL |
#define | DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) |
#define | DMA_IFC_ERR (0x1UL << 31) |
#define | _DMA_IFC_ERR_SHIFT 31 |
#define | _DMA_IFC_ERR_MASK 0x80000000UL |
#define | _DMA_IFC_ERR_DEFAULT 0x00000000UL |
#define | DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) |
#define | _DMA_IEN_RESETVALUE 0x00000000UL |
#define | _DMA_IEN_MASK 0x800000FFUL |
#define | DMA_IEN_CH0DONE (0x1UL << 0) |
#define | _DMA_IEN_CH0DONE_SHIFT 0 |
#define | _DMA_IEN_CH0DONE_MASK 0x1UL |
#define | _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) |
#define | DMA_IEN_CH1DONE (0x1UL << 1) |
#define | _DMA_IEN_CH1DONE_SHIFT 1 |
#define | _DMA_IEN_CH1DONE_MASK 0x2UL |
#define | _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) |
#define | DMA_IEN_CH2DONE (0x1UL << 2) |
#define | _DMA_IEN_CH2DONE_SHIFT 2 |
#define | _DMA_IEN_CH2DONE_MASK 0x4UL |
#define | _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) |
#define | DMA_IEN_CH3DONE (0x1UL << 3) |
#define | _DMA_IEN_CH3DONE_SHIFT 3 |
#define | _DMA_IEN_CH3DONE_MASK 0x8UL |
#define | _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) |
#define | DMA_IEN_CH4DONE (0x1UL << 4) |
#define | _DMA_IEN_CH4DONE_SHIFT 4 |
#define | _DMA_IEN_CH4DONE_MASK 0x10UL |
#define | _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) |
#define | DMA_IEN_CH5DONE (0x1UL << 5) |
#define | _DMA_IEN_CH5DONE_SHIFT 5 |
#define | _DMA_IEN_CH5DONE_MASK 0x20UL |
#define | _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) |
#define | DMA_IEN_CH6DONE (0x1UL << 6) |
#define | _DMA_IEN_CH6DONE_SHIFT 6 |
#define | _DMA_IEN_CH6DONE_MASK 0x40UL |
#define | _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) |
#define | DMA_IEN_CH7DONE (0x1UL << 7) |
#define | _DMA_IEN_CH7DONE_SHIFT 7 |
#define | _DMA_IEN_CH7DONE_MASK 0x80UL |
#define | _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL |
#define | DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) |
#define | DMA_IEN_ERR (0x1UL << 31) |
#define | _DMA_IEN_ERR_SHIFT 31 |
#define | _DMA_IEN_ERR_MASK 0x80000000UL |
#define | _DMA_IEN_ERR_DEFAULT 0x00000000UL |
#define | DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) |
#define | _DMA_CH_CTRL_RESETVALUE 0x00000000UL |
#define | _DMA_CH_CTRL_MASK 0x003F000FUL |
#define | _DMA_CH_CTRL_SIGSEL_SHIFT 0 |
#define | _DMA_CH_CTRL_SIGSEL_MASK 0xFUL |
#define | _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL |
#define | _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL |
#define | _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL |
#define | _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL |
#define | _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL |
#define | _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL |
#define | DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) |
#define | DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) |
#define | DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) |
#define | DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) |
#define | DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) |
#define | DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) |
#define | DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) |
#define | DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) |
#define | DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) |
#define | DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) |
#define | DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) |
#define | DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) |
#define | DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) |
#define | DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) |
#define | DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) |
#define | DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) |
#define | DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) |
#define | _DMA_CH_CTRL_SOURCESEL_SHIFT 16 |
#define | _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL |
#define | _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL |
#define | _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL |
#define | _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL |
#define | _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL |
#define | _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL |
#define | _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL |
#define | _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL |
#define | _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL |
#define | _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL |
#define | _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL |
#define | DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) |
#define | DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) |
#define | DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) |
#define | _CMU_CTRL_RESETVALUE 0x000C262CUL |
#define | _CMU_CTRL_MASK 0x00FE3EEFUL |
#define | _CMU_CTRL_HFXOMODE_SHIFT 0 |
#define | _CMU_CTRL_HFXOMODE_MASK 0x3UL |
#define | _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL |
#define | _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL |
#define | _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL |
#define | CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) |
#define | CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) |
#define | CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) |
#define | CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) |
#define | _CMU_CTRL_HFXOBOOST_SHIFT 2 |
#define | _CMU_CTRL_HFXOBOOST_MASK 0xCUL |
#define | _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL |
#define | _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL |
#define | _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL |
#define | _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL |
#define | _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL |
#define | CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) |
#define | CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) |
#define | CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) |
#define | CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) |
#define | CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) |
#define | _CMU_CTRL_HFXOBUFCUR_SHIFT 5 |
#define | _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL |
#define | _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL |
#define | CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) |
#define | CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) |
#define | _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 |
#define | _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL |
#define | _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL |
#define | CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) |
#define | _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 |
#define | _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL |
#define | _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL |
#define | _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL |
#define | _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL |
#define | _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL |
#define | _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL |
#define | CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) |
#define | CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) |
#define | _CMU_CTRL_LFXOMODE_SHIFT 11 |
#define | _CMU_CTRL_LFXOMODE_MASK 0x1800UL |
#define | _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL |
#define | _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL |
#define | _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL |
#define | CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) |
#define | CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) |
#define | CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) |
#define | CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) |
#define | CMU_CTRL_LFXOBOOST (0x1UL << 13) |
#define | _CMU_CTRL_LFXOBOOST_SHIFT 13 |
#define | _CMU_CTRL_LFXOBOOST_MASK 0x2000UL |
#define | _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL |
#define | _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL |
#define | _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL |
#define | CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) |
#define | CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) |
#define | CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) |
#define | CMU_CTRL_LFXOBUFCUR (0x1UL << 17) |
#define | _CMU_CTRL_LFXOBUFCUR_SHIFT 17 |
#define | _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL |
#define | _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL |
#define | CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) |
#define | _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 |
#define | _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL |
#define | _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL |
#define | _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL |
#define | _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL |
#define | _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL |
#define | _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL |
#define | CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) |
#define | CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) |
#define | _CMU_CTRL_CLKOUTSEL0_SHIFT 20 |
#define | _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL |
#define | _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL |
#define | _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL |
#define | _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL |
#define | CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) |
#define | CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) |
#define | CMU_CTRL_CLKOUTSEL1 (0x1UL << 23) |
#define | _CMU_CTRL_CLKOUTSEL1_SHIFT 23 |
#define | _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL |
#define | _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL |
#define | _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL |
#define | CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) |
#define | CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) |
#define | CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) |
#define | _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL |
#define | _CMU_HFCORECLKDIV_MASK 0x0000000FUL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL |
#define | _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) |
#define | CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) |
#define | _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL |
#define | _CMU_HFPERCLKDIV_MASK 0x0000010FUL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) |
#define | CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) |
#define | _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 |
#define | _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL |
#define | _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL |
#define | CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) |
#define | _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL |
#define | _CMU_HFRCOCTRL_MASK 0x0001F7FFUL |
#define | _CMU_HFRCOCTRL_TUNING_SHIFT 0 |
#define | _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL |
#define | _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL |
#define | CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) |
#define | _CMU_HFRCOCTRL_BAND_SHIFT 8 |
#define | _CMU_HFRCOCTRL_BAND_MASK 0x700UL |
#define | _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL |
#define | _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL |
#define | _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL |
#define | _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL |
#define | _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL |
#define | _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL |
#define | _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL |
#define | CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) |
#define | CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) |
#define | CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) |
#define | _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 |
#define | _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL |
#define | _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL |
#define | CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) |
#define | _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL |
#define | _CMU_LFRCOCTRL_MASK 0x0000007FUL |
#define | _CMU_LFRCOCTRL_TUNING_SHIFT 0 |
#define | _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL |
#define | _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL |
#define | CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) |
#define | _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL |
#define | _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL |
#define | _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 |
#define | _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL |
#define | _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL |
#define | CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) |
#define | _CMU_CALCTRL_RESETVALUE 0x00000000UL |
#define | _CMU_CALCTRL_MASK 0x00000007UL |
#define | _CMU_CALCTRL_UPSEL_SHIFT 0 |
#define | _CMU_CALCTRL_UPSEL_MASK 0x7UL |
#define | _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL |
#define | _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL |
#define | _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL |
#define | _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL |
#define | _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL |
#define | _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL |
#define | CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) |
#define | CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) |
#define | CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) |
#define | CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) |
#define | CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) |
#define | CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) |
#define | _CMU_CALCNT_RESETVALUE 0x00000000UL |
#define | _CMU_CALCNT_MASK 0x000FFFFFUL |
#define | _CMU_CALCNT_CALCNT_SHIFT 0 |
#define | _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL |
#define | _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL |
#define | CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) |
#define | _CMU_OSCENCMD_RESETVALUE 0x00000000UL |
#define | _CMU_OSCENCMD_MASK 0x000003FFUL |
#define | CMU_OSCENCMD_HFRCOEN (0x1UL << 0) |
#define | _CMU_OSCENCMD_HFRCOEN_SHIFT 0 |
#define | _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL |
#define | _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) |
#define | CMU_OSCENCMD_HFRCODIS (0x1UL << 1) |
#define | _CMU_OSCENCMD_HFRCODIS_SHIFT 1 |
#define | _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL |
#define | _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) |
#define | CMU_OSCENCMD_HFXOEN (0x1UL << 2) |
#define | _CMU_OSCENCMD_HFXOEN_SHIFT 2 |
#define | _CMU_OSCENCMD_HFXOEN_MASK 0x4UL |
#define | _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) |
#define | CMU_OSCENCMD_HFXODIS (0x1UL << 3) |
#define | _CMU_OSCENCMD_HFXODIS_SHIFT 3 |
#define | _CMU_OSCENCMD_HFXODIS_MASK 0x8UL |
#define | _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) |
#define | CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) |
#define | _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 |
#define | _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL |
#define | _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) |
#define | CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) |
#define | _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 |
#define | _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL |
#define | _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) |
#define | CMU_OSCENCMD_LFRCOEN (0x1UL << 6) |
#define | _CMU_OSCENCMD_LFRCOEN_SHIFT 6 |
#define | _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL |
#define | _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) |
#define | CMU_OSCENCMD_LFRCODIS (0x1UL << 7) |
#define | _CMU_OSCENCMD_LFRCODIS_SHIFT 7 |
#define | _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL |
#define | _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) |
#define | CMU_OSCENCMD_LFXOEN (0x1UL << 8) |
#define | _CMU_OSCENCMD_LFXOEN_SHIFT 8 |
#define | _CMU_OSCENCMD_LFXOEN_MASK 0x100UL |
#define | _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) |
#define | CMU_OSCENCMD_LFXODIS (0x1UL << 9) |
#define | _CMU_OSCENCMD_LFXODIS_SHIFT 9 |
#define | _CMU_OSCENCMD_LFXODIS_MASK 0x200UL |
#define | _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL |
#define | CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) |
#define | _CMU_CMD_RESETVALUE 0x00000000UL |
#define | _CMU_CMD_MASK 0x0000000FUL |
#define | _CMU_CMD_HFCLKSEL_SHIFT 0 |
#define | _CMU_CMD_HFCLKSEL_MASK 0x7UL |
#define | _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL |
#define | _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL |
#define | _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL |
#define | _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL |
#define | _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL |
#define | CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) |
#define | CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) |
#define | CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) |
#define | CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) |
#define | CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) |
#define | CMU_CMD_CALSTART (0x1UL << 3) |
#define | _CMU_CMD_CALSTART_SHIFT 3 |
#define | _CMU_CMD_CALSTART_MASK 0x8UL |
#define | _CMU_CMD_CALSTART_DEFAULT 0x00000000UL |
#define | CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) |
#define | _CMU_LFCLKSEL_RESETVALUE 0x00000005UL |
#define | _CMU_LFCLKSEL_MASK 0x0000000FUL |
#define | _CMU_LFCLKSEL_LFA_SHIFT 0 |
#define | _CMU_LFCLKSEL_LFA_MASK 0x3UL |
#define | _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL |
#define | _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL |
#define | _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL |
#define | _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL |
#define | _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL |
#define | CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) |
#define | CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) |
#define | CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) |
#define | CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) |
#define | CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) |
#define | _CMU_LFCLKSEL_LFB_SHIFT 2 |
#define | _CMU_LFCLKSEL_LFB_MASK 0xCUL |
#define | _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL |
#define | _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL |
#define | _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL |
#define | _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL |
#define | _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL |
#define | CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) |
#define | CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) |
#define | CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) |
#define | CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) |
#define | CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) |
#define | _CMU_STATUS_RESETVALUE 0x00000403UL |
#define | _CMU_STATUS_MASK 0x00007FFFUL |
#define | CMU_STATUS_HFRCOENS (0x1UL << 0) |
#define | _CMU_STATUS_HFRCOENS_SHIFT 0 |
#define | _CMU_STATUS_HFRCOENS_MASK 0x1UL |
#define | _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL |
#define | CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) |
#define | CMU_STATUS_HFRCORDY (0x1UL << 1) |
#define | _CMU_STATUS_HFRCORDY_SHIFT 1 |
#define | _CMU_STATUS_HFRCORDY_MASK 0x2UL |
#define | _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL |
#define | CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) |
#define | CMU_STATUS_HFXOENS (0x1UL << 2) |
#define | _CMU_STATUS_HFXOENS_SHIFT 2 |
#define | _CMU_STATUS_HFXOENS_MASK 0x4UL |
#define | _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) |
#define | CMU_STATUS_HFXORDY (0x1UL << 3) |
#define | _CMU_STATUS_HFXORDY_SHIFT 3 |
#define | _CMU_STATUS_HFXORDY_MASK 0x8UL |
#define | _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) |
#define | CMU_STATUS_AUXHFRCOENS (0x1UL << 4) |
#define | _CMU_STATUS_AUXHFRCOENS_SHIFT 4 |
#define | _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL |
#define | _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) |
#define | CMU_STATUS_AUXHFRCORDY (0x1UL << 5) |
#define | _CMU_STATUS_AUXHFRCORDY_SHIFT 5 |
#define | _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL |
#define | _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) |
#define | CMU_STATUS_LFRCOENS (0x1UL << 6) |
#define | _CMU_STATUS_LFRCOENS_SHIFT 6 |
#define | _CMU_STATUS_LFRCOENS_MASK 0x40UL |
#define | _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) |
#define | CMU_STATUS_LFRCORDY (0x1UL << 7) |
#define | _CMU_STATUS_LFRCORDY_SHIFT 7 |
#define | _CMU_STATUS_LFRCORDY_MASK 0x80UL |
#define | _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) |
#define | CMU_STATUS_LFXOENS (0x1UL << 8) |
#define | _CMU_STATUS_LFXOENS_SHIFT 8 |
#define | _CMU_STATUS_LFXOENS_MASK 0x100UL |
#define | _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) |
#define | CMU_STATUS_LFXORDY (0x1UL << 9) |
#define | _CMU_STATUS_LFXORDY_SHIFT 9 |
#define | _CMU_STATUS_LFXORDY_MASK 0x200UL |
#define | _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) |
#define | CMU_STATUS_HFRCOSEL (0x1UL << 10) |
#define | _CMU_STATUS_HFRCOSEL_SHIFT 10 |
#define | _CMU_STATUS_HFRCOSEL_MASK 0x400UL |
#define | _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL |
#define | CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) |
#define | CMU_STATUS_HFXOSEL (0x1UL << 11) |
#define | _CMU_STATUS_HFXOSEL_SHIFT 11 |
#define | _CMU_STATUS_HFXOSEL_MASK 0x800UL |
#define | _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL |
#define | CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) |
#define | CMU_STATUS_LFRCOSEL (0x1UL << 12) |
#define | _CMU_STATUS_LFRCOSEL_SHIFT 12 |
#define | _CMU_STATUS_LFRCOSEL_MASK 0x1000UL |
#define | _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) |
#define | CMU_STATUS_LFXOSEL (0x1UL << 13) |
#define | _CMU_STATUS_LFXOSEL_SHIFT 13 |
#define | _CMU_STATUS_LFXOSEL_MASK 0x2000UL |
#define | _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL |
#define | CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) |
#define | CMU_STATUS_CALBSY (0x1UL << 14) |
#define | _CMU_STATUS_CALBSY_SHIFT 14 |
#define | _CMU_STATUS_CALBSY_MASK 0x4000UL |
#define | _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL |
#define | CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) |
#define | _CMU_IF_RESETVALUE 0x00000001UL |
#define | _CMU_IF_MASK 0x0000003FUL |
#define | CMU_IF_HFRCORDY (0x1UL << 0) |
#define | _CMU_IF_HFRCORDY_SHIFT 0 |
#define | _CMU_IF_HFRCORDY_MASK 0x1UL |
#define | _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL |
#define | CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) |
#define | CMU_IF_HFXORDY (0x1UL << 1) |
#define | _CMU_IF_HFXORDY_SHIFT 1 |
#define | _CMU_IF_HFXORDY_MASK 0x2UL |
#define | _CMU_IF_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) |
#define | CMU_IF_LFRCORDY (0x1UL << 2) |
#define | _CMU_IF_LFRCORDY_SHIFT 2 |
#define | _CMU_IF_LFRCORDY_MASK 0x4UL |
#define | _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) |
#define | CMU_IF_LFXORDY (0x1UL << 3) |
#define | _CMU_IF_LFXORDY_SHIFT 3 |
#define | _CMU_IF_LFXORDY_MASK 0x8UL |
#define | _CMU_IF_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) |
#define | CMU_IF_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IF_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IF_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IF_CALRDY (0x1UL << 5) |
#define | _CMU_IF_CALRDY_SHIFT 5 |
#define | _CMU_IF_CALRDY_MASK 0x20UL |
#define | _CMU_IF_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) |
#define | _CMU_IFS_RESETVALUE 0x00000000UL |
#define | _CMU_IFS_MASK 0x0000003FUL |
#define | CMU_IFS_HFRCORDY (0x1UL << 0) |
#define | _CMU_IFS_HFRCORDY_SHIFT 0 |
#define | _CMU_IFS_HFRCORDY_MASK 0x1UL |
#define | _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) |
#define | CMU_IFS_HFXORDY (0x1UL << 1) |
#define | _CMU_IFS_HFXORDY_SHIFT 1 |
#define | _CMU_IFS_HFXORDY_MASK 0x2UL |
#define | _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) |
#define | CMU_IFS_LFRCORDY (0x1UL << 2) |
#define | _CMU_IFS_LFRCORDY_SHIFT 2 |
#define | _CMU_IFS_LFRCORDY_MASK 0x4UL |
#define | _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) |
#define | CMU_IFS_LFXORDY (0x1UL << 3) |
#define | _CMU_IFS_LFXORDY_SHIFT 3 |
#define | _CMU_IFS_LFXORDY_MASK 0x8UL |
#define | _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) |
#define | CMU_IFS_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IFS_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IFS_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IFS_CALRDY (0x1UL << 5) |
#define | _CMU_IFS_CALRDY_SHIFT 5 |
#define | _CMU_IFS_CALRDY_MASK 0x20UL |
#define | _CMU_IFS_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) |
#define | _CMU_IFC_RESETVALUE 0x00000000UL |
#define | _CMU_IFC_MASK 0x0000003FUL |
#define | CMU_IFC_HFRCORDY (0x1UL << 0) |
#define | _CMU_IFC_HFRCORDY_SHIFT 0 |
#define | _CMU_IFC_HFRCORDY_MASK 0x1UL |
#define | _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) |
#define | CMU_IFC_HFXORDY (0x1UL << 1) |
#define | _CMU_IFC_HFXORDY_SHIFT 1 |
#define | _CMU_IFC_HFXORDY_MASK 0x2UL |
#define | _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) |
#define | CMU_IFC_LFRCORDY (0x1UL << 2) |
#define | _CMU_IFC_LFRCORDY_SHIFT 2 |
#define | _CMU_IFC_LFRCORDY_MASK 0x4UL |
#define | _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) |
#define | CMU_IFC_LFXORDY (0x1UL << 3) |
#define | _CMU_IFC_LFXORDY_SHIFT 3 |
#define | _CMU_IFC_LFXORDY_MASK 0x8UL |
#define | _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) |
#define | CMU_IFC_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IFC_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IFC_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IFC_CALRDY (0x1UL << 5) |
#define | _CMU_IFC_CALRDY_SHIFT 5 |
#define | _CMU_IFC_CALRDY_MASK 0x20UL |
#define | _CMU_IFC_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) |
#define | _CMU_IEN_RESETVALUE 0x00000000UL |
#define | _CMU_IEN_MASK 0x0000003FUL |
#define | CMU_IEN_HFRCORDY (0x1UL << 0) |
#define | _CMU_IEN_HFRCORDY_SHIFT 0 |
#define | _CMU_IEN_HFRCORDY_MASK 0x1UL |
#define | _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) |
#define | CMU_IEN_HFXORDY (0x1UL << 1) |
#define | _CMU_IEN_HFXORDY_SHIFT 1 |
#define | _CMU_IEN_HFXORDY_MASK 0x2UL |
#define | _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) |
#define | CMU_IEN_LFRCORDY (0x1UL << 2) |
#define | _CMU_IEN_LFRCORDY_SHIFT 2 |
#define | _CMU_IEN_LFRCORDY_MASK 0x4UL |
#define | _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) |
#define | CMU_IEN_LFXORDY (0x1UL << 3) |
#define | _CMU_IEN_LFXORDY_SHIFT 3 |
#define | _CMU_IEN_LFXORDY_MASK 0x8UL |
#define | _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) |
#define | CMU_IEN_AUXHFRCORDY (0x1UL << 4) |
#define | _CMU_IEN_AUXHFRCORDY_SHIFT 4 |
#define | _CMU_IEN_AUXHFRCORDY_MASK 0x10UL |
#define | _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) |
#define | CMU_IEN_CALRDY (0x1UL << 5) |
#define | _CMU_IEN_CALRDY_SHIFT 5 |
#define | _CMU_IEN_CALRDY_MASK 0x20UL |
#define | _CMU_IEN_CALRDY_DEFAULT 0x00000000UL |
#define | CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) |
#define | _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_HFCORECLKEN0_MASK 0x00000006UL |
#define | CMU_HFCORECLKEN0_DMA (0x1UL << 1) |
#define | _CMU_HFCORECLKEN0_DMA_SHIFT 1 |
#define | _CMU_HFCORECLKEN0_DMA_MASK 0x2UL |
#define | _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL |
#define | CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) |
#define | CMU_HFCORECLKEN0_LE (0x1UL << 2) |
#define | _CMU_HFCORECLKEN0_LE_SHIFT 2 |
#define | _CMU_HFCORECLKEN0_LE_MASK 0x4UL |
#define | _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL |
#define | CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2) |
#define | _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_HFPERCLKEN0_MASK 0x0000FDB3UL |
#define | CMU_HFPERCLKEN0_USART0 (0x1UL << 0) |
#define | _CMU_HFPERCLKEN0_USART0_SHIFT 0 |
#define | _CMU_HFPERCLKEN0_USART0_MASK 0x1UL |
#define | _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) |
#define | CMU_HFPERCLKEN0_USART1 (0x1UL << 1) |
#define | _CMU_HFPERCLKEN0_USART1_SHIFT 1 |
#define | _CMU_HFPERCLKEN0_USART1_MASK 0x2UL |
#define | _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) |
#define | CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4) |
#define | _CMU_HFPERCLKEN0_TIMER0_SHIFT 4 |
#define | _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL |
#define | _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4) |
#define | CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5) |
#define | _CMU_HFPERCLKEN0_TIMER1_SHIFT 5 |
#define | _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL |
#define | _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5) |
#define | CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7) |
#define | _CMU_HFPERCLKEN0_ACMP0_SHIFT 7 |
#define | _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL |
#define | _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7) |
#define | CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8) |
#define | _CMU_HFPERCLKEN0_ACMP1_SHIFT 8 |
#define | _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL |
#define | _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8) |
#define | CMU_HFPERCLKEN0_PRS (0x1UL << 10) |
#define | _CMU_HFPERCLKEN0_PRS_SHIFT 10 |
#define | _CMU_HFPERCLKEN0_PRS_MASK 0x400UL |
#define | _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10) |
#define | CMU_HFPERCLKEN0_DAC0 (0x1UL << 11) |
#define | _CMU_HFPERCLKEN0_DAC0_SHIFT 11 |
#define | _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL |
#define | _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11) |
#define | CMU_HFPERCLKEN0_GPIO (0x1UL << 12) |
#define | _CMU_HFPERCLKEN0_GPIO_SHIFT 12 |
#define | _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL |
#define | _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12) |
#define | CMU_HFPERCLKEN0_VCMP (0x1UL << 13) |
#define | _CMU_HFPERCLKEN0_VCMP_SHIFT 13 |
#define | _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL |
#define | _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13) |
#define | CMU_HFPERCLKEN0_ADC0 (0x1UL << 14) |
#define | _CMU_HFPERCLKEN0_ADC0_SHIFT 14 |
#define | _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL |
#define | _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14) |
#define | CMU_HFPERCLKEN0_I2C0 (0x1UL << 15) |
#define | _CMU_HFPERCLKEN0_I2C0_SHIFT 15 |
#define | _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL |
#define | _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL |
#define | CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15) |
#define | _CMU_SYNCBUSY_RESETVALUE 0x00000000UL |
#define | _CMU_SYNCBUSY_MASK 0x00000055UL |
#define | CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) |
#define | _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 |
#define | _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL |
#define | _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) |
#define | CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) |
#define | _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 |
#define | _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL |
#define | _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) |
#define | CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) |
#define | _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 |
#define | _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL |
#define | _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) |
#define | CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) |
#define | _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 |
#define | _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL |
#define | _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL |
#define | CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) |
#define | _CMU_FREEZE_RESETVALUE 0x00000000UL |
#define | _CMU_FREEZE_MASK 0x00000001UL |
#define | CMU_FREEZE_REGFREEZE (0x1UL << 0) |
#define | _CMU_FREEZE_REGFREEZE_SHIFT 0 |
#define | _CMU_FREEZE_REGFREEZE_MASK 0x1UL |
#define | _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL |
#define | _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL |
#define | _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL |
#define | CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) |
#define | CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) |
#define | CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) |
#define | _CMU_LFACLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_LFACLKEN0_MASK 0x00000003UL |
#define | CMU_LFACLKEN0_RTC (0x1UL << 0) |
#define | _CMU_LFACLKEN0_RTC_SHIFT 0 |
#define | _CMU_LFACLKEN0_RTC_MASK 0x1UL |
#define | _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL |
#define | CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0) |
#define | CMU_LFACLKEN0_LETIMER0 (0x1UL << 1) |
#define | _CMU_LFACLKEN0_LETIMER0_SHIFT 1 |
#define | _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL |
#define | _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL |
#define | CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1) |
#define | _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL |
#define | _CMU_LFBCLKEN0_MASK 0x00000001UL |
#define | CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) |
#define | _CMU_LFBCLKEN0_LEUART0_SHIFT 0 |
#define | _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL |
#define | _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL |
#define | CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) |
#define | _CMU_LFAPRESC0_RESETVALUE 0x00000000UL |
#define | _CMU_LFAPRESC0_MASK 0x000000FFUL |
#define | _CMU_LFAPRESC0_RTC_SHIFT 0 |
#define | _CMU_LFAPRESC0_RTC_MASK 0xFUL |
#define | _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL |
#define | _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL |
#define | _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL |
#define | _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL |
#define | _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL |
#define | _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL |
#define | _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL |
#define | _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL |
#define | _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL |
#define | _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL |
#define | _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL |
#define | _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL |
#define | _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL |
#define | _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL |
#define | _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL |
#define | _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL |
#define | CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0) |
#define | CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0) |
#define | _CMU_LFAPRESC0_LETIMER0_SHIFT 4 |
#define | _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL |
#define | _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL |
#define | CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4) |
#define | CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4) |
#define | _CMU_LFBPRESC0_RESETVALUE 0x00000000UL |
#define | _CMU_LFBPRESC0_MASK 0x00000003UL |
#define | _CMU_LFBPRESC0_LEUART0_SHIFT 0 |
#define | _CMU_LFBPRESC0_LEUART0_MASK 0x3UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL |
#define | _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL |
#define | CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) |
#define | CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) |
#define | CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) |
#define | CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) |
#define | _CMU_PCNTCTRL_RESETVALUE 0x00000000UL |
#define | _CMU_PCNTCTRL_MASK 0x00000003UL |
#define | CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) |
#define | _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 |
#define | _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL |
#define | _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL |
#define | CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) |
#define | CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL |
#define | _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL |
#define | CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) |
#define | CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) |
#define | CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) |
#define | _CMU_ROUTE_RESETVALUE 0x00000000UL |
#define | _CMU_ROUTE_MASK 0x00000007UL |
#define | CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) |
#define | _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 |
#define | _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL |
#define | _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL |
#define | CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) |
#define | CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) |
#define | _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 |
#define | _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL |
#define | _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL |
#define | CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) |
#define | CMU_ROUTE_LOCATION (0x1UL << 2) |
#define | _CMU_ROUTE_LOCATION_SHIFT 2 |
#define | _CMU_ROUTE_LOCATION_MASK 0x4UL |
#define | _CMU_ROUTE_LOCATION_LOC0 0x00000000UL |
#define | _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL |
#define | _CMU_ROUTE_LOCATION_LOC1 0x00000001UL |
#define | CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) |
#define | CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) |
#define | CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) |
#define | _CMU_LOCK_RESETVALUE 0x00000000UL |
#define | _CMU_LOCK_MASK 0x0000FFFFUL |
#define | _CMU_LOCK_LOCKKEY_SHIFT 0 |
#define | _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL |
#define | _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL |
#define | _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL |
#define | _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL |
#define | _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL |
#define | _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL |
#define | CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) |
#define | CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) |
#define | CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) |
#define | CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) |
#define | CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) |
#define | _PRS_SWPULSE_RESETVALUE 0x00000000UL |
#define | _PRS_SWPULSE_MASK 0x000000FFUL |
#define | PRS_SWPULSE_CH0PULSE (0x1UL << 0) |
#define | _PRS_SWPULSE_CH0PULSE_SHIFT 0 |
#define | _PRS_SWPULSE_CH0PULSE_MASK 0x1UL |
#define | _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) |
#define | PRS_SWPULSE_CH1PULSE (0x1UL << 1) |
#define | _PRS_SWPULSE_CH1PULSE_SHIFT 1 |
#define | _PRS_SWPULSE_CH1PULSE_MASK 0x2UL |
#define | _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) |
#define | PRS_SWPULSE_CH2PULSE (0x1UL << 2) |
#define | _PRS_SWPULSE_CH2PULSE_SHIFT 2 |
#define | _PRS_SWPULSE_CH2PULSE_MASK 0x4UL |
#define | _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) |
#define | PRS_SWPULSE_CH3PULSE (0x1UL << 3) |
#define | _PRS_SWPULSE_CH3PULSE_SHIFT 3 |
#define | _PRS_SWPULSE_CH3PULSE_MASK 0x8UL |
#define | _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) |
#define | PRS_SWPULSE_CH4PULSE (0x1UL << 4) |
#define | _PRS_SWPULSE_CH4PULSE_SHIFT 4 |
#define | _PRS_SWPULSE_CH4PULSE_MASK 0x10UL |
#define | _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) |
#define | PRS_SWPULSE_CH5PULSE (0x1UL << 5) |
#define | _PRS_SWPULSE_CH5PULSE_SHIFT 5 |
#define | _PRS_SWPULSE_CH5PULSE_MASK 0x20UL |
#define | _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) |
#define | PRS_SWPULSE_CH6PULSE (0x1UL << 6) |
#define | _PRS_SWPULSE_CH6PULSE_SHIFT 6 |
#define | _PRS_SWPULSE_CH6PULSE_MASK 0x40UL |
#define | _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) |
#define | PRS_SWPULSE_CH7PULSE (0x1UL << 7) |
#define | _PRS_SWPULSE_CH7PULSE_SHIFT 7 |
#define | _PRS_SWPULSE_CH7PULSE_MASK 0x80UL |
#define | _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL |
#define | PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) |
#define | _PRS_SWLEVEL_RESETVALUE 0x00000000UL |
#define | _PRS_SWLEVEL_MASK 0x000000FFUL |
#define | PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) |
#define | _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 |
#define | _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL |
#define | _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) |
#define | PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) |
#define | _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 |
#define | _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL |
#define | _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) |
#define | PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) |
#define | _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 |
#define | _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL |
#define | _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) |
#define | PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) |
#define | _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 |
#define | _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL |
#define | _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) |
#define | PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) |
#define | _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 |
#define | _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL |
#define | _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) |
#define | PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) |
#define | _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 |
#define | _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL |
#define | _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) |
#define | PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) |
#define | _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 |
#define | _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL |
#define | _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) |
#define | PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) |
#define | _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 |
#define | _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL |
#define | _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL |
#define | PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) |
#define | _PRS_CH_CTRL_RESETVALUE 0x00000000UL |
#define | _PRS_CH_CTRL_MASK 0x033F0007UL |
#define | _PRS_CH_CTRL_SIGSEL_SHIFT 0 |
#define | _PRS_CH_CTRL_SIGSEL_MASK 0x7UL |
#define | _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL |
#define | _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL |
#define | _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL |
#define | _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL |
#define | PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) |
#define | PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) |
#define | PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) |
#define | PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) |
#define | PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) |
#define | _PRS_CH_CTRL_SOURCESEL_SHIFT 16 |
#define | _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL |
#define | _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL |
#define | _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL |
#define | _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL |
#define | _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL |
#define | _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL |
#define | _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL |
#define | _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL |
#define | _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL |
#define | _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL |
#define | _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL |
#define | _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL |
#define | PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) |
#define | PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) |
#define | PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) |
#define | PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) |
#define | PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) |
#define | _PRS_CH_CTRL_EDSEL_SHIFT 24 |
#define | _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL |
#define | _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL |
#define | _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL |
#define | _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL |
#define | _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL |
#define | _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL |
#define | PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) |
#define | PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) |
#define | PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) |
#define | PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) |
#define | PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) |
#define | MSC_UNLOCK_CODE 0x1B71 |
#define | EMU_UNLOCK_CODE 0xADE8 |
#define | CMU_UNLOCK_CODE 0x580E |
#define | TIMER_UNLOCK_CODE 0xCE80 |
#define | GPIO_UNLOCK_CODE 0xA534 |
#define | SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK)); |
Set the value of a bit field within a register. | |
Typedefs | |
typedef enum IRQn | IRQn_Type |
Enumerations | |
enum | IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, DMA_IRQn = 0, GPIO_EVEN_IRQn = 1, TIMER0_IRQn = 2, USART0_RX_IRQn = 3, USART0_TX_IRQn = 4, ACMP0_IRQn = 5, ADC0_IRQn = 6, DAC0_IRQn = 7, I2C0_IRQn = 8, GPIO_ODD_IRQn = 9, TIMER1_IRQn = 10, USART1_RX_IRQn = 12, USART1_TX_IRQn = 13, LEUART0_IRQn = 18, LETIMER0_IRQn = 20, PCNT0_IRQn = 21, RTC_IRQn = 24, CMU_IRQn = 25, VCMP_IRQn = 26, MSC_IRQn = 28 } |
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.
DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.
Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.
Definition in file efm32g200f16.h.