00001
00034 #ifndef __SILICON_LABS_EFM32G210F128_H__
00035 #define __SILICON_LABS_EFM32G210F128_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 MemoryManagement_IRQn = -12,
00058 BusFault_IRQn = -11,
00059 UsageFault_IRQn = -10,
00060 SVCall_IRQn = -5,
00061 DebugMonitor_IRQn = -4,
00062 PendSV_IRQn = -2,
00063 SysTick_IRQn = -1,
00065
00066 DMA_IRQn = 0,
00067 GPIO_EVEN_IRQn = 1,
00068 TIMER0_IRQn = 2,
00069 USART0_RX_IRQn = 3,
00070 USART0_TX_IRQn = 4,
00071 ACMP0_IRQn = 5,
00072 ADC0_IRQn = 6,
00073 DAC0_IRQn = 7,
00074 I2C0_IRQn = 8,
00075 GPIO_ODD_IRQn = 9,
00076 TIMER1_IRQn = 10,
00077 USART1_RX_IRQn = 12,
00078 USART1_TX_IRQn = 13,
00079 LEUART0_IRQn = 18,
00080 LETIMER0_IRQn = 20,
00081 PCNT0_IRQn = 21,
00082 RTC_IRQn = 24,
00083 CMU_IRQn = 25,
00084 VCMP_IRQn = 26,
00085 MSC_IRQn = 28,
00086 AES_IRQn = 29,
00087 } IRQn_Type;
00088
00089
00094 #define __MPU_PRESENT 1
00095 #define __NVIC_PRIO_BITS 3
00096 #define __Vendor_SysTickConfig 0
00100
00106 #define _EFM32_GECKO_FAMILY 1
00107 #define _EFM_DEVICE
00108 #define _SILICON_LABS_32B_PLATFORM_1
00109 #define _SILICON_LABS_32B_PLATFORM 1
00111
00112 #if !defined(EFM32G210F128)
00113 #define EFM32G210F128 1
00114 #endif
00115
00117 #define PART_NUMBER "EFM32G210F128"
00120 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00121 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00122 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00123 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00124 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00125 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00126 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00127 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00128 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00129 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00130 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00131 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00132 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00133 #define RAM_MEM_SIZE ((uint32_t) 0x8000UL)
00134 #define RAM_MEM_END ((uint32_t) 0x20007FFFUL)
00135 #define RAM_MEM_BITS ((uint32_t) 0x15UL)
00136 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00137 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
00138 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
00139 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
00140 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
00141 #define EBI_MEM_SIZE ((uint32_t) 0x10000000UL)
00142 #define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL)
00143 #define EBI_MEM_BITS ((uint32_t) 0x28UL)
00146 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
00147 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
00150 #define FLASH_BASE (0x00000000UL)
00151 #define FLASH_SIZE (0x00020000UL)
00152 #define FLASH_PAGE_SIZE 512
00153 #define SRAM_BASE (0x20000000UL)
00154 #define SRAM_SIZE (0x00004000UL)
00155 #define __CM3_REV 0x200
00156 #define PRS_CHAN_COUNT 8
00157 #define DMA_CHAN_COUNT 8
00160 #define AFCHAN_MAX 79
00161 #define AFCHANLOC_MAX 4
00162
00163 #define AFACHAN_MAX 37
00164
00165
00166
00167 #define TIMER_PRESENT
00168 #define TIMER_COUNT 2
00169 #define USART_PRESENT
00170 #define USART_COUNT 2
00171 #define LEUART_PRESENT
00172 #define LEUART_COUNT 1
00173 #define LETIMER_PRESENT
00174 #define LETIMER_COUNT 1
00175 #define PCNT_PRESENT
00176 #define PCNT_COUNT 1
00177 #define ACMP_PRESENT
00178 #define ACMP_COUNT 2
00179 #define DAC_PRESENT
00180 #define DAC_COUNT 1
00181 #define ADC_PRESENT
00182 #define ADC_COUNT 1
00183 #define I2C_PRESENT
00184 #define I2C_COUNT 1
00185 #define AES_PRESENT
00186 #define AES_COUNT 1
00187 #define DMA_PRESENT
00188 #define DMA_COUNT 1
00189 #define LE_PRESENT
00190 #define LE_COUNT 1
00191 #define MSC_PRESENT
00192 #define MSC_COUNT 1
00193 #define EMU_PRESENT
00194 #define EMU_COUNT 1
00195 #define RMU_PRESENT
00196 #define RMU_COUNT 1
00197 #define CMU_PRESENT
00198 #define CMU_COUNT 1
00199 #define RTC_PRESENT
00200 #define RTC_COUNT 1
00201 #define PRS_PRESENT
00202 #define PRS_COUNT 1
00203 #define GPIO_PRESENT
00204 #define GPIO_COUNT 1
00205 #define VCMP_PRESENT
00206 #define VCMP_COUNT 1
00207 #define HFXTAL_PRESENT
00208 #define HFXTAL_COUNT 1
00209 #define LFXTAL_PRESENT
00210 #define LFXTAL_COUNT 1
00211 #define WDOG_PRESENT
00212 #define WDOG_COUNT 1
00213 #define DBG_PRESENT
00214 #define DBG_COUNT 1
00215 #define BOOTLOADER_PRESENT
00216 #define BOOTLOADER_COUNT 1
00217 #define ANALOG_PRESENT
00218 #define ANALOG_COUNT 1
00219
00220 #include "core_cm3.h"
00221 #include "system_efm32g.h"
00222
00225
00231 #include "efm32g_aes.h"
00232 #include "efm32g_dma_ch.h"
00233
00234
00239 typedef struct
00240 {
00241 __I uint32_t STATUS;
00242 __O uint32_t CONFIG;
00243 __IO uint32_t CTRLBASE;
00244 __I uint32_t ALTCTRLBASE;
00245 __I uint32_t CHWAITSTATUS;
00246 __O uint32_t CHSWREQ;
00247 __IO uint32_t CHUSEBURSTS;
00248 __O uint32_t CHUSEBURSTC;
00249 __IO uint32_t CHREQMASKS;
00250 __O uint32_t CHREQMASKC;
00251 __IO uint32_t CHENS;
00252 __O uint32_t CHENC;
00253 __IO uint32_t CHALTS;
00254 __O uint32_t CHALTC;
00255 __IO uint32_t CHPRIS;
00256 __O uint32_t CHPRIC;
00257 uint32_t RESERVED0[3];
00258 __IO uint32_t ERRORC;
00259 uint32_t RESERVED1[880];
00260 __I uint32_t CHREQSTATUS;
00261 uint32_t RESERVED2[1];
00262 __I uint32_t CHSREQSTATUS;
00264 uint32_t RESERVED3[121];
00265 __I uint32_t IF;
00266 __IO uint32_t IFS;
00267 __IO uint32_t IFC;
00268 __IO uint32_t IEN;
00270 uint32_t RESERVED4[60];
00272 DMA_CH_TypeDef CH[8];
00273 } DMA_TypeDef;
00275 #include "efm32g_msc.h"
00276 #include "efm32g_emu.h"
00277 #include "efm32g_rmu.h"
00278
00279
00284 typedef struct
00285 {
00286 __IO uint32_t CTRL;
00287 __IO uint32_t HFCORECLKDIV;
00288 __IO uint32_t HFPERCLKDIV;
00289 __IO uint32_t HFRCOCTRL;
00290 __IO uint32_t LFRCOCTRL;
00291 __IO uint32_t AUXHFRCOCTRL;
00292 __IO uint32_t CALCTRL;
00293 __IO uint32_t CALCNT;
00294 __IO uint32_t OSCENCMD;
00295 __IO uint32_t CMD;
00296 __IO uint32_t LFCLKSEL;
00297 __I uint32_t STATUS;
00298 __I uint32_t IF;
00299 __IO uint32_t IFS;
00300 __IO uint32_t IFC;
00301 __IO uint32_t IEN;
00302 __IO uint32_t HFCORECLKEN0;
00303 __IO uint32_t HFPERCLKEN0;
00304 uint32_t RESERVED0[2];
00305 __I uint32_t SYNCBUSY;
00306 __IO uint32_t FREEZE;
00307 __IO uint32_t LFACLKEN0;
00308 uint32_t RESERVED1[1];
00309 __IO uint32_t LFBCLKEN0;
00310 uint32_t RESERVED2[1];
00311 __IO uint32_t LFAPRESC0;
00312 uint32_t RESERVED3[1];
00313 __IO uint32_t LFBPRESC0;
00314 uint32_t RESERVED4[1];
00315 __IO uint32_t PCNTCTRL;
00316 uint32_t RESERVED5[1];
00317 __IO uint32_t ROUTE;
00318 __IO uint32_t LOCK;
00319 } CMU_TypeDef;
00321 #include "efm32g_timer_cc.h"
00322 #include "efm32g_timer.h"
00323 #include "efm32g_usart.h"
00324 #include "efm32g_leuart.h"
00325 #include "efm32g_rtc.h"
00326 #include "efm32g_letimer.h"
00327 #include "efm32g_pcnt.h"
00328 #include "efm32g_acmp.h"
00329 #include "efm32g_prs_ch.h"
00330
00331
00336 typedef struct
00337 {
00338 __IO uint32_t SWPULSE;
00339 __IO uint32_t SWLEVEL;
00341 uint32_t RESERVED0[2];
00343 PRS_CH_TypeDef CH[8];
00344 } PRS_TypeDef;
00346 #include "efm32g_dac.h"
00347 #include "efm32g_gpio_p.h"
00348 #include "efm32g_gpio.h"
00349 #include "efm32g_vcmp.h"
00350 #include "efm32g_adc.h"
00351 #include "efm32g_i2c.h"
00352 #include "efm32g_wdog.h"
00353 #include "efm32g_dma_descriptor.h"
00354 #include "efm32g_devinfo.h"
00355 #include "efm32g_romtable.h"
00356 #include "efm32g_calibrate.h"
00357
00360
00365 #define AES_BASE (0x400E0000UL)
00366 #define DMA_BASE (0x400C2000UL)
00367 #define MSC_BASE (0x400C0000UL)
00368 #define EMU_BASE (0x400C6000UL)
00369 #define RMU_BASE (0x400CA000UL)
00370 #define CMU_BASE (0x400C8000UL)
00371 #define TIMER0_BASE (0x40010000UL)
00372 #define TIMER1_BASE (0x40010400UL)
00373 #define USART0_BASE (0x4000C000UL)
00374 #define USART1_BASE (0x4000C400UL)
00375 #define LEUART0_BASE (0x40084000UL)
00376 #define RTC_BASE (0x40080000UL)
00377 #define LETIMER0_BASE (0x40082000UL)
00378 #define PCNT0_BASE (0x40086000UL)
00379 #define ACMP0_BASE (0x40001000UL)
00380 #define ACMP1_BASE (0x40001400UL)
00381 #define PRS_BASE (0x400CC000UL)
00382 #define DAC0_BASE (0x40004000UL)
00383 #define GPIO_BASE (0x40006000UL)
00384 #define VCMP_BASE (0x40000000UL)
00385 #define ADC0_BASE (0x40002000UL)
00386 #define I2C0_BASE (0x4000A000UL)
00387 #define WDOG_BASE (0x40088000UL)
00388 #define CALIBRATE_BASE (0x0FE08000UL)
00389 #define DEVINFO_BASE (0x0FE081B0UL)
00390 #define ROMTABLE_BASE (0xE00FFFD0UL)
00391 #define LOCKBITS_BASE (0x0FE04000UL)
00392 #define USERDATA_BASE (0x0FE00000UL)
00396
00401 #define AES ((AES_TypeDef *) AES_BASE)
00402 #define DMA ((DMA_TypeDef *) DMA_BASE)
00403 #define MSC ((MSC_TypeDef *) MSC_BASE)
00404 #define EMU ((EMU_TypeDef *) EMU_BASE)
00405 #define RMU ((RMU_TypeDef *) RMU_BASE)
00406 #define CMU ((CMU_TypeDef *) CMU_BASE)
00407 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00408 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00409 #define USART0 ((USART_TypeDef *) USART0_BASE)
00410 #define USART1 ((USART_TypeDef *) USART1_BASE)
00411 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00412 #define RTC ((RTC_TypeDef *) RTC_BASE)
00413 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
00414 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00415 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00416 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
00417 #define PRS ((PRS_TypeDef *) PRS_BASE)
00418 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
00419 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00420 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00421 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00422 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00423 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00424 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00425 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00426 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00430
00435
00441 #define PRS_VCMP_OUT ((1 << 16) + 0)
00442 #define PRS_ACMP0_OUT ((2 << 16) + 0)
00443 #define PRS_ACMP1_OUT ((3 << 16) + 0)
00444 #define PRS_DAC0_CH0 ((6 << 16) + 0)
00445 #define PRS_DAC0_CH1 ((6 << 16) + 1)
00446 #define PRS_ADC0_SINGLE ((8 << 16) + 0)
00447 #define PRS_ADC0_SCAN ((8 << 16) + 1)
00448 #define PRS_USART0_IRTX ((16 << 16) + 0)
00449 #define PRS_USART0_TXC ((16 << 16) + 1)
00450 #define PRS_USART0_RXDATAV ((16 << 16) + 2)
00451 #define PRS_USART1_IRTX ((17 << 16) + 0)
00452 #define PRS_USART1_TXC ((17 << 16) + 1)
00453 #define PRS_USART1_RXDATAV ((17 << 16) + 2)
00454 #define PRS_TIMER0_UF ((28 << 16) + 0)
00455 #define PRS_TIMER0_OF ((28 << 16) + 1)
00456 #define PRS_TIMER0_CC0 ((28 << 16) + 2)
00457 #define PRS_TIMER0_CC1 ((28 << 16) + 3)
00458 #define PRS_TIMER0_CC2 ((28 << 16) + 4)
00459 #define PRS_TIMER1_UF ((29 << 16) + 0)
00460 #define PRS_TIMER1_OF ((29 << 16) + 1)
00461 #define PRS_TIMER1_CC0 ((29 << 16) + 2)
00462 #define PRS_TIMER1_CC1 ((29 << 16) + 3)
00463 #define PRS_TIMER1_CC2 ((29 << 16) + 4)
00464 #define PRS_RTC_OF ((40 << 16) + 0)
00465 #define PRS_RTC_COMP0 ((40 << 16) + 1)
00466 #define PRS_RTC_COMP1 ((40 << 16) + 2)
00467 #define PRS_GPIO_PIN0 ((48 << 16) + 0)
00468 #define PRS_GPIO_PIN1 ((48 << 16) + 1)
00469 #define PRS_GPIO_PIN2 ((48 << 16) + 2)
00470 #define PRS_GPIO_PIN3 ((48 << 16) + 3)
00471 #define PRS_GPIO_PIN4 ((48 << 16) + 4)
00472 #define PRS_GPIO_PIN5 ((48 << 16) + 5)
00473 #define PRS_GPIO_PIN6 ((48 << 16) + 6)
00474 #define PRS_GPIO_PIN7 ((48 << 16) + 7)
00475 #define PRS_GPIO_PIN8 ((49 << 16) + 0)
00476 #define PRS_GPIO_PIN9 ((49 << 16) + 1)
00477 #define PRS_GPIO_PIN10 ((49 << 16) + 2)
00478 #define PRS_GPIO_PIN11 ((49 << 16) + 3)
00479 #define PRS_GPIO_PIN12 ((49 << 16) + 4)
00480 #define PRS_GPIO_PIN13 ((49 << 16) + 5)
00481 #define PRS_GPIO_PIN14 ((49 << 16) + 6)
00482 #define PRS_GPIO_PIN15 ((49 << 16) + 7)
00486 #include "efm32g_dmareq.h"
00487 #include "efm32g_dmactrl.h"
00488
00489
00494
00495 #define _DMA_STATUS_RESETVALUE 0x10070000UL
00496 #define _DMA_STATUS_MASK 0x001F00F1UL
00497 #define DMA_STATUS_EN (0x1UL << 0)
00498 #define _DMA_STATUS_EN_SHIFT 0
00499 #define _DMA_STATUS_EN_MASK 0x1UL
00500 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL
00501 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
00502 #define _DMA_STATUS_STATE_SHIFT 4
00503 #define _DMA_STATUS_STATE_MASK 0xF0UL
00504 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL
00505 #define _DMA_STATUS_STATE_IDLE 0x00000000UL
00506 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
00507 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
00508 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
00509 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
00510 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
00511 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
00512 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
00513 #define _DMA_STATUS_STATE_STALLED 0x00000008UL
00514 #define _DMA_STATUS_STATE_DONE 0x00000009UL
00515 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
00516 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
00517 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
00518 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
00519 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
00520 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
00521 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
00522 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
00523 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
00524 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
00525 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
00526 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
00527 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
00528 #define _DMA_STATUS_CHNUM_SHIFT 16
00529 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL
00530 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL
00531 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
00533
00534 #define _DMA_CONFIG_RESETVALUE 0x00000000UL
00535 #define _DMA_CONFIG_MASK 0x00000021UL
00536 #define DMA_CONFIG_EN (0x1UL << 0)
00537 #define _DMA_CONFIG_EN_SHIFT 0
00538 #define _DMA_CONFIG_EN_MASK 0x1UL
00539 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL
00540 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
00541 #define DMA_CONFIG_CHPROT (0x1UL << 5)
00542 #define _DMA_CONFIG_CHPROT_SHIFT 5
00543 #define _DMA_CONFIG_CHPROT_MASK 0x20UL
00544 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
00545 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
00547
00548 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL
00549 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL
00550 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0
00551 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
00552 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
00553 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
00555
00556 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL
00557 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00558 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
00559 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00560 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL
00561 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
00563
00564 #define _DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL
00565 #define _DMA_CHWAITSTATUS_MASK 0x000000FFUL
00566 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
00567 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
00568 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
00569 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
00570 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
00571 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
00572 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
00573 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
00574 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
00575 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
00576 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
00577 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
00578 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
00579 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
00580 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
00581 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
00582 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
00583 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
00584 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
00585 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
00586 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)
00587 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4
00588 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL
00589 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL
00590 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
00591 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)
00592 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5
00593 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL
00594 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL
00595 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
00596 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6)
00597 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6
00598 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL
00599 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL
00600 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
00601 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7)
00602 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7
00603 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL
00604 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL
00605 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
00607
00608 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL
00609 #define _DMA_CHSWREQ_MASK 0x000000FFUL
00610 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
00611 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0
00612 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
00613 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
00614 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
00615 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
00616 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1
00617 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
00618 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
00619 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
00620 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
00621 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2
00622 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
00623 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
00624 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
00625 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
00626 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3
00627 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
00628 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
00629 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
00630 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)
00631 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4
00632 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL
00633 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL
00634 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
00635 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)
00636 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5
00637 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL
00638 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL
00639 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
00640 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6)
00641 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6
00642 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL
00643 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL
00644 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
00645 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7)
00646 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7
00647 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL
00648 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL
00649 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
00651
00652 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
00653 #define _DMA_CHUSEBURSTS_MASK 0x000000FFUL
00654 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
00655 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
00656 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
00657 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
00658 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
00659 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
00660 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
00661 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
00662 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
00663 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
00664 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
00665 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
00666 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
00667 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
00668 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
00669 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
00670 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
00671 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
00672 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
00673 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
00674 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
00675 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
00676 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
00677 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
00678 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)
00679 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4
00680 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL
00681 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL
00682 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
00683 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)
00684 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5
00685 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL
00686 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL
00687 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
00688 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6)
00689 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6
00690 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL
00691 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL
00692 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
00693 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7)
00694 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7
00695 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL
00696 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL
00697 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
00699
00700 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
00701 #define _DMA_CHUSEBURSTC_MASK 0x000000FFUL
00702 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
00703 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
00704 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
00705 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
00706 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
00707 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
00708 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
00709 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
00710 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
00711 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
00712 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
00713 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
00714 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
00715 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
00716 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
00717 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
00718 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
00719 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
00720 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
00721 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
00722 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)
00723 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4
00724 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL
00725 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL
00726 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
00727 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)
00728 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5
00729 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL
00730 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL
00731 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
00732 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6)
00733 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6
00734 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL
00735 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL
00736 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
00737 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7)
00738 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7
00739 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL
00740 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL
00741 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
00743
00744 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
00745 #define _DMA_CHREQMASKS_MASK 0x000000FFUL
00746 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
00747 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
00748 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
00749 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
00750 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
00751 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
00752 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
00753 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
00754 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
00755 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
00756 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
00757 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
00758 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
00759 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
00760 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
00761 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
00762 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
00763 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
00764 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
00765 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
00766 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)
00767 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
00768 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
00769 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
00770 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
00771 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)
00772 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
00773 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
00774 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
00775 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
00776 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6)
00777 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6
00778 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL
00779 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL
00780 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
00781 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7)
00782 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7
00783 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL
00784 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL
00785 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
00787
00788 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
00789 #define _DMA_CHREQMASKC_MASK 0x000000FFUL
00790 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
00791 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
00792 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
00793 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
00794 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
00795 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
00796 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
00797 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
00798 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
00799 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
00800 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
00801 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
00802 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
00803 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
00804 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
00805 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
00806 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
00807 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
00808 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
00809 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
00810 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)
00811 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
00812 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
00813 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
00814 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
00815 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)
00816 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
00817 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
00818 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
00819 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
00820 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6)
00821 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6
00822 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL
00823 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL
00824 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
00825 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7)
00826 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7
00827 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL
00828 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL
00829 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
00831
00832 #define _DMA_CHENS_RESETVALUE 0x00000000UL
00833 #define _DMA_CHENS_MASK 0x000000FFUL
00834 #define DMA_CHENS_CH0ENS (0x1UL << 0)
00835 #define _DMA_CHENS_CH0ENS_SHIFT 0
00836 #define _DMA_CHENS_CH0ENS_MASK 0x1UL
00837 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
00838 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
00839 #define DMA_CHENS_CH1ENS (0x1UL << 1)
00840 #define _DMA_CHENS_CH1ENS_SHIFT 1
00841 #define _DMA_CHENS_CH1ENS_MASK 0x2UL
00842 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
00843 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
00844 #define DMA_CHENS_CH2ENS (0x1UL << 2)
00845 #define _DMA_CHENS_CH2ENS_SHIFT 2
00846 #define _DMA_CHENS_CH2ENS_MASK 0x4UL
00847 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
00848 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
00849 #define DMA_CHENS_CH3ENS (0x1UL << 3)
00850 #define _DMA_CHENS_CH3ENS_SHIFT 3
00851 #define _DMA_CHENS_CH3ENS_MASK 0x8UL
00852 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
00853 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
00854 #define DMA_CHENS_CH4ENS (0x1UL << 4)
00855 #define _DMA_CHENS_CH4ENS_SHIFT 4
00856 #define _DMA_CHENS_CH4ENS_MASK 0x10UL
00857 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
00858 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)
00859 #define DMA_CHENS_CH5ENS (0x1UL << 5)
00860 #define _DMA_CHENS_CH5ENS_SHIFT 5
00861 #define _DMA_CHENS_CH5ENS_MASK 0x20UL
00862 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
00863 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)
00864 #define DMA_CHENS_CH6ENS (0x1UL << 6)
00865 #define _DMA_CHENS_CH6ENS_SHIFT 6
00866 #define _DMA_CHENS_CH6ENS_MASK 0x40UL
00867 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL
00868 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6)
00869 #define DMA_CHENS_CH7ENS (0x1UL << 7)
00870 #define _DMA_CHENS_CH7ENS_SHIFT 7
00871 #define _DMA_CHENS_CH7ENS_MASK 0x80UL
00872 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL
00873 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7)
00875
00876 #define _DMA_CHENC_RESETVALUE 0x00000000UL
00877 #define _DMA_CHENC_MASK 0x000000FFUL
00878 #define DMA_CHENC_CH0ENC (0x1UL << 0)
00879 #define _DMA_CHENC_CH0ENC_SHIFT 0
00880 #define _DMA_CHENC_CH0ENC_MASK 0x1UL
00881 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
00882 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
00883 #define DMA_CHENC_CH1ENC (0x1UL << 1)
00884 #define _DMA_CHENC_CH1ENC_SHIFT 1
00885 #define _DMA_CHENC_CH1ENC_MASK 0x2UL
00886 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
00887 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
00888 #define DMA_CHENC_CH2ENC (0x1UL << 2)
00889 #define _DMA_CHENC_CH2ENC_SHIFT 2
00890 #define _DMA_CHENC_CH2ENC_MASK 0x4UL
00891 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
00892 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
00893 #define DMA_CHENC_CH3ENC (0x1UL << 3)
00894 #define _DMA_CHENC_CH3ENC_SHIFT 3
00895 #define _DMA_CHENC_CH3ENC_MASK 0x8UL
00896 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
00897 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
00898 #define DMA_CHENC_CH4ENC (0x1UL << 4)
00899 #define _DMA_CHENC_CH4ENC_SHIFT 4
00900 #define _DMA_CHENC_CH4ENC_MASK 0x10UL
00901 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
00902 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)
00903 #define DMA_CHENC_CH5ENC (0x1UL << 5)
00904 #define _DMA_CHENC_CH5ENC_SHIFT 5
00905 #define _DMA_CHENC_CH5ENC_MASK 0x20UL
00906 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
00907 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)
00908 #define DMA_CHENC_CH6ENC (0x1UL << 6)
00909 #define _DMA_CHENC_CH6ENC_SHIFT 6
00910 #define _DMA_CHENC_CH6ENC_MASK 0x40UL
00911 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL
00912 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6)
00913 #define DMA_CHENC_CH7ENC (0x1UL << 7)
00914 #define _DMA_CHENC_CH7ENC_SHIFT 7
00915 #define _DMA_CHENC_CH7ENC_MASK 0x80UL
00916 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL
00917 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7)
00919
00920 #define _DMA_CHALTS_RESETVALUE 0x00000000UL
00921 #define _DMA_CHALTS_MASK 0x000000FFUL
00922 #define DMA_CHALTS_CH0ALTS (0x1UL << 0)
00923 #define _DMA_CHALTS_CH0ALTS_SHIFT 0
00924 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
00925 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
00926 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
00927 #define DMA_CHALTS_CH1ALTS (0x1UL << 1)
00928 #define _DMA_CHALTS_CH1ALTS_SHIFT 1
00929 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
00930 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
00931 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
00932 #define DMA_CHALTS_CH2ALTS (0x1UL << 2)
00933 #define _DMA_CHALTS_CH2ALTS_SHIFT 2
00934 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
00935 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
00936 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
00937 #define DMA_CHALTS_CH3ALTS (0x1UL << 3)
00938 #define _DMA_CHALTS_CH3ALTS_SHIFT 3
00939 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
00940 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
00941 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
00942 #define DMA_CHALTS_CH4ALTS (0x1UL << 4)
00943 #define _DMA_CHALTS_CH4ALTS_SHIFT 4
00944 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL
00945 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
00946 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
00947 #define DMA_CHALTS_CH5ALTS (0x1UL << 5)
00948 #define _DMA_CHALTS_CH5ALTS_SHIFT 5
00949 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL
00950 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
00951 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
00952 #define DMA_CHALTS_CH6ALTS (0x1UL << 6)
00953 #define _DMA_CHALTS_CH6ALTS_SHIFT 6
00954 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL
00955 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL
00956 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
00957 #define DMA_CHALTS_CH7ALTS (0x1UL << 7)
00958 #define _DMA_CHALTS_CH7ALTS_SHIFT 7
00959 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL
00960 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL
00961 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
00963
00964 #define _DMA_CHALTC_RESETVALUE 0x00000000UL
00965 #define _DMA_CHALTC_MASK 0x000000FFUL
00966 #define DMA_CHALTC_CH0ALTC (0x1UL << 0)
00967 #define _DMA_CHALTC_CH0ALTC_SHIFT 0
00968 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
00969 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
00970 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
00971 #define DMA_CHALTC_CH1ALTC (0x1UL << 1)
00972 #define _DMA_CHALTC_CH1ALTC_SHIFT 1
00973 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
00974 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
00975 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
00976 #define DMA_CHALTC_CH2ALTC (0x1UL << 2)
00977 #define _DMA_CHALTC_CH2ALTC_SHIFT 2
00978 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
00979 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
00980 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
00981 #define DMA_CHALTC_CH3ALTC (0x1UL << 3)
00982 #define _DMA_CHALTC_CH3ALTC_SHIFT 3
00983 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
00984 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
00985 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
00986 #define DMA_CHALTC_CH4ALTC (0x1UL << 4)
00987 #define _DMA_CHALTC_CH4ALTC_SHIFT 4
00988 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL
00989 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
00990 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
00991 #define DMA_CHALTC_CH5ALTC (0x1UL << 5)
00992 #define _DMA_CHALTC_CH5ALTC_SHIFT 5
00993 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL
00994 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
00995 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
00996 #define DMA_CHALTC_CH6ALTC (0x1UL << 6)
00997 #define _DMA_CHALTC_CH6ALTC_SHIFT 6
00998 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL
00999 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL
01000 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
01001 #define DMA_CHALTC_CH7ALTC (0x1UL << 7)
01002 #define _DMA_CHALTC_CH7ALTC_SHIFT 7
01003 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL
01004 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL
01005 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
01007
01008 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL
01009 #define _DMA_CHPRIS_MASK 0x000000FFUL
01010 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0)
01011 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0
01012 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
01013 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
01014 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
01015 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1)
01016 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1
01017 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
01018 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
01019 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
01020 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2)
01021 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2
01022 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
01023 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
01024 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
01025 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3)
01026 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3
01027 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
01028 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
01029 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
01030 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4)
01031 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4
01032 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL
01033 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
01034 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
01035 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5)
01036 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5
01037 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL
01038 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
01039 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
01040 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6)
01041 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6
01042 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL
01043 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL
01044 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
01045 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7)
01046 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7
01047 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL
01048 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL
01049 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
01051
01052 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL
01053 #define _DMA_CHPRIC_MASK 0x000000FFUL
01054 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0)
01055 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0
01056 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
01057 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
01058 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
01059 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1)
01060 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1
01061 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
01062 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
01063 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
01064 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2)
01065 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2
01066 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
01067 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
01068 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
01069 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3)
01070 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3
01071 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
01072 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
01073 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
01074 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4)
01075 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4
01076 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL
01077 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
01078 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
01079 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5)
01080 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5
01081 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL
01082 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
01083 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
01084 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6)
01085 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6
01086 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL
01087 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL
01088 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
01089 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7)
01090 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7
01091 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL
01092 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL
01093 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
01095
01096 #define _DMA_ERRORC_RESETVALUE 0x00000000UL
01097 #define _DMA_ERRORC_MASK 0x00000001UL
01098 #define DMA_ERRORC_ERRORC (0x1UL << 0)
01099 #define _DMA_ERRORC_ERRORC_SHIFT 0
01100 #define _DMA_ERRORC_ERRORC_MASK 0x1UL
01101 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
01102 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
01104
01105 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
01106 #define _DMA_CHREQSTATUS_MASK 0x000000FFUL
01107 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
01108 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
01109 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
01110 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
01111 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
01112 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
01113 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
01114 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
01115 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
01116 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
01117 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
01118 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
01119 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
01120 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
01121 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
01122 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
01123 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
01124 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
01125 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
01126 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
01127 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)
01128 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
01129 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
01130 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
01131 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
01132 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)
01133 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
01134 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
01135 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
01136 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
01137 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6)
01138 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6
01139 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL
01140 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL
01141 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
01142 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7)
01143 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7
01144 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL
01145 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL
01146 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
01148
01149 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
01150 #define _DMA_CHSREQSTATUS_MASK 0x000000FFUL
01151 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
01152 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
01153 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
01154 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
01155 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
01156 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
01157 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
01158 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
01159 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
01160 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
01161 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
01162 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
01163 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
01164 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
01165 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
01166 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
01167 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
01168 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
01169 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
01170 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
01171 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)
01172 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
01173 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
01174 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
01175 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
01176 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)
01177 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
01178 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
01179 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
01180 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
01181 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6)
01182 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6
01183 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL
01184 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL
01185 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
01186 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7)
01187 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7
01188 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL
01189 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL
01190 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
01192
01193 #define _DMA_IF_RESETVALUE 0x00000000UL
01194 #define _DMA_IF_MASK 0x800000FFUL
01195 #define DMA_IF_CH0DONE (0x1UL << 0)
01196 #define _DMA_IF_CH0DONE_SHIFT 0
01197 #define _DMA_IF_CH0DONE_MASK 0x1UL
01198 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL
01199 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
01200 #define DMA_IF_CH1DONE (0x1UL << 1)
01201 #define _DMA_IF_CH1DONE_SHIFT 1
01202 #define _DMA_IF_CH1DONE_MASK 0x2UL
01203 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL
01204 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
01205 #define DMA_IF_CH2DONE (0x1UL << 2)
01206 #define _DMA_IF_CH2DONE_SHIFT 2
01207 #define _DMA_IF_CH2DONE_MASK 0x4UL
01208 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL
01209 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
01210 #define DMA_IF_CH3DONE (0x1UL << 3)
01211 #define _DMA_IF_CH3DONE_SHIFT 3
01212 #define _DMA_IF_CH3DONE_MASK 0x8UL
01213 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL
01214 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
01215 #define DMA_IF_CH4DONE (0x1UL << 4)
01216 #define _DMA_IF_CH4DONE_SHIFT 4
01217 #define _DMA_IF_CH4DONE_MASK 0x10UL
01218 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL
01219 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)
01220 #define DMA_IF_CH5DONE (0x1UL << 5)
01221 #define _DMA_IF_CH5DONE_SHIFT 5
01222 #define _DMA_IF_CH5DONE_MASK 0x20UL
01223 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL
01224 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)
01225 #define DMA_IF_CH6DONE (0x1UL << 6)
01226 #define _DMA_IF_CH6DONE_SHIFT 6
01227 #define _DMA_IF_CH6DONE_MASK 0x40UL
01228 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL
01229 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6)
01230 #define DMA_IF_CH7DONE (0x1UL << 7)
01231 #define _DMA_IF_CH7DONE_SHIFT 7
01232 #define _DMA_IF_CH7DONE_MASK 0x80UL
01233 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL
01234 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7)
01235 #define DMA_IF_ERR (0x1UL << 31)
01236 #define _DMA_IF_ERR_SHIFT 31
01237 #define _DMA_IF_ERR_MASK 0x80000000UL
01238 #define _DMA_IF_ERR_DEFAULT 0x00000000UL
01239 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
01241
01242 #define _DMA_IFS_RESETVALUE 0x00000000UL
01243 #define _DMA_IFS_MASK 0x800000FFUL
01244 #define DMA_IFS_CH0DONE (0x1UL << 0)
01245 #define _DMA_IFS_CH0DONE_SHIFT 0
01246 #define _DMA_IFS_CH0DONE_MASK 0x1UL
01247 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
01248 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
01249 #define DMA_IFS_CH1DONE (0x1UL << 1)
01250 #define _DMA_IFS_CH1DONE_SHIFT 1
01251 #define _DMA_IFS_CH1DONE_MASK 0x2UL
01252 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
01253 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
01254 #define DMA_IFS_CH2DONE (0x1UL << 2)
01255 #define _DMA_IFS_CH2DONE_SHIFT 2
01256 #define _DMA_IFS_CH2DONE_MASK 0x4UL
01257 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
01258 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
01259 #define DMA_IFS_CH3DONE (0x1UL << 3)
01260 #define _DMA_IFS_CH3DONE_SHIFT 3
01261 #define _DMA_IFS_CH3DONE_MASK 0x8UL
01262 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
01263 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
01264 #define DMA_IFS_CH4DONE (0x1UL << 4)
01265 #define _DMA_IFS_CH4DONE_SHIFT 4
01266 #define _DMA_IFS_CH4DONE_MASK 0x10UL
01267 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL
01268 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)
01269 #define DMA_IFS_CH5DONE (0x1UL << 5)
01270 #define _DMA_IFS_CH5DONE_SHIFT 5
01271 #define _DMA_IFS_CH5DONE_MASK 0x20UL
01272 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL
01273 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)
01274 #define DMA_IFS_CH6DONE (0x1UL << 6)
01275 #define _DMA_IFS_CH6DONE_SHIFT 6
01276 #define _DMA_IFS_CH6DONE_MASK 0x40UL
01277 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL
01278 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6)
01279 #define DMA_IFS_CH7DONE (0x1UL << 7)
01280 #define _DMA_IFS_CH7DONE_SHIFT 7
01281 #define _DMA_IFS_CH7DONE_MASK 0x80UL
01282 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL
01283 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7)
01284 #define DMA_IFS_ERR (0x1UL << 31)
01285 #define _DMA_IFS_ERR_SHIFT 31
01286 #define _DMA_IFS_ERR_MASK 0x80000000UL
01287 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL
01288 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
01290
01291 #define _DMA_IFC_RESETVALUE 0x00000000UL
01292 #define _DMA_IFC_MASK 0x800000FFUL
01293 #define DMA_IFC_CH0DONE (0x1UL << 0)
01294 #define _DMA_IFC_CH0DONE_SHIFT 0
01295 #define _DMA_IFC_CH0DONE_MASK 0x1UL
01296 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
01297 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
01298 #define DMA_IFC_CH1DONE (0x1UL << 1)
01299 #define _DMA_IFC_CH1DONE_SHIFT 1
01300 #define _DMA_IFC_CH1DONE_MASK 0x2UL
01301 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
01302 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
01303 #define DMA_IFC_CH2DONE (0x1UL << 2)
01304 #define _DMA_IFC_CH2DONE_SHIFT 2
01305 #define _DMA_IFC_CH2DONE_MASK 0x4UL
01306 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
01307 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
01308 #define DMA_IFC_CH3DONE (0x1UL << 3)
01309 #define _DMA_IFC_CH3DONE_SHIFT 3
01310 #define _DMA_IFC_CH3DONE_MASK 0x8UL
01311 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
01312 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
01313 #define DMA_IFC_CH4DONE (0x1UL << 4)
01314 #define _DMA_IFC_CH4DONE_SHIFT 4
01315 #define _DMA_IFC_CH4DONE_MASK 0x10UL
01316 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL
01317 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)
01318 #define DMA_IFC_CH5DONE (0x1UL << 5)
01319 #define _DMA_IFC_CH5DONE_SHIFT 5
01320 #define _DMA_IFC_CH5DONE_MASK 0x20UL
01321 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL
01322 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)
01323 #define DMA_IFC_CH6DONE (0x1UL << 6)
01324 #define _DMA_IFC_CH6DONE_SHIFT 6
01325 #define _DMA_IFC_CH6DONE_MASK 0x40UL
01326 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL
01327 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6)
01328 #define DMA_IFC_CH7DONE (0x1UL << 7)
01329 #define _DMA_IFC_CH7DONE_SHIFT 7
01330 #define _DMA_IFC_CH7DONE_MASK 0x80UL
01331 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL
01332 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7)
01333 #define DMA_IFC_ERR (0x1UL << 31)
01334 #define _DMA_IFC_ERR_SHIFT 31
01335 #define _DMA_IFC_ERR_MASK 0x80000000UL
01336 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL
01337 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
01339
01340 #define _DMA_IEN_RESETVALUE 0x00000000UL
01341 #define _DMA_IEN_MASK 0x800000FFUL
01342 #define DMA_IEN_CH0DONE (0x1UL << 0)
01343 #define _DMA_IEN_CH0DONE_SHIFT 0
01344 #define _DMA_IEN_CH0DONE_MASK 0x1UL
01345 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
01346 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
01347 #define DMA_IEN_CH1DONE (0x1UL << 1)
01348 #define _DMA_IEN_CH1DONE_SHIFT 1
01349 #define _DMA_IEN_CH1DONE_MASK 0x2UL
01350 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
01351 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
01352 #define DMA_IEN_CH2DONE (0x1UL << 2)
01353 #define _DMA_IEN_CH2DONE_SHIFT 2
01354 #define _DMA_IEN_CH2DONE_MASK 0x4UL
01355 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
01356 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
01357 #define DMA_IEN_CH3DONE (0x1UL << 3)
01358 #define _DMA_IEN_CH3DONE_SHIFT 3
01359 #define _DMA_IEN_CH3DONE_MASK 0x8UL
01360 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
01361 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
01362 #define DMA_IEN_CH4DONE (0x1UL << 4)
01363 #define _DMA_IEN_CH4DONE_SHIFT 4
01364 #define _DMA_IEN_CH4DONE_MASK 0x10UL
01365 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL
01366 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)
01367 #define DMA_IEN_CH5DONE (0x1UL << 5)
01368 #define _DMA_IEN_CH5DONE_SHIFT 5
01369 #define _DMA_IEN_CH5DONE_MASK 0x20UL
01370 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL
01371 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)
01372 #define DMA_IEN_CH6DONE (0x1UL << 6)
01373 #define _DMA_IEN_CH6DONE_SHIFT 6
01374 #define _DMA_IEN_CH6DONE_MASK 0x40UL
01375 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL
01376 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6)
01377 #define DMA_IEN_CH7DONE (0x1UL << 7)
01378 #define _DMA_IEN_CH7DONE_SHIFT 7
01379 #define _DMA_IEN_CH7DONE_MASK 0x80UL
01380 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL
01381 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7)
01382 #define DMA_IEN_ERR (0x1UL << 31)
01383 #define _DMA_IEN_ERR_SHIFT 31
01384 #define _DMA_IEN_ERR_MASK 0x80000000UL
01385 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL
01386 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
01388
01389 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
01390 #define _DMA_CH_CTRL_MASK 0x003F000FUL
01391 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0
01392 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
01393 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
01394 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
01395 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL
01396 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
01397 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
01398 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
01399 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
01400 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
01401 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
01402 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL
01403 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
01404 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
01405 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL
01406 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
01407 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
01408 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
01409 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
01410 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
01411 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL
01412 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL
01413 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
01414 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
01415 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
01416 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
01417 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL
01418 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
01419 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
01420 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL
01421 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
01422 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0)
01423 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
01424 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
01425 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
01426 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
01427 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
01428 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
01429 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
01430 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
01431 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
01432 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0)
01433 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)
01434 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
01435 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
01436 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
01437 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
01438 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
01439 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
01440 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)
01441 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
01442 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
01443 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
01444 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
01445 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
01446 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
01447 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
01448 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
01449 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
01450 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
01451 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
01452 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
01453 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL
01454 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL
01455 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
01456 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
01457 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
01458 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
01459 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
01460 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
01461 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL
01462 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
01463 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
01464 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16)
01465 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)
01466 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
01467 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
01468 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
01469 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
01470 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
01471 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
01472 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)
01478
01483
01484 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
01485 #define _CMU_CTRL_MASK 0x00FE3EEFUL
01486 #define _CMU_CTRL_HFXOMODE_SHIFT 0
01487 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
01488 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
01489 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
01490 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
01491 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
01492 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
01493 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
01494 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
01495 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
01496 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
01497 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
01498 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
01499 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
01500 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
01501 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
01502 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
01503 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
01504 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
01505 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
01506 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
01507 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
01508 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
01509 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
01510 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
01511 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
01512 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
01513 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
01514 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
01515 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
01516 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
01517 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
01518 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
01519 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
01520 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
01521 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
01522 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
01523 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
01524 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
01525 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
01526 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
01527 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
01528 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
01529 #define _CMU_CTRL_LFXOMODE_SHIFT 11
01530 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
01531 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
01532 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
01533 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
01534 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
01535 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
01536 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
01537 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
01538 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
01539 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
01540 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
01541 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
01542 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
01543 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
01544 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
01545 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
01546 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
01547 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
01548 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
01549 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
01550 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
01551 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
01552 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
01553 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
01554 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
01555 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
01556 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
01557 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
01558 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
01559 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
01560 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
01561 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
01562 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
01563 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
01564 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
01565 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
01566 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
01567 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
01568 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
01569 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
01570 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
01571 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
01572 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
01573 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
01574 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
01575 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
01576 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
01577 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
01578 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
01579 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
01580 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
01581 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
01582 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
01583 #define CMU_CTRL_CLKOUTSEL1 (0x1UL << 23)
01584 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
01585 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL
01586 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
01587 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
01588 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
01589 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
01590 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
01591 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
01593
01594 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
01595 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
01596 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
01597 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
01598 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
01599 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
01600 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
01601 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
01602 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
01603 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
01604 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
01605 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
01606 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
01607 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
01608 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
01609 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
01610 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
01611 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
01612 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
01613 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
01614 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
01615 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
01616 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
01617 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
01618 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
01619 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
01621
01622 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
01623 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
01624 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
01625 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
01626 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
01627 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
01628 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
01629 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
01630 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
01631 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
01632 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
01633 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
01634 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
01635 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
01636 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
01637 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
01638 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
01639 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
01640 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
01641 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
01642 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
01643 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
01644 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
01645 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
01646 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
01647 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
01648 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
01649 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
01650 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
01651 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
01652 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
01654
01655 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
01656 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
01657 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
01658 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
01659 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01660 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
01661 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
01662 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
01663 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
01664 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
01665 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
01666 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
01667 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
01668 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
01669 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
01670 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
01671 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
01672 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
01673 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
01674 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
01675 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
01676 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
01677 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
01678 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
01679 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
01680 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
01682
01683 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
01684 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
01685 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
01686 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
01687 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
01688 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
01690
01691 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
01692 #define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL
01693 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
01694 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
01695 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01696 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
01698
01699 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
01700 #define _CMU_CALCTRL_MASK 0x00000007UL
01701 #define _CMU_CALCTRL_UPSEL_SHIFT 0
01702 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
01703 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
01704 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
01705 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
01706 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
01707 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
01708 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
01709 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
01710 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
01711 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
01712 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
01713 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
01714 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
01716
01717 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
01718 #define _CMU_CALCNT_MASK 0x000FFFFFUL
01719 #define _CMU_CALCNT_CALCNT_SHIFT 0
01720 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
01721 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
01722 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
01724
01725 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
01726 #define _CMU_OSCENCMD_MASK 0x000003FFUL
01727 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
01728 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
01729 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
01730 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
01731 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
01732 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
01733 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
01734 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
01735 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
01736 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
01737 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
01738 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
01739 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
01740 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
01741 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
01742 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
01743 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
01744 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
01745 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
01746 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
01747 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
01748 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
01749 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
01750 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
01751 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
01752 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
01753 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
01754 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
01755 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
01756 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
01757 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
01758 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
01759 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
01760 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
01761 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
01762 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
01763 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
01764 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
01765 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
01766 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
01767 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
01768 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
01769 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
01770 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
01771 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
01772 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
01773 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
01774 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
01775 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
01776 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
01778
01779 #define _CMU_CMD_RESETVALUE 0x00000000UL
01780 #define _CMU_CMD_MASK 0x0000000FUL
01781 #define _CMU_CMD_HFCLKSEL_SHIFT 0
01782 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
01783 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
01784 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
01785 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
01786 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
01787 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
01788 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
01789 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
01790 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
01791 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
01792 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
01793 #define CMU_CMD_CALSTART (0x1UL << 3)
01794 #define _CMU_CMD_CALSTART_SHIFT 3
01795 #define _CMU_CMD_CALSTART_MASK 0x8UL
01796 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
01797 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
01799
01800 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
01801 #define _CMU_LFCLKSEL_MASK 0x0000000FUL
01802 #define _CMU_LFCLKSEL_LFA_SHIFT 0
01803 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
01804 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
01805 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
01806 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
01807 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
01808 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
01809 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
01810 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
01811 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
01812 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
01813 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
01814 #define _CMU_LFCLKSEL_LFB_SHIFT 2
01815 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
01816 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
01817 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
01818 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
01819 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
01820 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
01821 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
01822 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
01823 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
01824 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
01825 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
01827
01828 #define _CMU_STATUS_RESETVALUE 0x00000403UL
01829 #define _CMU_STATUS_MASK 0x00007FFFUL
01830 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
01831 #define _CMU_STATUS_HFRCOENS_SHIFT 0
01832 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
01833 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
01834 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
01835 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
01836 #define _CMU_STATUS_HFRCORDY_SHIFT 1
01837 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
01838 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
01839 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
01840 #define CMU_STATUS_HFXOENS (0x1UL << 2)
01841 #define _CMU_STATUS_HFXOENS_SHIFT 2
01842 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
01843 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
01844 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
01845 #define CMU_STATUS_HFXORDY (0x1UL << 3)
01846 #define _CMU_STATUS_HFXORDY_SHIFT 3
01847 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
01848 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
01849 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
01850 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
01851 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
01852 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
01853 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
01854 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
01855 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
01856 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
01857 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
01858 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
01859 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
01860 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
01861 #define _CMU_STATUS_LFRCOENS_SHIFT 6
01862 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
01863 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
01864 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
01865 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
01866 #define _CMU_STATUS_LFRCORDY_SHIFT 7
01867 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
01868 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
01869 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
01870 #define CMU_STATUS_LFXOENS (0x1UL << 8)
01871 #define _CMU_STATUS_LFXOENS_SHIFT 8
01872 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
01873 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
01874 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
01875 #define CMU_STATUS_LFXORDY (0x1UL << 9)
01876 #define _CMU_STATUS_LFXORDY_SHIFT 9
01877 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
01878 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
01879 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
01880 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
01881 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
01882 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
01883 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
01884 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
01885 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
01886 #define _CMU_STATUS_HFXOSEL_SHIFT 11
01887 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
01888 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
01889 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
01890 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
01891 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
01892 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
01893 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
01894 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
01895 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
01896 #define _CMU_STATUS_LFXOSEL_SHIFT 13
01897 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
01898 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
01899 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
01900 #define CMU_STATUS_CALBSY (0x1UL << 14)
01901 #define _CMU_STATUS_CALBSY_SHIFT 14
01902 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
01903 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
01904 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
01906
01907 #define _CMU_IF_RESETVALUE 0x00000001UL
01908 #define _CMU_IF_MASK 0x0000003FUL
01909 #define CMU_IF_HFRCORDY (0x1UL << 0)
01910 #define _CMU_IF_HFRCORDY_SHIFT 0
01911 #define _CMU_IF_HFRCORDY_MASK 0x1UL
01912 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
01913 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
01914 #define CMU_IF_HFXORDY (0x1UL << 1)
01915 #define _CMU_IF_HFXORDY_SHIFT 1
01916 #define _CMU_IF_HFXORDY_MASK 0x2UL
01917 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
01918 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
01919 #define CMU_IF_LFRCORDY (0x1UL << 2)
01920 #define _CMU_IF_LFRCORDY_SHIFT 2
01921 #define _CMU_IF_LFRCORDY_MASK 0x4UL
01922 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
01923 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
01924 #define CMU_IF_LFXORDY (0x1UL << 3)
01925 #define _CMU_IF_LFXORDY_SHIFT 3
01926 #define _CMU_IF_LFXORDY_MASK 0x8UL
01927 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
01928 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
01929 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
01930 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
01931 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
01932 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
01933 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
01934 #define CMU_IF_CALRDY (0x1UL << 5)
01935 #define _CMU_IF_CALRDY_SHIFT 5
01936 #define _CMU_IF_CALRDY_MASK 0x20UL
01937 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
01938 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
01940
01941 #define _CMU_IFS_RESETVALUE 0x00000000UL
01942 #define _CMU_IFS_MASK 0x0000003FUL
01943 #define CMU_IFS_HFRCORDY (0x1UL << 0)
01944 #define _CMU_IFS_HFRCORDY_SHIFT 0
01945 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
01946 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
01947 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
01948 #define CMU_IFS_HFXORDY (0x1UL << 1)
01949 #define _CMU_IFS_HFXORDY_SHIFT 1
01950 #define _CMU_IFS_HFXORDY_MASK 0x2UL
01951 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
01952 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
01953 #define CMU_IFS_LFRCORDY (0x1UL << 2)
01954 #define _CMU_IFS_LFRCORDY_SHIFT 2
01955 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
01956 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
01957 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
01958 #define CMU_IFS_LFXORDY (0x1UL << 3)
01959 #define _CMU_IFS_LFXORDY_SHIFT 3
01960 #define _CMU_IFS_LFXORDY_MASK 0x8UL
01961 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
01962 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
01963 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
01964 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
01965 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
01966 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
01967 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
01968 #define CMU_IFS_CALRDY (0x1UL << 5)
01969 #define _CMU_IFS_CALRDY_SHIFT 5
01970 #define _CMU_IFS_CALRDY_MASK 0x20UL
01971 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
01972 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
01974
01975 #define _CMU_IFC_RESETVALUE 0x00000000UL
01976 #define _CMU_IFC_MASK 0x0000003FUL
01977 #define CMU_IFC_HFRCORDY (0x1UL << 0)
01978 #define _CMU_IFC_HFRCORDY_SHIFT 0
01979 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
01980 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
01981 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
01982 #define CMU_IFC_HFXORDY (0x1UL << 1)
01983 #define _CMU_IFC_HFXORDY_SHIFT 1
01984 #define _CMU_IFC_HFXORDY_MASK 0x2UL
01985 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
01986 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
01987 #define CMU_IFC_LFRCORDY (0x1UL << 2)
01988 #define _CMU_IFC_LFRCORDY_SHIFT 2
01989 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
01990 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
01991 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
01992 #define CMU_IFC_LFXORDY (0x1UL << 3)
01993 #define _CMU_IFC_LFXORDY_SHIFT 3
01994 #define _CMU_IFC_LFXORDY_MASK 0x8UL
01995 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
01996 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
01997 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
01998 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
01999 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
02000 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
02001 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
02002 #define CMU_IFC_CALRDY (0x1UL << 5)
02003 #define _CMU_IFC_CALRDY_SHIFT 5
02004 #define _CMU_IFC_CALRDY_MASK 0x20UL
02005 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
02006 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
02008
02009 #define _CMU_IEN_RESETVALUE 0x00000000UL
02010 #define _CMU_IEN_MASK 0x0000003FUL
02011 #define CMU_IEN_HFRCORDY (0x1UL << 0)
02012 #define _CMU_IEN_HFRCORDY_SHIFT 0
02013 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
02014 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
02015 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
02016 #define CMU_IEN_HFXORDY (0x1UL << 1)
02017 #define _CMU_IEN_HFXORDY_SHIFT 1
02018 #define _CMU_IEN_HFXORDY_MASK 0x2UL
02019 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
02020 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
02021 #define CMU_IEN_LFRCORDY (0x1UL << 2)
02022 #define _CMU_IEN_LFRCORDY_SHIFT 2
02023 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
02024 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
02025 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
02026 #define CMU_IEN_LFXORDY (0x1UL << 3)
02027 #define _CMU_IEN_LFXORDY_SHIFT 3
02028 #define _CMU_IEN_LFXORDY_MASK 0x8UL
02029 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
02030 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
02031 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
02032 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
02033 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
02034 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
02035 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
02036 #define CMU_IEN_CALRDY (0x1UL << 5)
02037 #define _CMU_IEN_CALRDY_SHIFT 5
02038 #define _CMU_IEN_CALRDY_MASK 0x20UL
02039 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
02040 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
02042
02043 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
02044 #define _CMU_HFCORECLKEN0_MASK 0x00000007UL
02045 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
02046 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
02047 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
02048 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
02049 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
02050 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
02051 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
02052 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
02053 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
02054 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
02055 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
02056 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
02057 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
02058 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
02059 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
02061
02062 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
02063 #define _CMU_HFPERCLKEN0_MASK 0x0000FDB3UL
02064 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0)
02065 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0
02066 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL
02067 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
02068 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
02069 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1)
02070 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1
02071 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL
02072 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
02073 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
02074 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
02075 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
02076 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
02077 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
02078 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
02079 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
02080 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
02081 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
02082 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
02083 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
02084 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7)
02085 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7
02086 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL
02087 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
02088 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)
02089 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8)
02090 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8
02091 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL
02092 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
02093 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)
02094 #define CMU_HFPERCLKEN0_PRS (0x1UL << 10)
02095 #define _CMU_HFPERCLKEN0_PRS_SHIFT 10
02096 #define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL
02097 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
02098 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)
02099 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 11)
02100 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 11
02101 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL
02102 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
02103 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)
02104 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 12)
02105 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 12
02106 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL
02107 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
02108 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)
02109 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 13)
02110 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 13
02111 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL
02112 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
02113 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)
02114 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 14)
02115 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 14
02116 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL
02117 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
02118 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)
02119 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 15)
02120 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 15
02121 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL
02122 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
02123 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)
02125
02126 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
02127 #define _CMU_SYNCBUSY_MASK 0x00000055UL
02128 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
02129 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
02130 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
02131 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
02132 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
02133 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
02134 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
02135 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
02136 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
02137 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
02138 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
02139 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
02140 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
02141 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
02142 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
02143 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
02144 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
02145 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
02146 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
02147 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
02149
02150 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
02151 #define _CMU_FREEZE_MASK 0x00000001UL
02152 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
02153 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
02154 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
02155 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
02156 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
02157 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
02158 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
02159 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
02160 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
02162
02163 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
02164 #define _CMU_LFACLKEN0_MASK 0x00000003UL
02165 #define CMU_LFACLKEN0_RTC (0x1UL << 0)
02166 #define _CMU_LFACLKEN0_RTC_SHIFT 0
02167 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL
02168 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
02169 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
02170 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 1)
02171 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 1
02172 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL
02173 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
02174 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1)
02176
02177 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
02178 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
02179 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
02180 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
02181 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
02182 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
02183 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
02185
02186 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
02187 #define _CMU_LFAPRESC0_MASK 0x000000FFUL
02188 #define _CMU_LFAPRESC0_RTC_SHIFT 0
02189 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL
02190 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
02191 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
02192 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
02193 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
02194 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
02195 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
02196 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
02197 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
02198 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
02199 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
02200 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
02201 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
02202 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
02203 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
02204 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
02205 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
02206 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
02207 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
02208 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
02209 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
02210 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
02211 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
02212 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
02213 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
02214 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
02215 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
02216 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
02217 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
02218 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
02219 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
02220 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
02221 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
02222 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 4
02223 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL
02224 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
02225 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
02226 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
02227 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
02228 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
02229 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
02230 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
02231 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
02232 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
02233 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
02234 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
02235 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
02236 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
02237 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
02238 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
02239 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
02240 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)
02241 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)
02242 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)
02243 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)
02244 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)
02245 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)
02246 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)
02247 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)
02248 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)
02249 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)
02250 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)
02251 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)
02252 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)
02253 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)
02254 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4)
02255 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4)
02257
02258 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
02259 #define _CMU_LFBPRESC0_MASK 0x00000003UL
02260 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
02261 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
02262 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
02263 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
02264 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
02265 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
02266 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
02267 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
02268 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
02269 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
02271
02272 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
02273 #define _CMU_PCNTCTRL_MASK 0x00000003UL
02274 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
02275 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
02276 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
02277 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
02278 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
02279 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
02280 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
02281 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
02282 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
02283 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
02284 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
02285 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
02286 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
02287 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
02289
02290 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
02291 #define _CMU_ROUTE_MASK 0x00000007UL
02292 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
02293 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
02294 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
02295 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
02296 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
02297 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
02298 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
02299 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
02300 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
02301 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
02302 #define CMU_ROUTE_LOCATION (0x1UL << 2)
02303 #define _CMU_ROUTE_LOCATION_SHIFT 2
02304 #define _CMU_ROUTE_LOCATION_MASK 0x4UL
02305 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
02306 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
02307 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
02308 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
02309 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
02310 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
02312
02313 #define _CMU_LOCK_RESETVALUE 0x00000000UL
02314 #define _CMU_LOCK_MASK 0x0000FFFFUL
02315 #define _CMU_LOCK_LOCKKEY_SHIFT 0
02316 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
02317 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
02318 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
02319 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
02320 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
02321 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
02322 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
02323 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
02324 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
02325 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
02326 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
02331
02336
02337 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL
02338 #define _PRS_SWPULSE_MASK 0x000000FFUL
02339 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0)
02340 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0
02341 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL
02342 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL
02343 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)
02344 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1)
02345 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1
02346 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL
02347 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL
02348 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)
02349 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2)
02350 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2
02351 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL
02352 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL
02353 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)
02354 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3)
02355 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3
02356 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL
02357 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL
02358 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)
02359 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4)
02360 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4
02361 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL
02362 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL
02363 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)
02364 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5)
02365 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5
02366 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL
02367 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL
02368 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)
02369 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6)
02370 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6
02371 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL
02372 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL
02373 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)
02374 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7)
02375 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7
02376 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL
02377 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL
02378 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)
02380
02381 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL
02382 #define _PRS_SWLEVEL_MASK 0x000000FFUL
02383 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0)
02384 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0
02385 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL
02386 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL
02387 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)
02388 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1)
02389 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1
02390 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL
02391 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL
02392 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)
02393 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2)
02394 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2
02395 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL
02396 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL
02397 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)
02398 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3)
02399 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3
02400 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL
02401 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL
02402 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)
02403 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4)
02404 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4
02405 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL
02406 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL
02407 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)
02408 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5)
02409 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5
02410 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL
02411 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL
02412 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)
02413 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6)
02414 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6
02415 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL
02416 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL
02417 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)
02418 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7)
02419 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7
02420 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL
02421 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL
02422 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)
02424
02425 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL
02426 #define _PRS_CH_CTRL_MASK 0x033F0007UL
02427 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0
02428 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL
02429 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL
02430 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL
02431 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL
02432 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL
02433 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
02434 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL
02435 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL
02436 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL
02437 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL
02438 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL
02439 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL
02440 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL
02441 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
02442 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL
02443 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL
02444 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL
02445 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL
02446 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL
02447 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL
02448 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL
02449 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL
02450 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL
02451 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL
02452 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL
02453 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL
02454 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL
02455 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL
02456 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL
02457 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL
02458 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL
02459 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL
02460 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL
02461 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL
02462 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL
02463 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL
02464 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL
02465 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL
02466 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL
02467 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL
02468 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL
02469 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL
02470 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)
02471 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)
02472 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)
02473 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0)
02474 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
02475 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)
02476 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)
02477 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)
02478 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)
02479 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)
02480 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)
02481 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0)
02482 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)
02483 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)
02484 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)
02485 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)
02486 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)
02487 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)
02488 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)
02489 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)
02490 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
02491 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
02492 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
02493 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
02494 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)
02495 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)
02496 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)
02497 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
02498 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
02499 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)
02500 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)
02501 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
02502 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
02503 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)
02504 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)
02505 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)
02506 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)
02507 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)
02508 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)
02509 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)
02510 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)
02511 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16
02512 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
02513 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL
02514 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL
02515 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL
02516 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL
02517 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL
02518 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
02519 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL
02520 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL
02521 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL
02522 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL
02523 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL
02524 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL
02525 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL
02526 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16)
02527 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)
02528 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)
02529 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)
02530 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16)
02531 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)
02532 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)
02533 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)
02534 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)
02535 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)
02536 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16)
02537 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)
02538 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)
02539 #define _PRS_CH_CTRL_EDSEL_SHIFT 24
02540 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL
02541 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL
02542 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL
02543 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL
02544 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL
02545 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL
02546 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)
02547 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24)
02548 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)
02549 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)
02550 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)
02556
02560 #define MSC_UNLOCK_CODE 0x1B71
02561 #define EMU_UNLOCK_CODE 0xADE8
02562 #define CMU_UNLOCK_CODE 0x580E
02563 #define TIMER_UNLOCK_CODE 0xCE80
02564 #define GPIO_UNLOCK_CODE 0xA534
02570
02575 #include "efm32g_af_ports.h"
02576 #include "efm32g_af_pins.h"
02577
02580
02593 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02594 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02595
02600 #ifdef __cplusplus
02601 }
02602 #endif
02603 #endif