00001
00034 #ifndef __SILICON_LABS_EFM32G290F128_H__
00035 #define __SILICON_LABS_EFM32G290F128_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 MemoryManagement_IRQn = -12,
00058 BusFault_IRQn = -11,
00059 UsageFault_IRQn = -10,
00060 SVCall_IRQn = -5,
00061 DebugMonitor_IRQn = -4,
00062 PendSV_IRQn = -2,
00063 SysTick_IRQn = -1,
00065
00066 DMA_IRQn = 0,
00067 GPIO_EVEN_IRQn = 1,
00068 TIMER0_IRQn = 2,
00069 USART0_RX_IRQn = 3,
00070 USART0_TX_IRQn = 4,
00071 ACMP0_IRQn = 5,
00072 ADC0_IRQn = 6,
00073 DAC0_IRQn = 7,
00074 I2C0_IRQn = 8,
00075 GPIO_ODD_IRQn = 9,
00076 TIMER1_IRQn = 10,
00077 TIMER2_IRQn = 11,
00078 USART1_RX_IRQn = 12,
00079 USART1_TX_IRQn = 13,
00080 USART2_RX_IRQn = 14,
00081 USART2_TX_IRQn = 15,
00082 UART0_RX_IRQn = 16,
00083 UART0_TX_IRQn = 17,
00084 LEUART0_IRQn = 18,
00085 LEUART1_IRQn = 19,
00086 LETIMER0_IRQn = 20,
00087 PCNT0_IRQn = 21,
00088 PCNT1_IRQn = 22,
00089 PCNT2_IRQn = 23,
00090 RTC_IRQn = 24,
00091 CMU_IRQn = 25,
00092 VCMP_IRQn = 26,
00093 MSC_IRQn = 28,
00094 AES_IRQn = 29,
00095 } IRQn_Type;
00096
00097
00102 #define __MPU_PRESENT 1
00103 #define __NVIC_PRIO_BITS 3
00104 #define __Vendor_SysTickConfig 0
00108
00114 #define _EFM32_GECKO_FAMILY 1
00115 #define _EFM_DEVICE
00116 #define _SILICON_LABS_32B_PLATFORM_1
00117 #define _SILICON_LABS_32B_PLATFORM 1
00119
00120 #if !defined(EFM32G290F128)
00121 #define EFM32G290F128 1
00122 #endif
00123
00125 #define PART_NUMBER "EFM32G290F128"
00128 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00129 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00130 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00131 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00132 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00133 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00134 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00135 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00136 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00137 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00138 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00139 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00140 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00141 #define RAM_MEM_SIZE ((uint32_t) 0x8000UL)
00142 #define RAM_MEM_END ((uint32_t) 0x20007FFFUL)
00143 #define RAM_MEM_BITS ((uint32_t) 0x15UL)
00144 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00145 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
00146 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
00147 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
00148 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
00149 #define EBI_MEM_SIZE ((uint32_t) 0x10000000UL)
00150 #define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL)
00151 #define EBI_MEM_BITS ((uint32_t) 0x28UL)
00154 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
00155 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
00158 #define FLASH_BASE (0x00000000UL)
00159 #define FLASH_SIZE (0x00020000UL)
00160 #define FLASH_PAGE_SIZE 512
00161 #define SRAM_BASE (0x20000000UL)
00162 #define SRAM_SIZE (0x00004000UL)
00163 #define __CM3_REV 0x200
00164 #define PRS_CHAN_COUNT 8
00165 #define DMA_CHAN_COUNT 8
00168 #define AFCHAN_MAX 79
00169 #define AFCHANLOC_MAX 4
00170
00171 #define AFACHAN_MAX 37
00172
00173
00174
00175 #define TIMER_PRESENT
00176 #define TIMER_COUNT 3
00177 #define USART_PRESENT
00178 #define USART_COUNT 3
00179 #define UART_PRESENT
00180 #define UART_COUNT 1
00181 #define LEUART_PRESENT
00182 #define LEUART_COUNT 2
00183 #define LETIMER_PRESENT
00184 #define LETIMER_COUNT 1
00185 #define PCNT_PRESENT
00186 #define PCNT_COUNT 3
00187 #define ACMP_PRESENT
00188 #define ACMP_COUNT 2
00189 #define DAC_PRESENT
00190 #define DAC_COUNT 1
00191 #define ADC_PRESENT
00192 #define ADC_COUNT 1
00193 #define I2C_PRESENT
00194 #define I2C_COUNT 1
00195 #define AES_PRESENT
00196 #define AES_COUNT 1
00197 #define DMA_PRESENT
00198 #define DMA_COUNT 1
00199 #define LE_PRESENT
00200 #define LE_COUNT 1
00201 #define MSC_PRESENT
00202 #define MSC_COUNT 1
00203 #define EMU_PRESENT
00204 #define EMU_COUNT 1
00205 #define RMU_PRESENT
00206 #define RMU_COUNT 1
00207 #define CMU_PRESENT
00208 #define CMU_COUNT 1
00209 #define EBI_PRESENT
00210 #define EBI_COUNT 1
00211 #define RTC_PRESENT
00212 #define RTC_COUNT 1
00213 #define PRS_PRESENT
00214 #define PRS_COUNT 1
00215 #define GPIO_PRESENT
00216 #define GPIO_COUNT 1
00217 #define VCMP_PRESENT
00218 #define VCMP_COUNT 1
00219 #define HFXTAL_PRESENT
00220 #define HFXTAL_COUNT 1
00221 #define LFXTAL_PRESENT
00222 #define LFXTAL_COUNT 1
00223 #define WDOG_PRESENT
00224 #define WDOG_COUNT 1
00225 #define DBG_PRESENT
00226 #define DBG_COUNT 1
00227 #define BOOTLOADER_PRESENT
00228 #define BOOTLOADER_COUNT 1
00229 #define ANALOG_PRESENT
00230 #define ANALOG_COUNT 1
00231
00232 #include "core_cm3.h"
00233 #include "system_efm32g.h"
00234
00237
00243 #include "efm32g_aes.h"
00244 #include "efm32g_dma_ch.h"
00245 #include "efm32g_dma.h"
00246 #include "efm32g_msc.h"
00247 #include "efm32g_emu.h"
00248 #include "efm32g_rmu.h"
00249
00250
00255 typedef struct
00256 {
00257 __IO uint32_t CTRL;
00258 __IO uint32_t HFCORECLKDIV;
00259 __IO uint32_t HFPERCLKDIV;
00260 __IO uint32_t HFRCOCTRL;
00261 __IO uint32_t LFRCOCTRL;
00262 __IO uint32_t AUXHFRCOCTRL;
00263 __IO uint32_t CALCTRL;
00264 __IO uint32_t CALCNT;
00265 __IO uint32_t OSCENCMD;
00266 __IO uint32_t CMD;
00267 __IO uint32_t LFCLKSEL;
00268 __I uint32_t STATUS;
00269 __I uint32_t IF;
00270 __IO uint32_t IFS;
00271 __IO uint32_t IFC;
00272 __IO uint32_t IEN;
00273 __IO uint32_t HFCORECLKEN0;
00274 __IO uint32_t HFPERCLKEN0;
00275 uint32_t RESERVED0[2];
00276 __I uint32_t SYNCBUSY;
00277 __IO uint32_t FREEZE;
00278 __IO uint32_t LFACLKEN0;
00279 uint32_t RESERVED1[1];
00280 __IO uint32_t LFBCLKEN0;
00281 uint32_t RESERVED2[1];
00282 __IO uint32_t LFAPRESC0;
00283 uint32_t RESERVED3[1];
00284 __IO uint32_t LFBPRESC0;
00285 uint32_t RESERVED4[1];
00286 __IO uint32_t PCNTCTRL;
00287 uint32_t RESERVED5[1];
00288 __IO uint32_t ROUTE;
00289 __IO uint32_t LOCK;
00290 } CMU_TypeDef;
00292 #include "efm32g_ebi.h"
00293 #include "efm32g_timer_cc.h"
00294 #include "efm32g_timer.h"
00295 #include "efm32g_usart.h"
00296 #include "efm32g_leuart.h"
00297 #include "efm32g_rtc.h"
00298 #include "efm32g_letimer.h"
00299 #include "efm32g_pcnt.h"
00300 #include "efm32g_acmp.h"
00301 #include "efm32g_prs_ch.h"
00302 #include "efm32g_prs.h"
00303 #include "efm32g_dac.h"
00304 #include "efm32g_gpio_p.h"
00305 #include "efm32g_gpio.h"
00306 #include "efm32g_vcmp.h"
00307 #include "efm32g_adc.h"
00308 #include "efm32g_i2c.h"
00309 #include "efm32g_wdog.h"
00310 #include "efm32g_dma_descriptor.h"
00311 #include "efm32g_devinfo.h"
00312 #include "efm32g_romtable.h"
00313 #include "efm32g_calibrate.h"
00314
00317
00322 #define AES_BASE (0x400E0000UL)
00323 #define DMA_BASE (0x400C2000UL)
00324 #define MSC_BASE (0x400C0000UL)
00325 #define EMU_BASE (0x400C6000UL)
00326 #define RMU_BASE (0x400CA000UL)
00327 #define CMU_BASE (0x400C8000UL)
00328 #define EBI_BASE (0x40008000UL)
00329 #define TIMER0_BASE (0x40010000UL)
00330 #define TIMER1_BASE (0x40010400UL)
00331 #define TIMER2_BASE (0x40010800UL)
00332 #define USART0_BASE (0x4000C000UL)
00333 #define USART1_BASE (0x4000C400UL)
00334 #define USART2_BASE (0x4000C800UL)
00335 #define UART0_BASE (0x4000E000UL)
00336 #define LEUART0_BASE (0x40084000UL)
00337 #define LEUART1_BASE (0x40084400UL)
00338 #define RTC_BASE (0x40080000UL)
00339 #define LETIMER0_BASE (0x40082000UL)
00340 #define PCNT0_BASE (0x40086000UL)
00341 #define PCNT1_BASE (0x40086400UL)
00342 #define PCNT2_BASE (0x40086800UL)
00343 #define ACMP0_BASE (0x40001000UL)
00344 #define ACMP1_BASE (0x40001400UL)
00345 #define PRS_BASE (0x400CC000UL)
00346 #define DAC0_BASE (0x40004000UL)
00347 #define GPIO_BASE (0x40006000UL)
00348 #define VCMP_BASE (0x40000000UL)
00349 #define ADC0_BASE (0x40002000UL)
00350 #define I2C0_BASE (0x4000A000UL)
00351 #define WDOG_BASE (0x40088000UL)
00352 #define CALIBRATE_BASE (0x0FE08000UL)
00353 #define DEVINFO_BASE (0x0FE081B0UL)
00354 #define ROMTABLE_BASE (0xE00FFFD0UL)
00355 #define LOCKBITS_BASE (0x0FE04000UL)
00356 #define USERDATA_BASE (0x0FE00000UL)
00360
00365 #define AES ((AES_TypeDef *) AES_BASE)
00366 #define DMA ((DMA_TypeDef *) DMA_BASE)
00367 #define MSC ((MSC_TypeDef *) MSC_BASE)
00368 #define EMU ((EMU_TypeDef *) EMU_BASE)
00369 #define RMU ((RMU_TypeDef *) RMU_BASE)
00370 #define CMU ((CMU_TypeDef *) CMU_BASE)
00371 #define EBI ((EBI_TypeDef *) EBI_BASE)
00372 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00373 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00374 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
00375 #define USART0 ((USART_TypeDef *) USART0_BASE)
00376 #define USART1 ((USART_TypeDef *) USART1_BASE)
00377 #define USART2 ((USART_TypeDef *) USART2_BASE)
00378 #define UART0 ((USART_TypeDef *) UART0_BASE)
00379 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00380 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
00381 #define RTC ((RTC_TypeDef *) RTC_BASE)
00382 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
00383 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00384 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
00385 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
00386 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00387 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
00388 #define PRS ((PRS_TypeDef *) PRS_BASE)
00389 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
00390 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00391 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00392 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00393 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00394 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00395 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00396 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00397 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00401
00406 #include "efm32g_prs_signals.h"
00407 #include "efm32g_dmareq.h"
00408 #include "efm32g_dmactrl.h"
00409 #include "efm32g_uart.h"
00410
00411
00416
00417 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
00418 #define _CMU_CTRL_MASK 0x00FE3EEFUL
00419 #define _CMU_CTRL_HFXOMODE_SHIFT 0
00420 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
00421 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
00422 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
00423 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
00424 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
00425 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
00426 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
00427 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
00428 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
00429 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
00430 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
00431 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
00432 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
00433 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
00434 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
00435 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
00436 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
00437 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
00438 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
00439 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
00440 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
00441 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
00442 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
00443 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
00444 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
00445 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
00446 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
00447 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
00448 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
00449 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
00450 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
00451 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
00452 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
00453 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
00454 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
00455 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
00456 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
00457 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
00458 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
00459 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
00460 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
00461 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
00462 #define _CMU_CTRL_LFXOMODE_SHIFT 11
00463 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
00464 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
00465 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
00466 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
00467 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
00468 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
00469 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
00470 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
00471 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
00472 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
00473 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
00474 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
00475 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
00476 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
00477 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
00478 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
00479 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
00480 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
00481 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
00482 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
00483 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
00484 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
00485 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
00486 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
00487 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
00488 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
00489 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
00490 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
00491 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
00492 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
00493 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
00494 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
00495 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
00496 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
00497 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
00498 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
00499 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
00500 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
00501 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
00502 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
00503 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
00504 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
00505 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
00506 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
00507 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
00508 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
00509 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
00510 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
00511 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
00512 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
00513 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
00514 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
00515 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
00516 #define CMU_CTRL_CLKOUTSEL1 (0x1UL << 23)
00517 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
00518 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x800000UL
00519 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
00520 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
00521 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
00522 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
00523 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
00524 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
00526
00527 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
00528 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
00529 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
00530 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
00531 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
00532 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
00533 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
00534 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
00535 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
00536 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
00537 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
00538 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
00539 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
00540 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
00541 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
00542 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
00543 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
00544 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
00545 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
00546 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
00547 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
00548 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
00549 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
00550 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
00551 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
00552 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
00554
00555 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
00556 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
00557 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
00558 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
00559 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
00560 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
00561 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
00562 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
00563 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
00564 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
00565 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
00566 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
00567 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
00568 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
00569 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
00570 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
00571 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
00572 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
00573 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
00574 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
00575 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
00576 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
00577 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
00578 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
00579 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
00580 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
00581 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
00582 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
00583 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
00584 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
00585 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
00587
00588 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
00589 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
00590 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
00591 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
00592 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00593 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
00594 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
00595 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
00596 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
00597 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
00598 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
00599 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
00600 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
00601 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
00602 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
00603 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
00604 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
00605 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
00606 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
00607 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
00608 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
00609 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
00610 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
00611 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
00612 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
00613 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
00615
00616 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
00617 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
00618 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
00619 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
00620 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
00621 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
00623
00624 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
00625 #define _CMU_AUXHFRCOCTRL_MASK 0x000000FFUL
00626 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
00627 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
00628 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00629 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
00631
00632 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
00633 #define _CMU_CALCTRL_MASK 0x00000007UL
00634 #define _CMU_CALCTRL_UPSEL_SHIFT 0
00635 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
00636 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
00637 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
00638 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
00639 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
00640 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
00641 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
00642 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
00643 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
00644 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
00645 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
00646 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
00647 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
00649
00650 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
00651 #define _CMU_CALCNT_MASK 0x000FFFFFUL
00652 #define _CMU_CALCNT_CALCNT_SHIFT 0
00653 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
00654 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
00655 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
00657
00658 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
00659 #define _CMU_OSCENCMD_MASK 0x000003FFUL
00660 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
00661 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
00662 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
00663 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
00664 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
00665 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
00666 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
00667 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
00668 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
00669 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
00670 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
00671 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
00672 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
00673 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
00674 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
00675 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
00676 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
00677 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
00678 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
00679 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
00680 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
00681 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
00682 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
00683 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
00684 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
00685 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
00686 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
00687 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
00688 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
00689 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
00690 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
00691 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
00692 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
00693 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
00694 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
00695 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
00696 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
00697 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
00698 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
00699 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
00700 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
00701 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
00702 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
00703 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
00704 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
00705 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
00706 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
00707 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
00708 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
00709 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
00711
00712 #define _CMU_CMD_RESETVALUE 0x00000000UL
00713 #define _CMU_CMD_MASK 0x0000000FUL
00714 #define _CMU_CMD_HFCLKSEL_SHIFT 0
00715 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
00716 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
00717 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
00718 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
00719 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
00720 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
00721 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
00722 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
00723 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
00724 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
00725 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
00726 #define CMU_CMD_CALSTART (0x1UL << 3)
00727 #define _CMU_CMD_CALSTART_SHIFT 3
00728 #define _CMU_CMD_CALSTART_MASK 0x8UL
00729 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
00730 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
00732
00733 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
00734 #define _CMU_LFCLKSEL_MASK 0x0000000FUL
00735 #define _CMU_LFCLKSEL_LFA_SHIFT 0
00736 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
00737 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
00738 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
00739 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
00740 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
00741 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
00742 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
00743 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
00744 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
00745 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
00746 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
00747 #define _CMU_LFCLKSEL_LFB_SHIFT 2
00748 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
00749 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
00750 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
00751 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
00752 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
00753 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
00754 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
00755 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
00756 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
00757 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
00758 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
00760
00761 #define _CMU_STATUS_RESETVALUE 0x00000403UL
00762 #define _CMU_STATUS_MASK 0x00007FFFUL
00763 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
00764 #define _CMU_STATUS_HFRCOENS_SHIFT 0
00765 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
00766 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
00767 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
00768 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
00769 #define _CMU_STATUS_HFRCORDY_SHIFT 1
00770 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
00771 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
00772 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
00773 #define CMU_STATUS_HFXOENS (0x1UL << 2)
00774 #define _CMU_STATUS_HFXOENS_SHIFT 2
00775 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
00776 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
00777 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
00778 #define CMU_STATUS_HFXORDY (0x1UL << 3)
00779 #define _CMU_STATUS_HFXORDY_SHIFT 3
00780 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
00781 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
00782 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
00783 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
00784 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
00785 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
00786 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
00787 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
00788 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
00789 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
00790 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
00791 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
00792 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
00793 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
00794 #define _CMU_STATUS_LFRCOENS_SHIFT 6
00795 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
00796 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
00797 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
00798 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
00799 #define _CMU_STATUS_LFRCORDY_SHIFT 7
00800 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
00801 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
00802 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
00803 #define CMU_STATUS_LFXOENS (0x1UL << 8)
00804 #define _CMU_STATUS_LFXOENS_SHIFT 8
00805 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
00806 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
00807 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
00808 #define CMU_STATUS_LFXORDY (0x1UL << 9)
00809 #define _CMU_STATUS_LFXORDY_SHIFT 9
00810 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
00811 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
00812 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
00813 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
00814 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
00815 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
00816 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
00817 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
00818 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
00819 #define _CMU_STATUS_HFXOSEL_SHIFT 11
00820 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
00821 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
00822 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
00823 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
00824 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
00825 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
00826 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
00827 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
00828 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
00829 #define _CMU_STATUS_LFXOSEL_SHIFT 13
00830 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
00831 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
00832 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
00833 #define CMU_STATUS_CALBSY (0x1UL << 14)
00834 #define _CMU_STATUS_CALBSY_SHIFT 14
00835 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
00836 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
00837 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
00839
00840 #define _CMU_IF_RESETVALUE 0x00000001UL
00841 #define _CMU_IF_MASK 0x0000003FUL
00842 #define CMU_IF_HFRCORDY (0x1UL << 0)
00843 #define _CMU_IF_HFRCORDY_SHIFT 0
00844 #define _CMU_IF_HFRCORDY_MASK 0x1UL
00845 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
00846 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
00847 #define CMU_IF_HFXORDY (0x1UL << 1)
00848 #define _CMU_IF_HFXORDY_SHIFT 1
00849 #define _CMU_IF_HFXORDY_MASK 0x2UL
00850 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
00851 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
00852 #define CMU_IF_LFRCORDY (0x1UL << 2)
00853 #define _CMU_IF_LFRCORDY_SHIFT 2
00854 #define _CMU_IF_LFRCORDY_MASK 0x4UL
00855 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
00856 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
00857 #define CMU_IF_LFXORDY (0x1UL << 3)
00858 #define _CMU_IF_LFXORDY_SHIFT 3
00859 #define _CMU_IF_LFXORDY_MASK 0x8UL
00860 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
00861 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
00862 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
00863 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
00864 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
00865 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
00866 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
00867 #define CMU_IF_CALRDY (0x1UL << 5)
00868 #define _CMU_IF_CALRDY_SHIFT 5
00869 #define _CMU_IF_CALRDY_MASK 0x20UL
00870 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
00871 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
00873
00874 #define _CMU_IFS_RESETVALUE 0x00000000UL
00875 #define _CMU_IFS_MASK 0x0000003FUL
00876 #define CMU_IFS_HFRCORDY (0x1UL << 0)
00877 #define _CMU_IFS_HFRCORDY_SHIFT 0
00878 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
00879 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
00880 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
00881 #define CMU_IFS_HFXORDY (0x1UL << 1)
00882 #define _CMU_IFS_HFXORDY_SHIFT 1
00883 #define _CMU_IFS_HFXORDY_MASK 0x2UL
00884 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
00885 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
00886 #define CMU_IFS_LFRCORDY (0x1UL << 2)
00887 #define _CMU_IFS_LFRCORDY_SHIFT 2
00888 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
00889 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
00890 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
00891 #define CMU_IFS_LFXORDY (0x1UL << 3)
00892 #define _CMU_IFS_LFXORDY_SHIFT 3
00893 #define _CMU_IFS_LFXORDY_MASK 0x8UL
00894 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
00895 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
00896 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
00897 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
00898 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
00899 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
00900 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
00901 #define CMU_IFS_CALRDY (0x1UL << 5)
00902 #define _CMU_IFS_CALRDY_SHIFT 5
00903 #define _CMU_IFS_CALRDY_MASK 0x20UL
00904 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
00905 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
00907
00908 #define _CMU_IFC_RESETVALUE 0x00000000UL
00909 #define _CMU_IFC_MASK 0x0000003FUL
00910 #define CMU_IFC_HFRCORDY (0x1UL << 0)
00911 #define _CMU_IFC_HFRCORDY_SHIFT 0
00912 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
00913 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
00914 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
00915 #define CMU_IFC_HFXORDY (0x1UL << 1)
00916 #define _CMU_IFC_HFXORDY_SHIFT 1
00917 #define _CMU_IFC_HFXORDY_MASK 0x2UL
00918 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
00919 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
00920 #define CMU_IFC_LFRCORDY (0x1UL << 2)
00921 #define _CMU_IFC_LFRCORDY_SHIFT 2
00922 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
00923 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
00924 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
00925 #define CMU_IFC_LFXORDY (0x1UL << 3)
00926 #define _CMU_IFC_LFXORDY_SHIFT 3
00927 #define _CMU_IFC_LFXORDY_MASK 0x8UL
00928 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
00929 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
00930 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
00931 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
00932 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
00933 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
00934 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
00935 #define CMU_IFC_CALRDY (0x1UL << 5)
00936 #define _CMU_IFC_CALRDY_SHIFT 5
00937 #define _CMU_IFC_CALRDY_MASK 0x20UL
00938 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
00939 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
00941
00942 #define _CMU_IEN_RESETVALUE 0x00000000UL
00943 #define _CMU_IEN_MASK 0x0000003FUL
00944 #define CMU_IEN_HFRCORDY (0x1UL << 0)
00945 #define _CMU_IEN_HFRCORDY_SHIFT 0
00946 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
00947 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
00948 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
00949 #define CMU_IEN_HFXORDY (0x1UL << 1)
00950 #define _CMU_IEN_HFXORDY_SHIFT 1
00951 #define _CMU_IEN_HFXORDY_MASK 0x2UL
00952 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
00953 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
00954 #define CMU_IEN_LFRCORDY (0x1UL << 2)
00955 #define _CMU_IEN_LFRCORDY_SHIFT 2
00956 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
00957 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
00958 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
00959 #define CMU_IEN_LFXORDY (0x1UL << 3)
00960 #define _CMU_IEN_LFXORDY_SHIFT 3
00961 #define _CMU_IEN_LFXORDY_MASK 0x8UL
00962 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
00963 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
00964 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
00965 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
00966 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
00967 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
00968 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
00969 #define CMU_IEN_CALRDY (0x1UL << 5)
00970 #define _CMU_IEN_CALRDY_SHIFT 5
00971 #define _CMU_IEN_CALRDY_MASK 0x20UL
00972 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
00973 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
00975
00976 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
00977 #define _CMU_HFCORECLKEN0_MASK 0x0000000FUL
00978 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
00979 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
00980 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
00981 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
00982 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
00983 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
00984 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
00985 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
00986 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
00987 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
00988 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
00989 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
00990 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
00991 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
00992 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
00993 #define CMU_HFCORECLKEN0_EBI (0x1UL << 3)
00994 #define _CMU_HFCORECLKEN0_EBI_SHIFT 3
00995 #define _CMU_HFCORECLKEN0_EBI_MASK 0x8UL
00996 #define _CMU_HFCORECLKEN0_EBI_DEFAULT 0x00000000UL
00997 #define CMU_HFCORECLKEN0_EBI_DEFAULT (_CMU_HFCORECLKEN0_EBI_DEFAULT << 3)
00999
01000 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
01001 #define _CMU_HFPERCLKEN0_MASK 0x0000FDFFUL
01002 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0)
01003 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0
01004 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL
01005 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
01006 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0)
01007 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1)
01008 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1
01009 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL
01010 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
01011 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1)
01012 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2)
01013 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2
01014 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL
01015 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL
01016 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2)
01017 #define CMU_HFPERCLKEN0_UART0 (0x1UL << 3)
01018 #define _CMU_HFPERCLKEN0_UART0_SHIFT 3
01019 #define _CMU_HFPERCLKEN0_UART0_MASK 0x8UL
01020 #define _CMU_HFPERCLKEN0_UART0_DEFAULT 0x00000000UL
01021 #define CMU_HFPERCLKEN0_UART0_DEFAULT (_CMU_HFPERCLKEN0_UART0_DEFAULT << 3)
01022 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
01023 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
01024 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
01025 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
01026 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
01027 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
01028 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
01029 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
01030 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
01031 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
01032 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 6)
01033 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 6
01034 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x40UL
01035 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
01036 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 6)
01037 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 7)
01038 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 7
01039 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x80UL
01040 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
01041 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 7)
01042 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 8)
01043 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 8
01044 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x100UL
01045 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
01046 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 8)
01047 #define CMU_HFPERCLKEN0_PRS (0x1UL << 10)
01048 #define _CMU_HFPERCLKEN0_PRS_SHIFT 10
01049 #define _CMU_HFPERCLKEN0_PRS_MASK 0x400UL
01050 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
01051 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 10)
01052 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 11)
01053 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 11
01054 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x800UL
01055 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
01056 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 11)
01057 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 12)
01058 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 12
01059 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x1000UL
01060 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
01061 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 12)
01062 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 13)
01063 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 13
01064 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x2000UL
01065 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
01066 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 13)
01067 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 14)
01068 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 14
01069 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x4000UL
01070 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
01071 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 14)
01072 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 15)
01073 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 15
01074 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x8000UL
01075 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
01076 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 15)
01078
01079 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
01080 #define _CMU_SYNCBUSY_MASK 0x00000055UL
01081 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
01082 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
01083 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
01084 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
01085 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
01086 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
01087 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
01088 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
01089 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
01090 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
01091 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
01092 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
01093 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
01094 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
01095 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
01096 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
01097 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
01098 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
01099 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
01100 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
01102
01103 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
01104 #define _CMU_FREEZE_MASK 0x00000001UL
01105 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
01106 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
01107 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
01108 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
01109 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
01110 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
01111 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
01112 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
01113 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
01115
01116 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
01117 #define _CMU_LFACLKEN0_MASK 0x00000003UL
01118 #define CMU_LFACLKEN0_RTC (0x1UL << 0)
01119 #define _CMU_LFACLKEN0_RTC_SHIFT 0
01120 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL
01121 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
01122 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
01123 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 1)
01124 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 1
01125 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x2UL
01126 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
01127 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 1)
01129
01130 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
01131 #define _CMU_LFBCLKEN0_MASK 0x00000003UL
01132 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
01133 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
01134 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
01135 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
01136 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
01137 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1)
01138 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1
01139 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL
01140 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL
01141 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1)
01143
01144 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
01145 #define _CMU_LFAPRESC0_MASK 0x000000FFUL
01146 #define _CMU_LFAPRESC0_RTC_SHIFT 0
01147 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL
01148 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
01149 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
01150 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
01151 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
01152 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
01153 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
01154 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
01155 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
01156 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
01157 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
01158 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
01159 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
01160 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
01161 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
01162 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
01163 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
01164 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
01165 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
01166 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
01167 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
01168 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
01169 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
01170 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
01171 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
01172 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
01173 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
01174 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
01175 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
01176 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
01177 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
01178 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
01179 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
01180 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 4
01181 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF0UL
01182 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
01183 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
01184 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
01185 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
01186 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
01187 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
01188 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
01189 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
01190 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
01191 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
01192 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
01193 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
01194 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
01195 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
01196 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
01197 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
01198 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 4)
01199 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 4)
01200 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 4)
01201 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 4)
01202 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 4)
01203 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 4)
01204 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 4)
01205 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 4)
01206 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 4)
01207 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 4)
01208 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 4)
01209 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 4)
01210 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 4)
01211 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 4)
01212 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 4)
01213 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 4)
01215
01216 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
01217 #define _CMU_LFBPRESC0_MASK 0x00000033UL
01218 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
01219 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
01220 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
01221 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
01222 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
01223 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
01224 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
01225 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
01226 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
01227 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
01228 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4
01229 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL
01230 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL
01231 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL
01232 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL
01233 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL
01234 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4)
01235 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4)
01236 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4)
01237 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4)
01239
01240 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
01241 #define _CMU_PCNTCTRL_MASK 0x0000003FUL
01242 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
01243 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
01244 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
01245 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
01246 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
01247 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
01248 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
01249 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
01250 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
01251 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
01252 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
01253 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
01254 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
01255 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
01256 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2)
01257 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2
01258 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL
01259 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL
01260 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2)
01261 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3)
01262 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3
01263 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL
01264 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL
01265 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL
01266 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL
01267 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3)
01268 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3)
01269 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3)
01270 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4)
01271 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4
01272 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL
01273 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL
01274 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4)
01275 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5)
01276 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5
01277 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL
01278 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL
01279 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL
01280 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL
01281 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5)
01282 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5)
01283 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5)
01285
01286 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
01287 #define _CMU_ROUTE_MASK 0x00000007UL
01288 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
01289 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
01290 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
01291 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
01292 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
01293 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
01294 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
01295 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
01296 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
01297 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
01298 #define CMU_ROUTE_LOCATION (0x1UL << 2)
01299 #define _CMU_ROUTE_LOCATION_SHIFT 2
01300 #define _CMU_ROUTE_LOCATION_MASK 0x4UL
01301 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
01302 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
01303 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
01304 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
01305 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
01306 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
01308
01309 #define _CMU_LOCK_RESETVALUE 0x00000000UL
01310 #define _CMU_LOCK_MASK 0x0000FFFFUL
01311 #define _CMU_LOCK_LOCKKEY_SHIFT 0
01312 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
01313 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
01314 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
01315 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
01316 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
01317 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
01318 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
01319 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
01320 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
01321 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
01322 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
01328
01332 #define MSC_UNLOCK_CODE 0x1B71
01333 #define EMU_UNLOCK_CODE 0xADE8
01334 #define CMU_UNLOCK_CODE 0x580E
01335 #define TIMER_UNLOCK_CODE 0xCE80
01336 #define GPIO_UNLOCK_CODE 0xA534
01342
01347 #include "efm32g_af_ports.h"
01348 #include "efm32g_af_pins.h"
01349
01352
01365 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
01366 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
01367
01372 #ifdef __cplusplus
01373 }
01374 #endif
01375 #endif