EFM32 Gecko Software Documentation  efm32g-doc-4.2.1
dmadrv.h
Go to the documentation of this file.
1 /***************************************************************************/
16 #ifndef __SILICON_LABS_DMADRV_H__
17 #define __SILICON_LABS_DMADRV_H__
18 
19 #include "em_device.h"
20 #include "ecode.h"
21 
22 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
23 #define EMDRV_DMADRV_UDMA
24 #define EMDRV_DMADRV_DMA_PRESENT
25 #include "em_dma.h"
26 #elif defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
27 #define EMDRV_DMADRV_LDMA
28 #define EMDRV_DMADRV_DMA_PRESENT
29 #include "em_ldma.h"
30 #else
31 #error "No valid DMA engine defined."
32 #endif
33 
34 #include "dmadrv_config.h"
35 
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39 
40 /***************************************************************************/
45 /***************************************************************************/
51 #define ECODE_EMDRV_DMADRV_OK ( ECODE_OK )
52 #define ECODE_EMDRV_DMADRV_PARAM_ERROR ( ECODE_EMDRV_DMADRV_BASE | 0x00000001 )
53 #define ECODE_EMDRV_DMADRV_NOT_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000002 )
54 #define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000003 )
55 #define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED ( ECODE_EMDRV_DMADRV_BASE | 0x00000004 )
56 #define ECODE_EMDRV_DMADRV_IN_USE ( ECODE_EMDRV_DMADRV_BASE | 0x00000005 )
57 #define ECODE_EMDRV_DMADRV_ALREADY_FREED ( ECODE_EMDRV_DMADRV_BASE | 0x00000006 )
58 #define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED ( ECODE_EMDRV_DMADRV_BASE | 0x00000007 )
59 
60 /***************************************************************************/
81 typedef bool (*DMADRV_Callback_t)( unsigned int channel,
82  unsigned int sequenceNo,
83  void *userParam );
84 
85 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
86 
88 #define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1))
89 
91 typedef enum
92 {
94  #if defined( DMAREQ_ADC0_SCAN )
96  #endif
97  #if defined( DMAREQ_ADC0_SINGLE )
99  #endif
100  #if defined( DMAREQ_AES_DATARD )
102  #endif
103  #if defined( DMAREQ_AES_DATAWR )
105  #endif
106  #if defined( DMAREQ_AES_KEYWR )
108  #endif
109  #if defined( DMAREQ_AES_XORDATAWR )
111  #endif
112  #if defined( DMAREQ_DAC0_CH0 )
114  #endif
115  #if defined( DMAREQ_DAC0_CH1 )
117  #endif
118  #if defined( DMAREQ_EBI_DDEMPTY )
119  dmadrvPeripheralSignal_EBI_DDEMPTY = DMAREQ_EBI_DDEMPTY,
120  #endif
121  #if defined( DMAREQ_EBI_PXL0EMPTY )
122  dmadrvPeripheralSignal_EBI_PXL0EMPTY = DMAREQ_EBI_PXL0EMPTY,
123  #endif
124  #if defined( DMAREQ_EBI_PXL1EMPTY )
125  dmadrvPeripheralSignal_EBI_PXL1EMPTY = DMAREQ_EBI_PXL1EMPTY,
126  #endif
127  #if defined( DMAREQ_EBI_PXLFULL )
128  dmadrvPeripheralSignal_EBI_PXLFULL = DMAREQ_EBI_PXLFULL,
129  #endif
130  #if defined( DMAREQ_I2C0_RXDATAV )
132  #endif
133  #if defined( DMAREQ_I2C0_TXBL )
135  #endif
136  #if defined( DMAREQ_I2C1_RXDATAV )
137  dmadrvPeripheralSignal_I2C1_RXDATAV = DMAREQ_I2C1_RXDATAV,
138  #endif
139  #if defined( DMAREQ_I2C1_TXBL )
140  dmadrvPeripheralSignal_I2C1_TXBL = DMAREQ_I2C1_TXBL,
141  #endif
142  #if defined( DMAREQ_LESENSE_BUFDATAV )
143  dmadrvPeripheralSignal_LESENSE_BUFDATAV = DMAREQ_LESENSE_BUFDATAV,
144  #endif
145  #if defined( DMAREQ_LEUART0_RXDATAV )
147  #endif
148  #if defined( DMAREQ_LEUART0_TXBL )
150  #endif
151  #if defined( DMAREQ_LEUART0_TXEMPTY )
153  #endif
154  #if defined( DMAREQ_LEUART1_RXDATAV )
156  #endif
157  #if defined( DMAREQ_LEUART1_TXBL )
159  #endif
160  #if defined( DMAREQ_LEUART1_TXEMPTY )
162  #endif
163  #if defined( DMAREQ_MSC_WDATA )
165  #endif
166  #if defined( DMAREQ_TIMER0_CC0 )
168  #endif
169  #if defined( DMAREQ_TIMER0_CC1 )
171  #endif
172  #if defined( DMAREQ_TIMER0_CC2 )
174  #endif
175  #if defined( DMAREQ_TIMER0_UFOF )
177  #endif
178  #if defined( DMAREQ_TIMER1_CC0 )
180  #endif
181  #if defined( DMAREQ_TIMER1_CC1 )
183  #endif
184  #if defined( DMAREQ_TIMER1_CC2 )
186  #endif
187  #if defined( DMAREQ_TIMER1_UFOF )
189  #endif
190  #if defined( DMAREQ_TIMER2_CC0 )
192  #endif
193  #if defined( DMAREQ_TIMER2_CC1 )
195  #endif
196  #if defined( DMAREQ_TIMER2_CC2 )
198  #endif
199  #if defined( DMAREQ_TIMER2_UFOF )
201  #endif
202  #if defined( DMAREQ_TIMER3_CC0 )
203  dmadrvPeripheralSignal_TIMER3_CC0 = DMAREQ_TIMER3_CC0,
204  #endif
205  #if defined( DMAREQ_TIMER3_CC1 )
206  dmadrvPeripheralSignal_TIMER3_CC1 = DMAREQ_TIMER3_CC1,
207  #endif
208  #if defined( DMAREQ_TIMER3_CC2 )
209  dmadrvPeripheralSignal_TIMER3_CC2 = DMAREQ_TIMER3_CC2,
210  #endif
211  #if defined( DMAREQ_TIMER3_UFOF )
212  dmadrvPeripheralSignal_TIMER3_UFOF = DMAREQ_TIMER3_UFOF,
213  #endif
214  #if defined( DMAREQ_UART0_RXDATAV )
216  #endif
217  #if defined( DMAREQ_UART0_TXBL )
219  #endif
220  #if defined( DMAREQ_UART0_TXEMPTY )
222  #endif
223  #if defined( DMAREQ_UART1_RXDATAV )
224  dmadrvPeripheralSignal_UART1_RXDATAV = DMAREQ_UART1_RXDATAV,
225  #endif
226  #if defined( DMAREQ_UART1_TXBL )
227  dmadrvPeripheralSignal_UART1_TXBL = DMAREQ_UART1_TXBL,
228  #endif
229  #if defined( DMAREQ_UART1_TXEMPTY )
230  dmadrvPeripheralSignal_UART1_TXEMPTY = DMAREQ_UART1_TXEMPTY,
231  #endif
232  #if defined( DMAREQ_USART0_RXDATAV )
234  #endif
235  #if defined( DMAREQ_USART0_TXBL )
237  #endif
238  #if defined( DMAREQ_USART0_TXEMPTY )
240  #endif
241  #if defined( DMAREQ_USARTRF0_RXDATAV )
242  dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV,
243  #endif
244  #if defined( DMAREQ_USARTRF0_TXBL )
245  dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL,
246  #endif
247  #if defined( DMAREQ_USARTRF0_TXEMPTY )
248  dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY,
249  #endif
250  #if defined( DMAREQ_USARTRF1_RXDATAV )
251  dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV,
252  #endif
253  #if defined( DMAREQ_USARTRF1_TXBL )
254  dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL,
255  #endif
256  #if defined( DMAREQ_USARTRF1_TXEMPTY )
257  dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY,
258  #endif
259  #if defined( DMAREQ_USART1_RXDATAV )
261  #endif
262  #if defined( DMAREQ_USART1_RXDATAVRIGHT )
263  dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = DMAREQ_USART1_RXDATAVRIGHT,
264  #endif
265  #if defined( DMAREQ_USART1_TXBL )
267  #endif
268  #if defined( DMAREQ_USART1_TXBLRIGHT )
269  dmadrvPeripheralSignal_USART1_TXBLRIGHT = DMAREQ_USART1_TXBLRIGHT,
270  #endif
271  #if defined( DMAREQ_USART1_TXEMPTY )
273  #endif
274  #if defined( DMAREQ_USART2_RXDATAV )
276  #endif
277  #if defined( DMAREQ_USART2_RXDATAVRIGHT )
278  dmadrvPeripheralSignal_USART2_RXDATAVRIGHT = DMAREQ_USART2_RXDATAVRIGHT,
279  #endif
280  #if defined( DMAREQ_USART2_TXBL )
282  #endif
283  #if defined( DMAREQ_USART2_TXBLRIGHT )
284  dmadrvPeripheralSignal_USART2_TXBLRIGHT = DMAREQ_USART2_TXBLRIGHT,
285  #endif
286  #if defined( DMAREQ_USART2_TXEMPTY )
288  #endif
289 #ifdef DOXY_DOC_ONLY
291 #else
292 } DMADRV_PeripheralSignal_t;
293 #endif
294 
296 typedef enum
297 {
301 #ifdef DOXY_DOC_ONLY
303 #else
304 } DMADRV_DataSize_t;
305 #endif
306 
307 #endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
308 
309 #if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
310 
312 #define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
313 
315 typedef enum
316 {
317  dmadrvPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE,
318  #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )
319  dmadrvPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0,
320  #endif
321  #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )
322  dmadrvPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0,
323  #endif
324  #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )
325  dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC,
326  #endif
327  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
328  dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
329  #endif
330  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
331  dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
332  #endif
333  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
334  dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
335  #endif
336  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
337  dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
338  #endif
339  #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
340  dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
341  #endif
342  #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )
343  dmadrvPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0,
344  #endif
345  #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )
346  dmadrvPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0,
347  #endif
348  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )
349  dmadrvPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
350  #endif
351  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )
352  dmadrvPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
353  #endif
354  #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )
355  dmadrvPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
356  #endif
357  #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )
358  dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM,
359  #endif
360  #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )
361  dmadrvPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC,
362  #endif
363  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )
364  dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
365  #endif
366  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )
367  dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
368  #endif
369  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )
370  dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
371  #endif
372  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )
373  dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
374  #endif
375  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )
376  dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
377  #endif
378  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )
379  dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
380  #endif
381  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )
382  dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
383  #endif
384  #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )
385  dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
386  #endif
387  #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )
388  dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS,
389  #endif
390  #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )
391  dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS,
392  #endif
393  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )
394  dmadrvPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
395  #endif
396  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )
397  dmadrvPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
398  #endif
399  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )
400  dmadrvPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
401  #endif
402  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )
403  dmadrvPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
404  #endif
405  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )
406  dmadrvPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
407  #endif
408  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )
409  dmadrvPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
410  #endif
411  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )
412  dmadrvPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
413  #endif
414  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )
415  dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
416  #endif
417  #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )
418  dmadrvPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
419  #endif
420  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )
421  dmadrvPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0,
422  #endif
423  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )
424  dmadrvPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0,
425  #endif
426  #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )
427  dmadrvPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0,
428  #endif
429  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )
430  dmadrvPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1,
431  #endif
432  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )
433  dmadrvPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
434  #endif
435  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )
436  dmadrvPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1,
437  #endif
438  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )
439  dmadrvPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
440  #endif
441  #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )
442  dmadrvPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1
443  #endif
444 } DMADRV_PeripheralSignal_t;
445 
447 typedef enum
448 {
449  dmadrvDataSize1 = ldmaCtrlSizeByte,
450  dmadrvDataSize2 = ldmaCtrlSizeHalf,
451  dmadrvDataSize4 = ldmaCtrlSizeWord
452 } DMADRV_DataSize_t;
453 
454 #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
455 
456 Ecode_t DMADRV_AllocateChannel( unsigned int *channelId, void *capabilities );
457 Ecode_t DMADRV_DeInit( void );
458 Ecode_t DMADRV_FreeChannel( unsigned int channelId );
459 Ecode_t DMADRV_Init( void );
460 
461 #if !defined( EMDRV_DMADRV_USE_NATIVE_API ) || defined( DOXY_DOC_ONLY )
462 Ecode_t DMADRV_MemoryPeripheral( unsigned int channelId,
463  DMADRV_PeripheralSignal_t
464  peripheralSignal,
465  void *dst,
466  void *src,
467  bool srcInc,
468  int len,
469  DMADRV_DataSize_t size,
470  DMADRV_Callback_t callback,
471  void *cbUserParam );
472 Ecode_t DMADRV_PeripheralMemory( unsigned int channelId,
473  DMADRV_PeripheralSignal_t
474  peripheralSignal,
475  void *dst,
476  void *src,
477  bool dstInc,
478  int len,
479  DMADRV_DataSize_t size,
480  DMADRV_Callback_t callback,
481  void *cbUserParam );
483  unsigned int channelId,
484  DMADRV_PeripheralSignal_t
485  peripheralSignal,
486  void *dst,
487  void *src0,
488  void *src1,
489  bool srcInc,
490  int len,
491  DMADRV_DataSize_t size,
492  DMADRV_Callback_t callback,
493  void *cbUserParam );
495  unsigned int channelId,
496  DMADRV_PeripheralSignal_t
497  peripheralSignal,
498  void *dst0,
499  void *dst1,
500  void *src,
501  bool dstInc,
502  int len,
503  DMADRV_DataSize_t size,
504  DMADRV_Callback_t callback,
505  void *cbUserParam );
506 #endif
507 
508 #if defined( EMDRV_DMADRV_LDMA ) && defined( EMDRV_DMADRV_USE_NATIVE_API )
509 
510 Ecode_t DMADRV_LdmaStartTransfer(
511  int channelId,
512  LDMA_TransferCfg_t *transfer,
513  LDMA_Descriptor_t *descriptor,
514  DMADRV_Callback_t callback,
515  void *cbUserParam );
516 
517 #endif /* !defined( EMDRV_DMADRV_USE_NATIVE_API ) */
518 
519 Ecode_t DMADRV_StopTransfer( unsigned int channelId );
520 Ecode_t DMADRV_TransferActive( unsigned int channelId, bool *active );
521 Ecode_t DMADRV_TransferCompletePending( unsigned int channelId, bool *pending );
522 Ecode_t DMADRV_TransferDone( unsigned int channelId, bool *done );
523 Ecode_t DMADRV_TransferRemainingCount( unsigned int channelId,
524  int *remaining );
525 
529 #ifdef __cplusplus
530 }
531 #endif
532 
533 #endif /* __SILICON_LABS_DMADRV_H__ */
Trig on TIMER1_UFOF.
Definition: dmadrv.h:188
#define DMAREQ_TIMER1_CC2
Definition: efm32g_dmareq.h:69
Trig on TIMER0_CC0.
Definition: dmadrv.h:167
Trig on USART2_TXEMPTY.
Definition: dmadrv.h:287
Trig on USART0_RXDATAV.
Definition: dmadrv.h:233
Trig on USART0_TXBL.
Definition: dmadrv.h:236
#define DMAREQ_AES_DATARD
Definition: efm32g_dmareq.h:80
#define DMAREQ_USART1_TXBL
Definition: efm32g_dmareq.h:49
#define DMAREQ_USART0_TXBL
Definition: efm32g_dmareq.h:46
Trig on AES_XORDATAWR.
Definition: dmadrv.h:110
#define DMAREQ_AES_KEYWR
Definition: efm32g_dmareq.h:81
Trig on USART1_RXDATAV.
Definition: dmadrv.h:260
#define DMAREQ_TIMER0_CC1
Definition: efm32g_dmareq.h:64
Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory DMA transfer.
Definition: dmadrv.c:535
Trig on USART1_TXEMPTY.
Definition: dmadrv.h:272
#define DMAREQ_AES_DATAWR
Definition: efm32g_dmareq.h:78
#define DMAREQ_UART0_RXDATAV
Definition: efm32g_dmareq.h:74
Trig on AES_KEYWR.
Definition: dmadrv.h:107
Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active)
Check if a transfer is running.
Definition: dmadrv.c:681
Energy Aware drivers error code definitions.
bool(* DMADRV_Callback_t)(unsigned int channel, unsigned int sequenceNo, void *userParam)
DMADRV transfer completion callback function.
Definition: dmadrv.h:81
Trig on LEUART1_RXDATAV.
Definition: dmadrv.h:155
#define DMAREQ_USART2_RXDATAV
Definition: efm32g_dmareq.h:51
Trig on LEUART0_TXEMPTY.
Definition: dmadrv.h:152
#define DMAREQ_MSC_WDATA
Definition: efm32g_dmareq.h:77
Trig on ADC0_SCAN.
Definition: dmadrv.h:95
No peripheral selected for DMA triggering.
Definition: dmadrv.h:93
#define DMAREQ_LEUART0_TXBL
Definition: efm32g_dmareq.h:55
#define DMAREQ_TIMER2_CC1
Definition: efm32g_dmareq.h:72
#define DMAREQ_TIMER0_CC0
Definition: efm32g_dmareq.h:63
Ecode_t DMADRV_StopTransfer(unsigned int channelId)
Stop an ongoing DMA transfer.
Definition: dmadrv.c:641
Trig on TIMER2_UFOF.
Definition: dmadrv.h:200
Trig on LEUART0_RXDATAV.
Definition: dmadrv.h:146
Halfword.
Definition: dmadrv.h:299
#define DMAREQ_TIMER0_CC2
Definition: efm32g_dmareq.h:65
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define DMAREQ_TIMER1_UFOF
Definition: efm32g_dmareq.h:66
#define DMAREQ_TIMER2_UFOF
Definition: efm32g_dmareq.h:70
Trig on TIMER1_CC2.
Definition: dmadrv.h:185
#define DMAREQ_LEUART1_RXDATAV
Definition: efm32g_dmareq.h:57
Trig on UART0_RXDATAV.
Definition: dmadrv.h:215
#define DMAREQ_TIMER0_UFOF
Definition: efm32g_dmareq.h:62
Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done)
Check if a transfer has completed.
Definition: dmadrv.c:786
Trig on DAC0_CH1.
Definition: dmadrv.h:116
#define DMAREQ_ADC0_SCAN
Definition: efm32g_dmareq.h:42
Byte.
Definition: dmadrv.h:298
#define DMAREQ_TIMER1_CC0
Definition: efm32g_dmareq.h:67
Trig on LEUART0_TXBL.
Definition: dmadrv.h:149
Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, int *remaining)
Get number of items remaining in a transfer.
Definition: dmadrv.c:852
Trig on USART1_TXBL.
Definition: dmadrv.h:266
#define DMAREQ_AES_XORDATAWR
Definition: efm32g_dmareq.h:79
#define DMAREQ_LEUART1_TXBL
Definition: efm32g_dmareq.h:58
Trig on TIMER2_CC2.
Definition: dmadrv.h:197
#define DMAREQ_USART2_TXEMPTY
Definition: efm32g_dmareq.h:53
#define DMAREQ_DAC0_CH1
Definition: efm32g_dmareq.h:44
Trig on TIMER0_CC1.
Definition: dmadrv.h:170
#define DMAREQ_ADC0_SINGLE
Definition: efm32g_dmareq.h:41
#define DMAREQ_I2C0_RXDATAV
Definition: efm32g_dmareq.h:60
Trig on LEUART1_TXBL.
Definition: dmadrv.h:158
DMADRV_Datasize_t
Data size of one UDMA transfer item.
Definition: dmadrv.h:296
Trig on UART0_TXBL.
Definition: dmadrv.h:218
Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src0, void *src1, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral ping-pong DMA transfer.
Definition: dmadrv.c:469
Trig on I2C0_RXDATAV.
Definition: dmadrv.h:131
#define DMAREQ_USART1_TXEMPTY
Definition: efm32g_dmareq.h:50
#define DMAREQ_USART0_RXDATAV
Definition: efm32g_dmareq.h:45
Trig on AES_DATAWR.
Definition: dmadrv.h:104
#define DMAREQ_TIMER2_CC2
Definition: efm32g_dmareq.h:73
Trig on ADC0_SINGLE.
Definition: dmadrv.h:98
#define DMAREQ_UART0_TXEMPTY
Definition: efm32g_dmareq.h:76
#define DMAREQ_I2C0_TXBL
Definition: efm32g_dmareq.h:61
Ecode_t DMADRV_Init(void)
Initialize DMADRV.
Definition: dmadrv.c:258
Trig on MSC_WDATA.
Definition: dmadrv.h:164
Trig on USART0_TXEMPTY.
Definition: dmadrv.h:239
Direct memory access (LDMA) API.
Trig on TIMER1_CC0.
Definition: dmadrv.h:179
Trig on TIMER0_UFOF.
Definition: dmadrv.h:176
Ecode_t DMADRV_DeInit(void)
Deinitialize DMADRV.
Definition: dmadrv.c:176
#define DMAREQ_USART1_RXDATAV
Definition: efm32g_dmareq.h:48
#define DMAREQ_LEUART0_TXEMPTY
Definition: efm32g_dmareq.h:56
Trig on DAC0_CH0.
Definition: dmadrv.h:113
Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities)
Allocate (reserve) a DMA channel.
Definition: dmadrv.c:131
#define DMAREQ_USART2_TXBL
Definition: efm32g_dmareq.h:52
Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral DMA transfer.
Definition: dmadrv.c:402
Trig on USART2_RXDATAV.
Definition: dmadrv.h:275
Trig on I2C0_TXBL.
Definition: dmadrv.h:134
uint32_t Ecode_t
Typedef for API function errorcode return values.
Definition: ecode.h:31
Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending)
Check if a transfer complete is pending.
Definition: dmadrv.c:733
#define DMAREQ_LEUART1_TXEMPTY
Definition: efm32g_dmareq.h:59
Word.
Definition: dmadrv.h:300
#define DMAREQ_USART0_TXEMPTY
Definition: efm32g_dmareq.h:47
#define DMAREQ_TIMER2_CC0
Definition: efm32g_dmareq.h:71
Trig on TIMER0_CC2.
Definition: dmadrv.h:173
DMADRV_Peripheralsignal_t
Peripherals that can trigger UDMA transfers.
Definition: dmadrv.h:91
#define DMAREQ_TIMER1_CC1
Definition: efm32g_dmareq.h:68
Trig on AES_DATARD.
Definition: dmadrv.h:101
Trig on USART2_TXBL.
Definition: dmadrv.h:281
Trig on TIMER1_CC1.
Definition: dmadrv.h:182
Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst0, void *dst1, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory ping-pong DMA transfer.
Definition: dmadrv.c:602
Direct memory access (DMA) API.
Trig on LEUART1_TXEMPTY.
Definition: dmadrv.h:161
Ecode_t DMADRV_FreeChannel(unsigned int channelId)
Free an allocate (reserved) DMA channel.
Definition: dmadrv.c:223
Trig on TIMER2_CC1.
Definition: dmadrv.h:194
#define DMAREQ_UART0_TXBL
Definition: efm32g_dmareq.h:75
Trig on TIMER2_CC0.
Definition: dmadrv.h:191
#define DMAREQ_DAC0_CH0
Definition: efm32g_dmareq.h:43
Trig on UART0_TXEMPTY.
Definition: dmadrv.h:221
#define DMAREQ_LEUART0_RXDATAV
Definition: efm32g_dmareq.h:54