EFM32 Gecko Software Documentation  efm32g-doc-4.2.1
efm32g890f128.h
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1 /**************************************************************************/
34 #ifndef EFM32G890F128_H
35 #define EFM32G890F128_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**************************************************************************/
46 /**************************************************************************/
52 typedef enum IRQn
53 {
54 /****** Cortex-M3 Processor Exceptions Numbers *******************************************/
58  BusFault_IRQn = -11,
60  SVCall_IRQn = -5,
62  PendSV_IRQn = -2,
63  SysTick_IRQn = -1,
65 /****** EFM32G Peripheral Interrupt Numbers **********************************************/
66  DMA_IRQn = 0,
71  ACMP0_IRQn = 5,
72  ADC0_IRQn = 6,
73  DAC0_IRQn = 7,
74  I2C0_IRQn = 8,
76  TIMER1_IRQn = 10,
77  TIMER2_IRQn = 11,
84  LEUART0_IRQn = 18,
85  LEUART1_IRQn = 19,
87  PCNT0_IRQn = 21,
88  PCNT1_IRQn = 22,
89  PCNT2_IRQn = 23,
90  RTC_IRQn = 24,
91  CMU_IRQn = 25,
92  VCMP_IRQn = 26,
93  LCD_IRQn = 27,
94  MSC_IRQn = 28,
95  AES_IRQn = 29,
96 } IRQn_Type;
97 
98 /**************************************************************************/
103 #define __MPU_PRESENT 1
104 #define __NVIC_PRIO_BITS 3
105 #define __Vendor_SysTickConfig 0
109 /**************************************************************************/
115 #define _EFM32_GECKO_FAMILY 1
116 #define _EFM_DEVICE
117 #define _SILICON_LABS_32B_PLATFORM_1
118 #define _SILICON_LABS_32B_PLATFORM 1
120 /* If part number is not defined as compiler option, define it */
121 #if !defined(EFM32G890F128)
122 #define EFM32G890F128 1
123 #endif
124 
126 #define PART_NUMBER "EFM32G890F128"
129 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
130 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
131 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
132 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
133 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
134 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
135 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
136 #define AES_MEM_BITS ((uint32_t) 0x10UL)
137 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
138 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
139 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
140 #define PER_MEM_BITS ((uint32_t) 0x20UL)
141 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
142 #define RAM_MEM_SIZE ((uint32_t) 0x8000UL)
143 #define RAM_MEM_END ((uint32_t) 0x20007FFFUL)
144 #define RAM_MEM_BITS ((uint32_t) 0x15UL)
145 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
146 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
147 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
148 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
149 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
150 #define EBI_MEM_SIZE ((uint32_t) 0x10000000UL)
151 #define EBI_MEM_END ((uint32_t) 0x8FFFFFFFUL)
152 #define EBI_MEM_BITS ((uint32_t) 0x28UL)
155 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
156 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
159 #define FLASH_BASE (0x00000000UL)
160 #define FLASH_SIZE (0x00020000UL)
161 #define FLASH_PAGE_SIZE 512
162 #define SRAM_BASE (0x20000000UL)
163 #define SRAM_SIZE (0x00004000UL)
164 #define __CM3_REV 0x200
165 #define PRS_CHAN_COUNT 8
166 #define DMA_CHAN_COUNT 8
169 #define AFCHAN_MAX 79
170 #define AFCHANLOC_MAX 4
171 
172 #define AFACHAN_MAX 37
173 
174 /* Part number capabilities */
175 
176 #define TIMER_PRESENT
177 #define TIMER_COUNT 3
178 #define USART_PRESENT
179 #define USART_COUNT 3
180 #define UART_PRESENT
181 #define UART_COUNT 1
182 #define LEUART_PRESENT
183 #define LEUART_COUNT 2
184 #define LETIMER_PRESENT
185 #define LETIMER_COUNT 1
186 #define PCNT_PRESENT
187 #define PCNT_COUNT 3
188 #define ACMP_PRESENT
189 #define ACMP_COUNT 2
190 #define DAC_PRESENT
191 #define DAC_COUNT 1
192 #define ADC_PRESENT
193 #define ADC_COUNT 1
194 #define I2C_PRESENT
195 #define I2C_COUNT 1
196 #define AES_PRESENT
197 #define AES_COUNT 1
198 #define DMA_PRESENT
199 #define DMA_COUNT 1
200 #define LE_PRESENT
201 #define LE_COUNT 1
202 #define MSC_PRESENT
203 #define MSC_COUNT 1
204 #define EMU_PRESENT
205 #define EMU_COUNT 1
206 #define RMU_PRESENT
207 #define RMU_COUNT 1
208 #define CMU_PRESENT
209 #define CMU_COUNT 1
210 #define EBI_PRESENT
211 #define EBI_COUNT 1
212 #define RTC_PRESENT
213 #define RTC_COUNT 1
214 #define PRS_PRESENT
215 #define PRS_COUNT 1
216 #define GPIO_PRESENT
217 #define GPIO_COUNT 1
218 #define VCMP_PRESENT
219 #define VCMP_COUNT 1
220 #define LCD_PRESENT
221 #define LCD_COUNT 1
222 #define HFXTAL_PRESENT
223 #define HFXTAL_COUNT 1
224 #define LFXTAL_PRESENT
225 #define LFXTAL_COUNT 1
226 #define WDOG_PRESENT
227 #define WDOG_COUNT 1
228 #define DBG_PRESENT
229 #define DBG_COUNT 1
230 #define BOOTLOADER_PRESENT
231 #define BOOTLOADER_COUNT 1
232 #define ANALOG_PRESENT
233 #define ANALOG_COUNT 1
234 
235 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
236 #include "system_efm32g.h" /* System Header */
237 
240 /**************************************************************************/
246 #include "efm32g_aes.h"
247 #include "efm32g_dma_ch.h"
248 #include "efm32g_dma.h"
249 #include "efm32g_msc.h"
250 #include "efm32g_emu.h"
251 #include "efm32g_rmu.h"
252 #include "efm32g_cmu.h"
253 #include "efm32g_ebi.h"
254 #include "efm32g_timer_cc.h"
255 #include "efm32g_timer.h"
256 #include "efm32g_usart.h"
257 #include "efm32g_leuart.h"
258 #include "efm32g_rtc.h"
259 #include "efm32g_letimer.h"
260 #include "efm32g_pcnt.h"
261 #include "efm32g_acmp.h"
262 #include "efm32g_prs_ch.h"
263 #include "efm32g_prs.h"
264 #include "efm32g_dac.h"
265 #include "efm32g_gpio_p.h"
266 #include "efm32g_gpio.h"
267 #include "efm32g_vcmp.h"
268 #include "efm32g_adc.h"
269 #include "efm32g_i2c.h"
270 #include "efm32g_lcd.h"
271 #include "efm32g_wdog.h"
272 #include "efm32g_dma_descriptor.h"
273 #include "efm32g_devinfo.h"
274 #include "efm32g_romtable.h"
275 #include "efm32g_calibrate.h"
276 
279 /**************************************************************************/
284 #define AES_BASE (0x400E0000UL)
285 #define DMA_BASE (0x400C2000UL)
286 #define MSC_BASE (0x400C0000UL)
287 #define EMU_BASE (0x400C6000UL)
288 #define RMU_BASE (0x400CA000UL)
289 #define CMU_BASE (0x400C8000UL)
290 #define EBI_BASE (0x40008000UL)
291 #define TIMER0_BASE (0x40010000UL)
292 #define TIMER1_BASE (0x40010400UL)
293 #define TIMER2_BASE (0x40010800UL)
294 #define USART0_BASE (0x4000C000UL)
295 #define USART1_BASE (0x4000C400UL)
296 #define USART2_BASE (0x4000C800UL)
297 #define UART0_BASE (0x4000E000UL)
298 #define LEUART0_BASE (0x40084000UL)
299 #define LEUART1_BASE (0x40084400UL)
300 #define RTC_BASE (0x40080000UL)
301 #define LETIMER0_BASE (0x40082000UL)
302 #define PCNT0_BASE (0x40086000UL)
303 #define PCNT1_BASE (0x40086400UL)
304 #define PCNT2_BASE (0x40086800UL)
305 #define ACMP0_BASE (0x40001000UL)
306 #define ACMP1_BASE (0x40001400UL)
307 #define PRS_BASE (0x400CC000UL)
308 #define DAC0_BASE (0x40004000UL)
309 #define GPIO_BASE (0x40006000UL)
310 #define VCMP_BASE (0x40000000UL)
311 #define ADC0_BASE (0x40002000UL)
312 #define I2C0_BASE (0x4000A000UL)
313 #define LCD_BASE (0x4008A000UL)
314 #define WDOG_BASE (0x40088000UL)
315 #define CALIBRATE_BASE (0x0FE08000UL)
316 #define DEVINFO_BASE (0x0FE081B0UL)
317 #define ROMTABLE_BASE (0xE00FFFD0UL)
318 #define LOCKBITS_BASE (0x0FE04000UL)
319 #define USERDATA_BASE (0x0FE00000UL)
323 /**************************************************************************/
328 #define AES ((AES_TypeDef *) AES_BASE)
329 #define DMA ((DMA_TypeDef *) DMA_BASE)
330 #define MSC ((MSC_TypeDef *) MSC_BASE)
331 #define EMU ((EMU_TypeDef *) EMU_BASE)
332 #define RMU ((RMU_TypeDef *) RMU_BASE)
333 #define CMU ((CMU_TypeDef *) CMU_BASE)
334 #define EBI ((EBI_TypeDef *) EBI_BASE)
335 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
336 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
337 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
338 #define USART0 ((USART_TypeDef *) USART0_BASE)
339 #define USART1 ((USART_TypeDef *) USART1_BASE)
340 #define USART2 ((USART_TypeDef *) USART2_BASE)
341 #define UART0 ((USART_TypeDef *) UART0_BASE)
342 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
343 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
344 #define RTC ((RTC_TypeDef *) RTC_BASE)
345 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
346 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
347 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
348 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
349 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
350 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
351 #define PRS ((PRS_TypeDef *) PRS_BASE)
352 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
353 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
354 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
355 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
356 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
357 #define LCD ((LCD_TypeDef *) LCD_BASE)
358 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
359 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
360 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
361 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
365 /**************************************************************************/
370 #include "efm32g_prs_signals.h"
371 #include "efm32g_dmareq.h"
372 #include "efm32g_dmactrl.h"
373 #include "efm32g_uart.h"
374 
375 /**************************************************************************/
379 #define MSC_UNLOCK_CODE 0x1B71
380 #define EMU_UNLOCK_CODE 0xADE8
381 #define CMU_UNLOCK_CODE 0x580E
382 #define TIMER_UNLOCK_CODE 0xCE80
383 #define GPIO_UNLOCK_CODE 0xA534
389 /**************************************************************************/
394 #include "efm32g_af_ports.h"
395 #include "efm32g_af_pins.h"
396 
399 /**************************************************************************/
412 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
413  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
414 
419 #ifdef __cplusplus
420 }
421 #endif
422 #endif /* EFM32G890F128_H */
EFM32G_ADC register and bit field definitions.
EFM32G_WDOG register and bit field definitions.
EFM32G_I2C register and bit field definitions.
EFM32G_DEVINFO register and bit field definitions.
EFM32G_GPIO register and bit field definitions.
EFM32G_LETIMER register and bit field definitions.
EFM32G_CALIBRATE register and bit field definitions.
EFM32G_CMU register and bit field definitions.
enum IRQn IRQn_Type
EFM32G_PCNT register and bit field definitions.
EFM32G_LEUART register and bit field definitions.
EFM32G_RTC register and bit field definitions.
EFM32G_USART register and bit field definitions.
EFM32G_DMA register and bit field definitions.
EFM32G_UART register and bit field definitions.
EFM32G_RMU register and bit field definitions.
EFM32G_ROMTABLE register and bit field definitions.
EFM32G_TIMER register and bit field definitions.
EFM32G_DMA_DESCRIPTOR register and bit field definitions.
EFM32G_DMACTRL register and bit field definitions.
EFM32G_AF_PINS register and bit field definitions.
EFM32G_MSC register and bit field definitions.
EFM32G_VCMP register and bit field definitions.
EFM32G_PRS_CH register and bit field definitions.
EFM32G_DMA_CH register and bit field definitions.
CMSIS Cortex-M3 System Layer for EFM32G devices.
EFM32G_PRS register and bit field definitions.
EFM32G_TIMER_CC register and bit field definitions.
EFM32G_DAC register and bit field definitions.
EFM32G_LCD register and bit field definitions.
EFM32G_GPIO_P register and bit field definitions.
EFM32G_AES register and bit field definitions.
EFM32G_EBI register and bit field definitions.
IRQn
Definition: efm32g890f128.h:52
EFM32G_EMU register and bit field definitions.
EFM32G_DMAREQ register and bit field definitions.
EFM32G_ACMP register and bit field definitions.