36 #if defined( EMU_PRESENT ) && ( EMU_COUNT > 0 )
55 #if (CMU_STATUS_AUXHFRCOENS != CMU_OSCENCMD_AUXHFRCOEN)
56 #error Conflict in AUXHFRCOENS and AUXHFRCOEN bitpositions
58 #if (CMU_STATUS_HFXOENS != CMU_OSCENCMD_HFXOEN)
59 #error Conflict in HFXOENS and HFXOEN bitpositions
61 #if (CMU_STATUS_LFRCOENS != CMU_OSCENCMD_LFRCOEN)
62 #error Conflict in LFRCOENS and LFRCOEN bitpositions
64 #if (CMU_STATUS_LFXOENS != CMU_OSCENCMD_LFXOEN)
65 #error Conflict in LFXOENS and LFXOEN bitpositions
71 #if defined( _EFM32_GECKO_FAMILY )
72 #define ERRATA_FIX_EMU_E107_EN
73 #define NON_WIC_INT_MASK_0 (~(0x0dfc0323U))
74 #define NON_WIC_INT_MASK_1 (~(0x0U))
76 #elif defined( _EFM32_TINY_FAMILY )
77 #define ERRATA_FIX_EMU_E107_EN
78 #define NON_WIC_INT_MASK_0 (~(0x001be323U))
79 #define NON_WIC_INT_MASK_1 (~(0x0U))
81 #elif defined( _EFM32_GIANT_FAMILY )
82 #define ERRATA_FIX_EMU_E107_EN
83 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
84 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
86 #elif defined( _EFM32_WONDER_FAMILY )
87 #define ERRATA_FIX_EMU_E107_EN
88 #define NON_WIC_INT_MASK_0 (~(0xff020e63U))
89 #define NON_WIC_INT_MASK_1 (~(0x00000046U))
96 #if defined( _EFM32_HAPPY_FAMILY )
97 #define ERRATA_FIX_EMU_E108_EN
102 #if defined( _EMU_DCDCCTRL_MASK )
104 #define PWRCFG_DCDCTODVDD_VMIN 1200
105 #define PWRCFG_DCDCTODVDD_VMAX 3000
109 errataFixDcdcHsTrimSet,
110 errataFixDcdcHsLnWaitDone
111 } errataFixDcdcHs_TypeDef;
112 errataFixDcdcHs_TypeDef errataFixDcdcHsState = errataFixDcdcHsInit;
129 static uint32_t cmuStatus;
130 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
131 static uint16_t cmuHfclkStatus;
133 #if defined( _EMU_DCDCCTRL_MASK )
134 static uint16_t dcdcMaxCurrent_mA;
135 static uint16_t dcdcOutput_mVout;
151 static void emuRestore(
void)
173 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
174 oscEnCmd |= ((cmuStatus & CMU_STATUS_USHFRCOENS) ? CMU_OSCENCMD_USHFRCOEN : 0);
176 CMU->OSCENCMD = oscEnCmd;
179 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
181 switch (cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
183 case CMU_HFCLKSTATUS_SELECTED_LFRCO:
188 if (!(
CMU->HFXOCTRL & CMU_HFXOCTRL_AUTOSTARTSELEM0EM1))
193 CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFRCO;
201 case CMU_HFCLKSTATUS_SELECTED_LFXO:
205 CMU->HFCLKSEL = CMU_HFCLKSEL_HF_LFXO;
208 case CMU_HFCLKSTATUS_SELECTED_HFXO:
212 CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
224 #
if defined( CMU_STATUS_USHFRCODIV2SEL )
225 | CMU_STATUS_USHFRCODIV2SEL
250 #if defined( CMU_STATUS_USHFRCODIV2SEL )
251 case CMU_STATUS_USHFRCODIV2SEL:
253 while (!(
CMU->STATUS & CMU_STATUS_USHFRCORDY))
255 CMU->CMD = _CMU_CMD_HFCLKSEL_USHFRCODIV2;
280 #if defined( ERRATA_FIX_EMU_E107_EN )
282 static __INLINE
bool getErrataFixEmuE107En(
void)
287 uint16_t majorMinorRev;
301 #if defined( _EFM32_GECKO_FAMILY )
302 return (majorMinorRev <= 0x0103);
303 #elif defined( _EFM32_TINY_FAMILY )
304 return (majorMinorRev <= 0x0102);
305 #elif defined( _EFM32_GIANT_FAMILY )
306 return (majorMinorRev <= 0x0103) || (majorMinorRev == 0x0204);
307 #elif defined( _EFM32_WONDER_FAMILY )
308 return (majorMinorRev == 0x0100);
317 #if defined( _EMU_DCDCCTRL_MASK )
319 static void maxCurrentUpdate(
void);
320 #define DCDC_LP_PFET_CNT 7
321 #define DCDC_LP_NFET_CNT 15
322 void dcdcFetCntSet(
bool lpModeSet)
325 static uint32_t emuDcdcMiscCtrlReg;
329 emuDcdcMiscCtrlReg =
EMU->DCDCMISCCTRL;
330 tmp =
EMU->DCDCMISCCTRL
331 & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK | _EMU_DCDCMISCCTRL_NFETCNT_MASK);
332 tmp |= (DCDC_LP_PFET_CNT << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT)
333 | (DCDC_LP_NFET_CNT << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
334 EMU->DCDCMISCCTRL = tmp;
339 EMU->DCDCMISCCTRL = emuDcdcMiscCtrlReg;
344 void dcdcHsFixLnBlock(
void)
346 #define EMU_DCDCSTATUS (* (volatile uint32_t *)(EMU_BASE + 0x7C))
347 if (errataFixDcdcHsState == errataFixDcdcHsTrimSet)
350 if ((
EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) == EMU_DCDCCTRL_DCDCMODE_LOWNOISE)
352 while (!(EMU_DCDCSTATUS & (0x1 << 16)));
354 errataFixDcdcHsState = errataFixDcdcHsLnWaitDone;
415 #if defined( ERRATA_FIX_EMU_E107_EN )
416 bool errataFixEmuE107En;
417 uint32_t nonWicIntEn[2];
422 cmuStatus =
CMU->STATUS;
423 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
424 cmuHfclkStatus = (uint16_t)(
CMU->HFCLKSTATUS);
428 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
432 #if defined( ERRATA_FIX_EMU_E107_EN )
433 errataFixEmuE107En = getErrataFixEmuE107En();
434 if (errataFixEmuE107En)
436 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
437 NVIC->ICER[0] = nonWicIntEn[0];
438 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
439 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
440 NVIC->ICER[1] = nonWicIntEn[1];
445 #if defined( _EMU_DCDCCTRL_MASK )
452 #if defined( _EMU_DCDCCTRL_MASK )
453 dcdcFetCntSet(
false);
457 #if defined( ERRATA_FIX_EMU_E107_EN )
458 if (errataFixEmuE107En)
460 NVIC->ISER[0] = nonWicIntEn[0];
461 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
462 NVIC->ISER[1] = nonWicIntEn[1];
475 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
476 else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
477 != CMU_HFCLKSTATUS_SELECTED_HFRCO)
533 #if defined( ERRATA_FIX_EMU_E107_EN )
534 bool errataFixEmuE107En;
535 uint32_t nonWicIntEn[2];
540 cmuStatus =
CMU->STATUS;
541 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
542 cmuHfclkStatus = (uint16_t)(
CMU->HFCLKSTATUS);
559 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
563 #if defined( ERRATA_FIX_EMU_E107_EN )
564 errataFixEmuE107En = getErrataFixEmuE107En();
565 if (errataFixEmuE107En)
567 nonWicIntEn[0] = NVIC->ISER[0] & NON_WIC_INT_MASK_0;
568 NVIC->ICER[0] = nonWicIntEn[0];
569 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
570 nonWicIntEn[1] = NVIC->ISER[1] & NON_WIC_INT_MASK_1;
571 NVIC->ICER[1] = nonWicIntEn[1];
577 #if defined( _EMU_DCDCCTRL_MASK )
584 #if defined( _EMU_DCDCCTRL_MASK )
585 dcdcFetCntSet(
false);
589 #if defined( ERRATA_FIX_EMU_E107_EN )
590 if (errataFixEmuE107En)
592 NVIC->ISER[0] = nonWicIntEn[0];
593 #if (NON_WIC_INT_MASK_1 != (~(0x0U)))
594 NVIC->ISER[1] = nonWicIntEn[1];
607 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
608 else if ((cmuHfclkStatus & _CMU_HFCLKSTATUS_SELECTED_MASK)
609 != CMU_HFCLKSTATUS_SELECTED_HFRCO)
630 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
631 uint32_t em4seq2 = (
EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
632 | (2 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
633 uint32_t em4seq3 = (
EMU->EM4CTRL & ~_EMU_EM4CTRL_EM4ENTRY_MASK)
634 | (3 << _EMU_EM4CTRL_EM4ENTRY_SHIFT);
645 #if defined( ERRATA_FIX_EMU_E108_EN )
648 *(
volatile uint32_t *)0x400C80E4 = 0;
651 #if defined( _EMU_DCDCCTRL_MASK )
656 for (i = 0; i < 4; i++)
658 #if defined( _EMU_EM4CTRL_EM4ENTRY_SHIFT )
659 EMU->EM4CTRL = em4seq2;
660 EMU->EM4CTRL = em4seq3;
662 EMU->EM4CTRL = em4seq2;
689 #if defined( _EMU_MEMCTRL_POWERDOWN_MASK )
692 EMU->MEMCTRL = blocks;
694 #elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK ) \
695 && defined( _EMU_MEMCTRL_RAMHPOWERDOWN_MASK ) \
696 && defined( _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK )
697 EFM_ASSERT((blocks & (_EMU_MEMCTRL_RAMPOWERDOWN_MASK
698 | _EMU_MEMCTRL_RAMHPOWERDOWN_MASK
699 | _EMU_MEMCTRL_SEQRAMPOWERDOWN_MASK))
701 EMU->MEMCTRL = blocks;
703 #elif defined( _EMU_MEMCTRL_RAMPOWERDOWN_MASK )
704 EFM_ASSERT((blocks & _EMU_MEMCTRL_RAMPOWERDOWN_MASK) == blocks);
705 EMU->MEMCTRL = blocks;
707 #elif defined( _EMU_RAM0CTRL_RAMPOWERDOWN_MASK )
708 EFM_ASSERT((blocks & _EMU_RAM0CTRL_RAMPOWERDOWN_MASK) == blocks);
709 EMU->RAM0CTRL = blocks;
739 cmuStatus =
CMU->STATUS;
740 #if defined( _CMU_HFCLKSTATUS_RESETVALUE )
741 cmuHfclkStatus = (uint16_t)(
CMU->HFCLKSTATUS);
755 #if defined( _EMU_CTRL_EMVREG_MASK )
758 #elif defined( _EMU_CTRL_EM23VREG_MASK )
760 : (
EMU->CTRL & ~EMU_CTRL_EM23VREG);
767 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
775 void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)
777 #if defined( _EMU_EM4CONF_MASK )
779 uint32_t em4conf =
EMU->EM4CONF;
782 em4conf &= ~(_EMU_EM4CONF_LOCKCONF_MASK
783 | _EMU_EM4CONF_OSC_MASK
784 | _EMU_EM4CONF_BURTCWU_MASK
785 | _EMU_EM4CONF_VREGEN_MASK);
788 em4conf |= (em4Init->lockConfig << _EMU_EM4CONF_LOCKCONF_SHIFT)
790 | (em4Init->buRtcWakeup << _EMU_EM4CONF_BURTCWU_SHIFT)
791 | (em4Init->vreg << _EMU_EM4CONF_VREGEN_SHIFT);
794 EMU->EM4CONF = em4conf;
796 #elif defined( _EMU_EM4CTRL_MASK )
799 uint32_t em4ctrl =
EMU->EM4CTRL;
801 em4ctrl &= ~(_EMU_EM4CTRL_RETAINLFXO_MASK
802 | _EMU_EM4CTRL_RETAINLFRCO_MASK
803 | _EMU_EM4CTRL_RETAINULFRCO_MASK
804 | _EMU_EM4CTRL_EM4STATE_MASK
805 | _EMU_EM4CTRL_EM4IORETMODE_MASK);
807 em4ctrl |= (em4Init->retainLfxo ? EMU_EM4CTRL_RETAINLFXO : 0)
808 | (em4Init->retainLfrco ? EMU_EM4CTRL_RETAINLFRCO : 0)
809 | (em4Init->retainUlfrco ? EMU_EM4CTRL_RETAINULFRCO : 0)
810 | (em4Init->em4State ? EMU_EM4CTRL_EM4STATE_EM4H : 0)
811 | (em4Init->pinRetentionMode);
813 EMU->EM4CTRL = em4ctrl;
819 #if defined( BU_PRESENT )
827 void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
832 reg =
EMU->PWRCONF & ~(_EMU_PWRCONF_PWRRES_MASK
833 | _EMU_PWRCONF_VOUTSTRONG_MASK
834 | _EMU_PWRCONF_VOUTMED_MASK
835 | _EMU_PWRCONF_VOUTWEAK_MASK);
837 reg |= bupdInit->resistor
838 | (bupdInit->voutStrong << _EMU_PWRCONF_VOUTSTRONG_SHIFT)
839 | (bupdInit->voutMed << _EMU_PWRCONF_VOUTMED_SHIFT)
840 | (bupdInit->voutWeak << _EMU_PWRCONF_VOUTWEAK_SHIFT);
845 reg =
EMU->BUINACT & ~(_EMU_BUINACT_PWRCON_MASK);
846 reg |= (bupdInit->inactivePower);
850 reg =
EMU->BUACT & ~(_EMU_BUACT_PWRCON_MASK);
851 reg |= (bupdInit->activePower);
855 reg =
EMU->BUCTRL & ~(_EMU_BUCTRL_PROBE_MASK
856 | _EMU_BUCTRL_BODCAL_MASK
857 | _EMU_BUCTRL_STATEN_MASK
858 | _EMU_BUCTRL_EN_MASK);
862 reg |= bupdInit->probe
863 | (bupdInit->bodCal << _EMU_BUCTRL_BODCAL_SHIFT)
864 | (bupdInit->statusPinEnable << _EMU_BUCTRL_STATEN_SHIFT)
865 | (bupdInit->enable << _EMU_BUCTRL_EN_SHIFT);
871 EMU_BUPinEnable(bupdInit->enable);
889 EFM_ASSERT(value<=(_EMU_BUACT_BUEXTHRES_MASK>>_EMU_BUACT_BUEXTHRES_SHIFT));
894 EMU->BUACT = (
EMU->BUACT & ~_EMU_BUACT_BUEXTHRES_MASK)
895 | (value<<_EMU_BUACT_BUEXTHRES_SHIFT);
898 EMU->BUINACT = (
EMU->BUINACT & ~_EMU_BUINACT_BUENTHRES_MASK)
899 | (value<<_EMU_BUINACT_BUENTHRES_SHIFT);
915 EFM_ASSERT(value < 4);
916 EFM_ASSERT(value<=(_EMU_BUACT_BUEXRANGE_MASK>>_EMU_BUACT_BUEXRANGE_SHIFT));
921 EMU->BUACT = (
EMU->BUACT & ~_EMU_BUACT_BUEXRANGE_MASK)
922 | (value<<_EMU_BUACT_BUEXRANGE_SHIFT);
925 EMU->BUINACT = (
EMU->BUINACT & ~_EMU_BUINACT_BUENRANGE_MASK)
926 | (value<<_EMU_BUINACT_BUENRANGE_SHIFT);
933 #if defined( _EMU_DCDCCTRL_MASK )
945 static bool ConstCalibrationLoad(
void)
948 volatile uint32_t *reg;
951 volatile uint32_t*
const diCal_EMU_DCDCLNFREQCTRL = (
volatile uint32_t *)(0x0FE08038);
952 volatile uint32_t*
const diCal_EMU_DCDCLNVCTRL = (
volatile uint32_t *)(0x0FE08040);
953 volatile uint32_t*
const diCal_EMU_DCDCLPCTRL = (
volatile uint32_t *)(0x0FE08048);
954 volatile uint32_t*
const diCal_EMU_DCDCLPVCTRL = (
volatile uint32_t *)(0x0FE08050);
955 volatile uint32_t*
const diCal_EMU_DCDCTRIM0 = (
volatile uint32_t *)(0x0FE08058);
956 volatile uint32_t*
const diCal_EMU_DCDCTRIM1 = (
volatile uint32_t *)(0x0FE08060);
958 if (
DEVINFO->DCDCLPVCTRL0 != UINT_MAX)
960 val = *(diCal_EMU_DCDCLNFREQCTRL + 1);
961 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLNFREQCTRL;
964 val = *(diCal_EMU_DCDCLNVCTRL + 1);
965 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLNVCTRL;
968 val = *(diCal_EMU_DCDCLPCTRL + 1);
969 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLPCTRL;
972 val = *(diCal_EMU_DCDCLPVCTRL + 1);
973 reg = (
volatile uint32_t *)*diCal_EMU_DCDCLPVCTRL;
976 val = *(diCal_EMU_DCDCTRIM0 + 1);
977 reg = (
volatile uint32_t *)*diCal_EMU_DCDCTRIM0;
980 val = *(diCal_EMU_DCDCTRIM1 + 1);
981 reg = (
volatile uint32_t *)*diCal_EMU_DCDCTRIM1;
997 void ValidatedConfigSet(
void)
999 #define EMU_DCDCSMCTRL (* (volatile uint32_t *)(EMU_BASE + 0x44))
1001 uint32_t dcdcTiming;
1006 EMU->DCDCLPCTRL |= EMU_DCDCLPCTRL_LPVREFDUTYEN;
1009 #if defined( _EFR_DEVICE )
1011 EMU->DCDCLNFREQCTRL = (
EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
1012 | (EMU_DcdcLnRcoBand_7MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
1015 EMU->DCDCLNFREQCTRL = (
EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
1016 | (EMU_DcdcLnRcoBand_3MHz << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
1019 EMU->DCDCTIMING &= ~_EMU_DCDCTIMING_DUTYSCALE_MASK;
1023 if ((((family >= systemPartFamilyMighty1P)
1024 && (family <= systemPartFamilyFlex1V))
1025 || (family == systemPartFamilyEfm32Pearl1B)
1026 || (family == systemPartFamilyEfm32Jade1B))
1028 && (errataFixDcdcHsState == errataFixDcdcHsInit))
1031 EMU_DCDCSMCTRL |= 1;
1033 dcdcTiming =
EMU->DCDCTIMING;
1034 dcdcTiming &= ~(_EMU_DCDCTIMING_LPINITWAIT_MASK
1035 |_EMU_DCDCTIMING_LNWAIT_MASK
1036 |_EMU_DCDCTIMING_BYPWAIT_MASK);
1038 dcdcTiming |= ((180 << _EMU_DCDCTIMING_LPINITWAIT_SHIFT)
1039 | (12 << _EMU_DCDCTIMING_LNWAIT_SHIFT)
1040 | (180 << _EMU_DCDCTIMING_BYPWAIT_SHIFT));
1041 EMU->DCDCTIMING = dcdcTiming;
1043 errataFixDcdcHsState = errataFixDcdcHsTrimSet;
1053 static void maxCurrentUpdate(
void)
1055 uint32_t lncLimImSel;
1056 uint32_t lpcLimImSel;
1059 pFetCnt = (
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_PFETCNT_MASK)
1060 >> _EMU_DCDCMISCCTRL_PFETCNT_SHIFT;
1064 lncLimImSel = (dcdcMaxCurrent_mA / (5 * (pFetCnt + 1))) - 1;
1066 lpcLimImSel = (80 / (5 * (pFetCnt + 1))) - 1;
1068 lncLimImSel <<= _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT;
1069 lpcLimImSel <<= _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT;
1070 EMU->DCDCMISCCTRL = (
EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK
1071 | _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK))
1072 | (lncLimImSel | lpcLimImSel);
1084 static void maxCurrentSet(uint32_t mAmaxCurrent)
1086 dcdcMaxCurrent_mA = mAmaxCurrent;
1101 static bool LpCmpHystCalibrationLoad(
bool lpAttenuation, uint32_t lpCmpBias)
1104 uint32_t lpcmpHystSel;
1107 devinfoRev = SYSTEM_GetDevinfoRev();
1112 lpcmpHystSel =
DEVINFO->DCDCLPCMPHYSSEL0;
1116 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_MASK)
1117 >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT1_SHIFT;
1121 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_MASK)
1122 >> _DEVINFO_DCDCLPCMPHYSSEL0_LPCMPHYSSELLPATT0_SHIFT;
1129 lpcmpHystSel =
DEVINFO->DCDCLPCMPHYSSEL1;
1132 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
1133 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_MASK)
1134 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS0_SHIFT;
1137 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
1138 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_MASK)
1139 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS1_SHIFT;
1142 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
1143 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_MASK)
1144 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS2_SHIFT;
1147 case _EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
1148 lpcmpHystSel = (lpcmpHystSel & _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_MASK)
1149 >> _DEVINFO_DCDCLPCMPHYSSEL1_LPCMPHYSSELLPCMPBIAS3_SHIFT;
1160 lpcmpHystSel <<= _EMU_DCDCLPCTRL_LPCMPHYSSEL_SHIFT;
1161 if (lpcmpHystSel & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK)
1167 EMU->DCDCLPCTRL = (
EMU->DCDCLPCTRL & ~_EMU_DCDCLPCTRL_LPCMPHYSSEL_MASK) | lpcmpHystSel;
1182 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode)
1184 while(
EMU->DCDCSYNC & EMU_DCDCSYNC_DCDCCTRLBUSY);
1185 BUS_RegBitWrite(&
EMU->DCDCCLIMCTRL, _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT, dcdcMode == emuDcdcMode_Bypass ? 0 : 1);
1186 EMU->DCDCCTRL = (
EMU->DCDCCTRL & ~_EMU_DCDCCTRL_DCDCMODE_MASK) | dcdcMode;
1204 bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit)
1206 uint32_t lpCmpBiasSel;
1210 EMU->PWRCFG = dcdcInit->powerConfig;
1214 if ((
EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != dcdcInit->powerConfig)
1224 ConstCalibrationLoad();
1227 EFM_ASSERT(dcdcInit->maxCurrent_mA <= 200);
1228 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= dcdcInit->maxCurrent_mA);
1231 if (dcdcInit->dcdcMode == emuDcdcMode_LowNoise)
1233 EFM_ASSERT(dcdcInit->em01LoadCurrent_mA <= 200);
1237 EFM_ASSERT(dcdcInit->em234LoadCurrent_uA <= 100);
1240 lpCmpBiasSel = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1;
1241 if (dcdcInit->em234LoadCurrent_uA <= 10)
1243 lpCmpBiasSel = EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0;
1247 EMU->DCDCMISCCTRL = (
EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK
1248 | _EMU_DCDCMISCCTRL_LNFORCECCM_MASK))
1249 | ((uint32_t)lpCmpBiasSel
1250 | (uint32_t)dcdcInit->lnTransientMode);
1253 ValidatedConfigSet();
1256 maxCurrentSet(dcdcInit->maxCurrent_mA);
1259 EMU_DCDCOptimizeSlice(dcdcInit->em01LoadCurrent_mA);
1262 dcdcOutput_mVout = dcdcInit->mVout;
1263 if (!EMU_DCDCOutputVoltageSet(dcdcOutput_mVout,
true,
true))
1272 EMU_DCDCModeSet(dcdcInit->dcdcMode);
1275 BUS_RegBitWrite(&
EMU->PWRCTRL, _EMU_PWRCTRL_ANASW_SHIFT, dcdcInit->anaPeripheralPower ? 1 : 0);
1291 bool EMU_DCDCOutputVoltageSet(uint32_t mV,
1295 #if defined( _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK )
1297 bool validOutVoltage;
1301 uint32_t vrefLow = 0;
1302 uint32_t vrefHigh = 0;
1303 uint32_t vrefVal = 0;
1305 uint32_t mVhigh = 0;
1308 volatile uint32_t* ctrlReg;
1312 validOutVoltage =
false;
1313 if ((
EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) == EMU_PWRCFG_PWRCFG_DCDCTODVDD)
1315 validOutVoltage = ((mV >= PWRCFG_DCDCTODVDD_VMIN)
1316 && (mV <= PWRCFG_DCDCTODVDD_VMAX));
1319 if (!validOutVoltage)
1327 for (lnMode = 0; lnMode <= 1; lnMode++)
1329 if (((lnMode == 0) && !setLpVoltage)
1330 || ((lnMode == 1) && !setLnVoltage))
1335 ctrlReg = (lnMode ? &
EMU->DCDCLNVCTRL : &
EMU->DCDCLPVCTRL);
1336 vrefShift = (lnMode ? _EMU_DCDCLNVCTRL_LNVREF_SHIFT
1337 : _EMU_DCDCLPVCTRL_LPVREF_SHIFT);
1340 attSet = (mV > 1800);
1345 attMask = (lnMode ? EMU_DCDCLNVCTRL_LNATT : EMU_DCDCLPVCTRL_LPATT);
1360 vrefLow =
DEVINFO->DCDCLNVCTRL0;
1361 vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_MASK)
1362 >> _DEVINFO_DCDCLNVCTRL0_3V0LNATT1_SHIFT;
1363 vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_MASK)
1364 >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT1_SHIFT;
1368 vrefLow =
DEVINFO->DCDCLNVCTRL0;
1369 vrefHigh = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_MASK)
1370 >> _DEVINFO_DCDCLNVCTRL0_1V8LNATT0_SHIFT;
1371 vrefLow = (vrefLow & _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_MASK)
1372 >> _DEVINFO_DCDCLNVCTRL0_1V2LNATT0_SHIFT;
1380 lpcmpBias =
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LPCMPBIAS_MASK;
1381 EFM_ASSERT(!(_EMU_DCDCMISCCTRL_LPCMPBIAS_MASK & attMask));
1382 switch (attMask | lpcmpBias)
1384 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
1385 vrefLow =
DEVINFO->DCDCLPVCTRL2;
1386 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_MASK)
1387 >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS0_SHIFT;
1388 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_MASK)
1389 >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS0_SHIFT;
1392 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
1393 vrefLow =
DEVINFO->DCDCLPVCTRL2;
1394 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_MASK)
1395 >> _DEVINFO_DCDCLPVCTRL2_3V0LPATT1LPCMPBIAS1_SHIFT;
1396 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_MASK)
1397 >> _DEVINFO_DCDCLPVCTRL2_1V8LPATT1LPCMPBIAS1_SHIFT;
1400 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
1401 vrefLow =
DEVINFO->DCDCLPVCTRL3;
1402 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_MASK)
1403 >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS2_SHIFT;
1404 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_MASK)
1405 >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS2_SHIFT;
1408 case EMU_DCDCLPVCTRL_LPATT | EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
1409 vrefLow =
DEVINFO->DCDCLPVCTRL3;
1410 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_MASK)
1411 >> _DEVINFO_DCDCLPVCTRL3_3V0LPATT1LPCMPBIAS3_SHIFT;
1412 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_MASK)
1413 >> _DEVINFO_DCDCLPVCTRL3_1V8LPATT1LPCMPBIAS3_SHIFT;
1416 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS0:
1417 vrefLow =
DEVINFO->DCDCLPVCTRL0;
1418 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_MASK)
1419 >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS0_SHIFT;
1420 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_MASK)
1421 >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS0_SHIFT;
1424 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS1:
1425 vrefLow =
DEVINFO->DCDCLPVCTRL0;
1426 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_MASK)
1427 >> _DEVINFO_DCDCLPVCTRL0_1V8LPATT0LPCMPBIAS1_SHIFT;
1428 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_MASK)
1429 >> _DEVINFO_DCDCLPVCTRL0_1V2LPATT0LPCMPBIAS1_SHIFT;
1432 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS2:
1433 vrefLow =
DEVINFO->DCDCLPVCTRL1;
1434 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_MASK)
1435 >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS2_SHIFT;
1436 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_MASK)
1437 >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS2_SHIFT;
1440 case EMU_DCDCMISCCTRL_LPCMPBIAS_BIAS3:
1441 vrefLow =
DEVINFO->DCDCLPVCTRL1;
1442 vrefHigh = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_MASK)
1443 >> _DEVINFO_DCDCLPVCTRL1_1V8LPATT0LPCMPBIAS3_SHIFT;
1444 vrefLow = (vrefLow & _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_MASK)
1445 >> _DEVINFO_DCDCLPVCTRL1_1V2LPATT0LPCMPBIAS3_SHIFT;
1454 if(!(LpCmpHystCalibrationLoad(attSet, lpcmpBias >> _EMU_DCDCMISCCTRL_LPCMPBIAS_SHIFT)))
1464 if ((vrefLow == 0xFF) && (vrefHigh == 0xFF))
1472 vrefVal = ((mV - mVlow) * (vrefHigh - vrefLow)) / (mVhigh - mVlow);
1476 if ((vrefVal > vrefHigh) || (vrefVal < vrefLow))
1484 *ctrlReg = (vrefVal << vrefShift) | attMask;
1499 void EMU_DCDCOptimizeSlice(uint32_t mAEm0LoadCurrent)
1501 uint32_t sliceCount = 0;
1502 uint32_t rcoBand = (
EMU->DCDCLNFREQCTRL & _EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
1503 >> _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT;
1506 if ((
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand >= EMU_DcdcLnRcoBand_5MHz))
1508 if (mAEm0LoadCurrent < 20)
1512 else if ((mAEm0LoadCurrent >= 20) && (mAEm0LoadCurrent < 40))
1521 else if ((!(
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK)) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))
1523 if (mAEm0LoadCurrent < 10)
1527 else if ((mAEm0LoadCurrent >= 10) && (mAEm0LoadCurrent < 20))
1536 else if ((
EMU->DCDCMISCCTRL & _EMU_DCDCMISCCTRL_LNFORCECCM_MASK) && (rcoBand <= EMU_DcdcLnRcoBand_4MHz))
1538 if (mAEm0LoadCurrent < 40)
1558 sliceCount = (sliceCount << _EMU_DCDCMISCCTRL_PFETCNT_SHIFT
1559 | sliceCount << _EMU_DCDCMISCCTRL_NFETCNT_SHIFT);
1560 EMU->DCDCMISCCTRL = (
EMU->DCDCMISCCTRL & ~(_EMU_DCDCMISCCTRL_PFETCNT_MASK
1561 | _EMU_DCDCMISCCTRL_NFETCNT_MASK))
1575 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band)
1577 EMU->DCDCLNFREQCTRL = (
EMU->DCDCLNFREQCTRL & ~_EMU_DCDCLNFREQCTRL_RCOBAND_MASK)
1578 | (band << _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT);
1594 bool EMU_DCDCPowerOff(
void)
1598 if ((
EMU->PWRCFG & _EMU_PWRCFG_PWRCFG_MASK) != 0xF)
1606 EMU->DCDCCTRL = EMU_DCDCCTRL_DCDCMODE_OFF;
1612 #if defined( EMU_STATUS_VMONRDY )
1614 __STATIC_INLINE uint32_t vmonMilliVoltToCoarseThreshold(
int mV)
1616 return (mV - 1200) / 200;
1619 __STATIC_INLINE uint32_t vmonMilliVoltToFineThreshold(
int mV, uint32_t coarseThreshold)
1621 return (mV - 1200 - (coarseThreshold * 200)) / 20;
1637 void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit)
1639 uint32_t thresholdCoarse, thresholdFine;
1640 EFM_ASSERT((vmonInit->threshold >= 1200) && (vmonInit->threshold <= 3980));
1642 thresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->threshold);
1643 thresholdFine = vmonMilliVoltToFineThreshold(vmonInit->threshold, thresholdCoarse);
1645 switch(vmonInit->channel)
1647 case emuVmonChannel_AVDD:
1648 EMU->VMONAVDDCTRL = (thresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
1649 | (thresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
1650 | (thresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
1651 | (thresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
1652 | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
1653 | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
1654 | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
1656 case emuVmonChannel_ALTAVDD:
1657 EMU->VMONALTAVDDCTRL = (thresholdCoarse << _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT)
1658 | (thresholdFine << _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT)
1659 | (vmonInit->riseWakeup ? EMU_VMONALTAVDDCTRL_RISEWU : 0)
1660 | (vmonInit->fallWakeup ? EMU_VMONALTAVDDCTRL_FALLWU : 0)
1661 | (vmonInit->enable ? EMU_VMONALTAVDDCTRL_EN : 0);
1663 case emuVmonChannel_DVDD:
1664 EMU->VMONDVDDCTRL = (thresholdCoarse << _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT)
1665 | (thresholdFine << _EMU_VMONDVDDCTRL_THRESFINE_SHIFT)
1666 | (vmonInit->riseWakeup ? EMU_VMONDVDDCTRL_RISEWU : 0)
1667 | (vmonInit->fallWakeup ? EMU_VMONDVDDCTRL_FALLWU : 0)
1668 | (vmonInit->enable ? EMU_VMONDVDDCTRL_EN : 0);
1670 case emuVmonChannel_IOVDD0:
1671 EMU->VMONIO0CTRL = (thresholdCoarse << _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT)
1672 | (thresholdFine << _EMU_VMONIO0CTRL_THRESFINE_SHIFT)
1673 | (vmonInit->retDisable ? EMU_VMONIO0CTRL_RETDIS : 0)
1674 | (vmonInit->riseWakeup ? EMU_VMONIO0CTRL_RISEWU : 0)
1675 | (vmonInit->fallWakeup ? EMU_VMONIO0CTRL_FALLWU : 0)
1676 | (vmonInit->enable ? EMU_VMONIO0CTRL_EN : 0);
1695 void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit)
1697 uint32_t riseThresholdCoarse, riseThresholdFine, fallThresholdCoarse, fallThresholdFine;
1699 EFM_ASSERT((vmonInit->riseThreshold >= 1200) && (vmonInit->riseThreshold < 4000));
1700 EFM_ASSERT((vmonInit->fallThreshold >= 1200) && (vmonInit->fallThreshold < 4000));
1702 EFM_ASSERT(vmonInit->fallThreshold <= vmonInit->riseThreshold);
1704 riseThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->riseThreshold);
1705 riseThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->riseThreshold, riseThresholdCoarse);
1706 fallThresholdCoarse = vmonMilliVoltToCoarseThreshold(vmonInit->fallThreshold);
1707 fallThresholdFine = vmonMilliVoltToFineThreshold(vmonInit->fallThreshold, fallThresholdCoarse);
1709 switch(vmonInit->channel)
1711 case emuVmonChannel_AVDD:
1712 EMU->VMONAVDDCTRL = (riseThresholdCoarse << _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT)
1713 | (riseThresholdFine << _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT)
1714 | (fallThresholdCoarse << _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT)
1715 | (fallThresholdFine << _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT)
1716 | (vmonInit->riseWakeup ? EMU_VMONAVDDCTRL_RISEWU : 0)
1717 | (vmonInit->fallWakeup ? EMU_VMONAVDDCTRL_FALLWU : 0)
1718 | (vmonInit->enable ? EMU_VMONAVDDCTRL_EN : 0);
1736 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel,
bool enable)
1738 uint32_t
volatile * reg;
1743 case emuVmonChannel_AVDD:
1744 reg = &(
EMU->VMONAVDDCTRL);
1745 bit = _EMU_VMONAVDDCTRL_EN_SHIFT;
1747 case emuVmonChannel_ALTAVDD:
1748 reg = &(
EMU->VMONALTAVDDCTRL);
1749 bit = _EMU_VMONALTAVDDCTRL_EN_SHIFT;
1751 case emuVmonChannel_DVDD:
1752 reg = &(
EMU->VMONDVDDCTRL);
1753 bit = _EMU_VMONDVDDCTRL_EN_SHIFT;
1755 case emuVmonChannel_IOVDD0:
1756 reg = &(
EMU->VMONIO0CTRL);
1757 bit = _EMU_VMONIO0CTRL_EN_SHIFT;
1777 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel)
1782 case emuVmonChannel_AVDD:
1783 bit = _EMU_STATUS_VMONAVDD_SHIFT;
1785 case emuVmonChannel_ALTAVDD:
1786 bit = _EMU_STATUS_VMONALTAVDD_SHIFT;
1788 case emuVmonChannel_DVDD:
1789 bit = _EMU_STATUS_VMONDVDD_SHIFT;
1791 case emuVmonChannel_IOVDD0:
1792 bit = _EMU_STATUS_VMONIO0_SHIFT;
Clock management unit (CMU) API.
#define CMU_STATUS_HFXOENS
__STATIC_INLINE void CMU_Lock(void)
Lock the CMU in order to protect some of its registers against unintended modification.
Emlib peripheral API "assert" implementation.
#define CMU_STATUS_LFRCORDY
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
void SYSTEM_ChipRevisionGet(SYSTEM_ChipRevision_TypeDef *rev)
Get chip major/minor revision.
#define CMU_STATUS_HFRCOENS
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
#define CMU_OSCENCMD_AUXHFRCOEN
#define CMU_LOCK_LOCKKEY_LOCKED
#define CMU_STATUS_LFRCOENS
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
#define CMU_STATUS_LFXOSEL
#define CMU_OSCENCMD_HFRCODIS
#define _ROMTABLE_PID0_REVMAJOR_MASK
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
#define CMU_STATUS_HFXOSEL
#define _ROMTABLE_PID2_REVMINORMSB_MASK
#define _EMU_MEMCTRL_POWERDOWN_SHIFT
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
Get family identifier of the MCU.
#define CMU_STATUS_LFRCOSEL
#define CMU_OSCENCMD_LFRCOEN
#define CMU_CMD_HFCLKSEL_LFXO
#define CMU_STATUS_LFXOENS
#define CMU_CMD_HFCLKSEL_LFRCO
#define CMU_OSCENCMD_LFRCODIS
#define CMU_OSCENCMD_LFXOEN
#define _EMU_MEMCTRL_POWERDOWN_MASK
void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
#define CMU_OSCENCMD_HFRCOEN
#define _EMU_CTRL_EM4CTRL_MASK
#define CMU_OSCENCMD_HFXOEN
Energy management unit (EMU) peripheral API.
#define _ROMTABLE_PID3_REVMINORLSB_MASK
#define _EMU_CTRL_EM4CTRL_SHIFT
#define CMU_OSCENCMD_LFXODIS
#define CMU_STATUS_AUXHFRCOENS
static __INLINE void SystemCoreClockUpdate(void)
Update CMSIS SystemCoreClock variable.
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
#define CMU_STATUS_LFXORDY
#define CMU_CMD_HFCLKSEL_HFXO
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define CMU_STATUS_HFRCOSEL
#define CMU_STATUS_HFXORDY
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
__STATIC_INLINE void CMU_Unlock(void)
Unlock the CMU so that writing to locked registers again is possible.
SYSTEM_PartFamily_TypeDef