EFM32 Gecko Software Documentation  efm32g-doc-4.2.1
em_cmu.c
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1 /***************************************************************************/
32 #include "em_cmu.h"
33 #if defined( CMU_PRESENT )
34 
35 #include <stddef.h>
36 #include <limits.h>
37 #include "em_assert.h"
38 #include "em_bus.h"
39 #include "em_emu.h"
40 #include "em_system.h"
41 
42 /***************************************************************************/
47 /***************************************************************************/
53 /*******************************************************************************
54  ****************************** DEFINES ************************************
55  ******************************************************************************/
56 
59 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
60 
61 #define CMU_MAX_FREQ_0WS 26000000
62 
63 #define CMU_MAX_FREQ_1WS 40000000
64 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
65 
66 #define CMU_MAX_FREQ_0WS 16000000
67 
68 #define CMU_MAX_FREQ_1WS 32000000
69 #else
70 #error "Unkown MCU platform."
71 #endif
72 
73 #if defined( CMU_CTRL_HFLE )
74 
76 #if defined( _EFM32_WONDER_FAMILY ) \
77  || defined( _EZR32_LEOPARD_FAMILY ) \
78  || defined( _EZR32_WONDER_FAMILY )
79 #define CMU_MAX_FREQ_HFLE() 24000000
80 #elif defined ( _EFM32_GIANT_FAMILY )
81 #define CMU_MAX_FREQ_HFLE() (maxFreqHfle())
82 #else
83 #error Invalid part/device.
84 #endif
85 #endif
86 
87 /*******************************************************************************
88  ************************** LOCAL VARIABLES ********************************
89  ******************************************************************************/
90 
91 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
92 static CMU_AUXHFRCOFreq_TypeDef auxHfrcoFreq = cmuAUXHFRCOFreq_19M0Hz;
93 #endif
94 
97 /*******************************************************************************
98  ************************** LOCAL FUNCTIONS ********************************
99  ******************************************************************************/
100 
103 /***************************************************************************/
111 static uint32_t auxClkGet(void)
112 {
113  uint32_t ret;
114 
115 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
116  ret = auxHfrcoFreq;
117 
118 #elif defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
119  /* All Geckos from TG and newer */
120  switch(CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_BAND_MASK)
121  {
122  case CMU_AUXHFRCOCTRL_BAND_1MHZ:
123  ret = 1000000;
124  break;
125 
126  case CMU_AUXHFRCOCTRL_BAND_7MHZ:
127  ret = 7000000;
128  break;
129 
130  case CMU_AUXHFRCOCTRL_BAND_11MHZ:
131  ret = 11000000;
132  break;
133 
134  case CMU_AUXHFRCOCTRL_BAND_14MHZ:
135  ret = 14000000;
136  break;
137 
138  case CMU_AUXHFRCOCTRL_BAND_21MHZ:
139  ret = 21000000;
140  break;
141 
142 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
143  case CMU_AUXHFRCOCTRL_BAND_28MHZ:
144  ret = 28000000;
145  break;
146 #endif
147 
148  default:
149  EFM_ASSERT(0);
150  ret = 0;
151  break;
152  }
153 
154 #else
155  /* Gecko has a fixed 14Mhz AUXHFRCO clock */
156  ret = 14000000;
157 
158 #endif
159 
160  return ret;
161 }
162 
163 
164 /***************************************************************************/
171 static uint32_t dbgClkGet(void)
172 {
173  uint32_t ret;
174  CMU_Select_TypeDef clk;
175 
176  /* Get selected clock source */
178 
179  switch(clk)
180  {
181  case cmuSelect_HFCLK:
182  ret = SystemHFClockGet();
183 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
184  /* Family with an additional divider. */
185  ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
186  >> _CMU_CTRL_HFCLKDIV_SHIFT));
187 #endif
188  break;
189 
190  case cmuSelect_AUXHFRCO:
191  ret = auxClkGet();
192  break;
193 
194  default:
195  EFM_ASSERT(0);
196  ret = 0;
197  break;
198  }
199  return ret;
200 }
201 
202 
203 /***************************************************************************/
211 static void flashWaitStateControl(uint32_t coreFreq)
212 {
213  uint32_t mode;
214  bool mscLocked;
215 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
216  bool scbtpEn; /* Suppressed Conditional Branch Target Prefetch setting. */
217 #endif
218 
219  /* Make sure the MSC is unlocked */
220  mscLocked = MSC->LOCK;
221  MSC->LOCK = MSC_UNLOCK_CODE;
222 
223  /* Get mode and SCBTP enable */
224  mode = MSC->READCTRL & _MSC_READCTRL_MODE_MASK;
225 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
226  switch(mode)
227  {
230 #if defined( MSC_READCTRL_MODE_WS2 )
231  case MSC_READCTRL_MODE_WS2:
232 #endif
233  scbtpEn = false;
234  break;
235 
236  default: /* WSxSCBTP */
237  scbtpEn = true;
238  break;
239  }
240 #endif
241 
242 
243  /* Set mode based on the core clock frequency and SCBTP enable */
244 #if defined( MSC_READCTRL_MODE_WS0SCBTP )
245  if (false)
246  {
247  }
248 #if defined( MSC_READCTRL_MODE_WS2 )
249  else if (coreFreq > CMU_MAX_FREQ_1WS)
250  {
251  mode = (scbtpEn ? MSC_READCTRL_MODE_WS2SCBTP : MSC_READCTRL_MODE_WS2);
252  }
253 #endif
254  else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
255  {
257  }
258  else
259  {
261  }
262 
263 #else /* If MODE and SCBTP is in separate register fields */
264 
265  if (false)
266  {
267  }
268 #if defined( MSC_READCTRL_MODE_WS2 )
269  else if (coreFreq > CMU_MAX_FREQ_1WS)
270  {
271  mode = MSC_READCTRL_MODE_WS2;
272  }
273 #endif
274  else if ((coreFreq <= CMU_MAX_FREQ_1WS) && (coreFreq > CMU_MAX_FREQ_0WS))
275  {
276  mode = MSC_READCTRL_MODE_WS1;
277  }
278  else
279  {
280  mode = MSC_READCTRL_MODE_WS0;
281  }
282 #endif
283 
284  /* BUS_RegMaskedWrite cannot be used here as it would temporarely set the
285  mode field to WS0 */
286  MSC->READCTRL = (MSC->READCTRL &~_MSC_READCTRL_MODE_MASK) | mode;
287 
288  if (mscLocked)
289  {
290  MSC->LOCK = 0;
291  }
292 }
293 
294 
295 /***************************************************************************/
301 static void flashWaitStateMax(void)
302 {
303  flashWaitStateControl(SystemMaxCoreClockGet());
304 }
305 
306 
307 /***************************************************************************/
318 static uint32_t lfClkGet(CMU_Clock_TypeDef lfClkBranch)
319 {
320  uint32_t sel;
321  uint32_t ret = 0;
322 
323  switch (lfClkBranch)
324  {
325  case cmuClock_LFA:
326  case cmuClock_LFB:
327 #if defined( _CMU_LFCCLKEN0_MASK )
328  case cmuClock_LFC:
329 #endif
330 #if defined( _CMU_LFECLKSEL_MASK )
331  case cmuClock_LFE:
332 #endif
333  break;
334 
335  default:
336  EFM_ASSERT(0);
337  break;
338  }
339 
340  sel = CMU_ClockSelectGet(lfClkBranch);
341 
342  /* Get clock select field */
343  switch (lfClkBranch)
344  {
345  case cmuClock_LFA:
346 #if defined( _CMU_LFCLKSEL_MASK )
347  sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK) >> _CMU_LFCLKSEL_LFA_SHIFT;
348 #elif defined( _CMU_LFACLKSEL_MASK )
349  sel = (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK) >> _CMU_LFACLKSEL_LFA_SHIFT;
350 #else
351  EFM_ASSERT(0);
352 #endif
353  break;
354 
355  case cmuClock_LFB:
356 #if defined( _CMU_LFCLKSEL_MASK )
357  sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK) >> _CMU_LFCLKSEL_LFB_SHIFT;
358 #elif defined( _CMU_LFBCLKSEL_MASK )
359  sel = (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK) >> _CMU_LFBCLKSEL_LFB_SHIFT;
360 #else
361  EFM_ASSERT(0);
362 #endif
363  break;
364 
365 #if defined( _CMU_LFCCLKEN0_MASK )
366  case cmuClock_LFC:
367  sel = (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK) >> _CMU_LFCLKSEL_LFC_SHIFT;
368  break;
369 #endif
370 
371 #if defined( _CMU_LFECLKSEL_MASK )
372  case cmuClock_LFE:
373  sel = (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK) >> _CMU_LFECLKSEL_LFE_SHIFT;
374  break;
375 #endif
376 
377  default:
378  EFM_ASSERT(0);
379  break;
380  }
381 
382  /* Get clock frequency */
383 #if defined( _CMU_LFCLKSEL_MASK )
384  switch (sel)
385  {
387  ret = SystemLFRCOClockGet();
388  break;
389 
391  ret = SystemLFXOClockGet();
392  break;
393 
394 #if defined( _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
396 #if defined( CMU_CTRL_HFLE )
397  /* Family which can use an extra div 4 divider */
398  /* (and must if >32MHz) or HFLE is set. */
399  if(((CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK)
400  == CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4)
401  || (CMU->CTRL & CMU_CTRL_HFLE))
402  {
403  ret = SystemCoreClockGet() / 4U;
404  }
405  else
406  {
407  ret = SystemCoreClockGet() / 2U;
408  }
409 #else
410  ret = SystemCoreClockGet() / 2U;
411 #endif
412  break;
413 #endif
414 
416  ret = 0;
417 #if defined( CMU_LFCLKSEL_LFAE )
418  /* Check LF Extended bit setting for LFA or LFB ULFRCO clock */
419  if ((lfClkBranch == cmuClock_LFA) || (lfClkBranch == cmuClock_LFB))
420  {
421  if (CMU->LFCLKSEL >> (lfClkBranch == cmuClock_LFA
422  ? _CMU_LFCLKSEL_LFAE_SHIFT
423  : _CMU_LFCLKSEL_LFBE_SHIFT))
424  {
425  ret = SystemULFRCOClockGet();
426  }
427  }
428 #endif
429  break;
430 
431  default:
432  EFM_ASSERT(0);
433  ret = 0U;
434  break;
435  }
436 #endif /* _CMU_LFCLKSEL_MASK */
437 
438 #if defined( _CMU_LFACLKSEL_MASK )
439  switch (sel)
440  {
441  case _CMU_LFACLKSEL_LFA_LFRCO:
442  ret = SystemLFRCOClockGet();
443  break;
444 
445  case _CMU_LFACLKSEL_LFA_LFXO:
446  ret = SystemLFXOClockGet();
447  break;
448 
449  case _CMU_LFACLKSEL_LFA_ULFRCO:
450  ret = SystemULFRCOClockGet();
451  break;
452 
453 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
454  case _CMU_LFACLKSEL_LFA_HFCLKLE:
455  ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
456  == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
457  ? SystemCoreClockGet() / 4U
458  : SystemCoreClockGet() / 2U;
459  break;
460 #elif defined( _CMU_LFBCLKSEL_LFB_HFCLKLE )
461  case _CMU_LFBCLKSEL_LFB_HFCLKLE:
462  ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
463  == CMU_HFPRESC_HFCLKLEPRESC_DIV4)
464  ? SystemCoreClockGet() / 4U
465  : SystemCoreClockGet() / 2U;
466  break;
467 #endif
468 
469  case _CMU_LFACLKSEL_LFA_DISABLED:
470  ret = 0;
471  break;
472  }
473 #endif
474 
475  return ret;
476 }
477 
478 
479 #if defined( CMU_CTRL_HFLE ) \
480  && !defined( _EFM32_WONDER_FAMILY ) \
481  && !defined( _EZR32_LEOPARD_FAMILY ) \
482  && !defined( _EZR32_WONDER_FAMILY )
483 /***************************************************************************/
487 static uint32_t maxFreqHfle(void)
488 {
489  uint16_t majorMinorRev;
490 
491  switch (SYSTEM_GetFamily())
492  {
494  /* CHIP MAJOR bit [5:0] */
495  majorMinorRev = (((ROMTABLE->PID0 & _ROMTABLE_PID0_REVMAJOR_MASK)
497  /* CHIP MINOR bit [7:4] */
498  majorMinorRev |= (((ROMTABLE->PID2 & _ROMTABLE_PID2_REVMINORMSB_MASK)
500  /* CHIP MINOR bit [3:0] */
501  majorMinorRev |= ((ROMTABLE->PID3 & _ROMTABLE_PID3_REVMINORLSB_MASK)
503 
504  if (majorMinorRev >= 0x0204)
505  return 24000000;
506  else
507  return 32000000;
508 
510  return 32000000;
511 
512  default:
513  /* Invalid device family. */
514  EFM_ASSERT(false);
515  return 0;
516  }
517 }
518 #endif
519 
520 
521 /***************************************************************************/
529 __STATIC_INLINE void syncReg(uint32_t mask)
530 {
531  /* Avoid deadlock if modifying the same register twice when freeze mode is */
532  /* activated. */
533  if (CMU->FREEZE & CMU_FREEZE_REGFREEZE)
534  return;
535 
536  /* Wait for any pending previous write operation to have been completed */
537  /* in low frequency domain */
538  while (CMU->SYNCBUSY & mask)
539  {
540  }
541 }
542 
543 
544 #if defined(USB_PRESENT)
545 /***************************************************************************/
552 static uint32_t usbCClkGet(void)
553 {
554  uint32_t ret;
555  CMU_Select_TypeDef clk;
556 
557  /* Get selected clock source */
558  clk = CMU_ClockSelectGet(cmuClock_USBC);
559 
560  switch(clk)
561  {
562  case cmuSelect_LFXO:
563  ret = SystemLFXOClockGet();
564  break;
565  case cmuSelect_LFRCO:
566  ret = SystemLFRCOClockGet();
567  break;
568  case cmuSelect_HFCLK:
569  ret = SystemHFClockGet();
570  break;
571  default:
572  /* Clock is not enabled */
573  ret = 0;
574  break;
575  }
576  return ret;
577 }
578 #endif
579 
580 
583 /*******************************************************************************
584  ************************** GLOBAL FUNCTIONS *******************************
585  ******************************************************************************/
586 
587 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
588 /***************************************************************************/
595 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
596 {
597  return (CMU_AUXHFRCOBand_TypeDef)((CMU->AUXHFRCOCTRL
598  & _CMU_AUXHFRCOCTRL_BAND_MASK)
599  >> _CMU_AUXHFRCOCTRL_BAND_SHIFT);
600 }
601 #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
602 
603 
604 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
605 /***************************************************************************/
613 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
614 {
615  uint32_t tuning;
616 
617  /* Read tuning value from calibration table */
618  switch (band)
619  {
620  case cmuAUXHFRCOBand_1MHz:
621  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND1_MASK)
622  >> _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT;
623  break;
624 
625  case cmuAUXHFRCOBand_7MHz:
626  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND7_MASK)
627  >> _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT;
628  break;
629 
630  case cmuAUXHFRCOBand_11MHz:
631  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND11_MASK)
632  >> _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT;
633  break;
634 
635  case cmuAUXHFRCOBand_14MHz:
636  tuning = (DEVINFO->AUXHFRCOCAL0 & _DEVINFO_AUXHFRCOCAL0_BAND14_MASK)
637  >> _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT;
638  break;
639 
640  case cmuAUXHFRCOBand_21MHz:
641  tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND21_MASK)
642  >> _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT;
643  break;
644 
645 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
646  case cmuAUXHFRCOBand_28MHz:
647  tuning = (DEVINFO->AUXHFRCOCAL1 & _DEVINFO_AUXHFRCOCAL1_BAND28_MASK)
648  >> _DEVINFO_AUXHFRCOCAL1_BAND28_SHIFT;
649  break;
650 #endif
651 
652  default:
653  EFM_ASSERT(0);
654  return;
655  }
656 
657  /* Set band/tuning */
658  CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL &
659  ~(_CMU_AUXHFRCOCTRL_BAND_MASK
661  | (band << _CMU_AUXHFRCOCTRL_BAND_SHIFT)
662  | (tuning << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
663 
664 }
665 #endif /* _CMU_AUXHFRCOCTRL_BAND_MASK */
666 
667 
668 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
669 /**************************************************************************/
679 static uint32_t CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)
680 {
681  switch (freq)
682  {
683  /* 1, 2 and 4MHz share the same calibration word */
684  case cmuAUXHFRCOFreq_1M0Hz:
685  case cmuAUXHFRCOFreq_2M0Hz:
686  case cmuAUXHFRCOFreq_4M0Hz:
687  return DEVINFO->AUXHFRCOCAL0;
688 
689  case cmuAUXHFRCOFreq_7M0Hz:
690  return DEVINFO->AUXHFRCOCAL3;
691 
692  case cmuAUXHFRCOFreq_13M0Hz:
693  return DEVINFO->AUXHFRCOCAL6;
694 
695  case cmuAUXHFRCOFreq_16M0Hz:
696  return DEVINFO->AUXHFRCOCAL7;
697 
698  case cmuAUXHFRCOFreq_19M0Hz:
699  return DEVINFO->AUXHFRCOCAL8;
700 
701  case cmuAUXHFRCOFreq_26M0Hz:
702  return DEVINFO->AUXHFRCOCAL10;
703 
704  case cmuAUXHFRCOFreq_32M0Hz:
705  return DEVINFO->AUXHFRCOCAL11;
706 
707  case cmuAUXHFRCOFreq_38M0Hz:
708  return DEVINFO->AUXHFRCOCAL12;
709 
710  default: /* cmuAUXHFRCOFreq_UserDefined */
711  return 0;
712  }
713 }
714 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
715 
716 
717 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
718 /***************************************************************************/
725 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(void)
726 {
727  return auxHfrcoFreq;
728 }
729 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
730 
731 
732 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
733 /***************************************************************************/
740 void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freq)
741 {
742  uint32_t freqCal;
743 
744  /* Get DEVINFO index, set global auxHfrcoFreq */
745  freqCal = CMU_AUXHFRCODevinfoGet(freq);
746  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
747  auxHfrcoFreq = freq;
748 
749  /* Wait for any previous sync to complete, and then set calibration data
750  for the selected frequency. */
751  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT));
752 
753  /* Set divider in AUXHFRCOCTRL for 1, 2 and 4MHz */
754  switch(freq)
755  {
756  case cmuAUXHFRCOFreq_1M0Hz:
757  freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
758  | CMU_AUXHFRCOCTRL_CLKDIV_DIV4;
759  break;
760 
761  case cmuAUXHFRCOFreq_2M0Hz:
762  freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
763  | CMU_AUXHFRCOCTRL_CLKDIV_DIV2;
764  break;
765 
766  case cmuAUXHFRCOFreq_4M0Hz:
767  freqCal = (freqCal & ~_CMU_AUXHFRCOCTRL_CLKDIV_MASK)
768  | CMU_AUXHFRCOCTRL_CLKDIV_DIV1;
769  break;
770 
771  default:
772  break;
773  }
774  CMU->AUXHFRCOCTRL = freqCal;
775 }
776 #endif /* _CMU_AUXHFRCOCTRL_FREQRANGE_MASK */
777 
778 
779 /***************************************************************************/
801 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef ref)
802 {
803  EFM_ASSERT(HFCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
804 
805  /* Set reference clock source */
806  switch (ref)
807  {
808  case cmuOsc_LFXO:
809  CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFXO;
810  break;
811 
812  case cmuOsc_LFRCO:
813  CMU->CALCTRL = CMU_CALCTRL_UPSEL_LFRCO;
814  break;
815 
816  case cmuOsc_HFXO:
817  CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFXO;
818  break;
819 
820  case cmuOsc_HFRCO:
821  CMU->CALCTRL = CMU_CALCTRL_UPSEL_HFRCO;
822  break;
823 
824  case cmuOsc_AUXHFRCO:
825  CMU->CALCTRL = CMU_CALCTRL_UPSEL_AUXHFRCO;
826  break;
827 
828  default:
829  EFM_ASSERT(0);
830  return 0;
831  }
832 
833  /* Set top value */
834  CMU->CALCNT = HFCycles;
835 
836  /* Start calibration */
837  CMU->CMD = CMU_CMD_CALSTART;
838 
839 #if defined( CMU_STATUS_CALRDY )
840  /* Wait until calibration completes */
841  while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
842  {
843  }
844 #else
845  /* Wait until calibration completes */
846  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
847  {
848  }
849 #endif
850 
851  return CMU->CALCNT;
852 }
853 
854 
855 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
856 /***************************************************************************/
882 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
883  CMU_Osc_TypeDef upSel)
884 {
885  /* Keep untouched configuration settings */
886  uint32_t calCtrl = CMU->CALCTRL
887  & ~(_CMU_CALCTRL_UPSEL_MASK | _CMU_CALCTRL_DOWNSEL_MASK);
888 
889  /* 20 bits of precision to calibration count register */
890  EFM_ASSERT(downCycles <= (_CMU_CALCNT_CALCNT_MASK >> _CMU_CALCNT_CALCNT_SHIFT));
891 
892  /* Set down counting clock source - down counter */
893  switch (downSel)
894  {
895  case cmuOsc_LFXO:
896  calCtrl |= CMU_CALCTRL_DOWNSEL_LFXO;
897  break;
898 
899  case cmuOsc_LFRCO:
900  calCtrl |= CMU_CALCTRL_DOWNSEL_LFRCO;
901  break;
902 
903  case cmuOsc_HFXO:
904  calCtrl |= CMU_CALCTRL_DOWNSEL_HFXO;
905  break;
906 
907  case cmuOsc_HFRCO:
908  calCtrl |= CMU_CALCTRL_DOWNSEL_HFRCO;
909  break;
910 
911  case cmuOsc_AUXHFRCO:
912  calCtrl |= CMU_CALCTRL_DOWNSEL_AUXHFRCO;
913  break;
914 
915  default:
916  EFM_ASSERT(0);
917  break;
918  }
919 
920  /* Set top value to be counted down by the downSel clock */
921  CMU->CALCNT = downCycles;
922 
923  /* Set reference clock source - up counter */
924  switch (upSel)
925  {
926  case cmuOsc_LFXO:
927  calCtrl |= CMU_CALCTRL_UPSEL_LFXO;
928  break;
929 
930  case cmuOsc_LFRCO:
931  calCtrl |= CMU_CALCTRL_UPSEL_LFRCO;
932  break;
933 
934  case cmuOsc_HFXO:
935  calCtrl |= CMU_CALCTRL_UPSEL_HFXO;
936  break;
937 
938  case cmuOsc_HFRCO:
939  calCtrl |= CMU_CALCTRL_UPSEL_HFRCO;
940  break;
941 
942  case cmuOsc_AUXHFRCO:
943  calCtrl |= CMU_CALCTRL_UPSEL_AUXHFRCO;
944  break;
945 
946  default:
947  EFM_ASSERT(0);
948  break;
949  }
950 
951  CMU->CALCTRL = calCtrl;
952 }
953 #endif
954 
955 
956 /***************************************************************************/
969 uint32_t CMU_CalibrateCountGet(void)
970 {
971  /* Wait until calibration completes, UNLESS continuous calibration mode is */
972  /* active */
973 #if defined( CMU_CALCTRL_CONT )
974  if (!BUS_RegBitRead(&CMU->CALCTRL, _CMU_CALCTRL_CONT_SHIFT))
975  {
976 #if defined( CMU_STATUS_CALRDY )
977  /* Wait until calibration completes */
978  while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALRDY_SHIFT))
979  {
980  }
981 #else
982  /* Wait until calibration completes */
983  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
984  {
985  }
986 #endif
987  }
988 #else
989  while (BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_CALBSY_SHIFT))
990  {
991  }
992 #endif
993  return CMU->CALCNT;
994 }
995 
996 
997 /***************************************************************************/
1010 {
1011 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1012  return 1 + (uint32_t)CMU_ClockPrescGet(clock);
1013 
1014 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
1015  uint32_t divReg;
1016  CMU_ClkDiv_TypeDef ret;
1017 
1018  /* Get divisor reg id */
1019  divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1020 
1021  switch (divReg)
1022  {
1023 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1024  case CMU_HFCLKDIV_REG:
1025  ret = 1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1026  >> _CMU_CTRL_HFCLKDIV_SHIFT);
1027  break;
1028 #endif
1029 
1030  case CMU_HFPERCLKDIV_REG:
1031  ret = (CMU_ClkDiv_TypeDef)((CMU->HFPERCLKDIV
1034  ret = CMU_Log2ToDiv(ret);
1035  break;
1036 
1037  case CMU_HFCORECLKDIV_REG:
1038  ret = (CMU_ClkDiv_TypeDef)((CMU->HFCORECLKDIV
1041  ret = CMU_Log2ToDiv(ret);
1042  break;
1043 
1044  case CMU_LFAPRESC0_REG:
1045  switch (clock)
1046  {
1047  case cmuClock_RTC:
1048  ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
1050  ret = CMU_Log2ToDiv(ret);
1051  break;
1052 
1053 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1054  case cmuClock_LETIMER0:
1055  ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1057  ret = CMU_Log2ToDiv(ret);
1058  break;
1059 #endif
1060 
1061 #if defined(_CMU_LFAPRESC0_LCD_MASK)
1062  case cmuClock_LCDpre:
1063  ret = (CMU_ClkDiv_TypeDef)(((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1066  ret = CMU_Log2ToDiv(ret);
1067  break;
1068 #endif
1069 
1070 #if defined(_CMU_LFAPRESC0_LESENSE_MASK)
1071  case cmuClock_LESENSE:
1072  ret = (CMU_ClkDiv_TypeDef)((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1073  >> _CMU_LFAPRESC0_LESENSE_SHIFT);
1074  ret = CMU_Log2ToDiv(ret);
1075  break;
1076 #endif
1077 
1078  default:
1079  EFM_ASSERT(0);
1080  ret = cmuClkDiv_1;
1081  break;
1082  }
1083  break;
1084 
1085  case CMU_LFBPRESC0_REG:
1086  switch (clock)
1087  {
1088 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1089  case cmuClock_LEUART0:
1090  ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1092  ret = CMU_Log2ToDiv(ret);
1093  break;
1094 #endif
1095 
1096 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1097  case cmuClock_LEUART1:
1098  ret = (CMU_ClkDiv_TypeDef)((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1100  ret = CMU_Log2ToDiv(ret);
1101  break;
1102 #endif
1103 
1104  default:
1105  EFM_ASSERT(0);
1106  ret = cmuClkDiv_1;
1107  break;
1108  }
1109  break;
1110 
1111  default:
1112  EFM_ASSERT(0);
1113  ret = cmuClkDiv_1;
1114  break;
1115  }
1116 
1117  return ret;
1118 #endif
1119 }
1120 
1121 
1122 /***************************************************************************/
1142 {
1143 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1144  CMU_ClockPrescSet(clock, (CMU_ClkPresc_TypeDef)(div - 1));
1145 
1146 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
1147  uint32_t freq;
1148  uint32_t divReg;
1149 
1150  /* Get divisor reg id */
1151  divReg = (clock >> CMU_DIV_REG_POS) & CMU_DIV_REG_MASK;
1152 
1153  switch (divReg)
1154  {
1155 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1156  case CMU_HFCLKDIV_REG:
1157  EFM_ASSERT((div>=cmuClkDiv_1) && (div<=cmuClkDiv_8));
1158 
1159  /* Configure worst case wait states for flash access before setting divisor */
1160  flashWaitStateMax();
1161 
1162  /* Set divider */
1163  CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFCLKDIV_MASK)
1164  | ((div-1) << _CMU_CTRL_HFCLKDIV_SHIFT);
1165 
1166  /* Update CMSIS core clock variable */
1167  /* (The function will update the global variable) */
1168  freq = SystemCoreClockGet();
1169 
1170  /* Optimize flash access wait state setting for current core clk */
1171  flashWaitStateControl(freq);
1172  break;
1173 #endif
1174 
1175  case CMU_HFPERCLKDIV_REG:
1176  EFM_ASSERT((div >= cmuClkDiv_1) && (div <= cmuClkDiv_512));
1177  /* Convert to correct scale */
1178  div = CMU_DivToLog2(div);
1179  CMU->HFPERCLKDIV = (CMU->HFPERCLKDIV & ~_CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1181  break;
1182 
1183  case CMU_HFCORECLKDIV_REG:
1184  EFM_ASSERT(div <= cmuClkDiv_512);
1185 
1186  /* Configure worst case wait states for flash access before setting divisor */
1187  flashWaitStateMax();
1188 
1189 #if defined( CMU_CTRL_HFLE )
1190  /* Clear HFLE and set DIV2 factor for peripheral clock
1191  when running at frequencies lower than or equal to CMU_MAX_FREQ_HFLE. */
1192  if ((CMU_ClockFreqGet(cmuClock_HF) / div) <= CMU_MAX_FREQ_HFLE())
1193  {
1194  /* Clear CMU HFLE */
1195  BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 0);
1196 
1197  /* Set DIV2 factor for peripheral clock */
1198  BUS_RegBitWrite(&CMU->HFCORECLKDIV,
1199  _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 0);
1200  }
1201  else
1202  {
1203  /* Set CMU HFLE */
1204  BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
1205 
1206  /* Set DIV4 factor for peripheral clock */
1207  BUS_RegBitWrite(&CMU->HFCORECLKDIV,
1208  _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
1209  }
1210 #endif
1211 
1212  /* Convert to correct scale */
1213  div = CMU_DivToLog2(div);
1214 
1215  CMU->HFCORECLKDIV = (CMU->HFCORECLKDIV
1218 
1219  /* Update CMSIS core clock variable */
1220  /* (The function will update the global variable) */
1221  freq = SystemCoreClockGet();
1222 
1223  /* Optimize flash access wait state setting for current core clk */
1224  flashWaitStateControl(freq);
1225  break;
1226 
1227  case CMU_LFAPRESC0_REG:
1228  switch (clock)
1229  {
1230  case cmuClock_RTC:
1231  EFM_ASSERT(div <= cmuClkDiv_32768);
1232 
1233  /* LF register about to be modified require sync. busy check */
1234  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1235 
1236  /* Convert to correct scale */
1237  div = CMU_DivToLog2(div);
1238 
1239  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
1240  | (div << _CMU_LFAPRESC0_RTC_SHIFT);
1241  break;
1242 
1243 #if defined(_CMU_LFAPRESC0_LETIMER0_MASK)
1244  case cmuClock_LETIMER0:
1245  EFM_ASSERT(div <= cmuClkDiv_32768);
1246 
1247  /* LF register about to be modified require sync. busy check */
1248  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1249 
1250  /* Convert to correct scale */
1251  div = CMU_DivToLog2(div);
1252 
1253  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
1254  | (div << _CMU_LFAPRESC0_LETIMER0_SHIFT);
1255  break;
1256 #endif
1257 
1258 #if defined(LCD_PRESENT)
1259  case cmuClock_LCDpre:
1260  EFM_ASSERT((div >= cmuClkDiv_16) && (div <= cmuClkDiv_128));
1261 
1262  /* LF register about to be modified require sync. busy check */
1263  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1264 
1265  /* Convert to correct scale */
1266  div = CMU_DivToLog2(div);
1267 
1268  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LCD_MASK)
1269  | ((div - CMU_DivToLog2(cmuClkDiv_16))
1271  break;
1272 #endif /* defined(LCD_PRESENT) */
1273 
1274 #if defined(LESENSE_PRESENT)
1275  case cmuClock_LESENSE:
1276  EFM_ASSERT(div <= cmuClkDiv_8);
1277 
1278  /* LF register about to be modified require sync. busy check */
1279  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1280 
1281  /* Convert to correct scale */
1282  div = CMU_DivToLog2(div);
1283 
1284  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LESENSE_MASK)
1285  | (div << _CMU_LFAPRESC0_LESENSE_SHIFT);
1286  break;
1287 #endif /* defined(LESENSE_PRESENT) */
1288 
1289  default:
1290  EFM_ASSERT(0);
1291  break;
1292  }
1293  break;
1294 
1295  case CMU_LFBPRESC0_REG:
1296  switch (clock)
1297  {
1298 #if defined(_CMU_LFBPRESC0_LEUART0_MASK)
1299  case cmuClock_LEUART0:
1300  EFM_ASSERT(div <= cmuClkDiv_8);
1301 
1302  /* LF register about to be modified require sync. busy check */
1303  syncReg(CMU_SYNCBUSY_LFBPRESC0);
1304 
1305  /* Convert to correct scale */
1306  div = CMU_DivToLog2(div);
1307 
1308  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
1309  | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART0_SHIFT);
1310  break;
1311 #endif
1312 
1313 #if defined(_CMU_LFBPRESC0_LEUART1_MASK)
1314  case cmuClock_LEUART1:
1315  EFM_ASSERT(div <= cmuClkDiv_8);
1316 
1317  /* LF register about to be modified require sync. busy check */
1318  syncReg(CMU_SYNCBUSY_LFBPRESC0);
1319 
1320  /* Convert to correct scale */
1321  div = CMU_DivToLog2(div);
1322 
1323  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
1324  | (((uint32_t)div) << _CMU_LFBPRESC0_LEUART1_SHIFT);
1325  break;
1326 #endif
1327 
1328  default:
1329  EFM_ASSERT(0);
1330  break;
1331  }
1332  break;
1333 
1334  default:
1335  EFM_ASSERT(0);
1336  break;
1337  }
1338 #endif
1339 }
1340 
1341 
1342 /***************************************************************************/
1369 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
1370 {
1371  volatile uint32_t *reg;
1372  uint32_t bit;
1373  uint32_t sync = 0;
1374 
1375  /* Identify enable register */
1376  switch ((clock >> CMU_EN_REG_POS) & CMU_EN_REG_MASK)
1377  {
1378 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1379  case CMU_CTRL_EN_REG:
1380  reg = &CMU->CTRL;
1381  break;
1382 #endif
1383 
1384 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1385  case CMU_HFCORECLKEN0_EN_REG:
1386  reg = &CMU->HFCORECLKEN0;
1387 #if defined( CMU_CTRL_HFLE )
1388  /* Set HFLE and DIV4 factor for peripheral clock when
1389  running at frequencies higher than or equal to CMU_MAX_FREQ_HFLE. */
1390  if ( CMU_ClockFreqGet(cmuClock_CORE) > CMU_MAX_FREQ_HFLE())
1391  {
1392  /* Enable CMU HFLE */
1393  BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
1394 
1395  /* Set DIV4 factor for peripheral clock */
1396  BUS_RegBitWrite(&CMU->HFCORECLKDIV,
1397  _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
1398  }
1399 #endif
1400  break;
1401 #endif
1402 
1403 #if defined( _CMU_HFBUSCLKEN0_MASK )
1404  case CMU_HFBUSCLKEN0_EN_REG:
1405  reg = &CMU->HFBUSCLKEN0;
1406  break;
1407 #endif
1408 
1409 #if defined( _CMU_HFRADIOCLKEN0_MASK )
1410  case CMU_HFRADIOCLKEN0_EN_REG:
1411  reg = &CMU->HFRADIOCLKEN0;
1412  break;
1413 #endif
1414 
1415 #if defined( _CMU_HFPERCLKDIV_MASK )
1416  case CMU_HFPERCLKDIV_EN_REG:
1417  reg = &CMU->HFPERCLKDIV;
1418  break;
1419 #endif
1420 
1421  case CMU_HFPERCLKEN0_EN_REG:
1422  reg = &CMU->HFPERCLKEN0;
1423  break;
1424 
1425  case CMU_LFACLKEN0_EN_REG:
1426  reg = &CMU->LFACLKEN0;
1427  sync = CMU_SYNCBUSY_LFACLKEN0;
1428  break;
1429 
1430  case CMU_LFBCLKEN0_EN_REG:
1431  reg = &CMU->LFBCLKEN0;
1432  sync = CMU_SYNCBUSY_LFBCLKEN0;
1433  break;
1434 
1435 #if defined( _CMU_LFCCLKEN0_MASK )
1436  case CMU_LFCCLKEN0_EN_REG:
1437  reg = &CMU->LFCCLKEN0;
1438  sync = CMU_SYNCBUSY_LFCCLKEN0;
1439  break;
1440 #endif
1441 
1442 #if defined( _CMU_LFECLKEN0_MASK )
1443  case CMU_LFECLKEN0_EN_REG:
1444  reg = &CMU->LFECLKEN0;
1445  sync = CMU_SYNCBUSY_LFECLKEN0;
1446  break;
1447 #endif
1448 
1449  case CMU_PCNT_EN_REG:
1450  reg = &CMU->PCNTCTRL;
1451  break;
1452 
1453  default: /* Cannot enable/disable clock point */
1454  EFM_ASSERT(0);
1455  return;
1456  }
1457 
1458  /* Get bit position used to enable/disable */
1459  bit = (clock >> CMU_EN_BIT_POS) & CMU_EN_BIT_MASK;
1460 
1461  /* LF synchronization required? */
1462  if (sync)
1463  {
1464  syncReg(sync);
1465  }
1466 
1467  /* Set/clear bit as requested */
1468  BUS_RegBitWrite(reg, bit, enable);
1469 }
1470 
1471 
1472 /***************************************************************************/
1483 {
1484  uint32_t ret;
1485 
1486  switch(clock & (CMU_CLK_BRANCH_MASK << CMU_CLK_BRANCH_POS))
1487  {
1488  case (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1489  ret = SystemHFClockGet();
1490 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1491  /* Family with an additional divider. */
1492  ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1493  >> _CMU_CTRL_HFCLKDIV_SHIFT));
1494 #endif
1495 #if defined( _CMU_HFPRESC_MASK )
1496  ret = ret / (1U + ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
1497  >> _CMU_HFPRESC_PRESC_SHIFT));
1498 #endif
1499  break;
1500 
1501  case (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1502  ret = SystemHFClockGet();
1503 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1504 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
1505  /* Family with an additional divider. */
1506  ret = ret / (1U + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)
1507  >> _CMU_CTRL_HFCLKDIV_SHIFT));
1508 #endif
1509  ret >>= (CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK)
1511 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1512  ret /= 1U + ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
1513  >> _CMU_HFPERPRESC_PRESC_SHIFT);
1514 #endif
1515  break;
1516 
1517 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1518 #if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
1519  case (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1520  ret = SystemHFClockGet();
1521  ret /= 1U + ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
1522  >> _CMU_HFRADIOPRESC_PRESC_SHIFT);
1523  break;
1524 #endif
1525 
1526 #if defined( CRYPTO_PRESENT ) \
1527  || defined( LDMA_PRESENT ) \
1528  || defined( GPCRC_PRESENT ) \
1529  || defined( PRS_PRESENT ) \
1530  || defined( GPIO_PRESENT )
1531  case (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1532  ret = SystemHFClockGet();
1533  break;
1534 #endif
1535 
1536  case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1537  ret = SystemHFClockGet();
1538  ret /= 1U + ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
1539  >> _CMU_HFCOREPRESC_PRESC_SHIFT);
1540  break;
1541 
1542  case (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1543  ret = SystemHFClockGet();
1544  ret /= 1U + ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
1545  >> _CMU_HFEXPPRESC_PRESC_SHIFT);
1546  break;
1547 #endif
1548 
1549 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1550 #if defined(AES_PRESENT) \
1551  || defined(DMA_PRESENT) \
1552  || defined(EBI_PRESENT) \
1553  || defined(USB_PRESENT)
1554  case (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1555  {
1556  ret = SystemCoreClockGet();
1557  } break;
1558 #endif
1559 #endif
1560 
1561  case (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1562  ret = lfClkGet(cmuClock_LFA);
1563  break;
1564 
1565 #if defined( _CMU_LFACLKEN0_RTC_MASK )
1566  case (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1567  ret = lfClkGet(cmuClock_LFA);
1568  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_RTC_MASK)
1570  break;
1571 #endif
1572 
1573 #if defined( _CMU_LFECLKEN0_RTCC_MASK )
1574  case (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1575  ret = lfClkGet(cmuClock_LFE);
1576  break;
1577 #endif
1578 
1579 #if defined( _CMU_LFACLKEN0_LETIMER0_MASK )
1580  case (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1581  ret = lfClkGet(cmuClock_LFA);
1582 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1583  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1585 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1586  ret /= CMU_Log2ToDiv((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1588 #endif
1589  break;
1590 #endif
1591 
1592 #if defined(_CMU_LFACLKEN0_LCD_MASK)
1593  case (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1594  ret = lfClkGet(cmuClock_LFA);
1595  ret >>= ((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1598  break;
1599 
1600  case (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1601  ret = lfClkGet(cmuClock_LFA);
1602  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LCD_MASK)
1604  ret /= 1U + ((CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK)
1606  break;
1607 #endif
1608 
1609 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
1610  case (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1611  ret = lfClkGet(cmuClock_LFA);
1612  ret >>= (CMU->LFAPRESC0 & _CMU_LFAPRESC0_LESENSE_MASK)
1613  >> _CMU_LFAPRESC0_LESENSE_SHIFT;
1614  break;
1615 #endif
1616 
1617  case (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1618  ret = lfClkGet(cmuClock_LFB);
1619  break;
1620 
1621 #if defined( _CMU_LFBCLKEN0_LEUART0_MASK )
1622  case (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1623  ret = lfClkGet(cmuClock_LFB);
1624 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1625  ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1627 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1628  ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1630 #endif
1631  break;
1632 #endif
1633 
1634 #if defined( _CMU_LFBCLKEN0_LEUART1_MASK )
1635  case (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1636  ret = lfClkGet(cmuClock_LFB);
1637 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
1638  ret >>= (CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1640 #elif defined( _SILICON_LABS_32B_PLATFORM_2 )
1641  ret /= CMU_Log2ToDiv((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1643 #endif
1644  break;
1645 #endif
1646 
1647 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1648  case (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1649  ret = lfClkGet(cmuClock_LFE);
1650  break;
1651 #endif
1652 
1653  case (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1654  ret = dbgClkGet();
1655  break;
1656 
1657  case (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1658  ret = auxClkGet();
1659  break;
1660 
1661 #if defined(USB_PRESENT)
1662  case (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS):
1663  ret = usbCClkGet();
1664  break;
1665 #endif
1666 
1667  default:
1668  EFM_ASSERT(0);
1669  ret = 0;
1670  break;
1671  }
1672 
1673  return ret;
1674 }
1675 
1676 
1677 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1678 /***************************************************************************/
1690 uint32_t CMU_ClockPrescGet(CMU_Clock_TypeDef clock)
1691 {
1692  uint32_t prescReg;
1693  uint32_t ret;
1694 
1695  /* Get prescaler register id. */
1696  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1697 
1698  switch (prescReg)
1699  {
1700  case CMU_HFPRESC_REG:
1701  ret = ((CMU->HFPRESC & _CMU_HFPRESC_PRESC_MASK)
1702  >> _CMU_HFPRESC_PRESC_SHIFT);
1703  break;
1704 
1705  case CMU_HFEXPPRESC_REG:
1706  ret = ((CMU->HFEXPPRESC & _CMU_HFEXPPRESC_PRESC_MASK)
1707  >> _CMU_HFEXPPRESC_PRESC_SHIFT);
1708  break;
1709 
1710  case CMU_HFCLKLEPRESC_REG:
1711  ret = ((CMU->HFPRESC & _CMU_HFPRESC_HFCLKLEPRESC_MASK)
1712  >> _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
1713  break;
1714 
1715  case CMU_HFPERPRESC_REG:
1716  ret = ((CMU->HFPERPRESC & _CMU_HFPERPRESC_PRESC_MASK)
1717  >> _CMU_HFPERPRESC_PRESC_SHIFT);
1718  break;
1719 
1720 #if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
1721  case CMU_HFRADIOPRESC_REG:
1722  ret = ((CMU->HFRADIOPRESC & _CMU_HFRADIOPRESC_PRESC_MASK)
1723  >> _CMU_HFRADIOPRESC_PRESC_SHIFT);
1724  break;
1725 #endif
1726 
1727  case CMU_HFCOREPRESC_REG:
1728  ret = ((CMU->HFCOREPRESC & _CMU_HFCOREPRESC_PRESC_MASK)
1729  >> _CMU_HFCOREPRESC_PRESC_SHIFT);
1730  break;
1731 
1732  case CMU_LFAPRESC0_REG:
1733  switch (clock)
1734  {
1735 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
1736  case cmuClock_LETIMER0:
1737  ret = (((CMU->LFAPRESC0 & _CMU_LFAPRESC0_LETIMER0_MASK)
1739  /* Convert the exponent to prescaler value. */
1740  ret = CMU_Log2ToDiv(ret) - 1U;
1741  break;
1742 #endif
1743 
1744  default:
1745  EFM_ASSERT(0);
1746  ret = 0U;
1747  break;
1748  }
1749  break;
1750 
1751  case CMU_LFBPRESC0_REG:
1752  switch (clock)
1753  {
1754 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
1755  case cmuClock_LEUART0:
1756  ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART0_MASK)
1758  /* Convert the exponent to prescaler value. */
1759  ret = CMU_Log2ToDiv(ret) - 1U;
1760  break;
1761 #endif
1762 
1763 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
1764  case cmuClock_LEUART1:
1765  ret = (((CMU->LFBPRESC0 & _CMU_LFBPRESC0_LEUART1_MASK)
1767  /* Convert the exponent to prescaler value. */
1768  ret = CMU_Log2ToDiv(ret) - 1U;
1769  break;
1770 #endif
1771 
1772  default:
1773  EFM_ASSERT(0);
1774  ret = 0U;
1775  break;
1776  }
1777  break;
1778 
1779  case CMU_LFEPRESC0_REG:
1780  switch (clock)
1781  {
1782 #if defined( RTCC_PRESENT )
1783  case cmuClock_RTCC:
1784  /* No need to compute with LFEPRESC0_RTCC - DIV1 is the only */
1785  /* allowed value. Convert the exponent to prescaler value. */
1786  ret = _CMU_LFEPRESC0_RTCC_DIV1;
1787  break;
1788 
1789  default:
1790  EFM_ASSERT(0);
1791  ret = 0U;
1792  break;
1793 #endif
1794  }
1795  break;
1796 
1797  default:
1798  EFM_ASSERT(0);
1799  ret = 0U;
1800  break;
1801  }
1802 
1803  return ret;
1804 }
1805 #endif
1806 
1807 
1808 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1809 /***************************************************************************/
1827 void CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)
1828 {
1829  uint32_t freq;
1830  uint32_t prescReg;
1831 
1832  /* Get divisor reg id */
1833  prescReg = (clock >> CMU_PRESC_REG_POS) & CMU_PRESC_REG_MASK;
1834 
1835  switch (prescReg)
1836  {
1837  case CMU_HFPRESC_REG:
1838  EFM_ASSERT(presc < 32U);
1839 
1840  CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_PRESC_MASK)
1841  | (presc << _CMU_HFPRESC_PRESC_SHIFT);
1842  break;
1843 
1844  case CMU_HFEXPPRESC_REG:
1845  EFM_ASSERT(presc < 32U);
1846 
1847  CMU->HFEXPPRESC = (CMU->HFEXPPRESC & ~_CMU_HFEXPPRESC_PRESC_MASK)
1848  | (presc << _CMU_HFEXPPRESC_PRESC_SHIFT);
1849  break;
1850 
1851  case CMU_HFCLKLEPRESC_REG:
1852  EFM_ASSERT(presc < 2U);
1853 
1854  /* Specifies the clock divider for HFCLKLE. When running at frequencies
1855  * higher than 32 MHz, this must be set to DIV4. */
1856  CMU->HFPRESC = (CMU->HFPRESC & ~_CMU_HFPRESC_HFCLKLEPRESC_MASK)
1857  | (presc << _CMU_HFPRESC_HFCLKLEPRESC_SHIFT);
1858  break;
1859 
1860  case CMU_HFPERPRESC_REG:
1861  EFM_ASSERT(presc < 512U);
1862 
1863  CMU->HFPERPRESC = (CMU->HFPERPRESC & ~_CMU_HFPERPRESC_PRESC_MASK)
1864  | (presc << _CMU_HFPERPRESC_PRESC_SHIFT);
1865  break;
1866 
1867 #if defined( _CMU_HFRADIOPRESC_PRESC_MASK )
1868  case CMU_HFRADIOPRESC_REG:
1869  EFM_ASSERT(presc < 512U);
1870 
1871  CMU->HFRADIOPRESC = (CMU->HFRADIOPRESC & ~_CMU_HFRADIOPRESC_PRESC_MASK)
1872  | (presc << _CMU_HFRADIOPRESC_PRESC_SHIFT);
1873  break;
1874 #endif
1875 
1876  case CMU_HFCOREPRESC_REG:
1877  EFM_ASSERT(presc < 512U);
1878 
1879  /* Configure worst case wait states for flash access before setting
1880  * the prescaler. */
1881  flashWaitStateControl(CMU_MAX_FREQ_0WS + 1);
1882 
1883  CMU->HFCOREPRESC = (CMU->HFCOREPRESC & ~_CMU_HFCOREPRESC_PRESC_MASK)
1884  | (presc << _CMU_HFCOREPRESC_PRESC_SHIFT);
1885 
1886  /* Update CMSIS core clock variable */
1887  /* (The function will update the global variable) */
1888  freq = SystemCoreClockGet();
1889 
1890  /* Optimize flash access wait state setting for current core clk */
1891  flashWaitStateControl(freq);
1892  break;
1893 
1894  case CMU_LFAPRESC0_REG:
1895  switch (clock)
1896  {
1897 #if defined( RTC_PRESENT )
1898  case cmuClock_RTC:
1899  EFM_ASSERT(presc <= 32768U);
1900 
1901  /* Convert prescaler value to DIV exponent scale. */
1902  presc = CMU_PrescToLog2(presc);
1903 
1904  /* LF register about to be modified require sync. Busy check. */
1905  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1906 
1907  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTC_MASK)
1908  | (presc << _CMU_LFAPRESC0_RTC_SHIFT);
1909  break;
1910 #endif
1911 
1912 #if defined( RTCC_PRESENT )
1913  case cmuClock_RTCC:
1914 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
1915  /* DIV1 is the only accepted value. */
1916  EFM_ASSERT(presc <= 0U);
1917 
1918  /* LF register about to be modified require sync. Busy check.. */
1919  syncReg(CMU_SYNCBUSY_LFEPRESC0);
1920 
1921  CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
1922  | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
1923 #else
1924  EFM_ASSERT(presc <= 32768U);
1925 
1926  /* Convert prescaler value to DIV exponent scale. */
1927  presc = CMU_PrescToLog2(presc);
1928 
1929  /* LF register about to be modified require sync. Busy check. */
1930  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1931 
1932  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_RTCC_MASK)
1933  | (presc << _CMU_LFAPRESC0_RTCC_SHIFT);
1934 #endif
1935  break;
1936 #endif
1937 
1938 #if defined( _CMU_LFAPRESC0_LETIMER0_MASK )
1939  case cmuClock_LETIMER0:
1940  EFM_ASSERT(presc <= 32768U);
1941 
1942  /* Convert prescaler value to DIV exponent scale. */
1943  presc = CMU_PrescToLog2(presc);
1944 
1945  /* LF register about to be modified require sync. Busy check. */
1946  syncReg(CMU_SYNCBUSY_LFAPRESC0);
1947 
1948  CMU->LFAPRESC0 = (CMU->LFAPRESC0 & ~_CMU_LFAPRESC0_LETIMER0_MASK)
1949  | (presc << _CMU_LFAPRESC0_LETIMER0_SHIFT);
1950  break;
1951 #endif
1952 
1953  default:
1954  EFM_ASSERT(0);
1955  break;
1956  }
1957  break;
1958 
1959  case CMU_LFBPRESC0_REG:
1960  switch (clock)
1961  {
1962 #if defined( _CMU_LFBPRESC0_LEUART0_MASK )
1963  case cmuClock_LEUART0:
1964  EFM_ASSERT(presc <= 8U);
1965 
1966  /* Convert prescaler value to DIV exponent scale. */
1967  presc = CMU_PrescToLog2(presc);
1968 
1969  /* LF register about to be modified require sync. Busy check. */
1970  syncReg(CMU_SYNCBUSY_LFBPRESC0);
1971 
1972  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART0_MASK)
1973  | (presc << _CMU_LFBPRESC0_LEUART0_SHIFT);
1974  break;
1975 #endif
1976 
1977 #if defined( _CMU_LFBPRESC0_LEUART1_MASK )
1978  case cmuClock_LEUART1:
1979  EFM_ASSERT(presc <= 8U);
1980 
1981  /* Convert prescaler value to DIV exponent scale. */
1982  presc = CMU_PrescToLog2(presc);
1983 
1984  /* LF register about to be modified require sync. Busy check. */
1985  syncReg(CMU_SYNCBUSY_LFBPRESC0);
1986 
1987  CMU->LFBPRESC0 = (CMU->LFBPRESC0 & ~_CMU_LFBPRESC0_LEUART1_MASK)
1988  | (presc << _CMU_LFBPRESC0_LEUART1_SHIFT);
1989  break;
1990 #endif
1991 
1992  default:
1993  EFM_ASSERT(0);
1994  break;
1995  }
1996  break;
1997 
1998  case CMU_LFEPRESC0_REG:
1999  switch (clock)
2000  {
2001 #if defined( _CMU_LFEPRESC0_RTCC_MASK )
2002  case cmuClock_RTCC:
2003  EFM_ASSERT(presc <= 0U);
2004 
2005  /* LF register about to be modified require sync. Busy check. */
2006  syncReg(CMU_SYNCBUSY_LFEPRESC0);
2007 
2008  CMU->LFEPRESC0 = (CMU->LFEPRESC0 & ~_CMU_LFEPRESC0_RTCC_MASK)
2009  | (presc << _CMU_LFEPRESC0_RTCC_SHIFT);
2010  break;
2011 #endif
2012 
2013  default:
2014  EFM_ASSERT(0);
2015  break;
2016  }
2017  break;
2018 
2019  default:
2020  EFM_ASSERT(0);
2021  break;
2022  }
2023 }
2024 #endif
2025 
2026 
2027 /***************************************************************************/
2049 {
2051  uint32_t selReg;
2052 
2053  selReg = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2054 
2055  switch (selReg)
2056  {
2057  case CMU_HFCLKSEL_REG:
2058 #if defined( _CMU_HFCLKSEL_HF_MASK )
2059  switch (CMU->HFCLKSEL & _CMU_HFCLKSEL_HF_MASK)
2060  {
2061  case CMU_HFCLKSEL_HF_LFXO:
2062  ret = cmuSelect_LFXO;
2063  break;
2064 
2065  case CMU_HFCLKSEL_HF_LFRCO:
2066  ret = cmuSelect_LFRCO;
2067  break;
2068 
2069  case CMU_HFCLKSEL_HF_HFXO:
2070  ret = cmuSelect_HFXO;
2071  break;
2072 
2073  default:
2074  ret = cmuSelect_HFRCO;
2075  break;
2076  }
2077 #else
2078  switch (CMU->STATUS
2082 #if defined( CMU_STATUS_USHFRCODIV2SEL )
2083  | CMU_STATUS_USHFRCODIV2SEL
2084 #endif
2085  | CMU_STATUS_LFXOSEL))
2086  {
2087  case CMU_STATUS_LFXOSEL:
2088  ret = cmuSelect_LFXO;
2089  break;
2090 
2091  case CMU_STATUS_LFRCOSEL:
2092  ret = cmuSelect_LFRCO;
2093  break;
2094 
2095  case CMU_STATUS_HFXOSEL:
2096  ret = cmuSelect_HFXO;
2097  break;
2098 
2099 #if defined( CMU_STATUS_USHFRCODIV2SEL )
2100  case CMU_STATUS_USHFRCODIV2SEL:
2101  ret = cmuSelect_USHFRCODIV2;
2102  break;
2103 #endif
2104 
2105  default:
2106  ret = cmuSelect_HFRCO;
2107  break;
2108  }
2109 #endif
2110  break;
2111 
2112  case CMU_LFACLKSEL_REG:
2113 #if defined( _CMU_LFCLKSEL_MASK )
2114  switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFA_MASK)
2115  {
2117  ret = cmuSelect_LFRCO;
2118  break;
2119 
2120  case CMU_LFCLKSEL_LFA_LFXO:
2121  ret = cmuSelect_LFXO;
2122  break;
2123 
2124 #if defined( CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 )
2126  ret = cmuSelect_CORELEDIV2;
2127  break;
2128 #endif
2129 
2130  default:
2131 #if defined( CMU_LFCLKSEL_LFAE )
2132  if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFAE_MASK)
2133  {
2134  ret = cmuSelect_ULFRCO;
2135  break;
2136  }
2137 #else
2138  ret = cmuSelect_Disabled;
2139 #endif
2140  break;
2141  }
2142 #endif /* _CMU_LFCLKSEL_MASK */
2143 
2144 #if defined( _CMU_LFACLKSEL_MASK )
2145  switch (CMU->LFACLKSEL & _CMU_LFACLKSEL_LFA_MASK)
2146  {
2147  case CMU_LFACLKSEL_LFA_LFRCO:
2148  ret = cmuSelect_LFRCO;
2149  break;
2150 
2151  case CMU_LFACLKSEL_LFA_LFXO:
2152  ret = cmuSelect_LFXO;
2153  break;
2154 
2155  case CMU_LFACLKSEL_LFA_ULFRCO:
2156  ret = cmuSelect_ULFRCO;
2157  break;
2158 
2159 #if defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2160  case CMU_LFACLKSEL_LFA_HFCLKLE:
2161  ret = cmuSelect_HFCLKLE;
2162  break;
2163 #endif
2164 
2165  default:
2166  ret = cmuSelect_Disabled;
2167  break;
2168  }
2169 #endif
2170  break;
2171 
2172  case CMU_LFBCLKSEL_REG:
2173 #if defined( _CMU_LFCLKSEL_MASK )
2174  switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFB_MASK)
2175  {
2177  ret = cmuSelect_LFRCO;
2178  break;
2179 
2180  case CMU_LFCLKSEL_LFB_LFXO:
2181  ret = cmuSelect_LFXO;
2182  break;
2183 
2184 #if defined( CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 )
2186  ret = cmuSelect_CORELEDIV2;
2187  break;
2188 #endif
2189 
2190 #if defined( CMU_LFCLKSEL_LFB_HFCLKLE )
2191  case CMU_LFCLKSEL_LFB_HFCLKLE:
2192  ret = cmuSelect_HFCLKLE;
2193  break;
2194 #endif
2195 
2196  default:
2197 #if defined( CMU_LFCLKSEL_LFBE )
2198  if (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFBE_MASK)
2199  {
2200  ret = cmuSelect_ULFRCO;
2201  break;
2202  }
2203 #else
2204  ret = cmuSelect_Disabled;
2205 #endif
2206  break;
2207  }
2208 #endif /* _CMU_LFCLKSEL_MASK */
2209 
2210 #if defined( _CMU_LFBCLKSEL_MASK )
2211  switch (CMU->LFBCLKSEL & _CMU_LFBCLKSEL_LFB_MASK)
2212  {
2213  case CMU_LFBCLKSEL_LFB_LFRCO:
2214  ret = cmuSelect_LFRCO;
2215  break;
2216 
2217  case CMU_LFBCLKSEL_LFB_LFXO:
2218  ret = cmuSelect_LFXO;
2219  break;
2220 
2221  case CMU_LFBCLKSEL_LFB_ULFRCO:
2222  ret = cmuSelect_ULFRCO;
2223  break;
2224 
2225  case CMU_LFBCLKSEL_LFB_HFCLKLE:
2226  ret = cmuSelect_HFCLKLE;
2227  break;
2228 
2229  default:
2230  ret = cmuSelect_Disabled;
2231  break;
2232  }
2233 #endif
2234  break;
2235 
2236 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2237  case CMU_LFCCLKSEL_REG:
2238  switch (CMU->LFCLKSEL & _CMU_LFCLKSEL_LFC_MASK)
2239  {
2240  case CMU_LFCLKSEL_LFC_LFRCO:
2241  ret = cmuSelect_LFRCO;
2242  break;
2243 
2244  case CMU_LFCLKSEL_LFC_LFXO:
2245  ret = cmuSelect_LFXO;
2246  break;
2247 
2248  default:
2249  ret = cmuSelect_Disabled;
2250  break;
2251  }
2252  break;
2253 #endif
2254 
2255 #if defined( _CMU_LFECLKSEL_LFE_MASK )
2256  case CMU_LFECLKSEL_REG:
2257  switch (CMU->LFECLKSEL & _CMU_LFECLKSEL_LFE_MASK)
2258  {
2259  case CMU_LFECLKSEL_LFE_LFRCO:
2260  ret = cmuSelect_LFRCO;
2261  break;
2262 
2263  case CMU_LFECLKSEL_LFE_LFXO:
2264  ret = cmuSelect_LFXO;
2265  break;
2266 
2267  case CMU_LFECLKSEL_LFE_ULFRCO:
2268  ret = cmuSelect_ULFRCO;
2269  break;
2270 
2271 #if defined ( _CMU_LFECLKSEL_LFE_HFCLKLE )
2272  case CMU_LFECLKSEL_LFE_HFCLKLE:
2273  ret = cmuSelect_HFCLKLE;
2274  break;
2275 #endif
2276 
2277  default:
2278  ret = cmuSelect_Disabled;
2279  break;
2280  }
2281  break;
2282 #endif /* CMU_LFECLKSEL_REG */
2283 
2284  case CMU_DBGCLKSEL_REG:
2285 #if defined( _CMU_DBGCLKSEL_DBG_MASK )
2286  switch (CMU->DBGCLKSEL & _CMU_DBGCLKSEL_DBG_MASK)
2287  {
2288  case CMU_DBGCLKSEL_DBG_HFCLK:
2289  ret = cmuSelect_HFCLK;
2290  break;
2291 
2292  case CMU_DBGCLKSEL_DBG_AUXHFRCO:
2293  ret = cmuSelect_AUXHFRCO;
2294  break;
2295  }
2296 #else
2297  ret = cmuSelect_AUXHFRCO;
2298 #endif /* CMU_DBGCLKSEL_DBG */
2299 
2300 #if defined( _CMU_CTRL_DBGCLK_MASK )
2301  switch(CMU->CTRL & _CMU_CTRL_DBGCLK_MASK)
2302  {
2303  case CMU_CTRL_DBGCLK_AUXHFRCO:
2304  ret = cmuSelect_AUXHFRCO;
2305  break;
2306 
2307  case CMU_CTRL_DBGCLK_HFCLK:
2308  ret = cmuSelect_HFCLK;
2309  break;
2310  }
2311 #else
2312  ret = cmuSelect_AUXHFRCO;
2313 #endif
2314  break;
2315 
2316 
2317 #if defined( USB_PRESENT )
2318  case CMU_USBCCLKSEL_REG:
2319  switch (CMU->STATUS
2320  & (CMU_STATUS_USBCLFXOSEL
2321 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2322  | CMU_STATUS_USBCHFCLKSEL
2323 #endif
2324 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2325  | CMU_STATUS_USBCUSHFRCOSEL
2326 #endif
2327  | CMU_STATUS_USBCLFRCOSEL))
2328  {
2329 #if defined(_CMU_STATUS_USBCHFCLKSEL_MASK)
2330  case CMU_STATUS_USBCHFCLKSEL:
2331  ret = cmuSelect_HFCLK;
2332  break;
2333 #endif
2334 
2335 #if defined(_CMU_STATUS_USBCUSHFRCOSEL_MASK)
2336  case CMU_STATUS_USBCUSHFRCOSEL:
2337  ret = cmuSelect_USHFRCO;
2338  break;
2339 #endif
2340 
2341  case CMU_STATUS_USBCLFXOSEL:
2342  ret = cmuSelect_LFXO;
2343  break;
2344 
2345  case CMU_STATUS_USBCLFRCOSEL:
2346  ret = cmuSelect_LFRCO;
2347  break;
2348 
2349  default:
2350  ret = cmuSelect_Disabled;
2351  break;
2352  }
2353  break;
2354 #endif
2355 
2356  default:
2357  EFM_ASSERT(0);
2358  ret = cmuSelect_Error;
2359  break;
2360  }
2361 
2362  return ret;
2363 }
2364 
2365 
2366 /***************************************************************************/
2407 {
2408  uint32_t select = cmuOsc_HFRCO;
2410  uint32_t freq;
2411  uint32_t tmp;
2412  uint32_t selRegId;
2413 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2414  volatile uint32_t *selReg = NULL;
2415 #endif
2416 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2417  uint32_t lfExtended = 0;
2418 #endif
2419 
2420  selRegId = (clock >> CMU_SEL_REG_POS) & CMU_SEL_REG_MASK;
2421 
2422  switch (selRegId)
2423  {
2424  case CMU_HFCLKSEL_REG:
2425  switch (ref)
2426  {
2427  case cmuSelect_LFXO:
2428 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2429  select = CMU_HFCLKSEL_HF_LFXO;
2430 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2431  select = CMU_CMD_HFCLKSEL_LFXO;
2432 #endif
2433  osc = cmuOsc_LFXO;
2434  break;
2435 
2436  case cmuSelect_LFRCO:
2437 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2438  select = CMU_HFCLKSEL_HF_LFRCO;
2439 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2440  select = CMU_CMD_HFCLKSEL_LFRCO;
2441 #endif
2442  osc = cmuOsc_LFRCO;
2443  break;
2444 
2445  case cmuSelect_HFXO:
2446  osc = cmuOsc_HFXO;
2447 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2448  select = CMU_HFCLKSEL_HF_HFXO;
2449  /* Adjust HFXO buffer current for high frequencies, */
2450  /* enable WSHFLE for frequencies above 32MHz. */
2451  if (SystemHFXOClockGet() > 32000000)
2452  {
2453  CMU->CTRL |= CMU_CTRL_WSHFLE;
2454  }
2455 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2456  select = CMU_CMD_HFCLKSEL_HFXO;
2457 #if defined( CMU_CTRL_HFLE )
2458  /* Adjust HFXO buffer current for high frequencies, */
2459  /* enable HFLE for frequencies above CMU_MAX_FREQ_HFLE. */
2460  if(SystemHFXOClockGet() > CMU_MAX_FREQ_HFLE())
2461  {
2462  CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
2463  | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ
2464  /* Must have HFLE enabled to access some LE peripherals >=32MHz */
2465  | CMU_CTRL_HFLE;
2466 
2467  /* Set HFLE and DIV4 factor for peripheral clock if HFCORE */
2468  /* clock for LE is enabled. */
2469  if (CMU->HFCORECLKEN0 & CMU_HFCORECLKEN0_LE)
2470  {
2471  BUS_RegBitWrite(&CMU->HFCORECLKDIV,
2472  _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
2473  }
2474  }
2475  else
2476  {
2477  /* This can happen if the user configures the EFM32_HFXO_FREQ to */
2478  /* use another oscillator frequency */
2479  CMU->CTRL = (CMU->CTRL & ~_CMU_CTRL_HFXOBUFCUR_MASK)
2480  | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ;
2481  }
2482 #endif
2483 #endif
2484  break;
2485 
2486  case cmuSelect_HFRCO:
2487 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2488  select = CMU_HFCLKSEL_HF_HFRCO;
2489 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2490  select = CMU_CMD_HFCLKSEL_HFRCO;
2491 #endif
2492  osc = cmuOsc_HFRCO;
2493  break;
2494 
2495 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
2496  case cmuSelect_USHFRCODIV2:
2497  select = CMU_CMD_HFCLKSEL_USHFRCODIV2;
2498  osc = cmuOsc_USHFRCO;
2499  break;
2500 #endif
2501 
2502 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
2503  case cmuSelect_ULFRCO:
2504  /* ULFRCO cannot be used as HFCLK */
2505  EFM_ASSERT(0);
2506  return;
2507 #endif
2508 
2509  default:
2510  EFM_ASSERT(0);
2511  return;
2512  }
2513 
2514  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2515  CMU_OscillatorEnable(osc, true, true);
2516 
2517  /* Configure worst case wait states for flash access before selecting */
2518  flashWaitStateMax();
2519 
2520  /* Switch to selected oscillator */
2521 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2522  CMU->HFCLKSEL = select;
2523 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2524  CMU->CMD = select;
2525 #endif
2526 
2527  /* Keep EMU module informed */
2529 
2530  /* Update CMSIS core clock variable */
2531  /* (The function will update the global variable) */
2532  freq = SystemCoreClockGet();
2533 
2534  /* Optimize flash access wait state setting for currently selected core clk */
2535  flashWaitStateControl(freq);
2536  break;
2537 
2538 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
2539  case CMU_LFACLKSEL_REG:
2540  selReg = (selReg == NULL) ? &CMU->LFACLKSEL : selReg;
2541 #if !defined( _CMU_LFACLKSEL_LFA_HFCLKLE )
2542  /* HFCLKCLE can not be used as LFACLK */
2543  EFM_ASSERT(ref != cmuSelect_HFCLKLE);
2544 #endif
2545  case CMU_LFECLKSEL_REG:
2546  selReg = (selReg == NULL) ? &CMU->LFECLKSEL : selReg;
2547 #if !defined( _CMU_LFECLKSEL_LFE_HFCLKLE )
2548  /* HFCLKCLE can not be used as LFECLK */
2549  EFM_ASSERT(ref != cmuSelect_HFCLKLE);
2550 #endif
2551  case CMU_LFBCLKSEL_REG:
2552  selReg = (selReg == NULL) ? &CMU->LFBCLKSEL : selReg;
2553  switch (ref)
2554  {
2555  case cmuSelect_Disabled:
2556  tmp = _CMU_LFACLKSEL_LFA_DISABLED;
2557  break;
2558 
2559  case cmuSelect_LFXO:
2560  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2561  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2562  tmp = _CMU_LFACLKSEL_LFA_LFXO;
2563  break;
2564 
2565  case cmuSelect_LFRCO:
2566  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2567  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2568  tmp = _CMU_LFACLKSEL_LFA_LFRCO;
2569  break;
2570 
2571  case cmuSelect_HFCLKLE:
2572  /* Ensure HFCORE to LE clocking is enabled */
2573  BUS_RegBitWrite(&CMU->HFBUSCLKEN0, _CMU_HFBUSCLKEN0_LE_SHIFT, 1);
2574  tmp = _CMU_LFBCLKSEL_LFB_HFCLKLE;
2575 
2576  /* If core frequency is > 32MHz enable WSHFLE */
2577  freq = SystemCoreClockGet();
2578  if (freq > 32000000U)
2579  {
2580  /* Enable CMU HFLE */
2581  BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_WSHFLE_SHIFT, 1);
2582 
2583  /* Enable DIV4 factor for peripheral clock */
2584  BUS_RegBitWrite(&CMU->HFPRESC, _CMU_HFPRESC_HFCLKLEPRESC_SHIFT, 1);
2585  }
2586  break;
2587 
2588  case cmuSelect_ULFRCO:
2589  /* ULFRCO is always on, there is no need to enable it. */
2590  tmp = _CMU_LFACLKSEL_LFA_ULFRCO;
2591  break;
2592 
2593  default:
2594  EFM_ASSERT(0);
2595  return;
2596  }
2597  *selReg = tmp;
2598  break;
2599 
2600 #elif defined( _SILICON_LABS_32B_PLATFORM_1 )
2601  case CMU_LFACLKSEL_REG:
2602  case CMU_LFBCLKSEL_REG:
2603  switch (ref)
2604  {
2605  case cmuSelect_Disabled:
2607  break;
2608 
2609  case cmuSelect_LFXO:
2610  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2611  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2612  tmp = _CMU_LFCLKSEL_LFA_LFXO;
2613  break;
2614 
2615  case cmuSelect_LFRCO:
2616  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2617  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2619  break;
2620 
2621  case cmuSelect_CORELEDIV2:
2622  /* Ensure HFCORE to LE clocking is enabled */
2623  BUS_RegBitWrite(&(CMU->HFCORECLKEN0), _CMU_HFCORECLKEN0_LE_SHIFT, 1);
2625 #if defined( CMU_CTRL_HFLE )
2626  /* If core frequency is higher than CMU_MAX_FREQ_HFLE on
2627  Giant/Leopard/Wonder, enable HFLE and DIV4. */
2628  freq = SystemCoreClockGet();
2629  if(freq > CMU_MAX_FREQ_HFLE())
2630  {
2631  /* Enable CMU HFLE */
2632  BUS_RegBitWrite(&CMU->CTRL, _CMU_CTRL_HFLE_SHIFT, 1);
2633 
2634  /* Enable DIV4 factor for peripheral clock */
2635  BUS_RegBitWrite(&CMU->HFCORECLKDIV,
2636  _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT, 1);
2637  }
2638 #endif
2639  break;
2640 
2641 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
2642  case cmuSelect_ULFRCO:
2643  /* ULFRCO is always enabled */
2645  lfExtended = 1;
2646  break;
2647 #endif
2648 
2649  default:
2650  /* Illegal clock source for LFA/LFB selected */
2651  EFM_ASSERT(0);
2652  return;
2653  }
2654 
2655  /* Apply select */
2656  if (selRegId == CMU_LFACLKSEL_REG)
2657  {
2658 #if defined( _CMU_LFCLKSEL_LFAE_MASK )
2659  CMU->LFCLKSEL = (CMU->LFCLKSEL
2660  & ~(_CMU_LFCLKSEL_LFA_MASK | _CMU_LFCLKSEL_LFAE_MASK))
2661  | (tmp << _CMU_LFCLKSEL_LFA_SHIFT)
2662  | (lfExtended << _CMU_LFCLKSEL_LFAE_SHIFT);
2663 #else
2664  CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFA_MASK)
2665  | (tmp << _CMU_LFCLKSEL_LFA_SHIFT);
2666 #endif
2667  }
2668  else
2669  {
2670 #if defined( _CMU_LFCLKSEL_LFBE_MASK )
2671  CMU->LFCLKSEL = (CMU->LFCLKSEL
2672  & ~(_CMU_LFCLKSEL_LFB_MASK | _CMU_LFCLKSEL_LFBE_MASK))
2673  | (tmp << _CMU_LFCLKSEL_LFB_SHIFT)
2674  | (lfExtended << _CMU_LFCLKSEL_LFBE_SHIFT);
2675 #else
2676  CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFB_MASK)
2677  | (tmp << _CMU_LFCLKSEL_LFB_SHIFT);
2678 #endif
2679  }
2680  break;
2681 
2682 #if defined( _CMU_LFCLKSEL_LFC_MASK )
2683  case CMU_LFCCLKSEL_REG:
2684  switch(ref)
2685  {
2686  case cmuSelect_Disabled:
2688  break;
2689 
2690  case cmuSelect_LFXO:
2691  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2692  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2693  tmp = _CMU_LFCLKSEL_LFC_LFXO;
2694  break;
2695 
2696  case cmuSelect_LFRCO:
2697  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2698  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2699  tmp = _CMU_LFCLKSEL_LFC_LFRCO;
2700  break;
2701 
2702  default:
2703  /* Illegal clock source for LFC selected */
2704  EFM_ASSERT(0);
2705  return;
2706  }
2707 
2708  /* Apply select */
2709  CMU->LFCLKSEL = (CMU->LFCLKSEL & ~_CMU_LFCLKSEL_LFC_MASK)
2710  | (tmp << _CMU_LFCLKSEL_LFC_SHIFT);
2711  break;
2712 #endif
2713 #endif
2714 
2715 #if defined( CMU_DBGCLKSEL_DBG ) || defined( CMU_CTRL_DBGCLK )
2716  case CMU_DBGCLKSEL_REG:
2717  switch(ref)
2718  {
2719 #if defined( CMU_DBGCLKSEL_DBG )
2720  case cmuSelect_AUXHFRCO:
2721  /* Select AUXHFRCO as debug clock */
2722  CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_AUXHFRCO;
2723  break;
2724 
2725  case cmuSelect_HFCLK:
2726  /* Select divided HFCLK as debug clock */
2727  CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
2728  break;
2729 #endif
2730 
2731 #if defined( CMU_CTRL_DBGCLK )
2732  case cmuSelect_AUXHFRCO:
2733  /* Select AUXHFRCO as debug clock */
2734  CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2735  | CMU_CTRL_DBGCLK_AUXHFRCO;
2736  break;
2737 
2738  case cmuSelect_HFCLK:
2739  /* Select divided HFCLK as debug clock */
2740  CMU->CTRL = (CMU->CTRL & ~(_CMU_CTRL_DBGCLK_MASK))
2741  | CMU_CTRL_DBGCLK_HFCLK;
2742  break;
2743 #endif
2744 
2745  default:
2746  /* Illegal clock source for debug selected */
2747  EFM_ASSERT(0);
2748  return;
2749  }
2750  break;
2751 #endif
2752 
2753 #if defined(USB_PRESENT)
2754  case CMU_USBCCLKSEL_REG:
2755  switch(ref)
2756  {
2757  case cmuSelect_LFXO:
2758  /* Select LFXO as clock source for USB, can only be used in sleep mode */
2759  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2760  CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
2761 
2762  /* Switch oscillator */
2763  CMU->CMD = CMU_CMD_USBCCLKSEL_LFXO;
2764 
2765  /* Wait until clock is activated */
2766  while((CMU->STATUS & CMU_STATUS_USBCLFXOSEL)==0)
2767  {
2768  }
2769  break;
2770 
2771  case cmuSelect_LFRCO:
2772  /* Select LFRCO as clock source for USB, can only be used in sleep mode */
2773  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2774  CMU_OscillatorEnable(cmuOsc_LFRCO, true, true);
2775 
2776  /* Switch oscillator */
2777  CMU->CMD = CMU_CMD_USBCCLKSEL_LFRCO;
2778 
2779  /* Wait until clock is activated */
2780  while((CMU->STATUS & CMU_STATUS_USBCLFRCOSEL)==0)
2781  {
2782  }
2783  break;
2784 
2785 #if defined( CMU_STATUS_USBCHFCLKSEL )
2786  case cmuSelect_HFCLK:
2787  /* Select undivided HFCLK as clock source for USB */
2788  /* Oscillator must already be enabled to avoid a core lockup */
2789  CMU->CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
2790  /* Wait until clock is activated */
2791  while((CMU->STATUS & CMU_STATUS_USBCHFCLKSEL)==0)
2792  {
2793  }
2794  break;
2795 #endif
2796 
2797 #if defined( CMU_CMD_USBCCLKSEL_USHFRCO )
2798  case cmuSelect_USHFRCO:
2799  /* Select USHFRCO as clock source for USB */
2800  /* Ensure selected oscillator is enabled, waiting for it to stabilize */
2801  CMU_OscillatorEnable(cmuOsc_USHFRCO, true, true);
2802 
2803  /* Switch oscillator */
2804  CMU->CMD = CMU_CMD_USBCCLKSEL_USHFRCO;
2805 
2806  /* Wait until clock is activated */
2807  while((CMU->STATUS & CMU_STATUS_USBCUSHFRCOSEL)==0)
2808  {
2809  }
2810  break;
2811 #endif
2812 
2813  default:
2814  /* Illegal clock source for USB */
2815  EFM_ASSERT(0);
2816  return;
2817  }
2818  break;
2819 #endif
2820 
2821  default:
2822  EFM_ASSERT(0);
2823  break;
2824  }
2825 }
2826 
2827 
2828 /**************************************************************************/
2857 void CMU_FreezeEnable(bool enable)
2858 {
2859  if (enable)
2860  {
2861  /* Wait for any ongoing LF synchronization to complete. This is just to */
2862  /* protect against the rare case when a user */
2863  /* - modifies a register requiring LF sync */
2864  /* - then enables freeze before LF sync completed */
2865  /* - then modifies the same register again */
2866  /* since modifying a register while it is in sync progress should be */
2867  /* avoided. */
2868  while (CMU->SYNCBUSY)
2869  {
2870  }
2871 
2872  CMU->FREEZE = CMU_FREEZE_REGFREEZE;
2873  }
2874  else
2875  {
2876  CMU->FREEZE = 0;
2877  }
2878 }
2879 
2880 
2881 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
2882 /***************************************************************************/
2890 {
2891  return (CMU_HFRCOBand_TypeDef)((CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK)
2893 }
2894 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
2895 
2896 
2897 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
2898 /***************************************************************************/
2907 {
2908  uint32_t tuning;
2909  uint32_t freq;
2910  CMU_Select_TypeDef osc;
2911 
2912  /* Read tuning value from calibration table */
2913  switch (band)
2914  {
2915  case cmuHFRCOBand_1MHz:
2916  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND1_MASK)
2918  break;
2919 
2920  case cmuHFRCOBand_7MHz:
2921  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND7_MASK)
2923  break;
2924 
2925  case cmuHFRCOBand_11MHz:
2926  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND11_MASK)
2928  break;
2929 
2930  case cmuHFRCOBand_14MHz:
2931  tuning = (DEVINFO->HFRCOCAL0 & _DEVINFO_HFRCOCAL0_BAND14_MASK)
2933  break;
2934 
2935  case cmuHFRCOBand_21MHz:
2936  tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND21_MASK)
2938  break;
2939 
2940 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
2941  case cmuHFRCOBand_28MHz:
2942  tuning = (DEVINFO->HFRCOCAL1 & _DEVINFO_HFRCOCAL1_BAND28_MASK)
2944  break;
2945 #endif
2946 
2947  default:
2948  EFM_ASSERT(0);
2949  return;
2950  }
2951 
2952  /* If HFRCO is used for core clock, we have to consider flash access WS. */
2954  if (osc == cmuSelect_HFRCO)
2955  {
2956  /* Configure worst case wait states for flash access before setting divider */
2957  flashWaitStateMax();
2958  }
2959 
2960  /* Set band/tuning */
2961  CMU->HFRCOCTRL = (CMU->HFRCOCTRL &
2963  | (band << _CMU_HFRCOCTRL_BAND_SHIFT)
2964  | (tuning << _CMU_HFRCOCTRL_TUNING_SHIFT);
2965 
2966  /* If HFRCO is used for core clock, optimize flash WS */
2967  if (osc == cmuSelect_HFRCO)
2968  {
2969  /* Update CMSIS core clock variable and get current core clock */
2970  /* (The function will update the global variable) */
2971  /* NOTE! We need at least 21 cycles before setting zero wait state to flash */
2972  /* (i.e. WS0) when going from the 28MHz to 1MHz in the HFRCO band */
2973  freq = SystemCoreClockGet();
2974 
2975  /* Optimize flash access wait state setting for current core clk */
2976  flashWaitStateControl(freq);
2977  }
2978 }
2979 #endif /* _CMU_HFRCOCTRL_BAND_MASK */
2980 
2981 
2982 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
2983 /**************************************************************************/
2993 static uint32_t CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)
2994 {
2995  switch (freq)
2996  {
2997  /* 1, 2 and 4MHz share the same calibration word */
2998  case cmuHFRCOFreq_1M0Hz:
2999  case cmuHFRCOFreq_2M0Hz:
3000  case cmuHFRCOFreq_4M0Hz:
3001  return DEVINFO->HFRCOCAL0;
3002 
3003  case cmuHFRCOFreq_7M0Hz:
3004  return DEVINFO->HFRCOCAL3;
3005 
3006  case cmuHFRCOFreq_13M0Hz:
3007  return DEVINFO->HFRCOCAL6;
3008 
3009  case cmuHFRCOFreq_16M0Hz:
3010  return DEVINFO->HFRCOCAL7;
3011 
3012  case cmuHFRCOFreq_19M0Hz:
3013  return DEVINFO->HFRCOCAL8;
3014 
3015  case cmuHFRCOFreq_26M0Hz:
3016  return DEVINFO->HFRCOCAL10;
3017 
3018  case cmuHFRCOFreq_32M0Hz:
3019  return DEVINFO->HFRCOCAL11;
3020 
3021  case cmuHFRCOFreq_38M0Hz:
3022  return DEVINFO->HFRCOCAL12;
3023 
3024  default: /* cmuHFRCOFreq_UserDefined */
3025  return 0;
3026  }
3027 }
3028 
3029 
3030 /***************************************************************************/
3037 CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(void)
3038 {
3039  return (CMU_HFRCOFreq_TypeDef)SystemHfrcoFreq;
3040 }
3041 
3042 
3043 /***************************************************************************/
3050 void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freq)
3051 {
3052  uint32_t freqCal;
3053 
3054  /* Get DEVINFO index, set CMSIS frequency SystemHfrcoFreq */
3055  freqCal = CMU_HFRCODevinfoGet(freq);
3056  EFM_ASSERT((freqCal != 0) && (freqCal != UINT_MAX));
3057  SystemHfrcoFreq = (uint32_t)freq;
3058 
3059  /* Set max wait-states while changing core clock */
3061  {
3062  flashWaitStateMax();
3063  }
3064 
3065  /* Wait for any previous sync to complete, and then set calibration data
3066  for the selected frequency. */
3067  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT));
3068 
3069  /* Check for valid calibration data */
3070  EFM_ASSERT(freqCal != UINT_MAX);
3071 
3072  /* Set divider in HFRCOCTRL for 1, 2 and 4MHz */
3073  switch(freq)
3074  {
3075  case cmuHFRCOFreq_1M0Hz:
3076  freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3077  | CMU_HFRCOCTRL_CLKDIV_DIV4;
3078  break;
3079 
3080  case cmuHFRCOFreq_2M0Hz:
3081  freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3082  | CMU_HFRCOCTRL_CLKDIV_DIV2;
3083  break;
3084 
3085  case cmuHFRCOFreq_4M0Hz:
3086  freqCal = (freqCal & ~_CMU_HFRCOCTRL_CLKDIV_MASK)
3087  | CMU_HFRCOCTRL_CLKDIV_DIV1;
3088  break;
3089 
3090  default:
3091  break;
3092  }
3093  CMU->HFRCOCTRL = freqCal;
3094 
3095  /* Optimize flash access wait-state configuration for this frequency, */
3096  /* if HFRCO is reference for core clock. */
3098  {
3099  flashWaitStateControl((uint32_t)freq);
3100  }
3101 }
3102 #endif /* _CMU_HFRCOCTRL_FREQRANGE_MASK */
3103 
3104 #if defined( _CMU_HFRCOCTRL_SUDELAY_MASK )
3105 /***************************************************************************/
3116 {
3117  return (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_SUDELAY_MASK)
3119 }
3120 
3121 
3122 /***************************************************************************/
3132 void CMU_HFRCOStartupDelaySet(uint32_t delay)
3133 {
3134  EFM_ASSERT(delay <= 31);
3135 
3137  CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_SUDELAY_MASK))
3138  | (delay << _CMU_HFRCOCTRL_SUDELAY_SHIFT);
3139 }
3140 #endif
3141 
3142 
3143 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
3144 /***************************************************************************/
3164 void CMU_HFXOAutostartEnable(bool enRACStartSel,
3165  bool enEM0EM1Start,
3166  bool enEM0EM1StartSel)
3167 {
3168  uint32_t hfxoCtrl;
3169  hfxoCtrl = CMU->HFXOCTRL & ~(_CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
3170  | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
3171  | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK);
3172 
3173  hfxoCtrl |= (enRACStartSel ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)
3174  | (enEM0EM1Start ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
3175  | (enEM0EM1StartSel ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0);
3176 
3177  CMU->HFXOCTRL = hfxoCtrl;
3178 }
3179 #endif /* _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK */
3180 
3181 
3182 #if defined( _CMU_HFXOCTRL_MASK )
3183 /**************************************************************************/
3195 void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit)
3196 {
3197  uint32_t ishReg;
3198  uint32_t ishMax;
3199 
3200  /* Do not disable HFXO if it is currently selected as HF/Core clock */
3202 
3203  /* HFXO must be disabled before reconfiguration */
3204  CMU_OscillatorEnable(cmuOsc_HFXO, false, false);
3205 
3206  /* Apply control settings */
3207  BUS_RegMaskedWrite(&CMU->HFXOCTRL,
3208  _CMU_HFXOCTRL_LOWPOWER_MASK
3209 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
3210  | _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK
3211 #endif
3212  | _CMU_HFXOCTRL_AUTOSTARTEM0EM1_MASK
3213  | _CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_MASK,
3214  (hfxoInit->lowPowerMode
3215  ? CMU_HFXOCTRL_LOWPOWER : 0)
3216 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
3217  | (hfxoInit->autoStartSelOnRacWakeup
3218  ? CMU_HFXOCTRL_AUTOSTARTRDYSELRAC : 0)
3219 #endif
3220  | (hfxoInit->autoStartEm01
3221  ? CMU_HFXOCTRL_AUTOSTARTEM0EM1 : 0)
3222  | (hfxoInit->autoSelEm01
3223  ? CMU_HFXOCTRL_AUTOSTARTSELEM0EM1 : 0));
3224 
3225  /* Set XTAL tuning parameters */
3226 
3227  /* Set peak detection threshold in CMU_HFXOCTRL1_PEAKDETTHR[2:0] (hidden). */
3228  BUS_RegMaskedWrite((volatile uint32_t *)0x400E4028, 0x7, hfxoInit->thresholdPeakDetect);
3229 
3230  /* Set tuning for startup and steady state */
3231  BUS_RegMaskedWrite(&CMU->HFXOSTARTUPCTRL,
3232  _CMU_HFXOSTARTUPCTRL_CTUNE_MASK
3233  | _CMU_HFXOSTARTUPCTRL_REGISHWARM_MASK
3234  | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_MASK
3235  | _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_MASK,
3236  (hfxoInit->ctuneStartup
3237  << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT)
3238  | (hfxoInit->regIshStartup
3239  << _CMU_HFXOSTARTUPCTRL_REGISHWARM_SHIFT)
3240  | (hfxoInit->xoCoreBiasTrimStartup
3241  << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_SHIFT)
3242  | 0x4 /* Recommended tuning */
3243  << _CMU_HFXOSTARTUPCTRL_IBTRIMXOCOREWARM_SHIFT);
3244 
3245  /* Adjust CMU_HFXOSTEADYSTATECTRL_REGISHUPPER according to regIshSteadyState.
3246  Saturate at max value. Please see the reference manual page 433 and Section
3247  12.5.10 CMU_HFXOSTEADYSTATECTRL for more details. */
3248  ishReg = hfxoInit->regIshSteadyState + 3;
3249  ishMax = _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK
3250  >> _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
3251  ishReg = ishReg > ishMax ? ishMax : ishReg;
3252  ishReg <<= _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_SHIFT;
3253 
3254  BUS_RegMaskedWrite(&CMU->HFXOSTEADYSTATECTRL,
3255  _CMU_HFXOSTEADYSTATECTRL_CTUNE_MASK
3256  | _CMU_HFXOSTEADYSTATECTRL_REGISH_MASK
3257  | _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_MASK
3258  | _CMU_HFXOSTEADYSTATECTRL_REGISHUPPER_MASK,
3259  (hfxoInit->ctuneSteadyState
3260  << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT)
3261  | (hfxoInit->regIshSteadyState
3262  << _CMU_HFXOSTEADYSTATECTRL_REGISH_SHIFT)
3263  | (hfxoInit->xoCoreBiasTrimSteadyState
3264  << _CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_SHIFT)
3265  | ishReg);
3266 
3267  /* Set timeouts */
3268  BUS_RegMaskedWrite(&CMU->HFXOTIMEOUTCTRL,
3269  _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_MASK
3270  | _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_MASK
3271  | _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_MASK
3272  | _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_MASK
3273  | _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_MASK,
3274  (hfxoInit->timeoutShuntOptimization
3275  << _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_SHIFT)
3276  | (hfxoInit->timeoutPeakDetect
3277  << _CMU_HFXOTIMEOUTCTRL_PEAKDETTIMEOUT_SHIFT)
3278  | (hfxoInit->timeoutWarmSteady
3279  << _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_SHIFT)
3280  | (hfxoInit->timeoutSteady
3281  << _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_SHIFT)
3282  | (hfxoInit->timeoutStartup
3283  << _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_SHIFT));
3284 }
3285 #endif
3286 
3287 
3288 /***************************************************************************/
3295 uint32_t CMU_LCDClkFDIVGet(void)
3296 {
3297 #if defined( LCD_PRESENT )
3298  return (CMU->LCDCTRL & _CMU_LCDCTRL_FDIV_MASK) >> _CMU_LCDCTRL_FDIV_SHIFT;
3299 #else
3300  return 0;
3301 #endif /* defined(LCD_PRESENT) */
3302 }
3303 
3304 
3305 /***************************************************************************/
3318 void CMU_LCDClkFDIVSet(uint32_t div)
3319 {
3320 #if defined( LCD_PRESENT )
3321  EFM_ASSERT(div <= cmuClkDiv_128);
3322 
3323  /* Do not allow modification if LCD clock enabled */
3324  if (CMU->LFACLKEN0 & CMU_LFACLKEN0_LCD)
3325  {
3326  return;
3327  }
3328 
3329  div <<= _CMU_LCDCTRL_FDIV_SHIFT;
3330  div &= _CMU_LCDCTRL_FDIV_MASK;
3331  CMU->LCDCTRL = (CMU->LCDCTRL & ~_CMU_LCDCTRL_FDIV_MASK) | div;
3332 #else
3333  (void)div; /* Unused parameter */
3334 #endif /* defined(LCD_PRESENT) */
3335 }
3336 
3337 
3338 #if defined( _CMU_LFXOCTRL_MASK )
3339 /**************************************************************************/
3351 void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit)
3352 {
3353  /* Do not disable LFXO if it is currently selected as HF/Core clock */
3355 
3356  /* LFXO must be disabled before reconfiguration */
3357  CMU_OscillatorEnable(cmuOsc_LFXO, false, false);
3358 
3359  BUS_RegMaskedWrite(&CMU->LFXOCTRL,
3360  _CMU_LFXOCTRL_TUNING_MASK
3361  | _CMU_LFXOCTRL_GAIN_MASK
3362  | _CMU_LFXOCTRL_TIMEOUT_MASK,
3363  (lfxoInit->ctune << _CMU_LFXOCTRL_TUNING_SHIFT)
3364  | (lfxoInit->gain << _CMU_LFXOCTRL_GAIN_SHIFT)
3365  | (lfxoInit->timeout << _CMU_LFXOCTRL_TIMEOUT_SHIFT));
3366 }
3367 #endif
3368 
3369 
3370 /***************************************************************************/
3394 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
3395 {
3396  uint32_t rdyBitPos;
3397 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3398  uint32_t ensBitPos;
3399 #endif
3400  uint32_t enBit;
3401  uint32_t disBit;
3402 
3403  switch (osc)
3404  {
3405  case cmuOsc_HFRCO:
3406  enBit = CMU_OSCENCMD_HFRCOEN;
3407  disBit = CMU_OSCENCMD_HFRCODIS;
3408  rdyBitPos = _CMU_STATUS_HFRCORDY_SHIFT;
3409 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3410  ensBitPos = _CMU_STATUS_HFRCOENS_SHIFT;
3411 #endif
3412  break;
3413 
3414  case cmuOsc_HFXO:
3415  enBit = CMU_OSCENCMD_HFXOEN;
3416  disBit = CMU_OSCENCMD_HFXODIS;
3417  rdyBitPos = _CMU_STATUS_HFXORDY_SHIFT;
3418 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3419  ensBitPos = _CMU_STATUS_HFXOENS_SHIFT;
3420 #endif
3421  break;
3422 
3423  case cmuOsc_AUXHFRCO:
3424  enBit = CMU_OSCENCMD_AUXHFRCOEN;
3425  disBit = CMU_OSCENCMD_AUXHFRCODIS;
3426  rdyBitPos = _CMU_STATUS_AUXHFRCORDY_SHIFT;
3427 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3428  ensBitPos = _CMU_STATUS_AUXHFRCOENS_SHIFT;
3429 #endif
3430  break;
3431 
3432  case cmuOsc_LFRCO:
3433  enBit = CMU_OSCENCMD_LFRCOEN;
3434  disBit = CMU_OSCENCMD_LFRCODIS;
3435  rdyBitPos = _CMU_STATUS_LFRCORDY_SHIFT;
3436 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3437  ensBitPos = _CMU_STATUS_LFRCOENS_SHIFT;
3438 #endif
3439  break;
3440 
3441  case cmuOsc_LFXO:
3442  enBit = CMU_OSCENCMD_LFXOEN;
3443  disBit = CMU_OSCENCMD_LFXODIS;
3444  rdyBitPos = _CMU_STATUS_LFXORDY_SHIFT;
3445 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3446  ensBitPos = _CMU_STATUS_LFXOENS_SHIFT;
3447 #endif
3448  break;
3449 
3450 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
3451  case cmuOsc_USHFRCO:
3452  enBit = CMU_OSCENCMD_USHFRCOEN;
3453  disBit = CMU_OSCENCMD_USHFRCODIS;
3454  rdyBitPos = _CMU_STATUS_USHFRCORDY_SHIFT;
3455 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3456  ensBitPos = _CMU_STATUS_USHFRCOENS_SHIFT;
3457 #endif
3458  break;
3459 #endif
3460 
3461 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO )
3462  case cmuOsc_ULFRCO:
3463  /* ULFRCO is always enabled, and cannot be turned off */
3464  return;
3465 #endif
3466 
3467  default:
3468  /* Undefined clock source */
3469  EFM_ASSERT(0);
3470  return;
3471  }
3472 
3473  if (enable)
3474  {
3475  CMU->OSCENCMD = enBit;
3476 
3477 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3478  /* Always wait for ENS to go high */
3479  while (!BUS_RegBitRead(&CMU->STATUS, ensBitPos))
3480  {
3481  }
3482 #endif
3483 
3484  /* Wait for clock to become ready after enable */
3485  if (wait)
3486  {
3487  while (!BUS_RegBitRead(&CMU->STATUS, rdyBitPos));
3488 #if defined( _CMU_STATUS_HFXOSHUNTOPTRDY_MASK )
3489  /* Wait for shunt current optimization to complete */
3490  if ((osc == cmuOsc_HFXO)
3491  && (BUS_RegMaskedRead(&CMU->HFXOCTRL,
3492  _CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_MASK)
3493  == CMU_HFXOCTRL_PEAKDETSHUNTOPTMODE_AUTOCMD))
3494  {
3495  while (!BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOSHUNTOPTRDY_SHIFT))
3496  {
3497  }
3498  /* Assert on failed peak detection. Incorrect HFXO initialization parameters
3499  caused startup to fail. Please review parameters. */
3500  EFM_ASSERT(BUS_RegBitRead(&CMU->STATUS, _CMU_STATUS_HFXOPEAKDETRDY_SHIFT));
3501  }
3502 #endif
3503  }
3504  }
3505  else
3506  {
3507  CMU->OSCENCMD = disBit;
3508 
3509 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3510  /* Always wait for ENS to go low */
3511  while (BUS_RegBitRead(&CMU->STATUS, ensBitPos))
3512  {
3513  }
3514 #endif
3515  }
3516 
3517  /* Keep EMU module informed */
3519 }
3520 
3521 
3522 /***************************************************************************/
3536 {
3537  uint32_t ret;
3538 
3539  switch (osc)
3540  {
3541  case cmuOsc_LFRCO:
3542  ret = (CMU->LFRCOCTRL & _CMU_LFRCOCTRL_TUNING_MASK)
3544  break;
3545 
3546  case cmuOsc_HFRCO:
3547  ret = (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_TUNING_MASK)
3549  break;
3550 
3551  case cmuOsc_AUXHFRCO:
3552  ret = (CMU->AUXHFRCOCTRL & _CMU_AUXHFRCOCTRL_TUNING_MASK)
3554  break;
3555 
3556  default:
3557  EFM_ASSERT(0);
3558  ret = 0;
3559  break;
3560  }
3561 
3562  return ret;
3563 }
3564 
3565 
3566 /***************************************************************************/
3585 {
3586  switch (osc)
3587  {
3588  case cmuOsc_LFRCO:
3589  EFM_ASSERT(val <= (_CMU_LFRCOCTRL_TUNING_MASK
3592 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3593  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_LFRCOBSY_SHIFT));
3594 #endif
3595  CMU->LFRCOCTRL = (CMU->LFRCOCTRL & ~(_CMU_LFRCOCTRL_TUNING_MASK))
3596  | (val << _CMU_LFRCOCTRL_TUNING_SHIFT);
3597  break;
3598 
3599  case cmuOsc_HFRCO:
3600  EFM_ASSERT(val <= (_CMU_HFRCOCTRL_TUNING_MASK
3603 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3604  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_HFRCOBSY_SHIFT))
3605  {
3606  }
3607 #endif
3608  CMU->HFRCOCTRL = (CMU->HFRCOCTRL & ~(_CMU_HFRCOCTRL_TUNING_MASK))
3609  | (val << _CMU_HFRCOCTRL_TUNING_SHIFT);
3610  break;
3611 
3612  case cmuOsc_AUXHFRCO:
3613  EFM_ASSERT(val <= (_CMU_AUXHFRCOCTRL_TUNING_MASK
3616 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
3617  while(BUS_RegBitRead(&CMU->SYNCBUSY, _CMU_SYNCBUSY_AUXHFRCOBSY_SHIFT))
3618  {
3619  }
3620 #endif
3621  CMU->AUXHFRCOCTRL = (CMU->AUXHFRCOCTRL & ~(_CMU_AUXHFRCOCTRL_TUNING_MASK))
3622  | (val << _CMU_AUXHFRCOCTRL_TUNING_SHIFT);
3623  break;
3624 
3625  default:
3626  EFM_ASSERT(0);
3627  break;
3628  }
3629 }
3630 
3631 
3632 /**************************************************************************/
3643 bool CMU_PCNTClockExternalGet(unsigned int instance)
3644 {
3645  uint32_t setting;
3646 
3647  switch (instance)
3648  {
3649 #if defined( _CMU_PCNTCTRL_PCNT0CLKEN_MASK )
3650  case 0:
3651  setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0;
3652  break;
3653 
3654 #if defined( _CMU_PCNTCTRL_PCNT1CLKEN_MASK )
3655  case 1:
3656  setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0;
3657  break;
3658 
3659 #if defined( _CMU_PCNTCTRL_PCNT2CLKEN_MASK )
3660  case 2:
3661  setting = CMU->PCNTCTRL & CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0;
3662  break;
3663 #endif
3664 #endif
3665 #endif
3666 
3667  default:
3668  setting = 0;
3669  break;
3670  }
3671  return (setting ? true : false);
3672 }
3673 
3674 
3675 /**************************************************************************/
3685 void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
3686 {
3687 #if defined( PCNT_PRESENT )
3688  uint32_t setting = 0;
3689 
3690  EFM_ASSERT(instance < PCNT_COUNT);
3691 
3692  if (external)
3693  {
3694  setting = 1;
3695  }
3696 
3697  BUS_RegBitWrite(&(CMU->PCNTCTRL), (instance * 2) + 1, setting);
3698 
3699 #else
3700  (void)instance; /* Unused parameter */
3701  (void)external; /* Unused parameter */
3702 #endif
3703 }
3704 
3705 
3706 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
3707 /***************************************************************************/
3714 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void)
3715 {
3716  return (CMU_USHFRCOBand_TypeDef)((CMU->USHFRCOCONF
3717  & _CMU_USHFRCOCONF_BAND_MASK)
3718  >> _CMU_USHFRCOCONF_BAND_SHIFT);
3719 }
3720 #endif
3721 
3722 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
3723 /***************************************************************************/
3730 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band)
3731 {
3732  uint32_t tuning;
3733  uint32_t fineTuning;
3734  CMU_Select_TypeDef osc;
3735 
3736  /* Cannot switch band if USHFRCO is already selected as HF clock. */
3738  EFM_ASSERT((CMU_USHFRCOBandGet() != band) && (osc != cmuSelect_USHFRCO));
3739 
3740  /* Read tuning value from calibration table */
3741  switch (band)
3742  {
3743  case cmuUSHFRCOBand_24MHz:
3744  tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK)
3745  >> _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT;
3746  fineTuning = (DEVINFO->USHFRCOCAL0
3747  & _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK)
3748  >> _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT;
3749  break;
3750 
3751  case cmuUSHFRCOBand_48MHz:
3752  tuning = (DEVINFO->USHFRCOCAL0 & _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK)
3753  >> _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT;
3754  fineTuning = (DEVINFO->USHFRCOCAL0
3755  & _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK)
3756  >> _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT;
3757  /* Enable the clock divider before switching the band from 24 to 48MHz */
3758  BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 0);
3759  break;
3760 
3761  default:
3762  EFM_ASSERT(0);
3763  return;
3764  }
3765 
3766  /* Set band and tuning */
3767  CMU->USHFRCOCONF = (CMU->USHFRCOCONF & ~_CMU_USHFRCOCONF_BAND_MASK)
3768  | (band << _CMU_USHFRCOCONF_BAND_SHIFT);
3769  CMU->USHFRCOCTRL = (CMU->USHFRCOCTRL & ~_CMU_USHFRCOCTRL_TUNING_MASK)
3770  | (tuning << _CMU_USHFRCOCTRL_TUNING_SHIFT);
3771  CMU->USHFRCOTUNE = (CMU->USHFRCOTUNE & ~_CMU_USHFRCOTUNE_FINETUNING_MASK)
3772  | (fineTuning << _CMU_USHFRCOTUNE_FINETUNING_SHIFT);
3773 
3774  /* Disable the clock divider after switching the band from 48 to 24MHz */
3775  if (band == cmuUSHFRCOBand_24MHz)
3776  {
3777  BUS_RegBitWrite(&CMU->USHFRCOCONF, _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT, 1);
3778  }
3779 }
3780 #endif
3781 
3782 
3783 
3786 #endif /* __EM_CMU_H */
#define _CMU_LFAPRESC0_LCD_SHIFT
Definition: efm32g_cmu.h:886
Clock management unit (CMU) API.
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
Definition: em_cmu.c:2406
#define _CMU_CTRL_HFXOBUFCUR_MASK
Definition: efm32g_cmu.h:109
#define _CMU_LFCLKSEL_LFA_SHIFT
Definition: efm32g_cmu.h:402
#define _CMU_AUXHFRCOCTRL_TUNING_MASK
Definition: efm32g_cmu.h:294
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK
Definition: efm32g_cmu.h:225
#define _DEVINFO_HFRCOCAL0_BAND7_MASK
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
Definition: em_cmu.c:3685
uint32_t SystemLFXOClockGet(void)
Get low frequency crystal oscillator clock frequency for target system.
Emlib peripheral API "assert" implementation.
uint32_t SystemLFRCOClockGet(void)
Get low frequency RC oscillator clock frequency for target system.
#define _CMU_STATUS_AUXHFRCOENS_SHIFT
Definition: efm32g_cmu.h:451
#define _CMU_LFBPRESC0_LEUART1_SHIFT
Definition: efm32g_cmu.h:910
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
Definition: em_cmu.c:801
#define _CMU_HFRCOCTRL_TUNING_SHIFT
Definition: efm32g_cmu.h:257
#define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2
Definition: efm32g_cmu.h:408
#define _CMU_LFCLKSEL_LFA_DISABLED
Definition: efm32g_cmu.h:404
RAM and peripheral bit-field set and clear API.
#define CMU_FREEZE_REGFREEZE
Definition: efm32g_cmu.h:772
#define CMU_OSCENCMD_AUXHFRCOEN
Definition: efm32g_cmu.h:347
#define MSC_READCTRL_MODE_WS0
Definition: efm32g_msc.h:87
CMU_Select_TypeDef
Definition: em_cmu.h:950
#define CMU_LFCLKSEL_LFB_LFXO
Definition: efm32g_cmu.h:424
#define _DEVINFO_HFRCOCAL1_BAND21_SHIFT
#define CMU_STATUS_LFXOSEL
Definition: efm32g_cmu.h:495
#define cmuClkDiv_8
Definition: em_cmu.h:151
#define _CMU_CALCNT_CALCNT_MASK
Definition: efm32g_cmu.h:320
#define _DEVINFO_HFRCOCAL0_BAND1_MASK
#define _CMU_LFAPRESC0_RTC_SHIFT
Definition: efm32g_cmu.h:818
#define _CMU_HFRCOCTRL_BAND_MASK
Definition: efm32g_cmu.h:262
#define CMU_OSCENCMD_HFRCODIS
Definition: efm32g_cmu.h:332
#define _ROMTABLE_PID0_REVMAJOR_MASK
#define DEVINFO
#define _CMU_LCDCTRL_FDIV_SHIFT
Definition: efm32g_cmu.h:970
#define _CMU_STATUS_HFXORDY_SHIFT
Definition: efm32g_cmu.h:446
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
Definition: em_cmu.c:2857
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
Definition: em_bus.h:185
uint32_t SystemCoreClockGet(void)
Get the current core clock frequency.
#define _ROMTABLE_PID2_REVMINORMSB_SHIFT
#define _CMU_STATUS_AUXHFRCORDY_SHIFT
Definition: efm32g_cmu.h:456
#define CMU_CALCTRL_UPSEL_HFRCO
Definition: efm32g_cmu.h:312
#define _CMU_CALCTRL_UPSEL_MASK
Definition: efm32g_cmu.h:302
#define CMU_CALCTRL_UPSEL_LFRCO
Definition: efm32g_cmu.h:313
#define _ROMTABLE_PID0_REVMAJOR_SHIFT
#define CMU_CALCTRL_UPSEL_LFXO
Definition: efm32g_cmu.h:311
#define _CMU_STATUS_CALBSY_SHIFT
Definition: efm32g_cmu.h:501
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT
Definition: efm32g_cmu.h:196
uint32_t CMU_ClkDiv_TypeDef
Definition: em_cmu.h:166
#define CMU_CALCTRL_UPSEL_AUXHFRCO
Definition: efm32g_cmu.h:314
#define CMU_OSCENCMD_AUXHFRCODIS
Definition: efm32g_cmu.h:352
#define CMU_SYNCBUSY_LFACLKEN0
Definition: efm32g_cmu.h:748
#define _CMU_LFAPRESC0_LETIMER0_SHIFT
Definition: efm32g_cmu.h:852
uint32_t CMU_HFRCOStartupDelayGet(void)
Get the HFRCO startup delay.
Definition: em_cmu.c:3115
#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2
Definition: efm32g_cmu.h:425
#define CMU_STATUS_HFXOSEL
Definition: efm32g_cmu.h:485
#define CMU_LFCLKSEL_LFA_LFRCO
Definition: efm32g_cmu.h:411
#define _CMU_STATUS_LFXOENS_SHIFT
Definition: efm32g_cmu.h:471
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
Definition: em_cmu.h:1334
#define MSC_READCTRL_MODE_WS1
Definition: efm32g_msc.h:89
#define _ROMTABLE_PID2_REVMINORMSB_MASK
#define _CMU_LFRCOCTRL_TUNING_SHIFT
Definition: efm32g_cmu.h:285
#define _CMU_STATUS_HFXOENS_SHIFT
Definition: efm32g_cmu.h:441
#define _DEVINFO_HFRCOCAL1_BAND21_MASK
#define _DEVINFO_HFRCOCAL0_BAND7_SHIFT
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
Definition: em_cmu.c:3584
#define CMU_LFACLKEN0_LCD
Definition: efm32g_cmu.h:795
__STATIC_INLINE SYSTEM_PartFamily_TypeDef SYSTEM_GetFamily(void)
Get family identifier of the MCU.
Definition: em_system.h:364
#define MSC
#define _CMU_STATUS_HFRCOENS_SHIFT
Definition: efm32g_cmu.h:431
#define CMU_STATUS_LFRCOSEL
Definition: efm32g_cmu.h:490
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0
Definition: efm32g_cmu.h:937
#define _DEVINFO_HFRCOCAL1_BAND28_SHIFT
#define _CMU_LFBPRESC0_LEUART0_SHIFT
Definition: efm32g_cmu.h:900
#define CMU_OSCENCMD_LFRCOEN
Definition: efm32g_cmu.h:357
#define PCNT_COUNT
#define CMU_HFCORECLKEN0_LE
Definition: efm32g_cmu.h:655
uint32_t SystemHFClockGet(void)
Get the current HFCLK frequency.
#define cmuClkDiv_32768
Definition: em_cmu.h:163
#define CMU_SYNCBUSY_LFBCLKEN0
Definition: efm32g_cmu.h:758
uint32_t SystemMaxCoreClockGet(void)
Get the maximum core clock frequency.
#define CMU_CMD_HFCLKSEL_LFXO
Definition: efm32g_cmu.h:392
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
Get HFRCO band in use.
Definition: em_cmu.c:2889
#define CMU_CMD_HFCLKSEL_LFRCO
Definition: efm32g_cmu.h:391
#define _CMU_LFBPRESC0_LEUART1_MASK
Definition: efm32g_cmu.h:911
#define _CMU_STATUS_LFRCOENS_SHIFT
Definition: efm32g_cmu.h:461
#define _CMU_HFCORECLKEN0_LE_SHIFT
Definition: efm32g_cmu.h:656
#define CMU_OSCENCMD_LFRCODIS
Definition: efm32g_cmu.h:362
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
Definition: em_cmu.c:3295
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
Definition: em_cmu.h:1196
#define CMU_OSCENCMD_LFXOEN
Definition: efm32g_cmu.h:367
CMU_Clock_TypeDef
Definition: em_cmu.h:256
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
Definition: em_cmu.c:969
#define cmuClkDiv_16
Definition: em_cmu.h:152
#define ROMTABLE
#define _CMU_STATUS_HFRCORDY_SHIFT
Definition: efm32g_cmu.h:436
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
Definition: em_cmu.c:1369
#define CMU_OSCENCMD_HFRCOEN
Definition: efm32g_cmu.h:327
#define _CMU_HFRCOCTRL_SUDELAY_SHIFT
Definition: efm32g_cmu.h:277
#define _CMU_LFCLKSEL_LFA_MASK
Definition: efm32g_cmu.h:403
#define CMU_OSCENCMD_HFXOEN
Definition: efm32g_cmu.h:337
CMU_HFRCOBand_TypeDef
Definition: em_cmu.h:175
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
Definition: em_cmu.c:3318
#define _CMU_LFCLKSEL_LFA_LFXO
Definition: efm32g_cmu.h:407
uint32_t SystemHFXOClockGet(void)
Get high frequency crystal oscillator clock frequency for target system.
#define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK
Definition: efm32g_cmu.h:197
#define _CMU_LFAPRESC0_LETIMER0_MASK
Definition: efm32g_cmu.h:853
#define _CMU_LCDCTRL_FDIV_MASK
Definition: efm32g_cmu.h:971
#define CMU_SYNCBUSY_LFBPRESC0
Definition: efm32g_cmu.h:763
void CMU_HFRCOStartupDelaySet(uint32_t delay)
Set the HFRCO startup delay.
Definition: em_cmu.c:3132
#define _CMU_LFRCOCTRL_TUNING_MASK
Definition: efm32g_cmu.h:286
#define _CMU_STATUS_LFXORDY_SHIFT
Definition: efm32g_cmu.h:476
#define cmuClkDiv_128
Definition: em_cmu.h:155
#define _CMU_LFCLKSEL_LFB_SHIFT
Definition: efm32g_cmu.h:414
#define _DEVINFO_HFRCOCAL0_BAND11_SHIFT
#define _MSC_READCTRL_MODE_MASK
Definition: efm32g_msc.h:81
__STATIC_INLINE uint32_t BUS_RegMaskedRead(volatile const uint32_t *addr, uint32_t mask)
Perform a peripheral register masked read.
Definition: em_bus.h:313
#define _DEVINFO_HFRCOCAL0_BAND1_SHIFT
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
Definition: em_cmu.c:3394
Energy management unit (EMU) peripheral API.
#define CMU_CMD_CALSTART
Definition: efm32g_cmu.h:393
#define _CMU_STATUS_LFRCORDY_SHIFT
Definition: efm32g_cmu.h:466
#define CMU
#define _DEVINFO_HFRCOCAL0_BAND14_SHIFT
#define _ROMTABLE_PID3_REVMINORLSB_MASK
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
Definition: em_bus.h:283
#define CMU_LFCLKSEL_LFB_LFRCO
Definition: efm32g_cmu.h:423
#define cmuClkDiv_1
Definition: em_cmu.h:148
CMU_Osc_TypeDef
Definition: em_cmu.h:933
#define MSC_UNLOCK_CODE
#define CMU_CALCTRL_UPSEL_HFXO
Definition: efm32g_cmu.h:310
#define CMU_LFCLKSEL_LFA_LFXO
Definition: efm32g_cmu.h:412
#define _CMU_HFRCOCTRL_BAND_SHIFT
Definition: efm32g_cmu.h:261
#define _CMU_LFCLKSEL_LFA_LFRCO
Definition: efm32g_cmu.h:406
#define CMU_OSCENCMD_HFXODIS
Definition: efm32g_cmu.h:342
System API.
#define CMU_OSCENCMD_LFXODIS
Definition: efm32g_cmu.h:372
#define _DEVINFO_HFRCOCAL0_BAND14_MASK
#define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT
Definition: efm32g_cmu.h:224
#define MSC_READCTRL_MODE_WS1SCBTP
Definition: efm32g_msc.h:91
#define _ROMTABLE_PID3_REVMINORLSB_SHIFT
#define CMU_CMD_HFCLKSEL_HFXO
Definition: efm32g_cmu.h:390
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2
Definition: efm32g_cmu.h:413
#define _CMU_LFAPRESC0_RTC_MASK
Definition: efm32g_cmu.h:819
#define cmuClkDiv_512
Definition: em_cmu.h:157
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
Definition: em_cmu.c:3535
#define _CMU_LFBPRESC0_LEUART0_MASK
Definition: efm32g_cmu.h:901
#define _CMU_HFRCOCTRL_TUNING_MASK
Definition: efm32g_cmu.h:258
#define _CMU_HFRCOCTRL_SUDELAY_MASK
Definition: efm32g_cmu.h:278
#define _CMU_LFAPRESC0_LCD_MASK
Definition: efm32g_cmu.h:887
#define _DEVINFO_HFRCOCAL1_BAND28_MASK
#define CMU_CMD_HFCLKSEL_HFRCO
Definition: efm32g_cmu.h:389
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
Set HFRCO band and the tuning value based on the value in the calibration table made during productio...
Definition: em_cmu.c:2906
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
Definition: em_cmu.c:3643
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
Definition: em_cmu.c:1482
#define CMU_STATUS_HFRCOSEL
Definition: efm32g_cmu.h:480
uint32_t SystemULFRCOClockGet(void)
Get ultra low frequency RC oscillator clock frequency for target system.
#define MSC_READCTRL_MODE_WS0SCBTP
Definition: efm32g_msc.h:90
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
Definition: em_emu.c:736
#define CMU_SYNCBUSY_LFAPRESC0
Definition: efm32g_cmu.h:753
#define _CMU_CALCNT_CALCNT_SHIFT
Definition: efm32g_cmu.h:319
#define _DEVINFO_HFRCOCAL0_BAND11_MASK
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
Definition: em_cmu.c:1141
#define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0
Definition: efm32g_cmu.h:951
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
Definition: em_cmu.c:1009
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.
Definition: em_cmu.c:2048
#define _CMU_AUXHFRCOCTRL_TUNING_SHIFT
Definition: efm32g_cmu.h:293
#define _CMU_LFCLKSEL_LFB_MASK
Definition: efm32g_cmu.h:415
#define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0
Definition: efm32g_cmu.h:965