33 #ifndef __SILICON_LABS_EM_MSC_H__
34 #define __SILICON_LABS_EM_MSC_H__
37 #if defined(MSC_COUNT) && (MSC_COUNT > 0)
72 #define MSC_PROGRAM_TIMEOUT 10000000ul
86 #if defined( DOXY_DOC_ONLY )
87 #define EM_MSC_RUN_FROM_FLASH
107 #if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
111 mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU,
112 mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA,
113 mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1,
114 mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE
115 } MSC_BusStrategy_Typedef;
130 #define MSC_EXECCONFIG_DEFAULT \
142 #define mscBusStrategy_Typedef MSC_BusStrategy_Typedef
143 #define msc_Return_TypeDef MSC_Status_TypeDef
152 #if !defined( _EFM32_GECKO_FAMILY )
179 MSC->IEN &= ~(flags);
238 return MSC->IF & ien;
256 #if defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF )
264 __STATIC_INLINE
void MSC_StartCacheMeasurement(
void)
267 MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF;
270 #if defined( _MSC_CACHECMD_MASK )
271 MSC->CACHECMD = MSC_CACHECMD_STARTPC;
273 MSC->CMD = MSC_CMD_STARTPC;
325 __STATIC_INLINE int32_t MSC_GetCacheMeasurement(
void)
329 #if defined( _MSC_CACHECMD_MASK )
330 MSC->CACHECMD = MSC_CACHECMD_STOPPC;
332 MSC->CMD = MSC_CMD_STOPPC;
336 if (
MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
342 total =
MSC->CACHEHITS;
343 total +=
MSC->CACHEMISSES;
349 return (
MSC->CACHEHITS * 100) / total;
357 __STATIC_INLINE
void MSC_FlushCache(
void)
359 #if defined( _MSC_CACHECMD_MASK )
360 MSC->CACHECMD = MSC_CACHECMD_INVCACHE;
362 MSC->CMD = MSC_CMD_INVCACHE;
373 __STATIC_INLINE
void MSC_EnableCache(
bool enable)
379 #if defined( MSC_READCTRL_ICCDIS )
386 __STATIC_INLINE
void MSC_EnableCacheIRQs(
bool enable)
399 __STATIC_INLINE
void MSC_EnableAutoCacheFlush(
bool enable)
406 #if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
413 __STATIC_INLINE
void MSC_BusStrategy(mscBusStrategy_Typedef mode)
415 MSC->READCTRL = (
MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode;
419 #if defined(EM_MSC_RUN_FROM_FLASH)
420 #define MSC_FUNC_PREFIX
421 #define MSC_FUNC_POSTFIX
422 #elif defined(__CC_ARM)
423 #define MSC_FUNC_PREFIX
424 #define MSC_FUNC_POSTFIX
425 #elif defined(__ICCARM__)
426 #define MSC_FUNC_PREFIX __ramfunc
427 #define MSC_FUNC_POSTFIX
428 #elif defined(__GNUC__) && defined(__CROSSWORKS_ARM)
429 #define MSC_FUNC_PREFIX
430 #define MSC_FUNC_POSTFIX __attribute__ ((section(".fast")))
431 #elif defined(__GNUC__)
432 #define MSC_FUNC_PREFIX
433 #define MSC_FUNC_POSTFIX __attribute__ ((section(".ram")))
440 uint32_t numBytes) MSC_FUNC_POSTFIX;
442 #if !defined( _EFM32_GECKO_FAMILY )
444 MSC_WriteWordFast(uint32_t *address,
446 uint32_t numBytes) MSC_FUNC_POSTFIX;
453 #if defined( _MSC_MASSLOCK_MASK )
__STATIC_INLINE uint32_t MSC_IntGetEnabled(void)
Get enabled and pending MSC interrupt flags. Useful for handling more interrupt sources in the same i...
RAM and peripheral bit-field set and clear API.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
void MSC_Init(void)
Enables the flash controller for writing.
void MSC_Deinit(void)
Disables the flash controller for writing.
__STATIC_INLINE void MSC_IntSet(uint32_t flags)
Set one or more pending MSC interrupts from SW.
MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) MSC_FUNC_POSTFIX
Erases a page in flash memory.
__STATIC_INLINE void MSC_IntEnable(uint32_t flags)
Enable one or more MSC interrupts.
__STATIC_INLINE uint32_t MSC_IntGet(void)
Get pending MSC interrupt flags.
__STATIC_INLINE void MSC_IntClear(uint32_t flags)
Clear one or more pending MSC interrupts.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
__STATIC_INLINE void MSC_IntDisable(uint32_t flags)
Disable one or more MSC interrupts.
MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) MSC_FUNC_POSTFIX
Writes data to flash memory. This function is interrupt safe, but slower than MSC_WriteWordFast(), which writes to flash with interrupts disabled. Write data must be aligned to words and contain a number of bytes that is divisable by four.