release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg308f64.h

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00001 /**************************************************************************/
00034 #ifndef __SILICON_LABS_EFM32HG308F64_H__
00035 #define __SILICON_LABS_EFM32HG308F64_H__
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
00055   NonMaskableInt_IRQn = -14,                
00056   HardFault_IRQn      = -13,                
00057   SVCall_IRQn         = -5,                 
00058   PendSV_IRQn         = -2,                 
00059   SysTick_IRQn        = -1,                 
00061 /******  EFM32HG Peripheral Interrupt Numbers *********************************************/
00062   DMA_IRQn            = 0,  
00063   GPIO_EVEN_IRQn      = 1,  
00064   TIMER0_IRQn         = 2,  
00065   ACMP0_IRQn          = 3,  
00066   I2C0_IRQn           = 5,  
00067   GPIO_ODD_IRQn       = 6,  
00068   TIMER1_IRQn         = 7,  
00069   USART1_RX_IRQn      = 8,  
00070   USART1_TX_IRQn      = 9,  
00071   LEUART0_IRQn        = 10, 
00072   PCNT0_IRQn          = 11, 
00073   RTC_IRQn            = 12, 
00074   CMU_IRQn            = 13, 
00075   VCMP_IRQn           = 14, 
00076   MSC_IRQn            = 15, 
00077   USART0_RX_IRQn      = 17, 
00078   USART0_TX_IRQn      = 18, 
00079   USB_IRQn            = 19, 
00080   TIMER2_IRQn         = 20, 
00081 } IRQn_Type;
00082 
00083 /**************************************************************************/
00088 #define __MPU_PRESENT             0 
00089 #define __VTOR_PRESENT            1 
00090 #define __NVIC_PRIO_BITS          2 
00091 #define __Vendor_SysTickConfig    0 
00095 /**************************************************************************/
00101 #define _EFM32_HAPPY_FAMILY             1 
00102 #define _EFM_DEVICE                       
00103 #define _SILICON_LABS_32B_PLATFORM_1      
00104 #define _SILICON_LABS_32B_PLATFORM      1 
00106 /* If part number is not defined as compiler option, define it */
00107 #if !defined(EFM32HG308F64)
00108 #define EFM32HG308F64    1 
00109 #endif
00110 
00112 #define PART_NUMBER          "EFM32HG308F64" 
00115 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00116 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00117 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00118 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00119 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00120 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00121 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00122 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00123 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL) 
00124 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)    
00125 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL) 
00126 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)       
00127 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00128 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00129 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00130 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00131 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00132 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00133 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00134 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00135 #define DEVICE_MEM_BASE      ((uint32_t) 0xF0040000UL) 
00136 #define DEVICE_MEM_SIZE      ((uint32_t) 0x1000UL)     
00137 #define DEVICE_MEM_END       ((uint32_t) 0xF0040FFFUL) 
00138 #define DEVICE_MEM_BITS      ((uint32_t) 0x12UL)       
00139 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00140 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00141 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00142 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00145 #define FLASH_BASE           (0x00000000UL) 
00146 #define FLASH_SIZE           (0x00010000UL) 
00147 #define FLASH_PAGE_SIZE      1024           
00148 #define SRAM_BASE            (0x20000000UL) 
00149 #define SRAM_SIZE            (0x00002000UL) 
00150 #define __CM0PLUS_REV        0x001          
00151 #define PRS_CHAN_COUNT       6              
00152 #define DMA_CHAN_COUNT       6              
00155 #define AFCHAN_MAX           42
00156 #define AFCHANLOC_MAX        7
00157 
00158 #define AFACHAN_MAX          27
00159 
00160 /* Part number capabilities */
00161 
00162 #define TIMER_PRESENT         
00163 #define TIMER_COUNT         3 
00164 #define ACMP_PRESENT          
00165 #define ACMP_COUNT          1 
00166 #define USART_PRESENT         
00167 #define USART_COUNT         2 
00168 #define LEUART_PRESENT        
00169 #define LEUART_COUNT        1 
00170 #define PCNT_PRESENT          
00171 #define PCNT_COUNT          1 
00172 #define I2C_PRESENT           
00173 #define I2C_COUNT           1 
00174 #define DMA_PRESENT
00175 #define DMA_COUNT           1
00176 #define LE_PRESENT
00177 #define LE_COUNT            1
00178 #define USBC_PRESENT
00179 #define USBC_COUNT          1
00180 #define USBLE_PRESENT
00181 #define USBLE_COUNT         1
00182 #define USB_PRESENT
00183 #define USB_COUNT           1
00184 #define MSC_PRESENT
00185 #define MSC_COUNT           1
00186 #define EMU_PRESENT
00187 #define EMU_COUNT           1
00188 #define RMU_PRESENT
00189 #define RMU_COUNT           1
00190 #define CMU_PRESENT
00191 #define CMU_COUNT           1
00192 #define PRS_PRESENT
00193 #define PRS_COUNT           1
00194 #define GPIO_PRESENT
00195 #define GPIO_COUNT          1
00196 #define VCMP_PRESENT
00197 #define VCMP_COUNT          1
00198 #define RTC_PRESENT
00199 #define RTC_COUNT           1
00200 #define HFXTAL_PRESENT
00201 #define HFXTAL_COUNT        1
00202 #define LFXTAL_PRESENT
00203 #define LFXTAL_COUNT        1
00204 #define USHFRCO_PRESENT
00205 #define USHFRCO_COUNT       1
00206 #define WDOG_PRESENT
00207 #define WDOG_COUNT          1
00208 #define DBG_PRESENT
00209 #define DBG_COUNT           1
00210 #define MTB_PRESENT
00211 #define MTB_COUNT           1
00212 #define BOOTLOADER_PRESENT
00213 #define BOOTLOADER_COUNT    1
00214 #define ANALOG_PRESENT
00215 #define ANALOG_COUNT        1
00216 
00219 #define ARM_MATH_CM0PLUS
00220 #include "arm_math.h"       /* To get __CLZ definitions etc. */
00221 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
00222 #include "system_efm32hg.h" /* System Header */
00223 
00224 /**************************************************************************/
00230 #include "efm32hg_dma_ch.h"
00231 
00232 /**************************************************************************/
00237 typedef struct
00238 {
00239   __I uint32_t   STATUS;         
00240   __O uint32_t   CONFIG;         
00241   __IO uint32_t  CTRLBASE;       
00242   __I uint32_t   ALTCTRLBASE;    
00243   __I uint32_t   CHWAITSTATUS;   
00244   __O uint32_t   CHSWREQ;        
00245   __IO uint32_t  CHUSEBURSTS;    
00246   __O uint32_t   CHUSEBURSTC;    
00247   __IO uint32_t  CHREQMASKS;     
00248   __O uint32_t   CHREQMASKC;     
00249   __IO uint32_t  CHENS;          
00250   __O uint32_t   CHENC;          
00251   __IO uint32_t  CHALTS;         
00252   __O uint32_t   CHALTC;         
00253   __IO uint32_t  CHPRIS;         
00254   __O uint32_t   CHPRIC;         
00255   uint32_t       RESERVED0[3];   
00256   __IO uint32_t  ERRORC;         
00258   uint32_t       RESERVED1[880]; 
00259   __I uint32_t   CHREQSTATUS;    
00260   uint32_t       RESERVED2[1];   
00261   __I uint32_t   CHSREQSTATUS;   
00263   uint32_t       RESERVED3[121]; 
00264   __I uint32_t   IF;             
00265   __IO uint32_t  IFS;            
00266   __IO uint32_t  IFC;            
00267   __IO uint32_t  IEN;            
00269   uint32_t       RESERVED4[60];  
00270   DMA_CH_TypeDef CH[6];          
00271 } DMA_TypeDef;                   
00273 #include "efm32hg_usb_diep.h"
00274 #include "efm32hg_usb_doep.h"
00275 #include "efm32hg_usb.h"
00276 #include "efm32hg_msc.h"
00277 #include "efm32hg_emu.h"
00278 #include "efm32hg_rmu.h"
00279 
00280 /**************************************************************************/
00285 typedef struct
00286 {
00287   __IO uint32_t CTRL;          
00288   __IO uint32_t HFCORECLKDIV;  
00289   __IO uint32_t HFPERCLKDIV;   
00290   __IO uint32_t HFRCOCTRL;     
00291   __IO uint32_t LFRCOCTRL;     
00292   __IO uint32_t AUXHFRCOCTRL;  
00293   __IO uint32_t CALCTRL;       
00294   __IO uint32_t CALCNT;        
00295   __IO uint32_t OSCENCMD;      
00296   __IO uint32_t CMD;           
00297   __IO uint32_t LFCLKSEL;      
00298   __I uint32_t  STATUS;        
00299   __I uint32_t  IF;            
00300   __IO uint32_t IFS;           
00301   __IO uint32_t IFC;           
00302   __IO uint32_t IEN;           
00303   __IO uint32_t HFCORECLKEN0;  
00304   __IO uint32_t HFPERCLKEN0;   
00305   uint32_t      RESERVED0[2];  
00306   __I uint32_t  SYNCBUSY;      
00307   __IO uint32_t FREEZE;        
00308   __IO uint32_t LFACLKEN0;     
00309   uint32_t      RESERVED1[1];  
00310   __IO uint32_t LFBCLKEN0;     
00311   __IO uint32_t LFCCLKEN0;     
00312   __IO uint32_t LFAPRESC0;     
00313   uint32_t      RESERVED2[1];  
00314   __IO uint32_t LFBPRESC0;     
00315   uint32_t      RESERVED3[1];  
00316   __IO uint32_t PCNTCTRL;      
00318   uint32_t      RESERVED4[1];  
00319   __IO uint32_t ROUTE;         
00320   __IO uint32_t LOCK;          
00322   uint32_t      RESERVED5[18]; 
00323   __IO uint32_t USBCRCTRL;     
00324   __IO uint32_t USHFRCOCTRL;   
00325   __IO uint32_t USHFRCOTUNE;   
00326   __IO uint32_t USHFRCOCONF;   
00327 } CMU_TypeDef;                 
00329 #include "efm32hg_timer_cc.h"
00330 #include "efm32hg_timer.h"
00331 #include "efm32hg_acmp.h"
00332 #include "efm32hg_usart.h"
00333 #include "efm32hg_prs_ch.h"
00334 
00335 /**************************************************************************/
00340 typedef struct
00341 {
00342   __IO uint32_t  SWPULSE;      
00343   __IO uint32_t  SWLEVEL;      
00344   __IO uint32_t  ROUTE;        
00346   uint32_t       RESERVED0[1]; 
00347   PRS_CH_TypeDef CH[6];        
00349   uint32_t       RESERVED1[6]; 
00350   __IO uint32_t  TRACECTRL;    
00351 } PRS_TypeDef;                 
00353 #include "efm32hg_gpio_p.h"
00354 #include "efm32hg_gpio.h"
00355 #include "efm32hg_vcmp.h"
00356 #include "efm32hg_leuart.h"
00357 #include "efm32hg_pcnt.h"
00358 #include "efm32hg_i2c.h"
00359 #include "efm32hg_rtc.h"
00360 #include "efm32hg_wdog.h"
00361 #include "efm32hg_mtb.h"
00362 #include "efm32hg_dma_descriptor.h"
00363 #include "efm32hg_devinfo.h"
00364 #include "efm32hg_romtable.h"
00365 #include "efm32hg_calibrate.h"
00366 
00369 /**************************************************************************/
00374 #define DMA_BASE          (0x400C2000UL) 
00375 #define USB_BASE          (0x400C4000UL) 
00376 #define MSC_BASE          (0x400C0000UL) 
00377 #define EMU_BASE          (0x400C6000UL) 
00378 #define RMU_BASE          (0x400CA000UL) 
00379 #define CMU_BASE          (0x400C8000UL) 
00380 #define TIMER0_BASE       (0x40010000UL) 
00381 #define TIMER1_BASE       (0x40010400UL) 
00382 #define TIMER2_BASE       (0x40010800UL) 
00383 #define ACMP0_BASE        (0x40001000UL) 
00384 #define USART0_BASE       (0x4000C000UL) 
00385 #define USART1_BASE       (0x4000C400UL) 
00386 #define PRS_BASE          (0x400CC000UL) 
00387 #define GPIO_BASE         (0x40006000UL) 
00388 #define VCMP_BASE         (0x40000000UL) 
00389 #define LEUART0_BASE      (0x40084000UL) 
00390 #define PCNT0_BASE        (0x40086000UL) 
00391 #define I2C0_BASE         (0x4000A000UL) 
00392 #define RTC_BASE          (0x40080000UL) 
00393 #define WDOG_BASE         (0x40088000UL) 
00394 #define MTB_BASE          (0xF0040000UL) 
00395 #define CALIBRATE_BASE    (0x0FE08000UL) 
00396 #define DEVINFO_BASE      (0x0FE081B0UL) 
00397 #define ROMTABLE_BASE     (0xF00FFFD0UL) 
00398 #define LOCKBITS_BASE     (0x0FE04000UL) 
00399 #define USERDATA_BASE     (0x0FE00000UL) 
00403 /**************************************************************************/
00408 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00409 #define USB          ((USB_TypeDef *) USB_BASE)             
00410 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00411 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00412 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00413 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00414 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00415 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00416 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        
00417 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00418 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00419 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00420 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00421 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00422 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00423 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00424 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00425 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00426 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00427 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00428 #define MTB          ((MTB_TypeDef *) MTB_BASE)             
00429 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00430 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00431 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00435 /**************************************************************************/
00440 /**************************************************************************/
00445 #define PRS_VCMP_OUT          ((1 << 16) + 0)  
00446 #define PRS_ACMP0_OUT         ((2 << 16) + 0)  
00447 #define PRS_USART0_IRTX       ((16 << 16) + 0) 
00448 #define PRS_USART0_TXC        ((16 << 16) + 1) 
00449 #define PRS_USART0_RXDATAV    ((16 << 16) + 2) 
00450 #define PRS_USART1_IRTX       ((17 << 16) + 0) 
00451 #define PRS_USART1_TXC        ((17 << 16) + 1) 
00452 #define PRS_USART1_RXDATAV    ((17 << 16) + 2) 
00453 #define PRS_TIMER0_UF         ((28 << 16) + 0) 
00454 #define PRS_TIMER0_OF         ((28 << 16) + 1) 
00455 #define PRS_TIMER0_CC0        ((28 << 16) + 2) 
00456 #define PRS_TIMER0_CC1        ((28 << 16) + 3) 
00457 #define PRS_TIMER0_CC2        ((28 << 16) + 4) 
00458 #define PRS_TIMER1_UF         ((29 << 16) + 0) 
00459 #define PRS_TIMER1_OF         ((29 << 16) + 1) 
00460 #define PRS_TIMER1_CC0        ((29 << 16) + 2) 
00461 #define PRS_TIMER1_CC1        ((29 << 16) + 3) 
00462 #define PRS_TIMER1_CC2        ((29 << 16) + 4) 
00463 #define PRS_TIMER2_UF         ((30 << 16) + 0) 
00464 #define PRS_TIMER2_OF         ((30 << 16) + 1) 
00465 #define PRS_TIMER2_CC0        ((30 << 16) + 2) 
00466 #define PRS_TIMER2_CC1        ((30 << 16) + 3) 
00467 #define PRS_TIMER2_CC2        ((30 << 16) + 4) 
00468 #define PRS_USB_SOF           ((36 << 16) + 0) 
00469 #define PRS_USB_SOFSR         ((36 << 16) + 1) 
00470 #define PRS_RTC_OF            ((40 << 16) + 0) 
00471 #define PRS_RTC_COMP0         ((40 << 16) + 1) 
00472 #define PRS_RTC_COMP1         ((40 << 16) + 2) 
00473 #define PRS_GPIO_PIN0         ((48 << 16) + 0) 
00474 #define PRS_GPIO_PIN1         ((48 << 16) + 1) 
00475 #define PRS_GPIO_PIN2         ((48 << 16) + 2) 
00476 #define PRS_GPIO_PIN3         ((48 << 16) + 3) 
00477 #define PRS_GPIO_PIN4         ((48 << 16) + 4) 
00478 #define PRS_GPIO_PIN5         ((48 << 16) + 5) 
00479 #define PRS_GPIO_PIN6         ((48 << 16) + 6) 
00480 #define PRS_GPIO_PIN7         ((48 << 16) + 7) 
00481 #define PRS_GPIO_PIN8         ((49 << 16) + 0) 
00482 #define PRS_GPIO_PIN9         ((49 << 16) + 1) 
00483 #define PRS_GPIO_PIN10        ((49 << 16) + 2) 
00484 #define PRS_GPIO_PIN11        ((49 << 16) + 3) 
00485 #define PRS_GPIO_PIN12        ((49 << 16) + 4) 
00486 #define PRS_GPIO_PIN13        ((49 << 16) + 5) 
00487 #define PRS_GPIO_PIN14        ((49 << 16) + 6) 
00488 #define PRS_GPIO_PIN15        ((49 << 16) + 7) 
00489 #define PRS_PCNT0_TCC         ((54 << 16) + 0) 
00493 #include "efm32hg_dmareq.h"
00494 #include "efm32hg_dmactrl.h"
00495 
00496 /**************************************************************************/
00501 /* Bit fields for DMA STATUS */
00502 #define _DMA_STATUS_RESETVALUE                          0x10050000UL                          
00503 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00504 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00505 #define _DMA_STATUS_EN_SHIFT                            0                                     
00506 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00507 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00508 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00509 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00510 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00511 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00512 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00513 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00514 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00515 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00516 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00517 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00518 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00519 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00520 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00521 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00522 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00523 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00524 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00525 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00526 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00527 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00528 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00529 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00530 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00531 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00532 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00533 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00534 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00535 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00536 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00537 #define _DMA_STATUS_CHNUM_DEFAULT                       0x00000005UL                          
00538 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00540 /* Bit fields for DMA CONFIG */
00541 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00542 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00543 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00544 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00545 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00546 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00547 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00548 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00549 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00550 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00551 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00552 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00554 /* Bit fields for DMA CTRLBASE */
00555 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00556 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00557 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00558 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00559 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00560 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00562 /* Bit fields for DMA ALTCTRLBASE */
00563 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000080UL                                
00564 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00565 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00566 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00567 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000080UL                                
00568 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00570 /* Bit fields for DMA CHWAITSTATUS */
00571 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x0000003FUL                                   
00572 #define _DMA_CHWAITSTATUS_MASK                          0x0000003FUL                                   
00573 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   
00574 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              
00575 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          
00576 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   
00577 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 
00578 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   
00579 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              
00580 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          
00581 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   
00582 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 
00583 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   
00584 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              
00585 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          
00586 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   
00587 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 
00588 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   
00589 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              
00590 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          
00591 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   
00592 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 
00593 #define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                   
00594 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                              
00595 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                         
00596 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                   
00597 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) 
00598 #define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                   
00599 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                              
00600 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                         
00601 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                   
00602 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) 
00604 /* Bit fields for DMA CHSWREQ */
00605 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         
00606 #define _DMA_CHSWREQ_MASK                               0x0000003FUL                         
00607 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         
00608 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    
00609 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                
00610 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         
00611 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 
00612 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         
00613 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    
00614 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                
00615 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         
00616 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 
00617 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         
00618 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    
00619 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                
00620 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         
00621 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 
00622 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         
00623 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    
00624 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                
00625 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         
00626 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 
00627 #define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                         
00628 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                    
00629 #define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                               
00630 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                         
00631 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) 
00632 #define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                         
00633 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                    
00634 #define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                               
00635 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                         
00636 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) 
00638 /* Bit fields for DMA CHUSEBURSTS */
00639 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00640 #define _DMA_CHUSEBURSTS_MASK                           0x0000003FUL                                        
00641 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00642 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00643 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00644 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00645 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00646 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00647 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00648 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00649 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00650 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00651 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00652 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00653 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00654 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00655 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00656 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00657 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00658 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00659 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00660 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00661 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00662 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00663 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00664 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00665 #define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        
00666 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   
00667 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              
00668 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        
00669 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        
00670 #define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        
00671 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   
00672 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              
00673 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        
00674 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        
00676 /* Bit fields for DMA CHUSEBURSTC */
00677 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 
00678 #define _DMA_CHUSEBURSTC_MASK                           0x0000003FUL                                 
00679 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 
00680 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            
00681 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        
00682 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 
00683 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 
00684 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 
00685 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            
00686 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        
00687 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 
00688 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 
00689 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 
00690 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            
00691 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        
00692 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 
00693 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 
00694 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 
00695 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            
00696 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        
00697 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 
00698 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 
00699 #define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                 
00700 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                            
00701 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                       
00702 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                 
00703 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) 
00704 #define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                 
00705 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                            
00706 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                       
00707 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                 
00708 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) 
00710 /* Bit fields for DMA CHREQMASKS */
00711 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               
00712 #define _DMA_CHREQMASKS_MASK                            0x0000003FUL                               
00713 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               
00714 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          
00715 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      
00716 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               
00717 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 
00718 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               
00719 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          
00720 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      
00721 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               
00722 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 
00723 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               
00724 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          
00725 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      
00726 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               
00727 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 
00728 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               
00729 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          
00730 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      
00731 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               
00732 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 
00733 #define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                               
00734 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                          
00735 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                     
00736 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                               
00737 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) 
00738 #define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                               
00739 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                          
00740 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                     
00741 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                               
00742 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) 
00744 /* Bit fields for DMA CHREQMASKC */
00745 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               
00746 #define _DMA_CHREQMASKC_MASK                            0x0000003FUL                               
00747 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               
00748 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          
00749 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      
00750 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               
00751 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 
00752 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               
00753 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          
00754 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      
00755 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               
00756 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 
00757 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               
00758 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          
00759 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      
00760 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               
00761 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 
00762 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               
00763 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          
00764 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      
00765 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               
00766 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 
00767 #define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                               
00768 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                          
00769 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                     
00770 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                               
00771 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) 
00772 #define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                               
00773 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                          
00774 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                     
00775 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                               
00776 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) 
00778 /* Bit fields for DMA CHENS */
00779 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                     
00780 #define _DMA_CHENS_MASK                                 0x0000003FUL                     
00781 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     
00782 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                
00783 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            
00784 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     
00785 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) 
00786 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     
00787 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                
00788 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            
00789 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     
00790 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) 
00791 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     
00792 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                
00793 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            
00794 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     
00795 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) 
00796 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     
00797 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                
00798 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            
00799 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     
00800 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) 
00801 #define DMA_CHENS_CH4ENS                                (0x1UL << 4)                     
00802 #define _DMA_CHENS_CH4ENS_SHIFT                         4                                
00803 #define _DMA_CHENS_CH4ENS_MASK                          0x10UL                           
00804 #define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                     
00805 #define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4) 
00806 #define DMA_CHENS_CH5ENS                                (0x1UL << 5)                     
00807 #define _DMA_CHENS_CH5ENS_SHIFT                         5                                
00808 #define _DMA_CHENS_CH5ENS_MASK                          0x20UL                           
00809 #define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                     
00810 #define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5) 
00812 /* Bit fields for DMA CHENC */
00813 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                     
00814 #define _DMA_CHENC_MASK                                 0x0000003FUL                     
00815 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     
00816 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                
00817 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            
00818 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     
00819 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) 
00820 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     
00821 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                
00822 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            
00823 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     
00824 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) 
00825 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     
00826 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                
00827 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            
00828 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     
00829 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) 
00830 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     
00831 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                
00832 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            
00833 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     
00834 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) 
00835 #define DMA_CHENC_CH4ENC                                (0x1UL << 4)                     
00836 #define _DMA_CHENC_CH4ENC_SHIFT                         4                                
00837 #define _DMA_CHENC_CH4ENC_MASK                          0x10UL                           
00838 #define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                     
00839 #define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4) 
00840 #define DMA_CHENC_CH5ENC                                (0x1UL << 5)                     
00841 #define _DMA_CHENC_CH5ENC_SHIFT                         5                                
00842 #define _DMA_CHENC_CH5ENC_MASK                          0x20UL                           
00843 #define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                     
00844 #define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5) 
00846 /* Bit fields for DMA CHALTS */
00847 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       
00848 #define _DMA_CHALTS_MASK                                0x0000003FUL                       
00849 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       
00850 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  
00851 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              
00852 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       
00853 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 
00854 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       
00855 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  
00856 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              
00857 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       
00858 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 
00859 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       
00860 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  
00861 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              
00862 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       
00863 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 
00864 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       
00865 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  
00866 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              
00867 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       
00868 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 
00869 #define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                       
00870 #define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                  
00871 #define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                             
00872 #define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                       
00873 #define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) 
00874 #define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                       
00875 #define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                  
00876 #define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                             
00877 #define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                       
00878 #define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) 
00880 /* Bit fields for DMA CHALTC */
00881 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       
00882 #define _DMA_CHALTC_MASK                                0x0000003FUL                       
00883 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       
00884 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  
00885 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              
00886 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       
00887 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 
00888 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       
00889 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  
00890 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              
00891 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       
00892 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 
00893 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       
00894 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  
00895 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              
00896 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       
00897 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 
00898 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       
00899 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  
00900 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              
00901 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       
00902 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 
00903 #define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                       
00904 #define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                  
00905 #define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                             
00906 #define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                       
00907 #define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) 
00908 #define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                       
00909 #define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                  
00910 #define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                             
00911 #define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                       
00912 #define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) 
00914 /* Bit fields for DMA CHPRIS */
00915 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       
00916 #define _DMA_CHPRIS_MASK                                0x0000003FUL                       
00917 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       
00918 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  
00919 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              
00920 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       
00921 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 
00922 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       
00923 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  
00924 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              
00925 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       
00926 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 
00927 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       
00928 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  
00929 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              
00930 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       
00931 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 
00932 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       
00933 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  
00934 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              
00935 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       
00936 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 
00937 #define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                       
00938 #define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                  
00939 #define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                             
00940 #define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                       
00941 #define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) 
00942 #define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                       
00943 #define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                  
00944 #define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                             
00945 #define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                       
00946 #define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) 
00948 /* Bit fields for DMA CHPRIC */
00949 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       
00950 #define _DMA_CHPRIC_MASK                                0x0000003FUL                       
00951 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       
00952 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  
00953 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              
00954 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       
00955 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 
00956 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       
00957 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  
00958 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              
00959 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       
00960 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 
00961 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       
00962 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  
00963 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              
00964 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       
00965 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 
00966 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       
00967 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  
00968 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              
00969 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       
00970 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 
00971 #define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                       
00972 #define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                  
00973 #define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                             
00974 #define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                       
00975 #define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) 
00976 #define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                       
00977 #define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                  
00978 #define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                             
00979 #define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                       
00980 #define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) 
00982 /* Bit fields for DMA ERRORC */
00983 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
00984 #define _DMA_ERRORC_MASK                                0x00000001UL                      
00985 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
00986 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
00987 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
00988 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
00989 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
00991 /* Bit fields for DMA CHREQSTATUS */
00992 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 
00993 #define _DMA_CHREQSTATUS_MASK                           0x0000003FUL                                 
00994 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 
00995 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            
00996 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        
00997 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 
00998 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 
00999 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 
01000 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            
01001 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        
01002 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 
01003 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 
01004 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 
01005 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            
01006 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        
01007 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 
01008 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 
01009 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 
01010 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            
01011 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        
01012 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 
01013 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 
01014 #define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                 
01015 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                            
01016 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                       
01017 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                 
01018 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) 
01019 #define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                 
01020 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                            
01021 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                       
01022 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                 
01023 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) 
01025 /* Bit fields for DMA CHSREQSTATUS */
01026 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   
01027 #define _DMA_CHSREQSTATUS_MASK                          0x0000003FUL                                   
01028 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   
01029 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              
01030 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          
01031 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   
01032 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 
01033 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   
01034 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              
01035 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          
01036 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   
01037 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 
01038 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   
01039 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              
01040 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          
01041 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   
01042 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 
01043 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   
01044 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              
01045 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          
01046 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   
01047 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 
01048 #define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                   
01049 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                              
01050 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                         
01051 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                   
01052 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) 
01053 #define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                   
01054 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                              
01055 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                         
01056 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                   
01057 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) 
01059 /* Bit fields for DMA IF */
01060 #define _DMA_IF_RESETVALUE                              0x00000000UL                   
01061 #define _DMA_IF_MASK                                    0x8000003FUL                   
01062 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                   
01063 #define _DMA_IF_CH0DONE_SHIFT                           0                              
01064 #define _DMA_IF_CH0DONE_MASK                            0x1UL                          
01065 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   
01066 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) 
01067 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                   
01068 #define _DMA_IF_CH1DONE_SHIFT                           1                              
01069 #define _DMA_IF_CH1DONE_MASK                            0x2UL                          
01070 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   
01071 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) 
01072 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                   
01073 #define _DMA_IF_CH2DONE_SHIFT                           2                              
01074 #define _DMA_IF_CH2DONE_MASK                            0x4UL                          
01075 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   
01076 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) 
01077 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                   
01078 #define _DMA_IF_CH3DONE_SHIFT                           3                              
01079 #define _DMA_IF_CH3DONE_MASK                            0x8UL                          
01080 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   
01081 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) 
01082 #define DMA_IF_CH4DONE                                  (0x1UL << 4)                   
01083 #define _DMA_IF_CH4DONE_SHIFT                           4                              
01084 #define _DMA_IF_CH4DONE_MASK                            0x10UL                         
01085 #define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                   
01086 #define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4) 
01087 #define DMA_IF_CH5DONE                                  (0x1UL << 5)                   
01088 #define _DMA_IF_CH5DONE_SHIFT                           5                              
01089 #define _DMA_IF_CH5DONE_MASK                            0x20UL                         
01090 #define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                   
01091 #define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5) 
01092 #define DMA_IF_ERR                                      (0x1UL << 31)                  
01093 #define _DMA_IF_ERR_SHIFT                               31                             
01094 #define _DMA_IF_ERR_MASK                                0x80000000UL                   
01095 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   
01096 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    
01098 /* Bit fields for DMA IFS */
01099 #define _DMA_IFS_RESETVALUE                             0x00000000UL                    
01100 #define _DMA_IFS_MASK                                   0x8000003FUL                    
01101 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    
01102 #define _DMA_IFS_CH0DONE_SHIFT                          0                               
01103 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                           
01104 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    
01105 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) 
01106 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    
01107 #define _DMA_IFS_CH1DONE_SHIFT                          1                               
01108 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                           
01109 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    
01110 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) 
01111 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    
01112 #define _DMA_IFS_CH2DONE_SHIFT                          2                               
01113 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                           
01114 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    
01115 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) 
01116 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    
01117 #define _DMA_IFS_CH3DONE_SHIFT                          3                               
01118 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                           
01119 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    
01120 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) 
01121 #define DMA_IFS_CH4DONE                                 (0x1UL << 4)                    
01122 #define _DMA_IFS_CH4DONE_SHIFT                          4                               
01123 #define _DMA_IFS_CH4DONE_MASK                           0x10UL                          
01124 #define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                    
01125 #define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4) 
01126 #define DMA_IFS_CH5DONE                                 (0x1UL << 5)                    
01127 #define _DMA_IFS_CH5DONE_SHIFT                          5                               
01128 #define _DMA_IFS_CH5DONE_MASK                           0x20UL                          
01129 #define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                    
01130 #define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5) 
01131 #define DMA_IFS_ERR                                     (0x1UL << 31)                   
01132 #define _DMA_IFS_ERR_SHIFT                              31                              
01133 #define _DMA_IFS_ERR_MASK                               0x80000000UL                    
01134 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    
01135 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    
01137 /* Bit fields for DMA IFC */
01138 #define _DMA_IFC_RESETVALUE                             0x00000000UL                    
01139 #define _DMA_IFC_MASK                                   0x8000003FUL                    
01140 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    
01141 #define _DMA_IFC_CH0DONE_SHIFT                          0                               
01142 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                           
01143 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    
01144 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) 
01145 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    
01146 #define _DMA_IFC_CH1DONE_SHIFT                          1                               
01147 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                           
01148 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    
01149 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) 
01150 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    
01151 #define _DMA_IFC_CH2DONE_SHIFT                          2                               
01152 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                           
01153 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    
01154 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) 
01155 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    
01156 #define _DMA_IFC_CH3DONE_SHIFT                          3                               
01157 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                           
01158 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    
01159 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) 
01160 #define DMA_IFC_CH4DONE                                 (0x1UL << 4)                    
01161 #define _DMA_IFC_CH4DONE_SHIFT                          4                               
01162 #define _DMA_IFC_CH4DONE_MASK                           0x10UL                          
01163 #define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                    
01164 #define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4) 
01165 #define DMA_IFC_CH5DONE                                 (0x1UL << 5)                    
01166 #define _DMA_IFC_CH5DONE_SHIFT                          5                               
01167 #define _DMA_IFC_CH5DONE_MASK                           0x20UL                          
01168 #define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                    
01169 #define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5) 
01170 #define DMA_IFC_ERR                                     (0x1UL << 31)                   
01171 #define _DMA_IFC_ERR_SHIFT                              31                              
01172 #define _DMA_IFC_ERR_MASK                               0x80000000UL                    
01173 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    
01174 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    
01176 /* Bit fields for DMA IEN */
01177 #define _DMA_IEN_RESETVALUE                             0x00000000UL                    
01178 #define _DMA_IEN_MASK                                   0x8000003FUL                    
01179 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    
01180 #define _DMA_IEN_CH0DONE_SHIFT                          0                               
01181 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                           
01182 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    
01183 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) 
01184 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    
01185 #define _DMA_IEN_CH1DONE_SHIFT                          1                               
01186 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                           
01187 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    
01188 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) 
01189 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    
01190 #define _DMA_IEN_CH2DONE_SHIFT                          2                               
01191 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                           
01192 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    
01193 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) 
01194 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    
01195 #define _DMA_IEN_CH3DONE_SHIFT                          3                               
01196 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                           
01197 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    
01198 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) 
01199 #define DMA_IEN_CH4DONE                                 (0x1UL << 4)                    
01200 #define _DMA_IEN_CH4DONE_SHIFT                          4                               
01201 #define _DMA_IEN_CH4DONE_MASK                           0x10UL                          
01202 #define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                    
01203 #define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4) 
01204 #define DMA_IEN_CH5DONE                                 (0x1UL << 5)                    
01205 #define _DMA_IEN_CH5DONE_SHIFT                          5                               
01206 #define _DMA_IEN_CH5DONE_MASK                           0x20UL                          
01207 #define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                    
01208 #define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5) 
01209 #define DMA_IEN_ERR                                     (0x1UL << 31)                   
01210 #define _DMA_IEN_ERR_SHIFT                              31                              
01211 #define _DMA_IEN_ERR_MASK                               0x80000000UL                    
01212 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    
01213 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    
01215 /* Bit fields for DMA CH_CTRL */
01216 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                                  
01217 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                                  
01218 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                             
01219 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                         
01220 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                                  
01221 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                                  
01222 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                                  
01223 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                                  
01224 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                                  
01225 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                                  
01226 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF                  0x00000000UL                                  
01227 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                                  
01228 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                                  
01229 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                                  
01230 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                                  
01231 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                                  
01232 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                                  
01233 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                                  
01234 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0                   0x00000001UL                                  
01235 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                                  
01236 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                                  
01237 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                                  
01238 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                                  
01239 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                                  
01240 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1                   0x00000002UL                                  
01241 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT          0x00000003UL                                  
01242 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                                  
01243 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                                  
01244 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2                   0x00000003UL                                  
01245 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT             0x00000004UL                                  
01246 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)      
01247 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)      
01248 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)     
01249 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)        
01250 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)         
01251 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)         
01252 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)         
01253 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)           
01254 #define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)         
01255 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)         
01256 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)        
01257 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)           
01258 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)          
01259 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)          
01260 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)          
01261 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)      
01262 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)      
01263 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)     
01264 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)          
01265 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)          
01266 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)          
01267 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) 
01268 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)          
01269 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)          
01270 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)          
01271 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)    
01272 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                            
01273 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                    
01274 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                                  
01275 #define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                                  
01276 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                                  
01277 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                                  
01278 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                                  
01279 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                                  
01280 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                                  
01281 #define _DMA_CH_CTRL_SOURCESEL_TIMER2                   0x0000001AUL                                  
01282 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                                  
01283 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)           
01284 #define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)         
01285 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)         
01286 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)        
01287 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)           
01288 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)         
01289 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)         
01290 #define DMA_CH_CTRL_SOURCESEL_TIMER2                    (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)         
01291 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)            
01297 /**************************************************************************/
01302 /* Bit fields for CMU CTRL */
01303 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             
01304 #define _CMU_CTRL_MASK                              0x07FFFEEFUL                             
01305 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        
01306 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    
01307 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                             
01308 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                             
01309 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                             
01310 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                             
01311 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        
01312 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)           
01313 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      
01314 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      
01315 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                        
01316 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                    
01317 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                             
01318 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                             
01319 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                             
01320 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                             
01321 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                             
01322 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       
01323 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       
01324 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       
01325 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       
01326 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      
01327 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                        
01328 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                   
01329 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                             
01330 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      
01331 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                             
01332 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                        
01333 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                   
01334 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                             
01335 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 
01336 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                        
01337 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                  
01338 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                             
01339 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                             
01340 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                             
01341 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                             
01342 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                             
01343 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     
01344 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   
01345 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    
01346 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     
01347 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   
01348 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                       
01349 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                 
01350 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                             
01351 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                             
01352 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                             
01353 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                             
01354 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       
01355 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)          
01356 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     
01357 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     
01358 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                            
01359 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                       
01360 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                 
01361 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                             
01362 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                             
01363 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                             
01364 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      
01365 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      
01366 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     
01367 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                       
01368 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                
01369 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                             
01370 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)       
01371 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                            
01372 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                       
01373 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                
01374 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                             
01375 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     
01376 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                       
01377 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                
01378 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                             
01379 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                             
01380 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                             
01381 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                             
01382 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                             
01383 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    
01384 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   
01385 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  
01386 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    
01387 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  
01388 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                       
01389 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                               
01390 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                             
01391 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                             
01392 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                             
01393 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                             
01394 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                             
01395 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                             
01396 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                             
01397 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                             
01398 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                             
01399 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     
01400 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       
01401 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        
01402 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      
01403 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      
01404 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      
01405 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     
01406 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      
01407 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)    
01408 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                       
01409 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                              
01410 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                             
01411 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                             
01412 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                             
01413 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                             
01414 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                             
01415 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                             
01416 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                             
01417 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                             
01418 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                             
01419 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO                0x00000008UL                             
01420 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     
01421 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       
01422 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        
01423 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)       
01424 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)       
01425 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)       
01426 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)      
01427 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)      
01428 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)   
01429 #define CMU_CTRL_CLKOUTSEL1_USHFRCO                 (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23)     
01431 /* Bit fields for CMU HFCORECLKDIV */
01432 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
01433 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
01434 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
01435 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
01436 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
01437 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
01438 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
01439 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
01440 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
01441 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
01442 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
01443 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
01444 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
01445 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
01446 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
01447 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
01448 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
01449 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
01450 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
01451 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
01452 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
01453 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
01454 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
01455 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
01456 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
01457 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
01458 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
01459 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
01460 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
01461 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
01462 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
01463 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
01464 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
01465 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
01466 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
01468 /* Bit fields for CMU HFPERCLKDIV */
01469 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
01470 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
01471 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
01472 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
01473 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
01474 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
01475 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
01476 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
01477 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
01478 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
01479 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
01480 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
01481 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
01482 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
01483 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
01484 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
01485 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
01486 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
01487 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
01488 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
01489 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
01490 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
01491 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
01492 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
01493 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
01494 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
01495 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
01496 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
01497 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
01498 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
01499 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
01501 /* Bit fields for CMU HFRCOCTRL */
01502 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
01503 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
01504 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
01505 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
01506 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
01507 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
01508 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
01509 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
01510 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
01511 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
01512 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
01513 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
01514 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
01515 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
01516 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
01517 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
01518 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
01519 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
01520 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
01521 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
01522 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
01523 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
01524 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
01525 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
01527 /* Bit fields for CMU LFRCOCTRL */
01528 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
01529 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
01530 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
01531 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
01532 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
01533 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
01535 /* Bit fields for CMU AUXHFRCOCTRL */
01536 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
01537 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
01538 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
01539 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
01540 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
01541 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
01542 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
01543 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
01544 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
01545 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
01546 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
01547 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
01548 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
01549 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
01550 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
01551 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
01552 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
01553 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
01554 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
01555 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
01557 /* Bit fields for CMU CALCTRL */
01558 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
01559 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
01560 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
01561 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
01562 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
01563 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
01564 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
01565 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
01566 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
01567 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
01568 #define _CMU_CALCTRL_UPSEL_USHFRCO                  0x00000005UL                         
01569 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
01570 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
01571 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
01572 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
01573 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
01574 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
01575 #define CMU_CALCTRL_UPSEL_USHFRCO                   (_CMU_CALCTRL_UPSEL_USHFRCO << 0)    
01576 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
01577 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
01578 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
01579 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
01580 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
01581 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
01582 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
01583 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
01584 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
01585 #define _CMU_CALCTRL_DOWNSEL_USHFRCO                0x00000006UL                         
01586 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
01587 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
01588 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
01589 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
01590 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
01591 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
01592 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
01593 #define CMU_CALCTRL_DOWNSEL_USHFRCO                 (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3)  
01594 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
01595 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
01596 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
01597 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
01598 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
01600 /* Bit fields for CMU CALCNT */
01601 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
01602 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
01603 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
01604 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
01605 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
01606 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
01608 /* Bit fields for CMU OSCENCMD */
01609 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
01610 #define _CMU_OSCENCMD_MASK                          0x00000FFFUL                             
01611 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
01612 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
01613 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
01614 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
01615 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
01616 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
01617 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
01618 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
01619 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
01620 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
01621 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
01622 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
01623 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
01624 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
01625 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
01626 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
01627 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
01628 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
01629 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
01630 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
01631 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
01632 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
01633 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
01634 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
01635 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
01636 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
01637 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
01638 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
01639 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
01640 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
01641 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
01642 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
01643 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
01644 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
01645 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
01646 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
01647 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
01648 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
01649 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
01650 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
01651 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
01652 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
01653 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
01654 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
01655 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
01656 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
01657 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
01658 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
01659 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
01660 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
01661 #define CMU_OSCENCMD_USHFRCOEN                      (0x1UL << 10)                            
01662 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT               10                                       
01663 #define _CMU_OSCENCMD_USHFRCOEN_MASK                0x400UL                                  
01664 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT             0x00000000UL                             
01665 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT              (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10)  
01666 #define CMU_OSCENCMD_USHFRCODIS                     (0x1UL << 11)                            
01667 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT              11                                       
01668 #define _CMU_OSCENCMD_USHFRCODIS_MASK               0x800UL                                  
01669 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT            0x00000000UL                             
01670 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT             (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) 
01672 /* Bit fields for CMU CMD */
01673 #define _CMU_CMD_RESETVALUE                         0x00000000UL                         
01674 #define _CMU_CMD_MASK                               0x000000FFUL                         
01675 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                    
01676 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                
01677 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                         
01678 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                         
01679 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                         
01680 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                         
01681 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                         
01682 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2               0x00000005UL                         
01683 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0)     
01684 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)       
01685 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)        
01686 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)       
01687 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)        
01688 #define CMU_CMD_HFCLKSEL_USHFRCODIV2                (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) 
01689 #define CMU_CMD_CALSTART                            (0x1UL << 3)                         
01690 #define _CMU_CMD_CALSTART_SHIFT                     3                                    
01691 #define _CMU_CMD_CALSTART_MASK                      0x8UL                                
01692 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                         
01693 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3)     
01694 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                         
01695 #define _CMU_CMD_CALSTOP_SHIFT                      4                                    
01696 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                               
01697 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                         
01698 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)      
01699 #define _CMU_CMD_USBCCLKSEL_SHIFT                   5                                    
01700 #define _CMU_CMD_USBCCLKSEL_MASK                    0xE0UL                               
01701 #define _CMU_CMD_USBCCLKSEL_DEFAULT                 0x00000000UL                         
01702 #define _CMU_CMD_USBCCLKSEL_LFXO                    0x00000002UL                         
01703 #define _CMU_CMD_USBCCLKSEL_LFRCO                   0x00000003UL                         
01704 #define _CMU_CMD_USBCCLKSEL_USHFRCO                 0x00000004UL                         
01705 #define CMU_CMD_USBCCLKSEL_DEFAULT                  (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)   
01706 #define CMU_CMD_USBCCLKSEL_LFXO                     (_CMU_CMD_USBCCLKSEL_LFXO << 5)      
01707 #define CMU_CMD_USBCCLKSEL_LFRCO                    (_CMU_CMD_USBCCLKSEL_LFRCO << 5)     
01708 #define CMU_CMD_USBCCLKSEL_USHFRCO                  (_CMU_CMD_USBCCLKSEL_USHFRCO << 5)   
01710 /* Bit fields for CMU LFCLKSEL */
01711 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000015UL                             
01712 #define _CMU_LFCLKSEL_MASK                          0x0011003FUL                             
01713 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
01714 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
01715 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
01716 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
01717 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
01718 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
01719 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
01720 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
01721 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
01722 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
01723 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
01724 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
01725 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
01726 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
01727 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
01728 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
01729 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
01730 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
01731 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
01732 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
01733 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
01734 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
01735 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
01736 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
01737 #define _CMU_LFCLKSEL_LFC_SHIFT                     4                                        
01738 #define _CMU_LFCLKSEL_LFC_MASK                      0x30UL                                   
01739 #define _CMU_LFCLKSEL_LFC_DISABLED                  0x00000000UL                             
01740 #define _CMU_LFCLKSEL_LFC_DEFAULT                   0x00000001UL                             
01741 #define _CMU_LFCLKSEL_LFC_LFRCO                     0x00000001UL                             
01742 #define _CMU_LFCLKSEL_LFC_LFXO                      0x00000002UL                             
01743 #define CMU_LFCLKSEL_LFC_DISABLED                   (_CMU_LFCLKSEL_LFC_DISABLED << 4)        
01744 #define CMU_LFCLKSEL_LFC_DEFAULT                    (_CMU_LFCLKSEL_LFC_DEFAULT << 4)         
01745 #define CMU_LFCLKSEL_LFC_LFRCO                      (_CMU_LFCLKSEL_LFC_LFRCO << 4)           
01746 #define CMU_LFCLKSEL_LFC_LFXO                       (_CMU_LFCLKSEL_LFC_LFXO << 4)            
01747 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
01748 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
01749 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
01750 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
01751 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
01752 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
01753 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
01754 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
01755 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
01756 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
01757 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
01758 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
01759 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
01760 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
01761 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
01762 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
01763 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
01764 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
01766 /* Bit fields for CMU STATUS */
01767 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                               
01768 #define _CMU_STATUS_MASK                            0x04F77FFFUL                               
01769 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                               
01770 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                          
01771 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                      
01772 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                               
01773 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)        
01774 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                               
01775 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                          
01776 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                      
01777 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                               
01778 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)        
01779 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                               
01780 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                          
01781 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                      
01782 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                               
01783 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)         
01784 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                               
01785 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                          
01786 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                      
01787 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                               
01788 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)         
01789 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                               
01790 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                          
01791 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                     
01792 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                               
01793 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)     
01794 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                               
01795 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                          
01796 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                     
01797 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                               
01798 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)     
01799 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                               
01800 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                          
01801 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                     
01802 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                               
01803 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)        
01804 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                               
01805 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                          
01806 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                     
01807 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                               
01808 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)        
01809 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                               
01810 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                          
01811 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                    
01812 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                               
01813 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)         
01814 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                               
01815 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                          
01816 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                    
01817 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                               
01818 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)         
01819 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                              
01820 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                         
01821 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                    
01822 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                               
01823 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)       
01824 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                              
01825 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                         
01826 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                    
01827 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                               
01828 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)        
01829 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                              
01830 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                         
01831 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                                   
01832 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                               
01833 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)       
01834 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                              
01835 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                         
01836 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                                   
01837 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                               
01838 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)        
01839 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                              
01840 #define _CMU_STATUS_CALBSY_SHIFT                    14                                         
01841 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                                   
01842 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                               
01843 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)         
01844 #define CMU_STATUS_USBCLFXOSEL                      (0x1UL << 16)                              
01845 #define _CMU_STATUS_USBCLFXOSEL_SHIFT               16                                         
01846 #define _CMU_STATUS_USBCLFXOSEL_MASK                0x10000UL                                  
01847 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT             0x00000000UL                               
01848 #define CMU_STATUS_USBCLFXOSEL_DEFAULT              (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)    
01849 #define CMU_STATUS_USBCLFRCOSEL                     (0x1UL << 17)                              
01850 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT              17                                         
01851 #define _CMU_STATUS_USBCLFRCOSEL_MASK               0x20000UL                                  
01852 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT            0x00000000UL                               
01853 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT             (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)   
01854 #define CMU_STATUS_USBCUSHFRCOSEL                   (0x1UL << 18)                              
01855 #define _CMU_STATUS_USBCUSHFRCOSEL_SHIFT            18                                         
01856 #define _CMU_STATUS_USBCUSHFRCOSEL_MASK             0x40000UL                                  
01857 #define _CMU_STATUS_USBCUSHFRCOSEL_DEFAULT          0x00000000UL                               
01858 #define CMU_STATUS_USBCUSHFRCOSEL_DEFAULT           (_CMU_STATUS_USBCUSHFRCOSEL_DEFAULT << 18) 
01859 #define CMU_STATUS_USBCHFCLKSYNC                    (0x1UL << 20)                              
01860 #define _CMU_STATUS_USBCHFCLKSYNC_SHIFT             20                                         
01861 #define _CMU_STATUS_USBCHFCLKSYNC_MASK              0x100000UL                                 
01862 #define _CMU_STATUS_USBCHFCLKSYNC_DEFAULT           0x00000000UL                               
01863 #define CMU_STATUS_USBCHFCLKSYNC_DEFAULT            (_CMU_STATUS_USBCHFCLKSYNC_DEFAULT << 20)  
01864 #define CMU_STATUS_USHFRCOENS                       (0x1UL << 21)                              
01865 #define _CMU_STATUS_USHFRCOENS_SHIFT                21                                         
01866 #define _CMU_STATUS_USHFRCOENS_MASK                 0x200000UL                                 
01867 #define _CMU_STATUS_USHFRCOENS_DEFAULT              0x00000000UL                               
01868 #define CMU_STATUS_USHFRCOENS_DEFAULT               (_CMU_STATUS_USHFRCOENS_DEFAULT << 21)     
01869 #define CMU_STATUS_USHFRCORDY                       (0x1UL << 22)                              
01870 #define _CMU_STATUS_USHFRCORDY_SHIFT                22                                         
01871 #define _CMU_STATUS_USHFRCORDY_MASK                 0x400000UL                                 
01872 #define _CMU_STATUS_USHFRCORDY_DEFAULT              0x00000000UL                               
01873 #define CMU_STATUS_USHFRCORDY_DEFAULT               (_CMU_STATUS_USHFRCORDY_DEFAULT << 22)     
01874 #define CMU_STATUS_USHFRCOSUSPEND                   (0x1UL << 23)                              
01875 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT            23                                         
01876 #define _CMU_STATUS_USHFRCOSUSPEND_MASK             0x800000UL                                 
01877 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT          0x00000000UL                               
01878 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT           (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) 
01879 #define CMU_STATUS_USHFRCODIV2SEL                   (0x1UL << 26)                              
01880 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT            26                                         
01881 #define _CMU_STATUS_USHFRCODIV2SEL_MASK             0x4000000UL                                
01882 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT          0x00000000UL                               
01883 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT           (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) 
01885 /* Bit fields for CMU IF */
01886 #define _CMU_IF_RESETVALUE                          0x00000001UL                        
01887 #define _CMU_IF_MASK                                0x0000037FUL                        
01888 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                        
01889 #define _CMU_IF_HFRCORDY_SHIFT                      0                                   
01890 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                               
01891 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                        
01892 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)     
01893 #define CMU_IF_HFXORDY                              (0x1UL << 1)                        
01894 #define _CMU_IF_HFXORDY_SHIFT                       1                                   
01895 #define _CMU_IF_HFXORDY_MASK                        0x2UL                               
01896 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                        
01897 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)      
01898 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                        
01899 #define _CMU_IF_LFRCORDY_SHIFT                      2                                   
01900 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                               
01901 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                        
01902 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)     
01903 #define CMU_IF_LFXORDY                              (0x1UL << 3)                        
01904 #define _CMU_IF_LFXORDY_SHIFT                       3                                   
01905 #define _CMU_IF_LFXORDY_MASK                        0x8UL                               
01906 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                        
01907 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)      
01908 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                        
01909 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                   
01910 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                              
01911 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                        
01912 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)  
01913 #define CMU_IF_CALRDY                               (0x1UL << 5)                        
01914 #define _CMU_IF_CALRDY_SHIFT                        5                                   
01915 #define _CMU_IF_CALRDY_MASK                         0x20UL                              
01916 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                        
01917 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)       
01918 #define CMU_IF_CALOF                                (0x1UL << 6)                        
01919 #define _CMU_IF_CALOF_SHIFT                         6                                   
01920 #define _CMU_IF_CALOF_MASK                          0x40UL                              
01921 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                        
01922 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)        
01923 #define CMU_IF_USHFRCORDY                           (0x1UL << 8)                        
01924 #define _CMU_IF_USHFRCORDY_SHIFT                    8                                   
01925 #define _CMU_IF_USHFRCORDY_MASK                     0x100UL                             
01926 #define _CMU_IF_USHFRCORDY_DEFAULT                  0x00000000UL                        
01927 #define CMU_IF_USHFRCORDY_DEFAULT                   (_CMU_IF_USHFRCORDY_DEFAULT << 8)   
01928 #define CMU_IF_USBCHFOSCSEL                         (0x1UL << 9)                        
01929 #define _CMU_IF_USBCHFOSCSEL_SHIFT                  9                                   
01930 #define _CMU_IF_USBCHFOSCSEL_MASK                   0x200UL                             
01931 #define _CMU_IF_USBCHFOSCSEL_DEFAULT                0x00000000UL                        
01932 #define CMU_IF_USBCHFOSCSEL_DEFAULT                 (_CMU_IF_USBCHFOSCSEL_DEFAULT << 9) 
01934 /* Bit fields for CMU IFS */
01935 #define _CMU_IFS_RESETVALUE                         0x00000000UL                         
01936 #define _CMU_IFS_MASK                               0x0000037FUL                         
01937 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                         
01938 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                    
01939 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                                
01940 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                         
01941 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)     
01942 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                         
01943 #define _CMU_IFS_HFXORDY_SHIFT                      1                                    
01944 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                                
01945 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                         
01946 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)      
01947 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                         
01948 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                    
01949 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                                
01950 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                         
01951 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)     
01952 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                         
01953 #define _CMU_IFS_LFXORDY_SHIFT                      3                                    
01954 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                                
01955 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                         
01956 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)      
01957 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                         
01958 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                    
01959 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                               
01960 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                         
01961 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)  
01962 #define CMU_IFS_CALRDY                              (0x1UL << 5)                         
01963 #define _CMU_IFS_CALRDY_SHIFT                       5                                    
01964 #define _CMU_IFS_CALRDY_MASK                        0x20UL                               
01965 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                         
01966 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)       
01967 #define CMU_IFS_CALOF                               (0x1UL << 6)                         
01968 #define _CMU_IFS_CALOF_SHIFT                        6                                    
01969 #define _CMU_IFS_CALOF_MASK                         0x40UL                               
01970 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                         
01971 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)        
01972 #define CMU_IFS_USHFRCORDY                          (0x1UL << 8)                         
01973 #define _CMU_IFS_USHFRCORDY_SHIFT                   8                                    
01974 #define _CMU_IFS_USHFRCORDY_MASK                    0x100UL                              
01975 #define _CMU_IFS_USHFRCORDY_DEFAULT                 0x00000000UL                         
01976 #define CMU_IFS_USHFRCORDY_DEFAULT                  (_CMU_IFS_USHFRCORDY_DEFAULT << 8)   
01977 #define CMU_IFS_USBCHFOSCSEL                        (0x1UL << 9)                         
01978 #define _CMU_IFS_USBCHFOSCSEL_SHIFT                 9                                    
01979 #define _CMU_IFS_USBCHFOSCSEL_MASK                  0x200UL                              
01980 #define _CMU_IFS_USBCHFOSCSEL_DEFAULT               0x00000000UL                         
01981 #define CMU_IFS_USBCHFOSCSEL_DEFAULT                (_CMU_IFS_USBCHFOSCSEL_DEFAULT << 9) 
01983 /* Bit fields for CMU IFC */
01984 #define _CMU_IFC_RESETVALUE                         0x00000000UL                         
01985 #define _CMU_IFC_MASK                               0x0000037FUL                         
01986 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                         
01987 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                    
01988 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                                
01989 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                         
01990 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)     
01991 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                         
01992 #define _CMU_IFC_HFXORDY_SHIFT                      1                                    
01993 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                                
01994 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                         
01995 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)      
01996 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                         
01997 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                    
01998 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                                
01999 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                         
02000 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)     
02001 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                         
02002 #define _CMU_IFC_LFXORDY_SHIFT                      3                                    
02003 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                                
02004 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                         
02005 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)      
02006 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                         
02007 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                    
02008 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                               
02009 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                         
02010 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)  
02011 #define CMU_IFC_CALRDY                              (0x1UL << 5)                         
02012 #define _CMU_IFC_CALRDY_SHIFT                       5                                    
02013 #define _CMU_IFC_CALRDY_MASK                        0x20UL                               
02014 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                         
02015 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)       
02016 #define CMU_IFC_CALOF                               (0x1UL << 6)                         
02017 #define _CMU_IFC_CALOF_SHIFT                        6                                    
02018 #define _CMU_IFC_CALOF_MASK                         0x40UL                               
02019 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                         
02020 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)        
02021 #define CMU_IFC_USHFRCORDY                          (0x1UL << 8)                         
02022 #define _CMU_IFC_USHFRCORDY_SHIFT                   8                                    
02023 #define _CMU_IFC_USHFRCORDY_MASK                    0x100UL                              
02024 #define _CMU_IFC_USHFRCORDY_DEFAULT                 0x00000000UL                         
02025 #define CMU_IFC_USHFRCORDY_DEFAULT                  (_CMU_IFC_USHFRCORDY_DEFAULT << 8)   
02026 #define CMU_IFC_USBCHFOSCSEL                        (0x1UL << 9)                         
02027 #define _CMU_IFC_USBCHFOSCSEL_SHIFT                 9                                    
02028 #define _CMU_IFC_USBCHFOSCSEL_MASK                  0x200UL                              
02029 #define _CMU_IFC_USBCHFOSCSEL_DEFAULT               0x00000000UL                         
02030 #define CMU_IFC_USBCHFOSCSEL_DEFAULT                (_CMU_IFC_USBCHFOSCSEL_DEFAULT << 9) 
02032 /* Bit fields for CMU IEN */
02033 #define _CMU_IEN_RESETVALUE                         0x00000000UL                         
02034 #define _CMU_IEN_MASK                               0x0000037FUL                         
02035 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                         
02036 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                    
02037 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                                
02038 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                         
02039 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)     
02040 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                         
02041 #define _CMU_IEN_HFXORDY_SHIFT                      1                                    
02042 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                                
02043 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                         
02044 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)      
02045 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                         
02046 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                    
02047 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                                
02048 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                         
02049 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)     
02050 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                         
02051 #define _CMU_IEN_LFXORDY_SHIFT                      3                                    
02052 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                                
02053 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                         
02054 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)      
02055 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                         
02056 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                    
02057 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                               
02058 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                         
02059 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)  
02060 #define CMU_IEN_CALRDY                              (0x1UL << 5)                         
02061 #define _CMU_IEN_CALRDY_SHIFT                       5                                    
02062 #define _CMU_IEN_CALRDY_MASK                        0x20UL                               
02063 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                         
02064 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)       
02065 #define CMU_IEN_CALOF                               (0x1UL << 6)                         
02066 #define _CMU_IEN_CALOF_SHIFT                        6                                    
02067 #define _CMU_IEN_CALOF_MASK                         0x40UL                               
02068 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                         
02069 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)        
02070 #define CMU_IEN_USHFRCORDY                          (0x1UL << 8)                         
02071 #define _CMU_IEN_USHFRCORDY_SHIFT                   8                                    
02072 #define _CMU_IEN_USHFRCORDY_MASK                    0x100UL                              
02073 #define _CMU_IEN_USHFRCORDY_DEFAULT                 0x00000000UL                         
02074 #define CMU_IEN_USHFRCORDY_DEFAULT                  (_CMU_IEN_USHFRCORDY_DEFAULT << 8)   
02075 #define CMU_IEN_USBCHFOSCSEL                        (0x1UL << 9)                         
02076 #define _CMU_IEN_USBCHFOSCSEL_SHIFT                 9                                    
02077 #define _CMU_IEN_USBCHFOSCSEL_MASK                  0x200UL                              
02078 #define _CMU_IEN_USBCHFOSCSEL_DEFAULT               0x00000000UL                         
02079 #define CMU_IEN_USBCHFOSCSEL_DEFAULT                (_CMU_IEN_USBCHFOSCSEL_DEFAULT << 9) 
02081 /* Bit fields for CMU HFCORECLKEN0 */
02082 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                          
02083 #define _CMU_HFCORECLKEN0_MASK                      0x0000001EUL                          
02084 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 1)                          
02085 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 1                                     
02086 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x2UL                                 
02087 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                          
02088 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)  
02089 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 2)                          
02090 #define _CMU_HFCORECLKEN0_LE_SHIFT                  2                                     
02091 #define _CMU_HFCORECLKEN0_LE_MASK                   0x4UL                                 
02092 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                          
02093 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)   
02094 #define CMU_HFCORECLKEN0_USBC                       (0x1UL << 3)                          
02095 #define _CMU_HFCORECLKEN0_USBC_SHIFT                3                                     
02096 #define _CMU_HFCORECLKEN0_USBC_MASK                 0x8UL                                 
02097 #define _CMU_HFCORECLKEN0_USBC_DEFAULT              0x00000000UL                          
02098 #define CMU_HFCORECLKEN0_USBC_DEFAULT               (_CMU_HFCORECLKEN0_USBC_DEFAULT << 3) 
02099 #define CMU_HFCORECLKEN0_USB                        (0x1UL << 4)                          
02100 #define _CMU_HFCORECLKEN0_USB_SHIFT                 4                                     
02101 #define _CMU_HFCORECLKEN0_USB_MASK                  0x10UL                                
02102 #define _CMU_HFCORECLKEN0_USB_DEFAULT               0x00000000UL                          
02103 #define CMU_HFCORECLKEN0_USB_DEFAULT                (_CMU_HFCORECLKEN0_USB_DEFAULT << 4)  
02105 /* Bit fields for CMU HFPERCLKEN0 */
02106 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
02107 #define _CMU_HFPERCLKEN0_MASK                       0x00000B7FUL                           
02108 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 0)                           
02109 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               0                                      
02110 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x1UL                                  
02111 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
02112 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) 
02113 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 1)                           
02114 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               1                                      
02115 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x2UL                                  
02116 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
02117 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) 
02118 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 2)                           
02119 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               2                                      
02120 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x4UL                                  
02121 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
02122 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) 
02123 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 3)                           
02124 #define _CMU_HFPERCLKEN0_USART0_SHIFT               3                                      
02125 #define _CMU_HFPERCLKEN0_USART0_MASK                0x8UL                                  
02126 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
02127 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) 
02128 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 4)                           
02129 #define _CMU_HFPERCLKEN0_USART1_SHIFT               4                                      
02130 #define _CMU_HFPERCLKEN0_USART1_MASK                0x10UL                                 
02131 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
02132 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) 
02133 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 5)                           
02134 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                5                                      
02135 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x20UL                                 
02136 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
02137 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5)  
02138 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 6)                           
02139 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  6                                      
02140 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x40UL                                 
02141 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
02142 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6)    
02143 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 8)                           
02144 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 8                                      
02145 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x100UL                                
02146 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
02147 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8)   
02148 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 9)                           
02149 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 9                                      
02150 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x200UL                                
02151 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
02152 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9)   
02153 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
02154 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
02155 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
02156 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
02157 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
02159 /* Bit fields for CMU SYNCBUSY */
02160 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
02161 #define _CMU_SYNCBUSY_MASK                          0x00000155UL                           
02162 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
02163 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
02164 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
02165 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
02166 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
02167 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
02168 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
02169 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
02170 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
02171 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
02172 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
02173 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
02174 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
02175 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
02176 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
02177 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
02178 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
02179 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
02180 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
02181 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
02182 #define CMU_SYNCBUSY_LFCCLKEN0                      (0x1UL << 8)                           
02183 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT               8                                      
02184 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK                0x100UL                                
02185 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT             0x00000000UL                           
02186 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) 
02188 /* Bit fields for CMU FREEZE */
02189 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
02190 #define _CMU_FREEZE_MASK                            0x00000001UL                         
02191 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
02192 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
02193 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
02194 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
02195 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
02196 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
02197 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
02198 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
02199 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
02201 /* Bit fields for CMU LFACLKEN0 */
02202 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                      
02203 #define _CMU_LFACLKEN0_MASK                         0x00000001UL                      
02204 #define CMU_LFACLKEN0_RTC                           (0x1UL << 0)                      
02205 #define _CMU_LFACLKEN0_RTC_SHIFT                    0                                 
02206 #define _CMU_LFACLKEN0_RTC_MASK                     0x1UL                             
02207 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                      
02208 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 0) 
02210 /* Bit fields for CMU LFBCLKEN0 */
02211 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
02212 #define _CMU_LFBCLKEN0_MASK                         0x00000001UL                          
02213 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
02214 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
02215 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
02216 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
02217 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
02219 /* Bit fields for CMU LFCCLKEN0 */
02220 #define _CMU_LFCCLKEN0_RESETVALUE                   0x00000000UL                        
02221 #define _CMU_LFCCLKEN0_MASK                         0x00000001UL                        
02222 #define CMU_LFCCLKEN0_USBLE                         (0x1UL << 0)                        
02223 #define _CMU_LFCCLKEN0_USBLE_SHIFT                  0                                   
02224 #define _CMU_LFCCLKEN0_USBLE_MASK                   0x1UL                               
02225 #define _CMU_LFCCLKEN0_USBLE_DEFAULT                0x00000000UL                        
02226 #define CMU_LFCCLKEN0_USBLE_DEFAULT                 (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) 
02228 /* Bit fields for CMU LFAPRESC0 */
02229 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                       
02230 #define _CMU_LFAPRESC0_MASK                         0x0000000FUL                       
02231 #define _CMU_LFAPRESC0_RTC_SHIFT                    0                                  
02232 #define _CMU_LFAPRESC0_RTC_MASK                     0xFUL                              
02233 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                       
02234 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                       
02235 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                       
02236 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                       
02237 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                       
02238 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                       
02239 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                       
02240 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                       
02241 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                       
02242 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                       
02243 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                       
02244 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                       
02245 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                       
02246 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                       
02247 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                       
02248 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                       
02249 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 0)     
02250 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 0)     
02251 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 0)     
02252 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 0)     
02253 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 0)    
02254 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 0)    
02255 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 0)    
02256 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 0)   
02257 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 0)   
02258 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 0)   
02259 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 0)  
02260 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 0)  
02261 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 0)  
02262 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 0)  
02263 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 0) 
02264 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 0) 
02266 /* Bit fields for CMU LFBPRESC0 */
02267 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
02268 #define _CMU_LFBPRESC0_MASK                         0x00000003UL                       
02269 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
02270 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
02271 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
02272 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
02273 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
02274 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
02275 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
02276 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
02277 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
02278 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
02280 /* Bit fields for CMU PCNTCTRL */
02281 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
02282 #define _CMU_PCNTCTRL_MASK                          0x00000003UL                             
02283 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
02284 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
02285 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
02286 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
02287 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
02288 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
02289 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
02290 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
02291 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
02292 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
02293 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
02294 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
02295 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
02296 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
02298 /* Bit fields for CMU ROUTE */
02299 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
02300 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
02301 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
02302 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
02303 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
02304 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
02305 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
02306 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
02307 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
02308 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
02309 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
02310 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
02311 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
02312 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
02313 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
02314 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
02315 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
02316 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
02317 #define _CMU_ROUTE_LOCATION_LOC3                    0x00000003UL                         
02318 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
02319 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
02320 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
02321 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
02322 #define CMU_ROUTE_LOCATION_LOC3                     (_CMU_ROUTE_LOCATION_LOC3 << 2)      
02324 /* Bit fields for CMU LOCK */
02325 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
02326 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
02327 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
02328 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
02329 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
02330 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
02331 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
02332 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
02333 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
02334 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
02335 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
02336 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
02337 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
02338 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
02340 /* Bit fields for CMU USBCRCTRL */
02341 #define _CMU_USBCRCTRL_RESETVALUE                   0x00000000UL                         
02342 #define _CMU_USBCRCTRL_MASK                         0x00000003UL                         
02343 #define CMU_USBCRCTRL_EN                            (0x1UL << 0)                         
02344 #define _CMU_USBCRCTRL_EN_SHIFT                     0                                    
02345 #define _CMU_USBCRCTRL_EN_MASK                      0x1UL                                
02346 #define _CMU_USBCRCTRL_EN_DEFAULT                   0x00000000UL                         
02347 #define CMU_USBCRCTRL_EN_DEFAULT                    (_CMU_USBCRCTRL_EN_DEFAULT << 0)     
02348 #define CMU_USBCRCTRL_LSMODE                        (0x1UL << 1)                         
02349 #define _CMU_USBCRCTRL_LSMODE_SHIFT                 1                                    
02350 #define _CMU_USBCRCTRL_LSMODE_MASK                  0x2UL                                
02351 #define _CMU_USBCRCTRL_LSMODE_DEFAULT               0x00000000UL                         
02352 #define CMU_USBCRCTRL_LSMODE_DEFAULT                (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) 
02354 /* Bit fields for CMU USHFRCOCTRL */
02355 #define _CMU_USHFRCOCTRL_RESETVALUE                 0x000FF040UL                             
02356 #define _CMU_USHFRCOCTRL_MASK                       0x000FF37FUL                             
02357 #define _CMU_USHFRCOCTRL_TUNING_SHIFT               0                                        
02358 #define _CMU_USHFRCOCTRL_TUNING_MASK                0x7FUL                                   
02359 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT             0x00000040UL                             
02360 #define CMU_USHFRCOCTRL_TUNING_DEFAULT              (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0)   
02361 #define CMU_USHFRCOCTRL_DITHEN                      (0x1UL << 8)                             
02362 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT               8                                        
02363 #define _CMU_USHFRCOCTRL_DITHEN_MASK                0x100UL                                  
02364 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT             0x00000000UL                             
02365 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT              (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8)   
02366 #define CMU_USHFRCOCTRL_SUSPEND                     (0x1UL << 9)                             
02367 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT              9                                        
02368 #define _CMU_USHFRCOCTRL_SUSPEND_MASK               0x200UL                                  
02369 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT            0x00000000UL                             
02370 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT             (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9)  
02371 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT              12                                       
02372 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK               0xFF000UL                                
02373 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT            0x000000FFUL                             
02374 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT             (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) 
02376 /* Bit fields for CMU USHFRCOTUNE */
02377 #define _CMU_USHFRCOTUNE_RESETVALUE                 0x00000020UL                               
02378 #define _CMU_USHFRCOTUNE_MASK                       0x0000003FUL                               
02379 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT           0                                          
02380 #define _CMU_USHFRCOTUNE_FINETUNING_MASK            0x3FUL                                     
02381 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT         0x00000020UL                               
02382 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT          (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) 
02384 /* Bit fields for CMU USHFRCOCONF */
02385 #define _CMU_USHFRCOCONF_RESETVALUE                 0x00000001UL                                   
02386 #define _CMU_USHFRCOCONF_MASK                       0x00000017UL                                   
02387 #define _CMU_USHFRCOCONF_BAND_SHIFT                 0                                              
02388 #define _CMU_USHFRCOCONF_BAND_MASK                  0x7UL                                          
02389 #define _CMU_USHFRCOCONF_BAND_DEFAULT               0x00000001UL                                   
02390 #define _CMU_USHFRCOCONF_BAND_48MHZ                 0x00000001UL                                   
02391 #define _CMU_USHFRCOCONF_BAND_24MHZ                 0x00000003UL                                   
02392 #define CMU_USHFRCOCONF_BAND_DEFAULT                (_CMU_USHFRCOCONF_BAND_DEFAULT << 0)           
02393 #define CMU_USHFRCOCONF_BAND_48MHZ                  (_CMU_USHFRCOCONF_BAND_48MHZ << 0)             
02394 #define CMU_USHFRCOCONF_BAND_24MHZ                  (_CMU_USHFRCOCONF_BAND_24MHZ << 0)             
02395 #define CMU_USHFRCOCONF_USHFRCODIV2DIS              (0x1UL << 4)                                   
02396 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT       4                                              
02397 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK        0x10UL                                         
02398 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT     0x00000000UL                                   
02399 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT      (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) 
02403 /**************************************************************************/
02408 /* Bit fields for PRS SWPULSE */
02409 #define _PRS_SWPULSE_RESETVALUE              0x00000000UL                         
02410 #define _PRS_SWPULSE_MASK                    0x0000003FUL                         
02411 #define PRS_SWPULSE_CH0PULSE                 (0x1UL << 0)                         
02412 #define _PRS_SWPULSE_CH0PULSE_SHIFT          0                                    
02413 #define _PRS_SWPULSE_CH0PULSE_MASK           0x1UL                                
02414 #define _PRS_SWPULSE_CH0PULSE_DEFAULT        0x00000000UL                         
02415 #define PRS_SWPULSE_CH0PULSE_DEFAULT         (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) 
02416 #define PRS_SWPULSE_CH1PULSE                 (0x1UL << 1)                         
02417 #define _PRS_SWPULSE_CH1PULSE_SHIFT          1                                    
02418 #define _PRS_SWPULSE_CH1PULSE_MASK           0x2UL                                
02419 #define _PRS_SWPULSE_CH1PULSE_DEFAULT        0x00000000UL                         
02420 #define PRS_SWPULSE_CH1PULSE_DEFAULT         (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) 
02421 #define PRS_SWPULSE_CH2PULSE                 (0x1UL << 2)                         
02422 #define _PRS_SWPULSE_CH2PULSE_SHIFT          2                                    
02423 #define _PRS_SWPULSE_CH2PULSE_MASK           0x4UL                                
02424 #define _PRS_SWPULSE_CH2PULSE_DEFAULT        0x00000000UL                         
02425 #define PRS_SWPULSE_CH2PULSE_DEFAULT         (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) 
02426 #define PRS_SWPULSE_CH3PULSE                 (0x1UL << 3)                         
02427 #define _PRS_SWPULSE_CH3PULSE_SHIFT          3                                    
02428 #define _PRS_SWPULSE_CH3PULSE_MASK           0x8UL                                
02429 #define _PRS_SWPULSE_CH3PULSE_DEFAULT        0x00000000UL                         
02430 #define PRS_SWPULSE_CH3PULSE_DEFAULT         (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) 
02431 #define PRS_SWPULSE_CH4PULSE                 (0x1UL << 4)                         
02432 #define _PRS_SWPULSE_CH4PULSE_SHIFT          4                                    
02433 #define _PRS_SWPULSE_CH4PULSE_MASK           0x10UL                               
02434 #define _PRS_SWPULSE_CH4PULSE_DEFAULT        0x00000000UL                         
02435 #define PRS_SWPULSE_CH4PULSE_DEFAULT         (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) 
02436 #define PRS_SWPULSE_CH5PULSE                 (0x1UL << 5)                         
02437 #define _PRS_SWPULSE_CH5PULSE_SHIFT          5                                    
02438 #define _PRS_SWPULSE_CH5PULSE_MASK           0x20UL                               
02439 #define _PRS_SWPULSE_CH5PULSE_DEFAULT        0x00000000UL                         
02440 #define PRS_SWPULSE_CH5PULSE_DEFAULT         (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) 
02442 /* Bit fields for PRS SWLEVEL */
02443 #define _PRS_SWLEVEL_RESETVALUE              0x00000000UL                         
02444 #define _PRS_SWLEVEL_MASK                    0x0000003FUL                         
02445 #define PRS_SWLEVEL_CH0LEVEL                 (0x1UL << 0)                         
02446 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT          0                                    
02447 #define _PRS_SWLEVEL_CH0LEVEL_MASK           0x1UL                                
02448 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT        0x00000000UL                         
02449 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT         (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) 
02450 #define PRS_SWLEVEL_CH1LEVEL                 (0x1UL << 1)                         
02451 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT          1                                    
02452 #define _PRS_SWLEVEL_CH1LEVEL_MASK           0x2UL                                
02453 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT        0x00000000UL                         
02454 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT         (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) 
02455 #define PRS_SWLEVEL_CH2LEVEL                 (0x1UL << 2)                         
02456 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT          2                                    
02457 #define _PRS_SWLEVEL_CH2LEVEL_MASK           0x4UL                                
02458 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT        0x00000000UL                         
02459 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT         (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) 
02460 #define PRS_SWLEVEL_CH3LEVEL                 (0x1UL << 3)                         
02461 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT          3                                    
02462 #define _PRS_SWLEVEL_CH3LEVEL_MASK           0x8UL                                
02463 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT        0x00000000UL                         
02464 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT         (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) 
02465 #define PRS_SWLEVEL_CH4LEVEL                 (0x1UL << 4)                         
02466 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT          4                                    
02467 #define _PRS_SWLEVEL_CH4LEVEL_MASK           0x10UL                               
02468 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT        0x00000000UL                         
02469 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT         (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) 
02470 #define PRS_SWLEVEL_CH5LEVEL                 (0x1UL << 5)                         
02471 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT          5                                    
02472 #define _PRS_SWLEVEL_CH5LEVEL_MASK           0x20UL                               
02473 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT        0x00000000UL                         
02474 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT         (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) 
02476 /* Bit fields for PRS ROUTE */
02477 #define _PRS_ROUTE_RESETVALUE                0x00000000UL                       
02478 #define _PRS_ROUTE_MASK                      0x0000070FUL                       
02479 #define PRS_ROUTE_CH0PEN                     (0x1UL << 0)                       
02480 #define _PRS_ROUTE_CH0PEN_SHIFT              0                                  
02481 #define _PRS_ROUTE_CH0PEN_MASK               0x1UL                              
02482 #define _PRS_ROUTE_CH0PEN_DEFAULT            0x00000000UL                       
02483 #define PRS_ROUTE_CH0PEN_DEFAULT             (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   
02484 #define PRS_ROUTE_CH1PEN                     (0x1UL << 1)                       
02485 #define _PRS_ROUTE_CH1PEN_SHIFT              1                                  
02486 #define _PRS_ROUTE_CH1PEN_MASK               0x2UL                              
02487 #define _PRS_ROUTE_CH1PEN_DEFAULT            0x00000000UL                       
02488 #define PRS_ROUTE_CH1PEN_DEFAULT             (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   
02489 #define PRS_ROUTE_CH2PEN                     (0x1UL << 2)                       
02490 #define _PRS_ROUTE_CH2PEN_SHIFT              2                                  
02491 #define _PRS_ROUTE_CH2PEN_MASK               0x4UL                              
02492 #define _PRS_ROUTE_CH2PEN_DEFAULT            0x00000000UL                       
02493 #define PRS_ROUTE_CH2PEN_DEFAULT             (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   
02494 #define PRS_ROUTE_CH3PEN                     (0x1UL << 3)                       
02495 #define _PRS_ROUTE_CH3PEN_SHIFT              3                                  
02496 #define _PRS_ROUTE_CH3PEN_MASK               0x8UL                              
02497 #define _PRS_ROUTE_CH3PEN_DEFAULT            0x00000000UL                       
02498 #define PRS_ROUTE_CH3PEN_DEFAULT             (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   
02499 #define _PRS_ROUTE_LOCATION_SHIFT            8                                  
02500 #define _PRS_ROUTE_LOCATION_MASK             0x700UL                            
02501 #define _PRS_ROUTE_LOCATION_LOC0             0x00000000UL                       
02502 #define _PRS_ROUTE_LOCATION_DEFAULT          0x00000000UL                       
02503 #define _PRS_ROUTE_LOCATION_LOC1             0x00000001UL                       
02504 #define _PRS_ROUTE_LOCATION_LOC2             0x00000002UL                       
02505 #define _PRS_ROUTE_LOCATION_LOC3             0x00000003UL                       
02506 #define PRS_ROUTE_LOCATION_LOC0              (_PRS_ROUTE_LOCATION_LOC0 << 8)    
02507 #define PRS_ROUTE_LOCATION_DEFAULT           (_PRS_ROUTE_LOCATION_DEFAULT << 8) 
02508 #define PRS_ROUTE_LOCATION_LOC1              (_PRS_ROUTE_LOCATION_LOC1 << 8)    
02509 #define PRS_ROUTE_LOCATION_LOC2              (_PRS_ROUTE_LOCATION_LOC2 << 8)    
02510 #define PRS_ROUTE_LOCATION_LOC3              (_PRS_ROUTE_LOCATION_LOC3 << 8)    
02512 /* Bit fields for PRS CH_CTRL */
02513 #define _PRS_CH_CTRL_RESETVALUE              0x00000000UL                             
02514 #define _PRS_CH_CTRL_MASK                    0x133F0007UL                             
02515 #define _PRS_CH_CTRL_SIGSEL_SHIFT            0                                        
02516 #define _PRS_CH_CTRL_SIGSEL_MASK             0x7UL                                    
02517 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT          0x00000000UL                             
02518 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT         0x00000000UL                             
02519 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX       0x00000000UL                             
02520 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX       0x00000000UL                             
02521 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF         0x00000000UL                             
02522 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF         0x00000000UL                             
02523 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF         0x00000000UL                             
02524 #define _PRS_CH_CTRL_SIGSEL_USBSOF           0x00000000UL                             
02525 #define _PRS_CH_CTRL_SIGSEL_RTCOF            0x00000000UL                             
02526 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0         0x00000000UL                             
02527 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8         0x00000000UL                             
02528 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC         0x00000000UL                             
02529 #define _PRS_CH_CTRL_SIGSEL_USART0TXC        0x00000001UL                             
02530 #define _PRS_CH_CTRL_SIGSEL_USART1TXC        0x00000001UL                             
02531 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF         0x00000001UL                             
02532 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF         0x00000001UL                             
02533 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF         0x00000001UL                             
02534 #define _PRS_CH_CTRL_SIGSEL_USBSOFSR         0x00000001UL                             
02535 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0         0x00000001UL                             
02536 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1         0x00000001UL                             
02537 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9         0x00000001UL                             
02538 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV    0x00000002UL                             
02539 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV    0x00000002UL                             
02540 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0        0x00000002UL                             
02541 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0        0x00000002UL                             
02542 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0        0x00000002UL                             
02543 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1         0x00000002UL                             
02544 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2         0x00000002UL                             
02545 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10        0x00000002UL                             
02546 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1        0x00000003UL                             
02547 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1        0x00000003UL                             
02548 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1        0x00000003UL                             
02549 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3         0x00000003UL                             
02550 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11        0x00000003UL                             
02551 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2        0x00000004UL                             
02552 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2        0x00000004UL                             
02553 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2        0x00000004UL                             
02554 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4         0x00000004UL                             
02555 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12        0x00000004UL                             
02556 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5         0x00000005UL                             
02557 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13        0x00000005UL                             
02558 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6         0x00000006UL                             
02559 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14        0x00000006UL                             
02560 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7         0x00000007UL                             
02561 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15        0x00000007UL                             
02562 #define PRS_CH_CTRL_SIGSEL_VCMPOUT           (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)       
02563 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT          (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)      
02564 #define PRS_CH_CTRL_SIGSEL_USART0IRTX        (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)    
02565 #define PRS_CH_CTRL_SIGSEL_USART1IRTX        (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0)    
02566 #define PRS_CH_CTRL_SIGSEL_TIMER0UF          (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)      
02567 #define PRS_CH_CTRL_SIGSEL_TIMER1UF          (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)      
02568 #define PRS_CH_CTRL_SIGSEL_TIMER2UF          (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)      
02569 #define PRS_CH_CTRL_SIGSEL_USBSOF            (_PRS_CH_CTRL_SIGSEL_USBSOF << 0)        
02570 #define PRS_CH_CTRL_SIGSEL_RTCOF             (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)         
02571 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0          (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)      
02572 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8          (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)      
02573 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC          (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)      
02574 #define PRS_CH_CTRL_SIGSEL_USART0TXC         (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)     
02575 #define PRS_CH_CTRL_SIGSEL_USART1TXC         (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)     
02576 #define PRS_CH_CTRL_SIGSEL_TIMER0OF          (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)      
02577 #define PRS_CH_CTRL_SIGSEL_TIMER1OF          (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)      
02578 #define PRS_CH_CTRL_SIGSEL_TIMER2OF          (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)      
02579 #define PRS_CH_CTRL_SIGSEL_USBSOFSR          (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0)      
02580 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0          (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)      
02581 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1          (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)      
02582 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9          (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)      
02583 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) 
02584 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 
02585 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0         (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)     
02586 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0         (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)     
02587 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0         (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)     
02588 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1          (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)      
02589 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2          (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)      
02590 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10         (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)     
02591 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1         (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)     
02592 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1         (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)     
02593 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1         (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)     
02594 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3          (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)      
02595 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11         (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)     
02596 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2         (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)     
02597 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2         (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)     
02598 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2         (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)     
02599 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4          (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)      
02600 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12         (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)     
02601 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5          (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)      
02602 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13         (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)     
02603 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6          (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)      
02604 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14         (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)     
02605 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7          (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)      
02606 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15         (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)     
02607 #define _PRS_CH_CTRL_SOURCESEL_SHIFT         16                                       
02608 #define _PRS_CH_CTRL_SOURCESEL_MASK          0x3F0000UL                               
02609 #define _PRS_CH_CTRL_SOURCESEL_NONE          0x00000000UL                             
02610 #define _PRS_CH_CTRL_SOURCESEL_VCMP          0x00000001UL                             
02611 #define _PRS_CH_CTRL_SOURCESEL_ACMP0         0x00000002UL                             
02612 #define _PRS_CH_CTRL_SOURCESEL_USART0        0x00000010UL                             
02613 #define _PRS_CH_CTRL_SOURCESEL_USART1        0x00000011UL                             
02614 #define _PRS_CH_CTRL_SOURCESEL_TIMER0        0x0000001CUL                             
02615 #define _PRS_CH_CTRL_SOURCESEL_TIMER1        0x0000001DUL                             
02616 #define _PRS_CH_CTRL_SOURCESEL_TIMER2        0x0000001EUL                             
02617 #define _PRS_CH_CTRL_SOURCESEL_USB           0x00000024UL                             
02618 #define _PRS_CH_CTRL_SOURCESEL_RTC           0x00000028UL                             
02619 #define _PRS_CH_CTRL_SOURCESEL_GPIOL         0x00000030UL                             
02620 #define _PRS_CH_CTRL_SOURCESEL_GPIOH         0x00000031UL                             
02621 #define _PRS_CH_CTRL_SOURCESEL_PCNT0         0x00000036UL                             
02622 #define PRS_CH_CTRL_SOURCESEL_NONE           (_PRS_CH_CTRL_SOURCESEL_NONE << 16)      
02623 #define PRS_CH_CTRL_SOURCESEL_VCMP           (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)      
02624 #define PRS_CH_CTRL_SOURCESEL_ACMP0          (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)     
02625 #define PRS_CH_CTRL_SOURCESEL_USART0         (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)    
02626 #define PRS_CH_CTRL_SOURCESEL_USART1         (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)    
02627 #define PRS_CH_CTRL_SOURCESEL_TIMER0         (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)    
02628 #define PRS_CH_CTRL_SOURCESEL_TIMER1         (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)    
02629 #define PRS_CH_CTRL_SOURCESEL_TIMER2         (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)    
02630 #define PRS_CH_CTRL_SOURCESEL_USB            (_PRS_CH_CTRL_SOURCESEL_USB << 16)       
02631 #define PRS_CH_CTRL_SOURCESEL_RTC            (_PRS_CH_CTRL_SOURCESEL_RTC << 16)       
02632 #define PRS_CH_CTRL_SOURCESEL_GPIOL          (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)     
02633 #define PRS_CH_CTRL_SOURCESEL_GPIOH          (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)     
02634 #define PRS_CH_CTRL_SOURCESEL_PCNT0          (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16)     
02635 #define _PRS_CH_CTRL_EDSEL_SHIFT             24                                       
02636 #define _PRS_CH_CTRL_EDSEL_MASK              0x3000000UL                              
02637 #define _PRS_CH_CTRL_EDSEL_DEFAULT           0x00000000UL                             
02638 #define _PRS_CH_CTRL_EDSEL_OFF               0x00000000UL                             
02639 #define _PRS_CH_CTRL_EDSEL_POSEDGE           0x00000001UL                             
02640 #define _PRS_CH_CTRL_EDSEL_NEGEDGE           0x00000002UL                             
02641 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES         0x00000003UL                             
02642 #define PRS_CH_CTRL_EDSEL_DEFAULT            (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)       
02643 #define PRS_CH_CTRL_EDSEL_OFF                (_PRS_CH_CTRL_EDSEL_OFF << 24)           
02644 #define PRS_CH_CTRL_EDSEL_POSEDGE            (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)       
02645 #define PRS_CH_CTRL_EDSEL_NEGEDGE            (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)       
02646 #define PRS_CH_CTRL_EDSEL_BOTHEDGES          (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)     
02647 #define PRS_CH_CTRL_ASYNC                    (0x1UL << 28)                            
02648 #define _PRS_CH_CTRL_ASYNC_SHIFT             28                                       
02649 #define _PRS_CH_CTRL_ASYNC_MASK              0x10000000UL                             
02650 #define _PRS_CH_CTRL_ASYNC_DEFAULT           0x00000000UL                             
02651 #define PRS_CH_CTRL_ASYNC_DEFAULT            (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)       
02653 /* Bit fields for PRS TRACECTRL */
02654 #define _PRS_TRACECTRL_RESETVALUE            0x00000000UL                           
02655 #define _PRS_TRACECTRL_MASK                  0x00000F0FUL                           
02656 #define PRS_TRACECTRL_TSTARTEN               (0x1UL << 0)                           
02657 #define _PRS_TRACECTRL_TSTARTEN_SHIFT        0                                      
02658 #define _PRS_TRACECTRL_TSTARTEN_MASK         0x1UL                                  
02659 #define _PRS_TRACECTRL_TSTARTEN_DEFAULT      0x00000000UL                           
02660 #define PRS_TRACECTRL_TSTARTEN_DEFAULT       (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) 
02661 #define _PRS_TRACECTRL_TSTART_SHIFT          1                                      
02662 #define _PRS_TRACECTRL_TSTART_MASK           0xEUL                                  
02663 #define _PRS_TRACECTRL_TSTART_DEFAULT        0x00000000UL                           
02664 #define _PRS_TRACECTRL_TSTART_PRSCH0         0x00000000UL                           
02665 #define _PRS_TRACECTRL_TSTART_PRSCH1         0x00000001UL                           
02666 #define _PRS_TRACECTRL_TSTART_PRSCH2         0x00000002UL                           
02667 #define _PRS_TRACECTRL_TSTART_PRSCH3         0x00000003UL                           
02668 #define _PRS_TRACECTRL_TSTART_PRSCH4         0x00000004UL                           
02669 #define _PRS_TRACECTRL_TSTART_PRSCH5         0x00000005UL                           
02670 #define PRS_TRACECTRL_TSTART_DEFAULT         (_PRS_TRACECTRL_TSTART_DEFAULT << 1)   
02671 #define PRS_TRACECTRL_TSTART_PRSCH0          (_PRS_TRACECTRL_TSTART_PRSCH0 << 1)    
02672 #define PRS_TRACECTRL_TSTART_PRSCH1          (_PRS_TRACECTRL_TSTART_PRSCH1 << 1)    
02673 #define PRS_TRACECTRL_TSTART_PRSCH2          (_PRS_TRACECTRL_TSTART_PRSCH2 << 1)    
02674 #define PRS_TRACECTRL_TSTART_PRSCH3          (_PRS_TRACECTRL_TSTART_PRSCH3 << 1)    
02675 #define PRS_TRACECTRL_TSTART_PRSCH4          (_PRS_TRACECTRL_TSTART_PRSCH4 << 1)    
02676 #define PRS_TRACECTRL_TSTART_PRSCH5          (_PRS_TRACECTRL_TSTART_PRSCH5 << 1)    
02677 #define PRS_TRACECTRL_TSTOPEN                (0x1UL << 8)                           
02678 #define _PRS_TRACECTRL_TSTOPEN_SHIFT         8                                      
02679 #define _PRS_TRACECTRL_TSTOPEN_MASK          0x100UL                                
02680 #define _PRS_TRACECTRL_TSTOPEN_DEFAULT       0x00000000UL                           
02681 #define PRS_TRACECTRL_TSTOPEN_DEFAULT        (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8)  
02682 #define _PRS_TRACECTRL_TSTOP_SHIFT           9                                      
02683 #define _PRS_TRACECTRL_TSTOP_MASK            0xE00UL                                
02684 #define _PRS_TRACECTRL_TSTOP_DEFAULT         0x00000000UL                           
02685 #define _PRS_TRACECTRL_TSTOP_PRSCH0          0x00000000UL                           
02686 #define _PRS_TRACECTRL_TSTOP_PRSCH1          0x00000001UL                           
02687 #define _PRS_TRACECTRL_TSTOP_PRSCH2          0x00000002UL                           
02688 #define _PRS_TRACECTRL_TSTOP_PRSCH3          0x00000003UL                           
02689 #define _PRS_TRACECTRL_TSTOP_PRSCH4          0x00000004UL                           
02690 #define _PRS_TRACECTRL_TSTOP_PRSCH5          0x00000005UL                           
02691 #define PRS_TRACECTRL_TSTOP_DEFAULT          (_PRS_TRACECTRL_TSTOP_DEFAULT << 9)    
02692 #define PRS_TRACECTRL_TSTOP_PRSCH0           (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9)     
02693 #define PRS_TRACECTRL_TSTOP_PRSCH1           (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9)     
02694 #define PRS_TRACECTRL_TSTOP_PRSCH2           (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9)     
02695 #define PRS_TRACECTRL_TSTOP_PRSCH3           (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9)     
02696 #define PRS_TRACECTRL_TSTOP_PRSCH4           (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9)     
02697 #define PRS_TRACECTRL_TSTOP_PRSCH5           (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9)     
02703 /**************************************************************************/
02707 #define MSC_UNLOCK_CODE      0x1B71 
02708 #define EMU_UNLOCK_CODE      0xADE8 
02709 #define CMU_UNLOCK_CODE      0x580E 
02710 #define TIMER_UNLOCK_CODE    0xCE80 
02711 #define GPIO_UNLOCK_CODE     0xA534 
02717 /**************************************************************************/
02722 #include "efm32hg_af_ports.h"
02723 #include "efm32hg_af_pins.h"
02724 
02727 /**************************************************************************/
02740 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02741   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02742 
02747 #ifdef __cplusplus
02748 }
02749 #endif
02750 #endif /* __SILICON_LABS_EFM32HG308F64_H__ */