release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg210f64.h

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00001 /**************************************************************************/
00034 #ifndef __SILICON_LABS_EFM32HG210F64_H__
00035 #define __SILICON_LABS_EFM32HG210F64_H__
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
00055   NonMaskableInt_IRQn = -14,                
00056   HardFault_IRQn      = -13,                
00057   SVCall_IRQn         = -5,                 
00058   PendSV_IRQn         = -2,                 
00059   SysTick_IRQn        = -1,                 
00061 /******  EFM32HG Peripheral Interrupt Numbers *********************************************/
00062   DMA_IRQn            = 0,  
00063   GPIO_EVEN_IRQn      = 1,  
00064   TIMER0_IRQn         = 2,  
00065   ACMP0_IRQn          = 3,  
00066   ADC0_IRQn           = 4,  
00067   I2C0_IRQn           = 5,  
00068   GPIO_ODD_IRQn       = 6,  
00069   TIMER1_IRQn         = 7,  
00070   USART1_RX_IRQn      = 8,  
00071   USART1_TX_IRQn      = 9,  
00072   LEUART0_IRQn        = 10, 
00073   PCNT0_IRQn          = 11, 
00074   RTC_IRQn            = 12, 
00075   CMU_IRQn            = 13, 
00076   VCMP_IRQn           = 14, 
00077   MSC_IRQn            = 15, 
00078   AES_IRQn            = 16, 
00079   USART0_RX_IRQn      = 17, 
00080   USART0_TX_IRQn      = 18, 
00081   TIMER2_IRQn         = 20, 
00082 } IRQn_Type;
00083 
00084 /**************************************************************************/
00089 #define __MPU_PRESENT             0 
00090 #define __VTOR_PRESENT            1 
00091 #define __NVIC_PRIO_BITS          2 
00092 #define __Vendor_SysTickConfig    0 
00096 /**************************************************************************/
00102 #define _EFM32_HAPPY_FAMILY             1 
00103 #define _EFM_DEVICE                       
00104 #define _SILICON_LABS_32B_PLATFORM_1      
00105 #define _SILICON_LABS_32B_PLATFORM      1 
00107 /* If part number is not defined as compiler option, define it */
00108 #if !defined(EFM32HG210F64)
00109 #define EFM32HG210F64    1 
00110 #endif
00111 
00113 #define PART_NUMBER          "EFM32HG210F64" 
00116 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00117 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00118 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00119 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00120 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00121 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00122 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00123 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00124 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL) 
00125 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)    
00126 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL) 
00127 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)       
00128 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00129 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00130 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00131 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00132 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00133 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00134 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00135 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00136 #define DEVICE_MEM_BASE      ((uint32_t) 0xF0040000UL) 
00137 #define DEVICE_MEM_SIZE      ((uint32_t) 0x1000UL)     
00138 #define DEVICE_MEM_END       ((uint32_t) 0xF0040FFFUL) 
00139 #define DEVICE_MEM_BITS      ((uint32_t) 0x12UL)       
00140 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00141 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00142 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00143 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00146 #define FLASH_BASE           (0x00000000UL) 
00147 #define FLASH_SIZE           (0x00010000UL) 
00148 #define FLASH_PAGE_SIZE      1024           
00149 #define SRAM_BASE            (0x20000000UL) 
00150 #define SRAM_SIZE            (0x00002000UL) 
00151 #define __CM0PLUS_REV        0x001          
00152 #define PRS_CHAN_COUNT       6              
00153 #define DMA_CHAN_COUNT       6              
00156 #define AFCHAN_MAX           42
00157 #define AFCHANLOC_MAX        7
00158 
00159 #define AFACHAN_MAX          27
00160 
00161 /* Part number capabilities */
00162 
00163 #define TIMER_PRESENT         
00164 #define TIMER_COUNT         3 
00165 #define ACMP_PRESENT          
00166 #define ACMP_COUNT          1 
00167 #define USART_PRESENT         
00168 #define USART_COUNT         2 
00169 #define IDAC_PRESENT          
00170 #define IDAC_COUNT          1 
00171 #define ADC_PRESENT           
00172 #define ADC_COUNT           1 
00173 #define LEUART_PRESENT        
00174 #define LEUART_COUNT        1 
00175 #define PCNT_PRESENT          
00176 #define PCNT_COUNT          1 
00177 #define I2C_PRESENT           
00178 #define I2C_COUNT           1 
00179 #define AES_PRESENT
00180 #define AES_COUNT           1
00181 #define DMA_PRESENT
00182 #define DMA_COUNT           1
00183 #define LE_PRESENT
00184 #define LE_COUNT            1
00185 #define USBLE_PRESENT
00186 #define USBLE_COUNT         1
00187 #define MSC_PRESENT
00188 #define MSC_COUNT           1
00189 #define EMU_PRESENT
00190 #define EMU_COUNT           1
00191 #define RMU_PRESENT
00192 #define RMU_COUNT           1
00193 #define CMU_PRESENT
00194 #define CMU_COUNT           1
00195 #define PRS_PRESENT
00196 #define PRS_COUNT           1
00197 #define GPIO_PRESENT
00198 #define GPIO_COUNT          1
00199 #define VCMP_PRESENT
00200 #define VCMP_COUNT          1
00201 #define RTC_PRESENT
00202 #define RTC_COUNT           1
00203 #define HFXTAL_PRESENT
00204 #define HFXTAL_COUNT        1
00205 #define LFXTAL_PRESENT
00206 #define LFXTAL_COUNT        1
00207 #define USHFRCO_PRESENT
00208 #define USHFRCO_COUNT       1
00209 #define WDOG_PRESENT
00210 #define WDOG_COUNT          1
00211 #define DBG_PRESENT
00212 #define DBG_COUNT           1
00213 #define MTB_PRESENT
00214 #define MTB_COUNT           1
00215 #define BOOTLOADER_PRESENT
00216 #define BOOTLOADER_COUNT    1
00217 #define ANALOG_PRESENT
00218 #define ANALOG_COUNT        1
00219 
00222 #define ARM_MATH_CM0PLUS
00223 #include "arm_math.h"       /* To get __CLZ definitions etc. */
00224 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
00225 #include "system_efm32hg.h" /* System Header */
00226 
00227 /**************************************************************************/
00233 #include "efm32hg_aes.h"
00234 #include "efm32hg_dma_ch.h"
00235 #include "efm32hg_dma.h"
00236 #include "efm32hg_msc.h"
00237 #include "efm32hg_emu.h"
00238 #include "efm32hg_rmu.h"
00239 
00240 /**************************************************************************/
00245 typedef struct
00246 {
00247   __IO uint32_t CTRL;          
00248   __IO uint32_t HFCORECLKDIV;  
00249   __IO uint32_t HFPERCLKDIV;   
00250   __IO uint32_t HFRCOCTRL;     
00251   __IO uint32_t LFRCOCTRL;     
00252   __IO uint32_t AUXHFRCOCTRL;  
00253   __IO uint32_t CALCTRL;       
00254   __IO uint32_t CALCNT;        
00255   __IO uint32_t OSCENCMD;      
00256   __IO uint32_t CMD;           
00257   __IO uint32_t LFCLKSEL;      
00258   __I uint32_t  STATUS;        
00259   __I uint32_t  IF;            
00260   __IO uint32_t IFS;           
00261   __IO uint32_t IFC;           
00262   __IO uint32_t IEN;           
00263   __IO uint32_t HFCORECLKEN0;  
00264   __IO uint32_t HFPERCLKEN0;   
00265   uint32_t      RESERVED0[2];  
00266   __I uint32_t  SYNCBUSY;      
00267   __IO uint32_t FREEZE;        
00268   __IO uint32_t LFACLKEN0;     
00269   uint32_t      RESERVED1[1];  
00270   __IO uint32_t LFBCLKEN0;     
00271   __IO uint32_t LFCCLKEN0;     
00272   __IO uint32_t LFAPRESC0;     
00273   uint32_t      RESERVED2[1];  
00274   __IO uint32_t LFBPRESC0;     
00275   uint32_t      RESERVED3[1];  
00276   __IO uint32_t PCNTCTRL;      
00278   uint32_t      RESERVED4[1];  
00279   __IO uint32_t ROUTE;         
00280   __IO uint32_t LOCK;          
00282   uint32_t      RESERVED5[18]; 
00283   __IO uint32_t USBCRCTRL;     
00284   __IO uint32_t USHFRCOCTRL;   
00285   __IO uint32_t USHFRCOTUNE;   
00286   __IO uint32_t USHFRCOCONF;   
00287 } CMU_TypeDef;                 
00289 #include "efm32hg_timer_cc.h"
00290 #include "efm32hg_timer.h"
00291 #include "efm32hg_acmp.h"
00292 #include "efm32hg_usart.h"
00293 #include "efm32hg_prs_ch.h"
00294 
00295 /**************************************************************************/
00300 typedef struct
00301 {
00302   __IO uint32_t  SWPULSE;      
00303   __IO uint32_t  SWLEVEL;      
00304   __IO uint32_t  ROUTE;        
00306   uint32_t       RESERVED0[1]; 
00307   PRS_CH_TypeDef CH[6];        
00309   uint32_t       RESERVED1[6]; 
00310   __IO uint32_t  TRACECTRL;    
00311 } PRS_TypeDef;                 
00313 #include "efm32hg_idac.h"
00314 #include "efm32hg_gpio_p.h"
00315 #include "efm32hg_gpio.h"
00316 #include "efm32hg_vcmp.h"
00317 #include "efm32hg_adc.h"
00318 #include "efm32hg_leuart.h"
00319 #include "efm32hg_pcnt.h"
00320 #include "efm32hg_i2c.h"
00321 #include "efm32hg_rtc.h"
00322 #include "efm32hg_wdog.h"
00323 #include "efm32hg_mtb.h"
00324 #include "efm32hg_dma_descriptor.h"
00325 #include "efm32hg_devinfo.h"
00326 #include "efm32hg_romtable.h"
00327 #include "efm32hg_calibrate.h"
00328 
00331 /**************************************************************************/
00336 #define AES_BASE          (0x400E0000UL) 
00337 #define DMA_BASE          (0x400C2000UL) 
00338 #define MSC_BASE          (0x400C0000UL) 
00339 #define EMU_BASE          (0x400C6000UL) 
00340 #define RMU_BASE          (0x400CA000UL) 
00341 #define CMU_BASE          (0x400C8000UL) 
00342 #define TIMER0_BASE       (0x40010000UL) 
00343 #define TIMER1_BASE       (0x40010400UL) 
00344 #define TIMER2_BASE       (0x40010800UL) 
00345 #define ACMP0_BASE        (0x40001000UL) 
00346 #define USART0_BASE       (0x4000C000UL) 
00347 #define USART1_BASE       (0x4000C400UL) 
00348 #define PRS_BASE          (0x400CC000UL) 
00349 #define IDAC0_BASE        (0x40004000UL) 
00350 #define GPIO_BASE         (0x40006000UL) 
00351 #define VCMP_BASE         (0x40000000UL) 
00352 #define ADC0_BASE         (0x40002000UL) 
00353 #define LEUART0_BASE      (0x40084000UL) 
00354 #define PCNT0_BASE        (0x40086000UL) 
00355 #define I2C0_BASE         (0x4000A000UL) 
00356 #define RTC_BASE          (0x40080000UL) 
00357 #define WDOG_BASE         (0x40088000UL) 
00358 #define MTB_BASE          (0xF0040000UL) 
00359 #define CALIBRATE_BASE    (0x0FE08000UL) 
00360 #define DEVINFO_BASE      (0x0FE081B0UL) 
00361 #define ROMTABLE_BASE     (0xF00FFFD0UL) 
00362 #define LOCKBITS_BASE     (0x0FE04000UL) 
00363 #define USERDATA_BASE     (0x0FE00000UL) 
00367 /**************************************************************************/
00372 #define AES          ((AES_TypeDef *) AES_BASE)             
00373 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00374 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00375 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00376 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00377 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00378 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00379 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00380 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        
00381 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00382 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00383 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00384 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00385 #define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          
00386 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00387 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00388 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
00389 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00390 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00391 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00392 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00393 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00394 #define MTB          ((MTB_TypeDef *) MTB_BASE)             
00395 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00396 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00397 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00401 /**************************************************************************/
00406 /**************************************************************************/
00411 #define PRS_VCMP_OUT          ((1 << 16) + 0)  
00412 #define PRS_ACMP0_OUT         ((2 << 16) + 0)  
00413 #define PRS_ADC0_SINGLE       ((8 << 16) + 0)  
00414 #define PRS_ADC0_SCAN         ((8 << 16) + 1)  
00415 #define PRS_USART0_IRTX       ((16 << 16) + 0) 
00416 #define PRS_USART0_TXC        ((16 << 16) + 1) 
00417 #define PRS_USART0_RXDATAV    ((16 << 16) + 2) 
00418 #define PRS_USART1_IRTX       ((17 << 16) + 0) 
00419 #define PRS_USART1_TXC        ((17 << 16) + 1) 
00420 #define PRS_USART1_RXDATAV    ((17 << 16) + 2) 
00421 #define PRS_TIMER0_UF         ((28 << 16) + 0) 
00422 #define PRS_TIMER0_OF         ((28 << 16) + 1) 
00423 #define PRS_TIMER0_CC0        ((28 << 16) + 2) 
00424 #define PRS_TIMER0_CC1        ((28 << 16) + 3) 
00425 #define PRS_TIMER0_CC2        ((28 << 16) + 4) 
00426 #define PRS_TIMER1_UF         ((29 << 16) + 0) 
00427 #define PRS_TIMER1_OF         ((29 << 16) + 1) 
00428 #define PRS_TIMER1_CC0        ((29 << 16) + 2) 
00429 #define PRS_TIMER1_CC1        ((29 << 16) + 3) 
00430 #define PRS_TIMER1_CC2        ((29 << 16) + 4) 
00431 #define PRS_TIMER2_UF         ((30 << 16) + 0) 
00432 #define PRS_TIMER2_OF         ((30 << 16) + 1) 
00433 #define PRS_TIMER2_CC0        ((30 << 16) + 2) 
00434 #define PRS_TIMER2_CC1        ((30 << 16) + 3) 
00435 #define PRS_TIMER2_CC2        ((30 << 16) + 4) 
00436 #define PRS_RTC_OF            ((40 << 16) + 0) 
00437 #define PRS_RTC_COMP0         ((40 << 16) + 1) 
00438 #define PRS_RTC_COMP1         ((40 << 16) + 2) 
00439 #define PRS_GPIO_PIN0         ((48 << 16) + 0) 
00440 #define PRS_GPIO_PIN1         ((48 << 16) + 1) 
00441 #define PRS_GPIO_PIN2         ((48 << 16) + 2) 
00442 #define PRS_GPIO_PIN3         ((48 << 16) + 3) 
00443 #define PRS_GPIO_PIN4         ((48 << 16) + 4) 
00444 #define PRS_GPIO_PIN5         ((48 << 16) + 5) 
00445 #define PRS_GPIO_PIN6         ((48 << 16) + 6) 
00446 #define PRS_GPIO_PIN7         ((48 << 16) + 7) 
00447 #define PRS_GPIO_PIN8         ((49 << 16) + 0) 
00448 #define PRS_GPIO_PIN9         ((49 << 16) + 1) 
00449 #define PRS_GPIO_PIN10        ((49 << 16) + 2) 
00450 #define PRS_GPIO_PIN11        ((49 << 16) + 3) 
00451 #define PRS_GPIO_PIN12        ((49 << 16) + 4) 
00452 #define PRS_GPIO_PIN13        ((49 << 16) + 5) 
00453 #define PRS_GPIO_PIN14        ((49 << 16) + 6) 
00454 #define PRS_GPIO_PIN15        ((49 << 16) + 7) 
00455 #define PRS_PCNT0_TCC         ((54 << 16) + 0) 
00459 #include "efm32hg_dmareq.h"
00460 #include "efm32hg_dmactrl.h"
00461 
00462 /**************************************************************************/
00467 /* Bit fields for CMU CTRL */
00468 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             
00469 #define _CMU_CTRL_MASK                              0x07FFFEEFUL                             
00470 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        
00471 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    
00472 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                             
00473 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                             
00474 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                             
00475 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                             
00476 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        
00477 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)           
00478 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      
00479 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      
00480 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                        
00481 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                    
00482 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                             
00483 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                             
00484 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                             
00485 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                             
00486 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                             
00487 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       
00488 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       
00489 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       
00490 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       
00491 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      
00492 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                        
00493 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                   
00494 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                             
00495 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      
00496 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                             
00497 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                        
00498 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                   
00499 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                             
00500 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 
00501 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                        
00502 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                  
00503 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                             
00504 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                             
00505 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                             
00506 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                             
00507 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                             
00508 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     
00509 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   
00510 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    
00511 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     
00512 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   
00513 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                       
00514 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                 
00515 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                             
00516 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                             
00517 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                             
00518 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                             
00519 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       
00520 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)          
00521 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     
00522 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     
00523 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                            
00524 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                       
00525 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                 
00526 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                             
00527 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                             
00528 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                             
00529 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      
00530 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      
00531 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     
00532 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                       
00533 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                
00534 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                             
00535 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)       
00536 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                            
00537 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                       
00538 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                
00539 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                             
00540 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     
00541 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                       
00542 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                
00543 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                             
00544 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                             
00545 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                             
00546 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                             
00547 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                             
00548 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    
00549 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   
00550 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  
00551 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    
00552 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  
00553 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                       
00554 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                               
00555 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                             
00556 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                             
00557 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                             
00558 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                             
00559 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                             
00560 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                             
00561 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                             
00562 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                             
00563 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                             
00564 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     
00565 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       
00566 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        
00567 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      
00568 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      
00569 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      
00570 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     
00571 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      
00572 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)    
00573 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                       
00574 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                              
00575 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                             
00576 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                             
00577 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                             
00578 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                             
00579 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                             
00580 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                             
00581 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                             
00582 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                             
00583 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                             
00584 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO                0x00000008UL                             
00585 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     
00586 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       
00587 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        
00588 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)       
00589 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)       
00590 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)       
00591 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)      
00592 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)      
00593 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)   
00594 #define CMU_CTRL_CLKOUTSEL1_USHFRCO                 (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23)     
00596 /* Bit fields for CMU HFCORECLKDIV */
00597 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
00598 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
00599 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
00600 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
00601 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
00602 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
00603 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
00604 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
00605 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
00606 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
00607 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
00608 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
00609 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
00610 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
00611 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
00612 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
00613 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
00614 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
00615 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
00616 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
00617 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
00618 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
00619 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
00620 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
00621 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
00622 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
00623 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
00624 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
00625 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
00626 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
00627 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
00628 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
00629 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
00630 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
00631 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
00633 /* Bit fields for CMU HFPERCLKDIV */
00634 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
00635 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
00636 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
00637 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
00638 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
00639 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
00640 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
00641 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
00642 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
00643 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
00644 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
00645 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
00646 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
00647 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
00648 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
00649 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
00650 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
00651 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
00652 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
00653 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
00654 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
00655 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
00656 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
00657 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
00658 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
00659 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
00660 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
00661 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
00662 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
00663 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
00664 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
00666 /* Bit fields for CMU HFRCOCTRL */
00667 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
00668 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
00669 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
00670 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
00671 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
00672 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
00673 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
00674 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
00675 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
00676 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
00677 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
00678 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
00679 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
00680 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
00681 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
00682 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
00683 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
00684 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
00685 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
00686 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
00687 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
00688 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
00689 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
00690 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
00692 /* Bit fields for CMU LFRCOCTRL */
00693 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
00694 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
00695 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
00696 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
00697 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
00698 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
00700 /* Bit fields for CMU AUXHFRCOCTRL */
00701 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
00702 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
00703 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
00704 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
00705 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
00706 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
00707 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
00708 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
00709 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
00710 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
00711 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
00712 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
00713 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
00714 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
00715 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
00716 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
00717 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
00718 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
00719 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
00720 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
00722 /* Bit fields for CMU CALCTRL */
00723 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
00724 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
00725 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
00726 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
00727 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
00728 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
00729 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
00730 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
00731 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
00732 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
00733 #define _CMU_CALCTRL_UPSEL_USHFRCO                  0x00000005UL                         
00734 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
00735 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
00736 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
00737 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
00738 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
00739 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
00740 #define CMU_CALCTRL_UPSEL_USHFRCO                   (_CMU_CALCTRL_UPSEL_USHFRCO << 0)    
00741 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
00742 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
00743 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
00744 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
00745 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
00746 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
00747 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
00748 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
00749 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
00750 #define _CMU_CALCTRL_DOWNSEL_USHFRCO                0x00000006UL                         
00751 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
00752 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
00753 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
00754 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
00755 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
00756 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
00757 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
00758 #define CMU_CALCTRL_DOWNSEL_USHFRCO                 (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3)  
00759 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
00760 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
00761 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
00762 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
00763 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
00765 /* Bit fields for CMU CALCNT */
00766 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
00767 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
00768 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
00769 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
00770 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
00771 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
00773 /* Bit fields for CMU OSCENCMD */
00774 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
00775 #define _CMU_OSCENCMD_MASK                          0x00000FFFUL                             
00776 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
00777 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
00778 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
00779 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
00780 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
00781 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
00782 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
00783 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
00784 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
00785 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
00786 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
00787 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
00788 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
00789 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
00790 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
00791 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
00792 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
00793 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
00794 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
00795 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
00796 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
00797 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
00798 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
00799 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
00800 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
00801 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
00802 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
00803 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
00804 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
00805 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
00806 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
00807 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
00808 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
00809 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
00810 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
00811 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
00812 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
00813 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
00814 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
00815 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
00816 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
00817 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
00818 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
00819 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
00820 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
00821 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
00822 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
00823 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
00824 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
00825 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
00826 #define CMU_OSCENCMD_USHFRCOEN                      (0x1UL << 10)                            
00827 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT               10                                       
00828 #define _CMU_OSCENCMD_USHFRCOEN_MASK                0x400UL                                  
00829 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT             0x00000000UL                             
00830 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT              (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10)  
00831 #define CMU_OSCENCMD_USHFRCODIS                     (0x1UL << 11)                            
00832 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT              11                                       
00833 #define _CMU_OSCENCMD_USHFRCODIS_MASK               0x800UL                                  
00834 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT            0x00000000UL                             
00835 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT             (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) 
00837 /* Bit fields for CMU CMD */
00838 #define _CMU_CMD_RESETVALUE                         0x00000000UL                         
00839 #define _CMU_CMD_MASK                               0x0000001FUL                         
00840 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                    
00841 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                
00842 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                         
00843 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                         
00844 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                         
00845 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                         
00846 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                         
00847 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2               0x00000005UL                         
00848 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0)     
00849 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)       
00850 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)        
00851 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)       
00852 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)        
00853 #define CMU_CMD_HFCLKSEL_USHFRCODIV2                (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) 
00854 #define CMU_CMD_CALSTART                            (0x1UL << 3)                         
00855 #define _CMU_CMD_CALSTART_SHIFT                     3                                    
00856 #define _CMU_CMD_CALSTART_MASK                      0x8UL                                
00857 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                         
00858 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3)     
00859 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                         
00860 #define _CMU_CMD_CALSTOP_SHIFT                      4                                    
00861 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                               
00862 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                         
00863 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)      
00865 /* Bit fields for CMU LFCLKSEL */
00866 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000015UL                             
00867 #define _CMU_LFCLKSEL_MASK                          0x0011003FUL                             
00868 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
00869 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
00870 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
00871 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
00872 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
00873 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
00874 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
00875 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
00876 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
00877 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
00878 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
00879 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
00880 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
00881 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
00882 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
00883 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
00884 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
00885 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
00886 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
00887 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
00888 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
00889 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
00890 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
00891 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
00892 #define _CMU_LFCLKSEL_LFC_SHIFT                     4                                        
00893 #define _CMU_LFCLKSEL_LFC_MASK                      0x30UL                                   
00894 #define _CMU_LFCLKSEL_LFC_DISABLED                  0x00000000UL                             
00895 #define _CMU_LFCLKSEL_LFC_DEFAULT                   0x00000001UL                             
00896 #define _CMU_LFCLKSEL_LFC_LFRCO                     0x00000001UL                             
00897 #define _CMU_LFCLKSEL_LFC_LFXO                      0x00000002UL                             
00898 #define CMU_LFCLKSEL_LFC_DISABLED                   (_CMU_LFCLKSEL_LFC_DISABLED << 4)        
00899 #define CMU_LFCLKSEL_LFC_DEFAULT                    (_CMU_LFCLKSEL_LFC_DEFAULT << 4)         
00900 #define CMU_LFCLKSEL_LFC_LFRCO                      (_CMU_LFCLKSEL_LFC_LFRCO << 4)           
00901 #define CMU_LFCLKSEL_LFC_LFXO                       (_CMU_LFCLKSEL_LFC_LFXO << 4)            
00902 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
00903 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
00904 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
00905 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
00906 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
00907 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
00908 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
00909 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
00910 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
00911 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
00912 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
00913 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
00914 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
00915 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
00916 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
00917 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
00918 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
00919 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
00921 /* Bit fields for CMU STATUS */
00922 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                               
00923 #define _CMU_STATUS_MASK                            0x04E07FFFUL                               
00924 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                               
00925 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                          
00926 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                      
00927 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                               
00928 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)        
00929 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                               
00930 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                          
00931 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                      
00932 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                               
00933 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)        
00934 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                               
00935 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                          
00936 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                      
00937 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                               
00938 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)         
00939 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                               
00940 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                          
00941 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                      
00942 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                               
00943 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)         
00944 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                               
00945 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                          
00946 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                     
00947 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                               
00948 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)     
00949 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                               
00950 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                          
00951 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                     
00952 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                               
00953 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)     
00954 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                               
00955 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                          
00956 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                     
00957 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                               
00958 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)        
00959 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                               
00960 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                          
00961 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                     
00962 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                               
00963 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)        
00964 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                               
00965 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                          
00966 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                    
00967 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                               
00968 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)         
00969 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                               
00970 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                          
00971 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                    
00972 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                               
00973 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)         
00974 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                              
00975 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                         
00976 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                    
00977 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                               
00978 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)       
00979 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                              
00980 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                         
00981 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                    
00982 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                               
00983 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)        
00984 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                              
00985 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                         
00986 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                                   
00987 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                               
00988 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)       
00989 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                              
00990 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                         
00991 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                                   
00992 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                               
00993 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)        
00994 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                              
00995 #define _CMU_STATUS_CALBSY_SHIFT                    14                                         
00996 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                                   
00997 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                               
00998 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)         
00999 #define CMU_STATUS_USHFRCOENS                       (0x1UL << 21)                              
01000 #define _CMU_STATUS_USHFRCOENS_SHIFT                21                                         
01001 #define _CMU_STATUS_USHFRCOENS_MASK                 0x200000UL                                 
01002 #define _CMU_STATUS_USHFRCOENS_DEFAULT              0x00000000UL                               
01003 #define CMU_STATUS_USHFRCOENS_DEFAULT               (_CMU_STATUS_USHFRCOENS_DEFAULT << 21)     
01004 #define CMU_STATUS_USHFRCORDY                       (0x1UL << 22)                              
01005 #define _CMU_STATUS_USHFRCORDY_SHIFT                22                                         
01006 #define _CMU_STATUS_USHFRCORDY_MASK                 0x400000UL                                 
01007 #define _CMU_STATUS_USHFRCORDY_DEFAULT              0x00000000UL                               
01008 #define CMU_STATUS_USHFRCORDY_DEFAULT               (_CMU_STATUS_USHFRCORDY_DEFAULT << 22)     
01009 #define CMU_STATUS_USHFRCOSUSPEND                   (0x1UL << 23)                              
01010 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT            23                                         
01011 #define _CMU_STATUS_USHFRCOSUSPEND_MASK             0x800000UL                                 
01012 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT          0x00000000UL                               
01013 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT           (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) 
01014 #define CMU_STATUS_USHFRCODIV2SEL                   (0x1UL << 26)                              
01015 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT            26                                         
01016 #define _CMU_STATUS_USHFRCODIV2SEL_MASK             0x4000000UL                                
01017 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT          0x00000000UL                               
01018 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT           (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) 
01020 /* Bit fields for CMU IF */
01021 #define _CMU_IF_RESETVALUE                          0x00000001UL                       
01022 #define _CMU_IF_MASK                                0x0000017FUL                       
01023 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                       
01024 #define _CMU_IF_HFRCORDY_SHIFT                      0                                  
01025 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                              
01026 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                       
01027 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)    
01028 #define CMU_IF_HFXORDY                              (0x1UL << 1)                       
01029 #define _CMU_IF_HFXORDY_SHIFT                       1                                  
01030 #define _CMU_IF_HFXORDY_MASK                        0x2UL                              
01031 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                       
01032 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)     
01033 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                       
01034 #define _CMU_IF_LFRCORDY_SHIFT                      2                                  
01035 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                              
01036 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                       
01037 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)    
01038 #define CMU_IF_LFXORDY                              (0x1UL << 3)                       
01039 #define _CMU_IF_LFXORDY_SHIFT                       3                                  
01040 #define _CMU_IF_LFXORDY_MASK                        0x8UL                              
01041 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                       
01042 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)     
01043 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                       
01044 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                  
01045 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                             
01046 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                       
01047 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
01048 #define CMU_IF_CALRDY                               (0x1UL << 5)                       
01049 #define _CMU_IF_CALRDY_SHIFT                        5                                  
01050 #define _CMU_IF_CALRDY_MASK                         0x20UL                             
01051 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                       
01052 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)      
01053 #define CMU_IF_CALOF                                (0x1UL << 6)                       
01054 #define _CMU_IF_CALOF_SHIFT                         6                                  
01055 #define _CMU_IF_CALOF_MASK                          0x40UL                             
01056 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                       
01057 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)       
01058 #define CMU_IF_USHFRCORDY                           (0x1UL << 8)                       
01059 #define _CMU_IF_USHFRCORDY_SHIFT                    8                                  
01060 #define _CMU_IF_USHFRCORDY_MASK                     0x100UL                            
01061 #define _CMU_IF_USHFRCORDY_DEFAULT                  0x00000000UL                       
01062 #define CMU_IF_USHFRCORDY_DEFAULT                   (_CMU_IF_USHFRCORDY_DEFAULT << 8)  
01064 /* Bit fields for CMU IFS */
01065 #define _CMU_IFS_RESETVALUE                         0x00000000UL                        
01066 #define _CMU_IFS_MASK                               0x0000017FUL                        
01067 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                        
01068 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                   
01069 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                               
01070 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                        
01071 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
01072 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                        
01073 #define _CMU_IFS_HFXORDY_SHIFT                      1                                   
01074 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                               
01075 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                        
01076 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)     
01077 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                        
01078 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                   
01079 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                               
01080 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                        
01081 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
01082 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                        
01083 #define _CMU_IFS_LFXORDY_SHIFT                      3                                   
01084 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                               
01085 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                        
01086 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)     
01087 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                        
01088 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                   
01089 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                              
01090 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01091 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
01092 #define CMU_IFS_CALRDY                              (0x1UL << 5)                        
01093 #define _CMU_IFS_CALRDY_SHIFT                       5                                   
01094 #define _CMU_IFS_CALRDY_MASK                        0x20UL                              
01095 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                        
01096 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)      
01097 #define CMU_IFS_CALOF                               (0x1UL << 6)                        
01098 #define _CMU_IFS_CALOF_SHIFT                        6                                   
01099 #define _CMU_IFS_CALOF_MASK                         0x40UL                              
01100 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                        
01101 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)       
01102 #define CMU_IFS_USHFRCORDY                          (0x1UL << 8)                        
01103 #define _CMU_IFS_USHFRCORDY_SHIFT                   8                                   
01104 #define _CMU_IFS_USHFRCORDY_MASK                    0x100UL                             
01105 #define _CMU_IFS_USHFRCORDY_DEFAULT                 0x00000000UL                        
01106 #define CMU_IFS_USHFRCORDY_DEFAULT                  (_CMU_IFS_USHFRCORDY_DEFAULT << 8)  
01108 /* Bit fields for CMU IFC */
01109 #define _CMU_IFC_RESETVALUE                         0x00000000UL                        
01110 #define _CMU_IFC_MASK                               0x0000017FUL                        
01111 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                        
01112 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                   
01113 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                               
01114 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                        
01115 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
01116 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                        
01117 #define _CMU_IFC_HFXORDY_SHIFT                      1                                   
01118 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                               
01119 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                        
01120 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)     
01121 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                        
01122 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                   
01123 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                               
01124 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                        
01125 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
01126 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                        
01127 #define _CMU_IFC_LFXORDY_SHIFT                      3                                   
01128 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                               
01129 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                        
01130 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)     
01131 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                        
01132 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                   
01133 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                              
01134 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01135 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
01136 #define CMU_IFC_CALRDY                              (0x1UL << 5)                        
01137 #define _CMU_IFC_CALRDY_SHIFT                       5                                   
01138 #define _CMU_IFC_CALRDY_MASK                        0x20UL                              
01139 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                        
01140 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)      
01141 #define CMU_IFC_CALOF                               (0x1UL << 6)                        
01142 #define _CMU_IFC_CALOF_SHIFT                        6                                   
01143 #define _CMU_IFC_CALOF_MASK                         0x40UL                              
01144 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                        
01145 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)       
01146 #define CMU_IFC_USHFRCORDY                          (0x1UL << 8)                        
01147 #define _CMU_IFC_USHFRCORDY_SHIFT                   8                                   
01148 #define _CMU_IFC_USHFRCORDY_MASK                    0x100UL                             
01149 #define _CMU_IFC_USHFRCORDY_DEFAULT                 0x00000000UL                        
01150 #define CMU_IFC_USHFRCORDY_DEFAULT                  (_CMU_IFC_USHFRCORDY_DEFAULT << 8)  
01152 /* Bit fields for CMU IEN */
01153 #define _CMU_IEN_RESETVALUE                         0x00000000UL                        
01154 #define _CMU_IEN_MASK                               0x0000017FUL                        
01155 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                        
01156 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                   
01157 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                               
01158 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                        
01159 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
01160 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                        
01161 #define _CMU_IEN_HFXORDY_SHIFT                      1                                   
01162 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                               
01163 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                        
01164 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)     
01165 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                        
01166 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                   
01167 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                               
01168 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                        
01169 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
01170 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                        
01171 #define _CMU_IEN_LFXORDY_SHIFT                      3                                   
01172 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                               
01173 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                        
01174 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)     
01175 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                        
01176 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                   
01177 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                              
01178 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01179 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
01180 #define CMU_IEN_CALRDY                              (0x1UL << 5)                        
01181 #define _CMU_IEN_CALRDY_SHIFT                       5                                   
01182 #define _CMU_IEN_CALRDY_MASK                        0x20UL                              
01183 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                        
01184 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)      
01185 #define CMU_IEN_CALOF                               (0x1UL << 6)                        
01186 #define _CMU_IEN_CALOF_SHIFT                        6                                   
01187 #define _CMU_IEN_CALOF_MASK                         0x40UL                              
01188 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                        
01189 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)       
01190 #define CMU_IEN_USHFRCORDY                          (0x1UL << 8)                        
01191 #define _CMU_IEN_USHFRCORDY_SHIFT                   8                                   
01192 #define _CMU_IEN_USHFRCORDY_MASK                    0x100UL                             
01193 #define _CMU_IEN_USHFRCORDY_DEFAULT                 0x00000000UL                        
01194 #define CMU_IEN_USHFRCORDY_DEFAULT                  (_CMU_IEN_USHFRCORDY_DEFAULT << 8)  
01196 /* Bit fields for CMU HFCORECLKEN0 */
01197 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                         
01198 #define _CMU_HFCORECLKEN0_MASK                      0x00000007UL                         
01199 #define CMU_HFCORECLKEN0_AES                        (0x1UL << 0)                         
01200 #define _CMU_HFCORECLKEN0_AES_SHIFT                 0                                    
01201 #define _CMU_HFCORECLKEN0_AES_MASK                  0x1UL                                
01202 #define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                         
01203 #define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) 
01204 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 1)                         
01205 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 1                                    
01206 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x2UL                                
01207 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                         
01208 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) 
01209 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 2)                         
01210 #define _CMU_HFCORECLKEN0_LE_SHIFT                  2                                    
01211 #define _CMU_HFCORECLKEN0_LE_MASK                   0x4UL                                
01212 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                         
01213 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)  
01215 /* Bit fields for CMU HFPERCLKEN0 */
01216 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
01217 #define _CMU_HFPERCLKEN0_MASK                       0x00000FFFUL                           
01218 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 0)                           
01219 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               0                                      
01220 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x1UL                                  
01221 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
01222 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) 
01223 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 1)                           
01224 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               1                                      
01225 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x2UL                                  
01226 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
01227 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) 
01228 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 2)                           
01229 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               2                                      
01230 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x4UL                                  
01231 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
01232 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) 
01233 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 3)                           
01234 #define _CMU_HFPERCLKEN0_USART0_SHIFT               3                                      
01235 #define _CMU_HFPERCLKEN0_USART0_MASK                0x8UL                                  
01236 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
01237 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) 
01238 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 4)                           
01239 #define _CMU_HFPERCLKEN0_USART1_SHIFT               4                                      
01240 #define _CMU_HFPERCLKEN0_USART1_MASK                0x10UL                                 
01241 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
01242 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) 
01243 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 5)                           
01244 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                5                                      
01245 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x20UL                                 
01246 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
01247 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5)  
01248 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 6)                           
01249 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  6                                      
01250 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x40UL                                 
01251 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
01252 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6)    
01253 #define CMU_HFPERCLKEN0_IDAC0                       (0x1UL << 7)                           
01254 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT                7                                      
01255 #define _CMU_HFPERCLKEN0_IDAC0_MASK                 0x80UL                                 
01256 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT              0x00000000UL                           
01257 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT               (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 7)  
01258 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 8)                           
01259 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 8                                      
01260 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x100UL                                
01261 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
01262 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8)   
01263 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 9)                           
01264 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 9                                      
01265 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x200UL                                
01266 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
01267 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9)   
01268 #define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 10)                          
01269 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                 10                                     
01270 #define _CMU_HFPERCLKEN0_ADC0_MASK                  0x400UL                                
01271 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           
01272 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10)  
01273 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
01274 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
01275 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
01276 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
01277 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
01279 /* Bit fields for CMU SYNCBUSY */
01280 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
01281 #define _CMU_SYNCBUSY_MASK                          0x00000155UL                           
01282 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
01283 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
01284 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
01285 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
01286 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
01287 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
01288 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
01289 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
01290 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
01291 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
01292 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
01293 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
01294 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
01295 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
01296 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
01297 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
01298 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
01299 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
01300 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
01301 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
01302 #define CMU_SYNCBUSY_LFCCLKEN0                      (0x1UL << 8)                           
01303 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT               8                                      
01304 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK                0x100UL                                
01305 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT             0x00000000UL                           
01306 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) 
01308 /* Bit fields for CMU FREEZE */
01309 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
01310 #define _CMU_FREEZE_MASK                            0x00000001UL                         
01311 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
01312 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
01313 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
01314 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
01315 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
01316 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
01317 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
01318 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
01319 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
01321 /* Bit fields for CMU LFACLKEN0 */
01322 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                      
01323 #define _CMU_LFACLKEN0_MASK                         0x00000001UL                      
01324 #define CMU_LFACLKEN0_RTC                           (0x1UL << 0)                      
01325 #define _CMU_LFACLKEN0_RTC_SHIFT                    0                                 
01326 #define _CMU_LFACLKEN0_RTC_MASK                     0x1UL                             
01327 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                      
01328 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 0) 
01330 /* Bit fields for CMU LFBCLKEN0 */
01331 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
01332 #define _CMU_LFBCLKEN0_MASK                         0x00000001UL                          
01333 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
01334 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
01335 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
01336 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
01337 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
01339 /* Bit fields for CMU LFCCLKEN0 */
01340 #define _CMU_LFCCLKEN0_RESETVALUE                   0x00000000UL                        
01341 #define _CMU_LFCCLKEN0_MASK                         0x00000001UL                        
01342 #define CMU_LFCCLKEN0_USBLE                         (0x1UL << 0)                        
01343 #define _CMU_LFCCLKEN0_USBLE_SHIFT                  0                                   
01344 #define _CMU_LFCCLKEN0_USBLE_MASK                   0x1UL                               
01345 #define _CMU_LFCCLKEN0_USBLE_DEFAULT                0x00000000UL                        
01346 #define CMU_LFCCLKEN0_USBLE_DEFAULT                 (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) 
01348 /* Bit fields for CMU LFAPRESC0 */
01349 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                       
01350 #define _CMU_LFAPRESC0_MASK                         0x0000000FUL                       
01351 #define _CMU_LFAPRESC0_RTC_SHIFT                    0                                  
01352 #define _CMU_LFAPRESC0_RTC_MASK                     0xFUL                              
01353 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                       
01354 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                       
01355 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                       
01356 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                       
01357 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                       
01358 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                       
01359 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                       
01360 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                       
01361 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                       
01362 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                       
01363 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                       
01364 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                       
01365 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                       
01366 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                       
01367 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                       
01368 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                       
01369 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 0)     
01370 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 0)     
01371 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 0)     
01372 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 0)     
01373 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 0)    
01374 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 0)    
01375 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 0)    
01376 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 0)   
01377 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 0)   
01378 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 0)   
01379 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 0)  
01380 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 0)  
01381 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 0)  
01382 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 0)  
01383 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 0) 
01384 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 0) 
01386 /* Bit fields for CMU LFBPRESC0 */
01387 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
01388 #define _CMU_LFBPRESC0_MASK                         0x00000003UL                       
01389 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
01390 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
01391 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
01392 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
01393 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
01394 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
01395 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
01396 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
01397 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
01398 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
01400 /* Bit fields for CMU PCNTCTRL */
01401 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
01402 #define _CMU_PCNTCTRL_MASK                          0x00000003UL                             
01403 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
01404 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
01405 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
01406 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
01407 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
01408 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
01409 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
01410 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
01411 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
01412 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
01413 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
01414 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
01415 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
01416 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
01418 /* Bit fields for CMU ROUTE */
01419 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
01420 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
01421 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
01422 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
01423 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
01424 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
01425 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
01426 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
01427 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
01428 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
01429 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
01430 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
01431 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
01432 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
01433 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
01434 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
01435 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
01436 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
01437 #define _CMU_ROUTE_LOCATION_LOC3                    0x00000003UL                         
01438 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
01439 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
01440 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
01441 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
01442 #define CMU_ROUTE_LOCATION_LOC3                     (_CMU_ROUTE_LOCATION_LOC3 << 2)      
01444 /* Bit fields for CMU LOCK */
01445 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
01446 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
01447 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
01448 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
01449 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
01450 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
01451 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
01452 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
01453 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
01454 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
01455 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
01456 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
01457 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
01458 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
01460 /* Bit fields for CMU USBCRCTRL */
01461 #define _CMU_USBCRCTRL_RESETVALUE                   0x00000000UL                         
01462 #define _CMU_USBCRCTRL_MASK                         0x00000003UL                         
01463 #define CMU_USBCRCTRL_EN                            (0x1UL << 0)                         
01464 #define _CMU_USBCRCTRL_EN_SHIFT                     0                                    
01465 #define _CMU_USBCRCTRL_EN_MASK                      0x1UL                                
01466 #define _CMU_USBCRCTRL_EN_DEFAULT                   0x00000000UL                         
01467 #define CMU_USBCRCTRL_EN_DEFAULT                    (_CMU_USBCRCTRL_EN_DEFAULT << 0)     
01468 #define CMU_USBCRCTRL_LSMODE                        (0x1UL << 1)                         
01469 #define _CMU_USBCRCTRL_LSMODE_SHIFT                 1                                    
01470 #define _CMU_USBCRCTRL_LSMODE_MASK                  0x2UL                                
01471 #define _CMU_USBCRCTRL_LSMODE_DEFAULT               0x00000000UL                         
01472 #define CMU_USBCRCTRL_LSMODE_DEFAULT                (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) 
01474 /* Bit fields for CMU USHFRCOCTRL */
01475 #define _CMU_USHFRCOCTRL_RESETVALUE                 0x000FF040UL                             
01476 #define _CMU_USHFRCOCTRL_MASK                       0x000FF37FUL                             
01477 #define _CMU_USHFRCOCTRL_TUNING_SHIFT               0                                        
01478 #define _CMU_USHFRCOCTRL_TUNING_MASK                0x7FUL                                   
01479 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT             0x00000040UL                             
01480 #define CMU_USHFRCOCTRL_TUNING_DEFAULT              (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0)   
01481 #define CMU_USHFRCOCTRL_DITHEN                      (0x1UL << 8)                             
01482 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT               8                                        
01483 #define _CMU_USHFRCOCTRL_DITHEN_MASK                0x100UL                                  
01484 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT             0x00000000UL                             
01485 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT              (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8)   
01486 #define CMU_USHFRCOCTRL_SUSPEND                     (0x1UL << 9)                             
01487 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT              9                                        
01488 #define _CMU_USHFRCOCTRL_SUSPEND_MASK               0x200UL                                  
01489 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT            0x00000000UL                             
01490 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT             (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9)  
01491 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT              12                                       
01492 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK               0xFF000UL                                
01493 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT            0x000000FFUL                             
01494 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT             (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) 
01496 /* Bit fields for CMU USHFRCOTUNE */
01497 #define _CMU_USHFRCOTUNE_RESETVALUE                 0x00000020UL                               
01498 #define _CMU_USHFRCOTUNE_MASK                       0x0000003FUL                               
01499 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT           0                                          
01500 #define _CMU_USHFRCOTUNE_FINETUNING_MASK            0x3FUL                                     
01501 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT         0x00000020UL                               
01502 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT          (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) 
01504 /* Bit fields for CMU USHFRCOCONF */
01505 #define _CMU_USHFRCOCONF_RESETVALUE                 0x00000001UL                                   
01506 #define _CMU_USHFRCOCONF_MASK                       0x00000017UL                                   
01507 #define _CMU_USHFRCOCONF_BAND_SHIFT                 0                                              
01508 #define _CMU_USHFRCOCONF_BAND_MASK                  0x7UL                                          
01509 #define _CMU_USHFRCOCONF_BAND_DEFAULT               0x00000001UL                                   
01510 #define _CMU_USHFRCOCONF_BAND_48MHZ                 0x00000001UL                                   
01511 #define _CMU_USHFRCOCONF_BAND_24MHZ                 0x00000003UL                                   
01512 #define CMU_USHFRCOCONF_BAND_DEFAULT                (_CMU_USHFRCOCONF_BAND_DEFAULT << 0)           
01513 #define CMU_USHFRCOCONF_BAND_48MHZ                  (_CMU_USHFRCOCONF_BAND_48MHZ << 0)             
01514 #define CMU_USHFRCOCONF_BAND_24MHZ                  (_CMU_USHFRCOCONF_BAND_24MHZ << 0)             
01515 #define CMU_USHFRCOCONF_USHFRCODIV2DIS              (0x1UL << 4)                                   
01516 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT       4                                              
01517 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK        0x10UL                                         
01518 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT     0x00000000UL                                   
01519 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT      (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) 
01523 /**************************************************************************/
01528 /* Bit fields for PRS SWPULSE */
01529 #define _PRS_SWPULSE_RESETVALUE              0x00000000UL                         
01530 #define _PRS_SWPULSE_MASK                    0x0000003FUL                         
01531 #define PRS_SWPULSE_CH0PULSE                 (0x1UL << 0)                         
01532 #define _PRS_SWPULSE_CH0PULSE_SHIFT          0                                    
01533 #define _PRS_SWPULSE_CH0PULSE_MASK           0x1UL                                
01534 #define _PRS_SWPULSE_CH0PULSE_DEFAULT        0x00000000UL                         
01535 #define PRS_SWPULSE_CH0PULSE_DEFAULT         (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) 
01536 #define PRS_SWPULSE_CH1PULSE                 (0x1UL << 1)                         
01537 #define _PRS_SWPULSE_CH1PULSE_SHIFT          1                                    
01538 #define _PRS_SWPULSE_CH1PULSE_MASK           0x2UL                                
01539 #define _PRS_SWPULSE_CH1PULSE_DEFAULT        0x00000000UL                         
01540 #define PRS_SWPULSE_CH1PULSE_DEFAULT         (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) 
01541 #define PRS_SWPULSE_CH2PULSE                 (0x1UL << 2)                         
01542 #define _PRS_SWPULSE_CH2PULSE_SHIFT          2                                    
01543 #define _PRS_SWPULSE_CH2PULSE_MASK           0x4UL                                
01544 #define _PRS_SWPULSE_CH2PULSE_DEFAULT        0x00000000UL                         
01545 #define PRS_SWPULSE_CH2PULSE_DEFAULT         (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) 
01546 #define PRS_SWPULSE_CH3PULSE                 (0x1UL << 3)                         
01547 #define _PRS_SWPULSE_CH3PULSE_SHIFT          3                                    
01548 #define _PRS_SWPULSE_CH3PULSE_MASK           0x8UL                                
01549 #define _PRS_SWPULSE_CH3PULSE_DEFAULT        0x00000000UL                         
01550 #define PRS_SWPULSE_CH3PULSE_DEFAULT         (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) 
01551 #define PRS_SWPULSE_CH4PULSE                 (0x1UL << 4)                         
01552 #define _PRS_SWPULSE_CH4PULSE_SHIFT          4                                    
01553 #define _PRS_SWPULSE_CH4PULSE_MASK           0x10UL                               
01554 #define _PRS_SWPULSE_CH4PULSE_DEFAULT        0x00000000UL                         
01555 #define PRS_SWPULSE_CH4PULSE_DEFAULT         (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) 
01556 #define PRS_SWPULSE_CH5PULSE                 (0x1UL << 5)                         
01557 #define _PRS_SWPULSE_CH5PULSE_SHIFT          5                                    
01558 #define _PRS_SWPULSE_CH5PULSE_MASK           0x20UL                               
01559 #define _PRS_SWPULSE_CH5PULSE_DEFAULT        0x00000000UL                         
01560 #define PRS_SWPULSE_CH5PULSE_DEFAULT         (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) 
01562 /* Bit fields for PRS SWLEVEL */
01563 #define _PRS_SWLEVEL_RESETVALUE              0x00000000UL                         
01564 #define _PRS_SWLEVEL_MASK                    0x0000003FUL                         
01565 #define PRS_SWLEVEL_CH0LEVEL                 (0x1UL << 0)                         
01566 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT          0                                    
01567 #define _PRS_SWLEVEL_CH0LEVEL_MASK           0x1UL                                
01568 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT        0x00000000UL                         
01569 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT         (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) 
01570 #define PRS_SWLEVEL_CH1LEVEL                 (0x1UL << 1)                         
01571 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT          1                                    
01572 #define _PRS_SWLEVEL_CH1LEVEL_MASK           0x2UL                                
01573 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT        0x00000000UL                         
01574 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT         (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) 
01575 #define PRS_SWLEVEL_CH2LEVEL                 (0x1UL << 2)                         
01576 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT          2                                    
01577 #define _PRS_SWLEVEL_CH2LEVEL_MASK           0x4UL                                
01578 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT        0x00000000UL                         
01579 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT         (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) 
01580 #define PRS_SWLEVEL_CH3LEVEL                 (0x1UL << 3)                         
01581 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT          3                                    
01582 #define _PRS_SWLEVEL_CH3LEVEL_MASK           0x8UL                                
01583 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT        0x00000000UL                         
01584 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT         (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) 
01585 #define PRS_SWLEVEL_CH4LEVEL                 (0x1UL << 4)                         
01586 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT          4                                    
01587 #define _PRS_SWLEVEL_CH4LEVEL_MASK           0x10UL                               
01588 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT        0x00000000UL                         
01589 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT         (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) 
01590 #define PRS_SWLEVEL_CH5LEVEL                 (0x1UL << 5)                         
01591 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT          5                                    
01592 #define _PRS_SWLEVEL_CH5LEVEL_MASK           0x20UL                               
01593 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT        0x00000000UL                         
01594 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT         (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) 
01596 /* Bit fields for PRS ROUTE */
01597 #define _PRS_ROUTE_RESETVALUE                0x00000000UL                       
01598 #define _PRS_ROUTE_MASK                      0x0000070FUL                       
01599 #define PRS_ROUTE_CH0PEN                     (0x1UL << 0)                       
01600 #define _PRS_ROUTE_CH0PEN_SHIFT              0                                  
01601 #define _PRS_ROUTE_CH0PEN_MASK               0x1UL                              
01602 #define _PRS_ROUTE_CH0PEN_DEFAULT            0x00000000UL                       
01603 #define PRS_ROUTE_CH0PEN_DEFAULT             (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   
01604 #define PRS_ROUTE_CH1PEN                     (0x1UL << 1)                       
01605 #define _PRS_ROUTE_CH1PEN_SHIFT              1                                  
01606 #define _PRS_ROUTE_CH1PEN_MASK               0x2UL                              
01607 #define _PRS_ROUTE_CH1PEN_DEFAULT            0x00000000UL                       
01608 #define PRS_ROUTE_CH1PEN_DEFAULT             (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   
01609 #define PRS_ROUTE_CH2PEN                     (0x1UL << 2)                       
01610 #define _PRS_ROUTE_CH2PEN_SHIFT              2                                  
01611 #define _PRS_ROUTE_CH2PEN_MASK               0x4UL                              
01612 #define _PRS_ROUTE_CH2PEN_DEFAULT            0x00000000UL                       
01613 #define PRS_ROUTE_CH2PEN_DEFAULT             (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   
01614 #define PRS_ROUTE_CH3PEN                     (0x1UL << 3)                       
01615 #define _PRS_ROUTE_CH3PEN_SHIFT              3                                  
01616 #define _PRS_ROUTE_CH3PEN_MASK               0x8UL                              
01617 #define _PRS_ROUTE_CH3PEN_DEFAULT            0x00000000UL                       
01618 #define PRS_ROUTE_CH3PEN_DEFAULT             (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   
01619 #define _PRS_ROUTE_LOCATION_SHIFT            8                                  
01620 #define _PRS_ROUTE_LOCATION_MASK             0x700UL                            
01621 #define _PRS_ROUTE_LOCATION_LOC0             0x00000000UL                       
01622 #define _PRS_ROUTE_LOCATION_DEFAULT          0x00000000UL                       
01623 #define _PRS_ROUTE_LOCATION_LOC1             0x00000001UL                       
01624 #define _PRS_ROUTE_LOCATION_LOC2             0x00000002UL                       
01625 #define _PRS_ROUTE_LOCATION_LOC3             0x00000003UL                       
01626 #define PRS_ROUTE_LOCATION_LOC0              (_PRS_ROUTE_LOCATION_LOC0 << 8)    
01627 #define PRS_ROUTE_LOCATION_DEFAULT           (_PRS_ROUTE_LOCATION_DEFAULT << 8) 
01628 #define PRS_ROUTE_LOCATION_LOC1              (_PRS_ROUTE_LOCATION_LOC1 << 8)    
01629 #define PRS_ROUTE_LOCATION_LOC2              (_PRS_ROUTE_LOCATION_LOC2 << 8)    
01630 #define PRS_ROUTE_LOCATION_LOC3              (_PRS_ROUTE_LOCATION_LOC3 << 8)    
01632 /* Bit fields for PRS CH_CTRL */
01633 #define _PRS_CH_CTRL_RESETVALUE              0x00000000UL                             
01634 #define _PRS_CH_CTRL_MASK                    0x133F0007UL                             
01635 #define _PRS_CH_CTRL_SIGSEL_SHIFT            0                                        
01636 #define _PRS_CH_CTRL_SIGSEL_MASK             0x7UL                                    
01637 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT          0x00000000UL                             
01638 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT         0x00000000UL                             
01639 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE       0x00000000UL                             
01640 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX       0x00000000UL                             
01641 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX       0x00000000UL                             
01642 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF         0x00000000UL                             
01643 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF         0x00000000UL                             
01644 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF         0x00000000UL                             
01645 #define _PRS_CH_CTRL_SIGSEL_RTCOF            0x00000000UL                             
01646 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0         0x00000000UL                             
01647 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8         0x00000000UL                             
01648 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC         0x00000000UL                             
01649 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN         0x00000001UL                             
01650 #define _PRS_CH_CTRL_SIGSEL_USART0TXC        0x00000001UL                             
01651 #define _PRS_CH_CTRL_SIGSEL_USART1TXC        0x00000001UL                             
01652 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF         0x00000001UL                             
01653 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF         0x00000001UL                             
01654 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF         0x00000001UL                             
01655 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0         0x00000001UL                             
01656 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1         0x00000001UL                             
01657 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9         0x00000001UL                             
01658 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV    0x00000002UL                             
01659 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV    0x00000002UL                             
01660 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0        0x00000002UL                             
01661 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0        0x00000002UL                             
01662 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0        0x00000002UL                             
01663 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1         0x00000002UL                             
01664 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2         0x00000002UL                             
01665 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10        0x00000002UL                             
01666 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1        0x00000003UL                             
01667 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1        0x00000003UL                             
01668 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1        0x00000003UL                             
01669 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3         0x00000003UL                             
01670 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11        0x00000003UL                             
01671 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2        0x00000004UL                             
01672 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2        0x00000004UL                             
01673 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2        0x00000004UL                             
01674 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4         0x00000004UL                             
01675 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12        0x00000004UL                             
01676 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5         0x00000005UL                             
01677 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13        0x00000005UL                             
01678 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6         0x00000006UL                             
01679 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14        0x00000006UL                             
01680 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7         0x00000007UL                             
01681 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15        0x00000007UL                             
01682 #define PRS_CH_CTRL_SIGSEL_VCMPOUT           (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)       
01683 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT          (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)      
01684 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE        (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0)    
01685 #define PRS_CH_CTRL_SIGSEL_USART0IRTX        (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)    
01686 #define PRS_CH_CTRL_SIGSEL_USART1IRTX        (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0)    
01687 #define PRS_CH_CTRL_SIGSEL_TIMER0UF          (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)      
01688 #define PRS_CH_CTRL_SIGSEL_TIMER1UF          (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)      
01689 #define PRS_CH_CTRL_SIGSEL_TIMER2UF          (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)      
01690 #define PRS_CH_CTRL_SIGSEL_RTCOF             (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)         
01691 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0          (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)      
01692 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8          (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)      
01693 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC          (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)      
01694 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN          (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0)      
01695 #define PRS_CH_CTRL_SIGSEL_USART0TXC         (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)     
01696 #define PRS_CH_CTRL_SIGSEL_USART1TXC         (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)     
01697 #define PRS_CH_CTRL_SIGSEL_TIMER0OF          (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)      
01698 #define PRS_CH_CTRL_SIGSEL_TIMER1OF          (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)      
01699 #define PRS_CH_CTRL_SIGSEL_TIMER2OF          (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)      
01700 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0          (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)      
01701 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1          (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)      
01702 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9          (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)      
01703 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) 
01704 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 
01705 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0         (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)     
01706 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0         (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)     
01707 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0         (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)     
01708 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1          (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)      
01709 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2          (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)      
01710 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10         (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)     
01711 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1         (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)     
01712 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1         (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)     
01713 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1         (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)     
01714 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3          (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)      
01715 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11         (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)     
01716 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2         (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)     
01717 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2         (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)     
01718 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2         (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)     
01719 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4          (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)      
01720 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12         (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)     
01721 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5          (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)      
01722 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13         (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)     
01723 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6          (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)      
01724 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14         (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)     
01725 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7          (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)      
01726 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15         (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)     
01727 #define _PRS_CH_CTRL_SOURCESEL_SHIFT         16                                       
01728 #define _PRS_CH_CTRL_SOURCESEL_MASK          0x3F0000UL                               
01729 #define _PRS_CH_CTRL_SOURCESEL_NONE          0x00000000UL                             
01730 #define _PRS_CH_CTRL_SOURCESEL_VCMP          0x00000001UL                             
01731 #define _PRS_CH_CTRL_SOURCESEL_ACMP0         0x00000002UL                             
01732 #define _PRS_CH_CTRL_SOURCESEL_ADC0          0x00000008UL                             
01733 #define _PRS_CH_CTRL_SOURCESEL_USART0        0x00000010UL                             
01734 #define _PRS_CH_CTRL_SOURCESEL_USART1        0x00000011UL                             
01735 #define _PRS_CH_CTRL_SOURCESEL_TIMER0        0x0000001CUL                             
01736 #define _PRS_CH_CTRL_SOURCESEL_TIMER1        0x0000001DUL                             
01737 #define _PRS_CH_CTRL_SOURCESEL_TIMER2        0x0000001EUL                             
01738 #define _PRS_CH_CTRL_SOURCESEL_RTC           0x00000028UL                             
01739 #define _PRS_CH_CTRL_SOURCESEL_GPIOL         0x00000030UL                             
01740 #define _PRS_CH_CTRL_SOURCESEL_GPIOH         0x00000031UL                             
01741 #define _PRS_CH_CTRL_SOURCESEL_PCNT0         0x00000036UL                             
01742 #define PRS_CH_CTRL_SOURCESEL_NONE           (_PRS_CH_CTRL_SOURCESEL_NONE << 16)      
01743 #define PRS_CH_CTRL_SOURCESEL_VCMP           (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)      
01744 #define PRS_CH_CTRL_SOURCESEL_ACMP0          (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)     
01745 #define PRS_CH_CTRL_SOURCESEL_ADC0           (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16)      
01746 #define PRS_CH_CTRL_SOURCESEL_USART0         (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)    
01747 #define PRS_CH_CTRL_SOURCESEL_USART1         (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)    
01748 #define PRS_CH_CTRL_SOURCESEL_TIMER0         (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)    
01749 #define PRS_CH_CTRL_SOURCESEL_TIMER1         (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)    
01750 #define PRS_CH_CTRL_SOURCESEL_TIMER2         (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)    
01751 #define PRS_CH_CTRL_SOURCESEL_RTC            (_PRS_CH_CTRL_SOURCESEL_RTC << 16)       
01752 #define PRS_CH_CTRL_SOURCESEL_GPIOL          (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)     
01753 #define PRS_CH_CTRL_SOURCESEL_GPIOH          (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)     
01754 #define PRS_CH_CTRL_SOURCESEL_PCNT0          (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16)     
01755 #define _PRS_CH_CTRL_EDSEL_SHIFT             24                                       
01756 #define _PRS_CH_CTRL_EDSEL_MASK              0x3000000UL                              
01757 #define _PRS_CH_CTRL_EDSEL_DEFAULT           0x00000000UL                             
01758 #define _PRS_CH_CTRL_EDSEL_OFF               0x00000000UL                             
01759 #define _PRS_CH_CTRL_EDSEL_POSEDGE           0x00000001UL                             
01760 #define _PRS_CH_CTRL_EDSEL_NEGEDGE           0x00000002UL                             
01761 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES         0x00000003UL                             
01762 #define PRS_CH_CTRL_EDSEL_DEFAULT            (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)       
01763 #define PRS_CH_CTRL_EDSEL_OFF                (_PRS_CH_CTRL_EDSEL_OFF << 24)           
01764 #define PRS_CH_CTRL_EDSEL_POSEDGE            (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)       
01765 #define PRS_CH_CTRL_EDSEL_NEGEDGE            (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)       
01766 #define PRS_CH_CTRL_EDSEL_BOTHEDGES          (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)     
01767 #define PRS_CH_CTRL_ASYNC                    (0x1UL << 28)                            
01768 #define _PRS_CH_CTRL_ASYNC_SHIFT             28                                       
01769 #define _PRS_CH_CTRL_ASYNC_MASK              0x10000000UL                             
01770 #define _PRS_CH_CTRL_ASYNC_DEFAULT           0x00000000UL                             
01771 #define PRS_CH_CTRL_ASYNC_DEFAULT            (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)       
01773 /* Bit fields for PRS TRACECTRL */
01774 #define _PRS_TRACECTRL_RESETVALUE            0x00000000UL                           
01775 #define _PRS_TRACECTRL_MASK                  0x00000F0FUL                           
01776 #define PRS_TRACECTRL_TSTARTEN               (0x1UL << 0)                           
01777 #define _PRS_TRACECTRL_TSTARTEN_SHIFT        0                                      
01778 #define _PRS_TRACECTRL_TSTARTEN_MASK         0x1UL                                  
01779 #define _PRS_TRACECTRL_TSTARTEN_DEFAULT      0x00000000UL                           
01780 #define PRS_TRACECTRL_TSTARTEN_DEFAULT       (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) 
01781 #define _PRS_TRACECTRL_TSTART_SHIFT          1                                      
01782 #define _PRS_TRACECTRL_TSTART_MASK           0xEUL                                  
01783 #define _PRS_TRACECTRL_TSTART_DEFAULT        0x00000000UL                           
01784 #define _PRS_TRACECTRL_TSTART_PRSCH0         0x00000000UL                           
01785 #define _PRS_TRACECTRL_TSTART_PRSCH1         0x00000001UL                           
01786 #define _PRS_TRACECTRL_TSTART_PRSCH2         0x00000002UL                           
01787 #define _PRS_TRACECTRL_TSTART_PRSCH3         0x00000003UL                           
01788 #define _PRS_TRACECTRL_TSTART_PRSCH4         0x00000004UL                           
01789 #define _PRS_TRACECTRL_TSTART_PRSCH5         0x00000005UL                           
01790 #define PRS_TRACECTRL_TSTART_DEFAULT         (_PRS_TRACECTRL_TSTART_DEFAULT << 1)   
01791 #define PRS_TRACECTRL_TSTART_PRSCH0          (_PRS_TRACECTRL_TSTART_PRSCH0 << 1)    
01792 #define PRS_TRACECTRL_TSTART_PRSCH1          (_PRS_TRACECTRL_TSTART_PRSCH1 << 1)    
01793 #define PRS_TRACECTRL_TSTART_PRSCH2          (_PRS_TRACECTRL_TSTART_PRSCH2 << 1)    
01794 #define PRS_TRACECTRL_TSTART_PRSCH3          (_PRS_TRACECTRL_TSTART_PRSCH3 << 1)    
01795 #define PRS_TRACECTRL_TSTART_PRSCH4          (_PRS_TRACECTRL_TSTART_PRSCH4 << 1)    
01796 #define PRS_TRACECTRL_TSTART_PRSCH5          (_PRS_TRACECTRL_TSTART_PRSCH5 << 1)    
01797 #define PRS_TRACECTRL_TSTOPEN                (0x1UL << 8)                           
01798 #define _PRS_TRACECTRL_TSTOPEN_SHIFT         8                                      
01799 #define _PRS_TRACECTRL_TSTOPEN_MASK          0x100UL                                
01800 #define _PRS_TRACECTRL_TSTOPEN_DEFAULT       0x00000000UL                           
01801 #define PRS_TRACECTRL_TSTOPEN_DEFAULT        (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8)  
01802 #define _PRS_TRACECTRL_TSTOP_SHIFT           9                                      
01803 #define _PRS_TRACECTRL_TSTOP_MASK            0xE00UL                                
01804 #define _PRS_TRACECTRL_TSTOP_DEFAULT         0x00000000UL                           
01805 #define _PRS_TRACECTRL_TSTOP_PRSCH0          0x00000000UL                           
01806 #define _PRS_TRACECTRL_TSTOP_PRSCH1          0x00000001UL                           
01807 #define _PRS_TRACECTRL_TSTOP_PRSCH2          0x00000002UL                           
01808 #define _PRS_TRACECTRL_TSTOP_PRSCH3          0x00000003UL                           
01809 #define _PRS_TRACECTRL_TSTOP_PRSCH4          0x00000004UL                           
01810 #define _PRS_TRACECTRL_TSTOP_PRSCH5          0x00000005UL                           
01811 #define PRS_TRACECTRL_TSTOP_DEFAULT          (_PRS_TRACECTRL_TSTOP_DEFAULT << 9)    
01812 #define PRS_TRACECTRL_TSTOP_PRSCH0           (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9)     
01813 #define PRS_TRACECTRL_TSTOP_PRSCH1           (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9)     
01814 #define PRS_TRACECTRL_TSTOP_PRSCH2           (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9)     
01815 #define PRS_TRACECTRL_TSTOP_PRSCH3           (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9)     
01816 #define PRS_TRACECTRL_TSTOP_PRSCH4           (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9)     
01817 #define PRS_TRACECTRL_TSTOP_PRSCH5           (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9)     
01823 /**************************************************************************/
01827 #define MSC_UNLOCK_CODE      0x1B71 
01828 #define EMU_UNLOCK_CODE      0xADE8 
01829 #define CMU_UNLOCK_CODE      0x580E 
01830 #define TIMER_UNLOCK_CODE    0xCE80 
01831 #define GPIO_UNLOCK_CODE     0xA534 
01837 /**************************************************************************/
01842 #include "efm32hg_af_ports.h"
01843 #include "efm32hg_af_pins.h"
01844 
01847 /**************************************************************************/
01860 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
01861   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
01862 
01867 #ifdef __cplusplus
01868 }
01869 #endif
01870 #endif /* __SILICON_LABS_EFM32HG210F64_H__ */