release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg_emu.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __IO uint32_t CTRL;         
00041   uint32_t      RESERVED0[1]; 
00042   __IO uint32_t LOCK;         
00044   uint32_t      RESERVED1[6]; 
00045   __IO uint32_t AUXCTRL;      
00046 } EMU_TypeDef;                
00048 /**************************************************************************/
00053 /* Bit fields for EMU CTRL */
00054 #define _EMU_CTRL_RESETVALUE           0x00000000UL                      
00055 #define _EMU_CTRL_MASK                 0x0000000FUL                      
00056 #define EMU_CTRL_EMVREG                (0x1UL << 0)                      
00057 #define _EMU_CTRL_EMVREG_SHIFT         0                                 
00058 #define _EMU_CTRL_EMVREG_MASK          0x1UL                             
00059 #define _EMU_CTRL_EMVREG_DEFAULT       0x00000000UL                      
00060 #define _EMU_CTRL_EMVREG_REDUCED       0x00000000UL                      
00061 #define _EMU_CTRL_EMVREG_FULL          0x00000001UL                      
00062 #define EMU_CTRL_EMVREG_DEFAULT        (_EMU_CTRL_EMVREG_DEFAULT << 0)   
00063 #define EMU_CTRL_EMVREG_REDUCED        (_EMU_CTRL_EMVREG_REDUCED << 0)   
00064 #define EMU_CTRL_EMVREG_FULL           (_EMU_CTRL_EMVREG_FULL << 0)      
00065 #define EMU_CTRL_EM2BLOCK              (0x1UL << 1)                      
00066 #define _EMU_CTRL_EM2BLOCK_SHIFT       1                                 
00067 #define _EMU_CTRL_EM2BLOCK_MASK        0x2UL                             
00068 #define _EMU_CTRL_EM2BLOCK_DEFAULT     0x00000000UL                      
00069 #define EMU_CTRL_EM2BLOCK_DEFAULT      (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) 
00070 #define _EMU_CTRL_EM4CTRL_SHIFT        2                                 
00071 #define _EMU_CTRL_EM4CTRL_MASK         0xCUL                             
00072 #define _EMU_CTRL_EM4CTRL_DEFAULT      0x00000000UL                      
00073 #define EMU_CTRL_EM4CTRL_DEFAULT       (_EMU_CTRL_EM4CTRL_DEFAULT << 2)  
00075 /* Bit fields for EMU LOCK */
00076 #define _EMU_LOCK_RESETVALUE           0x00000000UL                      
00077 #define _EMU_LOCK_MASK                 0x0000FFFFUL                      
00078 #define _EMU_LOCK_LOCKKEY_SHIFT        0                                 
00079 #define _EMU_LOCK_LOCKKEY_MASK         0xFFFFUL                          
00080 #define _EMU_LOCK_LOCKKEY_DEFAULT      0x00000000UL                      
00081 #define _EMU_LOCK_LOCKKEY_LOCK         0x00000000UL                      
00082 #define _EMU_LOCK_LOCKKEY_UNLOCKED     0x00000000UL                      
00083 #define _EMU_LOCK_LOCKKEY_LOCKED       0x00000001UL                      
00084 #define _EMU_LOCK_LOCKKEY_UNLOCK       0x0000ADE8UL                      
00085 #define EMU_LOCK_LOCKKEY_DEFAULT       (_EMU_LOCK_LOCKKEY_DEFAULT << 0)  
00086 #define EMU_LOCK_LOCKKEY_LOCK          (_EMU_LOCK_LOCKKEY_LOCK << 0)     
00087 #define EMU_LOCK_LOCKKEY_UNLOCKED      (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) 
00088 #define EMU_LOCK_LOCKKEY_LOCKED        (_EMU_LOCK_LOCKKEY_LOCKED << 0)   
00089 #define EMU_LOCK_LOCKKEY_UNLOCK        (_EMU_LOCK_LOCKKEY_UNLOCK << 0)   
00091 /* Bit fields for EMU AUXCTRL */
00092 #define _EMU_AUXCTRL_RESETVALUE        0x00000000UL                       
00093 #define _EMU_AUXCTRL_MASK              0x00000001UL                       
00094 #define EMU_AUXCTRL_HRCCLR             (0x1UL << 0)                       
00095 #define _EMU_AUXCTRL_HRCCLR_SHIFT      0                                  
00096 #define _EMU_AUXCTRL_HRCCLR_MASK       0x1UL                              
00097 #define _EMU_AUXCTRL_HRCCLR_DEFAULT    0x00000000UL                       
00098 #define EMU_AUXCTRL_HRCCLR_DEFAULT     (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0)