release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg_dma.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __I uint32_t   STATUS;         
00040   __O uint32_t   CONFIG;         
00041   __IO uint32_t  CTRLBASE;       
00042   __I uint32_t   ALTCTRLBASE;    
00043   __I uint32_t   CHWAITSTATUS;   
00044   __O uint32_t   CHSWREQ;        
00045   __IO uint32_t  CHUSEBURSTS;    
00046   __O uint32_t   CHUSEBURSTC;    
00047   __IO uint32_t  CHREQMASKS;     
00048   __O uint32_t   CHREQMASKC;     
00049   __IO uint32_t  CHENS;          
00050   __O uint32_t   CHENC;          
00051   __IO uint32_t  CHALTS;         
00052   __O uint32_t   CHALTC;         
00053   __IO uint32_t  CHPRIS;         
00054   __O uint32_t   CHPRIC;         
00055   uint32_t       RESERVED0[3];   
00056   __IO uint32_t  ERRORC;         
00058   uint32_t       RESERVED1[880]; 
00059   __I uint32_t   CHREQSTATUS;    
00060   uint32_t       RESERVED2[1];   
00061   __I uint32_t   CHSREQSTATUS;   
00063   uint32_t       RESERVED3[121]; 
00064   __I uint32_t   IF;             
00065   __IO uint32_t  IFS;            
00066   __IO uint32_t  IFC;            
00067   __IO uint32_t  IEN;            
00069   uint32_t       RESERVED4[60];  
00070   DMA_CH_TypeDef CH[6];          
00071 } DMA_TypeDef;                   
00073 /**************************************************************************/
00078 /* Bit fields for DMA STATUS */
00079 #define _DMA_STATUS_RESETVALUE                          0x10050000UL                          
00080 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00081 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00082 #define _DMA_STATUS_EN_SHIFT                            0                                     
00083 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00084 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00085 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00086 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00087 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00088 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00089 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00090 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00091 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00092 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00093 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00094 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00095 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00096 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00097 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00098 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00099 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00100 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00101 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00102 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00103 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00104 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00105 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00106 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00107 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00108 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00109 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00110 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00111 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00112 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00113 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00114 #define _DMA_STATUS_CHNUM_DEFAULT                       0x00000005UL                          
00115 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00117 /* Bit fields for DMA CONFIG */
00118 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00119 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00120 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00121 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00122 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00123 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00124 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00125 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00126 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00127 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00128 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00129 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00131 /* Bit fields for DMA CTRLBASE */
00132 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00133 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00134 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00135 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00136 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00137 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00139 /* Bit fields for DMA ALTCTRLBASE */
00140 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000080UL                                
00141 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00142 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00143 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00144 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000080UL                                
00145 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00147 /* Bit fields for DMA CHWAITSTATUS */
00148 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x0000003FUL                                   
00149 #define _DMA_CHWAITSTATUS_MASK                          0x0000003FUL                                   
00150 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   
00151 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              
00152 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          
00153 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   
00154 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 
00155 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   
00156 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              
00157 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          
00158 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   
00159 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 
00160 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   
00161 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              
00162 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          
00163 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   
00164 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 
00165 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   
00166 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              
00167 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          
00168 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   
00169 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 
00170 #define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                   
00171 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                              
00172 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                         
00173 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                   
00174 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) 
00175 #define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                   
00176 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                              
00177 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                         
00178 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                   
00179 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) 
00181 /* Bit fields for DMA CHSWREQ */
00182 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         
00183 #define _DMA_CHSWREQ_MASK                               0x0000003FUL                         
00184 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         
00185 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    
00186 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                
00187 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         
00188 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 
00189 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         
00190 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    
00191 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                
00192 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         
00193 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 
00194 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         
00195 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    
00196 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                
00197 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         
00198 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 
00199 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         
00200 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    
00201 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                
00202 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         
00203 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 
00204 #define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                         
00205 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                    
00206 #define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                               
00207 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                         
00208 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) 
00209 #define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                         
00210 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                    
00211 #define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                               
00212 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                         
00213 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) 
00215 /* Bit fields for DMA CHUSEBURSTS */
00216 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00217 #define _DMA_CHUSEBURSTS_MASK                           0x0000003FUL                                        
00218 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00219 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00220 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00221 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00222 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00223 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00224 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00225 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00226 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00227 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00228 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00229 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00230 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00231 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00232 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00233 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00234 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00235 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00236 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00237 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00238 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00239 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00240 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00241 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00242 #define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        
00243 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   
00244 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              
00245 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        
00246 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        
00247 #define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        
00248 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   
00249 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              
00250 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        
00251 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        
00253 /* Bit fields for DMA CHUSEBURSTC */
00254 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 
00255 #define _DMA_CHUSEBURSTC_MASK                           0x0000003FUL                                 
00256 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 
00257 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            
00258 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        
00259 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 
00260 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 
00261 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 
00262 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            
00263 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        
00264 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 
00265 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 
00266 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 
00267 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            
00268 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        
00269 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 
00270 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 
00271 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 
00272 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            
00273 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        
00274 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 
00275 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 
00276 #define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                 
00277 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                            
00278 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                       
00279 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                 
00280 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) 
00281 #define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                 
00282 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                            
00283 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                       
00284 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                 
00285 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) 
00287 /* Bit fields for DMA CHREQMASKS */
00288 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               
00289 #define _DMA_CHREQMASKS_MASK                            0x0000003FUL                               
00290 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               
00291 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          
00292 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      
00293 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               
00294 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 
00295 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               
00296 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          
00297 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      
00298 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               
00299 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 
00300 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               
00301 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          
00302 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      
00303 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               
00304 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 
00305 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               
00306 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          
00307 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      
00308 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               
00309 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 
00310 #define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                               
00311 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                          
00312 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                     
00313 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                               
00314 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) 
00315 #define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                               
00316 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                          
00317 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                     
00318 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                               
00319 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) 
00321 /* Bit fields for DMA CHREQMASKC */
00322 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               
00323 #define _DMA_CHREQMASKC_MASK                            0x0000003FUL                               
00324 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               
00325 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          
00326 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      
00327 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               
00328 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 
00329 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               
00330 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          
00331 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      
00332 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               
00333 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 
00334 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               
00335 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          
00336 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      
00337 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               
00338 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 
00339 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               
00340 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          
00341 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      
00342 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               
00343 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 
00344 #define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                               
00345 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                          
00346 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                     
00347 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                               
00348 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) 
00349 #define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                               
00350 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                          
00351 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                     
00352 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                               
00353 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) 
00355 /* Bit fields for DMA CHENS */
00356 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                     
00357 #define _DMA_CHENS_MASK                                 0x0000003FUL                     
00358 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     
00359 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                
00360 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            
00361 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     
00362 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) 
00363 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     
00364 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                
00365 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            
00366 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     
00367 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) 
00368 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     
00369 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                
00370 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            
00371 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     
00372 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) 
00373 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     
00374 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                
00375 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            
00376 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     
00377 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) 
00378 #define DMA_CHENS_CH4ENS                                (0x1UL << 4)                     
00379 #define _DMA_CHENS_CH4ENS_SHIFT                         4                                
00380 #define _DMA_CHENS_CH4ENS_MASK                          0x10UL                           
00381 #define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                     
00382 #define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4) 
00383 #define DMA_CHENS_CH5ENS                                (0x1UL << 5)                     
00384 #define _DMA_CHENS_CH5ENS_SHIFT                         5                                
00385 #define _DMA_CHENS_CH5ENS_MASK                          0x20UL                           
00386 #define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                     
00387 #define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5) 
00389 /* Bit fields for DMA CHENC */
00390 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                     
00391 #define _DMA_CHENC_MASK                                 0x0000003FUL                     
00392 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     
00393 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                
00394 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            
00395 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     
00396 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) 
00397 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     
00398 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                
00399 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            
00400 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     
00401 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) 
00402 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     
00403 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                
00404 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            
00405 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     
00406 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) 
00407 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     
00408 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                
00409 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            
00410 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     
00411 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) 
00412 #define DMA_CHENC_CH4ENC                                (0x1UL << 4)                     
00413 #define _DMA_CHENC_CH4ENC_SHIFT                         4                                
00414 #define _DMA_CHENC_CH4ENC_MASK                          0x10UL                           
00415 #define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                     
00416 #define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4) 
00417 #define DMA_CHENC_CH5ENC                                (0x1UL << 5)                     
00418 #define _DMA_CHENC_CH5ENC_SHIFT                         5                                
00419 #define _DMA_CHENC_CH5ENC_MASK                          0x20UL                           
00420 #define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                     
00421 #define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5) 
00423 /* Bit fields for DMA CHALTS */
00424 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       
00425 #define _DMA_CHALTS_MASK                                0x0000003FUL                       
00426 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       
00427 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  
00428 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              
00429 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       
00430 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 
00431 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       
00432 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  
00433 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              
00434 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       
00435 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 
00436 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       
00437 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  
00438 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              
00439 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       
00440 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 
00441 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       
00442 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  
00443 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              
00444 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       
00445 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 
00446 #define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                       
00447 #define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                  
00448 #define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                             
00449 #define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                       
00450 #define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) 
00451 #define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                       
00452 #define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                  
00453 #define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                             
00454 #define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                       
00455 #define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) 
00457 /* Bit fields for DMA CHALTC */
00458 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       
00459 #define _DMA_CHALTC_MASK                                0x0000003FUL                       
00460 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       
00461 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  
00462 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              
00463 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       
00464 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 
00465 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       
00466 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  
00467 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              
00468 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       
00469 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 
00470 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       
00471 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  
00472 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              
00473 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       
00474 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 
00475 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       
00476 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  
00477 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              
00478 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       
00479 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 
00480 #define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                       
00481 #define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                  
00482 #define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                             
00483 #define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                       
00484 #define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) 
00485 #define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                       
00486 #define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                  
00487 #define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                             
00488 #define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                       
00489 #define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) 
00491 /* Bit fields for DMA CHPRIS */
00492 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       
00493 #define _DMA_CHPRIS_MASK                                0x0000003FUL                       
00494 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       
00495 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  
00496 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              
00497 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       
00498 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 
00499 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       
00500 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  
00501 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              
00502 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       
00503 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 
00504 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       
00505 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  
00506 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              
00507 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       
00508 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 
00509 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       
00510 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  
00511 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              
00512 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       
00513 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 
00514 #define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                       
00515 #define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                  
00516 #define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                             
00517 #define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                       
00518 #define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) 
00519 #define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                       
00520 #define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                  
00521 #define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                             
00522 #define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                       
00523 #define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) 
00525 /* Bit fields for DMA CHPRIC */
00526 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       
00527 #define _DMA_CHPRIC_MASK                                0x0000003FUL                       
00528 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       
00529 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  
00530 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              
00531 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       
00532 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 
00533 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       
00534 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  
00535 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              
00536 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       
00537 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 
00538 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       
00539 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  
00540 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              
00541 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       
00542 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 
00543 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       
00544 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  
00545 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              
00546 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       
00547 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 
00548 #define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                       
00549 #define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                  
00550 #define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                             
00551 #define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                       
00552 #define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) 
00553 #define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                       
00554 #define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                  
00555 #define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                             
00556 #define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                       
00557 #define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) 
00559 /* Bit fields for DMA ERRORC */
00560 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
00561 #define _DMA_ERRORC_MASK                                0x00000001UL                      
00562 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
00563 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
00564 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
00565 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
00566 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
00568 /* Bit fields for DMA CHREQSTATUS */
00569 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 
00570 #define _DMA_CHREQSTATUS_MASK                           0x0000003FUL                                 
00571 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 
00572 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            
00573 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        
00574 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 
00575 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 
00576 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 
00577 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            
00578 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        
00579 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 
00580 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 
00581 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 
00582 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            
00583 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        
00584 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 
00585 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 
00586 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 
00587 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            
00588 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        
00589 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 
00590 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 
00591 #define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                 
00592 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                            
00593 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                       
00594 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                 
00595 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) 
00596 #define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                 
00597 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                            
00598 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                       
00599 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                 
00600 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) 
00602 /* Bit fields for DMA CHSREQSTATUS */
00603 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   
00604 #define _DMA_CHSREQSTATUS_MASK                          0x0000003FUL                                   
00605 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   
00606 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              
00607 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          
00608 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   
00609 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 
00610 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   
00611 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              
00612 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          
00613 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   
00614 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 
00615 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   
00616 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              
00617 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          
00618 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   
00619 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 
00620 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   
00621 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              
00622 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          
00623 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   
00624 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 
00625 #define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                   
00626 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                              
00627 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                         
00628 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                   
00629 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) 
00630 #define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                   
00631 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                              
00632 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                         
00633 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                   
00634 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) 
00636 /* Bit fields for DMA IF */
00637 #define _DMA_IF_RESETVALUE                              0x00000000UL                   
00638 #define _DMA_IF_MASK                                    0x8000003FUL                   
00639 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                   
00640 #define _DMA_IF_CH0DONE_SHIFT                           0                              
00641 #define _DMA_IF_CH0DONE_MASK                            0x1UL                          
00642 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   
00643 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) 
00644 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                   
00645 #define _DMA_IF_CH1DONE_SHIFT                           1                              
00646 #define _DMA_IF_CH1DONE_MASK                            0x2UL                          
00647 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   
00648 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) 
00649 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                   
00650 #define _DMA_IF_CH2DONE_SHIFT                           2                              
00651 #define _DMA_IF_CH2DONE_MASK                            0x4UL                          
00652 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   
00653 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) 
00654 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                   
00655 #define _DMA_IF_CH3DONE_SHIFT                           3                              
00656 #define _DMA_IF_CH3DONE_MASK                            0x8UL                          
00657 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   
00658 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) 
00659 #define DMA_IF_CH4DONE                                  (0x1UL << 4)                   
00660 #define _DMA_IF_CH4DONE_SHIFT                           4                              
00661 #define _DMA_IF_CH4DONE_MASK                            0x10UL                         
00662 #define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                   
00663 #define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4) 
00664 #define DMA_IF_CH5DONE                                  (0x1UL << 5)                   
00665 #define _DMA_IF_CH5DONE_SHIFT                           5                              
00666 #define _DMA_IF_CH5DONE_MASK                            0x20UL                         
00667 #define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                   
00668 #define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5) 
00669 #define DMA_IF_ERR                                      (0x1UL << 31)                  
00670 #define _DMA_IF_ERR_SHIFT                               31                             
00671 #define _DMA_IF_ERR_MASK                                0x80000000UL                   
00672 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   
00673 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    
00675 /* Bit fields for DMA IFS */
00676 #define _DMA_IFS_RESETVALUE                             0x00000000UL                    
00677 #define _DMA_IFS_MASK                                   0x8000003FUL                    
00678 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    
00679 #define _DMA_IFS_CH0DONE_SHIFT                          0                               
00680 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                           
00681 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    
00682 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) 
00683 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    
00684 #define _DMA_IFS_CH1DONE_SHIFT                          1                               
00685 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                           
00686 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    
00687 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) 
00688 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    
00689 #define _DMA_IFS_CH2DONE_SHIFT                          2                               
00690 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                           
00691 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    
00692 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) 
00693 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    
00694 #define _DMA_IFS_CH3DONE_SHIFT                          3                               
00695 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                           
00696 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    
00697 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) 
00698 #define DMA_IFS_CH4DONE                                 (0x1UL << 4)                    
00699 #define _DMA_IFS_CH4DONE_SHIFT                          4                               
00700 #define _DMA_IFS_CH4DONE_MASK                           0x10UL                          
00701 #define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                    
00702 #define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4) 
00703 #define DMA_IFS_CH5DONE                                 (0x1UL << 5)                    
00704 #define _DMA_IFS_CH5DONE_SHIFT                          5                               
00705 #define _DMA_IFS_CH5DONE_MASK                           0x20UL                          
00706 #define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                    
00707 #define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5) 
00708 #define DMA_IFS_ERR                                     (0x1UL << 31)                   
00709 #define _DMA_IFS_ERR_SHIFT                              31                              
00710 #define _DMA_IFS_ERR_MASK                               0x80000000UL                    
00711 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    
00712 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    
00714 /* Bit fields for DMA IFC */
00715 #define _DMA_IFC_RESETVALUE                             0x00000000UL                    
00716 #define _DMA_IFC_MASK                                   0x8000003FUL                    
00717 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    
00718 #define _DMA_IFC_CH0DONE_SHIFT                          0                               
00719 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                           
00720 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    
00721 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) 
00722 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    
00723 #define _DMA_IFC_CH1DONE_SHIFT                          1                               
00724 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                           
00725 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    
00726 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) 
00727 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    
00728 #define _DMA_IFC_CH2DONE_SHIFT                          2                               
00729 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                           
00730 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    
00731 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) 
00732 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    
00733 #define _DMA_IFC_CH3DONE_SHIFT                          3                               
00734 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                           
00735 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    
00736 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) 
00737 #define DMA_IFC_CH4DONE                                 (0x1UL << 4)                    
00738 #define _DMA_IFC_CH4DONE_SHIFT                          4                               
00739 #define _DMA_IFC_CH4DONE_MASK                           0x10UL                          
00740 #define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                    
00741 #define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4) 
00742 #define DMA_IFC_CH5DONE                                 (0x1UL << 5)                    
00743 #define _DMA_IFC_CH5DONE_SHIFT                          5                               
00744 #define _DMA_IFC_CH5DONE_MASK                           0x20UL                          
00745 #define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                    
00746 #define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5) 
00747 #define DMA_IFC_ERR                                     (0x1UL << 31)                   
00748 #define _DMA_IFC_ERR_SHIFT                              31                              
00749 #define _DMA_IFC_ERR_MASK                               0x80000000UL                    
00750 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    
00751 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    
00753 /* Bit fields for DMA IEN */
00754 #define _DMA_IEN_RESETVALUE                             0x00000000UL                    
00755 #define _DMA_IEN_MASK                                   0x8000003FUL                    
00756 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    
00757 #define _DMA_IEN_CH0DONE_SHIFT                          0                               
00758 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                           
00759 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    
00760 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) 
00761 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    
00762 #define _DMA_IEN_CH1DONE_SHIFT                          1                               
00763 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                           
00764 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    
00765 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) 
00766 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    
00767 #define _DMA_IEN_CH2DONE_SHIFT                          2                               
00768 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                           
00769 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    
00770 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) 
00771 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    
00772 #define _DMA_IEN_CH3DONE_SHIFT                          3                               
00773 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                           
00774 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    
00775 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) 
00776 #define DMA_IEN_CH4DONE                                 (0x1UL << 4)                    
00777 #define _DMA_IEN_CH4DONE_SHIFT                          4                               
00778 #define _DMA_IEN_CH4DONE_MASK                           0x10UL                          
00779 #define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                    
00780 #define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4) 
00781 #define DMA_IEN_CH5DONE                                 (0x1UL << 5)                    
00782 #define _DMA_IEN_CH5DONE_SHIFT                          5                               
00783 #define _DMA_IEN_CH5DONE_MASK                           0x20UL                          
00784 #define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                    
00785 #define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5) 
00786 #define DMA_IEN_ERR                                     (0x1UL << 31)                   
00787 #define _DMA_IEN_ERR_SHIFT                              31                              
00788 #define _DMA_IEN_ERR_MASK                               0x80000000UL                    
00789 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    
00790 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    
00792 /* Bit fields for DMA CH_CTRL */
00793 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                                  
00794 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                                  
00795 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                             
00796 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                         
00797 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE                  0x00000000UL                                  
00798 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                                  
00799 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                                  
00800 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                                  
00801 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                                  
00802 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                                  
00803 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                                  
00804 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF                  0x00000000UL                                  
00805 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                                  
00806 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR                   0x00000000UL                                  
00807 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN                    0x00000001UL                                  
00808 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                                  
00809 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                                  
00810 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                                  
00811 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                                  
00812 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                                  
00813 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                                  
00814 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0                   0x00000001UL                                  
00815 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR                0x00000001UL                                  
00816 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                                  
00817 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                                  
00818 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                                  
00819 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                                  
00820 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                                  
00821 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1                   0x00000002UL                                  
00822 #define _DMA_CH_CTRL_SIGSEL_AESDATARD                   0x00000002UL                                  
00823 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT          0x00000003UL                                  
00824 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                                  
00825 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                                  
00826 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2                   0x00000003UL                                  
00827 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR                    0x00000003UL                                  
00828 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT             0x00000004UL                                  
00829 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE                   (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)         
00830 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)      
00831 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)      
00832 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)     
00833 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)        
00834 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)         
00835 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)         
00836 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)         
00837 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)           
00838 #define DMA_CH_CTRL_SIGSEL_AESDATAWR                    (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)          
00839 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN                     (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)           
00840 #define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)         
00841 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)         
00842 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)        
00843 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)           
00844 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)          
00845 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)          
00846 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)          
00847 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR                 (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)       
00848 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)      
00849 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)      
00850 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)     
00851 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)          
00852 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)          
00853 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)          
00854 #define DMA_CH_CTRL_SIGSEL_AESDATARD                    (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)          
00855 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) 
00856 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)          
00857 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)          
00858 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)          
00859 #define DMA_CH_CTRL_SIGSEL_AESKEYWR                     (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)           
00860 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)    
00861 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                            
00862 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                    
00863 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                                  
00864 #define _DMA_CH_CTRL_SOURCESEL_ADC0                     0x00000008UL                                  
00865 #define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                                  
00866 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                                  
00867 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                                  
00868 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                                  
00869 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                                  
00870 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                                  
00871 #define _DMA_CH_CTRL_SOURCESEL_TIMER2                   0x0000001AUL                                  
00872 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                                  
00873 #define _DMA_CH_CTRL_SOURCESEL_AES                      0x00000031UL                                  
00874 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)           
00875 #define DMA_CH_CTRL_SOURCESEL_ADC0                      (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)           
00876 #define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)         
00877 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)         
00878 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)        
00879 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)           
00880 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)         
00881 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)         
00882 #define DMA_CH_CTRL_SOURCESEL_TIMER2                    (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)         
00883 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)            
00884 #define DMA_CH_CTRL_SOURCESEL_AES                       (_DMA_CH_CTRL_SOURCESEL_AES << 16)