release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg108f32.h

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00001 /**************************************************************************/
00034 #ifndef __SILICON_LABS_EFM32HG108F32_H__
00035 #define __SILICON_LABS_EFM32HG108F32_H__
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
00055   NonMaskableInt_IRQn = -14,                
00056   HardFault_IRQn      = -13,                
00057   SVCall_IRQn         = -5,                 
00058   PendSV_IRQn         = -2,                 
00059   SysTick_IRQn        = -1,                 
00061 /******  EFM32HG Peripheral Interrupt Numbers *********************************************/
00062   DMA_IRQn            = 0,  
00063   GPIO_EVEN_IRQn      = 1,  
00064   TIMER0_IRQn         = 2,  
00065   ACMP0_IRQn          = 3,  
00066   I2C0_IRQn           = 5,  
00067   GPIO_ODD_IRQn       = 6,  
00068   TIMER1_IRQn         = 7,  
00069   USART1_RX_IRQn      = 8,  
00070   USART1_TX_IRQn      = 9,  
00071   LEUART0_IRQn        = 10, 
00072   PCNT0_IRQn          = 11, 
00073   RTC_IRQn            = 12, 
00074   CMU_IRQn            = 13, 
00075   VCMP_IRQn           = 14, 
00076   MSC_IRQn            = 15, 
00077   USART0_RX_IRQn      = 17, 
00078   USART0_TX_IRQn      = 18, 
00079   TIMER2_IRQn         = 20, 
00080 } IRQn_Type;
00081 
00082 /**************************************************************************/
00087 #define __MPU_PRESENT             0 
00088 #define __VTOR_PRESENT            1 
00089 #define __NVIC_PRIO_BITS          2 
00090 #define __Vendor_SysTickConfig    0 
00094 /**************************************************************************/
00100 #define _EFM32_HAPPY_FAMILY             1 
00101 #define _EFM_DEVICE                       
00102 #define _SILICON_LABS_32B_PLATFORM_1      
00103 #define _SILICON_LABS_32B_PLATFORM      1 
00105 /* If part number is not defined as compiler option, define it */
00106 #if !defined(EFM32HG108F32)
00107 #define EFM32HG108F32    1 
00108 #endif
00109 
00111 #define PART_NUMBER          "EFM32HG108F32" 
00114 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00115 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00116 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00117 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00118 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00119 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00120 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00121 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00122 #define USBC_MEM_BASE        ((uint32_t) 0x40100000UL) 
00123 #define USBC_MEM_SIZE        ((uint32_t) 0x40000UL)    
00124 #define USBC_MEM_END         ((uint32_t) 0x4013FFFFUL) 
00125 #define USBC_MEM_BITS        ((uint32_t) 0x18UL)       
00126 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00127 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00128 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00129 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00130 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00131 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00132 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00133 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00134 #define DEVICE_MEM_BASE      ((uint32_t) 0xF0040000UL) 
00135 #define DEVICE_MEM_SIZE      ((uint32_t) 0x1000UL)     
00136 #define DEVICE_MEM_END       ((uint32_t) 0xF0040FFFUL) 
00137 #define DEVICE_MEM_BITS      ((uint32_t) 0x12UL)       
00138 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00139 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00140 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00141 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00144 #define FLASH_BASE           (0x00000000UL) 
00145 #define FLASH_SIZE           (0x00008000UL) 
00146 #define FLASH_PAGE_SIZE      1024           
00147 #define SRAM_BASE            (0x20000000UL) 
00148 #define SRAM_SIZE            (0x00001000UL) 
00149 #define __CM0PLUS_REV        0x001          
00150 #define PRS_CHAN_COUNT       6              
00151 #define DMA_CHAN_COUNT       6              
00154 #define AFCHAN_MAX           42
00155 #define AFCHANLOC_MAX        7
00156 
00157 #define AFACHAN_MAX          27
00158 
00159 /* Part number capabilities */
00160 
00161 #define TIMER_PRESENT         
00162 #define TIMER_COUNT         3 
00163 #define ACMP_PRESENT          
00164 #define ACMP_COUNT          1 
00165 #define USART_PRESENT         
00166 #define USART_COUNT         2 
00167 #define LEUART_PRESENT        
00168 #define LEUART_COUNT        1 
00169 #define PCNT_PRESENT          
00170 #define PCNT_COUNT          1 
00171 #define I2C_PRESENT           
00172 #define I2C_COUNT           1 
00173 #define DMA_PRESENT
00174 #define DMA_COUNT           1
00175 #define LE_PRESENT
00176 #define LE_COUNT            1
00177 #define USBLE_PRESENT
00178 #define USBLE_COUNT         1
00179 #define MSC_PRESENT
00180 #define MSC_COUNT           1
00181 #define EMU_PRESENT
00182 #define EMU_COUNT           1
00183 #define RMU_PRESENT
00184 #define RMU_COUNT           1
00185 #define CMU_PRESENT
00186 #define CMU_COUNT           1
00187 #define PRS_PRESENT
00188 #define PRS_COUNT           1
00189 #define GPIO_PRESENT
00190 #define GPIO_COUNT          1
00191 #define VCMP_PRESENT
00192 #define VCMP_COUNT          1
00193 #define RTC_PRESENT
00194 #define RTC_COUNT           1
00195 #define HFXTAL_PRESENT
00196 #define HFXTAL_COUNT        1
00197 #define LFXTAL_PRESENT
00198 #define LFXTAL_COUNT        1
00199 #define USHFRCO_PRESENT
00200 #define USHFRCO_COUNT       1
00201 #define WDOG_PRESENT
00202 #define WDOG_COUNT          1
00203 #define DBG_PRESENT
00204 #define DBG_COUNT           1
00205 #define MTB_PRESENT
00206 #define MTB_COUNT           1
00207 #define BOOTLOADER_PRESENT
00208 #define BOOTLOADER_COUNT    1
00209 #define ANALOG_PRESENT
00210 #define ANALOG_COUNT        1
00211 
00214 #define ARM_MATH_CM0PLUS
00215 #include "arm_math.h"       /* To get __CLZ definitions etc. */
00216 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
00217 #include "system_efm32hg.h" /* System Header */
00218 
00219 /**************************************************************************/
00225 #include "efm32hg_dma_ch.h"
00226 
00227 /**************************************************************************/
00232 typedef struct
00233 {
00234   __I uint32_t   STATUS;         
00235   __O uint32_t   CONFIG;         
00236   __IO uint32_t  CTRLBASE;       
00237   __I uint32_t   ALTCTRLBASE;    
00238   __I uint32_t   CHWAITSTATUS;   
00239   __O uint32_t   CHSWREQ;        
00240   __IO uint32_t  CHUSEBURSTS;    
00241   __O uint32_t   CHUSEBURSTC;    
00242   __IO uint32_t  CHREQMASKS;     
00243   __O uint32_t   CHREQMASKC;     
00244   __IO uint32_t  CHENS;          
00245   __O uint32_t   CHENC;          
00246   __IO uint32_t  CHALTS;         
00247   __O uint32_t   CHALTC;         
00248   __IO uint32_t  CHPRIS;         
00249   __O uint32_t   CHPRIC;         
00250   uint32_t       RESERVED0[3];   
00251   __IO uint32_t  ERRORC;         
00253   uint32_t       RESERVED1[880]; 
00254   __I uint32_t   CHREQSTATUS;    
00255   uint32_t       RESERVED2[1];   
00256   __I uint32_t   CHSREQSTATUS;   
00258   uint32_t       RESERVED3[121]; 
00259   __I uint32_t   IF;             
00260   __IO uint32_t  IFS;            
00261   __IO uint32_t  IFC;            
00262   __IO uint32_t  IEN;            
00264   uint32_t       RESERVED4[60];  
00265   DMA_CH_TypeDef CH[6];          
00266 } DMA_TypeDef;                   
00268 #include "efm32hg_msc.h"
00269 #include "efm32hg_emu.h"
00270 #include "efm32hg_rmu.h"
00271 
00272 /**************************************************************************/
00277 typedef struct
00278 {
00279   __IO uint32_t CTRL;          
00280   __IO uint32_t HFCORECLKDIV;  
00281   __IO uint32_t HFPERCLKDIV;   
00282   __IO uint32_t HFRCOCTRL;     
00283   __IO uint32_t LFRCOCTRL;     
00284   __IO uint32_t AUXHFRCOCTRL;  
00285   __IO uint32_t CALCTRL;       
00286   __IO uint32_t CALCNT;        
00287   __IO uint32_t OSCENCMD;      
00288   __IO uint32_t CMD;           
00289   __IO uint32_t LFCLKSEL;      
00290   __I uint32_t  STATUS;        
00291   __I uint32_t  IF;            
00292   __IO uint32_t IFS;           
00293   __IO uint32_t IFC;           
00294   __IO uint32_t IEN;           
00295   __IO uint32_t HFCORECLKEN0;  
00296   __IO uint32_t HFPERCLKEN0;   
00297   uint32_t      RESERVED0[2];  
00298   __I uint32_t  SYNCBUSY;      
00299   __IO uint32_t FREEZE;        
00300   __IO uint32_t LFACLKEN0;     
00301   uint32_t      RESERVED1[1];  
00302   __IO uint32_t LFBCLKEN0;     
00303   __IO uint32_t LFCCLKEN0;     
00304   __IO uint32_t LFAPRESC0;     
00305   uint32_t      RESERVED2[1];  
00306   __IO uint32_t LFBPRESC0;     
00307   uint32_t      RESERVED3[1];  
00308   __IO uint32_t PCNTCTRL;      
00310   uint32_t      RESERVED4[1];  
00311   __IO uint32_t ROUTE;         
00312   __IO uint32_t LOCK;          
00314   uint32_t      RESERVED5[18]; 
00315   __IO uint32_t USBCRCTRL;     
00316   __IO uint32_t USHFRCOCTRL;   
00317   __IO uint32_t USHFRCOTUNE;   
00318   __IO uint32_t USHFRCOCONF;   
00319 } CMU_TypeDef;                 
00321 #include "efm32hg_timer_cc.h"
00322 #include "efm32hg_timer.h"
00323 #include "efm32hg_acmp.h"
00324 #include "efm32hg_usart.h"
00325 #include "efm32hg_prs_ch.h"
00326 
00327 /**************************************************************************/
00332 typedef struct
00333 {
00334   __IO uint32_t  SWPULSE;      
00335   __IO uint32_t  SWLEVEL;      
00336   __IO uint32_t  ROUTE;        
00338   uint32_t       RESERVED0[1]; 
00339   PRS_CH_TypeDef CH[6];        
00341   uint32_t       RESERVED1[6]; 
00342   __IO uint32_t  TRACECTRL;    
00343 } PRS_TypeDef;                 
00345 #include "efm32hg_gpio_p.h"
00346 #include "efm32hg_gpio.h"
00347 #include "efm32hg_vcmp.h"
00348 #include "efm32hg_leuart.h"
00349 #include "efm32hg_pcnt.h"
00350 #include "efm32hg_i2c.h"
00351 #include "efm32hg_rtc.h"
00352 #include "efm32hg_wdog.h"
00353 #include "efm32hg_mtb.h"
00354 #include "efm32hg_dma_descriptor.h"
00355 #include "efm32hg_devinfo.h"
00356 #include "efm32hg_romtable.h"
00357 #include "efm32hg_calibrate.h"
00358 
00361 /**************************************************************************/
00366 #define DMA_BASE          (0x400C2000UL) 
00367 #define MSC_BASE          (0x400C0000UL) 
00368 #define EMU_BASE          (0x400C6000UL) 
00369 #define RMU_BASE          (0x400CA000UL) 
00370 #define CMU_BASE          (0x400C8000UL) 
00371 #define TIMER0_BASE       (0x40010000UL) 
00372 #define TIMER1_BASE       (0x40010400UL) 
00373 #define TIMER2_BASE       (0x40010800UL) 
00374 #define ACMP0_BASE        (0x40001000UL) 
00375 #define USART0_BASE       (0x4000C000UL) 
00376 #define USART1_BASE       (0x4000C400UL) 
00377 #define PRS_BASE          (0x400CC000UL) 
00378 #define GPIO_BASE         (0x40006000UL) 
00379 #define VCMP_BASE         (0x40000000UL) 
00380 #define LEUART0_BASE      (0x40084000UL) 
00381 #define PCNT0_BASE        (0x40086000UL) 
00382 #define I2C0_BASE         (0x4000A000UL) 
00383 #define RTC_BASE          (0x40080000UL) 
00384 #define WDOG_BASE         (0x40088000UL) 
00385 #define MTB_BASE          (0xF0040000UL) 
00386 #define CALIBRATE_BASE    (0x0FE08000UL) 
00387 #define DEVINFO_BASE      (0x0FE081B0UL) 
00388 #define ROMTABLE_BASE     (0xF00FFFD0UL) 
00389 #define LOCKBITS_BASE     (0x0FE04000UL) 
00390 #define USERDATA_BASE     (0x0FE00000UL) 
00394 /**************************************************************************/
00399 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00400 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00401 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00402 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00403 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00404 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00405 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00406 #define TIMER2       ((TIMER_TypeDef *) TIMER2_BASE)        
00407 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00408 #define USART0       ((USART_TypeDef *) USART0_BASE)        
00409 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00410 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00411 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00412 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00413 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00414 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00415 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00416 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00417 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00418 #define MTB          ((MTB_TypeDef *) MTB_BASE)             
00419 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00420 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00421 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00425 /**************************************************************************/
00430 /**************************************************************************/
00435 #define PRS_VCMP_OUT          ((1 << 16) + 0)  
00436 #define PRS_ACMP0_OUT         ((2 << 16) + 0)  
00437 #define PRS_USART0_IRTX       ((16 << 16) + 0) 
00438 #define PRS_USART0_TXC        ((16 << 16) + 1) 
00439 #define PRS_USART0_RXDATAV    ((16 << 16) + 2) 
00440 #define PRS_USART1_IRTX       ((17 << 16) + 0) 
00441 #define PRS_USART1_TXC        ((17 << 16) + 1) 
00442 #define PRS_USART1_RXDATAV    ((17 << 16) + 2) 
00443 #define PRS_TIMER0_UF         ((28 << 16) + 0) 
00444 #define PRS_TIMER0_OF         ((28 << 16) + 1) 
00445 #define PRS_TIMER0_CC0        ((28 << 16) + 2) 
00446 #define PRS_TIMER0_CC1        ((28 << 16) + 3) 
00447 #define PRS_TIMER0_CC2        ((28 << 16) + 4) 
00448 #define PRS_TIMER1_UF         ((29 << 16) + 0) 
00449 #define PRS_TIMER1_OF         ((29 << 16) + 1) 
00450 #define PRS_TIMER1_CC0        ((29 << 16) + 2) 
00451 #define PRS_TIMER1_CC1        ((29 << 16) + 3) 
00452 #define PRS_TIMER1_CC2        ((29 << 16) + 4) 
00453 #define PRS_TIMER2_UF         ((30 << 16) + 0) 
00454 #define PRS_TIMER2_OF         ((30 << 16) + 1) 
00455 #define PRS_TIMER2_CC0        ((30 << 16) + 2) 
00456 #define PRS_TIMER2_CC1        ((30 << 16) + 3) 
00457 #define PRS_TIMER2_CC2        ((30 << 16) + 4) 
00458 #define PRS_RTC_OF            ((40 << 16) + 0) 
00459 #define PRS_RTC_COMP0         ((40 << 16) + 1) 
00460 #define PRS_RTC_COMP1         ((40 << 16) + 2) 
00461 #define PRS_GPIO_PIN0         ((48 << 16) + 0) 
00462 #define PRS_GPIO_PIN1         ((48 << 16) + 1) 
00463 #define PRS_GPIO_PIN2         ((48 << 16) + 2) 
00464 #define PRS_GPIO_PIN3         ((48 << 16) + 3) 
00465 #define PRS_GPIO_PIN4         ((48 << 16) + 4) 
00466 #define PRS_GPIO_PIN5         ((48 << 16) + 5) 
00467 #define PRS_GPIO_PIN6         ((48 << 16) + 6) 
00468 #define PRS_GPIO_PIN7         ((48 << 16) + 7) 
00469 #define PRS_GPIO_PIN8         ((49 << 16) + 0) 
00470 #define PRS_GPIO_PIN9         ((49 << 16) + 1) 
00471 #define PRS_GPIO_PIN10        ((49 << 16) + 2) 
00472 #define PRS_GPIO_PIN11        ((49 << 16) + 3) 
00473 #define PRS_GPIO_PIN12        ((49 << 16) + 4) 
00474 #define PRS_GPIO_PIN13        ((49 << 16) + 5) 
00475 #define PRS_GPIO_PIN14        ((49 << 16) + 6) 
00476 #define PRS_GPIO_PIN15        ((49 << 16) + 7) 
00477 #define PRS_PCNT0_TCC         ((54 << 16) + 0) 
00481 #include "efm32hg_dmareq.h"
00482 #include "efm32hg_dmactrl.h"
00483 
00484 /**************************************************************************/
00489 /* Bit fields for DMA STATUS */
00490 #define _DMA_STATUS_RESETVALUE                          0x10050000UL                          
00491 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00492 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00493 #define _DMA_STATUS_EN_SHIFT                            0                                     
00494 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00495 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00496 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00497 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00498 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00499 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00500 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00501 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00502 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00503 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00504 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00505 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00506 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00507 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00508 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00509 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00510 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00511 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00512 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00513 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00514 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00515 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00516 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00517 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00518 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00519 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00520 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00521 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00522 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00523 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00524 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00525 #define _DMA_STATUS_CHNUM_DEFAULT                       0x00000005UL                          
00526 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00528 /* Bit fields for DMA CONFIG */
00529 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00530 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00531 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00532 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00533 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00534 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00535 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00536 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00537 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00538 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00539 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00540 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00542 /* Bit fields for DMA CTRLBASE */
00543 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00544 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00545 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00546 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00547 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00548 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00550 /* Bit fields for DMA ALTCTRLBASE */
00551 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000080UL                                
00552 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00553 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00554 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00555 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000080UL                                
00556 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00558 /* Bit fields for DMA CHWAITSTATUS */
00559 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x0000003FUL                                   
00560 #define _DMA_CHWAITSTATUS_MASK                          0x0000003FUL                                   
00561 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   
00562 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              
00563 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          
00564 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   
00565 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 
00566 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   
00567 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              
00568 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          
00569 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   
00570 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 
00571 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   
00572 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              
00573 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          
00574 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   
00575 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 
00576 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   
00577 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              
00578 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          
00579 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   
00580 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 
00581 #define DMA_CHWAITSTATUS_CH4WAITSTATUS                  (0x1UL << 4)                                   
00582 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT           4                                              
00583 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK            0x10UL                                         
00584 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT         0x00000001UL                                   
00585 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) 
00586 #define DMA_CHWAITSTATUS_CH5WAITSTATUS                  (0x1UL << 5)                                   
00587 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT           5                                              
00588 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK            0x20UL                                         
00589 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT         0x00000001UL                                   
00590 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) 
00592 /* Bit fields for DMA CHSWREQ */
00593 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         
00594 #define _DMA_CHSWREQ_MASK                               0x0000003FUL                         
00595 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         
00596 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    
00597 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                
00598 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         
00599 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 
00600 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         
00601 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    
00602 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                
00603 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         
00604 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 
00605 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         
00606 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    
00607 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                
00608 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         
00609 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 
00610 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         
00611 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    
00612 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                
00613 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         
00614 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 
00615 #define DMA_CHSWREQ_CH4SWREQ                            (0x1UL << 4)                         
00616 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT                     4                                    
00617 #define _DMA_CHSWREQ_CH4SWREQ_MASK                      0x10UL                               
00618 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT                   0x00000000UL                         
00619 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) 
00620 #define DMA_CHSWREQ_CH5SWREQ                            (0x1UL << 5)                         
00621 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT                     5                                    
00622 #define _DMA_CHSWREQ_CH5SWREQ_MASK                      0x20UL                               
00623 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT                   0x00000000UL                         
00624 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) 
00626 /* Bit fields for DMA CHUSEBURSTS */
00627 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00628 #define _DMA_CHUSEBURSTS_MASK                           0x0000003FUL                                        
00629 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00630 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00631 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00632 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00633 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00634 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00635 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00636 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00637 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00638 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00639 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00640 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00641 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00642 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00643 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00644 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00645 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00646 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00647 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00648 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00649 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00650 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00651 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00652 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00653 #define DMA_CHUSEBURSTS_CH4USEBURSTS                    (0x1UL << 4)                                        
00654 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT             4                                                   
00655 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK              0x10UL                                              
00656 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT           0x00000000UL                                        
00657 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)        
00658 #define DMA_CHUSEBURSTS_CH5USEBURSTS                    (0x1UL << 5)                                        
00659 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT             5                                                   
00660 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK              0x20UL                                              
00661 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT           0x00000000UL                                        
00662 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)        
00664 /* Bit fields for DMA CHUSEBURSTC */
00665 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 
00666 #define _DMA_CHUSEBURSTC_MASK                           0x0000003FUL                                 
00667 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 
00668 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            
00669 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        
00670 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 
00671 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 
00672 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 
00673 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            
00674 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        
00675 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 
00676 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 
00677 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 
00678 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            
00679 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        
00680 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 
00681 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 
00682 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 
00683 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            
00684 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        
00685 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 
00686 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 
00687 #define DMA_CHUSEBURSTC_CH4USEBURSTC                    (0x1UL << 4)                                 
00688 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT             4                                            
00689 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK              0x10UL                                       
00690 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT           0x00000000UL                                 
00691 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) 
00692 #define DMA_CHUSEBURSTC_CH5USEBURSTC                    (0x1UL << 5)                                 
00693 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT             5                                            
00694 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK              0x20UL                                       
00695 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT           0x00000000UL                                 
00696 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) 
00698 /* Bit fields for DMA CHREQMASKS */
00699 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               
00700 #define _DMA_CHREQMASKS_MASK                            0x0000003FUL                               
00701 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               
00702 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          
00703 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      
00704 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               
00705 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 
00706 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               
00707 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          
00708 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      
00709 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               
00710 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 
00711 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               
00712 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          
00713 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      
00714 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               
00715 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 
00716 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               
00717 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          
00718 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      
00719 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               
00720 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 
00721 #define DMA_CHREQMASKS_CH4REQMASKS                      (0x1UL << 4)                               
00722 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT               4                                          
00723 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK                0x10UL                                     
00724 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT             0x00000000UL                               
00725 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) 
00726 #define DMA_CHREQMASKS_CH5REQMASKS                      (0x1UL << 5)                               
00727 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT               5                                          
00728 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK                0x20UL                                     
00729 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT             0x00000000UL                               
00730 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) 
00732 /* Bit fields for DMA CHREQMASKC */
00733 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               
00734 #define _DMA_CHREQMASKC_MASK                            0x0000003FUL                               
00735 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               
00736 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          
00737 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      
00738 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               
00739 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 
00740 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               
00741 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          
00742 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      
00743 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               
00744 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 
00745 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               
00746 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          
00747 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      
00748 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               
00749 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 
00750 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               
00751 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          
00752 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      
00753 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               
00754 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 
00755 #define DMA_CHREQMASKC_CH4REQMASKC                      (0x1UL << 4)                               
00756 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT               4                                          
00757 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK                0x10UL                                     
00758 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT             0x00000000UL                               
00759 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) 
00760 #define DMA_CHREQMASKC_CH5REQMASKC                      (0x1UL << 5)                               
00761 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT               5                                          
00762 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK                0x20UL                                     
00763 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT             0x00000000UL                               
00764 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) 
00766 /* Bit fields for DMA CHENS */
00767 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                     
00768 #define _DMA_CHENS_MASK                                 0x0000003FUL                     
00769 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     
00770 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                
00771 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            
00772 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     
00773 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) 
00774 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     
00775 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                
00776 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            
00777 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     
00778 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) 
00779 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     
00780 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                
00781 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            
00782 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     
00783 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) 
00784 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     
00785 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                
00786 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            
00787 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     
00788 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) 
00789 #define DMA_CHENS_CH4ENS                                (0x1UL << 4)                     
00790 #define _DMA_CHENS_CH4ENS_SHIFT                         4                                
00791 #define _DMA_CHENS_CH4ENS_MASK                          0x10UL                           
00792 #define _DMA_CHENS_CH4ENS_DEFAULT                       0x00000000UL                     
00793 #define DMA_CHENS_CH4ENS_DEFAULT                        (_DMA_CHENS_CH4ENS_DEFAULT << 4) 
00794 #define DMA_CHENS_CH5ENS                                (0x1UL << 5)                     
00795 #define _DMA_CHENS_CH5ENS_SHIFT                         5                                
00796 #define _DMA_CHENS_CH5ENS_MASK                          0x20UL                           
00797 #define _DMA_CHENS_CH5ENS_DEFAULT                       0x00000000UL                     
00798 #define DMA_CHENS_CH5ENS_DEFAULT                        (_DMA_CHENS_CH5ENS_DEFAULT << 5) 
00800 /* Bit fields for DMA CHENC */
00801 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                     
00802 #define _DMA_CHENC_MASK                                 0x0000003FUL                     
00803 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     
00804 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                
00805 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            
00806 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     
00807 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) 
00808 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     
00809 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                
00810 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            
00811 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     
00812 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) 
00813 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     
00814 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                
00815 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            
00816 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     
00817 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) 
00818 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     
00819 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                
00820 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            
00821 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     
00822 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) 
00823 #define DMA_CHENC_CH4ENC                                (0x1UL << 4)                     
00824 #define _DMA_CHENC_CH4ENC_SHIFT                         4                                
00825 #define _DMA_CHENC_CH4ENC_MASK                          0x10UL                           
00826 #define _DMA_CHENC_CH4ENC_DEFAULT                       0x00000000UL                     
00827 #define DMA_CHENC_CH4ENC_DEFAULT                        (_DMA_CHENC_CH4ENC_DEFAULT << 4) 
00828 #define DMA_CHENC_CH5ENC                                (0x1UL << 5)                     
00829 #define _DMA_CHENC_CH5ENC_SHIFT                         5                                
00830 #define _DMA_CHENC_CH5ENC_MASK                          0x20UL                           
00831 #define _DMA_CHENC_CH5ENC_DEFAULT                       0x00000000UL                     
00832 #define DMA_CHENC_CH5ENC_DEFAULT                        (_DMA_CHENC_CH5ENC_DEFAULT << 5) 
00834 /* Bit fields for DMA CHALTS */
00835 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       
00836 #define _DMA_CHALTS_MASK                                0x0000003FUL                       
00837 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       
00838 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  
00839 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              
00840 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       
00841 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 
00842 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       
00843 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  
00844 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              
00845 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       
00846 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 
00847 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       
00848 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  
00849 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              
00850 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       
00851 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 
00852 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       
00853 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  
00854 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              
00855 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       
00856 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 
00857 #define DMA_CHALTS_CH4ALTS                              (0x1UL << 4)                       
00858 #define _DMA_CHALTS_CH4ALTS_SHIFT                       4                                  
00859 #define _DMA_CHALTS_CH4ALTS_MASK                        0x10UL                             
00860 #define _DMA_CHALTS_CH4ALTS_DEFAULT                     0x00000000UL                       
00861 #define DMA_CHALTS_CH4ALTS_DEFAULT                      (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) 
00862 #define DMA_CHALTS_CH5ALTS                              (0x1UL << 5)                       
00863 #define _DMA_CHALTS_CH5ALTS_SHIFT                       5                                  
00864 #define _DMA_CHALTS_CH5ALTS_MASK                        0x20UL                             
00865 #define _DMA_CHALTS_CH5ALTS_DEFAULT                     0x00000000UL                       
00866 #define DMA_CHALTS_CH5ALTS_DEFAULT                      (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) 
00868 /* Bit fields for DMA CHALTC */
00869 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       
00870 #define _DMA_CHALTC_MASK                                0x0000003FUL                       
00871 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       
00872 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  
00873 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              
00874 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       
00875 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 
00876 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       
00877 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  
00878 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              
00879 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       
00880 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 
00881 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       
00882 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  
00883 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              
00884 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       
00885 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 
00886 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       
00887 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  
00888 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              
00889 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       
00890 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 
00891 #define DMA_CHALTC_CH4ALTC                              (0x1UL << 4)                       
00892 #define _DMA_CHALTC_CH4ALTC_SHIFT                       4                                  
00893 #define _DMA_CHALTC_CH4ALTC_MASK                        0x10UL                             
00894 #define _DMA_CHALTC_CH4ALTC_DEFAULT                     0x00000000UL                       
00895 #define DMA_CHALTC_CH4ALTC_DEFAULT                      (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) 
00896 #define DMA_CHALTC_CH5ALTC                              (0x1UL << 5)                       
00897 #define _DMA_CHALTC_CH5ALTC_SHIFT                       5                                  
00898 #define _DMA_CHALTC_CH5ALTC_MASK                        0x20UL                             
00899 #define _DMA_CHALTC_CH5ALTC_DEFAULT                     0x00000000UL                       
00900 #define DMA_CHALTC_CH5ALTC_DEFAULT                      (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) 
00902 /* Bit fields for DMA CHPRIS */
00903 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       
00904 #define _DMA_CHPRIS_MASK                                0x0000003FUL                       
00905 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       
00906 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  
00907 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              
00908 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       
00909 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 
00910 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       
00911 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  
00912 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              
00913 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       
00914 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 
00915 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       
00916 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  
00917 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              
00918 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       
00919 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 
00920 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       
00921 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  
00922 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              
00923 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       
00924 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 
00925 #define DMA_CHPRIS_CH4PRIS                              (0x1UL << 4)                       
00926 #define _DMA_CHPRIS_CH4PRIS_SHIFT                       4                                  
00927 #define _DMA_CHPRIS_CH4PRIS_MASK                        0x10UL                             
00928 #define _DMA_CHPRIS_CH4PRIS_DEFAULT                     0x00000000UL                       
00929 #define DMA_CHPRIS_CH4PRIS_DEFAULT                      (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) 
00930 #define DMA_CHPRIS_CH5PRIS                              (0x1UL << 5)                       
00931 #define _DMA_CHPRIS_CH5PRIS_SHIFT                       5                                  
00932 #define _DMA_CHPRIS_CH5PRIS_MASK                        0x20UL                             
00933 #define _DMA_CHPRIS_CH5PRIS_DEFAULT                     0x00000000UL                       
00934 #define DMA_CHPRIS_CH5PRIS_DEFAULT                      (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) 
00936 /* Bit fields for DMA CHPRIC */
00937 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       
00938 #define _DMA_CHPRIC_MASK                                0x0000003FUL                       
00939 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       
00940 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  
00941 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              
00942 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       
00943 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 
00944 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       
00945 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  
00946 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              
00947 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       
00948 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 
00949 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       
00950 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  
00951 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              
00952 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       
00953 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 
00954 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       
00955 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  
00956 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              
00957 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       
00958 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 
00959 #define DMA_CHPRIC_CH4PRIC                              (0x1UL << 4)                       
00960 #define _DMA_CHPRIC_CH4PRIC_SHIFT                       4                                  
00961 #define _DMA_CHPRIC_CH4PRIC_MASK                        0x10UL                             
00962 #define _DMA_CHPRIC_CH4PRIC_DEFAULT                     0x00000000UL                       
00963 #define DMA_CHPRIC_CH4PRIC_DEFAULT                      (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) 
00964 #define DMA_CHPRIC_CH5PRIC                              (0x1UL << 5)                       
00965 #define _DMA_CHPRIC_CH5PRIC_SHIFT                       5                                  
00966 #define _DMA_CHPRIC_CH5PRIC_MASK                        0x20UL                             
00967 #define _DMA_CHPRIC_CH5PRIC_DEFAULT                     0x00000000UL                       
00968 #define DMA_CHPRIC_CH5PRIC_DEFAULT                      (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) 
00970 /* Bit fields for DMA ERRORC */
00971 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
00972 #define _DMA_ERRORC_MASK                                0x00000001UL                      
00973 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
00974 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
00975 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
00976 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
00977 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
00979 /* Bit fields for DMA CHREQSTATUS */
00980 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 
00981 #define _DMA_CHREQSTATUS_MASK                           0x0000003FUL                                 
00982 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 
00983 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            
00984 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        
00985 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 
00986 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 
00987 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 
00988 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            
00989 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        
00990 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 
00991 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 
00992 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 
00993 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            
00994 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        
00995 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 
00996 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 
00997 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 
00998 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            
00999 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        
01000 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 
01001 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 
01002 #define DMA_CHREQSTATUS_CH4REQSTATUS                    (0x1UL << 4)                                 
01003 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT             4                                            
01004 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK              0x10UL                                       
01005 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT           0x00000000UL                                 
01006 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) 
01007 #define DMA_CHREQSTATUS_CH5REQSTATUS                    (0x1UL << 5)                                 
01008 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT             5                                            
01009 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK              0x20UL                                       
01010 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT           0x00000000UL                                 
01011 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) 
01013 /* Bit fields for DMA CHSREQSTATUS */
01014 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   
01015 #define _DMA_CHSREQSTATUS_MASK                          0x0000003FUL                                   
01016 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   
01017 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              
01018 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          
01019 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   
01020 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 
01021 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   
01022 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              
01023 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          
01024 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   
01025 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 
01026 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   
01027 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              
01028 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          
01029 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   
01030 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 
01031 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   
01032 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              
01033 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          
01034 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   
01035 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 
01036 #define DMA_CHSREQSTATUS_CH4SREQSTATUS                  (0x1UL << 4)                                   
01037 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT           4                                              
01038 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK            0x10UL                                         
01039 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT         0x00000000UL                                   
01040 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) 
01041 #define DMA_CHSREQSTATUS_CH5SREQSTATUS                  (0x1UL << 5)                                   
01042 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT           5                                              
01043 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK            0x20UL                                         
01044 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT         0x00000000UL                                   
01045 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) 
01047 /* Bit fields for DMA IF */
01048 #define _DMA_IF_RESETVALUE                              0x00000000UL                   
01049 #define _DMA_IF_MASK                                    0x8000003FUL                   
01050 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                   
01051 #define _DMA_IF_CH0DONE_SHIFT                           0                              
01052 #define _DMA_IF_CH0DONE_MASK                            0x1UL                          
01053 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   
01054 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) 
01055 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                   
01056 #define _DMA_IF_CH1DONE_SHIFT                           1                              
01057 #define _DMA_IF_CH1DONE_MASK                            0x2UL                          
01058 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   
01059 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) 
01060 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                   
01061 #define _DMA_IF_CH2DONE_SHIFT                           2                              
01062 #define _DMA_IF_CH2DONE_MASK                            0x4UL                          
01063 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   
01064 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) 
01065 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                   
01066 #define _DMA_IF_CH3DONE_SHIFT                           3                              
01067 #define _DMA_IF_CH3DONE_MASK                            0x8UL                          
01068 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   
01069 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) 
01070 #define DMA_IF_CH4DONE                                  (0x1UL << 4)                   
01071 #define _DMA_IF_CH4DONE_SHIFT                           4                              
01072 #define _DMA_IF_CH4DONE_MASK                            0x10UL                         
01073 #define _DMA_IF_CH4DONE_DEFAULT                         0x00000000UL                   
01074 #define DMA_IF_CH4DONE_DEFAULT                          (_DMA_IF_CH4DONE_DEFAULT << 4) 
01075 #define DMA_IF_CH5DONE                                  (0x1UL << 5)                   
01076 #define _DMA_IF_CH5DONE_SHIFT                           5                              
01077 #define _DMA_IF_CH5DONE_MASK                            0x20UL                         
01078 #define _DMA_IF_CH5DONE_DEFAULT                         0x00000000UL                   
01079 #define DMA_IF_CH5DONE_DEFAULT                          (_DMA_IF_CH5DONE_DEFAULT << 5) 
01080 #define DMA_IF_ERR                                      (0x1UL << 31)                  
01081 #define _DMA_IF_ERR_SHIFT                               31                             
01082 #define _DMA_IF_ERR_MASK                                0x80000000UL                   
01083 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   
01084 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    
01086 /* Bit fields for DMA IFS */
01087 #define _DMA_IFS_RESETVALUE                             0x00000000UL                    
01088 #define _DMA_IFS_MASK                                   0x8000003FUL                    
01089 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    
01090 #define _DMA_IFS_CH0DONE_SHIFT                          0                               
01091 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                           
01092 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    
01093 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) 
01094 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    
01095 #define _DMA_IFS_CH1DONE_SHIFT                          1                               
01096 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                           
01097 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    
01098 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) 
01099 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    
01100 #define _DMA_IFS_CH2DONE_SHIFT                          2                               
01101 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                           
01102 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    
01103 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) 
01104 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    
01105 #define _DMA_IFS_CH3DONE_SHIFT                          3                               
01106 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                           
01107 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    
01108 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) 
01109 #define DMA_IFS_CH4DONE                                 (0x1UL << 4)                    
01110 #define _DMA_IFS_CH4DONE_SHIFT                          4                               
01111 #define _DMA_IFS_CH4DONE_MASK                           0x10UL                          
01112 #define _DMA_IFS_CH4DONE_DEFAULT                        0x00000000UL                    
01113 #define DMA_IFS_CH4DONE_DEFAULT                         (_DMA_IFS_CH4DONE_DEFAULT << 4) 
01114 #define DMA_IFS_CH5DONE                                 (0x1UL << 5)                    
01115 #define _DMA_IFS_CH5DONE_SHIFT                          5                               
01116 #define _DMA_IFS_CH5DONE_MASK                           0x20UL                          
01117 #define _DMA_IFS_CH5DONE_DEFAULT                        0x00000000UL                    
01118 #define DMA_IFS_CH5DONE_DEFAULT                         (_DMA_IFS_CH5DONE_DEFAULT << 5) 
01119 #define DMA_IFS_ERR                                     (0x1UL << 31)                   
01120 #define _DMA_IFS_ERR_SHIFT                              31                              
01121 #define _DMA_IFS_ERR_MASK                               0x80000000UL                    
01122 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    
01123 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    
01125 /* Bit fields for DMA IFC */
01126 #define _DMA_IFC_RESETVALUE                             0x00000000UL                    
01127 #define _DMA_IFC_MASK                                   0x8000003FUL                    
01128 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    
01129 #define _DMA_IFC_CH0DONE_SHIFT                          0                               
01130 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                           
01131 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    
01132 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) 
01133 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    
01134 #define _DMA_IFC_CH1DONE_SHIFT                          1                               
01135 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                           
01136 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    
01137 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) 
01138 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    
01139 #define _DMA_IFC_CH2DONE_SHIFT                          2                               
01140 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                           
01141 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    
01142 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) 
01143 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    
01144 #define _DMA_IFC_CH3DONE_SHIFT                          3                               
01145 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                           
01146 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    
01147 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) 
01148 #define DMA_IFC_CH4DONE                                 (0x1UL << 4)                    
01149 #define _DMA_IFC_CH4DONE_SHIFT                          4                               
01150 #define _DMA_IFC_CH4DONE_MASK                           0x10UL                          
01151 #define _DMA_IFC_CH4DONE_DEFAULT                        0x00000000UL                    
01152 #define DMA_IFC_CH4DONE_DEFAULT                         (_DMA_IFC_CH4DONE_DEFAULT << 4) 
01153 #define DMA_IFC_CH5DONE                                 (0x1UL << 5)                    
01154 #define _DMA_IFC_CH5DONE_SHIFT                          5                               
01155 #define _DMA_IFC_CH5DONE_MASK                           0x20UL                          
01156 #define _DMA_IFC_CH5DONE_DEFAULT                        0x00000000UL                    
01157 #define DMA_IFC_CH5DONE_DEFAULT                         (_DMA_IFC_CH5DONE_DEFAULT << 5) 
01158 #define DMA_IFC_ERR                                     (0x1UL << 31)                   
01159 #define _DMA_IFC_ERR_SHIFT                              31                              
01160 #define _DMA_IFC_ERR_MASK                               0x80000000UL                    
01161 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    
01162 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    
01164 /* Bit fields for DMA IEN */
01165 #define _DMA_IEN_RESETVALUE                             0x00000000UL                    
01166 #define _DMA_IEN_MASK                                   0x8000003FUL                    
01167 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    
01168 #define _DMA_IEN_CH0DONE_SHIFT                          0                               
01169 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                           
01170 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    
01171 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) 
01172 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    
01173 #define _DMA_IEN_CH1DONE_SHIFT                          1                               
01174 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                           
01175 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    
01176 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) 
01177 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    
01178 #define _DMA_IEN_CH2DONE_SHIFT                          2                               
01179 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                           
01180 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    
01181 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) 
01182 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    
01183 #define _DMA_IEN_CH3DONE_SHIFT                          3                               
01184 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                           
01185 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    
01186 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) 
01187 #define DMA_IEN_CH4DONE                                 (0x1UL << 4)                    
01188 #define _DMA_IEN_CH4DONE_SHIFT                          4                               
01189 #define _DMA_IEN_CH4DONE_MASK                           0x10UL                          
01190 #define _DMA_IEN_CH4DONE_DEFAULT                        0x00000000UL                    
01191 #define DMA_IEN_CH4DONE_DEFAULT                         (_DMA_IEN_CH4DONE_DEFAULT << 4) 
01192 #define DMA_IEN_CH5DONE                                 (0x1UL << 5)                    
01193 #define _DMA_IEN_CH5DONE_SHIFT                          5                               
01194 #define _DMA_IEN_CH5DONE_MASK                           0x20UL                          
01195 #define _DMA_IEN_CH5DONE_DEFAULT                        0x00000000UL                    
01196 #define DMA_IEN_CH5DONE_DEFAULT                         (_DMA_IEN_CH5DONE_DEFAULT << 5) 
01197 #define DMA_IEN_ERR                                     (0x1UL << 31)                   
01198 #define _DMA_IEN_ERR_SHIFT                              31                              
01199 #define _DMA_IEN_ERR_MASK                               0x80000000UL                    
01200 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    
01201 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    
01203 /* Bit fields for DMA CH_CTRL */
01204 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                                  
01205 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                                  
01206 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                             
01207 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                         
01208 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV               0x00000000UL                                  
01209 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                                  
01210 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                                  
01211 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                                  
01212 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                                  
01213 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                                  
01214 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF                  0x00000000UL                                  
01215 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                                  
01216 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL                  0x00000001UL                                  
01217 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                                  
01218 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                                  
01219 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                                  
01220 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                                  
01221 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                                  
01222 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0                   0x00000001UL                                  
01223 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY               0x00000002UL                                  
01224 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                                  
01225 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                                  
01226 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                                  
01227 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                                  
01228 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1                   0x00000002UL                                  
01229 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT          0x00000003UL                                  
01230 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                                  
01231 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                                  
01232 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2                   0x00000003UL                                  
01233 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT             0x00000004UL                                  
01234 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)      
01235 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)      
01236 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)     
01237 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)        
01238 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)         
01239 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)         
01240 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)         
01241 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)           
01242 #define DMA_CH_CTRL_SIGSEL_USART0TXBL                   (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)         
01243 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)         
01244 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)        
01245 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)           
01246 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)          
01247 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)          
01248 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)          
01249 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)      
01250 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)      
01251 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)     
01252 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)          
01253 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)          
01254 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)          
01255 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) 
01256 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)          
01257 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)          
01258 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)          
01259 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)    
01260 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                            
01261 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                    
01262 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                                  
01263 #define _DMA_CH_CTRL_SOURCESEL_USART0                   0x0000000CUL                                  
01264 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                                  
01265 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                                  
01266 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                                  
01267 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                                  
01268 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                                  
01269 #define _DMA_CH_CTRL_SOURCESEL_TIMER2                   0x0000001AUL                                  
01270 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                                  
01271 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)           
01272 #define DMA_CH_CTRL_SOURCESEL_USART0                    (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)         
01273 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)         
01274 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)        
01275 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)           
01276 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)         
01277 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)         
01278 #define DMA_CH_CTRL_SOURCESEL_TIMER2                    (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)         
01279 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)            
01285 /**************************************************************************/
01290 /* Bit fields for CMU CTRL */
01291 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             
01292 #define _CMU_CTRL_MASK                              0x07FFFEEFUL                             
01293 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        
01294 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    
01295 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                             
01296 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                             
01297 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                             
01298 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                             
01299 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        
01300 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)           
01301 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      
01302 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      
01303 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                        
01304 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                    
01305 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                             
01306 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                             
01307 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                             
01308 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                             
01309 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                             
01310 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       
01311 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       
01312 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       
01313 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       
01314 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      
01315 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                        
01316 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                   
01317 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                             
01318 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      
01319 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                             
01320 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                        
01321 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                   
01322 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                             
01323 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 
01324 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                        
01325 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                  
01326 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                             
01327 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                             
01328 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                             
01329 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                             
01330 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                             
01331 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     
01332 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   
01333 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    
01334 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     
01335 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   
01336 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                       
01337 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                 
01338 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                             
01339 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                             
01340 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                             
01341 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                             
01342 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       
01343 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)          
01344 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     
01345 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     
01346 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                            
01347 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                       
01348 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                 
01349 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                             
01350 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                             
01351 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                             
01352 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      
01353 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      
01354 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     
01355 #define _CMU_CTRL_HFCLKDIV_SHIFT                    14                                       
01356 #define _CMU_CTRL_HFCLKDIV_MASK                     0x1C000UL                                
01357 #define _CMU_CTRL_HFCLKDIV_DEFAULT                  0x00000000UL                             
01358 #define CMU_CTRL_HFCLKDIV_DEFAULT                   (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)       
01359 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                            
01360 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                       
01361 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                
01362 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                             
01363 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     
01364 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                       
01365 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                
01366 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                             
01367 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                             
01368 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                             
01369 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                             
01370 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                             
01371 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    
01372 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   
01373 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  
01374 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    
01375 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  
01376 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                       
01377 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                               
01378 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                             
01379 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                             
01380 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                             
01381 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                             
01382 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                             
01383 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                             
01384 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                             
01385 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                             
01386 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                             
01387 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     
01388 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       
01389 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        
01390 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      
01391 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      
01392 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      
01393 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     
01394 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      
01395 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)    
01396 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                       
01397 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                              
01398 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                             
01399 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                             
01400 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                             
01401 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                             
01402 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                             
01403 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                             
01404 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                             
01405 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                             
01406 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                             
01407 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO                0x00000008UL                             
01408 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     
01409 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       
01410 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        
01411 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)       
01412 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)       
01413 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)       
01414 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)      
01415 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)      
01416 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)   
01417 #define CMU_CTRL_CLKOUTSEL1_USHFRCO                 (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23)     
01419 /* Bit fields for CMU HFCORECLKDIV */
01420 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
01421 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
01422 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
01423 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
01424 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
01425 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
01426 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
01427 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
01428 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
01429 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
01430 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
01431 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
01432 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
01433 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
01434 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
01435 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
01436 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
01437 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
01438 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
01439 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
01440 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
01441 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
01442 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
01443 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
01444 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
01445 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
01446 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
01447 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
01448 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
01449 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
01450 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
01451 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
01452 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
01453 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
01454 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
01456 /* Bit fields for CMU HFPERCLKDIV */
01457 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
01458 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
01459 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
01460 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
01461 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
01462 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
01463 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
01464 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
01465 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
01466 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
01467 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
01468 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
01469 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
01470 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
01471 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
01472 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
01473 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
01474 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
01475 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
01476 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
01477 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
01478 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
01479 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
01480 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
01481 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
01482 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
01483 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
01484 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
01485 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
01486 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
01487 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
01489 /* Bit fields for CMU HFRCOCTRL */
01490 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
01491 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
01492 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
01493 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
01494 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
01495 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
01496 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
01497 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
01498 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
01499 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
01500 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
01501 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
01502 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
01503 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
01504 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
01505 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
01506 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
01507 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
01508 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
01509 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
01510 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
01511 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
01512 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
01513 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
01515 /* Bit fields for CMU LFRCOCTRL */
01516 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
01517 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
01518 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
01519 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
01520 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
01521 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
01523 /* Bit fields for CMU AUXHFRCOCTRL */
01524 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
01525 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
01526 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
01527 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
01528 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
01529 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
01530 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
01531 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
01532 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
01533 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
01534 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
01535 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
01536 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
01537 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
01538 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
01539 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
01540 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
01541 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
01542 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
01543 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
01545 /* Bit fields for CMU CALCTRL */
01546 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
01547 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
01548 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
01549 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
01550 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
01551 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
01552 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
01553 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
01554 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
01555 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
01556 #define _CMU_CALCTRL_UPSEL_USHFRCO                  0x00000005UL                         
01557 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
01558 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
01559 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
01560 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
01561 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
01562 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
01563 #define CMU_CALCTRL_UPSEL_USHFRCO                   (_CMU_CALCTRL_UPSEL_USHFRCO << 0)    
01564 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
01565 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
01566 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
01567 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
01568 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
01569 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
01570 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
01571 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
01572 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
01573 #define _CMU_CALCTRL_DOWNSEL_USHFRCO                0x00000006UL                         
01574 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
01575 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
01576 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
01577 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
01578 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
01579 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
01580 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
01581 #define CMU_CALCTRL_DOWNSEL_USHFRCO                 (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3)  
01582 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
01583 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
01584 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
01585 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
01586 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
01588 /* Bit fields for CMU CALCNT */
01589 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
01590 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
01591 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
01592 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
01593 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
01594 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
01596 /* Bit fields for CMU OSCENCMD */
01597 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
01598 #define _CMU_OSCENCMD_MASK                          0x00000FFFUL                             
01599 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
01600 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
01601 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
01602 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
01603 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
01604 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
01605 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
01606 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
01607 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
01608 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
01609 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
01610 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
01611 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
01612 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
01613 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
01614 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
01615 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
01616 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
01617 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
01618 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
01619 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
01620 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
01621 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
01622 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
01623 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
01624 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
01625 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
01626 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
01627 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
01628 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
01629 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
01630 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
01631 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
01632 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
01633 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
01634 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
01635 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
01636 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
01637 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
01638 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
01639 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
01640 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
01641 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
01642 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
01643 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
01644 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
01645 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
01646 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
01647 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
01648 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
01649 #define CMU_OSCENCMD_USHFRCOEN                      (0x1UL << 10)                            
01650 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT               10                                       
01651 #define _CMU_OSCENCMD_USHFRCOEN_MASK                0x400UL                                  
01652 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT             0x00000000UL                             
01653 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT              (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10)  
01654 #define CMU_OSCENCMD_USHFRCODIS                     (0x1UL << 11)                            
01655 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT              11                                       
01656 #define _CMU_OSCENCMD_USHFRCODIS_MASK               0x800UL                                  
01657 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT            0x00000000UL                             
01658 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT             (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11) 
01660 /* Bit fields for CMU CMD */
01661 #define _CMU_CMD_RESETVALUE                         0x00000000UL                         
01662 #define _CMU_CMD_MASK                               0x0000001FUL                         
01663 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                    
01664 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                                
01665 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                         
01666 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                         
01667 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                         
01668 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                         
01669 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                         
01670 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2               0x00000005UL                         
01671 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0)     
01672 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)       
01673 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)        
01674 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)       
01675 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)        
01676 #define CMU_CMD_HFCLKSEL_USHFRCODIV2                (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0) 
01677 #define CMU_CMD_CALSTART                            (0x1UL << 3)                         
01678 #define _CMU_CMD_CALSTART_SHIFT                     3                                    
01679 #define _CMU_CMD_CALSTART_MASK                      0x8UL                                
01680 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                         
01681 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3)     
01682 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                         
01683 #define _CMU_CMD_CALSTOP_SHIFT                      4                                    
01684 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                               
01685 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                         
01686 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)      
01688 /* Bit fields for CMU LFCLKSEL */
01689 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000015UL                             
01690 #define _CMU_LFCLKSEL_MASK                          0x0011003FUL                             
01691 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
01692 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
01693 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
01694 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
01695 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
01696 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
01697 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
01698 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
01699 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
01700 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
01701 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
01702 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
01703 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
01704 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
01705 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
01706 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
01707 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
01708 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
01709 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
01710 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
01711 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
01712 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
01713 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
01714 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
01715 #define _CMU_LFCLKSEL_LFC_SHIFT                     4                                        
01716 #define _CMU_LFCLKSEL_LFC_MASK                      0x30UL                                   
01717 #define _CMU_LFCLKSEL_LFC_DISABLED                  0x00000000UL                             
01718 #define _CMU_LFCLKSEL_LFC_DEFAULT                   0x00000001UL                             
01719 #define _CMU_LFCLKSEL_LFC_LFRCO                     0x00000001UL                             
01720 #define _CMU_LFCLKSEL_LFC_LFXO                      0x00000002UL                             
01721 #define CMU_LFCLKSEL_LFC_DISABLED                   (_CMU_LFCLKSEL_LFC_DISABLED << 4)        
01722 #define CMU_LFCLKSEL_LFC_DEFAULT                    (_CMU_LFCLKSEL_LFC_DEFAULT << 4)         
01723 #define CMU_LFCLKSEL_LFC_LFRCO                      (_CMU_LFCLKSEL_LFC_LFRCO << 4)           
01724 #define CMU_LFCLKSEL_LFC_LFXO                       (_CMU_LFCLKSEL_LFC_LFXO << 4)            
01725 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
01726 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
01727 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
01728 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
01729 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
01730 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
01731 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
01732 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
01733 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
01734 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
01735 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
01736 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
01737 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
01738 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
01739 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
01740 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
01741 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
01742 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
01744 /* Bit fields for CMU STATUS */
01745 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                               
01746 #define _CMU_STATUS_MASK                            0x04E07FFFUL                               
01747 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                               
01748 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                          
01749 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                      
01750 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                               
01751 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)        
01752 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                               
01753 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                          
01754 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                      
01755 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                               
01756 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)        
01757 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                               
01758 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                          
01759 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                      
01760 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                               
01761 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)         
01762 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                               
01763 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                          
01764 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                      
01765 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                               
01766 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)         
01767 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                               
01768 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                          
01769 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                     
01770 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                               
01771 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)     
01772 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                               
01773 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                          
01774 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                     
01775 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                               
01776 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)     
01777 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                               
01778 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                          
01779 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                     
01780 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                               
01781 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)        
01782 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                               
01783 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                          
01784 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                     
01785 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                               
01786 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)        
01787 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                               
01788 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                          
01789 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                    
01790 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                               
01791 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)         
01792 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                               
01793 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                          
01794 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                    
01795 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                               
01796 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)         
01797 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                              
01798 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                         
01799 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                    
01800 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                               
01801 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)       
01802 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                              
01803 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                         
01804 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                    
01805 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                               
01806 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)        
01807 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                              
01808 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                         
01809 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                                   
01810 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                               
01811 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)       
01812 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                              
01813 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                         
01814 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                                   
01815 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                               
01816 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)        
01817 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                              
01818 #define _CMU_STATUS_CALBSY_SHIFT                    14                                         
01819 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                                   
01820 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                               
01821 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)         
01822 #define CMU_STATUS_USHFRCOENS                       (0x1UL << 21)                              
01823 #define _CMU_STATUS_USHFRCOENS_SHIFT                21                                         
01824 #define _CMU_STATUS_USHFRCOENS_MASK                 0x200000UL                                 
01825 #define _CMU_STATUS_USHFRCOENS_DEFAULT              0x00000000UL                               
01826 #define CMU_STATUS_USHFRCOENS_DEFAULT               (_CMU_STATUS_USHFRCOENS_DEFAULT << 21)     
01827 #define CMU_STATUS_USHFRCORDY                       (0x1UL << 22)                              
01828 #define _CMU_STATUS_USHFRCORDY_SHIFT                22                                         
01829 #define _CMU_STATUS_USHFRCORDY_MASK                 0x400000UL                                 
01830 #define _CMU_STATUS_USHFRCORDY_DEFAULT              0x00000000UL                               
01831 #define CMU_STATUS_USHFRCORDY_DEFAULT               (_CMU_STATUS_USHFRCORDY_DEFAULT << 22)     
01832 #define CMU_STATUS_USHFRCOSUSPEND                   (0x1UL << 23)                              
01833 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT            23                                         
01834 #define _CMU_STATUS_USHFRCOSUSPEND_MASK             0x800000UL                                 
01835 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT          0x00000000UL                               
01836 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT           (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23) 
01837 #define CMU_STATUS_USHFRCODIV2SEL                   (0x1UL << 26)                              
01838 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT            26                                         
01839 #define _CMU_STATUS_USHFRCODIV2SEL_MASK             0x4000000UL                                
01840 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT          0x00000000UL                               
01841 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT           (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26) 
01843 /* Bit fields for CMU IF */
01844 #define _CMU_IF_RESETVALUE                          0x00000001UL                       
01845 #define _CMU_IF_MASK                                0x0000017FUL                       
01846 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                       
01847 #define _CMU_IF_HFRCORDY_SHIFT                      0                                  
01848 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                              
01849 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                       
01850 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)    
01851 #define CMU_IF_HFXORDY                              (0x1UL << 1)                       
01852 #define _CMU_IF_HFXORDY_SHIFT                       1                                  
01853 #define _CMU_IF_HFXORDY_MASK                        0x2UL                              
01854 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                       
01855 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)     
01856 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                       
01857 #define _CMU_IF_LFRCORDY_SHIFT                      2                                  
01858 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                              
01859 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                       
01860 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)    
01861 #define CMU_IF_LFXORDY                              (0x1UL << 3)                       
01862 #define _CMU_IF_LFXORDY_SHIFT                       3                                  
01863 #define _CMU_IF_LFXORDY_MASK                        0x8UL                              
01864 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                       
01865 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)     
01866 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                       
01867 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                  
01868 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                             
01869 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                       
01870 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
01871 #define CMU_IF_CALRDY                               (0x1UL << 5)                       
01872 #define _CMU_IF_CALRDY_SHIFT                        5                                  
01873 #define _CMU_IF_CALRDY_MASK                         0x20UL                             
01874 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                       
01875 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)      
01876 #define CMU_IF_CALOF                                (0x1UL << 6)                       
01877 #define _CMU_IF_CALOF_SHIFT                         6                                  
01878 #define _CMU_IF_CALOF_MASK                          0x40UL                             
01879 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                       
01880 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)       
01881 #define CMU_IF_USHFRCORDY                           (0x1UL << 8)                       
01882 #define _CMU_IF_USHFRCORDY_SHIFT                    8                                  
01883 #define _CMU_IF_USHFRCORDY_MASK                     0x100UL                            
01884 #define _CMU_IF_USHFRCORDY_DEFAULT                  0x00000000UL                       
01885 #define CMU_IF_USHFRCORDY_DEFAULT                   (_CMU_IF_USHFRCORDY_DEFAULT << 8)  
01887 /* Bit fields for CMU IFS */
01888 #define _CMU_IFS_RESETVALUE                         0x00000000UL                        
01889 #define _CMU_IFS_MASK                               0x0000017FUL                        
01890 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                        
01891 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                   
01892 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                               
01893 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                        
01894 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
01895 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                        
01896 #define _CMU_IFS_HFXORDY_SHIFT                      1                                   
01897 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                               
01898 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                        
01899 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)     
01900 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                        
01901 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                   
01902 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                               
01903 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                        
01904 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
01905 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                        
01906 #define _CMU_IFS_LFXORDY_SHIFT                      3                                   
01907 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                               
01908 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                        
01909 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)     
01910 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                        
01911 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                   
01912 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                              
01913 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01914 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
01915 #define CMU_IFS_CALRDY                              (0x1UL << 5)                        
01916 #define _CMU_IFS_CALRDY_SHIFT                       5                                   
01917 #define _CMU_IFS_CALRDY_MASK                        0x20UL                              
01918 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                        
01919 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)      
01920 #define CMU_IFS_CALOF                               (0x1UL << 6)                        
01921 #define _CMU_IFS_CALOF_SHIFT                        6                                   
01922 #define _CMU_IFS_CALOF_MASK                         0x40UL                              
01923 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                        
01924 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)       
01925 #define CMU_IFS_USHFRCORDY                          (0x1UL << 8)                        
01926 #define _CMU_IFS_USHFRCORDY_SHIFT                   8                                   
01927 #define _CMU_IFS_USHFRCORDY_MASK                    0x100UL                             
01928 #define _CMU_IFS_USHFRCORDY_DEFAULT                 0x00000000UL                        
01929 #define CMU_IFS_USHFRCORDY_DEFAULT                  (_CMU_IFS_USHFRCORDY_DEFAULT << 8)  
01931 /* Bit fields for CMU IFC */
01932 #define _CMU_IFC_RESETVALUE                         0x00000000UL                        
01933 #define _CMU_IFC_MASK                               0x0000017FUL                        
01934 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                        
01935 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                   
01936 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                               
01937 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                        
01938 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
01939 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                        
01940 #define _CMU_IFC_HFXORDY_SHIFT                      1                                   
01941 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                               
01942 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                        
01943 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)     
01944 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                        
01945 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                   
01946 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                               
01947 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                        
01948 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
01949 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                        
01950 #define _CMU_IFC_LFXORDY_SHIFT                      3                                   
01951 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                               
01952 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                        
01953 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)     
01954 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                        
01955 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                   
01956 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                              
01957 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01958 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
01959 #define CMU_IFC_CALRDY                              (0x1UL << 5)                        
01960 #define _CMU_IFC_CALRDY_SHIFT                       5                                   
01961 #define _CMU_IFC_CALRDY_MASK                        0x20UL                              
01962 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                        
01963 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)      
01964 #define CMU_IFC_CALOF                               (0x1UL << 6)                        
01965 #define _CMU_IFC_CALOF_SHIFT                        6                                   
01966 #define _CMU_IFC_CALOF_MASK                         0x40UL                              
01967 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                        
01968 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)       
01969 #define CMU_IFC_USHFRCORDY                          (0x1UL << 8)                        
01970 #define _CMU_IFC_USHFRCORDY_SHIFT                   8                                   
01971 #define _CMU_IFC_USHFRCORDY_MASK                    0x100UL                             
01972 #define _CMU_IFC_USHFRCORDY_DEFAULT                 0x00000000UL                        
01973 #define CMU_IFC_USHFRCORDY_DEFAULT                  (_CMU_IFC_USHFRCORDY_DEFAULT << 8)  
01975 /* Bit fields for CMU IEN */
01976 #define _CMU_IEN_RESETVALUE                         0x00000000UL                        
01977 #define _CMU_IEN_MASK                               0x0000017FUL                        
01978 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                        
01979 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                   
01980 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                               
01981 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                        
01982 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
01983 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                        
01984 #define _CMU_IEN_HFXORDY_SHIFT                      1                                   
01985 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                               
01986 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                        
01987 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)     
01988 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                        
01989 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                   
01990 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                               
01991 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                        
01992 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
01993 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                        
01994 #define _CMU_IEN_LFXORDY_SHIFT                      3                                   
01995 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                               
01996 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                        
01997 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)     
01998 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                        
01999 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                   
02000 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                              
02001 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                        
02002 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
02003 #define CMU_IEN_CALRDY                              (0x1UL << 5)                        
02004 #define _CMU_IEN_CALRDY_SHIFT                       5                                   
02005 #define _CMU_IEN_CALRDY_MASK                        0x20UL                              
02006 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                        
02007 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)      
02008 #define CMU_IEN_CALOF                               (0x1UL << 6)                        
02009 #define _CMU_IEN_CALOF_SHIFT                        6                                   
02010 #define _CMU_IEN_CALOF_MASK                         0x40UL                              
02011 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                        
02012 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)       
02013 #define CMU_IEN_USHFRCORDY                          (0x1UL << 8)                        
02014 #define _CMU_IEN_USHFRCORDY_SHIFT                   8                                   
02015 #define _CMU_IEN_USHFRCORDY_MASK                    0x100UL                             
02016 #define _CMU_IEN_USHFRCORDY_DEFAULT                 0x00000000UL                        
02017 #define CMU_IEN_USHFRCORDY_DEFAULT                  (_CMU_IEN_USHFRCORDY_DEFAULT << 8)  
02019 /* Bit fields for CMU HFCORECLKEN0 */
02020 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                         
02021 #define _CMU_HFCORECLKEN0_MASK                      0x00000006UL                         
02022 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 1)                         
02023 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 1                                    
02024 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x2UL                                
02025 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                         
02026 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) 
02027 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 2)                         
02028 #define _CMU_HFCORECLKEN0_LE_SHIFT                  2                                    
02029 #define _CMU_HFCORECLKEN0_LE_MASK                   0x4UL                                
02030 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                         
02031 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)  
02033 /* Bit fields for CMU HFPERCLKEN0 */
02034 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
02035 #define _CMU_HFPERCLKEN0_MASK                       0x00000B7FUL                           
02036 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 0)                           
02037 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               0                                      
02038 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x1UL                                  
02039 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
02040 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) 
02041 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 1)                           
02042 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               1                                      
02043 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x2UL                                  
02044 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
02045 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) 
02046 #define CMU_HFPERCLKEN0_TIMER2                      (0x1UL << 2)                           
02047 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT               2                                      
02048 #define _CMU_HFPERCLKEN0_TIMER2_MASK                0x4UL                                  
02049 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT             0x00000000UL                           
02050 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT              (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2) 
02051 #define CMU_HFPERCLKEN0_USART0                      (0x1UL << 3)                           
02052 #define _CMU_HFPERCLKEN0_USART0_SHIFT               3                                      
02053 #define _CMU_HFPERCLKEN0_USART0_MASK                0x8UL                                  
02054 #define _CMU_HFPERCLKEN0_USART0_DEFAULT             0x00000000UL                           
02055 #define CMU_HFPERCLKEN0_USART0_DEFAULT              (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3) 
02056 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 4)                           
02057 #define _CMU_HFPERCLKEN0_USART1_SHIFT               4                                      
02058 #define _CMU_HFPERCLKEN0_USART1_MASK                0x10UL                                 
02059 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
02060 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4) 
02061 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 5)                           
02062 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                5                                      
02063 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x20UL                                 
02064 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
02065 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5)  
02066 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 6)                           
02067 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  6                                      
02068 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x40UL                                 
02069 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
02070 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6)    
02071 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 8)                           
02072 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 8                                      
02073 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x100UL                                
02074 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
02075 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8)   
02076 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 9)                           
02077 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 9                                      
02078 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x200UL                                
02079 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
02080 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9)   
02081 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
02082 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
02083 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
02084 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
02085 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
02087 /* Bit fields for CMU SYNCBUSY */
02088 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
02089 #define _CMU_SYNCBUSY_MASK                          0x00000155UL                           
02090 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
02091 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
02092 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
02093 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
02094 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
02095 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
02096 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
02097 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
02098 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
02099 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
02100 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
02101 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
02102 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
02103 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
02104 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
02105 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
02106 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
02107 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
02108 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
02109 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
02110 #define CMU_SYNCBUSY_LFCCLKEN0                      (0x1UL << 8)                           
02111 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT               8                                      
02112 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK                0x100UL                                
02113 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT             0x00000000UL                           
02114 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8) 
02116 /* Bit fields for CMU FREEZE */
02117 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
02118 #define _CMU_FREEZE_MASK                            0x00000001UL                         
02119 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
02120 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
02121 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
02122 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
02123 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
02124 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
02125 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
02126 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
02127 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
02129 /* Bit fields for CMU LFACLKEN0 */
02130 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                      
02131 #define _CMU_LFACLKEN0_MASK                         0x00000001UL                      
02132 #define CMU_LFACLKEN0_RTC                           (0x1UL << 0)                      
02133 #define _CMU_LFACLKEN0_RTC_SHIFT                    0                                 
02134 #define _CMU_LFACLKEN0_RTC_MASK                     0x1UL                             
02135 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                      
02136 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 0) 
02138 /* Bit fields for CMU LFBCLKEN0 */
02139 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
02140 #define _CMU_LFBCLKEN0_MASK                         0x00000001UL                          
02141 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
02142 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
02143 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
02144 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
02145 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
02147 /* Bit fields for CMU LFCCLKEN0 */
02148 #define _CMU_LFCCLKEN0_RESETVALUE                   0x00000000UL                        
02149 #define _CMU_LFCCLKEN0_MASK                         0x00000001UL                        
02150 #define CMU_LFCCLKEN0_USBLE                         (0x1UL << 0)                        
02151 #define _CMU_LFCCLKEN0_USBLE_SHIFT                  0                                   
02152 #define _CMU_LFCCLKEN0_USBLE_MASK                   0x1UL                               
02153 #define _CMU_LFCCLKEN0_USBLE_DEFAULT                0x00000000UL                        
02154 #define CMU_LFCCLKEN0_USBLE_DEFAULT                 (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0) 
02156 /* Bit fields for CMU LFAPRESC0 */
02157 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                       
02158 #define _CMU_LFAPRESC0_MASK                         0x0000000FUL                       
02159 #define _CMU_LFAPRESC0_RTC_SHIFT                    0                                  
02160 #define _CMU_LFAPRESC0_RTC_MASK                     0xFUL                              
02161 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                       
02162 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                       
02163 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                       
02164 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                       
02165 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                       
02166 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                       
02167 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                       
02168 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                       
02169 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                       
02170 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                       
02171 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                       
02172 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                       
02173 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                       
02174 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                       
02175 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                       
02176 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                       
02177 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 0)     
02178 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 0)     
02179 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 0)     
02180 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 0)     
02181 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 0)    
02182 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 0)    
02183 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 0)    
02184 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 0)   
02185 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 0)   
02186 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 0)   
02187 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 0)  
02188 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 0)  
02189 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 0)  
02190 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 0)  
02191 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 0) 
02192 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 0) 
02194 /* Bit fields for CMU LFBPRESC0 */
02195 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
02196 #define _CMU_LFBPRESC0_MASK                         0x00000003UL                       
02197 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
02198 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
02199 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
02200 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
02201 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
02202 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
02203 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
02204 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
02205 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
02206 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
02208 /* Bit fields for CMU PCNTCTRL */
02209 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
02210 #define _CMU_PCNTCTRL_MASK                          0x00000003UL                             
02211 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
02212 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
02213 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
02214 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
02215 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
02216 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
02217 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
02218 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
02219 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
02220 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
02221 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
02222 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
02223 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
02224 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
02226 /* Bit fields for CMU ROUTE */
02227 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
02228 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
02229 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
02230 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
02231 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
02232 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
02233 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
02234 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
02235 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
02236 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
02237 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
02238 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
02239 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
02240 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
02241 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
02242 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
02243 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
02244 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
02245 #define _CMU_ROUTE_LOCATION_LOC3                    0x00000003UL                         
02246 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
02247 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
02248 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
02249 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
02250 #define CMU_ROUTE_LOCATION_LOC3                     (_CMU_ROUTE_LOCATION_LOC3 << 2)      
02252 /* Bit fields for CMU LOCK */
02253 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
02254 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
02255 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
02256 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
02257 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
02258 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
02259 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
02260 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
02261 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
02262 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
02263 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
02264 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
02265 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
02266 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
02268 /* Bit fields for CMU USBCRCTRL */
02269 #define _CMU_USBCRCTRL_RESETVALUE                   0x00000000UL                         
02270 #define _CMU_USBCRCTRL_MASK                         0x00000003UL                         
02271 #define CMU_USBCRCTRL_EN                            (0x1UL << 0)                         
02272 #define _CMU_USBCRCTRL_EN_SHIFT                     0                                    
02273 #define _CMU_USBCRCTRL_EN_MASK                      0x1UL                                
02274 #define _CMU_USBCRCTRL_EN_DEFAULT                   0x00000000UL                         
02275 #define CMU_USBCRCTRL_EN_DEFAULT                    (_CMU_USBCRCTRL_EN_DEFAULT << 0)     
02276 #define CMU_USBCRCTRL_LSMODE                        (0x1UL << 1)                         
02277 #define _CMU_USBCRCTRL_LSMODE_SHIFT                 1                                    
02278 #define _CMU_USBCRCTRL_LSMODE_MASK                  0x2UL                                
02279 #define _CMU_USBCRCTRL_LSMODE_DEFAULT               0x00000000UL                         
02280 #define CMU_USBCRCTRL_LSMODE_DEFAULT                (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1) 
02282 /* Bit fields for CMU USHFRCOCTRL */
02283 #define _CMU_USHFRCOCTRL_RESETVALUE                 0x000FF040UL                             
02284 #define _CMU_USHFRCOCTRL_MASK                       0x000FF37FUL                             
02285 #define _CMU_USHFRCOCTRL_TUNING_SHIFT               0                                        
02286 #define _CMU_USHFRCOCTRL_TUNING_MASK                0x7FUL                                   
02287 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT             0x00000040UL                             
02288 #define CMU_USHFRCOCTRL_TUNING_DEFAULT              (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0)   
02289 #define CMU_USHFRCOCTRL_DITHEN                      (0x1UL << 8)                             
02290 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT               8                                        
02291 #define _CMU_USHFRCOCTRL_DITHEN_MASK                0x100UL                                  
02292 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT             0x00000000UL                             
02293 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT              (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8)   
02294 #define CMU_USHFRCOCTRL_SUSPEND                     (0x1UL << 9)                             
02295 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT              9                                        
02296 #define _CMU_USHFRCOCTRL_SUSPEND_MASK               0x200UL                                  
02297 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT            0x00000000UL                             
02298 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT             (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9)  
02299 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT              12                                       
02300 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK               0xFF000UL                                
02301 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT            0x000000FFUL                             
02302 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT             (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12) 
02304 /* Bit fields for CMU USHFRCOTUNE */
02305 #define _CMU_USHFRCOTUNE_RESETVALUE                 0x00000020UL                               
02306 #define _CMU_USHFRCOTUNE_MASK                       0x0000003FUL                               
02307 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT           0                                          
02308 #define _CMU_USHFRCOTUNE_FINETUNING_MASK            0x3FUL                                     
02309 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT         0x00000020UL                               
02310 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT          (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0) 
02312 /* Bit fields for CMU USHFRCOCONF */
02313 #define _CMU_USHFRCOCONF_RESETVALUE                 0x00000001UL                                   
02314 #define _CMU_USHFRCOCONF_MASK                       0x00000017UL                                   
02315 #define _CMU_USHFRCOCONF_BAND_SHIFT                 0                                              
02316 #define _CMU_USHFRCOCONF_BAND_MASK                  0x7UL                                          
02317 #define _CMU_USHFRCOCONF_BAND_DEFAULT               0x00000001UL                                   
02318 #define _CMU_USHFRCOCONF_BAND_48MHZ                 0x00000001UL                                   
02319 #define _CMU_USHFRCOCONF_BAND_24MHZ                 0x00000003UL                                   
02320 #define CMU_USHFRCOCONF_BAND_DEFAULT                (_CMU_USHFRCOCONF_BAND_DEFAULT << 0)           
02321 #define CMU_USHFRCOCONF_BAND_48MHZ                  (_CMU_USHFRCOCONF_BAND_48MHZ << 0)             
02322 #define CMU_USHFRCOCONF_BAND_24MHZ                  (_CMU_USHFRCOCONF_BAND_24MHZ << 0)             
02323 #define CMU_USHFRCOCONF_USHFRCODIV2DIS              (0x1UL << 4)                                   
02324 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT       4                                              
02325 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK        0x10UL                                         
02326 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT     0x00000000UL                                   
02327 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT      (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4) 
02331 /**************************************************************************/
02336 /* Bit fields for PRS SWPULSE */
02337 #define _PRS_SWPULSE_RESETVALUE              0x00000000UL                         
02338 #define _PRS_SWPULSE_MASK                    0x0000003FUL                         
02339 #define PRS_SWPULSE_CH0PULSE                 (0x1UL << 0)                         
02340 #define _PRS_SWPULSE_CH0PULSE_SHIFT          0                                    
02341 #define _PRS_SWPULSE_CH0PULSE_MASK           0x1UL                                
02342 #define _PRS_SWPULSE_CH0PULSE_DEFAULT        0x00000000UL                         
02343 #define PRS_SWPULSE_CH0PULSE_DEFAULT         (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) 
02344 #define PRS_SWPULSE_CH1PULSE                 (0x1UL << 1)                         
02345 #define _PRS_SWPULSE_CH1PULSE_SHIFT          1                                    
02346 #define _PRS_SWPULSE_CH1PULSE_MASK           0x2UL                                
02347 #define _PRS_SWPULSE_CH1PULSE_DEFAULT        0x00000000UL                         
02348 #define PRS_SWPULSE_CH1PULSE_DEFAULT         (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) 
02349 #define PRS_SWPULSE_CH2PULSE                 (0x1UL << 2)                         
02350 #define _PRS_SWPULSE_CH2PULSE_SHIFT          2                                    
02351 #define _PRS_SWPULSE_CH2PULSE_MASK           0x4UL                                
02352 #define _PRS_SWPULSE_CH2PULSE_DEFAULT        0x00000000UL                         
02353 #define PRS_SWPULSE_CH2PULSE_DEFAULT         (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) 
02354 #define PRS_SWPULSE_CH3PULSE                 (0x1UL << 3)                         
02355 #define _PRS_SWPULSE_CH3PULSE_SHIFT          3                                    
02356 #define _PRS_SWPULSE_CH3PULSE_MASK           0x8UL                                
02357 #define _PRS_SWPULSE_CH3PULSE_DEFAULT        0x00000000UL                         
02358 #define PRS_SWPULSE_CH3PULSE_DEFAULT         (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) 
02359 #define PRS_SWPULSE_CH4PULSE                 (0x1UL << 4)                         
02360 #define _PRS_SWPULSE_CH4PULSE_SHIFT          4                                    
02361 #define _PRS_SWPULSE_CH4PULSE_MASK           0x10UL                               
02362 #define _PRS_SWPULSE_CH4PULSE_DEFAULT        0x00000000UL                         
02363 #define PRS_SWPULSE_CH4PULSE_DEFAULT         (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) 
02364 #define PRS_SWPULSE_CH5PULSE                 (0x1UL << 5)                         
02365 #define _PRS_SWPULSE_CH5PULSE_SHIFT          5                                    
02366 #define _PRS_SWPULSE_CH5PULSE_MASK           0x20UL                               
02367 #define _PRS_SWPULSE_CH5PULSE_DEFAULT        0x00000000UL                         
02368 #define PRS_SWPULSE_CH5PULSE_DEFAULT         (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) 
02370 /* Bit fields for PRS SWLEVEL */
02371 #define _PRS_SWLEVEL_RESETVALUE              0x00000000UL                         
02372 #define _PRS_SWLEVEL_MASK                    0x0000003FUL                         
02373 #define PRS_SWLEVEL_CH0LEVEL                 (0x1UL << 0)                         
02374 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT          0                                    
02375 #define _PRS_SWLEVEL_CH0LEVEL_MASK           0x1UL                                
02376 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT        0x00000000UL                         
02377 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT         (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) 
02378 #define PRS_SWLEVEL_CH1LEVEL                 (0x1UL << 1)                         
02379 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT          1                                    
02380 #define _PRS_SWLEVEL_CH1LEVEL_MASK           0x2UL                                
02381 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT        0x00000000UL                         
02382 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT         (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) 
02383 #define PRS_SWLEVEL_CH2LEVEL                 (0x1UL << 2)                         
02384 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT          2                                    
02385 #define _PRS_SWLEVEL_CH2LEVEL_MASK           0x4UL                                
02386 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT        0x00000000UL                         
02387 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT         (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) 
02388 #define PRS_SWLEVEL_CH3LEVEL                 (0x1UL << 3)                         
02389 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT          3                                    
02390 #define _PRS_SWLEVEL_CH3LEVEL_MASK           0x8UL                                
02391 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT        0x00000000UL                         
02392 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT         (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) 
02393 #define PRS_SWLEVEL_CH4LEVEL                 (0x1UL << 4)                         
02394 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT          4                                    
02395 #define _PRS_SWLEVEL_CH4LEVEL_MASK           0x10UL                               
02396 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT        0x00000000UL                         
02397 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT         (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) 
02398 #define PRS_SWLEVEL_CH5LEVEL                 (0x1UL << 5)                         
02399 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT          5                                    
02400 #define _PRS_SWLEVEL_CH5LEVEL_MASK           0x20UL                               
02401 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT        0x00000000UL                         
02402 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT         (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) 
02404 /* Bit fields for PRS ROUTE */
02405 #define _PRS_ROUTE_RESETVALUE                0x00000000UL                       
02406 #define _PRS_ROUTE_MASK                      0x0000070FUL                       
02407 #define PRS_ROUTE_CH0PEN                     (0x1UL << 0)                       
02408 #define _PRS_ROUTE_CH0PEN_SHIFT              0                                  
02409 #define _PRS_ROUTE_CH0PEN_MASK               0x1UL                              
02410 #define _PRS_ROUTE_CH0PEN_DEFAULT            0x00000000UL                       
02411 #define PRS_ROUTE_CH0PEN_DEFAULT             (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   
02412 #define PRS_ROUTE_CH1PEN                     (0x1UL << 1)                       
02413 #define _PRS_ROUTE_CH1PEN_SHIFT              1                                  
02414 #define _PRS_ROUTE_CH1PEN_MASK               0x2UL                              
02415 #define _PRS_ROUTE_CH1PEN_DEFAULT            0x00000000UL                       
02416 #define PRS_ROUTE_CH1PEN_DEFAULT             (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   
02417 #define PRS_ROUTE_CH2PEN                     (0x1UL << 2)                       
02418 #define _PRS_ROUTE_CH2PEN_SHIFT              2                                  
02419 #define _PRS_ROUTE_CH2PEN_MASK               0x4UL                              
02420 #define _PRS_ROUTE_CH2PEN_DEFAULT            0x00000000UL                       
02421 #define PRS_ROUTE_CH2PEN_DEFAULT             (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   
02422 #define PRS_ROUTE_CH3PEN                     (0x1UL << 3)                       
02423 #define _PRS_ROUTE_CH3PEN_SHIFT              3                                  
02424 #define _PRS_ROUTE_CH3PEN_MASK               0x8UL                              
02425 #define _PRS_ROUTE_CH3PEN_DEFAULT            0x00000000UL                       
02426 #define PRS_ROUTE_CH3PEN_DEFAULT             (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   
02427 #define _PRS_ROUTE_LOCATION_SHIFT            8                                  
02428 #define _PRS_ROUTE_LOCATION_MASK             0x700UL                            
02429 #define _PRS_ROUTE_LOCATION_LOC0             0x00000000UL                       
02430 #define _PRS_ROUTE_LOCATION_DEFAULT          0x00000000UL                       
02431 #define _PRS_ROUTE_LOCATION_LOC1             0x00000001UL                       
02432 #define _PRS_ROUTE_LOCATION_LOC2             0x00000002UL                       
02433 #define _PRS_ROUTE_LOCATION_LOC3             0x00000003UL                       
02434 #define PRS_ROUTE_LOCATION_LOC0              (_PRS_ROUTE_LOCATION_LOC0 << 8)    
02435 #define PRS_ROUTE_LOCATION_DEFAULT           (_PRS_ROUTE_LOCATION_DEFAULT << 8) 
02436 #define PRS_ROUTE_LOCATION_LOC1              (_PRS_ROUTE_LOCATION_LOC1 << 8)    
02437 #define PRS_ROUTE_LOCATION_LOC2              (_PRS_ROUTE_LOCATION_LOC2 << 8)    
02438 #define PRS_ROUTE_LOCATION_LOC3              (_PRS_ROUTE_LOCATION_LOC3 << 8)    
02440 /* Bit fields for PRS CH_CTRL */
02441 #define _PRS_CH_CTRL_RESETVALUE              0x00000000UL                             
02442 #define _PRS_CH_CTRL_MASK                    0x133F0007UL                             
02443 #define _PRS_CH_CTRL_SIGSEL_SHIFT            0                                        
02444 #define _PRS_CH_CTRL_SIGSEL_MASK             0x7UL                                    
02445 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT          0x00000000UL                             
02446 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT         0x00000000UL                             
02447 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX       0x00000000UL                             
02448 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX       0x00000000UL                             
02449 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF         0x00000000UL                             
02450 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF         0x00000000UL                             
02451 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF         0x00000000UL                             
02452 #define _PRS_CH_CTRL_SIGSEL_RTCOF            0x00000000UL                             
02453 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0         0x00000000UL                             
02454 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8         0x00000000UL                             
02455 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC         0x00000000UL                             
02456 #define _PRS_CH_CTRL_SIGSEL_USART0TXC        0x00000001UL                             
02457 #define _PRS_CH_CTRL_SIGSEL_USART1TXC        0x00000001UL                             
02458 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF         0x00000001UL                             
02459 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF         0x00000001UL                             
02460 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF         0x00000001UL                             
02461 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0         0x00000001UL                             
02462 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1         0x00000001UL                             
02463 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9         0x00000001UL                             
02464 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV    0x00000002UL                             
02465 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV    0x00000002UL                             
02466 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0        0x00000002UL                             
02467 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0        0x00000002UL                             
02468 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0        0x00000002UL                             
02469 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1         0x00000002UL                             
02470 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2         0x00000002UL                             
02471 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10        0x00000002UL                             
02472 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1        0x00000003UL                             
02473 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1        0x00000003UL                             
02474 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1        0x00000003UL                             
02475 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3         0x00000003UL                             
02476 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11        0x00000003UL                             
02477 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2        0x00000004UL                             
02478 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2        0x00000004UL                             
02479 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2        0x00000004UL                             
02480 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4         0x00000004UL                             
02481 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12        0x00000004UL                             
02482 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5         0x00000005UL                             
02483 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13        0x00000005UL                             
02484 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6         0x00000006UL                             
02485 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14        0x00000006UL                             
02486 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7         0x00000007UL                             
02487 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15        0x00000007UL                             
02488 #define PRS_CH_CTRL_SIGSEL_VCMPOUT           (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)       
02489 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT          (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)      
02490 #define PRS_CH_CTRL_SIGSEL_USART0IRTX        (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0)    
02491 #define PRS_CH_CTRL_SIGSEL_USART1IRTX        (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0)    
02492 #define PRS_CH_CTRL_SIGSEL_TIMER0UF          (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)      
02493 #define PRS_CH_CTRL_SIGSEL_TIMER1UF          (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)      
02494 #define PRS_CH_CTRL_SIGSEL_TIMER2UF          (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0)      
02495 #define PRS_CH_CTRL_SIGSEL_RTCOF             (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)         
02496 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0          (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)      
02497 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8          (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)      
02498 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC          (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)      
02499 #define PRS_CH_CTRL_SIGSEL_USART0TXC         (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0)     
02500 #define PRS_CH_CTRL_SIGSEL_USART1TXC         (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)     
02501 #define PRS_CH_CTRL_SIGSEL_TIMER0OF          (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)      
02502 #define PRS_CH_CTRL_SIGSEL_TIMER1OF          (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)      
02503 #define PRS_CH_CTRL_SIGSEL_TIMER2OF          (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0)      
02504 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0          (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)      
02505 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1          (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)      
02506 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9          (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)      
02507 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) 
02508 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 
02509 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0         (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)     
02510 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0         (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)     
02511 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0         (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0)     
02512 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1          (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)      
02513 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2          (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)      
02514 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10         (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)     
02515 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1         (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)     
02516 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1         (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)     
02517 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1         (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0)     
02518 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3          (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)      
02519 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11         (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)     
02520 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2         (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)     
02521 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2         (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)     
02522 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2         (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0)     
02523 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4          (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)      
02524 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12         (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)     
02525 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5          (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)      
02526 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13         (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)     
02527 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6          (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)      
02528 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14         (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)     
02529 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7          (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)      
02530 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15         (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)     
02531 #define _PRS_CH_CTRL_SOURCESEL_SHIFT         16                                       
02532 #define _PRS_CH_CTRL_SOURCESEL_MASK          0x3F0000UL                               
02533 #define _PRS_CH_CTRL_SOURCESEL_NONE          0x00000000UL                             
02534 #define _PRS_CH_CTRL_SOURCESEL_VCMP          0x00000001UL                             
02535 #define _PRS_CH_CTRL_SOURCESEL_ACMP0         0x00000002UL                             
02536 #define _PRS_CH_CTRL_SOURCESEL_USART0        0x00000010UL                             
02537 #define _PRS_CH_CTRL_SOURCESEL_USART1        0x00000011UL                             
02538 #define _PRS_CH_CTRL_SOURCESEL_TIMER0        0x0000001CUL                             
02539 #define _PRS_CH_CTRL_SOURCESEL_TIMER1        0x0000001DUL                             
02540 #define _PRS_CH_CTRL_SOURCESEL_TIMER2        0x0000001EUL                             
02541 #define _PRS_CH_CTRL_SOURCESEL_RTC           0x00000028UL                             
02542 #define _PRS_CH_CTRL_SOURCESEL_GPIOL         0x00000030UL                             
02543 #define _PRS_CH_CTRL_SOURCESEL_GPIOH         0x00000031UL                             
02544 #define _PRS_CH_CTRL_SOURCESEL_PCNT0         0x00000036UL                             
02545 #define PRS_CH_CTRL_SOURCESEL_NONE           (_PRS_CH_CTRL_SOURCESEL_NONE << 16)      
02546 #define PRS_CH_CTRL_SOURCESEL_VCMP           (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)      
02547 #define PRS_CH_CTRL_SOURCESEL_ACMP0          (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)     
02548 #define PRS_CH_CTRL_SOURCESEL_USART0         (_PRS_CH_CTRL_SOURCESEL_USART0 << 16)    
02549 #define PRS_CH_CTRL_SOURCESEL_USART1         (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)    
02550 #define PRS_CH_CTRL_SOURCESEL_TIMER0         (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)    
02551 #define PRS_CH_CTRL_SOURCESEL_TIMER1         (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)    
02552 #define PRS_CH_CTRL_SOURCESEL_TIMER2         (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16)    
02553 #define PRS_CH_CTRL_SOURCESEL_RTC            (_PRS_CH_CTRL_SOURCESEL_RTC << 16)       
02554 #define PRS_CH_CTRL_SOURCESEL_GPIOL          (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)     
02555 #define PRS_CH_CTRL_SOURCESEL_GPIOH          (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)     
02556 #define PRS_CH_CTRL_SOURCESEL_PCNT0          (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16)     
02557 #define _PRS_CH_CTRL_EDSEL_SHIFT             24                                       
02558 #define _PRS_CH_CTRL_EDSEL_MASK              0x3000000UL                              
02559 #define _PRS_CH_CTRL_EDSEL_DEFAULT           0x00000000UL                             
02560 #define _PRS_CH_CTRL_EDSEL_OFF               0x00000000UL                             
02561 #define _PRS_CH_CTRL_EDSEL_POSEDGE           0x00000001UL                             
02562 #define _PRS_CH_CTRL_EDSEL_NEGEDGE           0x00000002UL                             
02563 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES         0x00000003UL                             
02564 #define PRS_CH_CTRL_EDSEL_DEFAULT            (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)       
02565 #define PRS_CH_CTRL_EDSEL_OFF                (_PRS_CH_CTRL_EDSEL_OFF << 24)           
02566 #define PRS_CH_CTRL_EDSEL_POSEDGE            (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)       
02567 #define PRS_CH_CTRL_EDSEL_NEGEDGE            (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)       
02568 #define PRS_CH_CTRL_EDSEL_BOTHEDGES          (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)     
02569 #define PRS_CH_CTRL_ASYNC                    (0x1UL << 28)                            
02570 #define _PRS_CH_CTRL_ASYNC_SHIFT             28                                       
02571 #define _PRS_CH_CTRL_ASYNC_MASK              0x10000000UL                             
02572 #define _PRS_CH_CTRL_ASYNC_DEFAULT           0x00000000UL                             
02573 #define PRS_CH_CTRL_ASYNC_DEFAULT            (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)       
02575 /* Bit fields for PRS TRACECTRL */
02576 #define _PRS_TRACECTRL_RESETVALUE            0x00000000UL                           
02577 #define _PRS_TRACECTRL_MASK                  0x00000F0FUL                           
02578 #define PRS_TRACECTRL_TSTARTEN               (0x1UL << 0)                           
02579 #define _PRS_TRACECTRL_TSTARTEN_SHIFT        0                                      
02580 #define _PRS_TRACECTRL_TSTARTEN_MASK         0x1UL                                  
02581 #define _PRS_TRACECTRL_TSTARTEN_DEFAULT      0x00000000UL                           
02582 #define PRS_TRACECTRL_TSTARTEN_DEFAULT       (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) 
02583 #define _PRS_TRACECTRL_TSTART_SHIFT          1                                      
02584 #define _PRS_TRACECTRL_TSTART_MASK           0xEUL                                  
02585 #define _PRS_TRACECTRL_TSTART_DEFAULT        0x00000000UL                           
02586 #define _PRS_TRACECTRL_TSTART_PRSCH0         0x00000000UL                           
02587 #define _PRS_TRACECTRL_TSTART_PRSCH1         0x00000001UL                           
02588 #define _PRS_TRACECTRL_TSTART_PRSCH2         0x00000002UL                           
02589 #define _PRS_TRACECTRL_TSTART_PRSCH3         0x00000003UL                           
02590 #define _PRS_TRACECTRL_TSTART_PRSCH4         0x00000004UL                           
02591 #define _PRS_TRACECTRL_TSTART_PRSCH5         0x00000005UL                           
02592 #define PRS_TRACECTRL_TSTART_DEFAULT         (_PRS_TRACECTRL_TSTART_DEFAULT << 1)   
02593 #define PRS_TRACECTRL_TSTART_PRSCH0          (_PRS_TRACECTRL_TSTART_PRSCH0 << 1)    
02594 #define PRS_TRACECTRL_TSTART_PRSCH1          (_PRS_TRACECTRL_TSTART_PRSCH1 << 1)    
02595 #define PRS_TRACECTRL_TSTART_PRSCH2          (_PRS_TRACECTRL_TSTART_PRSCH2 << 1)    
02596 #define PRS_TRACECTRL_TSTART_PRSCH3          (_PRS_TRACECTRL_TSTART_PRSCH3 << 1)    
02597 #define PRS_TRACECTRL_TSTART_PRSCH4          (_PRS_TRACECTRL_TSTART_PRSCH4 << 1)    
02598 #define PRS_TRACECTRL_TSTART_PRSCH5          (_PRS_TRACECTRL_TSTART_PRSCH5 << 1)    
02599 #define PRS_TRACECTRL_TSTOPEN                (0x1UL << 8)                           
02600 #define _PRS_TRACECTRL_TSTOPEN_SHIFT         8                                      
02601 #define _PRS_TRACECTRL_TSTOPEN_MASK          0x100UL                                
02602 #define _PRS_TRACECTRL_TSTOPEN_DEFAULT       0x00000000UL                           
02603 #define PRS_TRACECTRL_TSTOPEN_DEFAULT        (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8)  
02604 #define _PRS_TRACECTRL_TSTOP_SHIFT           9                                      
02605 #define _PRS_TRACECTRL_TSTOP_MASK            0xE00UL                                
02606 #define _PRS_TRACECTRL_TSTOP_DEFAULT         0x00000000UL                           
02607 #define _PRS_TRACECTRL_TSTOP_PRSCH0          0x00000000UL                           
02608 #define _PRS_TRACECTRL_TSTOP_PRSCH1          0x00000001UL                           
02609 #define _PRS_TRACECTRL_TSTOP_PRSCH2          0x00000002UL                           
02610 #define _PRS_TRACECTRL_TSTOP_PRSCH3          0x00000003UL                           
02611 #define _PRS_TRACECTRL_TSTOP_PRSCH4          0x00000004UL                           
02612 #define _PRS_TRACECTRL_TSTOP_PRSCH5          0x00000005UL                           
02613 #define PRS_TRACECTRL_TSTOP_DEFAULT          (_PRS_TRACECTRL_TSTOP_DEFAULT << 9)    
02614 #define PRS_TRACECTRL_TSTOP_PRSCH0           (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9)     
02615 #define PRS_TRACECTRL_TSTOP_PRSCH1           (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9)     
02616 #define PRS_TRACECTRL_TSTOP_PRSCH2           (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9)     
02617 #define PRS_TRACECTRL_TSTOP_PRSCH3           (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9)     
02618 #define PRS_TRACECTRL_TSTOP_PRSCH4           (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9)     
02619 #define PRS_TRACECTRL_TSTOP_PRSCH5           (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9)     
02625 /**************************************************************************/
02629 #define MSC_UNLOCK_CODE      0x1B71 
02630 #define EMU_UNLOCK_CODE      0xADE8 
02631 #define CMU_UNLOCK_CODE      0x580E 
02632 #define TIMER_UNLOCK_CODE    0xCE80 
02633 #define GPIO_UNLOCK_CODE     0xA534 
02639 /**************************************************************************/
02644 #include "efm32hg_af_ports.h"
02645 #include "efm32hg_af_pins.h"
02646 
02649 /**************************************************************************/
02662 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02663   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02664 
02669 #ifdef __cplusplus
02670 }
02671 #endif
02672 #endif /* __SILICON_LABS_EFM32HG108F32_H__ */