release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg_devinfo.h

Go to the documentation of this file.
00001 /**************************************************************************/
00032 /**************************************************************************/
00036 typedef struct
00037 {
00038   __I uint32_t CAL;          
00039   __I uint32_t ADC0CAL0;     
00040   __I uint32_t ADC0CAL1;     
00041   __I uint32_t ADC0CAL2;     
00042   uint32_t     RESERVED0[2]; 
00043   __I uint32_t IDAC0CAL0;    
00044   __I uint32_t USHFRCOCAL0;  
00045   uint32_t     RESERVED1[1]; 
00046   __I uint32_t AUXHFRCOCAL0; 
00047   __I uint32_t AUXHFRCOCAL1; 
00048   __I uint32_t HFRCOCAL0;    
00049   __I uint32_t HFRCOCAL1;    
00050   __I uint32_t MEMINFO;      
00051   uint32_t     RESERVED2[2]; 
00052   __I uint32_t UNIQUEL;      
00053   __I uint32_t UNIQUEH;      
00054   __I uint32_t MSIZE;        
00055   __I uint32_t PART;         
00056 } DEVINFO_TypeDef;           
00058 /**************************************************************************/
00062 /* Bit fields for EFM32HG_DEVINFO */
00063 #define _DEVINFO_CAL_CRC_MASK                           0x0000FFFFUL 
00064 #define _DEVINFO_CAL_CRC_SHIFT                          0            
00065 #define _DEVINFO_CAL_TEMP_MASK                          0x00FF0000UL 
00066 #define _DEVINFO_CAL_TEMP_SHIFT                         16           
00067 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK                0x00007F00UL 
00068 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT               8            
00069 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK              0x0000007FUL 
00070 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT             0            
00071 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK                 0x7F000000UL 
00072 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT                24           
00073 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK               0x007F0000UL 
00074 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT              16           
00075 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK                 0x00007F00UL 
00076 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT                8            
00077 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK               0x0000007FUL 
00078 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT              0            
00079 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK              0x7F000000UL 
00080 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT             24           
00081 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK            0x007F0000UL 
00082 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT           16           
00083 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK          0x0000007FUL 
00084 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT         0            
00085 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK                 0xFFF00000UL 
00086 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT                20           
00087 #define _DEVINFO_IDAC0CAL0_RANGE0_MASK                  0x000000FFUL 
00088 #define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT                 0            
00089 #define _DEVINFO_IDAC0CAL0_RANGE1_MASK                  0x0000FF00UL 
00090 #define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT                 8            
00091 #define _DEVINFO_IDAC0CAL0_RANGE2_MASK                  0x00FF0000UL 
00092 #define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT                 16           
00093 #define _DEVINFO_IDAC0CAL0_RANGE3_MASK                  0xFF000000UL 
00094 #define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT                 24           
00095 #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_MASK         0x0000007FUL 
00096 #define _DEVINFO_USHFRCOCAL0_BAND24_TUNING_SHIFT        0            
00097 #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_MASK     0x00003F00UL 
00098 #define _DEVINFO_USHFRCOCAL0_BAND24_FINETUNING_SHIFT    8            
00099 #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_MASK         0x007F0000UL 
00100 #define _DEVINFO_USHFRCOCAL0_BAND48_TUNING_SHIFT        16           
00101 #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_MASK     0x3F000000UL 
00102 #define _DEVINFO_USHFRCOCAL0_BAND48_FINETUNING_SHIFT    24           
00103 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK                0x000000FFUL 
00104 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT               0            
00105 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK                0x0000FF00UL 
00106 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT               8            
00107 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK               0x00FF0000UL 
00108 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT              16           
00109 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK               0xFF000000UL 
00110 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT              24           
00111 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK               0x000000FFUL 
00112 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT              0            
00113 #define _DEVINFO_HFRCOCAL0_BAND1_MASK                   0x000000FFUL 
00114 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT                  0            
00115 #define _DEVINFO_HFRCOCAL0_BAND7_MASK                   0x0000FF00UL 
00116 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT                  8            
00117 #define _DEVINFO_HFRCOCAL0_BAND11_MASK                  0x00FF0000UL 
00118 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT                 16           
00119 #define _DEVINFO_HFRCOCAL0_BAND14_MASK                  0xFF000000UL 
00120 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT                 24           
00121 #define _DEVINFO_HFRCOCAL1_BAND21_MASK                  0x000000FFUL 
00122 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT                 0            
00123 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK           0xFF000000UL 
00124 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT          24           
00125 #define _DEVINFO_UNIQUEL_MASK                           0xFFFFFFFFUL 
00126 #define _DEVINFO_UNIQUEL_SHIFT                          0            
00127 #define _DEVINFO_UNIQUEH_MASK                           0xFFFFFFFFUL 
00128 #define _DEVINFO_UNIQUEH_SHIFT                          0            
00129 #define _DEVINFO_MSIZE_SRAM_MASK                        0xFFFF0000UL 
00130 #define _DEVINFO_MSIZE_SRAM_SHIFT                       16           
00131 #define _DEVINFO_MSIZE_FLASH_MASK                       0x0000FFFFUL 
00132 #define _DEVINFO_MSIZE_FLASH_SHIFT                      0            
00133 #define _DEVINFO_PART_PROD_REV_MASK                     0xFF000000UL 
00134 #define _DEVINFO_PART_PROD_REV_SHIFT                    24           
00135 #define _DEVINFO_PART_DEVICE_FAMILY_MASK                0x00FF0000UL 
00136 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT               16           
00137 /* Legacy family #defines */
00138 #define _DEVINFO_PART_DEVICE_FAMILY_G                   71           
00139 #define _DEVINFO_PART_DEVICE_FAMILY_GG                  72           
00140 #define _DEVINFO_PART_DEVICE_FAMILY_TG                  73           
00141 #define _DEVINFO_PART_DEVICE_FAMILY_LG                  74           
00142 #define _DEVINFO_PART_DEVICE_FAMILY_WG                  75           
00143 #define _DEVINFO_PART_DEVICE_FAMILY_ZG                  76           
00144 #define _DEVINFO_PART_DEVICE_FAMILY_HG                  77           
00145 /* New style family #defines */
00146 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G              71           
00147 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG             72           
00148 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG             73           
00149 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG             74           
00150 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG             75           
00151 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG             76           
00152 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG             77           
00153 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG             120          
00154 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG             121          
00155 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG             122          
00156 #define _DEVINFO_PART_DEVICE_NUMBER_MASK                0x0000FFFFUL 
00157 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT               0