00001
00034 #ifndef __SILICON_LABS_EFM32HG321F64_H__
00035 #define __SILICON_LABS_EFM32HG321F64_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 SVCall_IRQn = -5,
00058 PendSV_IRQn = -2,
00059 SysTick_IRQn = -1,
00061
00062 DMA_IRQn = 0,
00063 GPIO_EVEN_IRQn = 1,
00064 TIMER0_IRQn = 2,
00065 ACMP0_IRQn = 3,
00066 ADC0_IRQn = 4,
00067 I2C0_IRQn = 5,
00068 GPIO_ODD_IRQn = 6,
00069 TIMER1_IRQn = 7,
00070 USART1_RX_IRQn = 8,
00071 USART1_TX_IRQn = 9,
00072 LEUART0_IRQn = 10,
00073 PCNT0_IRQn = 11,
00074 RTC_IRQn = 12,
00075 CMU_IRQn = 13,
00076 VCMP_IRQn = 14,
00077 MSC_IRQn = 15,
00078 USART0_RX_IRQn = 17,
00079 USART0_TX_IRQn = 18,
00080 USB_IRQn = 19,
00081 TIMER2_IRQn = 20,
00082 } IRQn_Type;
00083
00084
00089 #define __MPU_PRESENT 0
00090 #define __VTOR_PRESENT 1
00091 #define __NVIC_PRIO_BITS 2
00092 #define __Vendor_SysTickConfig 0
00096
00102 #define _EFM32_HAPPY_FAMILY 1
00103 #define _EFM_DEVICE
00104 #define _SILICON_LABS_32B_PLATFORM_1
00105 #define _SILICON_LABS_32B_PLATFORM 1
00107
00108 #if !defined(EFM32HG321F64)
00109 #define EFM32HG321F64 1
00110 #endif
00111
00113 #define PART_NUMBER "EFM32HG321F64"
00116 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00117 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00118 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00119 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00120 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00121 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00122 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00123 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00124 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
00125 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
00126 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
00127 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
00128 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00129 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00130 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00131 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00132 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00133 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
00134 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
00135 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
00136 #define DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL)
00137 #define DEVICE_MEM_SIZE ((uint32_t) 0x1000UL)
00138 #define DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL)
00139 #define DEVICE_MEM_BITS ((uint32_t) 0x12UL)
00140 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00141 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
00142 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
00143 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
00146 #define FLASH_BASE (0x00000000UL)
00147 #define FLASH_SIZE (0x00010000UL)
00148 #define FLASH_PAGE_SIZE 1024
00149 #define SRAM_BASE (0x20000000UL)
00150 #define SRAM_SIZE (0x00002000UL)
00151 #define __CM0PLUS_REV 0x001
00152 #define PRS_CHAN_COUNT 6
00153 #define DMA_CHAN_COUNT 6
00156 #define AFCHAN_MAX 42
00157 #define AFCHANLOC_MAX 7
00158
00159 #define AFACHAN_MAX 27
00160
00161
00162
00163 #define TIMER_PRESENT
00164 #define TIMER_COUNT 3
00165 #define ACMP_PRESENT
00166 #define ACMP_COUNT 1
00167 #define USART_PRESENT
00168 #define USART_COUNT 2
00169 #define IDAC_PRESENT
00170 #define IDAC_COUNT 1
00171 #define ADC_PRESENT
00172 #define ADC_COUNT 1
00173 #define LEUART_PRESENT
00174 #define LEUART_COUNT 1
00175 #define PCNT_PRESENT
00176 #define PCNT_COUNT 1
00177 #define I2C_PRESENT
00178 #define I2C_COUNT 1
00179 #define DMA_PRESENT
00180 #define DMA_COUNT 1
00181 #define LE_PRESENT
00182 #define LE_COUNT 1
00183 #define USBC_PRESENT
00184 #define USBC_COUNT 1
00185 #define USBLE_PRESENT
00186 #define USBLE_COUNT 1
00187 #define USB_PRESENT
00188 #define USB_COUNT 1
00189 #define MSC_PRESENT
00190 #define MSC_COUNT 1
00191 #define EMU_PRESENT
00192 #define EMU_COUNT 1
00193 #define RMU_PRESENT
00194 #define RMU_COUNT 1
00195 #define CMU_PRESENT
00196 #define CMU_COUNT 1
00197 #define PRS_PRESENT
00198 #define PRS_COUNT 1
00199 #define GPIO_PRESENT
00200 #define GPIO_COUNT 1
00201 #define VCMP_PRESENT
00202 #define VCMP_COUNT 1
00203 #define RTC_PRESENT
00204 #define RTC_COUNT 1
00205 #define HFXTAL_PRESENT
00206 #define HFXTAL_COUNT 1
00207 #define LFXTAL_PRESENT
00208 #define LFXTAL_COUNT 1
00209 #define USHFRCO_PRESENT
00210 #define USHFRCO_COUNT 1
00211 #define WDOG_PRESENT
00212 #define WDOG_COUNT 1
00213 #define DBG_PRESENT
00214 #define DBG_COUNT 1
00215 #define MTB_PRESENT
00216 #define MTB_COUNT 1
00217 #define BOOTLOADER_PRESENT
00218 #define BOOTLOADER_COUNT 1
00219 #define ANALOG_PRESENT
00220 #define ANALOG_COUNT 1
00221
00224 #define ARM_MATH_CM0PLUS
00225 #include "arm_math.h"
00226 #include "core_cm0plus.h"
00227 #include "system_efm32hg.h"
00228
00229
00235 #include "efm32hg_dma_ch.h"
00236
00237
00242 typedef struct
00243 {
00244 __I uint32_t STATUS;
00245 __O uint32_t CONFIG;
00246 __IO uint32_t CTRLBASE;
00247 __I uint32_t ALTCTRLBASE;
00248 __I uint32_t CHWAITSTATUS;
00249 __O uint32_t CHSWREQ;
00250 __IO uint32_t CHUSEBURSTS;
00251 __O uint32_t CHUSEBURSTC;
00252 __IO uint32_t CHREQMASKS;
00253 __O uint32_t CHREQMASKC;
00254 __IO uint32_t CHENS;
00255 __O uint32_t CHENC;
00256 __IO uint32_t CHALTS;
00257 __O uint32_t CHALTC;
00258 __IO uint32_t CHPRIS;
00259 __O uint32_t CHPRIC;
00260 uint32_t RESERVED0[3];
00261 __IO uint32_t ERRORC;
00263 uint32_t RESERVED1[880];
00264 __I uint32_t CHREQSTATUS;
00265 uint32_t RESERVED2[1];
00266 __I uint32_t CHSREQSTATUS;
00268 uint32_t RESERVED3[121];
00269 __I uint32_t IF;
00270 __IO uint32_t IFS;
00271 __IO uint32_t IFC;
00272 __IO uint32_t IEN;
00274 uint32_t RESERVED4[60];
00275 DMA_CH_TypeDef CH[6];
00276 } DMA_TypeDef;
00278 #include "efm32hg_usb_diep.h"
00279 #include "efm32hg_usb_doep.h"
00280 #include "efm32hg_usb.h"
00281 #include "efm32hg_msc.h"
00282 #include "efm32hg_emu.h"
00283 #include "efm32hg_rmu.h"
00284
00285
00290 typedef struct
00291 {
00292 __IO uint32_t CTRL;
00293 __IO uint32_t HFCORECLKDIV;
00294 __IO uint32_t HFPERCLKDIV;
00295 __IO uint32_t HFRCOCTRL;
00296 __IO uint32_t LFRCOCTRL;
00297 __IO uint32_t AUXHFRCOCTRL;
00298 __IO uint32_t CALCTRL;
00299 __IO uint32_t CALCNT;
00300 __IO uint32_t OSCENCMD;
00301 __IO uint32_t CMD;
00302 __IO uint32_t LFCLKSEL;
00303 __I uint32_t STATUS;
00304 __I uint32_t IF;
00305 __IO uint32_t IFS;
00306 __IO uint32_t IFC;
00307 __IO uint32_t IEN;
00308 __IO uint32_t HFCORECLKEN0;
00309 __IO uint32_t HFPERCLKEN0;
00310 uint32_t RESERVED0[2];
00311 __I uint32_t SYNCBUSY;
00312 __IO uint32_t FREEZE;
00313 __IO uint32_t LFACLKEN0;
00314 uint32_t RESERVED1[1];
00315 __IO uint32_t LFBCLKEN0;
00316 __IO uint32_t LFCCLKEN0;
00317 __IO uint32_t LFAPRESC0;
00318 uint32_t RESERVED2[1];
00319 __IO uint32_t LFBPRESC0;
00320 uint32_t RESERVED3[1];
00321 __IO uint32_t PCNTCTRL;
00323 uint32_t RESERVED4[1];
00324 __IO uint32_t ROUTE;
00325 __IO uint32_t LOCK;
00327 uint32_t RESERVED5[18];
00328 __IO uint32_t USBCRCTRL;
00329 __IO uint32_t USHFRCOCTRL;
00330 __IO uint32_t USHFRCOTUNE;
00331 __IO uint32_t USHFRCOCONF;
00332 } CMU_TypeDef;
00334 #include "efm32hg_timer_cc.h"
00335 #include "efm32hg_timer.h"
00336 #include "efm32hg_acmp.h"
00337 #include "efm32hg_usart.h"
00338 #include "efm32hg_prs_ch.h"
00339 #include "efm32hg_prs.h"
00340 #include "efm32hg_idac.h"
00341 #include "efm32hg_gpio_p.h"
00342 #include "efm32hg_gpio.h"
00343 #include "efm32hg_vcmp.h"
00344 #include "efm32hg_adc.h"
00345 #include "efm32hg_leuart.h"
00346 #include "efm32hg_pcnt.h"
00347 #include "efm32hg_i2c.h"
00348 #include "efm32hg_rtc.h"
00349 #include "efm32hg_wdog.h"
00350 #include "efm32hg_mtb.h"
00351 #include "efm32hg_dma_descriptor.h"
00352 #include "efm32hg_devinfo.h"
00353 #include "efm32hg_romtable.h"
00354 #include "efm32hg_calibrate.h"
00355
00358
00363 #define DMA_BASE (0x400C2000UL)
00364 #define USB_BASE (0x400C4000UL)
00365 #define MSC_BASE (0x400C0000UL)
00366 #define EMU_BASE (0x400C6000UL)
00367 #define RMU_BASE (0x400CA000UL)
00368 #define CMU_BASE (0x400C8000UL)
00369 #define TIMER0_BASE (0x40010000UL)
00370 #define TIMER1_BASE (0x40010400UL)
00371 #define TIMER2_BASE (0x40010800UL)
00372 #define ACMP0_BASE (0x40001000UL)
00373 #define USART0_BASE (0x4000C000UL)
00374 #define USART1_BASE (0x4000C400UL)
00375 #define PRS_BASE (0x400CC000UL)
00376 #define IDAC0_BASE (0x40004000UL)
00377 #define GPIO_BASE (0x40006000UL)
00378 #define VCMP_BASE (0x40000000UL)
00379 #define ADC0_BASE (0x40002000UL)
00380 #define LEUART0_BASE (0x40084000UL)
00381 #define PCNT0_BASE (0x40086000UL)
00382 #define I2C0_BASE (0x4000A000UL)
00383 #define RTC_BASE (0x40080000UL)
00384 #define WDOG_BASE (0x40088000UL)
00385 #define MTB_BASE (0xF0040000UL)
00386 #define CALIBRATE_BASE (0x0FE08000UL)
00387 #define DEVINFO_BASE (0x0FE081B0UL)
00388 #define ROMTABLE_BASE (0xF00FFFD0UL)
00389 #define LOCKBITS_BASE (0x0FE04000UL)
00390 #define USERDATA_BASE (0x0FE00000UL)
00394
00399 #define DMA ((DMA_TypeDef *) DMA_BASE)
00400 #define USB ((USB_TypeDef *) USB_BASE)
00401 #define MSC ((MSC_TypeDef *) MSC_BASE)
00402 #define EMU ((EMU_TypeDef *) EMU_BASE)
00403 #define RMU ((RMU_TypeDef *) RMU_BASE)
00404 #define CMU ((CMU_TypeDef *) CMU_BASE)
00405 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00406 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00407 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
00408 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00409 #define USART0 ((USART_TypeDef *) USART0_BASE)
00410 #define USART1 ((USART_TypeDef *) USART1_BASE)
00411 #define PRS ((PRS_TypeDef *) PRS_BASE)
00412 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)
00413 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00414 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00415 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00416 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00417 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00418 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00419 #define RTC ((RTC_TypeDef *) RTC_BASE)
00420 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00421 #define MTB ((MTB_TypeDef *) MTB_BASE)
00422 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00423 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00424 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00428
00433 #include "efm32hg_prs_signals.h"
00434 #include "efm32hg_dmareq.h"
00435 #include "efm32hg_dmactrl.h"
00436
00437
00442
00443 #define _DMA_STATUS_RESETVALUE 0x10050000UL
00444 #define _DMA_STATUS_MASK 0x001F00F1UL
00445 #define DMA_STATUS_EN (0x1UL << 0)
00446 #define _DMA_STATUS_EN_SHIFT 0
00447 #define _DMA_STATUS_EN_MASK 0x1UL
00448 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL
00449 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
00450 #define _DMA_STATUS_STATE_SHIFT 4
00451 #define _DMA_STATUS_STATE_MASK 0xF0UL
00452 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL
00453 #define _DMA_STATUS_STATE_IDLE 0x00000000UL
00454 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
00455 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
00456 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
00457 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
00458 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
00459 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
00460 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
00461 #define _DMA_STATUS_STATE_STALLED 0x00000008UL
00462 #define _DMA_STATUS_STATE_DONE 0x00000009UL
00463 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
00464 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
00465 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
00466 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
00467 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
00468 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
00469 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
00470 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
00471 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
00472 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
00473 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
00474 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
00475 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
00476 #define _DMA_STATUS_CHNUM_SHIFT 16
00477 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL
00478 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000005UL
00479 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
00481
00482 #define _DMA_CONFIG_RESETVALUE 0x00000000UL
00483 #define _DMA_CONFIG_MASK 0x00000021UL
00484 #define DMA_CONFIG_EN (0x1UL << 0)
00485 #define _DMA_CONFIG_EN_SHIFT 0
00486 #define _DMA_CONFIG_EN_MASK 0x1UL
00487 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL
00488 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
00489 #define DMA_CONFIG_CHPROT (0x1UL << 5)
00490 #define _DMA_CONFIG_CHPROT_SHIFT 5
00491 #define _DMA_CONFIG_CHPROT_MASK 0x20UL
00492 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
00493 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
00495
00496 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL
00497 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL
00498 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0
00499 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
00500 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
00501 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
00503
00504 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL
00505 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00506 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
00507 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00508 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL
00509 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
00511
00512 #define _DMA_CHWAITSTATUS_RESETVALUE 0x0000003FUL
00513 #define _DMA_CHWAITSTATUS_MASK 0x0000003FUL
00514 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
00515 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
00516 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
00517 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
00518 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
00519 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
00520 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
00521 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
00522 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
00523 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
00524 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
00525 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
00526 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
00527 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
00528 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
00529 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
00530 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
00531 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
00532 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
00533 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
00534 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)
00535 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4
00536 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL
00537 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL
00538 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
00539 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)
00540 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5
00541 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL
00542 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL
00543 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
00545
00546 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL
00547 #define _DMA_CHSWREQ_MASK 0x0000003FUL
00548 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
00549 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0
00550 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
00551 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
00552 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
00553 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
00554 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1
00555 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
00556 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
00557 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
00558 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
00559 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2
00560 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
00561 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
00562 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
00563 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
00564 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3
00565 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
00566 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
00567 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
00568 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)
00569 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4
00570 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL
00571 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL
00572 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
00573 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)
00574 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5
00575 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL
00576 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL
00577 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
00579
00580 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
00581 #define _DMA_CHUSEBURSTS_MASK 0x0000003FUL
00582 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
00583 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
00584 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
00585 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
00586 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
00587 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
00588 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
00589 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
00590 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
00591 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
00592 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
00593 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
00594 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
00595 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
00596 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
00597 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
00598 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
00599 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
00600 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
00601 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
00602 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
00603 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
00604 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
00605 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
00606 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)
00607 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4
00608 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL
00609 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL
00610 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
00611 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)
00612 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5
00613 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL
00614 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL
00615 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
00617
00618 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
00619 #define _DMA_CHUSEBURSTC_MASK 0x0000003FUL
00620 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
00621 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
00622 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
00623 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
00624 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
00625 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
00626 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
00627 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
00628 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
00629 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
00630 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
00631 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
00632 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
00633 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
00634 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
00635 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
00636 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
00637 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
00638 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
00639 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
00640 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)
00641 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4
00642 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL
00643 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL
00644 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
00645 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)
00646 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5
00647 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL
00648 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL
00649 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
00651
00652 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
00653 #define _DMA_CHREQMASKS_MASK 0x0000003FUL
00654 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
00655 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
00656 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
00657 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
00658 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
00659 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
00660 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
00661 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
00662 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
00663 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
00664 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
00665 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
00666 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
00667 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
00668 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
00669 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
00670 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
00671 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
00672 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
00673 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
00674 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)
00675 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
00676 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
00677 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
00678 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
00679 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)
00680 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
00681 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
00682 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
00683 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
00685
00686 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
00687 #define _DMA_CHREQMASKC_MASK 0x0000003FUL
00688 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
00689 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
00690 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
00691 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
00692 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
00693 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
00694 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
00695 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
00696 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
00697 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
00698 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
00699 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
00700 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
00701 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
00702 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
00703 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
00704 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
00705 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
00706 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
00707 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
00708 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)
00709 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
00710 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
00711 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
00712 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
00713 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)
00714 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
00715 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
00716 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
00717 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
00719
00720 #define _DMA_CHENS_RESETVALUE 0x00000000UL
00721 #define _DMA_CHENS_MASK 0x0000003FUL
00722 #define DMA_CHENS_CH0ENS (0x1UL << 0)
00723 #define _DMA_CHENS_CH0ENS_SHIFT 0
00724 #define _DMA_CHENS_CH0ENS_MASK 0x1UL
00725 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
00726 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
00727 #define DMA_CHENS_CH1ENS (0x1UL << 1)
00728 #define _DMA_CHENS_CH1ENS_SHIFT 1
00729 #define _DMA_CHENS_CH1ENS_MASK 0x2UL
00730 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
00731 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
00732 #define DMA_CHENS_CH2ENS (0x1UL << 2)
00733 #define _DMA_CHENS_CH2ENS_SHIFT 2
00734 #define _DMA_CHENS_CH2ENS_MASK 0x4UL
00735 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
00736 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
00737 #define DMA_CHENS_CH3ENS (0x1UL << 3)
00738 #define _DMA_CHENS_CH3ENS_SHIFT 3
00739 #define _DMA_CHENS_CH3ENS_MASK 0x8UL
00740 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
00741 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
00742 #define DMA_CHENS_CH4ENS (0x1UL << 4)
00743 #define _DMA_CHENS_CH4ENS_SHIFT 4
00744 #define _DMA_CHENS_CH4ENS_MASK 0x10UL
00745 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
00746 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)
00747 #define DMA_CHENS_CH5ENS (0x1UL << 5)
00748 #define _DMA_CHENS_CH5ENS_SHIFT 5
00749 #define _DMA_CHENS_CH5ENS_MASK 0x20UL
00750 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
00751 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)
00753
00754 #define _DMA_CHENC_RESETVALUE 0x00000000UL
00755 #define _DMA_CHENC_MASK 0x0000003FUL
00756 #define DMA_CHENC_CH0ENC (0x1UL << 0)
00757 #define _DMA_CHENC_CH0ENC_SHIFT 0
00758 #define _DMA_CHENC_CH0ENC_MASK 0x1UL
00759 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
00760 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
00761 #define DMA_CHENC_CH1ENC (0x1UL << 1)
00762 #define _DMA_CHENC_CH1ENC_SHIFT 1
00763 #define _DMA_CHENC_CH1ENC_MASK 0x2UL
00764 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
00765 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
00766 #define DMA_CHENC_CH2ENC (0x1UL << 2)
00767 #define _DMA_CHENC_CH2ENC_SHIFT 2
00768 #define _DMA_CHENC_CH2ENC_MASK 0x4UL
00769 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
00770 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
00771 #define DMA_CHENC_CH3ENC (0x1UL << 3)
00772 #define _DMA_CHENC_CH3ENC_SHIFT 3
00773 #define _DMA_CHENC_CH3ENC_MASK 0x8UL
00774 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
00775 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
00776 #define DMA_CHENC_CH4ENC (0x1UL << 4)
00777 #define _DMA_CHENC_CH4ENC_SHIFT 4
00778 #define _DMA_CHENC_CH4ENC_MASK 0x10UL
00779 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
00780 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)
00781 #define DMA_CHENC_CH5ENC (0x1UL << 5)
00782 #define _DMA_CHENC_CH5ENC_SHIFT 5
00783 #define _DMA_CHENC_CH5ENC_MASK 0x20UL
00784 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
00785 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)
00787
00788 #define _DMA_CHALTS_RESETVALUE 0x00000000UL
00789 #define _DMA_CHALTS_MASK 0x0000003FUL
00790 #define DMA_CHALTS_CH0ALTS (0x1UL << 0)
00791 #define _DMA_CHALTS_CH0ALTS_SHIFT 0
00792 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
00793 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
00794 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
00795 #define DMA_CHALTS_CH1ALTS (0x1UL << 1)
00796 #define _DMA_CHALTS_CH1ALTS_SHIFT 1
00797 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
00798 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
00799 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
00800 #define DMA_CHALTS_CH2ALTS (0x1UL << 2)
00801 #define _DMA_CHALTS_CH2ALTS_SHIFT 2
00802 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
00803 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
00804 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
00805 #define DMA_CHALTS_CH3ALTS (0x1UL << 3)
00806 #define _DMA_CHALTS_CH3ALTS_SHIFT 3
00807 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
00808 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
00809 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
00810 #define DMA_CHALTS_CH4ALTS (0x1UL << 4)
00811 #define _DMA_CHALTS_CH4ALTS_SHIFT 4
00812 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL
00813 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
00814 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
00815 #define DMA_CHALTS_CH5ALTS (0x1UL << 5)
00816 #define _DMA_CHALTS_CH5ALTS_SHIFT 5
00817 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL
00818 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
00819 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
00821
00822 #define _DMA_CHALTC_RESETVALUE 0x00000000UL
00823 #define _DMA_CHALTC_MASK 0x0000003FUL
00824 #define DMA_CHALTC_CH0ALTC (0x1UL << 0)
00825 #define _DMA_CHALTC_CH0ALTC_SHIFT 0
00826 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
00827 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
00828 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
00829 #define DMA_CHALTC_CH1ALTC (0x1UL << 1)
00830 #define _DMA_CHALTC_CH1ALTC_SHIFT 1
00831 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
00832 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
00833 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
00834 #define DMA_CHALTC_CH2ALTC (0x1UL << 2)
00835 #define _DMA_CHALTC_CH2ALTC_SHIFT 2
00836 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
00837 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
00838 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
00839 #define DMA_CHALTC_CH3ALTC (0x1UL << 3)
00840 #define _DMA_CHALTC_CH3ALTC_SHIFT 3
00841 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
00842 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
00843 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
00844 #define DMA_CHALTC_CH4ALTC (0x1UL << 4)
00845 #define _DMA_CHALTC_CH4ALTC_SHIFT 4
00846 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL
00847 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
00848 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
00849 #define DMA_CHALTC_CH5ALTC (0x1UL << 5)
00850 #define _DMA_CHALTC_CH5ALTC_SHIFT 5
00851 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL
00852 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
00853 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
00855
00856 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL
00857 #define _DMA_CHPRIS_MASK 0x0000003FUL
00858 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0)
00859 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0
00860 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
00861 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
00862 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
00863 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1)
00864 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1
00865 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
00866 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
00867 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
00868 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2)
00869 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2
00870 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
00871 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
00872 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
00873 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3)
00874 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3
00875 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
00876 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
00877 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
00878 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4)
00879 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4
00880 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL
00881 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
00882 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
00883 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5)
00884 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5
00885 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL
00886 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
00887 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
00889
00890 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL
00891 #define _DMA_CHPRIC_MASK 0x0000003FUL
00892 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0)
00893 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0
00894 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
00895 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
00896 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
00897 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1)
00898 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1
00899 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
00900 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
00901 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
00902 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2)
00903 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2
00904 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
00905 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
00906 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
00907 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3)
00908 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3
00909 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
00910 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
00911 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
00912 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4)
00913 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4
00914 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL
00915 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
00916 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
00917 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5)
00918 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5
00919 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL
00920 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
00921 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
00923
00924 #define _DMA_ERRORC_RESETVALUE 0x00000000UL
00925 #define _DMA_ERRORC_MASK 0x00000001UL
00926 #define DMA_ERRORC_ERRORC (0x1UL << 0)
00927 #define _DMA_ERRORC_ERRORC_SHIFT 0
00928 #define _DMA_ERRORC_ERRORC_MASK 0x1UL
00929 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
00930 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
00932
00933 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
00934 #define _DMA_CHREQSTATUS_MASK 0x0000003FUL
00935 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
00936 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
00937 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
00938 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
00939 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
00940 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
00941 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
00942 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
00943 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
00944 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
00945 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
00946 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
00947 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
00948 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
00949 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
00950 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
00951 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
00952 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
00953 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
00954 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
00955 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)
00956 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
00957 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
00958 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
00959 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
00960 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)
00961 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
00962 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
00963 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
00964 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
00966
00967 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
00968 #define _DMA_CHSREQSTATUS_MASK 0x0000003FUL
00969 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
00970 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
00971 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
00972 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
00973 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
00974 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
00975 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
00976 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
00977 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
00978 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
00979 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
00980 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
00981 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
00982 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
00983 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
00984 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
00985 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
00986 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
00987 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
00988 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
00989 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)
00990 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
00991 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
00992 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
00993 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
00994 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)
00995 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
00996 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
00997 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
00998 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
01000
01001 #define _DMA_IF_RESETVALUE 0x00000000UL
01002 #define _DMA_IF_MASK 0x8000003FUL
01003 #define DMA_IF_CH0DONE (0x1UL << 0)
01004 #define _DMA_IF_CH0DONE_SHIFT 0
01005 #define _DMA_IF_CH0DONE_MASK 0x1UL
01006 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL
01007 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
01008 #define DMA_IF_CH1DONE (0x1UL << 1)
01009 #define _DMA_IF_CH1DONE_SHIFT 1
01010 #define _DMA_IF_CH1DONE_MASK 0x2UL
01011 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL
01012 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
01013 #define DMA_IF_CH2DONE (0x1UL << 2)
01014 #define _DMA_IF_CH2DONE_SHIFT 2
01015 #define _DMA_IF_CH2DONE_MASK 0x4UL
01016 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL
01017 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
01018 #define DMA_IF_CH3DONE (0x1UL << 3)
01019 #define _DMA_IF_CH3DONE_SHIFT 3
01020 #define _DMA_IF_CH3DONE_MASK 0x8UL
01021 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL
01022 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
01023 #define DMA_IF_CH4DONE (0x1UL << 4)
01024 #define _DMA_IF_CH4DONE_SHIFT 4
01025 #define _DMA_IF_CH4DONE_MASK 0x10UL
01026 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL
01027 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)
01028 #define DMA_IF_CH5DONE (0x1UL << 5)
01029 #define _DMA_IF_CH5DONE_SHIFT 5
01030 #define _DMA_IF_CH5DONE_MASK 0x20UL
01031 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL
01032 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)
01033 #define DMA_IF_ERR (0x1UL << 31)
01034 #define _DMA_IF_ERR_SHIFT 31
01035 #define _DMA_IF_ERR_MASK 0x80000000UL
01036 #define _DMA_IF_ERR_DEFAULT 0x00000000UL
01037 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
01039
01040 #define _DMA_IFS_RESETVALUE 0x00000000UL
01041 #define _DMA_IFS_MASK 0x8000003FUL
01042 #define DMA_IFS_CH0DONE (0x1UL << 0)
01043 #define _DMA_IFS_CH0DONE_SHIFT 0
01044 #define _DMA_IFS_CH0DONE_MASK 0x1UL
01045 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
01046 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
01047 #define DMA_IFS_CH1DONE (0x1UL << 1)
01048 #define _DMA_IFS_CH1DONE_SHIFT 1
01049 #define _DMA_IFS_CH1DONE_MASK 0x2UL
01050 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
01051 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
01052 #define DMA_IFS_CH2DONE (0x1UL << 2)
01053 #define _DMA_IFS_CH2DONE_SHIFT 2
01054 #define _DMA_IFS_CH2DONE_MASK 0x4UL
01055 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
01056 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
01057 #define DMA_IFS_CH3DONE (0x1UL << 3)
01058 #define _DMA_IFS_CH3DONE_SHIFT 3
01059 #define _DMA_IFS_CH3DONE_MASK 0x8UL
01060 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
01061 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
01062 #define DMA_IFS_CH4DONE (0x1UL << 4)
01063 #define _DMA_IFS_CH4DONE_SHIFT 4
01064 #define _DMA_IFS_CH4DONE_MASK 0x10UL
01065 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL
01066 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)
01067 #define DMA_IFS_CH5DONE (0x1UL << 5)
01068 #define _DMA_IFS_CH5DONE_SHIFT 5
01069 #define _DMA_IFS_CH5DONE_MASK 0x20UL
01070 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL
01071 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)
01072 #define DMA_IFS_ERR (0x1UL << 31)
01073 #define _DMA_IFS_ERR_SHIFT 31
01074 #define _DMA_IFS_ERR_MASK 0x80000000UL
01075 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL
01076 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
01078
01079 #define _DMA_IFC_RESETVALUE 0x00000000UL
01080 #define _DMA_IFC_MASK 0x8000003FUL
01081 #define DMA_IFC_CH0DONE (0x1UL << 0)
01082 #define _DMA_IFC_CH0DONE_SHIFT 0
01083 #define _DMA_IFC_CH0DONE_MASK 0x1UL
01084 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
01085 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
01086 #define DMA_IFC_CH1DONE (0x1UL << 1)
01087 #define _DMA_IFC_CH1DONE_SHIFT 1
01088 #define _DMA_IFC_CH1DONE_MASK 0x2UL
01089 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
01090 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
01091 #define DMA_IFC_CH2DONE (0x1UL << 2)
01092 #define _DMA_IFC_CH2DONE_SHIFT 2
01093 #define _DMA_IFC_CH2DONE_MASK 0x4UL
01094 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
01095 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
01096 #define DMA_IFC_CH3DONE (0x1UL << 3)
01097 #define _DMA_IFC_CH3DONE_SHIFT 3
01098 #define _DMA_IFC_CH3DONE_MASK 0x8UL
01099 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
01100 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
01101 #define DMA_IFC_CH4DONE (0x1UL << 4)
01102 #define _DMA_IFC_CH4DONE_SHIFT 4
01103 #define _DMA_IFC_CH4DONE_MASK 0x10UL
01104 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL
01105 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)
01106 #define DMA_IFC_CH5DONE (0x1UL << 5)
01107 #define _DMA_IFC_CH5DONE_SHIFT 5
01108 #define _DMA_IFC_CH5DONE_MASK 0x20UL
01109 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL
01110 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)
01111 #define DMA_IFC_ERR (0x1UL << 31)
01112 #define _DMA_IFC_ERR_SHIFT 31
01113 #define _DMA_IFC_ERR_MASK 0x80000000UL
01114 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL
01115 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
01117
01118 #define _DMA_IEN_RESETVALUE 0x00000000UL
01119 #define _DMA_IEN_MASK 0x8000003FUL
01120 #define DMA_IEN_CH0DONE (0x1UL << 0)
01121 #define _DMA_IEN_CH0DONE_SHIFT 0
01122 #define _DMA_IEN_CH0DONE_MASK 0x1UL
01123 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
01124 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
01125 #define DMA_IEN_CH1DONE (0x1UL << 1)
01126 #define _DMA_IEN_CH1DONE_SHIFT 1
01127 #define _DMA_IEN_CH1DONE_MASK 0x2UL
01128 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
01129 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
01130 #define DMA_IEN_CH2DONE (0x1UL << 2)
01131 #define _DMA_IEN_CH2DONE_SHIFT 2
01132 #define _DMA_IEN_CH2DONE_MASK 0x4UL
01133 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
01134 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
01135 #define DMA_IEN_CH3DONE (0x1UL << 3)
01136 #define _DMA_IEN_CH3DONE_SHIFT 3
01137 #define _DMA_IEN_CH3DONE_MASK 0x8UL
01138 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
01139 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
01140 #define DMA_IEN_CH4DONE (0x1UL << 4)
01141 #define _DMA_IEN_CH4DONE_SHIFT 4
01142 #define _DMA_IEN_CH4DONE_MASK 0x10UL
01143 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL
01144 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)
01145 #define DMA_IEN_CH5DONE (0x1UL << 5)
01146 #define _DMA_IEN_CH5DONE_SHIFT 5
01147 #define _DMA_IEN_CH5DONE_MASK 0x20UL
01148 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL
01149 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)
01150 #define DMA_IEN_ERR (0x1UL << 31)
01151 #define _DMA_IEN_ERR_SHIFT 31
01152 #define _DMA_IEN_ERR_MASK 0x80000000UL
01153 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL
01154 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
01156
01157 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
01158 #define _DMA_CH_CTRL_MASK 0x003F000FUL
01159 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0
01160 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
01161 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
01162 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL
01163 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
01164 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
01165 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
01166 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
01167 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
01168 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL
01169 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
01170 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
01171 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL
01172 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
01173 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
01174 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
01175 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
01176 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
01177 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL
01178 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL
01179 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
01180 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
01181 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
01182 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
01183 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL
01184 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL
01185 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
01186 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
01187 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL
01188 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL
01189 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
01190 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0)
01191 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
01192 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
01193 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
01194 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
01195 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
01196 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0)
01197 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
01198 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
01199 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0)
01200 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
01201 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
01202 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
01203 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
01204 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
01205 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0)
01206 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0)
01207 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
01208 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
01209 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
01210 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
01211 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0)
01212 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)
01213 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
01214 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
01215 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0)
01216 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)
01217 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
01218 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
01219 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
01220 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
01221 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL
01222 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
01223 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
01224 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
01225 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
01226 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
01227 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL
01228 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
01229 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
01230 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
01231 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16)
01232 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
01233 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
01234 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
01235 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
01236 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
01237 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16)
01238 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
01244
01249
01250 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
01251 #define _CMU_CTRL_MASK 0x07FFFEEFUL
01252 #define _CMU_CTRL_HFXOMODE_SHIFT 0
01253 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
01254 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
01255 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
01256 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
01257 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
01258 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
01259 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
01260 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
01261 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
01262 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
01263 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
01264 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
01265 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
01266 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
01267 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
01268 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
01269 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
01270 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
01271 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
01272 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
01273 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
01274 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
01275 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
01276 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
01277 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
01278 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
01279 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
01280 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
01281 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
01282 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
01283 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
01284 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
01285 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
01286 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
01287 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
01288 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
01289 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
01290 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
01291 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
01292 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
01293 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
01294 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
01295 #define _CMU_CTRL_LFXOMODE_SHIFT 11
01296 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
01297 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
01298 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
01299 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
01300 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
01301 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
01302 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
01303 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
01304 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
01305 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
01306 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
01307 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
01308 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
01309 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
01310 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
01311 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
01312 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
01313 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
01314 #define _CMU_CTRL_HFCLKDIV_SHIFT 14
01315 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL
01316 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL
01317 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)
01318 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
01319 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
01320 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
01321 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
01322 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
01323 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
01324 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
01325 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
01326 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
01327 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
01328 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
01329 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
01330 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
01331 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
01332 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
01333 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
01334 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
01335 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
01336 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
01337 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
01338 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
01339 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
01340 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
01341 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
01342 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
01343 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
01344 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
01345 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL
01346 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
01347 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
01348 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
01349 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
01350 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
01351 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
01352 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
01353 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
01354 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
01355 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
01356 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL
01357 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
01358 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
01359 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
01360 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL
01361 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL
01362 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL
01363 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL
01364 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL
01365 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL
01366 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO 0x00000008UL
01367 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
01368 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
01369 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
01370 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
01371 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
01372 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
01373 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
01374 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
01375 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
01376 #define CMU_CTRL_CLKOUTSEL1_USHFRCO (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23)
01378
01379 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
01380 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL
01381 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
01382 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
01383 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
01384 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
01385 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
01386 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
01387 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
01388 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
01389 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
01390 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
01391 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
01392 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
01393 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
01394 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
01395 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
01396 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
01397 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
01398 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
01399 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
01400 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
01401 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
01402 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
01403 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
01404 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
01405 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8)
01406 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8
01407 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL
01408 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL
01409 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL
01410 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL
01411 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)
01412 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)
01413 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)
01415
01416 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
01417 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
01418 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
01419 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
01420 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
01421 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
01422 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
01423 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
01424 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
01425 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
01426 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
01427 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
01428 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
01429 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
01430 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
01431 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
01432 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
01433 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
01434 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
01435 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
01436 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
01437 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
01438 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
01439 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
01440 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
01441 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
01442 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
01443 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
01444 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
01445 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
01446 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
01448
01449 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
01450 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
01451 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
01452 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
01453 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01454 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
01455 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
01456 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
01457 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
01458 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
01459 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
01460 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
01461 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
01462 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
01463 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
01464 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
01465 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
01466 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
01467 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
01468 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
01469 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
01470 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
01471 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
01472 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
01474
01475 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
01476 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
01477 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
01478 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
01479 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
01480 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
01482
01483 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
01484 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL
01485 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
01486 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
01487 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01488 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
01489 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8
01490 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL
01491 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL
01492 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL
01493 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL
01494 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL
01495 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL
01496 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL
01497 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
01498 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
01499 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
01500 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
01501 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
01502 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
01504
01505 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
01506 #define _CMU_CALCTRL_MASK 0x0000007FUL
01507 #define _CMU_CALCTRL_UPSEL_SHIFT 0
01508 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
01509 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
01510 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
01511 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
01512 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
01513 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
01514 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
01515 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000005UL
01516 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
01517 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
01518 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
01519 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
01520 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
01521 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
01522 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0)
01523 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3
01524 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL
01525 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
01526 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
01527 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
01528 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
01529 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
01530 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
01531 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
01532 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000006UL
01533 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
01534 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
01535 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
01536 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
01537 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
01538 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
01539 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
01540 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3)
01541 #define CMU_CALCTRL_CONT (0x1UL << 6)
01542 #define _CMU_CALCTRL_CONT_SHIFT 6
01543 #define _CMU_CALCTRL_CONT_MASK 0x40UL
01544 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
01545 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)
01547
01548 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
01549 #define _CMU_CALCNT_MASK 0x000FFFFFUL
01550 #define _CMU_CALCNT_CALCNT_SHIFT 0
01551 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
01552 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
01553 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
01555
01556 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
01557 #define _CMU_OSCENCMD_MASK 0x00000FFFUL
01558 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
01559 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
01560 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
01561 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
01562 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
01563 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
01564 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
01565 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
01566 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
01567 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
01568 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
01569 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
01570 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
01571 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
01572 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
01573 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
01574 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
01575 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
01576 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
01577 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
01578 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
01579 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
01580 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
01581 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
01582 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
01583 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
01584 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
01585 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
01586 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
01587 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
01588 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
01589 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
01590 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
01591 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
01592 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
01593 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
01594 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
01595 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
01596 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
01597 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
01598 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
01599 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
01600 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
01601 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
01602 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
01603 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
01604 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
01605 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
01606 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
01607 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
01608 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10)
01609 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10
01610 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL
01611 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL
01612 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10)
01613 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11)
01614 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11
01615 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL
01616 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL
01617 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11)
01619
01620 #define _CMU_CMD_RESETVALUE 0x00000000UL
01621 #define _CMU_CMD_MASK 0x000000FFUL
01622 #define _CMU_CMD_HFCLKSEL_SHIFT 0
01623 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
01624 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
01625 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
01626 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
01627 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
01628 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
01629 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2 0x00000005UL
01630 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
01631 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
01632 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
01633 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
01634 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
01635 #define CMU_CMD_HFCLKSEL_USHFRCODIV2 (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0)
01636 #define CMU_CMD_CALSTART (0x1UL << 3)
01637 #define _CMU_CMD_CALSTART_SHIFT 3
01638 #define _CMU_CMD_CALSTART_MASK 0x8UL
01639 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
01640 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
01641 #define CMU_CMD_CALSTOP (0x1UL << 4)
01642 #define _CMU_CMD_CALSTOP_SHIFT 4
01643 #define _CMU_CMD_CALSTOP_MASK 0x10UL
01644 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
01645 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)
01646 #define _CMU_CMD_USBCCLKSEL_SHIFT 5
01647 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL
01648 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL
01649 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL
01650 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL
01651 #define _CMU_CMD_USBCCLKSEL_USHFRCO 0x00000004UL
01652 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)
01653 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5)
01654 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5)
01655 #define CMU_CMD_USBCCLKSEL_USHFRCO (_CMU_CMD_USBCCLKSEL_USHFRCO << 5)
01657
01658 #define _CMU_LFCLKSEL_RESETVALUE 0x00000015UL
01659 #define _CMU_LFCLKSEL_MASK 0x0011003FUL
01660 #define _CMU_LFCLKSEL_LFA_SHIFT 0
01661 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
01662 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
01663 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
01664 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
01665 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
01666 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
01667 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
01668 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
01669 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
01670 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
01671 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
01672 #define _CMU_LFCLKSEL_LFB_SHIFT 2
01673 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
01674 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
01675 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
01676 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
01677 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
01678 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
01679 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
01680 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
01681 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
01682 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
01683 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
01684 #define _CMU_LFCLKSEL_LFC_SHIFT 4
01685 #define _CMU_LFCLKSEL_LFC_MASK 0x30UL
01686 #define _CMU_LFCLKSEL_LFC_DISABLED 0x00000000UL
01687 #define _CMU_LFCLKSEL_LFC_DEFAULT 0x00000001UL
01688 #define _CMU_LFCLKSEL_LFC_LFRCO 0x00000001UL
01689 #define _CMU_LFCLKSEL_LFC_LFXO 0x00000002UL
01690 #define CMU_LFCLKSEL_LFC_DISABLED (_CMU_LFCLKSEL_LFC_DISABLED << 4)
01691 #define CMU_LFCLKSEL_LFC_DEFAULT (_CMU_LFCLKSEL_LFC_DEFAULT << 4)
01692 #define CMU_LFCLKSEL_LFC_LFRCO (_CMU_LFCLKSEL_LFC_LFRCO << 4)
01693 #define CMU_LFCLKSEL_LFC_LFXO (_CMU_LFCLKSEL_LFC_LFXO << 4)
01694 #define CMU_LFCLKSEL_LFAE (0x1UL << 16)
01695 #define _CMU_LFCLKSEL_LFAE_SHIFT 16
01696 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL
01697 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL
01698 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL
01699 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL
01700 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
01701 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
01702 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
01703 #define CMU_LFCLKSEL_LFBE (0x1UL << 20)
01704 #define _CMU_LFCLKSEL_LFBE_SHIFT 20
01705 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL
01706 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL
01707 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL
01708 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL
01709 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
01710 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
01711 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
01713
01714 #define _CMU_STATUS_RESETVALUE 0x00000403UL
01715 #define _CMU_STATUS_MASK 0x04F77FFFUL
01716 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
01717 #define _CMU_STATUS_HFRCOENS_SHIFT 0
01718 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
01719 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
01720 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
01721 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
01722 #define _CMU_STATUS_HFRCORDY_SHIFT 1
01723 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
01724 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
01725 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
01726 #define CMU_STATUS_HFXOENS (0x1UL << 2)
01727 #define _CMU_STATUS_HFXOENS_SHIFT 2
01728 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
01729 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
01730 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
01731 #define CMU_STATUS_HFXORDY (0x1UL << 3)
01732 #define _CMU_STATUS_HFXORDY_SHIFT 3
01733 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
01734 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
01735 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
01736 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
01737 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
01738 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
01739 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
01740 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
01741 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
01742 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
01743 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
01744 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
01745 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
01746 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
01747 #define _CMU_STATUS_LFRCOENS_SHIFT 6
01748 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
01749 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
01750 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
01751 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
01752 #define _CMU_STATUS_LFRCORDY_SHIFT 7
01753 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
01754 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
01755 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
01756 #define CMU_STATUS_LFXOENS (0x1UL << 8)
01757 #define _CMU_STATUS_LFXOENS_SHIFT 8
01758 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
01759 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
01760 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
01761 #define CMU_STATUS_LFXORDY (0x1UL << 9)
01762 #define _CMU_STATUS_LFXORDY_SHIFT 9
01763 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
01764 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
01765 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
01766 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
01767 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
01768 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
01769 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
01770 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
01771 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
01772 #define _CMU_STATUS_HFXOSEL_SHIFT 11
01773 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
01774 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
01775 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
01776 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
01777 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
01778 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
01779 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
01780 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
01781 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
01782 #define _CMU_STATUS_LFXOSEL_SHIFT 13
01783 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
01784 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
01785 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
01786 #define CMU_STATUS_CALBSY (0x1UL << 14)
01787 #define _CMU_STATUS_CALBSY_SHIFT 14
01788 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
01789 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
01790 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
01791 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16)
01792 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16
01793 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL
01794 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL
01795 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)
01796 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17)
01797 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17
01798 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL
01799 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL
01800 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)
01801 #define CMU_STATUS_USBCUSHFRCOSEL (0x1UL << 18)
01802 #define _CMU_STATUS_USBCUSHFRCOSEL_SHIFT 18
01803 #define _CMU_STATUS_USBCUSHFRCOSEL_MASK 0x40000UL
01804 #define _CMU_STATUS_USBCUSHFRCOSEL_DEFAULT 0x00000000UL
01805 #define CMU_STATUS_USBCUSHFRCOSEL_DEFAULT (_CMU_STATUS_USBCUSHFRCOSEL_DEFAULT << 18)
01806 #define CMU_STATUS_USBCHFCLKSYNC (0x1UL << 20)
01807 #define _CMU_STATUS_USBCHFCLKSYNC_SHIFT 20
01808 #define _CMU_STATUS_USBCHFCLKSYNC_MASK 0x100000UL
01809 #define _CMU_STATUS_USBCHFCLKSYNC_DEFAULT 0x00000000UL
01810 #define CMU_STATUS_USBCHFCLKSYNC_DEFAULT (_CMU_STATUS_USBCHFCLKSYNC_DEFAULT << 20)
01811 #define CMU_STATUS_USHFRCOENS (0x1UL << 21)
01812 #define _CMU_STATUS_USHFRCOENS_SHIFT 21
01813 #define _CMU_STATUS_USHFRCOENS_MASK 0x200000UL
01814 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL
01815 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 21)
01816 #define CMU_STATUS_USHFRCORDY (0x1UL << 22)
01817 #define _CMU_STATUS_USHFRCORDY_SHIFT 22
01818 #define _CMU_STATUS_USHFRCORDY_MASK 0x400000UL
01819 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL
01820 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 22)
01821 #define CMU_STATUS_USHFRCOSUSPEND (0x1UL << 23)
01822 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT 23
01823 #define _CMU_STATUS_USHFRCOSUSPEND_MASK 0x800000UL
01824 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT 0x00000000UL
01825 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23)
01826 #define CMU_STATUS_USHFRCODIV2SEL (0x1UL << 26)
01827 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT 26
01828 #define _CMU_STATUS_USHFRCODIV2SEL_MASK 0x4000000UL
01829 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT 0x00000000UL
01830 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26)
01832
01833 #define _CMU_IF_RESETVALUE 0x00000001UL
01834 #define _CMU_IF_MASK 0x0000037FUL
01835 #define CMU_IF_HFRCORDY (0x1UL << 0)
01836 #define _CMU_IF_HFRCORDY_SHIFT 0
01837 #define _CMU_IF_HFRCORDY_MASK 0x1UL
01838 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
01839 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
01840 #define CMU_IF_HFXORDY (0x1UL << 1)
01841 #define _CMU_IF_HFXORDY_SHIFT 1
01842 #define _CMU_IF_HFXORDY_MASK 0x2UL
01843 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
01844 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
01845 #define CMU_IF_LFRCORDY (0x1UL << 2)
01846 #define _CMU_IF_LFRCORDY_SHIFT 2
01847 #define _CMU_IF_LFRCORDY_MASK 0x4UL
01848 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
01849 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
01850 #define CMU_IF_LFXORDY (0x1UL << 3)
01851 #define _CMU_IF_LFXORDY_SHIFT 3
01852 #define _CMU_IF_LFXORDY_MASK 0x8UL
01853 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
01854 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
01855 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
01856 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
01857 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
01858 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
01859 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
01860 #define CMU_IF_CALRDY (0x1UL << 5)
01861 #define _CMU_IF_CALRDY_SHIFT 5
01862 #define _CMU_IF_CALRDY_MASK 0x20UL
01863 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
01864 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
01865 #define CMU_IF_CALOF (0x1UL << 6)
01866 #define _CMU_IF_CALOF_SHIFT 6
01867 #define _CMU_IF_CALOF_MASK 0x40UL
01868 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
01869 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
01870 #define CMU_IF_USHFRCORDY (0x1UL << 8)
01871 #define _CMU_IF_USHFRCORDY_SHIFT 8
01872 #define _CMU_IF_USHFRCORDY_MASK 0x100UL
01873 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL
01874 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 8)
01875 #define CMU_IF_USBCHFOSCSEL (0x1UL << 9)
01876 #define _CMU_IF_USBCHFOSCSEL_SHIFT 9
01877 #define _CMU_IF_USBCHFOSCSEL_MASK 0x200UL
01878 #define _CMU_IF_USBCHFOSCSEL_DEFAULT 0x00000000UL
01879 #define CMU_IF_USBCHFOSCSEL_DEFAULT (_CMU_IF_USBCHFOSCSEL_DEFAULT << 9)
01881
01882 #define _CMU_IFS_RESETVALUE 0x00000000UL
01883 #define _CMU_IFS_MASK 0x0000037FUL
01884 #define CMU_IFS_HFRCORDY (0x1UL << 0)
01885 #define _CMU_IFS_HFRCORDY_SHIFT 0
01886 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
01887 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
01888 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
01889 #define CMU_IFS_HFXORDY (0x1UL << 1)
01890 #define _CMU_IFS_HFXORDY_SHIFT 1
01891 #define _CMU_IFS_HFXORDY_MASK 0x2UL
01892 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
01893 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
01894 #define CMU_IFS_LFRCORDY (0x1UL << 2)
01895 #define _CMU_IFS_LFRCORDY_SHIFT 2
01896 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
01897 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
01898 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
01899 #define CMU_IFS_LFXORDY (0x1UL << 3)
01900 #define _CMU_IFS_LFXORDY_SHIFT 3
01901 #define _CMU_IFS_LFXORDY_MASK 0x8UL
01902 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
01903 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
01904 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
01905 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
01906 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
01907 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
01908 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
01909 #define CMU_IFS_CALRDY (0x1UL << 5)
01910 #define _CMU_IFS_CALRDY_SHIFT 5
01911 #define _CMU_IFS_CALRDY_MASK 0x20UL
01912 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
01913 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
01914 #define CMU_IFS_CALOF (0x1UL << 6)
01915 #define _CMU_IFS_CALOF_SHIFT 6
01916 #define _CMU_IFS_CALOF_MASK 0x40UL
01917 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
01918 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
01919 #define CMU_IFS_USHFRCORDY (0x1UL << 8)
01920 #define _CMU_IFS_USHFRCORDY_SHIFT 8
01921 #define _CMU_IFS_USHFRCORDY_MASK 0x100UL
01922 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL
01923 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 8)
01924 #define CMU_IFS_USBCHFOSCSEL (0x1UL << 9)
01925 #define _CMU_IFS_USBCHFOSCSEL_SHIFT 9
01926 #define _CMU_IFS_USBCHFOSCSEL_MASK 0x200UL
01927 #define _CMU_IFS_USBCHFOSCSEL_DEFAULT 0x00000000UL
01928 #define CMU_IFS_USBCHFOSCSEL_DEFAULT (_CMU_IFS_USBCHFOSCSEL_DEFAULT << 9)
01930
01931 #define _CMU_IFC_RESETVALUE 0x00000000UL
01932 #define _CMU_IFC_MASK 0x0000037FUL
01933 #define CMU_IFC_HFRCORDY (0x1UL << 0)
01934 #define _CMU_IFC_HFRCORDY_SHIFT 0
01935 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
01936 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
01937 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
01938 #define CMU_IFC_HFXORDY (0x1UL << 1)
01939 #define _CMU_IFC_HFXORDY_SHIFT 1
01940 #define _CMU_IFC_HFXORDY_MASK 0x2UL
01941 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
01942 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
01943 #define CMU_IFC_LFRCORDY (0x1UL << 2)
01944 #define _CMU_IFC_LFRCORDY_SHIFT 2
01945 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
01946 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
01947 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
01948 #define CMU_IFC_LFXORDY (0x1UL << 3)
01949 #define _CMU_IFC_LFXORDY_SHIFT 3
01950 #define _CMU_IFC_LFXORDY_MASK 0x8UL
01951 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
01952 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
01953 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
01954 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
01955 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
01956 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
01957 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
01958 #define CMU_IFC_CALRDY (0x1UL << 5)
01959 #define _CMU_IFC_CALRDY_SHIFT 5
01960 #define _CMU_IFC_CALRDY_MASK 0x20UL
01961 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
01962 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
01963 #define CMU_IFC_CALOF (0x1UL << 6)
01964 #define _CMU_IFC_CALOF_SHIFT 6
01965 #define _CMU_IFC_CALOF_MASK 0x40UL
01966 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
01967 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
01968 #define CMU_IFC_USHFRCORDY (0x1UL << 8)
01969 #define _CMU_IFC_USHFRCORDY_SHIFT 8
01970 #define _CMU_IFC_USHFRCORDY_MASK 0x100UL
01971 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL
01972 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 8)
01973 #define CMU_IFC_USBCHFOSCSEL (0x1UL << 9)
01974 #define _CMU_IFC_USBCHFOSCSEL_SHIFT 9
01975 #define _CMU_IFC_USBCHFOSCSEL_MASK 0x200UL
01976 #define _CMU_IFC_USBCHFOSCSEL_DEFAULT 0x00000000UL
01977 #define CMU_IFC_USBCHFOSCSEL_DEFAULT (_CMU_IFC_USBCHFOSCSEL_DEFAULT << 9)
01979
01980 #define _CMU_IEN_RESETVALUE 0x00000000UL
01981 #define _CMU_IEN_MASK 0x0000037FUL
01982 #define CMU_IEN_HFRCORDY (0x1UL << 0)
01983 #define _CMU_IEN_HFRCORDY_SHIFT 0
01984 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
01985 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
01986 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
01987 #define CMU_IEN_HFXORDY (0x1UL << 1)
01988 #define _CMU_IEN_HFXORDY_SHIFT 1
01989 #define _CMU_IEN_HFXORDY_MASK 0x2UL
01990 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
01991 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
01992 #define CMU_IEN_LFRCORDY (0x1UL << 2)
01993 #define _CMU_IEN_LFRCORDY_SHIFT 2
01994 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
01995 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
01996 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
01997 #define CMU_IEN_LFXORDY (0x1UL << 3)
01998 #define _CMU_IEN_LFXORDY_SHIFT 3
01999 #define _CMU_IEN_LFXORDY_MASK 0x8UL
02000 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
02001 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
02002 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
02003 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
02004 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
02005 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
02006 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
02007 #define CMU_IEN_CALRDY (0x1UL << 5)
02008 #define _CMU_IEN_CALRDY_SHIFT 5
02009 #define _CMU_IEN_CALRDY_MASK 0x20UL
02010 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
02011 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
02012 #define CMU_IEN_CALOF (0x1UL << 6)
02013 #define _CMU_IEN_CALOF_SHIFT 6
02014 #define _CMU_IEN_CALOF_MASK 0x40UL
02015 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
02016 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
02017 #define CMU_IEN_USHFRCORDY (0x1UL << 8)
02018 #define _CMU_IEN_USHFRCORDY_SHIFT 8
02019 #define _CMU_IEN_USHFRCORDY_MASK 0x100UL
02020 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL
02021 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 8)
02022 #define CMU_IEN_USBCHFOSCSEL (0x1UL << 9)
02023 #define _CMU_IEN_USBCHFOSCSEL_SHIFT 9
02024 #define _CMU_IEN_USBCHFOSCSEL_MASK 0x200UL
02025 #define _CMU_IEN_USBCHFOSCSEL_DEFAULT 0x00000000UL
02026 #define CMU_IEN_USBCHFOSCSEL_DEFAULT (_CMU_IEN_USBCHFOSCSEL_DEFAULT << 9)
02028
02029 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
02030 #define _CMU_HFCORECLKEN0_MASK 0x0000001EUL
02031 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
02032 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
02033 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
02034 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
02035 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
02036 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
02037 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
02038 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
02039 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
02040 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
02041 #define CMU_HFCORECLKEN0_USBC (0x1UL << 3)
02042 #define _CMU_HFCORECLKEN0_USBC_SHIFT 3
02043 #define _CMU_HFCORECLKEN0_USBC_MASK 0x8UL
02044 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL
02045 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 3)
02046 #define CMU_HFCORECLKEN0_USB (0x1UL << 4)
02047 #define _CMU_HFCORECLKEN0_USB_SHIFT 4
02048 #define _CMU_HFCORECLKEN0_USB_MASK 0x10UL
02049 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL
02050 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 4)
02052
02053 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
02054 #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL
02055 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0)
02056 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0
02057 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL
02058 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
02059 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)
02060 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1)
02061 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1
02062 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL
02063 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
02064 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)
02065 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2)
02066 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2
02067 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL
02068 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
02069 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2)
02070 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3)
02071 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3
02072 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL
02073 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
02074 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3)
02075 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4)
02076 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4
02077 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL
02078 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
02079 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4)
02080 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 5)
02081 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 5
02082 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x20UL
02083 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
02084 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5)
02085 #define CMU_HFPERCLKEN0_PRS (0x1UL << 6)
02086 #define _CMU_HFPERCLKEN0_PRS_SHIFT 6
02087 #define _CMU_HFPERCLKEN0_PRS_MASK 0x40UL
02088 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
02089 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6)
02090 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 7)
02091 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 7
02092 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x80UL
02093 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL
02094 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 7)
02095 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 8)
02096 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 8
02097 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x100UL
02098 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
02099 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8)
02100 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 9)
02101 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 9
02102 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x200UL
02103 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
02104 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9)
02105 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10)
02106 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 10
02107 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL
02108 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
02109 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10)
02110 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)
02111 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11
02112 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL
02113 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
02114 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
02116
02117 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
02118 #define _CMU_SYNCBUSY_MASK 0x00000155UL
02119 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
02120 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
02121 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
02122 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
02123 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
02124 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
02125 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
02126 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
02127 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
02128 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
02129 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
02130 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
02131 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
02132 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
02133 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
02134 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
02135 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
02136 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
02137 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
02138 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
02139 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8)
02140 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8
02141 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL
02142 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL
02143 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8)
02145
02146 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
02147 #define _CMU_FREEZE_MASK 0x00000001UL
02148 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
02149 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
02150 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
02151 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
02152 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
02153 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
02154 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
02155 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
02156 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
02158
02159 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
02160 #define _CMU_LFACLKEN0_MASK 0x00000001UL
02161 #define CMU_LFACLKEN0_RTC (0x1UL << 0)
02162 #define _CMU_LFACLKEN0_RTC_SHIFT 0
02163 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL
02164 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
02165 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
02167
02168 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
02169 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
02170 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
02171 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
02172 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
02173 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
02174 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
02176
02177 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL
02178 #define _CMU_LFCCLKEN0_MASK 0x00000001UL
02179 #define CMU_LFCCLKEN0_USBLE (0x1UL << 0)
02180 #define _CMU_LFCCLKEN0_USBLE_SHIFT 0
02181 #define _CMU_LFCCLKEN0_USBLE_MASK 0x1UL
02182 #define _CMU_LFCCLKEN0_USBLE_DEFAULT 0x00000000UL
02183 #define CMU_LFCCLKEN0_USBLE_DEFAULT (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0)
02185
02186 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
02187 #define _CMU_LFAPRESC0_MASK 0x0000000FUL
02188 #define _CMU_LFAPRESC0_RTC_SHIFT 0
02189 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL
02190 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
02191 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
02192 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
02193 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
02194 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
02195 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
02196 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
02197 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
02198 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
02199 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
02200 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
02201 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
02202 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
02203 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
02204 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
02205 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
02206 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
02207 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
02208 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
02209 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
02210 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
02211 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
02212 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
02213 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
02214 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
02215 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
02216 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
02217 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
02218 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
02219 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
02220 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
02221 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
02223
02224 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
02225 #define _CMU_LFBPRESC0_MASK 0x00000003UL
02226 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
02227 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
02228 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
02229 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
02230 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
02231 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
02232 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
02233 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
02234 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
02235 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
02237
02238 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
02239 #define _CMU_PCNTCTRL_MASK 0x00000003UL
02240 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
02241 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
02242 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
02243 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
02244 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
02245 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
02246 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
02247 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
02248 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
02249 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
02250 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
02251 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
02252 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
02253 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
02255
02256 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
02257 #define _CMU_ROUTE_MASK 0x0000001FUL
02258 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
02259 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
02260 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
02261 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
02262 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
02263 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
02264 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
02265 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
02266 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
02267 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
02268 #define _CMU_ROUTE_LOCATION_SHIFT 2
02269 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL
02270 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
02271 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
02272 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
02273 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL
02274 #define _CMU_ROUTE_LOCATION_LOC3 0x00000003UL
02275 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
02276 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
02277 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
02278 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)
02279 #define CMU_ROUTE_LOCATION_LOC3 (_CMU_ROUTE_LOCATION_LOC3 << 2)
02281
02282 #define _CMU_LOCK_RESETVALUE 0x00000000UL
02283 #define _CMU_LOCK_MASK 0x0000FFFFUL
02284 #define _CMU_LOCK_LOCKKEY_SHIFT 0
02285 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
02286 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
02287 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
02288 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
02289 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
02290 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
02291 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
02292 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
02293 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
02294 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
02295 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
02297
02298 #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL
02299 #define _CMU_USBCRCTRL_MASK 0x00000003UL
02300 #define CMU_USBCRCTRL_EN (0x1UL << 0)
02301 #define _CMU_USBCRCTRL_EN_SHIFT 0
02302 #define _CMU_USBCRCTRL_EN_MASK 0x1UL
02303 #define _CMU_USBCRCTRL_EN_DEFAULT 0x00000000UL
02304 #define CMU_USBCRCTRL_EN_DEFAULT (_CMU_USBCRCTRL_EN_DEFAULT << 0)
02305 #define CMU_USBCRCTRL_LSMODE (0x1UL << 1)
02306 #define _CMU_USBCRCTRL_LSMODE_SHIFT 1
02307 #define _CMU_USBCRCTRL_LSMODE_MASK 0x2UL
02308 #define _CMU_USBCRCTRL_LSMODE_DEFAULT 0x00000000UL
02309 #define CMU_USBCRCTRL_LSMODE_DEFAULT (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1)
02311
02312 #define _CMU_USHFRCOCTRL_RESETVALUE 0x000FF040UL
02313 #define _CMU_USHFRCOCTRL_MASK 0x000FF37FUL
02314 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0
02315 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL
02316 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x00000040UL
02317 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0)
02318 #define CMU_USHFRCOCTRL_DITHEN (0x1UL << 8)
02319 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT 8
02320 #define _CMU_USHFRCOCTRL_DITHEN_MASK 0x100UL
02321 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT 0x00000000UL
02322 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8)
02323 #define CMU_USHFRCOCTRL_SUSPEND (0x1UL << 9)
02324 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT 9
02325 #define _CMU_USHFRCOCTRL_SUSPEND_MASK 0x200UL
02326 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT 0x00000000UL
02327 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9)
02328 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT 12
02329 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK 0xFF000UL
02330 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT 0x000000FFUL
02331 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12)
02333
02334 #define _CMU_USHFRCOTUNE_RESETVALUE 0x00000020UL
02335 #define _CMU_USHFRCOTUNE_MASK 0x0000003FUL
02336 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT 0
02337 #define _CMU_USHFRCOTUNE_FINETUNING_MASK 0x3FUL
02338 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT 0x00000020UL
02339 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0)
02341
02342 #define _CMU_USHFRCOCONF_RESETVALUE 0x00000001UL
02343 #define _CMU_USHFRCOCONF_MASK 0x00000017UL
02344 #define _CMU_USHFRCOCONF_BAND_SHIFT 0
02345 #define _CMU_USHFRCOCONF_BAND_MASK 0x7UL
02346 #define _CMU_USHFRCOCONF_BAND_DEFAULT 0x00000001UL
02347 #define _CMU_USHFRCOCONF_BAND_48MHZ 0x00000001UL
02348 #define _CMU_USHFRCOCONF_BAND_24MHZ 0x00000003UL
02349 #define CMU_USHFRCOCONF_BAND_DEFAULT (_CMU_USHFRCOCONF_BAND_DEFAULT << 0)
02350 #define CMU_USHFRCOCONF_BAND_48MHZ (_CMU_USHFRCOCONF_BAND_48MHZ << 0)
02351 #define CMU_USHFRCOCONF_BAND_24MHZ (_CMU_USHFRCOCONF_BAND_24MHZ << 0)
02352 #define CMU_USHFRCOCONF_USHFRCODIV2DIS (0x1UL << 4)
02353 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT 4
02354 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK 0x10UL
02355 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT 0x00000000UL
02356 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4)
02362
02366 #define MSC_UNLOCK_CODE 0x1B71
02367 #define EMU_UNLOCK_CODE 0xADE8
02368 #define CMU_UNLOCK_CODE 0x580E
02369 #define TIMER_UNLOCK_CODE 0xCE80
02370 #define GPIO_UNLOCK_CODE 0xA534
02376
02381 #include "efm32hg_af_ports.h"
02382 #include "efm32hg_af_pins.h"
02383
02386
02399 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02400 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02401
02406 #ifdef __cplusplus
02407 }
02408 #endif
02409 #endif