00001
00032
00037 typedef struct
00038 {
00039 __IO uint32_t CTRL;
00040 __IO uint32_t HFCORECLKDIV;
00041 __IO uint32_t HFPERCLKDIV;
00042 __IO uint32_t HFRCOCTRL;
00043 __IO uint32_t LFRCOCTRL;
00044 __IO uint32_t AUXHFRCOCTRL;
00045 __IO uint32_t CALCTRL;
00046 __IO uint32_t CALCNT;
00047 __IO uint32_t OSCENCMD;
00048 __IO uint32_t CMD;
00049 __IO uint32_t LFCLKSEL;
00050 __I uint32_t STATUS;
00051 __I uint32_t IF;
00052 __IO uint32_t IFS;
00053 __IO uint32_t IFC;
00054 __IO uint32_t IEN;
00055 __IO uint32_t HFCORECLKEN0;
00056 __IO uint32_t HFPERCLKEN0;
00057 uint32_t RESERVED0[2];
00058 __I uint32_t SYNCBUSY;
00059 __IO uint32_t FREEZE;
00060 __IO uint32_t LFACLKEN0;
00061 uint32_t RESERVED1[1];
00062 __IO uint32_t LFBCLKEN0;
00063 __IO uint32_t LFCCLKEN0;
00064 __IO uint32_t LFAPRESC0;
00065 uint32_t RESERVED2[1];
00066 __IO uint32_t LFBPRESC0;
00067 uint32_t RESERVED3[1];
00068 __IO uint32_t PCNTCTRL;
00070 uint32_t RESERVED4[1];
00071 __IO uint32_t ROUTE;
00072 __IO uint32_t LOCK;
00074 uint32_t RESERVED5[18];
00075 __IO uint32_t USBCRCTRL;
00076 __IO uint32_t USHFRCOCTRL;
00077 __IO uint32_t USHFRCOTUNE;
00078 __IO uint32_t USHFRCOCONF;
00079 } CMU_TypeDef;
00081
00086
00087 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
00088 #define _CMU_CTRL_MASK 0x07FFFEEFUL
00089 #define _CMU_CTRL_HFXOMODE_SHIFT 0
00090 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
00091 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
00092 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
00093 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
00094 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
00095 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
00096 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
00097 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
00098 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
00099 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
00100 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
00101 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
00102 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
00103 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
00104 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
00105 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
00106 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
00107 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
00108 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
00109 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
00110 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
00111 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
00112 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
00113 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
00114 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
00115 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
00116 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
00117 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
00118 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
00119 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
00120 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
00121 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
00122 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
00123 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
00124 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
00125 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
00126 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
00127 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
00128 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
00129 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
00130 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
00131 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
00132 #define _CMU_CTRL_LFXOMODE_SHIFT 11
00133 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
00134 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
00135 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
00136 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
00137 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
00138 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
00139 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
00140 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
00141 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
00142 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
00143 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
00144 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
00145 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
00146 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
00147 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
00148 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
00149 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
00150 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
00151 #define _CMU_CTRL_HFCLKDIV_SHIFT 14
00152 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL
00153 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL
00154 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14)
00155 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
00156 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
00157 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
00158 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
00159 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
00160 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
00161 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
00162 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
00163 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
00164 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
00165 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
00166 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
00167 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
00168 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
00169 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
00170 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
00171 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
00172 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
00173 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
00174 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
00175 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
00176 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
00177 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
00178 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
00179 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
00180 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
00181 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
00182 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL
00183 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
00184 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
00185 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
00186 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
00187 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
00188 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
00189 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
00190 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
00191 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
00192 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
00193 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL
00194 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
00195 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
00196 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
00197 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL
00198 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL
00199 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL
00200 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL
00201 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL
00202 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL
00203 #define _CMU_CTRL_CLKOUTSEL1_USHFRCO 0x00000008UL
00204 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
00205 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
00206 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
00207 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
00208 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
00209 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
00210 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
00211 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
00212 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
00213 #define CMU_CTRL_CLKOUTSEL1_USHFRCO (_CMU_CTRL_CLKOUTSEL1_USHFRCO << 23)
00215
00216 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
00217 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL
00218 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
00219 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
00220 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
00221 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
00222 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
00223 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
00224 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
00225 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
00226 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
00227 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
00228 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
00229 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
00230 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
00231 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
00232 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
00233 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
00234 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
00235 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
00236 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
00237 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
00238 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
00239 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
00240 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
00241 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
00242 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8)
00243 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8
00244 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL
00245 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL
00246 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL
00247 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL
00248 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8)
00249 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)
00250 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)
00252
00253 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
00254 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
00255 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
00256 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
00257 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
00258 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
00259 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
00260 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
00261 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
00262 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
00263 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
00264 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
00265 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
00266 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
00267 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
00268 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
00269 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
00270 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
00271 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
00272 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
00273 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
00274 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
00275 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
00276 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
00277 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
00278 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
00279 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
00280 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
00281 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
00282 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
00283 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
00285
00286 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
00287 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
00288 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
00289 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
00290 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00291 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
00292 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
00293 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
00294 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
00295 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
00296 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
00297 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
00298 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
00299 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
00300 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
00301 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
00302 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
00303 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
00304 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
00305 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
00306 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
00307 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
00308 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
00309 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
00311
00312 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
00313 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
00314 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
00315 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
00316 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
00317 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
00319
00320 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
00321 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL
00322 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
00323 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
00324 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00325 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
00326 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8
00327 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL
00328 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL
00329 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL
00330 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL
00331 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL
00332 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL
00333 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL
00334 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
00335 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
00336 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
00337 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
00338 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
00339 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
00341
00342 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
00343 #define _CMU_CALCTRL_MASK 0x0000007FUL
00344 #define _CMU_CALCTRL_UPSEL_SHIFT 0
00345 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
00346 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
00347 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
00348 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
00349 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
00350 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
00351 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
00352 #define _CMU_CALCTRL_UPSEL_USHFRCO 0x00000005UL
00353 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
00354 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
00355 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
00356 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
00357 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
00358 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
00359 #define CMU_CALCTRL_UPSEL_USHFRCO (_CMU_CALCTRL_UPSEL_USHFRCO << 0)
00360 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3
00361 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL
00362 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
00363 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
00364 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
00365 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
00366 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
00367 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
00368 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
00369 #define _CMU_CALCTRL_DOWNSEL_USHFRCO 0x00000006UL
00370 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
00371 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
00372 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
00373 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
00374 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
00375 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
00376 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
00377 #define CMU_CALCTRL_DOWNSEL_USHFRCO (_CMU_CALCTRL_DOWNSEL_USHFRCO << 3)
00378 #define CMU_CALCTRL_CONT (0x1UL << 6)
00379 #define _CMU_CALCTRL_CONT_SHIFT 6
00380 #define _CMU_CALCTRL_CONT_MASK 0x40UL
00381 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
00382 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)
00384
00385 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
00386 #define _CMU_CALCNT_MASK 0x000FFFFFUL
00387 #define _CMU_CALCNT_CALCNT_SHIFT 0
00388 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
00389 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
00390 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
00392
00393 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
00394 #define _CMU_OSCENCMD_MASK 0x00000FFFUL
00395 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
00396 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
00397 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
00398 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
00399 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
00400 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
00401 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
00402 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
00403 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
00404 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
00405 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
00406 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
00407 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
00408 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
00409 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
00410 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
00411 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
00412 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
00413 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
00414 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
00415 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
00416 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
00417 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
00418 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
00419 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
00420 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
00421 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
00422 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
00423 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
00424 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
00425 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
00426 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
00427 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
00428 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
00429 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
00430 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
00431 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
00432 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
00433 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
00434 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
00435 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
00436 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
00437 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
00438 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
00439 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
00440 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
00441 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
00442 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
00443 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
00444 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
00445 #define CMU_OSCENCMD_USHFRCOEN (0x1UL << 10)
00446 #define _CMU_OSCENCMD_USHFRCOEN_SHIFT 10
00447 #define _CMU_OSCENCMD_USHFRCOEN_MASK 0x400UL
00448 #define _CMU_OSCENCMD_USHFRCOEN_DEFAULT 0x00000000UL
00449 #define CMU_OSCENCMD_USHFRCOEN_DEFAULT (_CMU_OSCENCMD_USHFRCOEN_DEFAULT << 10)
00450 #define CMU_OSCENCMD_USHFRCODIS (0x1UL << 11)
00451 #define _CMU_OSCENCMD_USHFRCODIS_SHIFT 11
00452 #define _CMU_OSCENCMD_USHFRCODIS_MASK 0x800UL
00453 #define _CMU_OSCENCMD_USHFRCODIS_DEFAULT 0x00000000UL
00454 #define CMU_OSCENCMD_USHFRCODIS_DEFAULT (_CMU_OSCENCMD_USHFRCODIS_DEFAULT << 11)
00456
00457 #define _CMU_CMD_RESETVALUE 0x00000000UL
00458 #define _CMU_CMD_MASK 0x000000FFUL
00459 #define _CMU_CMD_HFCLKSEL_SHIFT 0
00460 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
00461 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
00462 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
00463 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
00464 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
00465 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
00466 #define _CMU_CMD_HFCLKSEL_USHFRCODIV2 0x00000005UL
00467 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
00468 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
00469 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
00470 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
00471 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
00472 #define CMU_CMD_HFCLKSEL_USHFRCODIV2 (_CMU_CMD_HFCLKSEL_USHFRCODIV2 << 0)
00473 #define CMU_CMD_CALSTART (0x1UL << 3)
00474 #define _CMU_CMD_CALSTART_SHIFT 3
00475 #define _CMU_CMD_CALSTART_MASK 0x8UL
00476 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
00477 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
00478 #define CMU_CMD_CALSTOP (0x1UL << 4)
00479 #define _CMU_CMD_CALSTOP_SHIFT 4
00480 #define _CMU_CMD_CALSTOP_MASK 0x10UL
00481 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
00482 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)
00483 #define _CMU_CMD_USBCCLKSEL_SHIFT 5
00484 #define _CMU_CMD_USBCCLKSEL_MASK 0xE0UL
00485 #define _CMU_CMD_USBCCLKSEL_DEFAULT 0x00000000UL
00486 #define _CMU_CMD_USBCCLKSEL_LFXO 0x00000002UL
00487 #define _CMU_CMD_USBCCLKSEL_LFRCO 0x00000003UL
00488 #define _CMU_CMD_USBCCLKSEL_USHFRCO 0x00000004UL
00489 #define CMU_CMD_USBCCLKSEL_DEFAULT (_CMU_CMD_USBCCLKSEL_DEFAULT << 5)
00490 #define CMU_CMD_USBCCLKSEL_LFXO (_CMU_CMD_USBCCLKSEL_LFXO << 5)
00491 #define CMU_CMD_USBCCLKSEL_LFRCO (_CMU_CMD_USBCCLKSEL_LFRCO << 5)
00492 #define CMU_CMD_USBCCLKSEL_USHFRCO (_CMU_CMD_USBCCLKSEL_USHFRCO << 5)
00494
00495 #define _CMU_LFCLKSEL_RESETVALUE 0x00000015UL
00496 #define _CMU_LFCLKSEL_MASK 0x0011003FUL
00497 #define _CMU_LFCLKSEL_LFA_SHIFT 0
00498 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
00499 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
00500 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
00501 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
00502 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
00503 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
00504 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
00505 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
00506 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
00507 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
00508 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
00509 #define _CMU_LFCLKSEL_LFB_SHIFT 2
00510 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
00511 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
00512 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
00513 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
00514 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
00515 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
00516 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
00517 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
00518 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
00519 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
00520 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
00521 #define _CMU_LFCLKSEL_LFC_SHIFT 4
00522 #define _CMU_LFCLKSEL_LFC_MASK 0x30UL
00523 #define _CMU_LFCLKSEL_LFC_DISABLED 0x00000000UL
00524 #define _CMU_LFCLKSEL_LFC_DEFAULT 0x00000001UL
00525 #define _CMU_LFCLKSEL_LFC_LFRCO 0x00000001UL
00526 #define _CMU_LFCLKSEL_LFC_LFXO 0x00000002UL
00527 #define CMU_LFCLKSEL_LFC_DISABLED (_CMU_LFCLKSEL_LFC_DISABLED << 4)
00528 #define CMU_LFCLKSEL_LFC_DEFAULT (_CMU_LFCLKSEL_LFC_DEFAULT << 4)
00529 #define CMU_LFCLKSEL_LFC_LFRCO (_CMU_LFCLKSEL_LFC_LFRCO << 4)
00530 #define CMU_LFCLKSEL_LFC_LFXO (_CMU_LFCLKSEL_LFC_LFXO << 4)
00531 #define CMU_LFCLKSEL_LFAE (0x1UL << 16)
00532 #define _CMU_LFCLKSEL_LFAE_SHIFT 16
00533 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL
00534 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL
00535 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL
00536 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL
00537 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
00538 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
00539 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
00540 #define CMU_LFCLKSEL_LFBE (0x1UL << 20)
00541 #define _CMU_LFCLKSEL_LFBE_SHIFT 20
00542 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL
00543 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL
00544 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL
00545 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL
00546 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
00547 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
00548 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
00550
00551 #define _CMU_STATUS_RESETVALUE 0x00000403UL
00552 #define _CMU_STATUS_MASK 0x04F77FFFUL
00553 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
00554 #define _CMU_STATUS_HFRCOENS_SHIFT 0
00555 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
00556 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
00557 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
00558 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
00559 #define _CMU_STATUS_HFRCORDY_SHIFT 1
00560 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
00561 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
00562 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
00563 #define CMU_STATUS_HFXOENS (0x1UL << 2)
00564 #define _CMU_STATUS_HFXOENS_SHIFT 2
00565 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
00566 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
00567 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
00568 #define CMU_STATUS_HFXORDY (0x1UL << 3)
00569 #define _CMU_STATUS_HFXORDY_SHIFT 3
00570 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
00571 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
00572 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
00573 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
00574 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
00575 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
00576 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
00577 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
00578 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
00579 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
00580 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
00581 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
00582 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
00583 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
00584 #define _CMU_STATUS_LFRCOENS_SHIFT 6
00585 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
00586 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
00587 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
00588 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
00589 #define _CMU_STATUS_LFRCORDY_SHIFT 7
00590 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
00591 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
00592 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
00593 #define CMU_STATUS_LFXOENS (0x1UL << 8)
00594 #define _CMU_STATUS_LFXOENS_SHIFT 8
00595 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
00596 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
00597 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
00598 #define CMU_STATUS_LFXORDY (0x1UL << 9)
00599 #define _CMU_STATUS_LFXORDY_SHIFT 9
00600 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
00601 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
00602 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
00603 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
00604 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
00605 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
00606 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
00607 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
00608 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
00609 #define _CMU_STATUS_HFXOSEL_SHIFT 11
00610 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
00611 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
00612 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
00613 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
00614 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
00615 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
00616 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
00617 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
00618 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
00619 #define _CMU_STATUS_LFXOSEL_SHIFT 13
00620 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
00621 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
00622 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
00623 #define CMU_STATUS_CALBSY (0x1UL << 14)
00624 #define _CMU_STATUS_CALBSY_SHIFT 14
00625 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
00626 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
00627 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
00628 #define CMU_STATUS_USBCLFXOSEL (0x1UL << 16)
00629 #define _CMU_STATUS_USBCLFXOSEL_SHIFT 16
00630 #define _CMU_STATUS_USBCLFXOSEL_MASK 0x10000UL
00631 #define _CMU_STATUS_USBCLFXOSEL_DEFAULT 0x00000000UL
00632 #define CMU_STATUS_USBCLFXOSEL_DEFAULT (_CMU_STATUS_USBCLFXOSEL_DEFAULT << 16)
00633 #define CMU_STATUS_USBCLFRCOSEL (0x1UL << 17)
00634 #define _CMU_STATUS_USBCLFRCOSEL_SHIFT 17
00635 #define _CMU_STATUS_USBCLFRCOSEL_MASK 0x20000UL
00636 #define _CMU_STATUS_USBCLFRCOSEL_DEFAULT 0x00000000UL
00637 #define CMU_STATUS_USBCLFRCOSEL_DEFAULT (_CMU_STATUS_USBCLFRCOSEL_DEFAULT << 17)
00638 #define CMU_STATUS_USBCUSHFRCOSEL (0x1UL << 18)
00639 #define _CMU_STATUS_USBCUSHFRCOSEL_SHIFT 18
00640 #define _CMU_STATUS_USBCUSHFRCOSEL_MASK 0x40000UL
00641 #define _CMU_STATUS_USBCUSHFRCOSEL_DEFAULT 0x00000000UL
00642 #define CMU_STATUS_USBCUSHFRCOSEL_DEFAULT (_CMU_STATUS_USBCUSHFRCOSEL_DEFAULT << 18)
00643 #define CMU_STATUS_USBCHFCLKSYNC (0x1UL << 20)
00644 #define _CMU_STATUS_USBCHFCLKSYNC_SHIFT 20
00645 #define _CMU_STATUS_USBCHFCLKSYNC_MASK 0x100000UL
00646 #define _CMU_STATUS_USBCHFCLKSYNC_DEFAULT 0x00000000UL
00647 #define CMU_STATUS_USBCHFCLKSYNC_DEFAULT (_CMU_STATUS_USBCHFCLKSYNC_DEFAULT << 20)
00648 #define CMU_STATUS_USHFRCOENS (0x1UL << 21)
00649 #define _CMU_STATUS_USHFRCOENS_SHIFT 21
00650 #define _CMU_STATUS_USHFRCOENS_MASK 0x200000UL
00651 #define _CMU_STATUS_USHFRCOENS_DEFAULT 0x00000000UL
00652 #define CMU_STATUS_USHFRCOENS_DEFAULT (_CMU_STATUS_USHFRCOENS_DEFAULT << 21)
00653 #define CMU_STATUS_USHFRCORDY (0x1UL << 22)
00654 #define _CMU_STATUS_USHFRCORDY_SHIFT 22
00655 #define _CMU_STATUS_USHFRCORDY_MASK 0x400000UL
00656 #define _CMU_STATUS_USHFRCORDY_DEFAULT 0x00000000UL
00657 #define CMU_STATUS_USHFRCORDY_DEFAULT (_CMU_STATUS_USHFRCORDY_DEFAULT << 22)
00658 #define CMU_STATUS_USHFRCOSUSPEND (0x1UL << 23)
00659 #define _CMU_STATUS_USHFRCOSUSPEND_SHIFT 23
00660 #define _CMU_STATUS_USHFRCOSUSPEND_MASK 0x800000UL
00661 #define _CMU_STATUS_USHFRCOSUSPEND_DEFAULT 0x00000000UL
00662 #define CMU_STATUS_USHFRCOSUSPEND_DEFAULT (_CMU_STATUS_USHFRCOSUSPEND_DEFAULT << 23)
00663 #define CMU_STATUS_USHFRCODIV2SEL (0x1UL << 26)
00664 #define _CMU_STATUS_USHFRCODIV2SEL_SHIFT 26
00665 #define _CMU_STATUS_USHFRCODIV2SEL_MASK 0x4000000UL
00666 #define _CMU_STATUS_USHFRCODIV2SEL_DEFAULT 0x00000000UL
00667 #define CMU_STATUS_USHFRCODIV2SEL_DEFAULT (_CMU_STATUS_USHFRCODIV2SEL_DEFAULT << 26)
00669
00670 #define _CMU_IF_RESETVALUE 0x00000001UL
00671 #define _CMU_IF_MASK 0x0000037FUL
00672 #define CMU_IF_HFRCORDY (0x1UL << 0)
00673 #define _CMU_IF_HFRCORDY_SHIFT 0
00674 #define _CMU_IF_HFRCORDY_MASK 0x1UL
00675 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
00676 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
00677 #define CMU_IF_HFXORDY (0x1UL << 1)
00678 #define _CMU_IF_HFXORDY_SHIFT 1
00679 #define _CMU_IF_HFXORDY_MASK 0x2UL
00680 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
00681 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
00682 #define CMU_IF_LFRCORDY (0x1UL << 2)
00683 #define _CMU_IF_LFRCORDY_SHIFT 2
00684 #define _CMU_IF_LFRCORDY_MASK 0x4UL
00685 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
00686 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
00687 #define CMU_IF_LFXORDY (0x1UL << 3)
00688 #define _CMU_IF_LFXORDY_SHIFT 3
00689 #define _CMU_IF_LFXORDY_MASK 0x8UL
00690 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
00691 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
00692 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
00693 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
00694 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
00695 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
00696 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
00697 #define CMU_IF_CALRDY (0x1UL << 5)
00698 #define _CMU_IF_CALRDY_SHIFT 5
00699 #define _CMU_IF_CALRDY_MASK 0x20UL
00700 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
00701 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
00702 #define CMU_IF_CALOF (0x1UL << 6)
00703 #define _CMU_IF_CALOF_SHIFT 6
00704 #define _CMU_IF_CALOF_MASK 0x40UL
00705 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
00706 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
00707 #define CMU_IF_USHFRCORDY (0x1UL << 8)
00708 #define _CMU_IF_USHFRCORDY_SHIFT 8
00709 #define _CMU_IF_USHFRCORDY_MASK 0x100UL
00710 #define _CMU_IF_USHFRCORDY_DEFAULT 0x00000000UL
00711 #define CMU_IF_USHFRCORDY_DEFAULT (_CMU_IF_USHFRCORDY_DEFAULT << 8)
00712 #define CMU_IF_USBCHFOSCSEL (0x1UL << 9)
00713 #define _CMU_IF_USBCHFOSCSEL_SHIFT 9
00714 #define _CMU_IF_USBCHFOSCSEL_MASK 0x200UL
00715 #define _CMU_IF_USBCHFOSCSEL_DEFAULT 0x00000000UL
00716 #define CMU_IF_USBCHFOSCSEL_DEFAULT (_CMU_IF_USBCHFOSCSEL_DEFAULT << 9)
00718
00719 #define _CMU_IFS_RESETVALUE 0x00000000UL
00720 #define _CMU_IFS_MASK 0x0000037FUL
00721 #define CMU_IFS_HFRCORDY (0x1UL << 0)
00722 #define _CMU_IFS_HFRCORDY_SHIFT 0
00723 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
00724 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
00725 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
00726 #define CMU_IFS_HFXORDY (0x1UL << 1)
00727 #define _CMU_IFS_HFXORDY_SHIFT 1
00728 #define _CMU_IFS_HFXORDY_MASK 0x2UL
00729 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
00730 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
00731 #define CMU_IFS_LFRCORDY (0x1UL << 2)
00732 #define _CMU_IFS_LFRCORDY_SHIFT 2
00733 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
00734 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
00735 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
00736 #define CMU_IFS_LFXORDY (0x1UL << 3)
00737 #define _CMU_IFS_LFXORDY_SHIFT 3
00738 #define _CMU_IFS_LFXORDY_MASK 0x8UL
00739 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
00740 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
00741 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
00742 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
00743 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
00744 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
00745 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
00746 #define CMU_IFS_CALRDY (0x1UL << 5)
00747 #define _CMU_IFS_CALRDY_SHIFT 5
00748 #define _CMU_IFS_CALRDY_MASK 0x20UL
00749 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
00750 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
00751 #define CMU_IFS_CALOF (0x1UL << 6)
00752 #define _CMU_IFS_CALOF_SHIFT 6
00753 #define _CMU_IFS_CALOF_MASK 0x40UL
00754 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
00755 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
00756 #define CMU_IFS_USHFRCORDY (0x1UL << 8)
00757 #define _CMU_IFS_USHFRCORDY_SHIFT 8
00758 #define _CMU_IFS_USHFRCORDY_MASK 0x100UL
00759 #define _CMU_IFS_USHFRCORDY_DEFAULT 0x00000000UL
00760 #define CMU_IFS_USHFRCORDY_DEFAULT (_CMU_IFS_USHFRCORDY_DEFAULT << 8)
00761 #define CMU_IFS_USBCHFOSCSEL (0x1UL << 9)
00762 #define _CMU_IFS_USBCHFOSCSEL_SHIFT 9
00763 #define _CMU_IFS_USBCHFOSCSEL_MASK 0x200UL
00764 #define _CMU_IFS_USBCHFOSCSEL_DEFAULT 0x00000000UL
00765 #define CMU_IFS_USBCHFOSCSEL_DEFAULT (_CMU_IFS_USBCHFOSCSEL_DEFAULT << 9)
00767
00768 #define _CMU_IFC_RESETVALUE 0x00000000UL
00769 #define _CMU_IFC_MASK 0x0000037FUL
00770 #define CMU_IFC_HFRCORDY (0x1UL << 0)
00771 #define _CMU_IFC_HFRCORDY_SHIFT 0
00772 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
00773 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
00774 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
00775 #define CMU_IFC_HFXORDY (0x1UL << 1)
00776 #define _CMU_IFC_HFXORDY_SHIFT 1
00777 #define _CMU_IFC_HFXORDY_MASK 0x2UL
00778 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
00779 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
00780 #define CMU_IFC_LFRCORDY (0x1UL << 2)
00781 #define _CMU_IFC_LFRCORDY_SHIFT 2
00782 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
00783 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
00784 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
00785 #define CMU_IFC_LFXORDY (0x1UL << 3)
00786 #define _CMU_IFC_LFXORDY_SHIFT 3
00787 #define _CMU_IFC_LFXORDY_MASK 0x8UL
00788 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
00789 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
00790 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
00791 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
00792 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
00793 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
00794 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
00795 #define CMU_IFC_CALRDY (0x1UL << 5)
00796 #define _CMU_IFC_CALRDY_SHIFT 5
00797 #define _CMU_IFC_CALRDY_MASK 0x20UL
00798 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
00799 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
00800 #define CMU_IFC_CALOF (0x1UL << 6)
00801 #define _CMU_IFC_CALOF_SHIFT 6
00802 #define _CMU_IFC_CALOF_MASK 0x40UL
00803 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
00804 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
00805 #define CMU_IFC_USHFRCORDY (0x1UL << 8)
00806 #define _CMU_IFC_USHFRCORDY_SHIFT 8
00807 #define _CMU_IFC_USHFRCORDY_MASK 0x100UL
00808 #define _CMU_IFC_USHFRCORDY_DEFAULT 0x00000000UL
00809 #define CMU_IFC_USHFRCORDY_DEFAULT (_CMU_IFC_USHFRCORDY_DEFAULT << 8)
00810 #define CMU_IFC_USBCHFOSCSEL (0x1UL << 9)
00811 #define _CMU_IFC_USBCHFOSCSEL_SHIFT 9
00812 #define _CMU_IFC_USBCHFOSCSEL_MASK 0x200UL
00813 #define _CMU_IFC_USBCHFOSCSEL_DEFAULT 0x00000000UL
00814 #define CMU_IFC_USBCHFOSCSEL_DEFAULT (_CMU_IFC_USBCHFOSCSEL_DEFAULT << 9)
00816
00817 #define _CMU_IEN_RESETVALUE 0x00000000UL
00818 #define _CMU_IEN_MASK 0x0000037FUL
00819 #define CMU_IEN_HFRCORDY (0x1UL << 0)
00820 #define _CMU_IEN_HFRCORDY_SHIFT 0
00821 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
00822 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
00823 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
00824 #define CMU_IEN_HFXORDY (0x1UL << 1)
00825 #define _CMU_IEN_HFXORDY_SHIFT 1
00826 #define _CMU_IEN_HFXORDY_MASK 0x2UL
00827 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
00828 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
00829 #define CMU_IEN_LFRCORDY (0x1UL << 2)
00830 #define _CMU_IEN_LFRCORDY_SHIFT 2
00831 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
00832 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
00833 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
00834 #define CMU_IEN_LFXORDY (0x1UL << 3)
00835 #define _CMU_IEN_LFXORDY_SHIFT 3
00836 #define _CMU_IEN_LFXORDY_MASK 0x8UL
00837 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
00838 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
00839 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
00840 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
00841 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
00842 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
00843 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
00844 #define CMU_IEN_CALRDY (0x1UL << 5)
00845 #define _CMU_IEN_CALRDY_SHIFT 5
00846 #define _CMU_IEN_CALRDY_MASK 0x20UL
00847 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
00848 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
00849 #define CMU_IEN_CALOF (0x1UL << 6)
00850 #define _CMU_IEN_CALOF_SHIFT 6
00851 #define _CMU_IEN_CALOF_MASK 0x40UL
00852 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
00853 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
00854 #define CMU_IEN_USHFRCORDY (0x1UL << 8)
00855 #define _CMU_IEN_USHFRCORDY_SHIFT 8
00856 #define _CMU_IEN_USHFRCORDY_MASK 0x100UL
00857 #define _CMU_IEN_USHFRCORDY_DEFAULT 0x00000000UL
00858 #define CMU_IEN_USHFRCORDY_DEFAULT (_CMU_IEN_USHFRCORDY_DEFAULT << 8)
00859 #define CMU_IEN_USBCHFOSCSEL (0x1UL << 9)
00860 #define _CMU_IEN_USBCHFOSCSEL_SHIFT 9
00861 #define _CMU_IEN_USBCHFOSCSEL_MASK 0x200UL
00862 #define _CMU_IEN_USBCHFOSCSEL_DEFAULT 0x00000000UL
00863 #define CMU_IEN_USBCHFOSCSEL_DEFAULT (_CMU_IEN_USBCHFOSCSEL_DEFAULT << 9)
00865
00866 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
00867 #define _CMU_HFCORECLKEN0_MASK 0x0000001FUL
00868 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
00869 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
00870 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
00871 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
00872 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
00873 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
00874 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
00875 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
00876 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
00877 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
00878 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
00879 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
00880 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
00881 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
00882 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
00883 #define CMU_HFCORECLKEN0_USBC (0x1UL << 3)
00884 #define _CMU_HFCORECLKEN0_USBC_SHIFT 3
00885 #define _CMU_HFCORECLKEN0_USBC_MASK 0x8UL
00886 #define _CMU_HFCORECLKEN0_USBC_DEFAULT 0x00000000UL
00887 #define CMU_HFCORECLKEN0_USBC_DEFAULT (_CMU_HFCORECLKEN0_USBC_DEFAULT << 3)
00888 #define CMU_HFCORECLKEN0_USB (0x1UL << 4)
00889 #define _CMU_HFCORECLKEN0_USB_SHIFT 4
00890 #define _CMU_HFCORECLKEN0_USB_MASK 0x10UL
00891 #define _CMU_HFCORECLKEN0_USB_DEFAULT 0x00000000UL
00892 #define CMU_HFCORECLKEN0_USB_DEFAULT (_CMU_HFCORECLKEN0_USB_DEFAULT << 4)
00894
00895 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
00896 #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL
00897 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 0)
00898 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 0
00899 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x1UL
00900 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
00901 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0)
00902 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 1)
00903 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 1
00904 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x2UL
00905 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
00906 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1)
00907 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 2)
00908 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 2
00909 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x4UL
00910 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL
00911 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 2)
00912 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 3)
00913 #define _CMU_HFPERCLKEN0_USART0_SHIFT 3
00914 #define _CMU_HFPERCLKEN0_USART0_MASK 0x8UL
00915 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
00916 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 3)
00917 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 4)
00918 #define _CMU_HFPERCLKEN0_USART1_SHIFT 4
00919 #define _CMU_HFPERCLKEN0_USART1_MASK 0x10UL
00920 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
00921 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 4)
00922 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 5)
00923 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 5
00924 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x20UL
00925 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
00926 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 5)
00927 #define CMU_HFPERCLKEN0_PRS (0x1UL << 6)
00928 #define _CMU_HFPERCLKEN0_PRS_SHIFT 6
00929 #define _CMU_HFPERCLKEN0_PRS_MASK 0x40UL
00930 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
00931 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 6)
00932 #define CMU_HFPERCLKEN0_IDAC0 (0x1UL << 7)
00933 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT 7
00934 #define _CMU_HFPERCLKEN0_IDAC0_MASK 0x80UL
00935 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT 0x00000000UL
00936 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 7)
00937 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 8)
00938 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 8
00939 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x100UL
00940 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
00941 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 8)
00942 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 9)
00943 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 9
00944 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x200UL
00945 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
00946 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 9)
00947 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 10)
00948 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 10
00949 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x400UL
00950 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
00951 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10)
00952 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)
00953 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11
00954 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL
00955 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
00956 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
00958
00959 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
00960 #define _CMU_SYNCBUSY_MASK 0x00000155UL
00961 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
00962 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
00963 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
00964 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
00965 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
00966 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
00967 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
00968 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
00969 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
00970 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
00971 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
00972 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
00973 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
00974 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
00975 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
00976 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
00977 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
00978 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
00979 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
00980 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
00981 #define CMU_SYNCBUSY_LFCCLKEN0 (0x1UL << 8)
00982 #define _CMU_SYNCBUSY_LFCCLKEN0_SHIFT 8
00983 #define _CMU_SYNCBUSY_LFCCLKEN0_MASK 0x100UL
00984 #define _CMU_SYNCBUSY_LFCCLKEN0_DEFAULT 0x00000000UL
00985 #define CMU_SYNCBUSY_LFCCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFCCLKEN0_DEFAULT << 8)
00987
00988 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
00989 #define _CMU_FREEZE_MASK 0x00000001UL
00990 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
00991 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
00992 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
00993 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
00994 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
00995 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
00996 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
00997 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
00998 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
01000
01001 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
01002 #define _CMU_LFACLKEN0_MASK 0x00000001UL
01003 #define CMU_LFACLKEN0_RTC (0x1UL << 0)
01004 #define _CMU_LFACLKEN0_RTC_SHIFT 0
01005 #define _CMU_LFACLKEN0_RTC_MASK 0x1UL
01006 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
01007 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 0)
01009
01010 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
01011 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
01012 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
01013 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
01014 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
01015 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
01016 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
01018
01019 #define _CMU_LFCCLKEN0_RESETVALUE 0x00000000UL
01020 #define _CMU_LFCCLKEN0_MASK 0x00000001UL
01021 #define CMU_LFCCLKEN0_USBLE (0x1UL << 0)
01022 #define _CMU_LFCCLKEN0_USBLE_SHIFT 0
01023 #define _CMU_LFCCLKEN0_USBLE_MASK 0x1UL
01024 #define _CMU_LFCCLKEN0_USBLE_DEFAULT 0x00000000UL
01025 #define CMU_LFCCLKEN0_USBLE_DEFAULT (_CMU_LFCCLKEN0_USBLE_DEFAULT << 0)
01027
01028 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
01029 #define _CMU_LFAPRESC0_MASK 0x0000000FUL
01030 #define _CMU_LFAPRESC0_RTC_SHIFT 0
01031 #define _CMU_LFAPRESC0_RTC_MASK 0xFUL
01032 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
01033 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
01034 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
01035 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
01036 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
01037 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
01038 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
01039 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
01040 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
01041 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
01042 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
01043 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
01044 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
01045 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
01046 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
01047 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
01048 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 0)
01049 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 0)
01050 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 0)
01051 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 0)
01052 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 0)
01053 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 0)
01054 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 0)
01055 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 0)
01056 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 0)
01057 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 0)
01058 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 0)
01059 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 0)
01060 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 0)
01061 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 0)
01062 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 0)
01063 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 0)
01065
01066 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
01067 #define _CMU_LFBPRESC0_MASK 0x00000003UL
01068 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
01069 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
01070 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
01071 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
01072 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
01073 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
01074 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
01075 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
01076 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
01077 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
01079
01080 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
01081 #define _CMU_PCNTCTRL_MASK 0x00000003UL
01082 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
01083 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
01084 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
01085 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
01086 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
01087 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
01088 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
01089 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
01090 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
01091 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
01092 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
01093 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
01094 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
01095 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
01097
01098 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
01099 #define _CMU_ROUTE_MASK 0x0000001FUL
01100 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
01101 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
01102 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
01103 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
01104 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
01105 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
01106 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
01107 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
01108 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
01109 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
01110 #define _CMU_ROUTE_LOCATION_SHIFT 2
01111 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL
01112 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
01113 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
01114 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
01115 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL
01116 #define _CMU_ROUTE_LOCATION_LOC3 0x00000003UL
01117 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
01118 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
01119 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
01120 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)
01121 #define CMU_ROUTE_LOCATION_LOC3 (_CMU_ROUTE_LOCATION_LOC3 << 2)
01123
01124 #define _CMU_LOCK_RESETVALUE 0x00000000UL
01125 #define _CMU_LOCK_MASK 0x0000FFFFUL
01126 #define _CMU_LOCK_LOCKKEY_SHIFT 0
01127 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
01128 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
01129 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
01130 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
01131 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
01132 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
01133 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
01134 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
01135 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
01136 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
01137 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
01139
01140 #define _CMU_USBCRCTRL_RESETVALUE 0x00000000UL
01141 #define _CMU_USBCRCTRL_MASK 0x00000003UL
01142 #define CMU_USBCRCTRL_EN (0x1UL << 0)
01143 #define _CMU_USBCRCTRL_EN_SHIFT 0
01144 #define _CMU_USBCRCTRL_EN_MASK 0x1UL
01145 #define _CMU_USBCRCTRL_EN_DEFAULT 0x00000000UL
01146 #define CMU_USBCRCTRL_EN_DEFAULT (_CMU_USBCRCTRL_EN_DEFAULT << 0)
01147 #define CMU_USBCRCTRL_LSMODE (0x1UL << 1)
01148 #define _CMU_USBCRCTRL_LSMODE_SHIFT 1
01149 #define _CMU_USBCRCTRL_LSMODE_MASK 0x2UL
01150 #define _CMU_USBCRCTRL_LSMODE_DEFAULT 0x00000000UL
01151 #define CMU_USBCRCTRL_LSMODE_DEFAULT (_CMU_USBCRCTRL_LSMODE_DEFAULT << 1)
01153
01154 #define _CMU_USHFRCOCTRL_RESETVALUE 0x000FF040UL
01155 #define _CMU_USHFRCOCTRL_MASK 0x000FF37FUL
01156 #define _CMU_USHFRCOCTRL_TUNING_SHIFT 0
01157 #define _CMU_USHFRCOCTRL_TUNING_MASK 0x7FUL
01158 #define _CMU_USHFRCOCTRL_TUNING_DEFAULT 0x00000040UL
01159 #define CMU_USHFRCOCTRL_TUNING_DEFAULT (_CMU_USHFRCOCTRL_TUNING_DEFAULT << 0)
01160 #define CMU_USHFRCOCTRL_DITHEN (0x1UL << 8)
01161 #define _CMU_USHFRCOCTRL_DITHEN_SHIFT 8
01162 #define _CMU_USHFRCOCTRL_DITHEN_MASK 0x100UL
01163 #define _CMU_USHFRCOCTRL_DITHEN_DEFAULT 0x00000000UL
01164 #define CMU_USHFRCOCTRL_DITHEN_DEFAULT (_CMU_USHFRCOCTRL_DITHEN_DEFAULT << 8)
01165 #define CMU_USHFRCOCTRL_SUSPEND (0x1UL << 9)
01166 #define _CMU_USHFRCOCTRL_SUSPEND_SHIFT 9
01167 #define _CMU_USHFRCOCTRL_SUSPEND_MASK 0x200UL
01168 #define _CMU_USHFRCOCTRL_SUSPEND_DEFAULT 0x00000000UL
01169 #define CMU_USHFRCOCTRL_SUSPEND_DEFAULT (_CMU_USHFRCOCTRL_SUSPEND_DEFAULT << 9)
01170 #define _CMU_USHFRCOCTRL_TIMEOUT_SHIFT 12
01171 #define _CMU_USHFRCOCTRL_TIMEOUT_MASK 0xFF000UL
01172 #define _CMU_USHFRCOCTRL_TIMEOUT_DEFAULT 0x000000FFUL
01173 #define CMU_USHFRCOCTRL_TIMEOUT_DEFAULT (_CMU_USHFRCOCTRL_TIMEOUT_DEFAULT << 12)
01175
01176 #define _CMU_USHFRCOTUNE_RESETVALUE 0x00000020UL
01177 #define _CMU_USHFRCOTUNE_MASK 0x0000003FUL
01178 #define _CMU_USHFRCOTUNE_FINETUNING_SHIFT 0
01179 #define _CMU_USHFRCOTUNE_FINETUNING_MASK 0x3FUL
01180 #define _CMU_USHFRCOTUNE_FINETUNING_DEFAULT 0x00000020UL
01181 #define CMU_USHFRCOTUNE_FINETUNING_DEFAULT (_CMU_USHFRCOTUNE_FINETUNING_DEFAULT << 0)
01183
01184 #define _CMU_USHFRCOCONF_RESETVALUE 0x00000001UL
01185 #define _CMU_USHFRCOCONF_MASK 0x00000017UL
01186 #define _CMU_USHFRCOCONF_BAND_SHIFT 0
01187 #define _CMU_USHFRCOCONF_BAND_MASK 0x7UL
01188 #define _CMU_USHFRCOCONF_BAND_DEFAULT 0x00000001UL
01189 #define _CMU_USHFRCOCONF_BAND_48MHZ 0x00000001UL
01190 #define _CMU_USHFRCOCONF_BAND_24MHZ 0x00000003UL
01191 #define CMU_USHFRCOCONF_BAND_DEFAULT (_CMU_USHFRCOCONF_BAND_DEFAULT << 0)
01192 #define CMU_USHFRCOCONF_BAND_48MHZ (_CMU_USHFRCOCONF_BAND_48MHZ << 0)
01193 #define CMU_USHFRCOCONF_BAND_24MHZ (_CMU_USHFRCOCONF_BAND_24MHZ << 0)
01194 #define CMU_USHFRCOCONF_USHFRCODIV2DIS (0x1UL << 4)
01195 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_SHIFT 4
01196 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_MASK 0x10UL
01197 #define _CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT 0x00000000UL
01198 #define CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT (_CMU_USHFRCOCONF_USHFRCODIV2DIS_DEFAULT << 4)