bsp_dk_bcreg_3201.h

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00001 /**************************************************************************/
00018 #ifndef __BSP_DK_BCREG_3201_H
00019 #define __BSP_DK_BCREG_3201_H
00020 
00021 #include <stdint.h>
00022 
00023 /***************************************************************************/
00028 /***************************************************************************/
00033 #ifdef __cplusplus
00034 extern "C" {
00035 #endif
00036 
00037 /**************************************************************************/
00041 #define BC_REGISTER_BASE    0x80000000  
00042 #define BC_SSD2119_BASE     0x84000000  
00043 #define BC_PSRAM_BASE       0x88000000  
00044 #define BC_FLASH_BASE       0x8C000000  
00047 /**************************************************************************/
00051 /* Define registers in a similar manner to CMSIS standards */
00052 
00053 #define __IO    volatile
00054 
00056 typedef struct
00057 {
00058   __IO uint16_t RESERVERD0;        
00059   __IO uint16_t EM;                
00060   __IO uint16_t MAGIC;             
00062   __IO uint16_t UIF_LEDS;          
00063   __IO uint16_t UIF_PB;            
00064   __IO uint16_t UIF_DIP;           
00065   __IO uint16_t UIF_JOYSTICK;      
00066   __IO uint16_t UIF_AEM;           
00067   __IO uint16_t UIF_CTRL;          
00068   __IO uint16_t DISPLAY_CTRL;      
00069   __IO uint16_t EBI_CTRL;          
00070   __IO uint16_t ARB_CTRL;          
00071   __IO uint16_t PERICON;           
00072   __IO uint16_t SPI_DEMUX;         
00073   __IO uint16_t RESERVERD1[0x02];  
00075   __IO uint16_t ADC_WRITE;         
00076   __IO uint16_t ADC_STATUS;        
00077   __IO uint16_t ADC_READ;          
00079   __IO uint16_t CLKRST;            
00081   __IO uint16_t HW_VERSION;        
00082   __IO uint16_t FW_BUILDNO;        
00083   __IO uint16_t FW_VERSION;        
00085   __IO uint16_t SCRATCH_COMMON;    
00087   __IO uint16_t SCRATCH_EFM0;      
00088   __IO uint16_t SCRATCH_EFM1;      
00089   __IO uint16_t SCRATCH_EFM2;      
00090   __IO uint16_t SCRATCH_EFM3;      
00092   __IO uint16_t SCRATCH_BC0;       
00093   __IO uint16_t SCRATCH_BC1;       
00094   __IO uint16_t SCRATCH_BC2;       
00095   __IO uint16_t SCRATCH_BC3;       
00097   __IO uint16_t INTFLAG;           
00098   __IO uint16_t INTEN;             
00099   __IO uint16_t INTCLEAR;          
00100   __IO uint16_t INTSET;            
00101   __IO uint16_t INTPCTRL;          
00102   __IO uint16_t INTPLOW;           
00103   __IO uint16_t INTPHIGH;          
00105   __IO uint16_t RESERVERD3[0x19];  
00107   __IO uint16_t BC_MBOX_TXCTRL;    
00108   __IO uint16_t BC_MBOX_TXDATA;    
00109   __IO uint16_t BC_MBOX_TXSTATUS0; 
00110   __IO uint16_t BC_MBOX_TXSTATUS1; 
00112   __IO uint16_t RESERVED4[0x0d];   
00114   __IO uint16_t MBOX_TXCTRL;       
00115   __IO uint16_t MBOX_TXDATA;       
00116   __IO uint16_t MBOX_TXSTATUS0;    
00117   __IO uint16_t MBOX_TXSTATUS1;    
00119   __IO uint16_t RESERVED5[0x0b];   
00121   __IO uint16_t BUF_CTRL;          
00122 } BC_TypeDef;
00123 
00124 /* Cast into register structure */
00125 #define BC_REGISTER                         ((BC_TypeDef *) BC_REGISTER_BASE) 
00127 /* Energy Mode indicator */
00128 #define BC_EM_EM0                           (0)  
00129 #define BC_EM_EM1                           (1)  
00130 #define BC_EM_EM2                           (2)  
00131 #define BC_EM_EM3                           (3)  
00132 #define BC_EM_EM4                           (4)  
00134 /* Magic value */
00135 #define BC_MAGIC_VALUE                      (0xef32)  
00137 /* Push buttons, PB1-PB4 */
00138 #define BC_UIF_PB_MASK                      (0x000f) 
00139 #define BC_UIF_PB1                          (1 << 0) 
00140 #define BC_UIF_PB2                          (1 << 1) 
00141 #define BC_UIF_PB3                          (1 << 2) 
00142 #define BC_UIF_PB4                          (1 << 3) 
00144 /* Dip switch */
00145 #define BC_DIPSWITCH_MASK                   (0x000f)  
00147 /* Joystick directions */
00148 #define BC_UIF_JOYSTICK_MASK                (0x001f)      
00149 #define BC_UIF_JOYSTICK_DOWN                (1 << 0)      
00150 #define BC_UIF_JOYSTICK_RIGHT               (1 << 1)      
00151 #define BC_UIF_JOYSTICK_UP                  (1 << 2)      
00152 #define BC_UIF_JOYSTICK_LEFT                (1 << 3)      
00153 #define BC_UIF_JOYSTICK_CENTER              (1 << 4)      
00155 /* AEM state */
00156 #define BC_UIF_AEM_BC                       (0) 
00157 #define BC_UIF_AEM_EFM                      (1) 
00159 /* Display control */
00160 #define BC_DISPLAY_CTRL_RESET               (1 << 1)                          
00161 #define BC_DISPLAY_CTRL_POWER_ENABLE        (1 << 0)                          
00162 #define BC_DISPLAY_CTRL_MODE_SHIFT          2                                 
00163 #define BC_DISPLAY_CTRL_MODE_8080           (0 << BC_DISPLAY_CTRL_MODE_SHIFT) 
00164 #define BC_DISPLAY_CTRL_MODE_GENERIC        (1 << BC_DISPLAY_CTRL_MODE_SHIFT) 
00166 /* EBI control - extended address range enable bit  */
00167 #define BC_EBI_CTRL_EXTADDR_MASK            (0x0001) 
00169 /* Arbiter control - directs access to display controller  */
00170 #define BC_ARB_CTRL_SHIFT                   0                        
00171 #define BC_ARB_CTRL_BC                      (0 << BC_ARB_CTRL_SHIFT) 
00172 #define BC_ARB_CTRL_EBI                     (1 << BC_ARB_CTRL_SHIFT) 
00173 #define BC_ARB_CTRL_SPI                     (2 << BC_ARB_CTRL_SHIFT) 
00175 /* Interrupt flag registers, INTEN and INTFLAG */
00176 #define BC_INTEN_MASK                       (0x001f)  
00177 #define BC_INTEN_PB                         (1 << 0)  
00178 #define BC_INTEN_DIP                        (1 << 1)  
00179 #define BC_INTEN_JOYSTICK                   (1 << 2)  
00180 #define BC_INTEN_AEM                        (1 << 3)  
00181 #define BC_INTEN_ETH                        (1 << 4)  
00183 #define BC_INTFLAG_MASK                     (0x001f)  
00184 #define BC_INTFLAG_PB                       (1 << 0)  
00185 #define BC_INTFLAG_DIP                      (1 << 1)  
00186 #define BC_INTFLAG_JOYSTICK                 (1 << 2)  
00187 #define BC_INTFLAG_AEM                      (1 << 3)  
00188 #define BC_INTFLAG_ETH                      (1 << 4)  
00190 /* Peripheral control registers */
00191 #define BC_PERICON_RS232_SHUTDOWN_SHIFT     13 
00192 #define BC_PERICON_RS232_UART_SHIFT         12 
00193 #define BC_PERICON_RS232_LEUART_SHIFT       11 
00194 #define BC_PERICON_I2C_SHIFT                10 
00195 #define BC_PERICON_I2S_ETH_SEL_SHIFT        9  
00196 #define BC_PERICON_I2S_ETH_SHIFT            8  
00197 #define BC_PERICON_TRACE_SHIFT              7  
00198 #define BC_PERICON_TOUCH_SHIFT              6  
00199 #define BC_PERICON_AUDIO_IN_SHIFT           5  
00200 #define BC_PERICON_AUDIO_OUT_SEL_SHIFT      4  
00201 #define BC_PERICON_AUDIO_OUT_SHIFT          3  
00202 #define BC_PERICON_ANALOG_DIFF_SHIFT        2  
00203 #define BC_PERICON_ANALOG_SE_SHIFT          1  
00204 #define BC_PERICON_SPI_SHIFT                0  
00206 /* SPI DEMUX control */
00207 #define BC_SPI_DEMUX_SLAVE_MASK             (0x0003) 
00208 #define BC_SPI_DEMUX_SLAVE_AUDIO            (0)      
00209 #define BC_SPI_DEMUX_SLAVE_ETHERNET         (1)      
00210 #define BC_SPI_DEMUX_SLAVE_DISPLAY          (2)      
00212 /* ADC */
00213 #define BC_ADC_STATUS_DONE                  (0)  
00214 #define BC_ADC_STATUS_BUSY                  (1)  
00216 /* Clock and Reset Control */
00217 #define BC_CLKRST_FLASH_SHIFT               (1 << 1) 
00218 #define BC_CLKRST_ETH_SHIFT                 (1 << 2) 
00220 /* Hardware version information */
00221 #define BC_HW_VERSION_PCB_MASK              (0x07f0)  
00222 #define BC_HW_VERSION_PCB_SHIFT             (4)       
00223 #define BC_HW_VERSION_BOARD_MASK            (0x000f)  
00224 #define BC_HW_VERSION_BOARD_SHIFT           (0)       
00226 /* Firmware version information */
00227 #define BC_FW_VERSION_MAJOR_MASK            (0xf000) 
00228 #define BC_FW_VERSION_MAJOR_SHIFT           (12)     
00229 #define BC_FW_VERSION_MINOR_MASK            (0x0f00) 
00230 #define BC_FW_VERSION_MINOR_SHIFT           (8)      
00231 #define BC_FW_VERSION_PATCHLEVEL_MASK       (0x00ff) 
00232 #define BC_FW_VERSION_PATCHLEVEL_SHIFT      (0)      
00234 /* MBOX - BC <-> EFM32 communication */
00235 #define BC_MBOX_TXSTATUS0_FIFOEMPTY         (1 << 0) 
00236 #define BC_MBOX_TXSTATUS0_FIFOFULL          (1 << 1) 
00237 #define BC_MBOX_TXSTATUS0_FIFOUNDERFLOW     (1 << 4) 
00238 #define BC_MBOX_TXSTATUS0_FIFOOVERFLOW      (1 << 5) 
00240 #define BC_MBOX_TXSTATUS1_WORDCOUNT_MASK    (0x07FF) 
00242 /* Buffer Controller */
00243 #define BC_BUF_CTRL_CS_ENABLE               (1 << 0) 
00245 #ifdef __cplusplus
00246 }
00247 #endif
00248 
00252 #endif  /* __BSP_DK_BCREG_3201_H */