00001
00034 #ifndef __SILICON_LABS_EFM32HG309F32_H__
00035 #define __SILICON_LABS_EFM32HG309F32_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 SVCall_IRQn = -5,
00058 PendSV_IRQn = -2,
00059 SysTick_IRQn = -1,
00061
00062 DMA_IRQn = 0,
00063 GPIO_EVEN_IRQn = 1,
00064 TIMER0_IRQn = 2,
00065 ACMP0_IRQn = 3,
00066 ADC0_IRQn = 4,
00067 I2C0_IRQn = 5,
00068 GPIO_ODD_IRQn = 6,
00069 TIMER1_IRQn = 7,
00070 USART1_RX_IRQn = 8,
00071 USART1_TX_IRQn = 9,
00072 LEUART0_IRQn = 10,
00073 PCNT0_IRQn = 11,
00074 RTC_IRQn = 12,
00075 CMU_IRQn = 13,
00076 VCMP_IRQn = 14,
00077 MSC_IRQn = 15,
00078 AES_IRQn = 16,
00079 USART0_RX_IRQn = 17,
00080 USART0_TX_IRQn = 18,
00081 USB_IRQn = 19,
00082 TIMER2_IRQn = 20,
00083 } IRQn_Type;
00084
00085
00090 #define __MPU_PRESENT 0
00091 #define __VTOR_PRESENT 1
00092 #define __NVIC_PRIO_BITS 2
00093 #define __Vendor_SysTickConfig 0
00097
00103 #define _EFM32_HAPPY_FAMILY 1
00104 #define _EFM_DEVICE
00105 #define _SILICON_LABS_32B_PLATFORM_1
00106 #define _SILICON_LABS_32B_PLATFORM 1
00108
00109 #if !defined(EFM32HG309F32)
00110 #define EFM32HG309F32 1
00111 #endif
00112
00114 #define PART_NUMBER "EFM32HG309F32"
00117 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00118 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00119 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00120 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00121 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00122 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00123 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00124 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00125 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
00126 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
00127 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
00128 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
00129 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00130 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00131 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00132 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00133 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00134 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
00135 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
00136 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
00137 #define DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL)
00138 #define DEVICE_MEM_SIZE ((uint32_t) 0x1000UL)
00139 #define DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL)
00140 #define DEVICE_MEM_BITS ((uint32_t) 0x12UL)
00141 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00142 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
00143 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
00144 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
00147 #define FLASH_BASE (0x00000000UL)
00148 #define FLASH_SIZE (0x00008000UL)
00149 #define FLASH_PAGE_SIZE 1024
00150 #define SRAM_BASE (0x20000000UL)
00151 #define SRAM_SIZE (0x00002000UL)
00152 #define __CM0PLUS_REV 0x001
00153 #define PRS_CHAN_COUNT 6
00154 #define DMA_CHAN_COUNT 6
00157 #define AFCHAN_MAX 42
00158 #define AFCHANLOC_MAX 7
00159
00160 #define AFACHAN_MAX 27
00161
00162
00163
00164 #define TIMER_PRESENT
00165 #define TIMER_COUNT 3
00166 #define ACMP_PRESENT
00167 #define ACMP_COUNT 1
00168 #define USART_PRESENT
00169 #define USART_COUNT 2
00170 #define IDAC_PRESENT
00171 #define IDAC_COUNT 1
00172 #define ADC_PRESENT
00173 #define ADC_COUNT 1
00174 #define LEUART_PRESENT
00175 #define LEUART_COUNT 1
00176 #define PCNT_PRESENT
00177 #define PCNT_COUNT 1
00178 #define I2C_PRESENT
00179 #define I2C_COUNT 1
00180 #define AES_PRESENT
00181 #define AES_COUNT 1
00182 #define DMA_PRESENT
00183 #define DMA_COUNT 1
00184 #define LE_PRESENT
00185 #define LE_COUNT 1
00186 #define USBC_PRESENT
00187 #define USBC_COUNT 1
00188 #define USBLE_PRESENT
00189 #define USBLE_COUNT 1
00190 #define USB_PRESENT
00191 #define USB_COUNT 1
00192 #define MSC_PRESENT
00193 #define MSC_COUNT 1
00194 #define EMU_PRESENT
00195 #define EMU_COUNT 1
00196 #define RMU_PRESENT
00197 #define RMU_COUNT 1
00198 #define CMU_PRESENT
00199 #define CMU_COUNT 1
00200 #define PRS_PRESENT
00201 #define PRS_COUNT 1
00202 #define GPIO_PRESENT
00203 #define GPIO_COUNT 1
00204 #define VCMP_PRESENT
00205 #define VCMP_COUNT 1
00206 #define RTC_PRESENT
00207 #define RTC_COUNT 1
00208 #define HFXTAL_PRESENT
00209 #define HFXTAL_COUNT 1
00210 #define LFXTAL_PRESENT
00211 #define LFXTAL_COUNT 1
00212 #define USHFRCO_PRESENT
00213 #define USHFRCO_COUNT 1
00214 #define WDOG_PRESENT
00215 #define WDOG_COUNT 1
00216 #define DBG_PRESENT
00217 #define DBG_COUNT 1
00218 #define MTB_PRESENT
00219 #define MTB_COUNT 1
00220 #define BOOTLOADER_PRESENT
00221 #define BOOTLOADER_COUNT 1
00222 #define ANALOG_PRESENT
00223 #define ANALOG_COUNT 1
00224
00227 #define ARM_MATH_CM0PLUS
00228 #include "arm_math.h"
00229 #include "core_cm0plus.h"
00230 #include "system_efm32hg.h"
00231
00232
00238 #include "efm32hg_aes.h"
00239 #include "efm32hg_dma_ch.h"
00240 #include "efm32hg_dma.h"
00241 #include "efm32hg_usb_diep.h"
00242 #include "efm32hg_usb_doep.h"
00243 #include "efm32hg_usb.h"
00244 #include "efm32hg_msc.h"
00245 #include "efm32hg_emu.h"
00246 #include "efm32hg_rmu.h"
00247 #include "efm32hg_cmu.h"
00248 #include "efm32hg_timer_cc.h"
00249 #include "efm32hg_timer.h"
00250 #include "efm32hg_acmp.h"
00251 #include "efm32hg_usart.h"
00252 #include "efm32hg_prs_ch.h"
00253 #include "efm32hg_prs.h"
00254 #include "efm32hg_idac.h"
00255 #include "efm32hg_gpio_p.h"
00256 #include "efm32hg_gpio.h"
00257 #include "efm32hg_vcmp.h"
00258 #include "efm32hg_adc.h"
00259 #include "efm32hg_leuart.h"
00260 #include "efm32hg_pcnt.h"
00261 #include "efm32hg_i2c.h"
00262 #include "efm32hg_rtc.h"
00263 #include "efm32hg_wdog.h"
00264 #include "efm32hg_mtb.h"
00265 #include "efm32hg_dma_descriptor.h"
00266 #include "efm32hg_devinfo.h"
00267 #include "efm32hg_romtable.h"
00268 #include "efm32hg_calibrate.h"
00269
00272
00277 #define AES_BASE (0x400E0000UL)
00278 #define DMA_BASE (0x400C2000UL)
00279 #define USB_BASE (0x400C4000UL)
00280 #define MSC_BASE (0x400C0000UL)
00281 #define EMU_BASE (0x400C6000UL)
00282 #define RMU_BASE (0x400CA000UL)
00283 #define CMU_BASE (0x400C8000UL)
00284 #define TIMER0_BASE (0x40010000UL)
00285 #define TIMER1_BASE (0x40010400UL)
00286 #define TIMER2_BASE (0x40010800UL)
00287 #define ACMP0_BASE (0x40001000UL)
00288 #define USART0_BASE (0x4000C000UL)
00289 #define USART1_BASE (0x4000C400UL)
00290 #define PRS_BASE (0x400CC000UL)
00291 #define IDAC0_BASE (0x40004000UL)
00292 #define GPIO_BASE (0x40006000UL)
00293 #define VCMP_BASE (0x40000000UL)
00294 #define ADC0_BASE (0x40002000UL)
00295 #define LEUART0_BASE (0x40084000UL)
00296 #define PCNT0_BASE (0x40086000UL)
00297 #define I2C0_BASE (0x4000A000UL)
00298 #define RTC_BASE (0x40080000UL)
00299 #define WDOG_BASE (0x40088000UL)
00300 #define MTB_BASE (0xF0040000UL)
00301 #define CALIBRATE_BASE (0x0FE08000UL)
00302 #define DEVINFO_BASE (0x0FE081B0UL)
00303 #define ROMTABLE_BASE (0xF00FFFD0UL)
00304 #define LOCKBITS_BASE (0x0FE04000UL)
00305 #define USERDATA_BASE (0x0FE00000UL)
00309
00314 #define AES ((AES_TypeDef *) AES_BASE)
00315 #define DMA ((DMA_TypeDef *) DMA_BASE)
00316 #define USB ((USB_TypeDef *) USB_BASE)
00317 #define MSC ((MSC_TypeDef *) MSC_BASE)
00318 #define EMU ((EMU_TypeDef *) EMU_BASE)
00319 #define RMU ((RMU_TypeDef *) RMU_BASE)
00320 #define CMU ((CMU_TypeDef *) CMU_BASE)
00321 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00322 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00323 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
00324 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00325 #define USART0 ((USART_TypeDef *) USART0_BASE)
00326 #define USART1 ((USART_TypeDef *) USART1_BASE)
00327 #define PRS ((PRS_TypeDef *) PRS_BASE)
00328 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)
00329 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00330 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00331 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00332 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00333 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00334 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00335 #define RTC ((RTC_TypeDef *) RTC_BASE)
00336 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00337 #define MTB ((MTB_TypeDef *) MTB_BASE)
00338 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00339 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00340 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00344
00349 #include "efm32hg_prs_signals.h"
00350 #include "efm32hg_dmareq.h"
00351 #include "efm32hg_dmactrl.h"
00352
00353
00357 #define MSC_UNLOCK_CODE 0x1B71
00358 #define EMU_UNLOCK_CODE 0xADE8
00359 #define CMU_UNLOCK_CODE 0x580E
00360 #define TIMER_UNLOCK_CODE 0xCE80
00361 #define GPIO_UNLOCK_CODE 0xA534
00367
00372 #include "efm32hg_af_ports.h"
00373 #include "efm32hg_af_pins.h"
00374
00377
00390 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
00391 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
00392
00397 #ifdef __cplusplus
00398 }
00399 #endif
00400 #endif