release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32HG/Include/efm32hg_dmactrl.h

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00001 /**************************************************************************/
00033 /**************************************************************************/
00037 #define _DMA_CTRL_DST_INC_MASK                         0xC0000000UL  
00038 #define _DMA_CTRL_DST_INC_SHIFT                        30            
00039 #define _DMA_CTRL_DST_INC_BYTE                         0x00          
00040 #define _DMA_CTRL_DST_INC_HALFWORD                     0x01          
00041 #define _DMA_CTRL_DST_INC_WORD                         0x02          
00042 #define _DMA_CTRL_DST_INC_NONE                         0x03          
00043 #define DMA_CTRL_DST_INC_BYTE                          0x00000000UL  
00044 #define DMA_CTRL_DST_INC_HALFWORD                      0x40000000UL  
00045 #define DMA_CTRL_DST_INC_WORD                          0x80000000UL  
00046 #define DMA_CTRL_DST_INC_NONE                          0xC0000000UL  
00047 #define _DMA_CTRL_DST_SIZE_MASK                        0x30000000UL  
00048 #define _DMA_CTRL_DST_SIZE_SHIFT                       28            
00049 #define _DMA_CTRL_DST_SIZE_BYTE                        0x00          
00050 #define _DMA_CTRL_DST_SIZE_HALFWORD                    0x01          
00051 #define _DMA_CTRL_DST_SIZE_WORD                        0x02          
00052 #define _DMA_CTRL_DST_SIZE_RSVD                        0x03          
00053 #define DMA_CTRL_DST_SIZE_BYTE                         0x00000000UL  
00054 #define DMA_CTRL_DST_SIZE_HALFWORD                     0x10000000UL  
00055 #define DMA_CTRL_DST_SIZE_WORD                         0x20000000UL  
00056 #define DMA_CTRL_DST_SIZE_RSVD                         0x30000000UL  
00057 #define _DMA_CTRL_SRC_INC_MASK                         0x0C000000UL  
00058 #define _DMA_CTRL_SRC_INC_SHIFT                        26            
00059 #define _DMA_CTRL_SRC_INC_BYTE                         0x00          
00060 #define _DMA_CTRL_SRC_INC_HALFWORD                     0x01          
00061 #define _DMA_CTRL_SRC_INC_WORD                         0x02          
00062 #define _DMA_CTRL_SRC_INC_NONE                         0x03          
00063 #define DMA_CTRL_SRC_INC_BYTE                          0x00000000UL  
00064 #define DMA_CTRL_SRC_INC_HALFWORD                      0x04000000UL  
00065 #define DMA_CTRL_SRC_INC_WORD                          0x08000000UL  
00066 #define DMA_CTRL_SRC_INC_NONE                          0x0C000000UL  
00067 #define _DMA_CTRL_SRC_SIZE_MASK                        0x03000000UL  
00068 #define _DMA_CTRL_SRC_SIZE_SHIFT                       24            
00069 #define _DMA_CTRL_SRC_SIZE_BYTE                        0x00          
00070 #define _DMA_CTRL_SRC_SIZE_HALFWORD                    0x01          
00071 #define _DMA_CTRL_SRC_SIZE_WORD                        0x02          
00072 #define _DMA_CTRL_SRC_SIZE_RSVD                        0x03          
00073 #define DMA_CTRL_SRC_SIZE_BYTE                         0x00000000UL  
00074 #define DMA_CTRL_SRC_SIZE_HALFWORD                     0x01000000UL  
00075 #define DMA_CTRL_SRC_SIZE_WORD                         0x02000000UL  
00076 #define DMA_CTRL_SRC_SIZE_RSVD                         0x03000000UL  
00077 #define _DMA_CTRL_DST_PROT_CTRL_MASK                   0x00E00000UL  
00078 #define _DMA_CTRL_DST_PROT_CTRL_SHIFT                  21            
00079 #define DMA_CTRL_DST_PROT_PRIVILEGED                   0x00200000UL  
00080 #define DMA_CTRL_DST_PROT_NON_PRIVILEGED               0x00000000UL  
00081 #define _DMA_CTRL_SRC_PROT_CTRL_MASK                   0x001C0000UL  
00082 #define _DMA_CTRL_SRC_PROT_CTRL_SHIFT                  18            
00083 #define DMA_CTRL_SRC_PROT_PRIVILEGED                   0x00040000UL  
00084 #define DMA_CTRL_SRC_PROT_NON_PRIVILEGED               0x00000000UL  
00085 #define _DMA_CTRL_PROT_NON_PRIVILEGED                  0x00          
00086 #define _DMA_CTRL_PROT_PRIVILEGED                      0x01          
00087 #define _DMA_CTRL_R_POWER_MASK                         0x0003C000UL  
00088 #define _DMA_CTRL_R_POWER_SHIFT                        14            
00089 #define _DMA_CTRL_R_POWER_1                            0x00          
00090 #define _DMA_CTRL_R_POWER_2                            0x01          
00091 #define _DMA_CTRL_R_POWER_4                            0x02          
00092 #define _DMA_CTRL_R_POWER_8                            0x03          
00093 #define _DMA_CTRL_R_POWER_16                           0x04          
00094 #define _DMA_CTRL_R_POWER_32                           0x05          
00095 #define _DMA_CTRL_R_POWER_64                           0x06          
00096 #define _DMA_CTRL_R_POWER_128                          0x07          
00097 #define _DMA_CTRL_R_POWER_256                          0x08          
00098 #define _DMA_CTRL_R_POWER_512                          0x09          
00099 #define _DMA_CTRL_R_POWER_1024                         0x0a          
00100 #define DMA_CTRL_R_POWER_1                             0x00000000UL  
00101 #define DMA_CTRL_R_POWER_2                             0x00004000UL  
00102 #define DMA_CTRL_R_POWER_4                             0x00008000UL  
00103 #define DMA_CTRL_R_POWER_8                             0x0000c000UL  
00104 #define DMA_CTRL_R_POWER_16                            0x00010000UL  
00105 #define DMA_CTRL_R_POWER_32                            0x00014000UL  
00106 #define DMA_CTRL_R_POWER_64                            0x00018000UL  
00107 #define DMA_CTRL_R_POWER_128                           0x0001c000UL  
00108 #define DMA_CTRL_R_POWER_256                           0x00020000UL  
00109 #define DMA_CTRL_R_POWER_512                           0x00024000UL  
00110 #define DMA_CTRL_R_POWER_1024                          0x00028000UL  
00111 #define _DMA_CTRL_N_MINUS_1_MASK                       0x00003FF0UL  
00112 #define _DMA_CTRL_N_MINUS_1_SHIFT                      4             
00113 #define _DMA_CTRL_NEXT_USEBURST_MASK                   0x00000008UL  
00114 #define _DMA_CTRL_NEXT_USEBURST_SHIFT                  3             
00115 #define _DMA_CTRL_CYCLE_CTRL_MASK                      0x00000007UL  
00116 #define _DMA_CTRL_CYCLE_CTRL_SHIFT                     0             
00117 #define _DMA_CTRL_CYCLE_CTRL_INVALID                   0x00          
00118 #define _DMA_CTRL_CYCLE_CTRL_BASIC                     0x01          
00119 #define _DMA_CTRL_CYCLE_CTRL_AUTO                      0x02          
00120 #define _DMA_CTRL_CYCLE_CTRL_PINGPONG                  0x03          
00121 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER        0x04          
00122 #define _DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT    0x05          
00123 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER        0x06          
00124 #define _DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT    0x07          
00125 #define DMA_CTRL_CYCLE_CTRL_INVALID                    0x00000000UL  
00126 #define DMA_CTRL_CYCLE_CTRL_BASIC                      0x00000001UL  
00127 #define DMA_CTRL_CYCLE_CTRL_AUTO                       0x00000002UL  
00128 #define DMA_CTRL_CYCLE_CTRL_PINGPONG                   0x00000003UL  
00129 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER         0x000000004UL 
00130 #define DMA_CTRL_CYCLE_CTRL_MEM_SCATTER_GATHER_ALT     0x000000005UL 
00131 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER         0x000000006UL 
00132 #define DMA_CTRL_CYCLE_CTRL_PER_SCATTER_GATHER_ALT     0x000000007UL