34 #if defined( ADC_COUNT ) && ( ADC_COUNT > 0 )
58 #define ADC_REF_VALID(ref) ((ref) == ADC0)
61 #if defined( _SILICON_LABS_32B_PLATFORM_1 )
62 #define ADC_MAX_CLOCK 13000000
64 #define ADC_MAX_CLOCK 16000000
68 #define ADC_MIN_CLOCK 32000
71 #if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_MASK )
72 #define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_1V25_GAIN_MASK
73 #elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_MASK )
74 #define DEVINFO_ADC0_GAIN1V25_MASK _DEVINFO_ADC0CAL0_GAIN1V25_MASK
77 #if defined( _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT )
78 #define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT
79 #elif defined( _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT )
80 #define DEVINFO_ADC0_GAIN1V25_SHIFT _DEVINFO_ADC0CAL0_GAIN1V25_SHIFT
83 #if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK )
84 #define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK
85 #elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_MASK )
86 #define DEVINFO_ADC0_OFFSET1V25_MASK _DEVINFO_ADC0CAL0_OFFSET1V25_MASK
89 #if defined( _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT )
90 #define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT
91 #elif defined( _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT )
92 #define DEVINFO_ADC0_OFFSET1V25_SHIFT _DEVINFO_ADC0CAL0_OFFSET1V25_SHIFT
95 #if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_MASK )
96 #define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_2V5_GAIN_MASK
97 #elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_MASK )
98 #define DEVINFO_ADC0_GAIN2V5_MASK _DEVINFO_ADC0CAL0_GAIN2V5_MASK
101 #if defined( _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT )
102 #define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT
103 #elif defined( _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT )
104 #define DEVINFO_ADC0_GAIN2V5_SHIFT _DEVINFO_ADC0CAL0_GAIN2V5_SHIFT
107 #if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK )
108 #define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK
109 #elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_MASK )
110 #define DEVINFO_ADC0_OFFSET2V5_MASK _DEVINFO_ADC0CAL0_OFFSET2V5_MASK
113 #if defined( _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT )
114 #define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT
115 #elif defined( _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT )
116 #define DEVINFO_ADC0_OFFSET2V5_SHIFT _DEVINFO_ADC0CAL0_OFFSET2V5_SHIFT
119 #if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_MASK )
120 #define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_VDD_GAIN_MASK
121 #elif defined( _DEVINFO_ADC0CAL1_GAINVDD_MASK )
122 #define DEVINFO_ADC0_GAINVDD_MASK _DEVINFO_ADC0CAL1_GAINVDD_MASK
125 #if defined( _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT )
126 #define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT
127 #elif defined( _DEVINFO_ADC0CAL1_GAINVDD_SHIFT )
128 #define DEVINFO_ADC0_GAINVDD_SHIFT _DEVINFO_ADC0CAL1_GAINVDD_SHIFT
131 #if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK )
132 #define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK
133 #elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_MASK )
134 #define DEVINFO_ADC0_OFFSETVDD_MASK _DEVINFO_ADC0CAL1_OFFSETVDD_MASK
137 #if defined( _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT )
138 #define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT
139 #elif defined( _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT )
140 #define DEVINFO_ADC0_OFFSETVDD_SHIFT _DEVINFO_ADC0CAL1_OFFSETVDD_SHIFT
143 #if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK )
144 #define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK
145 #elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK )
146 #define DEVINFO_ADC0_GAIN5VDIFF_MASK _DEVINFO_ADC0CAL1_GAIN5VDIFF_MASK
149 #if defined( _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT )
150 #define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT
151 #elif defined( _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT )
152 #define DEVINFO_ADC0_GAIN5VDIFF_SHIFT _DEVINFO_ADC0CAL1_GAIN5VDIFF_SHIFT
155 #if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK )
156 #define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK
157 #elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK )
158 #define DEVINFO_ADC0_OFFSET5VDIFF_MASK _DEVINFO_ADC0CAL1_OFFSET5VDIFF_MASK
161 #if defined( _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT )
162 #define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT
163 #elif defined( _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT )
164 #define DEVINFO_ADC0_OFFSET5VDIFF_SHIFT _DEVINFO_ADC0CAL1_OFFSET5VDIFF_SHIFT
167 #if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK )
168 #define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK
169 #elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK )
170 #define DEVINFO_ADC0_OFFSET2XVDD_MASK _DEVINFO_ADC0CAL2_OFFSET2XVDD_MASK
173 #if defined( _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT )
174 #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT
175 #elif defined( _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT )
176 #define DEVINFO_ADC0_OFFSET2XVDD_SHIFT _DEVINFO_ADC0CAL2_OFFSET2XVDD_SHIFT
221 #if defined( _ADC_CAL_SCANOFFSETINV_MASK )
222 | _ADC_CAL_SCANOFFSETINV_MASK
230 #if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
231 | _ADC_CAL_SINGLEOFFSETINV_MASK
236 calReg = adc->
CAL & mask;
242 newCal |= ((
DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN1V25_MASK)
243 >> DEVINFO_ADC0_GAIN1V25_SHIFT)
245 newCal |= ((
DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET1V25_MASK)
246 >> DEVINFO_ADC0_OFFSET1V25_SHIFT)
248 #if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
249 newCal |= ((
DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_MASK)
250 >> _DEVINFO_ADC0CAL0_NEGSEOFFSET1V25_SHIFT)
251 << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
256 newCal |= ((
DEVINFO->ADC0CAL0 & DEVINFO_ADC0_GAIN2V5_MASK)
257 >> DEVINFO_ADC0_GAIN2V5_SHIFT)
259 newCal |= ((
DEVINFO->ADC0CAL0 & DEVINFO_ADC0_OFFSET2V5_MASK)
260 >> DEVINFO_ADC0_OFFSET2V5_SHIFT)
262 #if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
263 newCal |= ((
DEVINFO->ADC0CAL0 & _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_MASK)
264 >> _DEVINFO_ADC0CAL0_NEGSEOFFSET2V5_SHIFT)
265 << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
270 newCal |= ((
DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
271 >> DEVINFO_ADC0_GAINVDD_SHIFT)
273 newCal |= ((
DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
274 >> DEVINFO_ADC0_OFFSETVDD_SHIFT)
276 #if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
277 newCal |= ((
DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
278 >> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
279 << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
284 newCal |= ((
DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAIN5VDIFF_MASK)
285 >> DEVINFO_ADC0_GAIN5VDIFF_SHIFT)
287 newCal |= ((
DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSET5VDIFF_MASK)
288 >> DEVINFO_ADC0_OFFSET5VDIFF_SHIFT)
290 #if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
291 newCal |= ((
DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_MASK)
292 >> _DEVINFO_ADC0CAL1_NEGSEOFFSET5VDIFF_SHIFT)
293 << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
299 newCal |= ((
DEVINFO->ADC0CAL2 & DEVINFO_ADC0_OFFSET2XVDD_MASK)
300 >> DEVINFO_ADC0_OFFSET2XVDD_SHIFT)
302 #if defined( _ADC_CAL_SINGLEOFFSETINV_MASK )
303 newCal |= ((
DEVINFO->ADC0CAL2 & _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_MASK)
304 >> _DEVINFO_ADC0CAL2_NEGSEOFFSET2XVDD_SHIFT)
305 << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
309 #if defined( _ADC_SINGLECTRLX_VREFSEL_VDDXWATT )
311 newCal |= ((
DEVINFO->ADC0CAL1 & DEVINFO_ADC0_GAINVDD_MASK)
312 >> DEVINFO_ADC0_GAINVDD_SHIFT)
314 newCal |= ((
DEVINFO->ADC0CAL1 & DEVINFO_ADC0_OFFSETVDD_MASK)
315 >> DEVINFO_ADC0_OFFSETVDD_SHIFT)
317 newCal |= ((
DEVINFO->ADC0CAL1 & _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_MASK)
318 >> _DEVINFO_ADC0CAL1_NEGSEOFFSETVDD_SHIFT)
319 << _ADC_CAL_SINGLEOFFSETINV_SHIFT;
332 adc->
CAL = calReg | (newCal << shift);
367 EFM_ASSERT(ADC_REF_VALID(adc));
389 #if defined( _ADC_CTRL_ADCCLKMODE_MASK )
391 _ADC_CTRL_ADCCLKMODE_MASK | _ADC_CTRL_ASYNCCLKEN_MASK,
392 init->em2ClockConfig << _ADC_CTRL_ASYNCCLKEN_SHIFT);
395 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
402 #if defined( _ADC_SCANINPUTSEL_MASK )
415 scanInit->scanInputConfig.scanInputSel = 0xFFFFFFFF;
416 scanInit->scanInputConfig.scanInputEn = 0;
419 scanInit->scanInputConfig.scanNegSel = _ADC_SCANNEGSEL_RESETVALUE;
446 ADC_ScanInputGroup_TypeDef inputGroup,
447 ADC_PosSel_TypeDef singleEndedSel)
453 scanInit->
diff =
false;
456 EFM_ASSERT((singleEndedSel <= adcPosSelAPORT0YCH0) || (singleEndedSel >= adcPosSelAPORT0YCH15));
459 newSel = singleEndedSel >> 3;
461 currentSel = (scanInit->scanInputConfig.scanInputSel >> (inputGroup * 8)) & 0xFF;
464 if (currentSel == 0xFF)
466 scanInit->scanInputConfig.scanInputSel &= ~(0xFF << (inputGroup * 8));
467 scanInit->scanInputConfig.scanInputSel |= (newSel << (inputGroup * 8));
469 else if (currentSel == newSel)
480 scanId = (inputGroup * 8) + (singleEndedSel & 0x7);
481 EFM_ASSERT(scanId < 32);
482 scanInit->scanInputConfig.scanInputEn |= 0x1 << scanId;
518 ADC_ScanInputGroup_TypeDef inputGroup,
519 ADC_PosSel_TypeDef posSel,
520 ADC_ScanNegInput_TypeDef negInput)
522 uint32_t negInputRegMask = 0;
523 uint32_t negInputRegShift = 0;
524 uint32_t negInputRegVal = 0;
528 scanId = ADC_ScanSingleEndedInputAdd(scanInit, inputGroup, posSel);
531 scanInit->
diff =
true;
534 if (negInput != adcScanNegInputDefault)
538 negInputRegMask = _ADC_SCANNEGSEL_INPUT0NEGSEL_MASK;
539 negInputRegShift = _ADC_SCANNEGSEL_INPUT0NEGSEL_SHIFT;
540 EFM_ASSERT(inputGroup == 0);
542 else if (scanId == 2)
544 negInputRegMask = _ADC_SCANNEGSEL_INPUT2NEGSEL_MASK;
545 negInputRegShift = _ADC_SCANNEGSEL_INPUT2NEGSEL_SHIFT;
546 EFM_ASSERT(inputGroup == 0);
548 else if (scanId == 4)
550 negInputRegMask = _ADC_SCANNEGSEL_INPUT4NEGSEL_MASK;
551 negInputRegShift = _ADC_SCANNEGSEL_INPUT4NEGSEL_SHIFT;
552 EFM_ASSERT(inputGroup == 0);
554 else if (scanId == 6)
556 negInputRegMask = _ADC_SCANNEGSEL_INPUT6NEGSEL_MASK;
557 negInputRegShift = _ADC_SCANNEGSEL_INPUT6NEGSEL_SHIFT;
558 EFM_ASSERT(inputGroup == 0);
560 else if (scanId == 9)
562 negInputRegMask = _ADC_SCANNEGSEL_INPUT9NEGSEL_MASK;
563 negInputRegShift = _ADC_SCANNEGSEL_INPUT9NEGSEL_SHIFT;
564 EFM_ASSERT(inputGroup == 1);
566 else if (scanId == 11)
568 negInputRegMask = _ADC_SCANNEGSEL_INPUT11NEGSEL_MASK;
569 negInputRegShift = _ADC_SCANNEGSEL_INPUT11NEGSEL_SHIFT;
570 EFM_ASSERT(inputGroup == 1);
572 else if (scanId == 13)
574 negInputRegMask = _ADC_SCANNEGSEL_INPUT13NEGSEL_MASK;
575 negInputRegShift = _ADC_SCANNEGSEL_INPUT13NEGSEL_SHIFT;
576 EFM_ASSERT(inputGroup == 1);
578 else if (scanId == 15)
580 negInputRegMask = _ADC_SCANNEGSEL_INPUT15NEGSEL_MASK;
581 negInputRegShift = _ADC_SCANNEGSEL_INPUT15NEGSEL_SHIFT;
582 EFM_ASSERT(inputGroup == 1);
595 case adcScanNegInput1:
596 negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT1;
599 case adcScanNegInput3:
600 negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT3;
603 case adcScanNegInput5:
604 negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT5;
607 case adcScanNegInput7:
608 negInputRegVal = _ADC_SCANNEGSEL_INPUT0NEGSEL_INPUT7;
617 else if (inputGroup == 1)
622 case adcScanNegInput8:
623 negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT8;
626 case adcScanNegInput10:
627 negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT10;
630 case adcScanNegInput12:
631 negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT12;
634 case adcScanNegInput14:
635 negInputRegVal = _ADC_SCANNEGSEL_INPUT9NEGSEL_INPUT14;
651 scanInit->scanInputConfig.scanNegSel &= ~negInputRegMask;
652 scanInit->scanInputConfig.scanNegSel |= negInputRegVal << negInputRegShift;
683 EFM_ASSERT(ADC_REF_VALID(adc));
689 ADC_LoadDevinfoCal(adc, init->
reference,
true);
692 #if defined ( _ADC_SCANCTRL_PRSSEL_MASK )
696 #if defined ( _ADC_SCANCTRL_INPUTMASK_MASK )
711 #if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
713 #elif defined( _ADC_SCANINPUTSEL_MASK )
722 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
730 #if defined ( _ADC_SCANCTRLX_VREFSEL_MASK )
731 if (init->
reference & ADC_CTRLX_VREFSEL_REG)
734 tmp |= ADC_SCANCTRL_REF_CONF;
744 #if defined( _ADC_SCANCTRL_INPUTMASK_MASK )
751 #if defined ( _ADC_SCANCTRLX_MASK )
752 tmp = adc->SCANCTRLX & ~(_ADC_SCANCTRLX_VREFSEL_MASK
753 | _ADC_SCANCTRLX_PRSSEL_MASK
754 | _ADC_SCANCTRLX_FIFOOFACT_MASK);
755 if (init->
reference & ADC_CTRLX_VREFSEL_REG)
757 tmp |= (init->
reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SCANCTRLX_VREFSEL_SHIFT;
760 tmp |= init->
prsSel << _ADC_SCANCTRLX_PRSSEL_SHIFT;
762 if (init->fifoOverwrite)
764 tmp |= ADC_SCANCTRLX_FIFOOFACT_OVERWRITE;
767 adc->SCANCTRLX = tmp;
770 #if defined( _ADC_CTRL_SCANDMAWU_MASK )
775 #if defined( _ADC_SCANINPUTSEL_MASK )
776 adc->SCANINPUTSEL = init->scanInputConfig.scanInputSel;
777 adc->SCANMASK = init->scanInputConfig.scanInputEn;
778 adc->SCANNEGSEL = init->scanInputConfig.scanNegSel;
782 #if defined( _ADC_BUSCONFLICT_MASK )
784 EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
785 EFM_ASSERT(!(adc->
STATUS & _ADC_STATUS_PROGERR_MASK));
814 EFM_ASSERT(ADC_REF_VALID(adc));
820 ADC_LoadDevinfoCal(adc, init->
reference,
false);
823 #if defined( _ADC_SINGLECTRL_PRSSEL_MASK )
827 #if defined( _ADC_SINGLECTRL_INPUTSEL_MASK )
830 #
if defined( _ADC_SINGLECTRL_POSSEL_MASK )
831 | (init->posSel << _ADC_SINGLECTRL_POSSEL_SHIFT)
833 #
if defined( _ADC_SINGLECTRL_NEGSEL_MASK )
834 | (init->negSel << _ADC_SINGLECTRL_NEGSEL_SHIFT)
859 #if defined ( _ADC_SINGLECTRLX_MASK )
860 if (init->
reference & ADC_CTRLX_VREFSEL_REG)
863 tmp |= ADC_SINGLECTRL_REF_CONF;
875 #if defined ( _ADC_SINGLECTRLX_VREFSEL_MASK )
876 tmp = adc->SINGLECTRLX & (_ADC_SINGLECTRLX_VREFSEL_MASK
877 | _ADC_SINGLECTRLX_PRSSEL_MASK
878 | _ADC_SINGLECTRLX_FIFOOFACT_MASK);
879 if (init->
reference & ADC_CTRLX_VREFSEL_REG)
881 tmp |= ((init->
reference & ~ADC_CTRLX_VREFSEL_REG) << _ADC_SINGLECTRLX_VREFSEL_SHIFT);
884 tmp |= ((init->
prsSel << _ADC_SINGLECTRLX_PRSSEL_SHIFT));
886 if (init->fifoOverwrite)
888 tmp |= ADC_SINGLECTRLX_FIFOOFACT_OVERWRITE;
891 adc->SINGLECTRLX = tmp;
895 #if defined( _ADC_CTRL_SINGLEDMAWU_MASK )
900 #if defined( _ADC_BUSCONFLICT_MASK )
902 EFM_ASSERT(!(tmp & adc->BUSCONFLICT));
903 EFM_ASSERT(!(adc->
STATUS & _ADC_STATUS_PROGERR_MASK));
908 #if defined( _ADC_SCANDATAX_MASK )
926 uint32_t ADC_DataIdScanGet(
ADC_TypeDef *adc, uint32_t *scanId)
931 scanData = adc->SCANDATAX;
932 *scanId = (scanData & _ADC_SCANDATAX_SCANINPUTID_MASK) >> _ADC_SCANDATAX_SCANINPUTID_SHIFT;
933 return (scanData & _ADC_SCANDATAX_DATA_MASK) >> _ADC_SCANDATAX_DATA_SHIFT;
960 if (adcFreq > ADC_MAX_CLOCK)
962 adcFreq = ADC_MAX_CLOCK;
964 else if (adcFreq < ADC_MIN_CLOCK)
966 adcFreq = ADC_MIN_CLOCK;
975 ret = (hfperFreq + adcFreq - 1) / adcFreq;
1001 #if defined( _ADC_SINGLECTRLX_MASK )
1002 adc->SINGLECTRLX = _ADC_SINGLECTRLX_RESETVALUE;
1005 #if defined( _ADC_SCANCTRLX_MASK )
1006 adc->SCANCTRLX = _ADC_SCANCTRLX_RESETVALUE;
1012 #if defined( _ADC_SCANMASK_MASK )
1013 adc->SCANMASK = _ADC_SCANMASK_RESETVALUE;
1015 #if defined( _ADC_SCANINPUTSEL_MASK )
1016 adc->SCANINPUTSEL = _ADC_SCANINPUTSEL_RESETVALUE;
1018 #if defined( _ADC_SCANNEGSEL_MASK )
1019 adc->SCANNEGSEL = _ADC_SCANNEGSEL_RESETVALUE;
1023 #if defined( _ADC_SINGLEFIFOCLEAR_MASK )
1024 adc->SINGLEFIFOCLEAR |= ADC_SINGLEFIFOCLEAR_SINGLEFIFOCLEAR;
1025 adc->SCANFIFOCLEAR |= ADC_SCANFIFOCLEAR_SCANFIFOCLEAR;
1032 #if defined( _ADC_SCANINPUTSEL_MASK )
1060 #if defined( _EFM32_GIANT_FAMILY ) || defined( _EFM32_WONDER_FAMILY )
1066 if ( hfperFreq > 32000000 )
1068 hfperFreq = 32000000;
1072 hfperFreq += 999999;
1073 hfperFreq /= 1000000;
1076 return (uint8_t)(hfperFreq - 1);
Clock management unit (CMU) API.
#define _ADC_CTRL_RESETVALUE
#define _ADC_CTRL_PRESC_MASK
#define ADC_SINGLECTRL_PRSEN
#define _ADC_CAL_SCANOFFSET_SHIFT
#define _ADC_CTRL_TIMEBASE_SHIFT
#define _ADC_SCANCTRL_PRSSEL_SHIFT
Emlib peripheral API "assert" implementation.
#define _ADC_BIASPROG_RESETVALUE
void ADC_Reset(ADC_TypeDef *adc)
Reset ADC to same state as after a HW reset.
#define _ADC_CAL_SINGLEOFFSET_MASK
#define _ADC_SINGLECTRL_PRSSEL_SHIFT
#define _ADC_CTRL_PRESC_SHIFT
#define _ADC_SINGLECTRL_AT_SHIFT
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT
ADC_AcqTime_TypeDef acqTime
__STATIC_INLINE void ADC_IntClear(ADC_TypeDef *adc, uint32_t flags)
Clear one or more pending ADC interrupts.
#define _ADC_SCANCTRL_RES_SHIFT
#define _ADC_SCANCTRL_REF_SHIFT
ADC_SingleInput_TypeDef input
#define _ADC_CTRL_LPFMODE_SHIFT
ADC_PRSSEL_TypeDef prsSel
#define _ADC_IEN_RESETVALUE
#define _ADC_SINGLECTRL_REF_SHIFT
#define _ADC_CAL_SINGLEGAIN_MASK
void ADC_Init(ADC_TypeDef *adc, const ADC_Init_TypeDef *init)
Initialize ADC.
#define ADC_SCANCTRL_PRSEN
ADC_PRSSEL_TypeDef prsSel
#define _ADC_CTRL_TIMEBASE_MASK
uint8_t ADC_TimebaseCalc(uint32_t hfperFreq)
Calculate timebase value in order to get a timebase providing at least 1us.
#define _ADC_CTRL_WARMUPMODE_SHIFT
#define ADC_SINGLECTRL_DIFF
#define ADC_SINGLECTRL_ADJ_LEFT
#define ADC_CTRL_TAILGATE
ADC_Res_TypeDef resolution
#define ADC_SCANCTRL_ADJ_LEFT
#define _ADC_CAL_SCANGAIN_MASK
void ADC_InitSingle(ADC_TypeDef *adc, const ADC_InitSingle_TypeDef *init)
Initialize single ADC sample conversion.
#define _ADC_SCANCTRL_RESETVALUE
#define _ADC_CTRL_OVSRSEL_SHIFT
#define ADC_SINGLECTRL_REP
#define ADC_CMD_SINGLESTOP
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
uint8_t ADC_PrescaleCalc(uint32_t adcFreq, uint32_t hfperFreq)
Calculate prescaler value used to determine ADC clock.
ADC_LPFilter_TypeDef lpfMode
void ADC_InitScan(ADC_TypeDef *adc, const ADC_InitScan_TypeDef *init)
Initialize ADC scan sequence.
Analog to Digital Converter (ADC) peripheral API.
#define _ADC_CAL_SCANOFFSET_MASK
#define _ADC_CAL_SINGLEOFFSET_SHIFT
#define _ADC_SCANCTRL_AT_SHIFT
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
ADC_Ref_TypeDef reference
#define ADC_SCANCTRL_DIFF
#define _ADC_SINGLECTRL_RES_SHIFT
ADC_OvsRateSel_TypeDef ovsRateSel
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
ADC_Ref_TypeDef reference
ADC_Res_TypeDef resolution
#define _ADC_SINGLECTRL_RESETVALUE
#define _ADC_CTRL_LPFMODE_MASK
ADC_AcqTime_TypeDef acqTime
ADC_Warmup_TypeDef warmUpMode
#define _ADC_CAL_SINGLEGAIN_SHIFT