34 #if defined(PCNT_COUNT) && (PCNT_COUNT > 0)
60 #define PCNT_REF_VALID(ref) ((ref) == PCNT0)
61 #elif (PCNT_COUNT == 2)
62 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1))
63 #elif (PCNT_COUNT == 3)
64 #define PCNT_REF_VALID(ref) (((ref) == PCNT0) || ((ref) == PCNT1) || \
67 #error "Undefined number of pulse counters (PCNT)."
89 __STATIC_INLINE
unsigned int PCNT_Map(
PCNT_TypeDef *pcnt)
106 __STATIC_INLINE
void PCNT_Sync(
PCNT_TypeDef *pcnt, uint32_t mask)
143 EFM_ASSERT(PCNT_REF_VALID(pcnt));
181 EFM_ASSERT(PCNT_REF_VALID(pcnt));
194 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > count);
195 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > top);
202 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > count);
203 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > top);
283 EFM_ASSERT(PCNT_REF_VALID(pcnt));
294 #if defined(_PCNT_INPUT_MASK)
315 EFM_ASSERT(PCNT_REF_VALID(pcnt));
368 EFM_ASSERT(PCNT_REF_VALID(pcnt));
435 EFM_ASSERT(PCNT_REF_VALID(pcnt));
448 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->
counter);
449 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > init->
top);
456 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->
counter);
457 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > init->
top);
462 inst = PCNT_Map(pcnt);
464 #if defined(_PCNT_INPUT_MASK)
491 #if defined(PCNT_CTRL_HYST)
498 #if defined(PCNT_CTRL_S1CDIR)
506 #if defined(_PCNT_CTRL_CNTEV_SHIFT)
510 #if defined(_PCNT_CTRL_AUXCNTEV_SHIFT)
517 uint32_t auxCntEventField = 0;
643 EFM_ASSERT(PCNT_REF_VALID(pcnt));
646 inst = PCNT_Map(pcnt);
675 #if defined(PCNT_OVSCFG_FILTLEN_DEFAULT)
693 void PCNT_FilterConfiguration(
PCNT_TypeDef *pcnt,
const PCNT_Filter_TypeDef *config,
bool enable) {
696 EFM_ASSERT(PCNT_REF_VALID(pcnt));
699 ovscfg = ((config->filtLen & _PCNT_OVSCFG_FILTLEN_MASK) << _PCNT_OVSCFG_FILTLEN_SHIFT)
700 | ((config->flutterrm & 0x1) << _PCNT_OVSCFG_FLUTTERRM_SHIFT);
703 PCNT_Sync(pcnt, PCNT_SYNCBUSY_OVSCFG);
704 pcnt->OVSCFG = ovscfg;
720 #if defined(PCNT_CTRL_TCCMODE_DEFAULT)
751 EFM_ASSERT(PCNT_REF_VALID(pcnt));
763 pcnt->
CTRL = (pcnt->
CTRL & (~mask)) | ctrl;
785 EFM_ASSERT(PCNT_REF_VALID(pcnt));
811 EFM_ASSERT(PCNT_REF_VALID(pcnt));
823 EFM_ASSERT((1<<PCNT1_CNT_SIZE) > val);
830 EFM_ASSERT((1<<PCNT2_CNT_SIZE) > val);
Clock management unit (CMU) API.
void PCNT_CounterTopSet(PCNT_TypeDef *pcnt, uint32_t count, uint32_t top)
Set counter and top values.
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
PCNT_TCCPresc_Typedef prescaler
void PCNT_Enable(PCNT_TypeDef *pcnt, PCNT_Mode_TypeDef mode)
Set PCNT operational mode.
Emlib peripheral API "assert" implementation.
#define _PCNT_CTRL_TCCMODE_MASK
#define _PCNT_CTRL_MODE_SHIFT
RAM and peripheral bit-field set and clear API.
void PCNT_TopSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top value.
#define PCNT_CTRL_EDGE_NEG
#define PCNT_SYNCBUSY_TOPB
void PCNT_PRSInputEnable(PCNT_TypeDef *pcnt, PCNT_PRSInput_TypeDef prsInput, bool enable)
Enable/disable the selected PRS input of PCNT.
PCNT_TCCMode_TypeDef mode
#define PCNT_SYNCBUSY_CMD
Pulse Counter (PCNT) peripheral API.
PCNT_CntEvent_TypeDef cntEvent
#define _PCNT_INPUT_S1PRSSEL_SHIFT
#define _PCNT_INPUT_S1PRSEN_SHIFT
#define _PCNT_CTRL_CNTEV_SHIFT
#define _PCNT_CTRL_TCCPRESC_MASK
#define _PCNT_INPUT_S1PRSSEL_MASK
#define _PCNT_TOPB_RESETVALUE
#define _PCNT_CTRL_MODE_MASK
PCNT_CntEvent_TypeDef auxCntEvent
#define _PCNT_IEN_RESETVALUE
#define _PCNT_INPUT_S0PRSSEL_SHIFT
#define PCNT_FREEZE_REGFREEZE
void PCNT_CounterReset(PCNT_TypeDef *pcnt)
Reset PCNT counters and TOP register.
#define PCNT_CTRL_MODE_DISABLE
#define PCNT_CTRL_CNTDIR_DOWN
void PCNT_Init(PCNT_TypeDef *pcnt, const PCNT_Init_TypeDef *init)
Init pulse counter.
#define _PCNT_CTRL_TCCPRESC_SHIFT
PCNT_PRSSel_TypeDef s1PRS
#define _PCNT_CTRL_AUXCNTEV_SHIFT
PCNT_PRSSel_TypeDef s0PRS
PCNT_PRSSel_TypeDef tccPRS
void PCNT_TopBufferSet(PCNT_TypeDef *pcnt, uint32_t val)
Set top buffer value.
#define _PCNT_CTRL_TCCPRSPOL_SHIFT
#define _PCNT_CTRL_RSTEN_SHIFT
#define _PCNT_CTRL_RESETVALUE
#define PCNT_SYNCBUSY_CTRL
#define _PCNT_CTRL_PRSGATEEN_SHIFT
#define _PCNT_INPUT_S0PRSSEL_MASK
void PCNT_FreezeEnable(PCNT_TypeDef *pcnt, bool enable)
PCNT register synchronization freeze control.
#define _PCNT_CTRL_TCCPRSPOL_MASK
#define _PCNT_CTRL_PRSGATEEN_MASK
#define _PCNT_CTRL_TCCPRSSEL_MASK
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _PCNT_CTRL_TCCCOMP_MASK
#define _PCNT_CTRL_TCCMODE_SHIFT
void PCNT_TCCConfiguration(PCNT_TypeDef *pcnt, const PCNT_TCC_TypeDef *config)
Set Triggered Compare and Clear configuration.
PCNT_TCCComp_Typedef compare
#define _PCNT_CTRL_TCCCOMP_SHIFT
void PCNT_Reset(PCNT_TypeDef *pcnt)
Reset PCNT to same state as after a HW reset.
#define _PCNT_INPUT_S0PRSEN_SHIFT
#define _PCNT_CTRL_TCCPRSSEL_SHIFT