34 #if defined(IDAC_COUNT) && (IDAC_COUNT > 0)
52 #if defined(_EFM32_ZERO_FAMILY) || defined(_EFM32_HAPPY_FAMILY)
53 #define ERRATA_FIX_IDAC_E101_EN
81 EFM_ASSERT(IDAC_REF_VALID(idac));
83 tmp = (uint32_t)(init->
prsSel);
116 volatile uint32_t *reg;
118 EFM_ASSERT(IDAC_REF_VALID(idac));
135 EFM_ASSERT(IDAC_REF_VALID(idac));
137 #if defined(ERRATA_FIX_IDAC_E101_EN)
156 #if defined ( _IDAC_CAL_MASK )
174 volatile uint32_t *reg;
176 EFM_ASSERT(IDAC_REF_VALID(idac));
203 #if defined( _IDAC_CURPROG_TUNING_MASK )
208 EFM_ASSERT(IDAC_REF_VALID(idac));
212 #if defined ( _IDAC_CAL_MASK )
236 tmp |= (uint32_t)range;
238 #elif defined( _IDAC_CURPROG_TUNING_MASK )
252 tmp = idac->
CURPROG & ~(_IDAC_CURPROG_TUNING_MASK
259 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_MASK)
260 >> _DEVINFO_IDAC0CAL1_SINKRANGE0TUNING_SHIFT)
261 << _IDAC_CURPROG_TUNING_SHIFT;
265 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_MASK)
266 >> _DEVINFO_IDAC0CAL1_SINKRANGE1TUNING_SHIFT)
267 << _IDAC_CURPROG_TUNING_SHIFT;
271 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_MASK)
272 >> _DEVINFO_IDAC0CAL1_SINKRANGE2TUNING_SHIFT)
273 << _IDAC_CURPROG_TUNING_SHIFT;
277 tmp |= ((diCal1 & _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_MASK)
278 >> _DEVINFO_IDAC0CAL1_SINKRANGE3TUNING_SHIFT)
279 << _IDAC_CURPROG_TUNING_SHIFT;
288 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_MASK)
289 >> _DEVINFO_IDAC0CAL0_SOURCERANGE0TUNING_SHIFT)
290 << _IDAC_CURPROG_TUNING_SHIFT;
294 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_MASK)
295 >> _DEVINFO_IDAC0CAL0_SOURCERANGE1TUNING_SHIFT)
296 << _IDAC_CURPROG_TUNING_SHIFT;
300 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_MASK)
301 >> _DEVINFO_IDAC0CAL0_SOURCERANGE2TUNING_SHIFT)
302 << _IDAC_CURPROG_TUNING_SHIFT;
306 tmp |= ((diCal0 & _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_MASK)
307 >> _DEVINFO_IDAC0CAL0_SOURCERANGE3TUNING_SHIFT)
308 << _IDAC_CURPROG_TUNING_SHIFT;
313 tmp |= (uint32_t)range;
316 #warning "IDAC calibration register definition unknown."
337 EFM_ASSERT(IDAC_REF_VALID(idac));
359 volatile uint32_t *reg;
361 EFM_ASSERT(IDAC_REF_VALID(idac));
Clock management unit (CMU) API.
IDAC_PRSSEL_TypeDef prsSel
#define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT
Emlib peripheral API "assert" implementation.
#define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT
#define _DEVINFO_IDAC0CAL0_RANGE2_MASK
RAM and peripheral bit-field set and clear API.
#define _DEVINFO_IDAC0CAL0_RANGE0_MASK
Current Digital to Analog Converter (IDAC) peripheral API.
#define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT
#define IDAC_CTRL_CURSINK
#define _IDAC_CTRL_RESETVALUE
#define _IDAC_DUTYCONFIG_RESETVALUE
void IDAC_Enable(IDAC_TypeDef *idac, bool enable)
Enable/disable IDAC.
void IDAC_MinimalOutputTransitionMode(IDAC_TypeDef *idac, bool enable)
Enable/disable Minimal Output Transition mode.
#define _IDAC_CAL_RESETVALUE
#define _IDAC_CTRL_OUTEN_SHIFT
#define _IDAC_CTRL_MINOUTTRANS_SHIFT
void IDAC_RangeSet(IDAC_TypeDef *idac, const IDAC_Range_TypeDef range)
Set the current range of the IDAC output.
#define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT
#define _IDAC_CURPROG_RANGESEL_MASK
void IDAC_Init(IDAC_TypeDef *idac, const IDAC_Init_TypeDef *init)
Initialize IDAC.
#define _DEVINFO_IDAC0CAL0_RANGE1_MASK
IDAC_OutMode_TypeDef outMode
void IDAC_StepSet(IDAC_TypeDef *idac, const uint32_t step)
Set the current step of the IDAC output.
#define _IDAC_CURPROG_RESETVALUE
#define _IDAC_CURPROG_STEPSEL_SHIFT
#define IDAC_CTRL_OUTENPRS
#define _IDAC_CTRL_EN_SHIFT
#define IDAC_DUTYCONFIG_DUTYCYCLEEN
#define _IDAC_CURPROG_STEPSEL_MASK
void IDAC_Reset(IDAC_TypeDef *idac)
Reset IDAC to same state as after a HW reset.
void IDAC_OutEnable(IDAC_TypeDef *idac, bool enable)
Enable/disable the IDAC OUT pin.
#define _DEVINFO_IDAC0CAL0_RANGE3_MASK
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _IDAC_CURPROG_RANGESEL_SHIFT
#define IDAC_CURPROG_RANGESEL_RANGE0