EFM32 Leopard Gecko Software Documentation  efm32lg-doc-4.2.1
em_usart.c
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1 /***************************************************************************/
34 #include "em_usart.h"
35 #if defined(USART_COUNT) && (USART_COUNT > 0)
36 
37 #include "em_cmu.h"
38 #include "em_bus.h"
39 #include "em_assert.h"
40 
41 /***************************************************************************/
46 /***************************************************************************/
53 /*******************************************************************************
54  ******************************* DEFINES ***********************************
55  ******************************************************************************/
56 
61 #if (USART_COUNT == 1) && defined(USART0)
62 #define USART_REF_VALID(ref) ((ref) == USART0)
63 
64 #elif (USART_COUNT == 1) && defined(USART1)
65 #define USART_REF_VALID(ref) ((ref) == USART1)
66 
67 #elif (USART_COUNT == 2) && defined(USART2)
68 #define USART_REF_VALID(ref) (((ref) == USART1) || ((ref) == USART2))
69 
70 #elif (USART_COUNT == 2)
71 #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
72 
73 #elif (USART_COUNT == 3)
74 #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
75  ((ref) == USART2))
76 #elif (USART_COUNT == 4)
77 #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
78  ((ref) == USART2) || ((ref) == USART3))
79 #elif (USART_COUNT == 5)
80 #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
81  ((ref) == USART2) || ((ref) == USART3) || \
82  ((ref) == USART4))
83 #elif (USART_COUNT == 6)
84 #define USART_REF_VALID(ref) (((ref) == USART0) || ((ref) == USART1) || \
85  ((ref) == USART2) || ((ref) == USART3) || \
86  ((ref) == USART4) || ((ref) == USART5))
87 #else
88 #error "Undefined number of USARTs."
89 #endif
90 
91 #if defined(USARTRF_COUNT) && (USARTRF_COUNT > 0)
92 #if (USARTRF_COUNT == 1) && defined(USARTRF0)
93 #define USARTRF_REF_VALID(ref) ((ref) == USARTRF0)
94 #elif (USARTRF_COUNT == 1) && defined(USARTRF1)
95 #define USARTRF_REF_VALID(ref) ((ref) == USARTRF1)
96 #else
97 #define USARTRF_REF_VALID(ref) (0)
98 #endif
99 #else
100 #define USARTRF_REF_VALID(ref) (0)
101 #endif
102 
103 #if defined(_EZR32_HAPPY_FAMILY)
104 #define USART_IRDA_VALID(ref) ((ref) == USART0)
105 #elif defined(_EFM32_HAPPY_FAMILY)
106 #define USART_IRDA_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
107 #elif defined(USART0)
108 #define USART_IRDA_VALID(ref) ((ref) == USART0)
109 #elif (USART_COUNT == 1) && defined(USART1)
110 #define USART_IRDA_VALID(ref) ((ref) == USART1)
111 #else
112 #define USART_IRDA_VALID(ref) (0)
113 #endif
114 
115 #if defined(_EZR32_HAPPY_FAMILY)
116 #define USART_I2S_VALID(ref) ((ref) == USART0)
117 #elif defined(_EFM32_HAPPY_FAMILY)
118 #define USART_I2S_VALID(ref) (((ref) == USART0) || ((ref) == USART1))
119 #elif defined(_EFM32_TINY_FAMILY) || defined(_EFM32_ZERO_FAMILY) || defined(_SILICON_LABS_32B_PLATFORM_2)
120 #define USART_I2S_VALID(ref) ((ref) == USART1)
121 #elif defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
122 #define USART_I2S_VALID(ref) (((ref) == USART1) || ((ref) == USART2))
123 #endif
124 
125 #if (UART_COUNT == 1)
126 #define UART_REF_VALID(ref) ((ref) == UART0)
127 #elif (UART_COUNT == 2)
128 #define UART_REF_VALID(ref) (((ref) == UART0) || ((ref) == UART1))
129 #else
130 #define UART_REF_VALID(ref) (0)
131 #endif
132 
136 /*******************************************************************************
137  ************************** GLOBAL FUNCTIONS *******************************
138  ******************************************************************************/
139 
140 /***************************************************************************/
163  uint32_t refFreq,
164  uint32_t baudrate,
165  USART_OVS_TypeDef ovs)
166 {
167  uint32_t clkdiv;
168  uint32_t oversample;
169 
170  /* Inhibit divide by 0 */
171  EFM_ASSERT(baudrate);
172 
173  /*
174  * We want to use integer division to avoid forcing in float division
175  * utils, and yet keep rounding effect errors to a minimum.
176  *
177  * CLKDIV in asynchronous mode is given by:
178  *
179  * CLKDIV = 256 * (fHFPERCLK/(oversample * br) - 1)
180  * or
181  * CLKDIV = (256 * fHFPERCLK)/(oversample * br) - 256
182  *
183  * The basic problem with integer division in the above formula is that
184  * the dividend (256 * fHFPERCLK) may become higher than max 32 bit
185  * integer. Yet, we want to evaluate dividend first before dividing in
186  * order to get as small rounding effects as possible. We do not want
187  * to make too harsh restrictions on max fHFPERCLK value either.
188  *
189  * One can possibly factorize 256 and oversample/br. However,
190  * since the last 6 or 3 bits of CLKDIV are don't care, we can base our
191  * integer arithmetic on the below formula
192  *
193  * CLKDIV / 64 = (4 * fHFPERCLK)/(oversample * br) - 4 (3 bits dont care)
194  * or
195  * CLKDIV / 8 = (32 * fHFPERCLK)/(oversample * br) - 32 (6 bits dont care)
196  *
197  * and calculate 1/64 of CLKDIV first. This allows for fHFPERCLK
198  * up to 1GHz without overflowing a 32 bit value!
199  */
200 
201  /* HFPERCLK used to clock all USART/UART peripheral modules */
202  if (!refFreq)
203  {
204  refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
205  }
206 
207  /* Map oversampling */
208  switch (ovs)
209  {
210  case USART_CTRL_OVS_X16:
211  EFM_ASSERT(baudrate <= (refFreq / 16));
212  oversample = 16;
213  break;
214 
215  case USART_CTRL_OVS_X8:
216  EFM_ASSERT(baudrate <= (refFreq / 8));
217  oversample = 8;
218  break;
219 
220  case USART_CTRL_OVS_X6:
221  EFM_ASSERT(baudrate <= (refFreq / 6));
222  oversample = 6;
223  break;
224 
225  case USART_CTRL_OVS_X4:
226  EFM_ASSERT(baudrate <= (refFreq / 4));
227  oversample = 4;
228  break;
229 
230  default:
231  /* Invalid input */
232  EFM_ASSERT(0);
233  return;
234  }
235 
236  /* Calculate and set CLKDIV with fractional bits.
237  * The addend (oversample*baudrate)/2 in the first line is to round the
238  * divisor up by half the divisor before the division in order to reduce the
239  * integer division error, which consequently results in a higher baudrate
240  * than desired. */
241 #if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
242  clkdiv = 32 * refFreq + (oversample * baudrate) / 2;
243  clkdiv /= (oversample * baudrate);
244  clkdiv -= 32;
245  clkdiv *= 8;
246 #else
247  clkdiv = 4 * refFreq + (oversample * baudrate) / 2;
248  clkdiv /= (oversample * baudrate);
249  clkdiv -= 4;
250  clkdiv *= 64;
251 #endif
252 
253  /* Verify that resulting clock divider is within limits */
254  EFM_ASSERT(clkdiv <= _USART_CLKDIV_DIV_MASK);
255 
256  /* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
257  clkdiv &= _USART_CLKDIV_DIV_MASK;
258 
259  usart->CTRL &= ~_USART_CTRL_OVS_MASK;
260  usart->CTRL |= ovs;
261  usart->CLKDIV = clkdiv;
262 }
263 
264 
265 /***************************************************************************/
293 uint32_t USART_BaudrateCalc(uint32_t refFreq,
294  uint32_t clkdiv,
295  bool syncmode,
296  USART_OVS_TypeDef ovs)
297 {
298  uint32_t oversample;
299  uint64_t divisor;
300  uint64_t factor;
301  uint64_t remainder;
302  uint64_t quotient;
303  uint32_t br;
304 
305  /* Mask out unused bits */
306  clkdiv &= _USART_CLKDIV_MASK;
307 
308  /* We want to use integer division to avoid forcing in float division */
309  /* utils, and yet keep rounding effect errors to a minimum. */
310 
311  /* Baudrate calculation depends on if synchronous or asynchronous mode */
312  if (syncmode)
313  {
314  /*
315  * Baudrate is given by:
316  *
317  * br = fHFPERCLK/(2 * (1 + (CLKDIV / 256)))
318  *
319  * which can be rewritten to
320  *
321  * br = (128 * fHFPERCLK)/(256 + CLKDIV)
322  */
323  oversample = 1; /* Not used in sync mode, ie 1 */
324  factor = 128;
325  }
326  else
327  {
328  /*
329  * Baudrate in asynchronous mode is given by:
330  *
331  * br = fHFPERCLK/(oversample * (1 + (CLKDIV / 256)))
332  *
333  * which can be rewritten to
334  *
335  * br = (256 * fHFPERCLK)/(oversample * (256 + CLKDIV))
336  *
337  * First of all we can reduce the 256 factor of the dividend with
338  * (part of) oversample part of the divisor.
339  */
340 
341  switch (ovs)
342  {
343  case USART_CTRL_OVS_X16:
344  oversample = 1;
345  factor = 256 / 16;
346  break;
347 
348  case USART_CTRL_OVS_X8:
349  oversample = 1;
350  factor = 256 / 8;
351  break;
352 
353  case USART_CTRL_OVS_X6:
354  oversample = 3;
355  factor = 256 / 2;
356  break;
357 
358  default:
359  oversample = 1;
360  factor = 256 / 4;
361  break;
362  }
363  }
364 
365  /*
366  * The basic problem with integer division in the above formula is that
367  * the dividend (factor * fHFPERCLK) may become larger than a 32 bit
368  * integer. Yet we want to evaluate dividend first before dividing in
369  * order to get as small rounding effects as possible. We do not want
370  * to make too harsh restrictions on max fHFPERCLK value either.
371  *
372  * For division a/b, we can write
373  *
374  * a = qb + r
375  *
376  * where q is the quotient and r is the remainder, both integers.
377  *
378  * The orignal baudrate formula can be rewritten as
379  *
380  * br = xa / b = x(qb + r)/b = xq + xr/b
381  *
382  * where x is 'factor', a is 'refFreq' and b is 'divisor', referring to
383  * variable names.
384  */
385 
386  /* Divisor will never exceed max 32 bit value since clkdiv <= 0xFFFFF8 */
387  /* and 'oversample' has been reduced to <= 3. */
388  divisor = oversample * (256 + clkdiv);
389 
390  quotient = refFreq / divisor;
391  remainder = refFreq % divisor;
392 
393  /* factor <= 128 and since divisor >= 256, the below cannot exceed max */
394  /* 32 bit value. However, factor * remainder can become larger than 32-bit */
395  /* because of the size of _USART_CLKDIV_DIV_MASK on some families. */
396  br = (uint32_t)(factor * quotient);
397 
398  /*
399  * factor <= 128 and remainder < (oversample*(256 + clkdiv)), which
400  * means dividend (factor * remainder) worst case is
401  * 128 * (3 * (256 + _USART_CLKDIV_DIV_MASK)) = 0x1_8001_7400.
402  */
403  br += (uint32_t)((factor * remainder) / divisor);
404 
405  return br;
406 }
407 
408 
409 /***************************************************************************/
424 {
425  uint32_t freq;
426  USART_OVS_TypeDef ovs;
427  bool syncmode;
428 
429  if (usart->CTRL & USART_CTRL_SYNC)
430  {
431  syncmode = true;
432  }
433  else
434  {
435  syncmode = false;
436  }
437 
438  /* HFPERCLK used to clock all USART/UART peripheral modules */
440  ovs = (USART_OVS_TypeDef)(usart->CTRL & _USART_CTRL_OVS_MASK);
441  return USART_BaudrateCalc(freq, usart->CLKDIV, syncmode, ovs);
442 }
443 
444 
445 /***************************************************************************/
472 void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate)
473 {
474 #if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
475  uint64_t clkdiv;
476 #else
477  uint32_t clkdiv;
478 #endif
479 
480  /* Inhibit divide by 0 */
481  EFM_ASSERT(baudrate);
482 
483  /*
484  * CLKDIV in synchronous mode is given by:
485  *
486  * CLKDIV = 256 * (fHFPERCLK/(2 * br) - 1)
487  */
488 
489  /* HFPERCLK used to clock all USART/UART peripheral modules */
490  if (!refFreq)
491  {
492  refFreq = CMU_ClockFreqGet(cmuClock_HFPER);
493  }
494 
495 #if defined(_USART_CLKDIV_DIV_MASK) && (_USART_CLKDIV_DIV_MASK >= 0x7FFFF8UL)
496  /* Calculate and set CLKDIV without fractional bits */
497  clkdiv = 2 * baudrate;
498  clkdiv = (0x100ULL * (uint64_t)refFreq) / clkdiv;
499 
500  /* Round up by not subtracting 256 and mask off fractional part */
501  clkdiv &= ~0xFF;
502 #else
503  /* Calculate and set CLKDIV with fractional bits */
504  clkdiv = 2 * refFreq;
505  clkdiv += baudrate - 1;
506  clkdiv /= baudrate;
507  clkdiv -= 4;
508  clkdiv *= 64;
509  /* Make sure we don't use fractional bits by rounding CLKDIV */
510  /* up (and thus reducing baudrate, not increasing baudrate above */
511  /* specified value). */
512  clkdiv += 0xc0;
513  clkdiv &= 0xffffff00;
514 #endif
515 
516  /* Verify that resulting clock divider is within limits */
517  EFM_ASSERT(!(clkdiv & ~_USART_CLKDIV_DIV_MASK));
518 
519  /* If EFM_ASSERT is not enabled, make sure we don't write to reserved bits */
520  clkdiv &= _USART_CLKDIV_DIV_MASK;
521 
523 }
524 
525 
526 /***************************************************************************/
542 {
543  uint32_t tmp;
544 
545  /* Make sure the module exists on the selected chip */
546  EFM_ASSERT( USART_REF_VALID(usart)
547  || USARTRF_REF_VALID(usart)
548  || UART_REF_VALID(usart) );
549 
550  /* Disable as specified */
551  tmp = ~((uint32_t) (enable));
553  usart->CMD = tmp << 1;
554 
555  /* Enable as specified */
556  usart->CMD = (uint32_t) (enable);
557 }
558 
559 
560 /***************************************************************************/
584 {
585  /* Make sure the module exists on the selected chip */
586  EFM_ASSERT( USART_REF_VALID(usart)
587  || USARTRF_REF_VALID(usart)
588  || UART_REF_VALID(usart) );
589 
590  /* Init USART registers to HW reset state. */
591  USART_Reset(usart);
592 
593 #if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
594  /* Disable majority vote if specified. */
595  if (init->mvdis)
596  {
597  usart->CTRL |= USART_CTRL_MVDIS;
598  }
599 
600  /* Configure PRS input mode. */
601  if (init->prsRxEnable)
602  {
603  usart->INPUT = (uint32_t) init->prsRxCh | USART_INPUT_RXPRS;
604  }
605 #endif
606 
607  /* Configure databits, stopbits and parity */
608  usart->FRAME = (uint32_t)init->databits
609  | (uint32_t)init->stopbits
610  | (uint32_t)init->parity;
611 
612  /* Configure baudrate */
613  USART_BaudrateAsyncSet(usart, init->refFreq, init->baudrate, init->oversampling);
614 
615 #if defined(_USART_TIMING_CSHOLD_MASK)
616  usart->TIMING = ((init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT)
617  & _USART_TIMING_CSHOLD_MASK)
618  | ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
619  & _USART_TIMING_CSSETUP_MASK);
620  if (init->autoCsEnable)
621  {
622  usart->CTRL |= USART_CTRL_AUTOCS;
623  }
624 #endif
625  /* Finally enable (as specified) */
626  usart->CMD = (uint32_t)init->enable;
627 }
628 
629 
630 /***************************************************************************/
655 {
656  /* Make sure the module exists on the selected chip */
657  EFM_ASSERT( USART_REF_VALID(usart) || USARTRF_REF_VALID(usart) );
658 
659  /* Init USART registers to HW reset state. */
660  USART_Reset(usart);
661 
662  /* Set bits for synchronous mode */
663  usart->CTRL |= (USART_CTRL_SYNC)
664  | (uint32_t)init->clockMode
665  | (init->msbf ? USART_CTRL_MSBF : 0);
666 
667 #if defined(_USART_CTRL_AUTOTX_MASK)
668  usart->CTRL |= init->autoTx ? USART_CTRL_AUTOTX : 0;
669 #endif
670 
671 #if defined(_USART_INPUT_RXPRS_MASK)
672  /* Configure PRS input mode. */
673  if (init->prsRxEnable)
674  {
675  usart->INPUT = (uint32_t)init->prsRxCh | USART_INPUT_RXPRS;
676  }
677 #endif
678 
679  /* Configure databits, leave stopbits and parity at reset default (not used) */
680  usart->FRAME = (uint32_t)init->databits
683 
684  /* Configure baudrate */
685  USART_BaudrateSyncSet(usart, init->refFreq, init->baudrate);
686 
687  /* Finally enable (as specified) */
688  if (init->master)
689  {
690  usart->CMD = USART_CMD_MASTEREN;
691  }
692 
693 #if defined(_USART_TIMING_CSHOLD_MASK)
694  usart->TIMING = ((init->autoCsHold << _USART_TIMING_CSHOLD_SHIFT)
695  & _USART_TIMING_CSHOLD_MASK)
696  | ((init->autoCsSetup << _USART_TIMING_CSSETUP_SHIFT)
697  & _USART_TIMING_CSSETUP_MASK);
698  if (init->autoCsEnable)
699  {
700  usart->CTRL |= USART_CTRL_AUTOCS;
701  }
702 #endif
703 
704  usart->CMD = (uint32_t)init->enable;
705 }
706 
707 
708 #if defined(USART0) || ((USART_COUNT == 1) && defined(USART1))
709 /***************************************************************************/
736 {
737  #if (USART_COUNT == 1) && defined(USART1)
738  USART_TypeDef *usart = USART1;
739  #else
740  USART_TypeDef *usart = USART0;
741  #endif
742 
743  /* Init USART as async device */
744  USART_InitAsync(usart, &(init->async));
745 
746  /* Set IrDA modulation to RZI (return-to-zero-inverted) */
747  usart->CTRL |= USART_CTRL_TXINV;
748 
749  /* Invert Rx signal before demodulator if enabled */
750  if (init->irRxInv)
751  {
752  usart->CTRL |= USART_CTRL_RXINV;
753  }
754 
755  /* Configure IrDA */
756  usart->IRCTRL |= (uint32_t)init->irPw
757  | (uint32_t)init->irPrsSel
758  | ((uint32_t)init->irFilt << _USART_IRCTRL_IRFILT_SHIFT)
759  | ((uint32_t)init->irPrsEn << _USART_IRCTRL_IRPRSEN_SHIFT);
760 
761  /* Enable IrDA */
762  usart->IRCTRL |= USART_IRCTRL_IREN;
763 }
764 #endif
765 
766 
767 #if defined(_USART_I2SCTRL_MASK)
768 /***************************************************************************/
798 {
799  USART_Enable_TypeDef enable;
800 
801  /* Make sure the module exists on the selected chip */
802  EFM_ASSERT(USART_I2S_VALID(usart));
803 
804  /* Override the enable setting. */
805  enable = init->sync.enable;
806  init->sync.enable = usartDisable;
807 
808  /* Init USART as a sync device. */
809  USART_InitSync(usart, &init->sync);
810 
811  /* Configure and enable I2CCTRL register acording to selected mode. */
812  usart->I2SCTRL = (uint32_t)init->format
813  | (uint32_t)init->justify
814  | (init->delay ? USART_I2SCTRL_DELAY : 0)
815  | (init->dmaSplit ? USART_I2SCTRL_DMASPLIT : 0)
816  | (init->mono ? USART_I2SCTRL_MONO : 0)
818 
819  if (enable != usartDisable)
820  {
821  USART_Enable(usart, enable);
822  }
823 }
824 #endif
825 
826 
827 /***************************************************************************/
837 {
838  uint32_t trigctrl;
839 
840  /* Clear values that will be reconfigured */
841  trigctrl = usart->TRIGCTRL & ~(_USART_TRIGCTRL_RXTEN_MASK
843 #if defined(USART_TRIGCTRL_AUTOTXTEN)
845 #endif
847 
848 #if defined(USART_TRIGCTRL_AUTOTXTEN)
849  if (init->autoTxTriggerEnable)
850  {
851  trigctrl |= USART_TRIGCTRL_AUTOTXTEN;
852  }
853 #endif
854  if (init->txTriggerEnable)
855  {
856  trigctrl |= USART_TRIGCTRL_TXTEN;
857  }
858  if (init->rxTriggerEnable)
859  {
860  trigctrl |= USART_TRIGCTRL_RXTEN;
861  }
862  trigctrl |= init->prsTriggerChannel;
863 
864  /* Enable new configuration */
865  usart->TRIGCTRL = trigctrl;
866 }
867 
868 
869 /***************************************************************************/
877 {
878  /* Make sure the module exists on the selected chip */
879  EFM_ASSERT( USART_REF_VALID(usart)
880  || USARTRF_REF_VALID(usart)
881  || UART_REF_VALID(usart) );
882 
883  /* Make sure disabled first, before resetting other registers */
887  usart->CTRL = _USART_CTRL_RESETVALUE;
891  usart->IEN = _USART_IEN_RESETVALUE;
892  usart->IFC = _USART_IFC_MASK;
893 #if defined(_USART_ROUTEPEN_MASK) || defined(_UART_ROUTEPEN_MASK)
894  usart->ROUTEPEN = _USART_ROUTEPEN_RESETVALUE;
895  usart->ROUTELOC0 = _USART_ROUTELOC0_RESETVALUE;
896  usart->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
897 #else
899 #endif
900 
901  if (USART_IRDA_VALID(usart))
902  {
904  }
905 
906 #if defined(_USART_INPUT_RESETVALUE)
908 #endif
909 
910 #if defined(_USART_I2SCTRL_RESETVALUE)
911  if (USART_I2S_VALID(usart))
912  {
914  }
915 #endif
916 }
917 
918 
919 /***************************************************************************/
943 uint8_t USART_Rx(USART_TypeDef *usart)
944 {
945  while (!(usart->STATUS & USART_STATUS_RXDATAV))
946  ;
947 
948  return (uint8_t)usart->RXDATA;
949 }
950 
951 
952 /***************************************************************************/
977 {
978  while (!(usart->STATUS & USART_STATUS_RXFULL))
979  ;
980 
981  return (uint16_t)usart->RXDOUBLE;
982 }
983 
984 
985 /***************************************************************************/
1010 {
1011  while (!(usart->STATUS & USART_STATUS_RXFULL))
1012  ;
1013 
1014  return usart->RXDOUBLEX;
1015 }
1016 
1017 
1018 /***************************************************************************/
1042 uint16_t USART_RxExt(USART_TypeDef *usart)
1043 {
1044  while (!(usart->STATUS & USART_STATUS_RXDATAV))
1045  ;
1046 
1047  return (uint16_t)usart->RXDATAX;
1048 }
1049 
1050 
1051 /***************************************************************************/
1070 uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data)
1071 {
1072  while (!(usart->STATUS & USART_STATUS_TXBL))
1073  ;
1074  usart->TXDATA = (uint32_t)data;
1075  while (!(usart->STATUS & USART_STATUS_TXC))
1076  ;
1077  return (uint8_t)usart->RXDATA;
1078 }
1079 
1080 
1081 /***************************************************************************/
1104 void USART_Tx(USART_TypeDef *usart, uint8_t data)
1105 {
1106  /* Check that transmit buffer is empty */
1107  while (!(usart->STATUS & USART_STATUS_TXBL))
1108  ;
1109  usart->TXDATA = (uint32_t)data;
1110 }
1111 
1112 
1113 /***************************************************************************/
1140 void USART_TxDouble(USART_TypeDef *usart, uint16_t data)
1141 {
1142  /* Check that transmit buffer is empty */
1143  while (!(usart->STATUS & USART_STATUS_TXBL))
1144  ;
1145  usart->TXDOUBLE = (uint32_t)data;
1146 }
1147 
1148 
1149 /***************************************************************************/
1176 void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data)
1177 {
1178  /* Check that transmit buffer is empty */
1179  while (!(usart->STATUS & USART_STATUS_TXBL))
1180  ;
1181  usart->TXDOUBLEX = data;
1182 }
1183 
1184 
1185 /***************************************************************************/
1204 void USART_TxExt(USART_TypeDef *usart, uint16_t data)
1205 {
1206  /* Check that transmit buffer is empty */
1207  while (!(usart->STATUS & USART_STATUS_TXBL))
1208  ;
1209  usart->TXDATAX = (uint32_t)data;
1210 }
1211 
1212 
1215 #endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
Clock management unit (CMU) API.
USART_Stopbits_TypeDef stopbits
Definition: em_usart.h:275
USART_I2sJustify_TypeDef justify
Definition: em_usart.h:534
#define USART_CTRL_MVDIS
__IO uint32_t TXDOUBLEX
Definition: efm32lg_usart.h:57
#define _USART_CTRL_RESETVALUE
Definition: efm32lg_usart.h:75
void USART_Tx(USART_TypeDef *usart, uint8_t data)
Transmit one 4-9 bit frame.
Definition: em_usart.c:1104
__IO uint32_t IRCTRL
Definition: efm32lg_usart.h:63
#define USART_STATUS_TXBL
#define USART_CTRL_AUTOCS
#define USART_TRIGCTRL_AUTOTXTEN
#define _USART_CMD_RXEN_MASK
Emlib peripheral API "assert" implementation.
USART_PrsTriggerCh_TypeDef prsTriggerChannel
Definition: em_usart.h:309
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init)
Init USART for synchronous mode.
Definition: em_usart.c:654
__IO uint32_t TRIGCTRL
Definition: efm32lg_usart.h:45
USART_OVS_TypeDef oversampling
Definition: em_usart.h:265
#define USART_CMD_TXDIS
#define _USART_CLKDIV_RESETVALUE
RAM and peripheral bit-field set and clear API.
void USART_BaudrateSyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate)
Configure USART operating in synchronous mode to use a given baudrate (or as close as possible to spe...
Definition: em_usart.c:472
__I uint32_t RXDOUBLE
Definition: efm32lg_usart.h:52
#define USART_CMD_CLEARTX
USART_Databits_TypeDef databits
Definition: em_usart.h:269
uint8_t USART_Rx(USART_TypeDef *usart)
Receive one 4-8 bit frame, (or part of 10-16 bit frame).
Definition: em_usart.c:943
USART_InitAsync_TypeDef async
Definition: em_usart.h:473
void USART_TxDoubleExt(USART_TypeDef *usart, uint32_t data)
Transmit two 4-9 bit frames, or one 10-16 bit frame with extended control.
Definition: em_usart.c:1176
#define USART_I2SCTRL_MONO
USART_InitSync_TypeDef sync
Definition: em_usart.h:520
uint32_t USART_RxDoubleExt(USART_TypeDef *usart)
Receive two 4-9 bit frames, or one 10-16 bit frame with extended information.
Definition: em_usart.c:1009
uint32_t USART_BaudrateCalc(uint32_t refFreq, uint32_t clkdiv, bool syncmode, USART_OVS_TypeDef ovs)
Calculate baudrate for USART/UART given reference frequency, clock division and oversampling rate (if...
Definition: em_usart.c:293
#define _USART_FRAME_RESETVALUE
USART_PrsRxCh_TypeDef prsRxCh
Definition: em_usart.h:407
__IO uint32_t ROUTE
Definition: efm32lg_usart.h:64
USART_IrDAPw_Typedef irPw
Definition: em_usart.h:483
USART_Parity_TypeDef parity
Definition: em_usart.h:272
Universal synchronous/asynchronous receiver/transmitter (USART/UART) peripheral API.
USART_Enable_TypeDef enable
Definition: em_usart.h:253
#define USART_FRAME_STOPBITS_DEFAULT
#define _USART_TRIGCTRL_AUTOTXTEN_MASK
__IO uint32_t IFC
Definition: efm32lg_usart.h:61
#define USART_CTRL_OVS_X6
__IO uint32_t INPUT
Definition: efm32lg_usart.h:65
#define _USART_IRCTRL_IRPRSEN_SHIFT
#define USART_STATUS_RXDATAV
USART_I2sFormat_TypeDef format
Definition: em_usart.h:523
#define USART_CTRL_OVS_X8
#define USART_TRIGCTRL_RXTEN
void USART_InitIrDA(const USART_InitIrDA_TypeDef *init)
Init USART0 for asynchronous IrDA mode.
Definition: em_usart.c:735
#define USART_CTRL_SYNC
Definition: efm32lg_usart.h:77
__IO uint32_t CTRL
Definition: efm32lg_usart.h:43
#define USART_TRIGCTRL_TXTEN
#define USART_CMD_CLEARRX
uint16_t USART_RxExt(USART_TypeDef *usart)
Receive one 4-9 bit frame, (or part of 10-16 bit frame) with extended information.
Definition: em_usart.c:1042
#define _USART_CLKDIV_DIV_MASK
#define USART_CMD_RXDIS
#define USART_I2SCTRL_DELAY
#define USART_FRAME_PARITY_DEFAULT
__I uint32_t RXDATA
Definition: efm32lg_usart.h:50
#define _USART_INPUT_RESETVALUE
#define _USART_CTRL_OVS_MASK
#define USART_CTRL_OVS_X4
#define USART_CMD_MASTEREN
__IO uint32_t TXDOUBLE
Definition: efm32lg_usart.h:58
USART_IrDAPrsSel_Typedef irPrsSel
Definition: em_usart.h:491
#define USART_STATUS_RXFULL
__I uint32_t RXDATAX
Definition: efm32lg_usart.h:49
__IO uint32_t IEN
Definition: efm32lg_usart.h:62
USART_ClockMode_TypeDef clockMode
Definition: em_usart.h:400
#define USART_CTRL_TXINV
__IO uint32_t I2SCTRL
Definition: efm32lg_usart.h:66
#define USART_CMD_RXBLOCKDIS
__IO uint32_t CMD
Definition: efm32lg_usart.h:46
USART_Enable_TypeDef enable
Definition: em_usart.h:379
void USART_TxExt(USART_TypeDef *usart, uint16_t data)
Transmit one 4-9 bit frame with extended control.
Definition: em_usart.c:1204
#define _USART_IEN_RESETVALUE
USART_Databits_TypeDef databits
Definition: em_usart.h:391
__IO uint32_t CLKDIV
Definition: efm32lg_usart.h:48
#define _USART_TRIGCTRL_RESETVALUE
__I uint32_t STATUS
Definition: efm32lg_usart.h:47
#define USART_CMD_TXTRIDIS
void USART_Reset(USART_TypeDef *usart)
Reset USART/UART to same state as after a HW reset.
Definition: em_usart.c:876
__I uint32_t RXDOUBLEX
Definition: efm32lg_usart.h:51
#define USART0
#define USART_CTRL_AUTOTX
#define USART_CTRL_MSBF
uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data)
Perform one 8 bit frame SPI transfer.
Definition: em_usart.c:1070
#define _USART_IFC_MASK
#define _USART_ROUTE_RESETVALUE
USART_OVS_TypeDef
Definition: em_usart.h:99
__STATIC_INLINE void BUS_RegMaskedWrite(volatile uint32_t *addr, uint32_t mask, uint32_t val)
Perform peripheral register masked clear and value write.
Definition: em_bus.h:283
__IO uint32_t TXDATAX
Definition: efm32lg_usart.h:55
#define USART_I2SCTRL_EN
void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init)
Init USART for I2S mode.
Definition: em_usart.c:797
__IO uint32_t TXDATA
Definition: efm32lg_usart.h:56
USART_Enable_TypeDef
Definition: em_usart.h:82
#define USART1
#define _USART_CMD_TXEN_MASK
#define USART_INPUT_RXPRS
#define _USART_TRIGCTRL_TSEL_MASK
#define USART_STATUS_TXC
void USART_Enable(USART_TypeDef *usart, USART_Enable_TypeDef enable)
Enable/disable USART/UART receiver and/or transmitter.
Definition: em_usart.c:541
void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init)
Initialize automatic transmissions using PRS channel as trigger.
Definition: em_usart.c:836
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init)
Init USART/UART for normal asynchronous mode.
Definition: em_usart.c:583
#define USART_I2SCTRL_DMASPLIT
uint16_t USART_RxDouble(USART_TypeDef *usart)
Receive two 4-8 bit frames, or one 10-16 bit frame.
Definition: em_usart.c:976
uint32_t USART_BaudrateGet(USART_TypeDef *usart)
Get current baudrate for USART/UART.
Definition: em_usart.c:423
#define USART_CTRL_OVS_X16
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
Definition: em_cmu.c:1482
#define USART_CMD_MASTERDIS
#define _USART_IRCTRL_RESETVALUE
#define USART_CTRL_RXINV
#define _USART_IRCTRL_IRFILT_SHIFT
__IO uint32_t FRAME
Definition: efm32lg_usart.h:44
#define USART_IRCTRL_IREN
void USART_TxDouble(USART_TypeDef *usart, uint16_t data)
Transmit two 4-9 bit frames, or one 10-16 bit frame.
Definition: em_usart.c:1140
#define _USART_TRIGCTRL_TXTEN_MASK
USART_PrsRxCh_TypeDef prsRxCh
Definition: em_usart.h:285
#define _USART_CLKDIV_MASK
#define _USART_I2SCTRL_RESETVALUE
void USART_BaudrateAsyncSet(USART_TypeDef *usart, uint32_t refFreq, uint32_t baudrate, USART_OVS_TypeDef ovs)
Configure USART/UART operating in asynchronous mode to use a given baudrate (or as close as possible ...
Definition: em_usart.c:162
#define _USART_TRIGCTRL_RXTEN_MASK