35 #if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
205 #if defined( LDMA_IRQ_HANDLER_TEMPLATE )
210 void LDMA_IRQHandler(
void )
212 uint32_t pending, chnum, chmask;
216 pending &= LDMA->IEN;
219 if ( pending & LDMA_IF_ERROR )
227 for ( chnum = 0, chmask = 1;
229 chnum++, chmask <<= 1 )
231 if ( pending & chmask )
248 void LDMA_DeInit(
void )
250 NVIC_DisableIRQ( LDMA_IRQn );
263 void LDMA_Init( LDMA_Init_t *init )
265 EFM_ASSERT( init != NULL );
266 EFM_ASSERT( !( ( init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT )
267 & ~_LDMA_CTRL_NUMFIXED_MASK ) );
268 EFM_ASSERT( !( ( init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
269 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
270 EFM_ASSERT( !( ( init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
271 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
276 LDMA->CTRL = ( init->ldmaInitCtrlNumFixed << _LDMA_CTRL_NUMFIXED_SHIFT )
277 | ( init->ldmaInitCtrlSyncPrsClrEn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
278 | ( init->ldmaInitCtrlSyncPrsSetEn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT );
285 LDMA->IEN = LDMA_IEN_ERROR;
286 LDMA->IFC = 0xFFFFFFFF;
288 NVIC_ClearPendingIRQ( LDMA_IRQn );
291 NVIC_SetPriority( LDMA_IRQn, init->ldmaInitIrqPriority );
293 NVIC_EnableIRQ( LDMA_IRQn );
309 void LDMA_StartTransfer(
int ch,
310 LDMA_TransferCfg_t *transfer,
311 LDMA_Descriptor_t *descriptor )
314 uint32_t chMask = 1 << ch;
316 EFM_ASSERT( ch < DMA_CHAN_COUNT );
317 EFM_ASSERT( transfer != NULL );
318 EFM_ASSERT( !( transfer->ldmaReqSel & ~_LDMA_CH_REQSEL_MASK ) );
320 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
321 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
322 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT )
323 & ~_LDMA_CTRL_SYNCPRSCLREN_MASK ) );
324 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
325 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
326 EFM_ASSERT( !( ( transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT )
327 & ~_LDMA_CTRL_SYNCPRSSETEN_MASK ) );
329 EFM_ASSERT( !( ( transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT )
330 & ~_LDMA_CH_CFG_ARBSLOTS_MASK ) );
331 EFM_ASSERT( !( ( transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT )
332 & ~_LDMA_CH_CFG_SRCINCSIGN_MASK ) );
333 EFM_ASSERT( !( ( transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT )
334 & ~_LDMA_CH_CFG_DSTINCSIGN_MASK ) );
335 EFM_ASSERT( !( ( transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT )
336 & ~_LDMA_CH_LOOP_LOOPCNT_MASK ) );
338 LDMA->CH[ ch ].REQSEL = transfer->ldmaReqSel;
340 LDMA->CH[ ch ].LOOP =
341 ( transfer->ldmaLoopCnt << _LDMA_CH_LOOP_LOOPCNT_SHIFT );
344 ( transfer->ldmaCfgArbSlots << _LDMA_CH_CFG_ARBSLOTS_SHIFT )
345 | ( transfer->ldmaCfgSrcIncSign << _LDMA_CH_CFG_SRCINCSIGN_SHIFT )
346 | ( transfer->ldmaCfgDstIncSign << _LDMA_CH_CFG_DSTINCSIGN_SHIFT );
349 LDMA->CH[ ch ].LINK = (uint32_t)descriptor & _LDMA_CH_LINK_LINKADDR_MASK;
360 if ( transfer->ldmaReqDis )
362 LDMA->REQDIS |= chMask;
365 if ( transfer->ldmaDbgHalt )
367 LDMA->DBGHALT |= chMask;
372 if ( transfer->ldmaCtrlSyncPrsClrOff )
374 tmp &= ~_LDMA_CTRL_SYNCPRSCLREN_MASK
375 | (~transfer->ldmaCtrlSyncPrsClrOff << _LDMA_CTRL_SYNCPRSCLREN_SHIFT);
378 if ( transfer->ldmaCtrlSyncPrsClrOn )
380 tmp |= transfer->ldmaCtrlSyncPrsClrOn << _LDMA_CTRL_SYNCPRSCLREN_SHIFT;
383 if ( transfer->ldmaCtrlSyncPrsSetOff )
385 tmp &= ~_LDMA_CTRL_SYNCPRSSETEN_MASK
386 | (~transfer->ldmaCtrlSyncPrsSetOff << _LDMA_CTRL_SYNCPRSSETEN_SHIFT);
389 if ( transfer->ldmaCtrlSyncPrsSetOn )
391 tmp |= transfer->ldmaCtrlSyncPrsSetOn << _LDMA_CTRL_SYNCPRSSETEN_SHIFT;
397 LDMA->LINKLOAD = chMask;
414 void LDMA_StopTransfer(
int ch )
416 uint32_t chMask = 1 << ch;
418 EFM_ASSERT( ch < DMA_CHAN_COUNT );
422 LDMA->IEN &= ~chMask;
438 bool LDMA_TransferDone(
int ch )
441 uint32_t chMask = 1 << ch;
443 EFM_ASSERT( ch < DMA_CHAN_COUNT );
446 if ( ( ( LDMA->CHEN & chMask ) == 0 )
447 && ( ( LDMA->CHDONE & chMask ) == chMask ) )
470 uint32_t LDMA_TransferRemainingCount(
int ch )
472 uint32_t remaining, done, iflag;
473 uint32_t chMask = 1 << ch;
475 EFM_ASSERT( ch < DMA_CHAN_COUNT );
480 remaining = LDMA->CH[ ch ].CTRL;
485 remaining = ( remaining
486 & _LDMA_CH_CTRL_XFERCNT_MASK )
487 >> _LDMA_CH_CTRL_XFERCNT_SHIFT;
489 if ( done || ( ( remaining == 0 ) && iflag ) )
494 return remaining + 1;
Clock management unit (CMU) API.
Emlib peripheral API "assert" implementation.
RAM and peripheral bit-field set and clear API.
__STATIC_INLINE uint32_t INT_Enable(void)
Enable interrupts.
Interrupt enable/disable unit API.
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
__STATIC_INLINE void BUS_RegMaskedSet(volatile uint32_t *addr, uint32_t mask)
Perform a masked set operation on peripheral register address.
Direct memory access (LDMA) API.
__STATIC_INLINE void BUS_RegMaskedClear(volatile uint32_t *addr, uint32_t mask)
Perform a masked clear operation on peripheral register address.
__STATIC_INLINE uint32_t INT_Disable(void)
Disable interrupts.