16 #ifndef __SILICON_LABS_DMADRV_H__
17 #define __SILICON_LABS_DMADRV_H__
22 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
23 #define EMDRV_DMADRV_UDMA
24 #define EMDRV_DMADRV_DMA_PRESENT
26 #elif defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
27 #define EMDRV_DMADRV_LDMA
28 #define EMDRV_DMADRV_DMA_PRESENT
31 #error "No valid DMA engine defined."
34 #include "dmadrv_config.h"
51 #define ECODE_EMDRV_DMADRV_OK ( ECODE_OK )
52 #define ECODE_EMDRV_DMADRV_PARAM_ERROR ( ECODE_EMDRV_DMADRV_BASE | 0x00000001 )
53 #define ECODE_EMDRV_DMADRV_NOT_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000002 )
54 #define ECODE_EMDRV_DMADRV_ALREADY_INITIALIZED ( ECODE_EMDRV_DMADRV_BASE | 0x00000003 )
55 #define ECODE_EMDRV_DMADRV_CHANNELS_EXHAUSTED ( ECODE_EMDRV_DMADRV_BASE | 0x00000004 )
56 #define ECODE_EMDRV_DMADRV_IN_USE ( ECODE_EMDRV_DMADRV_BASE | 0x00000005 )
57 #define ECODE_EMDRV_DMADRV_ALREADY_FREED ( ECODE_EMDRV_DMADRV_BASE | 0x00000006 )
58 #define ECODE_EMDRV_DMADRV_CH_NOT_ALLOCATED ( ECODE_EMDRV_DMADRV_BASE | 0x00000007 )
82 unsigned int sequenceNo,
85 #if defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
88 #define DMADRV_MAX_XFER_COUNT ((int)((_DMA_CTRL_N_MINUS_1_MASK >> _DMA_CTRL_N_MINUS_1_SHIFT) + 1))
94 #if defined( DMAREQ_ADC0_SCAN )
97 #if defined( DMAREQ_ADC0_SINGLE )
100 #if defined( DMAREQ_AES_DATARD )
103 #if defined( DMAREQ_AES_DATAWR )
106 #if defined( DMAREQ_AES_KEYWR )
109 #if defined( DMAREQ_AES_XORDATAWR )
112 #if defined( DMAREQ_DAC0_CH0 )
115 #if defined( DMAREQ_DAC0_CH1 )
118 #if defined( DMAREQ_EBI_DDEMPTY )
121 #if defined( DMAREQ_EBI_PXL0EMPTY )
124 #if defined( DMAREQ_EBI_PXL1EMPTY )
127 #if defined( DMAREQ_EBI_PXLFULL )
130 #if defined( DMAREQ_I2C0_RXDATAV )
133 #if defined( DMAREQ_I2C0_TXBL )
136 #if defined( DMAREQ_I2C1_RXDATAV )
139 #if defined( DMAREQ_I2C1_TXBL )
142 #if defined( DMAREQ_LESENSE_BUFDATAV )
145 #if defined( DMAREQ_LEUART0_RXDATAV )
148 #if defined( DMAREQ_LEUART0_TXBL )
151 #if defined( DMAREQ_LEUART0_TXEMPTY )
154 #if defined( DMAREQ_LEUART1_RXDATAV )
157 #if defined( DMAREQ_LEUART1_TXBL )
160 #if defined( DMAREQ_LEUART1_TXEMPTY )
163 #if defined( DMAREQ_MSC_WDATA )
166 #if defined( DMAREQ_TIMER0_CC0 )
169 #if defined( DMAREQ_TIMER0_CC1 )
172 #if defined( DMAREQ_TIMER0_CC2 )
175 #if defined( DMAREQ_TIMER0_UFOF )
178 #if defined( DMAREQ_TIMER1_CC0 )
181 #if defined( DMAREQ_TIMER1_CC1 )
184 #if defined( DMAREQ_TIMER1_CC2 )
187 #if defined( DMAREQ_TIMER1_UFOF )
190 #if defined( DMAREQ_TIMER2_CC0 )
193 #if defined( DMAREQ_TIMER2_CC1 )
196 #if defined( DMAREQ_TIMER2_CC2 )
199 #if defined( DMAREQ_TIMER2_UFOF )
202 #if defined( DMAREQ_TIMER3_CC0 )
205 #if defined( DMAREQ_TIMER3_CC1 )
208 #if defined( DMAREQ_TIMER3_CC2 )
211 #if defined( DMAREQ_TIMER3_UFOF )
214 #if defined( DMAREQ_UART0_RXDATAV )
217 #if defined( DMAREQ_UART0_TXBL )
220 #if defined( DMAREQ_UART0_TXEMPTY )
223 #if defined( DMAREQ_UART1_RXDATAV )
226 #if defined( DMAREQ_UART1_TXBL )
229 #if defined( DMAREQ_UART1_TXEMPTY )
232 #if defined( DMAREQ_USART0_RXDATAV )
235 #if defined( DMAREQ_USART0_TXBL )
238 #if defined( DMAREQ_USART0_TXEMPTY )
241 #if defined( DMAREQ_USARTRF0_RXDATAV )
242 dmadrvPeripheralSignal_USARTRF0_RXDATAV = DMAREQ_USARTRF0_RXDATAV,
244 #if defined( DMAREQ_USARTRF0_TXBL )
245 dmadrvPeripheralSignal_USARTRF0_TXBL = DMAREQ_USARTRF0_TXBL,
247 #if defined( DMAREQ_USARTRF0_TXEMPTY )
248 dmadrvPeripheralSignal_USARTRF0_TXEMPTY = DMAREQ_USARTRF0_TXEMPTY,
250 #if defined( DMAREQ_USARTRF1_RXDATAV )
251 dmadrvPeripheralSignal_USARTRF1_RXDATAV = DMAREQ_USARTRF1_RXDATAV,
253 #if defined( DMAREQ_USARTRF1_TXBL )
254 dmadrvPeripheralSignal_USARTRF1_TXBL = DMAREQ_USARTRF1_TXBL,
256 #if defined( DMAREQ_USARTRF1_TXEMPTY )
257 dmadrvPeripheralSignal_USARTRF1_TXEMPTY = DMAREQ_USARTRF1_TXEMPTY,
259 #if defined( DMAREQ_USART1_RXDATAV )
262 #if defined( DMAREQ_USART1_RXDATAVRIGHT )
265 #if defined( DMAREQ_USART1_TXBL )
268 #if defined( DMAREQ_USART1_TXBLRIGHT )
271 #if defined( DMAREQ_USART1_TXEMPTY )
274 #if defined( DMAREQ_USART2_RXDATAV )
277 #if defined( DMAREQ_USART2_RXDATAVRIGHT )
280 #if defined( DMAREQ_USART2_TXBL )
283 #if defined( DMAREQ_USART2_TXBLRIGHT )
286 #if defined( DMAREQ_USART2_TXEMPTY )
292 } DMADRV_PeripheralSignal_t;
307 #endif // defined( DMA_PRESENT ) && ( DMA_COUNT == 1 )
309 #if defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 )
312 #define DMADRV_MAX_XFER_COUNT ((int)((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
318 #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SCAN )
321 #if defined( LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE )
324 #if defined( LDMA_CH_REQSEL_SIGSEL_AGCRSSI )
325 dmadrvPeripheralSignal_AGC_RSSI = LDMA_CH_REQSEL_SIGSEL_AGCRSSI | LDMA_CH_REQSEL_SOURCESEL_AGC,
327 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD )
328 dmadrvPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
330 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR )
331 dmadrvPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
333 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR )
334 dmadrvPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
336 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD )
337 dmadrvPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
339 #if defined( LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR )
340 dmadrvPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO,
342 #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV )
345 #if defined( LDMA_CH_REQSEL_SIGSEL_I2C0TXBL )
348 #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV )
351 #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL )
354 #if defined( LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY )
357 #if defined( LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG )
358 dmadrvPeripheralSignal_MODEM_DEBUG = LDMA_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMA_CH_REQSEL_SOURCESEL_MODEM,
360 #if defined( LDMA_CH_REQSEL_SIGSEL_MSCWDATA )
363 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF )
364 dmadrvPeripheralSignal_PROTIMER_BOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
366 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 )
367 dmadrvPeripheralSignal_PROTIMER_CC0 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
369 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 )
370 dmadrvPeripheralSignal_PROTIMER_CC1 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
372 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 )
373 dmadrvPeripheralSignal_PROTIMER_CC2 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
375 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 )
376 dmadrvPeripheralSignal_PROTIMER_CC3 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
378 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 )
379 dmadrvPeripheralSignal_PROTIMER_CC4 = LDMA_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
381 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF )
382 dmadrvPeripheralSignal_PROTIMER_POF = LDMA_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
384 #if defined( LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF )
385 dmadrvPeripheralSignal_PROTIMER_WOF = LDMA_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMA_CH_REQSEL_SOURCESEL_PROTIMER,
387 #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ0 )
388 dmadrvPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS,
390 #if defined( LDMA_CH_REQSEL_SIGSEL_PRSREQ1 )
391 dmadrvPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS,
393 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 )
396 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 )
399 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 )
402 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF )
405 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 )
408 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 )
411 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 )
414 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 )
415 dmadrvPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
417 #if defined( LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF )
420 #if defined( LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV )
423 #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXBL )
426 #if defined( LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY )
429 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV )
432 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT )
435 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBL )
438 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT )
441 #if defined( LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY )
444 } DMADRV_PeripheralSignal_t;
461 #if !defined( EMDRV_DMADRV_USE_NATIVE_API ) || defined( DOXY_DOC_ONLY )
463 DMADRV_PeripheralSignal_t
469 DMADRV_DataSize_t size,
473 DMADRV_PeripheralSignal_t
479 DMADRV_DataSize_t size,
483 unsigned int channelId,
484 DMADRV_PeripheralSignal_t
491 DMADRV_DataSize_t size,
495 unsigned int channelId,
496 DMADRV_PeripheralSignal_t
503 DMADRV_DataSize_t size,
508 #if defined( EMDRV_DMADRV_LDMA ) && defined( EMDRV_DMADRV_USE_NATIVE_API )
510 Ecode_t DMADRV_LdmaStartTransfer(
512 LDMA_TransferCfg_t *transfer,
513 LDMA_Descriptor_t *descriptor,
#define DMAREQ_LESENSE_BUFDATAV
#define DMAREQ_UART0_RXDATAV
#define DMAREQ_LEUART1_TXBL
Trig on USART2_TXBLRIGHT.
#define DMAREQ_USART1_RXDATAV
#define DMAREQ_I2C1_RXDATAV
Ecode_t DMADRV_PeripheralMemory(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory DMA transfer.
#define DMAREQ_EBI_PXLFULL
Ecode_t DMADRV_TransferActive(unsigned int channelId, bool *active)
Check if a transfer is running.
Energy Aware drivers error code definitions.
bool(* DMADRV_Callback_t)(unsigned int channel, unsigned int sequenceNo, void *userParam)
DMADRV transfer completion callback function.
#define DMAREQ_UART1_RXDATAV
#define DMAREQ_TIMER0_CC0
No peripheral selected for DMA triggering.
#define DMAREQ_UART1_TXBL
Ecode_t DMADRV_StopTransfer(unsigned int channelId)
Stop an ongoing DMA transfer.
#define DMAREQ_USART0_TXBL
#define DMAREQ_LEUART1_TXEMPTY
#define DMAREQ_EBI_PXL1EMPTY
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
#define DMAREQ_UART0_TXEMPTY
Ecode_t DMADRV_TransferDone(unsigned int channelId, bool *done)
Check if a transfer has completed.
#define DMAREQ_LEUART1_RXDATAV
#define DMAREQ_USART2_TXBL
#define DMAREQ_LEUART0_TXEMPTY
#define DMAREQ_TIMER3_CC0
#define DMAREQ_TIMER2_CC1
Trig on LESENSE_BUFDATAV.
#define DMAREQ_TIMER3_CC1
Ecode_t DMADRV_TransferRemainingCount(unsigned int channelId, int *remaining)
Get number of items remaining in a transfer.
#define DMAREQ_I2C0_RXDATAV
#define DMAREQ_TIMER2_CC0
#define DMAREQ_USART1_TXBLRIGHT
#define DMAREQ_USART2_RXDATAV
#define DMAREQ_AES_DATAWR
DMADRV_Datasize_t
Data size of one UDMA transfer item.
#define DMAREQ_TIMER0_CC2
Ecode_t DMADRV_MemoryPeripheralPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src0, void *src1, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral ping-pong DMA transfer.
#define DMAREQ_TIMER2_UFOF
#define DMAREQ_TIMER0_CC1
#define DMAREQ_LEUART0_RXDATAV
#define DMAREQ_USART0_RXDATAV
#define DMAREQ_TIMER1_UFOF
Ecode_t DMADRV_Init(void)
Initialize DMADRV.
#define DMAREQ_EBI_DDEMPTY
#define DMAREQ_UART1_TXEMPTY
#define DMAREQ_USART0_TXEMPTY
#define DMAREQ_USART2_RXDATAVRIGHT
#define DMAREQ_LEUART0_TXBL
Direct memory access (LDMA) API.
Trig on USART2_RXDATAVRIGHT.
#define DMAREQ_ADC0_SINGLE
#define DMAREQ_AES_DATARD
Trig on USART1_RXDATAVRIGHT.
Ecode_t DMADRV_DeInit(void)
Deinitialize DMADRV.
#define DMAREQ_TIMER3_CC2
#define DMAREQ_USART2_TXBLRIGHT
#define DMAREQ_TIMER2_CC2
#define DMAREQ_USART1_RXDATAVRIGHT
#define DMAREQ_AES_XORDATAWR
Ecode_t DMADRV_AllocateChannel(unsigned int *channelId, void *capabilities)
Allocate (reserve) a DMA channel.
#define DMAREQ_EBI_PXL0EMPTY
#define DMAREQ_TIMER1_CC0
Ecode_t DMADRV_MemoryPeripheral(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst, void *src, bool srcInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a memory to peripheral DMA transfer.
uint32_t Ecode_t
Typedef for API function errorcode return values.
#define DMAREQ_UART0_TXBL
Ecode_t DMADRV_TransferCompletePending(unsigned int channelId, bool *pending)
Check if a transfer complete is pending.
DMADRV_Peripheralsignal_t
Peripherals that can trigger UDMA transfers.
#define DMAREQ_TIMER1_CC2
Ecode_t DMADRV_PeripheralMemoryPingPong(unsigned int channelId, DMADRV_PeripheralSignal_t peripheralSignal, void *dst0, void *dst1, void *src, bool dstInc, int len, DMADRV_DataSize_t size, DMADRV_Callback_t callback, void *cbUserParam)
Start a peripheral to memory ping-pong DMA transfer.
#define DMAREQ_USART1_TXEMPTY
Direct memory access (DMA) API.
#define DMAREQ_TIMER3_UFOF
#define DMAREQ_TIMER1_CC1
#define DMAREQ_USART2_TXEMPTY
#define DMAREQ_TIMER0_UFOF
Trig on USART1_TXBLRIGHT.
Ecode_t DMADRV_FreeChannel(unsigned int channelId)
Free an allocate (reserved) DMA channel.
#define DMAREQ_USART1_TXBL