00001
00032
00037 typedef struct
00038 {
00039 __IO uint32_t CTRL;
00040 __IO uint32_t HFCORECLKDIV;
00041 __IO uint32_t HFPERCLKDIV;
00042 __IO uint32_t HFRCOCTRL;
00043 __IO uint32_t LFRCOCTRL;
00044 __IO uint32_t AUXHFRCOCTRL;
00045 __IO uint32_t CALCTRL;
00046 __IO uint32_t CALCNT;
00047 __IO uint32_t OSCENCMD;
00048 __IO uint32_t CMD;
00049 __IO uint32_t LFCLKSEL;
00050 __I uint32_t STATUS;
00051 __I uint32_t IF;
00052 __IO uint32_t IFS;
00053 __IO uint32_t IFC;
00054 __IO uint32_t IEN;
00055 __IO uint32_t HFCORECLKEN0;
00056 __IO uint32_t HFPERCLKEN0;
00057 uint32_t RESERVED0[2];
00058 __I uint32_t SYNCBUSY;
00059 __IO uint32_t FREEZE;
00060 __IO uint32_t LFACLKEN0;
00061 uint32_t RESERVED1[1];
00062 __IO uint32_t LFBCLKEN0;
00063 uint32_t RESERVED2[1];
00064 __IO uint32_t LFAPRESC0;
00065 uint32_t RESERVED3[1];
00066 __IO uint32_t LFBPRESC0;
00067 uint32_t RESERVED4[1];
00068 __IO uint32_t PCNTCTRL;
00069 __IO uint32_t LCDCTRL;
00070 __IO uint32_t ROUTE;
00071 __IO uint32_t LOCK;
00072 } CMU_TypeDef;
00074
00079
00080 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
00081 #define _CMU_CTRL_MASK 0x17FE3EEFUL
00082 #define _CMU_CTRL_HFXOMODE_SHIFT 0
00083 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
00084 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
00085 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
00086 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
00087 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
00088 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
00089 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
00090 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
00091 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
00092 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
00093 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
00094 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
00095 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
00096 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
00097 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
00098 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
00099 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
00100 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
00101 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
00102 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
00103 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
00104 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
00105 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
00106 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
00107 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
00108 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
00109 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
00110 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
00111 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
00112 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
00113 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
00114 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
00115 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
00116 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
00117 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
00118 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
00119 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
00120 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
00121 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
00122 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
00123 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
00124 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
00125 #define _CMU_CTRL_LFXOMODE_SHIFT 11
00126 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
00127 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
00128 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
00129 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
00130 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
00131 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
00132 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
00133 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
00134 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
00135 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
00136 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
00137 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
00138 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
00139 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
00140 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
00141 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
00142 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
00143 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
00144 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
00145 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
00146 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
00147 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
00148 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
00149 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
00150 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
00151 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
00152 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
00153 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
00154 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
00155 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
00156 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
00157 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
00158 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
00159 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
00160 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
00161 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
00162 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
00163 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
00164 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
00165 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
00166 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
00167 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
00168 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
00169 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
00170 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
00171 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL
00172 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
00173 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
00174 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
00175 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
00176 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
00177 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
00178 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
00179 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
00180 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
00181 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
00182 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL
00183 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
00184 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
00185 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
00186 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL
00187 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL
00188 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL
00189 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL
00190 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL
00191 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL
00192 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
00193 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
00194 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
00195 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
00196 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
00197 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
00198 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
00199 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
00200 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
00201 #define CMU_CTRL_DBGCLK (0x1UL << 28)
00202 #define _CMU_CTRL_DBGCLK_SHIFT 28
00203 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL
00204 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL
00205 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL
00206 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL
00207 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28)
00208 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)
00209 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28)
00211
00212 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
00213 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
00214 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
00215 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
00216 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
00217 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
00218 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
00219 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
00220 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
00221 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
00222 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
00223 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
00224 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
00225 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
00226 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
00227 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
00228 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
00229 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
00230 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
00231 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
00232 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
00233 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
00234 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
00235 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
00236 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
00237 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
00239
00240 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
00241 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
00242 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
00243 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
00244 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
00245 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
00246 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
00247 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
00248 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
00249 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
00250 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
00251 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
00252 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
00253 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
00254 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
00255 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
00256 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
00257 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
00258 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
00259 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
00260 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
00261 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
00262 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
00263 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
00264 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
00265 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
00266 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
00267 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
00268 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
00269 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
00270 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
00272
00273 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
00274 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
00275 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
00276 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
00277 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00278 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
00279 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
00280 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
00281 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
00282 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
00283 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
00284 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
00285 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
00286 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
00287 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
00288 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
00289 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
00290 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
00291 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
00292 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
00293 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
00294 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
00295 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
00296 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
00297 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
00298 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
00300
00301 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
00302 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
00303 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
00304 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
00305 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
00306 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
00308
00309 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
00310 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL
00311 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
00312 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
00313 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00314 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
00315 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8
00316 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL
00317 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL
00318 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL
00319 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL
00320 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL
00321 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL
00322 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL
00323 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL
00324 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
00325 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
00326 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
00327 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
00328 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
00329 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)
00330 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
00332
00333 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
00334 #define _CMU_CALCTRL_MASK 0x0000007FUL
00335 #define _CMU_CALCTRL_UPSEL_SHIFT 0
00336 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
00337 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
00338 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
00339 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
00340 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
00341 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
00342 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
00343 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
00344 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
00345 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
00346 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
00347 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
00348 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
00349 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3
00350 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL
00351 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
00352 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
00353 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
00354 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
00355 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
00356 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
00357 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
00358 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
00359 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
00360 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
00361 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
00362 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
00363 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
00364 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
00365 #define CMU_CALCTRL_CONT (0x1UL << 6)
00366 #define _CMU_CALCTRL_CONT_SHIFT 6
00367 #define _CMU_CALCTRL_CONT_MASK 0x40UL
00368 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
00369 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)
00371
00372 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
00373 #define _CMU_CALCNT_MASK 0x000FFFFFUL
00374 #define _CMU_CALCNT_CALCNT_SHIFT 0
00375 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
00376 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
00377 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
00379
00380 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
00381 #define _CMU_OSCENCMD_MASK 0x000003FFUL
00382 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
00383 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
00384 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
00385 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
00386 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
00387 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
00388 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
00389 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
00390 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
00391 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
00392 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
00393 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
00394 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
00395 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
00396 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
00397 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
00398 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
00399 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
00400 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
00401 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
00402 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
00403 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
00404 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
00405 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
00406 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
00407 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
00408 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
00409 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
00410 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
00411 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
00412 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
00413 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
00414 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
00415 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
00416 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
00417 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
00418 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
00419 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
00420 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
00421 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
00422 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
00423 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
00424 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
00425 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
00426 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
00427 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
00428 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
00429 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
00430 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
00431 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
00433
00434 #define _CMU_CMD_RESETVALUE 0x00000000UL
00435 #define _CMU_CMD_MASK 0x0000001FUL
00436 #define _CMU_CMD_HFCLKSEL_SHIFT 0
00437 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
00438 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
00439 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
00440 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
00441 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
00442 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
00443 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
00444 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
00445 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
00446 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
00447 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
00448 #define CMU_CMD_CALSTART (0x1UL << 3)
00449 #define _CMU_CMD_CALSTART_SHIFT 3
00450 #define _CMU_CMD_CALSTART_MASK 0x8UL
00451 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
00452 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
00453 #define CMU_CMD_CALSTOP (0x1UL << 4)
00454 #define _CMU_CMD_CALSTOP_SHIFT 4
00455 #define _CMU_CMD_CALSTOP_MASK 0x10UL
00456 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
00457 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)
00459
00460 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
00461 #define _CMU_LFCLKSEL_MASK 0x0011000FUL
00462 #define _CMU_LFCLKSEL_LFA_SHIFT 0
00463 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
00464 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
00465 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
00466 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
00467 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
00468 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
00469 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
00470 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
00471 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
00472 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
00473 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
00474 #define _CMU_LFCLKSEL_LFB_SHIFT 2
00475 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
00476 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
00477 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
00478 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
00479 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
00480 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
00481 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
00482 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
00483 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
00484 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
00485 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
00486 #define CMU_LFCLKSEL_LFAE (0x1UL << 16)
00487 #define _CMU_LFCLKSEL_LFAE_SHIFT 16
00488 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL
00489 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL
00490 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL
00491 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL
00492 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
00493 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
00494 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
00495 #define CMU_LFCLKSEL_LFBE (0x1UL << 20)
00496 #define _CMU_LFCLKSEL_LFBE_SHIFT 20
00497 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL
00498 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL
00499 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL
00500 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL
00501 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
00502 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
00503 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
00505
00506 #define _CMU_STATUS_RESETVALUE 0x00000403UL
00507 #define _CMU_STATUS_MASK 0x00007FFFUL
00508 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
00509 #define _CMU_STATUS_HFRCOENS_SHIFT 0
00510 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
00511 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
00512 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
00513 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
00514 #define _CMU_STATUS_HFRCORDY_SHIFT 1
00515 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
00516 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
00517 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
00518 #define CMU_STATUS_HFXOENS (0x1UL << 2)
00519 #define _CMU_STATUS_HFXOENS_SHIFT 2
00520 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
00521 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
00522 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
00523 #define CMU_STATUS_HFXORDY (0x1UL << 3)
00524 #define _CMU_STATUS_HFXORDY_SHIFT 3
00525 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
00526 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
00527 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
00528 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
00529 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
00530 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
00531 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
00532 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
00533 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
00534 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
00535 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
00536 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
00537 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
00538 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
00539 #define _CMU_STATUS_LFRCOENS_SHIFT 6
00540 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
00541 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
00542 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
00543 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
00544 #define _CMU_STATUS_LFRCORDY_SHIFT 7
00545 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
00546 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
00547 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
00548 #define CMU_STATUS_LFXOENS (0x1UL << 8)
00549 #define _CMU_STATUS_LFXOENS_SHIFT 8
00550 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
00551 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
00552 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
00553 #define CMU_STATUS_LFXORDY (0x1UL << 9)
00554 #define _CMU_STATUS_LFXORDY_SHIFT 9
00555 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
00556 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
00557 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
00558 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
00559 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
00560 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
00561 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
00562 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
00563 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
00564 #define _CMU_STATUS_HFXOSEL_SHIFT 11
00565 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
00566 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
00567 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
00568 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
00569 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
00570 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
00571 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
00572 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
00573 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
00574 #define _CMU_STATUS_LFXOSEL_SHIFT 13
00575 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
00576 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
00577 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
00578 #define CMU_STATUS_CALBSY (0x1UL << 14)
00579 #define _CMU_STATUS_CALBSY_SHIFT 14
00580 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
00581 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
00582 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
00584
00585 #define _CMU_IF_RESETVALUE 0x00000001UL
00586 #define _CMU_IF_MASK 0x0000007FUL
00587 #define CMU_IF_HFRCORDY (0x1UL << 0)
00588 #define _CMU_IF_HFRCORDY_SHIFT 0
00589 #define _CMU_IF_HFRCORDY_MASK 0x1UL
00590 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
00591 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
00592 #define CMU_IF_HFXORDY (0x1UL << 1)
00593 #define _CMU_IF_HFXORDY_SHIFT 1
00594 #define _CMU_IF_HFXORDY_MASK 0x2UL
00595 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
00596 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
00597 #define CMU_IF_LFRCORDY (0x1UL << 2)
00598 #define _CMU_IF_LFRCORDY_SHIFT 2
00599 #define _CMU_IF_LFRCORDY_MASK 0x4UL
00600 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
00601 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
00602 #define CMU_IF_LFXORDY (0x1UL << 3)
00603 #define _CMU_IF_LFXORDY_SHIFT 3
00604 #define _CMU_IF_LFXORDY_MASK 0x8UL
00605 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
00606 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
00607 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
00608 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
00609 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
00610 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
00611 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
00612 #define CMU_IF_CALRDY (0x1UL << 5)
00613 #define _CMU_IF_CALRDY_SHIFT 5
00614 #define _CMU_IF_CALRDY_MASK 0x20UL
00615 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
00616 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
00617 #define CMU_IF_CALOF (0x1UL << 6)
00618 #define _CMU_IF_CALOF_SHIFT 6
00619 #define _CMU_IF_CALOF_MASK 0x40UL
00620 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
00621 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
00623
00624 #define _CMU_IFS_RESETVALUE 0x00000000UL
00625 #define _CMU_IFS_MASK 0x0000007FUL
00626 #define CMU_IFS_HFRCORDY (0x1UL << 0)
00627 #define _CMU_IFS_HFRCORDY_SHIFT 0
00628 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
00629 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
00630 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
00631 #define CMU_IFS_HFXORDY (0x1UL << 1)
00632 #define _CMU_IFS_HFXORDY_SHIFT 1
00633 #define _CMU_IFS_HFXORDY_MASK 0x2UL
00634 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
00635 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
00636 #define CMU_IFS_LFRCORDY (0x1UL << 2)
00637 #define _CMU_IFS_LFRCORDY_SHIFT 2
00638 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
00639 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
00640 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
00641 #define CMU_IFS_LFXORDY (0x1UL << 3)
00642 #define _CMU_IFS_LFXORDY_SHIFT 3
00643 #define _CMU_IFS_LFXORDY_MASK 0x8UL
00644 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
00645 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
00646 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
00647 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
00648 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
00649 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
00650 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
00651 #define CMU_IFS_CALRDY (0x1UL << 5)
00652 #define _CMU_IFS_CALRDY_SHIFT 5
00653 #define _CMU_IFS_CALRDY_MASK 0x20UL
00654 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
00655 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
00656 #define CMU_IFS_CALOF (0x1UL << 6)
00657 #define _CMU_IFS_CALOF_SHIFT 6
00658 #define _CMU_IFS_CALOF_MASK 0x40UL
00659 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
00660 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
00662
00663 #define _CMU_IFC_RESETVALUE 0x00000000UL
00664 #define _CMU_IFC_MASK 0x0000007FUL
00665 #define CMU_IFC_HFRCORDY (0x1UL << 0)
00666 #define _CMU_IFC_HFRCORDY_SHIFT 0
00667 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
00668 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
00669 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
00670 #define CMU_IFC_HFXORDY (0x1UL << 1)
00671 #define _CMU_IFC_HFXORDY_SHIFT 1
00672 #define _CMU_IFC_HFXORDY_MASK 0x2UL
00673 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
00674 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
00675 #define CMU_IFC_LFRCORDY (0x1UL << 2)
00676 #define _CMU_IFC_LFRCORDY_SHIFT 2
00677 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
00678 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
00679 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
00680 #define CMU_IFC_LFXORDY (0x1UL << 3)
00681 #define _CMU_IFC_LFXORDY_SHIFT 3
00682 #define _CMU_IFC_LFXORDY_MASK 0x8UL
00683 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
00684 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
00685 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
00686 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
00687 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
00688 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
00689 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
00690 #define CMU_IFC_CALRDY (0x1UL << 5)
00691 #define _CMU_IFC_CALRDY_SHIFT 5
00692 #define _CMU_IFC_CALRDY_MASK 0x20UL
00693 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
00694 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
00695 #define CMU_IFC_CALOF (0x1UL << 6)
00696 #define _CMU_IFC_CALOF_SHIFT 6
00697 #define _CMU_IFC_CALOF_MASK 0x40UL
00698 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
00699 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
00701
00702 #define _CMU_IEN_RESETVALUE 0x00000000UL
00703 #define _CMU_IEN_MASK 0x0000007FUL
00704 #define CMU_IEN_HFRCORDY (0x1UL << 0)
00705 #define _CMU_IEN_HFRCORDY_SHIFT 0
00706 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
00707 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
00708 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
00709 #define CMU_IEN_HFXORDY (0x1UL << 1)
00710 #define _CMU_IEN_HFXORDY_SHIFT 1
00711 #define _CMU_IEN_HFXORDY_MASK 0x2UL
00712 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
00713 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
00714 #define CMU_IEN_LFRCORDY (0x1UL << 2)
00715 #define _CMU_IEN_LFRCORDY_SHIFT 2
00716 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
00717 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
00718 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
00719 #define CMU_IEN_LFXORDY (0x1UL << 3)
00720 #define _CMU_IEN_LFXORDY_SHIFT 3
00721 #define _CMU_IEN_LFXORDY_MASK 0x8UL
00722 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
00723 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
00724 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
00725 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
00726 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
00727 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
00728 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
00729 #define CMU_IEN_CALRDY (0x1UL << 5)
00730 #define _CMU_IEN_CALRDY_SHIFT 5
00731 #define _CMU_IEN_CALRDY_MASK 0x20UL
00732 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
00733 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
00734 #define CMU_IEN_CALOF (0x1UL << 6)
00735 #define _CMU_IEN_CALOF_SHIFT 6
00736 #define _CMU_IEN_CALOF_MASK 0x40UL
00737 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
00738 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
00740
00741 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
00742 #define _CMU_HFCORECLKEN0_MASK 0x00000007UL
00743 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
00744 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
00745 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
00746 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
00747 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
00748 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
00749 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
00750 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
00751 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
00752 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
00753 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
00754 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
00755 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
00756 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
00757 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
00759
00760 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
00761 #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL
00762 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 0)
00763 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 0
00764 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x1UL
00765 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
00766 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 0)
00767 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 1)
00768 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 1
00769 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x2UL
00770 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
00771 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 1)
00772 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 2)
00773 #define _CMU_HFPERCLKEN0_USART0_SHIFT 2
00774 #define _CMU_HFPERCLKEN0_USART0_MASK 0x4UL
00775 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
00776 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2)
00777 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 3)
00778 #define _CMU_HFPERCLKEN0_USART1_SHIFT 3
00779 #define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL
00780 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
00781 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)
00782 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
00783 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
00784 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
00785 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
00786 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
00787 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
00788 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
00789 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
00790 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
00791 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
00792 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 6)
00793 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 6
00794 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x40UL
00795 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
00796 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 6)
00797 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 7)
00798 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 7
00799 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x80UL
00800 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
00801 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 7)
00802 #define CMU_HFPERCLKEN0_PRS (0x1UL << 8)
00803 #define _CMU_HFPERCLKEN0_PRS_SHIFT 8
00804 #define _CMU_HFPERCLKEN0_PRS_MASK 0x100UL
00805 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
00806 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 8)
00807 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 9)
00808 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 9
00809 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x200UL
00810 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
00811 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 9)
00812 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 10)
00813 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 10
00814 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x400UL
00815 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
00816 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 10)
00817 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)
00818 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11
00819 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL
00820 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
00821 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
00823
00824 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
00825 #define _CMU_SYNCBUSY_MASK 0x00000055UL
00826 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
00827 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
00828 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
00829 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
00830 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
00831 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
00832 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
00833 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
00834 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
00835 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
00836 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
00837 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
00838 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
00839 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
00840 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
00841 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
00842 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
00843 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
00844 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
00845 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
00847
00848 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
00849 #define _CMU_FREEZE_MASK 0x00000001UL
00850 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
00851 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
00852 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
00853 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
00854 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
00855 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
00856 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
00857 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
00858 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
00860
00861 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
00862 #define _CMU_LFACLKEN0_MASK 0x0000000FUL
00863 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0)
00864 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0
00865 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL
00866 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL
00867 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)
00868 #define CMU_LFACLKEN0_RTC (0x1UL << 1)
00869 #define _CMU_LFACLKEN0_RTC_SHIFT 1
00870 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL
00871 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
00872 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1)
00873 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2)
00874 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2
00875 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL
00876 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
00877 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)
00878 #define CMU_LFACLKEN0_LCD (0x1UL << 3)
00879 #define _CMU_LFACLKEN0_LCD_SHIFT 3
00880 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL
00881 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL
00882 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3)
00884
00885 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
00886 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
00887 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
00888 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
00889 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
00890 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
00891 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
00893
00894 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
00895 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL
00896 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0
00897 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL
00898 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL
00899 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL
00900 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL
00901 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL
00902 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)
00903 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)
00904 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)
00905 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)
00906 #define _CMU_LFAPRESC0_RTC_SHIFT 4
00907 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL
00908 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
00909 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
00910 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
00911 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
00912 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
00913 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
00914 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
00915 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
00916 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
00917 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
00918 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
00919 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
00920 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
00921 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
00922 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
00923 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
00924 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4)
00925 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4)
00926 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4)
00927 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4)
00928 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4)
00929 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4)
00930 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4)
00931 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4)
00932 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4)
00933 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4)
00934 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4)
00935 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4)
00936 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4)
00937 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4)
00938 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4)
00939 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4)
00940 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8
00941 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL
00942 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
00943 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
00944 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
00945 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
00946 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
00947 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
00948 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
00949 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
00950 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
00951 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
00952 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
00953 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
00954 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
00955 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
00956 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
00957 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
00958 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)
00959 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)
00960 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)
00961 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)
00962 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)
00963 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)
00964 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)
00965 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)
00966 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)
00967 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)
00968 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)
00969 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)
00970 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)
00971 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)
00972 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)
00973 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)
00974 #define _CMU_LFAPRESC0_LCD_SHIFT 12
00975 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL
00976 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL
00977 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL
00978 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL
00979 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL
00980 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12)
00981 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12)
00982 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12)
00983 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12)
00985
00986 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
00987 #define _CMU_LFBPRESC0_MASK 0x00000003UL
00988 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
00989 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
00990 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
00991 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
00992 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
00993 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
00994 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
00995 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
00996 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
00997 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
00999
01000 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
01001 #define _CMU_PCNTCTRL_MASK 0x00000003UL
01002 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
01003 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
01004 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
01005 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
01006 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
01007 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
01008 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
01009 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
01010 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
01011 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
01012 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
01013 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
01014 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
01015 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
01017
01018 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL
01019 #define _CMU_LCDCTRL_MASK 0x0000007FUL
01020 #define _CMU_LCDCTRL_FDIV_SHIFT 0
01021 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL
01022 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL
01023 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0)
01024 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3)
01025 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3
01026 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL
01027 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL
01028 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3)
01029 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4
01030 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL
01031 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL
01032 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL
01033 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL
01034 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL
01035 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL
01036 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL
01037 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL
01038 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL
01039 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL
01040 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4)
01041 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4)
01042 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4)
01043 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4)
01044 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4)
01045 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4)
01046 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4)
01047 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4)
01048 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4)
01050
01051 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
01052 #define _CMU_ROUTE_MASK 0x0000001FUL
01053 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
01054 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
01055 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
01056 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
01057 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
01058 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
01059 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
01060 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
01061 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
01062 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
01063 #define _CMU_ROUTE_LOCATION_SHIFT 2
01064 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL
01065 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
01066 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
01067 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
01068 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL
01069 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
01070 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
01071 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
01072 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)
01074
01075 #define _CMU_LOCK_RESETVALUE 0x00000000UL
01076 #define _CMU_LOCK_MASK 0x0000FFFFUL
01077 #define _CMU_LOCK_LOCKKEY_SHIFT 0
01078 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
01079 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
01080 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
01081 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
01082 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
01083 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
01084 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
01085 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
01086 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
01087 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
01088 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)