00001
00034 #ifndef __SILICON_LABS_EFM32TG225F32_H__
00035 #define __SILICON_LABS_EFM32TG225F32_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 MemoryManagement_IRQn = -12,
00058 BusFault_IRQn = -11,
00059 UsageFault_IRQn = -10,
00060 SVCall_IRQn = -5,
00061 DebugMonitor_IRQn = -4,
00062 PendSV_IRQn = -2,
00063 SysTick_IRQn = -1,
00065
00066 DMA_IRQn = 0,
00067 GPIO_EVEN_IRQn = 1,
00068 TIMER0_IRQn = 2,
00069 USART0_RX_IRQn = 3,
00070 USART0_TX_IRQn = 4,
00071 ACMP0_IRQn = 5,
00072 ADC0_IRQn = 6,
00073 DAC0_IRQn = 7,
00074 I2C0_IRQn = 8,
00075 GPIO_ODD_IRQn = 9,
00076 TIMER1_IRQn = 10,
00077 USART1_RX_IRQn = 11,
00078 USART1_TX_IRQn = 12,
00079 LESENSE_IRQn = 13,
00080 LEUART0_IRQn = 14,
00081 LETIMER0_IRQn = 15,
00082 PCNT0_IRQn = 16,
00083 RTC_IRQn = 17,
00084 CMU_IRQn = 18,
00085 VCMP_IRQn = 19,
00086 MSC_IRQn = 21,
00087 AES_IRQn = 22,
00088 } IRQn_Type;
00089
00090
00095 #define __MPU_PRESENT 0
00096 #define __NVIC_PRIO_BITS 3
00097 #define __Vendor_SysTickConfig 0
00101
00107 #define _EFM32_TINY_FAMILY 1
00108 #define _EFM_DEVICE
00109 #define _SILICON_LABS_32B_PLATFORM_1
00110 #define _SILICON_LABS_32B_PLATFORM 1
00112
00113 #if !defined(EFM32TG225F32)
00114 #define EFM32TG225F32 1
00115 #endif
00116
00118 #define PART_NUMBER "EFM32TG225F32"
00121 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00122 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00123 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00124 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00125 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00126 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00127 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00128 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00129 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00130 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00131 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00132 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00133 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00134 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
00135 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
00136 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
00137 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00138 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
00139 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
00140 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
00143 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
00144 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
00147 #define FLASH_BASE (0x00000000UL)
00148 #define FLASH_SIZE (0x00008000UL)
00149 #define FLASH_PAGE_SIZE 512
00150 #define SRAM_BASE (0x20000000UL)
00151 #define SRAM_SIZE (0x00001000UL)
00152 #define __CM3_REV 0x201
00153 #define PRS_CHAN_COUNT 8
00154 #define DMA_CHAN_COUNT 8
00157 #define AFCHAN_MAX 63
00158 #define AFCHANLOC_MAX 7
00159
00160 #define AFACHAN_MAX 47
00161
00162
00163
00164 #define ACMP_PRESENT
00165 #define ACMP_COUNT 2
00166 #define USART_PRESENT
00167 #define USART_COUNT 2
00168 #define TIMER_PRESENT
00169 #define TIMER_COUNT 2
00170 #define LEUART_PRESENT
00171 #define LEUART_COUNT 1
00172 #define LETIMER_PRESENT
00173 #define LETIMER_COUNT 1
00174 #define PCNT_PRESENT
00175 #define PCNT_COUNT 1
00176 #define ADC_PRESENT
00177 #define ADC_COUNT 1
00178 #define DAC_PRESENT
00179 #define DAC_COUNT 1
00180 #define I2C_PRESENT
00181 #define I2C_COUNT 1
00182 #define AES_PRESENT
00183 #define AES_COUNT 1
00184 #define DMA_PRESENT
00185 #define DMA_COUNT 1
00186 #define LE_PRESENT
00187 #define LE_COUNT 1
00188 #define MSC_PRESENT
00189 #define MSC_COUNT 1
00190 #define EMU_PRESENT
00191 #define EMU_COUNT 1
00192 #define RMU_PRESENT
00193 #define RMU_COUNT 1
00194 #define CMU_PRESENT
00195 #define CMU_COUNT 1
00196 #define LESENSE_PRESENT
00197 #define LESENSE_COUNT 1
00198 #define RTC_PRESENT
00199 #define RTC_COUNT 1
00200 #define GPIO_PRESENT
00201 #define GPIO_COUNT 1
00202 #define VCMP_PRESENT
00203 #define VCMP_COUNT 1
00204 #define PRS_PRESENT
00205 #define PRS_COUNT 1
00206 #define OPAMP_PRESENT
00207 #define OPAMP_COUNT 1
00208 #define HFXTAL_PRESENT
00209 #define HFXTAL_COUNT 1
00210 #define LFXTAL_PRESENT
00211 #define LFXTAL_COUNT 1
00212 #define WDOG_PRESENT
00213 #define WDOG_COUNT 1
00214 #define DBG_PRESENT
00215 #define DBG_COUNT 1
00216 #define BOOTLOADER_PRESENT
00217 #define BOOTLOADER_COUNT 1
00218 #define ANALOG_PRESENT
00219 #define ANALOG_COUNT 1
00220
00221 #include "core_cm3.h"
00222 #include "system_efm32tg.h"
00223
00226
00232 #include "efm32tg_aes.h"
00233 #include "efm32tg_dma_ch.h"
00234 #include "efm32tg_dma.h"
00235 #include "efm32tg_msc.h"
00236 #include "efm32tg_emu.h"
00237 #include "efm32tg_rmu.h"
00238
00239
00244 typedef struct
00245 {
00246 __IO uint32_t CTRL;
00247 __IO uint32_t HFCORECLKDIV;
00248 __IO uint32_t HFPERCLKDIV;
00249 __IO uint32_t HFRCOCTRL;
00250 __IO uint32_t LFRCOCTRL;
00251 __IO uint32_t AUXHFRCOCTRL;
00252 __IO uint32_t CALCTRL;
00253 __IO uint32_t CALCNT;
00254 __IO uint32_t OSCENCMD;
00255 __IO uint32_t CMD;
00256 __IO uint32_t LFCLKSEL;
00257 __I uint32_t STATUS;
00258 __I uint32_t IF;
00259 __IO uint32_t IFS;
00260 __IO uint32_t IFC;
00261 __IO uint32_t IEN;
00262 __IO uint32_t HFCORECLKEN0;
00263 __IO uint32_t HFPERCLKEN0;
00264 uint32_t RESERVED0[2];
00265 __I uint32_t SYNCBUSY;
00266 __IO uint32_t FREEZE;
00267 __IO uint32_t LFACLKEN0;
00268 uint32_t RESERVED1[1];
00269 __IO uint32_t LFBCLKEN0;
00270 uint32_t RESERVED2[1];
00271 __IO uint32_t LFAPRESC0;
00272 uint32_t RESERVED3[1];
00273 __IO uint32_t LFBPRESC0;
00274 uint32_t RESERVED4[1];
00275 __IO uint32_t PCNTCTRL;
00276 uint32_t RESERVED5[1];
00277 __IO uint32_t ROUTE;
00278 __IO uint32_t LOCK;
00279 } CMU_TypeDef;
00281 #include "efm32tg_lesense_st.h"
00282 #include "efm32tg_lesense_buf.h"
00283 #include "efm32tg_lesense_ch.h"
00284 #include "efm32tg_lesense.h"
00285 #include "efm32tg_rtc.h"
00286 #include "efm32tg_acmp.h"
00287 #include "efm32tg_usart.h"
00288 #include "efm32tg_timer_cc.h"
00289 #include "efm32tg_timer.h"
00290 #include "efm32tg_gpio_p.h"
00291 #include "efm32tg_gpio.h"
00292 #include "efm32tg_vcmp.h"
00293 #include "efm32tg_prs_ch.h"
00294 #include "efm32tg_prs.h"
00295 #include "efm32tg_leuart.h"
00296 #include "efm32tg_letimer.h"
00297 #include "efm32tg_pcnt.h"
00298 #include "efm32tg_adc.h"
00299 #include "efm32tg_dac.h"
00300 #include "efm32tg_i2c.h"
00301 #include "efm32tg_wdog.h"
00302 #include "efm32tg_dma_descriptor.h"
00303 #include "efm32tg_devinfo.h"
00304 #include "efm32tg_romtable.h"
00305 #include "efm32tg_calibrate.h"
00306
00309
00314 #define AES_BASE (0x400E0000UL)
00315 #define DMA_BASE (0x400C2000UL)
00316 #define MSC_BASE (0x400C0000UL)
00317 #define EMU_BASE (0x400C6000UL)
00318 #define RMU_BASE (0x400CA000UL)
00319 #define CMU_BASE (0x400C8000UL)
00320 #define LESENSE_BASE (0x4008C000UL)
00321 #define RTC_BASE (0x40080000UL)
00322 #define ACMP0_BASE (0x40001000UL)
00323 #define ACMP1_BASE (0x40001400UL)
00324 #define USART0_BASE (0x4000C000UL)
00325 #define USART1_BASE (0x4000C400UL)
00326 #define TIMER0_BASE (0x40010000UL)
00327 #define TIMER1_BASE (0x40010400UL)
00328 #define GPIO_BASE (0x40006000UL)
00329 #define VCMP_BASE (0x40000000UL)
00330 #define PRS_BASE (0x400CC000UL)
00331 #define LEUART0_BASE (0x40084000UL)
00332 #define LETIMER0_BASE (0x40082000UL)
00333 #define PCNT0_BASE (0x40086000UL)
00334 #define ADC0_BASE (0x40002000UL)
00335 #define DAC0_BASE (0x40004000UL)
00336 #define I2C0_BASE (0x4000A000UL)
00337 #define WDOG_BASE (0x40088000UL)
00338 #define CALIBRATE_BASE (0x0FE08000UL)
00339 #define DEVINFO_BASE (0x0FE081B0UL)
00340 #define ROMTABLE_BASE (0xE00FFFD0UL)
00341 #define LOCKBITS_BASE (0x0FE04000UL)
00342 #define USERDATA_BASE (0x0FE00000UL)
00346
00351 #define AES ((AES_TypeDef *) AES_BASE)
00352 #define DMA ((DMA_TypeDef *) DMA_BASE)
00353 #define MSC ((MSC_TypeDef *) MSC_BASE)
00354 #define EMU ((EMU_TypeDef *) EMU_BASE)
00355 #define RMU ((RMU_TypeDef *) RMU_BASE)
00356 #define CMU ((CMU_TypeDef *) CMU_BASE)
00357 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE)
00358 #define RTC ((RTC_TypeDef *) RTC_BASE)
00359 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00360 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
00361 #define USART0 ((USART_TypeDef *) USART0_BASE)
00362 #define USART1 ((USART_TypeDef *) USART1_BASE)
00363 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00364 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00365 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00366 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00367 #define PRS ((PRS_TypeDef *) PRS_BASE)
00368 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00369 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
00370 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00371 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
00372 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
00373 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00374 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00375 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00376 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00377 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00381
00386 #include "efm32tg_prs_signals.h"
00387 #include "efm32tg_dmareq.h"
00388 #include "efm32tg_dmactrl.h"
00389
00390
00395
00396 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
00397 #define _CMU_CTRL_MASK 0x17FE3EEFUL
00398 #define _CMU_CTRL_HFXOMODE_SHIFT 0
00399 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
00400 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
00401 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
00402 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
00403 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
00404 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
00405 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
00406 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
00407 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
00408 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
00409 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
00410 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
00411 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
00412 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
00413 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
00414 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
00415 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
00416 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
00417 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
00418 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
00419 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
00420 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
00421 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
00422 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
00423 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
00424 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
00425 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
00426 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
00427 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
00428 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
00429 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
00430 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
00431 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
00432 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
00433 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
00434 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
00435 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
00436 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
00437 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
00438 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
00439 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
00440 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
00441 #define _CMU_CTRL_LFXOMODE_SHIFT 11
00442 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
00443 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
00444 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
00445 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
00446 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
00447 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
00448 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
00449 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
00450 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
00451 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
00452 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
00453 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
00454 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
00455 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
00456 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
00457 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
00458 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
00459 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
00460 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
00461 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
00462 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
00463 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
00464 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
00465 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
00466 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
00467 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
00468 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
00469 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
00470 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
00471 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
00472 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
00473 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
00474 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
00475 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
00476 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
00477 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
00478 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
00479 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
00480 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
00481 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
00482 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
00483 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
00484 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
00485 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
00486 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
00487 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL
00488 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
00489 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
00490 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
00491 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
00492 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
00493 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
00494 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
00495 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
00496 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
00497 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
00498 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL
00499 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
00500 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
00501 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
00502 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL
00503 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL
00504 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL
00505 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL
00506 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL
00507 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL
00508 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
00509 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
00510 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
00511 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
00512 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
00513 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
00514 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
00515 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
00516 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
00517 #define CMU_CTRL_DBGCLK (0x1UL << 28)
00518 #define _CMU_CTRL_DBGCLK_SHIFT 28
00519 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL
00520 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL
00521 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL
00522 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL
00523 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28)
00524 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)
00525 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28)
00527
00528 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
00529 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
00530 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
00531 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
00532 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
00533 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
00534 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
00535 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
00536 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
00537 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
00538 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
00539 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
00540 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
00541 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
00542 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
00543 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
00544 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
00545 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
00546 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
00547 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
00548 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
00549 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
00550 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
00551 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
00552 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
00553 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
00555
00556 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
00557 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
00558 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
00559 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
00560 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
00561 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
00562 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
00563 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
00564 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
00565 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
00566 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
00567 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
00568 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
00569 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
00570 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
00571 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
00572 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
00573 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
00574 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
00575 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
00576 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
00577 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
00578 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
00579 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
00580 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
00581 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
00582 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
00583 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
00584 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
00585 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
00586 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
00588
00589 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
00590 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
00591 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
00592 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
00593 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00594 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
00595 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
00596 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
00597 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
00598 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
00599 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
00600 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
00601 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
00602 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
00603 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
00604 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
00605 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
00606 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
00607 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
00608 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
00609 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
00610 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
00611 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
00612 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
00613 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
00614 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
00616
00617 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
00618 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
00619 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
00620 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
00621 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
00622 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
00624
00625 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
00626 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL
00627 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
00628 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
00629 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
00630 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
00631 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8
00632 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL
00633 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL
00634 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL
00635 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL
00636 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL
00637 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL
00638 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL
00639 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL
00640 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
00641 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
00642 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
00643 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
00644 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
00645 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)
00646 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
00648
00649 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
00650 #define _CMU_CALCTRL_MASK 0x0000007FUL
00651 #define _CMU_CALCTRL_UPSEL_SHIFT 0
00652 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
00653 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
00654 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
00655 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
00656 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
00657 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
00658 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
00659 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
00660 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
00661 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
00662 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
00663 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
00664 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
00665 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3
00666 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL
00667 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
00668 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
00669 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
00670 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
00671 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
00672 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
00673 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
00674 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
00675 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
00676 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
00677 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
00678 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
00679 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
00680 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
00681 #define CMU_CALCTRL_CONT (0x1UL << 6)
00682 #define _CMU_CALCTRL_CONT_SHIFT 6
00683 #define _CMU_CALCTRL_CONT_MASK 0x40UL
00684 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
00685 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)
00687
00688 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
00689 #define _CMU_CALCNT_MASK 0x000FFFFFUL
00690 #define _CMU_CALCNT_CALCNT_SHIFT 0
00691 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
00692 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
00693 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
00695
00696 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
00697 #define _CMU_OSCENCMD_MASK 0x000003FFUL
00698 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
00699 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
00700 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
00701 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
00702 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
00703 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
00704 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
00705 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
00706 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
00707 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
00708 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
00709 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
00710 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
00711 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
00712 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
00713 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
00714 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
00715 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
00716 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
00717 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
00718 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
00719 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
00720 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
00721 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
00722 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
00723 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
00724 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
00725 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
00726 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
00727 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
00728 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
00729 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
00730 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
00731 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
00732 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
00733 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
00734 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
00735 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
00736 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
00737 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
00738 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
00739 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
00740 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
00741 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
00742 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
00743 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
00744 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
00745 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
00746 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
00747 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
00749
00750 #define _CMU_CMD_RESETVALUE 0x00000000UL
00751 #define _CMU_CMD_MASK 0x0000001FUL
00752 #define _CMU_CMD_HFCLKSEL_SHIFT 0
00753 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
00754 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
00755 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
00756 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
00757 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
00758 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
00759 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
00760 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
00761 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
00762 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
00763 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
00764 #define CMU_CMD_CALSTART (0x1UL << 3)
00765 #define _CMU_CMD_CALSTART_SHIFT 3
00766 #define _CMU_CMD_CALSTART_MASK 0x8UL
00767 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
00768 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
00769 #define CMU_CMD_CALSTOP (0x1UL << 4)
00770 #define _CMU_CMD_CALSTOP_SHIFT 4
00771 #define _CMU_CMD_CALSTOP_MASK 0x10UL
00772 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
00773 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)
00775
00776 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
00777 #define _CMU_LFCLKSEL_MASK 0x0011000FUL
00778 #define _CMU_LFCLKSEL_LFA_SHIFT 0
00779 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
00780 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
00781 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
00782 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
00783 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
00784 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
00785 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
00786 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
00787 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
00788 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
00789 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
00790 #define _CMU_LFCLKSEL_LFB_SHIFT 2
00791 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
00792 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
00793 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
00794 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
00795 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
00796 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
00797 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
00798 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
00799 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
00800 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
00801 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
00802 #define CMU_LFCLKSEL_LFAE (0x1UL << 16)
00803 #define _CMU_LFCLKSEL_LFAE_SHIFT 16
00804 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL
00805 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL
00806 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL
00807 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL
00808 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
00809 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
00810 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
00811 #define CMU_LFCLKSEL_LFBE (0x1UL << 20)
00812 #define _CMU_LFCLKSEL_LFBE_SHIFT 20
00813 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL
00814 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL
00815 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL
00816 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL
00817 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
00818 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
00819 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
00821
00822 #define _CMU_STATUS_RESETVALUE 0x00000403UL
00823 #define _CMU_STATUS_MASK 0x00007FFFUL
00824 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
00825 #define _CMU_STATUS_HFRCOENS_SHIFT 0
00826 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
00827 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
00828 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
00829 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
00830 #define _CMU_STATUS_HFRCORDY_SHIFT 1
00831 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
00832 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
00833 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
00834 #define CMU_STATUS_HFXOENS (0x1UL << 2)
00835 #define _CMU_STATUS_HFXOENS_SHIFT 2
00836 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
00837 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
00838 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
00839 #define CMU_STATUS_HFXORDY (0x1UL << 3)
00840 #define _CMU_STATUS_HFXORDY_SHIFT 3
00841 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
00842 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
00843 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
00844 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
00845 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
00846 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
00847 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
00848 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
00849 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
00850 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
00851 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
00852 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
00853 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
00854 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
00855 #define _CMU_STATUS_LFRCOENS_SHIFT 6
00856 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
00857 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
00858 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
00859 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
00860 #define _CMU_STATUS_LFRCORDY_SHIFT 7
00861 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
00862 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
00863 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
00864 #define CMU_STATUS_LFXOENS (0x1UL << 8)
00865 #define _CMU_STATUS_LFXOENS_SHIFT 8
00866 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
00867 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
00868 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
00869 #define CMU_STATUS_LFXORDY (0x1UL << 9)
00870 #define _CMU_STATUS_LFXORDY_SHIFT 9
00871 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
00872 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
00873 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
00874 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
00875 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
00876 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
00877 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
00878 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
00879 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
00880 #define _CMU_STATUS_HFXOSEL_SHIFT 11
00881 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
00882 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
00883 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
00884 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
00885 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
00886 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
00887 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
00888 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
00889 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
00890 #define _CMU_STATUS_LFXOSEL_SHIFT 13
00891 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
00892 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
00893 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
00894 #define CMU_STATUS_CALBSY (0x1UL << 14)
00895 #define _CMU_STATUS_CALBSY_SHIFT 14
00896 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
00897 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
00898 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
00900
00901 #define _CMU_IF_RESETVALUE 0x00000001UL
00902 #define _CMU_IF_MASK 0x0000007FUL
00903 #define CMU_IF_HFRCORDY (0x1UL << 0)
00904 #define _CMU_IF_HFRCORDY_SHIFT 0
00905 #define _CMU_IF_HFRCORDY_MASK 0x1UL
00906 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
00907 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
00908 #define CMU_IF_HFXORDY (0x1UL << 1)
00909 #define _CMU_IF_HFXORDY_SHIFT 1
00910 #define _CMU_IF_HFXORDY_MASK 0x2UL
00911 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
00912 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
00913 #define CMU_IF_LFRCORDY (0x1UL << 2)
00914 #define _CMU_IF_LFRCORDY_SHIFT 2
00915 #define _CMU_IF_LFRCORDY_MASK 0x4UL
00916 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
00917 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
00918 #define CMU_IF_LFXORDY (0x1UL << 3)
00919 #define _CMU_IF_LFXORDY_SHIFT 3
00920 #define _CMU_IF_LFXORDY_MASK 0x8UL
00921 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
00922 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
00923 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
00924 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
00925 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
00926 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
00927 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
00928 #define CMU_IF_CALRDY (0x1UL << 5)
00929 #define _CMU_IF_CALRDY_SHIFT 5
00930 #define _CMU_IF_CALRDY_MASK 0x20UL
00931 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
00932 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
00933 #define CMU_IF_CALOF (0x1UL << 6)
00934 #define _CMU_IF_CALOF_SHIFT 6
00935 #define _CMU_IF_CALOF_MASK 0x40UL
00936 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
00937 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
00939
00940 #define _CMU_IFS_RESETVALUE 0x00000000UL
00941 #define _CMU_IFS_MASK 0x0000007FUL
00942 #define CMU_IFS_HFRCORDY (0x1UL << 0)
00943 #define _CMU_IFS_HFRCORDY_SHIFT 0
00944 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
00945 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
00946 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
00947 #define CMU_IFS_HFXORDY (0x1UL << 1)
00948 #define _CMU_IFS_HFXORDY_SHIFT 1
00949 #define _CMU_IFS_HFXORDY_MASK 0x2UL
00950 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
00951 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
00952 #define CMU_IFS_LFRCORDY (0x1UL << 2)
00953 #define _CMU_IFS_LFRCORDY_SHIFT 2
00954 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
00955 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
00956 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
00957 #define CMU_IFS_LFXORDY (0x1UL << 3)
00958 #define _CMU_IFS_LFXORDY_SHIFT 3
00959 #define _CMU_IFS_LFXORDY_MASK 0x8UL
00960 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
00961 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
00962 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
00963 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
00964 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
00965 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
00966 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
00967 #define CMU_IFS_CALRDY (0x1UL << 5)
00968 #define _CMU_IFS_CALRDY_SHIFT 5
00969 #define _CMU_IFS_CALRDY_MASK 0x20UL
00970 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
00971 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
00972 #define CMU_IFS_CALOF (0x1UL << 6)
00973 #define _CMU_IFS_CALOF_SHIFT 6
00974 #define _CMU_IFS_CALOF_MASK 0x40UL
00975 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
00976 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
00978
00979 #define _CMU_IFC_RESETVALUE 0x00000000UL
00980 #define _CMU_IFC_MASK 0x0000007FUL
00981 #define CMU_IFC_HFRCORDY (0x1UL << 0)
00982 #define _CMU_IFC_HFRCORDY_SHIFT 0
00983 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
00984 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
00985 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
00986 #define CMU_IFC_HFXORDY (0x1UL << 1)
00987 #define _CMU_IFC_HFXORDY_SHIFT 1
00988 #define _CMU_IFC_HFXORDY_MASK 0x2UL
00989 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
00990 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
00991 #define CMU_IFC_LFRCORDY (0x1UL << 2)
00992 #define _CMU_IFC_LFRCORDY_SHIFT 2
00993 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
00994 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
00995 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
00996 #define CMU_IFC_LFXORDY (0x1UL << 3)
00997 #define _CMU_IFC_LFXORDY_SHIFT 3
00998 #define _CMU_IFC_LFXORDY_MASK 0x8UL
00999 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
01000 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
01001 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
01002 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
01003 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
01004 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
01005 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
01006 #define CMU_IFC_CALRDY (0x1UL << 5)
01007 #define _CMU_IFC_CALRDY_SHIFT 5
01008 #define _CMU_IFC_CALRDY_MASK 0x20UL
01009 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
01010 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
01011 #define CMU_IFC_CALOF (0x1UL << 6)
01012 #define _CMU_IFC_CALOF_SHIFT 6
01013 #define _CMU_IFC_CALOF_MASK 0x40UL
01014 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
01015 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
01017
01018 #define _CMU_IEN_RESETVALUE 0x00000000UL
01019 #define _CMU_IEN_MASK 0x0000007FUL
01020 #define CMU_IEN_HFRCORDY (0x1UL << 0)
01021 #define _CMU_IEN_HFRCORDY_SHIFT 0
01022 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
01023 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
01024 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
01025 #define CMU_IEN_HFXORDY (0x1UL << 1)
01026 #define _CMU_IEN_HFXORDY_SHIFT 1
01027 #define _CMU_IEN_HFXORDY_MASK 0x2UL
01028 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
01029 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
01030 #define CMU_IEN_LFRCORDY (0x1UL << 2)
01031 #define _CMU_IEN_LFRCORDY_SHIFT 2
01032 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
01033 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
01034 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
01035 #define CMU_IEN_LFXORDY (0x1UL << 3)
01036 #define _CMU_IEN_LFXORDY_SHIFT 3
01037 #define _CMU_IEN_LFXORDY_MASK 0x8UL
01038 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
01039 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
01040 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
01041 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
01042 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
01043 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
01044 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
01045 #define CMU_IEN_CALRDY (0x1UL << 5)
01046 #define _CMU_IEN_CALRDY_SHIFT 5
01047 #define _CMU_IEN_CALRDY_MASK 0x20UL
01048 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
01049 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
01050 #define CMU_IEN_CALOF (0x1UL << 6)
01051 #define _CMU_IEN_CALOF_SHIFT 6
01052 #define _CMU_IEN_CALOF_MASK 0x40UL
01053 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
01054 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
01056
01057 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
01058 #define _CMU_HFCORECLKEN0_MASK 0x00000007UL
01059 #define CMU_HFCORECLKEN0_AES (0x1UL << 0)
01060 #define _CMU_HFCORECLKEN0_AES_SHIFT 0
01061 #define _CMU_HFCORECLKEN0_AES_MASK 0x1UL
01062 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL
01063 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 0)
01064 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
01065 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
01066 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
01067 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
01068 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
01069 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
01070 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
01071 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
01072 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
01073 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
01075
01076 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
01077 #define _CMU_HFPERCLKEN0_MASK 0x00000FFFUL
01078 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 0)
01079 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 0
01080 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x1UL
01081 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
01082 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 0)
01083 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 1)
01084 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 1
01085 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x2UL
01086 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
01087 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 1)
01088 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 2)
01089 #define _CMU_HFPERCLKEN0_USART0_SHIFT 2
01090 #define _CMU_HFPERCLKEN0_USART0_MASK 0x4UL
01091 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL
01092 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 2)
01093 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 3)
01094 #define _CMU_HFPERCLKEN0_USART1_SHIFT 3
01095 #define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL
01096 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
01097 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)
01098 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
01099 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
01100 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
01101 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
01102 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
01103 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
01104 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
01105 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
01106 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
01107 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
01108 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 6)
01109 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 6
01110 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x40UL
01111 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
01112 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 6)
01113 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 7)
01114 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 7
01115 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x80UL
01116 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
01117 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 7)
01118 #define CMU_HFPERCLKEN0_PRS (0x1UL << 8)
01119 #define _CMU_HFPERCLKEN0_PRS_SHIFT 8
01120 #define _CMU_HFPERCLKEN0_PRS_MASK 0x100UL
01121 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
01122 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 8)
01123 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 9)
01124 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 9
01125 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x200UL
01126 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL
01127 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 9)
01128 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 10)
01129 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 10
01130 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x400UL
01131 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL
01132 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 10)
01133 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)
01134 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11
01135 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL
01136 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
01137 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
01139
01140 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
01141 #define _CMU_SYNCBUSY_MASK 0x00000055UL
01142 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
01143 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
01144 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
01145 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
01146 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
01147 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
01148 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
01149 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
01150 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
01151 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
01152 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
01153 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
01154 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
01155 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
01156 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
01157 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
01158 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
01159 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
01160 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
01161 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
01163
01164 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
01165 #define _CMU_FREEZE_MASK 0x00000001UL
01166 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
01167 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
01168 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
01169 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
01170 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
01171 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
01172 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
01173 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
01174 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
01176
01177 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
01178 #define _CMU_LFACLKEN0_MASK 0x00000007UL
01179 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0)
01180 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0
01181 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL
01182 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL
01183 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)
01184 #define CMU_LFACLKEN0_RTC (0x1UL << 1)
01185 #define _CMU_LFACLKEN0_RTC_SHIFT 1
01186 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL
01187 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
01188 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1)
01189 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2)
01190 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2
01191 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL
01192 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
01193 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)
01195
01196 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
01197 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
01198 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
01199 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
01200 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
01201 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
01202 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
01204
01205 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
01206 #define _CMU_LFAPRESC0_MASK 0x00000FF3UL
01207 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0
01208 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL
01209 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL
01210 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL
01211 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL
01212 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL
01213 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)
01214 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)
01215 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)
01216 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)
01217 #define _CMU_LFAPRESC0_RTC_SHIFT 4
01218 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL
01219 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
01220 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
01221 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
01222 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
01223 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
01224 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
01225 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
01226 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
01227 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
01228 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
01229 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
01230 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
01231 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
01232 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
01233 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
01234 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
01235 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4)
01236 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4)
01237 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4)
01238 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4)
01239 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4)
01240 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4)
01241 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4)
01242 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4)
01243 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4)
01244 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4)
01245 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4)
01246 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4)
01247 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4)
01248 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4)
01249 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4)
01250 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4)
01251 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8
01252 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL
01253 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
01254 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
01255 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
01256 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
01257 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
01258 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
01259 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
01260 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
01261 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
01262 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
01263 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
01264 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
01265 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
01266 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
01267 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
01268 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
01269 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)
01270 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)
01271 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)
01272 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)
01273 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)
01274 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)
01275 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)
01276 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)
01277 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)
01278 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)
01279 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)
01280 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)
01281 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)
01282 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)
01283 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)
01284 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)
01286
01287 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
01288 #define _CMU_LFBPRESC0_MASK 0x00000003UL
01289 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
01290 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
01291 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
01292 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
01293 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
01294 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
01295 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
01296 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
01297 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
01298 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
01300
01301 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
01302 #define _CMU_PCNTCTRL_MASK 0x00000003UL
01303 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
01304 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
01305 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
01306 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
01307 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
01308 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
01309 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
01310 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
01311 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
01312 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
01313 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
01314 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
01315 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
01316 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
01318
01319 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
01320 #define _CMU_ROUTE_MASK 0x0000001FUL
01321 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
01322 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
01323 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
01324 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
01325 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
01326 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
01327 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
01328 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
01329 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
01330 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
01331 #define _CMU_ROUTE_LOCATION_SHIFT 2
01332 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL
01333 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
01334 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
01335 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
01336 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL
01337 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
01338 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
01339 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
01340 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)
01342
01343 #define _CMU_LOCK_RESETVALUE 0x00000000UL
01344 #define _CMU_LOCK_MASK 0x0000FFFFUL
01345 #define _CMU_LOCK_LOCKKEY_SHIFT 0
01346 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
01347 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
01348 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
01349 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
01350 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
01351 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
01352 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
01353 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
01354 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
01355 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
01356 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
01362
01366 #define MSC_UNLOCK_CODE 0x1B71
01367 #define EMU_UNLOCK_CODE 0xADE8
01368 #define CMU_UNLOCK_CODE 0x580E
01369 #define TIMER_UNLOCK_CODE 0xCE80
01370 #define GPIO_UNLOCK_CODE 0xA534
01376
01381 #include "efm32tg_af_ports.h"
01382 #include "efm32tg_af_pins.h"
01383
01386
01399 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
01400 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
01401
01406 #ifdef __cplusplus
01407 }
01408 #endif
01409 #endif