00001
00034 #ifndef __SILICON_LABS_EFM32TG108F32_H__
00035 #define __SILICON_LABS_EFM32TG108F32_H__
00036
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040
00041
00046
00052 typedef enum IRQn
00053 {
00054
00055 NonMaskableInt_IRQn = -14,
00056 HardFault_IRQn = -13,
00057 MemoryManagement_IRQn = -12,
00058 BusFault_IRQn = -11,
00059 UsageFault_IRQn = -10,
00060 SVCall_IRQn = -5,
00061 DebugMonitor_IRQn = -4,
00062 PendSV_IRQn = -2,
00063 SysTick_IRQn = -1,
00065
00066 DMA_IRQn = 0,
00067 GPIO_EVEN_IRQn = 1,
00068 TIMER0_IRQn = 2,
00069 ACMP0_IRQn = 5,
00070 I2C0_IRQn = 8,
00071 GPIO_ODD_IRQn = 9,
00072 TIMER1_IRQn = 10,
00073 USART1_RX_IRQn = 11,
00074 USART1_TX_IRQn = 12,
00075 LESENSE_IRQn = 13,
00076 LEUART0_IRQn = 14,
00077 LETIMER0_IRQn = 15,
00078 PCNT0_IRQn = 16,
00079 RTC_IRQn = 17,
00080 CMU_IRQn = 18,
00081 VCMP_IRQn = 19,
00082 MSC_IRQn = 21,
00083 } IRQn_Type;
00084
00085
00090 #define __MPU_PRESENT 0
00091 #define __NVIC_PRIO_BITS 3
00092 #define __Vendor_SysTickConfig 0
00096
00102 #define _EFM32_TINY_FAMILY 1
00103 #define _EFM_DEVICE
00104 #define _SILICON_LABS_32B_PLATFORM_1
00105 #define _SILICON_LABS_32B_PLATFORM 1
00107
00108 #if !defined(EFM32TG108F32)
00109 #define EFM32TG108F32 1
00110 #endif
00111
00113 #define PART_NUMBER "EFM32TG108F32"
00116 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
00117 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
00118 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
00119 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
00120 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
00121 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
00122 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
00123 #define AES_MEM_BITS ((uint32_t) 0x10UL)
00124 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
00125 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
00126 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
00127 #define PER_MEM_BITS ((uint32_t) 0x20UL)
00128 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
00129 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
00130 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
00131 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
00132 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
00133 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x4000UL)
00134 #define RAM_CODE_MEM_END ((uint32_t) 0x10003FFFUL)
00135 #define RAM_CODE_MEM_BITS ((uint32_t) 0x14UL)
00138 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
00139 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
00142 #define FLASH_BASE (0x00000000UL)
00143 #define FLASH_SIZE (0x00008000UL)
00144 #define FLASH_PAGE_SIZE 512
00145 #define SRAM_BASE (0x20000000UL)
00146 #define SRAM_SIZE (0x00001000UL)
00147 #define __CM3_REV 0x201
00148 #define PRS_CHAN_COUNT 8
00149 #define DMA_CHAN_COUNT 8
00152 #define AFCHAN_MAX 63
00153 #define AFCHANLOC_MAX 7
00154
00155 #define AFACHAN_MAX 47
00156
00157
00158
00159 #define ACMP_PRESENT
00160 #define ACMP_COUNT 2
00161 #define USART_PRESENT
00162 #define USART_COUNT 1
00163 #define TIMER_PRESENT
00164 #define TIMER_COUNT 2
00165 #define LEUART_PRESENT
00166 #define LEUART_COUNT 1
00167 #define LETIMER_PRESENT
00168 #define LETIMER_COUNT 1
00169 #define PCNT_PRESENT
00170 #define PCNT_COUNT 1
00171 #define I2C_PRESENT
00172 #define I2C_COUNT 1
00173 #define DMA_PRESENT
00174 #define DMA_COUNT 1
00175 #define LE_PRESENT
00176 #define LE_COUNT 1
00177 #define MSC_PRESENT
00178 #define MSC_COUNT 1
00179 #define EMU_PRESENT
00180 #define EMU_COUNT 1
00181 #define RMU_PRESENT
00182 #define RMU_COUNT 1
00183 #define CMU_PRESENT
00184 #define CMU_COUNT 1
00185 #define LESENSE_PRESENT
00186 #define LESENSE_COUNT 1
00187 #define RTC_PRESENT
00188 #define RTC_COUNT 1
00189 #define GPIO_PRESENT
00190 #define GPIO_COUNT 1
00191 #define VCMP_PRESENT
00192 #define VCMP_COUNT 1
00193 #define PRS_PRESENT
00194 #define PRS_COUNT 1
00195 #define HFXTAL_PRESENT
00196 #define HFXTAL_COUNT 1
00197 #define LFXTAL_PRESENT
00198 #define LFXTAL_COUNT 1
00199 #define WDOG_PRESENT
00200 #define WDOG_COUNT 1
00201 #define DBG_PRESENT
00202 #define DBG_COUNT 1
00203 #define BOOTLOADER_PRESENT
00204 #define BOOTLOADER_COUNT 1
00205 #define ANALOG_PRESENT
00206 #define ANALOG_COUNT 1
00207
00208 #include "core_cm3.h"
00209 #include "system_efm32tg.h"
00210
00213
00219 #include "efm32tg_dma_ch.h"
00220
00221
00226 typedef struct
00227 {
00228 __I uint32_t STATUS;
00229 __O uint32_t CONFIG;
00230 __IO uint32_t CTRLBASE;
00231 __I uint32_t ALTCTRLBASE;
00232 __I uint32_t CHWAITSTATUS;
00233 __O uint32_t CHSWREQ;
00234 __IO uint32_t CHUSEBURSTS;
00235 __O uint32_t CHUSEBURSTC;
00236 __IO uint32_t CHREQMASKS;
00237 __O uint32_t CHREQMASKC;
00238 __IO uint32_t CHENS;
00239 __O uint32_t CHENC;
00240 __IO uint32_t CHALTS;
00241 __O uint32_t CHALTC;
00242 __IO uint32_t CHPRIS;
00243 __O uint32_t CHPRIC;
00244 uint32_t RESERVED0[3];
00245 __IO uint32_t ERRORC;
00246 uint32_t RESERVED1[880];
00247 __I uint32_t CHREQSTATUS;
00248 uint32_t RESERVED2[1];
00249 __I uint32_t CHSREQSTATUS;
00251 uint32_t RESERVED3[121];
00252 __I uint32_t IF;
00253 __IO uint32_t IFS;
00254 __IO uint32_t IFC;
00255 __IO uint32_t IEN;
00257 uint32_t RESERVED4[60];
00258 DMA_CH_TypeDef CH[8];
00259 } DMA_TypeDef;
00261 #include "efm32tg_msc.h"
00262 #include "efm32tg_emu.h"
00263 #include "efm32tg_rmu.h"
00264
00265
00270 typedef struct
00271 {
00272 __IO uint32_t CTRL;
00273 __IO uint32_t HFCORECLKDIV;
00274 __IO uint32_t HFPERCLKDIV;
00275 __IO uint32_t HFRCOCTRL;
00276 __IO uint32_t LFRCOCTRL;
00277 __IO uint32_t AUXHFRCOCTRL;
00278 __IO uint32_t CALCTRL;
00279 __IO uint32_t CALCNT;
00280 __IO uint32_t OSCENCMD;
00281 __IO uint32_t CMD;
00282 __IO uint32_t LFCLKSEL;
00283 __I uint32_t STATUS;
00284 __I uint32_t IF;
00285 __IO uint32_t IFS;
00286 __IO uint32_t IFC;
00287 __IO uint32_t IEN;
00288 __IO uint32_t HFCORECLKEN0;
00289 __IO uint32_t HFPERCLKEN0;
00290 uint32_t RESERVED0[2];
00291 __I uint32_t SYNCBUSY;
00292 __IO uint32_t FREEZE;
00293 __IO uint32_t LFACLKEN0;
00294 uint32_t RESERVED1[1];
00295 __IO uint32_t LFBCLKEN0;
00296 uint32_t RESERVED2[1];
00297 __IO uint32_t LFAPRESC0;
00298 uint32_t RESERVED3[1];
00299 __IO uint32_t LFBPRESC0;
00300 uint32_t RESERVED4[1];
00301 __IO uint32_t PCNTCTRL;
00302 uint32_t RESERVED5[1];
00303 __IO uint32_t ROUTE;
00304 __IO uint32_t LOCK;
00305 } CMU_TypeDef;
00307 #include "efm32tg_lesense_st.h"
00308 #include "efm32tg_lesense_buf.h"
00309 #include "efm32tg_lesense_ch.h"
00310 #include "efm32tg_lesense.h"
00311 #include "efm32tg_rtc.h"
00312 #include "efm32tg_acmp.h"
00313 #include "efm32tg_usart.h"
00314 #include "efm32tg_timer_cc.h"
00315 #include "efm32tg_timer.h"
00316 #include "efm32tg_gpio_p.h"
00317 #include "efm32tg_gpio.h"
00318 #include "efm32tg_vcmp.h"
00319 #include "efm32tg_prs_ch.h"
00320
00321
00326 typedef struct
00327 {
00328 __IO uint32_t SWPULSE;
00329 __IO uint32_t SWLEVEL;
00330 __IO uint32_t ROUTE;
00332 uint32_t RESERVED0[1];
00333 PRS_CH_TypeDef CH[8];
00334 } PRS_TypeDef;
00336 #include "efm32tg_leuart.h"
00337 #include "efm32tg_letimer.h"
00338 #include "efm32tg_pcnt.h"
00339 #include "efm32tg_i2c.h"
00340 #include "efm32tg_wdog.h"
00341 #include "efm32tg_dma_descriptor.h"
00342 #include "efm32tg_devinfo.h"
00343 #include "efm32tg_romtable.h"
00344 #include "efm32tg_calibrate.h"
00345
00348
00353 #define DMA_BASE (0x400C2000UL)
00354 #define MSC_BASE (0x400C0000UL)
00355 #define EMU_BASE (0x400C6000UL)
00356 #define RMU_BASE (0x400CA000UL)
00357 #define CMU_BASE (0x400C8000UL)
00358 #define LESENSE_BASE (0x4008C000UL)
00359 #define RTC_BASE (0x40080000UL)
00360 #define ACMP0_BASE (0x40001000UL)
00361 #define ACMP1_BASE (0x40001400UL)
00362 #define USART1_BASE (0x4000C400UL)
00363 #define TIMER0_BASE (0x40010000UL)
00364 #define TIMER1_BASE (0x40010400UL)
00365 #define GPIO_BASE (0x40006000UL)
00366 #define VCMP_BASE (0x40000000UL)
00367 #define PRS_BASE (0x400CC000UL)
00368 #define LEUART0_BASE (0x40084000UL)
00369 #define LETIMER0_BASE (0x40082000UL)
00370 #define PCNT0_BASE (0x40086000UL)
00371 #define I2C0_BASE (0x4000A000UL)
00372 #define WDOG_BASE (0x40088000UL)
00373 #define CALIBRATE_BASE (0x0FE08000UL)
00374 #define DEVINFO_BASE (0x0FE081B0UL)
00375 #define ROMTABLE_BASE (0xE00FFFD0UL)
00376 #define LOCKBITS_BASE (0x0FE04000UL)
00377 #define USERDATA_BASE (0x0FE00000UL)
00381
00386 #define DMA ((DMA_TypeDef *) DMA_BASE)
00387 #define MSC ((MSC_TypeDef *) MSC_BASE)
00388 #define EMU ((EMU_TypeDef *) EMU_BASE)
00389 #define RMU ((RMU_TypeDef *) RMU_BASE)
00390 #define CMU ((CMU_TypeDef *) CMU_BASE)
00391 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE)
00392 #define RTC ((RTC_TypeDef *) RTC_BASE)
00393 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
00394 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
00395 #define USART1 ((USART_TypeDef *) USART1_BASE)
00396 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
00397 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
00398 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
00399 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
00400 #define PRS ((PRS_TypeDef *) PRS_BASE)
00401 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
00402 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
00403 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
00404 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
00405 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
00406 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
00407 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
00408 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
00412
00417
00423 #define PRS_VCMP_OUT ((1 << 16) + 0)
00424 #define PRS_ACMP0_OUT ((2 << 16) + 0)
00425 #define PRS_ACMP1_OUT ((3 << 16) + 0)
00426 #define PRS_USART1_TXC ((17 << 16) + 1)
00427 #define PRS_USART1_RXDATAV ((17 << 16) + 2)
00428 #define PRS_TIMER0_UF ((28 << 16) + 0)
00429 #define PRS_TIMER0_OF ((28 << 16) + 1)
00430 #define PRS_TIMER0_CC0 ((28 << 16) + 2)
00431 #define PRS_TIMER0_CC1 ((28 << 16) + 3)
00432 #define PRS_TIMER0_CC2 ((28 << 16) + 4)
00433 #define PRS_TIMER1_UF ((29 << 16) + 0)
00434 #define PRS_TIMER1_OF ((29 << 16) + 1)
00435 #define PRS_TIMER1_CC0 ((29 << 16) + 2)
00436 #define PRS_TIMER1_CC1 ((29 << 16) + 3)
00437 #define PRS_TIMER1_CC2 ((29 << 16) + 4)
00438 #define PRS_RTC_OF ((40 << 16) + 0)
00439 #define PRS_RTC_COMP0 ((40 << 16) + 1)
00440 #define PRS_RTC_COMP1 ((40 << 16) + 2)
00441 #define PRS_GPIO_PIN0 ((48 << 16) + 0)
00442 #define PRS_GPIO_PIN1 ((48 << 16) + 1)
00443 #define PRS_GPIO_PIN2 ((48 << 16) + 2)
00444 #define PRS_GPIO_PIN3 ((48 << 16) + 3)
00445 #define PRS_GPIO_PIN4 ((48 << 16) + 4)
00446 #define PRS_GPIO_PIN5 ((48 << 16) + 5)
00447 #define PRS_GPIO_PIN6 ((48 << 16) + 6)
00448 #define PRS_GPIO_PIN7 ((48 << 16) + 7)
00449 #define PRS_GPIO_PIN8 ((49 << 16) + 0)
00450 #define PRS_GPIO_PIN9 ((49 << 16) + 1)
00451 #define PRS_GPIO_PIN10 ((49 << 16) + 2)
00452 #define PRS_GPIO_PIN11 ((49 << 16) + 3)
00453 #define PRS_GPIO_PIN12 ((49 << 16) + 4)
00454 #define PRS_GPIO_PIN13 ((49 << 16) + 5)
00455 #define PRS_GPIO_PIN14 ((49 << 16) + 6)
00456 #define PRS_GPIO_PIN15 ((49 << 16) + 7)
00457 #define PRS_LETIMER0_CH0 ((52 << 16) + 0)
00458 #define PRS_LETIMER0_CH1 ((52 << 16) + 1)
00459 #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0)
00460 #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1)
00461 #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2)
00462 #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3)
00463 #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4)
00464 #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5)
00465 #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6)
00466 #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7)
00467 #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0)
00468 #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1)
00469 #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2)
00470 #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3)
00471 #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4)
00472 #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5)
00473 #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6)
00474 #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7)
00475 #define PRS_LESENSE_DEC0 ((59 << 16) + 0)
00476 #define PRS_LESENSE_DEC1 ((59 << 16) + 1)
00477 #define PRS_LESENSE_DEC2 ((59 << 16) + 2)
00481 #include "efm32tg_dmareq.h"
00482 #include "efm32tg_dmactrl.h"
00483
00484
00489
00490 #define _DMA_STATUS_RESETVALUE 0x10070000UL
00491 #define _DMA_STATUS_MASK 0x001F00F1UL
00492 #define DMA_STATUS_EN (0x1UL << 0)
00493 #define _DMA_STATUS_EN_SHIFT 0
00494 #define _DMA_STATUS_EN_MASK 0x1UL
00495 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL
00496 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
00497 #define _DMA_STATUS_STATE_SHIFT 4
00498 #define _DMA_STATUS_STATE_MASK 0xF0UL
00499 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL
00500 #define _DMA_STATUS_STATE_IDLE 0x00000000UL
00501 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
00502 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
00503 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
00504 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
00505 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
00506 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
00507 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
00508 #define _DMA_STATUS_STATE_STALLED 0x00000008UL
00509 #define _DMA_STATUS_STATE_DONE 0x00000009UL
00510 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
00511 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
00512 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
00513 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
00514 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
00515 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
00516 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
00517 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
00518 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
00519 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
00520 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
00521 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
00522 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
00523 #define _DMA_STATUS_CHNUM_SHIFT 16
00524 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL
00525 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000007UL
00526 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
00528
00529 #define _DMA_CONFIG_RESETVALUE 0x00000000UL
00530 #define _DMA_CONFIG_MASK 0x00000021UL
00531 #define DMA_CONFIG_EN (0x1UL << 0)
00532 #define _DMA_CONFIG_EN_SHIFT 0
00533 #define _DMA_CONFIG_EN_MASK 0x1UL
00534 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL
00535 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
00536 #define DMA_CONFIG_CHPROT (0x1UL << 5)
00537 #define _DMA_CONFIG_CHPROT_SHIFT 5
00538 #define _DMA_CONFIG_CHPROT_MASK 0x20UL
00539 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
00540 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
00542
00543 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL
00544 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL
00545 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0
00546 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
00547 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
00548 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
00550
00551 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000080UL
00552 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00553 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
00554 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00555 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000080UL
00556 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
00558
00559 #define _DMA_CHWAITSTATUS_RESETVALUE 0x000000FFUL
00560 #define _DMA_CHWAITSTATUS_MASK 0x000000FFUL
00561 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
00562 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
00563 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
00564 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
00565 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
00566 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
00567 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
00568 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
00569 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
00570 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
00571 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
00572 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
00573 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
00574 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
00575 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
00576 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
00577 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
00578 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
00579 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
00580 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
00581 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4)
00582 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4
00583 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL
00584 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL
00585 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4)
00586 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5)
00587 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5
00588 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL
00589 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL
00590 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5)
00591 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6)
00592 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6
00593 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL
00594 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL
00595 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6)
00596 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7)
00597 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7
00598 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL
00599 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL
00600 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7)
00602
00603 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL
00604 #define _DMA_CHSWREQ_MASK 0x000000FFUL
00605 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
00606 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0
00607 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
00608 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
00609 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
00610 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
00611 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1
00612 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
00613 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
00614 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
00615 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
00616 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2
00617 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
00618 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
00619 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
00620 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
00621 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3
00622 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
00623 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
00624 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
00625 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4)
00626 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4
00627 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL
00628 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL
00629 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4)
00630 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5)
00631 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5
00632 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL
00633 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL
00634 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5)
00635 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6)
00636 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6
00637 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL
00638 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL
00639 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6)
00640 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7)
00641 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7
00642 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL
00643 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL
00644 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7)
00646
00647 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
00648 #define _DMA_CHUSEBURSTS_MASK 0x000000FFUL
00649 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
00650 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
00651 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
00652 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
00653 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
00654 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
00655 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
00656 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
00657 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
00658 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
00659 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
00660 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
00661 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
00662 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
00663 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
00664 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
00665 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
00666 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
00667 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
00668 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
00669 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
00670 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
00671 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
00672 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
00673 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4)
00674 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4
00675 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL
00676 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL
00677 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4)
00678 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5)
00679 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5
00680 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL
00681 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL
00682 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5)
00683 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6)
00684 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6
00685 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL
00686 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL
00687 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6)
00688 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7)
00689 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7
00690 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL
00691 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL
00692 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7)
00694
00695 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
00696 #define _DMA_CHUSEBURSTC_MASK 0x000000FFUL
00697 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
00698 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
00699 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
00700 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
00701 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
00702 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
00703 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
00704 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
00705 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
00706 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
00707 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
00708 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
00709 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
00710 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
00711 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
00712 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
00713 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
00714 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
00715 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
00716 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
00717 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4)
00718 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4
00719 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL
00720 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL
00721 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4)
00722 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5)
00723 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5
00724 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL
00725 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL
00726 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5)
00727 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6)
00728 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6
00729 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL
00730 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL
00731 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6)
00732 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7)
00733 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7
00734 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL
00735 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL
00736 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7)
00738
00739 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
00740 #define _DMA_CHREQMASKS_MASK 0x000000FFUL
00741 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
00742 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
00743 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
00744 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
00745 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
00746 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
00747 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
00748 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
00749 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
00750 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
00751 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
00752 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
00753 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
00754 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
00755 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
00756 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
00757 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
00758 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
00759 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
00760 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
00761 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4)
00762 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4
00763 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL
00764 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL
00765 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4)
00766 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5)
00767 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5
00768 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL
00769 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL
00770 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5)
00771 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6)
00772 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6
00773 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL
00774 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL
00775 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6)
00776 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7)
00777 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7
00778 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL
00779 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL
00780 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7)
00782
00783 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
00784 #define _DMA_CHREQMASKC_MASK 0x000000FFUL
00785 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
00786 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
00787 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
00788 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
00789 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
00790 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
00791 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
00792 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
00793 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
00794 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
00795 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
00796 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
00797 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
00798 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
00799 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
00800 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
00801 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
00802 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
00803 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
00804 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
00805 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4)
00806 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4
00807 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL
00808 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL
00809 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4)
00810 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5)
00811 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5
00812 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL
00813 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL
00814 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5)
00815 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6)
00816 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6
00817 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL
00818 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL
00819 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6)
00820 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7)
00821 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7
00822 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL
00823 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL
00824 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7)
00826
00827 #define _DMA_CHENS_RESETVALUE 0x00000000UL
00828 #define _DMA_CHENS_MASK 0x000000FFUL
00829 #define DMA_CHENS_CH0ENS (0x1UL << 0)
00830 #define _DMA_CHENS_CH0ENS_SHIFT 0
00831 #define _DMA_CHENS_CH0ENS_MASK 0x1UL
00832 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
00833 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
00834 #define DMA_CHENS_CH1ENS (0x1UL << 1)
00835 #define _DMA_CHENS_CH1ENS_SHIFT 1
00836 #define _DMA_CHENS_CH1ENS_MASK 0x2UL
00837 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
00838 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
00839 #define DMA_CHENS_CH2ENS (0x1UL << 2)
00840 #define _DMA_CHENS_CH2ENS_SHIFT 2
00841 #define _DMA_CHENS_CH2ENS_MASK 0x4UL
00842 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
00843 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
00844 #define DMA_CHENS_CH3ENS (0x1UL << 3)
00845 #define _DMA_CHENS_CH3ENS_SHIFT 3
00846 #define _DMA_CHENS_CH3ENS_MASK 0x8UL
00847 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
00848 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
00849 #define DMA_CHENS_CH4ENS (0x1UL << 4)
00850 #define _DMA_CHENS_CH4ENS_SHIFT 4
00851 #define _DMA_CHENS_CH4ENS_MASK 0x10UL
00852 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL
00853 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4)
00854 #define DMA_CHENS_CH5ENS (0x1UL << 5)
00855 #define _DMA_CHENS_CH5ENS_SHIFT 5
00856 #define _DMA_CHENS_CH5ENS_MASK 0x20UL
00857 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL
00858 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5)
00859 #define DMA_CHENS_CH6ENS (0x1UL << 6)
00860 #define _DMA_CHENS_CH6ENS_SHIFT 6
00861 #define _DMA_CHENS_CH6ENS_MASK 0x40UL
00862 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL
00863 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6)
00864 #define DMA_CHENS_CH7ENS (0x1UL << 7)
00865 #define _DMA_CHENS_CH7ENS_SHIFT 7
00866 #define _DMA_CHENS_CH7ENS_MASK 0x80UL
00867 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL
00868 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7)
00870
00871 #define _DMA_CHENC_RESETVALUE 0x00000000UL
00872 #define _DMA_CHENC_MASK 0x000000FFUL
00873 #define DMA_CHENC_CH0ENC (0x1UL << 0)
00874 #define _DMA_CHENC_CH0ENC_SHIFT 0
00875 #define _DMA_CHENC_CH0ENC_MASK 0x1UL
00876 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
00877 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
00878 #define DMA_CHENC_CH1ENC (0x1UL << 1)
00879 #define _DMA_CHENC_CH1ENC_SHIFT 1
00880 #define _DMA_CHENC_CH1ENC_MASK 0x2UL
00881 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
00882 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
00883 #define DMA_CHENC_CH2ENC (0x1UL << 2)
00884 #define _DMA_CHENC_CH2ENC_SHIFT 2
00885 #define _DMA_CHENC_CH2ENC_MASK 0x4UL
00886 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
00887 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
00888 #define DMA_CHENC_CH3ENC (0x1UL << 3)
00889 #define _DMA_CHENC_CH3ENC_SHIFT 3
00890 #define _DMA_CHENC_CH3ENC_MASK 0x8UL
00891 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
00892 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
00893 #define DMA_CHENC_CH4ENC (0x1UL << 4)
00894 #define _DMA_CHENC_CH4ENC_SHIFT 4
00895 #define _DMA_CHENC_CH4ENC_MASK 0x10UL
00896 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL
00897 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4)
00898 #define DMA_CHENC_CH5ENC (0x1UL << 5)
00899 #define _DMA_CHENC_CH5ENC_SHIFT 5
00900 #define _DMA_CHENC_CH5ENC_MASK 0x20UL
00901 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL
00902 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5)
00903 #define DMA_CHENC_CH6ENC (0x1UL << 6)
00904 #define _DMA_CHENC_CH6ENC_SHIFT 6
00905 #define _DMA_CHENC_CH6ENC_MASK 0x40UL
00906 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL
00907 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6)
00908 #define DMA_CHENC_CH7ENC (0x1UL << 7)
00909 #define _DMA_CHENC_CH7ENC_SHIFT 7
00910 #define _DMA_CHENC_CH7ENC_MASK 0x80UL
00911 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL
00912 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7)
00914
00915 #define _DMA_CHALTS_RESETVALUE 0x00000000UL
00916 #define _DMA_CHALTS_MASK 0x000000FFUL
00917 #define DMA_CHALTS_CH0ALTS (0x1UL << 0)
00918 #define _DMA_CHALTS_CH0ALTS_SHIFT 0
00919 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
00920 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
00921 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
00922 #define DMA_CHALTS_CH1ALTS (0x1UL << 1)
00923 #define _DMA_CHALTS_CH1ALTS_SHIFT 1
00924 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
00925 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
00926 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
00927 #define DMA_CHALTS_CH2ALTS (0x1UL << 2)
00928 #define _DMA_CHALTS_CH2ALTS_SHIFT 2
00929 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
00930 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
00931 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
00932 #define DMA_CHALTS_CH3ALTS (0x1UL << 3)
00933 #define _DMA_CHALTS_CH3ALTS_SHIFT 3
00934 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
00935 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
00936 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
00937 #define DMA_CHALTS_CH4ALTS (0x1UL << 4)
00938 #define _DMA_CHALTS_CH4ALTS_SHIFT 4
00939 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL
00940 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL
00941 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4)
00942 #define DMA_CHALTS_CH5ALTS (0x1UL << 5)
00943 #define _DMA_CHALTS_CH5ALTS_SHIFT 5
00944 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL
00945 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL
00946 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5)
00947 #define DMA_CHALTS_CH6ALTS (0x1UL << 6)
00948 #define _DMA_CHALTS_CH6ALTS_SHIFT 6
00949 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL
00950 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL
00951 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6)
00952 #define DMA_CHALTS_CH7ALTS (0x1UL << 7)
00953 #define _DMA_CHALTS_CH7ALTS_SHIFT 7
00954 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL
00955 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL
00956 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7)
00958
00959 #define _DMA_CHALTC_RESETVALUE 0x00000000UL
00960 #define _DMA_CHALTC_MASK 0x000000FFUL
00961 #define DMA_CHALTC_CH0ALTC (0x1UL << 0)
00962 #define _DMA_CHALTC_CH0ALTC_SHIFT 0
00963 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
00964 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
00965 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
00966 #define DMA_CHALTC_CH1ALTC (0x1UL << 1)
00967 #define _DMA_CHALTC_CH1ALTC_SHIFT 1
00968 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
00969 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
00970 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
00971 #define DMA_CHALTC_CH2ALTC (0x1UL << 2)
00972 #define _DMA_CHALTC_CH2ALTC_SHIFT 2
00973 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
00974 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
00975 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
00976 #define DMA_CHALTC_CH3ALTC (0x1UL << 3)
00977 #define _DMA_CHALTC_CH3ALTC_SHIFT 3
00978 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
00979 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
00980 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
00981 #define DMA_CHALTC_CH4ALTC (0x1UL << 4)
00982 #define _DMA_CHALTC_CH4ALTC_SHIFT 4
00983 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL
00984 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL
00985 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4)
00986 #define DMA_CHALTC_CH5ALTC (0x1UL << 5)
00987 #define _DMA_CHALTC_CH5ALTC_SHIFT 5
00988 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL
00989 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL
00990 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5)
00991 #define DMA_CHALTC_CH6ALTC (0x1UL << 6)
00992 #define _DMA_CHALTC_CH6ALTC_SHIFT 6
00993 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL
00994 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL
00995 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6)
00996 #define DMA_CHALTC_CH7ALTC (0x1UL << 7)
00997 #define _DMA_CHALTC_CH7ALTC_SHIFT 7
00998 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL
00999 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL
01000 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7)
01002
01003 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL
01004 #define _DMA_CHPRIS_MASK 0x000000FFUL
01005 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0)
01006 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0
01007 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
01008 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
01009 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
01010 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1)
01011 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1
01012 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
01013 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
01014 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
01015 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2)
01016 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2
01017 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
01018 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
01019 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
01020 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3)
01021 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3
01022 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
01023 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
01024 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
01025 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4)
01026 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4
01027 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL
01028 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL
01029 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4)
01030 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5)
01031 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5
01032 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL
01033 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL
01034 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5)
01035 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6)
01036 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6
01037 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL
01038 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL
01039 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6)
01040 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7)
01041 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7
01042 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL
01043 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL
01044 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7)
01046
01047 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL
01048 #define _DMA_CHPRIC_MASK 0x000000FFUL
01049 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0)
01050 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0
01051 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
01052 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
01053 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
01054 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1)
01055 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1
01056 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
01057 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
01058 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
01059 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2)
01060 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2
01061 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
01062 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
01063 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
01064 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3)
01065 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3
01066 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
01067 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
01068 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
01069 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4)
01070 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4
01071 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL
01072 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL
01073 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4)
01074 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5)
01075 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5
01076 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL
01077 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL
01078 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5)
01079 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6)
01080 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6
01081 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL
01082 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL
01083 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6)
01084 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7)
01085 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7
01086 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL
01087 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL
01088 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7)
01090
01091 #define _DMA_ERRORC_RESETVALUE 0x00000000UL
01092 #define _DMA_ERRORC_MASK 0x00000001UL
01093 #define DMA_ERRORC_ERRORC (0x1UL << 0)
01094 #define _DMA_ERRORC_ERRORC_SHIFT 0
01095 #define _DMA_ERRORC_ERRORC_MASK 0x1UL
01096 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
01097 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
01099
01100 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
01101 #define _DMA_CHREQSTATUS_MASK 0x000000FFUL
01102 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
01103 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
01104 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
01105 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
01106 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
01107 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
01108 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
01109 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
01110 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
01111 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
01112 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
01113 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
01114 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
01115 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
01116 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
01117 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
01118 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
01119 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
01120 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
01121 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
01122 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4)
01123 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4
01124 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL
01125 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL
01126 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4)
01127 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5)
01128 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5
01129 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL
01130 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL
01131 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5)
01132 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6)
01133 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6
01134 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL
01135 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL
01136 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6)
01137 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7)
01138 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7
01139 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL
01140 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL
01141 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7)
01143
01144 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
01145 #define _DMA_CHSREQSTATUS_MASK 0x000000FFUL
01146 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
01147 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
01148 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
01149 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
01150 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
01151 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
01152 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
01153 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
01154 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
01155 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
01156 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
01157 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
01158 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
01159 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
01160 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
01161 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
01162 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
01163 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
01164 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
01165 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
01166 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4)
01167 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4
01168 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL
01169 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL
01170 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4)
01171 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5)
01172 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5
01173 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL
01174 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL
01175 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5)
01176 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6)
01177 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6
01178 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL
01179 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL
01180 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6)
01181 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7)
01182 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7
01183 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL
01184 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL
01185 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7)
01187
01188 #define _DMA_IF_RESETVALUE 0x00000000UL
01189 #define _DMA_IF_MASK 0x800000FFUL
01190 #define DMA_IF_CH0DONE (0x1UL << 0)
01191 #define _DMA_IF_CH0DONE_SHIFT 0
01192 #define _DMA_IF_CH0DONE_MASK 0x1UL
01193 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL
01194 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
01195 #define DMA_IF_CH1DONE (0x1UL << 1)
01196 #define _DMA_IF_CH1DONE_SHIFT 1
01197 #define _DMA_IF_CH1DONE_MASK 0x2UL
01198 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL
01199 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
01200 #define DMA_IF_CH2DONE (0x1UL << 2)
01201 #define _DMA_IF_CH2DONE_SHIFT 2
01202 #define _DMA_IF_CH2DONE_MASK 0x4UL
01203 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL
01204 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
01205 #define DMA_IF_CH3DONE (0x1UL << 3)
01206 #define _DMA_IF_CH3DONE_SHIFT 3
01207 #define _DMA_IF_CH3DONE_MASK 0x8UL
01208 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL
01209 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
01210 #define DMA_IF_CH4DONE (0x1UL << 4)
01211 #define _DMA_IF_CH4DONE_SHIFT 4
01212 #define _DMA_IF_CH4DONE_MASK 0x10UL
01213 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL
01214 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4)
01215 #define DMA_IF_CH5DONE (0x1UL << 5)
01216 #define _DMA_IF_CH5DONE_SHIFT 5
01217 #define _DMA_IF_CH5DONE_MASK 0x20UL
01218 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL
01219 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5)
01220 #define DMA_IF_CH6DONE (0x1UL << 6)
01221 #define _DMA_IF_CH6DONE_SHIFT 6
01222 #define _DMA_IF_CH6DONE_MASK 0x40UL
01223 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL
01224 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6)
01225 #define DMA_IF_CH7DONE (0x1UL << 7)
01226 #define _DMA_IF_CH7DONE_SHIFT 7
01227 #define _DMA_IF_CH7DONE_MASK 0x80UL
01228 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL
01229 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7)
01230 #define DMA_IF_ERR (0x1UL << 31)
01231 #define _DMA_IF_ERR_SHIFT 31
01232 #define _DMA_IF_ERR_MASK 0x80000000UL
01233 #define _DMA_IF_ERR_DEFAULT 0x00000000UL
01234 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
01236
01237 #define _DMA_IFS_RESETVALUE 0x00000000UL
01238 #define _DMA_IFS_MASK 0x800000FFUL
01239 #define DMA_IFS_CH0DONE (0x1UL << 0)
01240 #define _DMA_IFS_CH0DONE_SHIFT 0
01241 #define _DMA_IFS_CH0DONE_MASK 0x1UL
01242 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
01243 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
01244 #define DMA_IFS_CH1DONE (0x1UL << 1)
01245 #define _DMA_IFS_CH1DONE_SHIFT 1
01246 #define _DMA_IFS_CH1DONE_MASK 0x2UL
01247 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
01248 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
01249 #define DMA_IFS_CH2DONE (0x1UL << 2)
01250 #define _DMA_IFS_CH2DONE_SHIFT 2
01251 #define _DMA_IFS_CH2DONE_MASK 0x4UL
01252 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
01253 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
01254 #define DMA_IFS_CH3DONE (0x1UL << 3)
01255 #define _DMA_IFS_CH3DONE_SHIFT 3
01256 #define _DMA_IFS_CH3DONE_MASK 0x8UL
01257 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
01258 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
01259 #define DMA_IFS_CH4DONE (0x1UL << 4)
01260 #define _DMA_IFS_CH4DONE_SHIFT 4
01261 #define _DMA_IFS_CH4DONE_MASK 0x10UL
01262 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL
01263 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4)
01264 #define DMA_IFS_CH5DONE (0x1UL << 5)
01265 #define _DMA_IFS_CH5DONE_SHIFT 5
01266 #define _DMA_IFS_CH5DONE_MASK 0x20UL
01267 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL
01268 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5)
01269 #define DMA_IFS_CH6DONE (0x1UL << 6)
01270 #define _DMA_IFS_CH6DONE_SHIFT 6
01271 #define _DMA_IFS_CH6DONE_MASK 0x40UL
01272 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL
01273 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6)
01274 #define DMA_IFS_CH7DONE (0x1UL << 7)
01275 #define _DMA_IFS_CH7DONE_SHIFT 7
01276 #define _DMA_IFS_CH7DONE_MASK 0x80UL
01277 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL
01278 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7)
01279 #define DMA_IFS_ERR (0x1UL << 31)
01280 #define _DMA_IFS_ERR_SHIFT 31
01281 #define _DMA_IFS_ERR_MASK 0x80000000UL
01282 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL
01283 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
01285
01286 #define _DMA_IFC_RESETVALUE 0x00000000UL
01287 #define _DMA_IFC_MASK 0x800000FFUL
01288 #define DMA_IFC_CH0DONE (0x1UL << 0)
01289 #define _DMA_IFC_CH0DONE_SHIFT 0
01290 #define _DMA_IFC_CH0DONE_MASK 0x1UL
01291 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
01292 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
01293 #define DMA_IFC_CH1DONE (0x1UL << 1)
01294 #define _DMA_IFC_CH1DONE_SHIFT 1
01295 #define _DMA_IFC_CH1DONE_MASK 0x2UL
01296 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
01297 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
01298 #define DMA_IFC_CH2DONE (0x1UL << 2)
01299 #define _DMA_IFC_CH2DONE_SHIFT 2
01300 #define _DMA_IFC_CH2DONE_MASK 0x4UL
01301 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
01302 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
01303 #define DMA_IFC_CH3DONE (0x1UL << 3)
01304 #define _DMA_IFC_CH3DONE_SHIFT 3
01305 #define _DMA_IFC_CH3DONE_MASK 0x8UL
01306 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
01307 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
01308 #define DMA_IFC_CH4DONE (0x1UL << 4)
01309 #define _DMA_IFC_CH4DONE_SHIFT 4
01310 #define _DMA_IFC_CH4DONE_MASK 0x10UL
01311 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL
01312 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4)
01313 #define DMA_IFC_CH5DONE (0x1UL << 5)
01314 #define _DMA_IFC_CH5DONE_SHIFT 5
01315 #define _DMA_IFC_CH5DONE_MASK 0x20UL
01316 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL
01317 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5)
01318 #define DMA_IFC_CH6DONE (0x1UL << 6)
01319 #define _DMA_IFC_CH6DONE_SHIFT 6
01320 #define _DMA_IFC_CH6DONE_MASK 0x40UL
01321 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL
01322 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6)
01323 #define DMA_IFC_CH7DONE (0x1UL << 7)
01324 #define _DMA_IFC_CH7DONE_SHIFT 7
01325 #define _DMA_IFC_CH7DONE_MASK 0x80UL
01326 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL
01327 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7)
01328 #define DMA_IFC_ERR (0x1UL << 31)
01329 #define _DMA_IFC_ERR_SHIFT 31
01330 #define _DMA_IFC_ERR_MASK 0x80000000UL
01331 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL
01332 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
01334
01335 #define _DMA_IEN_RESETVALUE 0x00000000UL
01336 #define _DMA_IEN_MASK 0x800000FFUL
01337 #define DMA_IEN_CH0DONE (0x1UL << 0)
01338 #define _DMA_IEN_CH0DONE_SHIFT 0
01339 #define _DMA_IEN_CH0DONE_MASK 0x1UL
01340 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
01341 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
01342 #define DMA_IEN_CH1DONE (0x1UL << 1)
01343 #define _DMA_IEN_CH1DONE_SHIFT 1
01344 #define _DMA_IEN_CH1DONE_MASK 0x2UL
01345 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
01346 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
01347 #define DMA_IEN_CH2DONE (0x1UL << 2)
01348 #define _DMA_IEN_CH2DONE_SHIFT 2
01349 #define _DMA_IEN_CH2DONE_MASK 0x4UL
01350 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
01351 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
01352 #define DMA_IEN_CH3DONE (0x1UL << 3)
01353 #define _DMA_IEN_CH3DONE_SHIFT 3
01354 #define _DMA_IEN_CH3DONE_MASK 0x8UL
01355 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
01356 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
01357 #define DMA_IEN_CH4DONE (0x1UL << 4)
01358 #define _DMA_IEN_CH4DONE_SHIFT 4
01359 #define _DMA_IEN_CH4DONE_MASK 0x10UL
01360 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL
01361 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4)
01362 #define DMA_IEN_CH5DONE (0x1UL << 5)
01363 #define _DMA_IEN_CH5DONE_SHIFT 5
01364 #define _DMA_IEN_CH5DONE_MASK 0x20UL
01365 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL
01366 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5)
01367 #define DMA_IEN_CH6DONE (0x1UL << 6)
01368 #define _DMA_IEN_CH6DONE_SHIFT 6
01369 #define _DMA_IEN_CH6DONE_MASK 0x40UL
01370 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL
01371 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6)
01372 #define DMA_IEN_CH7DONE (0x1UL << 7)
01373 #define _DMA_IEN_CH7DONE_SHIFT 7
01374 #define _DMA_IEN_CH7DONE_MASK 0x80UL
01375 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL
01376 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7)
01377 #define DMA_IEN_ERR (0x1UL << 31)
01378 #define _DMA_IEN_ERR_SHIFT 31
01379 #define _DMA_IEN_ERR_MASK 0x80000000UL
01380 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL
01381 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
01383
01384 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
01385 #define _DMA_CH_CTRL_MASK 0x003F000FUL
01386 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0
01387 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
01388 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
01389 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
01390 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
01391 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
01392 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
01393 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
01394 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL
01395 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
01396 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
01397 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
01398 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
01399 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
01400 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
01401 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
01402 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
01403 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
01404 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL
01405 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
01406 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
01407 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL
01408 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
01409 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
01410 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
01411 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
01412 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
01413 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
01414 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0)
01415 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
01416 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
01417 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
01418 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
01419 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
01420 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
01421 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
01422 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
01423 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
01424 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)
01425 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
01426 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
01427 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)
01428 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
01429 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
01430 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
01431 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
01432 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
01433 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
01434 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
01435 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
01436 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
01437 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL
01438 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
01439 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
01440 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
01441 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
01442 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
01443 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
01444 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
01445 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16)
01451
01456
01457 #define _CMU_CTRL_RESETVALUE 0x000C262CUL
01458 #define _CMU_CTRL_MASK 0x17FE3EEFUL
01459 #define _CMU_CTRL_HFXOMODE_SHIFT 0
01460 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL
01461 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL
01462 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL
01463 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL
01464 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL
01465 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0)
01466 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0)
01467 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)
01468 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)
01469 #define _CMU_CTRL_HFXOBOOST_SHIFT 2
01470 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL
01471 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL
01472 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL
01473 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL
01474 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL
01475 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL
01476 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2)
01477 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2)
01478 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2)
01479 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)
01480 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2)
01481 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5
01482 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL
01483 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL
01484 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)
01485 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7)
01486 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7
01487 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL
01488 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL
01489 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7)
01490 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9
01491 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL
01492 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL
01493 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL
01494 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL
01495 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL
01496 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL
01497 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)
01498 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)
01499 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)
01500 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)
01501 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)
01502 #define _CMU_CTRL_LFXOMODE_SHIFT 11
01503 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL
01504 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL
01505 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL
01506 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL
01507 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL
01508 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11)
01509 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11)
01510 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)
01511 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)
01512 #define CMU_CTRL_LFXOBOOST (0x1UL << 13)
01513 #define _CMU_CTRL_LFXOBOOST_SHIFT 13
01514 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL
01515 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL
01516 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL
01517 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL
01518 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13)
01519 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)
01520 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13)
01521 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17)
01522 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17
01523 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL
01524 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL
01525 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)
01526 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18
01527 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL
01528 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL
01529 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL
01530 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL
01531 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL
01532 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL
01533 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)
01534 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)
01535 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)
01536 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)
01537 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)
01538 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20
01539 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL
01540 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL
01541 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL
01542 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL
01543 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL
01544 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL
01545 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL
01546 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL
01547 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL
01548 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL
01549 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)
01550 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)
01551 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)
01552 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)
01553 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)
01554 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)
01555 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)
01556 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)
01557 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)
01558 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23
01559 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL
01560 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL
01561 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL
01562 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL
01563 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL
01564 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL
01565 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL
01566 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL
01567 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL
01568 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL
01569 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)
01570 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)
01571 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)
01572 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)
01573 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)
01574 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)
01575 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)
01576 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)
01577 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)
01578 #define CMU_CTRL_DBGCLK (0x1UL << 28)
01579 #define _CMU_CTRL_DBGCLK_SHIFT 28
01580 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL
01581 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL
01582 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL
01583 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL
01584 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28)
01585 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28)
01586 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28)
01588
01589 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL
01590 #define _CMU_HFCORECLKDIV_MASK 0x0000000FUL
01591 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0
01592 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL
01593 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL
01594 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL
01595 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL
01596 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL
01597 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL
01598 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL
01599 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL
01600 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL
01601 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL
01602 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL
01603 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL
01604 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)
01605 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)
01606 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)
01607 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)
01608 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)
01609 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)
01610 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)
01611 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)
01612 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)
01613 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)
01614 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)
01616
01617 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL
01618 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL
01619 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0
01620 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL
01621 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL
01622 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL
01623 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL
01624 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL
01625 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL
01626 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL
01627 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL
01628 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL
01629 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL
01630 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL
01631 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL
01632 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)
01633 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)
01634 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)
01635 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)
01636 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)
01637 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)
01638 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)
01639 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)
01640 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0)
01641 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0)
01642 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0)
01643 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8)
01644 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8
01645 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL
01646 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL
01647 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)
01649
01650 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL
01651 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL
01652 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0
01653 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL
01654 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01655 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)
01656 #define _CMU_HFRCOCTRL_BAND_SHIFT 8
01657 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL
01658 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL
01659 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL
01660 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL
01661 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL
01662 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL
01663 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL
01664 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL
01665 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8)
01666 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8)
01667 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8)
01668 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)
01669 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8)
01670 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8)
01671 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8)
01672 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12
01673 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL
01674 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL
01675 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12)
01677
01678 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL
01679 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL
01680 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0
01681 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL
01682 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL
01683 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0)
01685
01686 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL
01687 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL
01688 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0
01689 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL
01690 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL
01691 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0)
01692 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8
01693 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL
01694 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL
01695 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL
01696 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL
01697 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL
01698 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL
01699 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL
01700 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL
01701 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)
01702 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)
01703 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)
01704 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)
01705 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)
01706 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8)
01707 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)
01709
01710 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL
01711 #define _CMU_CALCTRL_MASK 0x0000007FUL
01712 #define _CMU_CALCTRL_UPSEL_SHIFT 0
01713 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL
01714 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL
01715 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL
01716 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL
01717 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL
01718 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL
01719 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL
01720 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0)
01721 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0)
01722 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0)
01723 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0)
01724 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0)
01725 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)
01726 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3
01727 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL
01728 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL
01729 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL
01730 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL
01731 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL
01732 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL
01733 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL
01734 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL
01735 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)
01736 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)
01737 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3)
01738 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3)
01739 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)
01740 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)
01741 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3)
01742 #define CMU_CALCTRL_CONT (0x1UL << 6)
01743 #define _CMU_CALCTRL_CONT_SHIFT 6
01744 #define _CMU_CALCTRL_CONT_MASK 0x40UL
01745 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL
01746 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6)
01748
01749 #define _CMU_CALCNT_RESETVALUE 0x00000000UL
01750 #define _CMU_CALCNT_MASK 0x000FFFFFUL
01751 #define _CMU_CALCNT_CALCNT_SHIFT 0
01752 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL
01753 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL
01754 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0)
01756
01757 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL
01758 #define _CMU_OSCENCMD_MASK 0x000003FFUL
01759 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0)
01760 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0
01761 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL
01762 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL
01763 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)
01764 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1)
01765 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1
01766 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL
01767 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL
01768 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)
01769 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2)
01770 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2
01771 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL
01772 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL
01773 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)
01774 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3)
01775 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3
01776 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL
01777 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL
01778 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)
01779 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4)
01780 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4
01781 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL
01782 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL
01783 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)
01784 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5)
01785 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5
01786 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL
01787 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL
01788 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5)
01789 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6)
01790 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6
01791 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL
01792 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL
01793 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)
01794 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7)
01795 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7
01796 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL
01797 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL
01798 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)
01799 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8)
01800 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8
01801 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL
01802 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL
01803 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)
01804 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9)
01805 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9
01806 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL
01807 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL
01808 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)
01810
01811 #define _CMU_CMD_RESETVALUE 0x00000000UL
01812 #define _CMU_CMD_MASK 0x0000001FUL
01813 #define _CMU_CMD_HFCLKSEL_SHIFT 0
01814 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL
01815 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL
01816 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL
01817 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL
01818 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL
01819 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL
01820 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0)
01821 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0)
01822 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0)
01823 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0)
01824 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0)
01825 #define CMU_CMD_CALSTART (0x1UL << 3)
01826 #define _CMU_CMD_CALSTART_SHIFT 3
01827 #define _CMU_CMD_CALSTART_MASK 0x8UL
01828 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL
01829 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3)
01830 #define CMU_CMD_CALSTOP (0x1UL << 4)
01831 #define _CMU_CMD_CALSTOP_SHIFT 4
01832 #define _CMU_CMD_CALSTOP_MASK 0x10UL
01833 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL
01834 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4)
01836
01837 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL
01838 #define _CMU_LFCLKSEL_MASK 0x0011000FUL
01839 #define _CMU_LFCLKSEL_LFA_SHIFT 0
01840 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL
01841 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL
01842 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL
01843 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL
01844 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL
01845 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL
01846 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0)
01847 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0)
01848 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0)
01849 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0)
01850 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0)
01851 #define _CMU_LFCLKSEL_LFB_SHIFT 2
01852 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL
01853 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL
01854 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL
01855 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL
01856 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL
01857 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL
01858 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2)
01859 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2)
01860 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2)
01861 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2)
01862 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2)
01863 #define CMU_LFCLKSEL_LFAE (0x1UL << 16)
01864 #define _CMU_LFCLKSEL_LFAE_SHIFT 16
01865 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL
01866 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL
01867 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL
01868 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL
01869 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)
01870 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16)
01871 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)
01872 #define CMU_LFCLKSEL_LFBE (0x1UL << 20)
01873 #define _CMU_LFCLKSEL_LFBE_SHIFT 20
01874 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL
01875 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL
01876 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL
01877 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL
01878 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)
01879 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20)
01880 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)
01882
01883 #define _CMU_STATUS_RESETVALUE 0x00000403UL
01884 #define _CMU_STATUS_MASK 0x00007FFFUL
01885 #define CMU_STATUS_HFRCOENS (0x1UL << 0)
01886 #define _CMU_STATUS_HFRCOENS_SHIFT 0
01887 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL
01888 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL
01889 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0)
01890 #define CMU_STATUS_HFRCORDY (0x1UL << 1)
01891 #define _CMU_STATUS_HFRCORDY_SHIFT 1
01892 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL
01893 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL
01894 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1)
01895 #define CMU_STATUS_HFXOENS (0x1UL << 2)
01896 #define _CMU_STATUS_HFXOENS_SHIFT 2
01897 #define _CMU_STATUS_HFXOENS_MASK 0x4UL
01898 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL
01899 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2)
01900 #define CMU_STATUS_HFXORDY (0x1UL << 3)
01901 #define _CMU_STATUS_HFXORDY_SHIFT 3
01902 #define _CMU_STATUS_HFXORDY_MASK 0x8UL
01903 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL
01904 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3)
01905 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4)
01906 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4
01907 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL
01908 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL
01909 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4)
01910 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5)
01911 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5
01912 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL
01913 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL
01914 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5)
01915 #define CMU_STATUS_LFRCOENS (0x1UL << 6)
01916 #define _CMU_STATUS_LFRCOENS_SHIFT 6
01917 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL
01918 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL
01919 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6)
01920 #define CMU_STATUS_LFRCORDY (0x1UL << 7)
01921 #define _CMU_STATUS_LFRCORDY_SHIFT 7
01922 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL
01923 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL
01924 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7)
01925 #define CMU_STATUS_LFXOENS (0x1UL << 8)
01926 #define _CMU_STATUS_LFXOENS_SHIFT 8
01927 #define _CMU_STATUS_LFXOENS_MASK 0x100UL
01928 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL
01929 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8)
01930 #define CMU_STATUS_LFXORDY (0x1UL << 9)
01931 #define _CMU_STATUS_LFXORDY_SHIFT 9
01932 #define _CMU_STATUS_LFXORDY_MASK 0x200UL
01933 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL
01934 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9)
01935 #define CMU_STATUS_HFRCOSEL (0x1UL << 10)
01936 #define _CMU_STATUS_HFRCOSEL_SHIFT 10
01937 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL
01938 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL
01939 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)
01940 #define CMU_STATUS_HFXOSEL (0x1UL << 11)
01941 #define _CMU_STATUS_HFXOSEL_SHIFT 11
01942 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL
01943 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL
01944 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11)
01945 #define CMU_STATUS_LFRCOSEL (0x1UL << 12)
01946 #define _CMU_STATUS_LFRCOSEL_SHIFT 12
01947 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL
01948 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL
01949 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)
01950 #define CMU_STATUS_LFXOSEL (0x1UL << 13)
01951 #define _CMU_STATUS_LFXOSEL_SHIFT 13
01952 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL
01953 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL
01954 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13)
01955 #define CMU_STATUS_CALBSY (0x1UL << 14)
01956 #define _CMU_STATUS_CALBSY_SHIFT 14
01957 #define _CMU_STATUS_CALBSY_MASK 0x4000UL
01958 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL
01959 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14)
01961
01962 #define _CMU_IF_RESETVALUE 0x00000001UL
01963 #define _CMU_IF_MASK 0x0000007FUL
01964 #define CMU_IF_HFRCORDY (0x1UL << 0)
01965 #define _CMU_IF_HFRCORDY_SHIFT 0
01966 #define _CMU_IF_HFRCORDY_MASK 0x1UL
01967 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL
01968 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0)
01969 #define CMU_IF_HFXORDY (0x1UL << 1)
01970 #define _CMU_IF_HFXORDY_SHIFT 1
01971 #define _CMU_IF_HFXORDY_MASK 0x2UL
01972 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL
01973 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1)
01974 #define CMU_IF_LFRCORDY (0x1UL << 2)
01975 #define _CMU_IF_LFRCORDY_SHIFT 2
01976 #define _CMU_IF_LFRCORDY_MASK 0x4UL
01977 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL
01978 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2)
01979 #define CMU_IF_LFXORDY (0x1UL << 3)
01980 #define _CMU_IF_LFXORDY_SHIFT 3
01981 #define _CMU_IF_LFXORDY_MASK 0x8UL
01982 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL
01983 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3)
01984 #define CMU_IF_AUXHFRCORDY (0x1UL << 4)
01985 #define _CMU_IF_AUXHFRCORDY_SHIFT 4
01986 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL
01987 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL
01988 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4)
01989 #define CMU_IF_CALRDY (0x1UL << 5)
01990 #define _CMU_IF_CALRDY_SHIFT 5
01991 #define _CMU_IF_CALRDY_MASK 0x20UL
01992 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL
01993 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5)
01994 #define CMU_IF_CALOF (0x1UL << 6)
01995 #define _CMU_IF_CALOF_SHIFT 6
01996 #define _CMU_IF_CALOF_MASK 0x40UL
01997 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL
01998 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6)
02000
02001 #define _CMU_IFS_RESETVALUE 0x00000000UL
02002 #define _CMU_IFS_MASK 0x0000007FUL
02003 #define CMU_IFS_HFRCORDY (0x1UL << 0)
02004 #define _CMU_IFS_HFRCORDY_SHIFT 0
02005 #define _CMU_IFS_HFRCORDY_MASK 0x1UL
02006 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL
02007 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0)
02008 #define CMU_IFS_HFXORDY (0x1UL << 1)
02009 #define _CMU_IFS_HFXORDY_SHIFT 1
02010 #define _CMU_IFS_HFXORDY_MASK 0x2UL
02011 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL
02012 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1)
02013 #define CMU_IFS_LFRCORDY (0x1UL << 2)
02014 #define _CMU_IFS_LFRCORDY_SHIFT 2
02015 #define _CMU_IFS_LFRCORDY_MASK 0x4UL
02016 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL
02017 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2)
02018 #define CMU_IFS_LFXORDY (0x1UL << 3)
02019 #define _CMU_IFS_LFXORDY_SHIFT 3
02020 #define _CMU_IFS_LFXORDY_MASK 0x8UL
02021 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL
02022 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3)
02023 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4)
02024 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4
02025 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL
02026 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL
02027 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4)
02028 #define CMU_IFS_CALRDY (0x1UL << 5)
02029 #define _CMU_IFS_CALRDY_SHIFT 5
02030 #define _CMU_IFS_CALRDY_MASK 0x20UL
02031 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL
02032 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5)
02033 #define CMU_IFS_CALOF (0x1UL << 6)
02034 #define _CMU_IFS_CALOF_SHIFT 6
02035 #define _CMU_IFS_CALOF_MASK 0x40UL
02036 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL
02037 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6)
02039
02040 #define _CMU_IFC_RESETVALUE 0x00000000UL
02041 #define _CMU_IFC_MASK 0x0000007FUL
02042 #define CMU_IFC_HFRCORDY (0x1UL << 0)
02043 #define _CMU_IFC_HFRCORDY_SHIFT 0
02044 #define _CMU_IFC_HFRCORDY_MASK 0x1UL
02045 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL
02046 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0)
02047 #define CMU_IFC_HFXORDY (0x1UL << 1)
02048 #define _CMU_IFC_HFXORDY_SHIFT 1
02049 #define _CMU_IFC_HFXORDY_MASK 0x2UL
02050 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL
02051 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1)
02052 #define CMU_IFC_LFRCORDY (0x1UL << 2)
02053 #define _CMU_IFC_LFRCORDY_SHIFT 2
02054 #define _CMU_IFC_LFRCORDY_MASK 0x4UL
02055 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL
02056 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2)
02057 #define CMU_IFC_LFXORDY (0x1UL << 3)
02058 #define _CMU_IFC_LFXORDY_SHIFT 3
02059 #define _CMU_IFC_LFXORDY_MASK 0x8UL
02060 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL
02061 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3)
02062 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4)
02063 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4
02064 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL
02065 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL
02066 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4)
02067 #define CMU_IFC_CALRDY (0x1UL << 5)
02068 #define _CMU_IFC_CALRDY_SHIFT 5
02069 #define _CMU_IFC_CALRDY_MASK 0x20UL
02070 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL
02071 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5)
02072 #define CMU_IFC_CALOF (0x1UL << 6)
02073 #define _CMU_IFC_CALOF_SHIFT 6
02074 #define _CMU_IFC_CALOF_MASK 0x40UL
02075 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL
02076 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6)
02078
02079 #define _CMU_IEN_RESETVALUE 0x00000000UL
02080 #define _CMU_IEN_MASK 0x0000007FUL
02081 #define CMU_IEN_HFRCORDY (0x1UL << 0)
02082 #define _CMU_IEN_HFRCORDY_SHIFT 0
02083 #define _CMU_IEN_HFRCORDY_MASK 0x1UL
02084 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL
02085 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0)
02086 #define CMU_IEN_HFXORDY (0x1UL << 1)
02087 #define _CMU_IEN_HFXORDY_SHIFT 1
02088 #define _CMU_IEN_HFXORDY_MASK 0x2UL
02089 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL
02090 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1)
02091 #define CMU_IEN_LFRCORDY (0x1UL << 2)
02092 #define _CMU_IEN_LFRCORDY_SHIFT 2
02093 #define _CMU_IEN_LFRCORDY_MASK 0x4UL
02094 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL
02095 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2)
02096 #define CMU_IEN_LFXORDY (0x1UL << 3)
02097 #define _CMU_IEN_LFXORDY_SHIFT 3
02098 #define _CMU_IEN_LFXORDY_MASK 0x8UL
02099 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL
02100 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3)
02101 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4)
02102 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4
02103 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL
02104 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL
02105 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4)
02106 #define CMU_IEN_CALRDY (0x1UL << 5)
02107 #define _CMU_IEN_CALRDY_SHIFT 5
02108 #define _CMU_IEN_CALRDY_MASK 0x20UL
02109 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL
02110 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5)
02111 #define CMU_IEN_CALOF (0x1UL << 6)
02112 #define _CMU_IEN_CALOF_SHIFT 6
02113 #define _CMU_IEN_CALOF_MASK 0x40UL
02114 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL
02115 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6)
02117
02118 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL
02119 #define _CMU_HFCORECLKEN0_MASK 0x00000006UL
02120 #define CMU_HFCORECLKEN0_DMA (0x1UL << 1)
02121 #define _CMU_HFCORECLKEN0_DMA_SHIFT 1
02122 #define _CMU_HFCORECLKEN0_DMA_MASK 0x2UL
02123 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL
02124 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1)
02125 #define CMU_HFCORECLKEN0_LE (0x1UL << 2)
02126 #define _CMU_HFCORECLKEN0_LE_SHIFT 2
02127 #define _CMU_HFCORECLKEN0_LE_MASK 0x4UL
02128 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL
02129 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)
02131
02132 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL
02133 #define _CMU_HFPERCLKEN0_MASK 0x000009FBUL
02134 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 0)
02135 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 0
02136 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x1UL
02137 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL
02138 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 0)
02139 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 1)
02140 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 1
02141 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x2UL
02142 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL
02143 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 1)
02144 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 3)
02145 #define _CMU_HFPERCLKEN0_USART1_SHIFT 3
02146 #define _CMU_HFPERCLKEN0_USART1_MASK 0x8UL
02147 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL
02148 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3)
02149 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 4)
02150 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 4
02151 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x10UL
02152 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL
02153 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 4)
02154 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 5)
02155 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 5
02156 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x20UL
02157 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL
02158 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 5)
02159 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 6)
02160 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 6
02161 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x40UL
02162 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL
02163 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 6)
02164 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 7)
02165 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 7
02166 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x80UL
02167 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL
02168 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 7)
02169 #define CMU_HFPERCLKEN0_PRS (0x1UL << 8)
02170 #define _CMU_HFPERCLKEN0_PRS_SHIFT 8
02171 #define _CMU_HFPERCLKEN0_PRS_MASK 0x100UL
02172 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL
02173 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 8)
02174 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11)
02175 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11
02176 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL
02177 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL
02178 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)
02180
02181 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL
02182 #define _CMU_SYNCBUSY_MASK 0x00000055UL
02183 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0)
02184 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0
02185 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL
02186 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL
02187 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0)
02188 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2)
02189 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2
02190 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL
02191 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL
02192 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2)
02193 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4)
02194 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4
02195 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL
02196 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL
02197 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4)
02198 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6)
02199 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6
02200 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL
02201 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL
02202 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6)
02204
02205 #define _CMU_FREEZE_RESETVALUE 0x00000000UL
02206 #define _CMU_FREEZE_MASK 0x00000001UL
02207 #define CMU_FREEZE_REGFREEZE (0x1UL << 0)
02208 #define _CMU_FREEZE_REGFREEZE_SHIFT 0
02209 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL
02210 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL
02211 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL
02212 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL
02213 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0)
02214 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0)
02215 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0)
02217
02218 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL
02219 #define _CMU_LFACLKEN0_MASK 0x00000007UL
02220 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0)
02221 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0
02222 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL
02223 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL
02224 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0)
02225 #define CMU_LFACLKEN0_RTC (0x1UL << 1)
02226 #define _CMU_LFACLKEN0_RTC_SHIFT 1
02227 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL
02228 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL
02229 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1)
02230 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2)
02231 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2
02232 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL
02233 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL
02234 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2)
02236
02237 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL
02238 #define _CMU_LFBCLKEN0_MASK 0x00000001UL
02239 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0)
02240 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0
02241 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL
02242 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL
02243 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0)
02245
02246 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL
02247 #define _CMU_LFAPRESC0_MASK 0x00000FF3UL
02248 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0
02249 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL
02250 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL
02251 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL
02252 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL
02253 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL
02254 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0)
02255 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0)
02256 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0)
02257 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0)
02258 #define _CMU_LFAPRESC0_RTC_SHIFT 4
02259 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL
02260 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL
02261 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL
02262 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL
02263 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL
02264 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL
02265 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL
02266 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL
02267 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL
02268 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL
02269 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL
02270 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL
02271 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL
02272 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL
02273 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL
02274 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL
02275 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL
02276 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4)
02277 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4)
02278 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4)
02279 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4)
02280 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4)
02281 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4)
02282 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4)
02283 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4)
02284 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4)
02285 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4)
02286 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4)
02287 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4)
02288 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4)
02289 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4)
02290 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4)
02291 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4)
02292 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8
02293 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL
02294 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL
02295 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL
02296 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL
02297 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL
02298 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL
02299 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL
02300 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL
02301 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL
02302 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL
02303 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL
02304 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL
02305 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL
02306 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL
02307 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL
02308 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL
02309 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL
02310 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8)
02311 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8)
02312 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8)
02313 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8)
02314 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8)
02315 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8)
02316 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8)
02317 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8)
02318 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8)
02319 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8)
02320 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8)
02321 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8)
02322 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8)
02323 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8)
02324 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8)
02325 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8)
02327
02328 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL
02329 #define _CMU_LFBPRESC0_MASK 0x00000003UL
02330 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0
02331 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL
02332 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL
02333 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL
02334 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL
02335 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL
02336 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0)
02337 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0)
02338 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0)
02339 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0)
02341
02342 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL
02343 #define _CMU_PCNTCTRL_MASK 0x00000003UL
02344 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0)
02345 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0
02346 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL
02347 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL
02348 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)
02349 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1)
02350 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1
02351 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL
02352 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL
02353 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL
02354 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL
02355 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1)
02356 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)
02357 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1)
02359
02360 #define _CMU_ROUTE_RESETVALUE 0x00000000UL
02361 #define _CMU_ROUTE_MASK 0x0000001FUL
02362 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0)
02363 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0
02364 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL
02365 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL
02366 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0)
02367 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1)
02368 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1
02369 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL
02370 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL
02371 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1)
02372 #define _CMU_ROUTE_LOCATION_SHIFT 2
02373 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL
02374 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL
02375 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL
02376 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL
02377 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL
02378 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2)
02379 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2)
02380 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2)
02381 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2)
02383
02384 #define _CMU_LOCK_RESETVALUE 0x00000000UL
02385 #define _CMU_LOCK_MASK 0x0000FFFFUL
02386 #define _CMU_LOCK_LOCKKEY_SHIFT 0
02387 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL
02388 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL
02389 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL
02390 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL
02391 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL
02392 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL
02393 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0)
02394 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0)
02395 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0)
02396 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0)
02397 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0)
02403
02408
02409 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL
02410 #define _PRS_SWPULSE_MASK 0x000000FFUL
02411 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0)
02412 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0
02413 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL
02414 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL
02415 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0)
02416 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1)
02417 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1
02418 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL
02419 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL
02420 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1)
02421 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2)
02422 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2
02423 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL
02424 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL
02425 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2)
02426 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3)
02427 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3
02428 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL
02429 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL
02430 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3)
02431 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4)
02432 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4
02433 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL
02434 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL
02435 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4)
02436 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5)
02437 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5
02438 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL
02439 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL
02440 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5)
02441 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6)
02442 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6
02443 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL
02444 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL
02445 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6)
02446 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7)
02447 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7
02448 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL
02449 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL
02450 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7)
02452
02453 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL
02454 #define _PRS_SWLEVEL_MASK 0x000000FFUL
02455 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0)
02456 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0
02457 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL
02458 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL
02459 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0)
02460 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1)
02461 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1
02462 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL
02463 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL
02464 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1)
02465 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2)
02466 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2
02467 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL
02468 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL
02469 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2)
02470 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3)
02471 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3
02472 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL
02473 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL
02474 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3)
02475 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4)
02476 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4
02477 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL
02478 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL
02479 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4)
02480 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5)
02481 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5
02482 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL
02483 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL
02484 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5)
02485 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6)
02486 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6
02487 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL
02488 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL
02489 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6)
02490 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7)
02491 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7
02492 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL
02493 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL
02494 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7)
02496
02497 #define _PRS_ROUTE_RESETVALUE 0x00000000UL
02498 #define _PRS_ROUTE_MASK 0x0000070FUL
02499 #define PRS_ROUTE_CH0PEN (0x1UL << 0)
02500 #define _PRS_ROUTE_CH0PEN_SHIFT 0
02501 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL
02502 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL
02503 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0)
02504 #define PRS_ROUTE_CH1PEN (0x1UL << 1)
02505 #define _PRS_ROUTE_CH1PEN_SHIFT 1
02506 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL
02507 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL
02508 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1)
02509 #define PRS_ROUTE_CH2PEN (0x1UL << 2)
02510 #define _PRS_ROUTE_CH2PEN_SHIFT 2
02511 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL
02512 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL
02513 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2)
02514 #define PRS_ROUTE_CH3PEN (0x1UL << 3)
02515 #define _PRS_ROUTE_CH3PEN_SHIFT 3
02516 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL
02517 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL
02518 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3)
02519 #define _PRS_ROUTE_LOCATION_SHIFT 8
02520 #define _PRS_ROUTE_LOCATION_MASK 0x700UL
02521 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL
02522 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL
02523 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL
02524 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8)
02525 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8)
02526 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8)
02528
02529 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL
02530 #define _PRS_CH_CTRL_MASK 0x133F0007UL
02531 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0
02532 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL
02533 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL
02534 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL
02535 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL
02536 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL
02537 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL
02538 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL
02539 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL
02540 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL
02541 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL
02542 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL
02543 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL
02544 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL
02545 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL
02546 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL
02547 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL
02548 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL
02549 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL
02550 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL
02551 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL
02552 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL
02553 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL
02554 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL
02555 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL
02556 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL
02557 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL
02558 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL
02559 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL
02560 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL
02561 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL
02562 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL
02563 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL
02564 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL
02565 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL
02566 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL
02567 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL
02568 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL
02569 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL
02570 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL
02571 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL
02572 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL
02573 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL
02574 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL
02575 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL
02576 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL
02577 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL
02578 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL
02579 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL
02580 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL
02581 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL
02582 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL
02583 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL
02584 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL
02585 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL
02586 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL
02587 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL
02588 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)
02589 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)
02590 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0)
02591 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)
02592 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)
02593 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)
02594 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)
02595 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)
02596 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0)
02597 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0)
02598 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0)
02599 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0)
02600 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)
02601 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)
02602 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)
02603 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)
02604 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)
02605 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)
02606 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0)
02607 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0)
02608 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0)
02609 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0)
02610 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
02611 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
02612 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
02613 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)
02614 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)
02615 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)
02616 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0)
02617 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0)
02618 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0)
02619 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
02620 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
02621 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)
02622 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)
02623 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0)
02624 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0)
02625 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
02626 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
02627 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)
02628 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)
02629 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0)
02630 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0)
02631 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)
02632 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)
02633 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0)
02634 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0)
02635 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)
02636 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)
02637 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0)
02638 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0)
02639 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)
02640 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)
02641 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0)
02642 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0)
02643 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16
02644 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
02645 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL
02646 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL
02647 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL
02648 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL
02649 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL
02650 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL
02651 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL
02652 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL
02653 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL
02654 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL
02655 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL
02656 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL
02657 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL
02658 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL
02659 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16)
02660 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)
02661 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)
02662 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16)
02663 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)
02664 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)
02665 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)
02666 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16)
02667 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)
02668 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)
02669 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16)
02670 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16)
02671 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16)
02672 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16)
02673 #define _PRS_CH_CTRL_EDSEL_SHIFT 24
02674 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL
02675 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL
02676 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL
02677 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL
02678 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL
02679 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL
02680 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)
02681 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24)
02682 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)
02683 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)
02684 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)
02685 #define PRS_CH_CTRL_ASYNC (0x1UL << 28)
02686 #define _PRS_CH_CTRL_ASYNC_SHIFT 28
02687 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL
02688 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL
02689 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)
02695
02699 #define MSC_UNLOCK_CODE 0x1B71
02700 #define EMU_UNLOCK_CODE 0xADE8
02701 #define CMU_UNLOCK_CODE 0x580E
02702 #define TIMER_UNLOCK_CODE 0xCE80
02703 #define GPIO_UNLOCK_CODE 0xA534
02709
02714 #include "efm32tg_af_ports.h"
02715 #include "efm32tg_af_pins.h"
02716
02719
02732 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02733 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02734
02739 #ifdef __cplusplus
02740 }
02741 #endif
02742 #endif