em_msc.h
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00033 #ifndef __SILICON_LABS_EM_MSC_H__
00034 #define __SILICON_LABS_EM_MSC_H__
00035
00036 #include "em_device.h"
00037 #if defined(MSC_COUNT) && (MSC_COUNT > 0)
00038
00039 #include <stdint.h>
00040 #include <stdbool.h>
00041 #include "em_bitband.h"
00042
00043 #ifdef __cplusplus
00044 extern "C" {
00045 #endif
00046
00047
00052
00058
00059
00060
00061
00072 #define MSC_PROGRAM_TIMEOUT 10000000ul
00073
00074
00075
00076
00077
00079 typedef enum
00080 {
00081 mscReturnOk = 0,
00082 mscReturnInvalidAddr = -1,
00083 mscReturnLocked = -2,
00084 mscReturnTimeOut = -3,
00085 mscReturnUnaligned = -4
00086 } MSC_Status_TypeDef;
00087
00088
00089 #if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
00090
00091 typedef enum {
00092 mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU,
00093 mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA,
00094 mscBusStrategyDMAEM1 = MSC_READCTRL_BUSSTRATEGY_DMAEM1,
00095 mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE
00096 } MSC_BusStrategy_Typedef;
00097 #endif
00098
00100
00101 #define mscBusStrategy_Typedef MSC_BusStrategy_Typedef
00102 #define msc_Return_TypeDef MSC_Status_TypeDef
00103
00105
00106
00107
00108
00109 void MSC_Init(void);
00110 void MSC_Deinit(void);
00111
00112
00120 __STATIC_INLINE void MSC_IntClear(uint32_t flags)
00121 {
00122 MSC->IFC = flags;
00123 }
00124
00125
00133 __STATIC_INLINE void MSC_IntDisable(uint32_t flags)
00134 {
00135 MSC->IEN &= ~(flags);
00136 }
00137
00138
00139
00152 __STATIC_INLINE void MSC_IntEnable(uint32_t flags)
00153 {
00154 MSC->IEN |= flags;
00155 }
00156
00157
00158
00169 __STATIC_INLINE uint32_t MSC_IntGet(void)
00170 {
00171 return(MSC->IF);
00172 }
00173
00174
00175
00189 __STATIC_INLINE uint32_t MSC_IntGetEnabled(void)
00190 {
00191 uint32_t ien;
00192
00193 ien = MSC->IEN;
00194 return MSC->IF & ien;
00195 }
00196
00197
00198
00206 __STATIC_INLINE void MSC_IntSet(uint32_t flags)
00207 {
00208 MSC->IFS = flags;
00209 }
00210
00211
00212 #if defined( MSC_IF_CHOF ) && defined( MSC_IF_CMOF )
00213
00220 __STATIC_INLINE void MSC_StartCacheMeasurement(void)
00221 {
00222
00223 MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF;
00224
00225
00226 #if defined( _MSC_CACHECMD_MASK )
00227 MSC->CACHECMD = MSC_CACHECMD_STARTPC;
00228 #else
00229 MSC->CMD = MSC_CMD_STARTPC;
00230 #endif
00231 }
00232
00233
00234
00281 __STATIC_INLINE int32_t MSC_GetCacheMeasurement(void)
00282 {
00283 int32_t total;
00284
00285 #if defined( _MSC_CACHECMD_MASK )
00286 MSC->CACHECMD = MSC_CACHECMD_STOPPC;
00287 #else
00288 MSC->CMD = MSC_CMD_STOPPC;
00289 #endif
00290
00291
00292 if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
00293 return -2;
00294
00295
00296
00297
00298 total = MSC->CACHEHITS;
00299 total += MSC->CACHEMISSES;
00300
00301
00302 if (total == 0)
00303 return -1;
00304
00305 return (MSC->CACHEHITS * 100) / total;
00306 }
00307
00308
00309
00313 __STATIC_INLINE void MSC_FlushCache(void)
00314 {
00315 #if defined( _MSC_CACHECMD_MASK )
00316 MSC->CACHECMD = MSC_CACHECMD_INVCACHE;
00317 #else
00318 MSC->CMD = MSC_CMD_INVCACHE;
00319 #endif
00320 }
00321
00322
00323
00329 __STATIC_INLINE void MSC_EnableCache(bool enable)
00330 {
00331 BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, ~enable);
00332 }
00333
00334
00335 #if defined( MSC_READCTRL_ICCDIS )
00336
00342 __STATIC_INLINE void MSC_EnableCacheIRQs(bool enable)
00343 {
00344 BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, ~enable);
00345 }
00346 #endif
00347
00348
00349
00355 __STATIC_INLINE void MSC_EnableAutoCacheFlush(bool enable)
00356 {
00357 BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, ~enable);
00358 }
00359 #endif
00360
00361
00362 #if defined( _MSC_READCTRL_BUSSTRATEGY_MASK )
00363
00369 __STATIC_INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode)
00370 {
00371 MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK)) | mode;
00372 }
00373 #endif
00374
00375
00376 #ifdef __CC_ARM
00377 MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes);
00378 #if !defined( _EFM32_GECKO_FAMILY )
00379 MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes);
00380 #endif
00381 MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress);
00382
00383 #if defined( _MSC_MASSLOCK_MASK )
00384 MSC_Status_TypeDef MSC_MassErase(void);
00385 #endif
00386 #endif
00387
00388 #ifdef __ICCARM__
00389 __ramfunc MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes);
00390 #if !defined( _EFM32_GECKO_FAMILY )
00391 __ramfunc MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes);
00392 #endif
00393 __ramfunc MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress);
00394
00395 #if defined( _MSC_MASSLOCK_MASK )
00396 __ramfunc MSC_Status_TypeDef MSC_MassErase(void);
00397 #endif
00398 #endif
00399
00400 #ifdef __GNUC__
00401 #ifdef __CROSSWORKS_ARM
00402 MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".fast")));
00403 #if !defined( _EFM32_GECKO_FAMILY )
00404 MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".fast")));
00405 #endif
00406 MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".fast")));
00407
00408 #if defined( _MSC_MASSLOCK_MASK )
00409 MSC_Status_TypeDef MSC_MassErase(void) __attribute__ ((section(".fast")));
00410 #endif
00411
00412 #else
00413 MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".ram")));
00414 #if !defined( _EFM32_GECKO_FAMILY )
00415 MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) __attribute__ ((section(".ram")));
00416 #endif
00417 MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".ram")));
00418
00419 #if defined( _MSC_MASSLOCK_MASK )
00420 MSC_Status_TypeDef MSC_MassErase(void) __attribute__ ((section(".ram")));
00421 #endif
00422
00423 #endif
00424 #endif
00425
00429 #ifdef __cplusplus
00430 }
00431 #endif
00432
00433 #endif
00434 #endif