00001
00034 #ifndef __SILICON_LABS_EM_CMU_H_
00035 #define __SILICON_LABS_EM_CMU_H_
00036
00037 #include "em_device.h"
00038 #if defined( CMU_PRESENT )
00039
00040 #include <stdbool.h>
00041 #include "em_bitband.h"
00042
00043 #ifdef __cplusplus
00044 extern "C" {
00045 #endif
00046
00047
00052
00059
00060 #define CMU_NOSEL_REG 0
00061 #define CMU_HFCLKSEL_REG 1
00062 #define CMU_LFACLKSEL_REG 2
00063 #define CMU_LFBCLKSEL_REG 3
00064 #define CMU_DBGCLKSEL_REG 4
00065 #if defined( _CMU_CMD_USBCCLKSEL_MASK )
00066 #define CMU_USBCCLKSEL_REG 5
00067 #endif
00068 #if defined( _CMU_LFCLKSEL_LFC_MASK )
00069 #define CMU_LFCCLKSEL_REG 6
00070 #endif
00071
00072 #define CMU_SEL_REG_POS 0
00073 #define CMU_SEL_REG_MASK 0xf
00074
00075
00076 #define CMU_NODIV_REG 0
00077 #define CMU_HFPERCLKDIV_REG 1
00078 #define CMU_HFCORECLKDIV_REG 2
00079 #define CMU_LFAPRESC0_REG 3
00080 #define CMU_LFBPRESC0_REG 4
00081 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00082 #define CMU_HFCLKDIV_REG 5
00083 #endif
00084 #define CMU_DIV_REG_POS 4
00085 #define CMU_DIV_REG_MASK 0xf
00086
00087
00088 #define CMU_NO_EN_REG 0
00089 #define CMU_HFPERCLKDIV_EN_REG 1
00090 #define CMU_HFPERCLKEN0_EN_REG 2
00091 #define CMU_HFCORECLKEN0_EN_REG 3
00092 #define CMU_LFACLKEN0_EN_REG 4
00093 #define CMU_LFBCLKEN0_EN_REG 5
00094 #define CMU_PCNT_EN_REG 6
00095 #if defined( _CMU_LFCCLKEN0_MASK )
00096 #define CMU_LFCCLKEN0_EN_REG 7
00097 #endif
00098
00099 #define CMU_EN_REG_POS 8
00100 #define CMU_EN_REG_MASK 0xf
00101
00102
00103 #define CMU_EN_BIT_POS 12
00104 #define CMU_EN_BIT_MASK 0x1f
00105
00106
00107 #define CMU_HF_CLK_BRANCH 0
00108 #define CMU_HFPER_CLK_BRANCH 1
00109 #define CMU_HFCORE_CLK_BRANCH 2
00110 #define CMU_LFA_CLK_BRANCH 3
00111 #define CMU_RTC_CLK_BRANCH 4
00112 #define CMU_LETIMER_CLK_BRANCH 5
00113 #define CMU_LCDPRE_CLK_BRANCH 6
00114 #define CMU_LCD_CLK_BRANCH 7
00115 #define CMU_LESENSE_CLK_BRANCH 8
00116 #define CMU_LFB_CLK_BRANCH 9
00117 #define CMU_LEUART0_CLK_BRANCH 10
00118 #define CMU_LEUART1_CLK_BRANCH 11
00119 #define CMU_DBG_CLK_BRANCH 12
00120 #define CMU_AUX_CLK_BRANCH 13
00121 #define CMU_USBC_CLK_BRANCH 14
00122 #define CMU_LFC_CLK_BRANCH 15
00123 #define CMU_USBLE_CLK_BRANCH 16
00124
00125 #define CMU_CLK_BRANCH_POS 17
00126 #define CMU_CLK_BRANCH_MASK 0x1f
00127
00130
00131
00132
00133
00135 #define cmuClkDiv_1 1
00136 #define cmuClkDiv_2 2
00137 #define cmuClkDiv_4 4
00138 #define cmuClkDiv_8 8
00139 #define cmuClkDiv_16 16
00140 #define cmuClkDiv_32 32
00141 #define cmuClkDiv_64 64
00142 #define cmuClkDiv_128 128
00143 #define cmuClkDiv_256 256
00144 #define cmuClkDiv_512 512
00145 #define cmuClkDiv_1024 1024
00146 #define cmuClkDiv_2048 2048
00147 #define cmuClkDiv_4096 4096
00148 #define cmuClkDiv_8192 8192
00149 #define cmuClkDiv_16384 16384
00150 #define cmuClkDiv_32768 32768
00153 typedef uint32_t CMU_ClkDiv_TypeDef;
00154
00156 typedef enum
00157 {
00159 cmuHFRCOBand_1MHz = _CMU_HFRCOCTRL_BAND_1MHZ,
00161 cmuHFRCOBand_7MHz = _CMU_HFRCOCTRL_BAND_7MHZ,
00163 cmuHFRCOBand_11MHz = _CMU_HFRCOCTRL_BAND_11MHZ,
00165 cmuHFRCOBand_14MHz = _CMU_HFRCOCTRL_BAND_14MHZ,
00167 cmuHFRCOBand_21MHz = _CMU_HFRCOCTRL_BAND_21MHZ,
00168 #if defined( _CMU_HFRCOCTRL_BAND_28MHZ )
00169
00170 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ
00171 #endif
00172 } CMU_HFRCOBand_TypeDef;
00173
00174
00175 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
00176
00177 typedef enum
00178 {
00180 cmuAUXHFRCOBand_1MHz = _CMU_AUXHFRCOCTRL_BAND_1MHZ,
00182 cmuAUXHFRCOBand_7MHz = _CMU_AUXHFRCOCTRL_BAND_7MHZ,
00184 cmuAUXHFRCOBand_11MHz = _CMU_AUXHFRCOCTRL_BAND_11MHZ,
00186 cmuAUXHFRCOBand_14MHz = _CMU_AUXHFRCOCTRL_BAND_14MHZ,
00188 cmuAUXHFRCOBand_21MHz = _CMU_AUXHFRCOCTRL_BAND_21MHZ,
00189 #if defined( _CMU_AUXHFRCOCTRL_BAND_28MHZ )
00190
00191 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ
00192 #endif
00193 } CMU_AUXHFRCOBand_TypeDef;
00194 #endif
00195
00196 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
00197
00198 typedef enum
00199 {
00201 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
00203 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
00204 } CMU_USHFRCOBand_TypeDef;
00205 #endif
00206
00207
00209 typedef enum
00210 {
00211
00212
00213
00214
00216 #if defined( _CMU_CTRL_HFCLKDIV_MASK )
00217 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) |
00218 (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
00219 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00220 (0 << CMU_EN_BIT_POS) |
00221 (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00222 #else
00223 cmuClock_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00224 (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) |
00225 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00226 (0 << CMU_EN_BIT_POS) |
00227 (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00228 #endif
00229
00231 cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00232 (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) |
00233 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00234 (0 << CMU_EN_BIT_POS) |
00235 (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00236
00238 cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00239 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00240 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00241 (0 << CMU_EN_BIT_POS) |
00242 (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00243
00244
00245
00246
00247
00249 cmuClock_HFPER = (CMU_HFPERCLKDIV_REG << CMU_DIV_REG_POS) |
00250 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00251 (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS) |
00252 (_CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) |
00253 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00254
00255 #if defined(_CMU_HFPERCLKEN0_USART0_MASK)
00257 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00258 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00259 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00260 (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) |
00261 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00262 #endif
00263
00264 #if defined(_CMU_HFPERCLKEN0_USARTRF0_MASK)
00266 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00267 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00268 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00269 (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS) |
00270 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00271 #endif
00272
00273 #if defined(_CMU_HFPERCLKEN0_USART1_MASK)
00275 cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00276 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00277 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00278 (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) |
00279 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00280 #endif
00281
00282 #if defined(_CMU_HFPERCLKEN0_USART2_MASK)
00284 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00285 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00286 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00287 (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) |
00288 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00289 #endif
00290
00291 #if defined(_CMU_HFPERCLKEN0_UART0_MASK)
00293 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00294 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00295 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00296 (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS) |
00297 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00298 #endif
00299
00300 #if defined(_CMU_HFPERCLKEN0_UART1_MASK)
00302 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00303 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00304 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00305 (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS) |
00306 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00307 #endif
00308
00309 #if defined(_CMU_HFPERCLKEN0_TIMER0_MASK)
00311 cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00312 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00313 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00314 (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) |
00315 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00316 #endif
00317
00318 #if defined(_CMU_HFPERCLKEN0_TIMER1_MASK)
00320 cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00321 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00322 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00323 (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) |
00324 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00325 #endif
00326
00327 #if defined(_CMU_HFPERCLKEN0_TIMER2_MASK)
00329 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00330 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00331 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00332 (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS) |
00333 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00334 #endif
00335
00336 #if defined(_CMU_HFPERCLKEN0_TIMER3_MASK)
00338 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00339 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00340 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00341 (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS) |
00342 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00343 #endif
00344
00345 #if defined(_CMU_HFPERCLKEN0_ACMP0_MASK)
00347 cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00348 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00349 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00350 (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) |
00351 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00352 #endif
00353
00354 #if defined(_CMU_HFPERCLKEN0_ACMP1_MASK)
00356 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00357 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00358 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00359 (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) |
00360 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00361 #endif
00362
00363 #if defined(_CMU_HFPERCLKEN0_PRS_MASK)
00365 cmuClock_PRS = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00366 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00367 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00368 (_CMU_HFPERCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) |
00369 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00370 #endif
00371
00372 #if defined(_CMU_HFPERCLKEN0_DAC0_MASK)
00374 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00375 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00376 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00377 (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS) |
00378 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00379 #endif
00380
00381 #if defined(_CMU_HFPERCLKEN0_IDAC0_MASK)
00383 cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00384 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00385 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00386 (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) |
00387 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00388 #endif
00389
00390 #if defined(GPIO_PRESENT)
00392 cmuClock_GPIO = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00393 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00394 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00395 (_CMU_HFPERCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) |
00396 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00397 #endif
00398
00399 #if defined(VCMP_PRESENT)
00401 cmuClock_VCMP = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00402 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00403 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00404 (_CMU_HFPERCLKEN0_VCMP_SHIFT << CMU_EN_BIT_POS) |
00405 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00406 #endif
00407
00408 #if defined(_CMU_HFPERCLKEN0_ADC0_MASK)
00410 cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00411 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00412 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00413 (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) |
00414 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00415 #endif
00416
00417 #if defined(_CMU_HFPERCLKEN0_I2C0_MASK)
00419 cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00420 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00421 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00422 (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) |
00423 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00424 #endif
00425
00426 #if defined(_CMU_HFPERCLKEN0_I2C1_MASK)
00428 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00429 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00430 (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) |
00431 (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) |
00432 (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00433 #endif
00434
00435
00436
00437
00438
00440 cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) |
00441 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00442 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00443 (0 << CMU_EN_BIT_POS) |
00444 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00445
00446 #if defined(AES_PRESENT)
00447
00448 cmuClock_AES = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00449 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00450 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00451 (_CMU_HFCORECLKEN0_AES_SHIFT << CMU_EN_BIT_POS) |
00452 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00453 #endif
00454
00455 #if defined(DMA_PRESENT)
00457 cmuClock_DMA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00458 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00459 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00460 (_CMU_HFCORECLKEN0_DMA_SHIFT << CMU_EN_BIT_POS) |
00461 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00462 #endif
00464 cmuClock_CORELE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00465 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00466 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00467 (_CMU_HFCORECLKEN0_LE_SHIFT << CMU_EN_BIT_POS) |
00468 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00469
00470 #if defined(EBI_PRESENT)
00471
00472 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00473 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00474 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00475 (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS) |
00476 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00477 #endif
00478
00479 #if defined(USB_PRESENT)
00481 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00482 (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS) |
00483 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00484 (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS) |
00485 (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00486
00487 #endif
00488
00489 #if defined(USB_PRESENT)
00491 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00492 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00493 (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS) |
00494 (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS) |
00495 (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00496 #endif
00497
00498
00499
00500
00501
00503 cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00504 (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) |
00505 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00506 (0 << CMU_EN_BIT_POS) |
00507 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00508
00509 #if defined(RTC_PRESENT)
00510
00511 cmuClock_RTC = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00512 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00513 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00514 (_CMU_LFACLKEN0_RTC_SHIFT << CMU_EN_BIT_POS) |
00515 (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00516 #endif
00517
00518 #if defined(_CMU_LFACLKEN0_LETIMER0_MASK)
00520 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00521 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00522 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00523 (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) |
00524 (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00525 #endif
00526
00527 #if defined(_CMU_LFACLKEN0_LCD_MASK)
00529 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00530 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00531 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00532 (0 << CMU_EN_BIT_POS) |
00533 (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00534
00537 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00538 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00539 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00540 (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS) |
00541 (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00542 #endif
00543
00544 #if defined(_CMU_PCNTCTRL_PCNT0CLKEN_MASK)
00545
00546 cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00547 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00548 (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
00549 (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) |
00550 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00551 #endif
00552
00553 #if defined(_CMU_PCNTCTRL_PCNT1CLKEN_MASK)
00555 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00556 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00557 (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
00558 (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS) |
00559 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00560 #endif
00561
00562 #if defined(_CMU_PCNTCTRL_PCNT2CLKEN_MASK)
00564 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00565 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00566 (CMU_PCNT_EN_REG << CMU_EN_REG_POS) |
00567 (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS) |
00568 (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00569 #endif
00570 #if defined(_CMU_LFACLKEN0_LESENSE_MASK)
00572 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) |
00573 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00574 (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) |
00575 (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) |
00576 (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00577 #endif
00578
00579
00580
00581
00582
00584 cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00585 (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) |
00586 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00587 (0 << CMU_EN_BIT_POS) |
00588 (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00589
00590 #if defined(_CMU_LFBCLKEN0_LEUART0_MASK)
00591
00592 cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
00593 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00594 (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
00595 (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) |
00596 (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00597 #endif
00598
00599 #if defined(_CMU_LFBCLKEN0_LEUART1_MASK)
00601 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) |
00602 (CMU_NOSEL_REG << CMU_SEL_REG_POS) |
00603 (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) |
00604 (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS) |
00605 (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00606 #endif
00607
00608
00609
00610
00611
00613 #if defined( _CMU_LFCLKSEL_LFC_MASK )
00614 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00615 (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |
00616 (CMU_NO_EN_REG << CMU_EN_REG_POS) |
00617 (0 << CMU_EN_BIT_POS) |
00618 (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00619 #endif
00620
00621 #if defined(_CMU_LFCCLKEN0_USBLE_MASK)
00623 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS) |
00624 (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS) |
00625 (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS) |
00626 (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS) |
00627 (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
00628 #endif
00629
00630 } CMU_Clock_TypeDef;
00631
00632
00634 typedef enum
00635 {
00636 cmuOsc_LFXO,
00637 cmuOsc_LFRCO,
00638 cmuOsc_HFXO,
00639 cmuOsc_HFRCO,
00640 cmuOsc_AUXHFRCO,
00641 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
00642 cmuOsc_USHFRCO,
00643 #endif
00644 #if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
00645 cmuOsc_ULFRCO
00646 #endif
00647 } CMU_Osc_TypeDef;
00648
00649
00651 typedef enum
00652 {
00653 cmuSelect_Error,
00654 cmuSelect_Disabled,
00655 cmuSelect_LFXO,
00656 cmuSelect_LFRCO,
00657 cmuSelect_HFXO,
00658 cmuSelect_HFRCO,
00659 cmuSelect_CORELEDIV2,
00660 cmuSelect_AUXHFRCO,
00661 cmuSelect_HFCLK,
00662 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
00663 cmuSelect_USHFRCO,
00664 #endif
00665 #if defined( _CMU_CMD_HFCLKSEL_USHFRCODIV2 )
00666 cmuSelect_USHFRCODIV2,
00667 #endif
00668 #if defined( _CMU_LFCLKSEL_LFAE_ULFRCO )
00669 cmuSelect_ULFRCO,
00670 #endif
00671 } CMU_Select_TypeDef;
00672
00673
00674
00675
00676
00677
00678 void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable);
00679 uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock);
00680 CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock);
00681 CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock);
00682 void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div);
00683 void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref);
00684
00685 CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void);
00686 void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band);
00687
00688 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
00689 CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void);
00690 void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band);
00691 #endif
00692
00693 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
00694 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(void);
00695 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
00696 #endif
00697
00698 void CMU_HFRCOStartupDelaySet(uint32_t delay);
00699 uint32_t CMU_HFRCOStartupDelayGet(void);
00700
00701 void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait);
00702 uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc);
00703 void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val);
00704
00705 bool CMU_PCNTClockExternalGet(unsigned int inst);
00706 void CMU_PCNTClockExternalSet(unsigned int inst, bool external);
00707
00708 uint32_t CMU_LCDClkFDIVGet(void);
00709 void CMU_LCDClkFDIVSet(uint32_t div);
00710
00711 void CMU_FreezeEnable(bool enable);
00712 uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference);
00713
00714 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
00715 void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel,
00716 CMU_Osc_TypeDef upSel);
00717 #endif
00718
00719
00726 __STATIC_INLINE void CMU_IntClear(uint32_t flags)
00727 {
00728 CMU->IFC = flags;
00729 }
00730
00731
00732
00739 __STATIC_INLINE void CMU_IntDisable(uint32_t flags)
00740 {
00741 CMU->IEN &= ~flags;
00742 }
00743
00744
00745
00757 __STATIC_INLINE void CMU_IntEnable(uint32_t flags)
00758 {
00759 CMU->IEN |= flags;
00760 }
00761
00762
00763
00770 __STATIC_INLINE uint32_t CMU_IntGet(void)
00771 {
00772 return CMU->IF;
00773 }
00774
00775
00776
00794 __STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
00795 {
00796 uint32_t tmp = 0U;
00797
00798
00799
00800
00801 tmp = CMU->IEN;
00802
00803
00804 return CMU->IF & tmp;
00805 }
00806
00807
00808
00815 __STATIC_INLINE void CMU_IntSet(uint32_t flags)
00816 {
00817 CMU->IFS = flags;
00818 }
00819
00820
00821
00834 __STATIC_INLINE void CMU_Lock(void)
00835 {
00836 CMU->LOCK = CMU_LOCK_LOCKKEY_LOCK;
00837 }
00838
00839
00840
00844 __STATIC_INLINE void CMU_Unlock(void)
00845 {
00846 CMU->LOCK = CMU_LOCK_LOCKKEY_UNLOCK;
00847 }
00848
00849
00850
00863 __STATIC_INLINE uint32_t CMU_CalibrateCountGet(void)
00864 {
00865
00866
00867 #if defined( CMU_CALCTRL_CONT )
00868 if (!(CMU->CALCTRL & CMU_CALCTRL_CONT))
00869 {
00870 while (CMU->STATUS & CMU_STATUS_CALBSY)
00871 ;
00872 }
00873 #else
00874 while (CMU->STATUS & CMU_STATUS_CALBSY)
00875 ;
00876 #endif
00877 return CMU->CALCNT;
00878 }
00879
00880
00881
00888 __STATIC_INLINE void CMU_CalibrateStart(void)
00889 {
00890 CMU->CMD = CMU_CMD_CALSTART;
00891 }
00892
00893
00894 #if defined( CMU_CMD_CALSTOP )
00895
00899 __STATIC_INLINE void CMU_CalibrateStop(void)
00900 {
00901 CMU->CMD = CMU_CMD_CALSTOP;
00902 }
00903 #endif
00904
00905
00906 #if defined( CMU_CALCTRL_CONT )
00907
00914 __STATIC_INLINE void CMU_CalibrateCont(bool enable)
00915 {
00916 BITBAND_Peripheral(&(CMU->CALCTRL), _CMU_CALCTRL_CONT_SHIFT, enable);
00917 }
00918 #endif
00919
00923 #ifdef __cplusplus
00924 }
00925 #endif
00926
00927 #endif
00928 #endif