EFM32 Wonder Gecko Software Documentation  efm32wg-doc-4.2.1
em_emu.h
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1 /***************************************************************************/
33 #ifndef __SILICON_LABS_EM_EMU_H__
34 #define __SILICON_LABS_EM_EMU_H__
35 
36 #include "em_device.h"
37 #if defined( EMU_PRESENT )
38 
39 #include <stdbool.h>
40 #include "em_bus.h"
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 /***************************************************************************/
51 /***************************************************************************/
56 /*******************************************************************************
57  ******************************** ENUMS ************************************
58  ******************************************************************************/
59 
60 #if defined( _EMU_EM4CONF_OSC_MASK )
61 
62 typedef enum
63 {
71 #endif
72 
73 #if defined( _EMU_BUCTRL_PROBE_MASK )
74 
75 typedef enum
76 {
86 #endif
87 
88 #if defined( _EMU_PWRCONF_PWRRES_MASK )
89 
90 typedef enum
91 {
101 #endif
102 
103 #if defined( BU_PRESENT )
104 
105 typedef enum
106 {
118 #endif
119 
121 typedef enum
122 {
128 
129 #if defined( _EMU_EM4CTRL_EM4STATE_MASK )
130 
131 typedef enum
132 {
134  emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
136  emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,
137 } EMU_EM4State_TypeDef;
138 #endif
139 
140 
141 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
142 typedef enum
143 {
145  emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
147  emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
150  emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
151 } EMU_EM4PinRetention_TypeDef;
152 #endif
153 
154 
155 #if defined( _EMU_PWRCFG_MASK )
156 
157 typedef enum
158 {
160  emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD,
161 } EMU_PowerConfig_TypeDef;
162 #endif
163 
164 #if defined( _EMU_DCDCCTRL_MASK )
165 
166 typedef enum
167 {
169  emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
171  emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
172 } EMU_DcdcMode_TypeDef;
173 #endif
174 
175 #if defined( _EMU_PWRCTRL_MASK )
176 
177 typedef enum
178 {
180  emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
182  emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
183 } EMU_DcdcAnaPeripheralPower_TypeDef;
184 #endif
185 
186 #if defined( _EMU_DCDCMISCCTRL_MASK )
187 
188 typedef enum
189 {
190 #if defined( _EFM_DEVICE )
191 
192  emuDcdcLnHighEfficiency = 0,
193 #endif
194 
195  emuDcdcLnFastTransient = EMU_DCDCMISCCTRL_LNFORCECCM,
196 } EMU_DcdcLnTransientMode_TypeDef;
197 #endif
198 
199 #if defined( _EMU_DCDCCTRL_MASK )
200 
201 typedef enum
202 {
204  EMU_DcdcLnRcoBand_3MHz = 0,
206  EMU_DcdcLnRcoBand_4MHz = 1,
208  EMU_DcdcLnRcoBand_5MHz = 2,
210  EMU_DcdcLnRcoBand_6MHz = 3,
212  EMU_DcdcLnRcoBand_7MHz = 4,
214  EMU_DcdcLnRcoBand_8MHz = 5,
216  EMU_DcdcLnRcoBand_9MHz = 6,
218  EMU_DcdcLnRcoBand_10MHz = 7,
219 } EMU_DcdcLnRcoBand_TypeDef;
220 
221 #endif
222 
223 #if defined( EMU_STATUS_VMONRDY )
224 
225 typedef enum
226 {
227  emuVmonChannel_AVDD,
228  emuVmonChannel_ALTAVDD,
229  emuVmonChannel_DVDD,
230  emuVmonChannel_IOVDD0
231 } EMU_VmonChannel_TypeDef;
232 #endif /* EMU_STATUS_VMONRDY */
233 
234 /*******************************************************************************
235  ******************************* STRUCTS ***********************************
236  ******************************************************************************/
237 
239 typedef struct
240 {
243 
245 #define EMU_EM23INIT_DEFAULT \
246 { false } /* Reduced voltage regulator drive strength in EM2 and EM3 */
247 
248 
249 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
250 
251 typedef struct
252 {
253 #if defined( _EMU_EM4CONF_MASK )
254  /* Init parameters for platforms with EMU->EM4CONF register */
255  bool lockConfig;
256  bool buBodRstDis;
258  bool buRtcWakeup;
259  bool vreg;
261 #elif defined( _EMU_EM4CTRL_MASK )
262  /* Init parameters for platforms with EMU->EM4CTRL register */
263  bool retainLfxo;
264  bool retainLfrco;
265  bool retainUlfrco;
266  EMU_EM4State_TypeDef em4State;
267  EMU_EM4PinRetention_TypeDef pinRetentionMode;
268 #endif
270 #endif
271 
273 #if defined( _EMU_EM4CONF_MASK )
274 #define EMU_EM4INIT_DEFAULT \
275 { \
276  false, /* Dont't lock configuration after it's been set */ \
277  false, /* No reset will be asserted due to Brownout when in EM4 */ \
278  emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \
279  true, /* Wake up on EM4 BURTC interrupt */ \
280  true, /* Enable VREG */ \
281 }
282 #endif
283 #if defined( _EMU_EM4CTRL_MASK )
284 #define EMU_EM4INIT_DEFAULT \
285 { \
286  false, /* Retain LFXO configuration upon EM4 entry */ \
287  false, /* Retain LFRCO configuration upon EM4 entry */ \
288  false, /* Retain ULFRCO configuration upon EM4 entry */ \
289  emuEM4Shutoff, /* Use EM4 shutoff state */ \
290  emuPinRetentionDisable, /* Do not retain pins in EM4 */ \
291 }
292 #endif
293 
294 #if defined( BU_PRESENT )
295 
296 typedef struct
297 {
298  /* Backup Power Domain power configuration */
299 
303  bool bodCal;
306 
307  /* Backup Power Domain connection configuration */
313  bool voutMed;
315  bool voutWeak;
321  bool enable;
323 
325 #define EMU_BUPDINIT_DEFAULT \
326 { \
327  emuProbe_Disable, /* Do not enable voltage probe */ \
328  false, /* Disable BOD calibration mode */ \
329  false, /* Disable BU_STAT pin for backup mode indication */ \
330  \
331  emuRes_Res0, /* RES0 series resistance between main and backup power */ \
332  false, /* Don't enable strong switch */ \
333  false, /* Don't enable medium switch */ \
334  false, /* Don't enable weak switch */ \
335  \
336  emuPower_None, /* No connection between main and backup power (inactive mode) */ \
337  emuPower_None, /* No connection between main and backup power (active mode) */ \
338  true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \
339 }
340 #endif
341 
342 #if defined( _EMU_DCDCCTRL_MASK )
343 
344 typedef struct
345 {
346  EMU_PowerConfig_TypeDef powerConfig;
347  EMU_DcdcMode_TypeDef dcdcMode;
348  uint16_t mVout;
349  uint16_t em01LoadCurrent_mA;
353  uint16_t em234LoadCurrent_uA;
357  uint16_t maxCurrent_mA;
360  EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower;
361  EMU_DcdcLnTransientMode_TypeDef lnTransientMode;
363 } EMU_DCDCInit_TypeDef;
364 
366 #if defined( _EFM_DEVICE )
367 #define EMU_DCDCINIT_DEFAULT \
368 { \
369  emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
370  emuDcdcMode_LowNoise, /* Low-niose mode in EM0 (can be set to LowPower on EFM32PG revB0) */ \
371  1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
372  5, /* Nominal EM0 load current of less than 5mA */ \
373  10, /* Nominal EM2/3 load current less than 10uA */ \
374  160, /* Maximum peak current of 160mA */ \
375  emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \
376  emuDcdcLnHighEfficiency, /* Use low-noise high-efficiency mode (ignored if emuDcdcMode_LowPower) */ \
377 }
378 #else /* EFR32 device */
379 #define EMU_DCDCINIT_DEFAULT \
380 { \
381  emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \
382  emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \
383  1800, /* Nominal output voltage for DVDD mode, 1.8V */ \
384  15, /* Nominal EM0 load current of less than 5mA */ \
385  10, /* Nominal EM2/3 load current less than 10uA */ \
386  160, /* Maximum peak current of 160mA */ \
387  emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply (less noise) */ \
388  emuDcdcLnFastTransient, /* Use low-noise fast-transient mode */ \
389 }
390 #endif
391 
392 #endif
393 
394 #if defined( EMU_STATUS_VMONRDY )
395 
396 typedef struct
397 {
398  EMU_VmonChannel_TypeDef channel;
399  int threshold;
400  bool riseWakeup;
401  bool fallWakeup;
402  bool enable;
403  bool retDisable;
404 } EMU_VmonInit_TypeDef;
405 
407 #define EMU_VMONINIT_DEFAULT \
408 { \
409  emuVmonChannel_AVDD, /* AVDD VMON channel */ \
410  3200, /* 3.2 V threshold */ \
411  false, /* Don't wake from EM4H on rising edge */ \
412  false, /* Don't wake from EM4H on falling edge */ \
413  true, /* Enable VMON channel */ \
414  false /* Don't disable IO0 retention */ \
415 }
416 
418 typedef struct
419 {
420  EMU_VmonChannel_TypeDef channel;
421  int riseThreshold;
422  int fallThreshold;
423  bool riseWakeup;
424  bool fallWakeup;
425  bool enable;
426 } EMU_VmonHystInit_TypeDef;
427 
429 #define EMU_VMONHYSTINIT_DEFAULT \
430 { \
431  emuVmonChannel_AVDD, /* AVDD VMON channel */ \
432  3200, /* 3.2 V rise threshold */ \
433  3200, /* 3.2 V fall threshold */ \
434  false, /* Don't wake from EM4H on rising edge */ \
435  false, /* Don't wake from EM4H on falling edge */ \
436  true /* Enable VMON channel */ \
437 }
438 #endif /* EMU_STATUS_VMONRDY */
439 
440 /*******************************************************************************
441  ***************************** PROTOTYPES **********************************
442  ******************************************************************************/
443 
444 /***************************************************************************/
448 __STATIC_INLINE void EMU_EnterEM1(void)
449 {
450  /* Enter sleep mode */
451  SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
452  __WFI();
453 }
454 
455 void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init);
456 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
457 void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init);
458 #endif
459 void EMU_EnterEM2(bool restore);
460 void EMU_EnterEM3(bool restore);
461 void EMU_EnterEM4(void);
462 void EMU_MemPwrDown(uint32_t blocks);
463 void EMU_UpdateOscConfig(void);
464 #if defined( BU_PRESENT )
465 void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit);
466 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
467 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
468 #endif
469 #if defined( _EMU_DCDCCTRL_MASK )
470 bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit);
471 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
472 bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
473 void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent);
474 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
475 bool EMU_DCDCPowerOff(void);
476 #endif
477 #if defined( EMU_STATUS_VMONRDY )
478 void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit);
479 void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit);
480 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
481 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
482 
483 /***************************************************************************/
491 __STATIC_INLINE bool EMU_VmonStatusGet(void)
492 {
493  return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT);
494 }
495 #endif /* EMU_STATUS_VMONRDY */
496 
497 #if defined( _EMU_IF_MASK )
498 /***************************************************************************/
506 __STATIC_INLINE void EMU_IntClear(uint32_t flags)
507 {
508  EMU->IFC = flags;
509 }
510 
511 
512 /***************************************************************************/
520 __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
521 {
522  EMU->IEN &= ~flags;
523 }
524 
525 
526 /***************************************************************************/
539 __STATIC_INLINE void EMU_IntEnable(uint32_t flags)
540 {
541  EMU->IEN |= flags;
542 }
543 
544 
545 /***************************************************************************/
556 __STATIC_INLINE uint32_t EMU_IntGet(void)
557 {
558  return EMU->IF;
559 }
560 
561 
562 /***************************************************************************/
576 __STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
577 {
578  uint32_t ien;
579 
580  ien = EMU->IEN;
581  return EMU->IF & ien;
582 }
583 
584 
585 /***************************************************************************/
593 __STATIC_INLINE void EMU_IntSet(uint32_t flags)
594 {
595  EMU->IFS = flags;
596 }
597 #endif /* _EMU_IF_MASK */
598 
599 
600 #if defined( _EMU_EM4CONF_LOCKCONF_MASK )
601 /***************************************************************************/
607 __STATIC_INLINE void EMU_EM4Lock(bool enable)
608 {
609  BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
610 }
611 #endif
612 
613 #if defined( _EMU_STATUS_BURDY_MASK )
614 /***************************************************************************/
618 __STATIC_INLINE void EMU_BUReady(void)
619 {
620  while(!(EMU->STATUS & EMU_STATUS_BURDY))
621  ;
622 }
623 #endif
624 
625 #if defined( _EMU_ROUTE_BUVINPEN_MASK )
626 /***************************************************************************/
632 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
633 {
634  BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
635 }
636 #endif
637 
638 /***************************************************************************/
650 __STATIC_INLINE void EMU_Lock(void)
651 {
652  EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK;
653 }
654 
655 
656 /***************************************************************************/
660 __STATIC_INLINE void EMU_Unlock(void)
661 {
663 }
664 
665 
666 #if defined( _EMU_PWRLOCK_MASK )
667 /***************************************************************************/
672 __STATIC_INLINE void EMU_PowerLock(void)
673 {
674  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
675 }
676 
677 
678 /***************************************************************************/
683 __STATIC_INLINE void EMU_PowerUnlock(void)
684 {
685  EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
686 }
687 #endif
688 
689 
690 /***************************************************************************/
694 __STATIC_INLINE void EMU_EM2Block(void)
695 {
697 }
698 
699 /***************************************************************************/
703 __STATIC_INLINE void EMU_EM2UnBlock(void)
704 {
706 }
707 
708 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
709 /***************************************************************************/
717 __STATIC_INLINE void EMU_UnlatchPinRetention(void)
718 {
719  EMU->CMD = EMU_CMD_EM4UNLATCH;
720 }
721 #endif
722 
726 #ifdef __cplusplus
727 }
728 #endif
729 
730 #endif /* defined( EMU_PRESENT ) */
731 #endif /* __SILICON_LABS_EM_EMU_H__ */
#define EMU_LOCK_LOCKKEY_UNLOCK
Definition: efm32wg_emu.h:108
__STATIC_INLINE void EMU_BUPinEnable(bool enable)
Disable BU_VIN support.
Definition: em_emu.h:632
void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
Configure Backup Power Domain settings.
Definition: em_emu.c:827
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
Definition: em_emu.c:626
EMU_Power_TypeDef inactivePower
Definition: em_emu.h:317
#define EMU_BUCTRL_PROBE_VDDDREG
Definition: efm32wg_emu.h:185
RAM and peripheral bit-field set and clear API.
__STATIC_INLINE void EMU_IntDisable(uint32_t flags)
Disable one or more EMU interrupts.
Definition: em_emu.h:520
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
Definition: em_emu.c:687
#define EMU_PWRCONF_PWRRES_RES1
Definition: efm32wg_emu.h:216
EMU_EM4Osc_TypeDef osc
Definition: em_emu.h:257
__STATIC_INLINE void EMU_BUReady(void)
Halts until backup power functionality is ready.
Definition: em_emu.h:618
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
Definition: em_emu.c:529
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
Definition: em_emu.c:413
#define EMU_BUCTRL_PROBE_BUIN
Definition: efm32wg_emu.h:186
#define EMU_EM4CONF_OSC_ULFRCO
Definition: efm32wg_emu.h:139
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
EMU_Resistor_TypeDef
Definition: em_emu.h:90
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
Definition: em_bus.h:185
#define EMU_BUCTRL_PROBE_BUOUT
Definition: efm32wg_emu.h:187
#define EMU_BUINACT_PWRCON_NODIODE
Definition: efm32wg_emu.h:242
#define _EMU_EM4CONF_LOCKCONF_SHIFT
Definition: efm32wg_emu.h:148
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
Definition: em_emu.h:660
__STATIC_INLINE void EMU_Lock(void)
Lock the EMU in order to protect its registers against unintended modification.
Definition: em_emu.h:650
#define EMU_PWRCONF_PWRRES_RES3
Definition: efm32wg_emu.h:218
EMU_Resistor_TypeDef resistor
Definition: em_emu.h:309
EMU_BODMode_TypeDef
Definition: em_emu.h:121
EMU_Power_TypeDef
Definition: em_emu.h:105
#define _EMU_ROUTE_BUVINPEN_SHIFT
Definition: efm32wg_emu.h:281
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
Configure Backup Power Domain BOD Threshold value.
Definition: em_emu.c:886
__STATIC_INLINE void EMU_EnterEM1(void)
Enter energy mode 1 (EM1).
Definition: em_emu.h:448
#define EMU_EM4CONF_OSC_LFXO
Definition: efm32wg_emu.h:141
#define EMU_BUINACT_PWRCON_NONE
Definition: efm32wg_emu.h:239
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value)
Configure Backup Power Domain BOD Threshold Range.
Definition: em_emu.c:913
#define EMU
__STATIC_INLINE void EMU_EM2UnBlock(void)
Unblock entering EM2 or higher number energy modes.
Definition: em_emu.h:703
void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
Definition: em_emu.c:753
#define EMU_PWRCONF_PWRRES_RES2
Definition: efm32wg_emu.h:217
__STATIC_INLINE void EMU_IntEnable(uint32_t flags)
Enable one or more EMU interrupts.
Definition: em_emu.h:539
__STATIC_INLINE void EMU_EM4Lock(bool enable)
Enable or disable EM4 lock configuration.
Definition: em_emu.h:607
EMU_Probe_TypeDef
Definition: em_emu.h:75
EMU_Power_TypeDef activePower
Definition: em_emu.h:319
#define EMU_BUINACT_PWRCON_BUMAIN
Definition: efm32wg_emu.h:240
__STATIC_INLINE void EMU_IntClear(uint32_t flags)
Clear one or more pending EMU interrupts.
Definition: em_emu.h:506
EMU_Probe_TypeDef probe
Definition: em_emu.h:301
__STATIC_INLINE uint32_t EMU_IntGet(void)
Get pending EMU interrupt flags.
Definition: em_emu.h:556
#define EMU_BUCTRL_PROBE_DISABLE
Definition: efm32wg_emu.h:184
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
Definition: em_bus.h:146
void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)
Update EMU module with Energy Mode 4 configuration.
Definition: em_emu.c:775
#define EMU_EM4CONF_OSC_LFRCO
Definition: efm32wg_emu.h:140
EMU_EM4Osc_TypeDef
Definition: em_emu.h:62
#define EMU_PWRCONF_PWRRES_RES0
Definition: efm32wg_emu.h:215
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
Definition: em_emu.c:736
__STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
Get enabled and pending EMU interrupt flags. Useful for handling more interrupt sources in the same i...
Definition: em_emu.h:576
#define EMU_STATUS_BURDY
Definition: efm32wg_emu.h:271
#define _EMU_CTRL_EM2BLOCK_SHIFT
Definition: efm32wg_emu.h:85
__STATIC_INLINE void EMU_EM2Block(void)
Block entering EM2 or higher number energy modes.
Definition: em_emu.h:694
__STATIC_INLINE void EMU_IntSet(uint32_t flags)
Set one or more pending EMU interrupts.
Definition: em_emu.h:593
#define EMU_BUINACT_PWRCON_MAINBU
Definition: efm32wg_emu.h:241
#define EMU_LOCK_LOCKKEY_LOCK
Definition: efm32wg_emu.h:105