34 #ifndef EFM32WG995F256_H
35 #define EFM32WG995F256_H
113 #define __MPU_PRESENT 1
114 #define __FPU_PRESENT 1
115 #define __NVIC_PRIO_BITS 3
116 #define __Vendor_SysTickConfig 0
126 #define _EFM32_WONDER_FAMILY 1
128 #define _SILICON_LABS_32B_PLATFORM_1
129 #define _SILICON_LABS_32B_PLATFORM 1
132 #if !defined(EFM32WG995F256)
133 #define EFM32WG995F256 1
137 #define PART_NUMBER "EFM32WG995F256"
140 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
141 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
142 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
143 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
144 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
145 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
146 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
147 #define AES_MEM_BITS ((uint32_t) 0x10UL)
148 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL)
149 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL)
150 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL)
151 #define USBC_MEM_BITS ((uint32_t) 0x18UL)
152 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL)
153 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL)
154 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL)
155 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL)
156 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
157 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
158 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
159 #define PER_MEM_BITS ((uint32_t) 0x20UL)
160 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
161 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
162 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
163 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
164 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
165 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
166 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
167 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
168 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL)
169 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL)
170 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL)
171 #define EBI_MEM_BITS ((uint32_t) 0x30UL)
174 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL)
175 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL)
178 #define FLASH_BASE (0x00000000UL)
179 #define FLASH_SIZE (0x00040000UL)
180 #define FLASH_PAGE_SIZE 2048
181 #define SRAM_BASE (0x20000000UL)
182 #define SRAM_SIZE (0x00008000UL)
183 #define __CM4_REV 0x001
184 #define PRS_CHAN_COUNT 12
185 #define DMA_CHAN_COUNT 12
188 #define AFCHAN_MAX 163
189 #define AFCHANLOC_MAX 7
191 #define AFACHAN_MAX 53
195 #define USART_PRESENT
196 #define USART_COUNT 3
199 #define TIMER_PRESENT
200 #define TIMER_COUNT 4
203 #define LEUART_PRESENT
204 #define LEUART_COUNT 2
205 #define LETIMER_PRESENT
206 #define LETIMER_COUNT 1
233 #define LESENSE_PRESENT
234 #define LESENSE_COUNT 1
237 #define FPUEH_PRESENT
238 #define FPUEH_COUNT 1
247 #define OPAMP_PRESENT
248 #define OPAMP_COUNT 1
253 #define BURTC_PRESENT
254 #define BURTC_COUNT 1
255 #define HFXTAL_PRESENT
256 #define HFXTAL_COUNT 1
257 #define LFXTAL_PRESENT
258 #define LFXTAL_COUNT 1
265 #define BOOTLOADER_PRESENT
266 #define BOOTLOADER_COUNT 1
267 #define ANALOG_PRESENT
268 #define ANALOG_COUNT 1
270 #include "core_cm4.h"
331 #define DMA_BASE (0x400C2000UL)
332 #define AES_BASE (0x400E0000UL)
333 #define USB_BASE (0x400C4000UL)
334 #define MSC_BASE (0x400C0000UL)
335 #define EMU_BASE (0x400C6000UL)
336 #define RMU_BASE (0x400CA000UL)
337 #define CMU_BASE (0x400C8000UL)
338 #define LESENSE_BASE (0x4008C000UL)
339 #define EBI_BASE (0x40008000UL)
340 #define FPUEH_BASE (0x400C1C00UL)
341 #define USART0_BASE (0x4000C000UL)
342 #define USART1_BASE (0x4000C400UL)
343 #define USART2_BASE (0x4000C800UL)
344 #define UART0_BASE (0x4000E000UL)
345 #define UART1_BASE (0x4000E400UL)
346 #define TIMER0_BASE (0x40010000UL)
347 #define TIMER1_BASE (0x40010400UL)
348 #define TIMER2_BASE (0x40010800UL)
349 #define TIMER3_BASE (0x40010C00UL)
350 #define ACMP0_BASE (0x40001000UL)
351 #define ACMP1_BASE (0x40001400UL)
352 #define LEUART0_BASE (0x40084000UL)
353 #define LEUART1_BASE (0x40084400UL)
354 #define RTC_BASE (0x40080000UL)
355 #define LETIMER0_BASE (0x40082000UL)
356 #define PCNT0_BASE (0x40086000UL)
357 #define PCNT1_BASE (0x40086400UL)
358 #define PCNT2_BASE (0x40086800UL)
359 #define I2C0_BASE (0x4000A000UL)
360 #define I2C1_BASE (0x4000A400UL)
361 #define GPIO_BASE (0x40006000UL)
362 #define VCMP_BASE (0x40000000UL)
363 #define PRS_BASE (0x400CC000UL)
364 #define ADC0_BASE (0x40002000UL)
365 #define DAC0_BASE (0x40004000UL)
366 #define LCD_BASE (0x4008A000UL)
367 #define BURTC_BASE (0x40081000UL)
368 #define WDOG_BASE (0x40088000UL)
369 #define ETM_BASE (0xE0041000UL)
370 #define CALIBRATE_BASE (0x0FE08000UL)
371 #define DEVINFO_BASE (0x0FE081B0UL)
372 #define ROMTABLE_BASE (0xE00FFFD0UL)
373 #define LOCKBITS_BASE (0x0FE04000UL)
374 #define USERDATA_BASE (0x0FE00000UL)
383 #define DMA ((DMA_TypeDef *) DMA_BASE)
384 #define AES ((AES_TypeDef *) AES_BASE)
385 #define USB ((USB_TypeDef *) USB_BASE)
386 #define MSC ((MSC_TypeDef *) MSC_BASE)
387 #define EMU ((EMU_TypeDef *) EMU_BASE)
388 #define RMU ((RMU_TypeDef *) RMU_BASE)
389 #define CMU ((CMU_TypeDef *) CMU_BASE)
390 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE)
391 #define EBI ((EBI_TypeDef *) EBI_BASE)
392 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE)
393 #define USART0 ((USART_TypeDef *) USART0_BASE)
394 #define USART1 ((USART_TypeDef *) USART1_BASE)
395 #define USART2 ((USART_TypeDef *) USART2_BASE)
396 #define UART0 ((USART_TypeDef *) UART0_BASE)
397 #define UART1 ((USART_TypeDef *) UART1_BASE)
398 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
399 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
400 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE)
401 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE)
402 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
403 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE)
404 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
405 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE)
406 #define RTC ((RTC_TypeDef *) RTC_BASE)
407 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE)
408 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
409 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE)
410 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE)
411 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
412 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
413 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
414 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
415 #define PRS ((PRS_TypeDef *) PRS_BASE)
416 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
417 #define DAC0 ((DAC_TypeDef *) DAC0_BASE)
418 #define LCD ((LCD_TypeDef *) LCD_BASE)
419 #define BURTC ((BURTC_TypeDef *) BURTC_BASE)
420 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
421 #define ETM ((ETM_TypeDef *) ETM_BASE)
422 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
423 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
424 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
433 #include "efm32wg_prs_signals.h"
442 #define MSC_UNLOCK_CODE 0x1B71
443 #define EMU_UNLOCK_CODE 0xADE8
444 #define CMU_UNLOCK_CODE 0x580E
445 #define TIMER_UNLOCK_CODE 0xCE80
446 #define GPIO_UNLOCK_CODE 0xA534
447 #define BURTC_UNLOCK_CODE 0xAEE8
458 #include "efm32wg_af_ports.h"
476 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
477 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
EFM32WG_DAC register and bit field definitions.
EFM32WG_VCMP register and bit field definitions.
EFM32WG_ETM register and bit field definitions.
EFM32WG_BURTC register and bit field definitions.
EFM32WG_USB_HC register and bit field definitions.
EFM32WG_LESENSE register and bit field definitions.
EFM32WG_TIMER_CC register and bit field definitions.
EFM32WG_RMU register and bit field definitions.
EFM32WG_USB_DOEP register and bit field definitions.
EFM32WG_USB register and bit field definitions.
EFM32WG_PCNT register and bit field definitions.
EFM32WG_WDOG register and bit field definitions.
EFM32WG_LESENSE_CH register and bit field definitions.
EFM32WG_PRS register and bit field definitions.
EFM32WG_EMU register and bit field definitions.
EFM32WG_GPIO_P register and bit field definitions.
EFM32WG_RTC register and bit field definitions.
EFM32WG_CMU register and bit field definitions.
EFM32WG_LESENSE_ST register and bit field definitions.
EFM32WG_USB_DIEP register and bit field definitions.
EFM32WG_DMACTRL register and bit field definitions.
EFM32WG_BURTC_RET register and bit field definitions.
EFM32WG_CALIBRATE register and bit field definitions.
EFM32WG_TIMER register and bit field definitions.
EFM32WG_LESENSE_BUF register and bit field definitions.
EFM32WG_GPIO register and bit field definitions.
EFM32WG_LEUART register and bit field definitions.
EFM32WG_LCD register and bit field definitions.
EFM32WG_ACMP register and bit field definitions.
EFM32WG_USART register and bit field definitions.
EFM32WG_I2C register and bit field definitions.
EFM32WG_FPUEH register and bit field definitions.
EFM32WG_DMA_DESCRIPTOR register and bit field definitions.
EFM32WG_EBI register and bit field definitions.
EFM32WG_ADC register and bit field definitions.
EFM32WG_ROMTABLE register and bit field definitions.
EFM32WG_DMAREQ register and bit field definitions.
EFM32WG_DMA_CH register and bit field definitions.
EFM32WG_DMA register and bit field definitions.
EFM32WG_DEVINFO register and bit field definitions.
CMSIS Cortex-M4 System Layer for EFM32WG devices.
EFM32WG_UART register and bit field definitions.
EFM32WG_AES register and bit field definitions.
EFM32WG_LETIMER register and bit field definitions.
EFM32WG_PRS_CH register and bit field definitions.
EFM32WG_AF_PINS register and bit field definitions.
EFM32WG_MSC register and bit field definitions.