33 #ifndef __SILICON_LABS_EM_EMU_H__
34 #define __SILICON_LABS_EM_EMU_H__
37 #if defined( EMU_PRESENT )
60 #if defined( _EMU_EM4CONF_OSC_MASK )
73 #if defined( _EMU_BUCTRL_PROBE_MASK )
88 #if defined( _EMU_PWRCONF_PWRRES_MASK )
103 #if defined( BU_PRESENT )
129 #if defined( _EMU_EM4CTRL_EM4STATE_MASK )
134 emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H,
136 emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S,
137 } EMU_EM4State_TypeDef;
141 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
145 emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
147 emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
150 emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
151 } EMU_EM4PinRetention_TypeDef;
155 #if defined( _EMU_PWRCFG_MASK )
160 emuPowerConfig_DcdcToDvdd = EMU_PWRCFG_PWRCFG_DCDCTODVDD,
161 } EMU_PowerConfig_TypeDef;
164 #if defined( _EMU_DCDCCTRL_MASK )
169 emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
171 emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
172 } EMU_DcdcMode_TypeDef;
175 #if defined( _EMU_PWRCTRL_MASK )
180 emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
182 emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
183 } EMU_DcdcAnaPeripheralPower_TypeDef;
186 #if defined( _EMU_DCDCMISCCTRL_MASK )
190 #if defined( _EFM_DEVICE )
192 emuDcdcLnHighEfficiency = 0,
195 emuDcdcLnFastTransient = EMU_DCDCMISCCTRL_LNFORCECCM,
196 } EMU_DcdcLnTransientMode_TypeDef;
199 #if defined( _EMU_DCDCCTRL_MASK )
204 EMU_DcdcLnRcoBand_3MHz = 0,
206 EMU_DcdcLnRcoBand_4MHz = 1,
208 EMU_DcdcLnRcoBand_5MHz = 2,
210 EMU_DcdcLnRcoBand_6MHz = 3,
212 EMU_DcdcLnRcoBand_7MHz = 4,
214 EMU_DcdcLnRcoBand_8MHz = 5,
216 EMU_DcdcLnRcoBand_9MHz = 6,
218 EMU_DcdcLnRcoBand_10MHz = 7,
219 } EMU_DcdcLnRcoBand_TypeDef;
223 #if defined( EMU_STATUS_VMONRDY )
228 emuVmonChannel_ALTAVDD,
230 emuVmonChannel_IOVDD0
231 } EMU_VmonChannel_TypeDef;
245 #define EMU_EM23INIT_DEFAULT \
249 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
253 #if defined( _EMU_EM4CONF_MASK )
261 #elif defined( _EMU_EM4CTRL_MASK )
266 EMU_EM4State_TypeDef em4State;
267 EMU_EM4PinRetention_TypeDef pinRetentionMode;
273 #if defined( _EMU_EM4CONF_MASK )
274 #define EMU_EM4INIT_DEFAULT \
283 #if defined( _EMU_EM4CTRL_MASK )
284 #define EMU_EM4INIT_DEFAULT \
290 emuPinRetentionDisable, \
294 #if defined( BU_PRESENT )
325 #define EMU_BUPDINIT_DEFAULT \
342 #if defined( _EMU_DCDCCTRL_MASK )
346 EMU_PowerConfig_TypeDef powerConfig;
347 EMU_DcdcMode_TypeDef dcdcMode;
349 uint16_t em01LoadCurrent_mA;
353 uint16_t em234LoadCurrent_uA;
357 uint16_t maxCurrent_mA;
360 EMU_DcdcAnaPeripheralPower_TypeDef anaPeripheralPower;
361 EMU_DcdcLnTransientMode_TypeDef lnTransientMode;
363 } EMU_DCDCInit_TypeDef;
366 #if defined( _EFM_DEVICE )
367 #define EMU_DCDCINIT_DEFAULT \
369 emuPowerConfig_DcdcToDvdd, \
370 emuDcdcMode_LowNoise, \
375 emuDcdcAnaPeripheralPower_DCDC, \
376 emuDcdcLnHighEfficiency, \
379 #define EMU_DCDCINIT_DEFAULT \
381 emuPowerConfig_DcdcToDvdd, \
382 emuDcdcMode_LowNoise, \
387 emuDcdcAnaPeripheralPower_AVDD, \
388 emuDcdcLnFastTransient, \
394 #if defined( EMU_STATUS_VMONRDY )
398 EMU_VmonChannel_TypeDef channel;
404 } EMU_VmonInit_TypeDef;
407 #define EMU_VMONINIT_DEFAULT \
409 emuVmonChannel_AVDD, \
420 EMU_VmonChannel_TypeDef channel;
426 } EMU_VmonHystInit_TypeDef;
429 #define EMU_VMONHYSTINIT_DEFAULT \
431 emuVmonChannel_AVDD, \
451 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
456 #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK )
464 #if defined( BU_PRESENT )
469 #if defined( _EMU_DCDCCTRL_MASK )
470 bool EMU_DCDCInit(EMU_DCDCInit_TypeDef *dcdcInit);
471 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
472 bool EMU_DCDCOutputVoltageSet(uint32_t mV,
bool setLpVoltage,
bool setLnVoltage);
473 void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent);
474 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
475 bool EMU_DCDCPowerOff(
void);
477 #if defined( EMU_STATUS_VMONRDY )
478 void EMU_VmonInit(EMU_VmonInit_TypeDef *vmonInit);
479 void EMU_VmonHystInit(EMU_VmonHystInit_TypeDef *vmonInit);
480 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel,
bool enable);
481 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
491 __STATIC_INLINE
bool EMU_VmonStatusGet(
void)
497 #if defined( _EMU_IF_MASK )
581 return EMU->IF & ien;
600 #if defined( _EMU_EM4CONF_LOCKCONF_MASK )
613 #if defined( _EMU_STATUS_BURDY_MASK )
625 #if defined( _EMU_ROUTE_BUVINPEN_MASK )
666 #if defined( _EMU_PWRLOCK_MASK )
672 __STATIC_INLINE
void EMU_PowerLock(
void)
674 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
683 __STATIC_INLINE
void EMU_PowerUnlock(
void)
685 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
708 #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK )
717 __STATIC_INLINE
void EMU_UnlatchPinRetention(
void)
719 EMU->CMD = EMU_CMD_EM4UNLATCH;
#define EMU_LOCK_LOCKKEY_UNLOCK
__STATIC_INLINE void EMU_BUPinEnable(bool enable)
Disable BU_VIN support.
void EMU_BUPDInit(EMU_BUPDInit_TypeDef *bupdInit)
Configure Backup Power Domain settings.
void EMU_EnterEM4(void)
Enter energy mode 4 (EM4).
EMU_Power_TypeDef inactivePower
#define EMU_BUCTRL_PROBE_VDDDREG
RAM and peripheral bit-field set and clear API.
__STATIC_INLINE void EMU_IntDisable(uint32_t flags)
Disable one or more EMU interrupts.
void EMU_MemPwrDown(uint32_t blocks)
Power down memory block.
#define EMU_PWRCONF_PWRRES_RES1
__STATIC_INLINE void EMU_BUReady(void)
Halts until backup power functionality is ready.
void EMU_EnterEM3(bool restore)
Enter energy mode 3 (EM3).
void EMU_EnterEM2(bool restore)
Enter energy mode 2 (EM2).
#define EMU_BUCTRL_PROBE_BUIN
#define EMU_EM4CONF_OSC_ULFRCO
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
__STATIC_INLINE unsigned int BUS_RegBitRead(volatile const uint32_t *addr, unsigned int bit)
Perform a single-bit read operation on a peripheral register.
#define EMU_BUCTRL_PROBE_BUOUT
#define EMU_BUINACT_PWRCON_NODIODE
#define _EMU_EM4CONF_LOCKCONF_SHIFT
__STATIC_INLINE void EMU_Unlock(void)
Unlock the EMU so that writing to locked registers again is possible.
__STATIC_INLINE void EMU_Lock(void)
Lock the EMU in order to protect its registers against unintended modification.
#define EMU_PWRCONF_PWRRES_RES3
EMU_Resistor_TypeDef resistor
#define _EMU_ROUTE_BUVINPEN_SHIFT
void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value)
Configure Backup Power Domain BOD Threshold value.
__STATIC_INLINE void EMU_EnterEM1(void)
Enter energy mode 1 (EM1).
#define EMU_EM4CONF_OSC_LFXO
#define EMU_BUINACT_PWRCON_NONE
void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value)
Configure Backup Power Domain BOD Threshold Range.
__STATIC_INLINE void EMU_EM2UnBlock(void)
Unblock entering EM2 or higher number energy modes.
void EMU_EM23Init(EMU_EM23Init_TypeDef *em23Init)
Update EMU module with Energy Mode 2 and 3 configuration.
#define EMU_PWRCONF_PWRRES_RES2
__STATIC_INLINE void EMU_IntEnable(uint32_t flags)
Enable one or more EMU interrupts.
__STATIC_INLINE void EMU_EM4Lock(bool enable)
Enable or disable EM4 lock configuration.
EMU_Power_TypeDef activePower
#define EMU_BUINACT_PWRCON_BUMAIN
__STATIC_INLINE void EMU_IntClear(uint32_t flags)
Clear one or more pending EMU interrupts.
__STATIC_INLINE uint32_t EMU_IntGet(void)
Get pending EMU interrupt flags.
#define EMU_BUCTRL_PROBE_DISABLE
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
void EMU_EM4Init(EMU_EM4Init_TypeDef *em4Init)
Update EMU module with Energy Mode 4 configuration.
#define EMU_EM4CONF_OSC_LFRCO
#define EMU_PWRCONF_PWRRES_RES0
void EMU_UpdateOscConfig(void)
Update EMU module with CMU oscillator selection/enable status.
__STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
Get enabled and pending EMU interrupt flags. Useful for handling more interrupt sources in the same i...
#define _EMU_CTRL_EM2BLOCK_SHIFT
__STATIC_INLINE void EMU_EM2Block(void)
Block entering EM2 or higher number energy modes.
__STATIC_INLINE void EMU_IntSet(uint32_t flags)
Set one or more pending EMU interrupts.
#define EMU_BUINACT_PWRCON_MAINBU
#define EMU_LOCK_LOCKKEY_LOCK