release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32ZG/Include/efm32zg_devinfo.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00036 typedef struct
00037 {
00038   __I uint32_t CAL;          
00039   __I uint32_t ADC0CAL0;     
00040   __I uint32_t ADC0CAL1;     
00041   __I uint32_t ADC0CAL2;     
00042   uint32_t     RESERVED0[2]; 
00043   __I uint32_t IDAC0CAL0;    
00044   uint32_t     RESERVED1[2]; 
00045   __I uint32_t AUXHFRCOCAL0; 
00046   __I uint32_t AUXHFRCOCAL1; 
00047   __I uint32_t HFRCOCAL0;    
00048   __I uint32_t HFRCOCAL1;    
00049   __I uint32_t MEMINFO;      
00050   uint32_t     RESERVED2[2]; 
00051   __I uint32_t UNIQUEL;      
00052   __I uint32_t UNIQUEH;      
00053   __I uint32_t MSIZE;        
00054   __I uint32_t PART;         
00055 } DEVINFO_TypeDef;           
00057 /**************************************************************************/
00061 /* Bit fields for EFM32ZG_DEVINFO */
00062 #define _DEVINFO_CAL_CRC_MASK                      0x0000FFFFUL 
00063 #define _DEVINFO_CAL_CRC_SHIFT                     0            
00064 #define _DEVINFO_CAL_TEMP_MASK                     0x00FF0000UL 
00065 #define _DEVINFO_CAL_TEMP_SHIFT                    16           
00066 #define _DEVINFO_ADC0CAL0_1V25_GAIN_MASK           0x00007F00UL 
00067 #define _DEVINFO_ADC0CAL0_1V25_GAIN_SHIFT          8            
00068 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_MASK         0x0000007FUL 
00069 #define _DEVINFO_ADC0CAL0_1V25_OFFSET_SHIFT        0            
00070 #define _DEVINFO_ADC0CAL0_2V5_GAIN_MASK            0x7F000000UL 
00071 #define _DEVINFO_ADC0CAL0_2V5_GAIN_SHIFT           24           
00072 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_MASK          0x007F0000UL 
00073 #define _DEVINFO_ADC0CAL0_2V5_OFFSET_SHIFT         16           
00074 #define _DEVINFO_ADC0CAL1_VDD_GAIN_MASK            0x00007F00UL 
00075 #define _DEVINFO_ADC0CAL1_VDD_GAIN_SHIFT           8            
00076 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_MASK          0x0000007FUL 
00077 #define _DEVINFO_ADC0CAL1_VDD_OFFSET_SHIFT         0            
00078 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_MASK         0x7F000000UL 
00079 #define _DEVINFO_ADC0CAL1_5VDIFF_GAIN_SHIFT        24           
00080 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_MASK       0x007F0000UL 
00081 #define _DEVINFO_ADC0CAL1_5VDIFF_OFFSET_SHIFT      16           
00082 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_MASK     0x0000007FUL 
00083 #define _DEVINFO_ADC0CAL2_2XVDDVSS_OFFSET_SHIFT    0            
00084 #define _DEVINFO_ADC0CAL2_TEMP1V25_MASK            0xFFF00000UL 
00085 #define _DEVINFO_ADC0CAL2_TEMP1V25_SHIFT           20           
00086 #define _DEVINFO_IDAC0CAL0_RANGE0_MASK             0x000000FFUL 
00087 #define _DEVINFO_IDAC0CAL0_RANGE0_SHIFT            0            
00088 #define _DEVINFO_IDAC0CAL0_RANGE1_MASK             0x0000FF00UL 
00089 #define _DEVINFO_IDAC0CAL0_RANGE1_SHIFT            8            
00090 #define _DEVINFO_IDAC0CAL0_RANGE2_MASK             0x00FF0000UL 
00091 #define _DEVINFO_IDAC0CAL0_RANGE2_SHIFT            16           
00092 #define _DEVINFO_IDAC0CAL0_RANGE3_MASK             0xFF000000UL 
00093 #define _DEVINFO_IDAC0CAL0_RANGE3_SHIFT            24           
00094 #define _DEVINFO_AUXHFRCOCAL0_BAND1_MASK           0x000000FFUL 
00095 #define _DEVINFO_AUXHFRCOCAL0_BAND1_SHIFT          0            
00096 #define _DEVINFO_AUXHFRCOCAL0_BAND7_MASK           0x0000FF00UL 
00097 #define _DEVINFO_AUXHFRCOCAL0_BAND7_SHIFT          8            
00098 #define _DEVINFO_AUXHFRCOCAL0_BAND11_MASK          0x00FF0000UL 
00099 #define _DEVINFO_AUXHFRCOCAL0_BAND11_SHIFT         16           
00100 #define _DEVINFO_AUXHFRCOCAL0_BAND14_MASK          0xFF000000UL 
00101 #define _DEVINFO_AUXHFRCOCAL0_BAND14_SHIFT         24           
00102 #define _DEVINFO_AUXHFRCOCAL1_BAND21_MASK          0x000000FFUL 
00103 #define _DEVINFO_AUXHFRCOCAL1_BAND21_SHIFT         0            
00104 #define _DEVINFO_HFRCOCAL0_BAND1_MASK              0x000000FFUL 
00105 #define _DEVINFO_HFRCOCAL0_BAND1_SHIFT             0            
00106 #define _DEVINFO_HFRCOCAL0_BAND7_MASK              0x0000FF00UL 
00107 #define _DEVINFO_HFRCOCAL0_BAND7_SHIFT             8            
00108 #define _DEVINFO_HFRCOCAL0_BAND11_MASK             0x00FF0000UL 
00109 #define _DEVINFO_HFRCOCAL0_BAND11_SHIFT            16           
00110 #define _DEVINFO_HFRCOCAL0_BAND14_MASK             0xFF000000UL 
00111 #define _DEVINFO_HFRCOCAL0_BAND14_SHIFT            24           
00112 #define _DEVINFO_HFRCOCAL1_BAND21_MASK             0x000000FFUL 
00113 #define _DEVINFO_HFRCOCAL1_BAND21_SHIFT            0            
00114 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_MASK      0xFF000000UL 
00115 #define _DEVINFO_MEMINFO_FLASH_PAGE_SIZE_SHIFT     24           
00116 #define _DEVINFO_UNIQUEL_MASK                      0xFFFFFFFFUL 
00117 #define _DEVINFO_UNIQUEL_SHIFT                     0            
00118 #define _DEVINFO_UNIQUEH_MASK                      0xFFFFFFFFUL 
00119 #define _DEVINFO_UNIQUEH_SHIFT                     0            
00120 #define _DEVINFO_MSIZE_SRAM_MASK                   0xFFFF0000UL 
00121 #define _DEVINFO_MSIZE_SRAM_SHIFT                  16           
00122 #define _DEVINFO_MSIZE_FLASH_MASK                  0x0000FFFFUL 
00123 #define _DEVINFO_MSIZE_FLASH_SHIFT                 0            
00124 #define _DEVINFO_PART_PROD_REV_MASK                0xFF000000UL 
00125 #define _DEVINFO_PART_PROD_REV_SHIFT               24           
00126 #define _DEVINFO_PART_DEVICE_FAMILY_MASK           0x00FF0000UL 
00127 #define _DEVINFO_PART_DEVICE_FAMILY_SHIFT          16           
00128 /* Legacy family #defines */
00129 #define _DEVINFO_PART_DEVICE_FAMILY_G              71           
00130 #define _DEVINFO_PART_DEVICE_FAMILY_GG             72           
00131 #define _DEVINFO_PART_DEVICE_FAMILY_TG             73           
00132 #define _DEVINFO_PART_DEVICE_FAMILY_LG             74           
00133 #define _DEVINFO_PART_DEVICE_FAMILY_WG             75           
00134 #define _DEVINFO_PART_DEVICE_FAMILY_ZG             76           
00135 #define _DEVINFO_PART_DEVICE_FAMILY_HG             77           
00136 /* New style family #defines */
00137 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32G         71           
00138 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32GG        72           
00139 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32TG        73           
00140 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32LG        74           
00141 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32WG        75           
00142 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32ZG        76           
00143 #define _DEVINFO_PART_DEVICE_FAMILY_EFM32HG        77           
00144 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32WG        120          
00145 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32LG        121          
00146 #define _DEVINFO_PART_DEVICE_FAMILY_EZR32HG        122          
00147 #define _DEVINFO_PART_DEVICE_NUMBER_MASK           0x0000FFFFUL 
00148 #define _DEVINFO_PART_DEVICE_NUMBER_SHIFT          0