release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32ZG/Include/efm32zg_cmu.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __IO uint32_t CTRL;         
00040   __IO uint32_t HFCORECLKDIV; 
00041   __IO uint32_t HFPERCLKDIV;  
00042   __IO uint32_t HFRCOCTRL;    
00043   __IO uint32_t LFRCOCTRL;    
00044   __IO uint32_t AUXHFRCOCTRL; 
00045   __IO uint32_t CALCTRL;      
00046   __IO uint32_t CALCNT;       
00047   __IO uint32_t OSCENCMD;     
00048   __IO uint32_t CMD;          
00049   __IO uint32_t LFCLKSEL;     
00050   __I uint32_t  STATUS;       
00051   __I uint32_t  IF;           
00052   __IO uint32_t IFS;          
00053   __IO uint32_t IFC;          
00054   __IO uint32_t IEN;          
00055   __IO uint32_t HFCORECLKEN0; 
00056   __IO uint32_t HFPERCLKEN0;  
00057   uint32_t      RESERVED0[2]; 
00058   __I uint32_t  SYNCBUSY;     
00059   __IO uint32_t FREEZE;       
00060   __IO uint32_t LFACLKEN0;    
00061   uint32_t      RESERVED1[1]; 
00062   __IO uint32_t LFBCLKEN0;    
00064   uint32_t      RESERVED2[1]; 
00065   __IO uint32_t LFAPRESC0;    
00066   uint32_t      RESERVED3[1]; 
00067   __IO uint32_t LFBPRESC0;    
00068   uint32_t      RESERVED4[1]; 
00069   __IO uint32_t PCNTCTRL;     
00071   uint32_t      RESERVED5[1]; 
00072   __IO uint32_t ROUTE;        
00073   __IO uint32_t LOCK;         
00074 } CMU_TypeDef;                
00076 /**************************************************************************/
00081 /* Bit fields for CMU CTRL */
00082 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             
00083 #define _CMU_CTRL_MASK                              0x07FE3EEFUL                             
00084 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        
00085 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    
00086 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                             
00087 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                             
00088 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                             
00089 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                             
00090 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        
00091 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)           
00092 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      
00093 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      
00094 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                        
00095 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                    
00096 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                             
00097 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                             
00098 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                             
00099 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                             
00100 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                             
00101 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       
00102 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       
00103 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       
00104 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       
00105 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      
00106 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                        
00107 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                   
00108 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                             
00109 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      
00110 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                             
00111 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                        
00112 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                   
00113 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                             
00114 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 
00115 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                        
00116 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                  
00117 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                             
00118 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                             
00119 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                             
00120 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                             
00121 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                             
00122 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     
00123 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   
00124 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    
00125 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     
00126 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   
00127 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                       
00128 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                 
00129 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                             
00130 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                             
00131 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                             
00132 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                             
00133 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       
00134 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)          
00135 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     
00136 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     
00137 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                            
00138 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                       
00139 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                 
00140 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                             
00141 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                             
00142 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                             
00143 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      
00144 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      
00145 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     
00146 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                            
00147 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                       
00148 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                
00149 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                             
00150 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     
00151 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                       
00152 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                
00153 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                             
00154 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                             
00155 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                             
00156 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                             
00157 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                             
00158 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    
00159 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   
00160 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  
00161 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    
00162 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  
00163 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                       
00164 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                               
00165 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                             
00166 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                             
00167 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                             
00168 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                             
00169 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                             
00170 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                             
00171 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                             
00172 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                             
00173 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                             
00174 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     
00175 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       
00176 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        
00177 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      
00178 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      
00179 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      
00180 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     
00181 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      
00182 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)    
00183 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                       
00184 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                              
00185 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                             
00186 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                             
00187 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                             
00188 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                             
00189 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                             
00190 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                             
00191 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                             
00192 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                             
00193 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                             
00194 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     
00195 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       
00196 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        
00197 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)       
00198 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)       
00199 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)       
00200 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)      
00201 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)      
00202 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)   
00204 /* Bit fields for CMU HFCORECLKDIV */
00205 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
00206 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
00207 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
00208 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
00209 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
00210 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
00211 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
00212 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
00213 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
00214 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
00215 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
00216 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
00217 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
00218 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
00219 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
00220 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
00221 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
00222 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
00223 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
00224 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
00225 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
00226 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
00227 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
00228 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
00229 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
00230 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
00231 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
00232 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
00233 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
00234 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
00235 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
00236 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
00237 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
00238 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
00239 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
00241 /* Bit fields for CMU HFPERCLKDIV */
00242 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
00243 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
00244 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
00245 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
00246 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
00247 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
00248 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
00249 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
00250 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
00251 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
00252 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
00253 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
00254 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
00255 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
00256 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
00257 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
00258 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
00259 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
00260 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
00261 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
00262 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
00263 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
00264 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
00265 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
00266 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
00267 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
00268 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
00269 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
00270 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
00271 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
00272 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
00274 /* Bit fields for CMU HFRCOCTRL */
00275 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
00276 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
00277 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
00278 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
00279 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
00280 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
00281 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
00282 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
00283 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
00284 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
00285 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
00286 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
00287 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
00288 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
00289 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
00290 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
00291 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
00292 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
00293 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
00294 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
00295 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
00296 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
00297 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
00298 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
00300 /* Bit fields for CMU LFRCOCTRL */
00301 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
00302 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
00303 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
00304 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
00305 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
00306 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
00308 /* Bit fields for CMU AUXHFRCOCTRL */
00309 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
00310 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
00311 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
00312 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
00313 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
00314 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
00315 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
00316 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
00317 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
00318 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
00319 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
00320 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
00321 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
00322 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
00323 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
00324 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
00325 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
00326 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
00327 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
00328 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
00330 /* Bit fields for CMU CALCTRL */
00331 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
00332 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
00333 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
00334 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
00335 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
00336 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
00337 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
00338 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
00339 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
00340 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
00341 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
00342 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
00343 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
00344 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
00345 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
00346 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
00347 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
00348 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
00349 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
00350 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
00351 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
00352 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
00353 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
00354 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
00355 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
00356 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
00357 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
00358 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
00359 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
00360 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
00361 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
00362 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
00363 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
00364 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
00365 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
00366 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
00367 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
00369 /* Bit fields for CMU CALCNT */
00370 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
00371 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
00372 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
00373 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
00374 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
00375 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
00377 /* Bit fields for CMU OSCENCMD */
00378 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
00379 #define _CMU_OSCENCMD_MASK                          0x000003FFUL                             
00380 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
00381 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
00382 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
00383 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
00384 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
00385 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
00386 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
00387 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
00388 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
00389 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
00390 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
00391 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
00392 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
00393 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
00394 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
00395 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
00396 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
00397 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
00398 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
00399 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
00400 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
00401 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
00402 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
00403 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
00404 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
00405 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
00406 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
00407 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
00408 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
00409 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
00410 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
00411 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
00412 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
00413 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
00414 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
00415 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
00416 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
00417 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
00418 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
00419 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
00420 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
00421 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
00422 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
00423 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
00424 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
00425 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
00426 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
00427 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
00428 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
00429 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
00431 /* Bit fields for CMU CMD */
00432 #define _CMU_CMD_RESETVALUE                         0x00000000UL                     
00433 #define _CMU_CMD_MASK                               0x0000001FUL                     
00434 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                
00435 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                            
00436 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                     
00437 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                     
00438 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                     
00439 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                     
00440 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                     
00441 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0) 
00442 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)   
00443 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)    
00444 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)   
00445 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)    
00446 #define CMU_CMD_CALSTART                            (0x1UL << 3)                     
00447 #define _CMU_CMD_CALSTART_SHIFT                     3                                
00448 #define _CMU_CMD_CALSTART_MASK                      0x8UL                            
00449 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                     
00450 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3) 
00451 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                     
00452 #define _CMU_CMD_CALSTOP_SHIFT                      4                                
00453 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                           
00454 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                     
00455 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)  
00457 /* Bit fields for CMU LFCLKSEL */
00458 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             
00459 #define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             
00460 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
00461 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
00462 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
00463 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
00464 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
00465 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
00466 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
00467 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
00468 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
00469 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
00470 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
00471 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
00472 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
00473 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
00474 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
00475 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
00476 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
00477 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
00478 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
00479 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
00480 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
00481 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
00482 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
00483 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
00484 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
00485 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
00486 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
00487 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
00488 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
00489 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
00490 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
00491 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
00492 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
00493 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
00494 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
00495 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
00496 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
00497 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
00498 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
00499 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
00500 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
00501 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
00503 /* Bit fields for CMU STATUS */
00504 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                           
00505 #define _CMU_STATUS_MASK                            0x00007FFFUL                           
00506 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                           
00507 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                      
00508 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                  
00509 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                           
00510 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)    
00511 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                           
00512 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                      
00513 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                  
00514 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                           
00515 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)    
00516 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                           
00517 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                      
00518 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                  
00519 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                           
00520 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)     
00521 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                           
00522 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                      
00523 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                  
00524 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                           
00525 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)     
00526 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                           
00527 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                      
00528 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                 
00529 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                           
00530 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) 
00531 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                           
00532 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                      
00533 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                 
00534 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                           
00535 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) 
00536 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                           
00537 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                      
00538 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                 
00539 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                           
00540 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)    
00541 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                           
00542 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                      
00543 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                 
00544 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                           
00545 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)    
00546 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                           
00547 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                      
00548 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                
00549 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                           
00550 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)     
00551 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                           
00552 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                      
00553 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                
00554 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                           
00555 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)     
00556 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                          
00557 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                     
00558 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                
00559 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                           
00560 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)   
00561 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                          
00562 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                     
00563 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                
00564 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                           
00565 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)    
00566 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                          
00567 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                     
00568 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                               
00569 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                           
00570 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)   
00571 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                          
00572 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                     
00573 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                               
00574 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                           
00575 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)    
00576 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                          
00577 #define _CMU_STATUS_CALBSY_SHIFT                    14                                     
00578 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                               
00579 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                           
00580 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)     
00582 /* Bit fields for CMU IF */
00583 #define _CMU_IF_RESETVALUE                          0x00000001UL                       
00584 #define _CMU_IF_MASK                                0x0000007FUL                       
00585 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                       
00586 #define _CMU_IF_HFRCORDY_SHIFT                      0                                  
00587 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                              
00588 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                       
00589 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)    
00590 #define CMU_IF_HFXORDY                              (0x1UL << 1)                       
00591 #define _CMU_IF_HFXORDY_SHIFT                       1                                  
00592 #define _CMU_IF_HFXORDY_MASK                        0x2UL                              
00593 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                       
00594 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)     
00595 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                       
00596 #define _CMU_IF_LFRCORDY_SHIFT                      2                                  
00597 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                              
00598 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                       
00599 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)    
00600 #define CMU_IF_LFXORDY                              (0x1UL << 3)                       
00601 #define _CMU_IF_LFXORDY_SHIFT                       3                                  
00602 #define _CMU_IF_LFXORDY_MASK                        0x8UL                              
00603 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                       
00604 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)     
00605 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                       
00606 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                  
00607 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                             
00608 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                       
00609 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
00610 #define CMU_IF_CALRDY                               (0x1UL << 5)                       
00611 #define _CMU_IF_CALRDY_SHIFT                        5                                  
00612 #define _CMU_IF_CALRDY_MASK                         0x20UL                             
00613 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                       
00614 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)      
00615 #define CMU_IF_CALOF                                (0x1UL << 6)                       
00616 #define _CMU_IF_CALOF_SHIFT                         6                                  
00617 #define _CMU_IF_CALOF_MASK                          0x40UL                             
00618 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                       
00619 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)       
00621 /* Bit fields for CMU IFS */
00622 #define _CMU_IFS_RESETVALUE                         0x00000000UL                        
00623 #define _CMU_IFS_MASK                               0x0000007FUL                        
00624 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                        
00625 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                   
00626 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                               
00627 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                        
00628 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
00629 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                        
00630 #define _CMU_IFS_HFXORDY_SHIFT                      1                                   
00631 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                               
00632 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                        
00633 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)     
00634 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                        
00635 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                   
00636 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                               
00637 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                        
00638 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
00639 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                        
00640 #define _CMU_IFS_LFXORDY_SHIFT                      3                                   
00641 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                               
00642 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                        
00643 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)     
00644 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                        
00645 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                   
00646 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                              
00647 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                        
00648 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
00649 #define CMU_IFS_CALRDY                              (0x1UL << 5)                        
00650 #define _CMU_IFS_CALRDY_SHIFT                       5                                   
00651 #define _CMU_IFS_CALRDY_MASK                        0x20UL                              
00652 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                        
00653 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)      
00654 #define CMU_IFS_CALOF                               (0x1UL << 6)                        
00655 #define _CMU_IFS_CALOF_SHIFT                        6                                   
00656 #define _CMU_IFS_CALOF_MASK                         0x40UL                              
00657 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                        
00658 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)       
00660 /* Bit fields for CMU IFC */
00661 #define _CMU_IFC_RESETVALUE                         0x00000000UL                        
00662 #define _CMU_IFC_MASK                               0x0000007FUL                        
00663 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                        
00664 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                   
00665 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                               
00666 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                        
00667 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
00668 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                        
00669 #define _CMU_IFC_HFXORDY_SHIFT                      1                                   
00670 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                               
00671 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                        
00672 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)     
00673 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                        
00674 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                   
00675 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                               
00676 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                        
00677 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
00678 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                        
00679 #define _CMU_IFC_LFXORDY_SHIFT                      3                                   
00680 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                               
00681 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                        
00682 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)     
00683 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                        
00684 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                   
00685 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                              
00686 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                        
00687 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
00688 #define CMU_IFC_CALRDY                              (0x1UL << 5)                        
00689 #define _CMU_IFC_CALRDY_SHIFT                       5                                   
00690 #define _CMU_IFC_CALRDY_MASK                        0x20UL                              
00691 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                        
00692 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)      
00693 #define CMU_IFC_CALOF                               (0x1UL << 6)                        
00694 #define _CMU_IFC_CALOF_SHIFT                        6                                   
00695 #define _CMU_IFC_CALOF_MASK                         0x40UL                              
00696 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                        
00697 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)       
00699 /* Bit fields for CMU IEN */
00700 #define _CMU_IEN_RESETVALUE                         0x00000000UL                        
00701 #define _CMU_IEN_MASK                               0x0000007FUL                        
00702 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                        
00703 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                   
00704 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                               
00705 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                        
00706 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
00707 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                        
00708 #define _CMU_IEN_HFXORDY_SHIFT                      1                                   
00709 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                               
00710 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                        
00711 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)     
00712 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                        
00713 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                   
00714 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                               
00715 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                        
00716 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
00717 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                        
00718 #define _CMU_IEN_LFXORDY_SHIFT                      3                                   
00719 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                               
00720 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                        
00721 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)     
00722 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                        
00723 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                   
00724 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                              
00725 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                        
00726 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
00727 #define CMU_IEN_CALRDY                              (0x1UL << 5)                        
00728 #define _CMU_IEN_CALRDY_SHIFT                       5                                   
00729 #define _CMU_IEN_CALRDY_MASK                        0x20UL                              
00730 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                        
00731 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)      
00732 #define CMU_IEN_CALOF                               (0x1UL << 6)                        
00733 #define _CMU_IEN_CALOF_SHIFT                        6                                   
00734 #define _CMU_IEN_CALOF_MASK                         0x40UL                              
00735 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                        
00736 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)       
00738 /* Bit fields for CMU HFCORECLKEN0 */
00739 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                         
00740 #define _CMU_HFCORECLKEN0_MASK                      0x00000007UL                         
00741 #define CMU_HFCORECLKEN0_AES                        (0x1UL << 0)                         
00742 #define _CMU_HFCORECLKEN0_AES_SHIFT                 0                                    
00743 #define _CMU_HFCORECLKEN0_AES_MASK                  0x1UL                                
00744 #define _CMU_HFCORECLKEN0_AES_DEFAULT               0x00000000UL                         
00745 #define CMU_HFCORECLKEN0_AES_DEFAULT                (_CMU_HFCORECLKEN0_AES_DEFAULT << 0) 
00746 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 1)                         
00747 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 1                                    
00748 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x2UL                                
00749 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                         
00750 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) 
00751 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 2)                         
00752 #define _CMU_HFCORECLKEN0_LE_SHIFT                  2                                    
00753 #define _CMU_HFCORECLKEN0_LE_MASK                   0x4UL                                
00754 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                         
00755 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)  
00757 /* Bit fields for CMU HFPERCLKEN0 */
00758 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
00759 #define _CMU_HFPERCLKEN0_MASK                       0x00000DDFUL                           
00760 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 0)                           
00761 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               0                                      
00762 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x1UL                                  
00763 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
00764 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) 
00765 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 1)                           
00766 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               1                                      
00767 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x2UL                                  
00768 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
00769 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) 
00770 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 2)                           
00771 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                2                                      
00772 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x4UL                                  
00773 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
00774 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 2)  
00775 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 3)                           
00776 #define _CMU_HFPERCLKEN0_USART1_SHIFT               3                                      
00777 #define _CMU_HFPERCLKEN0_USART1_MASK                0x8UL                                  
00778 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
00779 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3) 
00780 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 4)                           
00781 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  4                                      
00782 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x10UL                                 
00783 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
00784 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 4)    
00785 #define CMU_HFPERCLKEN0_IDAC0                       (0x1UL << 6)                           
00786 #define _CMU_HFPERCLKEN0_IDAC0_SHIFT                6                                      
00787 #define _CMU_HFPERCLKEN0_IDAC0_MASK                 0x40UL                                 
00788 #define _CMU_HFPERCLKEN0_IDAC0_DEFAULT              0x00000000UL                           
00789 #define CMU_HFPERCLKEN0_IDAC0_DEFAULT               (_CMU_HFPERCLKEN0_IDAC0_DEFAULT << 6)  
00790 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 7)                           
00791 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 7                                      
00792 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x80UL                                 
00793 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
00794 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 7)   
00795 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 8)                           
00796 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 8                                      
00797 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x100UL                                
00798 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
00799 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 8)   
00800 #define CMU_HFPERCLKEN0_ADC0                        (0x1UL << 10)                          
00801 #define _CMU_HFPERCLKEN0_ADC0_SHIFT                 10                                     
00802 #define _CMU_HFPERCLKEN0_ADC0_MASK                  0x400UL                                
00803 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT               0x00000000UL                           
00804 #define CMU_HFPERCLKEN0_ADC0_DEFAULT                (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 10)  
00805 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
00806 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
00807 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
00808 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
00809 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
00811 /* Bit fields for CMU SYNCBUSY */
00812 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
00813 #define _CMU_SYNCBUSY_MASK                          0x00000055UL                           
00814 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
00815 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
00816 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
00817 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
00818 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
00819 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
00820 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
00821 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
00822 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
00823 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
00824 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
00825 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
00826 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
00827 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
00828 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
00829 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
00830 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
00831 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
00832 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
00833 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
00835 /* Bit fields for CMU FREEZE */
00836 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
00837 #define _CMU_FREEZE_MASK                            0x00000001UL                         
00838 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
00839 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
00840 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
00841 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
00842 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
00843 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
00844 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
00845 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
00846 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
00848 /* Bit fields for CMU LFACLKEN0 */
00849 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                      
00850 #define _CMU_LFACLKEN0_MASK                         0x00000001UL                      
00851 #define CMU_LFACLKEN0_RTC                           (0x1UL << 0)                      
00852 #define _CMU_LFACLKEN0_RTC_SHIFT                    0                                 
00853 #define _CMU_LFACLKEN0_RTC_MASK                     0x1UL                             
00854 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                      
00855 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 0) 
00857 /* Bit fields for CMU LFBCLKEN0 */
00858 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
00859 #define _CMU_LFBCLKEN0_MASK                         0x00000001UL                          
00860 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
00861 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
00862 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
00863 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
00864 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
00866 /* Bit fields for CMU LFAPRESC0 */
00867 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                       
00868 #define _CMU_LFAPRESC0_MASK                         0x0000000FUL                       
00869 #define _CMU_LFAPRESC0_RTC_SHIFT                    0                                  
00870 #define _CMU_LFAPRESC0_RTC_MASK                     0xFUL                              
00871 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                       
00872 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                       
00873 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                       
00874 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                       
00875 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                       
00876 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                       
00877 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                       
00878 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                       
00879 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                       
00880 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                       
00881 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                       
00882 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                       
00883 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                       
00884 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                       
00885 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                       
00886 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                       
00887 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 0)     
00888 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 0)     
00889 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 0)     
00890 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 0)     
00891 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 0)    
00892 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 0)    
00893 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 0)    
00894 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 0)   
00895 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 0)   
00896 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 0)   
00897 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 0)  
00898 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 0)  
00899 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 0)  
00900 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 0)  
00901 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 0) 
00902 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 0) 
00904 /* Bit fields for CMU LFBPRESC0 */
00905 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
00906 #define _CMU_LFBPRESC0_MASK                         0x00000003UL                       
00907 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
00908 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
00909 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
00910 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
00911 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
00912 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
00913 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
00914 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
00915 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
00916 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
00918 /* Bit fields for CMU PCNTCTRL */
00919 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
00920 #define _CMU_PCNTCTRL_MASK                          0x00000003UL                             
00921 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
00922 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
00923 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
00924 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
00925 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
00926 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
00927 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
00928 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
00929 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
00930 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
00931 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
00932 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
00933 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
00934 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
00936 /* Bit fields for CMU ROUTE */
00937 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
00938 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
00939 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
00940 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
00941 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
00942 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
00943 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
00944 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
00945 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
00946 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
00947 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
00948 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
00949 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
00950 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
00951 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
00952 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
00953 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
00954 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
00955 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
00956 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
00957 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
00958 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
00960 /* Bit fields for CMU LOCK */
00961 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
00962 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
00963 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
00964 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
00965 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
00966 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
00967 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
00968 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
00969 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
00970 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
00971 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
00972 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
00973 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
00974 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)