release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32ZG/Include/efm32zg110f4.h

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00001 /**************************************************************************/
00034 #ifndef __SILICON_LABS_EFM32ZG110F4_H__
00035 #define __SILICON_LABS_EFM32ZG110F4_H__
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
00055   NonMaskableInt_IRQn = -14,                
00056   HardFault_IRQn      = -13,                
00057   SVCall_IRQn         = -5,                 
00058   PendSV_IRQn         = -2,                 
00059   SysTick_IRQn        = -1,                 
00061 /******  EFM32ZG Peripheral Interrupt Numbers *********************************************/
00062   DMA_IRQn            = 0,  
00063   GPIO_EVEN_IRQn      = 1,  
00064   TIMER0_IRQn         = 2,  
00065   ACMP0_IRQn          = 3,  
00066   ADC0_IRQn           = 4,  
00067   I2C0_IRQn           = 5,  
00068   GPIO_ODD_IRQn       = 6,  
00069   TIMER1_IRQn         = 7,  
00070   USART1_RX_IRQn      = 8,  
00071   USART1_TX_IRQn      = 9,  
00072   LEUART0_IRQn        = 10, 
00073   PCNT0_IRQn          = 11, 
00074   RTC_IRQn            = 12, 
00075   CMU_IRQn            = 13, 
00076   VCMP_IRQn           = 14, 
00077   MSC_IRQn            = 15, 
00078   AES_IRQn            = 16, 
00079 } IRQn_Type;
00080 
00081 /**************************************************************************/
00086 #define __MPU_PRESENT             0 
00087 #define __VTOR_PRESENT            1 
00088 #define __NVIC_PRIO_BITS          2 
00089 #define __Vendor_SysTickConfig    0 
00093 /**************************************************************************/
00099 #define _EFM32_ZERO_FAMILY              1 
00100 #define _EFM_DEVICE                       
00101 #define _SILICON_LABS_32B_PLATFORM_1      
00102 #define _SILICON_LABS_32B_PLATFORM      1 
00104 /* If part number is not defined as compiler option, define it */
00105 #if !defined(EFM32ZG110F4)
00106 #define EFM32ZG110F4    1 
00107 #endif
00108 
00110 #define PART_NUMBER          "EFM32ZG110F4" 
00113 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00114 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00115 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00116 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00117 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00118 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00119 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00120 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00121 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00122 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00123 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00124 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00125 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00126 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00127 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00128 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00129 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00130 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00131 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00132 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00135 #define FLASH_BASE           (0x00000000UL) 
00136 #define FLASH_SIZE           (0x00001000UL) 
00137 #define FLASH_PAGE_SIZE      1024           
00138 #define SRAM_BASE            (0x20000000UL) 
00139 #define SRAM_SIZE            (0x00000800UL) 
00140 #define __CM0PLUS_REV        0x001          
00141 #define PRS_CHAN_COUNT       4              
00142 #define DMA_CHAN_COUNT       4              
00145 #define AFCHAN_MAX           33
00146 #define AFCHANLOC_MAX        7
00147 
00148 #define AFACHAN_MAX          25
00149 
00150 /* Part number capabilities */
00151 
00152 #define TIMER_PRESENT         
00153 #define TIMER_COUNT         2 
00154 #define ACMP_PRESENT          
00155 #define ACMP_COUNT          1 
00156 #define USART_PRESENT         
00157 #define USART_COUNT         1 
00158 #define IDAC_PRESENT          
00159 #define IDAC_COUNT          1 
00160 #define ADC_PRESENT           
00161 #define ADC_COUNT           1 
00162 #define LEUART_PRESENT        
00163 #define LEUART_COUNT        1 
00164 #define PCNT_PRESENT          
00165 #define PCNT_COUNT          1 
00166 #define I2C_PRESENT           
00167 #define I2C_COUNT           1 
00168 #define AES_PRESENT
00169 #define AES_COUNT           1
00170 #define DMA_PRESENT
00171 #define DMA_COUNT           1
00172 #define LE_PRESENT
00173 #define LE_COUNT            1
00174 #define MSC_PRESENT
00175 #define MSC_COUNT           1
00176 #define EMU_PRESENT
00177 #define EMU_COUNT           1
00178 #define RMU_PRESENT
00179 #define RMU_COUNT           1
00180 #define CMU_PRESENT
00181 #define CMU_COUNT           1
00182 #define PRS_PRESENT
00183 #define PRS_COUNT           1
00184 #define GPIO_PRESENT
00185 #define GPIO_COUNT          1
00186 #define VCMP_PRESENT
00187 #define VCMP_COUNT          1
00188 #define RTC_PRESENT
00189 #define RTC_COUNT           1
00190 #define HFXTAL_PRESENT
00191 #define HFXTAL_COUNT        1
00192 #define LFXTAL_PRESENT
00193 #define LFXTAL_COUNT        1
00194 #define WDOG_PRESENT
00195 #define WDOG_COUNT          1
00196 #define DBG_PRESENT
00197 #define DBG_COUNT           1
00198 #define BOOTLOADER_PRESENT
00199 #define BOOTLOADER_COUNT    1
00200 #define ANALOG_PRESENT
00201 #define ANALOG_COUNT        1
00202 
00205 #define ARM_MATH_CM0PLUS
00206 #include "arm_math.h"       /* To get __CLZ definitions etc. */
00207 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
00208 #include "system_efm32zg.h" /* System Header */
00209 
00210 /**************************************************************************/
00216 #include "efm32zg_aes.h"
00217 #include "efm32zg_dma_ch.h"
00218 #include "efm32zg_dma.h"
00219 #include "efm32zg_msc.h"
00220 #include "efm32zg_emu.h"
00221 #include "efm32zg_rmu.h"
00222 #include "efm32zg_cmu.h"
00223 #include "efm32zg_timer_cc.h"
00224 #include "efm32zg_timer.h"
00225 #include "efm32zg_acmp.h"
00226 #include "efm32zg_usart.h"
00227 #include "efm32zg_prs_ch.h"
00228 #include "efm32zg_prs.h"
00229 #include "efm32zg_idac.h"
00230 #include "efm32zg_gpio_p.h"
00231 #include "efm32zg_gpio.h"
00232 #include "efm32zg_vcmp.h"
00233 #include "efm32zg_adc.h"
00234 #include "efm32zg_leuart.h"
00235 #include "efm32zg_pcnt.h"
00236 #include "efm32zg_i2c.h"
00237 #include "efm32zg_rtc.h"
00238 #include "efm32zg_wdog.h"
00239 #include "efm32zg_dma_descriptor.h"
00240 #include "efm32zg_devinfo.h"
00241 #include "efm32zg_romtable.h"
00242 #include "efm32zg_calibrate.h"
00243 
00246 /**************************************************************************/
00251 #define AES_BASE          (0x400E0000UL) 
00252 #define DMA_BASE          (0x400C2000UL) 
00253 #define MSC_BASE          (0x400C0000UL) 
00254 #define EMU_BASE          (0x400C6000UL) 
00255 #define RMU_BASE          (0x400CA000UL) 
00256 #define CMU_BASE          (0x400C8000UL) 
00257 #define TIMER0_BASE       (0x40010000UL) 
00258 #define TIMER1_BASE       (0x40010400UL) 
00259 #define ACMP0_BASE        (0x40001000UL) 
00260 #define USART1_BASE       (0x4000C400UL) 
00261 #define PRS_BASE          (0x400CC000UL) 
00262 #define IDAC0_BASE        (0x40004000UL) 
00263 #define GPIO_BASE         (0x40006000UL) 
00264 #define VCMP_BASE         (0x40000000UL) 
00265 #define ADC0_BASE         (0x40002000UL) 
00266 #define LEUART0_BASE      (0x40084000UL) 
00267 #define PCNT0_BASE        (0x40086000UL) 
00268 #define I2C0_BASE         (0x4000A000UL) 
00269 #define RTC_BASE          (0x40080000UL) 
00270 #define WDOG_BASE         (0x40088000UL) 
00271 #define CALIBRATE_BASE    (0x0FE08000UL) 
00272 #define DEVINFO_BASE      (0x0FE081B0UL) 
00273 #define ROMTABLE_BASE     (0xF00FFFD0UL) 
00274 #define LOCKBITS_BASE     (0x0FE04000UL) 
00275 #define USERDATA_BASE     (0x0FE00000UL) 
00279 /**************************************************************************/
00284 #define AES          ((AES_TypeDef *) AES_BASE)             
00285 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00286 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00287 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00288 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00289 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00290 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00291 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00292 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00293 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00294 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00295 #define IDAC0        ((IDAC_TypeDef *) IDAC0_BASE)          
00296 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00297 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00298 #define ADC0         ((ADC_TypeDef *) ADC0_BASE)            
00299 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00300 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00301 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00302 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00303 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00304 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00305 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00306 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00310 /**************************************************************************/
00315 #include "efm32zg_prs_signals.h"
00316 #include "efm32zg_dmareq.h"
00317 #include "efm32zg_dmactrl.h"
00318 
00319 /**************************************************************************/
00323 #define MSC_UNLOCK_CODE      0x1B71 
00324 #define EMU_UNLOCK_CODE      0xADE8 
00325 #define CMU_UNLOCK_CODE      0x580E 
00326 #define TIMER_UNLOCK_CODE    0xCE80 
00327 #define GPIO_UNLOCK_CODE     0xA534 
00333 /**************************************************************************/
00338 #include "efm32zg_af_ports.h"
00339 #include "efm32zg_af_pins.h"
00340 
00343 /**************************************************************************/
00356 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
00357   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
00358 
00363 #ifdef __cplusplus
00364 }
00365 #endif
00366 #endif /* __SILICON_LABS_EFM32ZG110F4_H__ */