release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32ZG/Include/efm32zg108f8.h

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00001 /**************************************************************************/
00034 #ifndef __SILICON_LABS_EFM32ZG108F8_H__
00035 #define __SILICON_LABS_EFM32ZG108F8_H__
00036 
00037 #ifdef __cplusplus
00038 extern "C" {
00039 #endif
00040 
00041 /**************************************************************************/
00046 /**************************************************************************/
00052 typedef enum IRQn
00053 {
00054 /******  Cortex-M0+ Processor Exceptions Numbers *****************************************/
00055   NonMaskableInt_IRQn = -14,                
00056   HardFault_IRQn      = -13,                
00057   SVCall_IRQn         = -5,                 
00058   PendSV_IRQn         = -2,                 
00059   SysTick_IRQn        = -1,                 
00061 /******  EFM32ZG Peripheral Interrupt Numbers *********************************************/
00062   DMA_IRQn            = 0,  
00063   GPIO_EVEN_IRQn      = 1,  
00064   TIMER0_IRQn         = 2,  
00065   ACMP0_IRQn          = 3,  
00066   I2C0_IRQn           = 5,  
00067   GPIO_ODD_IRQn       = 6,  
00068   TIMER1_IRQn         = 7,  
00069   USART1_RX_IRQn      = 8,  
00070   USART1_TX_IRQn      = 9,  
00071   LEUART0_IRQn        = 10, 
00072   PCNT0_IRQn          = 11, 
00073   RTC_IRQn            = 12, 
00074   CMU_IRQn            = 13, 
00075   VCMP_IRQn           = 14, 
00076   MSC_IRQn            = 15, 
00077 } IRQn_Type;
00078 
00079 /**************************************************************************/
00084 #define __MPU_PRESENT             0 
00085 #define __VTOR_PRESENT            1 
00086 #define __NVIC_PRIO_BITS          2 
00087 #define __Vendor_SysTickConfig    0 
00091 /**************************************************************************/
00097 #define _EFM32_ZERO_FAMILY              1 
00098 #define _EFM_DEVICE                       
00099 #define _SILICON_LABS_32B_PLATFORM_1      
00100 #define _SILICON_LABS_32B_PLATFORM      1 
00102 /* If part number is not defined as compiler option, define it */
00103 #if !defined(EFM32ZG108F8)
00104 #define EFM32ZG108F8    1 
00105 #endif
00106 
00108 #define PART_NUMBER          "EFM32ZG108F8" 
00111 #define FLASH_MEM_BASE       ((uint32_t) 0x0UL)        
00112 #define FLASH_MEM_SIZE       ((uint32_t) 0x10000000UL) 
00113 #define FLASH_MEM_END        ((uint32_t) 0xFFFFFFFUL)  
00114 #define FLASH_MEM_BITS       ((uint32_t) 0x28UL)       
00115 #define AES_MEM_BASE         ((uint32_t) 0x400E0000UL) 
00116 #define AES_MEM_SIZE         ((uint32_t) 0x400UL)      
00117 #define AES_MEM_END          ((uint32_t) 0x400E03FFUL) 
00118 #define AES_MEM_BITS         ((uint32_t) 0x10UL)       
00119 #define PER_MEM_BASE         ((uint32_t) 0x40000000UL) 
00120 #define PER_MEM_SIZE         ((uint32_t) 0xE0000UL)    
00121 #define PER_MEM_END          ((uint32_t) 0x400DFFFFUL) 
00122 #define PER_MEM_BITS         ((uint32_t) 0x20UL)       
00123 #define RAM_MEM_BASE         ((uint32_t) 0x20000000UL) 
00124 #define RAM_MEM_SIZE         ((uint32_t) 0x40000UL)    
00125 #define RAM_MEM_END          ((uint32_t) 0x2003FFFFUL) 
00126 #define RAM_MEM_BITS         ((uint32_t) 0x18UL)       
00127 #define RAM_CODE_MEM_BASE    ((uint32_t) 0x10000000UL) 
00128 #define RAM_CODE_MEM_SIZE    ((uint32_t) 0x20000UL)    
00129 #define RAM_CODE_MEM_END     ((uint32_t) 0x1001FFFFUL) 
00130 #define RAM_CODE_MEM_BITS    ((uint32_t) 0x17UL)       
00133 #define FLASH_BASE           (0x00000000UL) 
00134 #define FLASH_SIZE           (0x00002000UL) 
00135 #define FLASH_PAGE_SIZE      1024           
00136 #define SRAM_BASE            (0x20000000UL) 
00137 #define SRAM_SIZE            (0x00000800UL) 
00138 #define __CM0PLUS_REV        0x001          
00139 #define PRS_CHAN_COUNT       4              
00140 #define DMA_CHAN_COUNT       4              
00143 #define AFCHAN_MAX           33
00144 #define AFCHANLOC_MAX        7
00145 
00146 #define AFACHAN_MAX          25
00147 
00148 /* Part number capabilities */
00149 
00150 #define TIMER_PRESENT         
00151 #define TIMER_COUNT         2 
00152 #define ACMP_PRESENT          
00153 #define ACMP_COUNT          1 
00154 #define USART_PRESENT         
00155 #define USART_COUNT         1 
00156 #define LEUART_PRESENT        
00157 #define LEUART_COUNT        1 
00158 #define PCNT_PRESENT          
00159 #define PCNT_COUNT          1 
00160 #define I2C_PRESENT           
00161 #define I2C_COUNT           1 
00162 #define DMA_PRESENT
00163 #define DMA_COUNT           1
00164 #define LE_PRESENT
00165 #define LE_COUNT            1
00166 #define MSC_PRESENT
00167 #define MSC_COUNT           1
00168 #define EMU_PRESENT
00169 #define EMU_COUNT           1
00170 #define RMU_PRESENT
00171 #define RMU_COUNT           1
00172 #define CMU_PRESENT
00173 #define CMU_COUNT           1
00174 #define PRS_PRESENT
00175 #define PRS_COUNT           1
00176 #define GPIO_PRESENT
00177 #define GPIO_COUNT          1
00178 #define VCMP_PRESENT
00179 #define VCMP_COUNT          1
00180 #define RTC_PRESENT
00181 #define RTC_COUNT           1
00182 #define HFXTAL_PRESENT
00183 #define HFXTAL_COUNT        1
00184 #define LFXTAL_PRESENT
00185 #define LFXTAL_COUNT        1
00186 #define WDOG_PRESENT
00187 #define WDOG_COUNT          1
00188 #define DBG_PRESENT
00189 #define DBG_COUNT           1
00190 #define BOOTLOADER_PRESENT
00191 #define BOOTLOADER_COUNT    1
00192 #define ANALOG_PRESENT
00193 #define ANALOG_COUNT        1
00194 
00197 #define ARM_MATH_CM0PLUS
00198 #include "arm_math.h"       /* To get __CLZ definitions etc. */
00199 #include "core_cm0plus.h"   /* Cortex-M0+ processor and core peripherals */
00200 #include "system_efm32zg.h" /* System Header */
00201 
00202 /**************************************************************************/
00208 #include "efm32zg_dma_ch.h"
00209 
00210 /**************************************************************************/
00215 typedef struct
00216 {
00217   __I uint32_t   STATUS;         
00218   __O uint32_t   CONFIG;         
00219   __IO uint32_t  CTRLBASE;       
00220   __I uint32_t   ALTCTRLBASE;    
00221   __I uint32_t   CHWAITSTATUS;   
00222   __O uint32_t   CHSWREQ;        
00223   __IO uint32_t  CHUSEBURSTS;    
00224   __O uint32_t   CHUSEBURSTC;    
00225   __IO uint32_t  CHREQMASKS;     
00226   __O uint32_t   CHREQMASKC;     
00227   __IO uint32_t  CHENS;          
00228   __O uint32_t   CHENC;          
00229   __IO uint32_t  CHALTS;         
00230   __O uint32_t   CHALTC;         
00231   __IO uint32_t  CHPRIS;         
00232   __O uint32_t   CHPRIC;         
00233   uint32_t       RESERVED0[3];   
00234   __IO uint32_t  ERRORC;         
00236   uint32_t       RESERVED1[880]; 
00237   __I uint32_t   CHREQSTATUS;    
00238   uint32_t       RESERVED2[1];   
00239   __I uint32_t   CHSREQSTATUS;   
00241   uint32_t       RESERVED3[121]; 
00242   __I uint32_t   IF;             
00243   __IO uint32_t  IFS;            
00244   __IO uint32_t  IFC;            
00245   __IO uint32_t  IEN;            
00247   uint32_t       RESERVED4[60];  
00248   DMA_CH_TypeDef CH[4];          
00249 } DMA_TypeDef;                   
00251 #include "efm32zg_msc.h"
00252 #include "efm32zg_emu.h"
00253 #include "efm32zg_rmu.h"
00254 
00255 /**************************************************************************/
00260 typedef struct
00261 {
00262   __IO uint32_t CTRL;         
00263   __IO uint32_t HFCORECLKDIV; 
00264   __IO uint32_t HFPERCLKDIV;  
00265   __IO uint32_t HFRCOCTRL;    
00266   __IO uint32_t LFRCOCTRL;    
00267   __IO uint32_t AUXHFRCOCTRL; 
00268   __IO uint32_t CALCTRL;      
00269   __IO uint32_t CALCNT;       
00270   __IO uint32_t OSCENCMD;     
00271   __IO uint32_t CMD;          
00272   __IO uint32_t LFCLKSEL;     
00273   __I uint32_t  STATUS;       
00274   __I uint32_t  IF;           
00275   __IO uint32_t IFS;          
00276   __IO uint32_t IFC;          
00277   __IO uint32_t IEN;          
00278   __IO uint32_t HFCORECLKEN0; 
00279   __IO uint32_t HFPERCLKEN0;  
00280   uint32_t      RESERVED0[2]; 
00281   __I uint32_t  SYNCBUSY;     
00282   __IO uint32_t FREEZE;       
00283   __IO uint32_t LFACLKEN0;    
00284   uint32_t      RESERVED1[1]; 
00285   __IO uint32_t LFBCLKEN0;    
00287   uint32_t      RESERVED2[1]; 
00288   __IO uint32_t LFAPRESC0;    
00289   uint32_t      RESERVED3[1]; 
00290   __IO uint32_t LFBPRESC0;    
00291   uint32_t      RESERVED4[1]; 
00292   __IO uint32_t PCNTCTRL;     
00294   uint32_t      RESERVED5[1]; 
00295   __IO uint32_t ROUTE;        
00296   __IO uint32_t LOCK;         
00297 } CMU_TypeDef;                
00299 #include "efm32zg_timer_cc.h"
00300 #include "efm32zg_timer.h"
00301 #include "efm32zg_acmp.h"
00302 #include "efm32zg_usart.h"
00303 #include "efm32zg_prs_ch.h"
00304 
00305 /**************************************************************************/
00310 typedef struct
00311 {
00312   __IO uint32_t  SWPULSE;      
00313   __IO uint32_t  SWLEVEL;      
00314   __IO uint32_t  ROUTE;        
00316   uint32_t       RESERVED0[1]; 
00317   PRS_CH_TypeDef CH[4];        
00318 } PRS_TypeDef;                 
00320 #include "efm32zg_gpio_p.h"
00321 #include "efm32zg_gpio.h"
00322 #include "efm32zg_vcmp.h"
00323 #include "efm32zg_leuart.h"
00324 #include "efm32zg_pcnt.h"
00325 #include "efm32zg_i2c.h"
00326 #include "efm32zg_rtc.h"
00327 #include "efm32zg_wdog.h"
00328 #include "efm32zg_dma_descriptor.h"
00329 #include "efm32zg_devinfo.h"
00330 #include "efm32zg_romtable.h"
00331 #include "efm32zg_calibrate.h"
00332 
00335 /**************************************************************************/
00340 #define DMA_BASE          (0x400C2000UL) 
00341 #define MSC_BASE          (0x400C0000UL) 
00342 #define EMU_BASE          (0x400C6000UL) 
00343 #define RMU_BASE          (0x400CA000UL) 
00344 #define CMU_BASE          (0x400C8000UL) 
00345 #define TIMER0_BASE       (0x40010000UL) 
00346 #define TIMER1_BASE       (0x40010400UL) 
00347 #define ACMP0_BASE        (0x40001000UL) 
00348 #define USART1_BASE       (0x4000C400UL) 
00349 #define PRS_BASE          (0x400CC000UL) 
00350 #define GPIO_BASE         (0x40006000UL) 
00351 #define VCMP_BASE         (0x40000000UL) 
00352 #define LEUART0_BASE      (0x40084000UL) 
00353 #define PCNT0_BASE        (0x40086000UL) 
00354 #define I2C0_BASE         (0x4000A000UL) 
00355 #define RTC_BASE          (0x40080000UL) 
00356 #define WDOG_BASE         (0x40088000UL) 
00357 #define CALIBRATE_BASE    (0x0FE08000UL) 
00358 #define DEVINFO_BASE      (0x0FE081B0UL) 
00359 #define ROMTABLE_BASE     (0xF00FFFD0UL) 
00360 #define LOCKBITS_BASE     (0x0FE04000UL) 
00361 #define USERDATA_BASE     (0x0FE00000UL) 
00365 /**************************************************************************/
00370 #define DMA          ((DMA_TypeDef *) DMA_BASE)             
00371 #define MSC          ((MSC_TypeDef *) MSC_BASE)             
00372 #define EMU          ((EMU_TypeDef *) EMU_BASE)             
00373 #define RMU          ((RMU_TypeDef *) RMU_BASE)             
00374 #define CMU          ((CMU_TypeDef *) CMU_BASE)             
00375 #define TIMER0       ((TIMER_TypeDef *) TIMER0_BASE)        
00376 #define TIMER1       ((TIMER_TypeDef *) TIMER1_BASE)        
00377 #define ACMP0        ((ACMP_TypeDef *) ACMP0_BASE)          
00378 #define USART1       ((USART_TypeDef *) USART1_BASE)        
00379 #define PRS          ((PRS_TypeDef *) PRS_BASE)             
00380 #define GPIO         ((GPIO_TypeDef *) GPIO_BASE)           
00381 #define VCMP         ((VCMP_TypeDef *) VCMP_BASE)           
00382 #define LEUART0      ((LEUART_TypeDef *) LEUART0_BASE)      
00383 #define PCNT0        ((PCNT_TypeDef *) PCNT0_BASE)          
00384 #define I2C0         ((I2C_TypeDef *) I2C0_BASE)            
00385 #define RTC          ((RTC_TypeDef *) RTC_BASE)             
00386 #define WDOG         ((WDOG_TypeDef *) WDOG_BASE)           
00387 #define CALIBRATE    ((CALIBRATE_TypeDef *) CALIBRATE_BASE) 
00388 #define DEVINFO      ((DEVINFO_TypeDef *) DEVINFO_BASE)     
00389 #define ROMTABLE     ((ROMTABLE_TypeDef *) ROMTABLE_BASE)   
00393 /**************************************************************************/
00398 /**************************************************************************/
00403 #define PRS_VCMP_OUT          ((1 << 16) + 0)  
00404 #define PRS_ACMP0_OUT         ((2 << 16) + 0)  
00405 #define PRS_USART1_IRTX       ((17 << 16) + 0) 
00406 #define PRS_USART1_TXC        ((17 << 16) + 1) 
00407 #define PRS_USART1_RXDATAV    ((17 << 16) + 2) 
00408 #define PRS_TIMER0_UF         ((28 << 16) + 0) 
00409 #define PRS_TIMER0_OF         ((28 << 16) + 1) 
00410 #define PRS_TIMER0_CC0        ((28 << 16) + 2) 
00411 #define PRS_TIMER0_CC1        ((28 << 16) + 3) 
00412 #define PRS_TIMER0_CC2        ((28 << 16) + 4) 
00413 #define PRS_TIMER1_UF         ((29 << 16) + 0) 
00414 #define PRS_TIMER1_OF         ((29 << 16) + 1) 
00415 #define PRS_TIMER1_CC0        ((29 << 16) + 2) 
00416 #define PRS_TIMER1_CC1        ((29 << 16) + 3) 
00417 #define PRS_TIMER1_CC2        ((29 << 16) + 4) 
00418 #define PRS_RTC_OF            ((40 << 16) + 0) 
00419 #define PRS_RTC_COMP0         ((40 << 16) + 1) 
00420 #define PRS_RTC_COMP1         ((40 << 16) + 2) 
00421 #define PRS_GPIO_PIN0         ((48 << 16) + 0) 
00422 #define PRS_GPIO_PIN1         ((48 << 16) + 1) 
00423 #define PRS_GPIO_PIN2         ((48 << 16) + 2) 
00424 #define PRS_GPIO_PIN3         ((48 << 16) + 3) 
00425 #define PRS_GPIO_PIN4         ((48 << 16) + 4) 
00426 #define PRS_GPIO_PIN5         ((48 << 16) + 5) 
00427 #define PRS_GPIO_PIN6         ((48 << 16) + 6) 
00428 #define PRS_GPIO_PIN7         ((48 << 16) + 7) 
00429 #define PRS_GPIO_PIN8         ((49 << 16) + 0) 
00430 #define PRS_GPIO_PIN9         ((49 << 16) + 1) 
00431 #define PRS_GPIO_PIN10        ((49 << 16) + 2) 
00432 #define PRS_GPIO_PIN11        ((49 << 16) + 3) 
00433 #define PRS_GPIO_PIN12        ((49 << 16) + 4) 
00434 #define PRS_GPIO_PIN13        ((49 << 16) + 5) 
00435 #define PRS_GPIO_PIN14        ((49 << 16) + 6) 
00436 #define PRS_GPIO_PIN15        ((49 << 16) + 7) 
00437 #define PRS_PCNT0_TCC         ((54 << 16) + 0) 
00441 #include "efm32zg_dmareq.h"
00442 #include "efm32zg_dmactrl.h"
00443 
00444 /**************************************************************************/
00449 /* Bit fields for DMA STATUS */
00450 #define _DMA_STATUS_RESETVALUE                          0x10030000UL                          
00451 #define _DMA_STATUS_MASK                                0x001F00F1UL                          
00452 #define DMA_STATUS_EN                                   (0x1UL << 0)                          
00453 #define _DMA_STATUS_EN_SHIFT                            0                                     
00454 #define _DMA_STATUS_EN_MASK                             0x1UL                                 
00455 #define _DMA_STATUS_EN_DEFAULT                          0x00000000UL                          
00456 #define DMA_STATUS_EN_DEFAULT                           (_DMA_STATUS_EN_DEFAULT << 0)         
00457 #define _DMA_STATUS_STATE_SHIFT                         4                                     
00458 #define _DMA_STATUS_STATE_MASK                          0xF0UL                                
00459 #define _DMA_STATUS_STATE_DEFAULT                       0x00000000UL                          
00460 #define _DMA_STATUS_STATE_IDLE                          0x00000000UL                          
00461 #define _DMA_STATUS_STATE_RDCHCTRLDATA                  0x00000001UL                          
00462 #define _DMA_STATUS_STATE_RDSRCENDPTR                   0x00000002UL                          
00463 #define _DMA_STATUS_STATE_RDDSTENDPTR                   0x00000003UL                          
00464 #define _DMA_STATUS_STATE_RDSRCDATA                     0x00000004UL                          
00465 #define _DMA_STATUS_STATE_WRDSTDATA                     0x00000005UL                          
00466 #define _DMA_STATUS_STATE_WAITREQCLR                    0x00000006UL                          
00467 #define _DMA_STATUS_STATE_WRCHCTRLDATA                  0x00000007UL                          
00468 #define _DMA_STATUS_STATE_STALLED                       0x00000008UL                          
00469 #define _DMA_STATUS_STATE_DONE                          0x00000009UL                          
00470 #define _DMA_STATUS_STATE_PERSCATTRANS                  0x0000000AUL                          
00471 #define DMA_STATUS_STATE_DEFAULT                        (_DMA_STATUS_STATE_DEFAULT << 4)      
00472 #define DMA_STATUS_STATE_IDLE                           (_DMA_STATUS_STATE_IDLE << 4)         
00473 #define DMA_STATUS_STATE_RDCHCTRLDATA                   (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) 
00474 #define DMA_STATUS_STATE_RDSRCENDPTR                    (_DMA_STATUS_STATE_RDSRCENDPTR << 4)  
00475 #define DMA_STATUS_STATE_RDDSTENDPTR                    (_DMA_STATUS_STATE_RDDSTENDPTR << 4)  
00476 #define DMA_STATUS_STATE_RDSRCDATA                      (_DMA_STATUS_STATE_RDSRCDATA << 4)    
00477 #define DMA_STATUS_STATE_WRDSTDATA                      (_DMA_STATUS_STATE_WRDSTDATA << 4)    
00478 #define DMA_STATUS_STATE_WAITREQCLR                     (_DMA_STATUS_STATE_WAITREQCLR << 4)   
00479 #define DMA_STATUS_STATE_WRCHCTRLDATA                   (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) 
00480 #define DMA_STATUS_STATE_STALLED                        (_DMA_STATUS_STATE_STALLED << 4)      
00481 #define DMA_STATUS_STATE_DONE                           (_DMA_STATUS_STATE_DONE << 4)         
00482 #define DMA_STATUS_STATE_PERSCATTRANS                   (_DMA_STATUS_STATE_PERSCATTRANS << 4) 
00483 #define _DMA_STATUS_CHNUM_SHIFT                         16                                    
00484 #define _DMA_STATUS_CHNUM_MASK                          0x1F0000UL                            
00485 #define _DMA_STATUS_CHNUM_DEFAULT                       0x00000003UL                          
00486 #define DMA_STATUS_CHNUM_DEFAULT                        (_DMA_STATUS_CHNUM_DEFAULT << 16)     
00488 /* Bit fields for DMA CONFIG */
00489 #define _DMA_CONFIG_RESETVALUE                          0x00000000UL                      
00490 #define _DMA_CONFIG_MASK                                0x00000021UL                      
00491 #define DMA_CONFIG_EN                                   (0x1UL << 0)                      
00492 #define _DMA_CONFIG_EN_SHIFT                            0                                 
00493 #define _DMA_CONFIG_EN_MASK                             0x1UL                             
00494 #define _DMA_CONFIG_EN_DEFAULT                          0x00000000UL                      
00495 #define DMA_CONFIG_EN_DEFAULT                           (_DMA_CONFIG_EN_DEFAULT << 0)     
00496 #define DMA_CONFIG_CHPROT                               (0x1UL << 5)                      
00497 #define _DMA_CONFIG_CHPROT_SHIFT                        5                                 
00498 #define _DMA_CONFIG_CHPROT_MASK                         0x20UL                            
00499 #define _DMA_CONFIG_CHPROT_DEFAULT                      0x00000000UL                      
00500 #define DMA_CONFIG_CHPROT_DEFAULT                       (_DMA_CONFIG_CHPROT_DEFAULT << 5) 
00502 /* Bit fields for DMA CTRLBASE */
00503 #define _DMA_CTRLBASE_RESETVALUE                        0x00000000UL                          
00504 #define _DMA_CTRLBASE_MASK                              0xFFFFFFFFUL                          
00505 #define _DMA_CTRLBASE_CTRLBASE_SHIFT                    0                                     
00506 #define _DMA_CTRLBASE_CTRLBASE_MASK                     0xFFFFFFFFUL                          
00507 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT                  0x00000000UL                          
00508 #define DMA_CTRLBASE_CTRLBASE_DEFAULT                   (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) 
00510 /* Bit fields for DMA ALTCTRLBASE */
00511 #define _DMA_ALTCTRLBASE_RESETVALUE                     0x00000040UL                                
00512 #define _DMA_ALTCTRLBASE_MASK                           0xFFFFFFFFUL                                
00513 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT              0                                           
00514 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK               0xFFFFFFFFUL                                
00515 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT            0x00000040UL                                
00516 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT             (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) 
00518 /* Bit fields for DMA CHWAITSTATUS */
00519 #define _DMA_CHWAITSTATUS_RESETVALUE                    0x0000000FUL                                   
00520 #define _DMA_CHWAITSTATUS_MASK                          0x0000000FUL                                   
00521 #define DMA_CHWAITSTATUS_CH0WAITSTATUS                  (0x1UL << 0)                                   
00522 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT           0                                              
00523 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK            0x1UL                                          
00524 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT         0x00000001UL                                   
00525 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) 
00526 #define DMA_CHWAITSTATUS_CH1WAITSTATUS                  (0x1UL << 1)                                   
00527 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT           1                                              
00528 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK            0x2UL                                          
00529 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT         0x00000001UL                                   
00530 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) 
00531 #define DMA_CHWAITSTATUS_CH2WAITSTATUS                  (0x1UL << 2)                                   
00532 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT           2                                              
00533 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK            0x4UL                                          
00534 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT         0x00000001UL                                   
00535 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) 
00536 #define DMA_CHWAITSTATUS_CH3WAITSTATUS                  (0x1UL << 3)                                   
00537 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT           3                                              
00538 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK            0x8UL                                          
00539 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT         0x00000001UL                                   
00540 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT          (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) 
00542 /* Bit fields for DMA CHSWREQ */
00543 #define _DMA_CHSWREQ_RESETVALUE                         0x00000000UL                         
00544 #define _DMA_CHSWREQ_MASK                               0x0000000FUL                         
00545 #define DMA_CHSWREQ_CH0SWREQ                            (0x1UL << 0)                         
00546 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT                     0                                    
00547 #define _DMA_CHSWREQ_CH0SWREQ_MASK                      0x1UL                                
00548 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT                   0x00000000UL                         
00549 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) 
00550 #define DMA_CHSWREQ_CH1SWREQ                            (0x1UL << 1)                         
00551 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT                     1                                    
00552 #define _DMA_CHSWREQ_CH1SWREQ_MASK                      0x2UL                                
00553 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT                   0x00000000UL                         
00554 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) 
00555 #define DMA_CHSWREQ_CH2SWREQ                            (0x1UL << 2)                         
00556 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT                     2                                    
00557 #define _DMA_CHSWREQ_CH2SWREQ_MASK                      0x4UL                                
00558 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT                   0x00000000UL                         
00559 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) 
00560 #define DMA_CHSWREQ_CH3SWREQ                            (0x1UL << 3)                         
00561 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT                     3                                    
00562 #define _DMA_CHSWREQ_CH3SWREQ_MASK                      0x8UL                                
00563 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT                   0x00000000UL                         
00564 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT                    (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) 
00566 /* Bit fields for DMA CHUSEBURSTS */
00567 #define _DMA_CHUSEBURSTS_RESETVALUE                     0x00000000UL                                        
00568 #define _DMA_CHUSEBURSTS_MASK                           0x0000000FUL                                        
00569 #define DMA_CHUSEBURSTS_CH0USEBURSTS                    (0x1UL << 0)                                        
00570 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT             0                                                   
00571 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK              0x1UL                                               
00572 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT           0x00000000UL                                        
00573 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST    0x00000000UL                                        
00574 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY         0x00000001UL                                        
00575 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)        
00576 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST     (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) 
00577 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY          (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)      
00578 #define DMA_CHUSEBURSTS_CH1USEBURSTS                    (0x1UL << 1)                                        
00579 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT             1                                                   
00580 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK              0x2UL                                               
00581 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT           0x00000000UL                                        
00582 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)        
00583 #define DMA_CHUSEBURSTS_CH2USEBURSTS                    (0x1UL << 2)                                        
00584 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT             2                                                   
00585 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK              0x4UL                                               
00586 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT           0x00000000UL                                        
00587 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)        
00588 #define DMA_CHUSEBURSTS_CH3USEBURSTS                    (0x1UL << 3)                                        
00589 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT             3                                                   
00590 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK              0x8UL                                               
00591 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT           0x00000000UL                                        
00592 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT            (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)        
00594 /* Bit fields for DMA CHUSEBURSTC */
00595 #define _DMA_CHUSEBURSTC_RESETVALUE                     0x00000000UL                                 
00596 #define _DMA_CHUSEBURSTC_MASK                           0x0000000FUL                                 
00597 #define DMA_CHUSEBURSTC_CH0USEBURSTC                    (0x1UL << 0)                                 
00598 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT             0                                            
00599 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK              0x1UL                                        
00600 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT           0x00000000UL                                 
00601 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) 
00602 #define DMA_CHUSEBURSTC_CH1USEBURSTC                    (0x1UL << 1)                                 
00603 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT             1                                            
00604 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK              0x2UL                                        
00605 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT           0x00000000UL                                 
00606 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) 
00607 #define DMA_CHUSEBURSTC_CH2USEBURSTC                    (0x1UL << 2)                                 
00608 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT             2                                            
00609 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK              0x4UL                                        
00610 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT           0x00000000UL                                 
00611 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) 
00612 #define DMA_CHUSEBURSTC_CH3USEBURSTC                    (0x1UL << 3)                                 
00613 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT             3                                            
00614 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK              0x8UL                                        
00615 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT           0x00000000UL                                 
00616 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT            (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) 
00618 /* Bit fields for DMA CHREQMASKS */
00619 #define _DMA_CHREQMASKS_RESETVALUE                      0x00000000UL                               
00620 #define _DMA_CHREQMASKS_MASK                            0x0000000FUL                               
00621 #define DMA_CHREQMASKS_CH0REQMASKS                      (0x1UL << 0)                               
00622 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT               0                                          
00623 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK                0x1UL                                      
00624 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT             0x00000000UL                               
00625 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) 
00626 #define DMA_CHREQMASKS_CH1REQMASKS                      (0x1UL << 1)                               
00627 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT               1                                          
00628 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK                0x2UL                                      
00629 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT             0x00000000UL                               
00630 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) 
00631 #define DMA_CHREQMASKS_CH2REQMASKS                      (0x1UL << 2)                               
00632 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT               2                                          
00633 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK                0x4UL                                      
00634 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT             0x00000000UL                               
00635 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) 
00636 #define DMA_CHREQMASKS_CH3REQMASKS                      (0x1UL << 3)                               
00637 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT               3                                          
00638 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK                0x8UL                                      
00639 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT             0x00000000UL                               
00640 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT              (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) 
00642 /* Bit fields for DMA CHREQMASKC */
00643 #define _DMA_CHREQMASKC_RESETVALUE                      0x00000000UL                               
00644 #define _DMA_CHREQMASKC_MASK                            0x0000000FUL                               
00645 #define DMA_CHREQMASKC_CH0REQMASKC                      (0x1UL << 0)                               
00646 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT               0                                          
00647 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK                0x1UL                                      
00648 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT             0x00000000UL                               
00649 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) 
00650 #define DMA_CHREQMASKC_CH1REQMASKC                      (0x1UL << 1)                               
00651 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT               1                                          
00652 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK                0x2UL                                      
00653 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT             0x00000000UL                               
00654 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) 
00655 #define DMA_CHREQMASKC_CH2REQMASKC                      (0x1UL << 2)                               
00656 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT               2                                          
00657 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK                0x4UL                                      
00658 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT             0x00000000UL                               
00659 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) 
00660 #define DMA_CHREQMASKC_CH3REQMASKC                      (0x1UL << 3)                               
00661 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT               3                                          
00662 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK                0x8UL                                      
00663 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT             0x00000000UL                               
00664 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT              (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) 
00666 /* Bit fields for DMA CHENS */
00667 #define _DMA_CHENS_RESETVALUE                           0x00000000UL                     
00668 #define _DMA_CHENS_MASK                                 0x0000000FUL                     
00669 #define DMA_CHENS_CH0ENS                                (0x1UL << 0)                     
00670 #define _DMA_CHENS_CH0ENS_SHIFT                         0                                
00671 #define _DMA_CHENS_CH0ENS_MASK                          0x1UL                            
00672 #define _DMA_CHENS_CH0ENS_DEFAULT                       0x00000000UL                     
00673 #define DMA_CHENS_CH0ENS_DEFAULT                        (_DMA_CHENS_CH0ENS_DEFAULT << 0) 
00674 #define DMA_CHENS_CH1ENS                                (0x1UL << 1)                     
00675 #define _DMA_CHENS_CH1ENS_SHIFT                         1                                
00676 #define _DMA_CHENS_CH1ENS_MASK                          0x2UL                            
00677 #define _DMA_CHENS_CH1ENS_DEFAULT                       0x00000000UL                     
00678 #define DMA_CHENS_CH1ENS_DEFAULT                        (_DMA_CHENS_CH1ENS_DEFAULT << 1) 
00679 #define DMA_CHENS_CH2ENS                                (0x1UL << 2)                     
00680 #define _DMA_CHENS_CH2ENS_SHIFT                         2                                
00681 #define _DMA_CHENS_CH2ENS_MASK                          0x4UL                            
00682 #define _DMA_CHENS_CH2ENS_DEFAULT                       0x00000000UL                     
00683 #define DMA_CHENS_CH2ENS_DEFAULT                        (_DMA_CHENS_CH2ENS_DEFAULT << 2) 
00684 #define DMA_CHENS_CH3ENS                                (0x1UL << 3)                     
00685 #define _DMA_CHENS_CH3ENS_SHIFT                         3                                
00686 #define _DMA_CHENS_CH3ENS_MASK                          0x8UL                            
00687 #define _DMA_CHENS_CH3ENS_DEFAULT                       0x00000000UL                     
00688 #define DMA_CHENS_CH3ENS_DEFAULT                        (_DMA_CHENS_CH3ENS_DEFAULT << 3) 
00690 /* Bit fields for DMA CHENC */
00691 #define _DMA_CHENC_RESETVALUE                           0x00000000UL                     
00692 #define _DMA_CHENC_MASK                                 0x0000000FUL                     
00693 #define DMA_CHENC_CH0ENC                                (0x1UL << 0)                     
00694 #define _DMA_CHENC_CH0ENC_SHIFT                         0                                
00695 #define _DMA_CHENC_CH0ENC_MASK                          0x1UL                            
00696 #define _DMA_CHENC_CH0ENC_DEFAULT                       0x00000000UL                     
00697 #define DMA_CHENC_CH0ENC_DEFAULT                        (_DMA_CHENC_CH0ENC_DEFAULT << 0) 
00698 #define DMA_CHENC_CH1ENC                                (0x1UL << 1)                     
00699 #define _DMA_CHENC_CH1ENC_SHIFT                         1                                
00700 #define _DMA_CHENC_CH1ENC_MASK                          0x2UL                            
00701 #define _DMA_CHENC_CH1ENC_DEFAULT                       0x00000000UL                     
00702 #define DMA_CHENC_CH1ENC_DEFAULT                        (_DMA_CHENC_CH1ENC_DEFAULT << 1) 
00703 #define DMA_CHENC_CH2ENC                                (0x1UL << 2)                     
00704 #define _DMA_CHENC_CH2ENC_SHIFT                         2                                
00705 #define _DMA_CHENC_CH2ENC_MASK                          0x4UL                            
00706 #define _DMA_CHENC_CH2ENC_DEFAULT                       0x00000000UL                     
00707 #define DMA_CHENC_CH2ENC_DEFAULT                        (_DMA_CHENC_CH2ENC_DEFAULT << 2) 
00708 #define DMA_CHENC_CH3ENC                                (0x1UL << 3)                     
00709 #define _DMA_CHENC_CH3ENC_SHIFT                         3                                
00710 #define _DMA_CHENC_CH3ENC_MASK                          0x8UL                            
00711 #define _DMA_CHENC_CH3ENC_DEFAULT                       0x00000000UL                     
00712 #define DMA_CHENC_CH3ENC_DEFAULT                        (_DMA_CHENC_CH3ENC_DEFAULT << 3) 
00714 /* Bit fields for DMA CHALTS */
00715 #define _DMA_CHALTS_RESETVALUE                          0x00000000UL                       
00716 #define _DMA_CHALTS_MASK                                0x0000000FUL                       
00717 #define DMA_CHALTS_CH0ALTS                              (0x1UL << 0)                       
00718 #define _DMA_CHALTS_CH0ALTS_SHIFT                       0                                  
00719 #define _DMA_CHALTS_CH0ALTS_MASK                        0x1UL                              
00720 #define _DMA_CHALTS_CH0ALTS_DEFAULT                     0x00000000UL                       
00721 #define DMA_CHALTS_CH0ALTS_DEFAULT                      (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) 
00722 #define DMA_CHALTS_CH1ALTS                              (0x1UL << 1)                       
00723 #define _DMA_CHALTS_CH1ALTS_SHIFT                       1                                  
00724 #define _DMA_CHALTS_CH1ALTS_MASK                        0x2UL                              
00725 #define _DMA_CHALTS_CH1ALTS_DEFAULT                     0x00000000UL                       
00726 #define DMA_CHALTS_CH1ALTS_DEFAULT                      (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) 
00727 #define DMA_CHALTS_CH2ALTS                              (0x1UL << 2)                       
00728 #define _DMA_CHALTS_CH2ALTS_SHIFT                       2                                  
00729 #define _DMA_CHALTS_CH2ALTS_MASK                        0x4UL                              
00730 #define _DMA_CHALTS_CH2ALTS_DEFAULT                     0x00000000UL                       
00731 #define DMA_CHALTS_CH2ALTS_DEFAULT                      (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) 
00732 #define DMA_CHALTS_CH3ALTS                              (0x1UL << 3)                       
00733 #define _DMA_CHALTS_CH3ALTS_SHIFT                       3                                  
00734 #define _DMA_CHALTS_CH3ALTS_MASK                        0x8UL                              
00735 #define _DMA_CHALTS_CH3ALTS_DEFAULT                     0x00000000UL                       
00736 #define DMA_CHALTS_CH3ALTS_DEFAULT                      (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) 
00738 /* Bit fields for DMA CHALTC */
00739 #define _DMA_CHALTC_RESETVALUE                          0x00000000UL                       
00740 #define _DMA_CHALTC_MASK                                0x0000000FUL                       
00741 #define DMA_CHALTC_CH0ALTC                              (0x1UL << 0)                       
00742 #define _DMA_CHALTC_CH0ALTC_SHIFT                       0                                  
00743 #define _DMA_CHALTC_CH0ALTC_MASK                        0x1UL                              
00744 #define _DMA_CHALTC_CH0ALTC_DEFAULT                     0x00000000UL                       
00745 #define DMA_CHALTC_CH0ALTC_DEFAULT                      (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) 
00746 #define DMA_CHALTC_CH1ALTC                              (0x1UL << 1)                       
00747 #define _DMA_CHALTC_CH1ALTC_SHIFT                       1                                  
00748 #define _DMA_CHALTC_CH1ALTC_MASK                        0x2UL                              
00749 #define _DMA_CHALTC_CH1ALTC_DEFAULT                     0x00000000UL                       
00750 #define DMA_CHALTC_CH1ALTC_DEFAULT                      (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) 
00751 #define DMA_CHALTC_CH2ALTC                              (0x1UL << 2)                       
00752 #define _DMA_CHALTC_CH2ALTC_SHIFT                       2                                  
00753 #define _DMA_CHALTC_CH2ALTC_MASK                        0x4UL                              
00754 #define _DMA_CHALTC_CH2ALTC_DEFAULT                     0x00000000UL                       
00755 #define DMA_CHALTC_CH2ALTC_DEFAULT                      (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) 
00756 #define DMA_CHALTC_CH3ALTC                              (0x1UL << 3)                       
00757 #define _DMA_CHALTC_CH3ALTC_SHIFT                       3                                  
00758 #define _DMA_CHALTC_CH3ALTC_MASK                        0x8UL                              
00759 #define _DMA_CHALTC_CH3ALTC_DEFAULT                     0x00000000UL                       
00760 #define DMA_CHALTC_CH3ALTC_DEFAULT                      (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) 
00762 /* Bit fields for DMA CHPRIS */
00763 #define _DMA_CHPRIS_RESETVALUE                          0x00000000UL                       
00764 #define _DMA_CHPRIS_MASK                                0x0000000FUL                       
00765 #define DMA_CHPRIS_CH0PRIS                              (0x1UL << 0)                       
00766 #define _DMA_CHPRIS_CH0PRIS_SHIFT                       0                                  
00767 #define _DMA_CHPRIS_CH0PRIS_MASK                        0x1UL                              
00768 #define _DMA_CHPRIS_CH0PRIS_DEFAULT                     0x00000000UL                       
00769 #define DMA_CHPRIS_CH0PRIS_DEFAULT                      (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) 
00770 #define DMA_CHPRIS_CH1PRIS                              (0x1UL << 1)                       
00771 #define _DMA_CHPRIS_CH1PRIS_SHIFT                       1                                  
00772 #define _DMA_CHPRIS_CH1PRIS_MASK                        0x2UL                              
00773 #define _DMA_CHPRIS_CH1PRIS_DEFAULT                     0x00000000UL                       
00774 #define DMA_CHPRIS_CH1PRIS_DEFAULT                      (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) 
00775 #define DMA_CHPRIS_CH2PRIS                              (0x1UL << 2)                       
00776 #define _DMA_CHPRIS_CH2PRIS_SHIFT                       2                                  
00777 #define _DMA_CHPRIS_CH2PRIS_MASK                        0x4UL                              
00778 #define _DMA_CHPRIS_CH2PRIS_DEFAULT                     0x00000000UL                       
00779 #define DMA_CHPRIS_CH2PRIS_DEFAULT                      (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) 
00780 #define DMA_CHPRIS_CH3PRIS                              (0x1UL << 3)                       
00781 #define _DMA_CHPRIS_CH3PRIS_SHIFT                       3                                  
00782 #define _DMA_CHPRIS_CH3PRIS_MASK                        0x8UL                              
00783 #define _DMA_CHPRIS_CH3PRIS_DEFAULT                     0x00000000UL                       
00784 #define DMA_CHPRIS_CH3PRIS_DEFAULT                      (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) 
00786 /* Bit fields for DMA CHPRIC */
00787 #define _DMA_CHPRIC_RESETVALUE                          0x00000000UL                       
00788 #define _DMA_CHPRIC_MASK                                0x0000000FUL                       
00789 #define DMA_CHPRIC_CH0PRIC                              (0x1UL << 0)                       
00790 #define _DMA_CHPRIC_CH0PRIC_SHIFT                       0                                  
00791 #define _DMA_CHPRIC_CH0PRIC_MASK                        0x1UL                              
00792 #define _DMA_CHPRIC_CH0PRIC_DEFAULT                     0x00000000UL                       
00793 #define DMA_CHPRIC_CH0PRIC_DEFAULT                      (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) 
00794 #define DMA_CHPRIC_CH1PRIC                              (0x1UL << 1)                       
00795 #define _DMA_CHPRIC_CH1PRIC_SHIFT                       1                                  
00796 #define _DMA_CHPRIC_CH1PRIC_MASK                        0x2UL                              
00797 #define _DMA_CHPRIC_CH1PRIC_DEFAULT                     0x00000000UL                       
00798 #define DMA_CHPRIC_CH1PRIC_DEFAULT                      (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) 
00799 #define DMA_CHPRIC_CH2PRIC                              (0x1UL << 2)                       
00800 #define _DMA_CHPRIC_CH2PRIC_SHIFT                       2                                  
00801 #define _DMA_CHPRIC_CH2PRIC_MASK                        0x4UL                              
00802 #define _DMA_CHPRIC_CH2PRIC_DEFAULT                     0x00000000UL                       
00803 #define DMA_CHPRIC_CH2PRIC_DEFAULT                      (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) 
00804 #define DMA_CHPRIC_CH3PRIC                              (0x1UL << 3)                       
00805 #define _DMA_CHPRIC_CH3PRIC_SHIFT                       3                                  
00806 #define _DMA_CHPRIC_CH3PRIC_MASK                        0x8UL                              
00807 #define _DMA_CHPRIC_CH3PRIC_DEFAULT                     0x00000000UL                       
00808 #define DMA_CHPRIC_CH3PRIC_DEFAULT                      (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) 
00810 /* Bit fields for DMA ERRORC */
00811 #define _DMA_ERRORC_RESETVALUE                          0x00000000UL                      
00812 #define _DMA_ERRORC_MASK                                0x00000001UL                      
00813 #define DMA_ERRORC_ERRORC                               (0x1UL << 0)                      
00814 #define _DMA_ERRORC_ERRORC_SHIFT                        0                                 
00815 #define _DMA_ERRORC_ERRORC_MASK                         0x1UL                             
00816 #define _DMA_ERRORC_ERRORC_DEFAULT                      0x00000000UL                      
00817 #define DMA_ERRORC_ERRORC_DEFAULT                       (_DMA_ERRORC_ERRORC_DEFAULT << 0) 
00819 /* Bit fields for DMA CHREQSTATUS */
00820 #define _DMA_CHREQSTATUS_RESETVALUE                     0x00000000UL                                 
00821 #define _DMA_CHREQSTATUS_MASK                           0x0000000FUL                                 
00822 #define DMA_CHREQSTATUS_CH0REQSTATUS                    (0x1UL << 0)                                 
00823 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT             0                                            
00824 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK              0x1UL                                        
00825 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT           0x00000000UL                                 
00826 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) 
00827 #define DMA_CHREQSTATUS_CH1REQSTATUS                    (0x1UL << 1)                                 
00828 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT             1                                            
00829 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK              0x2UL                                        
00830 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT           0x00000000UL                                 
00831 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) 
00832 #define DMA_CHREQSTATUS_CH2REQSTATUS                    (0x1UL << 2)                                 
00833 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT             2                                            
00834 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK              0x4UL                                        
00835 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT           0x00000000UL                                 
00836 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) 
00837 #define DMA_CHREQSTATUS_CH3REQSTATUS                    (0x1UL << 3)                                 
00838 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT             3                                            
00839 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK              0x8UL                                        
00840 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT           0x00000000UL                                 
00841 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT            (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) 
00843 /* Bit fields for DMA CHSREQSTATUS */
00844 #define _DMA_CHSREQSTATUS_RESETVALUE                    0x00000000UL                                   
00845 #define _DMA_CHSREQSTATUS_MASK                          0x0000000FUL                                   
00846 #define DMA_CHSREQSTATUS_CH0SREQSTATUS                  (0x1UL << 0)                                   
00847 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT           0                                              
00848 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK            0x1UL                                          
00849 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT         0x00000000UL                                   
00850 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) 
00851 #define DMA_CHSREQSTATUS_CH1SREQSTATUS                  (0x1UL << 1)                                   
00852 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT           1                                              
00853 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK            0x2UL                                          
00854 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT         0x00000000UL                                   
00855 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) 
00856 #define DMA_CHSREQSTATUS_CH2SREQSTATUS                  (0x1UL << 2)                                   
00857 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT           2                                              
00858 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK            0x4UL                                          
00859 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT         0x00000000UL                                   
00860 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) 
00861 #define DMA_CHSREQSTATUS_CH3SREQSTATUS                  (0x1UL << 3)                                   
00862 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT           3                                              
00863 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK            0x8UL                                          
00864 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT         0x00000000UL                                   
00865 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT          (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) 
00867 /* Bit fields for DMA IF */
00868 #define _DMA_IF_RESETVALUE                              0x00000000UL                   
00869 #define _DMA_IF_MASK                                    0x8000000FUL                   
00870 #define DMA_IF_CH0DONE                                  (0x1UL << 0)                   
00871 #define _DMA_IF_CH0DONE_SHIFT                           0                              
00872 #define _DMA_IF_CH0DONE_MASK                            0x1UL                          
00873 #define _DMA_IF_CH0DONE_DEFAULT                         0x00000000UL                   
00874 #define DMA_IF_CH0DONE_DEFAULT                          (_DMA_IF_CH0DONE_DEFAULT << 0) 
00875 #define DMA_IF_CH1DONE                                  (0x1UL << 1)                   
00876 #define _DMA_IF_CH1DONE_SHIFT                           1                              
00877 #define _DMA_IF_CH1DONE_MASK                            0x2UL                          
00878 #define _DMA_IF_CH1DONE_DEFAULT                         0x00000000UL                   
00879 #define DMA_IF_CH1DONE_DEFAULT                          (_DMA_IF_CH1DONE_DEFAULT << 1) 
00880 #define DMA_IF_CH2DONE                                  (0x1UL << 2)                   
00881 #define _DMA_IF_CH2DONE_SHIFT                           2                              
00882 #define _DMA_IF_CH2DONE_MASK                            0x4UL                          
00883 #define _DMA_IF_CH2DONE_DEFAULT                         0x00000000UL                   
00884 #define DMA_IF_CH2DONE_DEFAULT                          (_DMA_IF_CH2DONE_DEFAULT << 2) 
00885 #define DMA_IF_CH3DONE                                  (0x1UL << 3)                   
00886 #define _DMA_IF_CH3DONE_SHIFT                           3                              
00887 #define _DMA_IF_CH3DONE_MASK                            0x8UL                          
00888 #define _DMA_IF_CH3DONE_DEFAULT                         0x00000000UL                   
00889 #define DMA_IF_CH3DONE_DEFAULT                          (_DMA_IF_CH3DONE_DEFAULT << 3) 
00890 #define DMA_IF_ERR                                      (0x1UL << 31)                  
00891 #define _DMA_IF_ERR_SHIFT                               31                             
00892 #define _DMA_IF_ERR_MASK                                0x80000000UL                   
00893 #define _DMA_IF_ERR_DEFAULT                             0x00000000UL                   
00894 #define DMA_IF_ERR_DEFAULT                              (_DMA_IF_ERR_DEFAULT << 31)    
00896 /* Bit fields for DMA IFS */
00897 #define _DMA_IFS_RESETVALUE                             0x00000000UL                    
00898 #define _DMA_IFS_MASK                                   0x8000000FUL                    
00899 #define DMA_IFS_CH0DONE                                 (0x1UL << 0)                    
00900 #define _DMA_IFS_CH0DONE_SHIFT                          0                               
00901 #define _DMA_IFS_CH0DONE_MASK                           0x1UL                           
00902 #define _DMA_IFS_CH0DONE_DEFAULT                        0x00000000UL                    
00903 #define DMA_IFS_CH0DONE_DEFAULT                         (_DMA_IFS_CH0DONE_DEFAULT << 0) 
00904 #define DMA_IFS_CH1DONE                                 (0x1UL << 1)                    
00905 #define _DMA_IFS_CH1DONE_SHIFT                          1                               
00906 #define _DMA_IFS_CH1DONE_MASK                           0x2UL                           
00907 #define _DMA_IFS_CH1DONE_DEFAULT                        0x00000000UL                    
00908 #define DMA_IFS_CH1DONE_DEFAULT                         (_DMA_IFS_CH1DONE_DEFAULT << 1) 
00909 #define DMA_IFS_CH2DONE                                 (0x1UL << 2)                    
00910 #define _DMA_IFS_CH2DONE_SHIFT                          2                               
00911 #define _DMA_IFS_CH2DONE_MASK                           0x4UL                           
00912 #define _DMA_IFS_CH2DONE_DEFAULT                        0x00000000UL                    
00913 #define DMA_IFS_CH2DONE_DEFAULT                         (_DMA_IFS_CH2DONE_DEFAULT << 2) 
00914 #define DMA_IFS_CH3DONE                                 (0x1UL << 3)                    
00915 #define _DMA_IFS_CH3DONE_SHIFT                          3                               
00916 #define _DMA_IFS_CH3DONE_MASK                           0x8UL                           
00917 #define _DMA_IFS_CH3DONE_DEFAULT                        0x00000000UL                    
00918 #define DMA_IFS_CH3DONE_DEFAULT                         (_DMA_IFS_CH3DONE_DEFAULT << 3) 
00919 #define DMA_IFS_ERR                                     (0x1UL << 31)                   
00920 #define _DMA_IFS_ERR_SHIFT                              31                              
00921 #define _DMA_IFS_ERR_MASK                               0x80000000UL                    
00922 #define _DMA_IFS_ERR_DEFAULT                            0x00000000UL                    
00923 #define DMA_IFS_ERR_DEFAULT                             (_DMA_IFS_ERR_DEFAULT << 31)    
00925 /* Bit fields for DMA IFC */
00926 #define _DMA_IFC_RESETVALUE                             0x00000000UL                    
00927 #define _DMA_IFC_MASK                                   0x8000000FUL                    
00928 #define DMA_IFC_CH0DONE                                 (0x1UL << 0)                    
00929 #define _DMA_IFC_CH0DONE_SHIFT                          0                               
00930 #define _DMA_IFC_CH0DONE_MASK                           0x1UL                           
00931 #define _DMA_IFC_CH0DONE_DEFAULT                        0x00000000UL                    
00932 #define DMA_IFC_CH0DONE_DEFAULT                         (_DMA_IFC_CH0DONE_DEFAULT << 0) 
00933 #define DMA_IFC_CH1DONE                                 (0x1UL << 1)                    
00934 #define _DMA_IFC_CH1DONE_SHIFT                          1                               
00935 #define _DMA_IFC_CH1DONE_MASK                           0x2UL                           
00936 #define _DMA_IFC_CH1DONE_DEFAULT                        0x00000000UL                    
00937 #define DMA_IFC_CH1DONE_DEFAULT                         (_DMA_IFC_CH1DONE_DEFAULT << 1) 
00938 #define DMA_IFC_CH2DONE                                 (0x1UL << 2)                    
00939 #define _DMA_IFC_CH2DONE_SHIFT                          2                               
00940 #define _DMA_IFC_CH2DONE_MASK                           0x4UL                           
00941 #define _DMA_IFC_CH2DONE_DEFAULT                        0x00000000UL                    
00942 #define DMA_IFC_CH2DONE_DEFAULT                         (_DMA_IFC_CH2DONE_DEFAULT << 2) 
00943 #define DMA_IFC_CH3DONE                                 (0x1UL << 3)                    
00944 #define _DMA_IFC_CH3DONE_SHIFT                          3                               
00945 #define _DMA_IFC_CH3DONE_MASK                           0x8UL                           
00946 #define _DMA_IFC_CH3DONE_DEFAULT                        0x00000000UL                    
00947 #define DMA_IFC_CH3DONE_DEFAULT                         (_DMA_IFC_CH3DONE_DEFAULT << 3) 
00948 #define DMA_IFC_ERR                                     (0x1UL << 31)                   
00949 #define _DMA_IFC_ERR_SHIFT                              31                              
00950 #define _DMA_IFC_ERR_MASK                               0x80000000UL                    
00951 #define _DMA_IFC_ERR_DEFAULT                            0x00000000UL                    
00952 #define DMA_IFC_ERR_DEFAULT                             (_DMA_IFC_ERR_DEFAULT << 31)    
00954 /* Bit fields for DMA IEN */
00955 #define _DMA_IEN_RESETVALUE                             0x00000000UL                    
00956 #define _DMA_IEN_MASK                                   0x8000000FUL                    
00957 #define DMA_IEN_CH0DONE                                 (0x1UL << 0)                    
00958 #define _DMA_IEN_CH0DONE_SHIFT                          0                               
00959 #define _DMA_IEN_CH0DONE_MASK                           0x1UL                           
00960 #define _DMA_IEN_CH0DONE_DEFAULT                        0x00000000UL                    
00961 #define DMA_IEN_CH0DONE_DEFAULT                         (_DMA_IEN_CH0DONE_DEFAULT << 0) 
00962 #define DMA_IEN_CH1DONE                                 (0x1UL << 1)                    
00963 #define _DMA_IEN_CH1DONE_SHIFT                          1                               
00964 #define _DMA_IEN_CH1DONE_MASK                           0x2UL                           
00965 #define _DMA_IEN_CH1DONE_DEFAULT                        0x00000000UL                    
00966 #define DMA_IEN_CH1DONE_DEFAULT                         (_DMA_IEN_CH1DONE_DEFAULT << 1) 
00967 #define DMA_IEN_CH2DONE                                 (0x1UL << 2)                    
00968 #define _DMA_IEN_CH2DONE_SHIFT                          2                               
00969 #define _DMA_IEN_CH2DONE_MASK                           0x4UL                           
00970 #define _DMA_IEN_CH2DONE_DEFAULT                        0x00000000UL                    
00971 #define DMA_IEN_CH2DONE_DEFAULT                         (_DMA_IEN_CH2DONE_DEFAULT << 2) 
00972 #define DMA_IEN_CH3DONE                                 (0x1UL << 3)                    
00973 #define _DMA_IEN_CH3DONE_SHIFT                          3                               
00974 #define _DMA_IEN_CH3DONE_MASK                           0x8UL                           
00975 #define _DMA_IEN_CH3DONE_DEFAULT                        0x00000000UL                    
00976 #define DMA_IEN_CH3DONE_DEFAULT                         (_DMA_IEN_CH3DONE_DEFAULT << 3) 
00977 #define DMA_IEN_ERR                                     (0x1UL << 31)                   
00978 #define _DMA_IEN_ERR_SHIFT                              31                              
00979 #define _DMA_IEN_ERR_MASK                               0x80000000UL                    
00980 #define _DMA_IEN_ERR_DEFAULT                            0x00000000UL                    
00981 #define DMA_IEN_ERR_DEFAULT                             (_DMA_IEN_ERR_DEFAULT << 31)    
00983 /* Bit fields for DMA CH_CTRL */
00984 #define _DMA_CH_CTRL_RESETVALUE                         0x00000000UL                                  
00985 #define _DMA_CH_CTRL_MASK                               0x003F000FUL                                  
00986 #define _DMA_CH_CTRL_SIGSEL_SHIFT                       0                                             
00987 #define _DMA_CH_CTRL_SIGSEL_MASK                        0xFUL                                         
00988 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV               0x00000000UL                                  
00989 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV              0x00000000UL                                  
00990 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                 0x00000000UL                                  
00991 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF                  0x00000000UL                                  
00992 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF                  0x00000000UL                                  
00993 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA                    0x00000000UL                                  
00994 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL                  0x00000001UL                                  
00995 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL                 0x00000001UL                                  
00996 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL                    0x00000001UL                                  
00997 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0                   0x00000001UL                                  
00998 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0                   0x00000001UL                                  
00999 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY               0x00000002UL                                  
01000 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY              0x00000002UL                                  
01001 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1                   0x00000002UL                                  
01002 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1                   0x00000002UL                                  
01003 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT          0x00000003UL                                  
01004 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2                   0x00000003UL                                  
01005 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2                   0x00000003UL                                  
01006 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT             0x00000004UL                                  
01007 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV                (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)      
01008 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV               (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)     
01009 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV                  (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)        
01010 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)         
01011 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF                   (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)         
01012 #define DMA_CH_CTRL_SIGSEL_MSCWDATA                     (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)           
01013 #define DMA_CH_CTRL_SIGSEL_USART1TXBL                   (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)         
01014 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL                  (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)        
01015 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL                     (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)           
01016 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)          
01017 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)          
01018 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY                (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)      
01019 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY               (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)     
01020 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)          
01021 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)          
01022 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT           (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) 
01023 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)          
01024 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2                    (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)          
01025 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT              (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)    
01026 #define _DMA_CH_CTRL_SOURCESEL_SHIFT                    16                                            
01027 #define _DMA_CH_CTRL_SOURCESEL_MASK                     0x3F0000UL                                    
01028 #define _DMA_CH_CTRL_SOURCESEL_NONE                     0x00000000UL                                  
01029 #define _DMA_CH_CTRL_SOURCESEL_USART1                   0x0000000DUL                                  
01030 #define _DMA_CH_CTRL_SOURCESEL_LEUART0                  0x00000010UL                                  
01031 #define _DMA_CH_CTRL_SOURCESEL_I2C0                     0x00000014UL                                  
01032 #define _DMA_CH_CTRL_SOURCESEL_TIMER0                   0x00000018UL                                  
01033 #define _DMA_CH_CTRL_SOURCESEL_TIMER1                   0x00000019UL                                  
01034 #define _DMA_CH_CTRL_SOURCESEL_MSC                      0x00000030UL                                  
01035 #define DMA_CH_CTRL_SOURCESEL_NONE                      (_DMA_CH_CTRL_SOURCESEL_NONE << 16)           
01036 #define DMA_CH_CTRL_SOURCESEL_USART1                    (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)         
01037 #define DMA_CH_CTRL_SOURCESEL_LEUART0                   (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)        
01038 #define DMA_CH_CTRL_SOURCESEL_I2C0                      (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)           
01039 #define DMA_CH_CTRL_SOURCESEL_TIMER0                    (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)         
01040 #define DMA_CH_CTRL_SOURCESEL_TIMER1                    (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)         
01041 #define DMA_CH_CTRL_SOURCESEL_MSC                       (_DMA_CH_CTRL_SOURCESEL_MSC << 16)            
01047 /**************************************************************************/
01052 /* Bit fields for CMU CTRL */
01053 #define _CMU_CTRL_RESETVALUE                        0x000C262CUL                             
01054 #define _CMU_CTRL_MASK                              0x07FE3EEFUL                             
01055 #define _CMU_CTRL_HFXOMODE_SHIFT                    0                                        
01056 #define _CMU_CTRL_HFXOMODE_MASK                     0x3UL                                    
01057 #define _CMU_CTRL_HFXOMODE_DEFAULT                  0x00000000UL                             
01058 #define _CMU_CTRL_HFXOMODE_XTAL                     0x00000000UL                             
01059 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK                0x00000001UL                             
01060 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK                0x00000002UL                             
01061 #define CMU_CTRL_HFXOMODE_DEFAULT                   (_CMU_CTRL_HFXOMODE_DEFAULT << 0)        
01062 #define CMU_CTRL_HFXOMODE_XTAL                      (_CMU_CTRL_HFXOMODE_XTAL << 0)           
01063 #define CMU_CTRL_HFXOMODE_BUFEXTCLK                 (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0)      
01064 #define CMU_CTRL_HFXOMODE_DIGEXTCLK                 (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0)      
01065 #define _CMU_CTRL_HFXOBOOST_SHIFT                   2                                        
01066 #define _CMU_CTRL_HFXOBOOST_MASK                    0xCUL                                    
01067 #define _CMU_CTRL_HFXOBOOST_50PCENT                 0x00000000UL                             
01068 #define _CMU_CTRL_HFXOBOOST_70PCENT                 0x00000001UL                             
01069 #define _CMU_CTRL_HFXOBOOST_80PCENT                 0x00000002UL                             
01070 #define _CMU_CTRL_HFXOBOOST_DEFAULT                 0x00000003UL                             
01071 #define _CMU_CTRL_HFXOBOOST_100PCENT                0x00000003UL                             
01072 #define CMU_CTRL_HFXOBOOST_50PCENT                  (_CMU_CTRL_HFXOBOOST_50PCENT << 2)       
01073 #define CMU_CTRL_HFXOBOOST_70PCENT                  (_CMU_CTRL_HFXOBOOST_70PCENT << 2)       
01074 #define CMU_CTRL_HFXOBOOST_80PCENT                  (_CMU_CTRL_HFXOBOOST_80PCENT << 2)       
01075 #define CMU_CTRL_HFXOBOOST_DEFAULT                  (_CMU_CTRL_HFXOBOOST_DEFAULT << 2)       
01076 #define CMU_CTRL_HFXOBOOST_100PCENT                 (_CMU_CTRL_HFXOBOOST_100PCENT << 2)      
01077 #define _CMU_CTRL_HFXOBUFCUR_SHIFT                  5                                        
01078 #define _CMU_CTRL_HFXOBUFCUR_MASK                   0x60UL                                   
01079 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT                0x00000001UL                             
01080 #define CMU_CTRL_HFXOBUFCUR_DEFAULT                 (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5)      
01081 #define CMU_CTRL_HFXOGLITCHDETEN                    (0x1UL << 7)                             
01082 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT             7                                        
01083 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK              0x80UL                                   
01084 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT           0x00000000UL                             
01085 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT            (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) 
01086 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT                 9                                        
01087 #define _CMU_CTRL_HFXOTIMEOUT_MASK                  0x600UL                                  
01088 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES               0x00000000UL                             
01089 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES             0x00000001UL                             
01090 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES              0x00000002UL                             
01091 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT               0x00000003UL                             
01092 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES             0x00000003UL                             
01093 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES                (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9)     
01094 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES              (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9)   
01095 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9)    
01096 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT                (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9)     
01097 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9)   
01098 #define _CMU_CTRL_LFXOMODE_SHIFT                    11                                       
01099 #define _CMU_CTRL_LFXOMODE_MASK                     0x1800UL                                 
01100 #define _CMU_CTRL_LFXOMODE_DEFAULT                  0x00000000UL                             
01101 #define _CMU_CTRL_LFXOMODE_XTAL                     0x00000000UL                             
01102 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK                0x00000001UL                             
01103 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK                0x00000002UL                             
01104 #define CMU_CTRL_LFXOMODE_DEFAULT                   (_CMU_CTRL_LFXOMODE_DEFAULT << 11)       
01105 #define CMU_CTRL_LFXOMODE_XTAL                      (_CMU_CTRL_LFXOMODE_XTAL << 11)          
01106 #define CMU_CTRL_LFXOMODE_BUFEXTCLK                 (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11)     
01107 #define CMU_CTRL_LFXOMODE_DIGEXTCLK                 (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11)     
01108 #define CMU_CTRL_LFXOBOOST                          (0x1UL << 13)                            
01109 #define _CMU_CTRL_LFXOBOOST_SHIFT                   13                                       
01110 #define _CMU_CTRL_LFXOBOOST_MASK                    0x2000UL                                 
01111 #define _CMU_CTRL_LFXOBOOST_70PCENT                 0x00000000UL                             
01112 #define _CMU_CTRL_LFXOBOOST_DEFAULT                 0x00000001UL                             
01113 #define _CMU_CTRL_LFXOBOOST_100PCENT                0x00000001UL                             
01114 #define CMU_CTRL_LFXOBOOST_70PCENT                  (_CMU_CTRL_LFXOBOOST_70PCENT << 13)      
01115 #define CMU_CTRL_LFXOBOOST_DEFAULT                  (_CMU_CTRL_LFXOBOOST_DEFAULT << 13)      
01116 #define CMU_CTRL_LFXOBOOST_100PCENT                 (_CMU_CTRL_LFXOBOOST_100PCENT << 13)     
01117 #define CMU_CTRL_LFXOBUFCUR                         (0x1UL << 17)                            
01118 #define _CMU_CTRL_LFXOBUFCUR_SHIFT                  17                                       
01119 #define _CMU_CTRL_LFXOBUFCUR_MASK                   0x20000UL                                
01120 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT                0x00000000UL                             
01121 #define CMU_CTRL_LFXOBUFCUR_DEFAULT                 (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17)     
01122 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT                 18                                       
01123 #define _CMU_CTRL_LFXOTIMEOUT_MASK                  0xC0000UL                                
01124 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES               0x00000000UL                             
01125 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES              0x00000001UL                             
01126 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES             0x00000002UL                             
01127 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT               0x00000003UL                             
01128 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES             0x00000003UL                             
01129 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES                (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18)    
01130 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES               (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18)   
01131 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18)  
01132 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT                (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18)    
01133 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES              (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18)  
01134 #define _CMU_CTRL_CLKOUTSEL0_SHIFT                  20                                       
01135 #define _CMU_CTRL_CLKOUTSEL0_MASK                   0x700000UL                               
01136 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT                0x00000000UL                             
01137 #define _CMU_CTRL_CLKOUTSEL0_HFRCO                  0x00000000UL                             
01138 #define _CMU_CTRL_CLKOUTSEL0_HFXO                   0x00000001UL                             
01139 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2                 0x00000002UL                             
01140 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4                 0x00000003UL                             
01141 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8                 0x00000004UL                             
01142 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16                0x00000005UL                             
01143 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO                 0x00000006UL                             
01144 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO               0x00000007UL                             
01145 #define CMU_CTRL_CLKOUTSEL0_DEFAULT                 (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20)     
01146 #define CMU_CTRL_CLKOUTSEL0_HFRCO                   (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20)       
01147 #define CMU_CTRL_CLKOUTSEL0_HFXO                    (_CMU_CTRL_CLKOUTSEL0_HFXO << 20)        
01148 #define CMU_CTRL_CLKOUTSEL0_HFCLK2                  (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20)      
01149 #define CMU_CTRL_CLKOUTSEL0_HFCLK4                  (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20)      
01150 #define CMU_CTRL_CLKOUTSEL0_HFCLK8                  (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20)      
01151 #define CMU_CTRL_CLKOUTSEL0_HFCLK16                 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20)     
01152 #define CMU_CTRL_CLKOUTSEL0_ULFRCO                  (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20)      
01153 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO                (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20)    
01154 #define _CMU_CTRL_CLKOUTSEL1_SHIFT                  23                                       
01155 #define _CMU_CTRL_CLKOUTSEL1_MASK                   0x7800000UL                              
01156 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT                0x00000000UL                             
01157 #define _CMU_CTRL_CLKOUTSEL1_LFRCO                  0x00000000UL                             
01158 #define _CMU_CTRL_CLKOUTSEL1_LFXO                   0x00000001UL                             
01159 #define _CMU_CTRL_CLKOUTSEL1_HFCLK                  0x00000002UL                             
01160 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ                  0x00000003UL                             
01161 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ                  0x00000004UL                             
01162 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ                 0x00000005UL                             
01163 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ                 0x00000006UL                             
01164 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ              0x00000007UL                             
01165 #define CMU_CTRL_CLKOUTSEL1_DEFAULT                 (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23)     
01166 #define CMU_CTRL_CLKOUTSEL1_LFRCO                   (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23)       
01167 #define CMU_CTRL_CLKOUTSEL1_LFXO                    (_CMU_CTRL_CLKOUTSEL1_LFXO << 23)        
01168 #define CMU_CTRL_CLKOUTSEL1_HFCLK                   (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23)       
01169 #define CMU_CTRL_CLKOUTSEL1_LFXOQ                   (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23)       
01170 #define CMU_CTRL_CLKOUTSEL1_HFXOQ                   (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23)       
01171 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23)      
01172 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ                  (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23)      
01173 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ               (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23)   
01175 /* Bit fields for CMU HFCORECLKDIV */
01176 #define _CMU_HFCORECLKDIV_RESETVALUE                0x00000000UL                                    
01177 #define _CMU_HFCORECLKDIV_MASK                      0x0000010FUL                                    
01178 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT        0                                               
01179 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK         0xFUL                                           
01180 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT      0x00000000UL                                    
01181 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK        0x00000000UL                                    
01182 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2       0x00000001UL                                    
01183 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4       0x00000002UL                                    
01184 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8       0x00000003UL                                    
01185 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16      0x00000004UL                                    
01186 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32      0x00000005UL                                    
01187 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64      0x00000006UL                                    
01188 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128     0x00000007UL                                    
01189 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256     0x00000008UL                                    
01190 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512     0x00000009UL                                    
01191 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT       (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0)   
01192 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK         (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0)     
01193 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0)    
01194 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0)    
01195 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8        (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0)    
01196 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0)   
01197 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0)   
01198 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64       (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0)   
01199 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0)  
01200 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0)  
01201 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512      (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0)  
01202 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV             (0x1UL << 8)                                    
01203 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT      8                                               
01204 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK       0x100UL                                         
01205 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT    0x00000000UL                                    
01206 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2       0x00000000UL                                    
01207 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4       0x00000001UL                                    
01208 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT     (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) 
01209 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8)    
01210 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4        (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8)    
01212 /* Bit fields for CMU HFPERCLKDIV */
01213 #define _CMU_HFPERCLKDIV_RESETVALUE                 0x00000100UL                                 
01214 #define _CMU_HFPERCLKDIV_MASK                       0x0000010FUL                                 
01215 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT          0                                            
01216 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK           0xFUL                                        
01217 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT        0x00000000UL                                 
01218 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK          0x00000000UL                                 
01219 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2         0x00000001UL                                 
01220 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4         0x00000002UL                                 
01221 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8         0x00000003UL                                 
01222 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16        0x00000004UL                                 
01223 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32        0x00000005UL                                 
01224 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64        0x00000006UL                                 
01225 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128       0x00000007UL                                 
01226 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256       0x00000008UL                                 
01227 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512       0x00000009UL                                 
01228 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT         (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0)  
01229 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK           (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0)    
01230 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0)   
01231 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0)   
01232 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8          (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0)   
01233 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0)  
01234 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0)  
01235 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64         (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0)  
01236 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) 
01237 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) 
01238 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512        (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) 
01239 #define CMU_HFPERCLKDIV_HFPERCLKEN                  (0x1UL << 8)                                 
01240 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT           8                                            
01241 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK            0x100UL                                      
01242 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT         0x00000001UL                                 
01243 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT          (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8)   
01245 /* Bit fields for CMU HFRCOCTRL */
01246 #define _CMU_HFRCOCTRL_RESETVALUE                   0x00000380UL                           
01247 #define _CMU_HFRCOCTRL_MASK                         0x0001F7FFUL                           
01248 #define _CMU_HFRCOCTRL_TUNING_SHIFT                 0                                      
01249 #define _CMU_HFRCOCTRL_TUNING_MASK                  0xFFUL                                 
01250 #define _CMU_HFRCOCTRL_TUNING_DEFAULT               0x00000080UL                           
01251 #define CMU_HFRCOCTRL_TUNING_DEFAULT                (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0)   
01252 #define _CMU_HFRCOCTRL_BAND_SHIFT                   8                                      
01253 #define _CMU_HFRCOCTRL_BAND_MASK                    0x700UL                                
01254 #define _CMU_HFRCOCTRL_BAND_1MHZ                    0x00000000UL                           
01255 #define _CMU_HFRCOCTRL_BAND_7MHZ                    0x00000001UL                           
01256 #define _CMU_HFRCOCTRL_BAND_11MHZ                   0x00000002UL                           
01257 #define _CMU_HFRCOCTRL_BAND_DEFAULT                 0x00000003UL                           
01258 #define _CMU_HFRCOCTRL_BAND_14MHZ                   0x00000003UL                           
01259 #define _CMU_HFRCOCTRL_BAND_21MHZ                   0x00000004UL                           
01260 #define CMU_HFRCOCTRL_BAND_1MHZ                     (_CMU_HFRCOCTRL_BAND_1MHZ << 8)        
01261 #define CMU_HFRCOCTRL_BAND_7MHZ                     (_CMU_HFRCOCTRL_BAND_7MHZ << 8)        
01262 #define CMU_HFRCOCTRL_BAND_11MHZ                    (_CMU_HFRCOCTRL_BAND_11MHZ << 8)       
01263 #define CMU_HFRCOCTRL_BAND_DEFAULT                  (_CMU_HFRCOCTRL_BAND_DEFAULT << 8)     
01264 #define CMU_HFRCOCTRL_BAND_14MHZ                    (_CMU_HFRCOCTRL_BAND_14MHZ << 8)       
01265 #define CMU_HFRCOCTRL_BAND_21MHZ                    (_CMU_HFRCOCTRL_BAND_21MHZ << 8)       
01266 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT                12                                     
01267 #define _CMU_HFRCOCTRL_SUDELAY_MASK                 0x1F000UL                              
01268 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT              0x00000000UL                           
01269 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT               (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) 
01271 /* Bit fields for CMU LFRCOCTRL */
01272 #define _CMU_LFRCOCTRL_RESETVALUE                   0x00000040UL                         
01273 #define _CMU_LFRCOCTRL_MASK                         0x0000007FUL                         
01274 #define _CMU_LFRCOCTRL_TUNING_SHIFT                 0                                    
01275 #define _CMU_LFRCOCTRL_TUNING_MASK                  0x7FUL                               
01276 #define _CMU_LFRCOCTRL_TUNING_DEFAULT               0x00000040UL                         
01277 #define CMU_LFRCOCTRL_TUNING_DEFAULT                (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) 
01279 /* Bit fields for CMU AUXHFRCOCTRL */
01280 #define _CMU_AUXHFRCOCTRL_RESETVALUE                0x00000080UL                            
01281 #define _CMU_AUXHFRCOCTRL_MASK                      0x000007FFUL                            
01282 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT              0                                       
01283 #define _CMU_AUXHFRCOCTRL_TUNING_MASK               0xFFUL                                  
01284 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT            0x00000080UL                            
01285 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT             (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) 
01286 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT                8                                       
01287 #define _CMU_AUXHFRCOCTRL_BAND_MASK                 0x700UL                                 
01288 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT              0x00000000UL                            
01289 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ                0x00000000UL                            
01290 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ                0x00000001UL                            
01291 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ                 0x00000002UL                            
01292 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ                 0x00000003UL                            
01293 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ                0x00000007UL                            
01294 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT               (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8)   
01295 #define CMU_AUXHFRCOCTRL_BAND_14MHZ                 (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8)     
01296 #define CMU_AUXHFRCOCTRL_BAND_11MHZ                 (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8)     
01297 #define CMU_AUXHFRCOCTRL_BAND_7MHZ                  (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8)      
01298 #define CMU_AUXHFRCOCTRL_BAND_1MHZ                  (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8)      
01299 #define CMU_AUXHFRCOCTRL_BAND_21MHZ                 (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8)     
01301 /* Bit fields for CMU CALCTRL */
01302 #define _CMU_CALCTRL_RESETVALUE                     0x00000000UL                         
01303 #define _CMU_CALCTRL_MASK                           0x0000007FUL                         
01304 #define _CMU_CALCTRL_UPSEL_SHIFT                    0                                    
01305 #define _CMU_CALCTRL_UPSEL_MASK                     0x7UL                                
01306 #define _CMU_CALCTRL_UPSEL_DEFAULT                  0x00000000UL                         
01307 #define _CMU_CALCTRL_UPSEL_HFXO                     0x00000000UL                         
01308 #define _CMU_CALCTRL_UPSEL_LFXO                     0x00000001UL                         
01309 #define _CMU_CALCTRL_UPSEL_HFRCO                    0x00000002UL                         
01310 #define _CMU_CALCTRL_UPSEL_LFRCO                    0x00000003UL                         
01311 #define _CMU_CALCTRL_UPSEL_AUXHFRCO                 0x00000004UL                         
01312 #define CMU_CALCTRL_UPSEL_DEFAULT                   (_CMU_CALCTRL_UPSEL_DEFAULT << 0)    
01313 #define CMU_CALCTRL_UPSEL_HFXO                      (_CMU_CALCTRL_UPSEL_HFXO << 0)       
01314 #define CMU_CALCTRL_UPSEL_LFXO                      (_CMU_CALCTRL_UPSEL_LFXO << 0)       
01315 #define CMU_CALCTRL_UPSEL_HFRCO                     (_CMU_CALCTRL_UPSEL_HFRCO << 0)      
01316 #define CMU_CALCTRL_UPSEL_LFRCO                     (_CMU_CALCTRL_UPSEL_LFRCO << 0)      
01317 #define CMU_CALCTRL_UPSEL_AUXHFRCO                  (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0)   
01318 #define _CMU_CALCTRL_DOWNSEL_SHIFT                  3                                    
01319 #define _CMU_CALCTRL_DOWNSEL_MASK                   0x38UL                               
01320 #define _CMU_CALCTRL_DOWNSEL_DEFAULT                0x00000000UL                         
01321 #define _CMU_CALCTRL_DOWNSEL_HFCLK                  0x00000000UL                         
01322 #define _CMU_CALCTRL_DOWNSEL_HFXO                   0x00000001UL                         
01323 #define _CMU_CALCTRL_DOWNSEL_LFXO                   0x00000002UL                         
01324 #define _CMU_CALCTRL_DOWNSEL_HFRCO                  0x00000003UL                         
01325 #define _CMU_CALCTRL_DOWNSEL_LFRCO                  0x00000004UL                         
01326 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO               0x00000005UL                         
01327 #define CMU_CALCTRL_DOWNSEL_DEFAULT                 (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3)  
01328 #define CMU_CALCTRL_DOWNSEL_HFCLK                   (_CMU_CALCTRL_DOWNSEL_HFCLK << 3)    
01329 #define CMU_CALCTRL_DOWNSEL_HFXO                    (_CMU_CALCTRL_DOWNSEL_HFXO << 3)     
01330 #define CMU_CALCTRL_DOWNSEL_LFXO                    (_CMU_CALCTRL_DOWNSEL_LFXO << 3)     
01331 #define CMU_CALCTRL_DOWNSEL_HFRCO                   (_CMU_CALCTRL_DOWNSEL_HFRCO << 3)    
01332 #define CMU_CALCTRL_DOWNSEL_LFRCO                   (_CMU_CALCTRL_DOWNSEL_LFRCO << 3)    
01333 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO                (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) 
01334 #define CMU_CALCTRL_CONT                            (0x1UL << 6)                         
01335 #define _CMU_CALCTRL_CONT_SHIFT                     6                                    
01336 #define _CMU_CALCTRL_CONT_MASK                      0x40UL                               
01337 #define _CMU_CALCTRL_CONT_DEFAULT                   0x00000000UL                         
01338 #define CMU_CALCTRL_CONT_DEFAULT                    (_CMU_CALCTRL_CONT_DEFAULT << 6)     
01340 /* Bit fields for CMU CALCNT */
01341 #define _CMU_CALCNT_RESETVALUE                      0x00000000UL                      
01342 #define _CMU_CALCNT_MASK                            0x000FFFFFUL                      
01343 #define _CMU_CALCNT_CALCNT_SHIFT                    0                                 
01344 #define _CMU_CALCNT_CALCNT_MASK                     0xFFFFFUL                         
01345 #define _CMU_CALCNT_CALCNT_DEFAULT                  0x00000000UL                      
01346 #define CMU_CALCNT_CALCNT_DEFAULT                   (_CMU_CALCNT_CALCNT_DEFAULT << 0) 
01348 /* Bit fields for CMU OSCENCMD */
01349 #define _CMU_OSCENCMD_RESETVALUE                    0x00000000UL                             
01350 #define _CMU_OSCENCMD_MASK                          0x000003FFUL                             
01351 #define CMU_OSCENCMD_HFRCOEN                        (0x1UL << 0)                             
01352 #define _CMU_OSCENCMD_HFRCOEN_SHIFT                 0                                        
01353 #define _CMU_OSCENCMD_HFRCOEN_MASK                  0x1UL                                    
01354 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT               0x00000000UL                             
01355 #define CMU_OSCENCMD_HFRCOEN_DEFAULT                (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0)     
01356 #define CMU_OSCENCMD_HFRCODIS                       (0x1UL << 1)                             
01357 #define _CMU_OSCENCMD_HFRCODIS_SHIFT                1                                        
01358 #define _CMU_OSCENCMD_HFRCODIS_MASK                 0x2UL                                    
01359 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT              0x00000000UL                             
01360 #define CMU_OSCENCMD_HFRCODIS_DEFAULT               (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1)    
01361 #define CMU_OSCENCMD_HFXOEN                         (0x1UL << 2)                             
01362 #define _CMU_OSCENCMD_HFXOEN_SHIFT                  2                                        
01363 #define _CMU_OSCENCMD_HFXOEN_MASK                   0x4UL                                    
01364 #define _CMU_OSCENCMD_HFXOEN_DEFAULT                0x00000000UL                             
01365 #define CMU_OSCENCMD_HFXOEN_DEFAULT                 (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2)      
01366 #define CMU_OSCENCMD_HFXODIS                        (0x1UL << 3)                             
01367 #define _CMU_OSCENCMD_HFXODIS_SHIFT                 3                                        
01368 #define _CMU_OSCENCMD_HFXODIS_MASK                  0x8UL                                    
01369 #define _CMU_OSCENCMD_HFXODIS_DEFAULT               0x00000000UL                             
01370 #define CMU_OSCENCMD_HFXODIS_DEFAULT                (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3)     
01371 #define CMU_OSCENCMD_AUXHFRCOEN                     (0x1UL << 4)                             
01372 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT              4                                        
01373 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK               0x10UL                                   
01374 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT            0x00000000UL                             
01375 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT             (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4)  
01376 #define CMU_OSCENCMD_AUXHFRCODIS                    (0x1UL << 5)                             
01377 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT             5                                        
01378 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK              0x20UL                                   
01379 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT           0x00000000UL                             
01380 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT            (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) 
01381 #define CMU_OSCENCMD_LFRCOEN                        (0x1UL << 6)                             
01382 #define _CMU_OSCENCMD_LFRCOEN_SHIFT                 6                                        
01383 #define _CMU_OSCENCMD_LFRCOEN_MASK                  0x40UL                                   
01384 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT               0x00000000UL                             
01385 #define CMU_OSCENCMD_LFRCOEN_DEFAULT                (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6)     
01386 #define CMU_OSCENCMD_LFRCODIS                       (0x1UL << 7)                             
01387 #define _CMU_OSCENCMD_LFRCODIS_SHIFT                7                                        
01388 #define _CMU_OSCENCMD_LFRCODIS_MASK                 0x80UL                                   
01389 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT              0x00000000UL                             
01390 #define CMU_OSCENCMD_LFRCODIS_DEFAULT               (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7)    
01391 #define CMU_OSCENCMD_LFXOEN                         (0x1UL << 8)                             
01392 #define _CMU_OSCENCMD_LFXOEN_SHIFT                  8                                        
01393 #define _CMU_OSCENCMD_LFXOEN_MASK                   0x100UL                                  
01394 #define _CMU_OSCENCMD_LFXOEN_DEFAULT                0x00000000UL                             
01395 #define CMU_OSCENCMD_LFXOEN_DEFAULT                 (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8)      
01396 #define CMU_OSCENCMD_LFXODIS                        (0x1UL << 9)                             
01397 #define _CMU_OSCENCMD_LFXODIS_SHIFT                 9                                        
01398 #define _CMU_OSCENCMD_LFXODIS_MASK                  0x200UL                                  
01399 #define _CMU_OSCENCMD_LFXODIS_DEFAULT               0x00000000UL                             
01400 #define CMU_OSCENCMD_LFXODIS_DEFAULT                (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9)     
01402 /* Bit fields for CMU CMD */
01403 #define _CMU_CMD_RESETVALUE                         0x00000000UL                     
01404 #define _CMU_CMD_MASK                               0x0000001FUL                     
01405 #define _CMU_CMD_HFCLKSEL_SHIFT                     0                                
01406 #define _CMU_CMD_HFCLKSEL_MASK                      0x7UL                            
01407 #define _CMU_CMD_HFCLKSEL_DEFAULT                   0x00000000UL                     
01408 #define _CMU_CMD_HFCLKSEL_HFRCO                     0x00000001UL                     
01409 #define _CMU_CMD_HFCLKSEL_HFXO                      0x00000002UL                     
01410 #define _CMU_CMD_HFCLKSEL_LFRCO                     0x00000003UL                     
01411 #define _CMU_CMD_HFCLKSEL_LFXO                      0x00000004UL                     
01412 #define CMU_CMD_HFCLKSEL_DEFAULT                    (_CMU_CMD_HFCLKSEL_DEFAULT << 0) 
01413 #define CMU_CMD_HFCLKSEL_HFRCO                      (_CMU_CMD_HFCLKSEL_HFRCO << 0)   
01414 #define CMU_CMD_HFCLKSEL_HFXO                       (_CMU_CMD_HFCLKSEL_HFXO << 0)    
01415 #define CMU_CMD_HFCLKSEL_LFRCO                      (_CMU_CMD_HFCLKSEL_LFRCO << 0)   
01416 #define CMU_CMD_HFCLKSEL_LFXO                       (_CMU_CMD_HFCLKSEL_LFXO << 0)    
01417 #define CMU_CMD_CALSTART                            (0x1UL << 3)                     
01418 #define _CMU_CMD_CALSTART_SHIFT                     3                                
01419 #define _CMU_CMD_CALSTART_MASK                      0x8UL                            
01420 #define _CMU_CMD_CALSTART_DEFAULT                   0x00000000UL                     
01421 #define CMU_CMD_CALSTART_DEFAULT                    (_CMU_CMD_CALSTART_DEFAULT << 3) 
01422 #define CMU_CMD_CALSTOP                             (0x1UL << 4)                     
01423 #define _CMU_CMD_CALSTOP_SHIFT                      4                                
01424 #define _CMU_CMD_CALSTOP_MASK                       0x10UL                           
01425 #define _CMU_CMD_CALSTOP_DEFAULT                    0x00000000UL                     
01426 #define CMU_CMD_CALSTOP_DEFAULT                     (_CMU_CMD_CALSTOP_DEFAULT << 4)  
01428 /* Bit fields for CMU LFCLKSEL */
01429 #define _CMU_LFCLKSEL_RESETVALUE                    0x00000005UL                             
01430 #define _CMU_LFCLKSEL_MASK                          0x0011000FUL                             
01431 #define _CMU_LFCLKSEL_LFA_SHIFT                     0                                        
01432 #define _CMU_LFCLKSEL_LFA_MASK                      0x3UL                                    
01433 #define _CMU_LFCLKSEL_LFA_DISABLED                  0x00000000UL                             
01434 #define _CMU_LFCLKSEL_LFA_DEFAULT                   0x00000001UL                             
01435 #define _CMU_LFCLKSEL_LFA_LFRCO                     0x00000001UL                             
01436 #define _CMU_LFCLKSEL_LFA_LFXO                      0x00000002UL                             
01437 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2           0x00000003UL                             
01438 #define CMU_LFCLKSEL_LFA_DISABLED                   (_CMU_LFCLKSEL_LFA_DISABLED << 0)        
01439 #define CMU_LFCLKSEL_LFA_DEFAULT                    (_CMU_LFCLKSEL_LFA_DEFAULT << 0)         
01440 #define CMU_LFCLKSEL_LFA_LFRCO                      (_CMU_LFCLKSEL_LFA_LFRCO << 0)           
01441 #define CMU_LFCLKSEL_LFA_LFXO                       (_CMU_LFCLKSEL_LFA_LFXO << 0)            
01442 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) 
01443 #define _CMU_LFCLKSEL_LFB_SHIFT                     2                                        
01444 #define _CMU_LFCLKSEL_LFB_MASK                      0xCUL                                    
01445 #define _CMU_LFCLKSEL_LFB_DISABLED                  0x00000000UL                             
01446 #define _CMU_LFCLKSEL_LFB_DEFAULT                   0x00000001UL                             
01447 #define _CMU_LFCLKSEL_LFB_LFRCO                     0x00000001UL                             
01448 #define _CMU_LFCLKSEL_LFB_LFXO                      0x00000002UL                             
01449 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2           0x00000003UL                             
01450 #define CMU_LFCLKSEL_LFB_DISABLED                   (_CMU_LFCLKSEL_LFB_DISABLED << 2)        
01451 #define CMU_LFCLKSEL_LFB_DEFAULT                    (_CMU_LFCLKSEL_LFB_DEFAULT << 2)         
01452 #define CMU_LFCLKSEL_LFB_LFRCO                      (_CMU_LFCLKSEL_LFB_LFRCO << 2)           
01453 #define CMU_LFCLKSEL_LFB_LFXO                       (_CMU_LFCLKSEL_LFB_LFXO << 2)            
01454 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2            (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) 
01455 #define CMU_LFCLKSEL_LFAE                           (0x1UL << 16)                            
01456 #define _CMU_LFCLKSEL_LFAE_SHIFT                    16                                       
01457 #define _CMU_LFCLKSEL_LFAE_MASK                     0x10000UL                                
01458 #define _CMU_LFCLKSEL_LFAE_DEFAULT                  0x00000000UL                             
01459 #define _CMU_LFCLKSEL_LFAE_DISABLED                 0x00000000UL                             
01460 #define _CMU_LFCLKSEL_LFAE_ULFRCO                   0x00000001UL                             
01461 #define CMU_LFCLKSEL_LFAE_DEFAULT                   (_CMU_LFCLKSEL_LFAE_DEFAULT << 16)       
01462 #define CMU_LFCLKSEL_LFAE_DISABLED                  (_CMU_LFCLKSEL_LFAE_DISABLED << 16)      
01463 #define CMU_LFCLKSEL_LFAE_ULFRCO                    (_CMU_LFCLKSEL_LFAE_ULFRCO << 16)        
01464 #define CMU_LFCLKSEL_LFBE                           (0x1UL << 20)                            
01465 #define _CMU_LFCLKSEL_LFBE_SHIFT                    20                                       
01466 #define _CMU_LFCLKSEL_LFBE_MASK                     0x100000UL                               
01467 #define _CMU_LFCLKSEL_LFBE_DEFAULT                  0x00000000UL                             
01468 #define _CMU_LFCLKSEL_LFBE_DISABLED                 0x00000000UL                             
01469 #define _CMU_LFCLKSEL_LFBE_ULFRCO                   0x00000001UL                             
01470 #define CMU_LFCLKSEL_LFBE_DEFAULT                   (_CMU_LFCLKSEL_LFBE_DEFAULT << 20)       
01471 #define CMU_LFCLKSEL_LFBE_DISABLED                  (_CMU_LFCLKSEL_LFBE_DISABLED << 20)      
01472 #define CMU_LFCLKSEL_LFBE_ULFRCO                    (_CMU_LFCLKSEL_LFBE_ULFRCO << 20)        
01474 /* Bit fields for CMU STATUS */
01475 #define _CMU_STATUS_RESETVALUE                      0x00000403UL                           
01476 #define _CMU_STATUS_MASK                            0x00007FFFUL                           
01477 #define CMU_STATUS_HFRCOENS                         (0x1UL << 0)                           
01478 #define _CMU_STATUS_HFRCOENS_SHIFT                  0                                      
01479 #define _CMU_STATUS_HFRCOENS_MASK                   0x1UL                                  
01480 #define _CMU_STATUS_HFRCOENS_DEFAULT                0x00000001UL                           
01481 #define CMU_STATUS_HFRCOENS_DEFAULT                 (_CMU_STATUS_HFRCOENS_DEFAULT << 0)    
01482 #define CMU_STATUS_HFRCORDY                         (0x1UL << 1)                           
01483 #define _CMU_STATUS_HFRCORDY_SHIFT                  1                                      
01484 #define _CMU_STATUS_HFRCORDY_MASK                   0x2UL                                  
01485 #define _CMU_STATUS_HFRCORDY_DEFAULT                0x00000001UL                           
01486 #define CMU_STATUS_HFRCORDY_DEFAULT                 (_CMU_STATUS_HFRCORDY_DEFAULT << 1)    
01487 #define CMU_STATUS_HFXOENS                          (0x1UL << 2)                           
01488 #define _CMU_STATUS_HFXOENS_SHIFT                   2                                      
01489 #define _CMU_STATUS_HFXOENS_MASK                    0x4UL                                  
01490 #define _CMU_STATUS_HFXOENS_DEFAULT                 0x00000000UL                           
01491 #define CMU_STATUS_HFXOENS_DEFAULT                  (_CMU_STATUS_HFXOENS_DEFAULT << 2)     
01492 #define CMU_STATUS_HFXORDY                          (0x1UL << 3)                           
01493 #define _CMU_STATUS_HFXORDY_SHIFT                   3                                      
01494 #define _CMU_STATUS_HFXORDY_MASK                    0x8UL                                  
01495 #define _CMU_STATUS_HFXORDY_DEFAULT                 0x00000000UL                           
01496 #define CMU_STATUS_HFXORDY_DEFAULT                  (_CMU_STATUS_HFXORDY_DEFAULT << 3)     
01497 #define CMU_STATUS_AUXHFRCOENS                      (0x1UL << 4)                           
01498 #define _CMU_STATUS_AUXHFRCOENS_SHIFT               4                                      
01499 #define _CMU_STATUS_AUXHFRCOENS_MASK                0x10UL                                 
01500 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT             0x00000000UL                           
01501 #define CMU_STATUS_AUXHFRCOENS_DEFAULT              (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) 
01502 #define CMU_STATUS_AUXHFRCORDY                      (0x1UL << 5)                           
01503 #define _CMU_STATUS_AUXHFRCORDY_SHIFT               5                                      
01504 #define _CMU_STATUS_AUXHFRCORDY_MASK                0x20UL                                 
01505 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT             0x00000000UL                           
01506 #define CMU_STATUS_AUXHFRCORDY_DEFAULT              (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) 
01507 #define CMU_STATUS_LFRCOENS                         (0x1UL << 6)                           
01508 #define _CMU_STATUS_LFRCOENS_SHIFT                  6                                      
01509 #define _CMU_STATUS_LFRCOENS_MASK                   0x40UL                                 
01510 #define _CMU_STATUS_LFRCOENS_DEFAULT                0x00000000UL                           
01511 #define CMU_STATUS_LFRCOENS_DEFAULT                 (_CMU_STATUS_LFRCOENS_DEFAULT << 6)    
01512 #define CMU_STATUS_LFRCORDY                         (0x1UL << 7)                           
01513 #define _CMU_STATUS_LFRCORDY_SHIFT                  7                                      
01514 #define _CMU_STATUS_LFRCORDY_MASK                   0x80UL                                 
01515 #define _CMU_STATUS_LFRCORDY_DEFAULT                0x00000000UL                           
01516 #define CMU_STATUS_LFRCORDY_DEFAULT                 (_CMU_STATUS_LFRCORDY_DEFAULT << 7)    
01517 #define CMU_STATUS_LFXOENS                          (0x1UL << 8)                           
01518 #define _CMU_STATUS_LFXOENS_SHIFT                   8                                      
01519 #define _CMU_STATUS_LFXOENS_MASK                    0x100UL                                
01520 #define _CMU_STATUS_LFXOENS_DEFAULT                 0x00000000UL                           
01521 #define CMU_STATUS_LFXOENS_DEFAULT                  (_CMU_STATUS_LFXOENS_DEFAULT << 8)     
01522 #define CMU_STATUS_LFXORDY                          (0x1UL << 9)                           
01523 #define _CMU_STATUS_LFXORDY_SHIFT                   9                                      
01524 #define _CMU_STATUS_LFXORDY_MASK                    0x200UL                                
01525 #define _CMU_STATUS_LFXORDY_DEFAULT                 0x00000000UL                           
01526 #define CMU_STATUS_LFXORDY_DEFAULT                  (_CMU_STATUS_LFXORDY_DEFAULT << 9)     
01527 #define CMU_STATUS_HFRCOSEL                         (0x1UL << 10)                          
01528 #define _CMU_STATUS_HFRCOSEL_SHIFT                  10                                     
01529 #define _CMU_STATUS_HFRCOSEL_MASK                   0x400UL                                
01530 #define _CMU_STATUS_HFRCOSEL_DEFAULT                0x00000001UL                           
01531 #define CMU_STATUS_HFRCOSEL_DEFAULT                 (_CMU_STATUS_HFRCOSEL_DEFAULT << 10)   
01532 #define CMU_STATUS_HFXOSEL                          (0x1UL << 11)                          
01533 #define _CMU_STATUS_HFXOSEL_SHIFT                   11                                     
01534 #define _CMU_STATUS_HFXOSEL_MASK                    0x800UL                                
01535 #define _CMU_STATUS_HFXOSEL_DEFAULT                 0x00000000UL                           
01536 #define CMU_STATUS_HFXOSEL_DEFAULT                  (_CMU_STATUS_HFXOSEL_DEFAULT << 11)    
01537 #define CMU_STATUS_LFRCOSEL                         (0x1UL << 12)                          
01538 #define _CMU_STATUS_LFRCOSEL_SHIFT                  12                                     
01539 #define _CMU_STATUS_LFRCOSEL_MASK                   0x1000UL                               
01540 #define _CMU_STATUS_LFRCOSEL_DEFAULT                0x00000000UL                           
01541 #define CMU_STATUS_LFRCOSEL_DEFAULT                 (_CMU_STATUS_LFRCOSEL_DEFAULT << 12)   
01542 #define CMU_STATUS_LFXOSEL                          (0x1UL << 13)                          
01543 #define _CMU_STATUS_LFXOSEL_SHIFT                   13                                     
01544 #define _CMU_STATUS_LFXOSEL_MASK                    0x2000UL                               
01545 #define _CMU_STATUS_LFXOSEL_DEFAULT                 0x00000000UL                           
01546 #define CMU_STATUS_LFXOSEL_DEFAULT                  (_CMU_STATUS_LFXOSEL_DEFAULT << 13)    
01547 #define CMU_STATUS_CALBSY                           (0x1UL << 14)                          
01548 #define _CMU_STATUS_CALBSY_SHIFT                    14                                     
01549 #define _CMU_STATUS_CALBSY_MASK                     0x4000UL                               
01550 #define _CMU_STATUS_CALBSY_DEFAULT                  0x00000000UL                           
01551 #define CMU_STATUS_CALBSY_DEFAULT                   (_CMU_STATUS_CALBSY_DEFAULT << 14)     
01553 /* Bit fields for CMU IF */
01554 #define _CMU_IF_RESETVALUE                          0x00000001UL                       
01555 #define _CMU_IF_MASK                                0x0000007FUL                       
01556 #define CMU_IF_HFRCORDY                             (0x1UL << 0)                       
01557 #define _CMU_IF_HFRCORDY_SHIFT                      0                                  
01558 #define _CMU_IF_HFRCORDY_MASK                       0x1UL                              
01559 #define _CMU_IF_HFRCORDY_DEFAULT                    0x00000001UL                       
01560 #define CMU_IF_HFRCORDY_DEFAULT                     (_CMU_IF_HFRCORDY_DEFAULT << 0)    
01561 #define CMU_IF_HFXORDY                              (0x1UL << 1)                       
01562 #define _CMU_IF_HFXORDY_SHIFT                       1                                  
01563 #define _CMU_IF_HFXORDY_MASK                        0x2UL                              
01564 #define _CMU_IF_HFXORDY_DEFAULT                     0x00000000UL                       
01565 #define CMU_IF_HFXORDY_DEFAULT                      (_CMU_IF_HFXORDY_DEFAULT << 1)     
01566 #define CMU_IF_LFRCORDY                             (0x1UL << 2)                       
01567 #define _CMU_IF_LFRCORDY_SHIFT                      2                                  
01568 #define _CMU_IF_LFRCORDY_MASK                       0x4UL                              
01569 #define _CMU_IF_LFRCORDY_DEFAULT                    0x00000000UL                       
01570 #define CMU_IF_LFRCORDY_DEFAULT                     (_CMU_IF_LFRCORDY_DEFAULT << 2)    
01571 #define CMU_IF_LFXORDY                              (0x1UL << 3)                       
01572 #define _CMU_IF_LFXORDY_SHIFT                       3                                  
01573 #define _CMU_IF_LFXORDY_MASK                        0x8UL                              
01574 #define _CMU_IF_LFXORDY_DEFAULT                     0x00000000UL                       
01575 #define CMU_IF_LFXORDY_DEFAULT                      (_CMU_IF_LFXORDY_DEFAULT << 3)     
01576 #define CMU_IF_AUXHFRCORDY                          (0x1UL << 4)                       
01577 #define _CMU_IF_AUXHFRCORDY_SHIFT                   4                                  
01578 #define _CMU_IF_AUXHFRCORDY_MASK                    0x10UL                             
01579 #define _CMU_IF_AUXHFRCORDY_DEFAULT                 0x00000000UL                       
01580 #define CMU_IF_AUXHFRCORDY_DEFAULT                  (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) 
01581 #define CMU_IF_CALRDY                               (0x1UL << 5)                       
01582 #define _CMU_IF_CALRDY_SHIFT                        5                                  
01583 #define _CMU_IF_CALRDY_MASK                         0x20UL                             
01584 #define _CMU_IF_CALRDY_DEFAULT                      0x00000000UL                       
01585 #define CMU_IF_CALRDY_DEFAULT                       (_CMU_IF_CALRDY_DEFAULT << 5)      
01586 #define CMU_IF_CALOF                                (0x1UL << 6)                       
01587 #define _CMU_IF_CALOF_SHIFT                         6                                  
01588 #define _CMU_IF_CALOF_MASK                          0x40UL                             
01589 #define _CMU_IF_CALOF_DEFAULT                       0x00000000UL                       
01590 #define CMU_IF_CALOF_DEFAULT                        (_CMU_IF_CALOF_DEFAULT << 6)       
01592 /* Bit fields for CMU IFS */
01593 #define _CMU_IFS_RESETVALUE                         0x00000000UL                        
01594 #define _CMU_IFS_MASK                               0x0000007FUL                        
01595 #define CMU_IFS_HFRCORDY                            (0x1UL << 0)                        
01596 #define _CMU_IFS_HFRCORDY_SHIFT                     0                                   
01597 #define _CMU_IFS_HFRCORDY_MASK                      0x1UL                               
01598 #define _CMU_IFS_HFRCORDY_DEFAULT                   0x00000000UL                        
01599 #define CMU_IFS_HFRCORDY_DEFAULT                    (_CMU_IFS_HFRCORDY_DEFAULT << 0)    
01600 #define CMU_IFS_HFXORDY                             (0x1UL << 1)                        
01601 #define _CMU_IFS_HFXORDY_SHIFT                      1                                   
01602 #define _CMU_IFS_HFXORDY_MASK                       0x2UL                               
01603 #define _CMU_IFS_HFXORDY_DEFAULT                    0x00000000UL                        
01604 #define CMU_IFS_HFXORDY_DEFAULT                     (_CMU_IFS_HFXORDY_DEFAULT << 1)     
01605 #define CMU_IFS_LFRCORDY                            (0x1UL << 2)                        
01606 #define _CMU_IFS_LFRCORDY_SHIFT                     2                                   
01607 #define _CMU_IFS_LFRCORDY_MASK                      0x4UL                               
01608 #define _CMU_IFS_LFRCORDY_DEFAULT                   0x00000000UL                        
01609 #define CMU_IFS_LFRCORDY_DEFAULT                    (_CMU_IFS_LFRCORDY_DEFAULT << 2)    
01610 #define CMU_IFS_LFXORDY                             (0x1UL << 3)                        
01611 #define _CMU_IFS_LFXORDY_SHIFT                      3                                   
01612 #define _CMU_IFS_LFXORDY_MASK                       0x8UL                               
01613 #define _CMU_IFS_LFXORDY_DEFAULT                    0x00000000UL                        
01614 #define CMU_IFS_LFXORDY_DEFAULT                     (_CMU_IFS_LFXORDY_DEFAULT << 3)     
01615 #define CMU_IFS_AUXHFRCORDY                         (0x1UL << 4)                        
01616 #define _CMU_IFS_AUXHFRCORDY_SHIFT                  4                                   
01617 #define _CMU_IFS_AUXHFRCORDY_MASK                   0x10UL                              
01618 #define _CMU_IFS_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01619 #define CMU_IFS_AUXHFRCORDY_DEFAULT                 (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) 
01620 #define CMU_IFS_CALRDY                              (0x1UL << 5)                        
01621 #define _CMU_IFS_CALRDY_SHIFT                       5                                   
01622 #define _CMU_IFS_CALRDY_MASK                        0x20UL                              
01623 #define _CMU_IFS_CALRDY_DEFAULT                     0x00000000UL                        
01624 #define CMU_IFS_CALRDY_DEFAULT                      (_CMU_IFS_CALRDY_DEFAULT << 5)      
01625 #define CMU_IFS_CALOF                               (0x1UL << 6)                        
01626 #define _CMU_IFS_CALOF_SHIFT                        6                                   
01627 #define _CMU_IFS_CALOF_MASK                         0x40UL                              
01628 #define _CMU_IFS_CALOF_DEFAULT                      0x00000000UL                        
01629 #define CMU_IFS_CALOF_DEFAULT                       (_CMU_IFS_CALOF_DEFAULT << 6)       
01631 /* Bit fields for CMU IFC */
01632 #define _CMU_IFC_RESETVALUE                         0x00000000UL                        
01633 #define _CMU_IFC_MASK                               0x0000007FUL                        
01634 #define CMU_IFC_HFRCORDY                            (0x1UL << 0)                        
01635 #define _CMU_IFC_HFRCORDY_SHIFT                     0                                   
01636 #define _CMU_IFC_HFRCORDY_MASK                      0x1UL                               
01637 #define _CMU_IFC_HFRCORDY_DEFAULT                   0x00000000UL                        
01638 #define CMU_IFC_HFRCORDY_DEFAULT                    (_CMU_IFC_HFRCORDY_DEFAULT << 0)    
01639 #define CMU_IFC_HFXORDY                             (0x1UL << 1)                        
01640 #define _CMU_IFC_HFXORDY_SHIFT                      1                                   
01641 #define _CMU_IFC_HFXORDY_MASK                       0x2UL                               
01642 #define _CMU_IFC_HFXORDY_DEFAULT                    0x00000000UL                        
01643 #define CMU_IFC_HFXORDY_DEFAULT                     (_CMU_IFC_HFXORDY_DEFAULT << 1)     
01644 #define CMU_IFC_LFRCORDY                            (0x1UL << 2)                        
01645 #define _CMU_IFC_LFRCORDY_SHIFT                     2                                   
01646 #define _CMU_IFC_LFRCORDY_MASK                      0x4UL                               
01647 #define _CMU_IFC_LFRCORDY_DEFAULT                   0x00000000UL                        
01648 #define CMU_IFC_LFRCORDY_DEFAULT                    (_CMU_IFC_LFRCORDY_DEFAULT << 2)    
01649 #define CMU_IFC_LFXORDY                             (0x1UL << 3)                        
01650 #define _CMU_IFC_LFXORDY_SHIFT                      3                                   
01651 #define _CMU_IFC_LFXORDY_MASK                       0x8UL                               
01652 #define _CMU_IFC_LFXORDY_DEFAULT                    0x00000000UL                        
01653 #define CMU_IFC_LFXORDY_DEFAULT                     (_CMU_IFC_LFXORDY_DEFAULT << 3)     
01654 #define CMU_IFC_AUXHFRCORDY                         (0x1UL << 4)                        
01655 #define _CMU_IFC_AUXHFRCORDY_SHIFT                  4                                   
01656 #define _CMU_IFC_AUXHFRCORDY_MASK                   0x10UL                              
01657 #define _CMU_IFC_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01658 #define CMU_IFC_AUXHFRCORDY_DEFAULT                 (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) 
01659 #define CMU_IFC_CALRDY                              (0x1UL << 5)                        
01660 #define _CMU_IFC_CALRDY_SHIFT                       5                                   
01661 #define _CMU_IFC_CALRDY_MASK                        0x20UL                              
01662 #define _CMU_IFC_CALRDY_DEFAULT                     0x00000000UL                        
01663 #define CMU_IFC_CALRDY_DEFAULT                      (_CMU_IFC_CALRDY_DEFAULT << 5)      
01664 #define CMU_IFC_CALOF                               (0x1UL << 6)                        
01665 #define _CMU_IFC_CALOF_SHIFT                        6                                   
01666 #define _CMU_IFC_CALOF_MASK                         0x40UL                              
01667 #define _CMU_IFC_CALOF_DEFAULT                      0x00000000UL                        
01668 #define CMU_IFC_CALOF_DEFAULT                       (_CMU_IFC_CALOF_DEFAULT << 6)       
01670 /* Bit fields for CMU IEN */
01671 #define _CMU_IEN_RESETVALUE                         0x00000000UL                        
01672 #define _CMU_IEN_MASK                               0x0000007FUL                        
01673 #define CMU_IEN_HFRCORDY                            (0x1UL << 0)                        
01674 #define _CMU_IEN_HFRCORDY_SHIFT                     0                                   
01675 #define _CMU_IEN_HFRCORDY_MASK                      0x1UL                               
01676 #define _CMU_IEN_HFRCORDY_DEFAULT                   0x00000000UL                        
01677 #define CMU_IEN_HFRCORDY_DEFAULT                    (_CMU_IEN_HFRCORDY_DEFAULT << 0)    
01678 #define CMU_IEN_HFXORDY                             (0x1UL << 1)                        
01679 #define _CMU_IEN_HFXORDY_SHIFT                      1                                   
01680 #define _CMU_IEN_HFXORDY_MASK                       0x2UL                               
01681 #define _CMU_IEN_HFXORDY_DEFAULT                    0x00000000UL                        
01682 #define CMU_IEN_HFXORDY_DEFAULT                     (_CMU_IEN_HFXORDY_DEFAULT << 1)     
01683 #define CMU_IEN_LFRCORDY                            (0x1UL << 2)                        
01684 #define _CMU_IEN_LFRCORDY_SHIFT                     2                                   
01685 #define _CMU_IEN_LFRCORDY_MASK                      0x4UL                               
01686 #define _CMU_IEN_LFRCORDY_DEFAULT                   0x00000000UL                        
01687 #define CMU_IEN_LFRCORDY_DEFAULT                    (_CMU_IEN_LFRCORDY_DEFAULT << 2)    
01688 #define CMU_IEN_LFXORDY                             (0x1UL << 3)                        
01689 #define _CMU_IEN_LFXORDY_SHIFT                      3                                   
01690 #define _CMU_IEN_LFXORDY_MASK                       0x8UL                               
01691 #define _CMU_IEN_LFXORDY_DEFAULT                    0x00000000UL                        
01692 #define CMU_IEN_LFXORDY_DEFAULT                     (_CMU_IEN_LFXORDY_DEFAULT << 3)     
01693 #define CMU_IEN_AUXHFRCORDY                         (0x1UL << 4)                        
01694 #define _CMU_IEN_AUXHFRCORDY_SHIFT                  4                                   
01695 #define _CMU_IEN_AUXHFRCORDY_MASK                   0x10UL                              
01696 #define _CMU_IEN_AUXHFRCORDY_DEFAULT                0x00000000UL                        
01697 #define CMU_IEN_AUXHFRCORDY_DEFAULT                 (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) 
01698 #define CMU_IEN_CALRDY                              (0x1UL << 5)                        
01699 #define _CMU_IEN_CALRDY_SHIFT                       5                                   
01700 #define _CMU_IEN_CALRDY_MASK                        0x20UL                              
01701 #define _CMU_IEN_CALRDY_DEFAULT                     0x00000000UL                        
01702 #define CMU_IEN_CALRDY_DEFAULT                      (_CMU_IEN_CALRDY_DEFAULT << 5)      
01703 #define CMU_IEN_CALOF                               (0x1UL << 6)                        
01704 #define _CMU_IEN_CALOF_SHIFT                        6                                   
01705 #define _CMU_IEN_CALOF_MASK                         0x40UL                              
01706 #define _CMU_IEN_CALOF_DEFAULT                      0x00000000UL                        
01707 #define CMU_IEN_CALOF_DEFAULT                       (_CMU_IEN_CALOF_DEFAULT << 6)       
01709 /* Bit fields for CMU HFCORECLKEN0 */
01710 #define _CMU_HFCORECLKEN0_RESETVALUE                0x00000000UL                         
01711 #define _CMU_HFCORECLKEN0_MASK                      0x00000006UL                         
01712 #define CMU_HFCORECLKEN0_DMA                        (0x1UL << 1)                         
01713 #define _CMU_HFCORECLKEN0_DMA_SHIFT                 1                                    
01714 #define _CMU_HFCORECLKEN0_DMA_MASK                  0x2UL                                
01715 #define _CMU_HFCORECLKEN0_DMA_DEFAULT               0x00000000UL                         
01716 #define CMU_HFCORECLKEN0_DMA_DEFAULT                (_CMU_HFCORECLKEN0_DMA_DEFAULT << 1) 
01717 #define CMU_HFCORECLKEN0_LE                         (0x1UL << 2)                         
01718 #define _CMU_HFCORECLKEN0_LE_SHIFT                  2                                    
01719 #define _CMU_HFCORECLKEN0_LE_MASK                   0x4UL                                
01720 #define _CMU_HFCORECLKEN0_LE_DEFAULT                0x00000000UL                         
01721 #define CMU_HFCORECLKEN0_LE_DEFAULT                 (_CMU_HFCORECLKEN0_LE_DEFAULT << 2)  
01723 /* Bit fields for CMU HFPERCLKEN0 */
01724 #define _CMU_HFPERCLKEN0_RESETVALUE                 0x00000000UL                           
01725 #define _CMU_HFPERCLKEN0_MASK                       0x0000099FUL                           
01726 #define CMU_HFPERCLKEN0_TIMER0                      (0x1UL << 0)                           
01727 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT               0                                      
01728 #define _CMU_HFPERCLKEN0_TIMER0_MASK                0x1UL                                  
01729 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT             0x00000000UL                           
01730 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT              (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 0) 
01731 #define CMU_HFPERCLKEN0_TIMER1                      (0x1UL << 1)                           
01732 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT               1                                      
01733 #define _CMU_HFPERCLKEN0_TIMER1_MASK                0x2UL                                  
01734 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT             0x00000000UL                           
01735 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT              (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 1) 
01736 #define CMU_HFPERCLKEN0_ACMP0                       (0x1UL << 2)                           
01737 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT                2                                      
01738 #define _CMU_HFPERCLKEN0_ACMP0_MASK                 0x4UL                                  
01739 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT              0x00000000UL                           
01740 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT               (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 2)  
01741 #define CMU_HFPERCLKEN0_USART1                      (0x1UL << 3)                           
01742 #define _CMU_HFPERCLKEN0_USART1_SHIFT               3                                      
01743 #define _CMU_HFPERCLKEN0_USART1_MASK                0x8UL                                  
01744 #define _CMU_HFPERCLKEN0_USART1_DEFAULT             0x00000000UL                           
01745 #define CMU_HFPERCLKEN0_USART1_DEFAULT              (_CMU_HFPERCLKEN0_USART1_DEFAULT << 3) 
01746 #define CMU_HFPERCLKEN0_PRS                         (0x1UL << 4)                           
01747 #define _CMU_HFPERCLKEN0_PRS_SHIFT                  4                                      
01748 #define _CMU_HFPERCLKEN0_PRS_MASK                   0x10UL                                 
01749 #define _CMU_HFPERCLKEN0_PRS_DEFAULT                0x00000000UL                           
01750 #define CMU_HFPERCLKEN0_PRS_DEFAULT                 (_CMU_HFPERCLKEN0_PRS_DEFAULT << 4)    
01751 #define CMU_HFPERCLKEN0_GPIO                        (0x1UL << 7)                           
01752 #define _CMU_HFPERCLKEN0_GPIO_SHIFT                 7                                      
01753 #define _CMU_HFPERCLKEN0_GPIO_MASK                  0x80UL                                 
01754 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT               0x00000000UL                           
01755 #define CMU_HFPERCLKEN0_GPIO_DEFAULT                (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 7)   
01756 #define CMU_HFPERCLKEN0_VCMP                        (0x1UL << 8)                           
01757 #define _CMU_HFPERCLKEN0_VCMP_SHIFT                 8                                      
01758 #define _CMU_HFPERCLKEN0_VCMP_MASK                  0x100UL                                
01759 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT               0x00000000UL                           
01760 #define CMU_HFPERCLKEN0_VCMP_DEFAULT                (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 8)   
01761 #define CMU_HFPERCLKEN0_I2C0                        (0x1UL << 11)                          
01762 #define _CMU_HFPERCLKEN0_I2C0_SHIFT                 11                                     
01763 #define _CMU_HFPERCLKEN0_I2C0_MASK                  0x800UL                                
01764 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT               0x00000000UL                           
01765 #define CMU_HFPERCLKEN0_I2C0_DEFAULT                (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11)  
01767 /* Bit fields for CMU SYNCBUSY */
01768 #define _CMU_SYNCBUSY_RESETVALUE                    0x00000000UL                           
01769 #define _CMU_SYNCBUSY_MASK                          0x00000055UL                           
01770 #define CMU_SYNCBUSY_LFACLKEN0                      (0x1UL << 0)                           
01771 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT               0                                      
01772 #define _CMU_SYNCBUSY_LFACLKEN0_MASK                0x1UL                                  
01773 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT             0x00000000UL                           
01774 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) 
01775 #define CMU_SYNCBUSY_LFAPRESC0                      (0x1UL << 2)                           
01776 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT               2                                      
01777 #define _CMU_SYNCBUSY_LFAPRESC0_MASK                0x4UL                                  
01778 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT             0x00000000UL                           
01779 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) 
01780 #define CMU_SYNCBUSY_LFBCLKEN0                      (0x1UL << 4)                           
01781 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT               4                                      
01782 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK                0x10UL                                 
01783 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT             0x00000000UL                           
01784 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT              (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) 
01785 #define CMU_SYNCBUSY_LFBPRESC0                      (0x1UL << 6)                           
01786 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT               6                                      
01787 #define _CMU_SYNCBUSY_LFBPRESC0_MASK                0x40UL                                 
01788 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT             0x00000000UL                           
01789 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT              (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) 
01791 /* Bit fields for CMU FREEZE */
01792 #define _CMU_FREEZE_RESETVALUE                      0x00000000UL                         
01793 #define _CMU_FREEZE_MASK                            0x00000001UL                         
01794 #define CMU_FREEZE_REGFREEZE                        (0x1UL << 0)                         
01795 #define _CMU_FREEZE_REGFREEZE_SHIFT                 0                                    
01796 #define _CMU_FREEZE_REGFREEZE_MASK                  0x1UL                                
01797 #define _CMU_FREEZE_REGFREEZE_DEFAULT               0x00000000UL                         
01798 #define _CMU_FREEZE_REGFREEZE_UPDATE                0x00000000UL                         
01799 #define _CMU_FREEZE_REGFREEZE_FREEZE                0x00000001UL                         
01800 #define CMU_FREEZE_REGFREEZE_DEFAULT                (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) 
01801 #define CMU_FREEZE_REGFREEZE_UPDATE                 (_CMU_FREEZE_REGFREEZE_UPDATE << 0)  
01802 #define CMU_FREEZE_REGFREEZE_FREEZE                 (_CMU_FREEZE_REGFREEZE_FREEZE << 0)  
01804 /* Bit fields for CMU LFACLKEN0 */
01805 #define _CMU_LFACLKEN0_RESETVALUE                   0x00000000UL                      
01806 #define _CMU_LFACLKEN0_MASK                         0x00000001UL                      
01807 #define CMU_LFACLKEN0_RTC                           (0x1UL << 0)                      
01808 #define _CMU_LFACLKEN0_RTC_SHIFT                    0                                 
01809 #define _CMU_LFACLKEN0_RTC_MASK                     0x1UL                             
01810 #define _CMU_LFACLKEN0_RTC_DEFAULT                  0x00000000UL                      
01811 #define CMU_LFACLKEN0_RTC_DEFAULT                   (_CMU_LFACLKEN0_RTC_DEFAULT << 0) 
01813 /* Bit fields for CMU LFBCLKEN0 */
01814 #define _CMU_LFBCLKEN0_RESETVALUE                   0x00000000UL                          
01815 #define _CMU_LFBCLKEN0_MASK                         0x00000001UL                          
01816 #define CMU_LFBCLKEN0_LEUART0                       (0x1UL << 0)                          
01817 #define _CMU_LFBCLKEN0_LEUART0_SHIFT                0                                     
01818 #define _CMU_LFBCLKEN0_LEUART0_MASK                 0x1UL                                 
01819 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT              0x00000000UL                          
01820 #define CMU_LFBCLKEN0_LEUART0_DEFAULT               (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) 
01822 /* Bit fields for CMU LFAPRESC0 */
01823 #define _CMU_LFAPRESC0_RESETVALUE                   0x00000000UL                       
01824 #define _CMU_LFAPRESC0_MASK                         0x0000000FUL                       
01825 #define _CMU_LFAPRESC0_RTC_SHIFT                    0                                  
01826 #define _CMU_LFAPRESC0_RTC_MASK                     0xFUL                              
01827 #define _CMU_LFAPRESC0_RTC_DIV1                     0x00000000UL                       
01828 #define _CMU_LFAPRESC0_RTC_DIV2                     0x00000001UL                       
01829 #define _CMU_LFAPRESC0_RTC_DIV4                     0x00000002UL                       
01830 #define _CMU_LFAPRESC0_RTC_DIV8                     0x00000003UL                       
01831 #define _CMU_LFAPRESC0_RTC_DIV16                    0x00000004UL                       
01832 #define _CMU_LFAPRESC0_RTC_DIV32                    0x00000005UL                       
01833 #define _CMU_LFAPRESC0_RTC_DIV64                    0x00000006UL                       
01834 #define _CMU_LFAPRESC0_RTC_DIV128                   0x00000007UL                       
01835 #define _CMU_LFAPRESC0_RTC_DIV256                   0x00000008UL                       
01836 #define _CMU_LFAPRESC0_RTC_DIV512                   0x00000009UL                       
01837 #define _CMU_LFAPRESC0_RTC_DIV1024                  0x0000000AUL                       
01838 #define _CMU_LFAPRESC0_RTC_DIV2048                  0x0000000BUL                       
01839 #define _CMU_LFAPRESC0_RTC_DIV4096                  0x0000000CUL                       
01840 #define _CMU_LFAPRESC0_RTC_DIV8192                  0x0000000DUL                       
01841 #define _CMU_LFAPRESC0_RTC_DIV16384                 0x0000000EUL                       
01842 #define _CMU_LFAPRESC0_RTC_DIV32768                 0x0000000FUL                       
01843 #define CMU_LFAPRESC0_RTC_DIV1                      (_CMU_LFAPRESC0_RTC_DIV1 << 0)     
01844 #define CMU_LFAPRESC0_RTC_DIV2                      (_CMU_LFAPRESC0_RTC_DIV2 << 0)     
01845 #define CMU_LFAPRESC0_RTC_DIV4                      (_CMU_LFAPRESC0_RTC_DIV4 << 0)     
01846 #define CMU_LFAPRESC0_RTC_DIV8                      (_CMU_LFAPRESC0_RTC_DIV8 << 0)     
01847 #define CMU_LFAPRESC0_RTC_DIV16                     (_CMU_LFAPRESC0_RTC_DIV16 << 0)    
01848 #define CMU_LFAPRESC0_RTC_DIV32                     (_CMU_LFAPRESC0_RTC_DIV32 << 0)    
01849 #define CMU_LFAPRESC0_RTC_DIV64                     (_CMU_LFAPRESC0_RTC_DIV64 << 0)    
01850 #define CMU_LFAPRESC0_RTC_DIV128                    (_CMU_LFAPRESC0_RTC_DIV128 << 0)   
01851 #define CMU_LFAPRESC0_RTC_DIV256                    (_CMU_LFAPRESC0_RTC_DIV256 << 0)   
01852 #define CMU_LFAPRESC0_RTC_DIV512                    (_CMU_LFAPRESC0_RTC_DIV512 << 0)   
01853 #define CMU_LFAPRESC0_RTC_DIV1024                   (_CMU_LFAPRESC0_RTC_DIV1024 << 0)  
01854 #define CMU_LFAPRESC0_RTC_DIV2048                   (_CMU_LFAPRESC0_RTC_DIV2048 << 0)  
01855 #define CMU_LFAPRESC0_RTC_DIV4096                   (_CMU_LFAPRESC0_RTC_DIV4096 << 0)  
01856 #define CMU_LFAPRESC0_RTC_DIV8192                   (_CMU_LFAPRESC0_RTC_DIV8192 << 0)  
01857 #define CMU_LFAPRESC0_RTC_DIV16384                  (_CMU_LFAPRESC0_RTC_DIV16384 << 0) 
01858 #define CMU_LFAPRESC0_RTC_DIV32768                  (_CMU_LFAPRESC0_RTC_DIV32768 << 0) 
01860 /* Bit fields for CMU LFBPRESC0 */
01861 #define _CMU_LFBPRESC0_RESETVALUE                   0x00000000UL                       
01862 #define _CMU_LFBPRESC0_MASK                         0x00000003UL                       
01863 #define _CMU_LFBPRESC0_LEUART0_SHIFT                0                                  
01864 #define _CMU_LFBPRESC0_LEUART0_MASK                 0x3UL                              
01865 #define _CMU_LFBPRESC0_LEUART0_DIV1                 0x00000000UL                       
01866 #define _CMU_LFBPRESC0_LEUART0_DIV2                 0x00000001UL                       
01867 #define _CMU_LFBPRESC0_LEUART0_DIV4                 0x00000002UL                       
01868 #define _CMU_LFBPRESC0_LEUART0_DIV8                 0x00000003UL                       
01869 #define CMU_LFBPRESC0_LEUART0_DIV1                  (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) 
01870 #define CMU_LFBPRESC0_LEUART0_DIV2                  (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) 
01871 #define CMU_LFBPRESC0_LEUART0_DIV4                  (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) 
01872 #define CMU_LFBPRESC0_LEUART0_DIV8                  (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) 
01874 /* Bit fields for CMU PCNTCTRL */
01875 #define _CMU_PCNTCTRL_RESETVALUE                    0x00000000UL                             
01876 #define _CMU_PCNTCTRL_MASK                          0x00000003UL                             
01877 #define CMU_PCNTCTRL_PCNT0CLKEN                     (0x1UL << 0)                             
01878 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT              0                                        
01879 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK               0x1UL                                    
01880 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT            0x00000000UL                             
01881 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT             (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0)  
01882 #define CMU_PCNTCTRL_PCNT0CLKSEL                    (0x1UL << 1)                             
01883 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT             1                                        
01884 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK              0x2UL                                    
01885 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT           0x00000000UL                             
01886 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK            0x00000000UL                             
01887 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0           0x00000001UL                             
01888 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT            (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) 
01889 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK             (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1)  
01890 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0            (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) 
01892 /* Bit fields for CMU ROUTE */
01893 #define _CMU_ROUTE_RESETVALUE                       0x00000000UL                         
01894 #define _CMU_ROUTE_MASK                             0x0000001FUL                         
01895 #define CMU_ROUTE_CLKOUT0PEN                        (0x1UL << 0)                         
01896 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT                 0                                    
01897 #define _CMU_ROUTE_CLKOUT0PEN_MASK                  0x1UL                                
01898 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT               0x00000000UL                         
01899 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT                (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) 
01900 #define CMU_ROUTE_CLKOUT1PEN                        (0x1UL << 1)                         
01901 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT                 1                                    
01902 #define _CMU_ROUTE_CLKOUT1PEN_MASK                  0x2UL                                
01903 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT               0x00000000UL                         
01904 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT                (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) 
01905 #define _CMU_ROUTE_LOCATION_SHIFT                   2                                    
01906 #define _CMU_ROUTE_LOCATION_MASK                    0x1CUL                               
01907 #define _CMU_ROUTE_LOCATION_LOC0                    0x00000000UL                         
01908 #define _CMU_ROUTE_LOCATION_DEFAULT                 0x00000000UL                         
01909 #define _CMU_ROUTE_LOCATION_LOC1                    0x00000001UL                         
01910 #define _CMU_ROUTE_LOCATION_LOC2                    0x00000002UL                         
01911 #define CMU_ROUTE_LOCATION_LOC0                     (_CMU_ROUTE_LOCATION_LOC0 << 2)      
01912 #define CMU_ROUTE_LOCATION_DEFAULT                  (_CMU_ROUTE_LOCATION_DEFAULT << 2)   
01913 #define CMU_ROUTE_LOCATION_LOC1                     (_CMU_ROUTE_LOCATION_LOC1 << 2)      
01914 #define CMU_ROUTE_LOCATION_LOC2                     (_CMU_ROUTE_LOCATION_LOC2 << 2)      
01916 /* Bit fields for CMU LOCK */
01917 #define _CMU_LOCK_RESETVALUE                        0x00000000UL                      
01918 #define _CMU_LOCK_MASK                              0x0000FFFFUL                      
01919 #define _CMU_LOCK_LOCKKEY_SHIFT                     0                                 
01920 #define _CMU_LOCK_LOCKKEY_MASK                      0xFFFFUL                          
01921 #define _CMU_LOCK_LOCKKEY_DEFAULT                   0x00000000UL                      
01922 #define _CMU_LOCK_LOCKKEY_LOCK                      0x00000000UL                      
01923 #define _CMU_LOCK_LOCKKEY_UNLOCKED                  0x00000000UL                      
01924 #define _CMU_LOCK_LOCKKEY_LOCKED                    0x00000001UL                      
01925 #define _CMU_LOCK_LOCKKEY_UNLOCK                    0x0000580EUL                      
01926 #define CMU_LOCK_LOCKKEY_DEFAULT                    (_CMU_LOCK_LOCKKEY_DEFAULT << 0)  
01927 #define CMU_LOCK_LOCKKEY_LOCK                       (_CMU_LOCK_LOCKKEY_LOCK << 0)     
01928 #define CMU_LOCK_LOCKKEY_UNLOCKED                   (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) 
01929 #define CMU_LOCK_LOCKKEY_LOCKED                     (_CMU_LOCK_LOCKKEY_LOCKED << 0)   
01930 #define CMU_LOCK_LOCKKEY_UNLOCK                     (_CMU_LOCK_LOCKKEY_UNLOCK << 0)   
01934 /**************************************************************************/
01939 /* Bit fields for PRS SWPULSE */
01940 #define _PRS_SWPULSE_RESETVALUE              0x00000000UL                         
01941 #define _PRS_SWPULSE_MASK                    0x0000000FUL                         
01942 #define PRS_SWPULSE_CH0PULSE                 (0x1UL << 0)                         
01943 #define _PRS_SWPULSE_CH0PULSE_SHIFT          0                                    
01944 #define _PRS_SWPULSE_CH0PULSE_MASK           0x1UL                                
01945 #define _PRS_SWPULSE_CH0PULSE_DEFAULT        0x00000000UL                         
01946 #define PRS_SWPULSE_CH0PULSE_DEFAULT         (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) 
01947 #define PRS_SWPULSE_CH1PULSE                 (0x1UL << 1)                         
01948 #define _PRS_SWPULSE_CH1PULSE_SHIFT          1                                    
01949 #define _PRS_SWPULSE_CH1PULSE_MASK           0x2UL                                
01950 #define _PRS_SWPULSE_CH1PULSE_DEFAULT        0x00000000UL                         
01951 #define PRS_SWPULSE_CH1PULSE_DEFAULT         (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) 
01952 #define PRS_SWPULSE_CH2PULSE                 (0x1UL << 2)                         
01953 #define _PRS_SWPULSE_CH2PULSE_SHIFT          2                                    
01954 #define _PRS_SWPULSE_CH2PULSE_MASK           0x4UL                                
01955 #define _PRS_SWPULSE_CH2PULSE_DEFAULT        0x00000000UL                         
01956 #define PRS_SWPULSE_CH2PULSE_DEFAULT         (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) 
01957 #define PRS_SWPULSE_CH3PULSE                 (0x1UL << 3)                         
01958 #define _PRS_SWPULSE_CH3PULSE_SHIFT          3                                    
01959 #define _PRS_SWPULSE_CH3PULSE_MASK           0x8UL                                
01960 #define _PRS_SWPULSE_CH3PULSE_DEFAULT        0x00000000UL                         
01961 #define PRS_SWPULSE_CH3PULSE_DEFAULT         (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) 
01963 /* Bit fields for PRS SWLEVEL */
01964 #define _PRS_SWLEVEL_RESETVALUE              0x00000000UL                         
01965 #define _PRS_SWLEVEL_MASK                    0x0000000FUL                         
01966 #define PRS_SWLEVEL_CH0LEVEL                 (0x1UL << 0)                         
01967 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT          0                                    
01968 #define _PRS_SWLEVEL_CH0LEVEL_MASK           0x1UL                                
01969 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT        0x00000000UL                         
01970 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT         (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) 
01971 #define PRS_SWLEVEL_CH1LEVEL                 (0x1UL << 1)                         
01972 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT          1                                    
01973 #define _PRS_SWLEVEL_CH1LEVEL_MASK           0x2UL                                
01974 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT        0x00000000UL                         
01975 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT         (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) 
01976 #define PRS_SWLEVEL_CH2LEVEL                 (0x1UL << 2)                         
01977 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT          2                                    
01978 #define _PRS_SWLEVEL_CH2LEVEL_MASK           0x4UL                                
01979 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT        0x00000000UL                         
01980 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT         (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) 
01981 #define PRS_SWLEVEL_CH3LEVEL                 (0x1UL << 3)                         
01982 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT          3                                    
01983 #define _PRS_SWLEVEL_CH3LEVEL_MASK           0x8UL                                
01984 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT        0x00000000UL                         
01985 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT         (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) 
01987 /* Bit fields for PRS ROUTE */
01988 #define _PRS_ROUTE_RESETVALUE                0x00000000UL                       
01989 #define _PRS_ROUTE_MASK                      0x0000070FUL                       
01990 #define PRS_ROUTE_CH0PEN                     (0x1UL << 0)                       
01991 #define _PRS_ROUTE_CH0PEN_SHIFT              0                                  
01992 #define _PRS_ROUTE_CH0PEN_MASK               0x1UL                              
01993 #define _PRS_ROUTE_CH0PEN_DEFAULT            0x00000000UL                       
01994 #define PRS_ROUTE_CH0PEN_DEFAULT             (_PRS_ROUTE_CH0PEN_DEFAULT << 0)   
01995 #define PRS_ROUTE_CH1PEN                     (0x1UL << 1)                       
01996 #define _PRS_ROUTE_CH1PEN_SHIFT              1                                  
01997 #define _PRS_ROUTE_CH1PEN_MASK               0x2UL                              
01998 #define _PRS_ROUTE_CH1PEN_DEFAULT            0x00000000UL                       
01999 #define PRS_ROUTE_CH1PEN_DEFAULT             (_PRS_ROUTE_CH1PEN_DEFAULT << 1)   
02000 #define PRS_ROUTE_CH2PEN                     (0x1UL << 2)                       
02001 #define _PRS_ROUTE_CH2PEN_SHIFT              2                                  
02002 #define _PRS_ROUTE_CH2PEN_MASK               0x4UL                              
02003 #define _PRS_ROUTE_CH2PEN_DEFAULT            0x00000000UL                       
02004 #define PRS_ROUTE_CH2PEN_DEFAULT             (_PRS_ROUTE_CH2PEN_DEFAULT << 2)   
02005 #define PRS_ROUTE_CH3PEN                     (0x1UL << 3)                       
02006 #define _PRS_ROUTE_CH3PEN_SHIFT              3                                  
02007 #define _PRS_ROUTE_CH3PEN_MASK               0x8UL                              
02008 #define _PRS_ROUTE_CH3PEN_DEFAULT            0x00000000UL                       
02009 #define PRS_ROUTE_CH3PEN_DEFAULT             (_PRS_ROUTE_CH3PEN_DEFAULT << 3)   
02010 #define _PRS_ROUTE_LOCATION_SHIFT            8                                  
02011 #define _PRS_ROUTE_LOCATION_MASK             0x700UL                            
02012 #define _PRS_ROUTE_LOCATION_LOC0             0x00000000UL                       
02013 #define _PRS_ROUTE_LOCATION_DEFAULT          0x00000000UL                       
02014 #define _PRS_ROUTE_LOCATION_LOC1             0x00000001UL                       
02015 #define _PRS_ROUTE_LOCATION_LOC2             0x00000002UL                       
02016 #define PRS_ROUTE_LOCATION_LOC0              (_PRS_ROUTE_LOCATION_LOC0 << 8)    
02017 #define PRS_ROUTE_LOCATION_DEFAULT           (_PRS_ROUTE_LOCATION_DEFAULT << 8) 
02018 #define PRS_ROUTE_LOCATION_LOC1              (_PRS_ROUTE_LOCATION_LOC1 << 8)    
02019 #define PRS_ROUTE_LOCATION_LOC2              (_PRS_ROUTE_LOCATION_LOC2 << 8)    
02021 /* Bit fields for PRS CH_CTRL */
02022 #define _PRS_CH_CTRL_RESETVALUE              0x00000000UL                             
02023 #define _PRS_CH_CTRL_MASK                    0x133F0007UL                             
02024 #define _PRS_CH_CTRL_SIGSEL_SHIFT            0                                        
02025 #define _PRS_CH_CTRL_SIGSEL_MASK             0x7UL                                    
02026 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT          0x00000000UL                             
02027 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT         0x00000000UL                             
02028 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX       0x00000000UL                             
02029 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF         0x00000000UL                             
02030 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF         0x00000000UL                             
02031 #define _PRS_CH_CTRL_SIGSEL_RTCOF            0x00000000UL                             
02032 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0         0x00000000UL                             
02033 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8         0x00000000UL                             
02034 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC         0x00000000UL                             
02035 #define _PRS_CH_CTRL_SIGSEL_USART1TXC        0x00000001UL                             
02036 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF         0x00000001UL                             
02037 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF         0x00000001UL                             
02038 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0         0x00000001UL                             
02039 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1         0x00000001UL                             
02040 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9         0x00000001UL                             
02041 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV    0x00000002UL                             
02042 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0        0x00000002UL                             
02043 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0        0x00000002UL                             
02044 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1         0x00000002UL                             
02045 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2         0x00000002UL                             
02046 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10        0x00000002UL                             
02047 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1        0x00000003UL                             
02048 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1        0x00000003UL                             
02049 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3         0x00000003UL                             
02050 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11        0x00000003UL                             
02051 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2        0x00000004UL                             
02052 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2        0x00000004UL                             
02053 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4         0x00000004UL                             
02054 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12        0x00000004UL                             
02055 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5         0x00000005UL                             
02056 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13        0x00000005UL                             
02057 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6         0x00000006UL                             
02058 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14        0x00000006UL                             
02059 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7         0x00000007UL                             
02060 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15        0x00000007UL                             
02061 #define PRS_CH_CTRL_SIGSEL_VCMPOUT           (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0)       
02062 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT          (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0)      
02063 #define PRS_CH_CTRL_SIGSEL_USART1IRTX        (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0)    
02064 #define PRS_CH_CTRL_SIGSEL_TIMER0UF          (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0)      
02065 #define PRS_CH_CTRL_SIGSEL_TIMER1UF          (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0)      
02066 #define PRS_CH_CTRL_SIGSEL_RTCOF             (_PRS_CH_CTRL_SIGSEL_RTCOF << 0)         
02067 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0          (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0)      
02068 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8          (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0)      
02069 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC          (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0)      
02070 #define PRS_CH_CTRL_SIGSEL_USART1TXC         (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0)     
02071 #define PRS_CH_CTRL_SIGSEL_TIMER0OF          (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0)      
02072 #define PRS_CH_CTRL_SIGSEL_TIMER1OF          (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0)      
02073 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0          (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0)      
02074 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1          (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0)      
02075 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9          (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0)      
02076 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV     (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) 
02077 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0         (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0)     
02078 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0         (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0)     
02079 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1          (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0)      
02080 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2          (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0)      
02081 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10         (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0)     
02082 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1         (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0)     
02083 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1         (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0)     
02084 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3          (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0)      
02085 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11         (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0)     
02086 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2         (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0)     
02087 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2         (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0)     
02088 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4          (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0)      
02089 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12         (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0)     
02090 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5          (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0)      
02091 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13         (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0)     
02092 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6          (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0)      
02093 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14         (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0)     
02094 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7          (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0)      
02095 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15         (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0)     
02096 #define _PRS_CH_CTRL_SOURCESEL_SHIFT         16                                       
02097 #define _PRS_CH_CTRL_SOURCESEL_MASK          0x3F0000UL                               
02098 #define _PRS_CH_CTRL_SOURCESEL_NONE          0x00000000UL                             
02099 #define _PRS_CH_CTRL_SOURCESEL_VCMP          0x00000001UL                             
02100 #define _PRS_CH_CTRL_SOURCESEL_ACMP0         0x00000002UL                             
02101 #define _PRS_CH_CTRL_SOURCESEL_USART1        0x00000011UL                             
02102 #define _PRS_CH_CTRL_SOURCESEL_TIMER0        0x0000001CUL                             
02103 #define _PRS_CH_CTRL_SOURCESEL_TIMER1        0x0000001DUL                             
02104 #define _PRS_CH_CTRL_SOURCESEL_RTC           0x00000028UL                             
02105 #define _PRS_CH_CTRL_SOURCESEL_GPIOL         0x00000030UL                             
02106 #define _PRS_CH_CTRL_SOURCESEL_GPIOH         0x00000031UL                             
02107 #define _PRS_CH_CTRL_SOURCESEL_PCNT0         0x00000036UL                             
02108 #define PRS_CH_CTRL_SOURCESEL_NONE           (_PRS_CH_CTRL_SOURCESEL_NONE << 16)      
02109 #define PRS_CH_CTRL_SOURCESEL_VCMP           (_PRS_CH_CTRL_SOURCESEL_VCMP << 16)      
02110 #define PRS_CH_CTRL_SOURCESEL_ACMP0          (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16)     
02111 #define PRS_CH_CTRL_SOURCESEL_USART1         (_PRS_CH_CTRL_SOURCESEL_USART1 << 16)    
02112 #define PRS_CH_CTRL_SOURCESEL_TIMER0         (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16)    
02113 #define PRS_CH_CTRL_SOURCESEL_TIMER1         (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16)    
02114 #define PRS_CH_CTRL_SOURCESEL_RTC            (_PRS_CH_CTRL_SOURCESEL_RTC << 16)       
02115 #define PRS_CH_CTRL_SOURCESEL_GPIOL          (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16)     
02116 #define PRS_CH_CTRL_SOURCESEL_GPIOH          (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16)     
02117 #define PRS_CH_CTRL_SOURCESEL_PCNT0          (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16)     
02118 #define _PRS_CH_CTRL_EDSEL_SHIFT             24                                       
02119 #define _PRS_CH_CTRL_EDSEL_MASK              0x3000000UL                              
02120 #define _PRS_CH_CTRL_EDSEL_DEFAULT           0x00000000UL                             
02121 #define _PRS_CH_CTRL_EDSEL_OFF               0x00000000UL                             
02122 #define _PRS_CH_CTRL_EDSEL_POSEDGE           0x00000001UL                             
02123 #define _PRS_CH_CTRL_EDSEL_NEGEDGE           0x00000002UL                             
02124 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES         0x00000003UL                             
02125 #define PRS_CH_CTRL_EDSEL_DEFAULT            (_PRS_CH_CTRL_EDSEL_DEFAULT << 24)       
02126 #define PRS_CH_CTRL_EDSEL_OFF                (_PRS_CH_CTRL_EDSEL_OFF << 24)           
02127 #define PRS_CH_CTRL_EDSEL_POSEDGE            (_PRS_CH_CTRL_EDSEL_POSEDGE << 24)       
02128 #define PRS_CH_CTRL_EDSEL_NEGEDGE            (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24)       
02129 #define PRS_CH_CTRL_EDSEL_BOTHEDGES          (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24)     
02130 #define PRS_CH_CTRL_ASYNC                    (0x1UL << 28)                            
02131 #define _PRS_CH_CTRL_ASYNC_SHIFT             28                                       
02132 #define _PRS_CH_CTRL_ASYNC_MASK              0x10000000UL                             
02133 #define _PRS_CH_CTRL_ASYNC_DEFAULT           0x00000000UL                             
02134 #define PRS_CH_CTRL_ASYNC_DEFAULT            (_PRS_CH_CTRL_ASYNC_DEFAULT << 28)       
02140 /**************************************************************************/
02144 #define MSC_UNLOCK_CODE      0x1B71 
02145 #define EMU_UNLOCK_CODE      0xADE8 
02146 #define CMU_UNLOCK_CODE      0x580E 
02147 #define TIMER_UNLOCK_CODE    0xCE80 
02148 #define GPIO_UNLOCK_CODE     0xA534 
02154 /**************************************************************************/
02159 #include "efm32zg_af_ports.h"
02160 #include "efm32zg_af_pins.h"
02161 
02164 /**************************************************************************/
02177 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
02178   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
02179 
02184 #ifdef __cplusplus
02185 }
02186 #endif
02187 #endif /* __SILICON_LABS_EFM32ZG108F8_H__ */