release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32ZG/Include/efm32zg210f4.h File Reference

CMSIS Cortex-M Peripheral Access Layer Header File for EFM32ZG210F4. More...

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Defines

#define __MPU_PRESENT   0
#define __VTOR_PRESENT   1
#define __NVIC_PRIO_BITS   2
#define __Vendor_SysTickConfig   0
#define _EFM32_ZERO_FAMILY   1
#define _EFM_DEVICE
#define _SILICON_LABS_32B_PLATFORM_1
#define _SILICON_LABS_32B_PLATFORM   1
#define EFM32ZG210F4   1
#define PART_NUMBER   "EFM32ZG210F4"
#define FLASH_MEM_BASE   ((uint32_t) 0x0UL)
#define FLASH_MEM_SIZE   ((uint32_t) 0x10000000UL)
#define FLASH_MEM_END   ((uint32_t) 0xFFFFFFFUL)
#define FLASH_MEM_BITS   ((uint32_t) 0x28UL)
#define AES_MEM_BASE   ((uint32_t) 0x400E0000UL)
#define AES_MEM_SIZE   ((uint32_t) 0x400UL)
#define AES_MEM_END   ((uint32_t) 0x400E03FFUL)
#define AES_MEM_BITS   ((uint32_t) 0x10UL)
#define PER_MEM_BASE   ((uint32_t) 0x40000000UL)
#define PER_MEM_SIZE   ((uint32_t) 0xE0000UL)
#define PER_MEM_END   ((uint32_t) 0x400DFFFFUL)
#define PER_MEM_BITS   ((uint32_t) 0x20UL)
#define RAM_MEM_BASE   ((uint32_t) 0x20000000UL)
#define RAM_MEM_SIZE   ((uint32_t) 0x40000UL)
#define RAM_MEM_END   ((uint32_t) 0x2003FFFFUL)
#define RAM_MEM_BITS   ((uint32_t) 0x18UL)
#define RAM_CODE_MEM_BASE   ((uint32_t) 0x10000000UL)
#define RAM_CODE_MEM_SIZE   ((uint32_t) 0x20000UL)
#define RAM_CODE_MEM_END   ((uint32_t) 0x1001FFFFUL)
#define RAM_CODE_MEM_BITS   ((uint32_t) 0x17UL)
#define FLASH_BASE   (0x00000000UL)
#define FLASH_SIZE   (0x00001000UL)
#define FLASH_PAGE_SIZE   1024
#define SRAM_BASE   (0x20000000UL)
#define SRAM_SIZE   (0x00000800UL)
#define __CM0PLUS_REV   0x001
#define PRS_CHAN_COUNT   4
#define DMA_CHAN_COUNT   4
#define AFCHAN_MAX   33
#define AFCHANLOC_MAX   7
#define AFACHAN_MAX   25
#define TIMER_PRESENT
#define TIMER_COUNT   2
#define ACMP_PRESENT
#define ACMP_COUNT   1
#define USART_PRESENT
#define USART_COUNT   1
#define IDAC_PRESENT
#define IDAC_COUNT   1
#define ADC_PRESENT
#define ADC_COUNT   1
#define LEUART_PRESENT
#define LEUART_COUNT   1
#define PCNT_PRESENT
#define PCNT_COUNT   1
#define I2C_PRESENT
#define I2C_COUNT   1
#define AES_PRESENT
#define AES_COUNT   1
#define DMA_PRESENT
#define DMA_COUNT   1
#define LE_PRESENT
#define LE_COUNT   1
#define MSC_PRESENT
#define MSC_COUNT   1
#define EMU_PRESENT
#define EMU_COUNT   1
#define RMU_PRESENT
#define RMU_COUNT   1
#define CMU_PRESENT
#define CMU_COUNT   1
#define PRS_PRESENT
#define PRS_COUNT   1
#define GPIO_PRESENT
#define GPIO_COUNT   1
#define VCMP_PRESENT
#define VCMP_COUNT   1
#define RTC_PRESENT
#define RTC_COUNT   1
#define HFXTAL_PRESENT
#define HFXTAL_COUNT   1
#define LFXTAL_PRESENT
#define LFXTAL_COUNT   1
#define WDOG_PRESENT
#define WDOG_COUNT   1
#define DBG_PRESENT
#define DBG_COUNT   1
#define BOOTLOADER_PRESENT
#define BOOTLOADER_COUNT   1
#define ANALOG_PRESENT
#define ANALOG_COUNT   1
#define ARM_MATH_CM0PLUS
#define AES_BASE   (0x400E0000UL)
#define DMA_BASE   (0x400C2000UL)
#define MSC_BASE   (0x400C0000UL)
#define EMU_BASE   (0x400C6000UL)
#define RMU_BASE   (0x400CA000UL)
#define CMU_BASE   (0x400C8000UL)
#define TIMER0_BASE   (0x40010000UL)
#define TIMER1_BASE   (0x40010400UL)
#define ACMP0_BASE   (0x40001000UL)
#define USART1_BASE   (0x4000C400UL)
#define PRS_BASE   (0x400CC000UL)
#define IDAC0_BASE   (0x40004000UL)
#define GPIO_BASE   (0x40006000UL)
#define VCMP_BASE   (0x40000000UL)
#define ADC0_BASE   (0x40002000UL)
#define LEUART0_BASE   (0x40084000UL)
#define PCNT0_BASE   (0x40086000UL)
#define I2C0_BASE   (0x4000A000UL)
#define RTC_BASE   (0x40080000UL)
#define WDOG_BASE   (0x40088000UL)
#define CALIBRATE_BASE   (0x0FE08000UL)
#define DEVINFO_BASE   (0x0FE081B0UL)
#define ROMTABLE_BASE   (0xF00FFFD0UL)
#define LOCKBITS_BASE   (0x0FE04000UL)
#define USERDATA_BASE   (0x0FE00000UL)
#define AES   ((AES_TypeDef *) AES_BASE)
#define DMA   ((DMA_TypeDef *) DMA_BASE)
#define MSC   ((MSC_TypeDef *) MSC_BASE)
#define EMU   ((EMU_TypeDef *) EMU_BASE)
#define RMU   ((RMU_TypeDef *) RMU_BASE)
#define CMU   ((CMU_TypeDef *) CMU_BASE)
#define TIMER0   ((TIMER_TypeDef *) TIMER0_BASE)
#define TIMER1   ((TIMER_TypeDef *) TIMER1_BASE)
#define ACMP0   ((ACMP_TypeDef *) ACMP0_BASE)
#define USART1   ((USART_TypeDef *) USART1_BASE)
#define PRS   ((PRS_TypeDef *) PRS_BASE)
#define IDAC0   ((IDAC_TypeDef *) IDAC0_BASE)
#define GPIO   ((GPIO_TypeDef *) GPIO_BASE)
#define VCMP   ((VCMP_TypeDef *) VCMP_BASE)
#define ADC0   ((ADC_TypeDef *) ADC0_BASE)
#define LEUART0   ((LEUART_TypeDef *) LEUART0_BASE)
#define PCNT0   ((PCNT_TypeDef *) PCNT0_BASE)
#define I2C0   ((I2C_TypeDef *) I2C0_BASE)
#define RTC   ((RTC_TypeDef *) RTC_BASE)
#define WDOG   ((WDOG_TypeDef *) WDOG_BASE)
#define CALIBRATE   ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
#define DEVINFO   ((DEVINFO_TypeDef *) DEVINFO_BASE)
#define ROMTABLE   ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
#define MSC_UNLOCK_CODE   0x1B71
#define EMU_UNLOCK_CODE   0xADE8
#define CMU_UNLOCK_CODE   0x580E
#define TIMER_UNLOCK_CODE   0xCE80
#define GPIO_UNLOCK_CODE   0xA534
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
 Set the value of a bit field within a register.

Typedefs

typedef enum IRQn IRQn_Type

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  SVCall_IRQn = -5,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  DMA_IRQn = 0,
  GPIO_EVEN_IRQn = 1,
  TIMER0_IRQn = 2,
  ACMP0_IRQn = 3,
  ADC0_IRQn = 4,
  I2C0_IRQn = 5,
  GPIO_ODD_IRQn = 6,
  TIMER1_IRQn = 7,
  USART1_RX_IRQn = 8,
  USART1_TX_IRQn = 9,
  LEUART0_IRQn = 10,
  PCNT0_IRQn = 11,
  RTC_IRQn = 12,
  CMU_IRQn = 13,
  VCMP_IRQn = 14,
  MSC_IRQn = 15,
  AES_IRQn = 16
}


Detailed Description

CMSIS Cortex-M Peripheral Access Layer Header File for EFM32ZG210F4.

Version:
4.0.0

License

(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software.
2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.

DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. has no obligation to support this Software. Silicon Laboratories, Inc. is providing the Software "AS IS", with no express or implied warranties of any kind, including, but not limited to, any implied warranties of merchantability or fitness for any particular purpose or warranties against infringement of any proprietary rights of a third party.

Silicon Laboratories, Inc. will not be liable for any consequential, incidental, or special damages, or any other relief, or for any claim by any third party, arising from your use of this Software.

Definition in file efm32zg210f4.h.