00001
00032
00037 typedef struct
00038 {
00039 __I uint32_t STATUS;
00040 __O uint32_t CONFIG;
00041 __IO uint32_t CTRLBASE;
00042 __I uint32_t ALTCTRLBASE;
00043 __I uint32_t CHWAITSTATUS;
00044 __O uint32_t CHSWREQ;
00045 __IO uint32_t CHUSEBURSTS;
00046 __O uint32_t CHUSEBURSTC;
00047 __IO uint32_t CHREQMASKS;
00048 __O uint32_t CHREQMASKC;
00049 __IO uint32_t CHENS;
00050 __O uint32_t CHENC;
00051 __IO uint32_t CHALTS;
00052 __O uint32_t CHALTC;
00053 __IO uint32_t CHPRIS;
00054 __O uint32_t CHPRIC;
00055 uint32_t RESERVED0[3];
00056 __IO uint32_t ERRORC;
00058 uint32_t RESERVED1[880];
00059 __I uint32_t CHREQSTATUS;
00060 uint32_t RESERVED2[1];
00061 __I uint32_t CHSREQSTATUS;
00063 uint32_t RESERVED3[121];
00064 __I uint32_t IF;
00065 __IO uint32_t IFS;
00066 __IO uint32_t IFC;
00067 __IO uint32_t IEN;
00069 uint32_t RESERVED4[60];
00070 DMA_CH_TypeDef CH[4];
00071 } DMA_TypeDef;
00073
00078
00079 #define _DMA_STATUS_RESETVALUE 0x10030000UL
00080 #define _DMA_STATUS_MASK 0x001F00F1UL
00081 #define DMA_STATUS_EN (0x1UL << 0)
00082 #define _DMA_STATUS_EN_SHIFT 0
00083 #define _DMA_STATUS_EN_MASK 0x1UL
00084 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL
00085 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0)
00086 #define _DMA_STATUS_STATE_SHIFT 4
00087 #define _DMA_STATUS_STATE_MASK 0xF0UL
00088 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL
00089 #define _DMA_STATUS_STATE_IDLE 0x00000000UL
00090 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL
00091 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL
00092 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL
00093 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL
00094 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL
00095 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL
00096 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL
00097 #define _DMA_STATUS_STATE_STALLED 0x00000008UL
00098 #define _DMA_STATUS_STATE_DONE 0x00000009UL
00099 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL
00100 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4)
00101 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4)
00102 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4)
00103 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4)
00104 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4)
00105 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4)
00106 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4)
00107 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4)
00108 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4)
00109 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4)
00110 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4)
00111 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4)
00112 #define _DMA_STATUS_CHNUM_SHIFT 16
00113 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL
00114 #define _DMA_STATUS_CHNUM_DEFAULT 0x00000003UL
00115 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16)
00117
00118 #define _DMA_CONFIG_RESETVALUE 0x00000000UL
00119 #define _DMA_CONFIG_MASK 0x00000021UL
00120 #define DMA_CONFIG_EN (0x1UL << 0)
00121 #define _DMA_CONFIG_EN_SHIFT 0
00122 #define _DMA_CONFIG_EN_MASK 0x1UL
00123 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL
00124 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0)
00125 #define DMA_CONFIG_CHPROT (0x1UL << 5)
00126 #define _DMA_CONFIG_CHPROT_SHIFT 5
00127 #define _DMA_CONFIG_CHPROT_MASK 0x20UL
00128 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL
00129 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5)
00131
00132 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL
00133 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL
00134 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0
00135 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL
00136 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL
00137 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0)
00139
00140 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000040UL
00141 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00142 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0
00143 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL
00144 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000040UL
00145 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0)
00147
00148 #define _DMA_CHWAITSTATUS_RESETVALUE 0x0000000FUL
00149 #define _DMA_CHWAITSTATUS_MASK 0x0000000FUL
00150 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0)
00151 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0
00152 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL
00153 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL
00154 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0)
00155 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1)
00156 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1
00157 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL
00158 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL
00159 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1)
00160 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2)
00161 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2
00162 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL
00163 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL
00164 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2)
00165 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3)
00166 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3
00167 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL
00168 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL
00169 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3)
00171
00172 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL
00173 #define _DMA_CHSWREQ_MASK 0x0000000FUL
00174 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0)
00175 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0
00176 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL
00177 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL
00178 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0)
00179 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1)
00180 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1
00181 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL
00182 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL
00183 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1)
00184 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2)
00185 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2
00186 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL
00187 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL
00188 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2)
00189 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3)
00190 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3
00191 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL
00192 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL
00193 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3)
00195
00196 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL
00197 #define _DMA_CHUSEBURSTS_MASK 0x0000000FUL
00198 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0)
00199 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0
00200 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL
00201 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL
00202 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL
00203 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL
00204 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0)
00205 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0)
00206 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0)
00207 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1)
00208 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1
00209 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL
00210 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL
00211 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1)
00212 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2)
00213 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2
00214 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL
00215 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL
00216 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2)
00217 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3)
00218 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3
00219 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL
00220 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL
00221 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3)
00223
00224 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL
00225 #define _DMA_CHUSEBURSTC_MASK 0x0000000FUL
00226 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0)
00227 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0
00228 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL
00229 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL
00230 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0)
00231 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1)
00232 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1
00233 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL
00234 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL
00235 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1)
00236 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2)
00237 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2
00238 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL
00239 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL
00240 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2)
00241 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3)
00242 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3
00243 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL
00244 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL
00245 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3)
00247
00248 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL
00249 #define _DMA_CHREQMASKS_MASK 0x0000000FUL
00250 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0)
00251 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0
00252 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL
00253 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL
00254 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0)
00255 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1)
00256 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1
00257 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL
00258 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL
00259 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1)
00260 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2)
00261 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2
00262 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL
00263 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL
00264 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2)
00265 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3)
00266 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3
00267 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL
00268 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL
00269 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3)
00271
00272 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL
00273 #define _DMA_CHREQMASKC_MASK 0x0000000FUL
00274 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0)
00275 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0
00276 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL
00277 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL
00278 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0)
00279 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1)
00280 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1
00281 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL
00282 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL
00283 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1)
00284 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2)
00285 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2
00286 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL
00287 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL
00288 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2)
00289 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3)
00290 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3
00291 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL
00292 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL
00293 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3)
00295
00296 #define _DMA_CHENS_RESETVALUE 0x00000000UL
00297 #define _DMA_CHENS_MASK 0x0000000FUL
00298 #define DMA_CHENS_CH0ENS (0x1UL << 0)
00299 #define _DMA_CHENS_CH0ENS_SHIFT 0
00300 #define _DMA_CHENS_CH0ENS_MASK 0x1UL
00301 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL
00302 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0)
00303 #define DMA_CHENS_CH1ENS (0x1UL << 1)
00304 #define _DMA_CHENS_CH1ENS_SHIFT 1
00305 #define _DMA_CHENS_CH1ENS_MASK 0x2UL
00306 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL
00307 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1)
00308 #define DMA_CHENS_CH2ENS (0x1UL << 2)
00309 #define _DMA_CHENS_CH2ENS_SHIFT 2
00310 #define _DMA_CHENS_CH2ENS_MASK 0x4UL
00311 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL
00312 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2)
00313 #define DMA_CHENS_CH3ENS (0x1UL << 3)
00314 #define _DMA_CHENS_CH3ENS_SHIFT 3
00315 #define _DMA_CHENS_CH3ENS_MASK 0x8UL
00316 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL
00317 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3)
00319
00320 #define _DMA_CHENC_RESETVALUE 0x00000000UL
00321 #define _DMA_CHENC_MASK 0x0000000FUL
00322 #define DMA_CHENC_CH0ENC (0x1UL << 0)
00323 #define _DMA_CHENC_CH0ENC_SHIFT 0
00324 #define _DMA_CHENC_CH0ENC_MASK 0x1UL
00325 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL
00326 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0)
00327 #define DMA_CHENC_CH1ENC (0x1UL << 1)
00328 #define _DMA_CHENC_CH1ENC_SHIFT 1
00329 #define _DMA_CHENC_CH1ENC_MASK 0x2UL
00330 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL
00331 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1)
00332 #define DMA_CHENC_CH2ENC (0x1UL << 2)
00333 #define _DMA_CHENC_CH2ENC_SHIFT 2
00334 #define _DMA_CHENC_CH2ENC_MASK 0x4UL
00335 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL
00336 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2)
00337 #define DMA_CHENC_CH3ENC (0x1UL << 3)
00338 #define _DMA_CHENC_CH3ENC_SHIFT 3
00339 #define _DMA_CHENC_CH3ENC_MASK 0x8UL
00340 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL
00341 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3)
00343
00344 #define _DMA_CHALTS_RESETVALUE 0x00000000UL
00345 #define _DMA_CHALTS_MASK 0x0000000FUL
00346 #define DMA_CHALTS_CH0ALTS (0x1UL << 0)
00347 #define _DMA_CHALTS_CH0ALTS_SHIFT 0
00348 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL
00349 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL
00350 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0)
00351 #define DMA_CHALTS_CH1ALTS (0x1UL << 1)
00352 #define _DMA_CHALTS_CH1ALTS_SHIFT 1
00353 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL
00354 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL
00355 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1)
00356 #define DMA_CHALTS_CH2ALTS (0x1UL << 2)
00357 #define _DMA_CHALTS_CH2ALTS_SHIFT 2
00358 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL
00359 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL
00360 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2)
00361 #define DMA_CHALTS_CH3ALTS (0x1UL << 3)
00362 #define _DMA_CHALTS_CH3ALTS_SHIFT 3
00363 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL
00364 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL
00365 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3)
00367
00368 #define _DMA_CHALTC_RESETVALUE 0x00000000UL
00369 #define _DMA_CHALTC_MASK 0x0000000FUL
00370 #define DMA_CHALTC_CH0ALTC (0x1UL << 0)
00371 #define _DMA_CHALTC_CH0ALTC_SHIFT 0
00372 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL
00373 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL
00374 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0)
00375 #define DMA_CHALTC_CH1ALTC (0x1UL << 1)
00376 #define _DMA_CHALTC_CH1ALTC_SHIFT 1
00377 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL
00378 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL
00379 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1)
00380 #define DMA_CHALTC_CH2ALTC (0x1UL << 2)
00381 #define _DMA_CHALTC_CH2ALTC_SHIFT 2
00382 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL
00383 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL
00384 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2)
00385 #define DMA_CHALTC_CH3ALTC (0x1UL << 3)
00386 #define _DMA_CHALTC_CH3ALTC_SHIFT 3
00387 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL
00388 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL
00389 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3)
00391
00392 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL
00393 #define _DMA_CHPRIS_MASK 0x0000000FUL
00394 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0)
00395 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0
00396 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL
00397 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL
00398 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0)
00399 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1)
00400 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1
00401 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL
00402 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL
00403 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1)
00404 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2)
00405 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2
00406 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL
00407 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL
00408 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2)
00409 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3)
00410 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3
00411 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL
00412 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL
00413 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3)
00415
00416 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL
00417 #define _DMA_CHPRIC_MASK 0x0000000FUL
00418 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0)
00419 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0
00420 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL
00421 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL
00422 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0)
00423 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1)
00424 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1
00425 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL
00426 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL
00427 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1)
00428 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2)
00429 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2
00430 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL
00431 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL
00432 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2)
00433 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3)
00434 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3
00435 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL
00436 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL
00437 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3)
00439
00440 #define _DMA_ERRORC_RESETVALUE 0x00000000UL
00441 #define _DMA_ERRORC_MASK 0x00000001UL
00442 #define DMA_ERRORC_ERRORC (0x1UL << 0)
00443 #define _DMA_ERRORC_ERRORC_SHIFT 0
00444 #define _DMA_ERRORC_ERRORC_MASK 0x1UL
00445 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL
00446 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0)
00448
00449 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL
00450 #define _DMA_CHREQSTATUS_MASK 0x0000000FUL
00451 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0)
00452 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0
00453 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL
00454 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL
00455 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0)
00456 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1)
00457 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1
00458 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL
00459 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL
00460 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1)
00461 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2)
00462 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2
00463 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL
00464 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL
00465 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2)
00466 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3)
00467 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3
00468 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL
00469 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL
00470 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3)
00472
00473 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL
00474 #define _DMA_CHSREQSTATUS_MASK 0x0000000FUL
00475 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0)
00476 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0
00477 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL
00478 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL
00479 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0)
00480 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1)
00481 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1
00482 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL
00483 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL
00484 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1)
00485 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2)
00486 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2
00487 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL
00488 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL
00489 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2)
00490 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3)
00491 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3
00492 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL
00493 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL
00494 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3)
00496
00497 #define _DMA_IF_RESETVALUE 0x00000000UL
00498 #define _DMA_IF_MASK 0x8000000FUL
00499 #define DMA_IF_CH0DONE (0x1UL << 0)
00500 #define _DMA_IF_CH0DONE_SHIFT 0
00501 #define _DMA_IF_CH0DONE_MASK 0x1UL
00502 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL
00503 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0)
00504 #define DMA_IF_CH1DONE (0x1UL << 1)
00505 #define _DMA_IF_CH1DONE_SHIFT 1
00506 #define _DMA_IF_CH1DONE_MASK 0x2UL
00507 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL
00508 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1)
00509 #define DMA_IF_CH2DONE (0x1UL << 2)
00510 #define _DMA_IF_CH2DONE_SHIFT 2
00511 #define _DMA_IF_CH2DONE_MASK 0x4UL
00512 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL
00513 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2)
00514 #define DMA_IF_CH3DONE (0x1UL << 3)
00515 #define _DMA_IF_CH3DONE_SHIFT 3
00516 #define _DMA_IF_CH3DONE_MASK 0x8UL
00517 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL
00518 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3)
00519 #define DMA_IF_ERR (0x1UL << 31)
00520 #define _DMA_IF_ERR_SHIFT 31
00521 #define _DMA_IF_ERR_MASK 0x80000000UL
00522 #define _DMA_IF_ERR_DEFAULT 0x00000000UL
00523 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31)
00525
00526 #define _DMA_IFS_RESETVALUE 0x00000000UL
00527 #define _DMA_IFS_MASK 0x8000000FUL
00528 #define DMA_IFS_CH0DONE (0x1UL << 0)
00529 #define _DMA_IFS_CH0DONE_SHIFT 0
00530 #define _DMA_IFS_CH0DONE_MASK 0x1UL
00531 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL
00532 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0)
00533 #define DMA_IFS_CH1DONE (0x1UL << 1)
00534 #define _DMA_IFS_CH1DONE_SHIFT 1
00535 #define _DMA_IFS_CH1DONE_MASK 0x2UL
00536 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL
00537 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1)
00538 #define DMA_IFS_CH2DONE (0x1UL << 2)
00539 #define _DMA_IFS_CH2DONE_SHIFT 2
00540 #define _DMA_IFS_CH2DONE_MASK 0x4UL
00541 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL
00542 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2)
00543 #define DMA_IFS_CH3DONE (0x1UL << 3)
00544 #define _DMA_IFS_CH3DONE_SHIFT 3
00545 #define _DMA_IFS_CH3DONE_MASK 0x8UL
00546 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL
00547 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3)
00548 #define DMA_IFS_ERR (0x1UL << 31)
00549 #define _DMA_IFS_ERR_SHIFT 31
00550 #define _DMA_IFS_ERR_MASK 0x80000000UL
00551 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL
00552 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31)
00554
00555 #define _DMA_IFC_RESETVALUE 0x00000000UL
00556 #define _DMA_IFC_MASK 0x8000000FUL
00557 #define DMA_IFC_CH0DONE (0x1UL << 0)
00558 #define _DMA_IFC_CH0DONE_SHIFT 0
00559 #define _DMA_IFC_CH0DONE_MASK 0x1UL
00560 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL
00561 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0)
00562 #define DMA_IFC_CH1DONE (0x1UL << 1)
00563 #define _DMA_IFC_CH1DONE_SHIFT 1
00564 #define _DMA_IFC_CH1DONE_MASK 0x2UL
00565 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL
00566 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1)
00567 #define DMA_IFC_CH2DONE (0x1UL << 2)
00568 #define _DMA_IFC_CH2DONE_SHIFT 2
00569 #define _DMA_IFC_CH2DONE_MASK 0x4UL
00570 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL
00571 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2)
00572 #define DMA_IFC_CH3DONE (0x1UL << 3)
00573 #define _DMA_IFC_CH3DONE_SHIFT 3
00574 #define _DMA_IFC_CH3DONE_MASK 0x8UL
00575 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL
00576 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3)
00577 #define DMA_IFC_ERR (0x1UL << 31)
00578 #define _DMA_IFC_ERR_SHIFT 31
00579 #define _DMA_IFC_ERR_MASK 0x80000000UL
00580 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL
00581 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31)
00583
00584 #define _DMA_IEN_RESETVALUE 0x00000000UL
00585 #define _DMA_IEN_MASK 0x8000000FUL
00586 #define DMA_IEN_CH0DONE (0x1UL << 0)
00587 #define _DMA_IEN_CH0DONE_SHIFT 0
00588 #define _DMA_IEN_CH0DONE_MASK 0x1UL
00589 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL
00590 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0)
00591 #define DMA_IEN_CH1DONE (0x1UL << 1)
00592 #define _DMA_IEN_CH1DONE_SHIFT 1
00593 #define _DMA_IEN_CH1DONE_MASK 0x2UL
00594 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL
00595 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1)
00596 #define DMA_IEN_CH2DONE (0x1UL << 2)
00597 #define _DMA_IEN_CH2DONE_SHIFT 2
00598 #define _DMA_IEN_CH2DONE_MASK 0x4UL
00599 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL
00600 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2)
00601 #define DMA_IEN_CH3DONE (0x1UL << 3)
00602 #define _DMA_IEN_CH3DONE_SHIFT 3
00603 #define _DMA_IEN_CH3DONE_MASK 0x8UL
00604 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL
00605 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3)
00606 #define DMA_IEN_ERR (0x1UL << 31)
00607 #define _DMA_IEN_ERR_SHIFT 31
00608 #define _DMA_IEN_ERR_MASK 0x80000000UL
00609 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL
00610 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31)
00612
00613 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL
00614 #define _DMA_CH_CTRL_MASK 0x003F000FUL
00615 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0
00616 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL
00617 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL
00618 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL
00619 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL
00620 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL
00621 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL
00622 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL
00623 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL
00624 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL
00625 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL
00626 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL
00627 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL
00628 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL
00629 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL
00630 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL
00631 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL
00632 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL
00633 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL
00634 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL
00635 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL
00636 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL
00637 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL
00638 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL
00639 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL
00640 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL
00641 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL
00642 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0)
00643 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0)
00644 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0)
00645 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0)
00646 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0)
00647 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0)
00648 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0)
00649 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0)
00650 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0)
00651 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0)
00652 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0)
00653 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0)
00654 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0)
00655 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0)
00656 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0)
00657 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0)
00658 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0)
00659 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0)
00660 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0)
00661 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0)
00662 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0)
00663 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0)
00664 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0)
00665 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0)
00666 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0)
00667 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16
00668 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL
00669 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL
00670 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL
00671 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL
00672 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL
00673 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL
00674 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL
00675 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL
00676 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL
00677 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL
00678 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16)
00679 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16)
00680 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16)
00681 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16)
00682 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16)
00683 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16)
00684 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16)
00685 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16)
00686 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16)