EFM32ZG108F8
[Parts]


Modules

 EFM32ZG108F8 Core
 Processor and Core Peripheral Section.
 EFM32ZG108F8 Part
 EFM32ZG108F8 Peripheral TypeDefs
 Device Specific Peripheral Register Structures.
 EFM32ZG108F8 Peripheral Memory Map
 EFM32ZG108F8 Peripheral Declarations
 EFM32ZG108F8 Bit Fields
 EFM32ZG108F8 Alternate Function

Defines

#define ARM_MATH_CM0PLUS
#define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET)   REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
 Set the value of a bit field within a register.

Typedefs

typedef enum IRQn IRQn_Type

Enumerations

enum  IRQn {
  NonMaskableInt_IRQn = -14,
  HardFault_IRQn = -13,
  SVCall_IRQn = -5,
  PendSV_IRQn = -2,
  SysTick_IRQn = -1,
  DMA_IRQn = 0,
  GPIO_EVEN_IRQn = 1,
  TIMER0_IRQn = 2,
  ACMP0_IRQn = 3,
  I2C0_IRQn = 5,
  GPIO_ODD_IRQn = 6,
  TIMER1_IRQn = 7,
  USART1_RX_IRQn = 8,
  USART1_TX_IRQn = 9,
  LEUART0_IRQn = 10,
  PCNT0_IRQn = 11,
  RTC_IRQn = 12,
  CMU_IRQn = 13,
  VCMP_IRQn = 14,
  MSC_IRQn = 15
}

Define Documentation

#define SET_BIT_FIELD ( REG,
MASK,
VALUE,
OFFSET   )     REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));

Set the value of a bit field within a register.

Parameters:
REG The register to update
MASK The mask for the bit field to update
VALUE The value to write to the bit field
OFFSET The number of bits that the field is offset within the register. 0 (zero) means LSB.

Definition at line 2177 of file efm32zg108f8.h.


Typedef Documentation

typedef enum IRQn IRQn_Type

Interrupt Number Definition


Enumeration Type Documentation

enum IRQn

Interrupt Number Definition

Enumerator:
NonMaskableInt_IRQn  2 Cortex-M0+ Non Maskable Interrupt
HardFault_IRQn  3 Cortex-M0+ Hard Fault Interrupt
SVCall_IRQn  11 Cortex-M0+ SV Call Interrupt
PendSV_IRQn  14 Cortex-M0+ Pend SV Interrupt
SysTick_IRQn  15 Cortex-M0+ System Tick Interrupt
DMA_IRQn  16+0 EFM32 DMA Interrupt
GPIO_EVEN_IRQn  16+1 EFM32 GPIO_EVEN Interrupt
TIMER0_IRQn  16+2 EFM32 TIMER0 Interrupt
ACMP0_IRQn  16+3 EFM32 ACMP0 Interrupt
I2C0_IRQn  16+5 EFM32 I2C0 Interrupt
GPIO_ODD_IRQn  16+6 EFM32 GPIO_ODD Interrupt
TIMER1_IRQn  16+7 EFM32 TIMER1 Interrupt
USART1_RX_IRQn  16+8 EFM32 USART1_RX Interrupt
USART1_TX_IRQn  16+9 EFM32 USART1_TX Interrupt
LEUART0_IRQn  16+10 EFM32 LEUART0 Interrupt
PCNT0_IRQn  16+11 EFM32 PCNT0 Interrupt
RTC_IRQn  16+12 EFM32 RTC Interrupt
CMU_IRQn  16+13 EFM32 CMU Interrupt
VCMP_IRQn  16+14 EFM32 VCMP Interrupt
MSC_IRQn  16+15 EFM32 MSC Interrupt

Definition at line 52 of file efm32zg108f8.h.