release/EM_CMSIS_P1_4.0.0/Device/SiliconLabs/EFM32ZG/Include/efm32zg_rtc.h

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00001 /**************************************************************************/
00032 /**************************************************************************/
00037 typedef struct
00038 {
00039   __IO uint32_t CTRL;     
00040   __IO uint32_t CNT;      
00041   __IO uint32_t COMP0;    
00042   __IO uint32_t COMP1;    
00043   __I uint32_t  IF;       
00044   __IO uint32_t IFS;      
00045   __IO uint32_t IFC;      
00046   __IO uint32_t IEN;      
00048   __IO uint32_t FREEZE;   
00049   __I uint32_t  SYNCBUSY; 
00050 } RTC_TypeDef;            
00052 /**************************************************************************/
00057 /* Bit fields for RTC CTRL */
00058 #define _RTC_CTRL_RESETVALUE             0x00000000UL                      
00059 #define _RTC_CTRL_MASK                   0x00000007UL                      
00060 #define RTC_CTRL_EN                      (0x1UL << 0)                      
00061 #define _RTC_CTRL_EN_SHIFT               0                                 
00062 #define _RTC_CTRL_EN_MASK                0x1UL                             
00063 #define _RTC_CTRL_EN_DEFAULT             0x00000000UL                      
00064 #define RTC_CTRL_EN_DEFAULT              (_RTC_CTRL_EN_DEFAULT << 0)       
00065 #define RTC_CTRL_DEBUGRUN                (0x1UL << 1)                      
00066 #define _RTC_CTRL_DEBUGRUN_SHIFT         1                                 
00067 #define _RTC_CTRL_DEBUGRUN_MASK          0x2UL                             
00068 #define _RTC_CTRL_DEBUGRUN_DEFAULT       0x00000000UL                      
00069 #define RTC_CTRL_DEBUGRUN_DEFAULT        (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) 
00070 #define RTC_CTRL_COMP0TOP                (0x1UL << 2)                      
00071 #define _RTC_CTRL_COMP0TOP_SHIFT         2                                 
00072 #define _RTC_CTRL_COMP0TOP_MASK          0x4UL                             
00073 #define _RTC_CTRL_COMP0TOP_DEFAULT       0x00000000UL                      
00074 #define _RTC_CTRL_COMP0TOP_DISABLE       0x00000000UL                      
00075 #define _RTC_CTRL_COMP0TOP_ENABLE        0x00000001UL                      
00076 #define RTC_CTRL_COMP0TOP_DEFAULT        (_RTC_CTRL_COMP0TOP_DEFAULT << 2) 
00077 #define RTC_CTRL_COMP0TOP_DISABLE        (_RTC_CTRL_COMP0TOP_DISABLE << 2) 
00078 #define RTC_CTRL_COMP0TOP_ENABLE         (_RTC_CTRL_COMP0TOP_ENABLE << 2)  
00080 /* Bit fields for RTC CNT */
00081 #define _RTC_CNT_RESETVALUE              0x00000000UL                
00082 #define _RTC_CNT_MASK                    0x00FFFFFFUL                
00083 #define _RTC_CNT_CNT_SHIFT               0                           
00084 #define _RTC_CNT_CNT_MASK                0xFFFFFFUL                  
00085 #define _RTC_CNT_CNT_DEFAULT             0x00000000UL                
00086 #define RTC_CNT_CNT_DEFAULT              (_RTC_CNT_CNT_DEFAULT << 0) 
00088 /* Bit fields for RTC COMP0 */
00089 #define _RTC_COMP0_RESETVALUE            0x00000000UL                    
00090 #define _RTC_COMP0_MASK                  0x00FFFFFFUL                    
00091 #define _RTC_COMP0_COMP0_SHIFT           0                               
00092 #define _RTC_COMP0_COMP0_MASK            0xFFFFFFUL                      
00093 #define _RTC_COMP0_COMP0_DEFAULT         0x00000000UL                    
00094 #define RTC_COMP0_COMP0_DEFAULT          (_RTC_COMP0_COMP0_DEFAULT << 0) 
00096 /* Bit fields for RTC COMP1 */
00097 #define _RTC_COMP1_RESETVALUE            0x00000000UL                    
00098 #define _RTC_COMP1_MASK                  0x00FFFFFFUL                    
00099 #define _RTC_COMP1_COMP1_SHIFT           0                               
00100 #define _RTC_COMP1_COMP1_MASK            0xFFFFFFUL                      
00101 #define _RTC_COMP1_COMP1_DEFAULT         0x00000000UL                    
00102 #define RTC_COMP1_COMP1_DEFAULT          (_RTC_COMP1_COMP1_DEFAULT << 0) 
00104 /* Bit fields for RTC IF */
00105 #define _RTC_IF_RESETVALUE               0x00000000UL                 
00106 #define _RTC_IF_MASK                     0x00000007UL                 
00107 #define RTC_IF_OF                        (0x1UL << 0)                 
00108 #define _RTC_IF_OF_SHIFT                 0                            
00109 #define _RTC_IF_OF_MASK                  0x1UL                        
00110 #define _RTC_IF_OF_DEFAULT               0x00000000UL                 
00111 #define RTC_IF_OF_DEFAULT                (_RTC_IF_OF_DEFAULT << 0)    
00112 #define RTC_IF_COMP0                     (0x1UL << 1)                 
00113 #define _RTC_IF_COMP0_SHIFT              1                            
00114 #define _RTC_IF_COMP0_MASK               0x2UL                        
00115 #define _RTC_IF_COMP0_DEFAULT            0x00000000UL                 
00116 #define RTC_IF_COMP0_DEFAULT             (_RTC_IF_COMP0_DEFAULT << 1) 
00117 #define RTC_IF_COMP1                     (0x1UL << 2)                 
00118 #define _RTC_IF_COMP1_SHIFT              2                            
00119 #define _RTC_IF_COMP1_MASK               0x4UL                        
00120 #define _RTC_IF_COMP1_DEFAULT            0x00000000UL                 
00121 #define RTC_IF_COMP1_DEFAULT             (_RTC_IF_COMP1_DEFAULT << 2) 
00123 /* Bit fields for RTC IFS */
00124 #define _RTC_IFS_RESETVALUE              0x00000000UL                  
00125 #define _RTC_IFS_MASK                    0x00000007UL                  
00126 #define RTC_IFS_OF                       (0x1UL << 0)                  
00127 #define _RTC_IFS_OF_SHIFT                0                             
00128 #define _RTC_IFS_OF_MASK                 0x1UL                         
00129 #define _RTC_IFS_OF_DEFAULT              0x00000000UL                  
00130 #define RTC_IFS_OF_DEFAULT               (_RTC_IFS_OF_DEFAULT << 0)    
00131 #define RTC_IFS_COMP0                    (0x1UL << 1)                  
00132 #define _RTC_IFS_COMP0_SHIFT             1                             
00133 #define _RTC_IFS_COMP0_MASK              0x2UL                         
00134 #define _RTC_IFS_COMP0_DEFAULT           0x00000000UL                  
00135 #define RTC_IFS_COMP0_DEFAULT            (_RTC_IFS_COMP0_DEFAULT << 1) 
00136 #define RTC_IFS_COMP1                    (0x1UL << 2)                  
00137 #define _RTC_IFS_COMP1_SHIFT             2                             
00138 #define _RTC_IFS_COMP1_MASK              0x4UL                         
00139 #define _RTC_IFS_COMP1_DEFAULT           0x00000000UL                  
00140 #define RTC_IFS_COMP1_DEFAULT            (_RTC_IFS_COMP1_DEFAULT << 2) 
00142 /* Bit fields for RTC IFC */
00143 #define _RTC_IFC_RESETVALUE              0x00000000UL                  
00144 #define _RTC_IFC_MASK                    0x00000007UL                  
00145 #define RTC_IFC_OF                       (0x1UL << 0)                  
00146 #define _RTC_IFC_OF_SHIFT                0                             
00147 #define _RTC_IFC_OF_MASK                 0x1UL                         
00148 #define _RTC_IFC_OF_DEFAULT              0x00000000UL                  
00149 #define RTC_IFC_OF_DEFAULT               (_RTC_IFC_OF_DEFAULT << 0)    
00150 #define RTC_IFC_COMP0                    (0x1UL << 1)                  
00151 #define _RTC_IFC_COMP0_SHIFT             1                             
00152 #define _RTC_IFC_COMP0_MASK              0x2UL                         
00153 #define _RTC_IFC_COMP0_DEFAULT           0x00000000UL                  
00154 #define RTC_IFC_COMP0_DEFAULT            (_RTC_IFC_COMP0_DEFAULT << 1) 
00155 #define RTC_IFC_COMP1                    (0x1UL << 2)                  
00156 #define _RTC_IFC_COMP1_SHIFT             2                             
00157 #define _RTC_IFC_COMP1_MASK              0x4UL                         
00158 #define _RTC_IFC_COMP1_DEFAULT           0x00000000UL                  
00159 #define RTC_IFC_COMP1_DEFAULT            (_RTC_IFC_COMP1_DEFAULT << 2) 
00161 /* Bit fields for RTC IEN */
00162 #define _RTC_IEN_RESETVALUE              0x00000000UL                  
00163 #define _RTC_IEN_MASK                    0x00000007UL                  
00164 #define RTC_IEN_OF                       (0x1UL << 0)                  
00165 #define _RTC_IEN_OF_SHIFT                0                             
00166 #define _RTC_IEN_OF_MASK                 0x1UL                         
00167 #define _RTC_IEN_OF_DEFAULT              0x00000000UL                  
00168 #define RTC_IEN_OF_DEFAULT               (_RTC_IEN_OF_DEFAULT << 0)    
00169 #define RTC_IEN_COMP0                    (0x1UL << 1)                  
00170 #define _RTC_IEN_COMP0_SHIFT             1                             
00171 #define _RTC_IEN_COMP0_MASK              0x2UL                         
00172 #define _RTC_IEN_COMP0_DEFAULT           0x00000000UL                  
00173 #define RTC_IEN_COMP0_DEFAULT            (_RTC_IEN_COMP0_DEFAULT << 1) 
00174 #define RTC_IEN_COMP1                    (0x1UL << 2)                  
00175 #define _RTC_IEN_COMP1_SHIFT             2                             
00176 #define _RTC_IEN_COMP1_MASK              0x4UL                         
00177 #define _RTC_IEN_COMP1_DEFAULT           0x00000000UL                  
00178 #define RTC_IEN_COMP1_DEFAULT            (_RTC_IEN_COMP1_DEFAULT << 2) 
00180 /* Bit fields for RTC FREEZE */
00181 #define _RTC_FREEZE_RESETVALUE           0x00000000UL                         
00182 #define _RTC_FREEZE_MASK                 0x00000001UL                         
00183 #define RTC_FREEZE_REGFREEZE             (0x1UL << 0)                         
00184 #define _RTC_FREEZE_REGFREEZE_SHIFT      0                                    
00185 #define _RTC_FREEZE_REGFREEZE_MASK       0x1UL                                
00186 #define _RTC_FREEZE_REGFREEZE_DEFAULT    0x00000000UL                         
00187 #define _RTC_FREEZE_REGFREEZE_UPDATE     0x00000000UL                         
00188 #define _RTC_FREEZE_REGFREEZE_FREEZE     0x00000001UL                         
00189 #define RTC_FREEZE_REGFREEZE_DEFAULT     (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) 
00190 #define RTC_FREEZE_REGFREEZE_UPDATE      (_RTC_FREEZE_REGFREEZE_UPDATE << 0)  
00191 #define RTC_FREEZE_REGFREEZE_FREEZE      (_RTC_FREEZE_REGFREEZE_FREEZE << 0)  
00193 /* Bit fields for RTC SYNCBUSY */
00194 #define _RTC_SYNCBUSY_RESETVALUE         0x00000000UL                       
00195 #define _RTC_SYNCBUSY_MASK               0x00000007UL                       
00196 #define RTC_SYNCBUSY_CTRL                (0x1UL << 0)                       
00197 #define _RTC_SYNCBUSY_CTRL_SHIFT         0                                  
00198 #define _RTC_SYNCBUSY_CTRL_MASK          0x1UL                              
00199 #define _RTC_SYNCBUSY_CTRL_DEFAULT       0x00000000UL                       
00200 #define RTC_SYNCBUSY_CTRL_DEFAULT        (_RTC_SYNCBUSY_CTRL_DEFAULT << 0)  
00201 #define RTC_SYNCBUSY_COMP0               (0x1UL << 1)                       
00202 #define _RTC_SYNCBUSY_COMP0_SHIFT        1                                  
00203 #define _RTC_SYNCBUSY_COMP0_MASK         0x2UL                              
00204 #define _RTC_SYNCBUSY_COMP0_DEFAULT      0x00000000UL                       
00205 #define RTC_SYNCBUSY_COMP0_DEFAULT       (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) 
00206 #define RTC_SYNCBUSY_COMP1               (0x1UL << 2)                       
00207 #define _RTC_SYNCBUSY_COMP1_SHIFT        2                                  
00208 #define _RTC_SYNCBUSY_COMP1_MASK         0x4UL                              
00209 #define _RTC_SYNCBUSY_COMP1_DEFAULT      0x00000000UL                       
00210 #define RTC_SYNCBUSY_COMP1_DEFAULT       (_RTC_SYNCBUSY_COMP1_DEFAULT << 2)