32 #ifndef __SILICON_LABS_EM_CMU_H__
33 #define __SILICON_LABS_EM_CMU_H__
36 #if defined( CMU_PRESENT )
59 #define CMU_NOSEL_REG 0
60 #define CMU_HFCLKSEL_REG 1
61 #define CMU_LFACLKSEL_REG 2
62 #define CMU_LFBCLKSEL_REG 3
63 #define CMU_LFCCLKSEL_REG 4
64 #define CMU_LFECLKSEL_REG 5
65 #define CMU_DBGCLKSEL_REG 6
66 #define CMU_USBCCLKSEL_REG 7
68 #define CMU_SEL_REG_POS 0
69 #define CMU_SEL_REG_MASK 0xf
72 #define CMU_NODIV_REG 0
73 #define CMU_NOPRESC_REG 0
74 #define CMU_HFPRESC_REG 1
75 #define CMU_HFCLKDIV_REG 1
76 #define CMU_HFEXPPRESC_REG 2
77 #define CMU_HFCLKLEPRESC_REG 3
78 #define CMU_HFPERPRESC_REG 4
79 #define CMU_HFPERCLKDIV_REG 4
80 #define CMU_HFCOREPRESC_REG 5
81 #define CMU_HFCORECLKDIV_REG 5
82 #define CMU_HFRADIOPRESC_REG 6
83 #define CMU_LFAPRESC0_REG 7
84 #define CMU_LFBPRESC0_REG 8
85 #define CMU_LFEPRESC0_REG 9
87 #define CMU_PRESC_REG_POS 4
88 #define CMU_DIV_REG_POS CMU_PRESC_REG_POS
89 #define CMU_PRESC_REG_MASK 0xf
90 #define CMU_DIV_REG_MASK CMU_PRESC_REG_MASK
93 #define CMU_NO_EN_REG 0
94 #define CMU_CTRL_EN_REG 1
95 #define CMU_HFPERCLKDIV_EN_REG 1
96 #define CMU_HFPERCLKEN0_EN_REG 2
97 #define CMU_HFCORECLKEN0_EN_REG 3
98 #define CMU_HFRADIOCLKEN0_EN_REG 4
99 #define CMU_HFBUSCLKEN0_EN_REG 5
100 #define CMU_LFACLKEN0_EN_REG 6
101 #define CMU_LFBCLKEN0_EN_REG 7
102 #define CMU_LFCCLKEN0_EN_REG 8
103 #define CMU_LFECLKEN0_EN_REG 9
104 #define CMU_PCNT_EN_REG 10
106 #define CMU_EN_REG_POS 8
107 #define CMU_EN_REG_MASK 0xf
110 #define CMU_EN_BIT_POS 12
111 #define CMU_EN_BIT_MASK 0x1f
114 #define CMU_HF_CLK_BRANCH 0
115 #define CMU_HFCORE_CLK_BRANCH 1
116 #define CMU_HFPER_CLK_BRANCH 2
117 #define CMU_HFRADIO_CLK_BRANCH 3
118 #define CMU_HFBUS_CLK_BRANCH 4
119 #define CMU_HFEXP_CLK_BRANCH 5
120 #define CMU_DBG_CLK_BRANCH 6
121 #define CMU_AUX_CLK_BRANCH 7
122 #define CMU_RTC_CLK_BRANCH 8
123 #define CMU_RTCC_CLK_BRANCH 8
124 #define CMU_LETIMER_CLK_BRANCH 9
125 #define CMU_LETIMER0_CLK_BRANCH 9
126 #define CMU_LEUART0_CLK_BRANCH 10
127 #define CMU_LEUART1_CLK_BRANCH 11
128 #define CMU_LFA_CLK_BRANCH 12
129 #define CMU_LFB_CLK_BRANCH 13
130 #define CMU_LFC_CLK_BRANCH 14
131 #define CMU_LFE_CLK_BRANCH 15
132 #define CMU_USBC_CLK_BRANCH 16
133 #define CMU_USBLE_CLK_BRANCH 17
134 #define CMU_LCDPRE_CLK_BRANCH 18
135 #define CMU_LCD_CLK_BRANCH 19
136 #define CMU_LESENSE_CLK_BRANCH 20
138 #define CMU_CLK_BRANCH_POS 17
139 #define CMU_CLK_BRANCH_MASK 0x1f
148 #define cmuClkDiv_1 1
149 #define cmuClkDiv_2 2
150 #define cmuClkDiv_4 4
151 #define cmuClkDiv_8 8
152 #define cmuClkDiv_16 16
153 #define cmuClkDiv_32 32
154 #define cmuClkDiv_64 64
155 #define cmuClkDiv_128 128
156 #define cmuClkDiv_256 256
157 #define cmuClkDiv_512 512
158 #define cmuClkDiv_1024 1024
159 #define cmuClkDiv_2048 2048
160 #define cmuClkDiv_4096 4096
161 #define cmuClkDiv_8192 8192
162 #define cmuClkDiv_16384 16384
163 #define cmuClkDiv_32768 32768
166 typedef uint32_t CMU_ClkDiv_TypeDef;
168 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
170 typedef uint32_t CMU_ClkPresc_TypeDef;
173 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
182 #if defined( CMU_HFRCOCTRL_BAND_28MHZ )
183 cmuHFRCOBand_28MHz = _CMU_HFRCOCTRL_BAND_28MHZ,
188 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
197 #if defined( CMU_AUXHFRCOCTRL_BAND_28MHZ )
198 cmuAUXHFRCOBand_28MHz = _CMU_AUXHFRCOCTRL_BAND_28MHZ,
203 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
208 cmuUSHFRCOBand_24MHz = _CMU_USHFRCOCONF_BAND_24MHZ,
210 cmuUSHFRCOBand_48MHz = _CMU_USHFRCOCONF_BAND_48MHZ,
211 } CMU_USHFRCOBand_TypeDef;
214 #if defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
218 cmuHFRCOFreq_1M0Hz = 1000000U,
219 cmuHFRCOFreq_2M0Hz = 2000000U,
220 cmuHFRCOFreq_4M0Hz = 4000000U,
221 cmuHFRCOFreq_7M0Hz = 7000000U,
222 cmuHFRCOFreq_13M0Hz = 13000000U,
223 cmuHFRCOFreq_16M0Hz = 16000000U,
224 cmuHFRCOFreq_19M0Hz = 19000000U,
225 cmuHFRCOFreq_26M0Hz = 26000000U,
226 cmuHFRCOFreq_32M0Hz = 32000000U,
227 cmuHFRCOFreq_38M0Hz = 38000000U,
228 cmuHFRCOFreq_UserDefined = 0,
229 } CMU_HFRCOFreq_TypeDef;
230 #define CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz
231 #define CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz
234 #if defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
238 cmuAUXHFRCOFreq_1M0Hz = 1000000U,
239 cmuAUXHFRCOFreq_2M0Hz = 2000000U,
240 cmuAUXHFRCOFreq_4M0Hz = 4000000U,
241 cmuAUXHFRCOFreq_7M0Hz = 7000000U,
242 cmuAUXHFRCOFreq_13M0Hz = 13000000U,
243 cmuAUXHFRCOFreq_16M0Hz = 16000000U,
244 cmuAUXHFRCOFreq_19M0Hz = 19000000U,
245 cmuAUXHFRCOFreq_26M0Hz = 26000000U,
246 cmuAUXHFRCOFreq_32M0Hz = 32000000U,
247 cmuAUXHFRCOFreq_38M0Hz = 38000000U,
248 cmuAUXHFRCOFreq_UserDefined = 0,
249 } CMU_AUXHFRCOFreq_TypeDef;
250 #define CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz
251 #define CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz
263 #if defined( _CMU_CTRL_HFCLKDIV_MASK ) \
264 || defined( _CMU_HFPRESC_MASK )
265 cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS)
266 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
267 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
268 | (0 << CMU_EN_BIT_POS)
269 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
272 | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS)
273 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
274 | (0 << CMU_EN_BIT_POS)
275 | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS),
280 | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS)
281 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
282 | (0 << CMU_EN_BIT_POS)
283 | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS),
287 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
288 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
289 | (0 << CMU_EN_BIT_POS)
290 | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS),
292 #if defined( _CMU_HFEXPPRESC_MASK )
298 cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS)
299 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
300 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
301 | (0 << CMU_EN_BIT_POS)
302 | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS),
305 #
if defined( _CMU_HFBUSCLKEN0_MASK )
311 cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
312 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
313 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
314 | (0 << CMU_EN_BIT_POS)
315 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
317 #
if defined( CMU_HFBUSCLKEN0_CRYPTO )
319 cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
320 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
321 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
322 | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS)
323 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
326 #
if defined( CMU_HFBUSCLKEN0_LDMA )
328 cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
329 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
330 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
331 | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
332 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
335 #
if defined( CMU_HFBUSCLKEN0_GPCRC )
337 cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
338 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
339 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
340 | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
341 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
344 #
if defined( CMU_HFBUSCLKEN0_GPIO )
347 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
348 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
349 | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
350 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
355 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
356 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
357 | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS)
358 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
360 #if defined( CMU_HFBUSCLKEN0_PRS )
363 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
364 | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS)
365 | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
366 | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS),
375 #
if defined( _CMU_HFPRESC_MASK )
377 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
378 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
379 | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS)
380 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
383 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
384 | (CMU_HFPERCLKDIV_EN_REG << CMU_EN_REG_POS)
386 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
389 #if defined( CMU_HFPERCLKEN0_USART0 )
391 cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
392 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
393 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
394 | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS)
395 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
398 #
if defined( CMU_HFPERCLKEN0_USARTRF0 )
400 cmuClock_USARTRF0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
401 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
402 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
403 | (_CMU_HFPERCLKEN0_USARTRF0_SHIFT << CMU_EN_BIT_POS)
404 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
407 #
if defined( CMU_HFPERCLKEN0_USARTRF1 )
409 cmuClock_USARTRF1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
410 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
411 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
412 | (_CMU_HFPERCLKEN0_USARTRF1_SHIFT << CMU_EN_BIT_POS)
413 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
419 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
420 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
422 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
425 #
if defined( CMU_HFPERCLKEN0_USART2 )
427 cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
428 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
429 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
430 | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS)
431 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
434 #
if defined( CMU_HFPERCLKEN0_USART3 )
436 cmuClock_USART3 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
437 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
438 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
439 | (_CMU_HFPERCLKEN0_USART3_SHIFT << CMU_EN_BIT_POS)
440 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
443 #
if defined( CMU_HFPERCLKEN0_USART4 )
445 cmuClock_USART4 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
446 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
447 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
448 | (_CMU_HFPERCLKEN0_USART4_SHIFT << CMU_EN_BIT_POS)
449 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
452 #
if defined( CMU_HFPERCLKEN0_USART5 )
454 cmuClock_USART5 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
455 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
456 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
457 | (_CMU_HFPERCLKEN0_USART5_SHIFT << CMU_EN_BIT_POS)
458 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
462 #
if defined( CMU_HFPERCLKEN0_UART0 )
464 cmuClock_UART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
465 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
466 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
467 | (_CMU_HFPERCLKEN0_UART0_SHIFT << CMU_EN_BIT_POS)
468 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
471 #
if defined( CMU_HFPERCLKEN0_UART1 )
473 cmuClock_UART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
474 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
475 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
476 | (_CMU_HFPERCLKEN0_UART1_SHIFT << CMU_EN_BIT_POS)
477 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
483 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
484 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
486 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
492 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
493 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
495 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
498 #
if defined( CMU_HFPERCLKEN0_TIMER2 )
500 cmuClock_TIMER2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
501 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
502 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
503 | (_CMU_HFPERCLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
504 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
507 #
if defined( CMU_HFPERCLKEN0_TIMER3 )
509 cmuClock_TIMER3 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
510 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
511 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
512 | (_CMU_HFPERCLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
513 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
516 #
if defined( CMU_HFPERCLKEN0_CRYOTIMER )
518 cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
519 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
520 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
521 | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS)
522 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
528 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
529 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
531 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
534 #
if defined( CMU_HFPERCLKEN0_ACMP1 )
536 cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
537 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
538 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
539 | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS)
540 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
546 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
547 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
549 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
552 #
if defined( CMU_HFPERCLKEN0_DAC0 )
554 cmuClock_DAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
555 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
556 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
557 | (_CMU_HFPERCLKEN0_DAC0_SHIFT << CMU_EN_BIT_POS)
558 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
564 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
565 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
567 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
573 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
574 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
576 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
582 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
583 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
585 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
591 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
592 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
594 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
600 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
601 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
603 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
606 #
if defined( CMU_HFPERCLKEN0_I2C1 )
608 cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
609 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
610 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
611 | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
612 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
615 #
if defined( CMU_HFPERCLKEN0_I2C2 )
617 cmuClock_I2C2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
618 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
619 | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS)
620 | (_CMU_HFPERCLKEN0_I2C2_SHIFT << CMU_EN_BIT_POS)
621 | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
630 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
631 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
632 | (0 << CMU_EN_BIT_POS)
633 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
635 #if defined( CMU_HFCORECLKEN0_AES )
638 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
639 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
641 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
647 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
648 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
650 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
656 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
657 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
659 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
662 #
if defined( CMU_HFCORECLKEN0_EBI )
664 cmuClock_EBI = (CMU_NODIV_REG << CMU_DIV_REG_POS)
665 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
666 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
667 | (_CMU_HFCORECLKEN0_EBI_SHIFT << CMU_EN_BIT_POS)
668 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
671 #
if defined( CMU_HFCORECLKEN0_USBC )
673 cmuClock_USBC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
674 | (CMU_USBCCLKSEL_REG << CMU_SEL_REG_POS)
675 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
676 | (_CMU_HFCORECLKEN0_USBC_SHIFT << CMU_EN_BIT_POS)
677 | (CMU_USBC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
681 #
if defined( CMU_HFCORECLKEN0_USB )
683 cmuClock_USB = (CMU_NODIV_REG << CMU_DIV_REG_POS)
684 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
685 | (CMU_HFCORECLKEN0_EN_REG << CMU_EN_REG_POS)
686 | (_CMU_HFCORECLKEN0_USB_SHIFT << CMU_EN_BIT_POS)
687 | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
690 #
if defined( CMU_CTRL_HFRADIOCLKEN )
696 cmuClock_RADIO = (CMU_HFRADIOPRESC_REG << CMU_PRESC_REG_POS)
697 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
698 | (CMU_CTRL_EN_REG << CMU_EN_REG_POS)
699 | (_CMU_CTRL_HFRADIOCLKEN_SHIFT << CMU_EN_BIT_POS)
700 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
702 #
if defined( CMU_HFRADIOCLKEN0_MODEM )
704 cmuClock_MODEM = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
705 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
706 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
707 | (_CMU_HFRADIOCLKEN0_MODEM_SHIFT << CMU_EN_BIT_POS)
708 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
711 #
if defined( CMU_HFRADIOCLKEN0_PROTIMER )
713 cmuClock_PROTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
714 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
715 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
716 | (_CMU_HFRADIOCLKEN0_PROTIMER_SHIFT << CMU_EN_BIT_POS)
717 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
720 #
if defined( CMU_HFRADIOCLKEN0_CRC )
722 cmuClock_CRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
723 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
724 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
725 | (_CMU_HFRADIOCLKEN0_CRC_SHIFT << CMU_EN_BIT_POS)
726 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
729 #
if defined( CMU_HFRADIOCLKEN0_AGC )
731 cmuClock_AGC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
732 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
733 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
734 | (_CMU_HFRADIOCLKEN0_AGC_SHIFT << CMU_EN_BIT_POS)
735 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
738 #
if defined( CMU_HFRADIOCLKEN0_FRC )
740 cmuClock_FRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
741 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
742 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
743 | (_CMU_HFRADIOCLKEN0_FRC_SHIFT << CMU_EN_BIT_POS)
744 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
747 #
if defined( CMU_HFRADIOCLKEN0_SYNTH )
749 cmuClock_SYNTH = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
750 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
751 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
752 | (_CMU_HFRADIOCLKEN0_SYNTH_SHIFT << CMU_EN_BIT_POS)
753 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
756 #
if defined( CMU_HFRADIOCLKEN0_BUFC )
758 cmuClock_BUFC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
759 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
760 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
761 | (_CMU_HFRADIOCLKEN0_BUFC_SHIFT << CMU_EN_BIT_POS)
762 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
765 #
if defined( CMU_HFRADIOCLKEN0_RAC )
767 cmuClock_RAC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
768 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
769 | (CMU_HFRADIOCLKEN0_EN_REG << CMU_EN_REG_POS)
770 | (_CMU_HFRADIOCLKEN0_RAC_SHIFT << CMU_EN_BIT_POS)
771 | (CMU_HFRADIO_CLK_BRANCH << CMU_CLK_BRANCH_POS),
781 | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS)
782 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
783 | (0 << CMU_EN_BIT_POS)
784 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
786 #if defined( CMU_LFACLKEN0_RTC )
789 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
790 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
792 | (CMU_RTC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
795 #
if defined( CMU_LFACLKEN0_LETIMER0 )
797 cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
798 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
799 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
800 | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
801 | (CMU_LETIMER_CLK_BRANCH << CMU_CLK_BRANCH_POS),
804 #
if defined( CMU_LFACLKEN0_LCD )
806 cmuClock_LCDpre = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
807 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
808 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
809 | (0 << CMU_EN_BIT_POS)
810 | (CMU_LCDPRE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
814 cmuClock_LCD = (CMU_NODIV_REG << CMU_DIV_REG_POS)
815 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
816 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
817 | (_CMU_LFACLKEN0_LCD_SHIFT << CMU_EN_BIT_POS)
818 | (CMU_LCD_CLK_BRANCH << CMU_CLK_BRANCH_POS),
821 #if defined( CMU_PCNTCTRL_PCNT0CLKEN )
824 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
825 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
827 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
830 #
if defined( CMU_PCNTCTRL_PCNT1CLKEN )
832 cmuClock_PCNT1 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
833 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
834 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
835 | (_CMU_PCNTCTRL_PCNT1CLKEN_SHIFT << CMU_EN_BIT_POS)
836 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
839 #
if defined( CMU_PCNTCTRL_PCNT2CLKEN )
841 cmuClock_PCNT2 = (CMU_NODIV_REG << CMU_DIV_REG_POS)
842 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
843 | (CMU_PCNT_EN_REG << CMU_EN_REG_POS)
844 | (_CMU_PCNTCTRL_PCNT2CLKEN_SHIFT << CMU_EN_BIT_POS)
845 | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS),
847 #
if defined( CMU_LFACLKEN0_LESENSE )
849 cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS)
850 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
851 | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS)
852 | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
853 | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
862 | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS)
863 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
864 | (0 << CMU_EN_BIT_POS)
865 | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS),
867 #if defined( CMU_LFBCLKEN0_LEUART0 )
870 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
871 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
873 | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS),
876 #
if defined( CMU_LFBCLKEN0_LEUART1 )
878 cmuClock_LEUART1 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS)
879 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
880 | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS)
881 | (_CMU_LFBCLKEN0_LEUART1_SHIFT << CMU_EN_BIT_POS)
882 | (CMU_LEUART1_CLK_BRANCH << CMU_CLK_BRANCH_POS),
885 #
if defined( _CMU_LFCCLKEN0_MASK )
891 cmuClock_LFC = (CMU_NODIV_REG << CMU_DIV_REG_POS)
892 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
893 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
894 | (0 << CMU_EN_BIT_POS)
895 | (CMU_LFC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
897 #
if defined( CMU_LFCCLKEN0_USBLE )
899 cmuClock_USBLE = (CMU_NODIV_REG << CMU_DIV_REG_POS)
900 | (CMU_LFCCLKSEL_REG << CMU_SEL_REG_POS)
901 | (CMU_LFCCLKEN0_EN_REG << CMU_EN_REG_POS)
902 | (_CMU_LFCCLKEN0_USBLE_SHIFT << CMU_EN_BIT_POS)
903 | (CMU_USBLE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
907 #
if defined( _CMU_LFECLKEN0_MASK )
913 cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS)
914 | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS)
915 | (CMU_NO_EN_REG << CMU_EN_REG_POS)
916 | (0 << CMU_EN_BIT_POS)
917 | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS),
920 #
if defined ( CMU_LFECLKEN0_RTCC )
921 cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS)
922 | (CMU_NOSEL_REG << CMU_SEL_REG_POS)
923 | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS)
924 | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS)
925 | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS),
940 #if defined( _CMU_STATUS_USHFRCOENS_MASK )
943 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
958 #if defined( CMU_LFACLKSEL_LFA_HFCLKLE ) || defined( CMU_LFBCLKSEL_LFB_HFCLKLE )
964 #if defined( CMU_STATUS_USHFRCOENS )
967 #if defined( CMU_CMD_HFCLKSEL_USHFRCODIV2 )
968 cmuSelect_USHFRCODIV2,
970 #if defined( CMU_LFCLKSEL_LFAE_ULFRCO ) || defined( CMU_LFACLKSEL_LFA_ULFRCO )
980 #if defined( _CMU_LFXOCTRL_MASK )
988 } CMU_LFXOInit_TypeDef;
991 #define CMU_LFXOINIT_DEFAULT \
993 _CMU_LFXOCTRL_TUNING_DEFAULT, \
994 _CMU_LFXOCTRL_GAIN_DEFAULT, \
995 _CMU_LFXOCTRL_TIMEOUT_DEFAULT, \
999 #if defined( _CMU_HFXOCTRL_MASK )
1007 bool autoStartSelOnRacWakeup;
1008 uint16_t ctuneStartup;
1009 uint16_t ctuneSteadyState;
1010 uint8_t regIshStartup;
1011 uint8_t regIshSteadyState;
1012 uint8_t xoCoreBiasTrimStartup;
1013 uint8_t xoCoreBiasTrimSteadyState;
1014 uint8_t thresholdPeakDetect;
1015 uint8_t timeoutShuntOptimization;
1016 uint8_t timeoutPeakDetect;
1017 uint8_t timeoutWarmSteady;
1018 uint8_t timeoutSteady;
1019 uint8_t timeoutStartup;
1020 } CMU_HFXOInit_TypeDef;
1023 #if defined( _EFR_DEVICE )
1024 #define CMU_HFXOINIT_DEFAULT \
1030 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
1031 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
1032 _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT, \
1033 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1034 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
1037 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1039 _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT, \
1040 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
1041 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
1045 #define CMU_HFXOINIT_DEFAULT \
1051 _CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
1052 _CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
1053 _CMU_HFXOSTARTUPCTRL_REGISHWARM_DEFAULT, \
1054 _CMU_HFXOSTEADYSTATECTRL_REGISH_DEFAULT, \
1055 _CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT, \
1058 _CMU_HFXOTIMEOUTCTRL_SHUNTOPTTIMEOUT_DEFAULT, \
1060 _CMU_HFXOTIMEOUTCTRL_WARMSTEADYTIMEOUT_DEFAULT, \
1061 _CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_DEFAULT, \
1062 _CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
1072 #if defined( _CMU_AUXHFRCOCTRL_BAND_MASK )
1076 #elif defined( _CMU_AUXHFRCOCTRL_FREQRANGE_MASK )
1077 CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOFreqGet(
void);
1078 void CMU_AUXHFRCOFreqSet(CMU_AUXHFRCOFreq_TypeDef freqEnum);
1083 #if defined( _CMU_CALCTRL_UPSEL_MASK ) && defined( _CMU_CALCTRL_DOWNSEL_MASK )
1094 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1103 #if defined( _CMU_HFRCOCTRL_BAND_MASK )
1107 #elif defined( _CMU_HFRCOCTRL_FREQRANGE_MASK )
1108 CMU_HFRCOFreq_TypeDef CMU_HFRCOFreqGet(
void);
1109 void CMU_HFRCOFreqSet(CMU_HFRCOFreq_TypeDef freqEnum);
1115 #if defined( _CMU_HFXOCTRL_AUTOSTARTRDYSELRAC_MASK )
1116 void CMU_HFXOAutostartEnable(
bool enRACStartSel,
1118 bool enEM0EM1StartSel);
1121 #if defined( _CMU_HFXOCTRL_MASK )
1122 void CMU_HFXOInit(CMU_HFXOInit_TypeDef *hfxoInit);
1129 #if defined( _CMU_LFXOCTRL_MASK )
1130 void CMU_LFXOInit(CMU_LFXOInit_TypeDef *lfxoInit);
1139 #if defined( _CMU_USHFRCOCONF_BAND_MASK )
1140 CMU_USHFRCOBand_TypeDef CMU_USHFRCOBandGet(
void);
1141 void CMU_USHFRCOBandSet(CMU_USHFRCOBand_TypeDef band);
1145 #if defined( CMU_CALCTRL_CONT )
1173 #if defined( CMU_CMD_CALSTOP )
1201 EFM_ASSERT((div > 0U) && (div <= 32768U));
1204 log2 = (31U - __CLZ(div));
1288 return CMU->IF & ien;
1340 #if defined( _SILICON_LABS_32B_PLATFORM_2 )
1352 __STATIC_INLINE uint32_t CMU_PrescToLog2(CMU_ClkPresc_TypeDef presc)
1357 EFM_ASSERT(presc < 32768U);
1360 log2 = (31U - __CLZ(presc + 1));
void CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)
Select reference clock/oscillator used for a clock branch.
#define CMU_LOCK_LOCKKEY_LOCK
void CMU_PCNTClockExternalSet(unsigned int instance, bool external)
Select PCNTn clock.
#define CMU_HFCORECLKEN0_LE
__STATIC_INLINE void CMU_Lock(void)
Lock the CMU in order to protect some of its registers against unintended modification.
void CMU_AUXHFRCOBandSet(CMU_AUXHFRCOBand_TypeDef band)
Set AUXHFRCO band and the tuning value based on the value in the calibration table made during produc...
Emlib peripheral API "assert" implementation.
#define _CMU_LFACLKEN0_RTC_SHIFT
uint32_t CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)
Calibrate clock.
#define _CMU_HFCORECLKEN0_DMA_SHIFT
RAM and peripheral bit-field set and clear API.
__STATIC_INLINE uint32_t CMU_IntGet(void)
Get pending CMU interrupts.
#define _CMU_HFPERCLKEN0_USART1_SHIFT
#define CMU_LOCK_LOCKKEY_UNLOCK
#define _CMU_HFPERCLKEN0_VCMP_SHIFT
__STATIC_INLINE void CMU_IntSet(uint32_t flags)
Set one or more pending CMU interrupts.
#define _CMU_HFPERCLKEN0_GPIO_SHIFT
__STATIC_INLINE void CMU_CalibrateCont(bool enable)
Configures continuous calibration mode.
CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories microcontroller devices.
__STATIC_INLINE uint32_t CMU_IntGetEnabled(void)
Get enabled and pending CMU interrupt flags.
void CMU_FreezeEnable(bool enable)
CMU low frequency register synchronization freeze control.
#define CMU_HFPERCLKEN0_TIMER0
uint32_t CMU_ClkDiv_TypeDef
#define _CMU_HFRCOCTRL_BAND_21MHZ
#define _CMU_HFCORECLKEN0_AES_SHIFT
uint32_t CMU_HFRCOStartupDelayGet(void)
Get the HFRCO startup delay.
#define _CMU_HFPERCLKEN0_IDAC0_SHIFT
__STATIC_INLINE uint32_t CMU_Log2ToDiv(uint32_t log2)
Convert logarithm of 2 prescaler to division factor.
#define _CMU_AUXHFRCOCTRL_BAND_21MHZ
__STATIC_INLINE void CMU_CalibrateStart(void)
Starts calibration.
void CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)
Set the oscillator frequency tuning control.
void CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)
Configure clock calibration.
#define CMU_HFPERCLKEN0_GPIO
__STATIC_INLINE void CMU_IntDisable(uint32_t flags)
Disable one or more CMU interrupts.
#define CMU_HFPERCLKEN0_USART1
CMU_HFRCOBand_TypeDef CMU_HFRCOBandGet(void)
Get HFRCO band in use.
#define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT
#define CMU_HFPERCLKEN0_ACMP0
uint32_t CMU_LCDClkFDIVGet(void)
Get the LCD framerate divisor (FDIV) setting.
__STATIC_INLINE uint32_t CMU_DivToLog2(CMU_ClkDiv_TypeDef div)
Convert dividend to logarithmic value. Only works for even numbers equal to 2^n.
uint32_t CMU_CalibrateCountGet(void)
Get calibration count register.
#define _CMU_HFRCOCTRL_BAND_14MHZ
#define _CMU_HFRCOCTRL_BAND_1MHZ
void CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)
Enable/disable a clock.
void CMU_LCDClkFDIVSet(uint32_t div)
Set the LCD framerate divisor (FDIV) setting.
void CMU_HFRCOStartupDelaySet(uint32_t delay)
Set the HFRCO startup delay.
#define _CMU_HFPERCLKEN0_TIMER0_SHIFT
void CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)
Enable/disable oscillator.
#define CMU_HFPERCLKEN0_IDAC0
#define CMU_HFPERCLKEN0_TIMER1
#define _CMU_HFCORECLKEN0_LE_SHIFT
#define _CMU_LFBCLKEN0_LEUART0_SHIFT
#define CMU_HFPERCLKEN0_ADC0
#define _CMU_AUXHFRCOCTRL_BAND_7MHZ
#define _CMU_AUXHFRCOCTRL_BAND_1MHZ
#define _CMU_HFPERCLKEN0_PRS_SHIFT
#define _CMU_HFPERCLKEN0_ACMP0_SHIFT
#define CMU_HFCORECLKEN0_DMA
#define _CMU_HFPERCLKEN0_TIMER1_SHIFT
#define _CMU_HFPERCLKEN0_I2C0_SHIFT
#define _CMU_AUXHFRCOCTRL_BAND_14MHZ
__STATIC_INLINE void CMU_IntClear(uint32_t flags)
Clear one or more pending CMU interrupts.
__STATIC_INLINE void BUS_RegBitWrite(volatile uint32_t *addr, unsigned int bit, unsigned int val)
Perform a single-bit write operation on a peripheral register.
#define _CMU_HFRCOCTRL_BAND_7MHZ
uint32_t CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)
Get oscillator frequency tuning setting.
__STATIC_INLINE void CMU_IntEnable(uint32_t flags)
Enable one or more CMU interrupts.
#define _CMU_CALCTRL_CONT_SHIFT
void CMU_HFRCOBandSet(CMU_HFRCOBand_TypeDef band)
Set HFRCO band and the tuning value based on the value in the calibration table made during productio...
bool CMU_PCNTClockExternalGet(unsigned int instance)
Determine if currently selected PCNTn clock used is external or LFBCLK.
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
#define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT
__STATIC_INLINE void CMU_Unlock(void)
Unlock the CMU so that writing to locked registers again is possible.
#define CMU_HFPERCLKEN0_VCMP
#define CMU_HFPERCLKEN0_I2C0
#define _CMU_AUXHFRCOCTRL_BAND_11MHZ
void CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)
Set clock divisor/prescaler.
__STATIC_INLINE void CMU_CalibrateStop(void)
Stop the calibration counters.
CMU_AUXHFRCOBand_TypeDef CMU_AUXHFRCOBandGet(void)
Get AUXHFRCO band in use.
CMU_ClkDiv_TypeDef CMU_ClockDivGet(CMU_Clock_TypeDef clock)
Get clock divisor/prescaler.
CMU_Select_TypeDef CMU_ClockSelectGet(CMU_Clock_TypeDef clock)
Get currently selected reference clock used for a clock branch.
#define CMU_HFPERCLKEN0_PRS
#define _CMU_HFPERCLKEN0_ADC0_SHIFT
#define _CMU_HFRCOCTRL_BAND_11MHZ