34 #if defined( MSC_COUNT ) && ( MSC_COUNT > 0 )
38 #if defined( _MSC_TIMEBASE_MASK )
45 #if defined( MSC_WRITECTRL_WDOUBLE )
46 #define WORDS_PER_DATA_PHASE (FLASH_SIZE < (512 * 1024) ? 1 : 2)
48 #define WORDS_PER_DATA_PHASE (1)
54 } MSC_WriteStrategy_Typedef;
57 MSC_WriteWordI(uint32_t *address,
60 MSC_WriteStrategy_Typedef writeStrategy) MSC_FUNC_POSTFIX;
63 MSC_LoadWriteData(uint32_t* data,
65 MSC_WriteStrategy_Typedef writeStrategy) MSC_FUNC_POSTFIX;
68 MSC_LoadVerifyAddress(uint32_t* address) MSC_FUNC_POSTFIX;
103 #if defined( _MSC_TIMEBASE_MASK )
104 uint32_t freq, cycles;
118 #if defined( _MSC_TIMEBASE_MASK )
125 freq = (freq * 11) / 10;
126 cycles = (freq / 1000000) + 1;
137 freq = (freq * 5 * 11) / 10;
138 cycles = (freq / 1000000) + 1;
162 #if !defined( _EFM32_GECKO_FAMILY )
172 uint32_t mscReadCtrl;
174 mscReadCtrl =
MSC->READCTRL & ~(0
175 #if defined( MSC_READCTRL_SCBTP )
178 #if defined( MSC_READCTRL_USEHPROT )
179 | MSC_READCTRL_USEHPROT
181 #if defined( MSC_READCTRL_PREFETCH )
182 | MSC_READCTRL_PREFETCH
184 #if defined( MSC_READCTRL_ICCDIS )
185 | MSC_READCTRL_ICCDIS
187 #if defined( MSC_READCTRL_AIDIS )
190 #if defined( MSC_READCTRL_IFCDIS )
195 #if defined( MSC_READCTRL_SCBTP )
196 | (execConfig->
scbtEn ? MSC_READCTRL_SCBTP : 0)
198 #
if defined( MSC_READCTRL_USEHPROT )
199 | (execConfig->
useHprot ? MSC_READCTRL_USEHPROT : 0)
201 #
if defined( MSC_READCTRL_PREFETCH )
202 | (execConfig->
prefetchEn ? MSC_READCTRL_PREFETCH : 0)
204 #
if defined( MSC_READCTRL_ICCDIS )
205 | (execConfig->
iccDis ? MSC_READCTRL_ICCDIS : 0)
214 MSC->READCTRL = mscReadCtrl;
237 #if !defined(EM_MSC_RUN_FROM_FLASH)
238 #if defined(__CC_ARM)
239 #pragma arm section code="ram_code"
240 #elif defined(__ICCARM__)
244 #pragma diag_suppress=Ta022
245 #pragma diag_suppress=Ta023
267 MSC->ADDRB = (uint32_t)address;
270 status =
MSC->STATUS;
282 #if defined(__ICCARM__)
283 #pragma diag_default=Ta022
284 #pragma diag_default=Ta023
285 #elif defined(__CC_ARM)
286 #pragma arm section code
310 #if !defined(EM_MSC_RUN_FROM_FLASH)
311 #if defined(__CC_ARM)
312 #pragma arm section code="ram_code"
313 #elif defined(__ICCARM__)
317 #pragma diag_suppress=Ta022
318 #pragma diag_suppress=Ta023
323 MSC_LoadWriteData(uint32_t* data,
325 MSC_WriteStrategy_Typedef writeStrategy)
329 uint32_t wordsPerDataPhase;
332 #if defined(_MSC_WRITECTRL_LPWRITE_MASK) && defined(_MSC_WRITECTRL_WDOUBLE_MASK)
334 if (!(
MSC->WRITECTRL & MSC_WRITECTRL_LPWRITE))
352 MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
354 MSC->WDATA = *data++;
375 MSC->WRITECTRL |= MSC_WRITECTRL_WDOUBLE;
376 wordsPerDataPhase = 2;
381 wordsPerDataPhase = 1;
388 if (writeStrategy == mscWriteIntSafe)
393 while(wordIndex < numWords)
395 MSC->WDATA = *data++;
397 if (wordsPerDataPhase == 2)
400 MSC->WDATA = *data++;
417 #if defined( _EFM32_GECKO_FAMILY )
427 #if defined( _EFM32_GECKO_FAMILY )
436 while(wordIndex < numWords)
459 if ((wordsPerDataPhase == 1)
460 || ((wordsPerDataPhase == 2) && (wordIndex & 0x1)))
484 #if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
486 MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
491 #if defined(__ICCARM__)
492 #pragma diag_default=Ta022
493 #pragma diag_default=Ta023
494 #elif defined(__CC_ARM)
495 #pragma arm section code
513 #if !defined(EM_MSC_RUN_FROM_FLASH)
514 #if defined(__CC_ARM)
515 #pragma arm section code="ram_code"
516 #elif defined(__ICCARM__)
520 #pragma diag_suppress=Ta022
521 #pragma diag_suppress=Ta023
527 MSC_WriteStrategy_Typedef writeStrategy)
536 EFM_ASSERT(((uint32_t) address & 0x3) == 0);
539 EFM_ASSERT((numBytes & 0x3) == 0);
545 numWords = numBytes >> 2;
546 EFM_ASSERT(numWords > 0);
551 for (wordCount = 0, pData = (uint32_t *)data; wordCount < numWords; )
555 retval = MSC_LoadVerifyAddress(address + wordCount);
565 if (pageWords > numWords - wordCount)
567 pageWords = numWords - wordCount;
570 retval = MSC_LoadWriteData(pData, pageWords, writeStrategy);
575 wordCount += pageWords;
582 #if defined( _MSC_WRITECTRL_WDOUBLE_MASK )
583 #if ( WORDS_PER_DATA_PHASE == 2 )
585 MSC->WRITECTRL &= ~MSC_WRITECTRL_WDOUBLE;
591 #if defined(__ICCARM__)
592 #pragma diag_default=Ta022
593 #pragma diag_default=Ta023
594 #elif defined(__CC_ARM)
595 #pragma arm section code
626 #if !defined(EM_MSC_RUN_FROM_FLASH)
627 #if defined(__CC_ARM)
628 #pragma arm section code="ram_code"
629 #elif defined(__ICCARM__)
633 #pragma diag_suppress=Ta022
634 #pragma diag_suppress=Ta023
648 MSC->ADDRB = (uint32_t)startAddress;
683 #if defined(__ICCARM__)
684 #pragma diag_default=Ta022
685 #pragma diag_default=Ta023
686 #elif defined(__CC_ARM)
687 #pragma arm section code
727 #if !defined(EM_MSC_RUN_FROM_FLASH)
728 #if defined(__CC_ARM)
729 #pragma arm section code="ram_code"
730 #elif defined(__ICCARM__)
734 #pragma diag_suppress=Ta022
735 #pragma diag_suppress=Ta023
742 return MSC_WriteWordI(address, data, numBytes, mscWriteIntSafe);
744 #if defined(__ICCARM__)
745 #pragma diag_default=Ta022
746 #pragma diag_default=Ta023
747 #elif defined(__CC_ARM)
748 #pragma arm section code
752 #if !defined( _EFM32_GECKO_FAMILY )
786 #if !defined(EM_MSC_RUN_FROM_FLASH)
787 #if defined(__CC_ARM)
788 #pragma arm section code="ram_code"
789 #elif defined(__ICCARM__)
793 #pragma diag_suppress=Ta022
794 #pragma diag_suppress=Ta023
801 return MSC_WriteWordI(address, data, numBytes, mscWriteFast);
803 #if defined(__ICCARM__)
804 #pragma diag_default=Ta022
805 #pragma diag_default=Ta023
806 #elif defined(__CC_ARM)
807 #pragma arm section code
812 #if defined( _MSC_MASSLOCK_MASK )
822 #if !defined(EM_MSC_RUN_FROM_FLASH)
823 #if defined(__CC_ARM)
824 #pragma arm section code="ram_code"
841 #if ((FLASH_SIZE >= (512 * 1024)) && defined( _MSC_WRITECMD_ERASEMAIN1_MASK ))
843 MSC->WRITECMD = MSC_WRITECMD_ERASEMAIN1;
855 #if defined(__CC_ARM)
856 #pragma arm section code
#define MSC_WRITECMD_LADDRIM
Clock management unit (CMU) API.
#define MSC_WRITECMD_ERASEMAIN0
Emlib peripheral API "assert" implementation.
#define MSC_TIMEBASE_PERIOD_1US
__STATIC_INLINE uint32_t INT_Enable(void)
Enable interrupts.
#define MSC_WRITECMD_WRITETRIG
#define MSC_STATUS_WORDTIMEOUT
void MSC_Init(void)
Enables the flash controller for writing.
#define _MSC_TIMEBASE_PERIOD_MASK
#define MSC_STATUS_WDATAREADY
void MSC_Deinit(void)
Disables the flash controller for writing.
MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_WriteWordFast(uint32_t *address, void const *data, uint32_t numBytes) MSC_FUNC_POSTFIX
Writes data to flash memory. This function is faster than MSC_WriteWord(), but it disables interrupts...
#define MSC_PROGRAM_TIMEOUT
The timeout used while waiting for the flash to become ready after a write. This number indicates the...
void MSC_ExecConfigSet(MSC_ExecConfig_TypeDef *execConfig)
Set MSC code execution configuration.
Flash controller module (MSC) peripheral API.
Interrupt enable/disable unit API.
#define MSC_READCTRL_AIDIS
#define MSC_STATUS_INVADDR
#define MSC_WRITECTRL_WREN
#define _MSC_TIMEBASE_BASE_SHIFT
#define MSC_MASSLOCK_LOCKKEY_LOCK
#define MSC_STATUS_LOCKED
#define _MSC_TIMEBASE_BASE_MASK
MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_ErasePage(uint32_t *startAddress) MSC_FUNC_POSTFIX
Erases a page in flash memory.
#define MSC_TIMEBASE_PERIOD_5US
MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_MassErase(void) MSC_FUNC_POSTFIX
Erase entire flash in one operation.
#define MSC_WRITECMD_ERASEPAGE
#define MSC_WRITECMD_WRITEONCE
__STATIC_INLINE uint32_t INT_Disable(void)
Disable interrupts.
MSC_FUNC_PREFIX MSC_Status_TypeDef MSC_WriteWord(uint32_t *address, void const *data, uint32_t numBytes) MSC_FUNC_POSTFIX
Writes data to flash memory. This function is interrupt safe, but slower than MSC_WriteWordFast(), which writes to flash with interrupts disabled. Write data must be aligned to words and contain a number of bytes that is divisable by four.
uint32_t CMU_ClockFreqGet(CMU_Clock_TypeDef clock)
Get clock frequency for a clock point.
#define MSC_MASSLOCK_LOCKKEY_UNLOCK
#define MSC_READCTRL_IFCDIS
uint32_t SystemCoreClockGet(void)
Get the current core clock frequency.