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efm32zg_adc.h
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1
/**************************************************************************/
32
/**************************************************************************/
36
/**************************************************************************/
41
typedef
struct
42
{
43
__IO
uint32_t
CTRL
;
44
__IO
uint32_t
CMD
;
45
__I uint32_t
STATUS
;
46
__IO
uint32_t
SINGLECTRL
;
47
__IO
uint32_t
SCANCTRL
;
48
__IO
uint32_t
IEN
;
49
__I uint32_t
IF
;
50
__IO
uint32_t
IFS
;
51
__IO
uint32_t
IFC
;
52
__I uint32_t
SINGLEDATA
;
53
__I uint32_t
SCANDATA
;
54
__I uint32_t
SINGLEDATAP
;
55
__I uint32_t
SCANDATAP
;
56
__IO
uint32_t
CAL
;
58
uint32_t RESERVED0[1];
59
__IO
uint32_t
BIASPROG
;
60
}
ADC_TypeDef
;
62
/**************************************************************************/
67
/* Bit fields for ADC CTRL */
68
#define _ADC_CTRL_RESETVALUE 0x001F0000UL
69
#define _ADC_CTRL_MASK 0x1F7F7F3BUL
70
#define _ADC_CTRL_WARMUPMODE_SHIFT 0
71
#define _ADC_CTRL_WARMUPMODE_MASK 0x3UL
72
#define _ADC_CTRL_WARMUPMODE_DEFAULT 0x00000000UL
73
#define _ADC_CTRL_WARMUPMODE_NORMAL 0x00000000UL
74
#define _ADC_CTRL_WARMUPMODE_FASTBG 0x00000001UL
75
#define _ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 0x00000002UL
76
#define _ADC_CTRL_WARMUPMODE_KEEPADCWARM 0x00000003UL
77
#define ADC_CTRL_WARMUPMODE_DEFAULT (_ADC_CTRL_WARMUPMODE_DEFAULT << 0)
78
#define ADC_CTRL_WARMUPMODE_NORMAL (_ADC_CTRL_WARMUPMODE_NORMAL << 0)
79
#define ADC_CTRL_WARMUPMODE_FASTBG (_ADC_CTRL_WARMUPMODE_FASTBG << 0)
80
#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM (_ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM << 0)
81
#define ADC_CTRL_WARMUPMODE_KEEPADCWARM (_ADC_CTRL_WARMUPMODE_KEEPADCWARM << 0)
82
#define ADC_CTRL_TAILGATE (0x1UL << 3)
83
#define _ADC_CTRL_TAILGATE_SHIFT 3
84
#define _ADC_CTRL_TAILGATE_MASK 0x8UL
85
#define _ADC_CTRL_TAILGATE_DEFAULT 0x00000000UL
86
#define ADC_CTRL_TAILGATE_DEFAULT (_ADC_CTRL_TAILGATE_DEFAULT << 3)
87
#define _ADC_CTRL_LPFMODE_SHIFT 4
88
#define _ADC_CTRL_LPFMODE_MASK 0x30UL
89
#define _ADC_CTRL_LPFMODE_DEFAULT 0x00000000UL
90
#define _ADC_CTRL_LPFMODE_BYPASS 0x00000000UL
91
#define _ADC_CTRL_LPFMODE_DECAP 0x00000001UL
92
#define _ADC_CTRL_LPFMODE_RCFILT 0x00000002UL
93
#define ADC_CTRL_LPFMODE_DEFAULT (_ADC_CTRL_LPFMODE_DEFAULT << 4)
94
#define ADC_CTRL_LPFMODE_BYPASS (_ADC_CTRL_LPFMODE_BYPASS << 4)
95
#define ADC_CTRL_LPFMODE_DECAP (_ADC_CTRL_LPFMODE_DECAP << 4)
96
#define ADC_CTRL_LPFMODE_RCFILT (_ADC_CTRL_LPFMODE_RCFILT << 4)
97
#define _ADC_CTRL_PRESC_SHIFT 8
98
#define _ADC_CTRL_PRESC_MASK 0x7F00UL
99
#define _ADC_CTRL_PRESC_DEFAULT 0x00000000UL
100
#define _ADC_CTRL_PRESC_NODIVISION 0x00000000UL
101
#define ADC_CTRL_PRESC_DEFAULT (_ADC_CTRL_PRESC_DEFAULT << 8)
102
#define ADC_CTRL_PRESC_NODIVISION (_ADC_CTRL_PRESC_NODIVISION << 8)
103
#define _ADC_CTRL_TIMEBASE_SHIFT 16
104
#define _ADC_CTRL_TIMEBASE_MASK 0x7F0000UL
105
#define _ADC_CTRL_TIMEBASE_DEFAULT 0x0000001FUL
106
#define ADC_CTRL_TIMEBASE_DEFAULT (_ADC_CTRL_TIMEBASE_DEFAULT << 16)
107
#define _ADC_CTRL_OVSRSEL_SHIFT 24
108
#define _ADC_CTRL_OVSRSEL_MASK 0xF000000UL
109
#define _ADC_CTRL_OVSRSEL_DEFAULT 0x00000000UL
110
#define _ADC_CTRL_OVSRSEL_X2 0x00000000UL
111
#define _ADC_CTRL_OVSRSEL_X4 0x00000001UL
112
#define _ADC_CTRL_OVSRSEL_X8 0x00000002UL
113
#define _ADC_CTRL_OVSRSEL_X16 0x00000003UL
114
#define _ADC_CTRL_OVSRSEL_X32 0x00000004UL
115
#define _ADC_CTRL_OVSRSEL_X64 0x00000005UL
116
#define _ADC_CTRL_OVSRSEL_X128 0x00000006UL
117
#define _ADC_CTRL_OVSRSEL_X256 0x00000007UL
118
#define _ADC_CTRL_OVSRSEL_X512 0x00000008UL
119
#define _ADC_CTRL_OVSRSEL_X1024 0x00000009UL
120
#define _ADC_CTRL_OVSRSEL_X2048 0x0000000AUL
121
#define _ADC_CTRL_OVSRSEL_X4096 0x0000000BUL
122
#define ADC_CTRL_OVSRSEL_DEFAULT (_ADC_CTRL_OVSRSEL_DEFAULT << 24)
123
#define ADC_CTRL_OVSRSEL_X2 (_ADC_CTRL_OVSRSEL_X2 << 24)
124
#define ADC_CTRL_OVSRSEL_X4 (_ADC_CTRL_OVSRSEL_X4 << 24)
125
#define ADC_CTRL_OVSRSEL_X8 (_ADC_CTRL_OVSRSEL_X8 << 24)
126
#define ADC_CTRL_OVSRSEL_X16 (_ADC_CTRL_OVSRSEL_X16 << 24)
127
#define ADC_CTRL_OVSRSEL_X32 (_ADC_CTRL_OVSRSEL_X32 << 24)
128
#define ADC_CTRL_OVSRSEL_X64 (_ADC_CTRL_OVSRSEL_X64 << 24)
129
#define ADC_CTRL_OVSRSEL_X128 (_ADC_CTRL_OVSRSEL_X128 << 24)
130
#define ADC_CTRL_OVSRSEL_X256 (_ADC_CTRL_OVSRSEL_X256 << 24)
131
#define ADC_CTRL_OVSRSEL_X512 (_ADC_CTRL_OVSRSEL_X512 << 24)
132
#define ADC_CTRL_OVSRSEL_X1024 (_ADC_CTRL_OVSRSEL_X1024 << 24)
133
#define ADC_CTRL_OVSRSEL_X2048 (_ADC_CTRL_OVSRSEL_X2048 << 24)
134
#define ADC_CTRL_OVSRSEL_X4096 (_ADC_CTRL_OVSRSEL_X4096 << 24)
135
#define ADC_CTRL_CHCONIDLE (0x1UL << 28)
136
#define _ADC_CTRL_CHCONIDLE_SHIFT 28
137
#define _ADC_CTRL_CHCONIDLE_MASK 0x10000000UL
138
#define _ADC_CTRL_CHCONIDLE_DEFAULT 0x00000000UL
139
#define _ADC_CTRL_CHCONIDLE_DISCONNECT 0x00000000UL
140
#define _ADC_CTRL_CHCONIDLE_KEEPCON 0x00000001UL
141
#define ADC_CTRL_CHCONIDLE_DEFAULT (_ADC_CTRL_CHCONIDLE_DEFAULT << 28)
142
#define ADC_CTRL_CHCONIDLE_DISCONNECT (_ADC_CTRL_CHCONIDLE_DISCONNECT << 28)
143
#define ADC_CTRL_CHCONIDLE_KEEPCON (_ADC_CTRL_CHCONIDLE_KEEPCON << 28)
145
/* Bit fields for ADC CMD */
146
#define _ADC_CMD_RESETVALUE 0x00000000UL
147
#define _ADC_CMD_MASK 0x0000000FUL
148
#define ADC_CMD_SINGLESTART (0x1UL << 0)
149
#define _ADC_CMD_SINGLESTART_SHIFT 0
150
#define _ADC_CMD_SINGLESTART_MASK 0x1UL
151
#define _ADC_CMD_SINGLESTART_DEFAULT 0x00000000UL
152
#define ADC_CMD_SINGLESTART_DEFAULT (_ADC_CMD_SINGLESTART_DEFAULT << 0)
153
#define ADC_CMD_SINGLESTOP (0x1UL << 1)
154
#define _ADC_CMD_SINGLESTOP_SHIFT 1
155
#define _ADC_CMD_SINGLESTOP_MASK 0x2UL
156
#define _ADC_CMD_SINGLESTOP_DEFAULT 0x00000000UL
157
#define ADC_CMD_SINGLESTOP_DEFAULT (_ADC_CMD_SINGLESTOP_DEFAULT << 1)
158
#define ADC_CMD_SCANSTART (0x1UL << 2)
159
#define _ADC_CMD_SCANSTART_SHIFT 2
160
#define _ADC_CMD_SCANSTART_MASK 0x4UL
161
#define _ADC_CMD_SCANSTART_DEFAULT 0x00000000UL
162
#define ADC_CMD_SCANSTART_DEFAULT (_ADC_CMD_SCANSTART_DEFAULT << 2)
163
#define ADC_CMD_SCANSTOP (0x1UL << 3)
164
#define _ADC_CMD_SCANSTOP_SHIFT 3
165
#define _ADC_CMD_SCANSTOP_MASK 0x8UL
166
#define _ADC_CMD_SCANSTOP_DEFAULT 0x00000000UL
167
#define ADC_CMD_SCANSTOP_DEFAULT (_ADC_CMD_SCANSTOP_DEFAULT << 3)
169
/* Bit fields for ADC STATUS */
170
#define _ADC_STATUS_RESETVALUE 0x00000000UL
171
#define _ADC_STATUS_MASK 0x07031303UL
172
#define ADC_STATUS_SINGLEACT (0x1UL << 0)
173
#define _ADC_STATUS_SINGLEACT_SHIFT 0
174
#define _ADC_STATUS_SINGLEACT_MASK 0x1UL
175
#define _ADC_STATUS_SINGLEACT_DEFAULT 0x00000000UL
176
#define ADC_STATUS_SINGLEACT_DEFAULT (_ADC_STATUS_SINGLEACT_DEFAULT << 0)
177
#define ADC_STATUS_SCANACT (0x1UL << 1)
178
#define _ADC_STATUS_SCANACT_SHIFT 1
179
#define _ADC_STATUS_SCANACT_MASK 0x2UL
180
#define _ADC_STATUS_SCANACT_DEFAULT 0x00000000UL
181
#define ADC_STATUS_SCANACT_DEFAULT (_ADC_STATUS_SCANACT_DEFAULT << 1)
182
#define ADC_STATUS_SINGLEREFWARM (0x1UL << 8)
183
#define _ADC_STATUS_SINGLEREFWARM_SHIFT 8
184
#define _ADC_STATUS_SINGLEREFWARM_MASK 0x100UL
185
#define _ADC_STATUS_SINGLEREFWARM_DEFAULT 0x00000000UL
186
#define ADC_STATUS_SINGLEREFWARM_DEFAULT (_ADC_STATUS_SINGLEREFWARM_DEFAULT << 8)
187
#define ADC_STATUS_SCANREFWARM (0x1UL << 9)
188
#define _ADC_STATUS_SCANREFWARM_SHIFT 9
189
#define _ADC_STATUS_SCANREFWARM_MASK 0x200UL
190
#define _ADC_STATUS_SCANREFWARM_DEFAULT 0x00000000UL
191
#define ADC_STATUS_SCANREFWARM_DEFAULT (_ADC_STATUS_SCANREFWARM_DEFAULT << 9)
192
#define ADC_STATUS_WARM (0x1UL << 12)
193
#define _ADC_STATUS_WARM_SHIFT 12
194
#define _ADC_STATUS_WARM_MASK 0x1000UL
195
#define _ADC_STATUS_WARM_DEFAULT 0x00000000UL
196
#define ADC_STATUS_WARM_DEFAULT (_ADC_STATUS_WARM_DEFAULT << 12)
197
#define ADC_STATUS_SINGLEDV (0x1UL << 16)
198
#define _ADC_STATUS_SINGLEDV_SHIFT 16
199
#define _ADC_STATUS_SINGLEDV_MASK 0x10000UL
200
#define _ADC_STATUS_SINGLEDV_DEFAULT 0x00000000UL
201
#define ADC_STATUS_SINGLEDV_DEFAULT (_ADC_STATUS_SINGLEDV_DEFAULT << 16)
202
#define ADC_STATUS_SCANDV (0x1UL << 17)
203
#define _ADC_STATUS_SCANDV_SHIFT 17
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#define _ADC_STATUS_SCANDV_MASK 0x20000UL
205
#define _ADC_STATUS_SCANDV_DEFAULT 0x00000000UL
206
#define ADC_STATUS_SCANDV_DEFAULT (_ADC_STATUS_SCANDV_DEFAULT << 17)
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#define _ADC_STATUS_SCANDATASRC_SHIFT 24
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#define _ADC_STATUS_SCANDATASRC_MASK 0x7000000UL
209
#define _ADC_STATUS_SCANDATASRC_DEFAULT 0x00000000UL
210
#define _ADC_STATUS_SCANDATASRC_CH0 0x00000000UL
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#define _ADC_STATUS_SCANDATASRC_CH1 0x00000001UL
212
#define _ADC_STATUS_SCANDATASRC_CH2 0x00000002UL
213
#define _ADC_STATUS_SCANDATASRC_CH3 0x00000003UL
214
#define _ADC_STATUS_SCANDATASRC_CH4 0x00000004UL
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#define _ADC_STATUS_SCANDATASRC_CH5 0x00000005UL
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#define _ADC_STATUS_SCANDATASRC_CH6 0x00000006UL
217
#define _ADC_STATUS_SCANDATASRC_CH7 0x00000007UL
218
#define ADC_STATUS_SCANDATASRC_DEFAULT (_ADC_STATUS_SCANDATASRC_DEFAULT << 24)
219
#define ADC_STATUS_SCANDATASRC_CH0 (_ADC_STATUS_SCANDATASRC_CH0 << 24)
220
#define ADC_STATUS_SCANDATASRC_CH1 (_ADC_STATUS_SCANDATASRC_CH1 << 24)
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#define ADC_STATUS_SCANDATASRC_CH2 (_ADC_STATUS_SCANDATASRC_CH2 << 24)
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#define ADC_STATUS_SCANDATASRC_CH3 (_ADC_STATUS_SCANDATASRC_CH3 << 24)
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#define ADC_STATUS_SCANDATASRC_CH4 (_ADC_STATUS_SCANDATASRC_CH4 << 24)
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#define ADC_STATUS_SCANDATASRC_CH5 (_ADC_STATUS_SCANDATASRC_CH5 << 24)
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#define ADC_STATUS_SCANDATASRC_CH6 (_ADC_STATUS_SCANDATASRC_CH6 << 24)
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#define ADC_STATUS_SCANDATASRC_CH7 (_ADC_STATUS_SCANDATASRC_CH7 << 24)
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/* Bit fields for ADC SINGLECTRL */
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#define _ADC_SINGLECTRL_RESETVALUE 0x00000000UL
230
#define _ADC_SINGLECTRL_MASK 0x31F70F37UL
231
#define ADC_SINGLECTRL_REP (0x1UL << 0)
232
#define _ADC_SINGLECTRL_REP_SHIFT 0
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#define _ADC_SINGLECTRL_REP_MASK 0x1UL
234
#define _ADC_SINGLECTRL_REP_DEFAULT 0x00000000UL
235
#define ADC_SINGLECTRL_REP_DEFAULT (_ADC_SINGLECTRL_REP_DEFAULT << 0)
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#define ADC_SINGLECTRL_DIFF (0x1UL << 1)
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#define _ADC_SINGLECTRL_DIFF_SHIFT 1
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#define _ADC_SINGLECTRL_DIFF_MASK 0x2UL
239
#define _ADC_SINGLECTRL_DIFF_DEFAULT 0x00000000UL
240
#define ADC_SINGLECTRL_DIFF_DEFAULT (_ADC_SINGLECTRL_DIFF_DEFAULT << 1)
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#define ADC_SINGLECTRL_ADJ (0x1UL << 2)
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#define _ADC_SINGLECTRL_ADJ_SHIFT 2
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#define _ADC_SINGLECTRL_ADJ_MASK 0x4UL
244
#define _ADC_SINGLECTRL_ADJ_DEFAULT 0x00000000UL
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#define _ADC_SINGLECTRL_ADJ_RIGHT 0x00000000UL
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#define _ADC_SINGLECTRL_ADJ_LEFT 0x00000001UL
247
#define ADC_SINGLECTRL_ADJ_DEFAULT (_ADC_SINGLECTRL_ADJ_DEFAULT << 2)
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#define ADC_SINGLECTRL_ADJ_RIGHT (_ADC_SINGLECTRL_ADJ_RIGHT << 2)
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#define ADC_SINGLECTRL_ADJ_LEFT (_ADC_SINGLECTRL_ADJ_LEFT << 2)
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#define _ADC_SINGLECTRL_RES_SHIFT 4
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#define _ADC_SINGLECTRL_RES_MASK 0x30UL
252
#define _ADC_SINGLECTRL_RES_DEFAULT 0x00000000UL
253
#define _ADC_SINGLECTRL_RES_12BIT 0x00000000UL
254
#define _ADC_SINGLECTRL_RES_8BIT 0x00000001UL
255
#define _ADC_SINGLECTRL_RES_6BIT 0x00000002UL
256
#define _ADC_SINGLECTRL_RES_OVS 0x00000003UL
257
#define ADC_SINGLECTRL_RES_DEFAULT (_ADC_SINGLECTRL_RES_DEFAULT << 4)
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#define ADC_SINGLECTRL_RES_12BIT (_ADC_SINGLECTRL_RES_12BIT << 4)
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#define ADC_SINGLECTRL_RES_8BIT (_ADC_SINGLECTRL_RES_8BIT << 4)
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#define ADC_SINGLECTRL_RES_6BIT (_ADC_SINGLECTRL_RES_6BIT << 4)
261
#define ADC_SINGLECTRL_RES_OVS (_ADC_SINGLECTRL_RES_OVS << 4)
262
#define _ADC_SINGLECTRL_INPUTSEL_SHIFT 8
263
#define _ADC_SINGLECTRL_INPUTSEL_MASK 0xF00UL
264
#define _ADC_SINGLECTRL_INPUTSEL_DEFAULT 0x00000000UL
265
#define _ADC_SINGLECTRL_INPUTSEL_CH0 0x00000000UL
266
#define _ADC_SINGLECTRL_INPUTSEL_CH0CH1 0x00000000UL
267
#define _ADC_SINGLECTRL_INPUTSEL_CH1 0x00000001UL
268
#define _ADC_SINGLECTRL_INPUTSEL_CH2CH3 0x00000001UL
269
#define _ADC_SINGLECTRL_INPUTSEL_CH2 0x00000002UL
270
#define _ADC_SINGLECTRL_INPUTSEL_CH4CH5 0x00000002UL
271
#define _ADC_SINGLECTRL_INPUTSEL_CH6CH7 0x00000003UL
272
#define _ADC_SINGLECTRL_INPUTSEL_CH3 0x00000003UL
273
#define _ADC_SINGLECTRL_INPUTSEL_CH4 0x00000004UL
274
#define _ADC_SINGLECTRL_INPUTSEL_DIFF0 0x00000004UL
275
#define _ADC_SINGLECTRL_INPUTSEL_CH5 0x00000005UL
276
#define _ADC_SINGLECTRL_INPUTSEL_CH6 0x00000006UL
277
#define _ADC_SINGLECTRL_INPUTSEL_CH7 0x00000007UL
278
#define _ADC_SINGLECTRL_INPUTSEL_TEMP 0x00000008UL
279
#define _ADC_SINGLECTRL_INPUTSEL_VDDDIV3 0x00000009UL
280
#define _ADC_SINGLECTRL_INPUTSEL_VDD 0x0000000AUL
281
#define _ADC_SINGLECTRL_INPUTSEL_VSS 0x0000000BUL
282
#define _ADC_SINGLECTRL_INPUTSEL_VREFDIV2 0x0000000CUL
283
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 0x0000000DUL
284
#define _ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 0x0000000EUL
285
#define ADC_SINGLECTRL_INPUTSEL_DEFAULT (_ADC_SINGLECTRL_INPUTSEL_DEFAULT << 8)
286
#define ADC_SINGLECTRL_INPUTSEL_CH0 (_ADC_SINGLECTRL_INPUTSEL_CH0 << 8)
287
#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 (_ADC_SINGLECTRL_INPUTSEL_CH0CH1 << 8)
288
#define ADC_SINGLECTRL_INPUTSEL_CH1 (_ADC_SINGLECTRL_INPUTSEL_CH1 << 8)
289
#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 (_ADC_SINGLECTRL_INPUTSEL_CH2CH3 << 8)
290
#define ADC_SINGLECTRL_INPUTSEL_CH2 (_ADC_SINGLECTRL_INPUTSEL_CH2 << 8)
291
#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 (_ADC_SINGLECTRL_INPUTSEL_CH4CH5 << 8)
292
#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 (_ADC_SINGLECTRL_INPUTSEL_CH6CH7 << 8)
293
#define ADC_SINGLECTRL_INPUTSEL_CH3 (_ADC_SINGLECTRL_INPUTSEL_CH3 << 8)
294
#define ADC_SINGLECTRL_INPUTSEL_CH4 (_ADC_SINGLECTRL_INPUTSEL_CH4 << 8)
295
#define ADC_SINGLECTRL_INPUTSEL_DIFF0 (_ADC_SINGLECTRL_INPUTSEL_DIFF0 << 8)
296
#define ADC_SINGLECTRL_INPUTSEL_CH5 (_ADC_SINGLECTRL_INPUTSEL_CH5 << 8)
297
#define ADC_SINGLECTRL_INPUTSEL_CH6 (_ADC_SINGLECTRL_INPUTSEL_CH6 << 8)
298
#define ADC_SINGLECTRL_INPUTSEL_CH7 (_ADC_SINGLECTRL_INPUTSEL_CH7 << 8)
299
#define ADC_SINGLECTRL_INPUTSEL_TEMP (_ADC_SINGLECTRL_INPUTSEL_TEMP << 8)
300
#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 (_ADC_SINGLECTRL_INPUTSEL_VDDDIV3 << 8)
301
#define ADC_SINGLECTRL_INPUTSEL_VDD (_ADC_SINGLECTRL_INPUTSEL_VDD << 8)
302
#define ADC_SINGLECTRL_INPUTSEL_VSS (_ADC_SINGLECTRL_INPUTSEL_VSS << 8)
303
#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 (_ADC_SINGLECTRL_INPUTSEL_VREFDIV2 << 8)
304
#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 << 8)
305
#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 (_ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 << 8)
306
#define _ADC_SINGLECTRL_REF_SHIFT 16
307
#define _ADC_SINGLECTRL_REF_MASK 0x70000UL
308
#define _ADC_SINGLECTRL_REF_DEFAULT 0x00000000UL
309
#define _ADC_SINGLECTRL_REF_1V25 0x00000000UL
310
#define _ADC_SINGLECTRL_REF_2V5 0x00000001UL
311
#define _ADC_SINGLECTRL_REF_VDD 0x00000002UL
312
#define _ADC_SINGLECTRL_REF_5VDIFF 0x00000003UL
313
#define _ADC_SINGLECTRL_REF_EXTSINGLE 0x00000004UL
314
#define _ADC_SINGLECTRL_REF_2XEXTDIFF 0x00000005UL
315
#define _ADC_SINGLECTRL_REF_2XVDD 0x00000006UL
316
#define ADC_SINGLECTRL_REF_DEFAULT (_ADC_SINGLECTRL_REF_DEFAULT << 16)
317
#define ADC_SINGLECTRL_REF_1V25 (_ADC_SINGLECTRL_REF_1V25 << 16)
318
#define ADC_SINGLECTRL_REF_2V5 (_ADC_SINGLECTRL_REF_2V5 << 16)
319
#define ADC_SINGLECTRL_REF_VDD (_ADC_SINGLECTRL_REF_VDD << 16)
320
#define ADC_SINGLECTRL_REF_5VDIFF (_ADC_SINGLECTRL_REF_5VDIFF << 16)
321
#define ADC_SINGLECTRL_REF_EXTSINGLE (_ADC_SINGLECTRL_REF_EXTSINGLE << 16)
322
#define ADC_SINGLECTRL_REF_2XEXTDIFF (_ADC_SINGLECTRL_REF_2XEXTDIFF << 16)
323
#define ADC_SINGLECTRL_REF_2XVDD (_ADC_SINGLECTRL_REF_2XVDD << 16)
324
#define _ADC_SINGLECTRL_AT_SHIFT 20
325
#define _ADC_SINGLECTRL_AT_MASK 0xF00000UL
326
#define _ADC_SINGLECTRL_AT_DEFAULT 0x00000000UL
327
#define _ADC_SINGLECTRL_AT_1CYCLE 0x00000000UL
328
#define _ADC_SINGLECTRL_AT_2CYCLES 0x00000001UL
329
#define _ADC_SINGLECTRL_AT_4CYCLES 0x00000002UL
330
#define _ADC_SINGLECTRL_AT_8CYCLES 0x00000003UL
331
#define _ADC_SINGLECTRL_AT_16CYCLES 0x00000004UL
332
#define _ADC_SINGLECTRL_AT_32CYCLES 0x00000005UL
333
#define _ADC_SINGLECTRL_AT_64CYCLES 0x00000006UL
334
#define _ADC_SINGLECTRL_AT_128CYCLES 0x00000007UL
335
#define _ADC_SINGLECTRL_AT_256CYCLES 0x00000008UL
336
#define ADC_SINGLECTRL_AT_DEFAULT (_ADC_SINGLECTRL_AT_DEFAULT << 20)
337
#define ADC_SINGLECTRL_AT_1CYCLE (_ADC_SINGLECTRL_AT_1CYCLE << 20)
338
#define ADC_SINGLECTRL_AT_2CYCLES (_ADC_SINGLECTRL_AT_2CYCLES << 20)
339
#define ADC_SINGLECTRL_AT_4CYCLES (_ADC_SINGLECTRL_AT_4CYCLES << 20)
340
#define ADC_SINGLECTRL_AT_8CYCLES (_ADC_SINGLECTRL_AT_8CYCLES << 20)
341
#define ADC_SINGLECTRL_AT_16CYCLES (_ADC_SINGLECTRL_AT_16CYCLES << 20)
342
#define ADC_SINGLECTRL_AT_32CYCLES (_ADC_SINGLECTRL_AT_32CYCLES << 20)
343
#define ADC_SINGLECTRL_AT_64CYCLES (_ADC_SINGLECTRL_AT_64CYCLES << 20)
344
#define ADC_SINGLECTRL_AT_128CYCLES (_ADC_SINGLECTRL_AT_128CYCLES << 20)
345
#define ADC_SINGLECTRL_AT_256CYCLES (_ADC_SINGLECTRL_AT_256CYCLES << 20)
346
#define ADC_SINGLECTRL_PRSEN (0x1UL << 24)
347
#define _ADC_SINGLECTRL_PRSEN_SHIFT 24
348
#define _ADC_SINGLECTRL_PRSEN_MASK 0x1000000UL
349
#define _ADC_SINGLECTRL_PRSEN_DEFAULT 0x00000000UL
350
#define ADC_SINGLECTRL_PRSEN_DEFAULT (_ADC_SINGLECTRL_PRSEN_DEFAULT << 24)
351
#define _ADC_SINGLECTRL_PRSSEL_SHIFT 28
352
#define _ADC_SINGLECTRL_PRSSEL_MASK 0x30000000UL
353
#define _ADC_SINGLECTRL_PRSSEL_DEFAULT 0x00000000UL
354
#define _ADC_SINGLECTRL_PRSSEL_PRSCH0 0x00000000UL
355
#define _ADC_SINGLECTRL_PRSSEL_PRSCH1 0x00000001UL
356
#define _ADC_SINGLECTRL_PRSSEL_PRSCH2 0x00000002UL
357
#define _ADC_SINGLECTRL_PRSSEL_PRSCH3 0x00000003UL
358
#define ADC_SINGLECTRL_PRSSEL_DEFAULT (_ADC_SINGLECTRL_PRSSEL_DEFAULT << 28)
359
#define ADC_SINGLECTRL_PRSSEL_PRSCH0 (_ADC_SINGLECTRL_PRSSEL_PRSCH0 << 28)
360
#define ADC_SINGLECTRL_PRSSEL_PRSCH1 (_ADC_SINGLECTRL_PRSSEL_PRSCH1 << 28)
361
#define ADC_SINGLECTRL_PRSSEL_PRSCH2 (_ADC_SINGLECTRL_PRSSEL_PRSCH2 << 28)
362
#define ADC_SINGLECTRL_PRSSEL_PRSCH3 (_ADC_SINGLECTRL_PRSSEL_PRSCH3 << 28)
364
/* Bit fields for ADC SCANCTRL */
365
#define _ADC_SCANCTRL_RESETVALUE 0x00000000UL
366
#define _ADC_SCANCTRL_MASK 0x31F7FF37UL
367
#define ADC_SCANCTRL_REP (0x1UL << 0)
368
#define _ADC_SCANCTRL_REP_SHIFT 0
369
#define _ADC_SCANCTRL_REP_MASK 0x1UL
370
#define _ADC_SCANCTRL_REP_DEFAULT 0x00000000UL
371
#define ADC_SCANCTRL_REP_DEFAULT (_ADC_SCANCTRL_REP_DEFAULT << 0)
372
#define ADC_SCANCTRL_DIFF (0x1UL << 1)
373
#define _ADC_SCANCTRL_DIFF_SHIFT 1
374
#define _ADC_SCANCTRL_DIFF_MASK 0x2UL
375
#define _ADC_SCANCTRL_DIFF_DEFAULT 0x00000000UL
376
#define ADC_SCANCTRL_DIFF_DEFAULT (_ADC_SCANCTRL_DIFF_DEFAULT << 1)
377
#define ADC_SCANCTRL_ADJ (0x1UL << 2)
378
#define _ADC_SCANCTRL_ADJ_SHIFT 2
379
#define _ADC_SCANCTRL_ADJ_MASK 0x4UL
380
#define _ADC_SCANCTRL_ADJ_DEFAULT 0x00000000UL
381
#define _ADC_SCANCTRL_ADJ_RIGHT 0x00000000UL
382
#define _ADC_SCANCTRL_ADJ_LEFT 0x00000001UL
383
#define ADC_SCANCTRL_ADJ_DEFAULT (_ADC_SCANCTRL_ADJ_DEFAULT << 2)
384
#define ADC_SCANCTRL_ADJ_RIGHT (_ADC_SCANCTRL_ADJ_RIGHT << 2)
385
#define ADC_SCANCTRL_ADJ_LEFT (_ADC_SCANCTRL_ADJ_LEFT << 2)
386
#define _ADC_SCANCTRL_RES_SHIFT 4
387
#define _ADC_SCANCTRL_RES_MASK 0x30UL
388
#define _ADC_SCANCTRL_RES_DEFAULT 0x00000000UL
389
#define _ADC_SCANCTRL_RES_12BIT 0x00000000UL
390
#define _ADC_SCANCTRL_RES_8BIT 0x00000001UL
391
#define _ADC_SCANCTRL_RES_6BIT 0x00000002UL
392
#define _ADC_SCANCTRL_RES_OVS 0x00000003UL
393
#define ADC_SCANCTRL_RES_DEFAULT (_ADC_SCANCTRL_RES_DEFAULT << 4)
394
#define ADC_SCANCTRL_RES_12BIT (_ADC_SCANCTRL_RES_12BIT << 4)
395
#define ADC_SCANCTRL_RES_8BIT (_ADC_SCANCTRL_RES_8BIT << 4)
396
#define ADC_SCANCTRL_RES_6BIT (_ADC_SCANCTRL_RES_6BIT << 4)
397
#define ADC_SCANCTRL_RES_OVS (_ADC_SCANCTRL_RES_OVS << 4)
398
#define _ADC_SCANCTRL_INPUTMASK_SHIFT 8
399
#define _ADC_SCANCTRL_INPUTMASK_MASK 0xFF00UL
400
#define _ADC_SCANCTRL_INPUTMASK_DEFAULT 0x00000000UL
401
#define _ADC_SCANCTRL_INPUTMASK_CH0 0x00000001UL
402
#define _ADC_SCANCTRL_INPUTMASK_CH0CH1 0x00000001UL
403
#define _ADC_SCANCTRL_INPUTMASK_CH1 0x00000002UL
404
#define _ADC_SCANCTRL_INPUTMASK_CH2CH3 0x00000002UL
405
#define _ADC_SCANCTRL_INPUTMASK_CH2 0x00000004UL
406
#define _ADC_SCANCTRL_INPUTMASK_CH4CH5 0x00000004UL
407
#define _ADC_SCANCTRL_INPUTMASK_CH6CH7 0x00000008UL
408
#define _ADC_SCANCTRL_INPUTMASK_CH3 0x00000008UL
409
#define _ADC_SCANCTRL_INPUTMASK_CH4 0x00000010UL
410
#define _ADC_SCANCTRL_INPUTMASK_CH5 0x00000020UL
411
#define _ADC_SCANCTRL_INPUTMASK_CH6 0x00000040UL
412
#define _ADC_SCANCTRL_INPUTMASK_CH7 0x00000080UL
413
#define ADC_SCANCTRL_INPUTMASK_DEFAULT (_ADC_SCANCTRL_INPUTMASK_DEFAULT << 8)
414
#define ADC_SCANCTRL_INPUTMASK_CH0 (_ADC_SCANCTRL_INPUTMASK_CH0 << 8)
415
#define ADC_SCANCTRL_INPUTMASK_CH0CH1 (_ADC_SCANCTRL_INPUTMASK_CH0CH1 << 8)
416
#define ADC_SCANCTRL_INPUTMASK_CH1 (_ADC_SCANCTRL_INPUTMASK_CH1 << 8)
417
#define ADC_SCANCTRL_INPUTMASK_CH2CH3 (_ADC_SCANCTRL_INPUTMASK_CH2CH3 << 8)
418
#define ADC_SCANCTRL_INPUTMASK_CH2 (_ADC_SCANCTRL_INPUTMASK_CH2 << 8)
419
#define ADC_SCANCTRL_INPUTMASK_CH4CH5 (_ADC_SCANCTRL_INPUTMASK_CH4CH5 << 8)
420
#define ADC_SCANCTRL_INPUTMASK_CH6CH7 (_ADC_SCANCTRL_INPUTMASK_CH6CH7 << 8)
421
#define ADC_SCANCTRL_INPUTMASK_CH3 (_ADC_SCANCTRL_INPUTMASK_CH3 << 8)
422
#define ADC_SCANCTRL_INPUTMASK_CH4 (_ADC_SCANCTRL_INPUTMASK_CH4 << 8)
423
#define ADC_SCANCTRL_INPUTMASK_CH5 (_ADC_SCANCTRL_INPUTMASK_CH5 << 8)
424
#define ADC_SCANCTRL_INPUTMASK_CH6 (_ADC_SCANCTRL_INPUTMASK_CH6 << 8)
425
#define ADC_SCANCTRL_INPUTMASK_CH7 (_ADC_SCANCTRL_INPUTMASK_CH7 << 8)
426
#define _ADC_SCANCTRL_REF_SHIFT 16
427
#define _ADC_SCANCTRL_REF_MASK 0x70000UL
428
#define _ADC_SCANCTRL_REF_DEFAULT 0x00000000UL
429
#define _ADC_SCANCTRL_REF_1V25 0x00000000UL
430
#define _ADC_SCANCTRL_REF_2V5 0x00000001UL
431
#define _ADC_SCANCTRL_REF_VDD 0x00000002UL
432
#define _ADC_SCANCTRL_REF_5VDIFF 0x00000003UL
433
#define _ADC_SCANCTRL_REF_EXTSINGLE 0x00000004UL
434
#define _ADC_SCANCTRL_REF_2XEXTDIFF 0x00000005UL
435
#define _ADC_SCANCTRL_REF_2XVDD 0x00000006UL
436
#define ADC_SCANCTRL_REF_DEFAULT (_ADC_SCANCTRL_REF_DEFAULT << 16)
437
#define ADC_SCANCTRL_REF_1V25 (_ADC_SCANCTRL_REF_1V25 << 16)
438
#define ADC_SCANCTRL_REF_2V5 (_ADC_SCANCTRL_REF_2V5 << 16)
439
#define ADC_SCANCTRL_REF_VDD (_ADC_SCANCTRL_REF_VDD << 16)
440
#define ADC_SCANCTRL_REF_5VDIFF (_ADC_SCANCTRL_REF_5VDIFF << 16)
441
#define ADC_SCANCTRL_REF_EXTSINGLE (_ADC_SCANCTRL_REF_EXTSINGLE << 16)
442
#define ADC_SCANCTRL_REF_2XEXTDIFF (_ADC_SCANCTRL_REF_2XEXTDIFF << 16)
443
#define ADC_SCANCTRL_REF_2XVDD (_ADC_SCANCTRL_REF_2XVDD << 16)
444
#define _ADC_SCANCTRL_AT_SHIFT 20
445
#define _ADC_SCANCTRL_AT_MASK 0xF00000UL
446
#define _ADC_SCANCTRL_AT_DEFAULT 0x00000000UL
447
#define _ADC_SCANCTRL_AT_1CYCLE 0x00000000UL
448
#define _ADC_SCANCTRL_AT_2CYCLES 0x00000001UL
449
#define _ADC_SCANCTRL_AT_4CYCLES 0x00000002UL
450
#define _ADC_SCANCTRL_AT_8CYCLES 0x00000003UL
451
#define _ADC_SCANCTRL_AT_16CYCLES 0x00000004UL
452
#define _ADC_SCANCTRL_AT_32CYCLES 0x00000005UL
453
#define _ADC_SCANCTRL_AT_64CYCLES 0x00000006UL
454
#define _ADC_SCANCTRL_AT_128CYCLES 0x00000007UL
455
#define _ADC_SCANCTRL_AT_256CYCLES 0x00000008UL
456
#define ADC_SCANCTRL_AT_DEFAULT (_ADC_SCANCTRL_AT_DEFAULT << 20)
457
#define ADC_SCANCTRL_AT_1CYCLE (_ADC_SCANCTRL_AT_1CYCLE << 20)
458
#define ADC_SCANCTRL_AT_2CYCLES (_ADC_SCANCTRL_AT_2CYCLES << 20)
459
#define ADC_SCANCTRL_AT_4CYCLES (_ADC_SCANCTRL_AT_4CYCLES << 20)
460
#define ADC_SCANCTRL_AT_8CYCLES (_ADC_SCANCTRL_AT_8CYCLES << 20)
461
#define ADC_SCANCTRL_AT_16CYCLES (_ADC_SCANCTRL_AT_16CYCLES << 20)
462
#define ADC_SCANCTRL_AT_32CYCLES (_ADC_SCANCTRL_AT_32CYCLES << 20)
463
#define ADC_SCANCTRL_AT_64CYCLES (_ADC_SCANCTRL_AT_64CYCLES << 20)
464
#define ADC_SCANCTRL_AT_128CYCLES (_ADC_SCANCTRL_AT_128CYCLES << 20)
465
#define ADC_SCANCTRL_AT_256CYCLES (_ADC_SCANCTRL_AT_256CYCLES << 20)
466
#define ADC_SCANCTRL_PRSEN (0x1UL << 24)
467
#define _ADC_SCANCTRL_PRSEN_SHIFT 24
468
#define _ADC_SCANCTRL_PRSEN_MASK 0x1000000UL
469
#define _ADC_SCANCTRL_PRSEN_DEFAULT 0x00000000UL
470
#define ADC_SCANCTRL_PRSEN_DEFAULT (_ADC_SCANCTRL_PRSEN_DEFAULT << 24)
471
#define _ADC_SCANCTRL_PRSSEL_SHIFT 28
472
#define _ADC_SCANCTRL_PRSSEL_MASK 0x30000000UL
473
#define _ADC_SCANCTRL_PRSSEL_DEFAULT 0x00000000UL
474
#define _ADC_SCANCTRL_PRSSEL_PRSCH0 0x00000000UL
475
#define _ADC_SCANCTRL_PRSSEL_PRSCH1 0x00000001UL
476
#define _ADC_SCANCTRL_PRSSEL_PRSCH2 0x00000002UL
477
#define _ADC_SCANCTRL_PRSSEL_PRSCH3 0x00000003UL
478
#define ADC_SCANCTRL_PRSSEL_DEFAULT (_ADC_SCANCTRL_PRSSEL_DEFAULT << 28)
479
#define ADC_SCANCTRL_PRSSEL_PRSCH0 (_ADC_SCANCTRL_PRSSEL_PRSCH0 << 28)
480
#define ADC_SCANCTRL_PRSSEL_PRSCH1 (_ADC_SCANCTRL_PRSSEL_PRSCH1 << 28)
481
#define ADC_SCANCTRL_PRSSEL_PRSCH2 (_ADC_SCANCTRL_PRSSEL_PRSCH2 << 28)
482
#define ADC_SCANCTRL_PRSSEL_PRSCH3 (_ADC_SCANCTRL_PRSSEL_PRSCH3 << 28)
484
/* Bit fields for ADC IEN */
485
#define _ADC_IEN_RESETVALUE 0x00000000UL
486
#define _ADC_IEN_MASK 0x00000303UL
487
#define ADC_IEN_SINGLE (0x1UL << 0)
488
#define _ADC_IEN_SINGLE_SHIFT 0
489
#define _ADC_IEN_SINGLE_MASK 0x1UL
490
#define _ADC_IEN_SINGLE_DEFAULT 0x00000000UL
491
#define ADC_IEN_SINGLE_DEFAULT (_ADC_IEN_SINGLE_DEFAULT << 0)
492
#define ADC_IEN_SCAN (0x1UL << 1)
493
#define _ADC_IEN_SCAN_SHIFT 1
494
#define _ADC_IEN_SCAN_MASK 0x2UL
495
#define _ADC_IEN_SCAN_DEFAULT 0x00000000UL
496
#define ADC_IEN_SCAN_DEFAULT (_ADC_IEN_SCAN_DEFAULT << 1)
497
#define ADC_IEN_SINGLEOF (0x1UL << 8)
498
#define _ADC_IEN_SINGLEOF_SHIFT 8
499
#define _ADC_IEN_SINGLEOF_MASK 0x100UL
500
#define _ADC_IEN_SINGLEOF_DEFAULT 0x00000000UL
501
#define ADC_IEN_SINGLEOF_DEFAULT (_ADC_IEN_SINGLEOF_DEFAULT << 8)
502
#define ADC_IEN_SCANOF (0x1UL << 9)
503
#define _ADC_IEN_SCANOF_SHIFT 9
504
#define _ADC_IEN_SCANOF_MASK 0x200UL
505
#define _ADC_IEN_SCANOF_DEFAULT 0x00000000UL
506
#define ADC_IEN_SCANOF_DEFAULT (_ADC_IEN_SCANOF_DEFAULT << 9)
508
/* Bit fields for ADC IF */
509
#define _ADC_IF_RESETVALUE 0x00000000UL
510
#define _ADC_IF_MASK 0x00000303UL
511
#define ADC_IF_SINGLE (0x1UL << 0)
512
#define _ADC_IF_SINGLE_SHIFT 0
513
#define _ADC_IF_SINGLE_MASK 0x1UL
514
#define _ADC_IF_SINGLE_DEFAULT 0x00000000UL
515
#define ADC_IF_SINGLE_DEFAULT (_ADC_IF_SINGLE_DEFAULT << 0)
516
#define ADC_IF_SCAN (0x1UL << 1)
517
#define _ADC_IF_SCAN_SHIFT 1
518
#define _ADC_IF_SCAN_MASK 0x2UL
519
#define _ADC_IF_SCAN_DEFAULT 0x00000000UL
520
#define ADC_IF_SCAN_DEFAULT (_ADC_IF_SCAN_DEFAULT << 1)
521
#define ADC_IF_SINGLEOF (0x1UL << 8)
522
#define _ADC_IF_SINGLEOF_SHIFT 8
523
#define _ADC_IF_SINGLEOF_MASK 0x100UL
524
#define _ADC_IF_SINGLEOF_DEFAULT 0x00000000UL
525
#define ADC_IF_SINGLEOF_DEFAULT (_ADC_IF_SINGLEOF_DEFAULT << 8)
526
#define ADC_IF_SCANOF (0x1UL << 9)
527
#define _ADC_IF_SCANOF_SHIFT 9
528
#define _ADC_IF_SCANOF_MASK 0x200UL
529
#define _ADC_IF_SCANOF_DEFAULT 0x00000000UL
530
#define ADC_IF_SCANOF_DEFAULT (_ADC_IF_SCANOF_DEFAULT << 9)
532
/* Bit fields for ADC IFS */
533
#define _ADC_IFS_RESETVALUE 0x00000000UL
534
#define _ADC_IFS_MASK 0x00000303UL
535
#define ADC_IFS_SINGLE (0x1UL << 0)
536
#define _ADC_IFS_SINGLE_SHIFT 0
537
#define _ADC_IFS_SINGLE_MASK 0x1UL
538
#define _ADC_IFS_SINGLE_DEFAULT 0x00000000UL
539
#define ADC_IFS_SINGLE_DEFAULT (_ADC_IFS_SINGLE_DEFAULT << 0)
540
#define ADC_IFS_SCAN (0x1UL << 1)
541
#define _ADC_IFS_SCAN_SHIFT 1
542
#define _ADC_IFS_SCAN_MASK 0x2UL
543
#define _ADC_IFS_SCAN_DEFAULT 0x00000000UL
544
#define ADC_IFS_SCAN_DEFAULT (_ADC_IFS_SCAN_DEFAULT << 1)
545
#define ADC_IFS_SINGLEOF (0x1UL << 8)
546
#define _ADC_IFS_SINGLEOF_SHIFT 8
547
#define _ADC_IFS_SINGLEOF_MASK 0x100UL
548
#define _ADC_IFS_SINGLEOF_DEFAULT 0x00000000UL
549
#define ADC_IFS_SINGLEOF_DEFAULT (_ADC_IFS_SINGLEOF_DEFAULT << 8)
550
#define ADC_IFS_SCANOF (0x1UL << 9)
551
#define _ADC_IFS_SCANOF_SHIFT 9
552
#define _ADC_IFS_SCANOF_MASK 0x200UL
553
#define _ADC_IFS_SCANOF_DEFAULT 0x00000000UL
554
#define ADC_IFS_SCANOF_DEFAULT (_ADC_IFS_SCANOF_DEFAULT << 9)
556
/* Bit fields for ADC IFC */
557
#define _ADC_IFC_RESETVALUE 0x00000000UL
558
#define _ADC_IFC_MASK 0x00000303UL
559
#define ADC_IFC_SINGLE (0x1UL << 0)
560
#define _ADC_IFC_SINGLE_SHIFT 0
561
#define _ADC_IFC_SINGLE_MASK 0x1UL
562
#define _ADC_IFC_SINGLE_DEFAULT 0x00000000UL
563
#define ADC_IFC_SINGLE_DEFAULT (_ADC_IFC_SINGLE_DEFAULT << 0)
564
#define ADC_IFC_SCAN (0x1UL << 1)
565
#define _ADC_IFC_SCAN_SHIFT 1
566
#define _ADC_IFC_SCAN_MASK 0x2UL
567
#define _ADC_IFC_SCAN_DEFAULT 0x00000000UL
568
#define ADC_IFC_SCAN_DEFAULT (_ADC_IFC_SCAN_DEFAULT << 1)
569
#define ADC_IFC_SINGLEOF (0x1UL << 8)
570
#define _ADC_IFC_SINGLEOF_SHIFT 8
571
#define _ADC_IFC_SINGLEOF_MASK 0x100UL
572
#define _ADC_IFC_SINGLEOF_DEFAULT 0x00000000UL
573
#define ADC_IFC_SINGLEOF_DEFAULT (_ADC_IFC_SINGLEOF_DEFAULT << 8)
574
#define ADC_IFC_SCANOF (0x1UL << 9)
575
#define _ADC_IFC_SCANOF_SHIFT 9
576
#define _ADC_IFC_SCANOF_MASK 0x200UL
577
#define _ADC_IFC_SCANOF_DEFAULT 0x00000000UL
578
#define ADC_IFC_SCANOF_DEFAULT (_ADC_IFC_SCANOF_DEFAULT << 9)
580
/* Bit fields for ADC SINGLEDATA */
581
#define _ADC_SINGLEDATA_RESETVALUE 0x00000000UL
582
#define _ADC_SINGLEDATA_MASK 0xFFFFFFFFUL
583
#define _ADC_SINGLEDATA_DATA_SHIFT 0
584
#define _ADC_SINGLEDATA_DATA_MASK 0xFFFFFFFFUL
585
#define _ADC_SINGLEDATA_DATA_DEFAULT 0x00000000UL
586
#define ADC_SINGLEDATA_DATA_DEFAULT (_ADC_SINGLEDATA_DATA_DEFAULT << 0)
588
/* Bit fields for ADC SCANDATA */
589
#define _ADC_SCANDATA_RESETVALUE 0x00000000UL
590
#define _ADC_SCANDATA_MASK 0xFFFFFFFFUL
591
#define _ADC_SCANDATA_DATA_SHIFT 0
592
#define _ADC_SCANDATA_DATA_MASK 0xFFFFFFFFUL
593
#define _ADC_SCANDATA_DATA_DEFAULT 0x00000000UL
594
#define ADC_SCANDATA_DATA_DEFAULT (_ADC_SCANDATA_DATA_DEFAULT << 0)
596
/* Bit fields for ADC SINGLEDATAP */
597
#define _ADC_SINGLEDATAP_RESETVALUE 0x00000000UL
598
#define _ADC_SINGLEDATAP_MASK 0xFFFFFFFFUL
599
#define _ADC_SINGLEDATAP_DATAP_SHIFT 0
600
#define _ADC_SINGLEDATAP_DATAP_MASK 0xFFFFFFFFUL
601
#define _ADC_SINGLEDATAP_DATAP_DEFAULT 0x00000000UL
602
#define ADC_SINGLEDATAP_DATAP_DEFAULT (_ADC_SINGLEDATAP_DATAP_DEFAULT << 0)
604
/* Bit fields for ADC SCANDATAP */
605
#define _ADC_SCANDATAP_RESETVALUE 0x00000000UL
606
#define _ADC_SCANDATAP_MASK 0xFFFFFFFFUL
607
#define _ADC_SCANDATAP_DATAP_SHIFT 0
608
#define _ADC_SCANDATAP_DATAP_MASK 0xFFFFFFFFUL
609
#define _ADC_SCANDATAP_DATAP_DEFAULT 0x00000000UL
610
#define ADC_SCANDATAP_DATAP_DEFAULT (_ADC_SCANDATAP_DATAP_DEFAULT << 0)
612
/* Bit fields for ADC CAL */
613
#define _ADC_CAL_RESETVALUE 0x3F003F00UL
614
#define _ADC_CAL_MASK 0x7F7F7F7FUL
615
#define _ADC_CAL_SINGLEOFFSET_SHIFT 0
616
#define _ADC_CAL_SINGLEOFFSET_MASK 0x7FUL
617
#define _ADC_CAL_SINGLEOFFSET_DEFAULT 0x00000000UL
618
#define ADC_CAL_SINGLEOFFSET_DEFAULT (_ADC_CAL_SINGLEOFFSET_DEFAULT << 0)
619
#define _ADC_CAL_SINGLEGAIN_SHIFT 8
620
#define _ADC_CAL_SINGLEGAIN_MASK 0x7F00UL
621
#define _ADC_CAL_SINGLEGAIN_DEFAULT 0x0000003FUL
622
#define ADC_CAL_SINGLEGAIN_DEFAULT (_ADC_CAL_SINGLEGAIN_DEFAULT << 8)
623
#define _ADC_CAL_SCANOFFSET_SHIFT 16
624
#define _ADC_CAL_SCANOFFSET_MASK 0x7F0000UL
625
#define _ADC_CAL_SCANOFFSET_DEFAULT 0x00000000UL
626
#define ADC_CAL_SCANOFFSET_DEFAULT (_ADC_CAL_SCANOFFSET_DEFAULT << 16)
627
#define _ADC_CAL_SCANGAIN_SHIFT 24
628
#define _ADC_CAL_SCANGAIN_MASK 0x7F000000UL
629
#define _ADC_CAL_SCANGAIN_DEFAULT 0x0000003FUL
630
#define ADC_CAL_SCANGAIN_DEFAULT (_ADC_CAL_SCANGAIN_DEFAULT << 24)
632
/* Bit fields for ADC BIASPROG */
633
#define _ADC_BIASPROG_RESETVALUE 0x00000747UL
634
#define _ADC_BIASPROG_MASK 0x00000F4FUL
635
#define _ADC_BIASPROG_BIASPROG_SHIFT 0
636
#define _ADC_BIASPROG_BIASPROG_MASK 0xFUL
637
#define _ADC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL
638
#define ADC_BIASPROG_BIASPROG_DEFAULT (_ADC_BIASPROG_BIASPROG_DEFAULT << 0)
639
#define ADC_BIASPROG_HALFBIAS (0x1UL << 6)
640
#define _ADC_BIASPROG_HALFBIAS_SHIFT 6
641
#define _ADC_BIASPROG_HALFBIAS_MASK 0x40UL
642
#define _ADC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL
643
#define ADC_BIASPROG_HALFBIAS_DEFAULT (_ADC_BIASPROG_HALFBIAS_DEFAULT << 6)
644
#define _ADC_BIASPROG_COMPBIAS_SHIFT 8
645
#define _ADC_BIASPROG_COMPBIAS_MASK 0xF00UL
646
#define _ADC_BIASPROG_COMPBIAS_DEFAULT 0x00000007UL
647
#define ADC_BIASPROG_COMPBIAS_DEFAULT (_ADC_BIASPROG_COMPBIAS_DEFAULT << 8)
ADC_TypeDef::SINGLEDATAP
__I uint32_t SINGLEDATAP
Definition:
efm32zg_adc.h:54
__IO
#define __IO
Definition:
bsp_dk_bcreg_3201.h:53
ADC_TypeDef
Definition:
efm32zg_adc.h:41
ADC_TypeDef::BIASPROG
__IO uint32_t BIASPROG
Definition:
efm32zg_adc.h:59
ADC_TypeDef::SINGLECTRL
__IO uint32_t SINGLECTRL
Definition:
efm32zg_adc.h:46
ADC_TypeDef::IFS
__IO uint32_t IFS
Definition:
efm32zg_adc.h:50
ADC_TypeDef::CMD
__IO uint32_t CMD
Definition:
efm32zg_adc.h:44
ADC_TypeDef::SCANCTRL
__IO uint32_t SCANCTRL
Definition:
efm32zg_adc.h:47
ADC_TypeDef::SCANDATAP
__I uint32_t SCANDATAP
Definition:
efm32zg_adc.h:55
ADC_TypeDef::SCANDATA
__I uint32_t SCANDATA
Definition:
efm32zg_adc.h:53
ADC_TypeDef::SINGLEDATA
__I uint32_t SINGLEDATA
Definition:
efm32zg_adc.h:52
ADC_TypeDef::IF
__I uint32_t IF
Definition:
efm32zg_adc.h:49
ADC_TypeDef::STATUS
__I uint32_t STATUS
Definition:
efm32zg_adc.h:45
ADC_TypeDef::IFC
__IO uint32_t IFC
Definition:
efm32zg_adc.h:51
ADC_TypeDef::IEN
__IO uint32_t IEN
Definition:
efm32zg_adc.h:48
ADC_TypeDef::CTRL
__IO uint32_t CTRL
Definition:
efm32zg_adc.h:43
ADC_TypeDef::CAL
__IO uint32_t CAL
Definition:
efm32zg_adc.h:56
Device
SiliconLabs
EFM32ZG
Include
efm32zg_adc.h
Generated on Tue Dec 8 2015 15:38:39 for EFM32 Zero Gecko Software Documentation by
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