EFM32 Zero Gecko Software Documentation  efm32zg-doc-4.2.1
efm32zg222f32.h
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1 /**************************************************************************/
34 #ifndef EFM32ZG222F32_H
35 #define EFM32ZG222F32_H
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 /**************************************************************************/
46 /**************************************************************************/
52 typedef enum IRQn
53 {
54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
57  SVCall_IRQn = -5,
58  PendSV_IRQn = -2,
59  SysTick_IRQn = -1,
61 /****** EFM32ZG Peripheral Interrupt Numbers *********************************************/
62  DMA_IRQn = 0,
65  ACMP0_IRQn = 3,
66  ADC0_IRQn = 4,
67  I2C0_IRQn = 5,
72  LEUART0_IRQn = 10,
73  PCNT0_IRQn = 11,
74  RTC_IRQn = 12,
75  CMU_IRQn = 13,
76  VCMP_IRQn = 14,
77  MSC_IRQn = 15,
78  AES_IRQn = 16,
79 } IRQn_Type;
80 
81 /**************************************************************************/
86 #define __MPU_PRESENT 0
87 #define __VTOR_PRESENT 1
88 #define __NVIC_PRIO_BITS 2
89 #define __Vendor_SysTickConfig 0
93 /**************************************************************************/
99 #define _EFM32_ZERO_FAMILY 1
100 #define _EFM_DEVICE
101 #define _SILICON_LABS_32B_PLATFORM_1
102 #define _SILICON_LABS_32B_PLATFORM 1
104 /* If part number is not defined as compiler option, define it */
105 #if !defined(EFM32ZG222F32)
106 #define EFM32ZG222F32 1
107 #endif
108 
110 #define PART_NUMBER "EFM32ZG222F32"
113 #define FLASH_MEM_BASE ((uint32_t) 0x0UL)
114 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL)
115 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL)
116 #define FLASH_MEM_BITS ((uint32_t) 0x28UL)
117 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL)
118 #define AES_MEM_SIZE ((uint32_t) 0x400UL)
119 #define AES_MEM_END ((uint32_t) 0x400E03FFUL)
120 #define AES_MEM_BITS ((uint32_t) 0x10UL)
121 #define PER_MEM_BASE ((uint32_t) 0x40000000UL)
122 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL)
123 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL)
124 #define PER_MEM_BITS ((uint32_t) 0x20UL)
125 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL)
126 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL)
127 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL)
128 #define RAM_MEM_BITS ((uint32_t) 0x18UL)
129 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL)
130 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL)
131 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL)
132 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL)
135 #define FLASH_BASE (0x00000000UL)
136 #define FLASH_SIZE (0x00008000UL)
137 #define FLASH_PAGE_SIZE 1024
138 #define SRAM_BASE (0x20000000UL)
139 #define SRAM_SIZE (0x00001000UL)
140 #define __CM0PLUS_REV 0x001
141 #define PRS_CHAN_COUNT 4
142 #define DMA_CHAN_COUNT 4
145 #define AFCHAN_MAX 33
146 #define AFCHANLOC_MAX 7
147 
148 #define AFACHAN_MAX 25
149 
150 /* Part number capabilities */
151 
152 #define TIMER_PRESENT
153 #define TIMER_COUNT 2
154 #define ACMP_PRESENT
155 #define ACMP_COUNT 1
156 #define USART_PRESENT
157 #define USART_COUNT 1
158 #define IDAC_PRESENT
159 #define IDAC_COUNT 1
160 #define ADC_PRESENT
161 #define ADC_COUNT 1
162 #define LEUART_PRESENT
163 #define LEUART_COUNT 1
164 #define PCNT_PRESENT
165 #define PCNT_COUNT 1
166 #define I2C_PRESENT
167 #define I2C_COUNT 1
168 #define AES_PRESENT
169 #define AES_COUNT 1
170 #define DMA_PRESENT
171 #define DMA_COUNT 1
172 #define LE_PRESENT
173 #define LE_COUNT 1
174 #define MSC_PRESENT
175 #define MSC_COUNT 1
176 #define EMU_PRESENT
177 #define EMU_COUNT 1
178 #define RMU_PRESENT
179 #define RMU_COUNT 1
180 #define CMU_PRESENT
181 #define CMU_COUNT 1
182 #define PRS_PRESENT
183 #define PRS_COUNT 1
184 #define GPIO_PRESENT
185 #define GPIO_COUNT 1
186 #define VCMP_PRESENT
187 #define VCMP_COUNT 1
188 #define RTC_PRESENT
189 #define RTC_COUNT 1
190 #define HFXTAL_PRESENT
191 #define HFXTAL_COUNT 1
192 #define LFXTAL_PRESENT
193 #define LFXTAL_COUNT 1
194 #define WDOG_PRESENT
195 #define WDOG_COUNT 1
196 #define DBG_PRESENT
197 #define DBG_COUNT 1
198 #define BOOTLOADER_PRESENT
199 #define BOOTLOADER_COUNT 1
200 #define ANALOG_PRESENT
201 #define ANALOG_COUNT 1
202 
205 #define ARM_MATH_CM0PLUS
206 #include "arm_math.h" /* To get __CLZ definitions etc. */
207 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
208 #include "system_efm32zg.h" /* System Header */
209 
210 /**************************************************************************/
216 #include "efm32zg_aes.h"
217 #include "efm32zg_dma_ch.h"
218 #include "efm32zg_dma.h"
219 #include "efm32zg_msc.h"
220 #include "efm32zg_emu.h"
221 #include "efm32zg_rmu.h"
222 #include "efm32zg_cmu.h"
223 #include "efm32zg_timer_cc.h"
224 #include "efm32zg_timer.h"
225 #include "efm32zg_acmp.h"
226 #include "efm32zg_usart.h"
227 #include "efm32zg_prs_ch.h"
228 #include "efm32zg_prs.h"
229 #include "efm32zg_idac.h"
230 #include "efm32zg_gpio_p.h"
231 #include "efm32zg_gpio.h"
232 #include "efm32zg_vcmp.h"
233 #include "efm32zg_adc.h"
234 #include "efm32zg_leuart.h"
235 #include "efm32zg_pcnt.h"
236 #include "efm32zg_i2c.h"
237 #include "efm32zg_rtc.h"
238 #include "efm32zg_wdog.h"
239 #include "efm32zg_dma_descriptor.h"
240 #include "efm32zg_devinfo.h"
241 #include "efm32zg_romtable.h"
242 #include "efm32zg_calibrate.h"
243 
246 /**************************************************************************/
251 #define AES_BASE (0x400E0000UL)
252 #define DMA_BASE (0x400C2000UL)
253 #define MSC_BASE (0x400C0000UL)
254 #define EMU_BASE (0x400C6000UL)
255 #define RMU_BASE (0x400CA000UL)
256 #define CMU_BASE (0x400C8000UL)
257 #define TIMER0_BASE (0x40010000UL)
258 #define TIMER1_BASE (0x40010400UL)
259 #define ACMP0_BASE (0x40001000UL)
260 #define USART1_BASE (0x4000C400UL)
261 #define PRS_BASE (0x400CC000UL)
262 #define IDAC0_BASE (0x40004000UL)
263 #define GPIO_BASE (0x40006000UL)
264 #define VCMP_BASE (0x40000000UL)
265 #define ADC0_BASE (0x40002000UL)
266 #define LEUART0_BASE (0x40084000UL)
267 #define PCNT0_BASE (0x40086000UL)
268 #define I2C0_BASE (0x4000A000UL)
269 #define RTC_BASE (0x40080000UL)
270 #define WDOG_BASE (0x40088000UL)
271 #define CALIBRATE_BASE (0x0FE08000UL)
272 #define DEVINFO_BASE (0x0FE081B0UL)
273 #define ROMTABLE_BASE (0xF00FFFD0UL)
274 #define LOCKBITS_BASE (0x0FE04000UL)
275 #define USERDATA_BASE (0x0FE00000UL)
279 /**************************************************************************/
284 #define AES ((AES_TypeDef *) AES_BASE)
285 #define DMA ((DMA_TypeDef *) DMA_BASE)
286 #define MSC ((MSC_TypeDef *) MSC_BASE)
287 #define EMU ((EMU_TypeDef *) EMU_BASE)
288 #define RMU ((RMU_TypeDef *) RMU_BASE)
289 #define CMU ((CMU_TypeDef *) CMU_BASE)
290 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
291 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
292 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE)
293 #define USART1 ((USART_TypeDef *) USART1_BASE)
294 #define PRS ((PRS_TypeDef *) PRS_BASE)
295 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE)
296 #define GPIO ((GPIO_TypeDef *) GPIO_BASE)
297 #define VCMP ((VCMP_TypeDef *) VCMP_BASE)
298 #define ADC0 ((ADC_TypeDef *) ADC0_BASE)
299 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE)
300 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE)
301 #define I2C0 ((I2C_TypeDef *) I2C0_BASE)
302 #define RTC ((RTC_TypeDef *) RTC_BASE)
303 #define WDOG ((WDOG_TypeDef *) WDOG_BASE)
304 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE)
305 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE)
306 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
310 /**************************************************************************/
315 #include "efm32zg_prs_signals.h"
316 #include "efm32zg_dmareq.h"
317 #include "efm32zg_dmactrl.h"
318 
319 /**************************************************************************/
323 #define MSC_UNLOCK_CODE 0x1B71
324 #define EMU_UNLOCK_CODE 0xADE8
325 #define CMU_UNLOCK_CODE 0x580E
326 #define TIMER_UNLOCK_CODE 0xCE80
327 #define GPIO_UNLOCK_CODE 0xA534
333 /**************************************************************************/
338 #include "efm32zg_af_ports.h"
339 #include "efm32zg_af_pins.h"
340 
343 /**************************************************************************/
356 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
357  REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
358 
363 #ifdef __cplusplus
364 }
365 #endif
366 #endif /* EFM32ZG222F32_H */
IRQn
Definition: efm32zg222f32.h:52
EFM32ZG_PRS_CH register and bit field definitions.
EFM32ZG_DMA_CH register and bit field definitions.
EFM32ZG_PCNT register and bit field definitions.
EFM32ZG_DMA_DESCRIPTOR register and bit field definitions.
EFM32ZG_DEVINFO register and bit field definitions.
EFM32ZG_USART register and bit field definitions.
EFM32ZG_TIMER register and bit field definitions.
EFM32ZG_ACMP register and bit field definitions.
EFM32ZG_AES register and bit field definitions.
EFM32ZG_RTC register and bit field definitions.
EFM32ZG_WDOG register and bit field definitions.
EFM32ZG_DMA register and bit field definitions.
EFM32ZG_TIMER_CC register and bit field definitions.
EFM32ZG_MSC register and bit field definitions.
EFM32ZG_GPIO_P register and bit field definitions.
EFM32ZG_CALIBRATE register and bit field definitions.
EFM32ZG_VCMP register and bit field definitions.
enum IRQn IRQn_Type
EFM32ZG_LEUART register and bit field definitions.
EFM32ZG_RMU register and bit field definitions.
EFM32ZG_IDAC register and bit field definitions.
EFM32ZG_ADC register and bit field definitions.
CMSIS Cortex-M System Layer for EFM32 devices.
EFM32ZG_DMAREQ register and bit field definitions.
EFM32ZG_AF_PINS register and bit field definitions.
EFM32ZG_DMACTRL register and bit field definitions.
EFM32ZG_ROMTABLE register and bit field definitions.
EFM32ZG_PRS register and bit field definitions.
EFM32ZG_EMU register and bit field definitions.
EFM32ZG_GPIO register and bit field definitions.
EFM32ZG_I2C register and bit field definitions.
EFM32ZG_CMU register and bit field definitions.