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Kinetis SDK v.1.2 API Reference Manual
Rev. 0
Freescale Semiconductor, Inc.
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The section describes the enumerations, macros and data structures for KL46Z4 SIM HAL driver. KL46Z4 SIM code is shared by KL16Z4, KL26Z4, KL36Z4 and KL46Z4.
Files | |
file | fsl_sim_hal_MKL46Z4.h |
Macros | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
Enumerations | |
enum | clock_cop_src_kl46z4_t { kClockCopSrcLpoClk, kClockCopSrcAltClk } |
COP clock source select. More... | |
enum | clock_tpm_src_kl46z4_t { kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk } |
TPM clock source select. More... | |
enum | clock_lptmr_src_kl46z4_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk } |
LPTMR clock source select. More... | |
enum | clock_lpsci_src_kl46z4_t { kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk } |
UART0 clock source select. More... | |
enum | clock_sai_src_kl46z4_t { kClockSaiSrcSysClk = 0U, kClockSaiSrcOsc0erClk = 1U, kClockSaiSrcPllClk = 3U } |
SAI clock source. More... | |
enum | clock_pllfll_sel_kl46z4_t { kClockPllFllSelFll, kClockPllFllSelPll } |
SIM PLLFLLSEL clock source select. More... | |
enum | clock_er32k_src_kl46z4_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL) More... | |
enum | clock_clkout_src_kl46z4_t { kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U } |
SIM CLKOUT_SEL clock source select. More... | |
enum | clock_rtcout_src_kl46z4_t { kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz } |
SIM RTCCLKOUTSEL clock source select. More... | |
enum | sim_adc_pretrg_sel_kl46z4_t { kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM ADCx pre-trigger select. More... | |
enum | sim_adc_trg_sel_kl46z4_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U } |
SIM ADCx trigger select. More... | |
enum | sim_uart_rxsrc_kl46z4_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0 } |
SIM UART receive data source select. More... | |
enum | sim_uart_txsrc_kl46z4_t { kSimUartTxsrcPin, kSimUartTxsrcTpm1, kSimUartTxsrcTpm2, kSimUartTxsrcReserved } |
SIM UART transmit data source select. More... | |
enum | sim_lpsci_rxsrc_kl46z4_t { kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0 } |
SIM LPSCI receive data source select. More... | |
enum | sim_lpsci_txsrc_kl46z4_t { kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcTpm2, kSimLpsciTxsrcReserved } |
SIM LPSCI transmit data source select. More... | |
enum | sim_tpm_clk_sel_kl46z4_t { kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. More... | |
enum | sim_tpm_ch_src_kl46z4_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3 } |
SIM Timer/PWM x channel y input capture source select. More... | |
enum | sim_clock_gate_name_kl46z4_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateSai0 = FSL_SIM_SCGC_BIT(6U, 15U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |