This section describes the programming interface of the SDHC HAL driver.
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#define | SDHC_HAL_DAT0_LEVEL (SDHC_PRSSTAT_DLSL_MASK & (1 << 24)) |
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#define | SDHC_HAL_MAX_BLOCK_COUNT ((1 << SDHC_BLKATTR_BLKCNT_WIDTH) - 1) |
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#define | SDHC_HAL_ENABLE_DMA SDHC_XFERTYP_DMAEN_MASK |
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#define | SDHC_HAL_CMD_TYPE_SUSPEND (SDHC_XFERTYP_CMDTYP(1)) |
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#define | SDHC_HAL_CMD_TYPE_RESUME (SDHC_XFERTYP_CMDTYP(2)) |
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#define | SDHC_HAL_CMD_TYPE_ABORT (SDHC_XFERTYP_CMDTYP(3)) |
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#define | SDHC_HAL_ENABLE_BLOCK_COUNT SDHC_XFERTYP_BCEN_MASK |
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#define | SDHC_HAL_ENABLE_AUTO_CMD12 SDHC_XFERTYP_AC12EN_MASK |
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#define | SDHC_HAL_ENABLE_DATA_READ SDHC_XFERTYP_DTDSEL_MASK |
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#define | SDHC_HAL_MULTIPLE_BLOCK SDHC_XFERTYP_MSBSEL_MASK |
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#define | SDHC_HAL_RESP_LEN_136 ((0x1 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK) |
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#define | SDHC_HAL_RESP_LEN_48 ((0x2 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK) |
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#define | SDHC_HAL_RESP_LEN_48_BC ((0x3 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK) |
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#define | SDHC_HAL_ENABLE_CRC_CHECK SDHC_XFERTYP_CCCEN_MASK |
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#define | SDHC_HAL_ENABLE_INDEX_CHECK SDHC_XFERTYP_CICEN_MASK |
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#define | SDHC_HAL_DATA_PRESENT SDHC_XFERTYP_DPSEL_MASK |
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#define | SDHC_HAL_MAX_DVS (16U) |
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#define | SDHC_HAL_INITIAL_DVS (1U) /* initial value of divisor to calculate clock rate */ |
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#define | SDHC_HAL_INITIAL_CLKFS (2U) /* initial value of clock selector to calculate clock rate */ |
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#define | SDHC_HAL_NEXT_DVS(x) do { ((x) += 1); } while(0) |
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#define | SDHC_HAL_PREV_DVS(x) do { ((x) -= 1); } while(0) |
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#define | SDHC_HAL_MAX_CLKFS (256U) |
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#define | SDHC_HAL_NEXT_CLKFS(x) do { ((x) <<= 1); } while(0) |
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#define | SDHC_HAL_PREV_CLKFS(x) do { ((x) >>= 1); } while(0) |
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#define | SDHC_HAL_CMD_COMPLETE_INT SDHC_IRQSTAT_CC_MASK |
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#define | SDHC_HAL_DATA_COMPLETE_INT SDHC_IRQSTAT_TC_MASK |
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#define | SDHC_HAL_BLOCK_GAP_EVENT_INT SDHC_IRQSTAT_BGE_MASK |
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#define | SDHC_HAL_DMA_INT SDHC_IRQSTAT_DINT_MASK |
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#define | SDHC_HAL_DMA_ERR_INT SDHC_IRQSTAT_DMAE_MASK |
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#define | SDHC_HAL_BUF_WRITE_READY_INT SDHC_IRQSTAT_BWR_MASK |
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#define | SDHC_HAL_BUF_READ_READY_INT SDHC_IRQSTAT_BRR_MASK |
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#define | SDHC_HAL_CARD_INSERTION_INT SDHC_IRQSTAT_CINS_MASK |
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#define | SDHC_HAL_CARD_REMOVAL_INT SDHC_IRQSTAT_CRM_MASK |
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#define | SDHC_HAL_CARD_INT SDHC_IRQSTAT_CINT_MASK |
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#define | SDHC_HAL_CMD_TIMEOUT_ERR_INT SDHC_IRQSTAT_CTOE_MASK |
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#define | SDHC_HAL_CMD_CRC_ERR_INT SDHC_IRQSTAT_CCE_MASK |
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#define | SDHC_HAL_CMD_END_BIT_ERR_INT SDHC_IRQSTAT_CEBE_MASK |
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#define | SDHC_HAL_CMD_INDEX_ERR_INT SDHC_IRQSTAT_CIE_MASK |
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#define | SDHC_HAL_DATA_TIMEOUT_ERR_INT SDHC_IRQSTAT_DTOE_MASK |
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#define | SDHC_HAL_DATA_CRC_ERR_INT SDHC_IRQSTAT_DCE_MASK |
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#define | SDHC_HAL_DATA_END_BIT_ERR_INT SDHC_IRQSTAT_DEBE_MASK |
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#define | SDHC_HAL_AUTO_CMD12_ERR_INT SDHC_IRQSTAT_AC12E_MASK |
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#define | SDHC_HAL_CMD_ERR_INT |
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#define | SDHC_HAL_DATA_ERR_INT |
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#define | SDHC_HAL_DATA_ALL_INT |
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#define | SDHC_HAL_CMD_ALL_INT |
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#define | SDHC_HAL_CD_ALL_INT |
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#define | SDHC_HAL_ALL_ERR_INT |
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#define | SDHC_HAL_ACMD12_NOT_EXEC_ERR SDHC_AC12ERR_AC12NE_MASK |
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#define | SDHC_HAL_ACMD12_TIMEOUT_ERR SDHC_AC12ERR_AC12TOE_MASK |
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#define | SDHC_HAL_ACMD12_END_BIT_ERR SDHC_AC12ERR_AC12EBE_MASK |
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#define | SDHC_HAL_ACMD12_CRC_ERR SDHC_AC12ERR_AC12CE_MASK |
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#define | SDHC_HAL_ACMD12_INDEX_ERR SDHC_AC12ERR_AC12IE_MASK |
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#define | SDHC_HAL_ACMD12_NOT_ISSUE_ERR SDHC_AC12ERR_CNIBAC12E_MASK |
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#define | SDHC_HAL_ADMA_STATE_ERR SDHC_ADMAES_ADMAES_MASK |
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#define | SDHC_HAL_ADMA_LEN_MIS_MATCH_FLAG SDHC_ADMAES_ADMALME_MASK |
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#define | SDHC_HAL_ADMA_DESP_ERR_FLAG SDHC_ADMAES_ADMADCE_MASK |
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#define | SDHC_HAL_SUPPORT_ADMA SDHC_HTCAPBLT_ADMAS_MASK |
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#define | SDHC_HAL_SUPPORT_HIGHSPEED SDHC_HTCAPBLT_HSS_MASK |
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#define | SDHC_HAL_SUPPORT_DMA SDHC_HTCAPBLT_DMAS_MASK |
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#define | SDHC_HAL_SUPPORT_SUSPEND_RESUME SDHC_HTCAPBLT_SRS_MASK |
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#define | SDHC_HAL_SUPPORT_3_3_V SDHC_HTCAPBLT_VS33_MASK |
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#define | SDHC_HAL_SUPPORT_3_0_V SDHC_HTCAPBLT_VS30_MASK |
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#define | SDHC_HAL_SUPPORT_1_8_V SDHC_HTCAPBLT_VS18_MASK |
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#define | SDHC_HAL_ACMD12_NOT_EXEC_ERR_EVENT SDHC_FEVT_AC12NE_MASK |
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#define | SDHC_HAL_ACMD12_TIMEOUT_ERR_EVENT SDHC_FEVT_AC12TOE_MASK |
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#define | SDHC_HAL_ACMD12_CRC_ERR_EVENT SDHC_FEVT_AC12CE_MASK |
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#define | SDHC_HAL_ACMD12_END_BIT_ERR_EVENT SDHC_FEVT_AC12EBE_MASK |
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#define | SDHC_HAL_ACMD12_INDEX_ERR_EVENT SDHC_FEVT_AC12IE_MASK |
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#define | SDHC_HAL_ACMD12_NOT_ISSUE_ERR_EVENT SDHC_FEVT_CNIBAC12E_MASK |
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#define | SDHC_HAL_CMD_TIMEOUT_ERR_EVENT SDHC_FEVT_CTOE_MASK |
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#define | SDHC_HAL_CMD_CRC_ERR_EVENT SDHC_FEVT_CCE_MASK |
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#define | SDHC_HAL_CMD_END_BIT_ERR_EVENT SDHC_FEVT_CEBE_MASK |
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#define | SDHC_HAL_CMD_INDEX_ERR_EVENT SDHC_FEVT_CIE_MASK |
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#define | SDHC_HAL_DATA_TIMEOUT_ERR_EVENT SDHC_FEVT_DTOE_MASK |
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#define | SDHC_HAL_DATA_CRC_ERR_EVENT SDHC_FEVT_DCE_MASK |
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#define | SDHC_HAL_DATA_END_BIT_ERR_EVENT SDHC_FEVT_DEBE_MASK |
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#define | SDHC_HAL_ACMD12_ERR_EVENT SDHC_FEVT_AC12E_MASK |
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#define | SDHC_HAL_CARD_INT_EVENT SDHC_FEVT_CINT_MASK |
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#define | SDHC_HAL_DMA_ERROR_EVENT SDHC_FEVT_DMAE_MASK |
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#define | SDHC_HAL_ADMA1_ADDR_ALIGN (4096) |
| SDHC ADMA address alignment size and length alignment size.
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#define | SDHC_HAL_ADMA1_LEN_ALIGN (4096) |
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#define | SDHC_HAL_ADMA2_ADDR_ALIGN (4) |
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#define | SDHC_HAL_ADMA2_LEN_ALIGN (4) |
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#define | SDHC_HAL_ADMA1_DESC_VALID_MASK (1 << 0) |
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#define | SDHC_HAL_ADMA1_DESC_END_MASK (1 << 1) |
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#define | SDHC_HAL_ADMA1_DESC_INT_MASK (1 << 2) |
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#define | SDHC_HAL_ADMA1_DESC_ACT1_MASK (1 << 4) |
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#define | SDHC_HAL_ADMA1_DESC_ACT2_MASK (1 << 5) |
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#define | SDHC_HAL_ADMA1_DESC_TYPE_NOP (SDHC_HAL_ADMA1_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA1_DESC_TYPE_TRAN (SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA1_DESC_TYPE_LINK (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA1_DESC_TYPE_SET (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT (12) |
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#define | SDHC_HAL_ADMA1_DESC_ADDRESS_MASK (0xFFFFFU) |
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#define | SDHC_HAL_ADMA1_DESC_LEN_SHIFT (12) |
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#define | SDHC_HAL_ADMA1_DESC_LEN_MASK (0xFFFFU) |
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#define | SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA1_DESC_LEN_MASK + 1) |
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#define | SDHC_HAL_ADMA2_DESC_VALID_MASK (1 << 0) |
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#define | SDHC_HAL_ADMA2_DESC_END_MASK (1 << 1) |
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#define | SDHC_HAL_ADMA2_DESC_INT_MASK (1 << 2) |
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#define | SDHC_HAL_ADMA2_DESC_ACT1_MASK (1 << 4) |
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#define | SDHC_HAL_ADMA2_DESC_ACT2_MASK (1 << 5) |
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#define | SDHC_HAL_ADMA2_DESC_TYPE_NOP (SDHC_HAL_ADMA2_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA2_DESC_TYPE_RCV (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA2_DESC_TYPE_TRAN (SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA2_DESC_TYPE_LINK (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) |
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#define | SDHC_HAL_ADMA2_DESC_LEN_SHIFT (16) |
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#define | SDHC_HAL_ADMA2_DESC_LEN_MASK (0xFFFFU) |
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#define | SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA2_DESC_LEN_MASK) |
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#define | SDHC_HAL_RST_TYPE_ALL SDHC_SYSCTL_RSTA_MASK |
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#define | SDHC_HAL_RST_TYPE_CMD SDHC_SYSCTL_RSTC_MASK |
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#define | SDHC_HAL_RST_TYPE_DATA SDHC_SYSCTL_RSTD_MASK |
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#define | SDHC_HAL_MAX_BLKLEN_512B (0U) |
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#define | SDHC_HAL_MAX_BLKLEN_1024B (1U) |
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#define | SDHC_HAL_MAX_BLKLEN_2048B (2U) |
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#define | SDHC_HAL_MAX_BLKLEN_4096B (3U) |
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#define | SDHC_HAL_SUPPORT_V330_FLAG (1U << 0) |
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#define | SDHC_HAL_SUPPORT_V300_FLAG (1U << 1) |
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#define | SDHC_HAL_SUPPORT_HIGHSPEED_FLAG (1U << 2) |
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#define | SDHC_HAL_SUPPORT_DMA_FLAG (1U << 3) |
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#define | SDHC_HAL_SUPPORT_ADMA_FLAG (1U << 4) |
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#define | SDHC_HAL_SUPPORT_SUSPEND_RESUME_FLAG (1U << 5) |
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#define | SDHC_HAL_SUPPORT_V180_FLAG (1U << 6) |
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#define | SDHC_HAL_SUPPORT_EXDMA_FLAG (1U << 7) |
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#define | SDHC_HAL_EN_D3CD_FLAG (1U << 0) |
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#define | SDHC_HAL_EN_CD_SIG_SEL_FLAG (1U << 1) |
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#define | SDHC_HAL_EN_STOP_AT_BLK_GAP_FLAG (1U << 2) |
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#define | SDHC_HAL_EN_READ_WAIT_CTRL_FLAG (1U << 3) |
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#define | SDHC_HAL_EN_INT_STOP_AT_BLK_GAP_FLAG (1U << 4) |
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#define | SDHC_HAL_EN_WAKEUP_ON_CARD_INT_FLAG (1U << 5) |
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#define | SDHC_HAL_EN_WAKEUP_ON_CARD_INS_FLAG (1U << 6) |
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#define | SDHC_HAL_EN_WAKEUP_ON_CARD_REM_FLAG (1U << 7) |
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#define | SDHC_HAL_EN_EXT_DMA_REQ_FLAG (1U << 8) |
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#define | SDHC_HAL_EN_EXACT_BLK_NUM_FLAG (1U << 9) |
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#define | SDHC_HAL_EN_BOOT_ACK_FLAG (1 << 0) |
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#define | SDHC_HAL_EN_FAST_BOOT_FLAG (1 << 1) |
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#define | SDHC_HAL_EN_BOOT_STOP_AT_BLK_GAP_FLAG (1 << 2) |
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void | SDHC_HAL_SendCmd (SDHC_Type *base, const sdhc_hal_cmd_req_t *cmdReq) |
| Sends command to card. More...
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static void | SDHC_HAL_SetData (SDHC_Type *base, uint32_t data) |
| Fills the the data port. More...
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static uint32_t | SDHC_HAL_GetData (SDHC_Type *base) |
| Retrieves the data from the data port. More...
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bool | SDHC_HAL_GetCurState (SDHC_Type *base, sdhc_hal_curstat_type_t stateType) |
| Gets current card's status. More...
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static void | SDHC_HAL_SetDataTransferWidth (SDHC_Type *base, sdhc_hal_dtw_t dtw) |
| Sets the data transfer width. More...
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static void | SDHC_HAL_SetContinueRequest (SDHC_Type *base) |
| Restarts a transaction which has stopped at the block gap. More...
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void | SDHC_HAL_Config (SDHC_Type *base, const sdhc_hal_config_t *initConfig) |
| Initialize the SDHC according to the configuration user input. More...
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void | SDHC_HAL_ConfigSdClock (SDHC_Type *base, sdhc_hal_sdclk_config_t *clkConfItms) |
| Sets SDHC SD protol unit clock. More...
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static uint32_t | SDHC_HAL_GetIntFlags (SDHC_Type *base) |
| Gets the current interrupt status. More...
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static void | SDHC_HAL_ClearIntFlags (SDHC_Type *base, uint32_t mask) |
| Clears a specified interrupt status. More...
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void | SDHC_HAL_GetAllErrStatus (SDHC_Type *base, sdhc_hal_err_type_t errType, uint32_t *errFlags) |
| Get the error status of SDHC . More...
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static void | SDHC_HAL_SetForceEventFlags (SDHC_Type *base, uint32_t mask) |
| Sets the force events according to the given mask. More...
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static void | SDHC_HAL_SetAdmaAddress (SDHC_Type *base, uint32_t address) |
| Sets the ADMA address. More...
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uint32_t | SDHC_HAL_GetResponse (SDHC_Type *base, uint32_t index) |
| Gets the command response. More...
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void | SDHC_HAL_SetIntSignal (SDHC_Type *base, bool enable, uint32_t mask) |
| Enables the specified interrupts. More...
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void | SDHC_HAL_SetIntState (SDHC_Type *base, bool enable, uint32_t mask) |
| Enables the specified interrupt state. More...
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uint32_t | SDHC_HAL_Reset (SDHC_Type *base, uint32_t type, uint32_t timeout) |
| Performs an SDHC reset. More...
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uint32_t | SDHC_HAL_InitCard (SDHC_Type *base, uint32_t timeout) |
| Sends 80 clocks to the card to initialize the card. More...
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void | SDHC_HAL_Init (SDHC_Type *base) |
| Initializes the SDHC HAL. More...
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void | SDHC_HAL_GetBasicInfo (SDHC_Type *base, sdhc_hal_basic_info_t *basicInfo) |
| Get the capability of SDHC. More...
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