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Kinetis SDK v.1.2 API Reference Manual
Rev. 0
Freescale Semiconductor, Inc.
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The section describes the enumerations, macros and data structures for K51D10 SIM HAL driver.
Files | |
file | fsl_sim_hal_MK51D10.h |
Macros | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
Enumerations | |
enum | clock_wdog_src_k51d10_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_trace_src_k51d10_t { kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk } |
Debug trace clock source select. More... | |
enum | clock_port_filter_src_k51d10_t { kClockPortFilterSrcBusClk, kClockPortFilterSrcLpoClk } |
PORTx digital input filter clock source select. More... | |
enum | clock_lptmr_src_k51d10_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk } |
LPTMR clock source select. More... | |
enum | clock_time_src_k51d10_t { kClockTimeSrcCoreSysClk, kClockTimeSrcPllFllSel, kClockTimeSrcOsc0erClk, kClockTimeSrcExt } |
SIM timestamp clock source. More... | |
enum | clock_rmii_src_k51d10_t { kClockRmiiSrcExtalClk, kClockRmiiSrcExt } |
SIM RMII clock source. More... | |
enum | clock_flexcan_src_k51d10_t { kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk } |
FLEXCAN clock source select. More... | |
enum | clock_sdhc_src_k51d10_t { kClockSdhcSrcCoreSysClk, kClockSdhcSrcPllFllSel, kClockSdhcSrcOsc0erClk, kClockSdhcSrcExt } |
SDHC clock source. More... | |
enum | clock_sai_src_k51d10_t { kClockSaiSrcSysClk = 0U, kClockSaiSrcOsc0erClk = 1U, kClockSaiSrcPllClk = 3U } |
SAI clock source. More... | |
enum | clock_tsi_active_mode_src_k51d10_t { kClockTsiActiveSrcBusClk, kClockTsiActiveSrcMcgIrClk, kClockTsiActiveSrcOsc0erClk } |
TSI Active Mode clock source. More... | |
enum | clock_tsi_lp_mode_src_k51d10_t { kClockTsiLpSrcLpoClk, kClockTsiLpSrcEr32kClk } |
TSI Low-power Mode clock source. More... | |
enum | clock_pllfll_sel_k51d10_t { kClockPllFllSelFll = 0U, kClockPllFllSelPll = 1U } |
SIM PLLFLLSEL clock source select. More... | |
enum | clock_er32k_src_k51d10_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_clkout_src_k51d10_t { kClockClkoutSelFlexbusClk = 0U, kClockClkoutSelFlashClk = 2U, kClockClkoutSelLpoClk = 3U, kClockClkoutSelMcgIrClk = 4U, kClockClkoutSelRtc32kClk = 5U, kClockClkoutSelOsc0erClk = 6U } |
SIM CLKOUT_SEL clock source select. More... | |
enum | clock_rtcout_src_k51d10_t { kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz } |
SIM RTCCLKOUTSEL clock source select. More... | |
enum | sim_adc_pretrg_sel_k51d10_t { kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM ADCx pre-trigger select. More... | |
enum | sim_adc_trg_sel_k51d10_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm2 = 10U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U } |
SIM ADCx trigger select. More... | |
enum | sim_uart_rxsrc_k51d10_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1 } |
SIM UART receive data source select. More... | |
enum | sim_uart_txsrc_k51d10_t { kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcFtm2 } |
SIM UART transmit data source select. More... | |
enum | sim_ftm_trg_src_k51d10_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. More... | |
enum | sim_ftm_clk_sel_k51d10_t { kSimFtmClkSel0, kSimFtmClkSel1 } |
SIM FlexTimer external clock select. More... | |
enum | sim_ftm_ch_src_k51d10_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. More... | |
enum | sim_ftm_flt_sel_k51d10_t { kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. More... | |
enum | sim_tpm_clk_sel_k51d10_t { kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. More... | |
enum | sim_tpm_ch_src_k51d10_t { kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. More... | |
enum | sim_cmtuartpad_strengh_k51d10_t { kSimCmtuartSinglePad, kSimCmtuartDualPad } |
SIM CMT/UART pad drive strength. More... | |
enum | sim_ptd7pad_strengh_k51d10_t { kSimPtd7padSinglePad, kSimPtd7padDualPad } |
SIM PTD7 pad drive strength. More... | |
enum | sim_flexbus_security_level_k51d10_t { kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3 } |
SIM FlexBus security level. More... | |
enum | sim_clock_gate_name_k51d10_t { kSimClockGateUart4 = FSL_SIM_SCGC_BIT(1U, 10U), kSimClockGateUart5 = FSL_SIM_SCGC_BIT(1U, 11U), kSimClockGateEnet0 = FSL_SIM_SCGC_BIT(2U, 0U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(2U, 12U), kSimClockGateDac1 = FSL_SIM_SCGC_BIT(2U, 13U), kSimClockGateRnga0 = FSL_SIM_SCGC_BIT(3U, 0U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(3U, 4U), kSimClockGateSpi2 = FSL_SIM_SCGC_BIT(3U, 12U), kSimClockGateSdhc0 = FSL_SIM_SCGC_BIT(3U, 17U), kSimClockGateFtm2 = FSL_SIM_SCGC_BIT(3U, 24U), kSimClockGateAdc1 = FSL_SIM_SCGC_BIT(3U, 27U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateCmt0 = FSL_SIM_SCGC_BIT(4U, 2U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUart3 = FSL_SIM_SCGC_BIT(4U, 13U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateVref0 = FSL_SIM_SCGC_BIT(4U, 20U), kSimClockGateLlwu0 = FSL_SIM_SCGC_BIT(4U, 28U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(6U, 13U), kSimClockGateSai0 = FSL_SIM_SCGC_BIT(6U, 15U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateFlexbus0 = FSL_SIM_SCGC_BIT(7U, 0U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 1U), kSimClockGateMpu0 = FSL_SIM_SCGC_BIT(7U, 2U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |