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Kinetis SDK v.1.2 API Reference Manual
Rev. 0
Freescale Semiconductor, Inc.
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The section describes the programming interface of the SIM HAL driver. The system integration module (SIM) provides the system control and device configuration registers. The sim_hal provides a set of API functions used to access the SIM registers including clock gate control and other configuration settings.
Clock gate control is based on the module. Each chip has a sub-set of modules that can be gated through gate control registers in SIM. The gate control names are defined in the enumeration sim_clock_gate_name_t. Pass the enumeration value and the parameter enables/disables the clock for a module accordingly. There is an example for clock gate APIs:
Clock source control is also based on the module. Only certain modules have the clock source control in SIM. For these modules, SIM HAL driver provides the separate APIs to set or get module source. The module source setting values are defined in the enumeration with the prefix clock_. For example, USB FS OTG module uses the MCGPLLFLLCLK or the external USB_CLKIN as a clock source. Therefore, the SIM HAL driver provides these for the USB FS OTG module clock source:
For other IP modules, the clock source selection register is in IP module, but the clock distribution is controlled by the system integration. Therefore, the SIM HAL driver provides the information for the IP modules and IP drivers know which clock sources are available and how to set their internal register to select a different clock source. This information is provided as an enumeration, such as SAI module using SYSCLK, OSC0ERCLK and MCGPLLCLK as a clock source. The SIM HAL driver provides:
See the appropriate reference manual for details.
Certain clocks use dividers configured in SIM module. The SIM HAL driver provides API functins to get/set the divider values. For example:
Files | |
file | fsl_sim_hal.h |
file | fsl_sim_hal_MKL14Z4.h |
file | fsl_sim_hal_MKL15Z4.h |
file | fsl_sim_hal_MKL24Z4.h |
file | fsl_sim_hal_MKL25Z4.h |
file | fsl_sim_hal_MKV40F15.h |
file | fsl_sim_hal_MKV43F15.h |
file | fsl_sim_hal_MKV44F15.h |
file | fsl_sim_hal_MKV45F15.h |
file | fsl_sim_hal_MKV46F15.h |
Macros | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
Enumerations | |
enum | sim_hal_status_t { kSimHalSuccess, kSimHalFail } |
SIM HAL API return status. More... | |
enum | clock_cop_src_t { kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk } |
COP clock source select. | |
enum | clock_tpm_src_t { kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk } |
TPM clock source select. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_lpsci_src_t { kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk } |
UART0 clock source select. | |
enum | clock_pllfll_sel_t { kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll } |
USB clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL) More... | |
enum | clock_clkout_src_t { kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U } |
SIM CLKOUT_SEL clock source select. | |
enum | clock_rtcout_src_t { kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz } |
SIM RTCCLKOUTSEL clock source select. | |
enum | sim_adc_pretrg_sel_t { kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM USB voltage regulator in standby mode setting during stop modes. More... | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADCx trigger select. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_lpsci_rxsrc_t { kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0 } |
SIM LPSCI receive data source select. | |
enum | sim_lpsci_txsrc_t { kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved } |
SIM LPSCI transmit data source select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
enum | clock_cop_src_t { kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk } |
COP clock source select. | |
enum | clock_tpm_src_t { kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk } |
TPM clock source select. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_lpsci_src_t { kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk } |
UART0 clock source select. | |
enum | clock_pllfll_sel_t { kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll } |
USB clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL) More... | |
enum | clock_clkout_src_t { kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U } |
SIM CLKOUT_SEL clock source select. | |
enum | clock_rtcout_src_t { kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz } |
SIM RTCCLKOUTSEL clock source select. | |
enum | sim_adc_pretrg_sel_t { kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM USB voltage regulator in standby mode setting during stop modes. More... | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADCx trigger select. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_lpsci_rxsrc_t { kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0 } |
SIM LPSCI receive data source select. | |
enum | sim_lpsci_txsrc_t { kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved } |
SIM LPSCI transmit data source select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
enum | clock_cop_src_t { kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk } |
COP clock source select. | |
enum | clock_tpm_src_t { kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk } |
TPM clock source select. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_lpsci_src_t { kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk } |
UART0 clock source select. | |
enum | clock_pllfll_sel_t { kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll } |
USB clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL) More... | |
enum | clock_clkout_src_t { kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U } |
SIM CLKOUT_SEL clock source select. | |
enum | clock_rtcout_src_t { kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz } |
SIM RTCCLKOUTSEL clock source select. | |
enum | sim_adc_pretrg_sel_t { kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM USB voltage regulator in standby mode setting during stop modes. More... | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADCx trigger select. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_lpsci_rxsrc_t { kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0 } |
SIM LPSCI receive data source select. | |
enum | sim_lpsci_txsrc_t { kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved } |
SIM LPSCI transmit data source select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
enum | clock_cop_src_t { kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk, kClockCopSrcLpoClk, kClockCopSrcAltClk } |
COP clock source select. | |
enum | clock_tpm_src_t { kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk, kClockTpmSrcNone, kClockTpmSrcPllFllSel, kClockTpmSrcOsc0erClk, kClockTpmSrcMcgIrClk } |
TPM clock source select. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_lpsci_src_t { kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk, kClockLpsciSrcNone, kClockLpsciSrcPllFllSel, kClockLpsciSrcOsc0erClk, kClockLpsciSrcMcgIrClk } |
UART0 clock source select. | |
enum | clock_pllfll_sel_t { kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll, kClockPllFllSelFll, kClockPllFllSelPll } |
USB clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL) More... | |
enum | clock_clkout_src_t { kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U, kClockClkoutReserved = 0U, kClockClkoutReserved1 = 1U, kClockClkoutBusClk = 2U, kClockClkoutLpoClk = 3U, kClockClkoutMcgIrClk = 4U, kClockClkoutReserved2 = 5U, kClockClkoutOsc0erClk = 6U, kClockClkoutReserved3 = 7U } |
SIM CLKOUT_SEL clock source select. | |
enum | clock_rtcout_src_t { kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz, kClockRtcoutSrc1Hz, kClockRtcoutSrc32kHz } |
SIM RTCCLKOUTSEL clock source select. | |
enum | sim_adc_pretrg_sel_t { kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB, kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM USB voltage regulator in standby mode setting during stop modes. More... | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADCx trigger select. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_lpsci_rxsrc_t { kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0, kSimLpsciRxsrcPin, kSimLpsciRxsrcCmp0 } |
SIM LPSCI receive data source select. | |
enum | sim_lpsci_txsrc_t { kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved, kSimLpsciTxsrcPin, kSimLpsciTxsrcTpm0, kSimLpsciTxsrcTpm1, kSimLpsciTxsrcReserved } |
SIM LPSCI transmit data source select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
enum | clock_wdog_src_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_trace_src_t { kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk } |
Debug trace clock source select. More... | |
enum | clock_nanoedge_clk2x_src { kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x } |
Debug trace clock source select. More... | |
enum | sim_osc32k_clock_sel_t { kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo } |
SIM OSC32KSEL clock source select. | |
enum | sim_nanoedge_clock_sel_t { kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk } |
SIM NANOEDGECLK2XSEL clock source select. | |
enum | sim_trace_clock_sel_t { kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk } |
SIM TRACECLKSEL clock source select. | |
enum | sim_clkout_clock_sel_t { kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk } |
SIM CLKOUT_SEL clock source select. | |
enum | sim_adcb_trg_sel_t { kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U } |
SIM ADCB trigger select. | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADC trigger select. | |
enum | sim_cadc_conv_id_t { kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U } |
Defines the type of enumerating ADC converter's ID. More... | |
enum | sim_adc_alt_trg_en { kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U } |
SIM ADC alternate trigger enable. | |
enum | sim_dac_hw_trg_sel { kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U } |
DAC0 Hardware Trigger Input Source. | |
enum | sim_ewm_in_src { kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U } |
the ewm_in source of EWM module. More... | |
enum | sim_cmp_win_in_src { kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U } |
CMP Sample/Window Input X Source. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_flexcan_src_t { kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk } |
FLEXCAN clock source select. More... | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
enum | clock_source_names_t { kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax } |
Clock source and sel names. | |
enum | clock_divider_names_t { kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax } |
Clock Divider names. | |
enum | sim_usbsstby_stop_t { kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during stop modes. | |
enum | sim_usbvstby_stop_t { kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes. | |
enum | sim_cmtuartpad_strengh_t { kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad } |
SIM CMT/UART pad drive strength. | |
enum | sim_ptd7pad_strengh_t { kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad } |
SIM PTD7 pad drive strength. | |
enum | sim_flexbus_security_level_t { kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3 } |
SIM FlexBus security level. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_ftm_trg_src_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. | |
enum | sim_ftm_clk_sel_t { kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2 } |
SIM FlexTimer external clock select. | |
enum | sim_ftm_ch_src_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. | |
enum | sim_ftm_ch_out_src_t { kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1 } |
SIM FlexTimer x channel y output source select. | |
enum | sim_ftm_flt_sel_t { kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | clock_wdog_src_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_trace_src_t { kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk } |
Debug trace clock source select. More... | |
enum | clock_nanoedge_clk2x_src { kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x } |
Debug trace clock source select. More... | |
enum | sim_osc32k_clock_sel_t { kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo } |
SIM OSC32KSEL clock source select. | |
enum | sim_nanoedge_clock_sel_t { kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk } |
SIM NANOEDGECLK2XSEL clock source select. | |
enum | sim_trace_clock_sel_t { kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk } |
SIM TRACECLKSEL clock source select. | |
enum | sim_clkout_clock_sel_t { kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk } |
SIM CLKOUT_SEL clock source select. | |
enum | sim_adcb_trg_sel_t { kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U } |
SIM ADCB trigger select. | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADC trigger select. | |
enum | sim_cadc_conv_id_t { kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U } |
Defines the type of enumerating ADC converter's ID. More... | |
enum | sim_adc_alt_trg_en { kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U } |
SIM ADC alternate trigger enable. | |
enum | sim_dac_hw_trg_sel { kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U } |
DAC0 Hardware Trigger Input Source. | |
enum | sim_ewm_in_src { kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U } |
the ewm_in source of EWM module. More... | |
enum | sim_cmp_win_in_src { kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U } |
CMP Sample/Window Input X Source. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_flexcan_src_t { kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk } |
FLEXCAN clock source select. More... | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
enum | clock_source_names_t { kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax } |
Clock source and sel names. | |
enum | clock_divider_names_t { kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax } |
Clock Divider names. | |
enum | sim_usbsstby_stop_t { kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during stop modes. | |
enum | sim_usbvstby_stop_t { kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes. | |
enum | sim_cmtuartpad_strengh_t { kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad } |
SIM CMT/UART pad drive strength. | |
enum | sim_ptd7pad_strengh_t { kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad } |
SIM PTD7 pad drive strength. | |
enum | sim_flexbus_security_level_t { kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3 } |
SIM FlexBus security level. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_ftm_trg_src_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. | |
enum | sim_ftm_clk_sel_t { kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2 } |
SIM FlexTimer external clock select. | |
enum | sim_ftm_ch_src_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. | |
enum | sim_ftm_ch_out_src_t { kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1 } |
SIM FlexTimer x channel y output source select. | |
enum | sim_ftm_flt_sel_t { kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | clock_wdog_src_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_trace_src_t { kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk } |
Debug trace clock source select. More... | |
enum | clock_nanoedge_clk2x_src { kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x } |
Debug trace clock source select. More... | |
enum | sim_osc32k_clock_sel_t { kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo } |
SIM OSC32KSEL clock source select. | |
enum | sim_nanoedge_clock_sel_t { kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk } |
SIM NANOEDGECLK2XSEL clock source select. | |
enum | sim_trace_clock_sel_t { kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk } |
SIM TRACECLKSEL clock source select. | |
enum | sim_clkout_clock_sel_t { kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk } |
SIM CLKOUT_SEL clock source select. | |
enum | sim_adcb_trg_sel_t { kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U } |
SIM ADCB trigger select. | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADC trigger select. | |
enum | sim_cadc_conv_id_t { kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U } |
Defines the type of enumerating ADC converter's ID. More... | |
enum | sim_adc_alt_trg_en { kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U } |
SIM ADC alternate trigger enable. | |
enum | sim_dac_hw_trg_sel { kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U } |
DAC0 Hardware Trigger Input Source. | |
enum | sim_ewm_in_src { kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U } |
the ewm_in source of EWM module. More... | |
enum | sim_cmp_win_in_src { kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U } |
CMP Sample/Window Input X Source. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_flexcan_src_t { kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk } |
FLEXCAN clock source select. More... | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
enum | clock_source_names_t { kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax } |
Clock source and sel names. | |
enum | clock_divider_names_t { kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax } |
Clock Divider names. | |
enum | sim_usbsstby_stop_t { kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during stop modes. | |
enum | sim_usbvstby_stop_t { kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes. | |
enum | sim_cmtuartpad_strengh_t { kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad } |
SIM CMT/UART pad drive strength. | |
enum | sim_ptd7pad_strengh_t { kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad } |
SIM PTD7 pad drive strength. | |
enum | sim_flexbus_security_level_t { kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3 } |
SIM FlexBus security level. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_ftm_trg_src_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. | |
enum | sim_ftm_clk_sel_t { kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2 } |
SIM FlexTimer external clock select. | |
enum | sim_ftm_ch_src_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. | |
enum | sim_ftm_ch_out_src_t { kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1 } |
SIM FlexTimer x channel y output source select. | |
enum | sim_ftm_flt_sel_t { kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | clock_wdog_src_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_trace_src_t { kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk } |
Debug trace clock source select. More... | |
enum | clock_nanoedge_clk2x_src { kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x } |
Debug trace clock source select. More... | |
enum | sim_osc32k_clock_sel_t { kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo } |
SIM OSC32KSEL clock source select. | |
enum | sim_nanoedge_clock_sel_t { kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk } |
SIM NANOEDGECLK2XSEL clock source select. | |
enum | sim_trace_clock_sel_t { kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk } |
SIM TRACECLKSEL clock source select. | |
enum | sim_clkout_clock_sel_t { kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk } |
SIM CLKOUT_SEL clock source select. | |
enum | sim_adcb_trg_sel_t { kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U } |
SIM ADCB trigger select. | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADC trigger select. | |
enum | sim_cadc_conv_id_t { kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U } |
Defines the type of enumerating ADC converter's ID. More... | |
enum | sim_adc_alt_trg_en { kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U } |
SIM ADC alternate trigger enable. | |
enum | sim_dac_hw_trg_sel { kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U } |
DAC0 Hardware Trigger Input Source. | |
enum | sim_ewm_in_src { kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U } |
the ewm_in source of EWM module. More... | |
enum | sim_cmp_win_in_src { kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U } |
CMP Sample/Window Input X Source. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_flexcan_src_t { kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk } |
FLEXCAN clock source select. More... | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
enum | clock_source_names_t { kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax } |
Clock source and sel names. | |
enum | clock_divider_names_t { kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax } |
Clock Divider names. | |
enum | sim_usbsstby_stop_t { kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during stop modes. | |
enum | sim_usbvstby_stop_t { kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes. | |
enum | sim_cmtuartpad_strengh_t { kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad } |
SIM CMT/UART pad drive strength. | |
enum | sim_ptd7pad_strengh_t { kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad } |
SIM PTD7 pad drive strength. | |
enum | sim_flexbus_security_level_t { kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3 } |
SIM FlexBus security level. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_ftm_trg_src_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. | |
enum | sim_ftm_clk_sel_t { kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2 } |
SIM FlexTimer external clock select. | |
enum | sim_ftm_ch_src_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. | |
enum | sim_ftm_ch_out_src_t { kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1 } |
SIM FlexTimer x channel y output source select. | |
enum | sim_ftm_flt_sel_t { kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
enum | clock_wdog_src_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk, kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_trace_src_t { kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk, kClockTraceSrcMcgoutClk, kClockTraceSrcCoreClk } |
Debug trace clock source select. More... | |
enum | clock_nanoedge_clk2x_src { kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x, kClockNanoedgeSrcMcgPllClk, kClockNanoedgeSrcMcgPllClk2x } |
Debug trace clock source select. More... | |
enum | sim_osc32k_clock_sel_t { kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo, kSimOsc32kSelOsc32k, kSimOsc32kSelReserved, kSimOsc32kSelReserved1, kSimOsc32kSelLpo } |
SIM OSC32KSEL clock source select. | |
enum | sim_nanoedge_clock_sel_t { kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk, kSimNanoEdgeMcgPllClk, kSimNanoEdgeMcgPll2xClk } |
SIM NANOEDGECLK2XSEL clock source select. | |
enum | sim_trace_clock_sel_t { kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk, kSimTraceMcgoutClk, kSimTraceCoreClk } |
SIM TRACECLKSEL clock source select. | |
enum | sim_clkout_clock_sel_t { kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk, kSimClkoutReserved, kSimClkoutReserved1, kSimClkoutFlashClk, kSimClkoutLpoClk, kSimClkoutMcgIrcClk, kSimClkoutOscErcClkUndiv, kSimClkoutOscErcClk } |
SIM CLKOUT_SEL clock source select. | |
enum | sim_adcb_trg_sel_t { kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U, kSimAdcbTrgSelHighSpeedComp0 = 1U, kSimAdcbTrgSelHighSpeedComp1 = 2U, kSimAdcbTrgSelHighSpeedComp2 = 3U, kSimAdcbTrgSelPit0 = 4U, kSimAdcbTrgSelPit1 = 5U, kSimAdcbTrgSelPit2 = 6U, kSimAdcbTrgSelPit3 = 7U, kSimAdcbTrgSelFtm0 = 8U, kSimAdcbTrgSelFtm1 = 9U, kSimAdcbTrgSelFtm3 = 11U, kSimAdcbTrgSelxbaraout41 = 12U, kSimAdcbTrgSelLptimer = 14U } |
SIM ADCB trigger select. | |
enum | sim_adc_trg_sel_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselExt = 0U, kSimAdcTrgSelComp0 = 1U, kSimAdcTrgSelReserved = 2U, kSimAdcTrgSelReserved1 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelReserved2 = 6U, kSimAdcTrgSelReserved3 = 7U, kSimAdcTrgSelTpm0 = 8U, kSimAdcTrgSelTpm1 = 9U, kSimAdcTrgSelTpm2 = 10U, kSimAdcTrgSelReserved4 = 11U, kSimAdcTrgSelRtcAlarm = 12U, kSimAdcTrgSelRtcSec = 13U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgSelReserved5 = 15U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U, kSimAdcTrgselPdb0Ext = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelHighSpeedComp2 = 3U, kSimAdcTrgSelPit0 = 4U, kSimAdcTrgSelPit1 = 5U, kSimAdcTrgSelPit2 = 6U, kSimAdcTrgSelPit3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm3 = 11U, kSimAdcTrgSelxbaraout = 12U, kSimAdcTrgSelLptimer = 14U } |
SIM ADC trigger select. | |
enum | sim_cadc_conv_id_t { kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U, kSimCAdcConvA = 0U, kSimCAdcConvB = 1U } |
Defines the type of enumerating ADC converter's ID. More... | |
enum | sim_adc_alt_trg_en { kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U, kSimAdcTrgenXbarout = 0U, kSimAdcTrgenPdb = 1U, kSimAdcTrgenalt0 = 2U, kSimAdcTrgenalt1 = 3U } |
SIM ADC alternate trigger enable. | |
enum | sim_dac_hw_trg_sel { kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U, kSimDacHwTrgSelXbarout15 = 0U, kSimDacHwTrgSelPdb01Int = 1U, kSimDacHwTrgSelPdb0Int = 2U, kSimDacHwTrgSelPdb1Int = 3U } |
DAC0 Hardware Trigger Input Source. | |
enum | sim_ewm_in_src { kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U, kSimDacHwTrgSelXbarout58 = 0U, kSimDacHwTrgSelEwnInPin = 1U } |
the ewm_in source of EWM module. More... | |
enum | sim_cmp_win_in_src { kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U, kSimCmpWinInSrcXbarout = 0U, kSimCmpWinInSrcPdb01Int = 1U, kSimCmpWinInSrcPdb0Int = 2U, kSimCmpWinInSrcPdb1Int = 3U } |
CMP Sample/Window Input X Source. | |
enum | clock_lptmr_src_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv, kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClkUndiv } |
LPTMR clock source select. More... | |
enum | clock_er32k_src_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcReserved = 1U, kClockEr32kSrcRtc = 2U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U, kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_flexcan_src_t { kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk, kClockFlexcanSrcOsc0erClk, kClockFlexcanSrcBusClk } |
FLEXCAN clock source select. More... | |
enum | sim_clock_gate_name_t { kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateI2c1 = FSL_SIM_SCGC_BIT(4U, 7U), kSimClockGateLpsci0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateUart2 = FSL_SIM_SCGC_BIT(4U, 12U), kSimClockGateUsbfs0 = FSL_SIM_SCGC_BIT(4U, 18U), kSimClockGateCmp0 = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(4U, 22U), kSimClockGateSpi1 = FSL_SIM_SCGC_BIT(4U, 23U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGateTsi0 = FSL_SIM_SCGC_BIT(5U, 5U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateTpm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateTpm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateTpm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateRtc0 = FSL_SIM_SCGC_BIT(6U, 29U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U), kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGatePwm0 = FSL_SIM_SCGC_BIT(4U, 24U), kSimClockGatePwm1 = FSL_SIM_SCGC_BIT(4U, 25U), kSimClockGatePwm2 = FSL_SIM_SCGC_BIT(4U, 26U), kSimClockGatePwm3 = FSL_SIM_SCGC_BIT(4U, 27U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateEnc0 = FSL_SIM_SCGC_BIT(5U, 21U), kSimClockGateXbarA = FSL_SIM_SCGC_BIT(5U, 25U), kSimClockGateXbarB = FSL_SIM_SCGC_BIT(5U, 26U), kSimClockGateAoi0 = FSL_SIM_SCGC_BIT(5U, 27U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(5U, 28U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateFlexcan0 = FSL_SIM_SCGC_BIT(6U, 4U), kSimClockGateFlexcan1 = FSL_SIM_SCGC_BIT(6U, 5U), kSimClockGateFtm3 = FSL_SIM_SCGC_BIT(6U, 6U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGatePdb1 = FSL_SIM_SCGC_BIT(6U, 17U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGatePit0 = FSL_SIM_SCGC_BIT(6U, 23U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
enum | clock_source_names_t { kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax, kClockNfcSrc, kClockEsdhcSrc, kClockSdhcSrc, kClockLcdcSrc, kClockTimeSrc, kClockRmiiSrc, kClockUsbfSrc, kClockUsbSrc, kClockUsbhSrc, kClockUart0Src, kClockLpuartSrc, kClockTpmSrc, kClockOsc32kSel, kClockUsbfSel, kClockPllfllSel, kClockNfcSel, kClockLcdcSel, kClockTraceSel, kClockClkoutSel, kClockRtcClkoutSel, kClockNanoEdgeClk2xSel, kClockSourceMax } |
Clock source and sel names. | |
enum | clock_divider_names_t { kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax, kClockDividerOutdiv1, kClockDividerOutdiv2, kClockDividerOutdiv3, kClockDividerOutdiv4, kClockDividerUsbFrac, kClockDividerUsbDiv, kClockDividerUsbfsFrac, kClockDividerUsbfsDiv, kClockDividerUsbhsFrac, kClockDividerUsbhsDiv, kClockDividerLcdcFrac, kClockDividerLcdcDiv, kClockDividerNfcFrac, kClockDividerNfcDiv, kClockDividerSpecial1, kClockDividerMax } |
Clock Divider names. | |
enum | sim_usbsstby_stop_t { kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator, kSimUsbsstbyNoRegulator, kSimUsbsstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during stop modes. | |
enum | sim_usbvstby_stop_t { kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator, kSimUsbvstbyNoRegulator, kSimUsbvstbyWithRegulator } |
SIM USB voltage regulator in standby mode setting during VLPR and VLPW modes. | |
enum | sim_cmtuartpad_strengh_t { kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad, kSimCmtuartSinglePad, kSimCmtuartDualPad } |
SIM CMT/UART pad drive strength. | |
enum | sim_ptd7pad_strengh_t { kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad, kSimPtd7padSinglePad, kSimPtd7padDualPad } |
SIM PTD7 pad drive strength. | |
enum | sim_flexbus_security_level_t { kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3, kSimFbslLevel0, kSimFbslLevel1, kSimFbslLevel2, kSimFbslLevel3 } |
SIM FlexBus security level. | |
enum | sim_uart_rxsrc_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved, kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1, kSimUartRxsrcReserved } |
SIM UART receive data source select. | |
enum | sim_uart_txsrc_t { kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcTpm0, kSimUartTxsrcTpm1, kSimUartTxsrcReserved, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcPin, kSimUartTxsrcFtm1 } |
SIM UART transmit data source select. | |
enum | sim_ftm_trg_src_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1, kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. | |
enum | sim_ftm_clk_sel_t { kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2, kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2 } |
SIM FlexTimer external clock select. | |
enum | sim_ftm_ch_src_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3, kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. | |
enum | sim_ftm_ch_out_src_t { kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1, kSimFtmChOutSrc0, kSimFtmChOutSrc1 } |
SIM FlexTimer x channel y output source select. | |
enum | sim_ftm_flt_sel_t { kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1, kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. | |
enum | sim_tpm_clk_sel_t { kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1, kSimTpmClkSel0, kSimTpmClkSel1 } |
SIM Timer/PWM external clock select. | |
enum | sim_tpm_ch_src_t { kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc2, kSimTpmChSrc3, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1, kSimTpmChSrc0, kSimTpmChSrc1 } |
SIM Timer/PWM x channel y input capture source select. | |
Functions | |
static void | SIM_HAL_EnableClock (SIM_Type *base, sim_clock_gate_name_t name) |
Enable the clock for specific module. More... | |
static void | SIM_HAL_DisableClock (SIM_Type *base, sim_clock_gate_name_t name) |
Disable the clock for specific module. More... | |
static bool | SIM_HAL_GetGateCmd (SIM_Type *base, sim_clock_gate_name_t name) |
Get the the clock gate state for specific module. More... | |
static void | CLOCK_HAL_SetExternalRefClock32kSrc (SIM_Type *base, clock_er32k_src_t setting) |
Set the clock selection of ERCLK32K. More... | |
static clock_er32k_src_t | CLOCK_HAL_GetExternalRefClock32kSrc (SIM_Type *base) |
Get the clock selection of ERCLK32K. More... | |
static void | CLOCK_HAL_SetOsc32kOutSel (SIM_Type *base, clock_osc32kout_sel_t setting) |
Set OSC32KOUT selection. More... | |
static clock_osc32kout_sel_t | CLOCK_HAL_GetOsc32kOutSel (SIM_Type *base) |
Get OSC32KOUT selection. More... | |
static uint32_t | SIM_HAL_GetRamSize (SIM_Type *base) |
Gets RAM size. More... | |
static void | CLOCK_HAL_SetPllfllSel (SIM_Type *base, clock_pllfll_sel_t setting) |
Set PLL/FLL clock selection. More... | |
static clock_pllfll_sel_t | CLOCK_HAL_GetPllfllSel (SIM_Type *base) |
Get PLL/FLL clock selection. More... | |
static void | CLOCK_HAL_SetTraceClkSrc (SIM_Type *base, clock_trace_src_t setting) |
Set debug trace clock selection. More... | |
static clock_trace_src_t | CLOCK_HAL_GetTraceClkSrc (SIM_Type *base) |
Get debug trace clock selection. More... | |
static void | CLOCK_HAL_SetClkOutSel (SIM_Type *base, clock_clkout_src_t setting) |
Set CLKOUTSEL selection. More... | |
static clock_clkout_src_t | CLOCK_HAL_GetClkOutSel (SIM_Type *base) |
Get CLKOUTSEL selection. More... | |
static void | CLOCK_HAL_SetOutDiv1 (SIM_Type *base, uint8_t setting) |
Set OUTDIV1. More... | |
static uint8_t | CLOCK_HAL_GetOutDiv1 (SIM_Type *base) |
Get OUTDIV1. More... | |
static void | CLOCK_HAL_SetOutDiv2 (SIM_Type *base, uint8_t setting) |
Set OUTDIV2. More... | |
static uint8_t | CLOCK_HAL_GetOutDiv2 (SIM_Type *base) |
Get OUTDIV2. More... | |
static void | CLOCK_HAL_SetOutDiv4 (SIM_Type *base, uint8_t setting) |
Set OUTDIV4. More... | |
static uint8_t | CLOCK_HAL_GetOutDiv4 (SIM_Type *base) |
Get OUTDIV4. More... | |
void | SIM_HAL_SetFtmTriggerSrcMode (SIM_Type *base, uint32_t instance, uint8_t trigger, sim_ftm_trg_src_t select) |
Sets the FlexTimer x hardware trigger y source select setting. More... | |
sim_ftm_trg_src_t | SIM_HAL_GetFtmTriggerSrcMode (SIM_Type *base, uint32_t instance, uint8_t trigger) |
Gets the FlexTimer x hardware trigger y source select setting. More... | |
void | SIM_HAL_SetFtmExternalClkPinMode (SIM_Type *base, uint32_t instance, sim_ftm_clk_sel_t select) |
Sets the FlexTimer x external clock pin select setting. More... | |
sim_ftm_clk_sel_t | SIM_HAL_GetFtmExternalClkPinMode (SIM_Type *base, uint32_t instance) |
Gets the FlexTimer x external clock pin select setting. More... | |
void | SIM_HAL_SetFtmChSrcMode (SIM_Type *base, uint32_t instance, uint8_t channel, sim_ftm_ch_src_t select) |
Sets the FlexTimer x channel y input capture source select setting. More... | |
sim_ftm_ch_src_t | SIM_HAL_GetFtmChSrcMode (SIM_Type *base, uint32_t instance, uint8_t channel) |
Gets the FlexTimer x channel y input capture source select setting. More... | |
void | SIM_HAL_SetFtmFaultSelMode (SIM_Type *base, uint32_t instance, uint8_t fault, sim_ftm_flt_sel_t select) |
Sets the FlexTimer x fault y select setting. More... | |
sim_ftm_flt_sel_t | SIM_HAL_GetFtmFaultSelMode (SIM_Type *base, uint32_t instance, uint8_t fault) |
Gets the FlexTimer x fault y select setting. More... | |
void | SIM_HAL_SetFtmChOutSrcMode (SIM_Type *base, uint32_t instance, uint8_t channel, sim_ftm_ch_out_src_t select) |
Sets the FlexTimer x channel y output source select setting. More... | |
sim_ftm_ch_out_src_t | SIM_HAL_GetFtmChOutSrcMode (SIM_Type *base, uint32_t instance, uint8_t channel) |
Gets the FlexTimer x channel y output source select setting. More... | |
void | SIM_HAL_SetFtmSyncCmd (SIM_Type *base, uint32_t instance, bool sync) |
Set FlexTimer x hardware trigger 0 software synchronization. More... | |
static bool | SIM_HAL_GetFtmSyncCmd (SIM_Type *base, uint32_t instance) |
Get FlexTimer x hardware trigger 0 software synchronization setting. More... | |
static uint32_t | SIM_HAL_GetFamilyId (SIM_Type *base) |
Gets the Kinetis Family ID in the System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetSubFamilyId (SIM_Type *base) |
Gets the Kinetis Sub-Family ID in the System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetSeriesId (SIM_Type *base) |
Gets the Kinetis SeriesID in the System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetRevId (SIM_Type *base) |
Gets the Kinetis Revision ID in the System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetDieId (SIM_Type *base) |
Gets the Kinetis Die ID in the System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetFamId (SIM_Type *base) |
Gets the Kinetis family identification in the System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetPinCntId (SIM_Type *base) |
Gets the Kinetis Pincount ID in System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetProgramFlashSize (SIM_Type *base) |
Gets the program flash size in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static void | SIM_HAL_SetFlashDoze (SIM_Type *base, uint32_t setting) |
Sets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static uint32_t | SIM_HAL_GetFlashDoze (SIM_Type *base) |
Gets the Flash Doze in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static void | SIM_HAL_SetFlashDisableCmd (SIM_Type *base, bool disable) |
Sets the Flash disable setting. More... | |
static bool | SIM_HAL_GetFlashDisableCmd (SIM_Type *base) |
Gets the Flash disable setting. More... | |
static uint32_t | SIM_HAL_GetFlashMaxAddrBlock0 (SIM_Type *base) |
Gets the Flash maximum address block 0 in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static void | CLOCK_HAL_SetSdhcSrc (SIM_Type *base, uint32_t instance, clock_sdhc_src_t setting) |
Set the SDHC clock source selection. More... | |
static clock_sdhc_src_t | CLOCK_HAL_GetSdhcSrc (SIM_Type *base, uint32_t instance) |
Get the SDHC clock source selection. More... | |
static void | CLOCK_HAL_SetTimeSrc (SIM_Type *base, uint32_t instance, clock_time_src_t setting) |
Set the ethernet timestamp clock source selection. More... | |
static clock_time_src_t | CLOCK_HAL_GetTimeSrc (SIM_Type *base, uint32_t instance) |
Get the ethernet timestamp clock source selection. More... | |
static void | CLOCK_HAL_SetRmiiSrc (SIM_Type *base, uint32_t instance, clock_rmii_src_t setting) |
Set the Ethernet RMII interface clock source selection. More... | |
static clock_rmii_src_t | CLOCK_HAL_GetRmiiSrc (SIM_Type *base, uint32_t instance) |
Get the Ethernet RMII interface clock source selection. More... | |
static void | CLOCK_HAL_SetRtcClkOutSel (SIM_Type *base, clock_rtcout_src_t setting) |
Set RTCCLKOUTSEL selection. More... | |
static clock_rtcout_src_t | CLOCK_HAL_GetRtcClkOutSel (SIM_Type *base) |
Get RTCCLKOUTSEL selection. More... | |
static void | CLOCK_HAL_SetOutDiv3 (SIM_Type *base, uint8_t setting) |
Set OUTDIV3. More... | |
static uint8_t | CLOCK_HAL_GetOutDiv3 (SIM_Type *base) |
Get OUTDIV3. More... | |
static void | SIM_HAL_SetPtd7PadDriveStrengthMode (SIM_Type *base, sim_ptd7pad_strengh_t setting) |
Sets the PTD7 pad drive strength setting. More... | |
static sim_ptd7pad_strengh_t | SIM_HAL_GetPtd7PadDriveStrengthMode (SIM_Type *base) |
Gets the PTD7 pad drive strength setting. More... | |
static void | SIM_HAL_SetFlexbusSecurityLevelMode (SIM_Type *base, sim_flexbus_security_level_t setting) |
Sets the FlexBus security level setting. More... | |
static sim_flexbus_security_level_t | SIM_HAL_GetFlexbusSecurityLevelMode (SIM_Type *base) |
Gets the FlexBus security level setting. More... | |
static uint32_t | SIM_HAL_GetFlexnvmSize (SIM_Type *base) |
Gets the FlexNVM size in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static uint32_t | SIM_HAL_GetEepromSize (SIM_Type *base) |
Gets the EEProm size in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static uint32_t | SIM_HAL_GetFlexnvmPartition (SIM_Type *base) |
Gets the FlexNVM partition in the Flash Configuration Register 1 (SIM_FCFG). More... | |
static uint32_t | SIM_HAL_GetFlashMaxAddrBlock1 (SIM_Type *base) |
Gets the Flash maximum address block 1 in Flash Configuration Register 2. More... | |
static uint32_t | SIM_HAL_GetProgramFlashCmd (SIM_Type *base) |
Gets the program flash in the Flash Configuration Register 2. More... | |
static bool | SIM_HAL_GetSwapProgramFlash (SIM_Type *base) |
Gets the Swap program flash flag in the Flash Configuration Register 2. More... | |
void | CLOCK_HAL_SetUsbfsDiv (SIM_Type *base, uint8_t usbdiv, uint8_t usbfrac) |
Set USB FS divider setting. More... | |
void | CLOCK_HAL_GetUsbfsDiv (SIM_Type *base, uint8_t *usbdiv, uint8_t *usbfrac) |
Get USB FS divider setting. More... | |
static void | CLOCK_HAL_SetUsbfsSrc (SIM_Type *base, uint32_t instance, clock_usbfs_src_t setting) |
Set the selection of the clock source for the USB FS 48 MHz clock. More... | |
static clock_usbfs_src_t | CLOCK_HAL_GetUsbfsSrc (SIM_Type *base, uint32_t instance) |
Get the selection of the clock source for the USB FS 48 MHz clock. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorCmd (SIM_Type *base, bool enable) |
Sets the USB voltage regulator enabled setting. More... | |
static bool | SIM_HAL_GetUsbVoltRegulatorCmd (SIM_Type *base) |
Gets the USB voltage regulator enabled setting. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopMode (SIM_Type *base, sim_usbsstby_mode_t setting) |
Sets the USB voltage regulator in a standby mode setting during Stop, VLPS, LLS, and VLLS. More... | |
static sim_usbsstby_mode_t | SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopMode (SIM_Type *base) |
Gets the USB voltage regulator in a standby mode setting. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwMode (SIM_Type *base, sim_usbvstby_mode_t setting) |
Sets the USB voltage regulator in a standby mode during the VLPR or the VLPW. More... | |
static sim_usbvstby_mode_t | SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwMode (SIM_Type *base) |
Gets the USB voltage regulator in a standby mode during the VLPR or the VLPW. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorInStdbyDuringStopCmd (SIM_Type *base, bool enable) |
Sets the USB voltage regulator stop standby write enable setting. More... | |
static bool | SIM_HAL_GetUsbVoltRegulatorInStdbyDuringStopCmd (SIM_Type *base) |
Gets the USB voltage regulator stop standby write enable setting. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorInStdbyDuringVlprwCmd (SIM_Type *base, bool enable) |
Sets the USB voltage regulator VLP standby write enable setting. More... | |
static bool | SIM_HAL_GetUsbVoltRegulatorInStdbyDuringVlprwCmd (SIM_Type *base) |
Gets the USB voltage regulator VLP standby write enable setting. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorWriteCmd (SIM_Type *base, bool enable) |
Sets the USB voltage regulator enable write enable setting. More... | |
static bool | SIM_HAL_GetUsbVoltRegulatorWriteCmd (SIM_Type *base) |
Gets the USB voltage regulator enable write enable setting. More... | |
static void | CLOCK_HAL_SetLpuartSrc (SIM_Type *base, uint32_t instance, clock_lpuart_src_t setting) |
Set LPUART clock source. More... | |
static clock_lpuart_src_t | CLOCK_HAL_GetLpuartSrc (SIM_Type *base, uint32_t instance) |
Get LPUART clock source. More... | |
static void | SIM_HAL_SetLpuartRxSrcMode (SIM_Type *base, uint32_t instance, sim_lpuart_rxsrc_t select) |
Sets the LPUARTx receive data source select setting. More... | |
static sim_lpuart_rxsrc_t | SIM_HAL_GetLpuartRxSrcMode (SIM_Type *base, uint32_t instance) |
Gets the LPUARTx receive data source select setting. More... | |
static void | CLOCK_HAL_SetUsbhsSlowClockSrc (SIM_Type *base, uint32_t instance, clock_usbhs_slowclk_src_t setting) |
Set the selection of the clock source for the USB HS/USB PHY slow clock. More... | |
static clock_usbhs_slowclk_src_t | CLOCK_HAL_GetUsbhsSlowClockSrc (SIM_Type *base, uint32_t instance) |
Get the selection of the clock source for the USB HS/USB PHY slow clock. More... | |
void | CLOCK_HAL_SetPllFllDiv (SIM_Type *base, uint8_t pllflldiv, uint8_t pllfllfrac) |
Set PLL/FLL divider setting. More... | |
void | CLOCK_HAL_GetPllFllDiv (SIM_Type *base, uint8_t *pllflldiv, uint8_t *pllfllfrac) |
Gets PLL/FLL divider setting. More... | |
void | CLOCK_HAL_SetTraceDiv (SIM_Type *base, uint8_t tracediv, uint8_t tracefrac) |
Set TRACECLK divider setting. More... | |
void | CLOCK_HAL_GetTraceDiv (SIM_Type *base, uint8_t *tracediv, uint8_t *tracefrac) |
Gets TRACECLK setting. More... | |
static void | CLOCK_HAL_SetTpmSrc (SIM_Type *base, uint32_t instance, clock_tpm_src_t setting) |
Set the TPM clock source selection. More... | |
static clock_tpm_src_t | CLOCK_HAL_GetTpmSrc (SIM_Type *base, uint32_t instance) |
Get the TPM clock source selection. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorInrushLimitCmd (SIM_Type *base, bool enable) |
Sets the USB voltage regulator inrush current limit setting. More... | |
static bool | SIM_HAL_GetUsbVoltRegulatorInrushLimitCmd (SIM_Type *base) |
Gets the USB voltage regulator inrush current limit setting. More... | |
static void | SIM_HAL_SetUsbVoltRegulatorOutputTargetCmd (SIM_Type *base, sim_usbvout_mode_t target) |
Sets the USB voltage regulator output target. More... | |
static sim_usbvout_mode_t | SIM_HAL_GetUsbVoltRegulatorOutputTargetCmd (SIM_Type *base) |
Gets the USB voltage regulator output target. More... | |
static void | SIM_HAL_SetUsbPhyPllRegulatorCmd (SIM_Type *base, bool enable) |
Sets the USB PHY PLL regulator enabled setting. More... | |
static bool | SIM_HAL_GetUsbPhyPllRegulatorCmd (SIM_Type *base) |
Gets the USB PHY PLL regulator enabled setting. More... | |
static void | SIM_HAL_SetLpuartTxSrcMode (SIM_Type *base, uint32_t instance, sim_lpuart_txsrc_t select) |
Sets the LPUARTx transmit data source select setting. More... | |
static sim_lpuart_rxsrc_t | SIM_HAL_GetLpuartTxSrcMode (SIM_Type *base, uint32_t instance) |
Gets the LPUARTx transmit data source select setting. More... | |
static void | CLOCK_HAL_SetLpsciSrc (SIM_Type *base, uint32_t instance, clock_lpsci_src_t setting) |
Set the LPSCI clock source selection. More... | |
static clock_lpsci_src_t | CLOCK_HAL_GetLpsciSrc (SIM_Type *base, uint32_t instance) |
Get the LPSCI clock source selection. More... | |
static void | SIM_HAL_SetLpsciRxSrcMode (SIM_Type *base, uint32_t instance, sim_lpsci_rxsrc_t select) |
Sets the LPSCIx receive data source select setting. More... | |
static sim_lpsci_rxsrc_t | SIM_HAL_GetLpsciRxSrcMode (SIM_Type *base, uint32_t instance) |
Gets the LPSCIx receive data source select setting. More... | |
static void | SIM_HAL_SetLpsciTxSrcMode (SIM_Type *base, uint32_t instance, sim_lpsci_txsrc_t select) |
Sets the LPSCIx transmit data source select setting. More... | |
static sim_lpsci_txsrc_t | SIM_HAL_GetLpsciTxSrcMode (SIM_Type *base, uint32_t instance) |
Gets the LPSCIx transmit data source select setting. More... | |
static uint32_t | SIM_HAL_GetSramSize (SIM_Type *base) |
Gets the Kinetis SramSize in the System Device ID register (SIM_SDID). More... | |
static void | CLOCK_HAL_SetCopSrc (SIM_Type *base, clock_cop_src_t setting) |
Set the clock selection of COP. More... | |
static clock_cop_src_t | CLOCK_HAL_GetCopSrc (SIM_Type *base) |
Get the clock selection of COP. More... | |
static void | SIM_HAL_SetLpuartOpenDrainCmd (SIM_Type *base, uint32_t instance, bool enable) |
Sets the LPUARTx Open Drain Enable setting. More... | |
static bool | SIM_HAL_GetLpuartOpenDrainCmd (SIM_Type *base, uint32_t instance) |
Gets the LPUARTx Open Drain Enable setting. More... | |
static void | SIM_HAL_SetTpmChSrcMode (SIM_Type *base, uint32_t instance, uint8_t channel, sim_tpm_ch_src_t select) |
Sets the Timer/PWM x channel y input capture source select setting. More... | |
static sim_tpm_ch_src_t | SIM_HAL_GetTpmChSrcMode (SIM_Type *base, uint32_t instance, uint8_t channel) |
Gets the Timer/PWM x channel y input capture source select setting. More... | |
void | SIM_HAL_SetTpmExternalClkPinSelMode (SIM_Type *base, uint32_t instance, sim_tpm_clk_sel_t select) |
Sets the Timer/PWM x external clock pin select setting. More... | |
sim_tpm_clk_sel_t | SIM_HAL_GetTpmExternalClkPinSelMode (SIM_Type *base, uint32_t instance) |
Gets the Timer/PWM x external clock pin select setting. More... | |
static void | CLOCK_HAL_SetFlexioSrc (SIM_Type *base, uint32_t instance, clock_flexio_src_t setting) |
Select the clock source for FLEXIO. More... | |
static clock_flexio_src_t | CLOCK_HAL_GetFlexioSrc (SIM_Type *base, uint32_t instance) |
Get the clock source of FLEXIO. More... | |
static void | SIM_HAL_SetUartOpenDrainCmd (SIM_Type *base, uint32_t instance, bool enable) |
Sets the UARTx Open Drain Enable setting. More... | |
static bool | SIM_HAL_GetUartOpenDrainCmd (SIM_Type *base, uint32_t instance) |
Gets the UARTx Open Drain Enable setting. More... | |
static uint32_t | SIM_HAL_GetSramSizeId (SIM_Type *base) |
Gets the Kinetis SRAMSIZE ID in the System Device ID register (SIM_SDID). More... | |
static void | CLOCK_HAL_SetOutDiv5ENCmd (SIM_Type *base, bool setting) |
Set OUTDIV5EN. More... | |
static bool | CLOCK_HAL_GetOutDiv5ENCmd (SIM_Type *base) |
Get OUTDIV5EN. More... | |
static void | CLOCK_HAL_SetOutDiv5 (SIM_Type *base, uint8_t setting) |
Set OUTDIV5. More... | |
static uint8_t | CLOCK_HAL_GetOutDiv5 (SIM_Type *base) |
Get OUTDIV5. More... | |
void | CLOCK_HAL_SetAdcAltClkSrc (SIM_Type *base, uint32_t instance, clock_adc_alt_src_t adcAltSrcSel) |
Sets the ADC ALT clock source selection setting. More... | |
clock_adc_alt_src_t | CLOCK_HAL_GetAdcAltClkSrc (SIM_Type *base, uint32_t instance) |
Gets the ADC ALT clock source selection setting. More... | |
void | SIM_HAL_SetUartOpenDrainMode (SIM_Type *base, uint32_t instance, bool enable) |
Sets the UARTx open drain enable setting. More... | |
bool | SIM_HAL_GetUartOpenDrainMode (SIM_Type *base, uint32_t instance) |
Gets the UARTx open drain enable setting. More... | |
static void | CLOCK_HAL_SetFtmFixFreqClkSrc (SIM_Type *base, clock_ftm_fixedfreq_src_t ftmFixedFreqSel) |
Sets the FTM Fixed clock source selection setting. More... | |
static clock_ftm_fixedfreq_src_t | CLOCK_HAL_GetFtmFixFreqClkSrc (SIM_Type *base) |
Gets the FTM Fixed clock source selection setting. More... | |
static void | SIM_HAL_SetFtmCarrierFreqMode (SIM_Type *base, sim_ftm_flt_carrier_sel_t select) |
Sets the Carrier frequency selection for FTM0/2 output channel. More... | |
static sim_ftm_flt_carrier_sel_t | SIM_HAL_GetFtmCarrierFreqMode (SIM_Type *base) |
Gets the Carrier frequency selection for FTM0/2 output channel. More... | |
static uint32_t | SIM_HAL_GetSubFamId (SIM_Type *base) |
Gets the Kinetis SbuFam ID in System Device ID register (SIM_SDID). More... | |
static uint32_t | SIM_HAL_GetFlashMaxAddrBlock (SIM_Type *base) |
Gets the Flash maximum address block in the Flash Configuration Register 1 (SIM_FCFG). More... | |
sim_hal_status_t | CLOCK_HAL_SetSource (SIM_Type *base, clock_source_names_t clockSource, uint8_t setting) |
Sets the clock source setting. More... | |
sim_hal_status_t | CLOCK_HAL_GetSource (SIM_Type *base, clock_source_names_t clockSource, uint8_t *setting) |
Gets the clock source setting. More... | |
sim_hal_status_t | CLOCK_HAL_SetDivider (SIM_Type *base, clock_divider_names_t clockDivider, uint32_t setting) |
Sets the clock divider setting. More... | |
IP related clock feature APIs | |
void | CLOCK_HAL_SetOutDiv (SIM_Type *base, uint8_t outdiv1, uint8_t outdiv2, uint8_t outdiv3, uint8_t outdiv4) |
Sets the clock out dividers setting. More... | |
void | CLOCK_HAL_GetOutDiv (SIM_Type *base, uint8_t *outdiv1, uint8_t *outdiv2, uint8_t *outdiv3, uint8_t *outdiv4) |
Gets the clock out dividers setting. More... | |
void | SIM_HAL_SetAdcAlternativeTriggerCmd (SIM_Type *base, uint32_t instance, bool enable) |
Sets the ADCx alternate trigger enable setting. More... | |
bool | SIM_HAL_GetAdcAlternativeTriggerCmd (SIM_Type *base, uint32_t instance) |
Gets the ADCx alternate trigger enable setting. More... | |
void | SIM_HAL_SetAdcPreTriggerMode (SIM_Type *base, uint32_t instance, sim_adc_pretrg_sel_t select) |
Sets the ADCx pre-trigger select setting. More... | |
sim_adc_pretrg_sel_t | SIM_HAL_GetAdcPreTriggerMode (SIM_Type *base, uint32_t instance) |
Gets the ADCx pre-trigger select setting. More... | |
void | SIM_HAL_SetAdcTriggerMode (SIM_Type *base, uint32_t instance, sim_adc_trg_sel_t select) |
Sets the ADCx trigger select setting. More... | |
sim_adc_trg_sel_t | SIM_HAL_GetAdcTriggerMode (SIM_Type *base, uint32_t instance) |
Gets the ADCx trigger select setting. More... | |
void | SIM_HAL_SetAdcTriggerModeOneStep (SIM_Type *base, uint32_t instance, bool altTrigEn, sim_adc_pretrg_sel_t preTrigSel, sim_adc_trg_sel_t trigSel) |
Sets the ADCx trigger select setting in one function. More... | |
void | SIM_HAL_SetUartRxSrcMode (SIM_Type *base, uint32_t instance, sim_uart_rxsrc_t select) |
Sets the UARTx receive data source select setting. More... | |
sim_uart_rxsrc_t | SIM_HAL_GetUartRxSrcMode (SIM_Type *base, uint32_t instance) |
Gets the UARTx receive data source select setting. More... | |
void | SIM_HAL_SetUartTxSrcMode (SIM_Type *base, uint32_t instance, sim_uart_txsrc_t select) |
Sets the UARTx transmit data source select setting. More... | |
sim_uart_txsrc_t | SIM_HAL_GetUartTxSrcMode (SIM_Type *base, uint32_t instance) |
Gets the UARTx transmit data source select setting. More... | |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |
enum sim_hal_status_t |
enum clock_lptmr_src_t |
enum clock_pllfll_sel_t |
SIM PLLFLLSEL clock source select
enum clock_er32k_src_t |
enum sim_adc_pretrg_sel_t |
SIM ADCx pre-trigger select
enum clock_lptmr_src_t |
enum clock_pllfll_sel_t |
SIM PLLFLLSEL clock source select
enum clock_er32k_src_t |
enum sim_adc_pretrg_sel_t |
SIM ADCx pre-trigger select
enum clock_lptmr_src_t |
enum clock_pllfll_sel_t |
SIM PLLFLLSEL clock source select
enum clock_er32k_src_t |
enum sim_adc_pretrg_sel_t |
SIM ADCx pre-trigger select
enum clock_lptmr_src_t |
enum clock_pllfll_sel_t |
SIM PLLFLLSEL clock source select
enum clock_er32k_src_t |
enum sim_adc_pretrg_sel_t |
SIM ADCx pre-trigger select
enum clock_wdog_src_t |
enum clock_trace_src_t |
enum sim_cadc_conv_id_t |
enum sim_ewm_in_src |
enum clock_lptmr_src_t |
enum clock_er32k_src_t |
enum clock_flexcan_src_t |
enum sim_clock_gate_name_t |
enum clock_wdog_src_t |
enum clock_trace_src_t |
enum sim_cadc_conv_id_t |
enum sim_ewm_in_src |
enum clock_lptmr_src_t |
enum clock_er32k_src_t |
enum clock_flexcan_src_t |
enum sim_clock_gate_name_t |
enum clock_wdog_src_t |
enum clock_trace_src_t |
enum sim_cadc_conv_id_t |
enum sim_ewm_in_src |
enum clock_lptmr_src_t |
enum clock_er32k_src_t |
enum clock_flexcan_src_t |
enum sim_clock_gate_name_t |
enum clock_wdog_src_t |
enum clock_trace_src_t |
enum sim_cadc_conv_id_t |
enum sim_ewm_in_src |
enum clock_lptmr_src_t |
enum clock_er32k_src_t |
enum clock_flexcan_src_t |
enum sim_clock_gate_name_t |
enum clock_wdog_src_t |
enum clock_trace_src_t |
enum sim_cadc_conv_id_t |
enum sim_ewm_in_src |
enum clock_lptmr_src_t |
enum clock_er32k_src_t |
enum clock_flexcan_src_t |
enum sim_clock_gate_name_t |
|
inlinestatic |
This function enables the clock for specific module.
base | Base address for current SIM instance. |
name | Name of the module to enable. |
|
inlinestatic |
This function disables the clock for specific module.
base | Base address for current SIM instance. |
name | Name of the module to disable. |
|
inlinestatic |
This function will get the clock gate state for specific module.
base | Base address for current SIM instance. |
name | Name of the module to get. |
|
inlinestatic |
This function sets the clock selection of ERCLK32K.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the clock selection of ERCLK32K.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets ERCLK32K output pin.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets ERCLK32K output pin setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the RAM size. The field specifies the amount of system RAM available on the device.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets the selection of the high frequency clock for various peripheral clocking options
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the selection of the high frequency clock for various peripheral clocking options
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets debug trace clock selection.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets debug trace clock selection.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets the selection of the clock to output on the CLKOUT pin.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the selection of the clock to output on the CLKOUT pin.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets divide value OUTDIV1.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets divide value OUTDIV1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets divide value OUTDIV2.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets divide value OUTDIV2.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets divide value OUTDIV4.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets divide value OUTDIV4.
base | Base address for current SIM instance. |
void CLOCK_HAL_SetOutDiv | ( | SIM_Type * | base, |
uint8_t | outdiv1, | ||
uint8_t | outdiv2, | ||
uint8_t | outdiv3, | ||
uint8_t | outdiv4 | ||
) |
This function sets the setting for all clock out dividers at the same time.
base | Base address for current SIM instance. |
outdiv1 | Outdivider1 setting |
outdiv2 | Outdivider2 setting |
outdiv3 | Outdivider3 setting |
outdiv4 | Outdivider4 setting |
This function sets the setting for all clock out dividers at the same time. See the reference manual for a supported clock divider and value range and the clock_divider_names_t for clock out dividers.
base | Base address for current SIM instance. |
outdiv1 | Outdivider1 setting |
outdiv2 | Outdivider2 setting |
outdiv3 | Outdivider3 setting |
outdiv4 | Outdivider4 setting |
void CLOCK_HAL_GetOutDiv | ( | SIM_Type * | base, |
uint8_t * | outdiv1, | ||
uint8_t * | outdiv2, | ||
uint8_t * | outdiv3, | ||
uint8_t * | outdiv4 | ||
) |
This function gets the setting for all clock out dividers at the same time.
base | Base address for current SIM instance. |
outdiv1 | Outdivider1 setting |
outdiv2 | Outdivider2 setting |
outdiv3 | Outdivider3 setting |
outdiv4 | Outdivider4 setting |
|
inline |
Sets the USB voltage regulator enabled setting.
This function enables/disables the alternative conversion triggers for ADCx.
base | Base address for current SIM instance. |
instance | device instance. |
enable | Enable alternative conversion triggers for ADCx
|
This function controls whether the USB voltage regulator is enabled. This bit can only be written when the SOPT1CFG[URWE] bit is set.
base | Base address for current SIM instance. |
enable | USB voltage regulator enable setting
|
Sets the ADCx alternate trigger enable setting.
This function enables/disables the alternative conversion triggers for ADCx.
base | Base address for current SIM instance. |
instance | device instance. |
enable | Enable alternative conversion triggers for ADCx
|
|
inline |
This function gets the ADCx alternate trigger enable setting.
base | Base address for current SIM instance. |
instance | device instance. |
|
inline |
This function selects the ADCx pre-trigger source when the alternative triggers are enabled through ADCxALTTRGEN.
base | Base address for current SIM instance. |
instance | device instance. |
select | pre-trigger select setting for ADCx |
|
inline |
This function gets the ADCx pre-trigger select setting.
base | Base address for current SIM instance. |
instance | device instance. |
|
inline |
This function selects the ADCx trigger source when alternative triggers are enabled through ADCxALTTRGEN.
base | Base address for current SIM instance. |
instance | device instance. |
select | trigger select setting for ADCx |
|
inline |
This function gets the ADCx trigger select setting.
base | Base address for current SIM instance. |
instance | device instance. |
void SIM_HAL_SetAdcTriggerModeOneStep | ( | SIM_Type * | base, |
uint32_t | instance, | ||
bool | altTrigEn, | ||
sim_adc_pretrg_sel_t | preTrigSel, | ||
sim_adc_trg_sel_t | trigSel | ||
) |
This function sets ADC alternate trigger, pre-trigger mode and trigger mode.
base | Base address for current SIM instance. |
instance | device instance. |
altTrigEn | Alternative trigger enable or not. |
preTrigSel | Pre-trigger mode. |
trigSel | Trigger mode. |
|
inline |
This function selects the source for the UARTx receive data.
base | Base address for current SIM instance. |
instance | device instance. |
select | the source for the UARTx receive data |
|
inline |
This function gets the UARTx receive data source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
|
inline |
This function selects the source for the UARTx transmit data.
base | Base address for current SIM instance. |
instance | device instance. |
select | the source for the UARTx transmit data |
|
inline |
This function gets the UARTx transmit data source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
void SIM_HAL_SetFtmTriggerSrcMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | trigger, | ||
sim_ftm_trg_src_t | select | ||
) |
This function selects the source of FTMx hardware trigger y.
base | Base address for current SIM instance. |
instance | device instance. |
trigger | hardware trigger y |
select | FlexTimer x hardware trigger y
|
sim_ftm_trg_src_t SIM_HAL_GetFtmTriggerSrcMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | trigger | ||
) |
This function gets the FlexTimer x hardware trigger y source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
trigger | hardware trigger y |
void SIM_HAL_SetFtmExternalClkPinMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
sim_ftm_clk_sel_t | select | ||
) |
This function selects the source of FTMx external clock pin select.
base | Base address for current SIM instance. |
instance | device instance. |
select | FTMx external clock pin select
|
sim_ftm_clk_sel_t SIM_HAL_GetFtmExternalClkPinMode | ( | SIM_Type * | base, |
uint32_t | instance | ||
) |
This function gets the FlexTimer x external clock pin select setting.
base | Base address for current SIM instance. |
instance | device instance. |
void SIM_HAL_SetFtmChSrcMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | channel, | ||
sim_ftm_ch_src_t | select | ||
) |
This function selects the FlexTimer x channel y input capture source.
base | Base address for current SIM instance. |
instance | device instance. |
channel | FlexTimer channel y |
select | FlexTimer x channel y input capture source |
sim_ftm_ch_src_t SIM_HAL_GetFtmChSrcMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | channel | ||
) |
This function gets the FlexTimer x channel y input capture source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
channel | FlexTimer channel y |
void SIM_HAL_SetFtmFaultSelMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | fault, | ||
sim_ftm_flt_sel_t | select | ||
) |
This function sets the FlexTimer x fault y select setting.
base | Base address for current SIM instance. |
instance | device instance. |
fault | fault y |
select | FlexTimer x fault y select setting
|
sim_ftm_flt_sel_t SIM_HAL_GetFtmFaultSelMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | fault | ||
) |
This function gets the FlexTimer x fault y select setting.
base | Base address for current SIM instance. |
instance | device instance. |
fault | fault y |
void SIM_HAL_SetFtmChOutSrcMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | channel, | ||
sim_ftm_ch_out_src_t | select | ||
) |
This function selects the FlexTimer x channel y output source.
base | Base address for current SIM instance. |
instance | device instance. |
channel | FlexTimer channel y |
select | FlexTimer x channel y output source |
sim_ftm_ch_out_src_t SIM_HAL_GetFtmChOutSrcMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
uint8_t | channel | ||
) |
This function gets the FlexTimer x channel y output source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
channel | FlexTimer channel y |
void SIM_HAL_SetFtmSyncCmd | ( | SIM_Type * | base, |
uint32_t | instance, | ||
bool | sync | ||
) |
This function sets FlexTimer x hardware trigger 0 software synchronization. FTMxSYNCBIT.
base | Base address for current SIM instance. |
instance | device instance. |
sync | Synchronize or not. |
|
inlinestatic |
This function gets FlexTimer x hardware trigger 0 software synchronization. FTMxSYNCBIT.
base | Base address for current SIM instance. |
instance | device instance. |
|
inlinestatic |
This function gets the Kinetis Family ID in the System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis Sub-Family ID in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis Series ID in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis Revision ID in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis Die ID in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis family identification in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis Pincount ID in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the program flash size in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets the Flash Doze in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
setting | Flash Doze setting |
|
inlinestatic |
This function gets the Flash Doze in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets the Flash disable setting in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
disable | Flash disable setting |
|
inlinestatic |
This function gets the Flash disable setting in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Flash maximum block 0 in Flash Configuration Register 2.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets the SDHC clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the SDHC clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
|
inlinestatic |
This function sets the ethernet timestamp clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the ethernet timestamp clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
|
inlinestatic |
This function sets the Ethernet RMII interface clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the Ethernet RMII interface clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
|
inlinestatic |
This function sets the selection of the clock to output on the RTC_CLKOUT pin.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the selection of the clock to output on the RTC_CLKOUT pin.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets divide value OUTDIV3.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets divide value OUTDIV3.
base | Base address for current SIM instance. |
|
inlinestatic |
This function controls the output drive strength of the PTD7 pin by selecting either one or two pads to drive it.
base | Base address for current SIM instance. |
setting | PTD7 pad drive strength setting
|
|
inlinestatic |
This function gets the PTD7 pad drive strength setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets the FlexBus security level setting. If the security is enabled, this field affects which CPU operations can access the off-chip via the FlexBus and DDR controller interfaces. This field has no effect if the security is not enabled.
base | Base address for current SIM instance. |
setting | FlexBus security level setting
|
|
inlinestatic |
This function gets the FlexBus security level setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the FlexNVM size in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the EEProm size in the Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the FlexNVM partition in the Flash Configuration Register1
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Flash maximum block 1 in Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the program flash maximum block 0 in Flash Configuration Register 1.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Swap program flash flag in the Flash Configuration Register 2.
base | Base address for current SIM instance. |
void CLOCK_HAL_SetUsbfsDiv | ( | SIM_Type * | base, |
uint8_t | usbdiv, | ||
uint8_t | usbfrac | ||
) |
This function sets USB FS divider setting. Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
base | Base address for current SIM instance. |
usbdiv | Value of USBFSDIV. |
usbfrac | Value of USBFSFRAC. |
void CLOCK_HAL_GetUsbfsDiv | ( | SIM_Type * | base, |
uint8_t * | usbdiv, | ||
uint8_t * | usbfrac | ||
) |
This function gets USB FS divider setting. Divider output clock = Divider input clock * [ (USBFSFRAC+1) / (USBFSDIV+1) ]
base | Base address for current SIM instance. |
usbdiv | Value of USBFSDIV. |
usbfrac | Value of USBFSFRAC. |
|
inlinestatic |
This function sets the selection of the clock source for the USB FS 48 MHz clock.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the selection of the clock source for the USB FS 48 MHz clock.
base | Base address for current SIM instance. |
instance | IP instance. |
|
inlinestatic |
This function controls whether the USB voltage regulator is enabled. This bit can only be written when the SOPT1CFG[URWE] bit is set.
base | Base address for current SIM instance. |
enable | USB voltage regulator enable setting
|
|
inlinestatic |
This function gets the USB voltage regulator enabled setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function controls whether the USB voltage regulator is placed in a standby mode during Stop, VLPS, LLS, and VLLS modes. This bit can only be written when the SOPT1CFG[USSWE] bit is set.
base | Base address for current SIM instance. |
setting | USB voltage regulator in standby mode setting
|
|
inlinestatic |
This function gets the USB voltage regulator in a standby mode setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function controls whether the USB voltage regulator is placed in a standby mode during the VLPR and the VLPW modes. This bit can only be written when the SOPT1CFG[UVSWE] bit is set.
base | Base address for current SIM instance. |
setting | USB voltage regulator in standby mode setting
|
|
inlinestatic |
This function gets the USB voltage regulator in a standby mode during the VLPR or the VLPW.
base | Base address for current SIM instance. |
|
inlinestatic |
This function controls whether the USB voltage regulator stop standby write feature is enabled. Writing one to this bit allows the SOPT1[USBSSTBY] bit to be written. This register bit clears after a write to SOPT1[USBSSTBY].
base | Base address for current SIM instance. |
enable | USB voltage regulator stop standby write enable setting
|
|
inlinestatic |
This function gets the USB voltage regulator stop standby write enable setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function controls whether USB voltage regulator VLP standby write feature is enabled. Writing one to this bit allows the SOPT1[USBVSTBY] bit to be written. This register bit clears after a write to SOPT1[USBVSTBY].
base | Base address for current SIM instance. |
enable | USB voltage regulator VLP standby write enable setting
|
|
inlinestatic |
This function gets the USB voltage regulator VLP standby write enable setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function controls whether the USB voltage regulator write enable feature is enabled. Writing one to this bit allows the SOPT1[USBREGEN] bit to be written. This register bit clears after a write to SOPT1[USBREGEN].
base | Base address for current SIM instance. |
enable | USB voltage regulator enable write enable setting
|
|
inlinestatic |
This function gets the USB voltage regulator enable write enable setting.
base | Base address for current SIM instance. |
|
inlinestatic |
Set the clock selection of LPUART.
This function sets lpuart clock source selection.
base | Base address for current SIM instance. |
instance | LPUART instance. |
setting | The value to set. |
This function sets the clock selection of LPUART.
base | Base address for current SIM instance. |
instance | LPUART instance. |
setting | The value to set. |
|
inlinestatic |
Get the clock selection of LPUART.
This function gets lpuart clock source selection.
base | Base address for current SIM instance. |
instance | LPUART instance. |
This function gets the clock selection of LPUART.
base | Base address for current SIM instance. |
instance | LPUART instance. |
|
inlinestatic |
This function selects the source for the LPUARTx receive data.
base | Base address for current SIM instance. |
instance | device instance. |
select | the source for the LPUARTx receive data |
This function selects the source for the LPUARTx receive data.
base | Register base address of SIM. |
instance | LPUART instance. |
select | the source for the LPUARTx receive data |
|
inlinestatic |
This function gets the LPUARTx receive data source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
This function gets the LPUARTx receive data source select setting.
base | Register base address of SIM. |
instance | LPUART instance. |
|
inlinestatic |
This function sets the selection of the clock source for the USB HS/USB PHY slow clock.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the selection of the clock source for the USB HS/USB PHY slow clock.
base | Base address for current SIM instance. |
instance | IP instance. |
void CLOCK_HAL_SetPllFllDiv | ( | SIM_Type * | base, |
uint8_t | pllflldiv, | ||
uint8_t | pllfllfrac | ||
) |
This function sets PLL/FLL divider setting. Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
base | Base address for current SIM instance. |
pllflldiv | Value of PLLFLLDIV. |
pllfllfrac | Value of PLLFLLFRAC. |
void CLOCK_HAL_GetPllFllDiv | ( | SIM_Type * | base, |
uint8_t * | pllflldiv, | ||
uint8_t * | pllfllfrac | ||
) |
This function gets PLL/FLL divider setting. Divider output clock = Divider input clock * [ (PLLFLLFRAC+1) / (PLLFLLDIV+1) ]
base | Base address for current SIM instance. |
pllflldiv | Value of PLLFLLDIV. |
pllfllfrac | Value of PLLFLLFRAC. |
void CLOCK_HAL_SetTraceDiv | ( | SIM_Type * | base, |
uint8_t | tracediv, | ||
uint8_t | tracefrac | ||
) |
This function sets TRACECLK divider setting. Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
base | Base address for current SIM instance. |
tracediv | Value of TRACEDIV. |
tracefrac | Value of PLLFLLFRAC. |
void CLOCK_HAL_GetTraceDiv | ( | SIM_Type * | base, |
uint8_t * | tracediv, | ||
uint8_t * | tracefrac | ||
) |
This function gets TRACECLK divider setting. Divider output clock = Divider input clock * [ (TRACEFRAC+1) / (TRACEDIV+1) ]
base | Base address for current SIM instance. |
tracediv | Value of PLLFLLDIV. |
tracefrac | Value of PLLFLLFRAC. |
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inlinestatic |
This function sets the TPM clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
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inlinestatic |
This function gets the TPM clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
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inlinestatic |
This function controls whether the USB voltage regulator inrush current limit is enabled.
base | Base address for current SIM instance. |
enable | USB voltage regulator inrush limit enable setting
|
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inlinestatic |
This function gets the USB voltage regulator inrush current limit enabled setting.
base | Base address for current SIM instance. |
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inlinestatic |
This function controls the USB voltage regulator output voltage.
base | Base address for current SIM instance. |
target | USB voltage regulator output target |
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inlinestatic |
This function gets the USB voltage regulator output voltage.
base | Base address for current SIM instance. |
enable | USB voltage regulator output target |
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inlinestatic |
This function controls whether the PLL regulator in the USB PHY is enabled. The regulator must be enabled before enabling the PLL in the USB HS PHY.
base | Base address for current SIM instance. |
enable | USB PHY PLL regulator enable setting
|
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inlinestatic |
This function gets the USB PHY PLL regulator enabled setting.
base | Base address for current SIM instance. |
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inlinestatic |
This function selects the source for the LPUARTx transmit data.
base | Base address for current SIM instance. |
instance | device instance. |
select | the source for the LPUARTx receive data |
This function selects the source for the LPUARTx transmit data.
base | Register base address of SIM. |
instance | LPUART instance. |
select | the source for the UARTx transmit data. |
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inlinestatic |
This function gets the LPUARTx transmit data source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
This function gets the LPUARTx transmit data source select setting.
base | Register base address of SIM. |
instance | LPUART instance. |
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inlinestatic |
This function sets the LPSCI clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
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inlinestatic |
This function gets the LPSCI clock source selection.
base | Base address for current SIM instance. |
instance | IP instance. |
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inlinestatic |
This function selects the source for the LPSCIx receive data.
base | Base address for current SIM instance. |
instance | device instance. |
select | the source for the LPSCIx receive data |
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inlinestatic |
This function gets the LPSCIx receive data source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
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inlinestatic |
This function selects the source for the LPSCIx transmit data.
base | Base address for current SIM instance. |
instance | device instance. |
select | the source for the LPSCIx transmit data |
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inlinestatic |
This function gets the LPSCIx transmit data source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
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inlinestatic |
This function gets the Kinetis SramSize in System Device ID register.
base | Base address for current SIM instance. |
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inlinestatic |
This function sets the clock selection of COP.
base | Base address for current SIM instance. |
setting | The value to set. |
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inlinestatic |
This function gets the clock selection of COP.
base | Base address for current SIM instance. |
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inlinestatic |
This function enables/disables the LPUARTx Open Drain.
base | Register base address of SIM. |
instance | LPUART instance. |
enable | Enable/disable LPUARTx Open Drain
|
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inlinestatic |
This function gets the LPUARTx Open Drain Enable setting.
base | Register base address of SIM. |
instance | LPUART instance. |
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inlinestatic |
This function selects the Timer/PWM x channel y input capture source.
base | Base address for current SIM instance. |
instance | device instance. |
channel | TPM channel y |
select | Timer/PWM x channel y input capture source |
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inlinestatic |
This function gets the Timer/PWM x channel y input capture source select setting.
base | Base address for current SIM instance. |
instance | device instance. |
channel | Tpm channel y |
void SIM_HAL_SetTpmExternalClkPinSelMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
sim_tpm_clk_sel_t | select | ||
) |
This function selects the source of the Timer/PWM x external clock pin select.
base | Base address for current SIM instance. |
instance | device instance. |
select | Timer/PWM x external clock pin select
|
sim_tpm_clk_sel_t SIM_HAL_GetTpmExternalClkPinSelMode | ( | SIM_Type * | base, |
uint32_t | instance | ||
) |
This function gets the Timer/PWM x external clock pin select setting.
base | Base address for current SIM instance. |
instance | device instance. |
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inlinestatic |
This function selects the clock source for FLEXIO.
base | Base address for current SIM instance. |
instance | IP instance. |
setting | The value to set. |
|
inlinestatic |
This function gets the clock source of FLEXIO.
base | Base address for current SIM instance. |
instance | IP instance. |
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inlinestatic |
This function enables/disables the UARTx Open Drain.
base | Register base address of SIM. |
instance | UART instance. |
enable | Enable/disable UARTx Open Drain
|
|
inlinestatic |
This function gets the UARTx Open Drain Enable setting.
base | Register base address of SIM. |
instance | UART instance. |
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inlinestatic |
This function gets the Kinetis SRAMSIZE ID in System Device ID register.
base | Base address for current SIM instance. |
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inlinestatic |
This function sets divide value OUTDIV5EN.
base | Base address for current SIM instance. |
setting | The value to set. |
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inlinestatic |
This function gets divide value OUTDIV5EN.
base | Base address for current SIM instance. |
|
inlinestatic |
This function sets divide value OUTDIV5.
base | Base address for current SIM instance. |
setting | The value to set. |
|
inlinestatic |
This function gets divide value OUTDIV5.
base | Base address for current SIM instance. |
void CLOCK_HAL_SetAdcAltClkSrc | ( | SIM_Type * | base, |
uint32_t | instance, | ||
clock_adc_alt_src_t | adcAltSrcSel | ||
) |
This function sets the ADC ALT clock source selection setting.
base | Base address for current SIM instance. |
instance | ADC module instance. |
adcAltSrcSel | ADC ALT clock source. |
clock_adc_alt_src_t CLOCK_HAL_GetAdcAltClkSrc | ( | SIM_Type * | base, |
uint32_t | instance | ||
) |
This function gets the ADC ALT clock source selection setting.
base | Base address for current SIM instance. |
instance | ADC module instance. |
void SIM_HAL_SetUartOpenDrainMode | ( | SIM_Type * | base, |
uint32_t | instance, | ||
bool | enable | ||
) |
This function enables/disables open drain for UARTx.
base | Base address for current SIM instance. |
instance | device instance. |
enable | Enable open drain for UARTx
|
bool SIM_HAL_GetUartOpenDrainMode | ( | SIM_Type * | base, |
uint32_t | instance | ||
) |
This function Gets the UARTx open drain enable setting for UARTx.
base | Base address for current SIM instance. |
instance | device instance. |
|
inlinestatic |
This function sets the FTM Fixed clock source selection setting.
base | Base address for current SIM instance. |
ftmFixedFreqSel | FTM Fixed clock source. |
|
inlinestatic |
This function gets the FTM Fixed clock source selection setting.
base | Base address for current SIM instance. |
|
inlinestatic |
This function Sets the Carrier frequency selection for FTM0/2 output channel.
base | Base address for current SIM instance. |
select | Carrier frequency source select.
|
|
inlinestatic |
This function gets Carrier frequency selection setting for FTM0/2 output channel.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Kinetis SubFam ID in System Device ID register.
base | Base address for current SIM instance. |
|
inlinestatic |
This function gets the Flash maximum block in Flash Configuration Register 2.
base | Base address for current SIM instance. |
sim_hal_status_t CLOCK_HAL_SetSource | ( | SIM_Type * | base, |
clock_source_names_t | clockSource, | ||
uint8_t | setting | ||
) |
This function sets the settings for a specified clock source. Each clock source has its own clock selection settings. See the chip reference manual for clock source detailed settings and the clock_source_names_t for clock sources.
base | Base address for current SIM instance. |
clockSource | Clock source name defined in sim_clock_source_names_t |
setting | Setting value |
sim_hal_status_t CLOCK_HAL_GetSource | ( | SIM_Type * | base, |
clock_source_names_t | clockSource, | ||
uint8_t * | setting | ||
) |
This function gets the settings for a specified clock source. Each clock source has its own clock selection settings. See the reference manual for clock source detailed settings and the clock_source_names_t for clock sources.
base | Base address for current SIM instance. |
clockSource | Clock source name |
setting | Current setting for the clock source |
sim_hal_status_t CLOCK_HAL_SetDivider | ( | SIM_Type * | base, |
clock_divider_names_t | clockDivider, | ||
uint32_t | setting | ||
) |
This function sets the setting for a specified clock divider. See the reference manual for a supported clock divider and value range and the clock_divider_names_t for dividers.
base | Base address for current SIM instance. |
clockDivider | Clock divider name |
setting | Divider setting |