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Kinetis SDK v.1.2 Demo Applications User's Guide
Rev. 0
Freescale Semiconductor, Inc.
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The FlexIO I2S example project is a demonstration program that uses the KSDK software. This example plays back a period of sound stored in the Flash. This example involves four methods:
This Tower System module is supported by the FlexIO I2S example:
This example requires connecting the FLEXIO pins with the SAI pins so that the I2S signals can route to the TWR-SGTL5000 board. Connect FlexIO pins to the SAI pins. Note that the default uses the FlexIO pin0 ~ pin3:
Flexio Pins | Connects To | SAI Pins | |
Flexio Pin0 | -> | SAI TxData | |
Flexio Pin1 | -> | SAI RxData | |
Flexio Pin2 | -> | SAI SCLK | |
Flexio Pin3 | -> | SAI FS |
Make these connections between the FlexIO pins and SAI pins by using external wires:
Flexio Pins | Connects To | SAI Pins | ||
Pin Name | Board Location | Pin Name | Board Location | |
PTD2/FLEXIO_PIN2 (*) | Primary Elevator B45 | -> | SAI SCLK (*) | Primary Elevator A22 |
PTD3/FLEXIO_PIN3 (*) | Primary Elevator B44 | -> | SAI Fs (*) | Primary Elevator A23 |
PTD0/FLEXIO_PIN0 | Primary Elevator B46 | -> | SAI TxData | Primary Elevator A25 |
PTD0/FLEXIO_PIN1 | Primary Elevator B48 | -> | SAI TxData | Primary Elevator A24 |
These instruction are repeatedly displayed/shown on the terminal window:
Users can hear the sine wave sound in the headphones. <note> Because the FlexIO does not have the MCLK, the example has to use the MCLK in the TWR-SGTL5000 board to make the codec work correctly. The clock, which is not a part of the FlexIO clock source, is not accurate. This issue causes the clock mismatch between the FlexIO and the sgtl5000 codec. As a result, when the FlexIO i2s is the master, it has a certain amount of noise.