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Kinetis SDK v.1.2 API Reference Manual
Rev. 0
Freescale Semiconductor, Inc.
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The section describes the enumerations, macros and data structures for KV10Z7 SIM HAL driver.
Files | |
file | fsl_sim_hal_MKV10Z7.h |
Macros | |
#define | FSL_SIM_SCGC_BIT(SCGCx, n) (((SCGCx-1U)<<5U) + n) |
SIM SCGC bit index. More... | |
Enumerations | |
enum | clock_wdog_src_kv10z7_t { kClockWdogSrcLpoClk, kClockWdogSrcAltClk } |
WDOG clock source select. More... | |
enum | clock_lptmr_src_kv10z7_t { kClockLptmrSrcMcgIrClk, kClockLptmrSrcLpoClk, kClockLptmrSrcEr32kClk, kClockLptmrSrcOsc0erClk } |
LPTMR clock source select. More... | |
enum | clock_er32k_src_kv10z7_t { kClockEr32kSrcOsc0 = 0U, kClockEr32kSrcLpo = 3U } |
SIM external reference clock source select (OSC32KSEL). More... | |
enum | clock_clkout_src_kv10z7_t { kClockClkoutSelBusClk = 2U, kClockClkoutSelLpoClk = 3U, kClockClkoutSelMcgIrClk = 4U, kClockClkoutSelOsc0erClk = 6U } |
SIM CLKOUT_SEL clock source select. More... | |
enum | sim_adc_pretrg_sel_kv10z7_t { kSimAdcPretrgselA, kSimAdcPretrgselB } |
SIM ADCx pre-trigger select. More... | |
enum | sim_adc_trg_sel_kv10z7_t { kSimAdcTrgselExt = 0U, kSimAdcTrgSelHighSpeedComp0 = 1U, kSimAdcTrgSelHighSpeedComp1 = 2U, kSimAdcTrgSelDma0 = 4U, kSimAdcTrgSelDma1 = 5U, kSimAdcTrgSelDma2 = 6U, kSimAdcTrgSelDma3 = 7U, kSimAdcTrgSelFtm0 = 8U, kSimAdcTrgSelFtm1 = 9U, kSimAdcTrgSelFtm2 = 10U, kSimAdcTrgSelLptimer = 14U } |
SIM ADCx trigger select. More... | |
enum | sim_uart_rxsrc_kv10z7_t { kSimUartRxsrcPin, kSimUartRxsrcCmp0, kSimUartRxsrcCmp1 } |
SIM UART receive data source select. More... | |
enum | sim_uart_txsrc_kv10z7_t { kSimUartTxsrcPin, kSimUartTxsrcFtm1, kSimUartTxsrcFtm2 } |
SIM UART transmit data source select. More... | |
enum | sim_ftm_trg_src_kv10z7_t { kSimFtmTrgSrc0, kSimFtmTrgSrc1 } |
SIM FlexTimer x trigger y select. More... | |
enum | sim_ftm_clk_sel_kv10z7_t { kSimFtmClkSel0, kSimFtmClkSel1, kSimFtmClkSel2 } |
SIM FlexTimer external clock select. More... | |
enum | clock_ftm_fixedfreq_src_kv10z7_t { kClockFtmClkMcgFfClk = 0U, kClockFtmClkMcgIrClk = 1U, kClockFtmClkOsc0erClk = 2U } |
SIM FlexTimer Fixed Frequency clock source. More... | |
enum | clock_adc_alt_src_kv10z7_t { kClockAdcAltClkSrcOutdiv5 = 0U, kClockAdcAltClkSrcMcgIrClk = 1U, kClockAdcAltClkSrcOsc0erClk = 2U } |
SIM ADC alt clock source. More... | |
enum | sim_ftm_ch_src_kv10z7_t { kSimFtmChSrc0, kSimFtmChSrc1, kSimFtmChSrc2, kSimFtmChSrc3 } |
SIM FlexTimer x channel y input capture source select. More... | |
enum | sim_ftm_ch_out_src_kv10z7_t { kSimFtmChOutSrc0, kSimFtmChOutSrc1 } |
SIM FlexTimer x channel y output source select. More... | |
enum | sim_ftm_flt_sel_kv10z7_t { kSimFtmFltSel0, kSimFtmFltSel1 } |
SIM FlexTimer x Fault y select. More... | |
enum | sim_ftm_flt_carrier_sel_kv10z7_t { kSimFtmCarrierSel0, kSimFtmCarrierSel1 } |
SIM FlexTimer0/2 output channel Carrier frequency selection. More... | |
enum | sim_clock_gate_name_kv10z7_t { kSimClockGateEwm0 = FSL_SIM_SCGC_BIT(4U, 1U), kSimClockGateI2c0 = FSL_SIM_SCGC_BIT(4U, 6U), kSimClockGateUart0 = FSL_SIM_SCGC_BIT(4U, 10U), kSimClockGateUart1 = FSL_SIM_SCGC_BIT(4U, 11U), kSimClockGateCmp = FSL_SIM_SCGC_BIT(4U, 19U), kSimClockGateLptmr0 = FSL_SIM_SCGC_BIT(5U, 0U), kSimClockGatePortA = FSL_SIM_SCGC_BIT(5U, 9U), kSimClockGatePortB = FSL_SIM_SCGC_BIT(5U, 10U), kSimClockGatePortC = FSL_SIM_SCGC_BIT(5U, 11U), kSimClockGatePortD = FSL_SIM_SCGC_BIT(5U, 12U), kSimClockGatePortE = FSL_SIM_SCGC_BIT(5U, 13U), kSimClockGateFtf0 = FSL_SIM_SCGC_BIT(6U, 0U), kSimClockGateDmamux0 = FSL_SIM_SCGC_BIT(6U, 1U), kSimClockGateSpi0 = FSL_SIM_SCGC_BIT(6U, 12U), kSimClockGateCrc0 = FSL_SIM_SCGC_BIT(6U, 18U), kSimClockGatePdb0 = FSL_SIM_SCGC_BIT(6U, 22U), kSimClockGateFtm0 = FSL_SIM_SCGC_BIT(6U, 24U), kSimClockGateFtm1 = FSL_SIM_SCGC_BIT(6U, 25U), kSimClockGateFtm2 = FSL_SIM_SCGC_BIT(6U, 26U), kSimClockGateAdc0 = FSL_SIM_SCGC_BIT(6U, 27U), kSimClockGateAdc1 = FSL_SIM_SCGC_BIT(6U, 28U), kSimClockGateDac0 = FSL_SIM_SCGC_BIT(6U, 31U), kSimClockGateDma0 = FSL_SIM_SCGC_BIT(7U, 8U) } |
Clock gate name used for SIM_HAL_EnableClock/SIM_HAL_DisableClock. More... | |
#define FSL_SIM_SCGC_BIT | ( | SCGCx, | |
n | |||
) | (((SCGCx-1U)<<5U) + n) |