24 #define ADC_CHANNEL_DCBI 4
25 #define ADC_CHANNEL_DCBV 5
26 #define ADC_CHANNEL_PHASEA 6
27 #define ADC_CHANNEL_PHASEB 9
28 #define ADC_CHANNEL_PHASEC 7
29 #define ADC_CHANNEL_DISABLED 31
31 #define ISR_PRIORITY_ADC0 1 // zero-cross, sensorless control
32 #define ISR_PRIORITY_SLOW_TIMER 3 // speed control loop (low ISR priority)
33 #define ISR_PRIORITY_FORCED_CMT 1 // forced commutation (when missed sensorless cmt, open loop, timing)
34 #define ISR_PRIORITY_PDB0 1 // PDB trigger error clearing
36 #define CPU_CLOCK 72000000UL
37 #define BUS_CLOCK (CPU_CLOCK / 3)
38 #define TIMER_FREQUENCY (CPU_CLOCK / 128) // 585.9375 kHz @ 75 MHz, 562.5 kHz @ 72 MHz
39 #define TIMER_1MS_CONST (TIMER_FREQUENCY / 1000)
40 #define SLOW_TIMER_PERIOD (CPU_CLOCK / 2000) // 1 ms period (slow control timer uses divider by 2 and cpu clock)
41 #define PWM_MODULO 3600 // 20 kHz = 3750 @ 75 MHz, 3600 @ 72 MHz
42 #define UART_BAUDRATE 9600
char swap
Definition: hwconfig.h:50
char mask
Definition: hwconfig.h:49
Definition: hwconfig.h:47
const unsigned short bldcAdcSectorCfg[8]
Definition: peripherals_init.c:47
const Pwm_sChannelControl bldcCommutationTableComp[8]
Definition: peripherals_init.c:36