31 #ifndef _FLASH_DEMO_H_
32 #define _FLASH_DEMO_H_
39 #define LAUNCH_CMD_SIZE 0x100
42 #define CALLBACK_SIZE 0x80
44 #define BUFFER_SIZE_BYTE 0x80
46 #define FTFx_REG_BASE 0x40020000
47 #define P_FLASH_BASE 0x00000000
50 #define P_FLASH_SIZE (FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE * FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT)
51 #define P_BLOCK_NUM FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT
52 #define P_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE
54 #define FLEXNVM_BASE FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS
55 #define FLEXNVM_SECTOR_SIZE FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE
56 #define FLEXNVM_BLOCK_SIZE FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE
57 #define FLEXNVM_BLOCK_NUM FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT
60 #define EERAM_BASE FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS
61 #define EERAM_SIZE FSL_FEATURE_FLASH_FLEX_RAM_SIZE
64 #if (FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE == 8)
65 #define SECURITY_LOCATION 0x408
67 #define SECURITY_LOCATION 0x40C
70 #define BACKDOOR_KEY_LOCATION 0x400
73 #if (FSL_FEATURE_FLASH_IS_FTFE == 1)
74 #define PFLASH_IFR 0x3C0
76 #define PFLASH_IFR 0xC0
79 #if (FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP == 1)
80 #if (FSL_FEATURE_FLASH_IS_FTFE == 1)
81 #define SWAP_STATUS_BIT (REG_READ(FTFx_REG_BASE + FTFx_SSD_FCNFG_OFFSET) & FTFE_FCNFG_SWAP_MASK)
83 #if (FSL_FEATURE_FLASH_IS_FTFL == 1)
84 #define SWAP_STATUS_BIT (REG_READ(FTFx_REG_BASE + FTFx_SSD_FCNFG_OFFSET) & FTFL_FCNFG_SWAP_MASK)
86 #if (FSL_FEATURE_FLASH_IS_FTFA == 1)
87 #define SWAP_STATUS_BIT (REG_READ(FTFx_REG_BASE + FTFx_SSD_FCNFG_OFFSET) & FTFA_FCNFG_SWAP_MASK)
92 #if (FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS == 1)
93 #define CACHE_DISABLE MCM_BWR_PLACR_DFCS(MCM_BASE_PTR, 1);
95 #elif (FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS == 1)
96 #if defined(FMC_PFB1CR) && defined(FMC_PFB1CR_B1SEBE_MASK)
97 #define CACHE_DISABLE FMC_PFB0CR &= ~(FMC_PFB0CR_B0SEBE_MASK | FMC_PFB0CR_B0IPE_MASK | FMC_PFB0CR_B0DPE_MASK | FMC_PFB0CR_B0ICE_MASK | FMC_PFB0CR_B0DCE_MASK);\
98 FMC_PFB1CR &= ~(FMC_PFB1CR_B1SEBE_MASK | FMC_PFB1CR_B1IPE_MASK | FMC_PFB1CR_B1DPE_MASK | FMC_PFB1CR_B1ICE_MASK | FMC_PFB1CR_B1DCE_MASK);
99 #elif defined(FMC_PFB23CR)
100 #define CACHE_DISABLE FMC_PFB01CR &= ~(FMC_PFB01CR_B0IPE_MASK | FMC_PFB01CR_B0DPE_MASK | FMC_PFB01CR_B0ICE_MASK | FMC_PFB01CR_B0DCE_MASK);\
101 FMC_PFB23CR &= ~(FMC_PFB23CR_B1IPE_MASK | FMC_PFB23CR_B1DPE_MASK | FMC_PFB23CR_B1ICE_MASK | FMC_PFB23CR_B1DCE_MASK);
103 #define CACHE_DISABLE FMC_PFB0CR &= ~(FMC_PFB0CR_B0SEBE_MASK | FMC_PFB0CR_B0IPE_MASK | FMC_PFB0CR_B0DPE_MASK | FMC_PFB0CR_B0ICE_MASK | FMC_PFB0CR_B0DCE_MASK);
107 #define CACHE_DISABLE
114 #define DEBUGENABLE 0x00
116 #define READ_NORMAL_MARGIN 0x00
117 #define READ_USER_MARGIN 0x01
118 #define READ_FACTORY_MARGIN 0x02
120 #define ONE_KB 1024 //0x400: 10 zeros
121 #define TWO_KB (2*ONE_KB)
122 #define THREE_KB (3*ONE_KB)
123 #define FOUR_KB (4*ONE_KB)
124 #define FIVE_KB (5*ONE_KB)
125 #define SIX_KB (6*ONE_KB)
126 #define SEVEN_KB (7*ONE_KB)
127 #define EIGHT_KB (8*ONE_KB)
128 #define NINE_KB (9*ONE_KB)
129 #define TEN_KB (10*ONE_KB)
130 #define ONE_MB (ONE_KB*ONE_KB) //0x100000: 20 zeros
131 #define ONE_GB (ONE_KB*ONE_KB*ONE_KB) //0x40000000: 30 zeros
143 #define PSWAP_INDICATOR_ADDR (P_FLASH_SIZE/2 - 2*(FTFx_PSECTOR_SIZE))
146 #define PSWAP_LOWERDATA_ADDR (PSWAP_INDICATOR_ADDR + FTFx_PSECTOR_SIZE + 0x100)
147 #define PSWAP_UPPERDATA_ADDR (PSWAP_INDICATOR_ADDR + FTFx_PSECTOR_SIZE + P_FLASH_SIZE/2 + 0x100)
154 extern uint32_t
RelocateFunction(uint32_t dest, uint32_t size, uint32_t src);
158 #if (defined(SWAP_M))
159 uint32_t flash_swap(
void);
160 void run_flash_swap(
void);
161 void print_swap_application_data(
void);
void ErrorTrap(uint32_t returnCode)
Definition: demo_apps/flash_demo/main.c:372
void callback(void)
Definition: flash_demo_ram.c:707
void print_welcome_message(void)
uint32_t RelocateFunction(uint32_t dest, uint32_t size, uint32_t src)