13 #include "rl_fs_lib.h"
23 #error "File System does not work with MicroLIB"
30 #define NOR0_DEFAULT_DRIVE 0
35 #define NOR1_DEFAULT_DRIVE 0
40 #define RAM0_DEFAULT_DRIVE 0
46 #define MC0_DEFAULT_DRIVE 0
52 #define MC1_DEFAULT_DRIVE 0
57 #define NAND0_ENABLE 0
58 #define NAND0_DEFAULT_DRIVE 0
63 #define NAND1_ENABLE 0
64 #define NAND1_DEFAULT_DRIVE 0
70 #define USB0_DEFAULT_DRIVE 0
76 #define USB1_DEFAULT_DRIVE 0
82 #define FS_NDRV (NOR0_ENABLE + NOR1_ENABLE + \
84 MC0_ENABLE + MC1_ENABLE + \
85 USB0_ENABLE + USB1_ENABLE + \
86 NAND0_ENABLE + NAND1_ENABLE)
88 #error "No drive enabled, File System requires at least on component ::File System:Drive"
92 #define FS_FAT_NDRV (RAM0_ENABLE \
93 MC0_ENABLE + MC1_ENABLE + \
94 USB0_ENABLE + USB1_ENABLE + \
95 NAND0_ENABLE + NAND1_ENABLE)
98 #define FS_NAND_NDRV (NAND0_ENABLE + NAND1_ENABLE)
101 #define __DEF ((NOR0_DEFAULT_DRIVE & NOR0_ENABLE) + \
102 (NOR1_DEFAULT_DRIVE & NOR1_ENABLE) + \
103 (RAM0_DEFAULT_DRIVE & RAM0_ENABLE) + \
104 (MC0_DEFAULT_DRIVE & MC0_ENABLE) + \
105 (MC1_DEFAULT_DRIVE & MC1_ENABLE) + \
106 (USB0_DEFAULT_DRIVE & USB0_ENABLE) + \
107 (USB1_DEFAULT_DRIVE & USB1_ENABLE) + \
108 (NAND0_DEFAULT_DRIVE & NAND0_ENABLE) + \
109 (NAND1_DEFAULT_DRIVE & NAND1_ENABLE))
111 #error "Default ::File System:Drive not specified"
113 #error "Multiple default ::File System:Drive: enabled"
117 #if (MC0_ENABLE && MC1_ENABLE)
118 #if (MC0_MCI_DRIVER == MC1_MCI_DRIVER)
119 #error "::File System:Drive:Memory Card: MCI ports for different drives must be different"
124 #define EFS_USE (NOR0_ENABLE + NOR1_ENABLE)
125 #define FAT_USE (RAM0_ENABLE + MC0_ENABLE + MC1_ENABLE + USB0_ENABLE + USB1_ENABLE + NAND0_ENABLE + NAND1_ENABLE)
128 #define FSJ_USE (MC0_ENABLE * MC0_FAT_JOURNAL + \
129 MC1_ENABLE * MC1_FAT_JOURNAL + \
130 USB0_ENABLE * USB0_FAT_JOURNAL + \
131 USB1_ENABLE * USB1_FAT_JOURNAL + \
132 NAND0_ENABLE * NAND0_FAT_JOURNAL + \
133 NAND1_ENABLE * NAND1_FAT_JOURNAL)
136 #define FAT_SECT_RSVD 64
140 extern volatile int _stream_list_lock;
141 #define STREAM_LIST_LOCK _stream_list_lock;
143 #define STREAM_LIST_LOCK
156 #if (FAT_NAME_CACNT == 0)
161 #if (FAT_NAME_RELOC == 1)
162 #define __AT_FAT_NAME __at(FAT_NAME_CADR)
164 #define __AT_FAT_NAME
168 #define FAT_NAME_MAX_DEPTH 8
171 #define FAT_NAME_CB_SZ (16)
172 #define FAT_NAME_CB_POOL_SZ (FAT_NAME_CB_SZ * FS_FAT_NDRV)
175 #define FAT_NAME_DEPTH_CB_SZ (8)
176 #define FAT_NAME_DEPTH_POOL_SZ (FAT_NAME_DEPTH_CB_SZ * FAT_NAME_MAX_DEPTH)
179 #define FAT_NAME_LINK_SZ (48)
180 #define FAT_NAME_LINK_POOL_SZ (FAT_NAME_LINK_SZ * FAT_NAME_CACNT)
183 #define FAT_NAME_CACHE_SZ (FAT_NAME_CB_POOL_SZ + \
184 FAT_NAME_DEPTH_POOL_SZ + \
185 FAT_NAME_LINK_POOL_SZ)
187 uint32_t fat_name_pool[FAT_NAME_CACHE_SZ/4] __AT_FAT_NAME;
197 #define EXPAND_SYMBOL(name, port) name##port
198 #define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
204 static EFS_VI nor0_vol;
206 extern ARM_DRIVER_NOR
CREATE_SYMBOL (Driver_NOR_, NOR0_NAME);
207 extern ARM_NOR_DEVICE
CREATE_SYMBOL (NOR_Device_, NOR0_NAME);
210 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, NOR0_SPI_DRIVER);
219 static EFS_VI nor1_vol;
221 extern ARM_DRIVER_NOR
CREATE_SYMBOL (Driver_NOR_, NOR1_NAME);
222 extern ARM_NOR_DEVICE
CREATE_SYMBOL (NOR_Device_, NOR1_NAME);
225 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, NOR1_SPI_DRIVER);
234 static FAT_VI mc0_vol;
235 static MCI_DEV mc0_dev;
237 #if (MC0_FAT_JOURNAL)
238 static FSJOUR mc0_fsj;
241 extern ARM_DRIVER_MCI
CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
243 #if (MC0_CACHE_RELOC == 1)
244 #define __AT_MC0 __at(MC0_CACHE_ADDR)
250 static uint32_t mc0_cache[(MC0_CACHE_SIZE+1) * 256 + MC0_FAT_JOURNAL * 128] __AT_MC0;
254 #define MC0_INIT(m) mc_mci_Init (m, &mc0_dev)
255 #define MC0_UNINIT(m) mc_mci_UnInit (m, &mc0_dev)
256 #define MC0_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc0_dev)
257 #define MC0_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc0_dev)
258 #define MC0_RDINFO(i) mc_mci_ReadInfo (i, &mc0_dev)
259 #define MC0_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc0_dev)
262 #define MC0_INIT(m) mc_spi_Init (m, &mc0_dev)
263 #define MC0_UNINIT(m) mc_spi_UnInit (m, &mc0_dev)
264 #define MC0_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc0_dev)
265 #define MC0_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc0_dev)
266 #define MC0_RDINFO(i) mc_spi_ReadInfo (i, &mc0_dev)
267 #define MC0_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc0_dev)
269 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
273 static uint32_t mc0_Init (uint32_t mode) {
274 return (MC0_INIT (mode));
276 static uint32_t mc0_UnInit (uint32_t mode) {
277 return (MC0_UNINIT (mode));
279 static uint32_t mc0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
280 return (MC0_RDSEC (sect, buf, cnt));
282 static uint32_t mc0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
283 return (MC0_WRSEC (sect, buf, cnt));
286 return (MC0_RDINFO (info));
289 return (MC0_DEVCTRL (code, p));
303 static void MC0_MCI_SignalEvent (ARM_MCI_EVENT event) {
304 mc_mci_DrvEvent (event, &mc0_dev);
307 static void MC0_SPI_SignalEvent (ARM_SPI_EVENT event) {
308 mc_spi_DrvEvent (event, &mc0_dev);
317 static FAT_VI mc1_vol;
318 static MCI_DEV mc1_dev;
320 #if (MC1_FAT_JOURNAL)
321 static FSJOUR mc1_fsj;
324 extern ARM_DRIVER_MCI
CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
326 #if (MC1_CACHE_RELOC == 1)
327 #define __AT_MC1 __at(MC1_CACHE_ADDR)
333 static uint32_t mc1_cache[(MC1_CACHE_SIZE+1) * 256 + MC1_FAT_JOURNAL * 128] __AT_MC1;
337 #define MC1_INIT(m) mc_mci_Init (m, &mc1_dev)
338 #define MC1_UNINIT(m) mc_mci_UnInit (m, &mc1_dev)
339 #define MC1_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc1_dev)
340 #define MC1_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc1_dev)
341 #define MC1_RDINFO(i) mc_mci_ReadInfo (i, &mc1_dev)
342 #define MC1_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc1_dev)
345 #define MC1_INIT(m) mc_spi_Init (m, &mc1_dev)
346 #define MC1_UNINIT(m) mc_spi_UnInit (m, &mc1_dev)
347 #define MC1_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc1_dev)
348 #define MC1_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc1_dev)
349 #define MC1_RDINFO(i) mc_spi_ReadInfo (i, &mc1_dev)
350 #define MC1_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc1_dev)
352 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
356 static uint32_t mc1_Init (uint32_t mode) {
357 return (MC1_INIT (mode));
359 static uint32_t mc1_UnInit (uint32_t mode) {
360 return (MC1_UNINIT (mode));
362 static uint32_t mc1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
363 return (MC1_RDSEC (sect, buf, cnt));
365 static uint32_t mc1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
366 return (MC1_WRSEC (sect, buf, cnt));
369 return (MC1_RDINFO (info));
372 return (MC1_DEVCTRL (code, p));
386 static void MC1_MCI_SignalEvent (ARM_MCI_EVENT event) {
387 mc_mci_DrvEvent (event, &mc1_dev);
390 static void MC1_SPI_SignalEvent (ARM_SPI_EVENT event) {
391 mc_spi_DrvEvent (event, &mc1_dev);
399 #ifdef RTE_FileSystem_Drive_NAND_0
401 #define NAND_INFO_0_DEV_0
403 #if ((NAND1_ENABLE) && (NAND1_DRIVER == NAND0_DRIVER))
404 #if (NAND1_DEV_NUM == NAND0_DEV_NUM)
405 #error "::File System:Drive:NAND: NAND ports for different drives must be different"
407 #define NAND_INFO_0_DEV_1
412 #ifdef RTE_FileSystem_Drive_NAND_1
413 #if (((NAND0_ENABLE == 0) && NAND1_ENABLE) || ((NAND0_ENABLE && NAND1_ENABLE) && (NAND1_DRIVER != NAND0_DRIVER)))
414 #define NAND_INFO_1_DEV_0
419 static FAT_VI nand0_vol;
420 static NAND_FTL_DEV nand0_dev;
422 #if (NAND0_FAT_JOURNAL)
423 static FSJOUR nand0_fsj;
426 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
430 static FAT_VI nand1_vol;
431 static NAND_FTL_DEV nand1_dev;
433 #if (NAND1_FAT_JOURNAL)
434 static FSJOUR nand1_fsj;
437 #if defined(NAND_INFO_1_DEV_0)
438 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
442 #if defined(NAND_INFO_0_DEV_0)
443 #define NAND0_EVENT_HANDLER NAND_SignalEventHandler0
444 #if defined(NAND_INFO_0_DEV_1)
445 #define NAND1_EVENT_HANDLER NAND_SignalEventHandler0
448 void NAND_SignalEventHandler0 (uint32_t dev_num) {
450 case NAND0_DEV_NUM: ftl_DrvEvent (&nand0_dev);
break;
452 #if defined(NAND_INFO_0_DEV_1)
453 case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev);
break;
460 ARM_NAND_DEVICE NAND_DevInfo0[] = {
467 NAND_SEC_BLOCK (NAND0_PAGE_COUNT, NAND0_PAGE_SIZE),
468 NAND_SEC_PAGE (NAND0_PAGE_SIZE),
469 NAND_ROW_CYCLES (NAND0_BLOCK_COUNT, NAND0_PAGE_COUNT),
470 NAND_COL_CYCLES (NAND0_PAGE_SIZE),
473 #if defined(NAND_INFO_0_DEV_1)
480 NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
481 NAND_SEC_PAGE (NAND1_PAGE_SIZE),
482 NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
483 NAND_COL_CYCLES (NAND1_PAGE_SIZE),
488 #define NAND_INFO0 NAND_DevInfo0
489 #define NAND_INFO0_SZ (sizeof(NAND_DevInfo0) / sizeof(NAND_DevInfo0[0]))
491 #define NAND_INFO0 NULL
492 #define NAND_INFO0_SZ 0
495 #if defined(NAND_INFO_1_DEV_0)
496 #define NAND1_EVENT_HANDLER NAND_SignalEventHandler1
498 void NAND_SignalEventHandler1 (uint32_t dev_num) {
500 case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev);
break;
506 ARM_NAND_DEVICE NAND_DevInfo1[] = {
513 NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
514 NAND_SEC_PAGE (NAND1_PAGE_SIZE),
515 NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
516 NAND_COL_CYCLES (NAND1_PAGE_SIZE),
520 #define NAND_INFO1 NAND_DevInfo1
521 #define NAND_INFO1_SZ (sizeof(NAND_DevInfo1) / sizeof(NAND_DevInfo1[0]))
523 #define NAND_INFO1 NULL
524 #define NAND_INFO1_SZ 0
531 #if (NAND0_CACHE_RELOC == 1)
532 #define __AT_NAND0 __at(NAND0_CACHE_ADDR)
538 #define NAND0_CSZ ((NAND0_CACHE_SIZE + 1) * 1024 + \
539 (NAND0_PAGE_CACHE + 2) * NAND0_PAGE_SIZE + \
540 (NAND0_BLOCK_CACHE + 2) * NAND0_PAGE_COUNT)
541 #define NAND0_FSJBUF (NAND0_FAT_JOURNAL * 512)
543 static uint32_t nand0_cache[NAND0_CSZ/4 + NAND0_FSJBUF/4] __AT_NAND0;
544 static PAGE_CACHE nand0_capg [NAND0_PAGE_CACHE + 1];
545 static BLOCK_CACHE nand0_cabl [NAND0_BLOCK_CACHE + 2];
546 static uint32_t nand0_ttsn [NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE)];
549 static NAND_FTL_CFG nand0_cfg = {
552 NAND_BTT_SIZE (NAND0_BLOCK_COUNT),
555 NAND_BTT_SIZE (NAND0_BLOCK_COUNT) + 1,
556 NAND0_BLOCK_COUNT - 1,
559 NAND0_BLOCK_CACHE + 2,
560 NAND0_PAGE_CACHE + 1,
561 NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE),
564 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256],
566 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+(NAND0_PAGE_CACHE+2)*NAND0_PAGE_SIZE/4],
568 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+NAND0_PAGE_SIZE/4],
573 static uint32_t nand0_Init (uint32_t mode) {
576 static uint32_t nand0_UnInit (uint32_t mode) {
577 return (ftl_UnInit (mode, &nand0_dev));
579 static uint32_t nand0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
580 uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand0_dev);
581 if (retv < 2)
return (
true);
584 static uint32_t nand0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
585 uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand0_dev);
586 if (retv < 2)
return (
true);
590 return (ftl_ReadInfo (info, &nand0_dev));
593 return (ftl_DevCtrl (code, p, &nand0_dev));
596 FAT_DRV nand0_drv = {
610 #if (NAND1_CACHE_RELOC == 1)
611 #define __AT_NAND1 __at(NAND1_CACHE_ADDR)
617 #define NAND1_CSZ ((NAND1_CACHE_SIZE + 1) * 1024 + \
618 (NAND1_PAGE_CACHE + 2) * NAND1_PAGE_SIZE + \
619 (NAND1_BLOCK_CACHE + 2) * NAND1_PAGE_COUNT)
620 #define NAND1_FSJBUF (NAND1_FAT_JOURNAL * 512)
622 static uint32_t nand1_cache[NAND1_CSZ/4 + NAND1_FSJBUF/4] __AT_NAND1;
623 static PAGE_CACHE nand1_capg [NAND1_PAGE_CACHE + 1];
624 static BLOCK_CACHE nand1_cabl [NAND1_BLOCK_CACHE + 2];
625 static uint32_t nand1_ttsn [NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE)];
628 static NAND_FTL_CFG nand1_cfg = {
631 NAND_BTT_SIZE (NAND1_BLOCK_COUNT),
634 NAND_BTT_SIZE (NAND1_BLOCK_COUNT) + 1,
635 NAND1_BLOCK_COUNT - 1,
638 NAND1_BLOCK_CACHE + 2,
639 NAND1_PAGE_CACHE + 1,
640 NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE),
643 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256],
645 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+(NAND1_PAGE_CACHE+2)*NAND1_PAGE_SIZE/4],
647 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+NAND1_PAGE_SIZE/4],
652 static uint32_t nand1_Init (uint32_t mode) {
655 static uint32_t nand1_UnInit (uint32_t mode) {
656 return (ftl_UnInit (mode, &nand1_dev));
658 static uint32_t nand1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
659 uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand1_dev);
660 if (retv < 2)
return (
true);
663 static uint32_t nand1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
664 uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand1_dev);
665 if (retv < 2)
return (
true);
669 return (ftl_ReadInfo (info, &nand1_dev));
672 return (ftl_DevCtrl (code, p, &nand1_dev));
675 FAT_DRV nand1_drv = {
689 static FAT_VI ram0_vol;
691 #if (RAM0_SIZE < 0x4A00)
692 #error "::File System:Drive:RAM requires minimum of 0x4A00 bytes of memory"
695 #if (RAM0_RELOC == 1)
696 #define __AT_RAM0 __at(RAM0_BASE_ADDR)
702 static uint32_t ram0_buf[256 + (RAM0_SIZE/4)] __AT_RAM0;
705 static RAM_DEV ram0_dev = {
706 (uint8_t *)&ram0_buf[256],
711 static uint32_t ram0_Init (uint32_t mode) {
712 return (ram_Init (mode, &ram0_dev));
714 static uint32_t ram0_UnInit (uint32_t mode) {
715 return (ram_UnInit (mode, &ram0_dev));
717 static uint32_t ram0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
718 return (ram_ReadSector (sect, buf, cnt, &ram0_dev));
720 static uint32_t ram0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
721 return (ram_WriteSector (sect, buf, cnt, &ram0_dev));
724 return (ram_ReadInfo (info, &ram0_dev));
727 return (ram_DevCtrl (code, p, &ram0_dev));
745 extern FAT_DRV usb0_drv;
747 #if (USB0_FAT_JOURNAL)
748 static FSJOUR usb0_fsj;
752 static uint32_t usb0_cache[(USB0_CACHE_SIZE+1) * 256 + USB0_FAT_JOURNAL * 128];
753 static FAT_VI usb0_vol;
756 static uint32_t usb0_Init (uint32_t mode) {
757 return (FS_USBH_MSC_Initialize (0, mode));
759 static uint32_t usb0_UnInit (uint32_t mode) {
760 return (FS_USBH_MSC_Uninitialize (0, mode));
762 static uint32_t usb0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
763 return (FS_USBH_MSC_ReadSectors (0, sect, cnt, buf));
765 static uint32_t usb0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
766 return (FS_USBH_MSC_WriteSectors (0, sect, cnt, buf));
769 return (FS_USBH_MSC_ReadInfo (0, info));
772 return (FS_USBH_MSC_DeviceCtrl (0, code, p));
789 extern FAT_DRV usb1_drv;
791 #if (USB1_FAT_JOURNAL)
792 static FSJOUR usb1_fsj;
796 static uint32_t usb1_cache[(USB1_CACHE_SIZE+1) * 256 + USB1_FAT_JOURNAL * 128];
797 static FAT_VI usb1_vol;
800 static uint32_t usb1_Init (uint32_t mode) {
801 return (FS_USBH_MSC_Initialize (1, mode));
803 static uint32_t usb1_UnInit (uint32_t mode) {
804 return (FS_USBH_MSC_Uninitialize (1, mode));
806 static uint32_t usb1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
807 return (FS_USBH_MSC_ReadSectors (1, sect, cnt, buf));
809 static uint32_t usb1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
810 return (FS_USBH_MSC_WriteSectors (1, sect, cnt, buf));
813 return (FS_USBH_MSC_ReadInfo (1, info));
816 return (FS_USBH_MSC_DeviceCtrl (1, code, p));
870 nor0_vol.BaseAdr = NOR0_BASE_ADDR;
871 nor0_vol.InitVal =
CREATE_SYMBOL (NOR_Device_, NOR0_NAME).erased_value * 0x01010101;
872 nor0_vol.NumSect =
CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_count;
874 nor0_vol.DevCfg =
CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_info;
879 nor1_vol.BaseAdr = NOR1_BASE_ADDR;
880 nor1_vol.InitVal =
CREATE_SYMBOL (NOR_Device_, NOR1_NAME).erased_value * 0x01010101;
881 nor1_vol.NumSect =
CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_count;
883 nor1_vol.DevCfg =
CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_info;
887 mc0_vol.Drv = &mc0_drv;
888 mc0_vol.CaBuf = mc0_cache;
889 mc0_vol.CaSize = MC0_CACHE_SIZE * 2;
892 mc0_dev.DrvMci = &
CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
893 mc0_dev.MCI_Callback = MC0_MCI_SignalEvent;
896 mc0_dev.DrvSpi = &
CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
897 mc0_dev.SPI_Callback = MC0_SPI_SignalEvent;
900 #if (MC0_FAT_JOURNAL)
902 mc0_fsj.buf = (uint8_t *)&mc0_cache[(MC0_CACHE_SIZE+1) * 256];
903 mc0_vol.fsj = &mc0_fsj;
912 mc1_vol.Drv = &mc1_drv;
913 mc1_vol.CaBuf = mc1_cache;
914 mc1_vol.CaSize = MC1_CACHE_SIZE * 2;
917 mc1_dev.DrvMci = &
CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
918 mc1_dev.MCI_Callback = MC1_MCI_SignalEvent;
921 mc1_dev.DrvSpi = &
CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
922 mc1_dev.SPI_Callback = MC1_SPI_SignalEvent;
925 #if (MC1_FAT_JOURNAL)
927 mc1_fsj.buf = (uint8_t *)&mc1_cache[(MC1_CACHE_SIZE+1) * 256];
928 mc1_vol.fsj = &mc1_fsj;
937 nand0_vol.Drv = &nand0_drv;
938 nand0_vol.CaBuf = nand0_cache;
939 nand0_vol.CaSize = NAND0_CACHE_SIZE * 2;
942 nand0_dev.Dev = &NAND_DevInfo0[0];
943 nand0_dev.Cfg = &nand0_cfg;
944 nand0_dev.Callback = NAND0_EVENT_HANDLER;
946 #if (NAND0_FAT_JOURNAL)
948 nand0_fsj.buf = (uint8_t *)&nand0_cache[NAND0_CSZ/4];
949 nand0_vol.fsj = &nand0_fsj;
952 nand0_vol.fsj = NULL;
958 nand1_vol.Drv = &nand1_drv;
959 nand1_vol.CaBuf = nand1_cache;
960 nand1_vol.CaSize = NAND1_CACHE_SIZE * 2;
963 #if defined(NAND_INFO_0_DEV_1)
964 nand1_dev.Dev = &NAND_DevInfo0[1];
966 nand1_dev.Dev = &NAND_DevInfo1[0];
968 nand1_dev.Cfg = &nand1_cfg;
969 nand1_dev.Callback = NAND1_EVENT_HANDLER;
971 #if (NAND1_FAT_JOURNAL)
973 nand1_fsj.buf = (uint8_t *)&nand1_cache[NAND1_CSZ/4];
974 nand1_vol.fsj = &nand1_fsj;
977 nand1_vol.fsj = NULL;
983 ram0_vol.Drv = &ram0_drv;
984 ram0_vol.CaBuf = ram0_buf;
991 usb0_vol.Drv = &usb0_drv;
992 usb0_vol.CaBuf = usb0_cache;
993 usb0_vol.CaSize = USB0_CACHE_SIZE * 2;
995 #if (USB0_FAT_JOURNAL)
997 usb0_fsj.buf = (uint8_t *)&usb0_cache[(USB0_CACHE_SIZE+1) * 256];
998 usb0_vol.fsj = &usb0_fsj;
1001 usb0_vol.fsj = NULL;
1007 usb1_vol.Drv = &usb1_drv;
1008 usb1_vol.CaSize = USB1_CACHE_SIZE * 2;
1009 usb1_vol.CaBuf = usb1_cache;
1012 #if (USB1_FAT_JOURNAL)
1014 usb1_fsj.buf = (uint8_t *)&usb1_cache[(USB1_CACHE_SIZE+1) * 256];
1015 usb1_vol.fsj = &usb1_fsj;
1018 usb1_vol.fsj = NULL;
1028 uint32_t
efs_rename (
const char *filename, IOB *fcb) {
return (
false); }
1029 uint32_t
efs_create (
const char *fname, IOB *fcb) {
return (
false); }
1035 uint32_t
efs_read (IOB *fcb, uint8_t *buf, uint32_t len) {
return (0); }
1036 uint32_t
efs_write (IOB *fcb,
const uint8_t *buf, uint32_t len){
return (
false); }
1038 uint32_t
efs_seek (IOB *fcb, uint32_t pos) {
return (
false); }
1040 uint32_t
efs_find (
const char *name, IOB *fcb) {
return (
false); }
1049 uint32_t
fat_find (
const char *fn, IOB *fcb) {
return (
false); }
1050 uint32_t
fat_seek (IOB *fcb, uint32_t pos) {
return (
false); }
1051 uint32_t
fat_read (IOB *fcb, uint8_t *buf, uint32_t len) {
return (0); }
1052 uint32_t
fat_write (IOB *fcb,
const uint8_t *buf, uint32_t len){
return (
false); }
1054 uint32_t
fat_delete (
const char *fn, IOB *fcb) {
return (
false); }
1056 uint32_t
fat_rename (
const char *old,
const char *newn, IOB *fcb) {
1058 uint32_t
fat_create (
const char *fn, IOB *fcb) {
return (
false); }
1059 uint32_t
fat_format (FAT_VI *vi,
const char *param) {
return (
false); }
1065 uint32_t
fat_attrib (IOB *fcb,
const char *fn, uint32_t attrib) {
1071 uint32_t fat_jour_prep (FAT_VI *vi) {
return (
true); }
1072 uint32_t fsj_set_space (FSJOUR *fsj, uint32_t start_sect, uint32_t cnt) {
1074 uint32_t fsj_write (FSJOUR *fsj, uint32_t sect, uint32_t cnt, uint8_t *buf) {
1076 uint32_t fsj_init (FSJOUR *fsj, FAT_DRV *drv) {
return (
false); }
1078 #if (FAT_NAME_CACNT == 0)
1079 uint32_t elink_init (
void) {
return (1); }
1080 uint32_t elink_init_path (
const char *drvLet) {
return (0xFF); }
1081 uint32_t elink_flush (
const char *drvLet) {
return (1); }
1082 void *elink_alloc (uint32_t i) {
return (NULL); }
1083 uint32_t elink_cmd (uint32_t i, uint32_t j) {
return (0); }
1084 void *elink_set (uint32_t i, uint32_t j) {
return (NULL); }
1085 uint32_t elink_prop (
void *p, uint32_t i) {
return (0); }
1086 uint32_t elink_insert (
void *p, uint32_t i, uint32_t j) {
return (1); }
1087 uint32_t elink_delete (
void *p, uint32_t i) {
return (0); }
1088 uint32_t elink_scan (uint32_t i,
void **pp, uint32_t j) {
return (1); }
1097 #pragma import(__use_no_semihosting_swi)
1099 #ifndef STDIO_DISABLE
1102 #define STDIN 0x8001
1103 #define STDOUT 0x8002
1104 #define STDERR 0x8003
1111 #if (__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
1137 #ifndef STDIO_DISABLE
1138 #ifndef STDOUT_LF_CR_DISABLE
1163 #ifndef STDIO_DISABLE
1164 if (strcmp(name,
"STDIN") == 0) {
1167 if (strcmp(name,
"STDOUT") == 0) {
1170 if (strcmp(name,
"STDERR") == 0) {
1174 return (__sys_open (name, openmode));
1190 #ifndef STDIO_DISABLE
1198 return (__sys_close (fh));
1220 int _sys_write (FILEHANDLE fh,
const uint8_t *buf, uint32_t len,
int mode) {
1221 #ifndef STDIO_DISABLE
1227 for ( ; len; len--) {
1229 #ifndef STDOUT_LF_CR_DISABLE
1240 return (__sys_write (fh, buf, len));
1271 int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len,
int mode) {
1272 #ifndef STDIO_DISABLE
1281 *buf++ = (uint8_t)ch;
1283 for ( ; len; len--) {
1286 *buf++ = (uint8_t)ch;
1294 return (__sys_read (fh, buf, len));
1314 #ifndef STDIO_DISABLE
1341 #ifndef STDIO_DISABLE
1349 return (__sys_seek (fh, pos));
1359 #ifndef STDIO_DISABLE
1367 return (__sys_ensure (fh));
1387 #ifndef STDIO_DISABLE
1395 return (__sys_flen (fh));