File System Component  Version 5.0
MDK-Professional Middleware for Devices with Flash File System
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fs_config.h
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1 /*------------------------------------------------------------------------------
2  * MDK Middleware - Component ::File System
3  * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
4  *------------------------------------------------------------------------------
5  * Name: fs_config.h
6  * Purpose: File System Library Configuration
7  * Rev.: V5.05
8  *----------------------------------------------------------------------------*/
9 
10 #include <absacc.h>
11 #include <string.h>
12 #include <rt_sys.h>
13 #include "rl_fs_lib.h"
14 
15 #pragma thumb
16 #pragma O3
17 
18 /*-----------------------------------------------------------------------------
19  * File System Configuration File
20  *----------------------------------------------------------------------------*/
21 
22 #ifdef __MICROLIB
23  #error "File System does not work with MicroLIB"
24 #endif
25 
26 /* ---------------------------------------------------------------------------*/
27 
28 #ifndef NOR0_ENABLE
29  #define NOR0_ENABLE 0
30  #define NOR0_DEFAULT_DRIVE 0
31 #endif
32 
33 #ifndef NOR1_ENABLE
34  #define NOR1_ENABLE 0
35  #define NOR1_DEFAULT_DRIVE 0
36 #endif
37 
38 #ifndef RAM0_ENABLE
39  #define RAM0_ENABLE 0
40  #define RAM0_DEFAULT_DRIVE 0
41 #endif
42 
43 /* If MC0 drive not defined */
44 #ifndef MC0_ENABLE
45  #define MC0_ENABLE 0
46  #define MC0_DEFAULT_DRIVE 0
47 #endif
48 
49 /* If MC1 drive not defined */
50 #ifndef MC1_ENABLE
51  #define MC1_ENABLE 0
52  #define MC1_DEFAULT_DRIVE 0
53 #endif
54 
55 /* If NAND0 drive not defined */
56 #ifndef NAND0_ENABLE
57  #define NAND0_ENABLE 0
58  #define NAND0_DEFAULT_DRIVE 0
59 #endif
60 
61 /* If NAND1 drive not defined */
62 #ifndef NAND1_ENABLE
63  #define NAND1_ENABLE 0
64  #define NAND1_DEFAULT_DRIVE 0
65 #endif
66 
67 /* If USB0 drive not defined */
68 #ifndef USB0_ENABLE
69  #define USB0_ENABLE 0
70  #define USB0_DEFAULT_DRIVE 0
71 #endif
72 
73 /* If USB1 drive not defined */
74 #ifndef USB1_ENABLE
75  #define USB1_ENABLE 0
76  #define USB1_DEFAULT_DRIVE 0
77 #endif
78 
79 /* FS_Config V5.00 compatibility */
80 #ifndef FAT_MAX_OPEN_FILES
81  #define FAT_MAX_OPEN_FILES NUM_FILES
82 #endif
83 #ifndef EFS_MAX_OPEN_FILES
84  #define EFS_MAX_OPEN_FILES NUM_FILES
85 #endif
86 
87 /* ---------------------------------------------------------------------------*/
88 
89 /* Check number of enabled drives */
90 #define FS_NDRV (NOR0_ENABLE + NOR1_ENABLE + \
91  RAM0_ENABLE + \
92  MC0_ENABLE + MC1_ENABLE + \
93  USB0_ENABLE + USB1_ENABLE + \
94  NAND0_ENABLE + NAND1_ENABLE)
95 #if (FS_NDRV == 0)
96  #error "No drive enabled, File System requires at least on component ::File System:Drive"
97 #endif
98 
99 /* Count number of enabled FAT drives */
100 #define FS_FAT_NDRV (RAM0_ENABLE + \
101  MC0_ENABLE + MC1_ENABLE + \
102  USB0_ENABLE + USB1_ENABLE + \
103  NAND0_ENABLE + NAND1_ENABLE)
104 
105 /* Count number of enabled NAND devices */
106 #define FS_NAND_NDRV (NAND0_ENABLE + NAND1_ENABLE)
107 
108 /* Check Default drive settings */
109 #define __DEF ((NOR0_DEFAULT_DRIVE & NOR0_ENABLE) + \
110  (NOR1_DEFAULT_DRIVE & NOR1_ENABLE) + \
111  (RAM0_DEFAULT_DRIVE & RAM0_ENABLE) + \
112  (MC0_DEFAULT_DRIVE & MC0_ENABLE) + \
113  (MC1_DEFAULT_DRIVE & MC1_ENABLE) + \
114  (USB0_DEFAULT_DRIVE & USB0_ENABLE) + \
115  (USB1_DEFAULT_DRIVE & USB1_ENABLE) + \
116  (NAND0_DEFAULT_DRIVE & NAND0_ENABLE) + \
117  (NAND1_DEFAULT_DRIVE & NAND1_ENABLE))
118 #if (__DEF == 0)
119  #error "Default ::File System:Drive not specified"
120 #elif (__DEF > 1)
121  #error "Multiple default ::File System:Drive: enabled"
122 #endif
123 
124 /* Check MCI port consistency */
125 #if (MC0_ENABLE && MC1_ENABLE)
126  #if (MC0_MCI_DRIVER == MC1_MCI_DRIVER)
127  #error "::File System:Drive:Memory Card: MCI ports for different drives must be different"
128  #endif
129 #endif
130 
131 /* Check FS usage */
132 #define EFS_USE (NOR0_ENABLE + NOR1_ENABLE)
133 #define FAT_USE (RAM0_ENABLE + MC0_ENABLE + MC1_ENABLE + USB0_ENABLE + USB1_ENABLE + NAND0_ENABLE + NAND1_ENABLE)
134 
135 /* Check journal usage */
136 #define FSJ_USE (MC0_ENABLE * MC0_FAT_JOURNAL + \
137  MC1_ENABLE * MC1_FAT_JOURNAL + \
138  USB0_ENABLE * USB0_FAT_JOURNAL + \
139  USB1_ENABLE * USB1_FAT_JOURNAL + \
140  NAND0_ENABLE * NAND0_FAT_JOURNAL + \
141  NAND1_ENABLE * NAND1_FAT_JOURNAL)
142 
143 /* Reserved sector count */
144 #define FAT_SECT_RSVD 64
145 
146 /* Make sure to resolve a weak stdlib symbol. */
147 #ifdef __RTX
148 extern volatile int _stream_list_lock;
149  #define STREAM_LIST_LOCK _stream_list_lock;
150 #else
151  #define STREAM_LIST_LOCK
152 #endif
153 
154 /* File Control Blocks for the FAT File System */
155 #define FAT_HANDLE_COUNT ((FAT_MAX_OPEN_FILES > 0) ? FAT_MAX_OPEN_FILES : 1)
158 
159 /* File Control Blocks for the Embedded File System */
160 #define EFS_HANDLE_COUNT ((EFS_MAX_OPEN_FILES > 0) ? EFS_MAX_OPEN_FILES : 1)
163 
164 /* Number of enabled drives */
165 uint8_t const _NDRV = FS_NDRV;
166 
167 /*----------------------------------------------------------------------------
168  * FAT Name Cache definition and configuration
169  *---------------------------------------------------------------------------*/
170 #if (FAT_NAME_CACHE_SIZE == 0)
171  FAT_NCACHE_CFG fat_ncache = {
172  0, 0, 0, NULL
173  };
174 #else
175  #if (FAT_NAME_CACHE_RELOC == 1)
176  #define __AT_FAT_NAME __at(FAT_NAME_CACHE_ADDR)
177  #else
178  #define __AT_FAT_NAME
179  #endif
180 
181  /* FAT name cache max folder depth */
182  #define FAT_NAME_MAX_DEPTH 8
183 
184  /* FAT name cache control block size and count */
185  #define FAT_NAME_CB_SZ (16)
186  #define FAT_NAME_CB_POOL_SZ (FAT_NAME_CB_SZ * FS_FAT_NDRV)
187 
188  /* FAT name cache folder depth control block size */
189  #define FAT_NAME_DEPTH_CB_SZ (8)
190  #define FAT_NAME_DEPTH_POOL_SZ (FAT_NAME_DEPTH_CB_SZ * FAT_NAME_MAX_DEPTH * FS_FAT_NDRV)
191 
192  /* FAT name cache pool size */
193  #define FAT_NAME_LINK_SZ (48)
194  #define FAT_NAME_LINK_POOL_SZ (FAT_NAME_LINK_SZ * FAT_NAME_CACHE_SIZE)
195 
196  /* FAT name cache buffer size in bytes */
197  #define FAT_NAME_POOL_SIZE (FAT_NAME_CB_POOL_SZ + \
198  FAT_NAME_DEPTH_POOL_SZ + \
199  FAT_NAME_LINK_POOL_SZ)
200 
201  static uint32_t fat_name_pool[FAT_NAME_POOL_SIZE/4] __AT_FAT_NAME;
202 
203  FAT_NCACHE_CFG fat_ncache = {
204  FAT_NAME_MAX_DEPTH,
205  FS_FAT_NDRV,
206  FAT_NAME_POOL_SIZE,
207  fat_name_pool
208  };
209 #endif /* FAT_NAME_CACNT */
210 
211 #define EXPAND_SYMBOL(name, port) name##port
212 #define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
213 
214 /*----------------------------------------------------------------------------
215  * Drive F0: NOR Flash device NOR0 configuration
216  *---------------------------------------------------------------------------*/
217 #if (NOR0_ENABLE)
218  static fsEFS_Volume nor0_vol;
219 
220  extern ARM_DRIVER_NOR CREATE_SYMBOL (Driver_NOR_, NOR0_NAME);
221  extern ARM_NOR_DEVICE CREATE_SYMBOL (NOR_Device_, NOR0_NAME);
222 
223  #if (NOR0_SPI)
224  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, NOR0_SPI_DRIVER);
225  ARM_DRIVER_SPI *CREATE_SYMBOL (NOR_SPI_Driver_, NOR0_NAME) = &CREATE_SYMBOL (Driver_SPI, NOR0_SPI_DRIVER);
226  #endif
227 #endif
228 
229 /*----------------------------------------------------------------------------
230  * Drive F1: NOR Flash device NOR1 configuration
231  *---------------------------------------------------------------------------*/
232 #if (NOR1_ENABLE)
233  static fsEFS_Volume nor1_vol;
234 
235  extern ARM_DRIVER_NOR CREATE_SYMBOL (Driver_NOR_, NOR1_NAME);
236  extern ARM_NOR_DEVICE CREATE_SYMBOL (NOR_Device_, NOR1_NAME);
237 
238  #if (NOR1_SPI)
239  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, NOR1_SPI_DRIVER);
240  ARM_DRIVER_SPI *CREATE_SYMBOL (NOR_SPI_Driver_, NOR1_NAME) = &CREATE_SYMBOL (Driver_SPI, NOR1_SPI_DRIVER);
241  #endif
242 #endif
243 
244 /*----------------------------------------------------------------------------
245  * Drive M0: Memory Card device MC0 configuration
246  *---------------------------------------------------------------------------*/
247 #if (MC0_ENABLE)
248  static fsFAT_Volume mc0_vol;
249  static MCI_DEV mc0_dev;
250 
251  #if (MC0_FAT_JOURNAL)
252  static FSJOUR mc0_fsj;
253  #endif
254 
255  extern ARM_DRIVER_MCI CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
256 
257  #if (MC0_CACHE_RELOC == 1)
258  #define __AT_MC0 __at(MC0_CACHE_ADDR)
259  #else
260  #define __AT_MC0
261  #endif
262 
263  /* MC0 Cache Buffer for Data and FAT Caching */
264  static uint32_t mc0_cache[(MC0_CACHE_SIZE+1) * 256 + MC0_FAT_JOURNAL * 128] __AT_MC0;
265 
266  #if (MC0_SPI == 0)
267  /* SD Native bus mode */
268  #define MC0_INIT(m) mc_mci_Init (m, &mc0_dev)
269  #define MC0_UNINIT(m) mc_mci_UnInit (m, &mc0_dev)
270  #define MC0_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc0_dev)
271  #define MC0_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc0_dev)
272  #define MC0_RDINFO(i) mc_mci_ReadInfo (i, &mc0_dev)
273  #define MC0_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc0_dev)
274  #else
275  /* SPI bus mode */
276  #define MC0_INIT(m) mc_spi_Init (m, &mc0_dev)
277  #define MC0_UNINIT(m) mc_spi_UnInit (m, &mc0_dev)
278  #define MC0_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc0_dev)
279  #define MC0_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc0_dev)
280  #define MC0_RDINFO(i) mc_spi_ReadInfo (i, &mc0_dev)
281  #define MC0_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc0_dev)
282 
283  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
284  #endif
285 
286  /* MC0 wrapper functions */
287  static uint32_t mc0_Init (uint32_t mode) {
288  return (MC0_INIT (mode));
289  }
290  static uint32_t mc0_UnInit (uint32_t mode) {
291  return (MC0_UNINIT (mode));
292  }
293  static uint32_t mc0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
294  return (MC0_RDSEC (sect, buf, cnt));
295  }
296  static uint32_t mc0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
297  return (MC0_WRSEC (sect, buf, cnt));
298  }
299  static uint32_t mc0_RdInfo (fsMediaInfo *info) {
300  return (MC0_RDINFO (info));
301  }
302  static fsStatus mc0_DevCtrl (fsDevCtrlCode code, void *p) {
303  return (MC0_DEVCTRL (code, p));
304  }
305 
306  /* MC0 FAT device driver */
307  FAT_DRV mc0_drv = {
308  mc0_Init,
309  mc0_UnInit,
310  mc0_RdSect,
311  mc0_WrSect,
312  mc0_RdInfo,
313  mc0_DevCtrl
314  };
315 
316  /* ------- MC0 MCI/SPI Callback ------- */
317  static void MC0_MCI_SignalEvent (ARM_MCI_EVENT event) {
318  mc_mci_DrvEvent (event, &mc0_dev);
319  }
320  #if (MC0_SPI != 0)
321  static void MC0_SPI_SignalEvent (ARM_SPI_EVENT event) {
322  mc_spi_DrvEvent (event, &mc0_dev);
323  }
324  #endif
325 #endif
326 
327 /*----------------------------------------------------------------------------
328  * Drive M1: Memory Card device MC1 configuration
329  *---------------------------------------------------------------------------*/
330 #if (MC1_ENABLE)
331  static fsFAT_Volume mc1_vol;
332  static MCI_DEV mc1_dev;
333 
334  #if (MC1_FAT_JOURNAL)
335  static FSJOUR mc1_fsj;
336  #endif
337 
338  extern ARM_DRIVER_MCI CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
339 
340  #if (MC1_CACHE_RELOC == 1)
341  #define __AT_MC1 __at(MC1_CACHE_ADDR)
342  #else
343  #define __AT_MC1
344  #endif
345 
346  /* MC1 Cache Buffer for Data and FAT Caching */
347  static uint32_t mc1_cache[(MC1_CACHE_SIZE+1) * 256 + MC1_FAT_JOURNAL * 128] __AT_MC1;
348 
349  #if (MC1_SPI == 0)
350  /* SD Native bus mode */
351  #define MC1_INIT(m) mc_mci_Init (m, &mc1_dev)
352  #define MC1_UNINIT(m) mc_mci_UnInit (m, &mc1_dev)
353  #define MC1_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc1_dev)
354  #define MC1_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc1_dev)
355  #define MC1_RDINFO(i) mc_mci_ReadInfo (i, &mc1_dev)
356  #define MC1_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc1_dev)
357  #else
358  /* SPI bus mode */
359  #define MC1_INIT(m) mc_spi_Init (m, &mc1_dev)
360  #define MC1_UNINIT(m) mc_spi_UnInit (m, &mc1_dev)
361  #define MC1_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc1_dev)
362  #define MC1_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc1_dev)
363  #define MC1_RDINFO(i) mc_spi_ReadInfo (i, &mc1_dev)
364  #define MC1_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc1_dev)
365 
366  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
367  #endif
368 
369  /* MC1 wrapper functions */
370  static uint32_t mc1_Init (uint32_t mode) {
371  return (MC1_INIT (mode));
372  }
373  static uint32_t mc1_UnInit (uint32_t mode) {
374  return (MC1_UNINIT (mode));
375  }
376  static uint32_t mc1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
377  return (MC1_RDSEC (sect, buf, cnt));
378  }
379  static uint32_t mc1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
380  return (MC1_WRSEC (sect, buf, cnt));
381  }
382  static uint32_t mc1_RdInfo (fsMediaInfo *info) {
383  return (MC1_RDINFO (info));
384  }
385  static fsStatus mc1_DevCtrl (fsDevCtrlCode code, void *p) {
386  return (MC1_DEVCTRL (code, p));
387  }
388 
389  /* MC1 FAT device driver */
390  FAT_DRV mc1_drv = {
391  mc1_Init,
392  mc1_UnInit,
393  mc1_RdSect,
394  mc1_WrSect,
395  mc1_RdInfo,
396  mc1_DevCtrl
397  };
398 
399  /* ------- MC1 MCI/SPI Callback ------- */
400  static void MC1_MCI_SignalEvent (ARM_MCI_EVENT event) {
401  mc_mci_DrvEvent (event, &mc1_dev);
402  }
403  #if (MC1_SPI != 0)
404  static void MC1_SPI_SignalEvent (ARM_SPI_EVENT event) {
405  mc_spi_DrvEvent (event, &mc1_dev);
406  }
407  #endif
408 #endif
409 
410 /*----------------------------------------------------------------------------
411  * General NAND Flash device configuration
412  *---------------------------------------------------------------------------*/
413 #ifdef RTE_FileSystem_Drive_NAND_0
414  #if (NAND0_ENABLE)
415  #define NAND_INFO_0_DEV_0
416 
417  #if ((NAND1_ENABLE) && (NAND1_DRIVER == NAND0_DRIVER))
418  #if (NAND1_DEV_NUM == NAND0_DEV_NUM)
419  #error "::File System:Drive:NAND: NAND ports for different drives must be different"
420  #endif
421  #define NAND_INFO_0_DEV_1
422  #endif
423  #endif
424 #endif
425 
426 #ifdef RTE_FileSystem_Drive_NAND_1
427  #if (((NAND0_ENABLE == 0) && NAND1_ENABLE) || ((NAND0_ENABLE && NAND1_ENABLE) && (NAND1_DRIVER != NAND0_DRIVER)))
428  #define NAND_INFO_1_DEV_0
429  #endif
430 #endif
431 
432 #if (NAND0_ENABLE)
433  static fsFAT_Volume nand0_vol;
434  static NAND_FTL_DEV nand0_dev;
435 
436  #if (NAND0_FAT_JOURNAL)
437  static FSJOUR nand0_fsj;
438  #endif
439 
440  extern ARM_DRIVER_NAND CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
441 #endif
442 
443 #if (NAND1_ENABLE)
444  static fsFAT_Volume nand1_vol;
445  static NAND_FTL_DEV nand1_dev;
446 
447  #if (NAND1_FAT_JOURNAL)
448  static FSJOUR nand1_fsj;
449  #endif
450 
451  #if defined(NAND_INFO_1_DEV_0)
452  extern ARM_DRIVER_NAND CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
453  #endif
454 #endif
455 
456 #if defined(NAND_INFO_0_DEV_0)
457  #define NAND0_EVENT_HANDLER NAND_SignalEventHandler0
458  #if defined(NAND_INFO_0_DEV_1)
459  #define NAND1_EVENT_HANDLER NAND_SignalEventHandler0
460  #endif
461 
462  void NAND_SignalEventHandler0 (uint32_t dev_num) {
463  switch (dev_num) {
464  case NAND0_DEV_NUM: ftl_DrvEvent (&nand0_dev); break;
465 
466  #if defined(NAND_INFO_0_DEV_1)
467  case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev); break;
468  #endif
469 
470  default: return;
471  }
472  }
473 
474  ARM_NAND_DEVICE NAND_DevInfo0[] = {
475  {&nand0_dev.PgLay,
476  NAND0_TYPE,
477  NAND0_DEV_NUM,
478  NAND0_PAGE_SIZE,
479  NAND0_BLOCK_COUNT,
480  NAND0_PAGE_COUNT,
481  NAND_SEC_BLOCK (NAND0_PAGE_COUNT, NAND0_PAGE_SIZE),
482  NAND_SEC_PAGE (NAND0_PAGE_SIZE),
483  NAND_ROW_CYCLES (NAND0_BLOCK_COUNT, NAND0_PAGE_COUNT),
484  NAND_COL_CYCLES (NAND0_PAGE_SIZE),
485  NAND0_SW_ECC
486  },
487  #if defined(NAND_INFO_0_DEV_1)
488  {&nand1_dev.PgLay,
489  NAND1_TYPE,
490  NAND1_DEV_NUM,
491  NAND1_PAGE_SIZE,
492  NAND1_BLOCK_COUNT,
493  NAND1_PAGE_COUNT,
494  NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
495  NAND_SEC_PAGE (NAND1_PAGE_SIZE),
496  NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
497  NAND_COL_CYCLES (NAND1_PAGE_SIZE),
498  NAND1_SW_ECC
499  },
500  #endif
501  };
502  #define NAND_INFO0 NAND_DevInfo0
503  #define NAND_INFO0_SZ (sizeof(NAND_DevInfo0) / sizeof(NAND_DevInfo0[0]))
504 #else
505  #define NAND_INFO0 NULL
506  #define NAND_INFO0_SZ 0
507 #endif
508 
509 #if defined(NAND_INFO_1_DEV_0)
510  #define NAND1_EVENT_HANDLER NAND_SignalEventHandler1
511 
512  void NAND_SignalEventHandler1 (uint32_t dev_num) {
513  switch (dev_num) {
514  case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev); break;
515 
516  default: return;
517  }
518  }
519 
520  ARM_NAND_DEVICE NAND_DevInfo1[] = {
521  {&nand1_dev.PgLay,
522  NAND1_TYPE,
523  NAND1_DEV_NUM,
524  NAND1_PAGE_SIZE,
525  NAND1_BLOCK_COUNT,
526  NAND1_PAGE_COUNT,
527  NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
528  NAND_SEC_PAGE (NAND1_PAGE_SIZE),
529  NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
530  NAND_COL_CYCLES (NAND1_PAGE_SIZE),
531  NAND1_SW_ECC
532  },
533  };
534  #define NAND_INFO1 NAND_DevInfo1
535  #define NAND_INFO1_SZ (sizeof(NAND_DevInfo1) / sizeof(NAND_DevInfo1[0]))
536 #else
537  #define NAND_INFO1 NULL
538  #define NAND_INFO1_SZ 0
539 #endif
540 
541 /*----------------------------------------------------------------------------
542  * Drive N0: NAND Flash device NAND0 configuration
543  *---------------------------------------------------------------------------*/
544 #if (NAND0_ENABLE)
545  #if (NAND0_CACHE_RELOC == 1)
546  #define __AT_NAND0 __at(NAND0_CACHE_ADDR)
547  #else
548  #define __AT_NAND0
549  #endif
550 
551  /* NAND Cache Buffer for FAT, Page and Block Caching */
552  #define NAND0_CSZ ((NAND0_CACHE_SIZE + 1) * 1024 + \
553  (NAND0_PAGE_CACHE + 2) * NAND0_PAGE_SIZE + \
554  (NAND0_BLOCK_CACHE + 2) * NAND0_PAGE_COUNT)
555  #define NAND0_FSJBUF (NAND0_FAT_JOURNAL * 512)
556 
557  static uint32_t nand0_cache[NAND0_CSZ/4 + NAND0_FSJBUF/4] __AT_NAND0;
558  static PAGE_CACHE nand0_capg [NAND0_PAGE_CACHE + 1];
559  static BLOCK_CACHE nand0_cabl [NAND0_BLOCK_CACHE + 2];
560  static uint32_t nand0_ttsn [NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE)];
561 
562  /* NAND Flash Configuration */
563  static NAND_FTL_CFG nand0_cfg = {
564  /* Block Translation Table Space */
565  1,
566  NAND_BTT_SIZE (NAND0_BLOCK_COUNT),
567 
568  /* Data Space */
569  NAND_BTT_SIZE (NAND0_BLOCK_COUNT) + 1,
570  NAND0_BLOCK_COUNT - 1,
571 
572  /* Caching */
573  NAND0_BLOCK_CACHE + 2,
574  NAND0_PAGE_CACHE + 1,
575  NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE),
576 
577  /* Page buffer & Caches */
578  (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256],
579  &nand0_cabl[0],
580  (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+(NAND0_PAGE_CACHE+2)*NAND0_PAGE_SIZE/4],
581  &nand0_capg[0],
582  (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+NAND0_PAGE_SIZE/4],
583  &nand0_ttsn[0]
584  };
585 
586  /* NAND0 wrapper functions */
587  static uint32_t nand0_Init (uint32_t mode) {
588  return (ftl_Init (mode, &nand0_dev, NAND_INFO0, NAND_INFO0_SZ));
589  }
590  static uint32_t nand0_UnInit (uint32_t mode) {
591  return (ftl_UnInit (mode, &nand0_dev));
592  }
593  static uint32_t nand0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
594  uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand0_dev);
595  if (retv < 2) return (true);
596  else return (false);
597  }
598  static uint32_t nand0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
599  uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand0_dev);
600  if (retv < 2) return (true);
601  else return (false);
602  }
603  static uint32_t nand0_RdInfo (fsMediaInfo *info) {
604  return (ftl_ReadInfo (info, &nand0_dev));
605  }
606  static fsStatus nand0_DevCtrl (fsDevCtrlCode code, void *p) {
607  return (ftl_DevCtrl (code, p, &nand0_dev));
608  }
609 
610  FAT_DRV nand0_drv = {
611  nand0_Init,
612  nand0_UnInit,
613  nand0_RdSect,
614  nand0_WrSect,
615  nand0_RdInfo,
616  nand0_DevCtrl
617  };
618 #endif
619 
620 /*----------------------------------------------------------------------------
621  * Drive N1: NAND Flash device NAND1 configuration
622  *---------------------------------------------------------------------------*/
623 #if (NAND1_ENABLE)
624  #if (NAND1_CACHE_RELOC == 1)
625  #define __AT_NAND1 __at(NAND1_CACHE_ADDR)
626  #else
627  #define __AT_NAND1
628  #endif
629 
630  /* NAND Cache Buffer for FAT, Page and Block Caching */
631  #define NAND1_CSZ ((NAND1_CACHE_SIZE + 1) * 1024 + \
632  (NAND1_PAGE_CACHE + 2) * NAND1_PAGE_SIZE + \
633  (NAND1_BLOCK_CACHE + 2) * NAND1_PAGE_COUNT)
634  #define NAND1_FSJBUF (NAND1_FAT_JOURNAL * 512)
635 
636  static uint32_t nand1_cache[NAND1_CSZ/4 + NAND1_FSJBUF/4] __AT_NAND1;
637  static PAGE_CACHE nand1_capg [NAND1_PAGE_CACHE + 1];
638  static BLOCK_CACHE nand1_cabl [NAND1_BLOCK_CACHE + 2];
639  static uint32_t nand1_ttsn [NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE)];
640 
641  /* NAND Flash Configuration */
642  static NAND_FTL_CFG nand1_cfg = {
643  /* Block Translation Table Space */
644  1,
645  NAND_BTT_SIZE (NAND1_BLOCK_COUNT),
646 
647  /* Data Space */
648  NAND_BTT_SIZE (NAND1_BLOCK_COUNT) + 1,
649  NAND1_BLOCK_COUNT - 1,
650 
651  /* Caching */
652  NAND1_BLOCK_CACHE + 2,
653  NAND1_PAGE_CACHE + 1,
654  NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE),
655 
656  /* Page buffer & Caches */
657  (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256],
658  &nand1_cabl[0],
659  (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+(NAND1_PAGE_CACHE+2)*NAND1_PAGE_SIZE/4],
660  &nand1_capg[0],
661  (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+NAND1_PAGE_SIZE/4],
662  &nand1_ttsn[0],
663  };
664 
665  /* NAND1 wrapper functions */
666  static uint32_t nand1_Init (uint32_t mode) {
667  return (ftl_Init(mode, &nand1_dev, NAND_INFO1, NAND_INFO1_SZ));
668  }
669  static uint32_t nand1_UnInit (uint32_t mode) {
670  return (ftl_UnInit (mode, &nand1_dev));
671  }
672  static uint32_t nand1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
673  uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand1_dev);
674  if (retv < 2) return (true);
675  else return (false);
676  }
677  static uint32_t nand1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
678  uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand1_dev);
679  if (retv < 2) return (true);
680  else return (false);
681  }
682  static uint32_t nand1_RdInfo (fsMediaInfo *info) {
683  return (ftl_ReadInfo (info, &nand1_dev));
684  }
685  static fsStatus nand1_DevCtrl (fsDevCtrlCode code, void *p) {
686  return (ftl_DevCtrl (code, p, &nand1_dev));
687  }
688 
689  FAT_DRV nand1_drv = {
690  nand1_Init,
691  nand1_UnInit,
692  nand1_RdSect,
693  nand1_WrSect,
694  nand1_RdInfo,
695  nand1_DevCtrl
696  };
697 #endif
698 
699 /*----------------------------------------------------------------------------
700  * Drive R0: RAM device RAM0 configuration
701  *---------------------------------------------------------------------------*/
702 #if (RAM0_ENABLE)
703  static fsFAT_Volume ram0_vol;
704 
705  #if (RAM0_SIZE < 0x4A00)
706  #error "::File System:Drive:RAM requires minimum of 0x4A00 bytes of memory"
707  #endif
708 
709  #if (RAM0_RELOC == 1)
710  #define __AT_RAM0 __at(RAM0_BASE_ADDR)
711  #else
712  #define __AT_RAM0
713  #endif
714 
715  /* RAM0 Device data buffer */
716  static uint32_t ram0_buf[256 + (RAM0_SIZE/4)] __AT_RAM0;
717 
718  /* RAM0 device info */
719  static RAM_DEV ram0_dev = {
720  (uint8_t *)&ram0_buf[256],
721  RAM0_SIZE
722  };
723 
724  /* RAM0 wrapper functions */
725  static uint32_t ram0_Init (uint32_t mode) {
726  return (ram_Init (mode, &ram0_dev));
727  }
728  static uint32_t ram0_UnInit (uint32_t mode) {
729  return (ram_UnInit (mode, &ram0_dev));
730  }
731  static uint32_t ram0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
732  return (ram_ReadSector (sect, buf, cnt, &ram0_dev));
733  }
734  static uint32_t ram0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
735  return (ram_WriteSector (sect, buf, cnt, &ram0_dev));
736  }
737  static uint32_t ram0_RdInfo (fsMediaInfo *info) {
738  return (ram_ReadInfo (info, &ram0_dev));
739  }
740  static fsStatus ram0_DevCtrl (fsDevCtrlCode code, void *p) {
741  return (ram_DevCtrl (code, p, &ram0_dev));
742  }
743 
744  /* FAT RAM Driver Control Block */
745  FAT_DRV ram0_drv = {
746  ram0_Init,
747  ram0_UnInit,
748  ram0_RdSect,
749  ram0_WrSect,
750  ram0_RdInfo,
751  ram0_DevCtrl
752  };
753 #endif
754 
755 /*----------------------------------------------------------------------------
756  * Drive U0: USB Flash device USB0 configuration
757  *---------------------------------------------------------------------------*/
758 #if (USB0_ENABLE)
759  extern FAT_DRV usb0_drv;
760 
761  #if (USB0_FAT_JOURNAL)
762  static FSJOUR usb0_fsj;
763  #endif
764 
765  /* USB Cache Buffer for Data and FAT Caching */
766  static uint32_t usb0_cache[(USB0_CACHE_SIZE+1) * 256 + USB0_FAT_JOURNAL * 128];
767  static fsFAT_Volume usb0_vol;
768 
769  /* USB0 wrapper functions */
770  static uint32_t usb0_Init (uint32_t mode) {
771  return (FS_USBH_MSC_Initialize (0, mode));
772  }
773  static uint32_t usb0_UnInit (uint32_t mode) {
774  return (FS_USBH_MSC_Uninitialize (0, mode));
775  }
776  static uint32_t usb0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
777  return (FS_USBH_MSC_ReadSectors (0, sect, cnt, buf));
778  }
779  static uint32_t usb0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
780  return (FS_USBH_MSC_WriteSectors (0, sect, cnt, buf));
781  }
782  static uint32_t usb0_RdInfo (fsMediaInfo *info) {
783  return (FS_USBH_MSC_ReadInfo (0, info));
784  }
785  static fsStatus usb0_DevCtrl (fsDevCtrlCode code, void *p) {
786  return (FS_USBH_MSC_DeviceCtrl (0, code, p));
787  }
788 
789  FAT_DRV usb0_drv = {
790  usb0_Init,
791  usb0_UnInit,
792  usb0_RdSect,
793  usb0_WrSect,
794  usb0_RdInfo,
795  usb0_DevCtrl
796  };
797 #endif
798 
799 /*----------------------------------------------------------------------------
800  * Drive U1: USB Flash device USB1 configuration
801  *---------------------------------------------------------------------------*/
802 #if (USB1_ENABLE)
803  extern FAT_DRV usb1_drv;
804 
805  #if (USB1_FAT_JOURNAL)
806  static FSJOUR usb1_fsj;
807  #endif
808 
809  /* USB Cache Buffer for Data and FAT Caching */
810  static uint32_t usb1_cache[(USB1_CACHE_SIZE+1) * 256 + USB1_FAT_JOURNAL * 128];
811  static fsFAT_Volume usb1_vol;
812 
813  /* USB1 wrapper functions */
814  static uint32_t usb1_Init (uint32_t mode) {
815  return (FS_USBH_MSC_Initialize (1, mode));
816  }
817  static uint32_t usb1_UnInit (uint32_t mode) {
818  return (FS_USBH_MSC_Uninitialize (1, mode));
819  }
820  static uint32_t usb1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
821  return (FS_USBH_MSC_ReadSectors (1, sect, cnt, buf));
822  }
823  static uint32_t usb1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
824  return (FS_USBH_MSC_WriteSectors (1, sect, cnt, buf));
825  }
826  static uint32_t usb1_RdInfo (fsMediaInfo *info) {
827  return (FS_USBH_MSC_ReadInfo (1, info));
828  }
829  static fsStatus usb1_DevCtrl (fsDevCtrlCode code, void *p) {
830  return (FS_USBH_MSC_DeviceCtrl (1, code, p));
831  }
832 
833  FAT_DRV usb1_drv = {
834  usb1_Init,
835  usb1_UnInit,
836  usb1_RdSect,
837  usb1_WrSect,
838  usb1_RdInfo,
839  usb1_DevCtrl
840  };
841 #endif
842 
843 
844 /*-----------------------------------------------------------------------------
845  * An array of installed Device drivers
846  *----------------------------------------------------------------------------*/
847 FS_DEV fs_DevPool[FS_NDRV] = {
848 #if (NOR0_ENABLE)
849  { &nor0_vol, "F0", FS_EMB | NOR0_DEFAULT_DRIVE },
850 #endif
851 #if (NOR1_ENABLE)
852  { &nor1_vol, "F1", FS_EMB | NOR1_DEFAULT_DRIVE },
853 #endif
854 #if (MC0_ENABLE)
855  { &mc0_vol, "M0", FS_FAT | MC0_DEFAULT_DRIVE | FS_IOC },
856 #endif
857 #if (MC1_ENABLE)
858  { &mc1_vol, "M1", FS_FAT | MC1_DEFAULT_DRIVE | FS_IOC },
859 #endif
860 #if (NAND0_ENABLE)
861  { &nand0_vol,"N0", FS_FAT | NAND0_DEFAULT_DRIVE | FS_IOC },
862 #endif
863 #if (NAND1_ENABLE)
864  { &nand1_vol,"N1", FS_FAT | NAND1_DEFAULT_DRIVE | FS_IOC },
865 #endif
866 #if (RAM0_ENABLE)
867  { &ram0_vol, "R0", FS_FAT | RAM0_DEFAULT_DRIVE },
868 #endif
869 #if (USB0_ENABLE)
870  { &usb0_vol, "U0", FS_FAT | USB0_DEFAULT_DRIVE },
871 #endif
872 #if (USB1_ENABLE)
873  { &usb1_vol, "U1", FS_FAT | USB1_DEFAULT_DRIVE },
874 #endif
875 };
876 
877 /*-----------------------------------------------------------------------------
878  * Configure Flash File System
879  *----------------------------------------------------------------------------*/
880 void fs_config (void) {
881 
882 #if (NOR0_ENABLE)
883  nor0_vol.Drv = &CREATE_SYMBOL (Driver_NOR_, NOR0_NAME);
884  nor0_vol.BaseAdr = NOR0_BASE_ADDR;
885  nor0_vol.InitVal = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).erased_value * 0x01010101;
886  nor0_vol.NumSect = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_count;
887  nor0_vol.Size = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).size;
888  nor0_vol.DevCfg = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_info;
889 #endif
890 
891 #if (NOR1_ENABLE)
892  nor1_vol.Drv = &CREATE_SYMBOL (Driver_NOR_, NOR1_NAME);
893  nor1_vol.BaseAdr = NOR1_BASE_ADDR;
894  nor1_vol.InitVal = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).erased_value * 0x01010101;
895  nor1_vol.NumSect = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_count;
896  nor1_vol.Size = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).size;
897  nor1_vol.DevCfg = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_info;
898 #endif
899 
900 #if (MC0_ENABLE)
901  mc0_vol.Drv = &mc0_drv;
902  mc0_vol.CaBuf = mc0_cache;
903  mc0_vol.CaSize = MC0_CACHE_SIZE * 2;
904 
905  /* Register MCI driver for Native mode */
906  mc0_dev.DrvMci = &CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
907  mc0_dev.MCI_Callback = MC0_MCI_SignalEvent;
908  #if (MC0_SPI != 0)
909  /* Register SPI driver for SPI mode */
910  mc0_dev.DrvSpi = &CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
911  mc0_dev.SPI_Callback = MC0_SPI_SignalEvent;
912  #endif
913 
914  #if (MC0_FAT_JOURNAL)
915  /* Register file system journal */
916  mc0_fsj.buf = (uint8_t *)&mc0_cache[(MC0_CACHE_SIZE+1) * 256];
917  mc0_vol.fsj = &mc0_fsj;
918  mc0_vol.RsvdS = FAT_SECT_RSVD;
919  #else
920  mc0_vol.fsj = NULL;
921  mc0_vol.RsvdS = 0;
922  #endif
923 #endif
924 
925 #if (MC1_ENABLE)
926  mc1_vol.Drv = &mc1_drv;
927  mc1_vol.CaBuf = mc1_cache;
928  mc1_vol.CaSize = MC1_CACHE_SIZE * 2;
929 
930  /* Register MCI driver for Native mode */
931  mc1_dev.DrvMci = &CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
932  mc1_dev.MCI_Callback = MC1_MCI_SignalEvent;
933  #if (MC1_SPI != 0)
934  /* Register SPI driver for SPI mode */
935  mc1_dev.DrvSpi = &CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
936  mc1_dev.SPI_Callback = MC1_SPI_SignalEvent;
937  #endif
938 
939  #if (MC1_FAT_JOURNAL)
940  /* Register file system journal */
941  mc1_fsj.buf = (uint8_t *)&mc1_cache[(MC1_CACHE_SIZE+1) * 256];
942  mc1_vol.fsj = &mc1_fsj;
943  mc1_vol.RsvdS = FAT_SECT_RSVD;
944  #else
945  mc1_vol.fsj = NULL;
946  mc1_vol.RsvdS = 0;
947  #endif
948 #endif
949 
950 #if (NAND0_ENABLE)
951  nand0_vol.Drv = &nand0_drv;
952  nand0_vol.CaBuf = nand0_cache;
953  nand0_vol.CaSize = NAND0_CACHE_SIZE * 2;
954 
955  nand0_dev.Drv = &CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
956  nand0_dev.Dev = &NAND_DevInfo0[0];
957  nand0_dev.Cfg = &nand0_cfg;
958  nand0_dev.Callback = NAND0_EVENT_HANDLER;
959 
960  #if (NAND0_FAT_JOURNAL)
961  /* Register file system journal */
962  nand0_fsj.buf = (uint8_t *)&nand0_cache[NAND0_CSZ/4];
963  nand0_vol.fsj = &nand0_fsj;
964  nand0_vol.RsvdS = FAT_SECT_RSVD;
965  #else
966  nand0_vol.fsj = NULL;
967  nand0_vol.RsvdS = 0;
968  #endif
969 #endif
970 
971 #if (NAND1_ENABLE)
972  nand1_vol.Drv = &nand1_drv;
973  nand1_vol.CaBuf = nand1_cache;
974  nand1_vol.CaSize = NAND1_CACHE_SIZE * 2;
975 
976  nand1_dev.Drv = &CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
977  #if defined(NAND_INFO_0_DEV_1)
978  nand1_dev.Dev = &NAND_DevInfo0[1];
979  #else
980  nand1_dev.Dev = &NAND_DevInfo1[0];
981  #endif
982  nand1_dev.Cfg = &nand1_cfg;
983  nand1_dev.Callback = NAND1_EVENT_HANDLER;
984 
985  #if (NAND1_FAT_JOURNAL)
986  /* Register file system journal */
987  nand1_fsj.buf = (uint8_t *)&nand1_cache[NAND1_CSZ/4];
988  nand1_vol.fsj = &nand1_fsj;
989  nand1_vol.RsvdS = FAT_SECT_RSVD;
990  #else
991  nand1_vol.fsj = NULL;
992  nand1_vol.RsvdS = 0;
993  #endif
994 #endif
995 
996 #if (RAM0_ENABLE)
997  ram0_vol.Drv = &ram0_drv;
998  ram0_vol.CaBuf = ram0_buf;
999  ram0_vol.CaSize = 0;
1000  ram0_vol.RsvdS = 0;
1001  ram0_vol.fsj = NULL;
1002 #endif
1003 
1004 #if (USB0_ENABLE)
1005  usb0_vol.Drv = &usb0_drv;
1006  usb0_vol.CaBuf = usb0_cache;
1007  usb0_vol.CaSize = USB0_CACHE_SIZE * 2;
1008 
1009  #if (USB0_FAT_JOURNAL)
1010  /* Register file system journal */
1011  usb0_fsj.buf = (uint8_t *)&usb0_cache[(USB0_CACHE_SIZE+1) * 256];
1012  usb0_vol.fsj = &usb0_fsj;
1013  usb0_vol.RsvdS = FAT_SECT_RSVD;
1014  #else
1015  usb0_vol.fsj = NULL;
1016  usb0_vol.RsvdS = 0;
1017  #endif
1018 #endif
1019 
1020 #if (USB1_ENABLE)
1021  usb1_vol.Drv = &usb1_drv;
1022  usb1_vol.CaSize = USB1_CACHE_SIZE * 2;
1023  usb1_vol.CaBuf = usb1_cache;
1024 
1025 
1026  #if (USB1_FAT_JOURNAL)
1027  /* Register file system journal */
1028  usb1_fsj.buf = (uint8_t *)&usb1_cache[(USB1_CACHE_SIZE+1) * 256];
1029  usb1_vol.fsj = &usb1_fsj;
1030  usb1_vol.RsvdS = FAT_SECT_RSVD;
1031  #else
1032  usb1_vol.fsj = NULL;
1033  usb1_vol.RsvdS = 0;
1034  #endif
1035 #endif
1036 
1038 }
1039 
1040 
1041 #if (EFS_USE == 0)
1042  /* Empty functions to reduce image size when EFS not used */
1043  bool efs_path_valid (const char *path) { return (false); }
1044  int32_t efs_handle_get (fsEFS_Volume *vol) { return (-1); }
1045  fsStatus efs_open (int32_t handle, const char *fn, int openmode) { return (fsError); }
1046  fsStatus efs_close (int32_t handle) { return (fsError); }
1047  int32_t efs_read (int32_t handle, uint8_t *buf, uint32_t len) { return (0); }
1048  int32_t efs_write (int32_t handle, const uint8_t *buf, uint32_t len) { return (-1); }
1049  fsStatus efs_flush (int32_t handle) { return (fsError); }
1050  int32_t efs_flen (int32_t handle) { return (-1); }
1051  fsStatus efs_seek (int32_t handle, uint32_t pos) { return (fsError); }
1052  fsStatus efs_ffind (int32_t handle, fsFileInfo *info) { return (fsError); }
1053  fsStatus efs_find (int32_t handle, const char *fname) { return (fsError); }
1054  fsStatus efs_delete(int32_t handle) { return (fsError); }
1055  int32_t efs_analyse(fsEFS_Volume *vol) { return (0); }
1056  fsStatus efs_check (fsEFS_Volume *vol) { return (fsError); }
1057  fsStatus efs_format (fsEFS_Volume *vol) { return (fsError); }
1058  uint32_t efs_free (fsEFS_Volume *vol) { return (0); }
1059  fsStatus efs_defrag (fsEFS_Volume *vol) { return (fsError); }
1060 #endif /* EFS_USE */
1061 
1062 #if (FAT_USE == 0)
1063  /* Empty functions to reduce image size when FAT not used */
1064  int32_t fat_handle_get (fsFAT_Volume *vol) { return (-1); }
1065  fsStatus fat_open (int32_t handle, const char *path, int32_t openmode){ return (fsError); }
1066  fsStatus fat_close(int32_t handle) { return (fsError); }
1067  int32_t fat_read (int32_t handle, uint8_t *buf, uint32_t len) { return(-1); }
1068  int32_t fat_write(int32_t handle, const uint8_t *buf, uint32_t len) { return(-1); }
1069  int32_t fat_flen (int32_t handle) { return (-1); }
1070  fsStatus fat_seek (int32_t handle, uint32_t pos) { return(fsError); }
1071  int32_t fat_init (fsFAT_Volume *vol) { return (0); }
1072  fsStatus fat_ffind (const char *fn, fsFileInfo *info, fsFAT_Volume *vol) { return (fsError); }
1073  fsStatus fat_delete (const char *fn, fsFAT_Volume *vol) { return(fsError); }
1074  fsStatus fat_rename (const char *path, const char *newname, fsFAT_Volume *vol) { return (fsError); }
1075  fsStatus fat_format (fsFAT_Volume *vol, const char *opt) { return (fsError); }
1076  uint64_t fat_free (fsFAT_Volume *vol) { return (0); }
1077  fsStatus fat_attrib (fsFAT_Volume *vol, const char *fn, uint32_t attrib) { return (fsError); }
1078  fsStatus fat_read_label (fsFAT_Volume *vol, char *buf) { return (fsError); }
1079  fsStatus fat_read_serial (fsFAT_Volume *vol, uint32_t *serial) { return (fsError); }
1080  fsStatus fat_mkdir (const char *path, fsFAT_Volume *vol) { return (fsError); }
1081  uint32_t fat_jour_init (fsFAT_Volume *vi) { return (true); }
1082 #else
1083  #if (FSJ_USE == 0)
1084  /* Empty functions to reduce image size when journal not used */
1085  uint32_t fat_jour_init (fsFAT_Volume *vol) { return (true); }
1086  uint32_t fat_jour_prep (fsFAT_Volume *vol) { return (true); }
1087  uint32_t fsj_set_space (FSJOUR *fsj, uint32_t start_sect, uint32_t cnt) {
1088  return (false); }
1089  uint32_t fsj_write (FSJOUR *fsj, uint32_t sect, uint32_t cnt, uint8_t *buf) {
1090  return (false); }
1091  uint32_t fsj_init (FSJOUR *fsj, FAT_DRV *drv) { return (false); }
1092  #endif
1093 #endif /* FAT_USE */
1094 
1095 #if (FAT_NAME_CACHE_SIZE == 0)
1096  uint32_t elink_init (void) { return (1); }
1097  uint32_t elink_init_path (const char *drvLet) { return (0xFF); }
1098  uint32_t elink_flush (const char *drvLet) { return (1); }
1099  uint32_t elink_cmd (uint32_t i, uint32_t j) { return (0); }
1100  uint32_t elink_insert (void *p, uint32_t i, uint32_t j) { return (1); }
1101  uint32_t elink_delete (void *p, uint32_t i) { return (0); }
1102  uint32_t elink_scan (uint32_t i, void **pp, uint32_t j) { return (1); }
1103 #endif
1104 
1105 
1106 /*-----------------------------------------------------------------------------
1107  * Retarget low level functions
1108  *----------------------------------------------------------------------------*/
1109 
1110 #pragma import(__use_no_semihosting_swi)
1111 
1112 #ifndef STDIO_DISABLE
1113 
1114 /* Standard IO device handles. */
1115 #define STDIN 0x8001
1116 #define STDOUT 0x8002
1117 #define STDERR 0x8003
1118 
1119 /* Standard IO device name defines. */
1120 const char __stdin_name[] = "STDIN";
1121 const char __stdout_name[] = "STDOUT";
1122 const char __stderr_name[] = "STDERR";
1123 
1124 #if (__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
1125 /* Redirected to ITM by default */
1126 extern int stdio_getc (void);
1127 extern int stdio_putc (int ch);
1128 #else
1129 /* Dummy implementation */
1130 __weak int stdio_getc (void) { return (-1); }
1131 __weak int stdio_putc (int ch) {}
1132 #endif
1133 
1134 #endif
1135 
1136 
1149 __weak void _ttywrch (int ch) {
1150 #ifndef STDIO_DISABLE
1151 #ifndef STDOUT_LF_CR_DISABLE
1152  if (ch == '\n') stdio_putc ('\r');
1153 #endif
1154  stdio_putc (ch);
1155 #endif
1156 }
1157 
1158 
1174 FILEHANDLE _sys_open (const char *name, int openmode) {
1175  /* Register standard Input Output devices. */
1176 #ifndef STDIO_DISABLE
1177  if (strcmp(name, "STDIN") == 0) {
1178  return (STDIN);
1179  }
1180  if (strcmp(name, "STDOUT") == 0) {
1181  return (STDOUT);
1182  }
1183  if (strcmp(name, "STDERR") == 0) {
1184  return (STDERR);
1185  }
1186 #endif
1187  return (__sys_open (name, openmode));
1188 }
1189 
1190 
1202 int _sys_close (FILEHANDLE fh) {
1203 #ifndef STDIO_DISABLE
1204  switch (fh) {
1205  case STDOUT:
1206  case STDIN:
1207  case STDERR:
1208  return (0);
1209  }
1210 #endif
1211  return (__sys_close (fh));
1212 }
1213 
1214 
1233 int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) {
1234 #ifndef STDIO_DISABLE
1235  int ch;
1236 
1237  switch (fh) {
1238  case STDOUT:
1239  /* Standard Output device. */
1240  for ( ; len; len--) {
1241  ch = *buf++;
1242 #ifndef STDOUT_LF_CR_DISABLE
1243  if (ch == '\n') stdio_putc ('\r');
1244 #endif
1245  stdio_putc (ch);
1246  }
1247  return (0);
1248  case STDIN:
1249  case STDERR:
1250  return (-1);
1251  }
1252 #endif
1253  return (__sys_write (fh, buf, len));
1254 }
1255 
1256 
1284 int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) {
1285 #ifndef STDIO_DISABLE
1286  int ch;
1287 
1288  switch (fh) {
1289  case STDIN:
1290  /* Standard Input device. */
1291  do {
1292  ch = stdio_getc ();
1293  } while (ch < 0);
1294  *buf++ = (uint8_t)ch;
1295  len--;
1296  for ( ; len; len--) {
1297  ch = stdio_getc ();
1298  if (ch < 0) break;
1299  *buf++ = (uint8_t)ch;
1300  }
1301  return (len);
1302  case STDOUT:
1303  case STDERR:
1304  return (-1);
1305  }
1306 #endif
1307  return (__sys_read (fh, buf, len));
1308 }
1309 
1310 
1326 int _sys_istty (FILEHANDLE fh) {
1327 #ifndef STDIO_DISABLE
1328  switch (fh) {
1329  case STDOUT:
1330  case STDIN:
1331  case STDERR:
1332  return (1);
1333  }
1334 #endif
1335  return (0);
1336 }
1337 
1338 
1353 int _sys_seek (FILEHANDLE fh, long pos) {
1354 #ifndef STDIO_DISABLE
1355  switch (fh) {
1356  case STDOUT:
1357  case STDIN:
1358  case STDERR:
1359  return (-1);
1360  }
1361 #endif
1362  return (__sys_seek (fh, pos));
1363 }
1364 
1365 
1371 int _sys_ensure (FILEHANDLE fh) {
1372 #ifndef STDIO_DISABLE
1373  switch (fh) {
1374  case STDOUT:
1375  case STDIN:
1376  case STDERR:
1377  return (-1);
1378  }
1379 #endif
1380  return (__sys_ensure (fh));
1381 }
1382 
1383 
1399 long _sys_flen (FILEHANDLE fh) {
1400 #ifndef STDIO_DISABLE
1401  switch (fh) {
1402  case STDOUT:
1403  case STDIN:
1404  case STDERR:
1405  return (0);
1406  }
1407 #endif
1408  return (__sys_flen (fh));
1409 }
1410 
1411 
1428 __weak void _sys_exit (int return_code) {
1429  /* Endless loop. */
1430  while (1);
1431 }