13 #include "rl_fs_lib.h"
23 #error "File System does not work with MicroLIB"
30 #define NOR0_DEFAULT_DRIVE 0
35 #define NOR1_DEFAULT_DRIVE 0
40 #define RAM0_DEFAULT_DRIVE 0
46 #define MC0_DEFAULT_DRIVE 0
52 #define MC1_DEFAULT_DRIVE 0
57 #define NAND0_ENABLE 0
58 #define NAND0_DEFAULT_DRIVE 0
63 #define NAND1_ENABLE 0
64 #define NAND1_DEFAULT_DRIVE 0
70 #define USB0_DEFAULT_DRIVE 0
76 #define USB1_DEFAULT_DRIVE 0
80 #ifndef FAT_MAX_OPEN_FILES
81 #define FAT_MAX_OPEN_FILES NUM_FILES
83 #ifndef EFS_MAX_OPEN_FILES
84 #define EFS_MAX_OPEN_FILES NUM_FILES
90 #define FS_NDRV (NOR0_ENABLE + NOR1_ENABLE + \
92 MC0_ENABLE + MC1_ENABLE + \
93 USB0_ENABLE + USB1_ENABLE + \
94 NAND0_ENABLE + NAND1_ENABLE)
96 #error "No drive enabled, File System requires at least on component ::File System:Drive"
100 #define FS_FAT_NDRV (RAM0_ENABLE + \
101 MC0_ENABLE + MC1_ENABLE + \
102 USB0_ENABLE + USB1_ENABLE + \
103 NAND0_ENABLE + NAND1_ENABLE)
106 #define FS_NAND_NDRV (NAND0_ENABLE + NAND1_ENABLE)
109 #define __DEF ((NOR0_DEFAULT_DRIVE & NOR0_ENABLE) + \
110 (NOR1_DEFAULT_DRIVE & NOR1_ENABLE) + \
111 (RAM0_DEFAULT_DRIVE & RAM0_ENABLE) + \
112 (MC0_DEFAULT_DRIVE & MC0_ENABLE) + \
113 (MC1_DEFAULT_DRIVE & MC1_ENABLE) + \
114 (USB0_DEFAULT_DRIVE & USB0_ENABLE) + \
115 (USB1_DEFAULT_DRIVE & USB1_ENABLE) + \
116 (NAND0_DEFAULT_DRIVE & NAND0_ENABLE) + \
117 (NAND1_DEFAULT_DRIVE & NAND1_ENABLE))
119 #error "Default ::File System:Drive not specified"
121 #error "Multiple default ::File System:Drive: enabled"
125 #if (MC0_ENABLE && MC1_ENABLE)
126 #if (MC0_MCI_DRIVER == MC1_MCI_DRIVER)
127 #error "::File System:Drive:Memory Card: MCI ports for different drives must be different"
132 #define EFS_USE (NOR0_ENABLE + NOR1_ENABLE)
133 #define FAT_USE (RAM0_ENABLE + MC0_ENABLE + MC1_ENABLE + USB0_ENABLE + USB1_ENABLE + NAND0_ENABLE + NAND1_ENABLE)
136 #define FSJ_USE (MC0_ENABLE * MC0_FAT_JOURNAL + \
137 MC1_ENABLE * MC1_FAT_JOURNAL + \
138 USB0_ENABLE * USB0_FAT_JOURNAL + \
139 USB1_ENABLE * USB1_FAT_JOURNAL + \
140 NAND0_ENABLE * NAND0_FAT_JOURNAL + \
141 NAND1_ENABLE * NAND1_FAT_JOURNAL)
144 #define FAT_SECT_RSVD 64
148 extern volatile int _stream_list_lock;
149 #define STREAM_LIST_LOCK _stream_list_lock;
151 #define STREAM_LIST_LOCK
155 #define FAT_HANDLE_COUNT ((FAT_MAX_OPEN_FILES > 0) ? FAT_MAX_OPEN_FILES : 1)
160 #define EFS_HANDLE_COUNT ((EFS_MAX_OPEN_FILES > 0) ? EFS_MAX_OPEN_FILES : 1)
170 #if (FAT_NAME_CACHE_SIZE == 0)
175 #if (FAT_NAME_CACHE_RELOC == 1)
176 #define __AT_FAT_NAME __at(FAT_NAME_CACHE_ADDR)
178 #define __AT_FAT_NAME
182 #define FAT_NAME_MAX_DEPTH 8
185 #define FAT_NAME_CB_SZ (16)
186 #define FAT_NAME_CB_POOL_SZ (FAT_NAME_CB_SZ * FS_FAT_NDRV)
189 #define FAT_NAME_DEPTH_CB_SZ (8)
190 #define FAT_NAME_DEPTH_POOL_SZ (FAT_NAME_DEPTH_CB_SZ * FAT_NAME_MAX_DEPTH * FS_FAT_NDRV)
193 #define FAT_NAME_LINK_SZ (48)
194 #define FAT_NAME_LINK_POOL_SZ (FAT_NAME_LINK_SZ * FAT_NAME_CACHE_SIZE)
197 #define FAT_NAME_POOL_SIZE (FAT_NAME_CB_POOL_SZ + \
198 FAT_NAME_DEPTH_POOL_SZ + \
199 FAT_NAME_LINK_POOL_SZ)
201 static uint32_t fat_name_pool[FAT_NAME_POOL_SIZE/4] __AT_FAT_NAME;
211 #define EXPAND_SYMBOL(name, port) name##port
212 #define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
218 static fsEFS_Volume nor0_vol;
220 extern ARM_DRIVER_NOR
CREATE_SYMBOL (Driver_NOR_, NOR0_NAME);
221 extern ARM_NOR_DEVICE
CREATE_SYMBOL (NOR_Device_, NOR0_NAME);
224 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, NOR0_SPI_DRIVER);
233 static fsEFS_Volume nor1_vol;
235 extern ARM_DRIVER_NOR
CREATE_SYMBOL (Driver_NOR_, NOR1_NAME);
236 extern ARM_NOR_DEVICE
CREATE_SYMBOL (NOR_Device_, NOR1_NAME);
239 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, NOR1_SPI_DRIVER);
248 static fsFAT_Volume mc0_vol;
249 static MCI_DEV mc0_dev;
251 #if (MC0_FAT_JOURNAL)
252 static FSJOUR mc0_fsj;
255 extern ARM_DRIVER_MCI
CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
257 #if (MC0_CACHE_RELOC == 1)
258 #define __AT_MC0 __at(MC0_CACHE_ADDR)
264 static uint32_t mc0_cache[(MC0_CACHE_SIZE+1) * 256 + MC0_FAT_JOURNAL * 128] __AT_MC0;
268 #define MC0_INIT(m) mc_mci_Init (m, &mc0_dev)
269 #define MC0_UNINIT(m) mc_mci_UnInit (m, &mc0_dev)
270 #define MC0_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc0_dev)
271 #define MC0_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc0_dev)
272 #define MC0_RDINFO(i) mc_mci_ReadInfo (i, &mc0_dev)
273 #define MC0_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc0_dev)
276 #define MC0_INIT(m) mc_spi_Init (m, &mc0_dev)
277 #define MC0_UNINIT(m) mc_spi_UnInit (m, &mc0_dev)
278 #define MC0_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc0_dev)
279 #define MC0_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc0_dev)
280 #define MC0_RDINFO(i) mc_spi_ReadInfo (i, &mc0_dev)
281 #define MC0_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc0_dev)
283 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
287 static uint32_t mc0_Init (uint32_t mode) {
288 return (MC0_INIT (mode));
290 static uint32_t mc0_UnInit (uint32_t mode) {
291 return (MC0_UNINIT (mode));
293 static uint32_t mc0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
294 return (MC0_RDSEC (sect, buf, cnt));
296 static uint32_t mc0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
297 return (MC0_WRSEC (sect, buf, cnt));
300 return (MC0_RDINFO (info));
303 return (MC0_DEVCTRL (code, p));
317 static void MC0_MCI_SignalEvent (ARM_MCI_EVENT event) {
318 mc_mci_DrvEvent (event, &mc0_dev);
321 static void MC0_SPI_SignalEvent (ARM_SPI_EVENT event) {
322 mc_spi_DrvEvent (event, &mc0_dev);
331 static fsFAT_Volume mc1_vol;
332 static MCI_DEV mc1_dev;
334 #if (MC1_FAT_JOURNAL)
335 static FSJOUR mc1_fsj;
338 extern ARM_DRIVER_MCI
CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
340 #if (MC1_CACHE_RELOC == 1)
341 #define __AT_MC1 __at(MC1_CACHE_ADDR)
347 static uint32_t mc1_cache[(MC1_CACHE_SIZE+1) * 256 + MC1_FAT_JOURNAL * 128] __AT_MC1;
351 #define MC1_INIT(m) mc_mci_Init (m, &mc1_dev)
352 #define MC1_UNINIT(m) mc_mci_UnInit (m, &mc1_dev)
353 #define MC1_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc1_dev)
354 #define MC1_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc1_dev)
355 #define MC1_RDINFO(i) mc_mci_ReadInfo (i, &mc1_dev)
356 #define MC1_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc1_dev)
359 #define MC1_INIT(m) mc_spi_Init (m, &mc1_dev)
360 #define MC1_UNINIT(m) mc_spi_UnInit (m, &mc1_dev)
361 #define MC1_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc1_dev)
362 #define MC1_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc1_dev)
363 #define MC1_RDINFO(i) mc_spi_ReadInfo (i, &mc1_dev)
364 #define MC1_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc1_dev)
366 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
370 static uint32_t mc1_Init (uint32_t mode) {
371 return (MC1_INIT (mode));
373 static uint32_t mc1_UnInit (uint32_t mode) {
374 return (MC1_UNINIT (mode));
376 static uint32_t mc1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
377 return (MC1_RDSEC (sect, buf, cnt));
379 static uint32_t mc1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
380 return (MC1_WRSEC (sect, buf, cnt));
383 return (MC1_RDINFO (info));
386 return (MC1_DEVCTRL (code, p));
400 static void MC1_MCI_SignalEvent (ARM_MCI_EVENT event) {
401 mc_mci_DrvEvent (event, &mc1_dev);
404 static void MC1_SPI_SignalEvent (ARM_SPI_EVENT event) {
405 mc_spi_DrvEvent (event, &mc1_dev);
413 #ifdef RTE_FileSystem_Drive_NAND_0
415 #define NAND_INFO_0_DEV_0
417 #if ((NAND1_ENABLE) && (NAND1_DRIVER == NAND0_DRIVER))
418 #if (NAND1_DEV_NUM == NAND0_DEV_NUM)
419 #error "::File System:Drive:NAND: NAND ports for different drives must be different"
421 #define NAND_INFO_0_DEV_1
426 #ifdef RTE_FileSystem_Drive_NAND_1
427 #if (((NAND0_ENABLE == 0) && NAND1_ENABLE) || ((NAND0_ENABLE && NAND1_ENABLE) && (NAND1_DRIVER != NAND0_DRIVER)))
428 #define NAND_INFO_1_DEV_0
433 static fsFAT_Volume nand0_vol;
434 static NAND_FTL_DEV nand0_dev;
436 #if (NAND0_FAT_JOURNAL)
437 static FSJOUR nand0_fsj;
440 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
444 static fsFAT_Volume nand1_vol;
445 static NAND_FTL_DEV nand1_dev;
447 #if (NAND1_FAT_JOURNAL)
448 static FSJOUR nand1_fsj;
451 #if defined(NAND_INFO_1_DEV_0)
452 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
456 #if defined(NAND_INFO_0_DEV_0)
457 #define NAND0_EVENT_HANDLER NAND_SignalEventHandler0
458 #if defined(NAND_INFO_0_DEV_1)
459 #define NAND1_EVENT_HANDLER NAND_SignalEventHandler0
462 void NAND_SignalEventHandler0 (uint32_t dev_num) {
464 case NAND0_DEV_NUM: ftl_DrvEvent (&nand0_dev);
break;
466 #if defined(NAND_INFO_0_DEV_1)
467 case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev);
break;
474 ARM_NAND_DEVICE NAND_DevInfo0[] = {
481 NAND_SEC_BLOCK (NAND0_PAGE_COUNT, NAND0_PAGE_SIZE),
482 NAND_SEC_PAGE (NAND0_PAGE_SIZE),
483 NAND_ROW_CYCLES (NAND0_BLOCK_COUNT, NAND0_PAGE_COUNT),
484 NAND_COL_CYCLES (NAND0_PAGE_SIZE),
487 #if defined(NAND_INFO_0_DEV_1)
494 NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
495 NAND_SEC_PAGE (NAND1_PAGE_SIZE),
496 NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
497 NAND_COL_CYCLES (NAND1_PAGE_SIZE),
502 #define NAND_INFO0 NAND_DevInfo0
503 #define NAND_INFO0_SZ (sizeof(NAND_DevInfo0) / sizeof(NAND_DevInfo0[0]))
505 #define NAND_INFO0 NULL
506 #define NAND_INFO0_SZ 0
509 #if defined(NAND_INFO_1_DEV_0)
510 #define NAND1_EVENT_HANDLER NAND_SignalEventHandler1
512 void NAND_SignalEventHandler1 (uint32_t dev_num) {
514 case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev);
break;
520 ARM_NAND_DEVICE NAND_DevInfo1[] = {
527 NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
528 NAND_SEC_PAGE (NAND1_PAGE_SIZE),
529 NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
530 NAND_COL_CYCLES (NAND1_PAGE_SIZE),
534 #define NAND_INFO1 NAND_DevInfo1
535 #define NAND_INFO1_SZ (sizeof(NAND_DevInfo1) / sizeof(NAND_DevInfo1[0]))
537 #define NAND_INFO1 NULL
538 #define NAND_INFO1_SZ 0
545 #if (NAND0_CACHE_RELOC == 1)
546 #define __AT_NAND0 __at(NAND0_CACHE_ADDR)
552 #define NAND0_CSZ ((NAND0_CACHE_SIZE + 1) * 1024 + \
553 (NAND0_PAGE_CACHE + 2) * NAND0_PAGE_SIZE + \
554 (NAND0_BLOCK_CACHE + 2) * NAND0_PAGE_COUNT)
555 #define NAND0_FSJBUF (NAND0_FAT_JOURNAL * 512)
557 static uint32_t nand0_cache[NAND0_CSZ/4 + NAND0_FSJBUF/4] __AT_NAND0;
558 static PAGE_CACHE nand0_capg [NAND0_PAGE_CACHE + 1];
559 static BLOCK_CACHE nand0_cabl [NAND0_BLOCK_CACHE + 2];
560 static uint32_t nand0_ttsn [NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE)];
563 static NAND_FTL_CFG nand0_cfg = {
566 NAND_BTT_SIZE (NAND0_BLOCK_COUNT),
569 NAND_BTT_SIZE (NAND0_BLOCK_COUNT) + 1,
570 NAND0_BLOCK_COUNT - 1,
573 NAND0_BLOCK_CACHE + 2,
574 NAND0_PAGE_CACHE + 1,
575 NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE),
578 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256],
580 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+(NAND0_PAGE_CACHE+2)*NAND0_PAGE_SIZE/4],
582 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+NAND0_PAGE_SIZE/4],
587 static uint32_t nand0_Init (uint32_t mode) {
590 static uint32_t nand0_UnInit (uint32_t mode) {
591 return (ftl_UnInit (mode, &nand0_dev));
593 static uint32_t nand0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
594 uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand0_dev);
595 if (retv < 2)
return (
true);
598 static uint32_t nand0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
599 uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand0_dev);
600 if (retv < 2)
return (
true);
604 return (ftl_ReadInfo (info, &nand0_dev));
607 return (ftl_DevCtrl (code, p, &nand0_dev));
610 FAT_DRV nand0_drv = {
624 #if (NAND1_CACHE_RELOC == 1)
625 #define __AT_NAND1 __at(NAND1_CACHE_ADDR)
631 #define NAND1_CSZ ((NAND1_CACHE_SIZE + 1) * 1024 + \
632 (NAND1_PAGE_CACHE + 2) * NAND1_PAGE_SIZE + \
633 (NAND1_BLOCK_CACHE + 2) * NAND1_PAGE_COUNT)
634 #define NAND1_FSJBUF (NAND1_FAT_JOURNAL * 512)
636 static uint32_t nand1_cache[NAND1_CSZ/4 + NAND1_FSJBUF/4] __AT_NAND1;
637 static PAGE_CACHE nand1_capg [NAND1_PAGE_CACHE + 1];
638 static BLOCK_CACHE nand1_cabl [NAND1_BLOCK_CACHE + 2];
639 static uint32_t nand1_ttsn [NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE)];
642 static NAND_FTL_CFG nand1_cfg = {
645 NAND_BTT_SIZE (NAND1_BLOCK_COUNT),
648 NAND_BTT_SIZE (NAND1_BLOCK_COUNT) + 1,
649 NAND1_BLOCK_COUNT - 1,
652 NAND1_BLOCK_CACHE + 2,
653 NAND1_PAGE_CACHE + 1,
654 NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE),
657 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256],
659 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+(NAND1_PAGE_CACHE+2)*NAND1_PAGE_SIZE/4],
661 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+NAND1_PAGE_SIZE/4],
666 static uint32_t nand1_Init (uint32_t mode) {
669 static uint32_t nand1_UnInit (uint32_t mode) {
670 return (ftl_UnInit (mode, &nand1_dev));
672 static uint32_t nand1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
673 uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand1_dev);
674 if (retv < 2)
return (
true);
677 static uint32_t nand1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
678 uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand1_dev);
679 if (retv < 2)
return (
true);
683 return (ftl_ReadInfo (info, &nand1_dev));
686 return (ftl_DevCtrl (code, p, &nand1_dev));
689 FAT_DRV nand1_drv = {
703 static fsFAT_Volume ram0_vol;
705 #if (RAM0_SIZE < 0x4A00)
706 #error "::File System:Drive:RAM requires minimum of 0x4A00 bytes of memory"
709 #if (RAM0_RELOC == 1)
710 #define __AT_RAM0 __at(RAM0_BASE_ADDR)
716 static uint32_t ram0_buf[256 + (RAM0_SIZE/4)] __AT_RAM0;
719 static RAM_DEV ram0_dev = {
720 (uint8_t *)&ram0_buf[256],
725 static uint32_t ram0_Init (uint32_t mode) {
726 return (ram_Init (mode, &ram0_dev));
728 static uint32_t ram0_UnInit (uint32_t mode) {
729 return (ram_UnInit (mode, &ram0_dev));
731 static uint32_t ram0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
732 return (ram_ReadSector (sect, buf, cnt, &ram0_dev));
734 static uint32_t ram0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
735 return (ram_WriteSector (sect, buf, cnt, &ram0_dev));
738 return (ram_ReadInfo (info, &ram0_dev));
741 return (ram_DevCtrl (code, p, &ram0_dev));
759 extern FAT_DRV usb0_drv;
761 #if (USB0_FAT_JOURNAL)
762 static FSJOUR usb0_fsj;
766 static uint32_t usb0_cache[(USB0_CACHE_SIZE+1) * 256 + USB0_FAT_JOURNAL * 128];
767 static fsFAT_Volume usb0_vol;
770 static uint32_t usb0_Init (uint32_t mode) {
771 return (FS_USBH_MSC_Initialize (0, mode));
773 static uint32_t usb0_UnInit (uint32_t mode) {
774 return (FS_USBH_MSC_Uninitialize (0, mode));
776 static uint32_t usb0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
777 return (FS_USBH_MSC_ReadSectors (0, sect, cnt, buf));
779 static uint32_t usb0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
780 return (FS_USBH_MSC_WriteSectors (0, sect, cnt, buf));
783 return (FS_USBH_MSC_ReadInfo (0, info));
786 return (FS_USBH_MSC_DeviceCtrl (0, code, p));
803 extern FAT_DRV usb1_drv;
805 #if (USB1_FAT_JOURNAL)
806 static FSJOUR usb1_fsj;
810 static uint32_t usb1_cache[(USB1_CACHE_SIZE+1) * 256 + USB1_FAT_JOURNAL * 128];
811 static fsFAT_Volume usb1_vol;
814 static uint32_t usb1_Init (uint32_t mode) {
815 return (FS_USBH_MSC_Initialize (1, mode));
817 static uint32_t usb1_UnInit (uint32_t mode) {
818 return (FS_USBH_MSC_Uninitialize (1, mode));
820 static uint32_t usb1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
821 return (FS_USBH_MSC_ReadSectors (1, sect, cnt, buf));
823 static uint32_t usb1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
824 return (FS_USBH_MSC_WriteSectors (1, sect, cnt, buf));
827 return (FS_USBH_MSC_ReadInfo (1, info));
830 return (FS_USBH_MSC_DeviceCtrl (1, code, p));
884 nor0_vol.BaseAdr = NOR0_BASE_ADDR;
885 nor0_vol.InitVal =
CREATE_SYMBOL (NOR_Device_, NOR0_NAME).erased_value * 0x01010101;
886 nor0_vol.NumSect =
CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_count;
888 nor0_vol.DevCfg =
CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_info;
893 nor1_vol.BaseAdr = NOR1_BASE_ADDR;
894 nor1_vol.InitVal =
CREATE_SYMBOL (NOR_Device_, NOR1_NAME).erased_value * 0x01010101;
895 nor1_vol.NumSect =
CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_count;
897 nor1_vol.DevCfg =
CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_info;
901 mc0_vol.Drv = &mc0_drv;
902 mc0_vol.CaBuf = mc0_cache;
903 mc0_vol.CaSize = MC0_CACHE_SIZE * 2;
906 mc0_dev.DrvMci = &
CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
907 mc0_dev.MCI_Callback = MC0_MCI_SignalEvent;
910 mc0_dev.DrvSpi = &
CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
911 mc0_dev.SPI_Callback = MC0_SPI_SignalEvent;
914 #if (MC0_FAT_JOURNAL)
916 mc0_fsj.buf = (uint8_t *)&mc0_cache[(MC0_CACHE_SIZE+1) * 256];
917 mc0_vol.fsj = &mc0_fsj;
926 mc1_vol.Drv = &mc1_drv;
927 mc1_vol.CaBuf = mc1_cache;
928 mc1_vol.CaSize = MC1_CACHE_SIZE * 2;
931 mc1_dev.DrvMci = &
CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
932 mc1_dev.MCI_Callback = MC1_MCI_SignalEvent;
935 mc1_dev.DrvSpi = &
CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
936 mc1_dev.SPI_Callback = MC1_SPI_SignalEvent;
939 #if (MC1_FAT_JOURNAL)
941 mc1_fsj.buf = (uint8_t *)&mc1_cache[(MC1_CACHE_SIZE+1) * 256];
942 mc1_vol.fsj = &mc1_fsj;
951 nand0_vol.Drv = &nand0_drv;
952 nand0_vol.CaBuf = nand0_cache;
953 nand0_vol.CaSize = NAND0_CACHE_SIZE * 2;
956 nand0_dev.Dev = &NAND_DevInfo0[0];
957 nand0_dev.Cfg = &nand0_cfg;
958 nand0_dev.Callback = NAND0_EVENT_HANDLER;
960 #if (NAND0_FAT_JOURNAL)
962 nand0_fsj.buf = (uint8_t *)&nand0_cache[NAND0_CSZ/4];
963 nand0_vol.fsj = &nand0_fsj;
966 nand0_vol.fsj = NULL;
972 nand1_vol.Drv = &nand1_drv;
973 nand1_vol.CaBuf = nand1_cache;
974 nand1_vol.CaSize = NAND1_CACHE_SIZE * 2;
977 #if defined(NAND_INFO_0_DEV_1)
978 nand1_dev.Dev = &NAND_DevInfo0[1];
980 nand1_dev.Dev = &NAND_DevInfo1[0];
982 nand1_dev.Cfg = &nand1_cfg;
983 nand1_dev.Callback = NAND1_EVENT_HANDLER;
985 #if (NAND1_FAT_JOURNAL)
987 nand1_fsj.buf = (uint8_t *)&nand1_cache[NAND1_CSZ/4];
988 nand1_vol.fsj = &nand1_fsj;
991 nand1_vol.fsj = NULL;
997 ram0_vol.Drv = &ram0_drv;
998 ram0_vol.CaBuf = ram0_buf;
1001 ram0_vol.fsj = NULL;
1005 usb0_vol.Drv = &usb0_drv;
1006 usb0_vol.CaBuf = usb0_cache;
1007 usb0_vol.CaSize = USB0_CACHE_SIZE * 2;
1009 #if (USB0_FAT_JOURNAL)
1011 usb0_fsj.buf = (uint8_t *)&usb0_cache[(USB0_CACHE_SIZE+1) * 256];
1012 usb0_vol.fsj = &usb0_fsj;
1015 usb0_vol.fsj = NULL;
1021 usb1_vol.Drv = &usb1_drv;
1022 usb1_vol.CaSize = USB1_CACHE_SIZE * 2;
1023 usb1_vol.CaBuf = usb1_cache;
1026 #if (USB1_FAT_JOURNAL)
1028 usb1_fsj.buf = (uint8_t *)&usb1_cache[(USB1_CACHE_SIZE+1) * 256];
1029 usb1_vol.fsj = &usb1_fsj;
1032 usb1_vol.fsj = NULL;
1047 int32_t
efs_read (int32_t handle, uint8_t *buf, uint32_t len) {
return (0); }
1048 int32_t
efs_write (int32_t handle,
const uint8_t *buf, uint32_t len) {
return (-1); }
1067 int32_t
fat_read (int32_t handle, uint8_t *buf, uint32_t len) {
return(-1); }
1068 int32_t
fat_write(int32_t handle,
const uint8_t *buf, uint32_t len) {
return(-1); }
1085 uint32_t
fat_jour_init (fsFAT_Volume *vol) {
return (
true); }
1086 uint32_t fat_jour_prep (fsFAT_Volume *vol) {
return (
true); }
1087 uint32_t fsj_set_space (FSJOUR *fsj, uint32_t start_sect, uint32_t cnt) {
1089 uint32_t fsj_write (FSJOUR *fsj, uint32_t sect, uint32_t cnt, uint8_t *buf) {
1091 uint32_t fsj_init (FSJOUR *fsj, FAT_DRV *drv) {
return (
false); }
1095 #if (FAT_NAME_CACHE_SIZE == 0)
1102 uint32_t
elink_scan (uint32_t i,
void **pp, uint32_t j) {
return (1); }
1110 #pragma import(__use_no_semihosting_swi)
1112 #ifndef STDIO_DISABLE
1115 #define STDIN 0x8001
1116 #define STDOUT 0x8002
1117 #define STDERR 0x8003
1124 #if (__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
1150 #ifndef STDIO_DISABLE
1151 #ifndef STDOUT_LF_CR_DISABLE
1176 #ifndef STDIO_DISABLE
1177 if (strcmp(name,
"STDIN") == 0) {
1180 if (strcmp(name,
"STDOUT") == 0) {
1183 if (strcmp(name,
"STDERR") == 0) {
1187 return (__sys_open (name, openmode));
1203 #ifndef STDIO_DISABLE
1211 return (__sys_close (fh));
1233 int _sys_write (FILEHANDLE fh,
const uint8_t *buf, uint32_t len,
int mode) {
1234 #ifndef STDIO_DISABLE
1240 for ( ; len; len--) {
1242 #ifndef STDOUT_LF_CR_DISABLE
1253 return (__sys_write (fh, buf, len));
1284 int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len,
int mode) {
1285 #ifndef STDIO_DISABLE
1294 *buf++ = (uint8_t)ch;
1296 for ( ; len; len--) {
1299 *buf++ = (uint8_t)ch;
1307 return (__sys_read (fh, buf, len));
1327 #ifndef STDIO_DISABLE
1354 #ifndef STDIO_DISABLE
1362 return (__sys_seek (fh, pos));
1372 #ifndef STDIO_DISABLE
1380 return (__sys_ensure (fh));
1400 #ifndef STDIO_DISABLE
1408 return (__sys_flen (fh));