File System Component  Version 5.0
MDK-Professional Middleware for Devices with Flash File System
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fs_config.h
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1 /*------------------------------------------------------------------------------
2  * MDK Middleware - Component ::File System
3  * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
4  *------------------------------------------------------------------------------
5  * Name: fs_config.h
6  * Purpose: File System Library Configuration
7  * Rev.: V5.05
8  *----------------------------------------------------------------------------*/
9 
10 #include <string.h>
11 #include <rt_sys.h>
12 #include "rl_fs_lib.h"
13 
14 #pragma thumb
15 #pragma O3
16 
17 /*-----------------------------------------------------------------------------
18  * File System Configuration File
19  *----------------------------------------------------------------------------*/
20 
21 #ifdef __MICROLIB
22  #error "File System does not work with MicroLIB"
23 #endif
24 
25 /* ---------------------------------------------------------------------------*/
26 
27 #ifndef NOR0_ENABLE
28  #define NOR0_ENABLE 0
29  #define NOR0_DEFAULT_DRIVE 0
30 #endif
31 
32 #ifndef NOR1_ENABLE
33  #define NOR1_ENABLE 0
34  #define NOR1_DEFAULT_DRIVE 0
35 #endif
36 
37 #ifndef RAM0_ENABLE
38  #define RAM0_ENABLE 0
39  #define RAM0_DEFAULT_DRIVE 0
40 #endif
41 
42 /* If MC0 drive not defined */
43 #ifndef MC0_ENABLE
44  #define MC0_ENABLE 0
45  #define MC0_DEFAULT_DRIVE 0
46 #endif
47 
48 /* If MC1 drive not defined */
49 #ifndef MC1_ENABLE
50  #define MC1_ENABLE 0
51  #define MC1_DEFAULT_DRIVE 0
52 #endif
53 
54 /* If NAND0 drive not defined */
55 #ifndef NAND0_ENABLE
56  #define NAND0_ENABLE 0
57  #define NAND0_DEFAULT_DRIVE 0
58 #endif
59 
60 /* If NAND1 drive not defined */
61 #ifndef NAND1_ENABLE
62  #define NAND1_ENABLE 0
63  #define NAND1_DEFAULT_DRIVE 0
64 #endif
65 
66 /* If USB0 drive not defined */
67 #ifndef USB0_ENABLE
68  #define USB0_ENABLE 0
69  #define USB0_DEFAULT_DRIVE 0
70 #endif
71 
72 /* If USB1 drive not defined */
73 #ifndef USB1_ENABLE
74  #define USB1_ENABLE 0
75  #define USB1_DEFAULT_DRIVE 0
76 #endif
77 
78 /* FS_Config V5.00 compatibility */
79 #ifndef FAT_MAX_OPEN_FILES
80  #define FAT_MAX_OPEN_FILES NUM_FILES
81 #endif
82 #ifndef EFS_MAX_OPEN_FILES
83  #define EFS_MAX_OPEN_FILES NUM_FILES
84 #endif
85 
86 /* ---------------------------------------------------------------------------*/
87 
88 /* Check number of enabled drives */
89 #define FS_NDRV (NOR0_ENABLE + NOR1_ENABLE + \
90  RAM0_ENABLE + \
91  MC0_ENABLE + MC1_ENABLE + \
92  USB0_ENABLE + USB1_ENABLE + \
93  NAND0_ENABLE + NAND1_ENABLE)
94 #if (FS_NDRV == 0)
95  #error "No drive enabled, File System requires at least on component ::File System:Drive"
96 #endif
97 
98 /* Count number of enabled FAT drives */
99 #define FS_FAT_NDRV (RAM0_ENABLE + \
100  MC0_ENABLE + MC1_ENABLE + \
101  USB0_ENABLE + USB1_ENABLE + \
102  NAND0_ENABLE + NAND1_ENABLE)
103 
104 /* Count number of enabled NAND devices */
105 #define FS_NAND_NDRV (NAND0_ENABLE + NAND1_ENABLE)
106 
107 /* Check Default drive settings */
108 #define __DEF ((NOR0_DEFAULT_DRIVE & NOR0_ENABLE) + \
109  (NOR1_DEFAULT_DRIVE & NOR1_ENABLE) + \
110  (RAM0_DEFAULT_DRIVE & RAM0_ENABLE) + \
111  (MC0_DEFAULT_DRIVE & MC0_ENABLE) + \
112  (MC1_DEFAULT_DRIVE & MC1_ENABLE) + \
113  (USB0_DEFAULT_DRIVE & USB0_ENABLE) + \
114  (USB1_DEFAULT_DRIVE & USB1_ENABLE) + \
115  (NAND0_DEFAULT_DRIVE & NAND0_ENABLE) + \
116  (NAND1_DEFAULT_DRIVE & NAND1_ENABLE))
117 #if (__DEF == 0)
118  #error "Default ::File System:Drive not specified"
119 #elif (__DEF > 1)
120  #error "Multiple default ::File System:Drive: enabled"
121 #endif
122 
123 /* Check MCI port consistency */
124 #if (MC0_ENABLE && MC1_ENABLE)
125  #if (MC0_MCI_DRIVER == MC1_MCI_DRIVER)
126  #error "::File System:Drive:Memory Card: MCI ports for different drives must be different"
127  #endif
128 #endif
129 
130 /* Check FS usage */
131 #define EFS_USE (NOR0_ENABLE + NOR1_ENABLE)
132 #define FAT_USE (RAM0_ENABLE + MC0_ENABLE + MC1_ENABLE + USB0_ENABLE + USB1_ENABLE + NAND0_ENABLE + NAND1_ENABLE)
133 
134 /* Check journal usage */
135 #define FSJ_USE (MC0_ENABLE * MC0_FAT_JOURNAL + \
136  MC1_ENABLE * MC1_FAT_JOURNAL + \
137  USB0_ENABLE * USB0_FAT_JOURNAL + \
138  USB1_ENABLE * USB1_FAT_JOURNAL + \
139  NAND0_ENABLE * NAND0_FAT_JOURNAL + \
140  NAND1_ENABLE * NAND1_FAT_JOURNAL)
141 
142 /* Reserved sector count */
143 #define FAT_SECT_RSVD 64
144 
145 /* Make sure to resolve a weak stdlib symbol. */
146 #ifdef __RTX
147 extern volatile int _stream_list_lock;
148  #define STREAM_LIST_LOCK _stream_list_lock;
149 #else
150  #define STREAM_LIST_LOCK
151 #endif
152 
153 /* File Control Blocks for the FAT File System */
154 #define FAT_HANDLE_COUNT ((FAT_MAX_OPEN_FILES > 0) ? FAT_MAX_OPEN_FILES : 1)
157 
158 /* File Control Blocks for the Embedded File System */
159 #define EFS_HANDLE_COUNT ((EFS_MAX_OPEN_FILES > 0) ? EFS_MAX_OPEN_FILES : 1)
162 
163 /* Number of enabled drives */
164 uint8_t const _NDRV = FS_NDRV;
165 
166 /*----------------------------------------------------------------------------
167  * FAT Name Cache definition and configuration
168  *---------------------------------------------------------------------------*/
169 #if (FAT_NAME_CACHE_SIZE == 0)
170  FAT_NCACHE_CFG fat_ncache = {
171  0, 0, 0, NULL
172  };
173 #else
174  #if (FAT_NAME_CACHE_RELOC == 1)
175  #define __AT_FAT_NAME __attribute__ ((at(FAT_NAME_CACHE_ADDR)))
176  #else
177  #define __AT_FAT_NAME
178  #endif
179 
180  /* FAT name cache max folder depth */
181  #define FAT_NAME_MAX_DEPTH 8
182 
183  /* FAT name cache control block size and count */
184  #define FAT_NAME_CB_SZ (16)
185  #define FAT_NAME_CB_POOL_SZ (FAT_NAME_CB_SZ * FS_FAT_NDRV)
186 
187  /* FAT name cache folder depth control block size */
188  #define FAT_NAME_DEPTH_CB_SZ (8)
189  #define FAT_NAME_DEPTH_POOL_SZ (FAT_NAME_DEPTH_CB_SZ * FAT_NAME_MAX_DEPTH * FS_FAT_NDRV)
190 
191  /* FAT name cache pool size */
192  #define FAT_NAME_LINK_SZ (48)
193  #define FAT_NAME_LINK_POOL_SZ (FAT_NAME_LINK_SZ * FAT_NAME_CACHE_SIZE)
194 
195  /* FAT name cache buffer size in bytes */
196  #define FAT_NAME_POOL_SIZE (FAT_NAME_CB_POOL_SZ + \
197  FAT_NAME_DEPTH_POOL_SZ + \
198  FAT_NAME_LINK_POOL_SZ)
199 
200  static uint32_t fat_name_pool[FAT_NAME_POOL_SIZE/4] __AT_FAT_NAME;
201 
202  FAT_NCACHE_CFG fat_ncache = {
203  FAT_NAME_MAX_DEPTH,
204  FS_FAT_NDRV,
205  FAT_NAME_POOL_SIZE,
206  fat_name_pool
207  };
208 #endif /* FAT_NAME_CACNT */
209 
210 #define EXPAND_SYMBOL(name, port) name##port
211 #define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
212 
213 /*----------------------------------------------------------------------------
214  * Drive F0: NOR Flash device NOR0 configuration
215  *---------------------------------------------------------------------------*/
216 #if (NOR0_ENABLE)
217  static fsEFS_Volume nor0_vol;
218 
219  extern ARM_DRIVER_NOR CREATE_SYMBOL (Driver_NOR_, NOR0_NAME);
220  extern ARM_NOR_DEVICE CREATE_SYMBOL (NOR_Device_, NOR0_NAME);
221 
222  #if (NOR0_SPI)
223  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, NOR0_SPI_DRIVER);
224  ARM_DRIVER_SPI *CREATE_SYMBOL (NOR_SPI_Driver_, NOR0_NAME) = &CREATE_SYMBOL (Driver_SPI, NOR0_SPI_DRIVER);
225  #endif
226 #endif
227 
228 /*----------------------------------------------------------------------------
229  * Drive F1: NOR Flash device NOR1 configuration
230  *---------------------------------------------------------------------------*/
231 #if (NOR1_ENABLE)
232  static fsEFS_Volume nor1_vol;
233 
234  extern ARM_DRIVER_NOR CREATE_SYMBOL (Driver_NOR_, NOR1_NAME);
235  extern ARM_NOR_DEVICE CREATE_SYMBOL (NOR_Device_, NOR1_NAME);
236 
237  #if (NOR1_SPI)
238  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, NOR1_SPI_DRIVER);
239  ARM_DRIVER_SPI *CREATE_SYMBOL (NOR_SPI_Driver_, NOR1_NAME) = &CREATE_SYMBOL (Driver_SPI, NOR1_SPI_DRIVER);
240  #endif
241 #endif
242 
243 /*----------------------------------------------------------------------------
244  * Drive M0: Memory Card device MC0 configuration
245  *---------------------------------------------------------------------------*/
246 #if (MC0_ENABLE)
247  static fsFAT_Volume mc0_vol;
248  static MCI_DEV mc0_dev;
249 
250  #if (MC0_FAT_JOURNAL)
251  static FSJOUR mc0_fsj;
252  #endif
253 
254  extern ARM_DRIVER_MCI CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
255 
256  #if (MC0_CACHE_RELOC == 1)
257  #define __AT_MC0 __attribute__ ((at(MC0_CACHE_ADDR)))
258  #else
259  #define __AT_MC0
260  #endif
261 
262  /* MC0 Cache Buffer for Data and FAT Caching */
263  static uint32_t mc0_cache[(MC0_CACHE_SIZE+1) * 256 + MC0_FAT_JOURNAL * 128] __AT_MC0;
264 
265  #if (MC0_SPI == 0)
266  /* SD Native bus mode */
267  #define MC0_INIT(m) mc_mci_Init (m, &mc0_dev)
268  #define MC0_UNINIT(m) mc_mci_UnInit (m, &mc0_dev)
269  #define MC0_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc0_dev)
270  #define MC0_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc0_dev)
271  #define MC0_RDINFO(i) mc_mci_ReadInfo (i, &mc0_dev)
272  #define MC0_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc0_dev)
273  #else
274  /* SPI bus mode */
275  #define MC0_INIT(m) mc_spi_Init (m, &mc0_dev)
276  #define MC0_UNINIT(m) mc_spi_UnInit (m, &mc0_dev)
277  #define MC0_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc0_dev)
278  #define MC0_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc0_dev)
279  #define MC0_RDINFO(i) mc_spi_ReadInfo (i, &mc0_dev)
280  #define MC0_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc0_dev)
281 
282  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
283  #endif
284 
285  /* MC0 wrapper functions */
286  static uint32_t mc0_Init (uint32_t mode) {
287  return (MC0_INIT (mode));
288  }
289  static uint32_t mc0_UnInit (uint32_t mode) {
290  return (MC0_UNINIT (mode));
291  }
292  static uint32_t mc0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
293  return (MC0_RDSEC (sect, buf, cnt));
294  }
295  static uint32_t mc0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
296  return (MC0_WRSEC (sect, buf, cnt));
297  }
298  static uint32_t mc0_RdInfo (fsMediaInfo *info) {
299  return (MC0_RDINFO (info));
300  }
301  static fsStatus mc0_DevCtrl (fsDevCtrlCode code, void *p) {
302  return (MC0_DEVCTRL (code, p));
303  }
304 
305  /* MC0 FAT device driver */
306  FAT_DRV mc0_drv = {
307  mc0_Init,
308  mc0_UnInit,
309  mc0_RdSect,
310  mc0_WrSect,
311  mc0_RdInfo,
312  mc0_DevCtrl
313  };
314 
315  /* ------- MC0 MCI/SPI Callback ------- */
316  static void MC0_MCI_SignalEvent (ARM_MCI_EVENT event) {
317  mc_mci_DrvEvent (event, &mc0_dev);
318  }
319  #if (MC0_SPI != 0)
320  static void MC0_SPI_SignalEvent (ARM_SPI_EVENT event) {
321  mc_spi_DrvEvent (event, &mc0_dev);
322  }
323  #endif
324 #endif
325 
326 /*----------------------------------------------------------------------------
327  * Drive M1: Memory Card device MC1 configuration
328  *---------------------------------------------------------------------------*/
329 #if (MC1_ENABLE)
330  static fsFAT_Volume mc1_vol;
331  static MCI_DEV mc1_dev;
332 
333  #if (MC1_FAT_JOURNAL)
334  static FSJOUR mc1_fsj;
335  #endif
336 
337  extern ARM_DRIVER_MCI CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
338 
339  #if (MC1_CACHE_RELOC == 1)
340  #define __AT_MC1 __attribute__ ((at(MC1_CACHE_ADDR)))
341  #else
342  #define __AT_MC1
343  #endif
344 
345  /* MC1 Cache Buffer for Data and FAT Caching */
346  static uint32_t mc1_cache[(MC1_CACHE_SIZE+1) * 256 + MC1_FAT_JOURNAL * 128] __AT_MC1;
347 
348  #if (MC1_SPI == 0)
349  /* SD Native bus mode */
350  #define MC1_INIT(m) mc_mci_Init (m, &mc1_dev)
351  #define MC1_UNINIT(m) mc_mci_UnInit (m, &mc1_dev)
352  #define MC1_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc1_dev)
353  #define MC1_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc1_dev)
354  #define MC1_RDINFO(i) mc_mci_ReadInfo (i, &mc1_dev)
355  #define MC1_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc1_dev)
356  #else
357  /* SPI bus mode */
358  #define MC1_INIT(m) mc_spi_Init (m, &mc1_dev)
359  #define MC1_UNINIT(m) mc_spi_UnInit (m, &mc1_dev)
360  #define MC1_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc1_dev)
361  #define MC1_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc1_dev)
362  #define MC1_RDINFO(i) mc_spi_ReadInfo (i, &mc1_dev)
363  #define MC1_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc1_dev)
364 
365  extern ARM_DRIVER_SPI CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
366  #endif
367 
368  /* MC1 wrapper functions */
369  static uint32_t mc1_Init (uint32_t mode) {
370  return (MC1_INIT (mode));
371  }
372  static uint32_t mc1_UnInit (uint32_t mode) {
373  return (MC1_UNINIT (mode));
374  }
375  static uint32_t mc1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
376  return (MC1_RDSEC (sect, buf, cnt));
377  }
378  static uint32_t mc1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
379  return (MC1_WRSEC (sect, buf, cnt));
380  }
381  static uint32_t mc1_RdInfo (fsMediaInfo *info) {
382  return (MC1_RDINFO (info));
383  }
384  static fsStatus mc1_DevCtrl (fsDevCtrlCode code, void *p) {
385  return (MC1_DEVCTRL (code, p));
386  }
387 
388  /* MC1 FAT device driver */
389  FAT_DRV mc1_drv = {
390  mc1_Init,
391  mc1_UnInit,
392  mc1_RdSect,
393  mc1_WrSect,
394  mc1_RdInfo,
395  mc1_DevCtrl
396  };
397 
398  /* ------- MC1 MCI/SPI Callback ------- */
399  static void MC1_MCI_SignalEvent (ARM_MCI_EVENT event) {
400  mc_mci_DrvEvent (event, &mc1_dev);
401  }
402  #if (MC1_SPI != 0)
403  static void MC1_SPI_SignalEvent (ARM_SPI_EVENT event) {
404  mc_spi_DrvEvent (event, &mc1_dev);
405  }
406  #endif
407 #endif
408 
409 /*----------------------------------------------------------------------------
410  * General NAND Flash device configuration
411  *---------------------------------------------------------------------------*/
412 #ifdef RTE_FileSystem_Drive_NAND_0
413  #if (NAND0_ENABLE)
414  #define NAND_INFO_0_DEV_0
415 
416  #if ((NAND1_ENABLE) && (NAND1_DRIVER == NAND0_DRIVER))
417  #if (NAND1_DEV_NUM == NAND0_DEV_NUM)
418  #error "::File System:Drive:NAND: NAND ports for different drives must be different"
419  #endif
420  #define NAND_INFO_0_DEV_1
421  #endif
422  #endif
423 #endif
424 
425 #ifdef RTE_FileSystem_Drive_NAND_1
426  #if (((NAND0_ENABLE == 0) && NAND1_ENABLE) || ((NAND0_ENABLE && NAND1_ENABLE) && (NAND1_DRIVER != NAND0_DRIVER)))
427  #define NAND_INFO_1_DEV_0
428  #endif
429 #endif
430 
431 #if (NAND0_ENABLE)
432  static fsFAT_Volume nand0_vol;
433  static NAND_FTL_DEV nand0_dev;
434 
435  #if (NAND0_FAT_JOURNAL)
436  static FSJOUR nand0_fsj;
437  #endif
438 
439  extern ARM_DRIVER_NAND CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
440 #endif
441 
442 #if (NAND1_ENABLE)
443  static fsFAT_Volume nand1_vol;
444  static NAND_FTL_DEV nand1_dev;
445 
446  #if (NAND1_FAT_JOURNAL)
447  static FSJOUR nand1_fsj;
448  #endif
449 
450  #if defined(NAND_INFO_1_DEV_0)
451  extern ARM_DRIVER_NAND CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
452  #endif
453 #endif
454 
455 #if defined(NAND_INFO_0_DEV_0)
456  #define NAND0_EVENT_HANDLER NAND_SignalEventHandler0
457  #if defined(NAND_INFO_0_DEV_1)
458  #define NAND1_EVENT_HANDLER NAND_SignalEventHandler0
459  #endif
460 
461  void NAND_SignalEventHandler0 (uint32_t dev_num) {
462  switch (dev_num) {
463  case NAND0_DEV_NUM: ftl_DrvEvent (&nand0_dev); break;
464 
465  #if defined(NAND_INFO_0_DEV_1)
466  case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev); break;
467  #endif
468 
469  default: return;
470  }
471  }
472 
473  ARM_NAND_DEVICE NAND_DevInfo0[] = {
474  {&nand0_dev.PgLay,
475  NAND0_TYPE,
476  NAND0_DEV_NUM,
477  NAND0_PAGE_SIZE,
478  NAND0_BLOCK_COUNT,
479  NAND0_PAGE_COUNT,
480  NAND_SEC_BLOCK (NAND0_PAGE_COUNT, NAND0_PAGE_SIZE),
481  NAND_SEC_PAGE (NAND0_PAGE_SIZE),
482  NAND_ROW_CYCLES (NAND0_BLOCK_COUNT, NAND0_PAGE_COUNT),
483  NAND_COL_CYCLES (NAND0_PAGE_SIZE),
484  NAND0_SW_ECC
485  },
486  #if defined(NAND_INFO_0_DEV_1)
487  {&nand1_dev.PgLay,
488  NAND1_TYPE,
489  NAND1_DEV_NUM,
490  NAND1_PAGE_SIZE,
491  NAND1_BLOCK_COUNT,
492  NAND1_PAGE_COUNT,
493  NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
494  NAND_SEC_PAGE (NAND1_PAGE_SIZE),
495  NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
496  NAND_COL_CYCLES (NAND1_PAGE_SIZE),
497  NAND1_SW_ECC
498  },
499  #endif
500  };
501  #define NAND_INFO0 NAND_DevInfo0
502  #define NAND_INFO0_SZ (sizeof(NAND_DevInfo0) / sizeof(NAND_DevInfo0[0]))
503 #else
504  #define NAND_INFO0 NULL
505  #define NAND_INFO0_SZ 0
506 #endif
507 
508 #if defined(NAND_INFO_1_DEV_0)
509  #define NAND1_EVENT_HANDLER NAND_SignalEventHandler1
510 
511  void NAND_SignalEventHandler1 (uint32_t dev_num) {
512  switch (dev_num) {
513  case NAND1_DEV_NUM: ftl_DrvEvent (&nand1_dev); break;
514 
515  default: return;
516  }
517  }
518 
519  ARM_NAND_DEVICE NAND_DevInfo1[] = {
520  {&nand1_dev.PgLay,
521  NAND1_TYPE,
522  NAND1_DEV_NUM,
523  NAND1_PAGE_SIZE,
524  NAND1_BLOCK_COUNT,
525  NAND1_PAGE_COUNT,
526  NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
527  NAND_SEC_PAGE (NAND1_PAGE_SIZE),
528  NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
529  NAND_COL_CYCLES (NAND1_PAGE_SIZE),
530  NAND1_SW_ECC
531  },
532  };
533  #define NAND_INFO1 NAND_DevInfo1
534  #define NAND_INFO1_SZ (sizeof(NAND_DevInfo1) / sizeof(NAND_DevInfo1[0]))
535 #else
536  #define NAND_INFO1 NULL
537  #define NAND_INFO1_SZ 0
538 #endif
539 
540 /*----------------------------------------------------------------------------
541  * Drive N0: NAND Flash device NAND0 configuration
542  *---------------------------------------------------------------------------*/
543 #if (NAND0_ENABLE)
544  #if (NAND0_CACHE_RELOC == 1)
545  #define __AT_NAND0 __attribute__ ((at(NAND0_CACHE_ADDR)))
546  #else
547  #define __AT_NAND0
548  #endif
549 
550  /* NAND Cache Buffer for FAT, Page and Block Caching */
551  #define NAND0_CSZ ((NAND0_CACHE_SIZE + 1) * 1024 + \
552  (NAND0_PAGE_CACHE + 2) * NAND0_PAGE_SIZE + \
553  (NAND0_BLOCK_CACHE + 2) * NAND0_PAGE_COUNT)
554  #define NAND0_FSJBUF (NAND0_FAT_JOURNAL * 512)
555 
556  static uint32_t nand0_cache[NAND0_CSZ/4 + NAND0_FSJBUF/4] __AT_NAND0;
557  static PAGE_CACHE nand0_capg [NAND0_PAGE_CACHE + 1];
558  static BLOCK_CACHE nand0_cabl [NAND0_BLOCK_CACHE + 2];
559  static uint32_t nand0_ttsn [NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE)];
560 
561  /* NAND Flash Configuration */
562  static NAND_FTL_CFG nand0_cfg = {
563  /* Block Translation Table Space */
564  1,
565  NAND_BTT_SIZE (NAND0_BLOCK_COUNT),
566 
567  /* Data Space */
568  NAND_BTT_SIZE (NAND0_BLOCK_COUNT) + 1,
569  NAND0_BLOCK_COUNT - 1,
570 
571  /* Caching */
572  NAND0_BLOCK_CACHE + 2,
573  NAND0_PAGE_CACHE + 1,
574  NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE),
575 
576  /* Page buffer & Caches */
577  (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256],
578  &nand0_cabl[0],
579  (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+(NAND0_PAGE_CACHE+2)*NAND0_PAGE_SIZE/4],
580  &nand0_capg[0],
581  (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+NAND0_PAGE_SIZE/4],
582  &nand0_ttsn[0]
583  };
584 
585  /* NAND0 wrapper functions */
586  static uint32_t nand0_Init (uint32_t mode) {
587  return (ftl_Init (mode, &nand0_dev, NAND_INFO0, NAND_INFO0_SZ));
588  }
589  static uint32_t nand0_UnInit (uint32_t mode) {
590  return (ftl_UnInit (mode, &nand0_dev));
591  }
592  static uint32_t nand0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
593  uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand0_dev);
594  if (retv < 2) return (true);
595  else return (false);
596  }
597  static uint32_t nand0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
598  uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand0_dev);
599  if (retv < 2) return (true);
600  else return (false);
601  }
602  static uint32_t nand0_RdInfo (fsMediaInfo *info) {
603  return (ftl_ReadInfo (info, &nand0_dev));
604  }
605  static fsStatus nand0_DevCtrl (fsDevCtrlCode code, void *p) {
606  return (ftl_DevCtrl (code, p, &nand0_dev));
607  }
608 
609  FAT_DRV nand0_drv = {
610  nand0_Init,
611  nand0_UnInit,
612  nand0_RdSect,
613  nand0_WrSect,
614  nand0_RdInfo,
615  nand0_DevCtrl
616  };
617 #endif
618 
619 /*----------------------------------------------------------------------------
620  * Drive N1: NAND Flash device NAND1 configuration
621  *---------------------------------------------------------------------------*/
622 #if (NAND1_ENABLE)
623  #if (NAND1_CACHE_RELOC == 1)
624  #define __AT_NAND1 __attribute__ ((at(NAND1_CACHE_ADDR)))
625  #else
626  #define __AT_NAND1
627  #endif
628 
629  /* NAND Cache Buffer for FAT, Page and Block Caching */
630  #define NAND1_CSZ ((NAND1_CACHE_SIZE + 1) * 1024 + \
631  (NAND1_PAGE_CACHE + 2) * NAND1_PAGE_SIZE + \
632  (NAND1_BLOCK_CACHE + 2) * NAND1_PAGE_COUNT)
633  #define NAND1_FSJBUF (NAND1_FAT_JOURNAL * 512)
634 
635  static uint32_t nand1_cache[NAND1_CSZ/4 + NAND1_FSJBUF/4] __AT_NAND1;
636  static PAGE_CACHE nand1_capg [NAND1_PAGE_CACHE + 1];
637  static BLOCK_CACHE nand1_cabl [NAND1_BLOCK_CACHE + 2];
638  static uint32_t nand1_ttsn [NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE)];
639 
640  /* NAND Flash Configuration */
641  static NAND_FTL_CFG nand1_cfg = {
642  /* Block Translation Table Space */
643  1,
644  NAND_BTT_SIZE (NAND1_BLOCK_COUNT),
645 
646  /* Data Space */
647  NAND_BTT_SIZE (NAND1_BLOCK_COUNT) + 1,
648  NAND1_BLOCK_COUNT - 1,
649 
650  /* Caching */
651  NAND1_BLOCK_CACHE + 2,
652  NAND1_PAGE_CACHE + 1,
653  NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE),
654 
655  /* Page buffer & Caches */
656  (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256],
657  &nand1_cabl[0],
658  (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+(NAND1_PAGE_CACHE+2)*NAND1_PAGE_SIZE/4],
659  &nand1_capg[0],
660  (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+NAND1_PAGE_SIZE/4],
661  &nand1_ttsn[0],
662  };
663 
664  /* NAND1 wrapper functions */
665  static uint32_t nand1_Init (uint32_t mode) {
666  return (ftl_Init(mode, &nand1_dev, NAND_INFO1, NAND_INFO1_SZ));
667  }
668  static uint32_t nand1_UnInit (uint32_t mode) {
669  return (ftl_UnInit (mode, &nand1_dev));
670  }
671  static uint32_t nand1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
672  uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand1_dev);
673  if (retv < 2) return (true);
674  else return (false);
675  }
676  static uint32_t nand1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
677  uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand1_dev);
678  if (retv < 2) return (true);
679  else return (false);
680  }
681  static uint32_t nand1_RdInfo (fsMediaInfo *info) {
682  return (ftl_ReadInfo (info, &nand1_dev));
683  }
684  static fsStatus nand1_DevCtrl (fsDevCtrlCode code, void *p) {
685  return (ftl_DevCtrl (code, p, &nand1_dev));
686  }
687 
688  FAT_DRV nand1_drv = {
689  nand1_Init,
690  nand1_UnInit,
691  nand1_RdSect,
692  nand1_WrSect,
693  nand1_RdInfo,
694  nand1_DevCtrl
695  };
696 #endif
697 
698 /*----------------------------------------------------------------------------
699  * Drive R0: RAM device RAM0 configuration
700  *---------------------------------------------------------------------------*/
701 #if (RAM0_ENABLE)
702  static fsFAT_Volume ram0_vol;
703 
704  #if (RAM0_SIZE < 0x4A00)
705  #error "::File System:Drive:RAM requires minimum of 0x4A00 bytes of memory"
706  #endif
707 
708  #if (RAM0_RELOC == 1)
709  #define __AT_RAM0 __attribute__ ((at(RAM0_BASE_ADDR)))
710  #else
711  #define __AT_RAM0
712  #endif
713 
714  /* RAM0 Device data buffer */
715  static uint32_t ram0_buf[256 + (RAM0_SIZE/4)] __AT_RAM0;
716 
717  /* RAM0 device info */
718  static RAM_DEV ram0_dev = {
719  (uint8_t *)&ram0_buf[256],
720  RAM0_SIZE
721  };
722 
723  /* RAM0 wrapper functions */
724  static uint32_t ram0_Init (uint32_t mode) {
725  return (ram_Init (mode, &ram0_dev));
726  }
727  static uint32_t ram0_UnInit (uint32_t mode) {
728  return (ram_UnInit (mode, &ram0_dev));
729  }
730  static uint32_t ram0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
731  return (ram_ReadSector (sect, buf, cnt, &ram0_dev));
732  }
733  static uint32_t ram0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
734  return (ram_WriteSector (sect, buf, cnt, &ram0_dev));
735  }
736  static uint32_t ram0_RdInfo (fsMediaInfo *info) {
737  return (ram_ReadInfo (info, &ram0_dev));
738  }
739  static fsStatus ram0_DevCtrl (fsDevCtrlCode code, void *p) {
740  return (ram_DevCtrl (code, p, &ram0_dev));
741  }
742 
743  /* FAT RAM Driver Control Block */
744  FAT_DRV ram0_drv = {
745  ram0_Init,
746  ram0_UnInit,
747  ram0_RdSect,
748  ram0_WrSect,
749  ram0_RdInfo,
750  ram0_DevCtrl
751  };
752 #endif
753 
754 /*----------------------------------------------------------------------------
755  * Drive U0: USB Flash device USB0 configuration
756  *---------------------------------------------------------------------------*/
757 #if (USB0_ENABLE)
758  extern FAT_DRV usb0_drv;
759 
760  #if (USB0_FAT_JOURNAL)
761  static FSJOUR usb0_fsj;
762  #endif
763 
764  /* USB Cache Buffer for Data and FAT Caching */
765  static uint32_t usb0_cache[(USB0_CACHE_SIZE+1) * 256 + USB0_FAT_JOURNAL * 128];
766  static fsFAT_Volume usb0_vol;
767 
768  /* USB0 wrapper functions */
769  static uint32_t usb0_Init (uint32_t mode) {
770  return (FS_USBH_MSC_Initialize (0, mode));
771  }
772  static uint32_t usb0_UnInit (uint32_t mode) {
773  return (FS_USBH_MSC_Uninitialize (0, mode));
774  }
775  static uint32_t usb0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
776  return (FS_USBH_MSC_ReadSectors (0, sect, cnt, buf));
777  }
778  static uint32_t usb0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
779  return (FS_USBH_MSC_WriteSectors (0, sect, cnt, buf));
780  }
781  static uint32_t usb0_RdInfo (fsMediaInfo *info) {
782  return (FS_USBH_MSC_ReadInfo (0, info));
783  }
784  static fsStatus usb0_DevCtrl (fsDevCtrlCode code, void *p) {
785  return (FS_USBH_MSC_DeviceCtrl (0, code, p));
786  }
787 
788  FAT_DRV usb0_drv = {
789  usb0_Init,
790  usb0_UnInit,
791  usb0_RdSect,
792  usb0_WrSect,
793  usb0_RdInfo,
794  usb0_DevCtrl
795  };
796 #endif
797 
798 /*----------------------------------------------------------------------------
799  * Drive U1: USB Flash device USB1 configuration
800  *---------------------------------------------------------------------------*/
801 #if (USB1_ENABLE)
802  extern FAT_DRV usb1_drv;
803 
804  #if (USB1_FAT_JOURNAL)
805  static FSJOUR usb1_fsj;
806  #endif
807 
808  /* USB Cache Buffer for Data and FAT Caching */
809  static uint32_t usb1_cache[(USB1_CACHE_SIZE+1) * 256 + USB1_FAT_JOURNAL * 128];
810  static fsFAT_Volume usb1_vol;
811 
812  /* USB1 wrapper functions */
813  static uint32_t usb1_Init (uint32_t mode) {
814  return (FS_USBH_MSC_Initialize (1, mode));
815  }
816  static uint32_t usb1_UnInit (uint32_t mode) {
817  return (FS_USBH_MSC_Uninitialize (1, mode));
818  }
819  static uint32_t usb1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
820  return (FS_USBH_MSC_ReadSectors (1, sect, cnt, buf));
821  }
822  static uint32_t usb1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
823  return (FS_USBH_MSC_WriteSectors (1, sect, cnt, buf));
824  }
825  static uint32_t usb1_RdInfo (fsMediaInfo *info) {
826  return (FS_USBH_MSC_ReadInfo (1, info));
827  }
828  static fsStatus usb1_DevCtrl (fsDevCtrlCode code, void *p) {
829  return (FS_USBH_MSC_DeviceCtrl (1, code, p));
830  }
831 
832  FAT_DRV usb1_drv = {
833  usb1_Init,
834  usb1_UnInit,
835  usb1_RdSect,
836  usb1_WrSect,
837  usb1_RdInfo,
838  usb1_DevCtrl
839  };
840 #endif
841 
842 
843 /*-----------------------------------------------------------------------------
844  * An array of installed Device drivers
845  *----------------------------------------------------------------------------*/
846 FS_DEV fs_DevPool[FS_NDRV] = {
847 #if (NOR0_ENABLE)
848  { &nor0_vol, "F0", FS_EMB | NOR0_DEFAULT_DRIVE },
849 #endif
850 #if (NOR1_ENABLE)
851  { &nor1_vol, "F1", FS_EMB | NOR1_DEFAULT_DRIVE },
852 #endif
853 #if (MC0_ENABLE)
854  { &mc0_vol, "M0", FS_FAT | MC0_DEFAULT_DRIVE | FS_IOC },
855 #endif
856 #if (MC1_ENABLE)
857  { &mc1_vol, "M1", FS_FAT | MC1_DEFAULT_DRIVE | FS_IOC },
858 #endif
859 #if (NAND0_ENABLE)
860  { &nand0_vol,"N0", FS_FAT | NAND0_DEFAULT_DRIVE | FS_IOC },
861 #endif
862 #if (NAND1_ENABLE)
863  { &nand1_vol,"N1", FS_FAT | NAND1_DEFAULT_DRIVE | FS_IOC },
864 #endif
865 #if (RAM0_ENABLE)
866  { &ram0_vol, "R0", FS_FAT | RAM0_DEFAULT_DRIVE },
867 #endif
868 #if (USB0_ENABLE)
869  { &usb0_vol, "U0", FS_FAT | USB0_DEFAULT_DRIVE },
870 #endif
871 #if (USB1_ENABLE)
872  { &usb1_vol, "U1", FS_FAT | USB1_DEFAULT_DRIVE },
873 #endif
874 };
875 
876 /*-----------------------------------------------------------------------------
877  * Configure Flash File System
878  *----------------------------------------------------------------------------*/
879 void fs_config (void) {
880 
881 #if (NOR0_ENABLE)
882  nor0_vol.Drv = &CREATE_SYMBOL (Driver_NOR_, NOR0_NAME);
883  nor0_vol.BaseAdr = NOR0_BASE_ADDR;
884  nor0_vol.InitVal = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).erased_value * 0x01010101;
885  nor0_vol.NumSect = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_count;
886  nor0_vol.Size = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).size;
887  nor0_vol.DevCfg = CREATE_SYMBOL (NOR_Device_, NOR0_NAME).sector_info;
888 #endif
889 
890 #if (NOR1_ENABLE)
891  nor1_vol.Drv = &CREATE_SYMBOL (Driver_NOR_, NOR1_NAME);
892  nor1_vol.BaseAdr = NOR1_BASE_ADDR;
893  nor1_vol.InitVal = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).erased_value * 0x01010101;
894  nor1_vol.NumSect = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_count;
895  nor1_vol.Size = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).size;
896  nor1_vol.DevCfg = CREATE_SYMBOL (NOR_Device_, NOR1_NAME).sector_info;
897 #endif
898 
899 #if (MC0_ENABLE)
900  mc0_vol.Drv = &mc0_drv;
901  mc0_vol.CaBuf = mc0_cache;
902  mc0_vol.CaSize = MC0_CACHE_SIZE * 2;
903 
904  /* Register MCI driver for Native mode */
905  mc0_dev.DrvMci = &CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
906  mc0_dev.MCI_Callback = MC0_MCI_SignalEvent;
907  #if (MC0_SPI != 0)
908  /* Register SPI driver for SPI mode */
909  mc0_dev.DrvSpi = &CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
910  mc0_dev.SPI_Callback = MC0_SPI_SignalEvent;
911  #endif
912 
913  #if (MC0_FAT_JOURNAL)
914  /* Register file system journal */
915  mc0_fsj.buf = (uint8_t *)&mc0_cache[(MC0_CACHE_SIZE+1) * 256];
916  mc0_vol.fsj = &mc0_fsj;
917  mc0_vol.RsvdS = FAT_SECT_RSVD;
918  #else
919  mc0_vol.fsj = NULL;
920  mc0_vol.RsvdS = 0;
921  #endif
922 #endif
923 
924 #if (MC1_ENABLE)
925  mc1_vol.Drv = &mc1_drv;
926  mc1_vol.CaBuf = mc1_cache;
927  mc1_vol.CaSize = MC1_CACHE_SIZE * 2;
928 
929  /* Register MCI driver for Native mode */
930  mc1_dev.DrvMci = &CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
931  mc1_dev.MCI_Callback = MC1_MCI_SignalEvent;
932  #if (MC1_SPI != 0)
933  /* Register SPI driver for SPI mode */
934  mc1_dev.DrvSpi = &CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
935  mc1_dev.SPI_Callback = MC1_SPI_SignalEvent;
936  #endif
937 
938  #if (MC1_FAT_JOURNAL)
939  /* Register file system journal */
940  mc1_fsj.buf = (uint8_t *)&mc1_cache[(MC1_CACHE_SIZE+1) * 256];
941  mc1_vol.fsj = &mc1_fsj;
942  mc1_vol.RsvdS = FAT_SECT_RSVD;
943  #else
944  mc1_vol.fsj = NULL;
945  mc1_vol.RsvdS = 0;
946  #endif
947 #endif
948 
949 #if (NAND0_ENABLE)
950  nand0_vol.Drv = &nand0_drv;
951  nand0_vol.CaBuf = nand0_cache;
952  nand0_vol.CaSize = NAND0_CACHE_SIZE * 2;
953 
954  nand0_dev.Drv = &CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
955  nand0_dev.Dev = &NAND_DevInfo0[0];
956  nand0_dev.Cfg = &nand0_cfg;
957  nand0_dev.Callback = NAND0_EVENT_HANDLER;
958 
959  #if (NAND0_FAT_JOURNAL)
960  /* Register file system journal */
961  nand0_fsj.buf = (uint8_t *)&nand0_cache[NAND0_CSZ/4];
962  nand0_vol.fsj = &nand0_fsj;
963  nand0_vol.RsvdS = FAT_SECT_RSVD;
964  #else
965  nand0_vol.fsj = NULL;
966  nand0_vol.RsvdS = 0;
967  #endif
968 #endif
969 
970 #if (NAND1_ENABLE)
971  nand1_vol.Drv = &nand1_drv;
972  nand1_vol.CaBuf = nand1_cache;
973  nand1_vol.CaSize = NAND1_CACHE_SIZE * 2;
974 
975  nand1_dev.Drv = &CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
976  #if defined(NAND_INFO_0_DEV_1)
977  nand1_dev.Dev = &NAND_DevInfo0[1];
978  #else
979  nand1_dev.Dev = &NAND_DevInfo1[0];
980  #endif
981  nand1_dev.Cfg = &nand1_cfg;
982  nand1_dev.Callback = NAND1_EVENT_HANDLER;
983 
984  #if (NAND1_FAT_JOURNAL)
985  /* Register file system journal */
986  nand1_fsj.buf = (uint8_t *)&nand1_cache[NAND1_CSZ/4];
987  nand1_vol.fsj = &nand1_fsj;
988  nand1_vol.RsvdS = FAT_SECT_RSVD;
989  #else
990  nand1_vol.fsj = NULL;
991  nand1_vol.RsvdS = 0;
992  #endif
993 #endif
994 
995 #if (RAM0_ENABLE)
996  ram0_vol.Drv = &ram0_drv;
997  ram0_vol.CaBuf = ram0_buf;
998  ram0_vol.CaSize = 0;
999  ram0_vol.RsvdS = 0;
1000  ram0_vol.fsj = NULL;
1001 #endif
1002 
1003 #if (USB0_ENABLE)
1004  usb0_vol.Drv = &usb0_drv;
1005  usb0_vol.CaBuf = usb0_cache;
1006  usb0_vol.CaSize = USB0_CACHE_SIZE * 2;
1007 
1008  #if (USB0_FAT_JOURNAL)
1009  /* Register file system journal */
1010  usb0_fsj.buf = (uint8_t *)&usb0_cache[(USB0_CACHE_SIZE+1) * 256];
1011  usb0_vol.fsj = &usb0_fsj;
1012  usb0_vol.RsvdS = FAT_SECT_RSVD;
1013  #else
1014  usb0_vol.fsj = NULL;
1015  usb0_vol.RsvdS = 0;
1016  #endif
1017 #endif
1018 
1019 #if (USB1_ENABLE)
1020  usb1_vol.Drv = &usb1_drv;
1021  usb1_vol.CaSize = USB1_CACHE_SIZE * 2;
1022  usb1_vol.CaBuf = usb1_cache;
1023 
1024 
1025  #if (USB1_FAT_JOURNAL)
1026  /* Register file system journal */
1027  usb1_fsj.buf = (uint8_t *)&usb1_cache[(USB1_CACHE_SIZE+1) * 256];
1028  usb1_vol.fsj = &usb1_fsj;
1029  usb1_vol.RsvdS = FAT_SECT_RSVD;
1030  #else
1031  usb1_vol.fsj = NULL;
1032  usb1_vol.RsvdS = 0;
1033  #endif
1034 #endif
1035 
1037 }
1038 
1039 
1040 #if (EFS_USE == 0)
1041  /* Empty functions to reduce image size when EFS not used */
1042  bool efs_path_valid (const char *path) { return (false); }
1043  int32_t efs_handle_get (fsEFS_Volume *vol) { return (-1); }
1044  fsStatus efs_open (int32_t handle, const char *fn, int openmode) { return (fsError); }
1045  fsStatus efs_close (int32_t handle) { return (fsError); }
1046  int32_t efs_read (int32_t handle, uint8_t *buf, uint32_t len) { return (0); }
1047  int32_t efs_write (int32_t handle, const uint8_t *buf, uint32_t len) { return (-1); }
1048  fsStatus efs_flush (int32_t handle) { return (fsError); }
1049  int32_t efs_flen (int32_t handle) { return (-1); }
1050  fsStatus efs_seek (int32_t handle, uint32_t pos) { return (fsError); }
1051  fsStatus efs_ffind (int32_t handle, fsFileInfo *info) { return (fsError); }
1052  fsStatus efs_find (int32_t handle, const char *fname) { return (fsError); }
1053  fsStatus efs_delete(int32_t handle) { return (fsError); }
1054  int32_t efs_analyse(fsEFS_Volume *vol) { return (0); }
1055  fsStatus efs_check (fsEFS_Volume *vol) { return (fsError); }
1056  fsStatus efs_format (fsEFS_Volume *vol) { return (fsError); }
1057  uint32_t efs_free (fsEFS_Volume *vol) { return (0); }
1058  fsStatus efs_defrag (fsEFS_Volume *vol) { return (fsError); }
1059 #endif /* EFS_USE */
1060 
1061 #if (FAT_USE == 0)
1062  /* Empty functions to reduce image size when FAT not used */
1063  int32_t fat_handle_get (fsFAT_Volume *vol) { return (-1); }
1064  fsStatus fat_open (int32_t handle, const char *path, int32_t openmode){ return (fsError); }
1065  fsStatus fat_close(int32_t handle) { return (fsError); }
1066  int32_t fat_read (int32_t handle, uint8_t *buf, uint32_t len) { return(-1); }
1067  int32_t fat_write(int32_t handle, const uint8_t *buf, uint32_t len) { return(-1); }
1068  int32_t fat_flen (int32_t handle) { return (-1); }
1069  fsStatus fat_seek (int32_t handle, uint32_t pos) { return(fsError); }
1070  int32_t fat_init (fsFAT_Volume *vol) { return (0); }
1071  fsStatus fat_ffind (const char *fn, fsFileInfo *info, fsFAT_Volume *vol) { return (fsError); }
1072  fsStatus fat_delete (const char *fn, fsFAT_Volume *vol) { return(fsError); }
1073  fsStatus fat_rename (const char *path, const char *newname, fsFAT_Volume *vol) { return (fsError); }
1074  fsStatus fat_format (fsFAT_Volume *vol, const char *opt) { return (fsError); }
1075  uint64_t fat_free (fsFAT_Volume *vol) { return (0); }
1076  fsStatus fat_attrib (fsFAT_Volume *vol, const char *fn, uint32_t attrib) { return (fsError); }
1077  fsStatus fat_read_label (fsFAT_Volume *vol, char *buf) { return (fsError); }
1078  fsStatus fat_read_serial (fsFAT_Volume *vol, uint32_t *serial) { return (fsError); }
1079  fsStatus fat_mkdir (const char *path, fsFAT_Volume *vol) { return (fsError); }
1080  uint32_t fat_jour_init (fsFAT_Volume *vi) { return (true); }
1081 #else
1082  #if (FSJ_USE == 0)
1083  /* Empty functions to reduce image size when journal not used */
1084  uint32_t fat_jour_init (fsFAT_Volume *vol) { return (true); }
1085  uint32_t fat_jour_prep (fsFAT_Volume *vol) { return (true); }
1086  uint32_t fsj_set_space (FSJOUR *fsj, uint32_t start_sect, uint32_t cnt) {
1087  return (false); }
1088  uint32_t fsj_write (FSJOUR *fsj, uint32_t sect, uint32_t cnt, uint8_t *buf) {
1089  return (false); }
1090  uint32_t fsj_init (FSJOUR *fsj, FAT_DRV *drv) { return (false); }
1091  #endif
1092 #endif /* FAT_USE */
1093 
1094 #if (FAT_NAME_CACHE_SIZE == 0)
1095  uint32_t elink_init (void) { return (1); }
1096  uint32_t elink_init_path (const char *drvLet) { return (0xFF); }
1097  uint32_t elink_flush (const char *drvLet) { return (1); }
1098  uint32_t elink_cmd (uint32_t i, uint32_t j) { return (0); }
1099  uint32_t elink_insert (void *p, uint32_t i, uint32_t j) { return (1); }
1100  uint32_t elink_delete (void *p, uint32_t i) { return (0); }
1101  uint32_t elink_scan (uint32_t i, void **pp, uint32_t j) { return (1); }
1102 #endif
1103 
1104 
1105 /*-----------------------------------------------------------------------------
1106  * Retarget low level functions
1107  *----------------------------------------------------------------------------*/
1108 
1109 #pragma import(__use_no_semihosting_swi)
1110 
1111 #ifndef STDIO_DISABLE
1112 
1113 /* Standard IO device handles. */
1114 #define STDIN 0x8001
1115 #define STDOUT 0x8002
1116 #define STDERR 0x8003
1117 
1118 /* Standard IO device name defines. */
1119 const char __stdin_name[] = "STDIN";
1120 const char __stdout_name[] = "STDOUT";
1121 const char __stderr_name[] = "STDERR";
1122 
1123 #if (__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
1124 /* Redirected to ITM by default */
1125 extern int stdio_getc (void);
1126 extern int stdio_putc (int ch);
1127 #else
1128 /* Dummy implementation */
1129 __weak int stdio_getc (void) { return (-1); }
1130 __weak int stdio_putc (int ch) {}
1131 #endif
1132 
1133 #endif
1134 
1135 
1148 __weak void _ttywrch (int ch) {
1149 #ifndef STDIO_DISABLE
1150 #ifndef STDOUT_LF_CR_DISABLE
1151  if (ch == '\n') stdio_putc ('\r');
1152 #endif
1153  stdio_putc (ch);
1154 #endif
1155 }
1156 
1157 
1173 FILEHANDLE _sys_open (const char *name, int openmode) {
1174  /* Register standard Input Output devices. */
1175 #ifndef STDIO_DISABLE
1176  if (strcmp(name, "STDIN") == 0) {
1177  return (STDIN);
1178  }
1179  if (strcmp(name, "STDOUT") == 0) {
1180  return (STDOUT);
1181  }
1182  if (strcmp(name, "STDERR") == 0) {
1183  return (STDERR);
1184  }
1185 #endif
1186  return (__sys_open (name, openmode));
1187 }
1188 
1189 
1201 int _sys_close (FILEHANDLE fh) {
1202 #ifndef STDIO_DISABLE
1203  switch (fh) {
1204  case STDOUT:
1205  case STDIN:
1206  case STDERR:
1207  return (0);
1208  }
1209 #endif
1210  return (__sys_close (fh));
1211 }
1212 
1213 
1232 int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) {
1233 #ifndef STDIO_DISABLE
1234  int ch;
1235 
1236  switch (fh) {
1237  case STDOUT:
1238  /* Standard Output device. */
1239  for ( ; len; len--) {
1240  ch = *buf++;
1241 #ifndef STDOUT_LF_CR_DISABLE
1242  if (ch == '\n') stdio_putc ('\r');
1243 #endif
1244  stdio_putc (ch);
1245  }
1246  return (0);
1247  case STDIN:
1248  case STDERR:
1249  return (-1);
1250  }
1251 #endif
1252  return (__sys_write (fh, buf, len));
1253 }
1254 
1255 
1283 int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) {
1284 #ifndef STDIO_DISABLE
1285  int ch;
1286 
1287  switch (fh) {
1288  case STDIN:
1289  /* Standard Input device. */
1290  do {
1291  ch = stdio_getc ();
1292  } while (ch < 0);
1293  *buf++ = (uint8_t)ch;
1294  len--;
1295  for ( ; len; len--) {
1296  ch = stdio_getc ();
1297  if (ch < 0) break;
1298  *buf++ = (uint8_t)ch;
1299  }
1300  return (len);
1301  case STDOUT:
1302  case STDERR:
1303  return (-1);
1304  }
1305 #endif
1306  return (__sys_read (fh, buf, len));
1307 }
1308 
1309 
1325 int _sys_istty (FILEHANDLE fh) {
1326 #ifndef STDIO_DISABLE
1327  switch (fh) {
1328  case STDOUT:
1329  case STDIN:
1330  case STDERR:
1331  return (1);
1332  }
1333 #endif
1334  return (0);
1335 }
1336 
1337 
1352 int _sys_seek (FILEHANDLE fh, long pos) {
1353 #ifndef STDIO_DISABLE
1354  switch (fh) {
1355  case STDOUT:
1356  case STDIN:
1357  case STDERR:
1358  return (-1);
1359  }
1360 #endif
1361  return (__sys_seek (fh, pos));
1362 }
1363 
1364 
1370 int _sys_ensure (FILEHANDLE fh) {
1371 #ifndef STDIO_DISABLE
1372  switch (fh) {
1373  case STDOUT:
1374  case STDIN:
1375  case STDERR:
1376  return (-1);
1377  }
1378 #endif
1379  return (__sys_ensure (fh));
1380 }
1381 
1382 
1398 long _sys_flen (FILEHANDLE fh) {
1399 #ifndef STDIO_DISABLE
1400  switch (fh) {
1401  case STDOUT:
1402  case STDIN:
1403  case STDERR:
1404  return (0);
1405  }
1406 #endif
1407  return (__sys_flen (fh));
1408 }
1409 
1410 
1427 __weak void _sys_exit (int return_code) {
1428  /* Endless loop. */
1429  while (1);
1430 }