12 #include "rl_fs_lib.h"
22 #error "File System does not work with MicroLIB"
29 #define NOR0_DEFAULT_DRIVE 0
34 #define NOR1_DEFAULT_DRIVE 0
39 #define RAM0_DEFAULT_DRIVE 0
45 #define MC0_DEFAULT_DRIVE 0
51 #define MC1_DEFAULT_DRIVE 0
56 #define NAND0_ENABLE 0
57 #define NAND0_DEFAULT_DRIVE 0
62 #define NAND1_ENABLE 0
63 #define NAND1_DEFAULT_DRIVE 0
69 #define USB0_DEFAULT_DRIVE 0
75 #define USB1_DEFAULT_DRIVE 0
79 #ifndef FAT_MAX_OPEN_FILES
80 #define FAT_MAX_OPEN_FILES NUM_FILES
82 #ifndef EFS_MAX_OPEN_FILES
83 #define EFS_MAX_OPEN_FILES NUM_FILES
89 #define FS_NDRV (NOR0_ENABLE + NOR1_ENABLE + \
91 MC0_ENABLE + MC1_ENABLE + \
92 USB0_ENABLE + USB1_ENABLE + \
93 NAND0_ENABLE + NAND1_ENABLE)
95 #error "No drive enabled, File System requires at least on component ::File System:Drive"
99 #define FS_FAT_NDRV (RAM0_ENABLE + \
100 MC0_ENABLE + MC1_ENABLE + \
101 USB0_ENABLE + USB1_ENABLE + \
102 NAND0_ENABLE + NAND1_ENABLE)
105 #define FS_NAND_NDRV (NAND0_ENABLE + NAND1_ENABLE)
108 #define __DEF ((NOR0_DEFAULT_DRIVE & NOR0_ENABLE) + \
109 (NOR1_DEFAULT_DRIVE & NOR1_ENABLE) + \
110 (RAM0_DEFAULT_DRIVE & RAM0_ENABLE) + \
111 (MC0_DEFAULT_DRIVE & MC0_ENABLE) + \
112 (MC1_DEFAULT_DRIVE & MC1_ENABLE) + \
113 (USB0_DEFAULT_DRIVE & USB0_ENABLE) + \
114 (USB1_DEFAULT_DRIVE & USB1_ENABLE) + \
115 (NAND0_DEFAULT_DRIVE & NAND0_ENABLE) + \
116 (NAND1_DEFAULT_DRIVE & NAND1_ENABLE))
118 #error "Default ::File System:Drive not specified"
120 #error "Multiple default ::File System:Drive: enabled"
124 #if (MC0_ENABLE && MC1_ENABLE)
125 #if ((MC0_SPI == 0) && (MC1_SPI == 0))
126 #if (MC0_MCI_DRIVER == MC1_MCI_DRIVER)
127 #error "::File System:Drive:Memory Card: MCI ports for different drives must be different"
129 #elif ((MC0_SPI == 1) && (MC1_SPI == 1))
130 #if (MC0_SPI_DRIVER == MC1_SPI_DRIVER)
131 #error "::File System:Drive:Memory Card: SPI ports for different drives must be different"
137 #define EFS_USE (NOR0_ENABLE + NOR1_ENABLE)
138 #define FAT_USE (RAM0_ENABLE + MC0_ENABLE + MC1_ENABLE + USB0_ENABLE + USB1_ENABLE + NAND0_ENABLE + NAND1_ENABLE)
141 #define FSJ_USE (MC0_ENABLE * MC0_FAT_JOURNAL + \
142 MC1_ENABLE * MC1_FAT_JOURNAL + \
143 USB0_ENABLE * USB0_FAT_JOURNAL + \
144 USB1_ENABLE * USB1_FAT_JOURNAL + \
145 NAND0_ENABLE * NAND0_FAT_JOURNAL + \
146 NAND1_ENABLE * NAND1_FAT_JOURNAL)
149 #define FAT_SECT_RSVD 64
153 extern volatile int _stream_list_lock;
154 #define STREAM_LIST_LOCK _stream_list_lock;
156 #define STREAM_LIST_LOCK
160 #define FAT_HANDLE_COUNT ((FAT_MAX_OPEN_FILES > 0) ? FAT_MAX_OPEN_FILES : 1)
165 #define EFS_HANDLE_COUNT ((EFS_MAX_OPEN_FILES > 0) ? EFS_MAX_OPEN_FILES : 1)
181 #if (FAT_NAME_CACHE_SIZE == 0)
186 #if (FAT_NAME_CACHE_RELOC == 1)
187 #define __AT_FAT_NAME __attribute__ ((at(FAT_NAME_CACHE_ADDR)))
189 #define __AT_FAT_NAME
193 #define FAT_NAME_MAX_DEPTH 8
196 #define FAT_NAME_CB_SZ (16)
197 #define FAT_NAME_CB_POOL_SZ (FAT_NAME_CB_SZ * FS_FAT_NDRV)
200 #define FAT_NAME_DEPTH_CB_SZ (8)
201 #define FAT_NAME_DEPTH_POOL_SZ (FAT_NAME_DEPTH_CB_SZ * FAT_NAME_MAX_DEPTH * FS_FAT_NDRV)
204 #define FAT_NAME_LINK_SZ (48)
205 #define FAT_NAME_LINK_POOL_SZ (FAT_NAME_LINK_SZ * FAT_NAME_CACHE_SIZE)
208 #define FAT_NAME_POOL_SIZE (FAT_NAME_CB_POOL_SZ + \
209 FAT_NAME_DEPTH_POOL_SZ + \
210 FAT_NAME_LINK_POOL_SZ)
212 static uint32_t fat_name_pool[FAT_NAME_POOL_SIZE/4] __AT_FAT_NAME;
222 #define EXPAND_SYMBOL(name, port) name##port
223 #define CREATE_SYMBOL(name, port) EXPAND_SYMBOL(name, port)
229 static fsEFS_Volume nor0_vol;
232 static void NOR0_DriverEvent (uint32_t event) {
233 efs_DrvEvent (event, &nor0_vol);
236 extern ARM_DRIVER_FLASH
CREATE_SYMBOL (Driver_Flash, NOR0_DRIVER);
243 static fsEFS_Volume nor1_vol;
246 static void NOR1_DriverEvent (uint32_t event) {
247 efs_DrvEvent (event, &nor1_vol);
250 extern ARM_DRIVER_FLASH
CREATE_SYMBOL (Driver_Flash, NOR1_DRIVER);
257 static fsFAT_Volume mc0_vol;
258 static MCI_DEV mc0_dev;
260 #if (MC0_FAT_JOURNAL)
261 static FSJOUR mc0_fsj;
264 #if (MC0_CACHE_RELOC == 1)
265 #define __AT_MC0 __attribute__ ((at(MC0_CACHE_ADDR)))
271 static uint32_t mc0_cache[(MC0_CACHE_SIZE+1) * 256 + MC0_FAT_JOURNAL * 128] __AT_MC0;
275 #define MC0_INIT(m) mc_mci_Init (m, &mc0_dev)
276 #define MC0_UNINIT(m) mc_mci_UnInit (m, &mc0_dev)
277 #define MC0_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc0_dev)
278 #define MC0_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc0_dev)
279 #define MC0_RDINFO(i) mc_mci_ReadInfo (i, &mc0_dev)
280 #define MC0_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc0_dev)
282 extern ARM_DRIVER_MCI
CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
285 #define MC0_INIT(m) mc_spi_Init (m, &mc0_dev)
286 #define MC0_UNINIT(m) mc_spi_UnInit (m, &mc0_dev)
287 #define MC0_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc0_dev)
288 #define MC0_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc0_dev)
289 #define MC0_RDINFO(i) mc_spi_ReadInfo (i, &mc0_dev)
290 #define MC0_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc0_dev)
292 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
296 static uint32_t mc0_Init (uint32_t mode) {
297 return (MC0_INIT (mode));
299 static uint32_t mc0_UnInit (uint32_t mode) {
300 return (MC0_UNINIT (mode));
302 static uint32_t mc0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
303 return (MC0_RDSEC (sect, buf, cnt));
305 static uint32_t mc0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
306 return (MC0_WRSEC (sect, buf, cnt));
309 return (MC0_RDINFO (info));
312 return (MC0_DEVCTRL (code, p));
327 static void MC0_MCI_SignalEvent (uint32_t event) {
328 mc_mci_DrvEvent (event, &mc0_dev);
332 static void MC0_SPI_SignalEvent (uint32_t event) {
333 mc_spi_DrvEvent (event, &mc0_dev);
342 static fsFAT_Volume mc1_vol;
343 static MCI_DEV mc1_dev;
345 #if (MC1_FAT_JOURNAL)
346 static FSJOUR mc1_fsj;
349 #if (MC1_CACHE_RELOC == 1)
350 #define __AT_MC1 __attribute__ ((at(MC1_CACHE_ADDR)))
356 static uint32_t mc1_cache[(MC1_CACHE_SIZE+1) * 256 + MC1_FAT_JOURNAL * 128] __AT_MC1;
360 #define MC1_INIT(m) mc_mci_Init (m, &mc1_dev)
361 #define MC1_UNINIT(m) mc_mci_UnInit (m, &mc1_dev)
362 #define MC1_RDSEC(s,b,c) mc_mci_ReadSector (s, b, c, &mc1_dev)
363 #define MC1_WRSEC(s,b,c) mc_mci_WriteSector (s, b, c, &mc1_dev)
364 #define MC1_RDINFO(i) mc_mci_ReadInfo (i, &mc1_dev)
365 #define MC1_DEVCTRL(c,p) mc_mci_DevCtrl (c, p, &mc1_dev)
367 extern ARM_DRIVER_MCI
CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
370 #define MC1_INIT(m) mc_spi_Init (m, &mc1_dev)
371 #define MC1_UNINIT(m) mc_spi_UnInit (m, &mc1_dev)
372 #define MC1_RDSEC(s,b,c) mc_spi_ReadSector (s, b, c, &mc1_dev)
373 #define MC1_WRSEC(s,b,c) mc_spi_WriteSector (s, b, c, &mc1_dev)
374 #define MC1_RDINFO(i) mc_spi_ReadInfo (i, &mc1_dev)
375 #define MC1_DEVCTRL(c,p) mc_spi_DevCtrl (c, p, &mc1_dev)
377 extern ARM_DRIVER_SPI
CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
381 static uint32_t mc1_Init (uint32_t mode) {
382 return (MC1_INIT (mode));
384 static uint32_t mc1_UnInit (uint32_t mode) {
385 return (MC1_UNINIT (mode));
387 static uint32_t mc1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
388 return (MC1_RDSEC (sect, buf, cnt));
390 static uint32_t mc1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
391 return (MC1_WRSEC (sect, buf, cnt));
394 return (MC1_RDINFO (info));
397 return (MC1_DEVCTRL (code, p));
412 static void MC1_MCI_SignalEvent (uint32_t event) {
413 mc_mci_DrvEvent (event, &mc1_dev);
417 static void MC1_SPI_SignalEvent (uint32_t event) {
418 mc_spi_DrvEvent (event, &mc1_dev);
427 static NAND_MEDIA_HANDLE nand0_media_handle;
428 static NAND_FTL_DEV nand0_handle;
432 static NAND_MEDIA_HANDLE nand1_media_handle;
433 static NAND_FTL_DEV nand1_handle;
436 #if (NAND0_ENABLE || NAND1_ENABLE)
437 extern void nand_DrvEvent (uint32_t event, NAND_MEDIA_HANDLE *h);
438 extern void nand_MediaEvent (NAND_FTL_DEV *ftl);
441 #ifdef RTE_FileSystem_Drive_NAND_0
443 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
445 static NAND_HW_DRIVER nand0_hw_driver;
448 #if ((NAND1_ENABLE) && (NAND1_DRIVER == NAND0_DRIVER))
449 #if (NAND1_DEV_NUM == NAND0_DEV_NUM)
450 #error "::File System:Drive:NAND: NAND ports for different drives must be different"
453 #define NAND0_DEVICE1
456 #define NAND1_MEDIA_EVENT_HANDLER NAND0_Media_SignalEventHandler
457 #define NAND1_HW_EVENT_HANDLER NAND0_HW_SignalEventHandler
458 #define NAND1_HW_DRIVER nand0_hw_driver
459 #define NAND1_DRIVER_CONFIG 0
462 static void NAND0_HW_SignalEventHandler (uint32_t dev_num, uint32_t event) {
465 case NAND0_DEV_NUM: nand_DrvEvent (event, &nand0_media_handle);
break;
467 #if defined(NAND0_DEVICE1)
468 case NAND1_DEV_NUM: nand_DrvEvent (event, &nand1_media_handle);
break;
475 static void NAND0_Media_SignalEventHandler (uint32_t dev_num, uint32_t event) {
478 case NAND0_DEV_NUM: nand_MediaEvent (&nand0_handle);
break;
480 #if defined(NAND0_DEVICE1)
481 case NAND1_DEV_NUM: nand_MediaEvent (&nand1_handle);
break;
490 #ifdef RTE_FileSystem_Drive_NAND_1
491 #if (((NAND0_ENABLE == 0) && NAND1_ENABLE) || ((NAND0_ENABLE && NAND1_ENABLE) && (NAND1_DRIVER != NAND0_DRIVER)))
492 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
494 static NAND_HW_DRIVER nand1_hw_driver;
497 #define NAND1_MEDIA_EVENT_HANDLER NAND1_Media_SignalEventHandler
498 #define NAND1_HW_EVENT_HANDLER NAND1_HW_SignalEventHandler
499 #define NAND1_HW_DRIVER nand1_hw_driver
500 #define NAND1_DRIVER_CONFIG 1
502 static void NAND1_HW_SignalEventHandler (uint32_t dev_num, uint32_t event) {
504 case NAND1_DEV_NUM: nand_DrvEvent (event, &nand1_media_handle);
break;
510 static void NAND1_Media_SignalEventHandler (uint32_t dev_num, uint32_t event) {
513 case NAND1_DEV_NUM: nand_MediaEvent (&nand1_handle);
break;
526 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
528 #if (NAND0_CACHE_RELOC == 1)
529 #define __AT_NAND0 __attribute__ ((at(NAND0_CACHE_ADDR)))
535 #define NAND0_CSZ ((NAND0_CACHE_SIZE + 1) * 1024 + \
536 (NAND0_PAGE_CACHE + 2) * NAND0_PAGE_SIZE + \
537 (NAND0_BLOCK_CACHE + 2) * NAND0_PAGE_COUNT)
538 #define NAND0_FSJBUF (NAND0_FAT_JOURNAL * 512)
540 static uint32_t nand0_cache[NAND0_CSZ/4 + NAND0_FSJBUF/4] __AT_NAND0;
541 static PAGE_CACHE nand0_capg [NAND0_PAGE_CACHE + 1];
542 static BLOCK_CACHE nand0_cabl [NAND0_BLOCK_CACHE + 2];
543 static uint32_t nand0_ttsn [NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE)];
545 static fsFAT_Volume nand0_vol;
546 #if (NAND0_FAT_JOURNAL)
547 static FSJOUR nand0_fsj;
550 const NAND_DEVICE nand0_device = {
557 NAND_SEC_BLOCK (NAND0_PAGE_COUNT, NAND0_PAGE_SIZE),
558 NAND_SEC_PAGE (NAND0_PAGE_SIZE),
559 NAND_ROW_CYCLES (NAND0_BLOCK_COUNT, NAND0_PAGE_COUNT),
560 NAND_COL_CYCLES (NAND0_PAGE_SIZE),
565 static NAND_FTL_CFG nand0_cfg = {
568 NAND_BTT_SIZE (NAND0_BLOCK_COUNT),
571 NAND_BTT_SIZE (NAND0_BLOCK_COUNT) + 1,
572 NAND0_BLOCK_COUNT - 1,
575 NAND0_BLOCK_CACHE + 2,
576 NAND0_PAGE_CACHE + 1,
577 NAND_TSN_SIZE(NAND0_BLOCK_COUNT, NAND0_PAGE_SIZE),
580 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256],
582 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+(NAND0_PAGE_CACHE+2)*NAND0_PAGE_SIZE/4],
584 (uint8_t *)&nand0_cache[(NAND0_CACHE_SIZE+1)*256+NAND0_PAGE_SIZE/4],
589 static uint32_t nand0_Init (uint32_t mode) {
590 return (ftl_Init (mode, &nand0_handle));
592 static uint32_t nand0_UnInit (uint32_t mode) {
593 return (ftl_UnInit (mode, &nand0_handle));
595 static uint32_t nand0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
596 uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand0_handle);
597 if (retv < 2)
return (
true);
600 static uint32_t nand0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
601 uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand0_handle);
602 if (retv < 2)
return (
true);
606 return (ftl_ReadInfo (info, &nand0_handle));
609 return (ftl_DevCtrl (code, p, &nand0_handle));
612 FAT_DRV nand0_drv = {
626 #if defined(NAND1_DEVICE0)
627 extern ARM_DRIVER_NAND
CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
630 #if (NAND1_CACHE_RELOC == 1)
631 #define __AT_NAND1 __attribute__ ((at(NAND1_CACHE_ADDR)))
637 #define NAND1_CSZ ((NAND1_CACHE_SIZE + 1) * 1024 + \
638 (NAND1_PAGE_CACHE + 2) * NAND1_PAGE_SIZE + \
639 (NAND1_BLOCK_CACHE + 2) * NAND1_PAGE_COUNT)
640 #define NAND1_FSJBUF (NAND1_FAT_JOURNAL * 512)
642 static uint32_t nand1_cache[NAND1_CSZ/4 + NAND1_FSJBUF/4] __AT_NAND1;
643 static PAGE_CACHE nand1_capg [NAND1_PAGE_CACHE + 1];
644 static BLOCK_CACHE nand1_cabl [NAND1_BLOCK_CACHE + 2];
645 static uint32_t nand1_ttsn [NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE)];
647 static fsFAT_Volume nand1_vol;
648 #if (NAND1_FAT_JOURNAL)
649 static FSJOUR nand1_fsj;
652 const NAND_DEVICE nand1_device = {
659 NAND_SEC_BLOCK (NAND1_PAGE_COUNT, NAND1_PAGE_SIZE),
660 NAND_SEC_PAGE (NAND1_PAGE_SIZE),
661 NAND_ROW_CYCLES (NAND1_BLOCK_COUNT, NAND1_PAGE_COUNT),
662 NAND_COL_CYCLES (NAND1_PAGE_SIZE),
667 static NAND_FTL_CFG nand1_cfg = {
670 NAND_BTT_SIZE (NAND1_BLOCK_COUNT),
673 NAND_BTT_SIZE (NAND1_BLOCK_COUNT) + 1,
674 NAND1_BLOCK_COUNT - 1,
677 NAND1_BLOCK_CACHE + 2,
678 NAND1_PAGE_CACHE + 1,
679 NAND_TSN_SIZE(NAND1_BLOCK_COUNT, NAND1_PAGE_SIZE),
682 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256],
684 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+(NAND1_PAGE_CACHE+2)*NAND1_PAGE_SIZE/4],
686 (uint8_t *)&nand1_cache[(NAND1_CACHE_SIZE+1)*256+NAND1_PAGE_SIZE/4],
691 static uint32_t nand1_Init (uint32_t mode) {
692 return (ftl_Init(mode, &nand1_handle));
694 static uint32_t nand1_UnInit (uint32_t mode) {
695 return (ftl_UnInit (mode, &nand1_handle));
697 static uint32_t nand1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
698 uint32_t retv = ftl_ReadSect (sect, buf, cnt, &nand1_handle);
699 if (retv < 2)
return (
true);
702 static uint32_t nand1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
703 uint32_t retv = ftl_WriteSect (sect, buf, cnt, &nand1_handle);
704 if (retv < 2)
return (
true);
708 return (ftl_ReadInfo (info, &nand1_handle));
711 return (ftl_DevCtrl (code, p, &nand1_handle));
714 FAT_DRV nand1_drv = {
728 static fsFAT_Volume ram0_vol;
730 #if (RAM0_SIZE < 0x4A00)
731 #error "::File System:Drive:RAM requires minimum of 0x4A00 bytes of memory"
734 #if (RAM0_RELOC == 1)
735 #define __AT_RAM0 __attribute__ ((at(RAM0_BASE_ADDR)))
741 static uint32_t ram0_buf[256 + (RAM0_SIZE/4)] __AT_RAM0;
744 static RAM_DEV ram0_dev = {
745 (uint8_t *)&ram0_buf[256],
750 static uint32_t ram0_Init (uint32_t mode) {
751 return (ram_Init (mode, &ram0_dev));
753 static uint32_t ram0_UnInit (uint32_t mode) {
754 return (ram_UnInit (mode, &ram0_dev));
756 static uint32_t ram0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
757 return (ram_ReadSector (sect, buf, cnt, &ram0_dev));
759 static uint32_t ram0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
760 return (ram_WriteSector (sect, buf, cnt, &ram0_dev));
763 return (ram_ReadInfo (info, &ram0_dev));
766 return (ram_DevCtrl (code, p, &ram0_dev));
784 extern FAT_DRV usb0_drv;
786 #if (USB0_FAT_JOURNAL)
787 static FSJOUR usb0_fsj;
791 static uint32_t usb0_cache[(USB0_CACHE_SIZE+1) * 256 + USB0_FAT_JOURNAL * 128];
792 static fsFAT_Volume usb0_vol;
795 static uint32_t usb0_Init (uint32_t mode) {
796 return (FS_USBH_MSC_Initialize (0, mode));
798 static uint32_t usb0_UnInit (uint32_t mode) {
799 return (FS_USBH_MSC_Uninitialize (0, mode));
801 static uint32_t usb0_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
802 return (FS_USBH_MSC_ReadSectors (0, sect, cnt, buf));
804 static uint32_t usb0_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
805 return (FS_USBH_MSC_WriteSectors (0, sect, cnt, buf));
808 return (FS_USBH_MSC_ReadInfo (0, info));
811 return (FS_USBH_MSC_DeviceCtrl (0, code, p));
828 extern FAT_DRV usb1_drv;
830 #if (USB1_FAT_JOURNAL)
831 static FSJOUR usb1_fsj;
835 static uint32_t usb1_cache[(USB1_CACHE_SIZE+1) * 256 + USB1_FAT_JOURNAL * 128];
836 static fsFAT_Volume usb1_vol;
839 static uint32_t usb1_Init (uint32_t mode) {
840 return (FS_USBH_MSC_Initialize (1, mode));
842 static uint32_t usb1_UnInit (uint32_t mode) {
843 return (FS_USBH_MSC_Uninitialize (1, mode));
845 static uint32_t usb1_RdSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
846 return (FS_USBH_MSC_ReadSectors (1, sect, cnt, buf));
848 static uint32_t usb1_WrSect (uint32_t sect, uint8_t *buf, uint32_t cnt) {
849 return (FS_USBH_MSC_WriteSectors (1, sect, cnt, buf));
852 return (FS_USBH_MSC_ReadInfo (1, info));
855 return (FS_USBH_MSC_DeviceCtrl (1, code, p));
909 nor0_vol.Callback = &NOR0_DriverEvent;
914 nor1_vol.Callback = &NOR1_DriverEvent;
918 mc0_vol.Drv = &mc0_drv;
919 mc0_vol.CaBuf = mc0_cache;
920 mc0_vol.CaSize = MC0_CACHE_SIZE * 2;
922 mc0_dev.Instance = 0;
925 mc0_dev.DrvMci = &
CREATE_SYMBOL (Driver_MCI, MC0_MCI_DRIVER);
926 mc0_dev.MCI_Callback = MC0_MCI_SignalEvent;
929 mc0_dev.DrvSpi = &
CREATE_SYMBOL (Driver_SPI, MC0_SPI_DRIVER);
930 mc0_dev.SPI_Callback = MC0_SPI_SignalEvent;
932 #error "Memory Card Interface Mode Invalid in FS_Config_MC_0.h"
935 #if (MC0_FAT_JOURNAL)
937 mc0_fsj.buf = (uint8_t *)&mc0_cache[(MC0_CACHE_SIZE+1) * 256];
938 mc0_vol.fsj = &mc0_fsj;
947 mc1_vol.Drv = &mc1_drv;
948 mc1_vol.CaBuf = mc1_cache;
949 mc1_vol.CaSize = MC1_CACHE_SIZE * 2;
951 mc1_dev.Instance = 1;
954 mc1_dev.DrvMci = &
CREATE_SYMBOL (Driver_MCI, MC1_MCI_DRIVER);
955 mc1_dev.MCI_Callback = MC1_MCI_SignalEvent;
958 mc1_dev.DrvSpi = &
CREATE_SYMBOL (Driver_SPI, MC1_SPI_DRIVER);
959 mc1_dev.SPI_Callback = MC1_SPI_SignalEvent;
961 #error "Memory Card Interface Mode Invalid in FS_Config_MC_1.h"
964 #if (MC1_FAT_JOURNAL)
966 mc1_fsj.buf = (uint8_t *)&mc1_cache[(MC1_CACHE_SIZE+1) * 256];
967 mc1_vol.fsj = &mc1_fsj;
976 nand0_vol.Drv = &nand0_drv;
977 nand0_vol.CaBuf = nand0_cache;
978 nand0_vol.CaSize = NAND0_CACHE_SIZE * 2;
980 nand0_handle.Media = &nand0_media_handle;
981 nand0_handle.Cfg = &nand0_cfg;
983 nand0_hw_driver.hw_cb = &NAND0_HW_SignalEventHandler;
984 nand0_hw_driver.drv = &
CREATE_SYMBOL (Driver_NAND, NAND0_DRIVER);
985 nand0_hw_driver.init = 0;
987 nand0_media_handle.media_cb = &NAND0_Media_SignalEventHandler;
988 nand0_media_handle.hw = &nand0_hw_driver;
989 nand0_media_handle.dev = &nand0_device;
990 nand0_media_handle.status = 0;
992 #if (NAND0_FAT_JOURNAL)
994 nand0_fsj.buf = (uint8_t *)&nand0_cache[NAND0_CSZ/4];
995 nand0_vol.fsj = &nand0_fsj;
998 nand0_vol.fsj = NULL;
1004 nand1_vol.Drv = &nand1_drv;
1005 nand1_vol.CaBuf = nand1_cache;
1006 nand1_vol.CaSize = NAND1_CACHE_SIZE * 2;
1008 nand1_handle.Media = &nand1_media_handle;
1009 nand1_handle.Cfg = &nand1_cfg;
1011 #if NAND1_DRIVER_CONFIG
1012 nand1_hw_driver.hw_cb = &NAND1_HW_EVENT_HANDLER;
1013 nand1_hw_driver.drv = &
CREATE_SYMBOL (Driver_NAND, NAND1_DRIVER);
1014 nand1_hw_driver.init = 0;
1017 nand1_media_handle.media_cb = &NAND1_MEDIA_EVENT_HANDLER;
1018 nand1_media_handle.hw = &NAND1_HW_DRIVER;
1019 nand1_media_handle.dev = &nand1_device;
1020 nand1_media_handle.status = 0;
1022 #if (NAND1_FAT_JOURNAL)
1024 nand1_fsj.buf = (uint8_t *)&nand1_cache[NAND1_CSZ/4];
1025 nand1_vol.fsj = &nand1_fsj;
1028 nand1_vol.fsj = NULL;
1029 nand1_vol.RsvdS = 0;
1034 ram0_vol.Drv = &ram0_drv;
1035 ram0_vol.CaBuf = ram0_buf;
1036 ram0_vol.CaSize = 0;
1038 ram0_vol.fsj = NULL;
1042 usb0_vol.Drv = &usb0_drv;
1043 usb0_vol.CaBuf = usb0_cache;
1044 usb0_vol.CaSize = USB0_CACHE_SIZE * 2;
1046 #if (USB0_FAT_JOURNAL)
1048 usb0_fsj.buf = (uint8_t *)&usb0_cache[(USB0_CACHE_SIZE+1) * 256];
1049 usb0_vol.fsj = &usb0_fsj;
1052 usb0_vol.fsj = NULL;
1058 usb1_vol.Drv = &usb1_drv;
1059 usb1_vol.CaSize = USB1_CACHE_SIZE * 2;
1060 usb1_vol.CaBuf = usb1_cache;
1063 #if (USB1_FAT_JOURNAL)
1065 usb1_fsj.buf = (uint8_t *)&usb1_cache[(USB1_CACHE_SIZE+1) * 256];
1066 usb1_vol.fsj = &usb1_fsj;
1069 usb1_vol.fsj = NULL;
1084 int32_t
efs_read (int32_t handle, uint8_t *buf, uint32_t len) {
return (0); }
1085 int32_t
efs_write (int32_t handle,
const uint8_t *buf, uint32_t len) {
return (-1); }
1104 int32_t
fat_read (int32_t handle, uint8_t *buf, uint32_t len) {
return(-1); }
1105 int32_t
fat_write(int32_t handle,
const uint8_t *buf, uint32_t len) {
return(-1); }
1122 uint32_t
fat_jour_init (fsFAT_Volume *vol) {
return (
true); }
1123 uint32_t fat_jour_prep (fsFAT_Volume *vol) {
return (
true); }
1124 uint32_t fsj_set_space (FSJOUR *fsj, uint32_t start_sect, uint32_t cnt) {
1126 uint32_t fsj_write (FSJOUR *fsj, uint32_t sect, uint32_t cnt, uint8_t *buf) {
1128 uint32_t fsj_init (FSJOUR *fsj, FAT_DRV *drv) {
return (
false); }
1132 #if (FAT_NAME_CACHE_SIZE == 0)
1139 uint32_t
elink_scan (uint32_t i,
void **pp, uint32_t j) {
return (1); }
1147 #pragma import(__use_no_semihosting_swi)
1149 #ifndef STDIO_DISABLE
1152 #define STDIN 0x8001
1153 #define STDOUT 0x8002
1154 #define STDERR 0x8003
1161 #if (__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M)
1187 #ifndef STDIO_DISABLE
1188 #ifndef STDOUT_LF_CR_DISABLE
1213 #ifndef STDIO_DISABLE
1214 if (strcmp(name,
"STDIN") == 0) {
1217 if (strcmp(name,
"STDOUT") == 0) {
1220 if (strcmp(name,
"STDERR") == 0) {
1224 return (__sys_open (name, openmode));
1240 #ifndef STDIO_DISABLE
1248 return (__sys_close (fh));
1270 int _sys_write (FILEHANDLE fh,
const uint8_t *buf, uint32_t len,
int mode) {
1271 #ifndef STDIO_DISABLE
1277 for ( ; len; len--) {
1279 #ifndef STDOUT_LF_CR_DISABLE
1290 return (__sys_write (fh, buf, len));
1321 int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len,
int mode) {
1322 #ifndef STDIO_DISABLE
1331 *buf++ = (uint8_t)ch;
1333 for ( ; len; len--) {
1336 *buf++ = (uint8_t)ch;
1344 return (__sys_read (fh, buf, len));
1364 #ifndef STDIO_DISABLE
1391 #ifndef STDIO_DISABLE
1399 return (__sys_seek (fh, pos));
1409 #ifndef STDIO_DISABLE
1417 return (__sys_ensure (fh));
1437 #ifndef STDIO_DISABLE
1445 return (__sys_flen (fh));