S32 SDK
S32K142_features.h
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1 /*
2  * Copyright (c) 2015 Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
57 #if !defined(S32K142_FEATURES_H)
58 #define S32K142_FEATURES_H
59 
60 /* ERRATA sections*/
61 
62 /* @brief ARM Errata 838869: Store immediate overlapping exception return operation might vector to
63  * incorrect interrupt. */
64 #define ERRATA_E9005
65 
66 /* @brief ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
67  * short ISRs are used. */
68 #define ERRATA_E6940
69 
70 /* @brief E10655: When using LPSPI in master mode and the SR[MBF] bit is read as a one, then, the
71  * flag is set. If it is read as a zero, it must be read second time and this second read will be
72  * the correct state of the bit.​ */
73 #define ERRATA_E10655
74 
75 /* @brief E10792: LPI2C: Slave Transmit Data Flag may incorrectly read as one when TXCFG is zero.
76  * Interrupts for transfer data should be enabled after the address valid event is detected and
77  * disabled at the end of the transfer. */
78 #define ERRATA_E10792
79 
80 /* @brief Errata workaround: System clock status register may be a erroneous status during the system clock switch.
81  * Read system clock source twice. */
82 #define ERRATA_E10777
83 
84 /* @brief E10856: FTM: Safe state is not removed from channel outputs after fault condition
85  * ends if SWOCTRL is being used to control the pin */
86 #define ERRATA_E10856
87 
88 /* PORT module features */
90 #define FEATURE_PINS_DRIVER_USING_PORT (1)
91 /* @brief Has control lock (register bit PCR[LK]). */
92 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
93 /* @brief Has open drain control (register bit PCR[ODE]). */
94 #define FEATURE_PINS_HAS_OPEN_DRAIN (0)
95 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
96 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
97 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
98 #define FEATURE_PORT_HAS_DMA_REQUEST (1)
99 /* @brief Has pull resistor selection available. */
100 #define FEATURE_PINS_HAS_PULL_SELECTION (1)
101 /* @brief Has slew rate control (register bit PCR[SRE]). */
102 #define FEATURE_PINS_HAS_SLEW_RATE (0)
103 /* @brief Has passive filter (register bit field PCR[PFE]). */
104 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
105 /* @brief Has drive strength (register bit PCR[DSE]). */
106 #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
107 /* @brief Has drive strength control bits*/
108 #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
109 
110 /* SOC module features */
111 
112 /* @brief PORT availability on the SoC. */
113 #define FEATURE_SOC_PORT_COUNT (5)
114 
115 #define FEATURE_SOC_SCG_COUNT (1)
116 /* @brief Slow IRC low range clock frequency. */
117 #define FEATURE_SCG_SIRC_LOW_RANGE_FREQ (2000000U)
118 /* @brief Slow IRC high range clock frequency. */
119 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
120 
121 /* @brief Fast IRC trimmed clock frequency(48MHz). */
122 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
123 /* @brief Fast IRC trimmed clock frequency(52MHz). */
124 #define FEATURE_SCG_FIRC_FREQ1 (52000000U)
125 /* @brief Fast IRC trimmed clock frequency(56MHz). */
126 #define FEATURE_SCG_FIRC_FREQ2 (56000000U)
127 /* @brief Fast IRC trimmed clock frequency(60MHz). */
128 #define FEATURE_SCG_FIRC_FREQ3 (60000000U)
129 
130 /* FLASH module features */
131 
132 /* @brief Is of type FTFA. */
133 #define FEATURE_FLS_IS_FTFA (0u)
134 /* @brief Is of type FTFC. */
135 #define FEATURE_FLS_IS_FTFC (1u)
136 /* @brief Is of type FTFE. */
137 #define FEATURE_FLS_IS_FTFE (0u)
138 /* @brief Is of type FTFL. */
139 #define FEATURE_FLS_IS_FTFL (0u)
140 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
141 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
142 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
143 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
144 /* @brief Has EEPROM region protection (register FEPROT). */
145 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
146 /* @brief Has data flash region protection (register FDPROT). */
147 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
148 /* @brief P-Flash block count. */
149 #define FEATURE_FLS_PF_BLOCK_COUNT (1u)
150 /* @brief P-Flash block size. */
151 #define FEATURE_FLS_PF_BLOCK_SIZE (262144u)
152 /* @brief P-Flash sector size. */
153 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (2048u)
154 /* @brief P-Flash write unit size. */
155 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
156 /* @brief P-Flash block swap feature. */
157 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
158 /* @brief Has FlexNVM memory. */
159 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
160 /* @brief FlexNVM block count. */
161 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
162 /* @brief FlexNVM block size. */
163 #define FEATURE_FLS_DF_BLOCK_SIZE (65536u)
164 /* @brief FlexNVM sector size. */
165 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u)
166 /* @brief FlexNVM write unit size. */
167 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
168 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
169 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
170 /* @brief Has FlexRAM memory. */
171 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
172 /* @brief FlexRAM size. */
173 #define FEATURE_FLS_FLEX_RAM_SIZE (4096u)
174 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
175 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
176 /* @brief Has 0x00 Read 1s Block command. */
177 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
178 /* @brief Has 0x01 Read 1s Section command. */
179 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
180 /* @brief Has 0x02 Program Check command. */
181 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
182 /* @brief Has 0x03 Read Resource command. */
183 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
184 /* @brief Has 0x06 Program Longword command. */
185 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
186 /* @brief Has 0x07 Program Phrase command. */
187 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
188 /* @brief Has 0x08 Erase Flash Block command. */
189 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
190 /* @brief Has 0x09 Erase Flash Sector command. */
191 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
192 /* @brief Has 0x0B Program Section command. */
193 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
194 /* @brief Has 0x40 Read 1s All Blocks command. */
195 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
196 /* @brief Has 0x41 Read Once command. */
197 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
198 /* @brief Has 0x43 Program Once command. */
199 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
200 /* @brief Has 0x44 Erase All Blocks command. */
201 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
202 /* @brief Has 0x45 Verify Backdoor Access Key command. */
203 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
204 /* @brief Has 0x46 Swap Control command. */
205 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
206 /* @brief Has 0x49 Erase All Blocks unsecure command. */
207 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
208 /* @brief Has 0x80 Program Partition command. */
209 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
210 /* @brief Has 0x81 Set FlexRAM Function command. */
211 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
212 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
213 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
214 /* @brief P-Flash Erase sector command address alignment. */
215 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
216 /* @brief P-Flash Program/Verify section command address alignment. */
217 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
218 /* @brief P-Flash Read resource command address alignment. */
219 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
220 /* @brief P-Flash Program check command address alignment. */
221 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
222 /* @brief P-Flash Program check command address alignment. */
223 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
224 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
225 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
226 /* @brief FlexNVM Erase sector command address alignment. */
227 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
228 /* @brief FlexNVM Program/Verify section command address alignment. */
229 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
230 /* @brief FlexNVM Read resource command address alignment. */
231 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
232 /* @brief FlexNVM Program check command address alignment. */
233 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
234 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
235 #define FEATURE_FLS_DF_SIZE_0000 (0x00010000u)
236 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
237 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
238 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
239 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
240 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
241 #define FEATURE_FLS_DF_SIZE_0011 (0x00008000u)
242 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
243 #define FEATURE_FLS_DF_SIZE_0100 (0x00000000u)
244 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
245 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
246 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
247 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
248 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
249 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
250 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
251 #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u)
252 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
253 #define FEATURE_FLS_DF_SIZE_1001 (0xFFFFFFFFu)
254 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
255 #define FEATURE_FLS_DF_SIZE_1010 (0x00004000u)
256 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
257 #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u)
258 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
259 #define FEATURE_FLS_DF_SIZE_1100 (0x00010000u)
260 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
261 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
262 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
263 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
264 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
265 #define FEATURE_FLS_DF_SIZE_1111 (0x00010000u)
266 /* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
267 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
268 /* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
269 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
270 /* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
271 #define FEATURE_FLS_EE_SIZE_0010 (0x1000u)
272 /* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
273 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
274 /* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
275 #define FEATURE_FLS_EE_SIZE_0100 (0x0400u)
276 /* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
277 #define FEATURE_FLS_EE_SIZE_0101 (0x0200u)
278 /* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
279 #define FEATURE_FLS_EE_SIZE_0110 (0x0100u)
280 /* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
281 #define FEATURE_FLS_EE_SIZE_0111 (0x0080u)
282 /* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
283 #define FEATURE_FLS_EE_SIZE_1000 (0x0040u)
284 /* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
285 #define FEATURE_FLS_EE_SIZE_1001 (0x0020u)
286 /* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
287 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
288 /* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
289 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
290 /* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
291 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
292 /* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
293 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
294 /* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
295 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
296 /* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
297 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
298 
299 /* LPUART module features */
300 
301 /* @brief Has extended data register ED. */
302 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
303 /* @brief Hardware flow control (RTS, CTS) is supported. */
304 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
305 /* @brief Baud rate oversampling is available. */
306 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
307 /* @brief Baud rate oversampling is available. */
308 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
309 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
310 #define FEATURE_LPUART_FIFO_SIZE (4U)
311 /* @brief Supports two match addresses to filter incoming frames. */
312 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
313 /* @brief Has transmitter/receiver DMA enable bits. */
314 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
315 /* @brief Flag clearance mask for STAT register. */
316 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
317 /* @brief Flag clearance mask for FIFO register. */
318 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
319 /* @brief Default oversampling ratio. */
320 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
321 /* @brief Default baud rate modulo divisor. */
322 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
323 /* @brief Clock names for LPUART. */
324 #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK}
325 
326 /* FlexIO module features */
327 
328 /* @brief Define the maximum number of shifters for any FlexIO instance. */
329 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
330 /* @brief Define DMA request names for Flexio. */
331 #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
332 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
333 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2
334 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3
335 
336 /* LPI2C module features */
337 
338 /* @brief DMA instance used for LPI2C module */
339 #define LPI2C_DMA_INSTANCE 0U
340 
341 /* @brief EDMA requests for LPI2C module. */
342 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
343 /* @brief PCC clocks for LPI2C module. */
344 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
345 
346 /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */
347 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
348 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
349 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
350 
351 /* PDB module features */
352 
353 /* @brief Define the count of supporting ADC channels per each PDB. */
354 #define FEATURE_PDB_ADC_CHANNEL_COUNT (2U)
355 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
356 #define FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (8U)
357 /* @brief Define the count of supporting Pulse-Out outputs per each PDB. */
358 #define FEATURE_PDB_PODLY_COUNT (1U)
359 /* System Control Block module features */
360 
361 /* @brief VECTKEY value so that AIRCR register write is not ignored. */
362 #define FEATURE_SCB_VECTKEY (0x05FAU)
363 
364 
365 /* SMC module features */
366 
367 /* @brief Has stop option (register bit STOPCTRL[STOPO]). */
368 #define FEATURE_SMC_HAS_STOPO (1)
369 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
370 #define FEATURE_SMC_HAS_PSTOPO (0)
371 /* @brief Has WAIT and VLPW options. */
372 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
373 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
374 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
375 
376 
377 /* MPU module features */
378 
379 /* @brief Specifies hardware revision level. */
380 #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
381 /* @brief Has process identifier support. */
382 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
383 /* @brief Specifies total number of bus masters. */
384 #define FEATURE_MPU_MASTER_COUNT (3U)
385 /* @brief Specifies maximum number of masters which have separated
386 privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K14x).
387 */
388 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
389 /* @brief Specifies maximum number of masters which have only
390 read and write permissions (e.g. master4~7 in S32K14x).
391 */
392 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
393 
394 /* @brief Specifies number of set access control right bits for
395  masters which have separated privilege rights for user and
396  supervisor mode accesses (e.g. master0~3 in S32K14x).
397 */
398 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
399 /* @brief Specifies number of set access control right bits for
400  masters which have only read and write permissions(e.g. master4~7 in S32K14x).
401 */
402 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
403 
404 /* @brief The MPU Logical Bus Master Number for core bus master. */
405 #define FEATURE_MPU_MASTER_CORE (0U)
406 /* @brief The MPU Logical Bus Master Number for Debugger master. */
407 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
408 /* @brief The MPU Logical Bus Master Number for DMA master. */
409 #define FEATURE_MPU_MASTER_DMA (2U)
410 /* @brief Specifies master number. */
411 #define FEATURE_MPU_MASTER \
412 { \
413  FEATURE_MPU_MASTER_CORE, \
414  FEATURE_MPU_MASTER_DEBUGGER, \
415  FEATURE_MPU_MASTER_DMA, \
416 }
417 
418 /* @brief Specifies total number of slave ports. */
419 #define FEATURE_MPU_SLAVE_COUNT (4U)
420 /* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */
421 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
422 /* @brief The MPU Slave Port Assignment for SRAM back door. */
423 #define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U)
424 /* @brief The MPU Slave Port Assignment for SRAM_L front door. */
425 #define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U)
426 /* @brief The MPU Slave Port Assignment for SRAM_U front door. */
427 #define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U)
428 /* @brief The MPU Slave Port mask. */
429 #define FEATURE_MPU_SLAVE_MASK (0xF0000000U)
430 #define FEATURE_MPU_SLAVE_SHIFT (28u)
431 #define FEATURE_MPU_SLAVE_WIDTH (4u)
432 #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
433 
434 
435 /* WDOG module features */
436 
437 /* @brief The 32-bit value used for unlocking the WDOG. */
438 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
439 /* @brief The 32-bit value used for resetting the WDOG counter. */
440 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
441 /* @brief The reset value of the timeout register. */
442 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
443 /* @brief The value minimum of the timeout register. */
444 #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
445 /* @brief The reset value of the window register. */
446 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
447 /* @brief The mask of the reserved bit in the CS register. */
448 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
449 /* @brief The value used to set WDOG source clock from LPO. */
450 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
451 /* @brief The first 16-bit value used for unlocking the WDOG. */
452 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
453 /* @brief The second 16-bit value used for unlocking the WDOG. */
454 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
455 /* @brief The first 16-bit value used for resetting the WDOG counter. */
456 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
457 /* @brief The second 16-bit value used for resetting the WDOG counter. */
458 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
459 
460 /* FTM module features */
461 
462 /* @brief Number of PWM channels */
463 #define FEATURE_FTM_CHANNEL_COUNT (8U)
464 /* @brief Number of fault channels */
465 #define FTM_FEATURE_FAULT_CHANNELS (4U)
466 /* @brief Width of control channel */
467 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
468 /* @brief Output channel offset */
469 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
470 /* @brief Max counter value */
471 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
472 /* @brief Input capture for single shot */
473 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
474 /* @brief Dithering has supported on the generated PWM signals */
475 #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U)
476 
477 /* CRC module features */
478 
479 /* @brief CRC module use for S32K1xx. */
480 #define FEATURE_CRC_DRIVER_S32K1xx (1)
481 /* Default CRC bit width */
482 #define CRC_DEFAULT_WIDTH CRC_BITS_16
483 /* Default CRC read transpose */
484 #define CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
485 /* Default polynomial 0x1021U */
486 #define CRC_DEFAULT_POLYNOMIAL (0x1021U)
487 
488 /* EWM module features */
489 
490 /* @brief First byte of the EWM Service key */
491 #define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U)
492 /* @brief Second byte of the EWM Service key */
493 #define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU)
494 /* @brief EWM Compare High register maximum value */
495 #define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU)
496 /* @brief EWM Compare Low register minimum value */
497 #define FEATURE_EWM_CMPL_MIN_VALUE (0x00U)
498 
499 /* CLOCK names */
500 
502 typedef enum {
503 
504  /* Main clocks */
505  CORE_CLK = 0u,
506  BUS_CLK = 1u,
507  SLOW_CLK = 2u,
508  CLKOUT_CLK = 3u,
510  /* Other internal clocks used by peripherals. */
511  SIRC_CLK = 4u,
512  FIRC_CLK = 5u,
513  SOSC_CLK = 6u,
514  SPLL_CLK = 7u,
518  SIRCDIV1_CLK = 10u,
519  SIRCDIV2_CLK = 11u,
520  FIRCDIV1_CLK = 12u,
521  FIRCDIV2_CLK = 13u,
522  SOSCDIV1_CLK = 14u,
523  SOSCDIV2_CLK = 15u,
524  SPLLDIV1_CLK = 16u,
525  SPLLDIV2_CLK = 17u,
529  /* SIM clocks */
536  SIM_LPO_CLK = 27u,
540  SIM_EIM_CLK = 31u,
541  SIM_ERM_CLK = 32u,
542  SIM_DMA_CLK = 33u,
543  SIM_MPU_CLK = 34u,
544  SIM_MSCM_CLK = 35u,
547  /* PCC clocks */
548  CMP0_CLK = 41u,
549  CRC0_CLK = 42u,
550  DMAMUX0_CLK = 43u,
551  EWM0_CLK = 44u,
552  PORTA_CLK = 45u,
553  PORTB_CLK = 46u,
554  PORTC_CLK = 47u,
555  PORTD_CLK = 48u,
556  PORTE_CLK = 49u,
557  RTC0_CLK = 50u,
559  FlexCAN0_CLK = 52u,
560  FlexCAN1_CLK = 53u,
561  PDB0_CLK = 54u,
562  PDB1_CLK = 55u,
564  FTFC0_CLK = 57u,
566  FTM0_CLK = 59u,
567  FTM1_CLK = 60u,
568  FTM2_CLK = 61u,
569  FTM3_CLK = 62u,
571  ADC0_CLK = 64u,
572  ADC1_CLK = 65u,
573  FLEXIO0_CLK = 66u,
574  LPI2C0_CLK = 67u,
575  LPIT0_CLK = 68u,
576  LPSPI0_CLK = 69u,
577  LPSPI1_CLK = 70u,
578  LPTMR0_CLK = 71u,
579  LPUART0_CLK = 72u,
580  LPUART1_CLK = 73u,
584 } clock_names_t;
585 
586 #define PCC_INVALID_INDEX 0
587 
593 #define PCC_CLOCK_NAME_MAPPINGS \
594 { \
595 PCC_INVALID_INDEX, \
596 PCC_INVALID_INDEX, \
597 PCC_INVALID_INDEX, \
598 PCC_INVALID_INDEX, \
599 PCC_INVALID_INDEX, \
600 PCC_INVALID_INDEX, \
601 PCC_INVALID_INDEX, \
602 PCC_INVALID_INDEX, \
603 PCC_INVALID_INDEX, \
604 PCC_INVALID_INDEX, \
605 PCC_INVALID_INDEX, \
606 PCC_INVALID_INDEX, \
607 PCC_INVALID_INDEX, \
608 PCC_INVALID_INDEX, \
609 PCC_INVALID_INDEX, \
610 PCC_INVALID_INDEX, \
611 PCC_INVALID_INDEX, \
612 PCC_INVALID_INDEX, \
613 PCC_INVALID_INDEX, \
614 PCC_INVALID_INDEX, \
615 PCC_INVALID_INDEX, \
616 PCC_INVALID_INDEX, \
617 PCC_INVALID_INDEX, \
618 PCC_INVALID_INDEX, \
619 PCC_INVALID_INDEX, \
620 PCC_INVALID_INDEX, \
621 PCC_INVALID_INDEX, \
622 PCC_INVALID_INDEX, \
623 PCC_INVALID_INDEX, \
624 PCC_INVALID_INDEX, \
625 PCC_INVALID_INDEX, \
626 PCC_INVALID_INDEX, \
627 PCC_INVALID_INDEX, \
628 PCC_INVALID_INDEX, \
629 PCC_INVALID_INDEX, \
630 PCC_INVALID_INDEX, \
631 PCC_INVALID_INDEX, \
632 PCC_INVALID_INDEX, \
633 PCC_INVALID_INDEX, \
634 PCC_INVALID_INDEX, \
635 PCC_INVALID_INDEX, \
636 PCC_CMP0_INDEX, \
637 PCC_CRC_INDEX, \
638 PCC_DMAMUX_INDEX, \
639 PCC_EWM_INDEX, \
640 PCC_PORTA_INDEX, \
641 PCC_PORTB_INDEX, \
642 PCC_PORTC_INDEX, \
643 PCC_PORTD_INDEX, \
644 PCC_PORTE_INDEX, \
645 PCC_RTC_INDEX, \
646 PCC_INVALID_INDEX, \
647 PCC_FlexCAN0_INDEX, \
648 PCC_FlexCAN1_INDEX, \
649 PCC_PDB0_INDEX, \
650 PCC_PDB1_INDEX, \
651 PCC_INVALID_INDEX, \
652 PCC_FTFC_INDEX, \
653 PCC_INVALID_INDEX, \
654 PCC_FTM0_INDEX, \
655 PCC_FTM1_INDEX, \
656 PCC_FTM2_INDEX, \
657 PCC_FTM3_INDEX, \
658 PCC_INVALID_INDEX, \
659 PCC_ADC0_INDEX, \
660 PCC_ADC1_INDEX, \
661 PCC_FlexIO_INDEX, \
662 PCC_LPI2C0_INDEX, \
663 PCC_LPIT_INDEX, \
664 PCC_LPSPI0_INDEX, \
665 PCC_LPSPI1_INDEX, \
666 PCC_LPTMR0_INDEX, \
667 PCC_LPUART0_INDEX, \
668 PCC_LPUART1_INDEX, \
669 PCC_INVALID_INDEX, \
670 PCC_INVALID_INDEX, \
671 }
672 
676 #define NO_PERIPHERAL_FEATURE (0U) /* It's not a peripheral instance, there is no peripheral feature. */
677 #define HAS_CLOCK_GATING_IN_SIM (1U << 0U) /* Clock gating is implemented in SIM (it's not in PCC) */
678 #define HAS_MULTIPLIER (1U << 1U) /* Multiplier is implemented in PCC */
679 #define HAS_DIVIDER (1U << 2U) /* Divider is implemented in PCC */
680 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U) /* Functional clock source is provided by the first asynchronous clock. */
681 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U) /* Functional clock source is provided by the second asynchronous clock. */
682 #define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U) /* Interface clock is provided by the bus clock. */
683 #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U) /* Interface clock is provided by the sys clock. */
684 #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U) /* Interface clock is provided by the slow clock. */
685 
690 #define PERIPHERAL_FEATURES \
691 { \
692 (NO_PERIPHERAL_FEATURE), \
693 (NO_PERIPHERAL_FEATURE), \
694 (NO_PERIPHERAL_FEATURE), \
695 (NO_PERIPHERAL_FEATURE), \
696 (NO_PERIPHERAL_FEATURE), \
697 (NO_PERIPHERAL_FEATURE), \
698 (NO_PERIPHERAL_FEATURE), \
699 (NO_PERIPHERAL_FEATURE), \
700 (NO_PERIPHERAL_FEATURE), \
701 (NO_PERIPHERAL_FEATURE), \
702 (NO_PERIPHERAL_FEATURE), \
703 (NO_PERIPHERAL_FEATURE), \
704 (NO_PERIPHERAL_FEATURE), \
705 (NO_PERIPHERAL_FEATURE), \
706 (NO_PERIPHERAL_FEATURE), \
707 (NO_PERIPHERAL_FEATURE), \
708 (NO_PERIPHERAL_FEATURE), \
709 (NO_PERIPHERAL_FEATURE), \
710 (NO_PERIPHERAL_FEATURE), \
711 (NO_PERIPHERAL_FEATURE), \
712 (NO_PERIPHERAL_FEATURE), \
713 (NO_PERIPHERAL_FEATURE), \
714 (NO_PERIPHERAL_FEATURE), \
715 (NO_PERIPHERAL_FEATURE), \
716 (NO_PERIPHERAL_FEATURE), \
717 (NO_PERIPHERAL_FEATURE), \
718 (NO_PERIPHERAL_FEATURE), \
719 (NO_PERIPHERAL_FEATURE), \
720 (NO_PERIPHERAL_FEATURE), \
721 (NO_PERIPHERAL_FEATURE), \
722 (NO_PERIPHERAL_FEATURE), \
723 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
724 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
725 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
726 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
727 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
728 (NO_PERIPHERAL_FEATURE), \
729 (NO_PERIPHERAL_FEATURE), \
730 (NO_PERIPHERAL_FEATURE), \
731 (NO_PERIPHERAL_FEATURE), \
732 (NO_PERIPHERAL_FEATURE), \
733 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
734 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
735 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
736 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
737 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
738 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
739 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
740 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
741 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
742 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
743 (NO_PERIPHERAL_FEATURE), \
744 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
745 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
746 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
747 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
748 (NO_PERIPHERAL_FEATURE), \
749 (HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
750 (NO_PERIPHERAL_FEATURE), \
751 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
752 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
753 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
754 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
755 (NO_PERIPHERAL_FEATURE), \
756 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
757 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
758 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
759 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
760 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
761 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
762 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
763 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
764 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
765 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
766 (NO_PERIPHERAL_FEATURE), \
767 (NO_PERIPHERAL_FEATURE), \
768 }
769 
770 
771 /* Time to wait for SIRC to stabilize (number of
772  * cycles when core runs at maximum speed - 112 MHz */
773 #define SIRC_STABILIZATION_TIMEOUT 26U;
774 
775 /* Time to wait for FIRC to stabilize (number of
776  * cycles when core runs at maximum speed - 112 MHz */
777 #define FIRC_STABILIZATION_TIMEOUT 10U;
778 
779 /* Time to wait for SOSC to stabilize (number of
780  * cycles when core runs at maximum speed - 112 MHz */
781 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
782 
783 /* Time to wait for SPLL to stabilize (number of
784  * cycles when core runs at maximum speed - 112 MHz */
785 #define SPLL_STABILIZATION_TIMEOUT 1000U;
786 
797 #define MAX_FREQ_VLPR 0U
798 #define MAX_FREQ_RUN 1U
799 #define MAX_FREQ_HSRUN 2U
800 
801 #define MAX_FREQ_SYS_CLK 0U
802 #define MAX_FREQ_BUS_CLK 1U
803 #define MAX_FREQ_SLOW_CLK 2U
804 
805 #define MAX_FREQ_MODES_NO 3U
806 #define MAX_FREQ_CLK_NO 3U
807 
808 #define CLOCK_MAX_FREQUENCIES \
809 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
810 { 4000000, 4000000, 1000000}, \
811 { 80000000,40000000,26670000}, \
812 {112000000,56000000,28000000}, \
813 }
814 
815 
826 #define TMP_SIRC_CLK 0U
827 #define TMP_FIRC_CLK 1U
828 #define TMP_SOSC_CLK 2U
829 #define TMP_SPLL_CLK 3U
830 
831 #define TMP_SYS_DIV 0U
832 #define TMP_BUS_DIV 1U
833 #define TMP_SLOW_DIV 2U
834 
835 #define TMP_SYS_CLK_NO 4U
836 #define TMP_SYS_DIV_NO 3U
837 
838 #define TMP_SYSTEM_CLOCK_CONFIGS \
839 { /* SYS_CLK BUS_CLK SLOW_CLK */ \
840 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1}, \
841 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
842 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
843 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
844 }
845 
846 /* Do not use the old names of the renamed symbols */
847 /* #define DO_NOT_USE_DEPRECATED_SYMBOLS */
848 
854 #if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS)
855 #define CORE_CLOCK CORE_CLK
856 #define BUS_CLOCK BUS_CLK
857 #define SLOW_CLOCK SLOW_CLK
858 #define CLKOUT_CLOCK CLKOUT_CLK
859 #define SIRC_CLOCK SIRC_CLK
860 #define FIRC_CLOCK FIRC_CLK
861 #define SOSC_CLOCK SOSC_CLK
862 #define SPLL_CLOCK SPLL_CLK
863 #define RTC_CLKIN_CLOCK RTC_CLKIN_CLK
864 #define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK
865 #define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK
866 #define SIM_LPO_CLOCK SIM_LPO_CLK
867 #define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK
868 #define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK
869 #define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK
870 #define SIM_EIM_CLOCK SIM_EIM_CLK
871 #define SIM_ERM_CLOCK SIM_ERM_CLK
872 #define SIM_DMA_CLOCK SIM_DMA_CLK
873 #define SIM_MPU_CLOCK SIM_MPU_CLK
874 #define SIM_MSCM_CLOCK SIM_MSCM_CLK
875 #define PCC_DMAMUX0_CLOCK DMAMUX0_CLK
876 #define PCC_CRC0_CLOCK CRC0_CLK
877 #define PCC_RTC0_CLOCK RTC0_CLK
878 #define PCC_PORTA_CLOCK PORTA_CLK
879 #define PCC_PORTB_CLOCK PORTB_CLK
880 #define PCC_PORTC_CLOCK PORTC_CLK
881 #define PCC_PORTD_CLOCK PORTD_CLK
882 #define PCC_PORTE_CLOCK PORTE_CLK
883 #define PCC_EWM0_CLOCK EWM0_CLK
884 #define PCC_CMP0_CLOCK CMP0_CLK
885 #define PCC_FlexCAN0_CLOCK FlexCAN0_CLK
886 #define PCC_FlexCAN1_CLOCK FlexCAN1_CLK
887 #define PCC_FlexCAN2_CLOCK FlexCAN2_CLK
888 #define PCC_PDB1_CLOCK PDB1_CLK
889 #define PCC_PDB0_CLOCK PDB0_CLK
890 #define PCC_FTFC0_CLOCK FTFC0_CLK
891 #define PCC_FTM0_CLOCK FTM0_CLK
892 #define PCC_FTM1_CLOCK FTM1_CLK
893 #define PCC_FTM2_CLOCK FTM2_CLK
894 #define PCC_FTM3_CLOCK FTM3_CLK
895 #define PCC_ADC1_CLOCK ADC1_CLK
896 #define PCC_LPSPI0_CLOCK LPSPI0_CLK
897 #define PCC_LPSPI1_CLOCK LPSPI1_CLK
898 #define PCC_LPSPI2_CLOCK LPSPI2_CLK
899 #define PCC_LPIT0_CLOCK LPIT0_CLK
900 #define PCC_ADC0_CLOCK ADC0_CLK
901 #define PCC_LPTMR0_CLOCK LPTMR0_CLK
902 #define PCC_FLEXIO0_CLOCK FLEXIO0_CLK
903 #define PCC_LPI2C0_CLOCK LPI2C0_CLK
904 #define PCC_LPUART0_CLOCK LPUART0_CLK
905 #define PCC_LPUART1_CLOCK LPUART1_CLK
906 #define PCC_LPUART2_CLOCK LPUART2_CLK
907 #endif /* !DO_NOT_USE_DEPRECATED_SYMBOLS */
908 
909 
910 /* Interrupt module features */
911 
912 /* @brief Lowest interrupt request number. */
913 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
914 /* @brief Highest interrupt request number. */
915 #define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn)
916 
917 #define FEATURE_NVIC_PRIO_BITS (4U)
918 /* @brief Has software interrupt. */
919 #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
920 /* @brief Has pending interrupt state. */
921 #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
922 /* @brief Has active interrupt state. */
923 #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u)
924 
925 
926 /* CSEc module features */
927 
930 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
931 
933 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
934 
936 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
937 
939 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
940 
942 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
943 
945 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
946 
948 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
949 
950 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
951 
953 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
954 
956 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
957 
958 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
959 
960 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
961 
962 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
963 
964 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
965 
966 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
967 
968 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
969 
970 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
971 
972 
973 /* ADC module features */
974 
977 #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0)
978 
982 #define FEATURE_ADC_MAX_NUM_EXT_CHANS (16)
983 
985 #if FEATURE_ADC_HAS_EXTRA_NUM_REGS
986 #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
987 #else
988 #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
989 #endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */
990 
992 #define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
993 
994 #define ADC_DEFAULT_USER_GAIN (0x04U)
995 
996 
997 /* EDMA module features */
998 
999 /* @brief Number of EDMA channels. */
1000 #define FEATURE_EDMA_MODULE_CHANNELS (16U)
1001 /* @brief Number of EDMA channel interrupt lines. */
1002 #define FEATURE_CHANNEL_INTERRUPT_LINES (16U)
1003 /* @brief Number of EDMA error interrupt lines. */
1004 #define FEATURE_ERROR_INTERRUPT_LINES (1U)
1005 /* @brief eDMA module has error interrupt. */
1006 #define FEATURE_EDMA_HAS_ERROR_IRQ
1007 /* @brief eDMA module has separate interrupt lines for each channel. */
1008 #define FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
1009 /* @brief Conversion from channel index to DCHPRI index. */
1010 #define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
1011 /* @brief eDMA channel groups count. */
1012 #define FEATURE_EDMA_CHANNEL_GROUP_COUNT (1U)
1013 /* @brief Number of eDMA channels with asynchronous request capability. */
1014 #define FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16U)
1015 /* @brief Clock names for eDMA. */
1016 #define EDMA_CLOCK_NAMES {SIM_DMA_CLK}
1017 
1018 
1019 /* DMAMUX module features */
1020 
1021 /* @brief Number of DMA channels. */
1022 #define FEATURE_DMAMUX_MODULE_CHANNELS (16U)
1023 /* @brief Has the periodic trigger capability */
1024 #define FEATURE_DMAMUX_HAS_TRIG (1)
1025 /* @brief Conversion from request source to the actual DMAMUX channel */
1026 #define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x) (x)
1027 /* @brief Mapping between request source and DMAMUX instance */
1028 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
1029 /* @brief Conversion from eDMA channel index to DMAMUX channel. */
1030 #define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x) (x)
1031 /* @brief Conversion from DMAMUX channel DMAMUX register index. */
1032 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
1033 /* @brief Clock names for DMAMUX. */
1034 #define DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
1035 
1043 typedef enum {
1093 
1094 
1095 /* MSCM module features */
1096 
1097 /* @brief Has interrupt router control registers (IRSPRCn). */
1098 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
1099 /* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */
1100 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
1101 
1102 
1103 /* OSIF module features */
1104 
1105 #define FEATURE_OSIF_USE_SYSTICK (1)
1106 #define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */
1107 
1108 /* CAN module features */
1109 
1110 /* @brief Frames available in Rx FIFO flag shift */
1111 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
1112 /* @brief Rx FIFO warning flag shift */
1113 #define FEATURE_CAN_RXFIFO_WARNING (6U)
1114 /* @brief Rx FIFO overflow flag shift */
1115 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
1116 /* @brief Has Flexible Data Rate for CAN0 */
1117 #define FEATURE_CAN0_HAS_FD (1)
1118 /* @brief Has Flexible Data Rate for CAN1 */
1119 #define FEATURE_CAN1_HAS_FD (0)
1120 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */
1121 #define FEATURE_CAN0_MAX_MB_NUM (32U)
1122 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN1 */
1123 #define FEATURE_CAN1_MAX_MB_NUM (16U)
1124 /* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */
1125 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
1126 /* @brief Has DMA enable (bit field MCR[DMA]). */
1127 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
1128 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
1129 #define FEATURE_CAN_MAX_MB_NUM (32U)
1130 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
1131 #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM, \
1132  FEATURE_CAN1_MAX_MB_NUM }
1133 /* @brief Has Pretending Networking mode */
1134 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
1135 /* @brief Has Stuff Bit Count Enable Bit */
1136 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
1137 /* @brief Has ISO CAN FD Enable Bit */
1138 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
1139 /* @brief Has Message Buffer Data Size Region 1 */
1140 #define FEATURE_CAN_HAS_MBDSR1 (0)
1141 /* @brief Has Message Buffer Data Size Region 2 */
1142 #define FEATURE_CAN_HAS_MBDSR2 (0)
1143 /* @brief DMA hardware requests for all FlexCAN instances */
1144 #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0, \
1145  EDMA_REQ_FLEXCAN1 }
1146 
1147 /* @brief Maximum number of Message Buffers IRQs */
1148 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
1149 /* @brief Message Buffers IRQs */
1150 #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
1151  CAN_ORed_16_31_MB_IRQS }
1152 /* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */
1153 #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1)
1154 
1155 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
1156 
1157 #define FEATURE_CAN_PE_CLK_NUM 2U
1158 /* @brief FlexCAN clock source */
1159 typedef enum {
1163 /* @brief Clock names for FlexCAN PE clock */
1164 #define FLEXCAN_PE_CLOCK_NAMES { FLEXCAN_CLK_SOURCE_SOSCDIV2, FLEXCAN_CLK_SOURCE_SYS }
1165 #endif
1166 /* @brief Has Self Wake Up mode */
1167 #define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
1168 
1169 /* TRGMUX module features */
1170 #define FEATURE_TRGMUX_HAS_EXTENDED_NUM_TRIGS (0)
1171 
1172 /* LPSPI module features */
1173 /* @brief Initial value for state structure */
1174 #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL}
1175 
1176 #endif /* S32K142_FEATURES_H */
1177 
1178 /*******************************************************************************
1179  * EOF
1180  ******************************************************************************/
dma_request_source_t
Structure for the DMA hardware request.
clock_names_t
Clock names.
flexcan_clk_source_t