48 #include "sim_hw_access.h"
49 #include "scg_hw_access.h"
50 #include "pcc_hw_access.h"
51 #include "pmc_hw_access.h"
52 #include "smc_hw_access.h"
79 #define SCG_SPLL_MULT_BASE 16U
85 #define SCG_SPLL_PREDIV_BASE 1U
91 #define SCG_SPLL_REF_MIN 8000000U
97 #define SCG_SPLL_REF_MAX 32000000U
102 #define LPO_128K_FREQUENCY 128000UL
107 #define LPO_32K_FREQUENCY 32000UL
112 #define LPO_1K_FREQUENCY 1000UL
117 #define HIGH_SPEED_RUNNING_MODE (1UL << 7U)
118 #define RUN_SPEED_RUNNING_MODE (1UL << 0U)
119 #define VLPR_SPEED_RUNNING_MODE (1UL << 2U)
175 uint32_t * frequency);
178 uint32_t * frequency);
181 uint32_t * frequency);
279 if (scgConfig != NULL)
340 if ((peripheralClockConfig != NULL) && (peripheralClockConfig->
peripheralClocks != NULL))
342 for (i = 0U; i < peripheralClockConfig->
count; i++)
348 PCC_SetPeripheralClockControl(
PCC,
379 SIM_SetLpoClocks(
SIM,
394 #if defined (QuadSPI_INSTANCE_COUNT)
404 if (i < NUMBER_OF_TCLK_INPUTS)
414 SIM_ClearTraceClockConfig(
SIM);
416 SIM_SetTraceClockConfig(
SIM,
452 uint32_t * frequency)
521 if (frequency != NULL)
536 uint32_t * frequency)
539 uint32_t clockPinSelect;
546 clockPinSelect = SIM_GetFtm0ExternalClkPinMode(
SIM);
554 clockPinSelect = SIM_GetFtm1ExternalClkPinMode(
SIM);
562 clockPinSelect = SIM_GetFtm2ExternalClkPinMode(
SIM);
570 clockPinSelect = SIM_GetFtm3ExternalClkPinMode(
SIM);
577 #if FTM_INSTANCE_COUNT > 4U
578 case SIM_FTM4_CLOCKSEL:
579 clockPinSelect = SIM_GetFtm4ExternalClkPinMode(
SIM);
587 #if FTM_INSTANCE_COUNT > 5U
588 case SIM_FTM5_CLOCKSEL:
589 clockPinSelect = SIM_GetFtm5ExternalClkPinMode(
SIM);
597 #if FTM_INSTANCE_COUNT > 6U
598 case SIM_FTM6_CLOCKSEL:
599 clockPinSelect = SIM_GetFtm6ExternalClkPinMode(
SIM);
607 #if FTM_INSTANCE_COUNT > 7U
608 case SIM_FTM7_CLOCKSEL:
609 clockPinSelect = SIM_GetFtm7ExternalClkPinMode(
SIM);
624 if (PMC_GetLpoMode(
PMC))
631 if (PMC_GetLpoMode(
PMC))
638 if (PMC_GetLpoMode(
PMC))
645 if (PMC_GetLpoMode(
PMC))
652 if (!SIM_GetEimClockGate(
SIM))
660 if (!SIM_GetErmClockGate(
SIM))
668 if (!SIM_GetDmaClockGate(
SIM))
676 if (!SIM_GetMpuClockGate(
SIM))
684 if (!SIM_GetMscmClockGate(
SIM))
696 if (frequency != NULL)
710 uint32_t * frequency)
725 else if (PCC_GetClockMode(
PCC, clockName) ==
false)
782 if (frequency != NULL)
798 uint32_t * frequency)
834 uint32_t frequency = 0;
835 uint32_t fracValue = PCC_GetFracValueSel(
PCC, clockName);
836 uint32_t divValue = PCC_GetDividerSel(
PCC, clockName);
839 if (((uint32_t)fracValue) <= ((uint32_t)divValue))
842 if (PCC_GetClockMode(
PCC, clockName))
845 switch (PCC_GetClockSourceSel(
PCC, clockName))
864 frequency = frequency / (divValue + 1U);
865 frequency = frequency * (fracValue + 1U);
881 switch (SMC_GetCurrentRunningMode(
SMC))
941 while ((SCG_GetCurrentSystemClockSource(
SCG) != ((uint32_t)to_clk->
src)) && (timeout > 0U));
960 if (SIM_GetClockoutStatus(
SIM))
962 switch (SIM_GetClockoutSelectorValue(
SIM))
995 frequency /= (SIM_GetClockoutDividerValue(
SIM) + 1U);
1014 switch (SCG_GetClockoutSourceSel(
SCG))
1049 switch (SIM_GetRtcClkSrc(
SIM))
1083 if (sircConfig == NULL)
1087 sircDefaultConfig.
locked =
false;
1094 sircCfg = &sircDefaultConfig;
1098 sircCfg = sircConfig;
1102 if (SCG_GetSircSystemClockMode(
SCG))
1110 SCG_ClearSircLock(
SCG);
1113 SCG_ClearSircControl(
SCG);
1121 SCG_SetSircAsyncConfig(
SCG, sircCfg->
div1, sircCfg->
div2);
1124 SCG_SetSircConfiguration(
SCG, sircCfg->
range);
1156 if (fircConfig == NULL)
1161 fircDefaultConfig.
locked =
false;
1168 fircCfg = &fircDefaultConfig;
1172 fircCfg = fircConfig;
1176 if (SCG_GetFircSystemClockMode(
SCG))
1184 SCG_ClearFircLock(
SCG);
1187 SCG_ClearFircControl(
SCG);
1195 SCG_SetFircAsyncConfig(
SCG, fircCfg->
div1, fircCfg->
div2);
1198 SCG_SetFircConfiguration(
SCG, fircCfg->
range);
1230 if (soscConfig == NULL)
1236 soscDefaultConfig.
locked =
false;
1245 soscCfg = &soscDefaultConfig;
1249 soscCfg = soscConfig;
1253 if (SCG_GetSoscSystemClockMode(
SCG))
1261 SCG_ClearSoscLock(
SCG);
1264 SCG_ClearSoscControl(
SCG);
1274 SCG_SetSoscAsyncConfig(
SCG, soscCfg->
div1, soscCfg->
div2);
1284 SCG_SetSoscControl(
SCG,
false,
false, soscCfg->
locked);
1289 SCG_SetSoscControl(
SCG,
true,
false, soscCfg->
locked);
1294 SCG_SetSoscControl(
SCG,
true,
true, soscCfg->
locked);
1330 uint32_t srcFreq, timeout;
1332 if (spllConfig == NULL)
1336 spllDefaultConfig.
locked =
false;
1341 spllDefaultConfig.
prediv = 0;
1342 spllDefaultConfig.
mult = 0;
1343 spllDefaultConfig.
src = 0;
1345 spllCfg = &spllDefaultConfig;
1349 spllCfg = spllConfig;
1353 if (SCG_GetSpllSystemClockMode(
SCG))
1361 SCG_ClearSpllLock(
SCG);
1364 SCG_ClearSpllControl(
SCG);
1379 SCG_SetSpllAsyncConfig(
SCG, spllCfg->
div1, spllCfg->
div2);
1382 SCG_SetSpllConfiguration(
SCG, spllCfg->
prediv, spllCfg->
mult);
1389 SCG_SetSpllControl(
SCG,
false,
false, spllCfg->
locked);
1394 SCG_SetSpllControl(
SCG,
true,
false, spllCfg->
locked);
1399 SCG_SetSpllControl(
SCG,
true,
true, spllCfg->
locked);
1504 nextSysClockConfig = NULL;
1558 sysClockConfig.
src = nextSysClockConfig->
src;
1568 sysClockConfig.
src = nextSysClockConfig->
src;
1597 switch (SCG_GetCurrentSystemClockSource(
SCG))
1616 freq /= (SCG_GetCurrentCoreClockDividerRatio(
SCG) + 1U);
1624 freq /= (SCG_GetCurrentBusClockDividerRatio(
SCG) + 1U);
1627 freq /= (SCG_GetCurrentSlowClockDividerRatio(
SCG) + 1U);
1645 uint32_t srcFreq = 0U;
1649 uint32_t maxFreqRunMode = 0U;
1650 const uint32_t sysFreqMul = ((uint32_t)config->
divCore) + 1UL;
1651 const uint32_t busFreqMul = (((uint32_t)config->
divCore) + 1UL) * (((uint32_t)config->
divBus) + 1UL);
1652 const uint32_t slowFreqMul = (((uint32_t)config->
divCore) + 1UL) * (((uint32_t)config->
divSlow) + 1UL);
1657 switch (config->
src)
1695 if ((srcFreq > (sysFreqMul * maxClocksFreq[maxFreqRunMode][
MAX_FREQ_SYS_CLK])) ||
1696 (srcFreq > (busFreqMul * maxClocksFreq[maxFreqRunMode][
MAX_FREQ_BUS_CLK])) ||
1708 SCG_SetRunClockControl(
SCG, (uint32_t)config->
src, (uint32_t)config->
divCore, (uint32_t)config->
divBus, (uint32_t)config->
divSlow);
1712 SCG_SetVlprClockControl(
SCG, (uint32_t)config->
src, (uint32_t)config->
divCore, (uint32_t)config->
divBus, (uint32_t)config->
divSlow);
1715 SCG_SetHsrunClockControl(
SCG, (uint32_t)config->
src, (uint32_t)config->
divCore, (uint32_t)config->
divBus, (uint32_t)config->
divSlow);
1734 uint32_t freq, div = 0U;
1740 switch (clockSource)
1745 div = SCG_GetFircFirstAsyncDivider(
SCG);
1751 div = SCG_GetSircFirstAsyncDivider(
SCG);
1757 div = SCG_GetSoscFirstAsyncDivider(
SCG);
1763 div = SCG_GetSpllFirstAsyncDivider(
SCG);
1778 switch (clockSource)
1783 div = SCG_GetFircSecondAsyncDivider(
SCG);
1789 div = SCG_GetSircSecondAsyncDivider(
SCG);
1795 div = SCG_GetSoscSecondAsyncDivider(
SCG);
1801 div = SCG_GetSpllSecondAsyncDivider(
SCG);
1824 freq = (freq >> (div - 1U));
1841 if (SCG_GetSoscStatus(
SCG))
1861 if (SCG_GetSircStatus(
SCG))
1881 static const uint32_t fircFreq[] = {
1885 if (SCG_GetFircStatus(
SCG))
1887 retValue = fircFreq[SCG_GetFircRange(
SCG)];
1903 uint32_t freq, retValue;
1905 if (SCG_GetSpllStatus(
SCG))
1935 switch (SIM_GetLpoClkSelectorValue(
SIM))
2032 sysClockConfig->
src = sysClkSrcMappings[SCG_GetCurrentSystemClockSource(
SCG)];
2033 sysClockConfig->
divBus = sysClkDivMappings[SCG_GetCurrentBusClockDividerRatio(
SCG)];
2034 sysClockConfig->
divCore = sysClkDivMappings[SCG_GetCurrentCoreClockDividerRatio(
SCG)];
2035 sysClockConfig->
divSlow = sysClkDivMappings[SCG_GetCurrentSlowClockDividerRatio(
SCG)];
2048 uint32_t source, divider, multiplier;
2053 if (periphClkConfig == NULL)
2058 periphClkCfg = &defaultPeriphClkCfg;
2062 periphClkCfg = periphClkConfig;
2070 ((uint32_t) periphClkCfg->
source) : 0U;
2078 ((uint32_t) periphClkCfg->
divider) : 0U;
2081 PCC_SetClockMode(
PCC, clockName,
false);
2084 PCC_SetPeripheralClockControl(
PCC, clockName,
true, source, divider, multiplier);
2091 SIM_SetMscmClockGate(
SIM,
true);
2095 SIM_SetMpuClockGate(
SIM,
true);
2099 SIM_SetDmaClockGate(
SIM,
true);
2103 SIM_SetErmClockGate(
SIM,
true);
2107 SIM_SetEimClockGate(
SIM,
true);
2130 PCC_SetClockMode(
PCC, clockName,
false);
2138 SIM_SetMscmClockGate(
SIM,
false);
2142 SIM_SetMpuClockGate(
SIM,
false);
2146 SIM_SetDmaClockGate(
SIM,
false);
2150 SIM_SetErmClockGate(
SIM,
false);
2154 SIM_SetEimClockGate(
SIM,
false);
2180 static const scg_system_clock_div_t sysClkDivMappings[] = {
SCG_SYSTEM_CLOCK_DIV_BY_1,
SCG_SYSTEM_CLOCK_DIV_BY_1,
SCG_SYSTEM_CLOCK_DIV_BY_2,
SCG_SYSTEM_CLOCK_DIV_BY_3,
SCG_SYSTEM_CLOCK_DIV_BY_4,
SCG_SYSTEM_CLOCK_DIV_BY_5,
SCG_SYSTEM_CLOCK_DIV_BY_6,
SCG_SYSTEM_CLOCK_DIV_BY_7,
SCG_SYSTEM_CLOCK_DIV_BY_8,
SCG_SYSTEM_CLOCK_DIV_BY_9,
SCG_SYSTEM_CLOCK_DIV_BY_10,
SCG_SYSTEM_CLOCK_DIV_BY_11,
SCG_SYSTEM_CLOCK_DIV_BY_12,
SCG_SYSTEM_CLOCK_DIV_BY_13,
SCG_SYSTEM_CLOCK_DIV_BY_14,
SCG_SYSTEM_CLOCK_DIV_BY_15,
SCG_SYSTEM_CLOCK_DIV_BY_16};
2186 sysClockMode = currentSysClockMode;
2213 if (sysClkConfig == NULL)
2259 sysClockConfig.
src = sysClkSrcMappings[sysClkConfig->
src];
2260 sysClockConfig.
divCore = sysClkDivMappings[sysClkConfig->
core];
2261 sysClockConfig.
divBus = sysClkDivMappings[sysClkConfig->
bus];
2262 sysClockConfig.
divSlow = sysClkDivMappings[sysClkConfig->
slow];
2267 if (sysClockMode == currentSysClockMode)
2291 bool revertTmpSysClkTransition =
false;
2299 if (enable ==
false)
2312 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
2318 if (sircConfig == NULL)
2325 if (((((uint32_t)sircConfig->
modes) & ((uint32_t)
VLPR_MODE)) != 0U) || ((((uint32_t)sircConfig->
modes) & ((uint32_t)
VLPS_MODE)) != 0U))
2335 if (((((uint32_t)sircConfig->
modes) & ((uint32_t)
STOP_MODE)) != 0U))
2344 scgSircConfig.
locked =
false;
2349 scgSircConfig.
range = sircRangeMappings[sircConfig->
range];
2356 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
2377 bool revertTmpSysClkTransition =
false;
2385 if (enable ==
false)
2398 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
2404 if (fircConfig == NULL)
2411 if (((((uint32_t)fircConfig->
modes) & ((uint32_t)
VLPR_MODE)) != 0U) || ((((uint32_t)fircConfig->
modes) & ((uint32_t)
VLPS_MODE)) != 0U))
2421 if (((((uint32_t)fircConfig->
modes) & ((uint32_t)
STOP_MODE)) != 0U))
2430 scgFircConfig.
locked =
false;
2435 scgFircConfig.
range = fircRangeMappings[fircConfig->
range];
2443 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
2464 bool revertTmpSysClkTransition =
false;
2473 if (enable ==
false)
2486 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
2492 if (soscConfig == NULL)
2499 if (((((uint32_t)soscConfig->
modes) & ((uint32_t)
VLPR_MODE)) != 0U) || ((((uint32_t)soscConfig->
modes) & ((uint32_t)
VLPS_MODE)) != 0U))
2509 if (((((uint32_t)soscConfig->
modes) & ((uint32_t)
STOP_MODE)) != 0U))
2518 scgSoscConfig.
freq = soscConfig->
freq;
2521 scgSoscConfig.
locked =
false;
2526 scgSoscConfig.
extRef = soscRefMappings[soscConfig->
ref];
2528 scgSoscConfig.
range = soscRangeMappings[soscConfig->
range];
2535 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
2556 bool revertTmpSysClkTransition =
false;
2562 if (enable ==
false)
2575 revertTmpSysClkTransition = (retCode ==
STATUS_SUCCESS) ?
true :
false;
2581 if (spllConfig == NULL)
2588 if (((((uint32_t)spllConfig->
modes) & ((uint32_t)
STOP_MODE)) != 0U))
2598 scgSpllConfig.
locked =
false;
2603 scgSpllConfig.
mult = (uint8_t) spllConfig->
mult;
2611 if ((retCode ==
STATUS_SUCCESS) && (revertTmpSysClkTransition ==
true))
2632 PMC_SetLpoMode(
PMC,
true);
2636 PMC_SetLpoMode(
PMC,
false);
static scg_system_clock_mode_t CLOCK_SYS_GetCurrentRunMode(void)
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2
scg_async_clock_div_t div1
scg_async_clock_div_t div2
#define SOSC_STABILIZATION_TIMEOUT
scg_async_clock_div_t div1
sim_tclk_config_t tclkConfig
static status_t CLOCK_SYS_TransitionToTmpSysClk(scg_system_clock_src_t currentSysClkSrc)
status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
Configures the system clocks.
static status_t CLOCK_SYS_SetSystemClockConfig(scg_system_clock_mode_t mode, scg_system_clock_config_t const *config)
#define VLPR_SPEED_RUNNING_MODE
scg_async_clock_div_t div2
scg_rtc_config_t rtcConfig
pwr_modes_t
Power mode. Implements pwr_modes_t_Class.
static status_t CLOCK_SYS_ConfigureSPLL(bool enable, const scg_spll_config_t *spllConfig)
#define TMP_SYSTEM_CLOCK_CONFIGS
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1
scg_async_clock_type_t
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
scg_system_clock_type_t
SCG system clock type. Implements scg_system_clock_type_t_Class.
SCG configure structure. Implements scg_config_t_Class.
scg_system_clock_config_t vccrConfig
#define LPO_128K_FREQUENCY
#define HAS_INT_CLOCK_FROM_SLOW_CLOCK
scg_spll_monitor_mode_t monitorMode
scg_async_clock_div_t div2
peripheral_clock_source_t clkSrc
peripheral instance clock configuration. Implements periph_clk_config_t_Class
SIM configure structure. Implements sim_clock_config_t_Class.
scg_firc_range_t
SCG fast IRC clock frequency range. Implements scg_firc_range_t_Class.
uint32_t tclkFreq[NUMBER_OF_TCLK_INPUTS]
void CLOCK_DRV_EnablePeripheralClock(clock_names_t clockName, const periph_clk_config_t *periphClkConfig)
Enables peripheral clock.
static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName, scg_async_clock_type_t divider)
scg_firc_config_t fircConfig
scg_sosc_config_t soscConfig
#define FIRC_STABILIZATION_TIMEOUT
scg_system_clock_mode_t
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
#define LPO_32K_FREQUENCY
scg_sosc_ext_ref_t extRef
sim_trace_clock_config_t traceClockConfig
static uint32_t CLOCK_SYS_GetSimClkOutFreq(void)
#define SPLL_STABILIZATION_TIMEOUT
#define HIGH_SPEED_RUNNING_MODE
sim_rtc_clk_sel_src_t sourceRtcClk
static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t *soscConfig)
peripheral_clock_config_t * peripheralClocks
#define HAS_INT_CLOCK_FROM_BUS_CLOCK
SCG system PLL configuration. Implements scg_spll_config_t_Class.
#define MAX_FREQ_VLPR
Maximum frequencies of core, bus and flash clocks. Each entry represents the maximum frequency of SYS...
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
sim_plat_gate_config_t platGateConfig
static uint32_t CLOCK_SYS_GetSystemClockFreq(scg_system_clock_type_t type)
clock_names_t
Clock names.
static uint32_t CLOCK_SYS_GetSysPllFreq(void)
status_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const *config)
Set system clock configuration.
#define SIRC_STABILIZATION_TIMEOUT
status_t CLOCK_DRV_SetSirc(bool enable, const sirc_config_t *sircConfig)
This function enables or disables SIRC clock source.
static status_t CLOCK_SYS_TransitionSystemClock(const scg_system_clock_config_t *to_clk)
scg_clockout_config_t clockOutConfig
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
void CLOCK_DRV_DisablePeripheralClock(clock_names_t clockName)
Disables peripheral clock.
#define SCG_SPLL_PREDIV_BASE
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
scg_spll_config_t spllConfig
scg_clockout_src_t source
status_t CLOCK_DRV_SetLpo(bool enable)
This function enables or disables LPO clock source.
scg_clock_mode_config_t clockModeConfig
#define SIM_LPO_32K_CLOCK
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
scg_sirc_config_t sircConfig
pmc_lpo_clock_config_t lpoClockConfig
scg_async_clock_div_t div1
static status_t CLOCK_SYS_GetSimClockFreq(clock_names_t clockName, uint32_t *frequency)
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
#define FEATURE_SCG_FIRC_FREQ2
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
scg_sirc_range_t
SCG slow IRC clock frequency range. Implements scg_sirc_range_t_Class.
status_t CLOCK_DRV_SetSpll(bool enable, const spll_config_t *spllConfig)
This function enables or disables SPLL clock source.
const uint16_t clockNameMappings[]
Clock name mappings Constant array storing the mappings between clock names and peripheral clock cont...
scg_system_clock_div_t divCore
#define SCG_SPLL_MULT_BASE
#define SIM_LPO_128K_CLOCK
scg_async_clock_div_t div2
#define CLOCK_MAX_FREQUENCIES
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
scg_system_clock_div_t divSlow
scg_sosc_range_t
SCG OSC frequency range select Implements scg_sosc_range_t_Class.
sim_clock_out_config_t clockOutConfig
status_t CLOCK_SYS_SetScgConfiguration(const scg_config_t *scgConfig)
Configures SCG module.
#define NUMBER_OF_TCLK_INPUTS
static uint32_t CLOCK_SYS_GetSircFreq(void)
scg_async_clock_div_t div1
static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t *fircConfig)
static status_t CLOCK_SYS_GetPccClockFreq(clock_names_t clockName, uint32_t *frequency)
#define MAX_FREQ_MODES_NO
status_t CLOCK_DRV_SetFirc(bool enable, const firc_config_t *fircConfig)
This function enables or disables FIRC clock source.
void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t *simClockConfig)
Configures SIM module.
sim_qspi_ref_clk_gating_t qspiRefClkGating
#define HAS_INT_CLOCK_FROM_SYS_CLOCK
scg_sosc_monitor_mode_t monitorMode
SCG slow IRC clock configuration. Implements sirc_config_t_Class.
peripheral_clock_divider_t divider
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
#define PCC_CLOCK_NAME_MAPPINGS
PCC clock name mappings Mappings between clock names and peripheral clock control indexes...
sim_lpo_clock_config_t lpoClockConfig
static status_t CLOCK_SYS_ConfigureTemporarySystemClock(void)
static status_t CLOCK_SYS_ConfigureModulesFromScg(const scg_config_t *scgConfig)
#define FEATURE_SCG_FIRC_FREQ1
#define RUN_SPEED_RUNNING_MODE
static status_t CLOCK_SYS_GetScgClockFreq(clock_names_t clockName, uint32_t *frequency)
sim_lpoclk_sel_src_t sourceLpoClk
#define FEATURE_SCG_FIRC_FREQ3
void CLOCK_SYS_SetPccConfiguration(const pcc_config_t *peripheralClockConfig)
Configures PCC module.
static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t *sircConfig)
void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t *pmcConfig)
Configures PMC module.
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
const uint8_t peripheralFeaturesList[]
Peripheral features list Constant array storing the mappings between clock names of the peripherals a...
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
#define PERIPHERAL_FEATURES
Peripheral features. List of features for each clock name. If a clock name is not a peripheral...
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
scg_system_clock_config_t rccrConfig
static uint32_t CLOCK_SYS_GetScgClkOutFreq(void)
scg_system_clock_src_t src
#define HAS_CLOCK_GATING_IN_SIM
#define MAX_FREQ_SLOW_CLK
static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource, scg_async_clock_type_t type)
Clock configuration structure. Implements clock_manager_user_config_t_Class.
static uint32_t CLOCK_SYS_GetSysOscFreq(void)
peripheral_clock_frac_t frac
#define FEATURE_SCG_FIRC_FREQ0
scg_sosc_ext_ref_t
SCG OSC external reference clock select. Implements scg_sosc_ext_ref_t_Class.
#define TMP_SIRC_CLK
Temporary system clock source configurations. Each line represents the SYS(CORE), BUS and SLOW(FLASH)...
status_t CLOCK_DRV_SetSosc(bool enable, const sosc_config_t *soscConfig)
This function enables or disables SOSC clock source.
static uint32_t CLOCK_SYS_GetLpoFreq(void)
static uint32_t CLOCK_SYS_GetFircFreq(void)
static uint32_t CLOCK_SYS_GetSimRtcClkFreq(void)
scg_system_clock_config_t hccrConfig
static void CLOCK_SYS_GetCurrentSysClkConfig(scg_system_clock_config_t *sysClockConfig)
scg_system_clock_div_t divBus
system clock configuration. Implements sys_clk_config_t_Class
PCC configuration. Implements pcc_config_t_Class.