S32 SDK
clock_S32K1xx.h File Reference
#include "device_registers.h"
#include "status.h"
#include <stdint.h>
#include <stdbool.h>

Go to the source code of this file.

Data Structures

struct  sim_clock_out_config_t
 SIM ClockOut configuration. Implements sim_clock_out_config_t_Class. More...
 
struct  sim_lpo_clock_config_t
 SIM LPO Clocks configuration. Implements sim_lpo_clock_config_t_Class. More...
 
struct  sim_tclk_config_t
 SIM Platform Gate Clock configuration. Implements sim_tclk_config_t_Class. More...
 
struct  sim_plat_gate_config_t
 SIM Platform Gate Clock configuration. Implements sim_plat_gate_config_t_Class. More...
 
struct  sim_qspi_ref_clk_gating_t
 SIM QSPI reference clock gating. Implements sim_qspi_ref_clk_gating_t_Class. More...
 
struct  sim_trace_clock_config_t
 SIM Debug Trace clock configuration. Implements sim_trace_clock_config_t_Class. More...
 
struct  sim_clock_config_t
 SIM configure structure. Implements sim_clock_config_t_Class. More...
 
struct  scg_system_clock_config_t
 SCG system clock configuration. Implements scg_system_clock_config_t_Class. More...
 
struct  scg_sosc_config_t
 SCG system OSC configuration. Implements scg_sosc_config_t_Class. More...
 
struct  scg_sirc_config_t
 SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class. More...
 
struct  scg_firc_config_t
 SCG fast IRC clock configuration. Implements scg_firc_config_t_Class. More...
 
struct  scg_spll_config_t
 SCG system PLL configuration. Implements scg_spll_config_t_Class. More...
 
struct  scg_rtc_config_t
 SCG RTC configuration. Implements scg_rtc_config_t_Class. More...
 
struct  scg_clock_mode_config_t
 SCG Clock Mode Configuration structure. Implements scg_clock_mode_config_t_Class. More...
 
struct  scg_clockout_config_t
 SCG ClockOut Configuration structure. Implements scg_clockout_config_t_Class. More...
 
struct  scg_config_t
 SCG configure structure. Implements scg_config_t_Class. More...
 
struct  peripheral_clock_config_t
 PCC peripheral instance clock configuration. Implements peripheral_clock_config_t_Class. More...
 
struct  pcc_config_t
 PCC configuration. Implements pcc_config_t_Class. More...
 
struct  pmc_lpo_clock_config_t
 PMC LPO configuration. More...
 
struct  pmc_config_t
 PMC configure structure. More...
 
struct  periph_clk_config_t
 peripheral instance clock configuration. Implements periph_clk_config_t_Class More...
 
struct  sys_clk_config_t
 system clock configuration. Implements sys_clk_config_t_Class More...
 
struct  sirc_config_t
 SCG slow IRC clock configuration. Implements sirc_config_t_Class. More...
 
struct  firc_config_t
 SCG fast IRC clock configuration. Implements scg_firc_config_t_Class. More...
 
struct  sosc_config_t
 SCG system OSC configuration. Implements scg_sosc_config_t_Class. More...
 
struct  spll_config_t
 

Macros

#define NUMBER_OF_TCLK_INPUTS   3U
 

Enumerations

enum  sim_rtc_clk_sel_src_t { SIM_RTCCLK_SEL_SOSCDIV1_CLK = 0x0U, SIM_RTCCLK_SEL_LPO_32K = 0x1U, SIM_RTCCLK_SEL_RTC_CLKIN = 0x2U, SIM_RTCCLK_SEL_FIRCDIV1_CLK = 0x3U }
 SIM CLK32KSEL clock source select Implements sim_rtc_clk_sel_src_t_Class. More...
 
enum  sim_lpoclk_sel_src_t { SIM_LPO_CLK_SEL_LPO_128K = 0x0, SIM_LPO_CLK_SEL_NO_CLOCK = 0x1, SIM_LPO_CLK_SEL_LPO_32K = 0x2, SIM_LPO_CLK_SEL_LPO_1K = 0x3 }
 SIM LPOCLKSEL clock source select Implements sim_lpoclk_sel_src_t_Class. More...
 
enum  sim_clkout_src_t {
  SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT = 0x0U, SIM_CLKOUT_SEL_SYSTEM_SOSC_DIV2_CLK = 0x2U, SIM_CLKOUT_SEL_SYSTEM_SIRC_DIV2_CLK = 0x4U, SIM_CLKOUT_SEL_SYSTEM_FIRC_DIV2_CLK = 0x6U,
  SIM_CLKOUT_SEL_SYSTEM_HCLK = 0x7U, SIM_CLKOUT_SEL_SYSTEM_SPLL_DIV2_CLK = 0x8U, SIM_CLKOUT_SEL_SYSTEM_BUS_CLK = 0x9U, SIM_CLKOUT_SEL_SYSTEM_LPO_128K_CLK = 0x10U,
  SIM_CLKOUT_SEL_SYSTEM_LPO_CLK = 0x12U, SIM_CLKOUT_SEL_SYSTEM_RTC_CLK = 0x14U
}
 SIM CLKOUT select. More...
 
enum  sim_clkout_div_t {
  SIM_CLKOUT_DIV_BY_1 = 0x0U, SIM_CLKOUT_DIV_BY_2 = 0x1U, SIM_CLKOUT_DIV_BY_3 = 0x2U, SIM_CLKOUT_DIV_BY_4 = 0x3U,
  SIM_CLKOUT_DIV_BY_5 = 0x4U, SIM_CLKOUT_DIV_BY_6 = 0x5U, SIM_CLKOUT_DIV_BY_7 = 0x6U, SIM_CLKOUT_DIV_BY_8 = 0x7U
}
 SIM CLKOUT divider. More...
 
enum  clock_trace_src_t { CLOCK_TRACE_SRC_CORE_CLK = 0x0, CLOCK_TRACE_SRC_PLATFORM_CLK = 0x1 }
 Debug trace clock source select Implements clock_trace_src_t_Class. More...
 
enum  scg_system_clock_src_t {
  SCG_SYSTEM_CLOCK_SRC_SYS_OSC = 1U, SCG_SYSTEM_CLOCK_SRC_SIRC = 2U, SCG_SYSTEM_CLOCK_SRC_FIRC = 3U, SCG_SYSTEM_CLOCK_SRC_SYS_PLL = 6U,
  SCG_SYSTEM_CLOCK_SRC_NONE = 255U
}
 SCG system clock source. Implements scg_system_clock_src_t_Class. More...
 
enum  scg_system_clock_div_t {
  SCG_SYSTEM_CLOCK_DIV_BY_1 = 0U, SCG_SYSTEM_CLOCK_DIV_BY_2 = 1U, SCG_SYSTEM_CLOCK_DIV_BY_3 = 2U, SCG_SYSTEM_CLOCK_DIV_BY_4 = 3U,
  SCG_SYSTEM_CLOCK_DIV_BY_5 = 4U, SCG_SYSTEM_CLOCK_DIV_BY_6 = 5U, SCG_SYSTEM_CLOCK_DIV_BY_7 = 6U, SCG_SYSTEM_CLOCK_DIV_BY_8 = 7U,
  SCG_SYSTEM_CLOCK_DIV_BY_9 = 8U, SCG_SYSTEM_CLOCK_DIV_BY_10 = 9U, SCG_SYSTEM_CLOCK_DIV_BY_11 = 10U, SCG_SYSTEM_CLOCK_DIV_BY_12 = 11U,
  SCG_SYSTEM_CLOCK_DIV_BY_13 = 12U, SCG_SYSTEM_CLOCK_DIV_BY_14 = 13U, SCG_SYSTEM_CLOCK_DIV_BY_15 = 14U, SCG_SYSTEM_CLOCK_DIV_BY_16 = 15U
}
 SCG system clock divider value. Implements scg_system_clock_div_t_Class. More...
 
enum  scg_async_clock_div_t {
  SCG_ASYNC_CLOCK_DISABLE = 0U, SCG_ASYNC_CLOCK_DIV_BY_1 = 1U, SCG_ASYNC_CLOCK_DIV_BY_2 = 2U, SCG_ASYNC_CLOCK_DIV_BY_4 = 3U,
  SCG_ASYNC_CLOCK_DIV_BY_8 = 4U, SCG_ASYNC_CLOCK_DIV_BY_16 = 5U, SCG_ASYNC_CLOCK_DIV_BY_32 = 6U, SCG_ASYNC_CLOCK_DIV_BY_64 = 7U
}
 SCG asynchronous clock divider value. More...
 
enum  scg_sosc_monitor_mode_t { SCG_SOSC_MONITOR_DISABLE = 0U, SCG_SOSC_MONITOR_INT = 1U, SCG_SOSC_MONITOR_RESET = 2U }
 SCG system OSC monitor mode. Implements scg_sosc_monitor_mode_t_Class. More...
 
enum  scg_sosc_range_t { SCG_SOSC_RANGE_LOW = 1U, SCG_SOSC_RANGE_MID = 2U, SCG_SOSC_RANGE_HIGH = 3U }
 SCG OSC frequency range select Implements scg_sosc_range_t_Class. More...
 
enum  scg_sosc_gain_t { SCG_SOSC_GAIN_LOW = 0x0, SCG_SOSC_GAIN_HIGH = 0x1 }
 SCG OSC high gain oscillator select. Implements scg_sosc_gain_t_Class. More...
 
enum  scg_sosc_ext_ref_t { SCG_SOSC_REF_EXT = 0x0, SCG_SOSC_REF_OSC = 0x1 }
 SCG OSC external reference clock select. Implements scg_sosc_ext_ref_t_Class. More...
 
enum  scg_sirc_range_t { SCG_SIRC_RANGE_LOW, SCG_SIRC_RANGE_HIGH }
 SCG slow IRC clock frequency range. Implements scg_sirc_range_t_Class. More...
 
enum  scg_firc_range_t { SCG_FIRC_RANGE_48M, SCG_FIRC_RANGE_52M, SCG_FIRC_RANGE_56M, SCG_FIRC_RANGE_60M }
 SCG fast IRC clock frequency range. Implements scg_firc_range_t_Class. More...
 
enum  scg_spll_monitor_mode_t { SCG_SPLL_MONITOR_DISABLE = 0U, SCG_SPLL_MONITOR_INT = 1U, SCG_SPLL_MONITOR_RESET = 2U }
 SCG system PLL monitor mode. Implements scg_spll_monitor_mode_t_Class. More...
 
enum  peripheral_clock_source_t {
  CLK_SRC_OFF = 0x00U, CLK_SRC_SOSC = 0x01U, CLK_SRC_SIRC = 0x02U, CLK_SRC_FIRC = 0x03U,
  CLK_SRC_SPLL = 0x06U
}
 PCC clock source select Implements peripheral_clock_source_t_Class. More...
 
enum  peripheral_clock_frac_t { MULTIPLY_BY_ONE = 0x00U, MULTIPLY_BY_TWO = 0x01U }
 PCC fractional value select Implements peripheral_clock_frac_t_Class. More...
 
enum  peripheral_clock_divider_t {
  DIVIDE_BY_ONE = 0x00U, DIVIDE_BY_TWO = 0x01U, DIVIDE_BY_THREE = 0x02U, DIVIDE_BY_FOUR = 0x03U,
  DIVIDE_BY_FIVE = 0x04U, DIVIDE_BY_SIX = 0x05U, DIVIDE_BY_SEVEN = 0x06U, DIVIDE_BY_EIGTH = 0x07U
}
 PCC divider value select Implements peripheral_clock_divider_t_Class. More...
 
enum  periph_mul_t { DO_NOT_MULTIPLY, MUL_BY_TWO }
 Peripheral multiplier value Implements periph_mul_t_Class. More...
 
enum  periph_div_t {
  DO_NOT_DIVIDE, DIV_BY_TWO, DIV_BY_THREE, DIV_BY_FOUR,
  DIV_BY_FIVE, DIV_BY_SIX, DIV_BY_SEVEN, DIV_BY_EIGTH
}
 Peripheral divider value Implements periph_div_t_Class. More...
 
enum  periph_clk_src_t {
  DISABLE_CLK, SIRC_CLK_SRC, FIRC_CLK_SRC, SOSC_CLK_SRC,
  SPLL_CLK_SRC
}
 Peripheral clock source value Implements periph_clk_src_t_Class. More...
 
enum  sys_clk_src_t { SYS_CLK_SIRC = 0U, SYS_CLK_FIRC = 1U, SYS_CLK_SOSC = 2U, SYS_CLK_SPLL = 3U }
 system clock source. Implements sys_clk_src_t_Class More...
 
enum  sys_clk_div_t {
  SYS_CLK_DO_NOT_DIVIDE = 0U, SYS_CLK_DISABLE_DIVIDER = 1U, SYS_CLK_DIV_BY_2 = 2U, SYS_CLK_DIV_BY_3 = 3U,
  SYS_CLK_DIV_BY_4 = 4U, SYS_CLK_DIV_BY_5 = 5U, SYS_CLK_DIV_BY_6 = 6U, SYS_CLK_DIV_BY_7 = 7U,
  SYS_CLK_DIV_BY_8 = 8U, SYS_CLK_DIV_BY_9 = 9U, SYS_CLK_DIV_BY_10 = 10U, SYS_CLK_DIV_BY_11 = 11U,
  SYS_CLK_DIV_BY_12 = 12U, SYS_CLK_DIV_BY_13 = 13U, SYS_CLK_DIV_BY_14 = 14U, SYS_CLK_DIV_BY_15 = 15U,
  SYS_CLK_DIV_BY_16 = 16U
}
 system clock divider value. Implements sys_clk_div_t_Class More...
 
enum  pwr_modes_t {
  NO_MODE = 0U, RUN_MODE = (1U<<0U), VLPR_MODE = (1U<<1U), HSRUN_MODE = (1U<<2U),
  STOP_MODE = (1U<<3U), VLPS_MODE = (1U<<4U), ALL_MODES = 0x7FFFFFFF
}
 Power mode. Implements pwr_modes_t_Class. More...
 
enum  sirc_range_t { SIRC_RANGE_LOW = 0U, SIRC_RANGE_HIGH = 1U, SIRC_RANGES_MAX = 2U }
 Slow IRC clock frequency range. Implements sirc_range_t_Class. More...
 
enum  firc_range_t {
  FIRC_RANGE_48M = 0U, FIRC_RANGE_52M = 1U, FIRC_RANGE_56M = 2U, FIRC_RANGE_60M = 3U,
  FIRC_RANGES_MAX = 4U
}
 SCG fast IRC clock frequency range. Implements firc_range_t_Class. More...
 
enum  sosc_range_t { LOW_RANGE_SOSC = 0U, MID_RANGE_SOSC = 1U, HIGH_RANGE_SOSC = 2U, SOSC_RANGES_MAX = 3U }
 OSC frequency range select Implements sosc_range_t_Class. More...
 
enum  sosc_ref_t { SOSC_EXT_REF = 0U, SOSC_INT_OSC = 1U, SOSC_REFS_MAX = 2U }
 OSC reference clock select (internal oscillator is bypassed or not) Implements sosc_ext_ref_t_Class. More...
 
enum  spll_clock_div_t {
  SPLL_CLOCK_DIV_BY_1 = 0U, SPLL_CLOCK_DIV_BY_2 = 1U, SPLL_CLOCK_DIV_BY_3 = 2U, SPLL_CLOCK_DIV_BY_4 = 3U,
  SPLL_CLOCK_DIV_BY_5 = 4U, SPLL_CLOCK_DIV_BY_6 = 5U, SPLL_CLOCK_DIV_BY_7 = 6U, SPLL_CLOCK_DIV_BY_8 = 7U
}
 SPLL clock divider value. Implements spll_clock_div_t_Class. More...
 
enum  spll_clock_mul_t {
  SPLL_CLOCK_MUL_BY_16 = 0U, SPLL_CLOCK_MUL_BY_17 = 1U, SPLL_CLOCK_MUL_BY_18 = 2U, SPLL_CLOCK_MUL_BY_19 = 3U,
  SPLL_CLOCK_MUL_BY_20 = 4U, SPLL_CLOCK_MUL_BY_21 = 5U, SPLL_CLOCK_MUL_BY_22 = 6U, SPLL_CLOCK_MUL_BY_23 = 7U,
  SPLL_CLOCK_MUL_BY_24 = 8U, SPLL_CLOCK_MUL_BY_25 = 9U, SPLL_CLOCK_MUL_BY_26 = 10U, SPLL_CLOCK_MUL_BY_27 = 11U,
  SPLL_CLOCK_MUL_BY_28 = 12U, SPLL_CLOCK_MUL_BY_29 = 13U, SPLL_CLOCK_MUL_BY_30 = 14U, SPLL_CLOCK_MUL_BY_31 = 15U,
  SPLL_CLOCK_MUL_BY_32 = 16U, SPLL_CLOCK_MUL_BY_33 = 17U, SPLL_CLOCK_MUL_BY_34 = 18U, SPLL_CLOCK_MUL_BY_35 = 19U,
  SPLL_CLOCK_MUL_BY_36 = 20U, SPLL_CLOCK_MUL_BY_37 = 21U, SPLL_CLOCK_MUL_BY_38 = 22U, SPLL_CLOCK_MUL_BY_39 = 23U,
  SPLL_CLOCK_MUL_BY_40 = 24U, SPLL_CLOCK_MUL_BY_41 = 25U, SPLL_CLOCK_MUL_BY_42 = 26U, SPLL_CLOCK_MUL_BY_43 = 27U,
  SPLL_CLOCK_MUL_BY_44 = 28U, SPLL_CLOCK_MUL_BY_45 = 29U, SPLL_CLOCK_MUL_BY_46 = 30U, SPLL_CLOCK_MUL_BY_47 = 31U
}
 SPLL clock multiplier value. Implements spll_clock_mul_t_Class. More...
 
SCG Clockout.
enum  scg_clockout_src_t {
  SCG_CLOCKOUT_SRC_SCG_SLOW = 0U, SCG_CLOCKOUT_SRC_SOSC = 1U, SCG_CLOCKOUT_SRC_SIRC = 2U, SCG_CLOCKOUT_SRC_FIRC = 3U,
  SCG_CLOCKOUT_SRC_SPLL = 6U
}
 SCG ClockOut type. Implements scg_clockout_src_t_Class. More...
 

Functions

status_t CLOCK_SYS_SetScgConfiguration (const scg_config_t *scgConfig)
 Configures SCG module. More...
 
void CLOCK_SYS_SetPccConfiguration (const pcc_config_t *peripheralClockConfig)
 Configures PCC module. More...
 
void CLOCK_SYS_SetSimConfiguration (const sim_clock_config_t *simClockConfig)
 Configures SIM module. More...
 
void CLOCK_SYS_SetPmcConfiguration (const pmc_config_t *pmcConfig)
 Configures PMC module. More...
 
void CLOCK_DRV_EnablePeripheralClock (clock_names_t clockName, const periph_clk_config_t *periphClkConfig)
 Enables peripheral clock. More...
 
void CLOCK_DRV_DisablePeripheralClock (clock_names_t clockName)
 Disables peripheral clock. More...
 
status_t CLOCK_DRV_SetSystemClock (const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
 Configures the system clocks. More...
 
status_t CLOCK_DRV_SetSirc (bool enable, const sirc_config_t *sircConfig)
 This function enables or disables SIRC clock source. More...
 
status_t CLOCK_DRV_SetFirc (bool enable, const firc_config_t *fircConfig)
 This function enables or disables FIRC clock source. More...
 
status_t CLOCK_DRV_SetSosc (bool enable, const sosc_config_t *soscConfig)
 This function enables or disables SOSC clock source. More...
 
status_t CLOCK_DRV_SetSpll (bool enable, const spll_config_t *spllConfig)
 This function enables or disables SPLL clock source. More...
 
status_t CLOCK_DRV_SetLpo (bool enable)
 This function enables or disables LPO clock source. More...
 

Variables

const uint8_t peripheralFeaturesList [CLOCK_NAME_COUNT]
 Peripheral features list Constant array storing the mappings between clock names of the peripherals and feature lists. More...
 
uint32_t g_TClkFreq [NUMBER_OF_TCLK_INPUTS]
 
uint32_t g_xtal0ClkFreq
 
uint32_t g_RtcClkInFreq
 

Enumeration Type Documentation

SCG fast IRC clock frequency range. Implements firc_range_t_Class.

Enumerator
FIRC_RANGE_48M 

Fast IRC is trimmed to 48MHz.

FIRC_RANGE_52M 

Fast IRC is trimmed to 52MHz.

FIRC_RANGE_56M 

Fast IRC is trimmed to 56MHz.

FIRC_RANGE_60M 

Fast IRC is trimmed to 60MHz.

FIRC_RANGES_MAX 

The total number of options

Definition at line 728 of file clock_S32K1xx.h.

Peripheral clock source value Implements periph_clk_src_t_Class.

Enumerator
DISABLE_CLK 
SIRC_CLK_SRC 
FIRC_CLK_SRC 
SOSC_CLK_SRC 
SPLL_CLK_SRC 

Definition at line 616 of file clock_S32K1xx.h.

Peripheral divider value Implements periph_div_t_Class.

Enumerator
DO_NOT_DIVIDE 
DIV_BY_TWO 
DIV_BY_THREE 
DIV_BY_FOUR 
DIV_BY_FIVE 
DIV_BY_SIX 
DIV_BY_SEVEN 
DIV_BY_EIGTH 

Definition at line 601 of file clock_S32K1xx.h.

Peripheral multiplier value Implements periph_mul_t_Class.

Enumerator
DO_NOT_MULTIPLY 
MUL_BY_TWO 

Definition at line 592 of file clock_S32K1xx.h.

PCC divider value select Implements peripheral_clock_divider_t_Class.

Enumerator
DIVIDE_BY_ONE 
DIVIDE_BY_TWO 
DIVIDE_BY_THREE 
DIVIDE_BY_FOUR 
DIVIDE_BY_FIVE 
DIVIDE_BY_SIX 
DIVIDE_BY_SEVEN 
DIVIDE_BY_EIGTH 

Definition at line 532 of file clock_S32K1xx.h.

PCC fractional value select Implements peripheral_clock_frac_t_Class.

Enumerator
MULTIPLY_BY_ONE 
MULTIPLY_BY_TWO 

Definition at line 523 of file clock_S32K1xx.h.

PCC clock source select Implements peripheral_clock_source_t_Class.

Enumerator
CLK_SRC_OFF 
CLK_SRC_SOSC 
CLK_SRC_SIRC 
CLK_SRC_FIRC 
CLK_SRC_SPLL 

Definition at line 511 of file clock_S32K1xx.h.

Power mode. Implements pwr_modes_t_Class.

Enumerator
NO_MODE 
RUN_MODE 
VLPR_MODE 
HSRUN_MODE 
STOP_MODE 
VLPS_MODE 
ALL_MODES 

Definition at line 690 of file clock_S32K1xx.h.

SCG asynchronous clock divider value.

Enumerator
SCG_ASYNC_CLOCK_DISABLE 

Clock output is disabled.

SCG_ASYNC_CLOCK_DIV_BY_1 

Divided by 1.

SCG_ASYNC_CLOCK_DIV_BY_2 

Divided by 2.

SCG_ASYNC_CLOCK_DIV_BY_4 

Divided by 4.

SCG_ASYNC_CLOCK_DIV_BY_8 

Divided by 8.

SCG_ASYNC_CLOCK_DIV_BY_16 

Divided by 16.

SCG_ASYNC_CLOCK_DIV_BY_32 

Divided by 32.

SCG_ASYNC_CLOCK_DIV_BY_64 

Divided by 64.

Definition at line 287 of file clock_S32K1xx.h.

SCG ClockOut type. Implements scg_clockout_src_t_Class.

Enumerator
SCG_CLOCKOUT_SRC_SCG_SLOW 

SCG SLOW.

SCG_CLOCKOUT_SRC_SOSC 

System OSC.

SCG_CLOCKOUT_SRC_SIRC 

Slow IRC.

SCG_CLOCKOUT_SRC_FIRC 

Fast IRC.

SCG_CLOCKOUT_SRC_SPLL 

System PLL.

Definition at line 273 of file clock_S32K1xx.h.

SCG fast IRC clock frequency range. Implements scg_firc_range_t_Class.

Enumerator
SCG_FIRC_RANGE_48M 

Fast IRC is trimmed to 48MHz.

SCG_FIRC_RANGE_52M 

Fast IRC is trimmed to 52MHz.

SCG_FIRC_RANGE_56M 

Fast IRC is trimmed to 56MHz.

SCG_FIRC_RANGE_60M 

Fast IRC is trimmed to 60MHz.

Definition at line 400 of file clock_S32K1xx.h.

SCG slow IRC clock frequency range. Implements scg_sirc_range_t_Class.

Enumerator
SCG_SIRC_RANGE_LOW 

Slow IRC low range clock (2 MHz).

SCG_SIRC_RANGE_HIGH 

Slow IRC high range clock (8 MHz).

Definition at line 372 of file clock_S32K1xx.h.

SCG OSC external reference clock select. Implements scg_sosc_ext_ref_t_Class.

Enumerator
SCG_SOSC_REF_EXT 
SCG_SOSC_REF_OSC 

Definition at line 336 of file clock_S32K1xx.h.

SCG OSC high gain oscillator select. Implements scg_sosc_gain_t_Class.

Enumerator
SCG_SOSC_GAIN_LOW 
SCG_SOSC_GAIN_HIGH 

Definition at line 326 of file clock_S32K1xx.h.

SCG system OSC monitor mode. Implements scg_sosc_monitor_mode_t_Class.

Enumerator
SCG_SOSC_MONITOR_DISABLE 

Monitor disable.

SCG_SOSC_MONITOR_INT 

Interrupt when system OSC error detected.

SCG_SOSC_MONITOR_RESET 

Reset when system OSC error detected.

Definition at line 304 of file clock_S32K1xx.h.

SCG OSC frequency range select Implements scg_sosc_range_t_Class.

Enumerator
SCG_SOSC_RANGE_LOW 

Low frequency range selected for the crystal OSC (32 kHz to 40 kHz).

SCG_SOSC_RANGE_MID 

Medium frequency range selected for the crystal OSC (1 Mhz to 8 Mhz).

SCG_SOSC_RANGE_HIGH 

High frequency range selected for the crystal OSC (8 Mhz to 40 Mhz).

Definition at line 315 of file clock_S32K1xx.h.

SCG system PLL monitor mode. Implements scg_spll_monitor_mode_t_Class.

Enumerator
SCG_SPLL_MONITOR_DISABLE 

Monitor disable.

SCG_SPLL_MONITOR_INT 

Interrupt when system PLL error detected.

SCG_SPLL_MONITOR_RESET 

Reset when system PLL error detected.

Definition at line 431 of file clock_S32K1xx.h.

Slow IRC clock frequency range. Implements sirc_range_t_Class.

Enumerator
SIRC_RANGE_LOW 

Slow IRC low range clock (2 MHz).

SIRC_RANGE_HIGH 

Slow IRC high range clock (8 MHz).

SIRC_RANGES_MAX 

The total number of options.

Definition at line 706 of file clock_S32K1xx.h.

OSC frequency range select Implements sosc_range_t_Class.

Enumerator
LOW_RANGE_SOSC 

Low frequency range selected for the crystal OSC (32 kHz to 40 kHz).

MID_RANGE_SOSC 

Medium frequency range selected for the crystal OSC (1 Mhz to 8 Mhz).

HIGH_RANGE_SOSC 

High frequency range selected for the crystal OSC (8 Mhz to 40 Mhz).

SOSC_RANGES_MAX 

The total number of options

Definition at line 753 of file clock_S32K1xx.h.

enum sosc_ref_t

OSC reference clock select (internal oscillator is bypassed or not) Implements sosc_ext_ref_t_Class.

Enumerator
SOSC_EXT_REF 
SOSC_INT_OSC 
SOSC_REFS_MAX 

The total number of options

Definition at line 765 of file clock_S32K1xx.h.

SPLL clock divider value. Implements spll_clock_div_t_Class.

Enumerator
SPLL_CLOCK_DIV_BY_1 

Divided by 1.

SPLL_CLOCK_DIV_BY_2 

Divided by 2.

SPLL_CLOCK_DIV_BY_3 

Divided by 3.

SPLL_CLOCK_DIV_BY_4 

Divided by 4.

SPLL_CLOCK_DIV_BY_5 

Divided by 5.

SPLL_CLOCK_DIV_BY_6 

Divided by 6.

SPLL_CLOCK_DIV_BY_7 

Divided by 7.

SPLL_CLOCK_DIV_BY_8 

Divided by 8.

Definition at line 790 of file clock_S32K1xx.h.

SPLL clock multiplier value. Implements spll_clock_mul_t_Class.

Enumerator
SPLL_CLOCK_MUL_BY_16 

Multiplied by 16.

SPLL_CLOCK_MUL_BY_17 

Multiplied by 17.

SPLL_CLOCK_MUL_BY_18 

Multiplied by 18.

SPLL_CLOCK_MUL_BY_19 

Multiplied by 19.

SPLL_CLOCK_MUL_BY_20 

Multiplied by 20.

SPLL_CLOCK_MUL_BY_21 

Multiplied by 21.

SPLL_CLOCK_MUL_BY_22 

Multiplied by 22.

SPLL_CLOCK_MUL_BY_23 

Multiplied by 23.

SPLL_CLOCK_MUL_BY_24 

Multiplied by 24.

SPLL_CLOCK_MUL_BY_25 

Multiplied by 25.

SPLL_CLOCK_MUL_BY_26 

Multiplied by 26.

SPLL_CLOCK_MUL_BY_27 

Multiplied by 27.

SPLL_CLOCK_MUL_BY_28 

Multiplied by 28.

SPLL_CLOCK_MUL_BY_29 

Multiplied by 29.

SPLL_CLOCK_MUL_BY_30 

Multiplied by 30.

SPLL_CLOCK_MUL_BY_31 

Multiplied by 31.

SPLL_CLOCK_MUL_BY_32 

Multiplied by 32.

SPLL_CLOCK_MUL_BY_33 

Multiplied by 33.

SPLL_CLOCK_MUL_BY_34 

Multiplied by 34.

SPLL_CLOCK_MUL_BY_35 

Multiplied by 35.

SPLL_CLOCK_MUL_BY_36 

Multiplied by 36.

SPLL_CLOCK_MUL_BY_37 

Multiplied by 37.

SPLL_CLOCK_MUL_BY_38 

Multiplied by 38.

SPLL_CLOCK_MUL_BY_39 

Multiplied by 39.

SPLL_CLOCK_MUL_BY_40 

Multiplied by 40.

SPLL_CLOCK_MUL_BY_41 

Multiplied by 41.

SPLL_CLOCK_MUL_BY_42 

Multiplied by 42.

SPLL_CLOCK_MUL_BY_43 

Multiplied by 43.

SPLL_CLOCK_MUL_BY_44 

Multiplied by 44.

SPLL_CLOCK_MUL_BY_45 

Multiplied by 45.

SPLL_CLOCK_MUL_BY_46 

Multiplied by 46.

SPLL_CLOCK_MUL_BY_47 

Multiplied by 47.

Definition at line 806 of file clock_S32K1xx.h.

system clock divider value. Implements sys_clk_div_t_Class

Enumerator
SYS_CLK_DO_NOT_DIVIDE 

Divided by 1.

SYS_CLK_DISABLE_DIVIDER 

Divider is disabled, output frequency is zero.

SYS_CLK_DIV_BY_2 

Divided by 2.

SYS_CLK_DIV_BY_3 

Divided by 3.

SYS_CLK_DIV_BY_4 

Divided by 4.

SYS_CLK_DIV_BY_5 

Divided by 5.

SYS_CLK_DIV_BY_6 

Divided by 6.

SYS_CLK_DIV_BY_7 

Divided by 7.

SYS_CLK_DIV_BY_8 

Divided by 8.

SYS_CLK_DIV_BY_9 

Divided by 9.

SYS_CLK_DIV_BY_10 

Divided by 10.

SYS_CLK_DIV_BY_11 

Divided by 11.

SYS_CLK_DIV_BY_12 

Divided by 12.

SYS_CLK_DIV_BY_13 

Divided by 13.

SYS_CLK_DIV_BY_14 

Divided by 14.

SYS_CLK_DIV_BY_15 

Divided by 15.

SYS_CLK_DIV_BY_16 

Divided by 16.

Definition at line 653 of file clock_S32K1xx.h.

system clock source. Implements sys_clk_src_t_Class

Enumerator
SYS_CLK_SIRC 

Slow IRC.

SYS_CLK_FIRC 

Fast IRC.

SYS_CLK_SOSC 

System OSC.

SYS_CLK_SPLL 

System PLL.

Definition at line 641 of file clock_S32K1xx.h.

Function Documentation

void CLOCK_DRV_DisablePeripheralClock ( clock_names_t  clockName)

Disables peripheral clock.

This function disables a peripheral clock.

Parameters
[in]clockNameClock name of the configured peripheral clock

Definition at line 2124 of file clock_S32K1xx.c.

void CLOCK_DRV_EnablePeripheralClock ( clock_names_t  clockName,
const periph_clk_config_t periphClkConfig 
)

Enables peripheral clock.

This function enables a peripheral clock according to the configuration. If no configuration is provided (periphClkConfig is null), then a default one is used

Parameters
[in]clockNameClock name of the configured peripheral clock
[in]periphClkConfigPointer to the configuration structure.

Definition at line 2045 of file clock_S32K1xx.c.

status_t CLOCK_DRV_SetFirc ( bool  enable,
const firc_config_t fircConfig 
)

This function enables or disables FIRC clock source.

When FIRC is enabled, the clock source is configured based on the provided configuration. All values from the previous configuration of FIRC clock are overwritten. If no configuration is provided, then a default one is used. When FIRC is disabled, no configuration is required.

Parameters
[in]enableEnables or disables the clock source.
[in]fircConfigPointer to the configuration structure, this parameter is unused when FIRC is disabled and is optional when FIRC is enabled.
Returns
Status of module initialization

Definition at line 2372 of file clock_S32K1xx.c.

status_t CLOCK_DRV_SetLpo ( bool  enable)

This function enables or disables LPO clock source.

Parameters
[in]enabledEnable command.
Returns
Status of module initialization

Definition at line 2627 of file clock_S32K1xx.c.

status_t CLOCK_DRV_SetSirc ( bool  enable,
const sirc_config_t sircConfig 
)

This function enables or disables SIRC clock source.

When SIRC is enabled, the clock source is configured based on the provided configuration. All values from the previous configuration of SIRC clock are overwritten. If no configuration is provided, then a default one is used. When SIRC is disabled, no configuration is required.

Parameters
[in]enableEnables or disables the clock source.
[in]sircConfigPointer to the configuration structure, this parameter is unused when SIRC is disabled and is optional when SIRC is enabled.
Returns
Status of module initialization

Definition at line 2286 of file clock_S32K1xx.c.

status_t CLOCK_DRV_SetSosc ( bool  enable,
const sosc_config_t soscConfig 
)

This function enables or disables SOSC clock source.

When SOSC is enabled, the clock source is configured based on the provided configuration. All values from the previous configuration of SOSC clock are overwritten. If no configuration is provided, then a default one is used. When SOSC is disabled, no configuration is required.

Parameters
[in]enableEnables or disables the clock source.
[in]soscConfigPointer to the configuration structure, this parameter is unused when SOSC is disabled and is optional when SOSC is enabled.
Returns
Status of module initialization

Definition at line 2459 of file clock_S32K1xx.c.

status_t CLOCK_DRV_SetSpll ( bool  enable,
const spll_config_t spllConfig 
)

This function enables or disables SPLL clock source.

When SPLL is enabled, the clock source is configured based on the provided configuration. All values from the previous configuration of SPLL clock are overwritten. If no configuration is provided, then a default one is used. When SPLL is disabled, no configuration is required.

Parameters
[in]enableEnables or disables the clock source.
[in]spllConfigPointer to the configuration structure, this parameter is unused when SPLL is disabled and is optional when SPLL is enabled.
Returns
Status of module initialization

Definition at line 2551 of file clock_S32K1xx.c.

status_t CLOCK_DRV_SetSystemClock ( const pwr_modes_t mode,
const sys_clk_config_t sysClkConfig 
)

Configures the system clocks.

This function configures the system clocks (core, bus and flash clocks) in the specified power mode. If no power mode is specified (null parameter) then it is the current power mode.

Parameters
[in]modePointer to power mode for which the configured system clocks apply
[in]sysClkConfigPointer to the system clocks configuration structure.

Definition at line 2171 of file clock_S32K1xx.c.

void CLOCK_SYS_SetPccConfiguration ( const pcc_config_t peripheralClockConfig)

Configures PCC module.

This function configures the PCC module according to the configuration.

Parameters
[in]peripheralClockConfigPointer to the configuration structure.

Definition at line 334 of file clock_S32K1xx.c.

void CLOCK_SYS_SetPmcConfiguration ( const pmc_config_t pmcConfig)

Configures PMC module.

This function configures the PMC module according to the configuration.

Parameters
[in]pmcConfigPointer to the configuration structure.

Definition at line 430 of file clock_S32K1xx.c.

status_t CLOCK_SYS_SetScgConfiguration ( const scg_config_t scgConfig)

Configures SCG module.

This function configures the SCG module according to the configuration.

Parameters
[in]scgConfigPointer to the configuration structure.
Returns
Status of module initialization

Definition at line 274 of file clock_S32K1xx.c.

void CLOCK_SYS_SetSimConfiguration ( const sim_clock_config_t simClockConfig)

Configures SIM module.

This function configures the SIM module according to the configuration.

Parameters
[in]simClockConfigPointer to the configuration structure.

Definition at line 365 of file clock_S32K1xx.c.