87 uint8_t DEPartitionCode)
109 #if (FEATURE_FLS_IS_FTFC == 0U)
117 uint8_t EEEDataSetSize)
154 #if FEATURE_FLS_HAS_FLEX_NVM
155 uint8_t DEPartitionCode;
164 #if FEATURE_FLS_HAS_FLEX_NVM
169 FLASH_DRV_GetDEPartitionCode(pSSDConfig, DEPartitionCode);
200 FTFx_FSTAT |= FTFx_FSTAT_CCIF_MASK;
202 while (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
219 if ((FTFx_FSTAT & (FTFx_FSTAT_MGSTAT0_MASK | FTFx_FSTAT_FPVIOL_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_RDCOLERR_MASK)) != 0U)
241 uint32_t reg0, reg1, reg2, reg3;
248 *protectStatus = (uint32_t)((reg0 << 24U) | (reg1 << 16U) | (reg2 << 8U) | reg3);
264 uint8_t reg0, reg1, reg2, reg3;
265 bool flag0, flag1, flag2, flag3;
280 flag0 = (FTFx_FPROT0 != reg0);
281 flag1 = (FTFx_FPROT1 != reg1);
282 flag2 = (FTFx_FPROT2 != reg2);
283 flag3 = (FTFx_FPROT3 != reg3);
286 if (flag0 || flag1 || flag2 || flag3)
309 regValue = FTFx_FSEC;
322 if (0x80U == (regValue & FTFx_FSEC_KEYEN_MASK))
345 const uint8_t * keyBuffer)
354 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
365 for (i = 0U; i < 8U; i++)
367 temp = FTFx_BASE + i + 0x08U;
368 *(uint8_t *)temp = keyBuffer[i];
391 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
426 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
437 FTFx_FCCOB1 = marginLevel;
463 uint32_t tempSize = size;
465 #if FEATURE_FLS_HAS_FLEX_NVM
467 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
469 dest += 0x800000U - temp;
476 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
490 if ((tempSize & (sectorSize - 1U)) != 0U)
499 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
518 tempSize -= sectorSize;
544 #if FEATURE_FLS_HAS_FLEX_NVM
546 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
548 dest += 0x800000U - temp;
554 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
567 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
583 FTFx_FCCOB6 = marginLevel;
606 if ((FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK) == 0U)
608 FTFx_FCNFG |= FTFx_FCNFG_ERSSUSP_MASK;
611 while (((FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK) == 0U) && (count > 0U))
632 if ((FTFx_FCNFG & FTFx_FCNFG_ERSSUSP_MASK) == FTFx_FCNFG_ERSSUSP_MASK)
635 FTFx_FSTAT |= FTFx_FSTAT_CCIF_MASK;
637 while ((0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK)) && (i <
RESUME_WAIT_CNT))
654 uint8_t * pDataArray)
663 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
674 FTFx_FCCOB1 = recordIndex;
685 temp = FTFx_BASE + i + 0x08U;
686 pDataArray[i] = *(uint8_t *)temp;
705 const uint8_t * pDataArray)
714 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
725 FTFx_FCCOB1 = recordIndex;
729 temp = FTFx_BASE + i + 0x08U;
730 *(uint8_t *)temp = pDataArray[i];
740 #if FEATURE_FLS_HAS_READ_RESOURCE_CMD
750 uint8_t * pDataArray,
751 uint8_t resourceSelectCode)
760 #if FEATURE_FLS_HAS_FLEX_NVM
762 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
764 dest += 0x800000U - temp;
770 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
783 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
805 temp = FTFx_BASE + i + 0x08U;
806 pDataArray[i] = *(uint8_t *)temp;
829 const uint8_t * pData)
843 #if FEATURE_FLS_HAS_FLEX_NVM
845 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
847 dest += 0x800000U - temp;
853 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
866 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
876 #if (FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE == FTFx_PHRASE_SIZE)
887 temp = FTFx_BASE + i + 0x08U;
888 *(uint8_t *)(temp) = pData[i];
920 const uint8_t * pExpectedData,
921 uint32_t * pFailAddr,
930 uint32_t tempSize = size;
940 #if FEATURE_FLS_HAS_FLEX_NVM
942 if ((dest >= offsetAddr) && (dest < (offsetAddr + pSSDConfig->
DFlashSize)))
944 dest += 0x800000U - offsetAddr;
950 if ((dest >= offsetAddr) && (dest < (offsetAddr + pSSDConfig->
PFlashSize)))
961 while (tempSize > 0U)
964 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
978 FTFx_FCCOB4 = marginLevel;
982 temp = FTFx_BASE + i + 0x0CU;
983 *(uint8_t *)(temp) = pExpectedData[i];
992 #if FEATURE_FLS_HAS_FLEX_NVM
993 if (dest >= 0x800000U)
995 *pFailAddr = dest + offsetAddr - 0x800000U;
1000 *pFailAddr = dest + offsetAddr;
1041 uint32_t counter = 0U;
1043 uint32_t endAddress;
1044 uint32_t tempSize = size;
1047 endAddress = dest + tempSize;
1050 if ((dest < pSSDConfig->PFlashBase) || (endAddress > (pSSDConfig->
PFlashBase + pSSDConfig->
PFlashSize)))
1052 #if FEATURE_FLS_HAS_FLEX_NVM
1053 if ((dest < pSSDConfig->DFlashBase) || (endAddress > (pSSDConfig->
DFlashBase + pSSDConfig->
DFlashSize)))
1058 #if FEATURE_FLS_HAS_FLEX_NVM
1065 while (tempSize > 0U)
1067 data = *(uint8_t *)(dest);
1090 #if FEATURE_FLS_HAS_PROGRAM_SECTION_CMD
1116 if (0U == (FTFx_FCNFG & FTFx_FCNFG_RAMRDY_MASK))
1123 #if FEATURE_FLS_HAS_FLEX_NVM
1125 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
1127 dest += 0x800000U - temp;
1133 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
1146 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
1174 #if FEATURE_FLS_HAS_ERASE_BLOCK_CMD
1192 #if FEATURE_FLS_HAS_FLEX_NVM
1194 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
1196 dest += 0x800000U - temp;
1202 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
1215 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
1239 #if FEATURE_FLS_HAS_READ_1S_BLOCK_CMD
1251 uint8_t marginLevel)
1258 #if FEATURE_FLS_HAS_FLEX_NVM
1260 if ((dest >= temp) && (dest < (temp + pSSDConfig->
DFlashSize)))
1262 dest += 0x800000U - temp;
1268 if ((dest >= temp) && (dest < (temp + pSSDConfig->
PFlashSize)))
1281 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
1295 FTFx_FCCOB4 = marginLevel;
1306 #if FEATURE_FLS_HAS_FLEX_NVM
1317 status_t FLASH_DRV_GetEERAMProtection(uint8_t * protectStatus)
1323 if ((FTFx_FCNFG & FTFx_FCNFG_EEERDY_MASK) == FTFx_FCNFG_EEERDY_MASK)
1325 *protectStatus = FTFx_FEPROT;
1345 status_t FLASH_DRV_SetEERAMProtection(uint8_t protectStatus)
1350 if (0U == (FTFx_FCNFG & FTFx_FCNFG_EEERDY_MASK))
1357 FTFx_FEPROT = protectStatus;
1358 if (protectStatus != FTFx_FEPROT)
1387 uint16_t byteOfQuickWrite,
1394 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
1405 FTFx_FCCOB1 = (uint8_t)flexRamFuncCode;
1409 FTFx_FCCOB4 = (uint8_t)(byteOfQuickWrite >> 0x8U);
1410 FTFx_FCCOB5 = (uint8_t)(byteOfQuickWrite & 0xFFU);
1418 if (pEEPROMStatus == NULL)
1444 const uint8_t * pData,
1453 *(uint8_t *)dest = *pData;
1458 temp = (uint32_t)(pData[1]) << 8U;
1459 temp |= (uint32_t)(pData[0]);
1460 *(
volatile uint16_t *)dest = (uint16_t)temp;
1465 temp = (uint32_t)(pData[3]) << 24U;
1466 temp |= (uint32_t)(pData[2]) << 16U;
1467 temp |= (uint32_t)(pData[1]) << 8U;
1468 temp |= (uint32_t)(pData[0]);
1469 *(
volatile uint32_t *)dest = temp;
1472 while (0U == (FTFx_FCNFG & FTFx_FCNFG_EEERDY_MASK))
1484 if ((FTFx_FSTAT & (FTFx_FSTAT_MGSTAT0_MASK | FTFx_FSTAT_FPVIOL_MASK | FTFx_FSTAT_ACCERR_MASK | FTFx_FSTAT_RDCOLERR_MASK)) != 0U)
1514 const uint8_t * pData)
1522 if ((FTFx_FCNFG & FTFx_FCNFG_EEERDY_MASK) == FTFx_FCNFG_EEERDY_MASK)
1525 if ((dest < pSSDConfig->EERAMBase) || ((dest + size) > (pSSDConfig->
EERAMBase + pSSDConfig->
EEESize)))
1533 if ((0U == (dest & 3U)) && (size >= 4U))
1537 else if ((0U == (dest & 1U)) && (size >= 2U))
1546 ret = FLASH_DRV_WaitEEWriteToFinish(pSSDConfig,
1577 uint8_t uEEEDataSizeCode,
1578 uint8_t uDEPartitionCode,
1579 uint8_t uCSEcKeySize,
1581 bool flexRamEnableLoadEEEData)
1588 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
1599 FTFx_FCCOB1 = uCSEcKeySize;
1600 FTFx_FCCOB2 = (uint8_t)(uSFE ? 1U : 0U);
1601 FTFx_FCCOB3 = (uint8_t)(flexRamEnableLoadEEEData ? 0U : 1U);
1602 FTFx_FCCOB4 = uEEEDataSizeCode;
1603 FTFx_FCCOB5 = uDEPartitionCode;
1622 uint8_t * protectStatus)
1635 *protectStatus = FTFx_FDPROT;
1652 uint8_t protectStatus)
1664 FTFx_FDPROT = protectStatus;
1665 if (protectStatus != FTFx_FDPROT)
1679 #if FEATURE_FLS_HAS_PF_BLOCK_SWAP
1707 flash_swap_callback_t pSwapCallback)
1712 uint8_t currentSwapMode, currentSwapBlockStatus, nextSwapBlockStatus;
1714 currentSwapMode = 0xFFU;
1715 currentSwapBlockStatus = 0xFFU;
1716 nextSwapBlockStatus = 0xFFU;
1717 swapContinue =
false;
1720 ret = FLASH_DRV_PFlashSwapCtl(pSSDConfig, addr,
FTFx_SWAP_REPORT_STATUS, ¤tSwapMode, ¤tSwapBlockStatus, &nextSwapBlockStatus);
1730 ret = FLASH_DRV_PFlashSwapCtl(pSSDConfig,
1734 ¤tSwapBlockStatus,
1735 &nextSwapBlockStatus);
1741 ret = FLASH_DRV_PFlashSwapCtl(pSSDConfig,
1745 ¤tSwapBlockStatus,
1746 &nextSwapBlockStatus);
1756 if ((NULL_SWAP_CALLBACK != pSwapCallback) && (
STATUS_SUCCESS == ret))
1758 swapContinue = pSwapCallback(currentSwapMode);
1760 if (swapContinue ==
true)
1763 ret = FLASH_DRV_PFlashSwapCtl(pSSDConfig,
1767 ¤tSwapBlockStatus,
1768 &nextSwapBlockStatus);
1777 if ((NULL_SWAP_CALLBACK == pSwapCallback) && (
FTFx_SWAP_UPDATE == currentSwapMode))
1784 ret = FLASH_DRV_PFlashSwapCtl(pSSDConfig,
1788 ¤tSwapBlockStatus,
1789 &nextSwapBlockStatus);
1796 if (NULL_SWAP_CALLBACK == pSwapCallback)
1798 swapContinue =
true;
1802 swapContinue = pSwapCallback(currentSwapMode);
1805 if (swapContinue ==
true)
1808 ret = FLASH_DRV_PFlashSwapCtl(pSSDConfig,
1812 ¤tSwapBlockStatus,
1813 &nextSwapBlockStatus);
1831 uint8_t * pCurrentSwapMode,
1832 uint8_t * pCurrentSwapBlockStatus,
1833 uint8_t * pNextSwapBlockStatus)
1842 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
1856 FTFx_FCCOB4 = swapcmd;
1857 FTFx_FCCOB5 = 0xFFU;
1858 FTFx_FCCOB6 = 0xFFU;
1859 FTFx_FCCOB7 = 0xFFU;
1866 *pCurrentSwapMode = FTFx_FCCOB5;
1867 *pCurrentSwapBlockStatus = FTFx_FCCOB6;
1868 *pNextSwapBlockStatus = FTFx_FCCOB7;
1876 #if FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD
1891 if (0U == (FTFx_FSTAT & FTFx_FSTAT_CCIF_MASK))
#define FTFx_SWAP_SET_IN_COMPLETE
Set Swap in Complete State.
status_t FLASH_DRV_VerifyAllBlock(const flash_ssd_config_t *pSSDConfig, uint8_t marginLevel)
Flash verify all blocks.
#define NULL_CALLBACK
Null callback.
#define FEATURE_FLS_EE_SIZE_1001
#define FEATURE_FLS_DF_SIZE_1011
#define FTFx_VERIFY_BLOCK
#define FTFx_VERIFY_SECTION
uint16_t sectorEraseCount
void FLASH_DRV_EraseResume(void)
Flash erase resume.
flash_callback_t CallBack
#define FEATURE_FLS_EE_SIZE_0111
#define FEATURE_FLS_EE_SIZE_0011
#define FEATURE_FLS_EE_SIZE_1000
#define CLEAR_FTFx_FSTAT_ERROR_BITS
#define FTFx_SWAP_SET_IN_PREPARE
Set Swap in Update State.
#define FEATURE_FLS_DF_SIZE_1001
#define FLASH_NOT_SECURE
Flash currently not in secure state.
void FLASH_DRV_EraseSuspend(void)
Flash erase suspend.
#define FEATURE_FLS_EE_SIZE_0100
#define FTFx_PROGRAM_ONCE
#define FLASH_SECURE_BACKDOOR_DISABLED
Flash is secured and backdoor key access disabled.
status_t FLASH_DRV_EraseSector(const flash_ssd_config_t *pSSDConfig, uint32_t dest, uint32_t size)
Flash erase sector.
#define GET_BIT_0_7(value)
#define FEATURE_FLS_DF_SIZE_0010
#define FEATURE_FLS_FLEX_RAM_SIZE
#define END_FUNCTION_DECLARATION_RAMSECTION
#define FTFx_SWAP_UPDATE
Update swap mode.
#define FEATURE_FLS_DF_SIZE_1100
#define FLASH_CALLBACK_CS
Callback period count for FlashCheckSum.
#define FTFx_PROGRAM_CHECK
#define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE
#define FEATURE_FLS_EE_SIZE_1111
status_t FLASH_DRV_Init(const flash_user_config_t *const pUserConf, flash_ssd_config_t *const pSSDConfig)
Initializes Flash.
#define FTFx_SECURITY_BY_PASS
#define FTFx_ERASE_ALL_BLOCK
#define FEATURE_FLS_EE_SIZE_0000
status_t FLASH_DRV_Program(const flash_ssd_config_t *pSSDConfig, uint32_t dest, uint32_t size, const uint8_t *pData)
Flash program.
#define FTFx_ERASE_ALL_BLOCK_UNSECURE
#define FTFx_SWAP_REPORT_STATUS
Report Swap Status.
#define FTFx_SWAP_READY
Ready swap mode.
#define FEATURE_FLS_EE_SIZE_1011
#define FEATURE_FLS_DF_BLOCK_SIZE
#define CSE_KEY_SIZE_CODE_MAX
#define FEATURE_FLS_DF_SIZE_1111
flash_flexRam_function_control_code_t
FlexRAM Function control Code.
#define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE
#define SIM_FCFG1_DEPART_SHIFT
#define FEATURE_FLS_DF_SIZE_0110
#define FTFx_RSRC_CODE_REG
#define FEATURE_FLS_DF_SIZE_1000
#define FEATURE_FLS_EE_SIZE_1101
#define FEATURE_FLS_EE_SIZE_1010
static START_FUNCTION_DECLARATION_RAMSECTION status_t FLASH_DRV_CommandSequence(const flash_ssd_config_t *pSSDConfig) END_FUNCTION_DECLARATION_RAMSECTION static void FLASH_DRV_GetDEPartitionCode(flash_ssd_config_t *const pSSDConfig
#define GET_BIT_8_15(value)
void FLASH_DRV_GetPFlashProtection(uint32_t *protectStatus)
P-Flash get protection.
status_t FLASH_DRV_ProgramCheck(const flash_ssd_config_t *pSSDConfig, uint32_t dest, uint32_t size, const uint8_t *pExpectedData, uint32_t *pFailAddr, uint8_t marginLevel)
Flash program check.
#define ENABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define END_FUNCTION_DEFINITION_RAMSECTION
#define FTFx_SWAP_SET_INDICATOR_ADDR
Initialize Swap System control code.
#define FEATURE_FLS_EE_SIZE_0101
status_t FLASH_DRV_CheckSum(const flash_ssd_config_t *pSSDConfig, uint32_t dest, uint32_t size, uint32_t *pSum)
Calculates check sum.
#define FTFx_PROGRAM_LONGWORD
#define GET_BIT_24_31(value)
#define START_FUNCTION_DECLARATION_RAMSECTION
Places a function in RAM.
#define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE
#define FEATURE_FLS_EE_SIZE_1100
#define SUSPEND_WAIT_CNT
Suspend wait count used in FLASH_DRV_EraseSuspend function.
#define FEATURE_FLS_EE_SIZE_0010
#define FLASH_SECURITY_STATE_UNSECURED
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
#define FEATURE_FLS_DF_SIZE_0001
#define START_FUNCTION_DEFINITION_RAMSECTION
uint16_t numOfRecordReqMaintain
status_t FLASH_DRV_SetPFlashProtection(uint32_t protectStatus)
P-Flash set protection.
#define DISABLE_CHECK_RAMSECTION_FUNCTION_CALL
#define FEATURE_FLS_DF_SIZE_0011
#define FEATURE_FLS_DF_SIZE_1101
#define FEATURE_FLS_DF_SIZE_0000
#define FTFx_SWAP_UPDATE_ERASED
Update-Erased swap mode.
#define FTFx_PROGRAM_PHRASE
#define FTFx_READ_RESOURCE
status_t FLASH_DRV_VerifySection(const flash_ssd_config_t *pSSDConfig, uint32_t dest, uint16_t number, uint8_t marginLevel)
Flash verify section.
status_t FLASH_DRV_ReadOnce(const flash_ssd_config_t *pSSDConfig, uint8_t recordIndex, uint8_t *pDataArray)
Flash read once.
#define FEATURE_FLS_DF_SIZE_0111
#define FTFx_VERIFY_ALL_BLOCK
#define FEATURE_FLS_DF_SIZE_1010
#define FTFx_PROGRAM_SECTION
Flash SSD Configuration Structure.
#define FEATURE_FLS_EE_SIZE_1110
status_t FLASH_DRV_EraseAllBlock(const flash_ssd_config_t *pSSDConfig)
Flash erase all blocks.
#define FTFx_ERASE_SECTOR
#define SIM_FCFG1_DEPART_MASK
#define FLASH_SECURE_BACKDOOR_ENABLED
Flash is secured and backdoor key access enabled.
#define FEATURE_FLS_EE_SIZE_0110
#define GET_BIT_16_23(value)
#define RESUME_WAIT_CNT
Resume wait count used in FLASH_DRV_EraseResume function.
#define FEATURE_FLS_DF_SIZE_0101
#define FTFx_SWAP_UNINIT
Uninitialized swap mode.
Flash User Configuration Structure.
status_t FLASH_DRV_SecurityBypass(const flash_ssd_config_t *pSSDConfig, const uint8_t *keyBuffer)
Flash security bypass.
#define FEATURE_FLS_EE_SIZE_0001
#define FEATURE_FLS_DF_SIZE_1110
#define FTFx_PROGRAM_PARTITION
status_t FLASH_DRV_ProgramOnce(const flash_ssd_config_t *pSSDConfig, uint8_t recordIndex, const uint8_t *pDataArray)
Flash program once.
#define FEATURE_FLS_DF_SIZE_0100
#define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT
void FLASH_DRV_GetSecurityState(uint8_t *securityState)
Flash get security state.