S32 SDK

#include <S32K142.h>

Data Fields

__I uint32_t VERID
 
__I uint32_t PARAM
 
__IO uint32_t MCR
 
__IO uint32_t MSR
 
__IO uint32_t MIER
 
__IO uint32_t SETTEN
 
__IO uint32_t CLRTEN
 
uint8_t RESERVED_0 [4]
 
struct {
   __IO uint32_t   TVAL
 
   __I uint32_t   CVAL
 
   __IO uint32_t   TCTRL
 
   uint8_t   RESERVED_0 [4]
 
TMR [LPIT_TMR_COUNT]
 

Detailed Description

LPIT - Register Layout Typedef

Definition at line 5884 of file S32K142.h.

Field Documentation

__IO uint32_t CLRTEN

Clear Timer Enable Register, offset: 0x18

Definition at line 5891 of file S32K142.h.

__I uint32_t CVAL

Current Timer Value, array offset: 0x24, array step: 0x10

Definition at line 5895 of file S32K142.h.

__IO uint32_t MCR

Module Control Register, offset: 0x8

Definition at line 5887 of file S32K142.h.

__IO uint32_t MIER

Module Interrupt Enable Register, offset: 0x10

Definition at line 5889 of file S32K142.h.

__IO uint32_t MSR

Module Status Register, offset: 0xC

Definition at line 5888 of file S32K142.h.

__I uint32_t PARAM

Parameter Register, offset: 0x4

Definition at line 5886 of file S32K142.h.

uint8_t RESERVED_0[4]

Definition at line 5892 of file S32K142.h.

__IO uint32_t SETTEN

Set Timer Enable Register, offset: 0x14

Definition at line 5890 of file S32K142.h.

__IO uint32_t TCTRL

Timer Control Register, array offset: 0x28, array step: 0x10

Definition at line 5896 of file S32K142.h.

struct { ... } TMR[LPIT_TMR_COUNT]
__IO uint32_t TVAL

Timer Value Register, array offset: 0x20, array step: 0x10

Definition at line 5894 of file S32K142.h.

__I uint32_t VERID

Version ID Register, offset: 0x0

Definition at line 5885 of file S32K142.h.


The documentation for this struct was generated from the following file: