100 WDOG->TOVAL = (uint32_t )0xFFFF;
106 #ifdef SYSTEM_SMC_PMPROT_VALUE
108 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
123 uint32_t SCGOUTClock = 0U;
125 uint32_t divider, prediv, multi;
126 bool validSystemClockSource =
true;
127 static const uint32_t fircFreq[] = {
144 SCGOUTClock = (regValue != 0U) ?
150 SCGOUTClock= fircFreq[regValue];
157 SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
160 validSystemClockSource =
false;
164 if (validSystemClockSource ==
true) {
#define SCG_SPLLCFG_MULT_MASK
#define SCG_FIRCCFG_RANGE_SHIFT
#define WDOG_CS_CMD32EN_SHIFT
#define WDOG_CS_CLK_SHIFT
#define S32_SCB_AIRCR_SYSRESETREQ(x)
#define SCG_FIRCCFG_RANGE_MASK
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock variable.
#define S32_SCB_CPACR_CP10_MASK
#define SCG_CSR_DIVCORE_SHIFT
#define FEATURE_SCB_VECTKEY
#define SCG_CSR_DIVCORE_MASK
#define S32_SCB_AIRCR_VECTKEY(x)
Device specific configuration file for S32K142.
#define SCG_CSR_SCS_SHIFT
#define FEATURE_SCG_FIRC_FREQ2
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
#define DEFAULT_SYSTEM_CLOCK
uint32_t SystemCoreClock
System clock frequency (core clock)
void SystemInit(void)
Setup the SoC.
#define SCG_SPLLCFG_PREDIV_MASK
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
#define S32_SCB_FPCCR_LSPEN_MASK
#define S32_SCB_AIRCR_VECTKEY_MASK
#define SCG_SIRCCFG_RANGE_SHIFT
#define FEATURE_SCG_FIRC_FREQ1
#define FEATURE_WDOG_CLK_FROM_LPO
#define FEATURE_SCG_FIRC_FREQ3
#define SCG_SPLLCFG_MULT_SHIFT
#define SCG_SPLLCFG_PREDIV_SHIFT
#define S32_SCB_CPACR_CP11_MASK
void SystemSoftwareReset(void)
Initiates a system reset.
#define FEATURE_SCG_FIRC_FREQ0
#define SCG_SIRCCFG_RANGE_MASK
#define WDOG_CS_UPDATE_SHIFT
#define FEATURE_WDOG_UNLOCK_VALUE