S32 SDK
pins_driver.h
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1 /*
2  * Copyright (c) 2014 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef PINS_DRIVER_H
20 #define PINS_DRIVER_H
21 
22 #include <stddef.h>
23 #include "device_registers.h"
24 #include "status.h"
25 
33 /*******************************************************************************
34  * Definitions
35  ******************************************************************************/
36 #if defined(FEATURE_PINS_DRIVER_USING_PORT)
37 
41 typedef uint32_t pins_channel_type_t;
42 
43 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
44 
48 typedef uint16_t pins_channel_type_t;
49 
50 #endif /* if defined(FEATURE_PINS_DRIVER_USING_PORT) */
51 
56 typedef uint8_t pins_level_type_t;
57 
62 typedef enum
63 {
68 
69 #if FEATURE_PINS_HAS_PULL_SELECTION
70 
74 typedef enum
75 {
76  PORT_INTERNAL_PULL_NOT_ENABLED = 0U,
77  PORT_INTERNAL_PULL_DOWN_ENABLED = 1U,
78  PORT_INTERNAL_PULL_UP_ENABLED = 2U
79 } port_pull_config_t;
80 #endif
81 
82 #if FEATURE_PINS_HAS_OPEN_DRAIN
83 
87 typedef enum
88 {
89  PORT_OPEN_DRAIN_DISABLED = 0U,
90  PORT_OPEN_DRAIN_ENABLED = 1U
91 } port_open_drain_t;
92 #endif /* FEATURE_PINS_HAS_OPEN_DRAIN */
93 
94 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
95 
99 typedef enum
100 {
101 #if FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL
102  PORT_STRENGTH_DISABLED = 0U,
103  PORT_LOW_DRIVE_STRENGTH = 1U,
104  PORT_STR1_DRIVE_STRENGTH = 1U,
105  PORT_STR2_DRIVE_STRENGTH = 2U,
106  PORT_STR3_DRIVE_STRENGTH = 3U,
107  PORT_STR4_DRIVE_STRENGTH = 4U,
108  PORT_STR5_DRIVE_STRENGTH = 5U,
109  PORT_STR6_DRIVE_STRENGTH = 6U,
110  PORT_STR7_DRIVE_STRENGTH = 7U,
111  PORT_HIGH_DRIVE_STRENGTH = 7U
112 #else /* if not FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL */
113  PORT_LOW_DRIVE_STRENGTH = 0U,
114  PORT_HIGH_DRIVE_STRENGTH = 1U
115 #endif /* if FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL */
116 } port_drive_strength_t;
117 #endif /* FEATURE_PINS_HAS_DRIVE_STRENGTH */
118 
119 #ifdef FEATURE_PINS_DRIVER_USING_PORT
120 
124 typedef enum
125 {
126  PORT_PIN_DISABLED = 0U,
127  PORT_MUX_AS_GPIO = 1U,
128  PORT_MUX_ALT2 = 2U,
129  PORT_MUX_ALT3 = 3U,
130  PORT_MUX_ALT4 = 4U,
131  PORT_MUX_ALT5 = 5U,
132  PORT_MUX_ALT6 = 6U,
133  PORT_MUX_ALT7 = 7U
134 } port_mux_t;
135 
140 typedef enum
141 {
142  PORT_DMA_INT_DISABLED = 0x0U,
143 #if FEATURE_PORT_HAS_DMA_REQUEST
144  PORT_DMA_RISING_EDGE = 0x1U,
145  PORT_DMA_FALLING_EDGE = 0x2U,
146  PORT_DMA_EITHER_EDGE = 0x3U,
147 #endif
148  PORT_INT_LOGIC_ZERO = 0x8U,
149  PORT_INT_RISING_EDGE = 0x9U,
150  PORT_INT_FALLING_EDGE = 0xAU,
151  PORT_INT_EITHER_EDGE = 0xBU,
152  PORT_INT_LOGIC_ONE = 0xCU
153 } port_interrupt_config_t;
154 
155 #if FEATURE_PINS_HAS_SLEW_RATE
156 
160 typedef enum
161 {
162  PORT_FAST_SLEW_RATE = 0U,
163  PORT_SLOW_SLEW_RATE = 1U
164 } port_slew_rate_t;
165 #endif
166 
167 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
168 #if FEATURE_SIUL2_HAS_DDR_PAD
169 
175 typedef enum
176 {
177  DDR_DDR3_MODE = 0x0U,
178  DDR_LPDDR2_MODE = 0x2U
179 } port_ddr_type_t;
180 
189 typedef enum
190 {
191  DDR_MIN_DELAY = 0x0U,
192  DDR_50PS_DELAY = 0x1U,
193  DDR_100PS_DELAY = 0x2U,
194  DDR_150PS_DELAY = 0x3U
195 } port_ddr_trim_delay_t;
196 
205 typedef enum
206 {
207  DDR_NO_CRPOINT = 0x0U,
208  DDR_MINUS_CRPOINT = 0x1U,
209  DDR_PLUS_CRPOINT = 0x2U,
210  DDR_DOUBLE_CRPOINT = 0x3U
211 } port_ddr_crpoint_t;
212 
221 typedef enum
222 {
223  DDR_NO_TRIM = 0x0U,
224  DDR_LEFT_TRIM = 0x1U,
225  DDR_RIGHT_TRIM = 0x2U
226 } port_ddr_trim_t;
227 
232 typedef enum
233 {
234  PORT_DDR_INPUT_CMOS = 0U,
235  PORT_DDR_INPUT_DIFFERENTIAL = 1U
236 } port_ddr_input_t;
237 
242 typedef enum
243 {
244  PORT_STR0_ON_DIE_TERMINATION = 0U,
245  PORT_STR1_ON_DIE_TERMINATION = 1U,
246  PORT_STR2_ON_DIE_TERMINATION = 2U,
247  PORT_STR3_ON_DIE_TERMINATION = 3U,
248  PORT_STR4_ON_DIE_TERMINATION = 4U,
249  PORT_STR5_ON_DIE_TERMINATION = 5U,
250  PORT_STR6_ON_DIE_TERMINATION = 6U,
251  PORT_STR7_ON_DIE_TERMINATION = 7U
252 } port_on_die_termination_t;
253 
260 typedef struct
261 {
262  port_ddr_type_t ddrSelection;
263  port_ddr_trim_delay_t trimmingDelay;
264  port_ddr_crpoint_t crosspointAdjustment;
265  port_ddr_trim_t trimmingAdjustment;
266 } pin_ddr_config_t;
267 
268 #endif /* FEATURE_SIUL2_HAS_DDR_PAD */
269 
274 typedef enum
275 {
276  PORT_MUX_AS_GPIO = 0U,
277  PORT_MUX_ALT1 = 1U,
278  PORT_MUX_ALT2 = 2U,
279  PORT_MUX_ALT3 = 3U,
280  PORT_MUX_ALT4 = 4U,
281  PORT_MUX_ALT5 = 5U,
282  PORT_MUX_ALT6 = 6U,
283  PORT_MUX_ALT7 = 7U,
284  PORT_MUX_ALT8 = 8U,
285  PORT_MUX_ALT9 = 9U,
286  PORT_MUX_ALT10 = 10U,
287  PORT_MUX_ALT11 = 11U,
288  PORT_MUX_ALT12 = 12U,
289  PORT_MUX_ALT13 = 13U,
290  PORT_MUX_ALT14 = 14U,
291  PORT_MUX_ALT15 = 15U
292 } port_mux_t;
293 
298 typedef enum
299 {
300  SIUL2_INT_DISABLE = 0x0U,
301  SIUL2_INT_RISING_EDGE = 0x1U,
302  SIUL2_INT_FALLING_EDGE = 0x2U,
303  SIUL2_INT_EITHER_EDGE = 0x3U
304 } suil2_interrupt_type_t;
305 
306 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
307 
311 typedef enum
312 {
313  SIUL2_INT_USING_INTERUPT = 0x0U,
314  SIUL2_INT_USING_DMA = 0x1U
315 } suil2_interrupt_dma_select_t;
316 #endif /* FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA */
317 
322 typedef struct
323 {
324  uint8_t eirq_pinIdx;
325  suil2_interrupt_type_t intEdgeSel;
326 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
327  suil2_interrupt_dma_select_t intExeSel;
328 #endif
329 } suil2_interupt_config_t;
330 
335 typedef enum
336 {
337  PORT_OUTPUT_BUFFER_DISABLED = 0U,
338  PORT_OUTPUT_BUFFER_ENABLED = 1U
339 } port_output_buffer_t;
340 
345 typedef enum
346 {
347  PORT_INPUT_BUFFER_DISABLED = 0U,
348  PORT_INPUT_BUFFER_ENABLED = 1U
349 } port_input_buffer_t;
350 
351 #if FEATURE_SIUL2_HAS_HYSTERESIS
352 
356 typedef enum
357 {
358  PORT_HYSTERESYS_CMOS = 0U,
359  PORT_HYSTERESYS_SCHMITT = 1U,
360  PORT_HYSTERESYS_DISABLED = 0U,
361  PORT_HYSTERESYS_ENABLED = 1U
362 } port_hysteresis_t;
363 #endif /* FEATURE_SIUL2_HAS_HYSTERESIS */
364 
365 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
366 
370 typedef enum
371 {
372  PORT_INVERT_OUTPUT_DISABLED = 0U,
373  PORT_INVERT_OUTPUT_ENABLED = 1U
374 } port_invert_output_t;
375 #endif /* FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT */
376 
377 #if FEATURE_SIUL2_HAS_PULL_KEEPER
378 
382 typedef enum
383 {
384  PORT_PULL_KEEP_DISABLED = 0U,
385  PORT_PULL_KEEP_ENABLED = 1U
386 } port_pull_keep_t;
387 
392 typedef enum
393 {
394  PORT_KEEPER_ENABLED = 0U,
395  PORT_PULL_ENABLED = 1U
396 } port_pull_keeper_select_t;
397 
402 typedef enum
403 {
404  PORT_PULL_DOWN_ENABLED = 0U,
405  PORT_PULL_UP_MEDIUM = 1U,
406  PORT_PULL_UP_HIGH = 2U,
407  PORT_PULL_UP_LOW = 3U
408 } port_pull_up_down_t;
409 
410 #endif /* FEATURE_SIUL2_HAS_PULL_KEEPER */
411 
412 #if FEATURE_SIUL2_HAS_ANALOG_PAD
413 
417 typedef enum
418 {
419  PORT_ANALOG_PAD_CONTROL_DISABLED = 0U,
420  PORT_ANALOG_PAD_CONTROL_ENABLED = 1U
421 } port_analog_pad_t;
422 #endif /* FEATURE_SIUL2_HAS_ANALOG_PAD */
423 
428 typedef enum
429 {
430 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 1U)
431  PORT_INPUT_MUX_ALT0 = 0U,
432  PORT_INPUT_MUX_ALT1 = 1U,
433 #endif
434 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 2U)
435  PORT_INPUT_MUX_ALT2 = 2U,
436  PORT_INPUT_MUX_ALT3 = 3U,
437 #endif
438 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 3U)
439  PORT_INPUT_MUX_ALT4 = 4U,
440  PORT_INPUT_MUX_ALT5 = 5U,
441  PORT_INPUT_MUX_ALT6 = 6U,
442  PORT_INPUT_MUX_ALT7 = 7U,
443 #endif
444 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 4U)
445  PORT_INPUT_MUX_ALT8 = 8U,
446  PORT_INPUT_MUX_ALT9 = 9U,
447  PORT_INPUT_MUX_ALT10 = 10U,
448  PORT_INPUT_MUX_ALT11 = 11U,
449  PORT_INPUT_MUX_ALT12 = 12U,
450  PORT_INPUT_MUX_ALT13 = 13U,
451  PORT_INPUT_MUX_ALT14 = 14U,
452  PORT_INPUT_MUX_ALT15 = 15U,
453 #endif
454  PORT_INPUT_MUX_NO_INIT
455 } port_input_mux_t;
456 
461 typedef enum
462 {
463  PORT_SAFE_MODE_DISABLED = 0U,
465  PORT_SAFE_MODE_ENABLED = 1U
466 } port_safe_mode_t;
467 
468 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
469 
473 typedef enum
474 {
475  HALF_STRENGTH_WITH_SLEWRATE_CONTROL = 0u,
476  FULL_STRENGTH_WITH_SLEWRATE_CONTROL = 1u,
477  HALF_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 2u,
478  FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 3u
479 } port_slew_rate_control_t;
480 #endif /* FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL */
481 
482 #if FEATURE_PINS_HAS_SLEW_RATE
483 
487 typedef enum
488 {
489  PORT_LOW_SLEW_RATE = 0U,
490  PORT_MEDIUM_SLEW_RATE = 1U,
491  PORT_MEDIUM_SLEW_RATE2 = 2U,
492  PORT_HIGH_SLEW_RATE = 3U
493 } port_slew_rate_t;
494 #endif
495 
496 #endif /* FEATURE_PINS_DRIVER_USING_SIUL2 */
497 
504 typedef struct
505 {
506 #ifdef FEATURE_PINS_DRIVER_USING_PORT
507  PORT_Type * base;
508 #elif defined FEATURE_PINS_DRIVER_USING_SIUL2
509  SIUL2_Type * base;
510 #endif
511  uint32_t pinPortIdx;
512 #if FEATURE_PINS_HAS_PULL_SELECTION
513  port_pull_config_t pullConfig;
514 #endif
515 #if FEATURE_PINS_HAS_SLEW_RATE
516  port_slew_rate_t rateSelect;
517 #endif
518 #if FEATURE_PORT_HAS_PASSIVE_FILTER
519  bool passiveFilter;
520 #endif
521 #if FEATURE_PINS_HAS_OPEN_DRAIN
522  port_open_drain_t openDrain;
523 #endif
524 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
525  port_drive_strength_t driveSelect;
526 #endif
527  port_mux_t mux;
528 #if FEATURE_PORT_HAS_PIN_CONTROL_LOCK
529  bool pinLock;
530 #endif
531 #ifdef FEATURE_PINS_DRIVER_USING_PORT
532  port_interrupt_config_t intConfig;
533  bool clearIntFlag;
534 #endif
537 #ifdef FEATURE_PINS_DRIVER_USING_SIUL2
538  port_input_mux_t inputMux[FEATURE_SIUL2_INPUT_MUX_WIDTH];
539  uint32_t inputMuxReg[FEATURE_SIUL2_INPUT_MUX_WIDTH];
540  port_output_buffer_t outputBuffer;
541  port_input_buffer_t inputBuffer;
542  suil2_interupt_config_t intConfig;
543 #if FEATURE_SIUL2_HAS_SAFE_MODE_CONTROL
544  port_safe_mode_t safeMode;
545 #endif
546 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
547  port_slew_rate_control_t slewRateCtrlSel;
548 #endif
549 #if FEATURE_SIUL2_HAS_HYSTERESIS
550  port_hysteresis_t hysteresisSelect;
551 #endif /* FEATURE_SIUL2_HAS_HYSTERESIS */
552 #if FEATURE_SIUL2_HAS_DDR_PAD
553  pin_ddr_config_t ddrConfiguration;
554  port_ddr_input_t inputMode;
555  port_on_die_termination_t odtSelect;
556 #endif /* FEATURE_SIUL2_HAS_DDR_PAD */
557 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
558  port_invert_output_t invertOutput;
559 #endif
560 #if FEATURE_SIUL2_HAS_PULL_KEEPER
561  port_pull_keep_t pullKeepEnable;
562  port_pull_keeper_select_t pullKeepSelect;
563  port_pull_up_down_t pullSelect;
564 #endif
565 #if FEATURE_SIUL2_HAS_ANALOG_PAD
566  port_analog_pad_t analogPadCtrlSel;
567 #endif
568 #endif /* FEATURE_PINS_DRIVER_USING_SIUL2 */
570 
571 /*******************************************************************************
572  * API
573  ******************************************************************************/
579 #if defined(__cplusplus)
580 extern "C" {
581 #endif
582 
593 status_t PINS_DRV_Init(uint32_t pinCount,
594  const pin_settings_config_t config[]);
595 
596 #ifdef FEATURE_PINS_DRIVER_USING_PORT
597 #if FEATURE_PINS_HAS_PULL_SELECTION
598 
607 void PINS_DRV_SetPullSel(PORT_Type * const base,
608  uint32_t pin,
609  port_pull_config_t pullConfig);
610 
611 #endif /* FEATURE_PINS_HAS_PULL_SELECTION */
612 
622 void PINS_DRV_SetMuxModeSel(PORT_Type * const base,
623  uint32_t pin,
624  port_mux_t mux);
625 
635 void PINS_DRV_SetPinIntSel(PORT_Type * const base,
636  uint32_t pin,
637  port_interrupt_config_t intConfig);
638 
648 port_interrupt_config_t PINS_DRV_GetPinIntSel(const PORT_Type * const base,
649  uint32_t pin);
650 
659 void PINS_DRV_ClearPinIntFlagCmd(PORT_Type * const base,
660  uint32_t pin);
661 
670 uint32_t PINS_DRV_GetPortIntFlag(const PORT_Type * const base);
671 
679 void PINS_DRV_ClearPortIntFlagCmd(PORT_Type * const base);
680 
694 pins_channel_type_t PINS_DRV_GetPinsDirection(const GPIO_Type * const base);
695 
709 void PINS_DRV_SetPinDirection(GPIO_Type * const base,
710  pins_channel_type_t pin,
711  pins_level_type_t direction);
712 
727 void PINS_DRV_SetPinsDirection(GPIO_Type * const base,
728  pins_channel_type_t pins);
729 
744 void PINS_DRV_SetPortInputDisable(GPIO_Type * const base,
745  pins_channel_type_t pins);
746 
760 pins_channel_type_t PINS_DRV_GetPortInputDisable(const GPIO_Type * const base);
761 
762 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
763 
772 void PINS_DRV_SetPinIntSel(PORT_Type * const base,
773  uint32_t pin,
774  suil2_interupt_config_t intConfig);
775 
785 suil2_interupt_config_t PINS_DRV_GetPinIntSel(const PORT_Type * const base,
786  uint32_t pin);
787 
788 #endif /* FEATURE_PINS_DRIVER_USING_PORT */
789 
802 void PINS_DRV_WritePin(GPIO_Type * const base,
803  pins_channel_type_t pin,
804  pins_level_type_t value);
805 
817 void PINS_DRV_WritePins(GPIO_Type * const base,
818  pins_channel_type_t pins);
819 
832 pins_channel_type_t PINS_DRV_GetPinsOutput(const GPIO_Type * const base);
833 
847 void PINS_DRV_SetPins(GPIO_Type * const base,
848  pins_channel_type_t pins);
849 
863 void PINS_DRV_ClearPins(GPIO_Type * const base,
864  pins_channel_type_t pins);
865 
878 void PINS_DRV_TogglePins(GPIO_Type * const base,
879  pins_channel_type_t pins);
880 
893 pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type * const base);
894 
897 #if defined(__cplusplus)
898 }
899 #endif
900 
903 #endif /* PINS_DRIVER_H */
904 /*******************************************************************************
905  * EOF
906  ******************************************************************************/
rtc_interrupt_config_t * intConfig
Definition: rtc_driver.c:78
status_t PINS_DRV_Init(uint32_t pinCount, const pin_settings_config_t config[])
Initializes the pins with the given configuration structure.
Definition: pins_driver.c:53
pins_channel_type_t PINS_DRV_GetPinsOutput(const GPIO_Type *const base)
Get the current output from a port.
Definition: pins_driver.c:283
port_mux_t mux
Pin (C55: Out) mux selection.
Definition: pins_driver.h:527
void PINS_DRV_WritePin(GPIO_Type *const base, pins_channel_type_t pin, pins_level_type_t value)
Write a pin of a port with a given value.
Definition: pins_driver.c:254
void PINS_DRV_TogglePins(GPIO_Type *const base, pins_channel_type_t pins)
Toggle pins value.
Definition: pins_driver.c:326
GPIO_Type * gpioBase
Definition: pins_driver.h:535
void PINS_DRV_WritePins(GPIO_Type *const base, pins_channel_type_t pins)
Write all pins of a port.
Definition: pins_driver.c:269
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
port_data_direction_t
Configures the port data direction Implements : port_data_direction_t_Class.
Definition: pins_driver.h:62
Defines the converter configuration.
Definition: pins_driver.h:504
void PINS_DRV_SetPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins with 'Set' value.
Definition: pins_driver.c:297
pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type *const base)
Read input pins.
Definition: pins_driver.c:340
port_data_direction_t direction
Definition: pins_driver.h:536
uint8_t pins_level_type_t
Type of a port levels representation. Implements : pins_level_type_t_Class.
Definition: pins_driver.h:56
void PINS_DRV_ClearPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins to 'Clear' value.
Definition: pins_driver.c:312