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S32 SDK
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SCG system PLL configuration. Implements scg_spll_config_t_Class. More...
#include <clock_S32K1xx.h>
Data Fields | |
scg_spll_monitor_mode_t | monitorMode |
uint8_t | prediv |
uint8_t | mult |
uint8_t | src |
scg_async_clock_div_t | div1 |
scg_async_clock_div_t | div2 |
bool | enableInStop |
bool | locked |
bool | initialize |
SCG system PLL configuration. Implements scg_spll_config_t_Class.
Definition at line 443 of file clock_S32K1xx.h.
Divider for platform asynchronous clock.
Definition at line 451 of file clock_S32K1xx.h.
Divider for bus asynchronous clock.
Definition at line 452 of file clock_S32K1xx.h.
bool enableInStop |
System PLL clock is enable or not in stop mode.
Definition at line 454 of file clock_S32K1xx.h.
bool initialize |
Initialize or not the System PLL module.
Definition at line 457 of file clock_S32K1xx.h.
bool locked |
System PLL Control Register can be written.
Definition at line 456 of file clock_S32K1xx.h.
scg_spll_monitor_mode_t monitorMode |
Clock monitor mode selected.
Definition at line 445 of file clock_S32K1xx.h.
uint8_t mult |
System PLL multiplier.
Definition at line 448 of file clock_S32K1xx.h.
uint8_t prediv |
PLL reference clock divider.
Definition at line 447 of file clock_S32K1xx.h.
uint8_t src |
System PLL source.
Definition at line 449 of file clock_S32K1xx.h.