S32 SDK
ftm_common.c
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
63 #include "ftm_common.h"
64 
65 /*******************************************************************************
66  * Variables
67  ******************************************************************************/
68 
71 
77 
78 #ifdef ERRATA_E10856
79 bool faultDetection = false;
80 #endif
81 
84 
90 #if (FTM_INSTANCE_COUNT > 4U)
91  {SIM_FTM4_CLOCKSEL, FTM4_CLK},
92 #endif
93 #if (FTM_INSTANCE_COUNT > 5U)
94  {SIM_FTM5_CLOCKSEL, FTM5_CLK},
95 #endif
96 #if (FTM_INSTANCE_COUNT > 6U)
97  {SIM_FTM6_CLOCKSEL, FTM6_CLK},
98 #endif
99 #if (FTM_INSTANCE_COUNT > 7U)
100  {SIM_FTM7_CLOCKSEL, FTM7_CLK},
101 #endif
102  };
103 
104 /*FUNCTION**********************************************************************
105  *
106  * Function Name : FTM_DRV_Init
107  * Description : Initializes the FTM driver and get the clock frequency value
108  * which select one of three possible clock sources for the FTM counter.
109  *
110  * Implements : FTM_DRV_Init_Activity
111  *END**************************************************************************/
112 status_t FTM_DRV_Init(uint32_t instance,
113  const ftm_user_config_t * info,
114  ftm_state_t * state)
115 {
116  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
117  DEV_ASSERT(info != NULL);
118  DEV_ASSERT(state != NULL);
119  FTM_Type * ftmBase = g_ftmBase[instance];
120  status_t status = STATUS_SUCCESS;
121 
122  /* Check if this instance is already initialized */
123  if (ftmStatePtr[instance] != NULL)
124  {
125  status = STATUS_ERROR;
126  }
127  else
128  {
129  /* Configure state structure. */
130  state->ftmClockSource = info->ftmClockSource;
132  state->ftmPeriod = 0U;
133  ftmStatePtr[instance] = state;
134  /* The reset operation doesn't care about write protection. FTM_DRV_Reset will
135  * disable this protection.*/
136  FTM_DRV_Reset(ftmBase);
137  FTM_DRV_InitModule(ftmBase, info->ftmPrescaler);
138  /* Get clock name used to configure the FlexTimer module */
140  /* Check the functional clock is selected for FTM */
141  DEV_ASSERT(state->ftmSourceClockFrequency > 0U);
142  }
143 
144  if (STATUS_SUCCESS == status)
145  {
146  /* Check if the mode operation in PWM mode */
148  {
149  /* Configure sync for between registers and buffers */
150  status = FTM_DRV_SetSync(instance, &(info->syncMethod));
151  }
152 
153  /* Enable the generation of initialization trigger on chip module */
154  FTM_DRV_SetInitTriggerCmd(ftmBase, info->enableInitializationTrigger);
155  FTM_DRV_SetBdmMode(ftmBase, info->BDMMode);
156 
157  /* Check if enable interrupt in counter mode */
158  if (info->isTofIsrEnabled)
159  {
160  FTM_DRV_SetTimerOverflowInt(ftmBase, true);
162  }
163  else
164  {
165  FTM_DRV_SetTimerOverflowInt(ftmBase, false);
167  }
168  }
169 
170  return status;
171 }
172 
173 /*FUNCTION**********************************************************************
174  *
175  * Function Name : FTM_DRV_Deinit
176  * Description : Shuts down the FTM driver.
177  * First, FTM_DRV_Init must be called. Then this function will disables the FTM module.
178  *
179  * Implements : FTM_DRV_Deinit_Activity
180  *END**************************************************************************/
181 status_t FTM_DRV_Deinit(uint32_t instance)
182 {
183  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
184  FTM_Type * ftmBase = g_ftmBase[instance];
185 
186  /* Reset all FTM register */
187  FTM_DRV_Reset(ftmBase);
188  ftmStatePtr[instance] = NULL;
189 
190  return STATUS_SUCCESS;
191 }
192 
193 /*FUNCTION**********************************************************************
194  *
195  * Function Name : FTM_DRV_MaskOutputChannels
196  * Description : This function will mask the output of the channels and at match
197  * events will be ignored by the masked channels.
198  *
199  * Implements : FTM_DRV_MaskOutputChannels_Activity
200  *END**************************************************************************/
202  uint32_t channelsMask,
203  bool softwareTrigger)
204 {
205  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
206  FTM_Type * ftmBase = g_ftmBase[instance];
207 
208  FTM_DRV_SetOutmaskReg(ftmBase, channelsMask);
209  if (softwareTrigger)
210  {
211  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
212  }
213 
214  return STATUS_SUCCESS;
215 }
216 
217 /*FUNCTION**********************************************************************
218  *
219  * Function Name : FTM_DRV_SetInitialCounterValue
220  * Description : This function configure the initial counter value. The counter
221  * will get this value after an overflow event.
222  *
223  * Implements : FTM_DRV_SetInitialCounterValue_Activity
224  *END**************************************************************************/
226  uint16_t counterValue,
227  bool softwareTrigger)
228 {
229  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
230  FTM_Type * ftmBase = g_ftmBase[instance];
231 
232  FTM_DRV_SetCounterInitVal(ftmBase, counterValue);
233  if (softwareTrigger)
234  {
235  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
236  }
237 
238  return STATUS_SUCCESS;
239 }
240 
241 /*FUNCTION**********************************************************************
242  *
243  * Function Name : FTM_DRV_SetHalfCycleReloadPoint
244  * Description : This function configure the value of the counter which will
245  * generates an reload point.
246  *
247  * Implements : FTM_DRV_SetHalfCycleReloadPoint_Activity
248  *END**************************************************************************/
250  uint16_t reloadPoint,
251  bool softwareTrigger)
252 {
253  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
254  FTM_Type * ftmBase = g_ftmBase[instance];
255 
256  FTM_DRV_SetHalfCycleValue(ftmBase, reloadPoint);
257  if (softwareTrigger)
258  {
259  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
260  }
261 
262  return STATUS_SUCCESS;
263 }
264 
265 /*FUNCTION**********************************************************************
266  *
267  * Function Name : FTM_DRV_SetSoftwareOutputChannelValue
268  * Description : This function will force the output value of a channel to a specific value.
269  * Before using this function it's mandatory to mask the match events using
270  * FTM_DRV_MaskOutputChannels and to enable software output control using
271  * FTM_DRV_SetSoftwareOutputChannelControl.
272  *
273  * Implements : FTM_DRV_SetSoftOutChnValue_Activity
274  *END**************************************************************************/
276  uint8_t channelsValues,
277  bool softwareTrigger)
278 {
279  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
280  FTM_Type * ftmBase = g_ftmBase[instance];
281  FTM_DRV_SetAllChnSoftwareCtrlVal(ftmBase, channelsValues);
282  if (softwareTrigger)
283  {
284  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
285  }
286 
287  return STATUS_SUCCESS;
288 }
289 
290 /*FUNCTION**********************************************************************
291  *
292  * Function Name : FTM_DRV_SetSoftwareOutputChannelControl
293  * Description : This function will configure which output channel can be
294  * software controlled.
295  *
296  * Implements : FTM_DRV_SetSoftwareOutputChannelControl_Activity
297  *END**************************************************************************/
299  uint8_t channelsMask,
300  bool softwareTrigger)
301 {
302  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
303  FTM_Type * ftmBase = g_ftmBase[instance];
304  FTM_DRV_SetAllChnSoftwareCtrlCmd(ftmBase, channelsMask);
305  if (softwareTrigger)
306  {
307  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
308  }
309 
310  return STATUS_SUCCESS;
311 }
312 
313 /*FUNCTION**********************************************************************
314  *
315  * Function Name : FTM_DRV_SetInvertingControl
316  * Description : This function will configure if the second channel of a pair
317  * will be inverted or not.
318  *
319  * Implements : FTM_DRV_SetInvertingControl_Activity
320  *END**************************************************************************/
322  uint8_t channelsPairMask,
323  bool softwareTrigger)
324 {
325  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
326  FTM_Type * ftmBase = g_ftmBase[instance];
327 
328  FTM_DRV_SetInvctrlReg(ftmBase, channelsPairMask);
329  if (softwareTrigger)
330  {
331  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
332  }
333 
334  return STATUS_SUCCESS;
335 }
336 
337 /*FUNCTION**********************************************************************
338  *
339  * Function Name : FTM_DRV_SetModuloCounterValue
340  * Description : This function configure the maximum counter value.
341  *
342  * Implements : FTM_DRV_SetModuloCounterValue_Activity
343  *END**************************************************************************/
345  uint16_t counterValue,
346  bool softwareTrigger)
347 {
348  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
349  FTM_Type * ftmBase = g_ftmBase[instance];
350 
351  FTM_DRV_SetMod(ftmBase, counterValue);
352  if (softwareTrigger)
353  {
354  FTM_DRV_SetSoftwareTriggerCmd(ftmBase, true);
355  }
356 
357  return STATUS_SUCCESS;
358 }
359 
360 /*FUNCTION**********************************************************************
361  *
362  * Function Name : FTM_DRV_SetSync
363  * Description : This function configure the synchronization for PWM register
364  * (CnV, MOD, CINT, HCR, OUTMASK).If this function is used whit wrong parameters
365  * it's possible to generate wrong waveform. Registers synchronization need to
366  * be configured for PWM and output compare mode.
367  *
368  * Implements : FTM_DRV_SetSync_Activity
369  *END**************************************************************************/
370 status_t FTM_DRV_SetSync(uint32_t instance,
371  const ftm_pwm_sync_t * param)
372 {
373  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
374  DEV_ASSERT(param != NULL);
375  FTM_Type * ftmBase = g_ftmBase[instance];
376  status_t retStatus = STATUS_SUCCESS;
377  bool hardwareSync = param->hardwareSync0 || param->hardwareSync1 || param->hardwareSync2;
378 
379  /* Software and hardware triggers are not allowed in the same time */
380  if ((param->softwareSync && hardwareSync) || (true != (param->softwareSync || hardwareSync)))
381  {
382  retStatus = STATUS_ERROR;
383  }
384  else if (param->softwareSync)
385  {
386  /* Configure sync for OUTMASK register */
387  FTM_DRV_SetOutmaskSoftwareSyncModeCmd(ftmBase, true);
388  /* Configure sync for INVCTRL register */
389  FTM_DRV_SetInvctrlSoftwareSyncModeCmd(ftmBase, true);
390  /* Configure sync for SWOCTRL register */
391  FTM_DRV_SetSwoctrlSoftwareSyncModeCmd(ftmBase, true);
392  /* Configure sync for MOD, HCR, CNTIN, and CnV registers */
393  FTM_DRV_SetModCntinCvSoftwareSyncModeCmd(ftmBase, true);
394  /* Configure synchronization method (waiting next loading point or now) */
395  FTM_DRV_SetCounterSoftwareSyncModeCmd(ftmBase, param->syncPoint);
396  }
397  else
398  {
399  /* Configure sync for OUTMASK register */
400  FTM_DRV_SetOutmaskHardwareSyncModeCmd(ftmBase, true);
401  /* Configure sync for INVCTRL register */
402  FTM_DRV_SetInvctrlHardwareSyncModeCmd(ftmBase, true);
403  /* Configure sync for SWOCTRL register */
404  FTM_DRV_SetSwoctrlHardwareSyncModeCmd(ftmBase, true);
405  /* Configure sync for MOD, HCR, CNTIN, and CnV registers */
406  FTM_DRV_SetModCntinCvHardwareSyncModeCmd(ftmBase, true);
407  /* Configure synchronization method (waiting next loading point or now) */
408  FTM_DRV_SetCounterHardwareSyncModeCmd(ftmBase, (bool)param->syncPoint);
409  }
410 
411  if (STATUS_SUCCESS == retStatus)
412  {
413  /* Enhanced PWM sync is used */
414  FTM_DRV_SetPwmSyncModeCmd(ftmBase, true);
415  /* Configure trigger source for sync */
416  FTM_DRV_SetHardwareSyncTriggerSrc(ftmBase, 0U, param->hardwareSync0);
417  FTM_DRV_SetHardwareSyncTriggerSrc(ftmBase, 1U, param->hardwareSync1);
418  FTM_DRV_SetHardwareSyncTriggerSrc(ftmBase, 2U, param->hardwareSync2);
419  /* Configure loading points */
420  FTM_DRV_SetMaxLoadingCmd(ftmBase, param->maxLoadingPoint);
421  FTM_DRV_SetMinLoadingCmd(ftmBase, param->minLoadingPoint);
422  /* Configure sync for OUTMASK register */
423  FTM_DRV_SetOutmaskPwmSyncModeCmd(ftmBase, (bool)param->maskRegSync);
424  /* Configure sync for INVCTRL register */
425  FTM_DRV_SetInvctrlPwmSyncModeCmd(ftmBase, param->inverterSync);
426  /* Configure sync for SWOCTRL register */
427  FTM_DRV_SetSwoctrlPwmSyncModeCmd(ftmBase, param->outRegSync);
428  /* Configure sync for MOD, HCR, CNTIN, and CnV registers */
429  FTM_DRV_SetCntinPwmSyncModeCmd(ftmBase, param->initCounterSync);
430  /* Configure if FTM clears TRIGj (j=0,1,2) when the hardware trigger j is detected. */
431  FTM_DRV_SetHwTriggerSyncModeCmd(ftmBase, param->autoClearTrigger);
432  }
433 
434  return retStatus;
435 }
436 
437 /*FUNCTION**********************************************************************
438  *
439  * Function Name : FTM_DRV_GetFrequency
440  * Description : Retrieves the frequency of the clock source feeding the FTM counter.
441  * Function will return a 0 if no clock source is selected and the FTM counter is disabled.
442  * The returned value is clock sources for the FTM counter.
443  *
444  * Implements : FTM_DRV_GetFrequency_Activity
445  *END**************************************************************************/
446 uint32_t FTM_DRV_GetFrequency(uint32_t instance)
447 {
448  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
449  FTM_Type const * ftmBase = g_ftmBase[instance];
450  status_t returnCode = STATUS_SUCCESS;
451  clock_names_t ftmClkName;
452  uint8_t clkPs;
453  uint32_t frequency = 0U;
454  const ftm_state_t * state = ftmStatePtr[instance];
455  clkPs = (uint8_t)(1U << FTM_DRV_GetClockPs(ftmBase));
456 
457  switch (state->ftmClockSource)
458  {
459  case FTM_CLOCK_SOURCE_EXTERNALCLK:
460  returnCode = CLOCK_SYS_GetFreq(g_ftmExtClockSel[instance][1], &frequency);
461  if (0U == frequency)
462  {
463  ftmClkName = g_ftmExtClockSel[instance][0];
464  }
465  else
466  {
467  ftmClkName = g_ftmExtClockSel[instance][1];
468  }
469 
470  /* Get the clock frequency value */
471  returnCode = CLOCK_SYS_GetFreq(ftmClkName, &frequency);
472  break;
473  case FTM_CLOCK_SOURCE_FIXEDCLK:
474  /* Get the clock frequency value */
475  returnCode = CLOCK_SYS_GetFreq(SIM_RTCCLK_CLK, &frequency);
476  break;
477  case FTM_CLOCK_SOURCE_SYSTEMCLK:
478  /* Get the clock frequency value */
479  returnCode = CLOCK_SYS_GetFreq(CORE_CLK, &frequency);
480  break;
481  default:
482  /* Nothing to do */
483  break;
484  }
485 
486  /* Checks the functional clock of FTM module */
487  (void)returnCode;
488  DEV_ASSERT(returnCode == STATUS_SUCCESS);
489 
490  return (uint32_t)(frequency / clkPs);
491 }
492 
493 /*FUNCTION**********************************************************************
494  *
495  * Function Name : FTM_DRV_ConvertFreqToPeriodTicks
496  * Description : This function converts the input parameters representing
497  * frequency in Hz to a period value in ticks needed by the hardware timer.
498  *
499  * Implements : FTM_DRV_ConvertFreqToPeriodTicks_Activity
500  *END**************************************************************************/
501 uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance,
502  uint32_t freqencyHz)
503 {
504  DEV_ASSERT(instance < FTM_INSTANCE_COUNT);
505  DEV_ASSERT(freqencyHz != 0U);
506  uint32_t uFTMhz;
507  const ftm_state_t * state = ftmStatePtr[instance];
508  uFTMhz = state->ftmSourceClockFrequency;
509 
510  return (uint16_t)(uFTMhz / freqencyHz);
511 }
512 
513 /*******************************************************************************
514 * EOF
515 ******************************************************************************/
const IRQn_Type g_ftmOverflowIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_common.c:75
ftm_reg_update_t initCounterSync
Definition: ftm_common.h:154
#define FTM_Reload_IRQS
Definition: S32K142.h:3980
status_t FTM_DRV_SetSoftwareOutputChannelControl(uint32_t instance, uint8_t channelsMask, bool softwareTrigger)
This function will configure which output channel can be software controlled.
Definition: ftm_common.c:298
ftm_pwm_sync_t syncMethod
Definition: ftm_common.h:167
FlexTimer state structure of the driver.
Definition: ftm_common.h:121
status_t FTM_DRV_SetSync(uint32_t instance, const ftm_pwm_sync_t *param)
This function configures sync mechanism for some FTM registers (MOD, CNINT, HCR, CnV, OUTMASK, INVCTRL, SWOCTRL).
Definition: ftm_common.c:370
#define FTM_IRQS
Definition: S32K142.h:3974
ftm_bdm_mode_t BDMMode
Definition: ftm_common.h:173
bool hardwareSync2
Definition: ftm_common.h:145
Configuration structure that the user needs to set.
Definition: ftm_common.h:165
uint16_t ftmPeriod
Definition: ftm_common.h:125
FTM_Type *const g_ftmBase[FTM_INSTANCE_COUNT]
Table of base addresses for FTM instances.
Definition: ftm_common.c:70
static uint8_t FTM_DRV_GetClockPs(const FTM_Type *ftmBase)
Reads the FTM clock divider.
Definition: ftm_common.h:249
FlexTimer Registers sync parameters Please don't use software and hardware trigger simultaneously Imp...
Definition: ftm_common.h:137
ftm_state_t * ftmStatePtr[FTM_INSTANCE_COUNT]
Pointer to runtime state structure.
Definition: ftm_common.c:83
status_t FTM_DRV_SetInitialCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the initial counter value. The counter will get this value after an overflow ...
Definition: ftm_common.c:225
bool hardwareSync1
Definition: ftm_common.h:143
status_t FTM_DRV_SetHalfCycleReloadPoint(uint32_t instance, uint16_t reloadPoint, bool softwareTrigger)
This function configure the value of the counter which will generates an reload point.
Definition: ftm_common.c:249
#define FEATURE_FTM_CHANNEL_COUNT
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
#define DEV_ASSERT(x)
Definition: devassert.h:77
uint32_t FTM_DRV_GetFrequency(uint32_t instance)
Retrieves the frequency of the clock source feeding the FTM counter.
Definition: ftm_common.c:446
clock_names_t
Clock names.
uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance, uint32_t freqencyHz)
This function is used to covert the given frequency to period in ticks.
Definition: ftm_common.c:501
const IRQn_Type g_ftmReloadIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_common.c:76
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
ftm_clock_source_t ftmClockSource
Definition: ftm_common.h:123
bool hardwareSync0
Definition: ftm_common.h:141
#define FTM_Fault_IRQS
Definition: S32K142.h:3978
ftm_pwm_sync_mode_t syncPoint
Definition: ftm_common.h:156
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
bool maxLoadingPoint
Definition: ftm_common.h:147
#define FTM_INSTANCE_COUNT
Definition: S32K142.h:3939
status_t FTM_DRV_SetInvertingControl(uint32_t instance, uint8_t channelsPairMask, bool softwareTrigger)
This function will configure if the second channel of a pair will be inverted or not.
Definition: ftm_common.c:321
bool enableInitializationTrigger
Definition: ftm_common.h:176
#define FTM_Overflow_IRQS
Definition: S32K142.h:3979
ftm_reg_update_t inverterSync
Definition: ftm_common.h:151
const IRQn_Type g_ftmFaultIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_common.c:74
ftm_config_mode_t ftmMode
Definition: ftm_common.h:124
status_t FTM_DRV_SetModuloCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the maximum counter value.
Definition: ftm_common.c:344
ftm_config_mode_t ftmMode
Definition: ftm_common.h:169
status_t FTM_DRV_Deinit(uint32_t instance)
Shuts down the FTM driver.
Definition: ftm_common.c:181
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
status_t FTM_DRV_MaskOutputChannels(uint32_t instance, uint32_t channelsMask, bool softwareTrigger)
This function will mask the output of the channels and at match events will be ignored by the masked ...
Definition: ftm_common.c:201
ftm_reg_update_t maskRegSync
Definition: ftm_common.h:153
static const clock_names_t g_ftmExtClockSel[FTM_INSTANCE_COUNT][2]
Select external clock pin or clock source for peripheral.
Definition: ftm_common.c:86
bool minLoadingPoint
Definition: ftm_common.h:149
bool autoClearTrigger
Definition: ftm_common.h:155
#define FTM_BASE_PTRS
Definition: S32K142.h:3962
status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t *info, ftm_state_t *state)
Initializes the FTM driver.
Definition: ftm_common.c:112
status_t FTM_DRV_SetSoftOutChnValue(uint32_t instance, uint8_t channelsValues, bool softwareTrigger)
This function will force the output value of a channel to a specific value. Before using this functio...
Definition: ftm_common.c:275
ftm_clock_source_t ftmClockSource
Definition: ftm_common.h:172
uint32_t ftmSourceClockFrequency
Definition: ftm_common.h:126
const IRQn_Type g_ftmIrqId[FTM_INSTANCE_COUNT][FEATURE_FTM_CHANNEL_COUNT]
Interrupt vectors for the FTM peripheral.
Definition: ftm_common.c:73
ftm_reg_update_t outRegSync
Definition: ftm_common.h:152
ftm_clock_ps_t ftmPrescaler
Definition: ftm_common.h:170
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K142.h:192