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S32 SDK
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#define SIM_ADCOPT_ADC0PRETRGSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC0PRETRGSEL_MASK) |
#define SIM_ADCOPT_ADC0SWPRETRG | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0SWPRETRG_SHIFT))&SIM_ADCOPT_ADC0SWPRETRG_MASK) |
#define SIM_ADCOPT_ADC0TRGSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0TRGSEL_SHIFT))&SIM_ADCOPT_ADC0TRGSEL_MASK) |
#define SIM_ADCOPT_ADC1PRETRGSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC1PRETRGSEL_MASK) |
#define SIM_ADCOPT_ADC1SWPRETRG | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1SWPRETRG_SHIFT))&SIM_ADCOPT_ADC1SWPRETRG_MASK) |
#define SIM_ADCOPT_ADC1TRGSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1TRGSEL_SHIFT))&SIM_ADCOPT_ADC1TRGSEL_MASK) |
#define SIM_CHIPCTL_ADC_INTERLEAVE_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT))&SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK) |
#define SIM_CHIPCTL_ADC_SUPPLY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLY_SHIFT))&SIM_CHIPCTL_ADC_SUPPLY_MASK) |
#define SIM_CHIPCTL_ADC_SUPPLYEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT))&SIM_CHIPCTL_ADC_SUPPLYEN_MASK) |
#define SIM_CHIPCTL_CLKOUTDIV | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTDIV_SHIFT))&SIM_CHIPCTL_CLKOUTDIV_MASK) |
#define SIM_CHIPCTL_CLKOUTEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTEN_SHIFT))&SIM_CHIPCTL_CLKOUTEN_MASK) |
#define SIM_CHIPCTL_CLKOUTSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTSEL_SHIFT))&SIM_CHIPCTL_CLKOUTSEL_MASK) |
#define SIM_CHIPCTL_PDB_BB_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_PDB_BB_SEL_SHIFT))&SIM_CHIPCTL_PDB_BB_SEL_MASK) |
#define SIM_CHIPCTL_SRAML_RETEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAML_RETEN_SHIFT))&SIM_CHIPCTL_SRAML_RETEN_MASK) |
#define SIM_CHIPCTL_SRAMU_RETEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAMU_RETEN_SHIFT))&SIM_CHIPCTL_SRAMU_RETEN_MASK) |
#define SIM_CHIPCTL_TRACECLK_SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_TRACECLK_SEL_SHIFT))&SIM_CHIPCTL_TRACECLK_SEL_MASK) |
#define SIM_CLKDIV4_TRACEDIV | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIV_SHIFT))&SIM_CLKDIV4_TRACEDIV_MASK) |
#define SIM_CLKDIV4_TRACEDIVEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIVEN_SHIFT))&SIM_CLKDIV4_TRACEDIVEN_MASK) |
#define SIM_CLKDIV4_TRACEFRAC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEFRAC_SHIFT))&SIM_CLKDIV4_TRACEFRAC_MASK) |
#define SIM_FCFG1_DEPART | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK) |
#define SIM_FCFG1_EEERAMSIZE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EEERAMSIZE_SHIFT))&SIM_FCFG1_EEERAMSIZE_MASK) |
#define SIM_FTMOPT0_FTM0CLKSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0CLKSEL_SHIFT))&SIM_FTMOPT0_FTM0CLKSEL_MASK) |
#define SIM_FTMOPT0_FTM0FLTxSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM0FLTxSEL_MASK) |
#define SIM_FTMOPT0_FTM1CLKSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1CLKSEL_SHIFT))&SIM_FTMOPT0_FTM1CLKSEL_MASK) |
#define SIM_FTMOPT0_FTM1FLTxSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM1FLTxSEL_MASK) |
#define SIM_FTMOPT0_FTM2CLKSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2CLKSEL_SHIFT))&SIM_FTMOPT0_FTM2CLKSEL_MASK) |
#define SIM_FTMOPT0_FTM2FLTxSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM2FLTxSEL_MASK) |
#define SIM_FTMOPT0_FTM3CLKSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3CLKSEL_SHIFT))&SIM_FTMOPT0_FTM3CLKSEL_MASK) |
#define SIM_FTMOPT0_FTM3FLTxSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM3FLTxSEL_MASK) |
#define SIM_FTMOPT1_FTM0_OUTSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM0_OUTSEL_MASK) |
#define SIM_FTMOPT1_FTM0SYNCBIT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM0SYNCBIT_MASK) |
#define SIM_FTMOPT1_FTM1CH0SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1CH0SEL_SHIFT))&SIM_FTMOPT1_FTM1CH0SEL_MASK) |
#define SIM_FTMOPT1_FTM1SYNCBIT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM1SYNCBIT_MASK) |
#define SIM_FTMOPT1_FTM2CH0SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH0SEL_SHIFT))&SIM_FTMOPT1_FTM2CH0SEL_MASK) |
#define SIM_FTMOPT1_FTM2CH1SEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH1SEL_SHIFT))&SIM_FTMOPT1_FTM2CH1SEL_MASK) |
#define SIM_FTMOPT1_FTM2SYNCBIT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM2SYNCBIT_MASK) |
#define SIM_FTMOPT1_FTM3_OUTSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM3_OUTSEL_MASK) |
#define SIM_FTMOPT1_FTM3SYNCBIT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM3SYNCBIT_MASK) |
#define SIM_FTMOPT1_FTMGLDOK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTMGLDOK_SHIFT))&SIM_FTMOPT1_FTMGLDOK_MASK) |
#define SIM_LPOCLKS_LPO1KCLKEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO1KCLKEN_SHIFT))&SIM_LPOCLKS_LPO1KCLKEN_MASK) |
#define SIM_LPOCLKS_LPO32KCLKEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO32KCLKEN_SHIFT))&SIM_LPOCLKS_LPO32KCLKEN_MASK) |
#define SIM_LPOCLKS_LPOCLKSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPOCLKSEL_SHIFT))&SIM_LPOCLKS_LPOCLKSEL_MASK) |
#define SIM_LPOCLKS_RTCCLKSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_RTCCLKSEL_SHIFT))&SIM_LPOCLKS_RTCCLKSEL_MASK) |
#define SIM_MISCTRL0_FTM0_OBE_CTRL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM0_OBE_CTRL_MASK) |
#define SIM_MISCTRL0_FTM1_OBE_CTRL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM1_OBE_CTRL_MASK) |
#define SIM_MISCTRL0_FTM2_OBE_CTRL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM2_OBE_CTRL_MASK) |
#define SIM_MISCTRL0_FTM3_OBE_CTRL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM3_OBE_CTRL_MASK) |
#define SIM_MISCTRL1_SW_TRG | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL1_SW_TRG_SHIFT))&SIM_MISCTRL1_SW_TRG_MASK) |
#define SIM_PLATCGC_CGCDMA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCDMA_SHIFT))&SIM_PLATCGC_CGCDMA_MASK) |
#define SIM_PLATCGC_CGCEIM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCEIM_SHIFT))&SIM_PLATCGC_CGCEIM_MASK) |
#define SIM_PLATCGC_CGCERM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCERM_SHIFT))&SIM_PLATCGC_CGCERM_MASK) |
#define SIM_PLATCGC_CGCMPU | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMPU_SHIFT))&SIM_PLATCGC_CGCMPU_MASK) |
#define SIM_PLATCGC_CGCMSCM | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMSCM_SHIFT))&SIM_PLATCGC_CGCMSCM_MASK) |
#define SIM_SDID_DERIVATE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DERIVATE_SHIFT))&SIM_SDID_DERIVATE_MASK) |
#define SIM_SDID_FEATURES | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FEATURES_SHIFT))&SIM_SDID_FEATURES_MASK) |
#define SIM_SDID_GENERATION | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_GENERATION_SHIFT))&SIM_SDID_GENERATION_MASK) |
#define SIM_SDID_PACKAGE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PACKAGE_SHIFT))&SIM_SDID_PACKAGE_MASK) |
#define SIM_SDID_RAMSIZE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_RAMSIZE_SHIFT))&SIM_SDID_RAMSIZE_MASK) |
#define SIM_SDID_REVID | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) |
#define SIM_SDID_SUBSERIES | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBSERIES_SHIFT))&SIM_SDID_SUBSERIES_MASK) |
#define SIM_UIDH_UID127_96 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID127_96_SHIFT))&SIM_UIDH_UID127_96_MASK) |
#define SIM_UIDL_UID31_0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID31_0_SHIFT))&SIM_UIDL_UID31_0_MASK) |
#define SIM_UIDMH_UID95_64 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID95_64_SHIFT))&SIM_UIDMH_UID95_64_MASK) |
#define SIM_UIDML_UID63_32 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID63_32_SHIFT))&SIM_UIDML_UID63_32_MASK) |