S32 SDK
Interrupt vector numbers for S32K142

Detailed Description

Macros

#define NUMBER_OF_INT_VECTORS   139u
 

Enumerations

enum  IRQn_Type {
  NotAvail_IRQn = -128, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,
  PendSV_IRQn = -2, SysTick_IRQn = -1, DMA0_IRQn = 0u, DMA1_IRQn = 1u,
  DMA2_IRQn = 2u, DMA3_IRQn = 3u, DMA4_IRQn = 4u, DMA5_IRQn = 5u,
  DMA6_IRQn = 6u, DMA7_IRQn = 7u, DMA8_IRQn = 8u, DMA9_IRQn = 9u,
  DMA10_IRQn = 10u, DMA11_IRQn = 11u, DMA12_IRQn = 12u, DMA13_IRQn = 13u,
  DMA14_IRQn = 14u, DMA15_IRQn = 15u, DMA_Error_IRQn = 16u, MCM_IRQn = 17u,
  FTFC_IRQn = 18u, Read_Collision_IRQn = 19u, LVD_LVW_IRQn = 20u, FTFC_Fault_IRQn = 21u,
  WDOG_EWM_IRQn = 22u, RCM_IRQn = 23u, LPI2C0_Master_IRQn = 24u, LPI2C0_Slave_IRQn = 25u,
  LPSPI0_IRQn = 26u, LPSPI1_IRQn = 27u, LPUART0_RxTx_IRQn = 31u, LPUART1_RxTx_IRQn = 33u,
  ADC0_IRQn = 39u, ADC1_IRQn = 40u, CMP0_IRQn = 41u, ERM_single_fault_IRQn = 44u,
  ERM_double_fault_IRQn = 45u, RTC_IRQn = 46u, RTC_Seconds_IRQn = 47u, LPIT0_Ch0_IRQn = 48u,
  LPIT0_Ch1_IRQn = 49u, LPIT0_Ch2_IRQn = 50u, LPIT0_Ch3_IRQn = 51u, PDB0_IRQn = 52u,
  SCG_IRQn = 57u, LPTMR0_IRQn = 58u, PORTA_IRQn = 59u, PORTB_IRQn = 60u,
  PORTC_IRQn = 61u, PORTD_IRQn = 62u, PORTE_IRQn = 63u, SWI_IRQn = 64u,
  PDB1_IRQn = 68u, FLEXIO_IRQn = 69u, CAN0_ORed_IRQn = 78u, CAN0_Error_IRQn = 79u,
  CAN0_Wake_Up_IRQn = 80u, CAN0_ORed_0_15_MB_IRQn = 81u, CAN0_ORed_16_31_MB_IRQn = 82u, CAN1_ORed_IRQn = 85u,
  CAN1_Error_IRQn = 86u, CAN1_ORed_0_15_MB_IRQn = 88u, FTM0_Ch0_Ch1_IRQn = 99u, FTM0_Ch2_Ch3_IRQn = 100u,
  FTM0_Ch4_Ch5_IRQn = 101u, FTM0_Ch6_Ch7_IRQn = 102u, FTM0_Fault_IRQn = 103u, FTM0_Ovf_Reload_IRQn = 104u,
  FTM1_Ch0_Ch1_IRQn = 105u, FTM1_Ch2_Ch3_IRQn = 106u, FTM1_Ch4_Ch5_IRQn = 107u, FTM1_Ch6_Ch7_IRQn = 108u,
  FTM1_Fault_IRQn = 109u, FTM1_Ovf_Reload_IRQn = 110u, FTM2_Ch0_Ch1_IRQn = 111u, FTM2_Ch2_Ch3_IRQn = 112u,
  FTM2_Ch4_Ch5_IRQn = 113u, FTM2_Ch6_Ch7_IRQn = 114u, FTM2_Fault_IRQn = 115u, FTM2_Ovf_Reload_IRQn = 116u,
  FTM3_Ch0_Ch1_IRQn = 117u, FTM3_Ch2_Ch3_IRQn = 118u, FTM3_Ch4_Ch5_IRQn = 119u, FTM3_Ch6_Ch7_IRQn = 120u,
  FTM3_Fault_IRQn = 121u, FTM3_Ovf_Reload_IRQn = 122u
}
 Defines the Interrupt Numbers definitions. More...
 

Macro Definition Documentation

#define NUMBER_OF_INT_VECTORS   139u

Interrupt Number Definitions Number of interrupts in the Vector table

Definition at line 183 of file S32K142.h.

Enumeration Type Documentation

enum IRQn_Type

Defines the Interrupt Numbers definitions.

This enumeration is used to configure the interrupts.

Implements : IRQn_Type_Class

Enumerator
NotAvail_IRQn 

Not available device specific interrupt

NonMaskableInt_IRQn 

Non Maskable Interrupt

HardFault_IRQn 

Cortex-M4 SV Hard Fault Interrupt

MemoryManagement_IRQn 

Cortex-M4 Memory Management Interrupt

BusFault_IRQn 

Cortex-M4 Bus Fault Interrupt

UsageFault_IRQn 

Cortex-M4 Usage Fault Interrupt

SVCall_IRQn 

Cortex-M4 SV Call Interrupt

DebugMonitor_IRQn 

Cortex-M4 Debug Monitor Interrupt

PendSV_IRQn 

Cortex-M4 Pend SV Interrupt

SysTick_IRQn 

Cortex-M4 System Tick Interrupt

DMA0_IRQn 

DMA channel 0 transfer complete

DMA1_IRQn 

DMA channel 1 transfer complete

DMA2_IRQn 

DMA channel 2 transfer complete

DMA3_IRQn 

DMA channel 3 transfer complete

DMA4_IRQn 

DMA channel 4 transfer complete

DMA5_IRQn 

DMA channel 5 transfer complete

DMA6_IRQn 

DMA channel 6 transfer complete

DMA7_IRQn 

DMA channel 7 transfer complete

DMA8_IRQn 

DMA channel 8 transfer complete

DMA9_IRQn 

DMA channel 9 transfer complete

DMA10_IRQn 

DMA channel 10 transfer complete

DMA11_IRQn 

DMA channel 11 transfer complete

DMA12_IRQn 

DMA channel 12 transfer complete

DMA13_IRQn 

DMA channel 13 transfer complete

DMA14_IRQn 

DMA channel 14 transfer complete

DMA15_IRQn 

DMA channel 15 transfer complete

DMA_Error_IRQn 

DMA error interrupt channels 0-15

MCM_IRQn 

FPU sources

FTFC_IRQn 

FTFC Command complete

Read_Collision_IRQn 

FTFC Read collision

LVD_LVW_IRQn 

PMC Low voltage detect interrupt

FTFC_Fault_IRQn 

FTFC Double bit fault detect

WDOG_EWM_IRQn 

Single interrupt vector for WDOG and EWM

RCM_IRQn 

RCM Asynchronous Interrupt

LPI2C0_Master_IRQn 

LPI2C0 Master Interrupt

LPI2C0_Slave_IRQn 

LPI2C0 Slave Interrupt

LPSPI0_IRQn 

LPSPI0 Interrupt

LPSPI1_IRQn 

LPSPI1 Interrupt

LPUART0_RxTx_IRQn 

LPUART0 Transmit / Receive Interrupt

LPUART1_RxTx_IRQn 

LPUART1 Transmit / Receive Interrupt

ADC0_IRQn 

ADC0 interrupt request.

ADC1_IRQn 

ADC1 interrupt request.

CMP0_IRQn 

CMP0 interrupt request

ERM_single_fault_IRQn 

ERM single bit error correction

ERM_double_fault_IRQn 

ERM double bit error non-correctable

RTC_IRQn 

RTC alarm interrupt

RTC_Seconds_IRQn 

RTC seconds interrupt

LPIT0_Ch0_IRQn 

LPIT0 channel 0 overflow interrupt

LPIT0_Ch1_IRQn 

LPIT0 channel 1 overflow interrupt

LPIT0_Ch2_IRQn 

LPIT0 channel 2 overflow interrupt

LPIT0_Ch3_IRQn 

LPIT0 channel 3 overflow interrupt

PDB0_IRQn 

PDB0 interrupt

SCG_IRQn 

SCG bus interrupt request

LPTMR0_IRQn 

LPTIMER interrupt request

PORTA_IRQn 

Port A pin detect interrupt

PORTB_IRQn 

Port B pin detect interrupt

PORTC_IRQn 

Port C pin detect interrupt

PORTD_IRQn 

Port D pin detect interrupt

PORTE_IRQn 

Port E pin detect interrupt

SWI_IRQn 

Software interrupt

PDB1_IRQn 

PDB1 interrupt

FLEXIO_IRQn 

FlexIO Interrupt

CAN0_ORed_IRQn 

CAN0 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]

CAN0_Error_IRQn 

CAN0 Interrupt indicating that errors were detected on the CAN bus

CAN0_Wake_Up_IRQn 

CAN0 Interrupt asserted when Pretended Networking operation is enabled, and a valid message matches the selected filter criteria during Low Power mode

CAN0_ORed_0_15_MB_IRQn 

CAN0 OR'ed Message buffer (0-15)

CAN0_ORed_16_31_MB_IRQn 

CAN0 OR'ed Message buffer (16-31)

CAN1_ORed_IRQn 

CAN1 OR'ed [Bus Off OR Transmit Warning OR Receive Warning]

CAN1_Error_IRQn 

CAN1 Interrupt indicating that errors were detected on the CAN bus

CAN1_ORed_0_15_MB_IRQn 

CAN1 OR'ed Interrupt for Message buffer (0-15)

FTM0_Ch0_Ch1_IRQn 

FTM0 Channel 0 and 1 interrupt

FTM0_Ch2_Ch3_IRQn 

FTM0 Channel 2 and 3 interrupt

FTM0_Ch4_Ch5_IRQn 

FTM0 Channel 4 and 5 interrupt

FTM0_Ch6_Ch7_IRQn 

FTM0 Channel 6 and 7 interrupt

FTM0_Fault_IRQn 

FTM0 Fault interrupt

FTM0_Ovf_Reload_IRQn 

FTM0 Counter overflow and Reload interrupt

FTM1_Ch0_Ch1_IRQn 

FTM1 Channel 0 and 1 interrupt

FTM1_Ch2_Ch3_IRQn 

FTM1 Channel 2 and 3 interrupt

FTM1_Ch4_Ch5_IRQn 

FTM1 Channel 4 and 5 interrupt

FTM1_Ch6_Ch7_IRQn 

FTM1 Channel 6 and 7 interrupt

FTM1_Fault_IRQn 

FTM1 Fault interrupt

FTM1_Ovf_Reload_IRQn 

FTM1 Counter overflow and Reload interrupt

FTM2_Ch0_Ch1_IRQn 

FTM2 Channel 0 and 1 interrupt

FTM2_Ch2_Ch3_IRQn 

FTM2 Channel 2 and 3 interrupt

FTM2_Ch4_Ch5_IRQn 

FTM2 Channel 4 and 5 interrupt

FTM2_Ch6_Ch7_IRQn 

FTM2 Channel 6 and 7 interrupt

FTM2_Fault_IRQn 

FTM2 Fault interrupt

FTM2_Ovf_Reload_IRQn 

FTM2 Counter overflow and Reload interrupt

FTM3_Ch0_Ch1_IRQn 

FTM3 Channel 0 and 1 interrupt

FTM3_Ch2_Ch3_IRQn 

FTM3 Channel 2 and 3 interrupt

FTM3_Ch4_Ch5_IRQn 

FTM3 Channel 4 and 5 interrupt

FTM3_Ch6_Ch7_IRQn 

FTM3 Channel 6 and 7 interrupt

FTM3_Fault_IRQn 

FTM3 Fault interrupt

FTM3_Ovf_Reload_IRQn 

FTM3 Counter overflow and Reload interrupt

Definition at line 192 of file S32K142.h.