S32 SDK
quadspi_driver.h
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
18 #ifndef QUADSPI_DRIVER_H
19 #define QUADSPI_DRIVER_H
20 
21 #include <stddef.h>
22 #include <stdbool.h>
23 #include "device_registers.h"
24 #include "status.h"
25 
31 /*******************************************************************************
32  * Enumerations.
33  ******************************************************************************/
34 
37 #define QSPI_AHB_BUFFERS 4
38 
41 #define QSPI_LUT_LOCK_KEY 0x5AF05AF0U
42 
46 typedef enum
47 {
68 
72 typedef enum
73 {
79 
83 typedef enum
84 {
89 
90 
94 typedef enum
95 {
100 
101 
105 typedef enum
106 {
112 
116 typedef enum
117 {
121 
125 typedef enum
126 {
130 
131 
135 typedef enum
136 {
140 
141 
145 typedef enum
146 {
150 
154 typedef enum
155 {
159 
160 
161 /*******************************************************************************
162 * Definitions
163 ******************************************************************************/
164 
166 typedef void (* qspi_callback_t)(uint32_t instance, void * param);
167 
175 typedef struct
176 {
178  bool dmaSupport;
179  uint8_t dmaChannel;
181  void * callbackParam;
184  uint32_t memSize;
185  uint8_t csHoldTime;
186  uint8_t csSetupTime;
187  uint8_t columnAddr;
193  uint8_t io2IdleValue;
194  uint8_t io3IdleValue;
196 
204 typedef struct
205 {
206  uint8_t masters[QSPI_AHB_BUFFERS];
207  uint16_t sizes[QSPI_AHB_BUFFERS];
208  bool allMasters;
211 
212 
221 typedef struct
222 {
224  uint32_t instance; /* QuadSPI instance number */
225  bool dmaSupport; /* Enables DMA support in the driver */
226  uint8_t dmaChannel; /* DMA channel number. Only used if dmaSupport is true */
227  status_t status; /* Status of the current operation */
228  qspi_callback_t callback; /* User callback for reporting asynchronous events */
229  void * callbackParam; /* Parameter for user callback */
230  uint8_t * data; /* Buffer for data being currently received */
231  const uint8_t * roData; /* Read-only data (for program or verify operations) */
232  uint32_t size; /* Size of data being currently transmitted or received */
233  uint8_t operation; /* True if receiving in interrupt mode */
235 } qspi_state_t;
236 
237 
241 extern QuadSPI_Type * const g_qspiBase[];
242 
243 
244 /*******************************************************************************
245  * API
246  ******************************************************************************/
252 #if defined(__cplusplus)
253 extern "C" {
254 #endif
255 
256 
273 status_t QSPI_DRV_Init(uint32_t instance,
274  const qspi_user_config_t * userConfigPtr,
275  qspi_state_t * state);
276 
277 
288 status_t QSPI_DRV_Deinit(uint32_t instance);
289 
290 
298 
299 
307 status_t QSPI_DRV_AhbSetup(uint32_t instance, const qspi_ahb_config_t *config);
308 
309 
310 
327 static inline void QSPI_DRV_SetLut(uint32_t instance,
328  uint8_t lut,
329  qspi_lut_commands_t instr0,
330  qspi_lut_pads_t pad0,
331  uint8_t oprnd0,
332  qspi_lut_commands_t instr1,
333  qspi_lut_pads_t pad1,
334  uint8_t oprnd1)
335 {
336  QuadSPI_Type *baseAddr;
339 
340  baseAddr = g_qspiBase[instance];
341  baseAddr->LUT[lut] = QuadSPI_LUT_INSTR0(instr0)
342  | QuadSPI_LUT_PAD0(pad0)
343  | QuadSPI_LUT_OPRND0(oprnd0)
344  | QuadSPI_LUT_INSTR1(instr1)
345  | QuadSPI_LUT_PAD1(pad1)
346  | QuadSPI_LUT_OPRND1(oprnd1);
347 }
348 
349 
356 static inline void QSPI_DRV_LockLut(uint32_t instance)
357 {
358  QuadSPI_Type *baseAddr;
360 
361  baseAddr = g_qspiBase[instance];
362  baseAddr->LUTKEY = QSPI_LUT_LOCK_KEY;
363  baseAddr->LCKCR = QuadSPI_LCKCR_LOCK_MASK;
364 }
365 
366 
367 
374 static inline void QSPI_DRV_UnlockLut(uint32_t instance)
375 {
376  QuadSPI_Type *baseAddr;
378 
379  baseAddr = g_qspiBase[instance];
380  baseAddr->LUTKEY = QSPI_LUT_LOCK_KEY;
381  baseAddr->LCKCR = QuadSPI_LCKCR_UNLOCK_MASK;
382 }
383 
384 
391 static inline void QSPI_DRV_ClearIpSeqPointer(uint32_t instance)
392 {
393  QuadSPI_Type *baseAddr;
395 
396  baseAddr = g_qspiBase[instance];
398 }
399 
400 
407 static inline void QSPI_DRV_ClearAHBSeqPointer(uint32_t instance)
408 {
409  QuadSPI_Type *baseAddr;
411 
412  baseAddr = g_qspiBase[instance];
414 }
415 
416 
424 static inline void QSPI_DRV_SetAhbSeqId(uint32_t instance,
425  uint8_t seqID)
426 {
427  QuadSPI_Type *baseAddr;
429 
430  baseAddr = g_qspiBase[instance];
431  baseAddr->BFGENCR = QuadSPI_BFGENCR_SEQID(seqID);
432 }
433 
434 
443 status_t QSPI_DRV_IpCommand(uint32_t instance, uint8_t lut, uint32_t timeout);
444 
445 
465 status_t QSPI_DRV_IpRead(uint32_t instance,
466  uint8_t lut,
467  uint32_t addr,
468  uint8_t * dataRead,
469  const uint8_t * dataCmp,
470  uint32_t size,
471  qspi_transfer_type_t transferType,
472  uint32_t timeout);
473 
474 
487 status_t QSPI_DRV_IpWrite(uint32_t instance,
488  uint8_t lut,
489  uint32_t addr,
490  uint8_t * data,
491  uint32_t size,
492  qspi_transfer_type_t transferType,
493  uint32_t timeout);
494 
495 
504 status_t QSPI_DRV_IpErase(uint32_t instance,
505  uint8_t lut,
506  uint32_t addr);
507 
508 
515 status_t QSPI_DRV_IpGetStatus(uint32_t instance);
516 
517 
519 #if defined(__cplusplus)
520 }
521 #endif
522 
525 #endif /* QUADSPI_DRIVER_H */
526 /*******************************************************************************
527  * EOF
528  ******************************************************************************/
static void QSPI_DRV_LockLut(uint32_t instance)
Locks LUT table.
status_t QSPI_DRV_IpRead(uint32_t instance, uint8_t lut, uint32_t addr, uint8_t *dataRead, const uint8_t *dataCmp, uint32_t size, qspi_transfer_type_t transferType, uint32_t timeout)
Launches an IP read command.
qspi_endianess_t endianess
#define QuadSPI_LUT_COUNT
Definition: S32K148.h:9752
qspi_sample_delay_t sampleDelay
__IO uint32_t LUTKEY
Definition: S32K148.h:9793
#define QuadSPI_LCKCR_LOCK_MASK
Definition: S32K148.h:10296
qspi_flash_side_t
External flash connection options (side A/B) Implements : qspi_flash_side_t_Class.
qspi_date_rate_t
Clock phase used for sampling Rx data Implements : qspi_date_rate_t_Class.
status_t QSPI_DRV_IpWrite(uint32_t instance, uint8_t lut, uint32_t addr, uint8_t *data, uint32_t size, qspi_transfer_type_t transferType, uint32_t timeout)
Launches an IP write command.
qspi_transfer_type_t
Driver type Implements : qspi_transfer_type_t_Class.
qspi_lut_pads_t
Lut pad options Implements : qspi_lut_pads_t_Class.
qspi_clock_src_t clock_src
static void QSPI_DRV_UnlockLut(uint32_t instance)
Unlocks LUT table.
#define QuadSPI_BFGENCR_SEQID(x)
Definition: S32K148.h:9967
qspi_endianess_t
Endianess options Implements : qspi_endianess_t_Class.
status_t QSPI_DRV_Deinit(uint32_t instance)
De-initialize the qspi driver.
qspi_sample_delay_t
Delay used for sampling Rx data Implements : qspi_sample_delay_t_Class.
#define QuadSPI_LUT_PAD0(x)
Definition: S32K148.h:10312
#define QuadSPI_SPTRCLR_IPPTRC_MASK
Definition: S32K148.h:10261
#define DEV_ASSERT(x)
Definition: devassert.h:77
qspi_callback_t callback
__IO uint32_t LCKCR
Definition: S32K148.h:9794
#define QuadSPI_LUT_PAD1(x)
Definition: S32K148.h:10324
static void QSPI_DRV_ClearIpSeqPointer(uint32_t instance)
Clears IP sequence pointer.
qspi_date_rate_t dataRate
qspi_lut_commands_t
Lut commands Implements : qspi_lut_commands_t_Class.
static void QSPI_DRV_ClearAHBSeqPointer(uint32_t instance)
Clears AHB sequence pointer.
status_t QSPI_DRV_IpErase(uint32_t instance, uint8_t lut, uint32_t addr)
Launches an IP erase command.
#define QuadSPI_INSTANCE_COUNT
Definition: S32K148.h:9800
#define QuadSPI_LUT_INSTR1(x)
Definition: S32K148.h:10328
Driver configuration structure.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
static void QSPI_DRV_SetAhbSeqId(uint32_t instance, uint8_t seqID)
Sets sequence ID for AHB operations.
status_t QSPI_DRV_AhbSetup(uint32_t instance, const qspi_ahb_config_t *config)
Sets up AHB accesses to the serial flash.
qspi_sample_phase_t
Clock phase used for sampling Rx data Implements : qspi_sample_phase_t_Class.
status_t QSPI_DRV_IpGetStatus(uint32_t instance)
Checks the status of the currently running IP command.
void(* qspi_callback_t)(uint32_t instance, void *param)
QuadSPI callback function type.
status_t QSPI_DRV_IpCommand(uint32_t instance, uint8_t lut, uint32_t timeout)
Launches a simple IP command.
#define QuadSPI_LCKCR_UNLOCK_MASK
Definition: S32K148.h:10300
qspi_read_mode_t readMode
qspi_read_mode_t
Read mode Implements : qspi_read_mode_t_Class.
Driver internal context structure.
qspi_sample_phase_t clockPhase
#define QSPI_AHB_BUFFERS
Number of AHB buffers in the device.
qspi_flash_side_t side
static void QSPI_DRV_SetLut(uint32_t instance, uint8_t lut, qspi_lut_commands_t instr0, qspi_lut_pads_t pad0, uint8_t oprnd0, qspi_lut_commands_t instr1, qspi_lut_pads_t pad1, uint8_t oprnd1)
Configures LUT commands.
#define QSPI_LUT_LOCK_KEY
Key to lock/unlock LUT.
#define QuadSPI_SPTRCLR_BFPTRC_MASK
Definition: S32K148.h:10257
AHB configuration structure.
#define QuadSPI_LUT_OPRND1(x)
Definition: S32K148.h:10320
#define QuadSPI_LUT_INSTR0(x)
Definition: S32K148.h:10316
status_t QSPI_DRV_GetDefaultConfig(qspi_user_config_t *userConfigPtr)
Returns default configuration structure for QuadSPI.
#define QuadSPI_LUT_OPRND0(x)
Definition: S32K148.h:10308
__IO uint32_t SPTRCLR
Definition: S32K148.h:9784
QuadSPI_Type *const g_qspiBase[]
Table of base addresses for QuadSPI instances.
qspi_clock_src_t
Source of QuadSPI internal reference clock Implements : qspi_clock_src_t_Class.
__IO uint32_t BFGENCR
Definition: S32K148.h:9764
status_t QSPI_DRV_Init(uint32_t instance, const qspi_user_config_t *userConfigPtr, qspi_state_t *state)
Initializes the qspi driver.
__IO uint32_t LUT[QuadSPI_LUT_COUNT]
Definition: S32K148.h:9796