S32 SDK

#include <S32K142.h>

Data Fields

__I uint32_t VERID
 
__I uint32_t PARAM
 
uint8_t RESERVED_0 [8]
 
__IO uint32_t MCR
 
__IO uint32_t MSR
 
__IO uint32_t MIER
 
__IO uint32_t MDER
 
__IO uint32_t MCFGR0
 
__IO uint32_t MCFGR1
 
__IO uint32_t MCFGR2
 
__IO uint32_t MCFGR3
 
uint8_t RESERVED_1 [16]
 
__IO uint32_t MDMR
 
uint8_t RESERVED_2 [4]
 
__IO uint32_t MCCR0
 
uint8_t RESERVED_3 [4]
 
__IO uint32_t MCCR1
 
uint8_t RESERVED_4 [4]
 
__IO uint32_t MFCR
 
__I uint32_t MFSR
 
__IO uint32_t MTDR
 
uint8_t RESERVED_5 [12]
 
__I uint32_t MRDR
 
uint8_t RESERVED_6 [156]
 
__IO uint32_t SCR
 
__IO uint32_t SSR
 
__IO uint32_t SIER
 
__IO uint32_t SDER
 
uint8_t RESERVED_7 [4]
 
__IO uint32_t SCFGR1
 
__IO uint32_t SCFGR2
 
uint8_t RESERVED_8 [20]
 
__IO uint32_t SAMR
 
uint8_t RESERVED_9 [12]
 
__I uint32_t SASR
 
__IO uint32_t STAR
 
uint8_t RESERVED_10 [8]
 
__IO uint32_t STDR
 
uint8_t RESERVED_11 [12]
 
__I uint32_t SRDR
 

Detailed Description

LPI2C - Size of Registers Arrays LPI2C - Register Layout Typedef

Definition at line 5264 of file S32K142.h.

Field Documentation

__IO uint32_t MCCR0

Master Clock Configuration Register 0, offset: 0x48

Definition at line 5279 of file S32K142.h.

__IO uint32_t MCCR1

Master Clock Configuration Register 1, offset: 0x50

Definition at line 5281 of file S32K142.h.

__IO uint32_t MCFGR0

Master Configuration Register 0, offset: 0x20

Definition at line 5272 of file S32K142.h.

__IO uint32_t MCFGR1

Master Configuration Register 1, offset: 0x24

Definition at line 5273 of file S32K142.h.

__IO uint32_t MCFGR2

Master Configuration Register 2, offset: 0x28

Definition at line 5274 of file S32K142.h.

__IO uint32_t MCFGR3

Master Configuration Register 3, offset: 0x2C

Definition at line 5275 of file S32K142.h.

__IO uint32_t MCR

Master Control Register, offset: 0x10

Definition at line 5268 of file S32K142.h.

__IO uint32_t MDER

Master DMA Enable Register, offset: 0x1C

Definition at line 5271 of file S32K142.h.

__IO uint32_t MDMR

Master Data Match Register, offset: 0x40

Definition at line 5277 of file S32K142.h.

__IO uint32_t MFCR

Master FIFO Control Register, offset: 0x58

Definition at line 5283 of file S32K142.h.

__I uint32_t MFSR

Master FIFO Status Register, offset: 0x5C

Definition at line 5284 of file S32K142.h.

__IO uint32_t MIER

Master Interrupt Enable Register, offset: 0x18

Definition at line 5270 of file S32K142.h.

__I uint32_t MRDR

Master Receive Data Register, offset: 0x70

Definition at line 5287 of file S32K142.h.

__IO uint32_t MSR

Master Status Register, offset: 0x14

Definition at line 5269 of file S32K142.h.

__IO uint32_t MTDR

Master Transmit Data Register, offset: 0x60

Definition at line 5285 of file S32K142.h.

__I uint32_t PARAM

Parameter Register, offset: 0x4

Definition at line 5266 of file S32K142.h.

uint8_t RESERVED_0[8]

Definition at line 5267 of file S32K142.h.

uint8_t RESERVED_1[16]

Definition at line 5276 of file S32K142.h.

uint8_t RESERVED_10[8]

Definition at line 5301 of file S32K142.h.

uint8_t RESERVED_11[12]

Definition at line 5303 of file S32K142.h.

uint8_t RESERVED_2[4]

Definition at line 5278 of file S32K142.h.

uint8_t RESERVED_3[4]

Definition at line 5280 of file S32K142.h.

uint8_t RESERVED_4[4]

Definition at line 5282 of file S32K142.h.

uint8_t RESERVED_5[12]

Definition at line 5286 of file S32K142.h.

uint8_t RESERVED_6[156]

Definition at line 5288 of file S32K142.h.

uint8_t RESERVED_7[4]

Definition at line 5293 of file S32K142.h.

uint8_t RESERVED_8[20]

Definition at line 5296 of file S32K142.h.

uint8_t RESERVED_9[12]

Definition at line 5298 of file S32K142.h.

__IO uint32_t SAMR

Slave Address Match Register, offset: 0x140

Definition at line 5297 of file S32K142.h.

__I uint32_t SASR

Slave Address Status Register, offset: 0x150

Definition at line 5299 of file S32K142.h.

__IO uint32_t SCFGR1

Slave Configuration Register 1, offset: 0x124

Definition at line 5294 of file S32K142.h.

__IO uint32_t SCFGR2

Slave Configuration Register 2, offset: 0x128

Definition at line 5295 of file S32K142.h.

__IO uint32_t SCR

Slave Control Register, offset: 0x110

Definition at line 5289 of file S32K142.h.

__IO uint32_t SDER

Slave DMA Enable Register, offset: 0x11C

Definition at line 5292 of file S32K142.h.

__IO uint32_t SIER

Slave Interrupt Enable Register, offset: 0x118

Definition at line 5291 of file S32K142.h.

__I uint32_t SRDR

Slave Receive Data Register, offset: 0x170

Definition at line 5304 of file S32K142.h.

__IO uint32_t SSR

Slave Status Register, offset: 0x114

Definition at line 5290 of file S32K142.h.

__IO uint32_t STAR

Slave Transmit ACK Register, offset: 0x154

Definition at line 5300 of file S32K142.h.

__IO uint32_t STDR

Slave Transmit Data Register, offset: 0x160

Definition at line 5302 of file S32K142.h.

__I uint32_t VERID

Version ID Register, offset: 0x0

Definition at line 5265 of file S32K142.h.


The documentation for this struct was generated from the following file: