S32 SDK
sbc_uja1169_driver.c
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
54 #include "sbc_uja1169_driver.h"
55 #include "clock_manager.h"
56 #include "osif.h"
57 
58 /*******************************************************************************
59  * Variables - for internal use only.
60  ******************************************************************************/
61 typedef struct{
63  uint32_t lpspiIntace;
64  bool isInit;
66 
67 /*******************************************************************************
68  * Variables
69  ******************************************************************************/
70 /* Structure for storing SBC internal runtime data. */
72 
73 /*******************************************************************************
74  * Private Functions
75  ******************************************************************************/
76 
77 static status_t sbc_write_can_others(const sbc_can_conf_t* const can);
79 static void sbc_clean_events_status(sbc_evn_capt_t *event);
80 static status_t sbc_change_factories_direct(const sbc_factories_conf_t* const factory);
81 static uint8_t sbc_get_factories_crc(uint8_t* data);
82 
83 /*******************************************************************************
84  * Code
85  ******************************************************************************/
86 
87 /*FUNCTION**********************************************************************
88  *
89  * Function Name : SBC_Init
90  * Description : This function initializes all registers. It waits 10ms and
91  * then writes to all registers.
92  * The following is an example of how to initialize device and set up all
93  * registers by passing config parameter to SBC_Init
94  * function:
95  * sbc_int_config_t config;
96  * config.regulator.regulator.pdc = SBC_UJA_REGULATOR_PDC_HV;
97  * ...
98  * config.supplyEvnt.v2oe = SBC_UJA_SUPPLY_EVNT_V2OE_DIS;
99  * ...
100  * ...
101  * config.can.wakePin.wpfe = SBC_UJA_WAKE_EN_WPFE_DIS;
102  *
103  * lpspiInstance is instance of LPSPI device.
104 
105  * status_t status = SBC_SetVreg(&regulator);
106  *
107  * Implements : SBC_Init_Activity
108  *END**************************************************************************/
109 status_t SBC_Init(const sbc_int_config_t *const config, const uint32_t lpspiInstance)
110 {
111  status_t status = STATUS_SUCCESS;
112 
113  DEV_ASSERT(config != NULL);
114 
115  /* Set initial value */
116  g_drvConfig.lpspiIntace = lpspiInstance;
117  /* Device is being initialized. */
118  g_drvConfig.isInit = true;
119  g_drvConfig.watchdogCtr.modeControl = config->watchdog.modeControl;
120  g_drvConfig.watchdogCtr.nominalPeriod = config->watchdog.nominalPeriod;
121 
122  /* SBC initialization. */
123  /* Waiting while device leave reset mode. */
124  OSIF_TimeDelay(20);
125  /* Take device in stand by mode during initialization. */
127 
128  if(status == STATUS_SUCCESS)
129  {
130  status = SBC_SetVreg(&config->regulatorCtr);
131  }
132 
133  if(status == STATUS_SUCCESS)
134  {
135  status = SBC_SetWatchdog(&config->watchdog);
136  }
137 
138  if(status == STATUS_SUCCESS)
139  {
140  status = SBC_SetFailSafe(config->lhc, NULL);
141  }
142 
143  if(status == STATUS_SUCCESS)
144  {
145  status = SBC_SetSystemEvents(&config->sysEvnt);
146  }
147 
148  if(status == STATUS_SUCCESS)
149  {
150  status = SBC_SetLock(config->lockMask);
151  }
152 
153  if(status == STATUS_SUCCESS)
154  {
155  status = SBC_SetCanConfig(&config->can);
156  }
157 
158  if(status == STATUS_SUCCESS)
159  {
160  status = SBC_SetWakePin(&config->wakePin);
161  }
162 
163  if(status == STATUS_SUCCESS)
164  {
165  status = SBC_SetMode(config->mode);
166  }
167  /* Device was initialized successfully. */
168  g_drvConfig.isInit = false;
169 
170  return status;
171 }
172 
173 /*FUNCTION**********************************************************************
174  *
175  * Function Name : SBC_SetVreg
176  * Description : This function configures Regulator control registers:
177  * Regulator control (0x10), Supply event enable(0x1C).
178  * The following is an example of how to set up regulator registers by
179  * passing regulator parameter to SBC_SetVreg function:
180  * sbc_regulator_ctr_t regulator;
181  * Regulator Register.
182  * regulator.regulator.pdc = SBC_UJA_REGULATOR_PDC_LV;
183  * regulator.regulator.v2c = SBC_UJA_REGULATOR_V2C_N_S_R;
184  * regulator.regulator.v1rtc = SBC_UJA_REGULATOR_V1RTC_80;
185  * Supply register.
186  * regulator.supplyEvnt.v1ue = SBC_UJA_SUPPLY_EVNT_V1UE_EN;
187  * regulator.supplyEvnt.v2oe = SBC_UJA_SUPPLY_EVNT_V2OE_DIS;
188  * regulator.supplyEvnt.v2ue = SBC_UJA_SUPPLY_EVNT_V2UE_EN;
189  * status_t status = SBC_SetVreg(&regulator);
190  *
191  * Implements : SBC_SetVreg_Activity
192  *END**************************************************************************/
193 status_t SBC_SetVreg(const sbc_regulator_ctr_t* const regulatorCtr)
194 {
195  status_t status = STATUS_SUCCESS;
196  status_t spiStat = STATUS_SUCCESS;
197 
198  DEV_ASSERT(regulatorCtr != NULL);
199 
200  const sbc_regulator_t *regulator = &regulatorCtr->regulator;
201  uint8_t regData = (uint8_t)((uint8_t)regulator->pdc | (uint8_t)regulator->v2c
202  | (uint8_t)regulator->v1rtc);
203 
204  /* Send configuration to Regulator control register. */
205  spiStat = SBC_DataTransfer(SBC_UJA_REGULATOR, &regData, NULL);
206  regData = 0U;
207 
208  if(spiStat == STATUS_SUCCESS )
209  {
210  const sbc_supply_evnt_t *sEvnt = &regulatorCtr->supplyEvnt;
211  /* Send configuration to Supply Event register. */
212  regData = (uint8_t)((uint8_t)sEvnt->v2oe | (uint8_t)sEvnt->v2ue
213  | (uint8_t)sEvnt->v1ue);
214  spiStat = SBC_DataTransfer(SBC_UJA_SUPPLY_EVNT, &regData, NULL);
215  }
216 
217  if(spiStat != STATUS_SUCCESS)
218  {
219  status = SBC_COMM_ERROR;
220  }
221 
222  return status;
223 }
224 
225 /*FUNCTION**********************************************************************
226  *
227  * Function Name : SBC_GetVreg
228  * Description : This function reads Regulator control registers:
229  * Regulator control (0x10), Supply event enable(0x1C).
230  * The following is an example of how to read content of Regulator registers by
231  * passing regulator parameter to SBC_GetVreg function:
232  * sbc_regulator_ctr_t regulator;
233  * status_t status = SBC_GetVreg(&regulator);
234  *
235  * Implements : SBC_GetVreg_Activity
236  *END**************************************************************************/
238 {
239  status_t status = STATUS_SUCCESS;
240  status_t spiStat = STATUS_SUCCESS;
241 
242  DEV_ASSERT(regulatorCtr != NULL);
243 
244  sbc_regulator_t *regulator = &regulatorCtr->regulator;
245  uint8_t regData = 0;
246 
247  /* Read configuration from Regulator control register. */
248  spiStat = SBC_DataTransfer(SBC_UJA_REGULATOR, NULL, &regData);
249 
250  if(spiStat == STATUS_SUCCESS )
251  {
252  /* Set regulator structure. */
253  regulator->pdc = (sbc_regulator_pdc_t)(regData & SBC_UJA_REGULATOR_PDC_MASK);
254  regulator->v2c = (sbc_regulator_v2c_t)(regData & SBC_UJA_REGULATOR_V2C_MASK);
255  regulator->v1rtc = (sbc_regulator_v1rtc_t)(regData & SBC_UJA_REGULATOR_V1RTC_MASK);
256 
257  sbc_supply_evnt_t *sEvnt = &regulatorCtr->supplyEvnt;
258  /* Read configuration from Supply Event register. */
259  regData = 0;
260  spiStat = SBC_DataTransfer(SBC_UJA_SUPPLY_EVNT, NULL, &regData);
261 
262  /* Set Supply Event structure. */
266  }
267 
268  if(spiStat != STATUS_SUCCESS)
269  {
270  status = SBC_COMM_ERROR;
271  }
272 
273  return status;
274 }
275 
276 /*FUNCTION**********************************************************************
277  *
278  * Function Name : SBC_SetWatchdog
279  * Description : This function writes to Watchdog control register (0x00).
280  * This function can select Watchdog mode control, and nominal watchdog period.
281  * The UJA1169 contains a watchdog that supports three operating modes: Window,
282  * Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a
283  * watchdog trigger event within a defined watchdog window triggers and resets
284  * the watchdog timer. In Timeout mode, the watchdog runs continuously and can
285  * be triggered and reset at any time within the watchdog period by a watchdog
286  * trigger. Watchdog time-out mode can also be used for cyclic wake-up
287  * of the microcontroller. In Autonomous mode, the watchdog can be off or
288  * autonomously in Timeout mode, depending on the selected SBC mode.
289  * Note SBC mode will temporary set to StandBy while WatchDog configuration
290  * is changed.
291  * The following is an example of how to set up Watchdog register by
292  * passing wtdog parameter to SBC_SetWatchdog function:
293  * wtdog.modeControl = SBC_UJA_WTDOG_CTR_WMC_AUTO;
294  * wtdog.nominalPeriod = SBC_UJA_WTDOG_CTR_NWP_4096;
295  * status_t status = SBC_SetWatchdog(&wtdog);
296  *
297  * Implements : SBC_SetWatchdog_Activity
298  *END**************************************************************************/
300 {
301  status_t status = STATUS_SUCCESS;
302  status_t spiStat = STATUS_SUCCESS;
303 
304  DEV_ASSERT(wtdog != NULL);
305 
306  bool newWdMode = false;
307  /* Variable for storing current Mode settings. */
308  sbc_mode_mc_t currentMode = SBC_UJA_MODE_MC_SLEEP;
309 
310  /* Test if new Watchdog value is different. */
311  if((g_drvConfig.watchdogCtr.modeControl != wtdog->modeControl) ||
312  (g_drvConfig.watchdogCtr.nominalPeriod != wtdog->nominalPeriod)
313  || g_drvConfig.isInit)
314  {
315  newWdMode = true;
316  /* Read current mode. */
317  status = SBC_GetMode(&currentMode);
318  }
319 
320  /* Set device to stand by mode. */
321  if(newWdMode && (status == STATUS_SUCCESS) &&
322  (currentMode != SBC_UJA_MODE_MC_STANDBY))
323  {
325  }
326 
327  if(status == STATUS_SUCCESS)
328  {
329  uint8_t regData = (uint8_t)((uint8_t)wtdog->modeControl
330  | (uint8_t)wtdog->nominalPeriod);
331 
332  /* Send configuration to Watchdog control register. */
333  spiStat = SBC_DataTransfer(SBC_UJA_WTDOG_CTR, &regData, NULL);
334  }
335 
336  if(newWdMode && (spiStat == STATUS_SUCCESS) &&
337  (status == STATUS_SUCCESS) &&
338  (currentMode != SBC_UJA_MODE_MC_STANDBY))
339  {
340  /* Return to previous mode. */
341  status = SBC_SetMode(currentMode);
342 
343  g_drvConfig.watchdogCtr.modeControl = wtdog->modeControl;
344  g_drvConfig.watchdogCtr.nominalPeriod = wtdog->nominalPeriod;
345  }
346 
347  if(spiStat != STATUS_SUCCESS)
348  {
349  status = SBC_COMM_ERROR;
350  }
351 
352  return status;
353 }
354 
355 /*FUNCTION**********************************************************************
356  *
357  * Function Name : SBC_GetWatchdog
358  * Description : This function reads Watchdog control register (0x00).
359  * This function reads Watchdog mode control, and nominal watchdog period.
360  * The UJA1169 contains a watchdog that supports three operating modes: Window,
361  * Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a
362  * watchdog trigger event within a defined watchdog window triggers and resets
363  * the watchdog timer. In Timeout mode, the watchdog runs continuously and can
364  * be triggered and reset at any time within the watchdog period by a watchdog
365  * trigger. Watchdog time-out mode can also be used for cyclic wake-up
366  * of the microcontroller. In Autonomous mode, the watchdog can be off or
367  * autonomously in Timeout mode, depending on the selected SBC mode.
368  * The following is an example of how to read from Watchdog register by
369  * passing wtdog parameter to SBC_GetWatchdog function:
370  * sbc_wtdog_ctr_t wtdog;
371  * status_t status = SBC_GetWatchdog(&wtdog);
372  *
373  * Implements : SBC_GetWatchdog_Activity
374  *END**************************************************************************/
376 {
377  status_t status = STATUS_SUCCESS;
378  status_t spiStat = STATUS_SUCCESS;
379 
380  DEV_ASSERT(wtdog != NULL);
381 
382  uint8_t regData = 0;
383 
384  /* Read configuration from Watchdog control register. */
385  spiStat = SBC_DataTransfer(SBC_UJA_WTDOG_CTR, NULL, &regData);
386 
387  if(spiStat == STATUS_SUCCESS)
388  {
391 
392  g_drvConfig.watchdogCtr.modeControl = wtdog->modeControl;
393  g_drvConfig.watchdogCtr.nominalPeriod = wtdog->nominalPeriod;
394  }
395 
396  if(spiStat != STATUS_SUCCESS)
397  {
398  status = SBC_COMM_ERROR;
399  }
400 
401  return status;
402 }
403 
404 /*FUNCTION**********************************************************************
405  *
406  * Function Name : SBC_FeedWatchdog
407  * Description : This function refresh watchdog period by writing byte to
408  * the SBC watchdog register. This function must be called periodically
409  * according Watchdog mode control and Nominal watchdog period settings.
410  * Note: Unxpected behaviour can happend if watchdog mode is set to timeout
411  * period and watchdog is triggered exactly at 50% of period.
412  * Be sure you trigger watchdog before 50% or above 50% of watchdog period.
413  * The following is an example of how to use sbc_refresh_watchdog function:
414  * SBC_SetWatchdog();
415  *
416  * Implements : SBC_FeedWatchdog_Activity
417  *END**************************************************************************/
419 {
420  (void)SBC_SetWatchdog(&g_drvConfig.watchdogCtr);
421 }
422 
423 /*FUNCTION**********************************************************************
424  *
425  * Function Name : SBC_SetMode
426  * Description : This function write to Mode control register (0x01).
427  * Normal mode is the active operating mode. In this mode, all the hardware on
428  * the device is available and can be activated. Voltage regulator
429  * V1 is enabled to supply the microcontroller.
430  * Standby mode is the first-level power-saving mode of the UJA1169, offering
431  * reduced current consumption. The transceiver is unable to transmit or
432  * receive data in Standby mode. The SPI remains enabled and V1 is still active;
433  * the watchdog is active (in Timeout mode) if enabled. The behavior
434  * of V2/VEXT is determined by the SPI setting.
435  * Sleep mode is the second-level power-saving mode of the UJA1169.
436  * The difference between Sleep and Standby modes is that V1 is off in
437  * Sleep mode and temperature protection is inactive.
438  * Note event status are cleared before device move to sleep mode. At least
439  * one wake up event must be enabled before moving to sleep mode otherwise SBC
440  * will be reseted.
441  * The following is an example of how to set up Mode register by
442  * passing mode parameter to SBC_SetMode function:
443  * sbc_mode_mc_t mode;
444  * mode = SBC_UJA_MODE_MC_STANDBY;
445  * status_t status = SBC_SetMode(&mode);
446  *
447  * Implements : SBC_SetMode_Activity
448  *END**************************************************************************/
450 {
451  status_t status = STATUS_SUCCESS;
452  status_t spiStat = STATUS_SUCCESS;
453 
454  uint8_t regData = (uint8_t)mode;
455 
456  if((mode == SBC_UJA_MODE_MC_SLEEP) || (mode == SBC_UJA_MODE_MC_STANDBY)
457  || (mode == SBC_UJA_MODE_MC_NORMAL))
458  {
459  if((mode == SBC_UJA_MODE_MC_SLEEP) || (mode == SBC_UJA_MODE_MC_STANDBY))
460  {
461  /* Clear all events and move to sleep mode. */
462  sbc_evn_capt_t events;
463  status = SBC_GetEventsStatus(&events);
464 
465  if(status == STATUS_SUCCESS)
466  {
467  status = SBC_CleanEvents(&events);
468  }
469  }
470  }
471  else
472  {
473  status = SBC_CMD_ERROR;
474  }
475 
476  if(status == STATUS_SUCCESS)
477  {
478  /* Write mode. */
479  spiStat = SBC_DataTransfer(SBC_UJA_MODE, &regData, NULL);
480  }
481 
482  if(spiStat != STATUS_SUCCESS)
483  {
484  status = SBC_COMM_ERROR;
485  }
486 
487  return status;
488 }
489 
490 /*FUNCTION**********************************************************************
491  *
492  * Function Name : SBC_GetMode
493  * Description : This function reads the Mode control register (0x01).
494  * Normal mode is the active operating mode. In this mode, all the hardware on
495  * the device is available and can be activated. Voltage regulator
496  * V1 is enabled to supply the microcontroller.
497  * Standby mode is the first-level power-saving mode of the UJA1169, offering
498  * reduced current consumption. The transceiver is unable to transmit or
499  * receive data in Standby mode. The SPI remains enabled and V1 is still active;
500  * the watchdog is active (in Timeout mode) if enabled. The behavior
501  * of V2/VEXT is determined by the SPI setting.
502  * Sleep mode is the second-level power-saving mode of the UJA1169.
503  * The difference between Sleep and Standby modes is that V1 is off in
504  * Sleep mode and temperature protection is inactive.
505  * The following is an example of how to read from Mode register by
506  * passing mode parameter to SBC_GetMode function:
507  * sbc_mode_mc_t mode;
508  * status_t status = SBC_GetMode(&mode);
509  *
510  * Implements : SBC_GetMode_Activity
511  *END**************************************************************************/
513 {
514  status_t status = STATUS_SUCCESS;
515  status_t spiStat = STATUS_SUCCESS;
516  uint8_t regData = 0;
517 
518  DEV_ASSERT(mode != NULL);
519 
520  /* Read mode. */
521  spiStat = SBC_DataTransfer(SBC_UJA_MODE, NULL, &regData);
522 
523  if(spiStat == STATUS_SUCCESS)
524  {
525  *mode = (sbc_mode_mc_t)(regData & SBC_UJA_MODE_MC_MASK);
526  }
527 
528  if(spiStat != STATUS_SUCCESS)
529  {
530  status = SBC_COMM_ERROR;
531  }
532 
533  return status;
534 }
535 
536 /*FUNCTION**********************************************************************
537  *
538  * Function Name : SBC_SetFailSafe
539  * Description : This function writes to Fail-safe control register (0x02).
540  * The dedicated LIMP pin can be used to enable so called limp home hardware
541  * in the event of a serious ECU failure. Detectable failure conditions include
542  * SBC overtemperature events, loss of watchdog service, short-circuits on pins
543  * RSTN or V1 and user-initiated or external reset events.
544  * The LIMP pin is a battery-robust, active-LOW, open-drain output.
545  * The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe
546  * control register.
547  * The limp-home function and the reset counter are disabled in
548  * Forced Normal mode. The LIMP pin is floating, RCC remains unchanged
549  * and bit LHC = 0.
550  * RCC -reset counter control.
551  * incremented every time the SBC enters Reset mode while FNMC = 0;
552  * RCC overflows from 11 to 00; default at power-on is 00. For ignore settings
553  * of rcc use NULL pointer or otherwise send pointer to variable.
554  * The following is an example of how to write to limp home control by
555  * passing lhc parameter to SBC_SetFailSafe function:
556  * sbc_fail_safe_lhc_t lhc;
557  * lhc = SBC_UJA_FAIL_SAFE_LHC_FLOAT;
558  * status_t status = SBC_SetFailSafe(&lhc, NULL);
559  *
560  * Implements : SBC_SetFailSafe_Activity
561  *END**************************************************************************/
563  const sbc_fail_safe_rcc_t* const rcc)
564 {
565  status_t status = STATUS_SUCCESS;
566  status_t spiStat = STATUS_SUCCESS;
567 
569  {
570  uint8_t regData = (uint8_t)lhc;
571 
572  /* Test if rcc should be changed. */
573  if((rcc != NULL) && ( (*rcc == 0U) || (*rcc <=3U) ) )
574  {
575  regData |= (uint8_t)SBC_UJA_FAIL_SAFE_RCC_F(*rcc);
576  }
577 
578  /* Send configuration to Fail-safe control register. */
579  spiStat = SBC_DataTransfer(SBC_UJA_FAIL_SAFE, &regData, NULL);
580  }
581  else
582  {
583  status = SBC_CMD_ERROR;
584  }
585 
586  if(spiStat != STATUS_SUCCESS)
587  {
588  status = SBC_COMM_ERROR;
589  }
590 
591  return status;
592 }
593 
594 /*FUNCTION**********************************************************************
595  *
596  * Function Name : SBC_GetFailSafe
597  * Description : This function reads from Fail-safe control register (0x02).
598  * The dedicated LIMP pin can be used to enable so called limp home hardware
599  * in the event of a serious ECU failure. Detectable failure conditions include
600  * SBC overtemperature events, loss of watchdog service, short-circuits on pins
601  * RSTN or V1 and user-initiated or external reset events.
602  * The LIMP pin is a battery-robust, active-LOW, open-drain output.
603  * The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe
604  * control register.
605  * The limp-home function and the reset counter are disabled in
606  * Forced Normal mode. The LIMP pin is floating, RCC remains unchanged
607  * and bit LHC = 0.
608  * The following is an example of how to read from limp home control by
609  * passing lhc parameter to SBC_GetFailSafe function:
610  * sbc_fail_safe_lhc_t lhc;
611  * sbc_fail_safe_rcc_t rcc;
612  * status_t status = SBC_GetFailSafe(&lhc, &rcc);
613  *
614  * Implements : SBC_GetFailSafe_Activity
615  *END**************************************************************************/
617  sbc_fail_safe_rcc_t * const rcc)
618 {
619  status_t status = STATUS_SUCCESS;
620  status_t spiStat = STATUS_SUCCESS;
621 
622  DEV_ASSERT(lhc != NULL);
623 
624  uint8_t regData = 0;
625 
626  /* Read configuration from Fail-safe control register. */
627  spiStat = SBC_DataTransfer(SBC_UJA_FAIL_SAFE, NULL, &regData);
628 
629  /* Test if rcc should be read. */
630  if( (rcc != NULL) && (spiStat == STATUS_SUCCESS) )
631  {
633  }
634 
635  if(spiStat == STATUS_SUCCESS)
636  {
638  }
639 
640  if(spiStat != STATUS_SUCCESS)
641  {
642  status = SBC_COMM_ERROR;
643  }
644 
645  return status;
646 }
647 
648 /*FUNCTION**********************************************************************
649  *
650  * Function Name : SBC_SetSystemEvents
651  * Description : This function write System event capture enable
652  * register (0x04).
653  * This function enables or disables overtemperature warning,
654  * SPI failure enable.
655  * The following is an example of how to write to System event capture enable
656  * register by passing sysEvnt parameter to SBC_SetSystemEvents function:
657  * sbc_sys_evnt_t sysEvnt;
658  * sysEvnt.owte = SBC_UJA_SYS_EVNT_OTWE_DIS;
659  * sysEvnt.spife = SBC_UJA_SYS_EVNT_SPIFE_DIS;
660  * status_t status = SBC_SetSystemEvents(&sysEvnt);
661  *
662  * Implements : SBC_SetSystemEvents_Activity
663  *END**************************************************************************/
665 {
666  status_t status = STATUS_SUCCESS;
667  status_t spiStat = STATUS_SUCCESS;
668 
669  DEV_ASSERT(sysEvnt != NULL);
670 
671  uint8_t regData = (uint8_t)((uint8_t)sysEvnt->owte | (uint8_t)sysEvnt->spife);
672 
673  /* Send configuration to System event register. */
674  spiStat = SBC_DataTransfer(SBC_UJA_SYSTEM_EVNT, &regData, NULL);
675 
676  if(spiStat != STATUS_SUCCESS)
677  {
678  status = SBC_COMM_ERROR;
679  }
680 
681  return status;
682 }
683 
684 /*FUNCTION**********************************************************************
685  *
686  * Function Name : SBC_GetSystemEvents
687  * Description : This function reads System event capture enable
688  * register (0x04).
689  * This function reads content of overtemperature warning and SPI failure
690  * settings.
691  * The following is an example of how to write to System event capture enable
692  * register by passing sysEvnt parameter to SBC_GetSystemEvents function:
693  * sbc_sys_evnt_t sysEvnt;
694  * status_t status = SBC_GetSystemEvents(&sysEvnt);
695  *
696  * Implements : SBC_GetSystemEvents_Activity
697  *END**************************************************************************/
699 {
700  status_t status = STATUS_SUCCESS;
701  status_t spiStat = STATUS_SUCCESS;
702 
703  DEV_ASSERT(sysEvnt != NULL);
704 
705  uint8_t regData = 0;
706 
707  /* Read configuration from System event register. */
708  spiStat = SBC_DataTransfer(SBC_UJA_SYSTEM_EVNT, NULL, &regData);
709  if(spiStat == STATUS_SUCCESS)
710  {
711  sysEvnt->owte = (sbc_sys_evnt_otwe_t)(regData & SBC_UJA_SYS_EVNT_OTWE_MASK);
713  }
714 
715  if(spiStat != STATUS_SUCCESS)
716  {
717  status = SBC_COMM_ERROR;
718  }
719 
720  return status;
721 }
722 
723 /*FUNCTION**********************************************************************
724  *
725  * Function Name : SBC_SetLock
726  * Description : This function writes to Lock control register (0x0A).
727  * Sections of the register address area can be write-protected to protect
728  * against unintended modifications. This facility only protects locked bits
729  * from being modified via the SPI and will not prevent the UJA1169 updating
730  * status registers etc. For SPI write disable set lock bit to 1.
731  * This is mask for set lock control register.
732  * The following is an example of how to write to Lock control register
733  * by passing lockMask parameter to SBC_SetLock function:
734  * sbc_lock_t lockMask;
735  * lockMask = LK0C | LK1C | LK2C | LK3C | LK4C - Enable lock.
736  * lockMask &= ~(LK5C | LK6C) - Disable lock.
737  * status_t status = SBC_SetLock(lockMask);
738  *
739  * Implements : SBC_SetLock_Activity
740  *END**************************************************************************/
742 {
743  status_t status = STATUS_SUCCESS;
744  status_t spiStat = STATUS_SUCCESS;
745 
746  uint8_t regData = (uint8_t)lockMask;
747 
748  /* Send lock mask to Lock control register. */
749  spiStat = SBC_DataTransfer(SBC_UJA_LOCK, &regData, NULL);
750 
751  if(spiStat != STATUS_SUCCESS)
752  {
753  status = SBC_COMM_ERROR;
754  }
755 
756  return status;
757 }
758 
759 /*FUNCTION**********************************************************************
760  *
761  * Function Name : SBC_GetLock
762  * Description : This function reads Lock control register (0x0A).
763  * Sections of the register address area can be write-protected to protect
764  * against unintended modifications. This facility only protects locked bits
765  * from being modified via the SPI and will not prevent the UJA1169 updating
766  * status registers etc. For SPI write disable set lock bit to 1.
767  * This is mask for set lock control register.
768  * The following is an example of how to read to Lock control register
769  * by passing lockMask parameter to SBC_GetLock function:
770  * sbc_lock_t lockMask;
771  * status_t status = SBC_GetLock(lockMask);
772  *
773  * Implements : SBC_GetLock_Activity
774  *END**************************************************************************/
776 {
777  status_t status = STATUS_SUCCESS;
778  status_t spiStat = STATUS_SUCCESS;
779 
780  DEV_ASSERT(lockMask != NULL);
781 
782  uint8_t regData = 0;
783 
784  /* Read configuration from Lock control register. */
785  spiStat = SBC_DataTransfer(SBC_UJA_LOCK, NULL, &regData);
786 
787  if(spiStat == STATUS_SUCCESS)
788  {
789  *lockMask = (sbc_lock_t)(regData & SBC_UJA_LOCK_LKNC_MASK);
790  }
791 
792  if(spiStat != STATUS_SUCCESS)
793  {
794  status = SBC_COMM_ERROR;
795  }
796 
797  return status;
798 }
799 
800 /*FUNCTION**********************************************************************
801  *
802  * Function Name : SBC_SetCanConfig
803  * Description : This function configures CAN peripheral behavior.
804  * This function configures several registers which configure CAN.
805  * It contains CAN control register, Transceiver event capture enable register,
806  * CAN data rate selection, ID registers, ID mask registers,
807  * Frame control register, Data mask 0 - 7 configuration.
808  * The following is an example of how to write to CAN control registers
809  * by passing can parameter to SBC_SetCanConfig function:
810  * sbc_can_conf_t can;
811  can.canConf.cfdc = SBC_UJA_CAN_CFDC_DIS;
812  can.canTransEvnt.cbse = SBC_UJA_TRANS_EVNT_CBSE_DIS;
813  can.datRate = SBC_UJA_DAT_RATE_CDR_50KB;
814  * status_t status = SBC_SetCanConfig(&can);
815  *
816  * Implements : SBC_SetCanConfig_Activity
817  *END**************************************************************************/
819 {
820  status_t status = STATUS_SUCCESS;
821  status_t spiStat = STATUS_SUCCESS;
822 
823  DEV_ASSERT(can != NULL);
824 
825  const sbc_can_ctr_t *canC = &can->canConf;
826  uint8_t regData = (uint8_t)((uint8_t)canC->cfdc | (uint8_t)canC->pncok
827  | (uint8_t)canC->cpnc | (uint8_t)canC->cmc);
828 
829  /* Send configuration to CAN control register. */
830  spiStat = SBC_DataTransfer(SBC_UJA_CAN, &regData, NULL);
831  regData = 0U;
832 
833  if(spiStat == STATUS_SUCCESS )
834  {
835  const sbc_trans_evnt_t *tEvnt = &can->canTransEvnt;
836  /* Send configuration to Transceiver event register. */
837  regData = (uint8_t)((uint8_t)tEvnt->cbse | (uint8_t)tEvnt->cfe
838  | (uint8_t)tEvnt->cwe);
839  spiStat = SBC_DataTransfer(SBC_UJA_TRANS_EVNT, &regData, NULL);
840  regData = 0U;
841  }
842  if(spiStat == STATUS_SUCCESS )
843  {
844  /* Send configuration to CAN data rate selection. */
845  regData = can->datRate;
846  spiStat = SBC_DataTransfer(SBC_UJA_DAT_RATE, &regData, NULL);
847  }
848  if(spiStat == STATUS_SUCCESS )
849  {
850  /* Write other Can registers. */
851  spiStat = sbc_write_can_others(can);
852  }
853 
854  if(spiStat != STATUS_SUCCESS)
855  {
856  status = SBC_COMM_ERROR;
857  }
858 
859  return status;
860 }
861 
862 /*FUNCTION**********************************************************************
863  *
864  * Function Name : SBC_GetCanConfig
865  * Description : This function reads CAN peripheral settings.
866  * This function configures several registers which configure CAN.
867  * It contains CAN control register, Transceiver event capture enable register,
868  * CAN data rate selection, ID registers, ID mask registers,
869  * Frame control register, Data mask 0 - 7 configuration.
870  * The following is an example of how to read the CAN control registers
871  * by passing can parameter to SBC_GetCanConfig function:
872  * sbc_can_conf_t can;
873  * status_t status = SBC_GetCanConfig(&can);
874  *
875  * Implements : SBC_GetCanConfig_Activity
876  *END**************************************************************************/
878 {
879  status_t status = STATUS_SUCCESS;
880  status_t spiStat = STATUS_SUCCESS;
881 
882  DEV_ASSERT(can != NULL);
883 
884  sbc_can_ctr_t *canC = &can->canConf;
885  uint8_t regData = 0;
886  /* Read configuration from CAN control register. */
887  spiStat = SBC_DataTransfer(SBC_UJA_CAN, NULL, &regData);
888 
889  if(spiStat == STATUS_SUCCESS )
890  {
891  /* Set CAN control register from device. */
892  canC->cfdc = (sbc_can_cfdc_t)(regData & SBC_UJA_CAN_CFDC_MASK);
893  canC->pncok = (sbc_can_pncok_t)(regData & SBC_UJA_CAN_PNCOK_MASK);
894  canC->cpnc = (sbc_can_cpnc_t)(regData & SBC_UJA_CAN_CPNC_MASK);
895  canC->cmc = (sbc_can_cmc_t)(regData & SBC_UJA_CAN_CMC_MASK);
896 
897  sbc_trans_evnt_t *tEvnt = &can->canTransEvnt;
898  /* Read Transceiver event register. */
899  regData = 0;
900  spiStat = SBC_DataTransfer(SBC_UJA_TRANS_EVNT, NULL, &regData);
901  /* Set Transceiver event register from device. */
905  }
906 
907  if(spiStat == STATUS_SUCCESS )
908  {
909  /* Read CAN data rate. */
910  regData = 0;
911  spiStat = SBC_DataTransfer(SBC_UJA_DAT_RATE, NULL, &regData);
913  }
914 
915  if(spiStat == STATUS_SUCCESS )
916  {
917  /* Read other can configuration register. */
918  spiStat = sbc_read_can_others(can);
919  }
920 
921  if(spiStat != STATUS_SUCCESS)
922  {
923  status = SBC_COMM_ERROR;
924  }
925 
926  return status;
927 }
928 
929 /*FUNCTION**********************************************************************
930  *
931  * Function Name : SBC_SetWakePin
932  * Description : This function writes to WAKE pin event capture enable register (0x4C).
933  * Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture
934  * enable register. A wake-up event is triggered
935  * by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition
936  * on the WAKE pin. This arrangement allows for maximum flexibility when
937  * designing a local wake-up circuit. In applications that do not use the local
938  * wake-up facility, local wake-up should be disabled and the WAKE pin
939  * connected to GND.
940  * The following is an example of how to write to WAKE pin event capture enable
941  * register by passing wakePin parameter to SBC_SetWakePin function:
942  * sbc_wake_t wakePin;
943  * wakePin.wpre = SBC_UJA_WAKE_EN_WPRE_DIS;
944  * wakePin.wpfe = SBC_UJA_WAKE_EN_WPFE_DIS;
945  * status_t status = SBC_SetWakePin(&wakePin);
946  *
947  * Implements : SBC_SetWakePin_Activity
948  *END**************************************************************************/
949 status_t SBC_SetWakePin(const sbc_wake_t* const wakePin)
950 {
951  status_t status = STATUS_SUCCESS;
952  status_t spiStat = STATUS_SUCCESS;
953 
954  DEV_ASSERT(wakePin != NULL);
955 
956  uint8_t regData = (uint8_t)((uint8_t)wakePin->wpre | (uint8_t)wakePin->wpfe);
957 
958  /* Send configuration to WAKE pin event capture enable register. */
959  spiStat = SBC_DataTransfer(SBC_UJA_WAKE_EN, &regData, NULL);
960 
961  if(spiStat != STATUS_SUCCESS)
962  {
963  status = SBC_COMM_ERROR;
964  }
965 
966  return status;
967 }
968 
969 /*FUNCTION**********************************************************************
970  *
971  * Function Name : SBC_GetWakePin
972  * Description : This function reads WAKE pin event capture enable register (0x4C).
973  * Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture
974  * enable register. A wake-up event is triggered
975  * by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition
976  * on the WAKE pin. This arrangement allows for maximum flexibility when
977  * designing a local wake-up circuit. In applications that do not use the local
978  * wake-up facility, local wake-up should be disabled and the WAKE pin
979  * connected to GND.
980  * The following is an example of how to read from WAKE pin event capture enable
981  * register by passing wakePin parameter to SBC_SetWakePin function:
982  * sbc_wake_t wakePin;
983  * status_t status = SBC_GetWakePin(&wakePin);
984  *
985  * Implements : SBC_GetWakePin_Activity
986  *END**************************************************************************/
988 {
989  status_t status = STATUS_SUCCESS;
990  status_t spiStat = STATUS_SUCCESS;
991 
992  uint8_t regData = 0;
993 
994  DEV_ASSERT(wakePin != NULL);
995 
996  /* Read configuration from WAKE pin event capture enable register. */
997  spiStat = SBC_DataTransfer(SBC_UJA_WAKE_EN, NULL, &regData);
998 
999  if(spiStat == STATUS_SUCCESS)
1000  {
1001  wakePin->wpre = (sbc_wake_en_wpre_t)(regData & SBC_UJA_WAKE_EN_WPRE_MASK);
1002  wakePin->wpfe = (sbc_wake_en_wpfe_t)(regData & SBC_UJA_WAKE_EN_WPFE_MASK);
1003  }
1004 
1005  if(spiStat != STATUS_SUCCESS)
1006  {
1007  status = SBC_COMM_ERROR;
1008  }
1009 
1010  return status;
1011 }
1012 
1013 /*FUNCTION**********************************************************************
1014  *
1015  * Function Name : SBC_GetMainStatus
1016  * Description : This function reads the Main status register.
1017  * This function will clear R/W registers automatically after reading.
1018  * The following is an example of how to read Main status register.
1019  * by passing mainStatus parameter to SBC_GetMainStatus function:
1020  * sbc_main_status_t mainStatus;
1021  * status_t status = SBC_GetMainStatus(&mainStatus);
1022  *
1023  * Implements : SBC_GetMainStatus_Activity
1024  *END**************************************************************************/
1026 {
1027  status_t ujaStat = STATUS_SUCCESS;
1028  status_t spiStat = STATUS_SUCCESS;
1029 
1030  DEV_ASSERT(mainStatus != NULL);
1031 
1032  uint8_t readData = 0U;
1033  spiStat = SBC_DataTransfer(SBC_UJA_MAIN, NULL, &readData );
1034 
1035  if(spiStat == STATUS_SUCCESS)
1036  {
1037  mainStatus->otws = (sbc_main_otws_t)(readData & SBC_UJA_MAIN_OTWS_MASK);
1038  mainStatus->nms = (sbc_main_nms_t)(readData & SBC_UJA_MAIN_NMS_MASK);
1039  mainStatus->rss = (sbc_main_rss_t)(readData & SBC_UJA_MAIN_RSS_MASK);
1040  }
1041 
1042  if(spiStat != STATUS_SUCCESS)
1043  {
1044  ujaStat = SBC_COMM_ERROR;
1045  }
1046 
1047  return ujaStat;
1048 }
1049 
1050 /*FUNCTION**********************************************************************
1051  *
1052  * Function Name : SBC_GetWatchdogStatus
1053  * Description : This function read Watchdog status register.
1054  * Watchdog status register.
1055  * This function will clear R/W registers automatically after reading.
1056  * The following is an example of how to read Watchdog status register
1057  * by passing mainStatus parameter to SBC_GetMainStatus function:
1058  * sbc_wtdog_status_t watchdogStatus;
1059  * status_t status = SBC_GetWatchdogStatus(&watchdogStatus);
1060  *
1061  * Implements : SBC_GetWatchdogStatus_Activity
1062  *END**************************************************************************/
1064 {
1065  status_t ujaStat = STATUS_SUCCESS;
1066  status_t spiStat = STATUS_SUCCESS;
1067 
1068  DEV_ASSERT(watchdogStatus != NULL);
1069 
1070  uint8_t readData = 0U;
1071  spiStat = SBC_DataTransfer(SBC_UJA_WTDOG_STAT, NULL, &readData );
1072 
1073  if(spiStat == STATUS_SUCCESS)
1074  {
1075  watchdogStatus->fnms = (sbc_wtdog_stat_fnms_t)(readData & SBC_UJA_WTDOG_STAT_FNMS_MASK);
1076  watchdogStatus->sdms = (sbc_wtdog_stat_sdms_t)(readData & SBC_UJA_WTDOG_STAT_SDMS_MASK);
1077  watchdogStatus->wds = (sbc_wtdog_stat_wds_t)(readData & SBC_UJA_WTDOG_STAT_WDS_MASK);
1078  /* Clear fnnms and sdmms register. */
1079  readData &= (uint8_t)~SBC_UJA_WTDOG_STAT_FNMS_MASK;
1080  readData &= (uint8_t)~SBC_UJA_WTDOG_STAT_SDMS_MASK;
1081  spiStat = SBC_DataTransfer(SBC_UJA_WTDOG_STAT, &readData, NULL );
1082  }
1083 
1084  if(spiStat != STATUS_SUCCESS)
1085  {
1086  ujaStat = SBC_COMM_ERROR;
1087  }
1088 
1089  return ujaStat;
1090 }
1091 
1092 /*FUNCTION**********************************************************************
1093  *
1094  * Function Name : SBC_GetSupplyStatus
1095  * Description : This functions reads Supply voltage status register.
1096  * This function clear R/W status after reading writing 0 to register.
1097  * It contains V2/VEXT status and V1 status.
1098  * The following is an example of how to read Supply voltage status register
1099  * by passing supStatus parameter to SBC_GetSupplyStatus function:
1100  * sbc_supply_status_t supStatus;
1101  * status_t status = SBC_GetSupplyStatus(&supStatus);
1102  *
1103  * Implements : SBC_GetSupplyStatus_Activity
1104  *END**************************************************************************/
1106 {
1107  status_t ujaStat = STATUS_SUCCESS;
1108  status_t spiStat = STATUS_SUCCESS;
1109 
1110  DEV_ASSERT(supStatus != NULL);
1111 
1112  uint8_t readData = 0U;
1113  spiStat = SBC_DataTransfer(SBC_UJA_SUPPLY_STAT, NULL, &readData );
1114 
1115  if(spiStat == STATUS_SUCCESS)
1116  {
1117  supStatus->v2s = (sbc_supply_stat_v2s_t)(readData & SBC_UJA_SUPPLY_STAT_V2S_MASK);
1118  supStatus->v1s = (sbc_supply_stat_v1s_t)(readData & SBC_UJA_SUPPLY_STAT_V1S_MASK);
1119  /* Clear Supply status. */
1120  readData &= (uint8_t)~SBC_UJA_SUPPLY_STAT_V2S_MASK;
1121  readData &= (uint8_t)~SBC_UJA_SUPPLY_STAT_V1S_MASK;
1122  spiStat = SBC_DataTransfer(SBC_UJA_SUPPLY_STAT, &readData, NULL );
1123  }
1124 
1125  if(spiStat != STATUS_SUCCESS)
1126  {
1127  ujaStat = SBC_COMM_ERROR;
1128  }
1129 
1130  return ujaStat;
1131 }
1132 
1133 /*FUNCTION**********************************************************************
1134  *
1135  * Function Name : SBC_GetCanStatus
1136  * Description : This functions reads Transceiver status register.
1137  * It contains CAN transceiver status, CAN partial networking error,
1138  * CAN partial networking status, CAN oscillator status, CAN-bus silence status,
1139  * VCAN status, CAN failure status.
1140  * The following is an example of how to read Transceiver status register
1141  * by passing transStatus parameter to SBC_GetCanStatus function:
1142  * sbc_trans_stat_t transStatus;
1143  * status_t status = SBC_GetCanStatus(&supStatus);
1144  *
1145  * Implements : SBC_GetCanStatus_Activity
1146  *END**************************************************************************/
1148 {
1149  status_t ujaStat = STATUS_SUCCESS;
1150  status_t spiStat = STATUS_SUCCESS;
1151 
1152  uint8_t readData = 0U;
1153  DEV_ASSERT(transStatus != NULL);
1154 
1155  spiStat = SBC_DataTransfer(SBC_UJA_TRANS_STAT, NULL, &readData );
1156 
1157  if(spiStat == STATUS_SUCCESS)
1158  {
1159  transStatus->cts = (sbc_trans_stat_cts_t)(readData & SBC_UJA_TRANS_STAT_CTS_MASK);
1160  transStatus->cpnerr = (sbc_trans_stat_cpnerr_t)(readData & SBC_UJA_TRANS_STAT_CPNERR_MASK);
1161  transStatus->cpns = (sbc_trans_stat_cpns_t)(readData & SBC_UJA_TRANS_STAT_CPNS_MASK);
1162  transStatus->coscs = (sbc_trans_stat_coscs_t)(readData & SBC_UJA_TRANS_STAT_COSCS_MASK);
1163  transStatus->cbss = (sbc_trans_stat_cbss_t)(readData & SBC_UJA_TRANS_STAT_CBSS_MASK);
1164  transStatus->vcs = (sbc_trans_stat_vcs_t)(readData & SBC_UJA_TRANS_STAT_VCS_MASK);
1165  transStatus->cfs = (sbc_trans_stat_cfs_t)(readData & SBC_UJA_TRANS_STAT_CFS_MASK);
1166  }
1167 
1168  if(spiStat != STATUS_SUCCESS)
1169  {
1170  ujaStat = SBC_COMM_ERROR;
1171  }
1172 
1173  return ujaStat;
1174 }
1175 
1176 /*FUNCTION**********************************************************************
1177  *
1178  * Function Name : SBC_GetWakeStatus
1179  * Description : This functions reads WAKE pin status register.
1180  * This function reads switching threshold of voltage on WAKE pin.
1181  * The following is an example of how to read WAKE pin status register
1182  * by passing wakeStatus parameter to SBC_GetWakeStatus function:
1183  * sbc_wake_stat_wpvs_t wakeStatus;
1184  * status_t status = SBC_GetWakeStatus(&wakeStatus);
1185  *
1186  * Implements : SBC_GetWakeStatus_Activity
1187  *END**************************************************************************/
1189 {
1190  status_t ujaStat = STATUS_SUCCESS;
1191  status_t spiStat = STATUS_SUCCESS;
1192 
1193  DEV_ASSERT(wakeStatus != NULL);
1194 
1195  uint8_t readData = 0U;
1196  spiStat = SBC_DataTransfer(SBC_UJA_WAKE_STAT, NULL, &readData );
1197 
1198  if(spiStat == STATUS_SUCCESS)
1199  {
1200  *wakeStatus = (sbc_wake_stat_wpvs_t)(readData & SBC_UJA_WAKE_STAT_WPVS_MASK);
1201  }
1202 
1203  if(spiStat != STATUS_SUCCESS)
1204  {
1205  ujaStat = SBC_COMM_ERROR;
1206  }
1207 
1208  return ujaStat;
1209 }
1210 
1211 /*FUNCTION**********************************************************************
1212  *
1213  * Function Name : SBC_GetEventsStatus
1214  * Description : This functions reads Event capture registers.
1215  * This functions reads global events statuses: Global event status,
1216  * System event status, Supply event status, Transceiver event status,
1217  * WAKE pin event status.
1218  * The following is an example of how to read WAKE pin status register
1219  * by passing events parameter to SBC_GetEventsStatus function:
1220  * sbc_evn_capt_t events;
1221  * status_t status = SBC_GetEventsStatus(&events);
1222  *
1223  * Implements : SBC_GetEventsStatus_Activity
1224  *END**************************************************************************/
1226 {
1227  status_t ujaStat = STATUS_SUCCESS;
1228  status_t spiStat = STATUS_SUCCESS;
1229 
1230  DEV_ASSERT(events != NULL);
1231 
1232  /* Clean events statuses structure. */
1233  sbc_clean_events_status(events);
1234  /* Global event status. */
1235  uint8_t readData = 0U;
1236  spiStat = SBC_DataTransfer(SBC_UJA_GL_EVNT_STAT, NULL, &readData );
1237 
1238  sbc_gl_evnt_stat_t* glEvent = &events->glEvnt;
1239 
1240  if(spiStat == STATUS_SUCCESS)
1241  {
1242  glEvent->wpe = (sbc_gl_evnt_stat_wpe_t)(readData & SBC_UJA_GL_EVNT_STAT_WPE_MASK);
1246  }
1247 
1248  /* System event status. */
1249  readData = 0;
1250  /* Test if System event occurred. */
1251  if(glEvent->syse == SBC_UJA_GL_EVNT_STAT_SYSE)
1252  {
1253  spiStat = SBC_DataTransfer(SBC_UJA_SYS_EVNT_STAT, NULL, &readData );
1254  if(spiStat == STATUS_SUCCESS)
1255  {
1256  sbc_sys_evnt_stat_t* sysEvent = &events->sysEvnt;
1257  sysEvent->po = (sbc_sys_evnt_stat_po_t)(readData & SBC_UJA_SYS_EVNT_STAT_PO_MASK);
1261  }
1262  }
1263  /* Supply event status. */
1264  readData = 0;
1265  /* Test if Supply event occurred. */
1266  if(glEvent->supe == SBC_UJA_GL_EVNT_STAT_SUPE)
1267  {
1268  spiStat = SBC_DataTransfer(SBC_UJA_SUP_EVNT_STAT, NULL, &readData );
1269  if(spiStat == STATUS_SUCCESS)
1270  {
1271  sbc_sup_evnt_stat_t* supEvent = &events->supEvnt;
1275  }
1276  }
1277 
1278  /* Transceiver event status. */
1279  readData = 0;
1280  /* Test if Transceiver event occurred. */
1281  if(glEvent->trxe == SBC_UJA_GL_EVNT_STAT_TRXE)
1282  {
1283  spiStat = SBC_DataTransfer(SBC_UJA_TRANS_EVNT_STAT, NULL, &readData );
1284  if(spiStat == STATUS_SUCCESS)
1285  {
1286  sbc_trans_evnt_stat_t* transEvent = &events->transEvnt;
1289  transEvent->cf = (sbc_trans_evnt_stat_cf_t)(readData & SBC_UJA_TRANS_EVNT_STAT_CF_MASK);
1290  transEvent->cw = (sbc_trans_evnt_stat_cw_t)(readData & SBC_UJA_TRANS_EVNT_STAT_CW_MASK);
1291  }
1292  }
1293 
1294  /* WAKE pin event status. */
1295  readData = 0;
1296  /* Test if WAKE pin event occurred. */
1297  if(glEvent->wpe == SBC_UJA_GL_EVNT_STAT_WPE)
1298  {
1299  spiStat = SBC_DataTransfer(SBC_UJA_WAKE_EVNT_STAT, NULL, &readData );
1300  if(spiStat == STATUS_SUCCESS)
1301  {
1302  sbc_wake_evnt_stat_t* wakeEvent = &events->wakePinEvnt;
1305  }
1306  }
1307 
1308  if(spiStat != STATUS_SUCCESS)
1309  {
1310  ujaStat = SBC_COMM_ERROR;
1311  }
1312 
1313  return ujaStat;
1314 }
1315 
1316 /*FUNCTION**********************************************************************
1317  *
1318  * Function Name : SBC_CleanEvents
1319  * Description : This function clears Event capture registers.
1320  * It contains Global event status, System event status, Supply event status,
1321  * Transceiver event status, WAKE pin event status.
1322  * This function write 1 to bit which should be delete.
1323  * After an event source has been identified, the status flag should be cleared
1324  * (set to 0) by writing 1 to the relevant status bit
1325  * (writing 0 will have no effect). Write true value to appropriate enumeration.
1326  * The following is an example of how to read from WAKE pin event capture enable
1327  * register by passing events parameter to SBC_CleanEvents function
1328  * (Global event status does not have effect to clearing statuses):
1329  * sbc_evn_capt_t events;
1330  * events.sysEvnt.po = SBC_UJA_SYS_EVNT_STAT_PO;
1331  * events.sysEvnt.otw = SBC_UJA_SYS_EVNT_STAT_OTW;
1332  * events.sysEvnt.spif = SBC_UJA_SYS_EVNT_STAT_SPIF;
1333  * events.sysEvnt.wdf = SBC_UJA_SYS_EVNT_STAT_WDF;
1334  *
1335  * events.supEvnt.v1u = SBC_UJA_SUP_EVNT_STAT_V1U;
1336  * events.supEvnt.v2u = SBC_UJA_SUP_EVNT_STAT_V2U;
1337  * events.supEvnt.v2o = SBC_UJA_SUP_EVNT_STAT_V2O;
1338  * status_t status = SBC_CleanEvents(&events);
1339  *
1340  * Implements : SBC_CleanEvents_Activity
1341  *END**************************************************************************/
1343 {
1344 
1345  status_t ujaStat = STATUS_SUCCESS;
1346  status_t spiStat = STATUS_SUCCESS;
1347  uint8_t clearMask = 0;
1348 
1349  DEV_ASSERT(events != NULL);
1350 
1351  const sbc_gl_evnt_stat_t* glEvents = &events->glEvnt;
1352 
1353  /* Clear global events. */
1354  clearMask = (uint8_t)((uint8_t)glEvents->supe | (uint8_t)glEvents->syse
1355  | (uint8_t)glEvents->trxe | (uint8_t)glEvents->wpe);
1356  spiStat = SBC_DataTransfer(SBC_UJA_GL_EVNT_STAT, &clearMask, NULL);
1357  ujaStat = (status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1358  const sbc_sys_evnt_stat_t* sysEvents = &events->sysEvnt;
1359 
1360  /* Clear system events. */
1361  clearMask = (uint8_t)((uint8_t)sysEvents->otw | (uint8_t)sysEvents->po
1362  | (uint8_t)sysEvents->spif | (uint8_t)sysEvents->wdf);
1363  spiStat = SBC_DataTransfer(SBC_UJA_SYS_EVNT_STAT, &clearMask, NULL);
1364  ujaStat = (status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1365  const sbc_sup_evnt_stat_t* supEvents = &events->supEvnt;
1366 
1367  /* Clear supply events. */
1368  clearMask = (uint8_t)((uint8_t)supEvents->v1u | (uint8_t)supEvents->v2o
1369  | (uint8_t)supEvents->v2u);
1370  spiStat = SBC_DataTransfer(SBC_UJA_SUP_EVNT_STAT, &clearMask, NULL);
1371  ujaStat = (status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1372  const sbc_trans_evnt_stat_t* transEvents = &events->transEvnt;
1373 
1374  /* Clear transfer events. */
1375  clearMask = (uint8_t)( (uint8_t)transEvents->cbs | (uint8_t)transEvents->cf
1376  | (uint8_t)transEvents->cw | (uint8_t)transEvents->pnfde);
1377  spiStat = SBC_DataTransfer(SBC_UJA_TRANS_EVNT_STAT, &clearMask, NULL);
1378  ujaStat = (status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1379  const sbc_wake_evnt_stat_t* wakeEvent = &events->wakePinEvnt;
1380 
1381  /* Clear wake up events. */
1382  clearMask = (uint8_t)((uint8_t)wakeEvent->wpf | (uint8_t)wakeEvent->wpr);
1383  spiStat = SBC_DataTransfer(SBC_UJA_WAKE_EVNT_STAT, &clearMask, NULL);
1384  ujaStat = (status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1385 
1386  if(ujaStat != STATUS_SUCCESS)
1387  {
1388  ujaStat = SBC_COMM_ERROR;
1389  }
1390 
1391  return ujaStat;
1392 
1393 }
1394 
1395 /*FUNCTION**********************************************************************
1396  *
1397  * Function Name : SBC_GetAllStatus
1398  * Description : This function reads all statuses from SBC device.
1399  * It reads all status registers: Main status and Watchdog status,
1400  * Supply voltage status, Transceiver status, WAKE pin status,
1401  * Event capture registers.
1402  *
1403  * The following is an example of how to read all registers by passing status
1404  * parameter to SBC_GetAllStatus function:
1405  * sbc_status_group_t status;
1406  * status_t status = SBC_GetAllStatus(&events);
1407  *
1408  * Implements : SBC_GetAllStatus_Activity
1409  *END**************************************************************************/
1411 {
1412  status_t ujaStat = STATUS_SUCCESS;
1413 
1414  DEV_ASSERT(status != NULL);
1415 
1416  ujaStat = SBC_GetMainStatus(&status->mainS);
1417 
1418  if(ujaStat == STATUS_SUCCESS)
1419  {
1420  ujaStat = SBC_GetWatchdogStatus(&status->wtdog);
1421  }
1422 
1423  if(ujaStat == STATUS_SUCCESS)
1424  {
1425  ujaStat = SBC_GetSupplyStatus(&status->supply);
1426  }
1427 
1428  if(ujaStat == STATUS_SUCCESS)
1429  {
1430  ujaStat = SBC_GetCanStatus(&status->trans);
1431  }
1432 
1433  if(ujaStat == STATUS_SUCCESS)
1434  {
1435  ujaStat = SBC_GetWakeStatus(&status->wakePin);
1436  }
1437 
1438  if(ujaStat == STATUS_SUCCESS)
1439  {
1440  ujaStat = SBC_GetEventsStatus(&status->events);
1441  }
1442 
1443  return ujaStat;
1444 }
1445 
1446 /*FUNCTION**********************************************************************
1447  *
1448  * Function Name : SBC_GetMtpnvStatus
1449  * Description : This function reads MTPNV status register.
1450  * The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP).
1451  * Bit NVMPS in the MTPNV status register indicates
1452  * whether the non-volatile cells can be reprogrammed. This register also
1453  * contains a write counter, WRCNTS, that is incremented each time the
1454  * MTPNV cells are reprogrammed (up to a maximum value of 111111; there is
1455  * no overflow; performing a factory reset also increments the counter).
1456  * This counter is provided for information purposes only; reprogramming will
1457  * not be rejected when it reaches its maximum value.
1458  *
1459  * The following is an example of how to read all registers by passing mtpnv
1460  * parameter to SBC_GetMtpnvStatus function:
1461  * sbc_status_group_t status;
1462  * status_t status = SBC_GetMtpnvStatus(&events);
1463  *
1464  * Implements : SBC_GetMtpnvStatus_Activity
1465  *END**************************************************************************/
1467 {
1468  status_t ujaStat = STATUS_SUCCESS;
1469  status_t spiStat = STATUS_SUCCESS;
1470 
1471  DEV_ASSERT(mtpnv != NULL);
1472 
1473  uint8_t readData = 0U;
1474  spiStat = SBC_DataTransfer(SBC_UJA_MTPNV_STAT, NULL, &readData);
1475 
1476  if(spiStat == STATUS_SUCCESS)
1477  {
1481  }
1482 
1483  if(spiStat != STATUS_SUCCESS)
1484  {
1485  ujaStat = SBC_COMM_ERROR;
1486  }
1487 
1488  return ujaStat;
1489 }
1490 
1491 /*FUNCTION**********************************************************************
1492  *
1493  * Function Name : SBC_GetFactoriesSettings
1494  * Description : This function reads Start-up control register and
1495  * SBC configuration control register.
1496  * It is non-volatile memory with limited write access.
1497  * The UJA1169 contains Multiple Time Programmable Non-Volatile
1498  * (MTPNV) memory cells that allow some of the default device settings
1499  * to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74.
1500  * NXP delivers the UJA1169 in so-called Forced Normal mode,
1501  * also referred to as the factory preset configuration. In order
1502  * to change the default settings, the device must be in Forced Normal mode
1503  * with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled,
1504  * all regulators are on and the CAN transceiver is in Active mode.
1505  *
1506  * The following is an example of how to read Start-up control register and
1507  * SBC configuration control register by passing factoriesConf
1508  * parameter to SBC_GetFactoriesSettings function:
1509  * sbc_factories_conf_t factoriesConf;
1510  * status_t status = SBC_GetFactoriesSettings(&factoriesConf);
1511  *
1512  * Implements : SBC_GetFactoriesSettings_Activity
1513  *END**************************************************************************/
1515 {
1516  status_t ujaStat = STATUS_SUCCESS;
1517  status_t spiStat = STATUS_SUCCESS;
1518 
1519  DEV_ASSERT(factoriesConf != NULL);
1520 
1521  /* Read Start-up control register. */
1522  uint8_t readData = 0U;
1523  spiStat = SBC_DataTransfer(SBC_UJA_START_UP, NULL, &readData);
1524 
1525  if(spiStat == STATUS_SUCCESS)
1526  {
1527  sbc_start_up_t* startUp = &factoriesConf->startUp;
1528  startUp->rlc = (sbc_start_up_rlc_t)(readData & SBC_UJA_START_UP_RLC_MASK);
1529  startUp->v2suc = (sbc_start_up_v2suc_t)(readData & SBC_UJA_START_UP_V2SUC_MASK);
1530  readData = 0;
1531  spiStat = SBC_DataTransfer(SBC_UJA_SBC, NULL, &readData);
1532  }
1533 
1534  if(spiStat == STATUS_SUCCESS)
1535  {
1536  sbc_sbc_t* sbc = &factoriesConf->control;
1537  sbc->v1rtsuc = (sbc_sbc_v1rtsuc_t)(readData & SBC_UJA_SBC_V1RTSUC_MASK);
1538  sbc->fnmc = (sbc_sbc_fnmc_t)(readData & SBC_UJA_SBC_FNMC_MASK);
1539  sbc->sdmc = (sbc_sbc_sdmc_t)(readData & SBC_UJA_SBC_SDMC_MASK);
1540  sbc->slpc = (sbc_sbc_slpc_t)(readData & SBC_UJA_SBC_SLPC_MASK);
1541  }
1542 
1543  if(spiStat != STATUS_SUCCESS)
1544  {
1545  ujaStat = SBC_COMM_ERROR;
1546  }
1547 
1548  return ujaStat;
1549 }
1550 
1551 /*FUNCTION**********************************************************************
1552  *
1553  * Function Name : SBC_ChangeFactoriesSettings
1554  * Description : This function sets Start-up control register and
1555  * SBC configuration control register.
1556  * It is non-volatile memory with limited write access.
1557  * The UJA1169 contains Multiple Time Programmable Non-Volatile
1558  * (MTPNV) memory cells that allow some of the default device settings
1559  * to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74.
1560  * NXP delivers the UJA1169 in so-called Forced Normal mode,
1561  * also referred to as the factory preset configuration. In order
1562  * to change the default settings, the device must be in Forced Normal mode
1563  * with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled,
1564  * all regulators are on and the CAN transceiver is in Active mode.
1565  * Note for default settings see sbc_factories_conf_t comment.
1566  * If the device has been programmed previously, the factory presets may need
1567  * to be restored before reprogramming can begin. When the factory presets
1568  * have been restored successfully, a system reset is generated automatically
1569  * and UJA1169 switches back to Forced Normal mode.
1570  * Factory preset values are restored if the following conditions apply
1571  * continuously for at least td(MTPNV) during battery power-up:
1572  * -pin RSTN is held LOW
1573  * -CANH is pulled up to VBAT
1574  * -CANL is pulled down to GND
1575  *
1576  * The following is an example of how to write Start-up control register and
1577  * SBC configuration control register by passing parameter
1578  * to SBC_ChangeFactoriesSettings function:
1579  * sbc_factories_conf_t newConf;
1580  * status_t status = SBC_ChangeFactoriesSettings(&newConf);
1581  *
1582  * Implements : SBC_ChangeFactoriesSettings_Activity
1583  *END**************************************************************************/
1585 {
1586  status_t ujaStat = STATUS_SUCCESS;
1587  /* Read if writing is possible. */
1588  sbc_mtpnv_stat_t mtvnStatus;
1589 
1590  DEV_ASSERT(newConf != NULL);
1591 
1592  ujaStat = SBC_GetMtpnvStatus(&mtvnStatus);
1593 
1594  if((ujaStat == STATUS_SUCCESS) && (mtvnStatus.eccs == SBC_UJA_MTPNV_STAT_ECCS_NO)
1595  && (mtvnStatus.nvmps == SBC_UJA_MTPNV_STAT_NVMPS))
1596  {
1597  ujaStat = sbc_change_factories_direct(newConf);
1598  OSIF_TimeDelay(1);
1599  }
1600  else
1601  {
1602  if(ujaStat == STATUS_SUCCESS)
1603  {
1604  ujaStat = SBC_NVN_ERROR;
1605  }
1606  }
1607 
1608  return ujaStat;
1609 }
1610 /*FUNCTION**********************************************************************
1611  *
1612  * Function Name : SBC_DataTransfer
1613  * Description : This function sends data over LSPI to SBC device.
1614  * This function send 8 bites to SBC device register according device address
1615  * which is selected. This transfer uses 16bit LSPI. CS polarity - active low,
1616  * clock phase on second edge. Clock polarity active high.
1617  *
1618  * The following is an example of how to send data to SBC device by passing
1619  * sendData parameter to SBC_DataTransfer function:
1620  * uint8_t sendData = wtdog->modeControl | wtdog->nominalPeriod;
1621  * status_t status = SBC_DataTransfer(SBC_UJA_WTDOG_CTR, &sendData, NULL);
1622  *
1623  * The following is an example of how to read data to SBC device by passing
1624  * sendData parameter to SBC_DataTransfer function:
1625  * uint8_t receiveData = 0;
1626  * status_t status = SBC_DataTransfer(SBC_UJA_WTDOG_CTR, NULL, &receiveData);
1627  *
1628  * Implements : SBC_DataTransfer_Activity
1629  *END**************************************************************************/
1631  const uint8_t* const sendData, uint8_t* const receiveData)
1632 {
1633 
1634  status_t status = STATUS_SUCCESS;
1635 
1636  uint8_t command[2] = {0U, 0U};
1637  uint8_t readOnlyMask = 0x00U;
1638  uint8_t readData[2] = {0U, 0U};
1639 
1640  /* Test if there is data for sending. */
1641  if(sendData == NULL)
1642  {
1643  /* This transfer is read only. */
1644  readOnlyMask = 0x01U;
1645  command[0] = 0U;
1646  }
1647  else
1648  {
1649  command[0] = *sendData;
1650  }
1651 
1652  /* Address of device with read only bit. */
1653  command[1] = (uint8_t)((SBC_UJA_REG_ADDR_F(regName) | readOnlyMask) & 0xFFU);
1654 
1655  status = LPSPI_DRV_MasterTransferBlocking(g_drvConfig.lpspiIntace, command,
1656  readData, 2U, SBC_UJA_TIMEOUT );
1657 
1658  if( readData[1] != command[1])
1659  {
1660  status = SBC_COMM_ERROR;
1661  }
1662 
1663  /* Copy content of register to receive data. */
1664  if(receiveData != NULL)
1665  {
1666  *receiveData = readData[0];
1667  }
1668 
1669  return status;
1670 }
1671 
1672 /*FUNCTION**********************************************************************
1673  *
1674  * Function Name : sbc_write_can_others
1675  * Description : This function is internal function. It is not accessible outside
1676  * this file. This function writes to ID registers, ID mask registers, Frame
1677  * control register and Data mask registers.
1678  *
1679  *END**************************************************************************/
1681 {
1682  status_t spiStat = STATUS_SUCCESS;
1683  uint8_t i;
1684  uint8_t regData = 0;
1685  for(i=0; i< SBC_UJA_COUNT_DMASK; i++)
1686  {
1687  if(i < SBC_UJA_COUNT_ID_REG)
1688  {
1689  /* Set ID registers. */
1690  spiStat = SBC_DataTransfer((sbc_register_t)( (uint8_t)SBC_UJA_IDENTIF_0 + i),
1691  &can->identif[i], NULL);
1692  /* Set ID mask registers. */
1693 
1694  if(spiStat == STATUS_SUCCESS)
1695  {
1696  spiStat = SBC_DataTransfer((sbc_register_t)(
1697  (uint8_t)SBC_UJA_MASK_0 + i),&can->mask[i], NULL);
1698  }
1699 
1700  }
1701 
1702  /* Set Data mask registers. */
1703  if(spiStat == STATUS_SUCCESS)
1704  {
1705  spiStat = SBC_DataTransfer((sbc_register_t)(
1706  (uint8_t)SBC_UJA_DAT_MASK_0 + i),&can->dataMask[i], NULL);
1707  }
1708 
1709  }
1710 
1711  if(spiStat == STATUS_SUCCESS)
1712  {
1713  /* Set configuration to Frame control register. */
1714  const sbc_frame_t* const frame = &can->frame;
1715  regData = (uint8_t)( (uint8_t)frame->ide | (uint8_t)frame->pndm |
1716  (uint8_t)frame->dlc);
1717  spiStat = SBC_DataTransfer(SBC_UJA_FRAME_CTR, &regData, NULL);
1718  }
1719 
1720  return spiStat;
1721 }
1722 
1723 /*FUNCTION**********************************************************************
1724  *
1725  * Function Name : sbc_read_can_others
1726  * Description : This function is internal function. It is not accessible outside
1727  * this file. This function reads to ID registers, ID mask registers, Frame
1728  * control register and Data mask registers.
1729  *
1730  *END**************************************************************************/
1732 {
1733  status_t spiStat = STATUS_SUCCESS;
1734  uint8_t i;
1735  uint8_t regData = 0;
1736  for(i=0; i< SBC_UJA_COUNT_DMASK; i++)
1737  {
1738  if(i < SBC_UJA_COUNT_ID_REG)
1739  {
1740  /* Read ID registers. */
1741  regData = 0;
1742  spiStat = SBC_DataTransfer((sbc_register_t)( (uint8_t)SBC_UJA_IDENTIF_0 + i), NULL, &regData);
1743  can->identif[i] = (sbc_identifier_t)(regData & SBC_UJA_IDENTIF_X_MASK);
1744  /* Read ID mask registers. */
1745  regData = 0;
1746 
1747  if(spiStat == STATUS_SUCCESS)
1748  {
1749  spiStat = SBC_DataTransfer((sbc_register_t)(
1750  (uint8_t)SBC_UJA_MASK_0 + i), NULL, &regData);
1751  can->mask[i] = (sbc_identif_mask_t)(regData & SBC_UJA_MASK_X_MASK);
1752  }
1753 
1754  }
1755 
1756  /* Read Data mask registers. */
1757  regData = 0;
1758 
1759  if(spiStat == STATUS_SUCCESS)
1760  {
1761  spiStat = SBC_DataTransfer((sbc_register_t)(
1762  (uint8_t)SBC_UJA_DAT_MASK_0 + i), NULL, &regData);
1763  can->dataMask[i] = (sbc_data_mask_t)(regData & SBC_UJA_DATA_MASK_X_MASK);
1764  }
1765 
1766  }
1767 
1768  if(spiStat == STATUS_SUCCESS)
1769  {
1770  /* Read Frame control register. */
1771  regData = 0;
1772  sbc_frame_t* frame = &can->frame;
1773  spiStat = SBC_DataTransfer(SBC_UJA_FRAME_CTR, NULL, &regData);
1774  frame->ide = (sbc_frame_ctr_ide_t)(regData & SBC_UJA_FRAME_CTR_IDE_MASK);
1776  frame->dlc = (sbc_frame_ctr_dlc_t)(regData & SBC_UJA_FRAME_CTR_DLC_MASK);
1777  }
1778 
1779  return spiStat;
1780 }
1781 
1782 /*FUNCTION**********************************************************************
1783  *
1784  * Function Name : sbc_clean_events_status
1785  * Description : This function is internal function. It is not accessible outside
1786  * this file. This function clean event status structure to 0
1787  *
1788  *END**************************************************************************/
1790 {
1791  /* Clean system events status. */
1792  event->sysEvnt.po = (sbc_sys_evnt_stat_po_t)0U;
1793  event->sysEvnt.otw = (sbc_sys_evnt_stat_otw_t)0U;
1794  event->sysEvnt.spif = (sbc_sys_evnt_stat_spif_t)0U;
1795  event->sysEvnt.wdf = (sbc_sys_evnt_stat_wdf_t)0U;
1796  /* Clean supply events status. */
1797  event->supEvnt.v2o = (sbc_sup_evnt_stat_v2o_t)0U;
1798  event->supEvnt.v2u = (sbc_sup_evnt_stat_v2u_t)0U;
1799  event->supEvnt.v1u = (sbc_sup_evnt_stat_v1u_t)0U;
1800  /* Clean trans. events status. */
1801  event->transEvnt.pnfde = (sbc_trans_evnt_stat_pnfde_t)0U;
1802  event->transEvnt.cbs = (sbc_trans_evnt_stat_cbs_t)0U;
1803  event->transEvnt.cf = (sbc_trans_evnt_stat_cf_t)0U;
1804  event->transEvnt.cw = (sbc_trans_evnt_stat_cw_t)0U;
1805  /* Clean wake pin events status. */
1806  event->wakePinEvnt.wpr = (sbc_wake_evnt_stat_wpr_t)0U;
1807  event->wakePinEvnt.wpf = (sbc_wake_evnt_stat_wpf_t)0U;
1808 }
1809 
1810 /*FUNCTION**********************************************************************
1811  *
1812  * Function Name : sbc_get_factories_crc
1813  * Description : This function is internal function. It is not accessible outside
1814  * this file. It return CRC of factories settings - Start-up control register
1815  * and SBC configuration control register.
1816  *
1817  *END**************************************************************************/
1818 static uint8_t sbc_get_factories_crc(uint8_t* data)
1819 {
1820  uint8_t crc = 0xFF, i,j;
1821 
1822  for(i = 0; i<= 1U; i++ )
1823  {
1824  data[i] = (uint8_t)(data[i] ^ crc);
1825  for(j = 0; j<=7U; j++)
1826  {
1827  if(data[i] >= 128U)
1828  {
1829  data[i] = (uint8_t)( (uint8_t)data[i] << 1U);
1830  data[i] = (uint8_t)(data[i] ^ 0x2FU);
1831  }
1832  else
1833  {
1834  data[i] = (uint8_t)(data[i] << 1U);
1835  }
1836  }
1837  crc = data[i];
1838  }
1839  crc = (uint8_t)(crc ^ 0xFFU);
1840  return crc;
1841 }
1842 
1843 /*FUNCTION**********************************************************************
1844  *
1845  * Function Name : sbc_change_factories_direct
1846  * Description : This function is internal function. It is not accessible outside
1847  * this file. This function tries to set Start-up control register and
1848  * SBC configuration control register without checking if it is possible.
1849  * Check must be done before.
1850  *
1851  *END**************************************************************************/
1853 {
1854  status_t ujaStat = STATUS_SUCCESS;
1855  uint8_t sendData[2] = {0, 0};
1856 
1857  DEV_ASSERT(factory != NULL);
1858 
1859  sendData[0] = (uint8_t)((uint8_t)factory->startUp.rlc | (uint8_t)factory->startUp.v2suc);
1860  ujaStat = SBC_DataTransfer(SBC_UJA_START_UP, &sendData[0], NULL);
1861 
1862  if(ujaStat == STATUS_SUCCESS)
1863  {
1864  const sbc_sbc_t* ctrl = &factory->control;
1865  sendData[1] = (uint8_t)((uint8_t)ctrl->v1rtsuc | (uint8_t)ctrl->fnmc |
1866  (uint8_t)ctrl->sdmc | (uint8_t)ctrl->slpc);
1867  ujaStat = SBC_DataTransfer(SBC_UJA_SBC, &sendData[1], NULL);
1868  }
1869 
1870  if(ujaStat == STATUS_SUCCESS)
1871  {
1872  uint8_t crc = sbc_get_factories_crc(sendData);
1873  ujaStat = SBC_DataTransfer(SBC_UJA_MTPNV_CRC, &crc, NULL);
1874  }
1875 
1876  return ujaStat;
1877 }
#define SBC_UJA_SYS_EVNT_STAT_WDF_MASK
System event status register, watchdog failure macros.
Definition: UJA1169.h:702
sbc_wake_en_wpre_t
WAKE pin event capture enable register, WAKE pin rising-edge enable (0x4C).
status_t SBC_GetWatchdog(sbc_wtdog_ctr_t *const wtdog)
This function reads Watchdog control register (0x00).
Init configuration structure. This structure is used for initialization of sbc.
#define SBC_UJA_COUNT_ID_REG
#define SBC_UJA_TRANS_STAT_CPNS_MASK
Transceiver status register, CAN partial networking status macros.
Definition: UJA1169.h:385
Main status register structure. The Main status register can be accessed to monitor the status of the...
#define SBC_UJA_TRANS_STAT_COSCS_MASK
Transceiver status register, CAN oscillator status macros.
Definition: UJA1169.h:392
sbc_fail_safe_lhc_t
Fail-safe control register, LIMP home control (0x02). The dedicated LIMP pin can be used to enable so...
sbc_mode_mc_t
Mode control register, mode control (0x01)
#define SBC_UJA_START_UP_V2SUC_MASK
Start-up control register, V2/VEXT start-up control macros.
Definition: UJA1169.h:840
sbc_sys_evnt_otwe_t
System event capture enable, overtemperature warning enable (0x04).
status_t SBC_GetFailSafe(sbc_fail_safe_lhc_t *const lhc, sbc_fail_safe_rcc_t *const rcc)
This function reads from Fail-safe control register (0x02). The dedicated LIMP pin can be used to ena...
sbc_sup_evnt_stat_t supEvnt
sbc_gl_evnt_stat_trxe_t trxe
sbc_main_otws_t otws
sbc_trans_evnt_cfe_t
Transceiver event capture enable register, CAN failure enable (0x23).
sbc_data_mask_t dataMask[SBC_UJA_COUNT_DMASK]
sbc_wake_stat_wpvs_t wakePin
sbc_mtpnv_stat_nvmps_t nvmps
sbc_dat_rate_t
Data rate register, CAN data rate selection (0x26). CAN partial networking configuration registers...
#define SBC_UJA_TRANS_EVNT_STAT_CBS_MASK
Transceiver event status register, CAN-bus status macros.
Definition: UJA1169.h:754
sbc_trans_evnt_stat_pnfde_t pnfde
#define SBC_UJA_WTDOG_CTR_WMC_MASK
Watchdog mode control, watchdog mode control macros.
Definition: UJA1169.h:55
sbc_supply_evnt_t supplyEvnt
#define SBC_UJA_SYS_EVNT_STAT_OTW_MASK
System event status register, overtemperature warning macros.
Definition: UJA1169.h:688
sbc_sys_evnt_stat_po_t po
sbc_trans_stat_cbss_t
Transceiver status register, CAN-bus silence status (0x22).
sbc_trans_stat_coscs_t
Transceiver status register, CAN oscillator status (0x22).
sbc_start_up_v2suc_t v2suc
sbc_sys_evnt_stat_po_t
System event status register, power-on (0x61).
status_t SBC_SetSystemEvents(const sbc_sys_evnt_t *const sysEvnt)
This function writes System event capture enable register (0x04). This function enables or disables o...
#define SBC_UJA_FAIL_SAFE_RCC_MASK
Fail-safe control register, reset counter control macros.
Definition: UJA1169.h:97
sbc_can_cpnc_t cpnc
sbc_regulator_v2c_t
Regulator control register, V2/VEXT configuration (0x10).
sbc_wake_en_wpfe_t
WAKE pin event capture enable register, WAKE pin falling-edge enable (0x4C).
#define SBC_UJA_MAIN_OTWS_MASK
Main status register, Overtemperature warning status macros.
Definition: UJA1169.h:111
#define SBC_UJA_SBC_SDMC_MASK
SBC configuration control register, Software Development mode control macros.
Definition: UJA1169.h:871
sbc_wtdog_stat_sdms_t sdms
Transceiver status register structure. There are stored CAN transceiver statuses. ...
sbc_main_nms_t
Main status register, normal mode status (0x03).
void OSIF_TimeDelay(const uint32_t delay)
Delays execution for a number of milliseconds.
status_t SBC_SetCanConfig(const sbc_can_conf_t *const can)
This function configures CAN peripheral behavior. This function configures CAN peripheral behavior...
Regulator control register structure. This structure set power distribution control, V2/VEXT configuration, set V1 reset threshold.
Global event status register. The microcontroller can monitor events via the event status registers...
sbc_gl_evnt_stat_trxe_t
Global event status register, transceiver event (0x60).
sbc_sys_evnt_stat_spif_t
System event status register, SPI failure (0x61).
#define SBC_UJA_FRAME_CTR_PNDM_MASK
Frame control register, partial networking data mask macros.
Definition: UJA1169.h:578
sbc_sup_evnt_stat_v2u_t v2u
sbc_sys_evnt_stat_otw_t
System event status register, overtemperature warning (0x61).
#define SBC_UJA_IDENTIF_X_MASK
Identifier X macros (0x27-0x2Ah).
Definition: UJA1169.h:515
sbc_trans_stat_cts_t cts
#define SBC_UJA_SYS_EVNT_OTWE_MASK
System event capture enable, overtemperature warning enable macros.
Definition: UJA1169.h:139
sbc_supply_stat_v2s_t
Supply voltage status register, V2/VEXT status (0x1B).
sbc_supply_evnt_v2ue_t v2ue
sbc_trans_evnt_stat_cf_t cf
static uint8_t sbc_get_factories_crc(uint8_t *data)
Event capture registers structure. This structure contains Global event status, System event status...
sbc_regulator_t regulator
sbc_regulator_pdc_t
Regulator control register, power distribution control (0x10).
#define SBC_UJA_SYS_EVNT_STAT_PO_MASK
System event status register, power-on macros.
Definition: UJA1169.h:681
status_t SBC_SetWatchdog(const sbc_wtdog_ctr_t *const wtdog)
This function configures Watchdog control register (0x00).
Factory configuration structure. It contains Start-up control register and SBC configuration control ...
uint8_t sbc_data_mask_t
Data mask registers. The data field indicates the nodes to be woken up. Within the data field...
#define SBC_UJA_SYS_EVNT_SPIFE_MASK
System event capture enable, SPI failure enable.
Definition: UJA1169.h:146
sbc_supply_status_t supply
sbc_trans_stat_cfs_t cfs
#define SBC_UJA_MAIN_RSS_MASK
Main status register, Reset source status macros.
Definition: UJA1169.h:125
#define SBC_UJA_TRANS_STAT_VCS_MASK
Transceiver status register, VCAN status macros.
Definition: UJA1169.h:406
Supply voltage status register structure. V2/VEXT and V1 undervoltage and overvoltage status...
sbc_gl_evnt_stat_wpe_t
Global event status register, WAKE pin event (0x60).
#define SBC_UJA_WTDOG_STAT_FNMS_MASK
Watchdog status register, forced Normal mode status macros.
Definition: UJA1169.h:160
static status_t sbc_change_factories_direct(const sbc_factories_conf_t *const factory)
sbc_wtdog_ctr_t watchdog
#define SBC_UJA_GL_EVNT_STAT_SUPE_MASK
Global event status register, supply event macros.
Definition: UJA1169.h:659
sbc_supply_evnt_v1ue_t
Supply event capture enable register, V1 undervoltage enable (0x1C).
status_t SBC_GetAllStatus(sbc_status_group_t *const status)
This function reads all statuses from SBC device. It reads all status registers: Main status and Watc...
sbc_sbc_v1rtsuc_t v1rtsuc
sbc_gl_evnt_stat_syse_t syse
sbc_trans_evnt_t canTransEvnt
sbc_frame_ctr_ide_t ide
Watchdog control register structure. Watchdog configuration structure.
status_t SBC_GetMainStatus(sbc_main_status_t *const mainStatus)
This function reads Main status register. This function will clear R/W registers automatically after ...
#define SBC_UJA_FAIL_SAFE_RCC_F(x)
Definition: UJA1169.h:99
#define SBC_UJA_TRANS_EVNT_STAT_CW_MASK
Transceiver event status register, CAN wake-up.
Definition: UJA1169.h:768
sbc_wtdog_ctr_wmc_t modeControl
status_t SBC_GetMode(sbc_mode_mc_t *const mode)
This function reads Mode control register. (0x01).
uint8_t sbc_mtpnv_stat_wrcnts_t
MTPNV status register, write counter status (0x70). 6-bits - contains the number of times the MTPNV c...
sbc_main_status_t mainS
sbc_frame_ctr_pndm_t
Frame control register, partial networking data mask (0x2F).
sbc_can_pncok_t pncok
sbc_sys_evnt_stat_otw_t otw
sbc_sbc_sdmc_t sdmc
#define SBC_UJA_TIMEOUT
status_t SBC_GetEventsStatus(sbc_evn_capt_t *const events)
This functions reads Event capture registers. This function reads switching threshold of voltage on W...
#define SBC_UJA_REGULATOR_V2C_MASK
Regulator control register, V2/VEXT configuration macros.
Definition: UJA1169.h:262
status_t SBC_GetSupplyStatus(sbc_supply_status_t *const supStatus)
This functions reads Supply voltage status register. This function clear R/W status after reading wri...
status_t SBC_GetWakePin(sbc_wake_t *const wakePin)
This function reads WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits ...
#define SBC_UJA_FRAME_CTR_DLC_MASK
Frame control register, number of data bytes expected in a CAN frame macros.
Definition: UJA1169.h:585
sbc_sup_evnt_stat_v1u_t
Supply event status register, V1 undervoltage (0x62).
#define SBC_UJA_WAKE_STAT_WPVS_MASK
WAKE pin status register, WAKE pin status macros.
Definition: UJA1169.h:608
#define SBC_UJA_SUPPLY_STAT_V1S_MASK
Supply voltage status register, V1 status macros.
Definition: UJA1169.h:290
sbc_gl_evnt_stat_supe_t supe
sbc_trans_stat_coscs_t coscs
uint8_t sbc_identif_mask_t
ID mask registers (0x2B to 0x2E). The identifier mask is defined in the ID mask registers, where a 1 means dont care.
sbc_trans_stat_cfs_t
Transceiver status register, CAN failure status (0x22).
#define SBC_UJA_SBC_V1RTSUC_MASK
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up macr...
Definition: UJA1169.h:855
sbc_trans_evnt_cwe_t
Transceiver event capture enable register, CAN wake-up enable (0x23).
status_t SBC_GetFactoriesSettings(sbc_factories_conf_t *const factoriesConf)
This function reads Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode.
sbc_trans_stat_t trans
sbc_identif_mask_t mask[SBC_UJA_COUNT_MASK]
sbc_identifier_t identif[SBC_UJA_COUNT_ID_REG]
sbc_trans_stat_cpns_t
Transceiver status register, CAN partial networking status (0x22).
#define SBC_UJA_MTPNV_STAT_ECCS_MASK
MTPNV status register, error correction code status.
Definition: UJA1169.h:811
#define SBC_UJA_SUP_EVNT_STAT_V2O_MASK
Supply event status register, V2/VEXT overvoltage macros.
Definition: UJA1169.h:717
sbc_main_rss_t
Main status register, Reset source status (0x03).
static status_t sbc_read_can_others(sbc_can_conf_t *const can)
Start-up control register structure. This structure contains settings of RSTN output reset pulse widt...
sbc_trans_stat_cpns_t cpns
#define DEV_ASSERT(x)
Definition: devassert.h:77
#define SBC_UJA_FAIL_SAFE_LHC_MASK
Fail-safe control register, LIMP home control macros.
Definition: UJA1169.h:90
sbc_can_pncok_t
CAN control register, CAN partial networking configuration OK (0x20).
sbc_trans_evnt_stat_cw_t cw
status_t SBC_GetMtpnvStatus(sbc_mtpnv_stat_t *const mtpnv)
This function reads MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times...
sbc_sys_evnt_stat_wdf_t wdf
sbc_trans_evnt_stat_cbs_t
Transceiver event status register, CAN-bus status (0x63).
MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP)...
Frame control register structure. The wake-up frame format, standard (11-bit) or extended (29-bit) id...
CAN configuration group structure. This structure configure CAN peripheral behavior.
static drv_config_t g_drvConfig
#define SBC_UJA_SYS_EVNT_STAT_SPIF_MASK
System event status register, SPI failure macros.
Definition: UJA1169.h:695
sbc_sup_evnt_stat_v2o_t v2o
sbc_supply_evnt_v2oe_t
Supply event capture enable register, V2/VEXT overvoltage enable (0x1C).
#define SBC_UJA_SUPPLY_STAT_V2S_MASK
Supply voltage status register, V2/VEXT status macros.
Definition: UJA1169.h:283
sbc_sup_evnt_stat_v2u_t
Supply event status register, V2/VEXT undervoltage (0x62).
sbc_sys_evnt_stat_t sysEvnt
sbc_wake_en_wpre_t wpre
sbc_trans_stat_cts_t
Transceiver status register, CAN transceiver status (0x22).
sbc_sup_evnt_stat_v2o_t
Supply event status register, V2/VEXT overvoltage (0x62).
Transceiver event capture enable register structure. Can bus silence, Can failure and Can wake-up set...
#define SBC_UJA_WTDOG_CTR_NWP_MASK
Watchdog mode control, nominal watchdog period macros.
Definition: UJA1169.h:62
#define SBC_UJA_MODE_MC_MASK
Mode control, mode control macros.
Definition: UJA1169.h:76
#define SBC_UJA_SUP_EVNT_STAT_V1U_MASK
Supply event status register, V1 undervoltage: macros.
Definition: UJA1169.h:731
sbc_regulator_v1rtc_t v1rtc
#define SBC_UJA_TRANS_STAT_CPNERR_MASK
Transceiver status register, CAN partial networking error macros.
Definition: UJA1169.h:378
#define SBC_UJA_SUPPLY_EVNT_V2UE_MASK
Supply event capture enable register, V2/VEXT undervoltage enable macros.
Definition: UJA1169.h:313
#define SBC_UJA_CAN_CPNC_MASK
CAN control register, CAN partial networking control macros.
Definition: UJA1169.h:349
#define SBC_UJA_REGULATOR_V1RTC_MASK
Regulator control register, set V1 reset threshold macros.
Definition: UJA1169.h:269
status_t SBC_Init(const sbc_int_config_t *const config, const uint32_t lpspiInstance)
This function initializes all registers. It waits 10ms and then writes to all registers.
sbc_trans_evnt_stat_cbs_t cbs
sbc_fail_safe_lhc_t lhc
#define SBC_UJA_CAN_PNCOK_MASK
CAN control register, CAN partial networking configuration OK macros.
Definition: UJA1169.h:342
System event capture enable register structure. This structure enables or disables overtemperature wa...
sbc_mtpnv_stat_wrcnts_t wrcnts
#define SBC_UJA_GL_EVNT_STAT_WPE_MASK
Global event status register, WAKE pin event macros.
Definition: UJA1169.h:645
#define SBC_UJA_SBC_FNMC_MASK
SBC configuration control register, Forced Normal mode control macros.
Definition: UJA1169.h:863
sbc_wake_evnt_stat_wpr_t
WAKE pin event status register, WAKE pin rising edge (0x64).
status_t SBC_GetVreg(sbc_regulator_ctr_t *const regulatorCtr)
This function reads Regulator control registers.
sbc_can_cmc_t cmc
status_t SBC_GetCanConfig(sbc_can_conf_t *const can)
This function reads CAN peripheral settings. This function configures CAN peripheral behavior...
sbc_frame_ctr_dlc_t dlc
status_t LPSPI_DRV_MasterTransferBlocking(uint32_t instance, const uint8_t *sendBuffer, uint8_t *receiveBuffer, uint16_t transferByteCount, uint32_t timeout)
Performs an interrupt driven blocking SPI master mode transfer.
sbc_sys_evnt_spife_t
System event capture enable, SPI failure enable (0x04).
#define SBC_UJA_CAN_CFDC_MASK
CAN control register, CAN FD control macros.
Definition: UJA1169.h:335
sbc_wake_evnt_stat_wpr_t wpr
status_t SBC_CleanEvents(const sbc_evn_capt_t *const events)
This function clears Event capture registers. It contains Global event status, System event status...
static void sbc_clean_events_status(sbc_evn_capt_t *event)
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
status_t SBC_SetLock(const sbc_lock_t lockMask)
This function writes to Lock control register (0x0A). Sections of the register address area can be wr...
Transceiver event status register.
sbc_sbc_sdmc_t
SBC configuration control register, Software Development mode control (0x74).
sbc_wake_evnt_stat_wpf_t wpf
Watchdog status register structure. Information on the status of the watchdog is available from the W...
sbc_wtdog_ctr_wmc_t
Watchdog control register, watchdog mode control (0x00). The UJA1169 contains a watchdog that support...
#define SBC_UJA_WAKE_EVNT_STAT_WPF_MASK
WAKE pin event status register, WAKE pin falling edge macros.
Definition: UJA1169.h:790
#define SBC_UJA_LOCK_LKNC_MASK
Lock control N macros.
Definition: UJA1169.h:245
CAN control register structure. This structure configure CAN peripheral behavior. ...
sbc_mtpnv_stat_eccs_t eccs
#define SBC_UJA_FAIL_SAFE_RCC_SHIFT
Definition: UJA1169.h:98
sbc_wtdog_stat_wds_t wds
sbc_gl_evnt_stat_supe_t
Global event status register, supply event (0x60).
sbc_frame_ctr_ide_t
Frame control register, identifier format (0x2F). The wake-up frame format, standard (11-bit) or exte...
sbc_regulator_v2c_t v2c
#define SBC_UJA_SBC_SLPC_MASK
SBC configuration control register, Sleep control macros.
Definition: UJA1169.h:878
#define SBC_UJA_WAKE_EVNT_STAT_WPR_MASK
WAKE pin event status register, WAKE pin rising edge macros.
Definition: UJA1169.h:783
status_t SBC_GetSystemEvents(sbc_sys_evnt_t *const sysEvnt)
This function reads System event capture enable register (0x04). This function reads content of overt...
#define SBC_UJA_REGULATOR_PDC_MASK
Regulator control register, power distribution control macros.
Definition: UJA1169.h:255
#define SBC_UJA_TRANS_EVNT_CBSE_MASK
Transceiver event capture enable register, CAN-bus silence enable macros.
Definition: UJA1169.h:430
sbc_supply_stat_v2s_t v2s
#define SBC_UJA_COUNT_DMASK
WAKE pin event status register.
sbc_wtdog_status_t wtdog
#define SBC_UJA_WAKE_EN_WPFE_MASK
WAKE pin event capture enable register, WAKE pin falling-edge enable macros.
Definition: UJA1169.h:631
#define SBC_UJA_SUPPLY_EVNT_V2OE_MASK
Supply event capture enable register, V2/VEXT overvoltage enable macros.
Definition: UJA1169.h:305
sbc_frame_ctr_pndm_t pndm
Supply event capture enable register structure. This structure enables or disables detection of V2/VE...
sbc_can_cmc_t
CAN control register, CAN mode control (0x20).
#define SBC_UJA_CAN_CMC_MASK
CAN control register, CAN mode control macros.
Definition: UJA1169.h:356
status_t SBC_GetLock(sbc_lock_t *const lockMask)
This function reads Lock control register (0x0A). Sections of the register address area can be write-...
uint8_t sbc_identifier_t
ID registers, identifier format (0x27 to 0x2A). A valid WUF identifier is defined and stored in the I...
#define SBC_UJA_DATA_MASK_X_MASK
Data mask registers (0x68 to 0x6F) macros Data mask 0-7 configuration.
Definition: UJA1169.h:601
sbc_can_ctr_t canConf
#define SBC_UJA_TRANS_EVNT_CWE_MASK
Transceiver event capture enable register, CAN wake-up enable.
Definition: UJA1169.h:444
sbc_can_cfdc_t cfdc
sbc_gl_evnt_stat_t glEvnt
sbc_sbc_fnmc_t fnmc
#define SBC_UJA_GL_EVNT_STAT_TRXE_MASK
Global event status register, transceiver event macros.
Definition: UJA1169.h:652
sbc_wtdog_ctr_nwp_t
Watchdog control register, nominal watchdog period (0x00). Eight watchdog periods are supported...
sbc_trans_evnt_stat_pnfde_t
Transceiver event status register,partial networking frame detection error (0x63).
#define SBC_UJA_WAKE_EN_WPRE_MASK
WAKE pin event capture enable register, WAKE pin rising-edge enable macros.
Definition: UJA1169.h:623
#define SBC_UJA_MTPNV_STAT_WRCNTS_MASK
MTPNV status register, write counter status macros.
Definition: UJA1169.h:804
uint32_t lpspiIntace
uint8_t sbc_fail_safe_rcc_t
Fail-safe control register, reset counter control (0x02). incremented every time the SBC enters Reset...
sbc_gl_evnt_stat_wpe_t wpe
sbc_register_t
Register map.
sbc_sys_evnt_stat_spif_t spif
sbc_trans_evnt_cfe_t cfe
sbc_wake_en_wpfe_t wpfe
sbc_regulator_pdc_t pdc
sbc_can_cpnc_t
CAN control register, CAN partial networking control (0x20).
sbc_lock_t
Lock control(0x0A). Sections of the register address area can be write-protected to protect against u...
sbc_sys_evnt_spife_t spife
sbc_main_otws_t
Main status register, Overtemperature warning status (0x03).
sbc_wtdog_stat_wds_t
Watchdog status register, watchdog status (0x05).
sbc_trans_evnt_cwe_t cwe
#define SBC_UJA_TRANS_STAT_CTS_MASK
Transceiver status register, CAN transceiver status macros.
Definition: UJA1169.h:371
#define SBC_UJA_MAIN_NMS_MASK
Main status register, Normal mode status macros.
Definition: UJA1169.h:118
status_t SBC_GetWatchdogStatus(sbc_wtdog_status_t *const watchdogStatus)
This function reads Watchdog status register. This function will clear R/W registers automatically af...
sbc_sup_evnt_stat_v1u_t v1u
sbc_trans_stat_cpnerr_t cpnerr
sbc_dat_rate_t datRate
#define SBC_UJA_WTDOG_STAT_SDMS_MASK
Watchdog status register, Software Development mode status macros.
Definition: UJA1169.h:167
Regulator control register group. This structure is group of regulator settings.
sbc_wtdog_stat_fnms_t
Watchdog status register, forced Normal mode status (0x05).
sbc_start_up_rlc_t rlc
#define SBC_UJA_MTPNV_STAT_NVMPS_MASK
MTPNV status register, non-volatile memory programming status.
Definition: UJA1169.h:818
static status_t sbc_write_can_others(const sbc_can_conf_t *const can)
#define SBC_UJA_TRANS_STAT_CBSS_MASK
Transceiver status register, CAN-bus silence status macros.
Definition: UJA1169.h:399
Supply event status register.
Status group structure. All statuses of SBC are stored in this structure.
sbc_sys_evnt_t sysEvnt
sbc_sbc_slpc_t
SBC configuration control register, Sleep control (0x74).
#define SBC_UJA_TRANS_STAT_CFS_MASK
Transceiver status register, CAN failure status macros.
Definition: UJA1169.h:413
sbc_trans_evnt_cbse_t cbse
#define SBC_UJA_SUPPLY_EVNT_V1UE_MASK
Supply event capture enable register, V1 undervoltage enable macros.
Definition: UJA1169.h:320
status_t SBC_SetVreg(const sbc_regulator_ctr_t *const regulatorCtr)
This function configures Regulator control registers.
sbc_supply_evnt_v2oe_t v2oe
sbc_sys_evnt_stat_wdf_t
System event status register, watchdog failure (0x61).
sbc_start_up_rlc_t
Start-up control register, RSTN output reset pulse width macros (0x73).
#define SBC_UJA_REG_ADDR_F(x)
Definition: UJA1169.h:50
sbc_trans_evnt_stat_cf_t
Transceiver event status register, CAN failure (0x63).
sbc_start_up_v2suc_t
Start-up control register, V2/VEXT start-up control (0x73).
sbc_gl_evnt_stat_syse_t
Global event status register, system event (0x60).
System event status register. Wake-up and interrupt event diagnosis in the UJA1169 is intended to pro...
sbc_supply_evnt_v1ue_t v1ue
sbc_trans_evnt_stat_cw_t
Transceiver event status register, CAN wake-up (0x63).
#define SBC_UJA_TRANS_EVNT_STAT_CF_MASK
Transceiver event status register, CAN failure.
Definition: UJA1169.h:761
SBC configuration control register structure. Two operating modes have a major impact on the operatio...
sbc_supply_stat_v1s_t
Supply voltage status register, V1 status (0x1B).
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK
Transceiver event status register, partial networking frame detection error macros.
Definition: UJA1169.h:747
status_t SBC_DataTransfer(const sbc_register_t regName, const uint8_t *const sendData, uint8_t *const receiveData)
This function sends data over LSPI to SBC device. This function sends 8 bites to SBC device register ...
sbc_supply_evnt_v2ue_t
Supply event capture enable register, V2/VEXT undervoltage enable (0x1C).
sbc_regulator_ctr_t regulatorCtr
status_t SBC_GetCanStatus(sbc_trans_stat_t *const transStatus)
This functions reads Transceiver status register. It contains CAN transceiver status, CAN partial networking error, CAN partial networking status, CAN oscillator status, CAN-bus silence status, VCAN status, CAN failure status.
sbc_trans_stat_vcs_t vcs
#define SBC_UJA_WTDOG_STAT_WDS_MASK
Watchdog status register, watchdog status macros.
Definition: UJA1169.h:174
void SBC_FeedWatchdog(void)
This function refreshes watchdog period by writing byte to the SBC watchdog register. This function must be called periodically according Watchdog mode control and Nominal watchdog period settings. Note: Unxpected behaviour can happend if watchdog mode is set to timeout period and watchdog is triggered exactly at 50% of period. Be sure you trigger watchdog before 50% or above 50% of watchdog period.
sbc_trans_stat_vcs_t
Transceiver status register, VCAN status (0x22).
status_t SBC_SetFailSafe(const sbc_fail_safe_lhc_t lhc, const sbc_fail_safe_rcc_t *const rcc)
This function writes to Fail-safe control register (0x02). The dedicated LIMP pin can be used to enab...
#define SBC_UJA_FRAME_CTR_IDE_MASK
Frame control register, identifier format macros.
Definition: UJA1169.h:571
sbc_sbc_fnmc_t
SBC configuration control register, Forced Normal mode control (0x74).
sbc_trans_stat_cpnerr_t
Transceiver status register, CAN partial networking error (0x22).
sbc_mtpnv_stat_eccs_t
MTPNV status register, error correction code status (0x70).
status_t SBC_GetWakeStatus(sbc_wake_stat_wpvs_t *const wakeStatus)
This functions reads WAKE pin status register. This function reads switching threshold of voltage on ...
WAKE pin event capture enable register structure. Local wake-up is enabled via bits WPRE and WPFE in ...
sbc_sbc_slpc_t slpc
sbc_wake_evnt_stat_t wakePinEvnt
sbc_trans_evnt_cbse_t
Transceiver event capture enable register, CAN-bus silence enable (0x23).
sbc_wake_stat_wpvs_t
WAKE pin status register, WAKE pin status (0x4B).
sbc_sys_evnt_otwe_t owte
sbc_mtpnv_stat_nvmps_t
MTPNV status register, non-volatile memory programming status (0x70).
sbc_regulator_v1rtc_t
Regulator control register, set V1 reset threshold (0x10).
status_t SBC_ChangeFactoriesSettings(const sbc_factories_conf_t *const newConf)
This function sets Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode. Note for default settings see sbc_factories_conf_t comment. If the device has been programmed previously, the factory presets may need to be restored before reprogramming can begin. When the factory presets have been restored successfully, a system reset is generated automatically and UJA1169 switches back to Forced Normal mode. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: -pin RSTN is held LOW -CANH is pulled up to VBAT -CANL is pulled down to GND.
uint8_t sbc_frame_ctr_dlc_t
Frame control register, number of data bytes expected in a CAN frame (0x2F).
sbc_wtdog_stat_sdms_t
Watchdog status register, Software Development mode status (0x05).
status_t SBC_SetMode(const sbc_mode_mc_t mode)
This function writes to Mode control register. (0x01).
sbc_can_cfdc_t
CAN control register, CAN FD control (0x20).
sbc_wtdog_ctr_t watchdogCtr
sbc_trans_evnt_stat_t transEvnt
sbc_wake_evnt_stat_wpf_t
WAKE pin event status register, WAKE pin falling edge (0x64).
#define SBC_UJA_DAT_RATE_CDR_MASK
Data rate register, CAN data rate selection macros.
Definition: UJA1169.h:459
#define SBC_UJA_TRANS_EVNT_CFE_MASK
Transceiver event capture enable register, CAN failure enable macros.
Definition: UJA1169.h:437
#define SBC_UJA_GL_EVNT_STAT_SYSE_MASK
Global event status register, system event macros.
Definition: UJA1169.h:666
sbc_wtdog_ctr_nwp_t nominalPeriod
sbc_sbc_v1rtsuc_t
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x7...
sbc_trans_stat_cbss_t cbss
#define SBC_UJA_START_UP_RLC_MASK
Start-up control register, RSTN output reset pulse width macros.
Definition: UJA1169.h:833
#define SBC_UJA_MASK_X_MASK
Mask X macros (0x2b-0x2e).
Definition: UJA1169.h:564
sbc_supply_stat_v1s_t v1s
#define SBC_UJA_SUP_EVNT_STAT_V2U_MASK
Supply event status register, V2/VEXT undervoltage macros.
Definition: UJA1169.h:724
status_t SBC_SetWakePin(const sbc_wake_t *const wakePin)
This function writes to WAKE pin event capture enable register (0x4C). Local wake-up is enabled via b...
sbc_wtdog_stat_fnms_t fnms