118 g_drvConfig.
isInit =
true;
168 g_drvConfig.
isInit =
false;
201 uint8_t regData = (uint8_t)((uint8_t)regulator->
pdc | (uint8_t)regulator->
v2c
202 | (uint8_t)regulator->
v1rtc);
212 regData = (uint8_t)((uint8_t)sEvnt->
v2oe | (uint8_t)sEvnt->
v2ue
213 | (uint8_t)sEvnt->
v1ue);
306 bool newWdMode =
false;
329 uint8_t regData = (uint8_t)((uint8_t)wtdog->
modeControl
454 uint8_t regData = (uint8_t)mode;
570 uint8_t regData = (uint8_t)lhc;
573 if((rcc != NULL) && ( (*rcc == 0U) || (*rcc <=3U) ) )
671 uint8_t regData = (uint8_t)((uint8_t)sysEvnt->
owte | (uint8_t)sysEvnt->
spife);
746 uint8_t regData = (uint8_t)lockMask;
826 uint8_t regData = (uint8_t)((uint8_t)canC->
cfdc | (uint8_t)canC->
pncok
827 | (uint8_t)canC->
cpnc | (uint8_t)canC->
cmc);
837 regData = (uint8_t)((uint8_t)tEvnt->
cbse | (uint8_t)tEvnt->
cfe
838 | (uint8_t)tEvnt->
cwe);
956 uint8_t regData = (uint8_t)((uint8_t)wakePin->
wpre | (uint8_t)wakePin->
wpfe);
1032 uint8_t readData = 0U;
1070 uint8_t readData = 0U;
1079 readData &= (uint8_t)~SBC_UJA_WTDOG_STAT_FNMS_MASK;
1080 readData &= (uint8_t)~SBC_UJA_WTDOG_STAT_SDMS_MASK;
1112 uint8_t readData = 0U;
1120 readData &= (uint8_t)~SBC_UJA_SUPPLY_STAT_V2S_MASK;
1121 readData &= (uint8_t)~SBC_UJA_SUPPLY_STAT_V1S_MASK;
1152 uint8_t readData = 0U;
1195 uint8_t readData = 0U;
1235 uint8_t readData = 0U;
1347 uint8_t clearMask = 0;
1354 clearMask = (uint8_t)((uint8_t)glEvents->
supe | (uint8_t)glEvents->
syse
1355 | (uint8_t)glEvents->
trxe | (uint8_t)glEvents->
wpe);
1357 ujaStat = (
status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1361 clearMask = (uint8_t)((uint8_t)sysEvents->
otw | (uint8_t)sysEvents->
po
1362 | (uint8_t)sysEvents->
spif | (uint8_t)sysEvents->
wdf);
1364 ujaStat = (
status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1368 clearMask = (uint8_t)((uint8_t)supEvents->
v1u | (uint8_t)supEvents->
v2o
1369 | (uint8_t)supEvents->
v2u);
1371 ujaStat = (
status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1375 clearMask = (uint8_t)( (uint8_t)transEvents->
cbs | (uint8_t)transEvents->
cf
1376 | (uint8_t)transEvents->
cw | (uint8_t)transEvents->
pnfde);
1378 ujaStat = (
status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1382 clearMask = (uint8_t)((uint8_t)wakeEvent->
wpf | (uint8_t)wakeEvent->
wpr);
1384 ujaStat = (
status_t)((uint32_t)ujaStat | (uint32_t)spiStat);
1473 uint8_t readData = 0U;
1522 uint8_t readData = 0U;
1631 const uint8_t*
const sendData, uint8_t*
const receiveData)
1636 uint8_t command[2] = {0U, 0U};
1637 uint8_t readOnlyMask = 0x00U;
1638 uint8_t readData[2] = {0U, 0U};
1641 if(sendData == NULL)
1644 readOnlyMask = 0x01U;
1649 command[0] = *sendData;
1658 if( readData[1] != command[1])
1664 if(receiveData != NULL)
1666 *receiveData = readData[0];
1684 uint8_t regData = 0;
1715 regData = (uint8_t)( (uint8_t)frame->
ide | (uint8_t)frame->
pndm |
1716 (uint8_t)frame->
dlc);
1735 uint8_t regData = 0;
1820 uint8_t crc = 0xFF, i,j;
1822 for(i = 0; i<= 1U; i++ )
1824 data[i] = (uint8_t)(data[i] ^ crc);
1825 for(j = 0; j<=7U; j++)
1829 data[i] = (uint8_t)( (uint8_t)data[i] << 1U);
1830 data[i] = (uint8_t)(data[i] ^ 0x2FU);
1834 data[i] = (uint8_t)(data[i] << 1U);
1839 crc = (uint8_t)(crc ^ 0xFFU);
1855 uint8_t sendData[2] = {0, 0};
1865 sendData[1] = (uint8_t)((uint8_t)ctrl->
v1rtsuc | (uint8_t)ctrl->
fnmc |
1866 (uint8_t)ctrl->
sdmc | (uint8_t)ctrl->
slpc);
#define SBC_UJA_SYS_EVNT_STAT_WDF_MASK
System event status register, watchdog failure macros.
sbc_wake_en_wpre_t
WAKE pin event capture enable register, WAKE pin rising-edge enable (0x4C).
status_t SBC_GetWatchdog(sbc_wtdog_ctr_t *const wtdog)
This function reads Watchdog control register (0x00).
Init configuration structure. This structure is used for initialization of sbc.
#define SBC_UJA_COUNT_ID_REG
#define SBC_UJA_TRANS_STAT_CPNS_MASK
Transceiver status register, CAN partial networking status macros.
Main status register structure. The Main status register can be accessed to monitor the status of the...
#define SBC_UJA_TRANS_STAT_COSCS_MASK
Transceiver status register, CAN oscillator status macros.
sbc_fail_safe_lhc_t
Fail-safe control register, LIMP home control (0x02). The dedicated LIMP pin can be used to enable so...
sbc_mode_mc_t
Mode control register, mode control (0x01)
#define SBC_UJA_START_UP_V2SUC_MASK
Start-up control register, V2/VEXT start-up control macros.
sbc_sys_evnt_otwe_t
System event capture enable, overtemperature warning enable (0x04).
status_t SBC_GetFailSafe(sbc_fail_safe_lhc_t *const lhc, sbc_fail_safe_rcc_t *const rcc)
This function reads from Fail-safe control register (0x02). The dedicated LIMP pin can be used to ena...
sbc_sup_evnt_stat_t supEvnt
sbc_gl_evnt_stat_trxe_t trxe
sbc_trans_evnt_cfe_t
Transceiver event capture enable register, CAN failure enable (0x23).
sbc_data_mask_t dataMask[SBC_UJA_COUNT_DMASK]
sbc_wake_stat_wpvs_t wakePin
sbc_mtpnv_stat_nvmps_t nvmps
sbc_dat_rate_t
Data rate register, CAN data rate selection (0x26). CAN partial networking configuration registers...
#define SBC_UJA_TRANS_EVNT_STAT_CBS_MASK
Transceiver event status register, CAN-bus status macros.
sbc_trans_evnt_stat_pnfde_t pnfde
#define SBC_UJA_WTDOG_CTR_WMC_MASK
Watchdog mode control, watchdog mode control macros.
sbc_supply_evnt_t supplyEvnt
#define SBC_UJA_SYS_EVNT_STAT_OTW_MASK
System event status register, overtemperature warning macros.
sbc_sys_evnt_stat_po_t po
sbc_trans_stat_cbss_t
Transceiver status register, CAN-bus silence status (0x22).
sbc_trans_stat_coscs_t
Transceiver status register, CAN oscillator status (0x22).
sbc_start_up_v2suc_t v2suc
sbc_sys_evnt_stat_po_t
System event status register, power-on (0x61).
status_t SBC_SetSystemEvents(const sbc_sys_evnt_t *const sysEvnt)
This function writes System event capture enable register (0x04). This function enables or disables o...
#define SBC_UJA_FAIL_SAFE_RCC_MASK
Fail-safe control register, reset counter control macros.
sbc_regulator_v2c_t
Regulator control register, V2/VEXT configuration (0x10).
sbc_wake_en_wpfe_t
WAKE pin event capture enable register, WAKE pin falling-edge enable (0x4C).
#define SBC_UJA_MAIN_OTWS_MASK
Main status register, Overtemperature warning status macros.
#define SBC_UJA_SBC_SDMC_MASK
SBC configuration control register, Software Development mode control macros.
sbc_wtdog_stat_sdms_t sdms
Transceiver status register structure. There are stored CAN transceiver statuses. ...
sbc_main_nms_t
Main status register, normal mode status (0x03).
void OSIF_TimeDelay(const uint32_t delay)
Delays execution for a number of milliseconds.
status_t SBC_SetCanConfig(const sbc_can_conf_t *const can)
This function configures CAN peripheral behavior. This function configures CAN peripheral behavior...
Regulator control register structure. This structure set power distribution control, V2/VEXT configuration, set V1 reset threshold.
Global event status register. The microcontroller can monitor events via the event status registers...
sbc_gl_evnt_stat_trxe_t
Global event status register, transceiver event (0x60).
sbc_sys_evnt_stat_spif_t
System event status register, SPI failure (0x61).
#define SBC_UJA_FRAME_CTR_PNDM_MASK
Frame control register, partial networking data mask macros.
sbc_sup_evnt_stat_v2u_t v2u
sbc_sys_evnt_stat_otw_t
System event status register, overtemperature warning (0x61).
#define SBC_UJA_IDENTIF_X_MASK
Identifier X macros (0x27-0x2Ah).
#define SBC_UJA_SYS_EVNT_OTWE_MASK
System event capture enable, overtemperature warning enable macros.
sbc_supply_stat_v2s_t
Supply voltage status register, V2/VEXT status (0x1B).
sbc_supply_evnt_v2ue_t v2ue
sbc_trans_evnt_stat_cf_t cf
static uint8_t sbc_get_factories_crc(uint8_t *data)
Event capture registers structure. This structure contains Global event status, System event status...
sbc_regulator_t regulator
sbc_regulator_pdc_t
Regulator control register, power distribution control (0x10).
#define SBC_UJA_SYS_EVNT_STAT_PO_MASK
System event status register, power-on macros.
status_t SBC_SetWatchdog(const sbc_wtdog_ctr_t *const wtdog)
This function configures Watchdog control register (0x00).
Factory configuration structure. It contains Start-up control register and SBC configuration control ...
uint8_t sbc_data_mask_t
Data mask registers. The data field indicates the nodes to be woken up. Within the data field...
#define SBC_UJA_SYS_EVNT_SPIFE_MASK
System event capture enable, SPI failure enable.
sbc_supply_status_t supply
#define SBC_UJA_MAIN_RSS_MASK
Main status register, Reset source status macros.
#define SBC_UJA_TRANS_STAT_VCS_MASK
Transceiver status register, VCAN status macros.
Supply voltage status register structure. V2/VEXT and V1 undervoltage and overvoltage status...
sbc_gl_evnt_stat_wpe_t
Global event status register, WAKE pin event (0x60).
#define SBC_UJA_WTDOG_STAT_FNMS_MASK
Watchdog status register, forced Normal mode status macros.
static status_t sbc_change_factories_direct(const sbc_factories_conf_t *const factory)
#define SBC_UJA_GL_EVNT_STAT_SUPE_MASK
Global event status register, supply event macros.
sbc_supply_evnt_v1ue_t
Supply event capture enable register, V1 undervoltage enable (0x1C).
status_t SBC_GetAllStatus(sbc_status_group_t *const status)
This function reads all statuses from SBC device. It reads all status registers: Main status and Watc...
sbc_sbc_v1rtsuc_t v1rtsuc
sbc_gl_evnt_stat_syse_t syse
sbc_trans_evnt_t canTransEvnt
Watchdog control register structure. Watchdog configuration structure.
status_t SBC_GetMainStatus(sbc_main_status_t *const mainStatus)
This function reads Main status register. This function will clear R/W registers automatically after ...
#define SBC_UJA_FAIL_SAFE_RCC_F(x)
#define SBC_UJA_TRANS_EVNT_STAT_CW_MASK
Transceiver event status register, CAN wake-up.
sbc_wtdog_ctr_wmc_t modeControl
status_t SBC_GetMode(sbc_mode_mc_t *const mode)
This function reads Mode control register. (0x01).
uint8_t sbc_mtpnv_stat_wrcnts_t
MTPNV status register, write counter status (0x70). 6-bits - contains the number of times the MTPNV c...
sbc_frame_ctr_pndm_t
Frame control register, partial networking data mask (0x2F).
sbc_sys_evnt_stat_otw_t otw
status_t SBC_GetEventsStatus(sbc_evn_capt_t *const events)
This functions reads Event capture registers. This function reads switching threshold of voltage on W...
#define SBC_UJA_REGULATOR_V2C_MASK
Regulator control register, V2/VEXT configuration macros.
status_t SBC_GetSupplyStatus(sbc_supply_status_t *const supStatus)
This functions reads Supply voltage status register. This function clear R/W status after reading wri...
status_t SBC_GetWakePin(sbc_wake_t *const wakePin)
This function reads WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits ...
#define SBC_UJA_FRAME_CTR_DLC_MASK
Frame control register, number of data bytes expected in a CAN frame macros.
sbc_sup_evnt_stat_v1u_t
Supply event status register, V1 undervoltage (0x62).
#define SBC_UJA_WAKE_STAT_WPVS_MASK
WAKE pin status register, WAKE pin status macros.
#define SBC_UJA_SUPPLY_STAT_V1S_MASK
Supply voltage status register, V1 status macros.
sbc_gl_evnt_stat_supe_t supe
sbc_trans_stat_coscs_t coscs
uint8_t sbc_identif_mask_t
ID mask registers (0x2B to 0x2E). The identifier mask is defined in the ID mask registers, where a 1 means dont care.
sbc_trans_stat_cfs_t
Transceiver status register, CAN failure status (0x22).
#define SBC_UJA_SBC_V1RTSUC_MASK
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up macr...
sbc_trans_evnt_cwe_t
Transceiver event capture enable register, CAN wake-up enable (0x23).
status_t SBC_GetFactoriesSettings(sbc_factories_conf_t *const factoriesConf)
This function reads Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode.
sbc_identif_mask_t mask[SBC_UJA_COUNT_MASK]
sbc_identifier_t identif[SBC_UJA_COUNT_ID_REG]
sbc_trans_stat_cpns_t
Transceiver status register, CAN partial networking status (0x22).
#define SBC_UJA_MTPNV_STAT_ECCS_MASK
MTPNV status register, error correction code status.
#define SBC_UJA_SUP_EVNT_STAT_V2O_MASK
Supply event status register, V2/VEXT overvoltage macros.
sbc_main_rss_t
Main status register, Reset source status (0x03).
static status_t sbc_read_can_others(sbc_can_conf_t *const can)
Start-up control register structure. This structure contains settings of RSTN output reset pulse widt...
sbc_trans_stat_cpns_t cpns
#define SBC_UJA_FAIL_SAFE_LHC_MASK
Fail-safe control register, LIMP home control macros.
sbc_can_pncok_t
CAN control register, CAN partial networking configuration OK (0x20).
sbc_trans_evnt_stat_cw_t cw
status_t SBC_GetMtpnvStatus(sbc_mtpnv_stat_t *const mtpnv)
This function reads MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times...
sbc_sys_evnt_stat_wdf_t wdf
sbc_trans_evnt_stat_cbs_t
Transceiver event status register, CAN-bus status (0x63).
MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP)...
Frame control register structure. The wake-up frame format, standard (11-bit) or extended (29-bit) id...
CAN configuration group structure. This structure configure CAN peripheral behavior.
static drv_config_t g_drvConfig
#define SBC_UJA_SYS_EVNT_STAT_SPIF_MASK
System event status register, SPI failure macros.
sbc_sup_evnt_stat_v2o_t v2o
sbc_supply_evnt_v2oe_t
Supply event capture enable register, V2/VEXT overvoltage enable (0x1C).
#define SBC_UJA_SUPPLY_STAT_V2S_MASK
Supply voltage status register, V2/VEXT status macros.
sbc_sup_evnt_stat_v2u_t
Supply event status register, V2/VEXT undervoltage (0x62).
sbc_sys_evnt_stat_t sysEvnt
sbc_trans_stat_cts_t
Transceiver status register, CAN transceiver status (0x22).
sbc_sup_evnt_stat_v2o_t
Supply event status register, V2/VEXT overvoltage (0x62).
Transceiver event capture enable register structure. Can bus silence, Can failure and Can wake-up set...
#define SBC_UJA_WTDOG_CTR_NWP_MASK
Watchdog mode control, nominal watchdog period macros.
#define SBC_UJA_MODE_MC_MASK
Mode control, mode control macros.
#define SBC_UJA_SUP_EVNT_STAT_V1U_MASK
Supply event status register, V1 undervoltage: macros.
sbc_regulator_v1rtc_t v1rtc
#define SBC_UJA_TRANS_STAT_CPNERR_MASK
Transceiver status register, CAN partial networking error macros.
#define SBC_UJA_SUPPLY_EVNT_V2UE_MASK
Supply event capture enable register, V2/VEXT undervoltage enable macros.
#define SBC_UJA_CAN_CPNC_MASK
CAN control register, CAN partial networking control macros.
#define SBC_UJA_REGULATOR_V1RTC_MASK
Regulator control register, set V1 reset threshold macros.
status_t SBC_Init(const sbc_int_config_t *const config, const uint32_t lpspiInstance)
This function initializes all registers. It waits 10ms and then writes to all registers.
sbc_trans_evnt_stat_cbs_t cbs
#define SBC_UJA_CAN_PNCOK_MASK
CAN control register, CAN partial networking configuration OK macros.
System event capture enable register structure. This structure enables or disables overtemperature wa...
sbc_mtpnv_stat_wrcnts_t wrcnts
#define SBC_UJA_GL_EVNT_STAT_WPE_MASK
Global event status register, WAKE pin event macros.
#define SBC_UJA_SBC_FNMC_MASK
SBC configuration control register, Forced Normal mode control macros.
sbc_wake_evnt_stat_wpr_t
WAKE pin event status register, WAKE pin rising edge (0x64).
status_t SBC_GetVreg(sbc_regulator_ctr_t *const regulatorCtr)
This function reads Regulator control registers.
status_t SBC_GetCanConfig(sbc_can_conf_t *const can)
This function reads CAN peripheral settings. This function configures CAN peripheral behavior...
status_t LPSPI_DRV_MasterTransferBlocking(uint32_t instance, const uint8_t *sendBuffer, uint8_t *receiveBuffer, uint16_t transferByteCount, uint32_t timeout)
Performs an interrupt driven blocking SPI master mode transfer.
sbc_sys_evnt_spife_t
System event capture enable, SPI failure enable (0x04).
#define SBC_UJA_CAN_CFDC_MASK
CAN control register, CAN FD control macros.
sbc_wake_evnt_stat_wpr_t wpr
status_t SBC_CleanEvents(const sbc_evn_capt_t *const events)
This function clears Event capture registers. It contains Global event status, System event status...
static void sbc_clean_events_status(sbc_evn_capt_t *event)
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t SBC_SetLock(const sbc_lock_t lockMask)
This function writes to Lock control register (0x0A). Sections of the register address area can be wr...
Transceiver event status register.
sbc_sbc_sdmc_t
SBC configuration control register, Software Development mode control (0x74).
sbc_wake_evnt_stat_wpf_t wpf
Watchdog status register structure. Information on the status of the watchdog is available from the W...
sbc_wtdog_ctr_wmc_t
Watchdog control register, watchdog mode control (0x00). The UJA1169 contains a watchdog that support...
#define SBC_UJA_WAKE_EVNT_STAT_WPF_MASK
WAKE pin event status register, WAKE pin falling edge macros.
#define SBC_UJA_LOCK_LKNC_MASK
Lock control N macros.
CAN control register structure. This structure configure CAN peripheral behavior. ...
sbc_mtpnv_stat_eccs_t eccs
#define SBC_UJA_FAIL_SAFE_RCC_SHIFT
sbc_gl_evnt_stat_supe_t
Global event status register, supply event (0x60).
sbc_frame_ctr_ide_t
Frame control register, identifier format (0x2F). The wake-up frame format, standard (11-bit) or exte...
#define SBC_UJA_SBC_SLPC_MASK
SBC configuration control register, Sleep control macros.
#define SBC_UJA_WAKE_EVNT_STAT_WPR_MASK
WAKE pin event status register, WAKE pin rising edge macros.
status_t SBC_GetSystemEvents(sbc_sys_evnt_t *const sysEvnt)
This function reads System event capture enable register (0x04). This function reads content of overt...
#define SBC_UJA_REGULATOR_PDC_MASK
Regulator control register, power distribution control macros.
#define SBC_UJA_TRANS_EVNT_CBSE_MASK
Transceiver event capture enable register, CAN-bus silence enable macros.
sbc_supply_stat_v2s_t v2s
#define SBC_UJA_COUNT_DMASK
WAKE pin event status register.
#define SBC_UJA_WAKE_EN_WPFE_MASK
WAKE pin event capture enable register, WAKE pin falling-edge enable macros.
#define SBC_UJA_SUPPLY_EVNT_V2OE_MASK
Supply event capture enable register, V2/VEXT overvoltage enable macros.
sbc_frame_ctr_pndm_t pndm
Supply event capture enable register structure. This structure enables or disables detection of V2/VE...
sbc_can_cmc_t
CAN control register, CAN mode control (0x20).
#define SBC_UJA_CAN_CMC_MASK
CAN control register, CAN mode control macros.
status_t SBC_GetLock(sbc_lock_t *const lockMask)
This function reads Lock control register (0x0A). Sections of the register address area can be write-...
uint8_t sbc_identifier_t
ID registers, identifier format (0x27 to 0x2A). A valid WUF identifier is defined and stored in the I...
#define SBC_UJA_DATA_MASK_X_MASK
Data mask registers (0x68 to 0x6F) macros Data mask 0-7 configuration.
#define SBC_UJA_TRANS_EVNT_CWE_MASK
Transceiver event capture enable register, CAN wake-up enable.
sbc_gl_evnt_stat_t glEvnt
#define SBC_UJA_GL_EVNT_STAT_TRXE_MASK
Global event status register, transceiver event macros.
sbc_wtdog_ctr_nwp_t
Watchdog control register, nominal watchdog period (0x00). Eight watchdog periods are supported...
sbc_trans_evnt_stat_pnfde_t
Transceiver event status register,partial networking frame detection error (0x63).
#define SBC_UJA_WAKE_EN_WPRE_MASK
WAKE pin event capture enable register, WAKE pin rising-edge enable macros.
#define SBC_UJA_MTPNV_STAT_WRCNTS_MASK
MTPNV status register, write counter status macros.
uint8_t sbc_fail_safe_rcc_t
Fail-safe control register, reset counter control (0x02). incremented every time the SBC enters Reset...
sbc_gl_evnt_stat_wpe_t wpe
sbc_register_t
Register map.
sbc_sys_evnt_stat_spif_t spif
sbc_can_cpnc_t
CAN control register, CAN partial networking control (0x20).
sbc_lock_t
Lock control(0x0A). Sections of the register address area can be write-protected to protect against u...
sbc_sys_evnt_spife_t spife
sbc_main_otws_t
Main status register, Overtemperature warning status (0x03).
sbc_wtdog_stat_wds_t
Watchdog status register, watchdog status (0x05).
#define SBC_UJA_TRANS_STAT_CTS_MASK
Transceiver status register, CAN transceiver status macros.
#define SBC_UJA_MAIN_NMS_MASK
Main status register, Normal mode status macros.
status_t SBC_GetWatchdogStatus(sbc_wtdog_status_t *const watchdogStatus)
This function reads Watchdog status register. This function will clear R/W registers automatically af...
sbc_sup_evnt_stat_v1u_t v1u
sbc_trans_stat_cpnerr_t cpnerr
#define SBC_UJA_WTDOG_STAT_SDMS_MASK
Watchdog status register, Software Development mode status macros.
Regulator control register group. This structure is group of regulator settings.
sbc_wtdog_stat_fnms_t
Watchdog status register, forced Normal mode status (0x05).
#define SBC_UJA_MTPNV_STAT_NVMPS_MASK
MTPNV status register, non-volatile memory programming status.
static status_t sbc_write_can_others(const sbc_can_conf_t *const can)
#define SBC_UJA_TRANS_STAT_CBSS_MASK
Transceiver status register, CAN-bus silence status macros.
Supply event status register.
Status group structure. All statuses of SBC are stored in this structure.
sbc_sbc_slpc_t
SBC configuration control register, Sleep control (0x74).
#define SBC_UJA_TRANS_STAT_CFS_MASK
Transceiver status register, CAN failure status macros.
sbc_trans_evnt_cbse_t cbse
#define SBC_UJA_SUPPLY_EVNT_V1UE_MASK
Supply event capture enable register, V1 undervoltage enable macros.
status_t SBC_SetVreg(const sbc_regulator_ctr_t *const regulatorCtr)
This function configures Regulator control registers.
sbc_supply_evnt_v2oe_t v2oe
sbc_sys_evnt_stat_wdf_t
System event status register, watchdog failure (0x61).
sbc_start_up_rlc_t
Start-up control register, RSTN output reset pulse width macros (0x73).
#define SBC_UJA_REG_ADDR_F(x)
sbc_trans_evnt_stat_cf_t
Transceiver event status register, CAN failure (0x63).
sbc_start_up_v2suc_t
Start-up control register, V2/VEXT start-up control (0x73).
sbc_gl_evnt_stat_syse_t
Global event status register, system event (0x60).
System event status register. Wake-up and interrupt event diagnosis in the UJA1169 is intended to pro...
sbc_supply_evnt_v1ue_t v1ue
sbc_trans_evnt_stat_cw_t
Transceiver event status register, CAN wake-up (0x63).
#define SBC_UJA_TRANS_EVNT_STAT_CF_MASK
Transceiver event status register, CAN failure.
SBC configuration control register structure. Two operating modes have a major impact on the operatio...
sbc_supply_stat_v1s_t
Supply voltage status register, V1 status (0x1B).
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_MASK
Transceiver event status register, partial networking frame detection error macros.
status_t SBC_DataTransfer(const sbc_register_t regName, const uint8_t *const sendData, uint8_t *const receiveData)
This function sends data over LSPI to SBC device. This function sends 8 bites to SBC device register ...
sbc_supply_evnt_v2ue_t
Supply event capture enable register, V2/VEXT undervoltage enable (0x1C).
sbc_regulator_ctr_t regulatorCtr
status_t SBC_GetCanStatus(sbc_trans_stat_t *const transStatus)
This functions reads Transceiver status register. It contains CAN transceiver status, CAN partial networking error, CAN partial networking status, CAN oscillator status, CAN-bus silence status, VCAN status, CAN failure status.
#define SBC_UJA_WTDOG_STAT_WDS_MASK
Watchdog status register, watchdog status macros.
void SBC_FeedWatchdog(void)
This function refreshes watchdog period by writing byte to the SBC watchdog register. This function must be called periodically according Watchdog mode control and Nominal watchdog period settings. Note: Unxpected behaviour can happend if watchdog mode is set to timeout period and watchdog is triggered exactly at 50% of period. Be sure you trigger watchdog before 50% or above 50% of watchdog period.
sbc_trans_stat_vcs_t
Transceiver status register, VCAN status (0x22).
status_t SBC_SetFailSafe(const sbc_fail_safe_lhc_t lhc, const sbc_fail_safe_rcc_t *const rcc)
This function writes to Fail-safe control register (0x02). The dedicated LIMP pin can be used to enab...
#define SBC_UJA_FRAME_CTR_IDE_MASK
Frame control register, identifier format macros.
sbc_sbc_fnmc_t
SBC configuration control register, Forced Normal mode control (0x74).
sbc_trans_stat_cpnerr_t
Transceiver status register, CAN partial networking error (0x22).
sbc_mtpnv_stat_eccs_t
MTPNV status register, error correction code status (0x70).
status_t SBC_GetWakeStatus(sbc_wake_stat_wpvs_t *const wakeStatus)
This functions reads WAKE pin status register. This function reads switching threshold of voltage on ...
WAKE pin event capture enable register structure. Local wake-up is enabled via bits WPRE and WPFE in ...
sbc_wake_evnt_stat_t wakePinEvnt
sbc_trans_evnt_cbse_t
Transceiver event capture enable register, CAN-bus silence enable (0x23).
sbc_wake_stat_wpvs_t
WAKE pin status register, WAKE pin status (0x4B).
sbc_mtpnv_stat_nvmps_t
MTPNV status register, non-volatile memory programming status (0x70).
sbc_regulator_v1rtc_t
Regulator control register, set V1 reset threshold (0x10).
status_t SBC_ChangeFactoriesSettings(const sbc_factories_conf_t *const newConf)
This function sets Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode. Note for default settings see sbc_factories_conf_t comment. If the device has been programmed previously, the factory presets may need to be restored before reprogramming can begin. When the factory presets have been restored successfully, a system reset is generated automatically and UJA1169 switches back to Forced Normal mode. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: -pin RSTN is held LOW -CANH is pulled up to VBAT -CANL is pulled down to GND.
uint8_t sbc_frame_ctr_dlc_t
Frame control register, number of data bytes expected in a CAN frame (0x2F).
sbc_wtdog_stat_sdms_t
Watchdog status register, Software Development mode status (0x05).
status_t SBC_SetMode(const sbc_mode_mc_t mode)
This function writes to Mode control register. (0x01).
sbc_can_cfdc_t
CAN control register, CAN FD control (0x20).
sbc_wtdog_ctr_t watchdogCtr
sbc_trans_evnt_stat_t transEvnt
sbc_wake_evnt_stat_wpf_t
WAKE pin event status register, WAKE pin falling edge (0x64).
#define SBC_UJA_DAT_RATE_CDR_MASK
Data rate register, CAN data rate selection macros.
#define SBC_UJA_TRANS_EVNT_CFE_MASK
Transceiver event capture enable register, CAN failure enable macros.
#define SBC_UJA_GL_EVNT_STAT_SYSE_MASK
Global event status register, system event macros.
sbc_wtdog_ctr_nwp_t nominalPeriod
sbc_sbc_v1rtsuc_t
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x7...
sbc_trans_stat_cbss_t cbss
#define SBC_UJA_START_UP_RLC_MASK
Start-up control register, RSTN output reset pulse width macros.
#define SBC_UJA_MASK_X_MASK
Mask X macros (0x2b-0x2e).
sbc_supply_stat_v1s_t v1s
#define SBC_UJA_SUP_EVNT_STAT_V2U_MASK
Supply event status register, V2/VEXT undervoltage macros.
status_t SBC_SetWakePin(const sbc_wake_t *const wakePin)
This function writes to WAKE pin event capture enable register (0x4C). Local wake-up is enabled via b...
sbc_wtdog_stat_fnms_t fnms