S32 SDK

#include <S32K142.h>

Data Fields

__IO uint32_t MCR
 
__IO uint32_t CTRL1
 
__IO uint32_t TIMER
 
uint8_t RESERVED_0 [4]
 
__IO uint32_t RXMGMASK
 
__IO uint32_t RX14MASK
 
__IO uint32_t RX15MASK
 
__IO uint32_t ECR
 
__IO uint32_t ESR1
 
uint8_t RESERVED_1 [4]
 
__IO uint32_t IMASK1
 
uint8_t RESERVED_2 [4]
 
__IO uint32_t IFLAG1
 
__IO uint32_t CTRL2
 
__I uint32_t ESR2
 
uint8_t RESERVED_3 [8]
 
__I uint32_t CRCR
 
__IO uint32_t RXFGMASK
 
__I uint32_t RXFIR
 
__IO uint32_t CBT
 
uint8_t RESERVED_4 [44]
 
__IO uint32_t RAMn [CAN_RAMn_COUNT]
 
uint8_t RESERVED_5 [1536]
 
__IO uint32_t RXIMR [CAN_RXIMR_COUNT]
 
uint8_t RESERVED_6 [576]
 
__IO uint32_t CTRL1_PN
 
__IO uint32_t CTRL2_PN
 
__IO uint32_t WU_MTC
 
__IO uint32_t FLT_ID1
 
__IO uint32_t FLT_DLC
 
__IO uint32_t PL1_LO
 
__IO uint32_t PL1_HI
 
__IO uint32_t FLT_ID2_IDMASK
 
__IO uint32_t PL2_PLMASK_LO
 
__IO uint32_t PL2_PLMASK_HI
 
uint8_t RESERVED_7 [24]
 
struct {
   __I uint32_t   WMBn_CS
 
   __I uint32_t   WMBn_ID
 
   __I uint32_t   WMBn_D03
 
   __I uint32_t   WMBn_D47
 
WMB [CAN_WMB_COUNT]
 
uint8_t RESERVED_8 [128]
 
__IO uint32_t FDCTRL
 
__IO uint32_t FDCBT
 
__I uint32_t FDCRC
 

Detailed Description

CAN - Register Layout Typedef

Definition at line 854 of file S32K142.h.

Field Documentation

__IO uint32_t CBT

CAN Bit Timing Register, offset: 0x50

Definition at line 874 of file S32K142.h.

__I uint32_t CRCR

CRC Register, offset: 0x44

Definition at line 871 of file S32K142.h.

__IO uint32_t CTRL1

Control 1 register, offset: 0x4

Definition at line 856 of file S32K142.h.

__IO uint32_t CTRL1_PN

Pretended Networking Control 1 Register, offset: 0xB00

Definition at line 880 of file S32K142.h.

__IO uint32_t CTRL2

Control 2 register, offset: 0x34

Definition at line 868 of file S32K142.h.

__IO uint32_t CTRL2_PN

Pretended Networking Control 2 Register, offset: 0xB04

Definition at line 881 of file S32K142.h.

__IO uint32_t ECR

Error Counter, offset: 0x1C

Definition at line 862 of file S32K142.h.

__IO uint32_t ESR1

Error and Status 1 register, offset: 0x20

Definition at line 863 of file S32K142.h.

__I uint32_t ESR2

Error and Status 2 register, offset: 0x38

Definition at line 869 of file S32K142.h.

__IO uint32_t FDCBT

CAN FD Bit Timing Register, offset: 0xC04

Definition at line 899 of file S32K142.h.

__I uint32_t FDCRC

CAN FD CRC Register, offset: 0xC08

Definition at line 900 of file S32K142.h.

__IO uint32_t FDCTRL

CAN FD Control Register, offset: 0xC00

Definition at line 898 of file S32K142.h.

__IO uint32_t FLT_DLC

Pretended Networking DLC Filter Register, offset: 0xB10

Definition at line 884 of file S32K142.h.

__IO uint32_t FLT_ID1

Pretended Networking ID Filter 1 Register, offset: 0xB0C

Definition at line 883 of file S32K142.h.

__IO uint32_t FLT_ID2_IDMASK

Pretended Networking ID Filter 2 Register / ID Mask Register, offset: 0xB1C

Definition at line 887 of file S32K142.h.

__IO uint32_t IFLAG1

Interrupt Flags 1 register, offset: 0x30

Definition at line 867 of file S32K142.h.

__IO uint32_t IMASK1

Interrupt Masks 1 register, offset: 0x28

Definition at line 865 of file S32K142.h.

__IO uint32_t MCR

Module Configuration Register, offset: 0x0

Definition at line 855 of file S32K142.h.

__IO uint32_t PL1_HI

Pretended Networking Payload High Filter 1 Register, offset: 0xB18

Definition at line 886 of file S32K142.h.

__IO uint32_t PL1_LO

Pretended Networking Payload Low Filter 1 Register, offset: 0xB14

Definition at line 885 of file S32K142.h.

__IO uint32_t PL2_PLMASK_HI

Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register, offset: 0xB24

Definition at line 889 of file S32K142.h.

__IO uint32_t PL2_PLMASK_LO

Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register, offset: 0xB20

Definition at line 888 of file S32K142.h.

__IO uint32_t RAMn[CAN_RAMn_COUNT]

Embedded RAM, array offset: 0x80, array step: 0x4

Definition at line 876 of file S32K142.h.

uint8_t RESERVED_0[4]

Definition at line 858 of file S32K142.h.

uint8_t RESERVED_1[4]

Definition at line 864 of file S32K142.h.

uint8_t RESERVED_2[4]

Definition at line 866 of file S32K142.h.

uint8_t RESERVED_3[8]

Definition at line 870 of file S32K142.h.

uint8_t RESERVED_4[44]

Definition at line 875 of file S32K142.h.

uint8_t RESERVED_5[1536]

Definition at line 877 of file S32K142.h.

uint8_t RESERVED_6[576]

Definition at line 879 of file S32K142.h.

uint8_t RESERVED_7[24]

Definition at line 890 of file S32K142.h.

uint8_t RESERVED_8[128]

Definition at line 897 of file S32K142.h.

__IO uint32_t RX14MASK

Rx 14 Mask register, offset: 0x14

Definition at line 860 of file S32K142.h.

__IO uint32_t RX15MASK

Rx 15 Mask register, offset: 0x18

Definition at line 861 of file S32K142.h.

__IO uint32_t RXFGMASK

Rx FIFO Global Mask register, offset: 0x48

Definition at line 872 of file S32K142.h.

__I uint32_t RXFIR

Rx FIFO Information Register, offset: 0x4C

Definition at line 873 of file S32K142.h.

__IO uint32_t RXIMR[CAN_RXIMR_COUNT]

Rx Individual Mask Registers, array offset: 0x880, array step: 0x4

Definition at line 878 of file S32K142.h.

__IO uint32_t RXMGMASK

Rx Mailboxes Global Mask Register, offset: 0x10

Definition at line 859 of file S32K142.h.

__IO uint32_t TIMER

Free Running Timer, offset: 0x8

Definition at line 857 of file S32K142.h.

struct { ... } WMB[CAN_WMB_COUNT]
__I uint32_t WMBn_CS

Wake Up Message Buffer Register for C/S, array offset: 0xB40, array step: 0x10

Definition at line 892 of file S32K142.h.

__I uint32_t WMBn_D03

Wake Up Message Buffer Register for Data 0-3, array offset: 0xB48, array step: 0x10

Definition at line 894 of file S32K142.h.

__I uint32_t WMBn_D47

Wake Up Message Buffer Register Data 4-7, array offset: 0xB4C, array step: 0x10

Definition at line 895 of file S32K142.h.

__I uint32_t WMBn_ID

Wake Up Message Buffer Register for ID, array offset: 0xB44, array step: 0x10

Definition at line 893 of file S32K142.h.

__IO uint32_t WU_MTC

Pretended Networking Wake Up Match Register, offset: 0xB08

Definition at line 882 of file S32K142.h.


The documentation for this struct was generated from the following file: