74 #define TX_WATERMARK 2U
75 #define RX_WATERMARK 5U
77 #define BIT_CLK_SWAP false
78 #define BIT_CLK_AS_EXTERNAL false
79 #define WORD_FLAG_INDEX 0
80 #define CONT_ON_ERROR true
82 #define SYNC_ON_DEMAND true
83 #define TX_FIFO_SIZE (FIFO_SIZE-TX_WATERMARK)
84 #define RX_FIFO_SIZE (RX_WATERMARK+1U)
89 static void SAI_DRV_TxResetVar(uint32_t instNum);
90 static void SAI_DRV_RxResetVar(uint32_t instNum);
91 static void SAI_DRV_CompleteSendDataUsingDma(
void * parameter,
93 static void SAI_DRV_CompleteReceiveDataUsingDma(
void * parameter,
95 static void SAI_DRV_TxIRQ(uint32_t instNum);
96 static void SAI_DRV_RxIRQ(uint32_t instNum);
97 static void SAI_DRV_SendInt(uint32_t instNum,
98 const uint8_t* data[],
100 static void SAI_DRV_SendDma(uint32_t instNum,
101 const uint8_t* data[],
103 static void SAI_DRV_ReceiveDma(uint32_t instNum,
106 static void SAI_DRV_ReceiveInt(uint32_t instNum,
109 void SAI0_Tx_IRQHandler(
void);
110 void SAI0_Rx_IRQHandler(
void);
111 void SAI1_Tx_IRQHandler(
void);
112 void SAI1_Rx_IRQHandler(
void);
114 #if (SAI_INSTANCE_COUNT > 0U)
116 void SAI0_Tx_IRQHandler(
void)
120 void SAI0_Rx_IRQHandler(
void)
126 #if (SAI_INSTANCE_COUNT > 1U)
128 void SAI1_Tx_IRQHandler(
void)
132 void SAI1_Rx_IRQHandler(
void)
139 #if (SAI_INSTANCE_COUNT == 2U)
141 #elif (SAI_INSTANCE_COUNT == 3U)
144 #if (SAI_INSTANCE_COUNT == 2U)
146 #elif (SAI_INSTANCE_COUNT == 3U)
166 static inline uint32_t TO_BIT(
bool x)
168 return x ? 1UL : 0UL;
177 static void SAI_DRV_TxResetVar(uint32_t instNum)
180 for (j = 0; j < sai_channel_count[instNum]; j++)
182 TxState[instNum]->ChnState[j].data = NULL;
183 TxState[instNum]->ChnState[j].count = 0U;
187 TxState[instNum]->Blocking =
false;
188 TxState[instNum]->Callback = NULL;
189 TxState[instNum]->NextChn = 0U;
198 static void SAI_DRV_RxResetVar(uint32_t instNum)
201 for (j = 0; j < sai_channel_count[instNum]; j++)
203 RxState[instNum]->ChnState[j].data = NULL;
204 RxState[instNum]->ChnState[j].count = 0U;
208 RxState[instNum]->Blocking =
false;
209 RxState[instNum]->Callback = NULL;
210 RxState[instNum]->NextChn = 0U;
219 static void SAI_DRV_CompleteSendDataUsingDma(
void * parameter,
222 uint32_t instNum = ((uint32_t)parameter & 0xffUL);
223 uint8_t ChnNum = (uint8_t)(((uint32_t)parameter >> 16UL) & 0xffUL);
224 uint8_t DmaChn = (uint8_t)(((uint32_t)parameter >> 8UL) & 0xffUL);
237 for (i = 0; i < sai_channel_count[instNum]; i++)
239 if (SAI_DRV_IsTxChannelEnabled(inst, i))
243 TxState[instNum]->ChnState[i].count = 0U;
250 TxState[instNum]->ChnState[0].count = 0U;
257 TxState[instNum]->ChnState[ChnNum].count = 0U;
261 for (i = 0; i < sai_channel_count[instNum]; i++)
263 if (SAI_DRV_IsTxChannelEnabled(inst, i))
265 if (TxState[instNum]->ChnState[i].count > 0U)
281 SAI_DRV_TxDisableFifoReqDma(inst);
286 if (TxState[instNum]->Blocking)
293 if (TxState[instNum]->Callback != NULL)
307 static void SAI_DRV_CompleteReceiveDataUsingDma(
void * parameter,
310 uint32_t instNum = ((uint32_t)parameter & 0xffUL);
311 uint8_t ChnNum = (uint8_t)(((uint32_t)parameter >> 16U) & 0xffUL);
312 uint8_t DmaChn = (uint8_t)(((uint32_t)parameter >> 8U) & 0xffUL);
325 for (i = 0; i < sai_channel_count[instNum]; i++)
327 if (SAI_DRV_IsRxChannelEnabled(inst, i))
331 RxState[instNum]->ChnState[i].count = 0U;
338 RxState[instNum]->ChnState[0].count = 0U;
345 RxState[instNum]->ChnState[ChnNum].count = 0U;
349 for (i = 0; i < sai_channel_count[instNum]; i++)
351 if (SAI_DRV_IsRxChannelEnabled(inst, i))
353 if (RxState[instNum]->ChnState[i].count > 0U)
369 SAI_DRV_RxDisableFifoReqDma(inst);
374 if (RxState[instNum]->Blocking)
381 if (RxState[instNum]->Callback != NULL)
397 static void SAI_DRV_TxIRQ(uint32_t instNum)
404 if (SAI_DRV_TxGetFifoReqFlag(inst))
411 for (i = 0U; i < sai_channel_count[instNum]; i++)
413 if (SAI_DRV_IsTxChannelEnabled(inst, i))
415 if (TxState[instNum]->ChnState[0].count < TX_FIFO_SIZE)
417 temp = TxState[instNum]->ChnState[0].count;
423 for (j = 0U; j < temp; j++)
425 if (TxState[instNum]->ElementSize == 1U)
427 SAI_DRV_TxWrite(inst, i, (uint32_t)*TxState[instNum]->ChnState[TxState[instNum]->NextChn].data);
429 else if (TxState[instNum]->ElementSize == 2U)
431 SAI_DRV_TxWrite(inst, i, (uint32_t)*((uint16_t*) TxState[instNum]->ChnState[TxState[instNum]->NextChn].data));
433 else if (TxState[instNum]->ElementSize == 4U)
435 SAI_DRV_TxWrite(inst, i, *((uint32_t*) TxState[instNum]->ChnState[TxState[instNum]->NextChn].data));
441 TxState[instNum]->ChnState[TxState[instNum]->NextChn].data += TxState[instNum]->ElementSize;
442 TxState[instNum]->NextChn++;
443 if (TxState[instNum]->NextChn == TxState[instNum]->ChannelCount)
445 TxState[instNum]->NextChn = 0U;
448 if (TxState[instNum]->ChnState[0].count <= TX_FIFO_SIZE)
451 TxState[instNum]->ChnState[0].count = 0;
455 TxState[instNum]->ChnState[0].count -= TX_FIFO_SIZE;
463 if (TxState[instNum]->ChnState[0].count < TX_FIFO_SIZE)
465 temp = TxState[instNum]->ChnState[0].count;
471 for (j = 0U; j < temp; j++)
473 for (i = 0U; i < sai_channel_count[instNum]; i++)
475 if (SAI_DRV_IsTxChannelEnabled(inst, i))
477 if (TxState[instNum]->ElementSize == 1U)
479 SAI_DRV_TxWrite(inst, i, (uint32_t)*TxState[instNum]->ChnState[0].data);
481 else if (TxState[instNum]->ElementSize == 2U)
483 SAI_DRV_TxWrite(inst, i, (uint32_t)*((uint16_t*) TxState[instNum]->ChnState[0U].data));
485 else if (TxState[instNum]->ElementSize == 4U)
487 SAI_DRV_TxWrite(inst, i, *((uint32_t*) TxState[instNum]->ChnState[0U].data));
493 TxState[instNum]->ChnState[0U].data += TxState[instNum]->ElementSize;
497 if (TxState[instNum]->ChnState[0].count <= TX_FIFO_SIZE)
500 TxState[instNum]->ChnState[0].count = 0;
504 TxState[instNum]->ChnState[0].count -= TX_FIFO_SIZE;
509 if (TxState[instNum]->ChnState[0].count < TX_FIFO_SIZE)
511 temp = TxState[instNum]->ChnState[0].count;
517 for (i = 0U; i < sai_channel_count[instNum]; i++)
519 if (SAI_DRV_IsTxChannelEnabled(inst, i))
521 for (j = 0U; j < temp; j++)
523 if (TxState[instNum]->ElementSize == 1U)
525 SAI_DRV_TxWrite(inst, i, (uint32_t)*TxState[instNum]->ChnState[i].data);
527 else if (TxState[instNum]->ElementSize == 2U)
529 SAI_DRV_TxWrite(inst, i, (uint32_t)*((uint16_t*) TxState[instNum]->ChnState[i].data));
531 else if (TxState[instNum]->ElementSize == 4U)
533 SAI_DRV_TxWrite(inst, i, *((uint32_t*) TxState[instNum]->ChnState[i].data));
539 TxState[instNum]->ChnState[i].data += TxState[instNum]->ElementSize;
543 if (TxState[instNum]->ChnState[0].count <= TX_FIFO_SIZE)
546 TxState[instNum]->ChnState[0].count = 0;
550 TxState[instNum]->ChnState[0].count -= TX_FIFO_SIZE;
556 SAI_DRV_TxDisableFifoReqInt(inst);
557 if (TxState[instNum]->Blocking)
563 if (TxState[instNum]->Callback != NULL)
571 if (TxState[instNum]->Callback != NULL)
573 if (SAI_DRV_TxGetFifoErrorFlag(inst))
575 for (i = 0; i < sai_channel_count[instNum]; i++)
577 if (SAI_DRV_IsTxChannelEnabled(inst, i))
579 if (SAI_DRV_IsTxFifoEmpty(inst, i))
587 if (SAI_DRV_TxGetWordStartFlag(inst))
592 if (SAI_DRV_TxGetSyncErrorFlag(inst))
608 static void SAI_DRV_RxIRQ(uint32_t instNum)
615 if (SAI_DRV_RxGetFifoReqFlag(inst))
622 for (i = 0U; i < sai_channel_count[instNum]; i++)
624 if (SAI_DRV_IsRxChannelEnabled(inst, i))
626 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
628 temp = RxState[instNum]->ChnState[0].count;
634 for (j = 0U; j < temp; j++)
636 if (RxState[instNum]->ElementSize == 1U)
638 *RxState[instNum]->ChnState[RxState[instNum]->NextChn].data = (uint8_t) SAI_DRV_RxRead(inst, i);
640 else if (RxState[instNum]->ElementSize == 2U)
642 *(uint16_t*)RxState[instNum]->ChnState[RxState[instNum]->NextChn].data = (uint16_t) SAI_DRV_RxRead(inst, i);
644 else if (RxState[instNum]->ElementSize == 4U)
646 *(uint32_t*)RxState[instNum]->ChnState[RxState[instNum]->NextChn].data = SAI_DRV_RxRead(inst, i);
652 RxState[instNum]->ChnState[RxState[instNum]->NextChn].data += RxState[instNum]->ElementSize;
653 RxState[instNum]->NextChn++;
654 if (RxState[instNum]->NextChn == RxState[instNum]->ChannelCount)
656 RxState[instNum]->NextChn = 0U;
659 if (RxState[instNum]->ChnState[0].count <= RX_FIFO_SIZE)
662 RxState[instNum]->ChnState[0].count = 0;
666 RxState[instNum]->ChnState[0].count -= RX_FIFO_SIZE;
667 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
669 SAI_DRV_RxSetWatermark(inst, (uint8_t)(RxState[instNum]->ChnState[0].count - 1UL));
678 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
680 temp = RxState[instNum]->ChnState[0].count;
686 for (j = 0U; j < temp; j++)
688 for (i = 0U; i < sai_channel_count[instNum]; i++)
690 if (SAI_DRV_IsRxChannelEnabled(inst, i))
692 if (RxState[instNum]->ElementSize == 1U)
694 *RxState[instNum]->ChnState[0U].data = (uint8_t) SAI_DRV_RxRead(inst, i);
696 else if (RxState[instNum]->ElementSize == 2U)
698 *(uint16_t*)RxState[instNum]->ChnState[0U].data = (uint16_t) SAI_DRV_RxRead(inst, i);
700 else if (RxState[instNum]->ElementSize == 4U)
702 *(uint32_t*)RxState[instNum]->ChnState[0U].data = SAI_DRV_RxRead(inst, i);
708 RxState[instNum]->ChnState[0U].data += RxState[instNum]->ElementSize;
712 if (RxState[instNum]->ChnState[0].count <= RX_FIFO_SIZE)
715 RxState[instNum]->ChnState[0].count = 0;
719 RxState[instNum]->ChnState[0].count -= RX_FIFO_SIZE;
720 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
722 SAI_DRV_RxSetWatermark(inst, (uint8_t)(RxState[instNum]->ChnState[0].count - 1UL));
728 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
730 temp = RxState[instNum]->ChnState[0].count;
736 for (i = 0U; i < sai_channel_count[instNum]; i++)
738 if (SAI_DRV_IsRxChannelEnabled(inst, i))
740 for (j = 0U; j < temp; j++)
742 if (RxState[instNum]->ElementSize == 1U)
744 *RxState[instNum]->ChnState[i].data = (uint8_t) SAI_DRV_RxRead(inst, i);
746 else if (RxState[instNum]->ElementSize == 2U)
748 *(uint16_t*)RxState[instNum]->ChnState[i].data = (uint16_t) SAI_DRV_RxRead(inst, i);
750 else if (RxState[instNum]->ElementSize == 4U)
752 *(uint32_t*)RxState[instNum]->ChnState[i].data = SAI_DRV_RxRead(inst, i);
758 RxState[instNum]->ChnState[i].data += RxState[instNum]->ElementSize;
762 if (RxState[instNum]->ChnState[0].count <= RX_FIFO_SIZE)
765 RxState[instNum]->ChnState[0].count = 0;
769 RxState[instNum]->ChnState[0].count -= RX_FIFO_SIZE;
770 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
772 SAI_DRV_RxSetWatermark(inst, (uint8_t)(RxState[instNum]->ChnState[0].count - 1UL));
779 SAI_DRV_RxSetWatermark(inst, RX_WATERMARK);
780 SAI_DRV_RxDisableFifoReqInt(inst);
781 if (RxState[instNum]->Blocking)
787 if (RxState[instNum]->Callback != NULL)
795 if (RxState[instNum]->Callback != NULL)
797 if (SAI_DRV_RxGetFifoErrorFlag(inst))
799 for (i = 0; i < sai_channel_count[instNum]; i++)
801 if (SAI_DRV_IsRxChannelEnabled(inst, i))
803 if (SAI_DRV_IsRxFifoFull(inst, i))
811 if (SAI_DRV_RxGetWordStartFlag(inst))
816 if (SAI_DRV_RxGetSyncErrorFlag(inst))
830 static void SAI_DRV_SendInt(uint32_t instNum,
831 const uint8_t* data[],
841 for (i = 0; i < TxState[instNum]->ChannelCount; i++)
845 TxState[instNum]->ChnState[i].data = (uint8_t*) data[i];
847 TxState[instNum]->ChnState[0].count = count * TxState[instNum]->ChannelCount;
853 TxState[instNum]->ChnState[0].data = (uint8_t*) data[0];
854 TxState[instNum]->ChnState[0].count = count;
858 for (i = 0; i < sai_channel_count[instNum]; i++)
860 if (SAI_DRV_IsTxChannelEnabled(inst, i))
864 TxState[instNum]->ChnState[i].data = (uint8_t*) data[c];
868 TxState[instNum]->ChnState[0].count = count;
870 SAI_DRV_TxEnableFifoReqInt(inst);
879 static void SAI_DRV_SendDma(uint32_t instNum,
880 const uint8_t* data[],
890 if (TxState[instNum]->ElementSize == 1U)
894 else if (TxState[instNum]->ElementSize == 2U)
898 else if (TxState[instNum]->ElementSize == 4U)
910 for (i = 0; i < sai_channel_count[instNum]; i++)
912 if (SAI_DRV_IsTxChannelEnabled(inst, i))
915 TxState[instNum]->ChnState[i].count = count;
917 (uint32_t)data[c], (uint32_t)(&(inst->
TDR[i])), xferSize,
918 TxState[instNum]->ElementSize, count,
true);
923 (
void*)(instNum | ((uint32_t)i << 16U) | ((uint32_t)c << 8U)));
933 for (i = 0; i < sai_channel_count[instNum]; i++)
935 if (SAI_DRV_IsTxChannelEnabled(inst, i))
940 temp = count * numChan;
941 TxState[instNum]->ChnState[0].count = count;
944 (uint32_t)data[0], (uint32_t)(&(inst->
TDR[0])), xferSize,
945 TxState[instNum]->ElementSize, temp,
true);
959 SAI_DRV_TxEnableFifoReqDma(inst);
968 static void SAI_DRV_ReceiveInt(uint32_t instNum,
979 for (i = 0; i < RxState[instNum]->ChannelCount; i++)
982 RxState[instNum]->ChnState[i].data = data[i];
984 RxState[instNum]->ChnState[0].count = RxState[instNum]->ChannelCount * count;
985 if (RxState[instNum]->ChnState[0].count < RX_FIFO_SIZE)
987 SAI_DRV_RxSetWatermark(inst, (uint8_t)(RxState[instNum]->ChnState[0].count - 1UL));
991 SAI_DRV_RxSetWatermark(inst, RX_WATERMARK);
997 RxState[instNum]->ChnState[0].data = data[0];
998 RxState[instNum]->ChnState[0].count = count;
999 if (count < RX_FIFO_SIZE)
1001 SAI_DRV_RxSetWatermark(inst, (uint8_t)(RxState[instNum]->ChnState[0].count - 1UL));
1005 SAI_DRV_RxSetWatermark(inst, RX_WATERMARK);
1010 for (i = 0; i < sai_channel_count[instNum]; i++)
1012 if (SAI_DRV_IsRxChannelEnabled(inst, i))
1015 RxState[instNum]->ChnState[i].data = data[c];
1019 RxState[instNum]->ChnState[0].count = count;
1020 if (count < RX_FIFO_SIZE)
1022 SAI_DRV_RxSetWatermark(inst, (uint8_t) (count - 1UL));
1026 SAI_DRV_RxSetWatermark(inst, RX_WATERMARK);
1029 SAI_DRV_RxEnableFifoReqInt(inst);
1038 static void SAI_DRV_ReceiveDma(uint32_t instNum,
1046 uint8_t numChan = 0;
1049 if (RxState[instNum]->ElementSize == 1U)
1053 else if (RxState[instNum]->ElementSize == 2U)
1057 else if (RxState[instNum]->ElementSize == 4U)
1069 for (i = 0; i < sai_channel_count[instNum]; i++)
1071 if (SAI_DRV_IsRxChannelEnabled(inst, i))
1074 RxState[instNum]->ChnState[i].count = count;
1076 (uint32_t)(&(inst->
RDR[i])), (uint32_t)data[c], xferSize,
1077 RxState[instNum]->ElementSize, count,
true);
1082 (
void*)(instNum | ((uint32_t)i << 16U) | ((uint32_t)c << 8U)));
1092 for (i = 0; i < sai_channel_count[instNum]; i++)
1094 if (SAI_DRV_IsRxChannelEnabled(inst, i))
1099 temp = count * numChan;
1100 RxState[instNum]->ChnState[0].count = count;
1103 (uint32_t)(&(inst->
RDR[0])), (uint32_t)data[0], xferSize,
1104 RxState[instNum]->ElementSize, temp,
true);
1118 SAI_DRV_RxEnableFifoReqDma(inst);
1154 #ifdef DEV_ERROR_DETECT
1155 uint32_t temp = inst->
RCSR;
1156 uint32_t temp2 = inst->
RCR2;
1168 uint32_t SourceClock = 0U;
1169 uint32_t divisor = 0U;
1170 uint8_t CombineMode = 0U;
1173 uint8_t channel = 0U;
1193 TxState[instNum] = StateAlloc;
1194 SAI_DRV_TxResetVar(instNum);
1201 divisor = ((SourceClock / saiUserConfig->
BitClkFreq) / 2UL) - 1UL;
1209 divisor = ((uint32_t)saiUserConfig->
BitClkDiv / 2UL) - 1UL;
1212 TxState[instNum]->ElementSize = saiUserConfig->
ElementSize;
1213 TxState[instNum]->XferType = saiUserConfig->
TransferType;
1214 TxState[instNum]->mux = saiUserConfig->
MuxMode;
1217 for (i = 0; i < sai_channel_count[instNum]; i++)
1219 TxState[instNum]->DmaChannel[i] = saiUserConfig->
DmaChannel[i];
1221 CombineMode = (uint8_t)saiUserConfig->
MuxMode;
1226 TxState[instNum]->ChannelCount = saiUserConfig->
ChannelCount;
1235 TxState[instNum]->Callback = saiUserConfig->
callback;
1288 #ifdef DEV_ERROR_DETECT
1289 uint32_t temp = inst->
TCSR;
1290 uint32_t temp2 = inst->
TCR2;
1302 uint32_t SourceClock = 0U;
1303 uint32_t divisor = 0U;
1304 uint8_t CombineMode = 0U;
1307 uint8_t channel = 0U;
1327 RxState[instNum] = StateAlloc;
1328 SAI_DRV_RxResetVar(instNum);
1335 divisor = ((SourceClock / saiUserConfig->
BitClkFreq) / 2UL) - 1UL;
1343 divisor = ((uint32_t)saiUserConfig->
BitClkDiv / 2UL) - 1UL;
1346 RxState[instNum]->ElementSize = saiUserConfig->
ElementSize;
1347 RxState[instNum]->XferType = saiUserConfig->
TransferType;
1348 RxState[instNum]->mux = saiUserConfig->
MuxMode;
1351 for (i = 0; i < sai_channel_count[instNum]; i++)
1353 RxState[instNum]->DmaChannel[i] = saiUserConfig->
DmaChannel[i];
1355 CombineMode = (uint8_t)saiUserConfig->
MuxMode;
1360 RxState[instNum]->ChannelCount = saiUserConfig->
ChannelCount;
1369 RxState[instNum]->Callback = saiUserConfig->
callback;
1423 SAI_DRV_TxResetVar(instNum);
1447 SAI_DRV_RxResetVar(instNum);
1461 const SAI_Type* inst = SAIBase[instNum];
1463 uint32_t SourceClock = 0U;
1464 uint32_t ClockSetting;
1469 #ifdef DEV_ERROR_DETECT
1470 uint32_t temp = inst->
RCR2;
1488 return SourceClock / div;
1502 const SAI_Type* inst = SAIBase[instNum];
1504 uint32_t SourceClock = 0U;
1505 uint32_t ClockSetting;
1510 #ifdef DEV_ERROR_DETECT
1511 uint32_t temp = inst->
TCR2;
1530 return SourceClock / div;
1544 const SAI_Type* inst = SAIBase[instNum];
1559 const SAI_Type* inst = SAIBase[instNum];
1602 const uint8_t* data[],
1612 TxState[instNum]->Blocking =
true;
1614 osifError =
OSIF_SemaWait(&TxState[instNum]->Sema, timeout);
1615 TxState[instNum]->Blocking =
false;
1625 res = TxState[instNum]->status;
1639 const uint8_t* data[],
1645 if (TxState[instNum]->XferType ==
SAI_DMA)
1647 SAI_DRV_SendDma(instNum, data, count);
1651 SAI_DRV_SendInt(instNum, data, count);
1667 uint32_t *countRemain)
1672 status_t CurStatus = TxState[instNum]->status;
1676 if (countRemain != NULL)
1684 if (countRemain != NULL)
1692 if (TxState[instNum]->XferType ==
SAI_DMA)
1694 if (countRemain != NULL)
1701 if (countRemain != NULL)
1703 *countRemain = TxState[instNum]->ChnState[0].count;
1710 if (countRemain != NULL)
1712 *countRemain = TxState[instNum]->ChnState[0].count;
1742 if (TxState[instNum]->XferType ==
SAI_DMA)
1746 SAI_DRV_TxDisableFifoReqDma(inst);
1750 for (i = 0; i < sai_channel_count[instNum]; i++)
1752 if (SAI_DRV_IsTxChannelEnabled(inst, i))
1766 SAI_DRV_TxDisableFifoReqInt(inst);
1768 SAI_DRV_TxResetFifo(inst);
1769 if (TxState[instNum]->Blocking)
1795 RxState[instNum]->Blocking =
true;
1797 osifError =
OSIF_SemaWait(&RxState[instNum]->Sema, timeout);
1798 RxState[instNum]->Blocking =
false;
1808 res = RxState[instNum]->status;
1828 if (RxState[instNum]->XferType ==
SAI_DMA)
1830 SAI_DRV_ReceiveDma(instNum, data, count);
1834 SAI_DRV_ReceiveInt(instNum, data, count);
1850 uint32_t *countRemain)
1856 status_t CurStatus = RxState[instNum]->status;
1860 if (countRemain != NULL)
1868 if (countRemain != NULL)
1876 if (RxState[instNum]->XferType ==
SAI_DMA)
1878 if (countRemain != NULL)
1885 if (countRemain != NULL)
1887 *countRemain = RxState[instNum]->ChnState[0].count;
1894 if (countRemain != NULL)
1896 *countRemain = RxState[instNum]->ChnState[0].count;
1926 if (RxState[instNum]->XferType ==
SAI_DMA)
1930 SAI_DRV_RxDisableFifoReqDma(inst);
1934 for (i = 0; i < sai_channel_count[instNum]; i++)
1936 if (SAI_DRV_IsRxChannelEnabled(inst, i))
1950 SAI_DRV_RxDisableFifoReqInt(inst);
1952 SAI_DRV_RxResetFifo(inst);
1953 if (RxState[instNum]->Blocking)
void SAI_DRV_AbortSending(uint32_t instNum)
Abort an ongoing transfer.
__O uint32_t TDR[SAI_TDR_COUNT]
sai_transfer_type_t TransferType
#define SAI_RCR2_MSEL_MASK
void SAI_DRV_RxInit(uint32_t instNum, const sai_user_config_t *saiUserConfig, sai_state_t *StateAlloc)
Initialize the receiver of driver.
#define SAI_TCR2_DIV_MASK
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t SAI_DRV_GetSendingStatus(uint32_t instNum, uint32_t *countRemain)
Get status of a non-blocking transfer.
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t channel)
Returns the remaining major loop iteration count.
#define SAI_TCSR_FEF_SHIFT
#define SAI_RCR4_FPACK(x)
#define SAI_TCSR_SEF_SHIFT
#define SAI_RCR2_DIV_SHIFT
#define SAI_RCR2_MSEL_SHIFT
uint32_t SAI_DRV_RxGetBitClockFreq(uint32_t instNum)
Return true bit clock frequency of receiver.
status_t SAI_DRV_ReceiveBlocking(uint32_t instNum, uint8_t *data[], uint32_t count, uint32_t timeout)
Receive a block of data, return when transfer complete.
void SAI_DRV_RxSetNextMaskWords(uint32_t instNum, uint16_t Words)
Set masked word index of subsequent frames for receiver.
void SAI_DRV_GetDefaultConfig(sai_user_config_t *uc)
Get default config structure for I2S standard. Init config structure for I2S interface: Interrupt mod...
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
sai_transfer_callback_t callback
sai_master_clk_source_t MasterClkSrc
#define SAI_RCSR_SEF_SHIFT
#define SAI_TCR2_DIV_SHIFT
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
IRQn_Type
Defines the Interrupt Numbers definitions.
Structure for internal use. This structure is used by the driver for its internal logic...
#define SAI1_CHANNEL_COUNT
#define SAI_RCSR_FEF_SHIFT
#define SAI_TCSR_WSF_SHIFT
#define SAI_TCR4_CHMOD(x)
uint32_t SAI_DRV_RxGetBitClockDiv(uint32_t instNum)
Return true bit clock divisor of receiver.
#define SAI_TCR2_BCD_MASK
__I uint32_t RDR[SAI_RDR_COUNT]
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
edma_chn_status_t
Channel status for eDMA channel.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
uint8_t DmaChannel[SAI_MAX_CHANNEL_COUNT]
#define SAI_RCR2_BCD_MASK
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
void SAI_DRV_TxInit(uint32_t instNum, const sai_user_config_t *saiUserConfig, sai_state_t *StateAlloc)
Initialize the transmitter of driver.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
clock_names_t
Clock names.
#define SAI_TCR4_FPACK(x)
uint32_t SAI_DRV_TxGetBitClockDiv(uint32_t instNum)
Return true bit clock divisor of transmitter.
#define SAI_TCR4_ONDEM(x)
void SAI_DRV_AbortReceiving(uint32_t instNum)
Abort an ongoing transfer.
void SAI_DRV_RxDeinit(uint32_t instNum)
De-initialize receiver.
void SAI_DRV_Receive(uint32_t instNum, uint8_t *data[], uint32_t count)
Receive a block of data, return immidiately.
void SAI_DRV_TxDeinit(uint32_t instNum)
De-initialize transmitter.
status_t SAI_DRV_SendBlocking(uint32_t instNum, const uint8_t *data[], uint32_t count, uint32_t timeout)
Send a block of data, return when transfer complete.
#define SAI_TCR4_FCOMB(x)
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
#define SAI0_CHANNEL_COUNT
#define SAI_RCR2_SYNC_MASK
status_t SAI_DRV_GetReceivingStatus(uint32_t instNum, uint32_t *countRemain)
Get status of a non-blocking transfer.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
#define SAI_TCR2_MSEL_SHIFT
#define SAI_RCR4_ONDEM(x)
uint32_t SAI_DRV_TxGetBitClockFreq(uint32_t instNum)
Return true bit clock frequency of transmitter.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
#define SAI_RCR4_FCOMB(x)
#define SAI_RCR4_FCONT(x)
void SAI_DRV_TxSetNextMaskWords(uint32_t instNum, uint16_t Words)
Set masked word index of subsequent frames for transmitter.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
#define SAI_RCSR_WSF_SHIFT
#define SAI_RCR2_DIV_MASK
#define SAI_TCR4_FCONT(x)
void SAI_DRV_Send(uint32_t instNum, const uint8_t *data[], uint32_t count)
Send a block of data, return immidiately.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
#define SAI_INSTANCE_COUNT
#define SAI_TCR2_MSEL_MASK
#define SAI_TCR2_SYNC_MASK