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S32K148_features.h
Go to the documentation of this file.
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/*
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** ###################################################################
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** Abstract:
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** Chip specific module features.
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**
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** Copyright (c) 2015 Freescale Semiconductor, Inc.
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** Copyright 2016-2017 NXP
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** All rights reserved.
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**
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** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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** THE POSSIBILITY OF SUCH DAMAGE.
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**
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** ###################################################################
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*/
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#if !defined(S32K148_FEATURES_H)
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#define S32K148_FEATURES_H
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/* ERRATA sections*/
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/* @brief ARM Errata 838869: Store immediate overlapping exception return operation might vector to
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* incorrect interrupt. */
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#define ERRATA_E9005
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/* @brief ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
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* short ISRs are used. */
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#define ERRATA_E6940
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/* @brief Errata workaround: System clock status register may be a erroneous status during the system clock switch.
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* Read system clock source twice. */
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#define ERRATA_E10777
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/* @brief E10792: LPI2C: Slave Transmit Data Flag may incorrectly read as one when TXCFG is zero.
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* Interrupts for transfer data should be enabled after the address valid event is detected and
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* disabled at the end of the transfer. */
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#define ERRATA_E10792
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/* LPI2C module features */
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/* @brief EDMA requests for LPI2C module */
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#define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}, {(uint8_t)EDMA_REQ_LPI2C1_TX, (uint8_t)EDMA_REQ_LPI2C1_RX}}
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/* @brief PCC clocks for LPI2C module */
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#define LPI2C_PCC_CLOCKS {LPI2C0_CLK, LPI2C1_CLK}
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/* PCC module features */
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/* @brief Has InUse feature (register bit PCC[INUSE]). */
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#define FEATURE_PCC_HAS_IN_USE_FEATURE (0)
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/* PORT module features */
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#define FEATURE_PINS_DRIVER_USING_PORT (1)
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/* @brief Has control lock (register bit PCR[LK]). */
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#define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
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/* @brief Has open drain control (register bit PCR[ODE]). */
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#define FEATURE_PINS_HAS_OPEN_DRAIN (0)
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/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
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#define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
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/* @brief Has DMA request (register bit field PCR[IRQC] values). */
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#define FEATURE_PORT_HAS_DMA_REQUEST (1)
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/* @brief Has pull resistor selection available. */
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#define FEATURE_PINS_HAS_PULL_SELECTION (1)
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/* @brief Has slew rate control (register bit PCR[SRE]). */
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#define FEATURE_PINS_HAS_SLEW_RATE (0)
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/* @brief Has passive filter (register bit field PCR[PFE]). */
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#define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
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/* @brief Has drive strength (register bit PCR[DSE]). */
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#define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
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/* @brief Has drive strength control bits*/
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#define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
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/* SOC module features */
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/* @brief PORT availability on the SoC. */
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#define FEATURE_SOC_PORT_COUNT (5)
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#define FEATURE_SOC_SCG_COUNT (1)
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/* @brief Slow IRC low range clock frequency. */
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#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ (2000000U)
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/* @brief Slow IRC high range clock frequency. */
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#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
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/* @brief Fast IRC trimmed clock frequency(48MHz). */
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#define FEATURE_SCG_FIRC_FREQ0 (48000000U)
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/* @brief Fast IRC trimmed clock frequency(52MHz). */
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#define FEATURE_SCG_FIRC_FREQ1 (52000000U)
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/* @brief Fast IRC trimmed clock frequency(56MHz). */
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#define FEATURE_SCG_FIRC_FREQ2 (56000000U)
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/* @brief Fast IRC trimmed clock frequency(60MHz). */
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#define FEATURE_SCG_FIRC_FREQ3 (60000000U)
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/* FLASH module features */
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/* @brief Is of type FTFA. */
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#define FEATURE_FLS_IS_FTFA (0u)
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/* @brief Is of type FTFC. */
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#define FEATURE_FLS_IS_FTFC (1u)
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/* @brief Is of type FTFE. */
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#define FEATURE_FLS_IS_FTFE (0u)
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/* @brief Is of type FTFL. */
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#define FEATURE_FLS_IS_FTFL (0u)
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/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
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#define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
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/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
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#define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
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/* @brief Has EEPROM region protection (register FEPROT). */
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#define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
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/* @brief Has data flash region protection (register FDPROT). */
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#define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
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/* @brief P-Flash block count. */
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#define FEATURE_FLS_PF_BLOCK_COUNT (3u)
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/* @brief P-Flash block size. */
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#define FEATURE_FLS_PF_BLOCK_SIZE (1572864u)
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/* @brief P-Flash sector size. */
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#define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (4096u)
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/* @brief P-Flash write unit size. */
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#define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
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/* @brief P-Flash block swap feature. */
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#define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
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/* @brief Has FlexNVM memory. */
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#define FEATURE_FLS_HAS_FLEX_NVM (1u)
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/* @brief FlexNVM block count. */
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#define FEATURE_FLS_DF_BLOCK_COUNT (1u)
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/* @brief FlexNVM block size. */
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#define FEATURE_FLS_DF_BLOCK_SIZE (524288u)
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/* @brief FlexNVM sector size. */
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#define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (4096u)
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/* @brief FlexNVM write unit size. */
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#define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
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/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
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#define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
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/* @brief Has FlexRAM memory. */
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#define FEATURE_FLS_HAS_FLEX_RAM (1u)
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/* @brief FlexRAM size. */
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#define FEATURE_FLS_FLEX_RAM_SIZE (4096u)
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/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
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#define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
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/* @brief Has 0x00 Read 1s Block command. */
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#define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
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/* @brief Has 0x01 Read 1s Section command. */
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#define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
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/* @brief Has 0x02 Program Check command. */
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#define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
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/* @brief Has 0x03 Read Resource command. */
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#define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
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/* @brief Has 0x06 Program Longword command. */
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#define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
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/* @brief Has 0x07 Program Phrase command. */
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#define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
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/* @brief Has 0x08 Erase Flash Block command. */
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#define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
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/* @brief Has 0x09 Erase Flash Sector command. */
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#define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
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/* @brief Has 0x0B Program Section command. */
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#define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
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/* @brief Has 0x40 Read 1s All Blocks command. */
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#define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
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/* @brief Has 0x41 Read Once command. */
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#define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
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/* @brief Has 0x43 Program Once command. */
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#define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
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/* @brief Has 0x44 Erase All Blocks command. */
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#define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
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/* @brief Has 0x45 Verify Backdoor Access Key command. */
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#define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
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/* @brief Has 0x46 Swap Control command. */
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#define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
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/* @brief Has 0x49 Erase All Blocks unsecure command. */
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#define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
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/* @brief Has 0x80 Program Partition command. */
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#define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
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/* @brief Has 0x81 Set FlexRAM Function command. */
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#define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
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/* @brief P-Flash Erase/Read 1st all block command address alignment. */
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#define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (16u)
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/* @brief P-Flash Erase sector command address alignment. */
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#define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (16u)
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/* @brief P-Flash Program/Verify section command address alignment. */
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#define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (16u)
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/* @brief P-Flash Read resource command address alignment. */
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#define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
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/* @brief P-Flash Program check command address alignment. */
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#define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
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/* @brief P-Flash Program check command address alignment. */
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#define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
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/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
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#define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (16u)
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/* @brief FlexNVM Erase sector command address alignment. */
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#define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (16u)
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/* @brief FlexNVM Program/Verify section command address alignment. */
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#define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (16u)
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/* @brief FlexNVM Read resource command address alignment. */
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#define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
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/* @brief FlexNVM Program check command address alignment. */
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#define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
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/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0000 (0x00080000u)
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/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0011 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0100 (0x000070000u)
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/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1000 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1001 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1010 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1011 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1100 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
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/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
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#define FEATURE_FLS_DF_SIZE_1111 (0x00080000u)
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/* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
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/* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
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/* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0010 (0x1000u)
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/* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
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/* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0100 (0x0400u)
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/* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0101 (0x0200u)
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/* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0110 (0x0100u)
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/* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_0111 (0x0080u)
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/* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1000 (0x0040u)
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/* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1001 (0x0020u)
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/* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
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/* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
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/* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
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/* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
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/* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
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/* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
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#define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
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/* CAN module features */
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/* @brief Frames available in Rx FIFO flag shift */
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#define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
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/* @brief Rx FIFO warning flag shift */
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#define FEATURE_CAN_RXFIFO_WARNING (6U)
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/* @brief Rx FIFO overflow flag shift */
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#define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
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/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */
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#define FEATURE_CAN0_MAX_MB_NUM (32U)
317
/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN1 */
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#define FEATURE_CAN1_MAX_MB_NUM (32U)
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/* @brief Maximum number of Message Buffers supported for payload size 8 for CAN2 */
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#define FEATURE_CAN2_MAX_MB_NUM (32U)
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/* @brief Array of maximum number of Message Buffers supported for payload size 8 for all the CAN instances */
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#define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM, \
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FEATURE_CAN1_MAX_MB_NUM, \
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FEATURE_CAN2_MAX_MB_NUM }
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/* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */
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#define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
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/* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
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#define FEATURE_CAN_MAX_MB_NUM (32U)
329
/* @brief Has Pretending Networking mode */
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#define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
331
/* @brief Has Stuff Bit Count Enable Bit */
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#define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
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/* @brief Has ISO CAN FD Enable Bit */
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#define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
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/* @brief Has Message Buffer Data Size Region 1 */
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#define FEATURE_CAN_HAS_MBDSR1 (0)
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/* @brief Has Message Buffer Data Size Region 2 */
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#define FEATURE_CAN_HAS_MBDSR2 (0)
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/* @brief Has DMA enable (bit field MCR[DMA]). */
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#define FEATURE_CAN_HAS_DMA_ENABLE (1)
341
/* @brief DMA hardware requests for all FlexCAN instances */
342
#define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0, \
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EDMA_REQ_FLEXCAN1, \
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EDMA_REQ_FLEXCAN2 }
345
/* @brief Maximum number of Message Buffers IRQs */
346
#define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
347
/* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */
348
#define FEATURE_CAN_HAS_WAKE_UP_IRQ (1U)
349
/* @brief Message Buffers IRQs */
350
#define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
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CAN_ORed_16_31_MB_IRQS }
352
353
#define FEATURE_CAN_RAM_OFFSET (0x00000080u)
354
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#if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
356
357
#define FEATURE_CAN_PE_CLK_NUM 2U
358
/* @brief FlexCAN clock source */
359
typedef
enum
{
360
FLEXCAN_CLK_SOURCE_SOSCDIV2
= 0U,
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FLEXCAN_CLK_SOURCE_SYS
= 1U
362
}
flexcan_clk_source_t
;
363
/* @brief Clock names for FlexCAN PE clock */
364
#define FLEXCAN_PE_CLOCK_NAMES { FLEXCAN_CLK_SOURCE_SOSCDIV2, FLEXCAN_CLK_SOURCE_SYS }
365
#endif
366
/* @brief Has Self Wake Up mode */
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#define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
368
369
/* LPUART module features */
370
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/* @brief Has extended data register ED. */
372
#define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
373
/* @brief Hardware flow control (RTS, CTS) is supported. */
374
#define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
375
/* @brief Baud rate oversampling is available. */
376
#define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
377
/* @brief Baud rate oversampling is available. */
378
#define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
379
/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
380
#define FEATURE_LPUART_FIFO_SIZE (4U)
381
/* @brief Supports two match addresses to filter incoming frames. */
382
#define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
383
/* @brief Has transmitter/receiver DMA enable bits. */
384
#define FEATURE_LPUART_HAS_DMA_ENABLE (1)
385
/* @brief Flag clearance mask for STAT register. */
386
#define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
387
/* @brief Flag clearance mask for FIFO register. */
388
#define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
389
/* @brief Default oversampling ratio. */
390
#define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
391
/* @brief Default baud rate modulo divisor. */
392
#define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
393
/* @brief Clock names for LPUART. */
394
#define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK, LPUART2_CLK}
395
396
/* FlexIO module features */
397
398
/* @brief Define the maximum number of shifters for any FlexIO instance. */
399
#define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
400
/* @brief Define DMA request names for Flexio. */
401
#define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
402
#define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
403
#define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2_SAI1_RX
404
#define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3_SAI1_TX
405
406
/* LPSPI module features */
407
408
/* @brief DMA instance used for LPSPI module */
409
#define LPSPI_DMA_INSTANCE 0U
410
411
/* @brief DMA instance used for LPI2C module */
412
#define LPI2C_DMA_INSTANCE 0U
413
414
/* PDB module features */
415
416
/* @brief Define the count of supporting ADC channels per each PDB. */
417
#define FEATURE_PDB_ADC_CHANNEL_COUNT (4U)
418
/* @brief Define the count of supporting ADC pre-trigger for each channel. */
419
#define FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (8U)
420
/* @brief Define the count of supporting Pulse-Out outputs per each PDB. */
421
#define FEATURE_PDB_PODLY_COUNT (1U)
422
423
/* Interrupt module features */
424
425
/* @brief Lowest interrupt request number. */
426
#define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
427
/* @brief Highest interrupt request number. */
428
#define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn)
429
430
#define FEATURE_NVIC_PRIO_BITS (4U)
431
/* @brief Has software interrupt. */
432
#define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
433
/* @brief Has pending interrupt state. */
434
#define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
435
/* @brief Has active interrupt state. */
436
#define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u)
437
438
439
/* System Control Block module features */
440
441
/* @brief VECTKEY value so that AIRCR register write is not ignored. */
442
#define FEATURE_SCB_VECTKEY (0x05FAU)
443
444
445
/* SMC module features */
446
447
/* @brief Has stop option (register bit STOPCTRL[STOPO]). */
448
#define FEATURE_SMC_HAS_STOPO (1)
449
/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
450
#define FEATURE_SMC_HAS_PSTOPO (0)
451
/* @brief Has WAIT and VLPW options. */
452
#define FEATURE_SMC_HAS_WAIT_VLPW (0)
453
/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
454
#define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
455
456
457
/* MPU module features */
458
459
/* @brief Specifies hardware revision level. */
460
#define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
461
/* @brief Has process identifier support. */
462
#define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
463
/* @brief Specifies total number of bus masters. */
464
#define FEATURE_MPU_MASTER_COUNT (4U)
465
/* @brief Specifies maximum number of masters which have separated
466
privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K14x).
467
*/
468
#define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
469
/* @brief Specifies maximum number of masters which have only
470
read and write permissions (e.g. master4~7 in S32K14x).
471
*/
472
#define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
473
474
/* @brief Specifies number of set access control right bits for
475
masters which have separated privilege rights for user and
476
supervisor mode accesses (e.g. master0~3 in S32K14x).
477
*/
478
#define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
479
/* @brief Specifies number of set access control right bits for
480
masters which have only read and write permissions(e.g. master4~7 in S32K14x).
481
*/
482
#define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
483
484
/* @brief The MPU Logical Bus Master Number for core bus master. */
485
#define FEATURE_MPU_MASTER_CORE (0U)
486
/* @brief The MPU Logical Bus Master Number for Debugger master. */
487
#define FEATURE_MPU_MASTER_DEBUGGER (1U)
488
/* @brief The MPU Logical Bus Master Number for DMA master. */
489
#define FEATURE_MPU_MASTER_DMA (2U)
490
/* @brief The MPU Logical Bus Master Number for ENET master. */
491
#define FEATURE_MPU_MASTER_ENET (3U)
492
/* @brief Specifies master number. */
493
#define FEATURE_MPU_MASTER \
494
{ \
495
FEATURE_MPU_MASTER_CORE, \
496
FEATURE_MPU_MASTER_DEBUGGER, \
497
FEATURE_MPU_MASTER_DMA, \
498
FEATURE_MPU_MASTER_ENET, \
499
}
500
501
/* @brief Specifies total number of slave ports. */
502
#define FEATURE_MPU_SLAVE_COUNT (5U)
503
/* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */
504
#define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
505
/* @brief The MPU Slave Port Assignment for SRAM back door. */
506
#define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U)
507
/* @brief The MPU Slave Port Assignment for SRAM_L front door. */
508
#define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U)
509
/* @brief The MPU Slave Port Assignment for SRAM_U front door. */
510
#define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U)
511
/* @brief The MPU Slave Port Assignment for QuadSPI. */
512
#define FEATURE_MPU_SLAVE_QUADSPI (4U)
513
/* @brief The MPU Slave Port mask. */
514
#define FEATURE_MPU_SLAVE_MASK (0xF8000000U)
515
#define FEATURE_MPU_SLAVE_SHIFT (27u)
516
#define FEATURE_MPU_SLAVE_WIDTH (5u)
517
#define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
518
519
/* WDOG module features */
520
521
/* @brief The 32-bit value used for unlocking the WDOG. */
522
#define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
523
/* @brief The 32-bit value used for resetting the WDOG counter. */
524
#define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
525
/* @brief The reset value of the timeout register. */
526
#define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
527
/* @brief The value minimum of the timeout register. */
528
#define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
529
/* @brief The reset value of the window register. */
530
#define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
531
/* @brief The mask of the reserved bit in the CS register. */
532
#define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
533
/* @brief The value used to set WDOG source clock from LPO. */
534
#define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
535
/* @brief The first 16-bit value used for unlocking the WDOG. */
536
#define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
537
/* @brief The second 16-bit value used for unlocking the WDOG. */
538
#define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
539
/* @brief The first 16-bit value used for resetting the WDOG counter. */
540
#define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
541
/* @brief The second 16-bit value used for resetting the WDOG counter. */
542
#define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
543
544
545
/* EDMA module features */
546
547
/* @brief Number of EDMA channels. */
548
#define FEATURE_EDMA_MODULE_CHANNELS (16U)
549
/* @brief Number of EDMA channel interrupt lines. */
550
#define FEATURE_CHANNEL_INTERRUPT_LINES (16U)
551
/* @brief Number of EDMA error interrupt lines. */
552
#define FEATURE_ERROR_INTERRUPT_LINES (1U)
553
/* @brief eDMA module has error interrupt. */
554
#define FEATURE_EDMA_HAS_ERROR_IRQ
555
/* @brief eDMA module has separate interrupt lines for each channel. */
556
#define FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
557
/* @brief Conversion from channel index to DCHPRI index. */
558
#define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
559
/* @brief eDMA channel groups count. */
560
#define FEATURE_EDMA_CHANNEL_GROUP_COUNT (1U)
561
/* @brief Number of eDMA channels with asynchronous request capability. */
562
#define FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16U)
563
/* @brief Clock names for eDMA. */
564
#define EDMA_CLOCK_NAMES {SIM_DMA_CLK}
565
566
/* DMAMUX module features */
567
568
/* @brief Number of DMA channels. */
569
#define FEATURE_DMAMUX_MODULE_CHANNELS (16U)
570
/* @brief Has the periodic trigger capability */
571
#define FEATURE_DMAMUX_HAS_TRIG (1)
572
/* @brief Conversion from request source to the actual DMAMUX channel */
573
#define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x) (x)
574
/* @brief Mapping between request source and DMAMUX instance */
575
#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
576
/* @brief Conversion from eDMA channel index to DMAMUX channel. */
577
#define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x) (x)
578
/* @brief Conversion from DMAMUX channel DMAMUX register index. */
579
#define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
580
/* @brief Clock names for DMAMUX. */
581
#define DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
582
590
typedef
enum
{
591
EDMA_REQ_DISABLED
= 0U,
592
ENET_MAC0_TIMER_OR_CH0_CH3
= 1U,
593
EDMA_REQ_LPUART0_RX
= 2U,
594
EDMA_REQ_LPUART0_TX
= 3U,
595
EDMA_REQ_LPUART1_RX
= 4U,
596
EDMA_REQ_LPUART1_TX
= 5U,
597
EDMA_REQ_LPUART2_RX
= 6U,
598
EDMA_REQ_LPUART2_TX
= 7U,
599
EDMA_REQ_LPI2C1_RX
= 8U,
600
EDMA_REQ_LPI2C1_TX
= 9U,
601
EDMA_REQ_FLEXIO_SHIFTER0
= 10U,
602
EDMA_REQ_FLEXIO_SHIFTER1
= 11U,
603
EDMA_REQ_FLEXIO_SHIFTER2_SAI1_RX
= 12U,
604
EDMA_REQ_FLEXIO_SHIFTER3_SAI1_TX
= 13U,
605
EDMA_REQ_LPSPI0_RX
= 14U,
606
EDMA_REQ_LPSPI0_TX
= 15U,
607
EDMA_REQ_LPSPI1_RX
= 16U,
608
EDMA_REQ_LPSPI1_TX
= 17U,
609
EDMA_REQ_LPSPI2_RX
= 18U,
610
EDMA_REQ_LPSPI2_TX
= 19U,
611
EDMA_REQ_FTM1_CHANNEL_0
= 20U,
612
EDMA_REQ_FTM1_CHANNEL_1
= 21U,
613
EDMA_REQ_FTM1_CHANNEL_2
= 22U,
614
EDMA_REQ_FTM1_CHANNEL_3
= 23U,
615
EDMA_REQ_FTM1_CHANNEL_4
= 24U,
616
EDMA_REQ_FTM1_CHANNEL_5
= 25U,
617
EDMA_REQ_FTM1_CHANNEL_6
= 26U,
618
EDMA_REQ_FTM1_CHANNEL_7
= 27U,
619
EDMA_REQ_FTM2_CHANNEL_0
= 28U,
620
EDMA_REQ_FTM2_CHANNEL_1
= 29U,
621
EDMA_REQ_FTM2_CHANNEL_2
= 30U,
622
EDMA_REQ_FTM2_CHANNEL_3
= 31U,
623
EDMA_REQ_FTM2_CHANNEL_4
= 32U,
624
EDMA_REQ_FTM2_CHANNEL_5
= 33U,
625
EDMA_REQ_FTM2_CHANNEL_6
= 34U,
626
EDMA_REQ_FTM2_CHANNEL_7
= 35U,
627
EDMA_REQ_FTM0_OR_CH0_CH7
= 36U,
628
EDMA_REQ_FTM3_OR_CH0_CH7
= 37U,
629
EDMA_REQ_FTM4_OR_CH0_CH7
= 38U,
630
EDMA_REQ_FTM5_OR_CH0_CH7
= 39U,
631
EDMA_REQ_FTM6_OR_CH0_CH7
= 40U,
632
EDMA_REQ_FTM7_OR_CH0_CH7
= 41U,
633
EDMA_REQ_ADC0
= 42U,
634
EDMA_REQ_ADC1
= 43U,
635
EDMA_REQ_LPI2C0_RX
= 44U,
636
EDMA_REQ_LPI2C0_TX
= 45U,
637
EDMA_REQ_PDB0
= 46U,
638
EDMA_REQ_PDB1
= 47U,
639
EDMA_REQ_CMP0
= 48U,
640
EDMA_REQ_PORTA
= 49U,
641
EDMA_REQ_PORTB
= 50U,
642
EDMA_REQ_PORTC
= 51U,
643
EDMA_REQ_PORTD
= 52U,
644
EDMA_REQ_PORTE
= 53U,
645
EDMA_REQ_FLEXCAN0
= 54U,
646
EDMA_REQ_FLEXCAN1
= 55U,
647
EDMA_REQ_FLEXCAN2
= 56U,
648
EDMA_REQ_SAI0_RX
= 57U,
649
EDMA_REQ_SAI0_TX
= 58U,
650
EDMA_REQ_LPTMR0
= 59U,
651
EDMA_REQ_QUADSPI_RX
= 60U,
652
EDMA_REQ_QUADSPI_TX
= 61U,
653
EDMA_REQ_DMAMUX_ALWAYS_ENABLED0
= 62U,
654
EDMA_REQ_DMAMUX_ALWAYS_ENABLED1
= 63U
655
}
dma_request_source_t
;
656
657
/* LPI2C module features */
658
659
/* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */
660
#define LPI2C_HAS_FAST_PLUS_MODE (0U)
661
#define LPI2C_HAS_HIGH_SPEED_MODE (0U)
662
#define LPI2C_HAS_ULTRA_FAST_MODE (0U)
663
664
/* FTM module features */
665
/* @brief Number of PWM channels */
666
#define FEATURE_FTM_CHANNEL_COUNT (8U)
667
/* @brief Number of fault channels */
668
#define FTM_FEATURE_FAULT_CHANNELS (4U)
669
/* @brief Width of control channel */
670
#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
671
/* @brief Output channel offset */
672
#define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
673
/* @brief Max counter value */
674
#define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
675
/* @brief Input capture for single shot */
676
#define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
677
/* @brief Dithering has supported on the generated PWM signals */
678
#define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U)
679
680
/* CRC module features */
681
682
/* @brief CRC module use for S32K1xx. */
683
#define FEATURE_CRC_DRIVER_S32K1xx (1)
684
/* Default CRC bit width */
685
#define CRC_DEFAULT_WIDTH CRC_BITS_16
686
/* Default CRC read transpose */
687
#define CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
688
/* Default polynomial 0x1021U */
689
#define CRC_DEFAULT_POLYNOMIAL (0x1021U)
690
691
/* EWM module features */
692
693
/* @brief First byte of the EWM Service key */
694
#define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U)
695
/* @brief Second byte of the EWM Service key */
696
#define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU)
697
/* @brief EWM Compare High register maximum value */
698
#define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU)
699
/* @brief EWM Compare Low register minimum value */
700
#define FEATURE_EWM_CMPL_MIN_VALUE (0x00U)
701
702
/* CLOCK names */
703
705
typedef
enum
{
706
707
/* Main clocks */
708
CORE_CLK
= 0u,
709
BUS_CLK
= 1u,
710
SLOW_CLK
= 2u,
711
CLKOUT_CLK
= 3u,
713
/* Other internal clocks used by peripherals. */
714
SIRC_CLK
= 4u,
715
FIRC_CLK
= 5u,
716
SOSC_CLK
= 6u,
717
SPLL_CLK
= 7u,
718
RTC_CLKIN_CLK
= 8u,
719
SCG_CLKOUT_CLK
= 9u,
720
SIRCDIV1_CLK
= 10u,
721
SIRCDIV2_CLK
= 11u,
722
FIRCDIV1_CLK
= 12u,
723
FIRCDIV2_CLK
= 13u,
724
SOSCDIV1_CLK
= 14u,
725
SOSCDIV2_CLK
= 15u,
726
SPLLDIV1_CLK
= 16u,
727
SPLLDIV2_CLK
= 17u,
728
SCG_END_OF_CLOCKS
= 18u,
730
/* SIM clocks */
731
SIM_FTM0_CLOCKSEL
= 21u,
732
SIM_FTM1_CLOCKSEL
= 22u,
733
SIM_FTM2_CLOCKSEL
= 23u,
734
SIM_FTM3_CLOCKSEL
= 24u,
735
SIM_FTM4_CLOCKSEL
= 25u,
736
SIM_FTM5_CLOCKSEL
= 26u,
737
SIM_FTM6_CLOCKSEL
= 27u,
738
SIM_FTM7_CLOCKSEL
= 28u,
739
SIM_CLKOUTSELL
= 29u,
740
SIM_RTCCLK_CLK
= 30u,
741
SIM_LPO_CLK
= 31u,
742
SIM_LPO_1K_CLK
= 32u,
743
SIM_LPO_32K_CLK
= 33u,
744
SIM_LPO_128K_CLK
= 34u,
745
SIM_EIM_CLK
= 35u,
746
SIM_ERM_CLK
= 36u,
747
SIM_DMA_CLK
= 37u,
748
SIM_MPU_CLK
= 38u,
749
SIM_MSCM_CLK
= 39u,
750
SIM_END_OF_CLOCKS
= 40u,
752
/* PCC clocks */
753
CMP0_CLK
= 41u,
754
CRC0_CLK
= 42u,
755
DMAMUX0_CLK
= 43u,
756
EWM0_CLK
= 44u,
757
PORTA_CLK
= 45u,
758
PORTB_CLK
= 46u,
759
PORTC_CLK
= 47u,
760
PORTD_CLK
= 48u,
761
PORTE_CLK
= 49u,
762
QSPI0_CLK
= 50u,
763
RTC0_CLK
= 51u,
764
SAI0_CLK
= 52u,
765
SAI1_CLK
= 53u,
766
PCC_END_OF_BUS_CLOCKS
= 54u,
767
FlexCAN0_CLK
= 55u,
768
FlexCAN1_CLK
= 56u,
769
FlexCAN2_CLK
= 57u,
770
PDB0_CLK
= 58u,
771
PDB1_CLK
= 59u,
772
PCC_END_OF_SYS_CLOCKS
= 60u,
773
FTFC0_CLK
= 61u,
774
PCC_END_OF_SLOW_CLOCKS
= 62u,
775
ENET0_CLK
= 63u,
776
FTM0_CLK
= 64u,
777
FTM1_CLK
= 65u,
778
FTM2_CLK
= 66u,
779
FTM3_CLK
= 67u,
780
FTM4_CLK
= 68u,
781
FTM5_CLK
= 69u,
782
FTM6_CLK
= 70u,
783
FTM7_CLK
= 71u,
784
PCC_END_OF_ASYNCH_DIV1_CLOCKS
= 72u,
785
ADC0_CLK
= 73u,
786
ADC1_CLK
= 74u,
787
FLEXIO0_CLK
= 75u,
788
LPI2C0_CLK
= 76u,
789
LPI2C1_CLK
= 77u,
790
LPIT0_CLK
= 78u,
791
LPSPI0_CLK
= 79u,
792
LPSPI1_CLK
= 80u,
793
LPSPI2_CLK
= 81u,
794
LPTMR0_CLK
= 82u,
795
LPUART0_CLK
= 83u,
796
LPUART1_CLK
= 84u,
797
LPUART2_CLK
= 85u,
798
PCC_END_OF_ASYNCH_DIV2_CLOCKS
= 86u,
799
PCC_END_OF_CLOCKS
= 87u,
800
CLOCK_NAME_COUNT
= 88u,
801
}
clock_names_t
;
802
803
#define PCC_INVALID_INDEX 0
804
810
#define PCC_CLOCK_NAME_MAPPINGS \
811
{ \
812
PCC_INVALID_INDEX, \
813
PCC_INVALID_INDEX, \
814
PCC_INVALID_INDEX, \
815
PCC_INVALID_INDEX, \
816
PCC_INVALID_INDEX, \
817
PCC_INVALID_INDEX, \
818
PCC_INVALID_INDEX, \
819
PCC_INVALID_INDEX, \
820
PCC_INVALID_INDEX, \
821
PCC_INVALID_INDEX, \
822
PCC_INVALID_INDEX, \
823
PCC_INVALID_INDEX, \
824
PCC_INVALID_INDEX, \
825
PCC_INVALID_INDEX, \
826
PCC_INVALID_INDEX, \
827
PCC_INVALID_INDEX, \
828
PCC_INVALID_INDEX, \
829
PCC_INVALID_INDEX, \
830
PCC_INVALID_INDEX, \
831
PCC_INVALID_INDEX, \
832
PCC_INVALID_INDEX, \
833
PCC_INVALID_INDEX, \
834
PCC_INVALID_INDEX, \
835
PCC_INVALID_INDEX, \
836
PCC_INVALID_INDEX, \
837
PCC_INVALID_INDEX, \
838
PCC_INVALID_INDEX, \
839
PCC_INVALID_INDEX, \
840
PCC_INVALID_INDEX, \
841
PCC_INVALID_INDEX, \
842
PCC_INVALID_INDEX, \
843
PCC_INVALID_INDEX, \
844
PCC_INVALID_INDEX, \
845
PCC_INVALID_INDEX, \
846
PCC_INVALID_INDEX, \
847
PCC_INVALID_INDEX, \
848
PCC_INVALID_INDEX, \
849
PCC_INVALID_INDEX, \
850
PCC_INVALID_INDEX, \
851
PCC_INVALID_INDEX, \
852
PCC_INVALID_INDEX, \
853
PCC_CMP0_INDEX, \
854
PCC_CRC_INDEX, \
855
PCC_DMAMUX_INDEX, \
856
PCC_EWM_INDEX, \
857
PCC_PORTA_INDEX, \
858
PCC_PORTB_INDEX, \
859
PCC_PORTC_INDEX, \
860
PCC_PORTD_INDEX, \
861
PCC_PORTE_INDEX, \
862
PCC_QSPI_INDEX, \
863
PCC_RTC_INDEX, \
864
PCC_SAI0_INDEX, \
865
PCC_SAI1_INDEX, \
866
PCC_INVALID_INDEX, \
867
PCC_FlexCAN0_INDEX, \
868
PCC_FlexCAN1_INDEX, \
869
PCC_FlexCAN2_INDEX, \
870
PCC_PDB0_INDEX, \
871
PCC_PDB1_INDEX, \
872
PCC_INVALID_INDEX, \
873
PCC_FTFC_INDEX, \
874
PCC_INVALID_INDEX, \
875
PCC_ENET_INDEX, \
876
PCC_FTM0_INDEX, \
877
PCC_FTM1_INDEX, \
878
PCC_FTM2_INDEX, \
879
PCC_FTM3_INDEX, \
880
PCC_FTM4_INDEX, \
881
PCC_FTM5_INDEX, \
882
PCC_FTM6_INDEX, \
883
PCC_FTM7_INDEX, \
884
PCC_INVALID_INDEX, \
885
PCC_ADC0_INDEX, \
886
PCC_ADC1_INDEX, \
887
PCC_FlexIO_INDEX, \
888
PCC_LPI2C0_INDEX, \
889
PCC_LPI2C1_INDEX, \
890
PCC_LPIT_INDEX, \
891
PCC_LPSPI0_INDEX, \
892
PCC_LPSPI1_INDEX, \
893
PCC_LPSPI2_INDEX, \
894
PCC_LPTMR0_INDEX, \
895
PCC_LPUART0_INDEX, \
896
PCC_LPUART1_INDEX, \
897
PCC_LPUART2_INDEX, \
898
PCC_INVALID_INDEX, \
899
PCC_INVALID_INDEX, \
900
}
901
905
#define NO_PERIPHERAL_FEATURE (0U)
/* It's not a peripheral instance, there is no peripheral feature. */
906
#define HAS_CLOCK_GATING_IN_SIM (1U << 0U)
/* Clock gating is implemented in SIM (it's not in PCC) */
907
#define HAS_MULTIPLIER (1U << 1U)
/* Multiplier is implemented in PCC */
908
#define HAS_DIVIDER (1U << 2U)
/* Divider is implemented in PCC */
909
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U)
/* Functional clock source is provided by the first asynchronous clock. */
910
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U)
/* Functional clock source is provided by the second asynchronous clock. */
911
#define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U)
/* Interface clock is provided by the bus clock. */
912
#define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U)
/* Interface clock is provided by the sys clock. */
913
#define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U)
/* Interface clock is provided by the slow clock. */
914
919
#define PERIPHERAL_FEATURES \
920
{ \
921
(NO_PERIPHERAL_FEATURE), \
922
(NO_PERIPHERAL_FEATURE), \
923
(NO_PERIPHERAL_FEATURE), \
924
(NO_PERIPHERAL_FEATURE), \
925
(NO_PERIPHERAL_FEATURE), \
926
(NO_PERIPHERAL_FEATURE), \
927
(NO_PERIPHERAL_FEATURE), \
928
(NO_PERIPHERAL_FEATURE), \
929
(NO_PERIPHERAL_FEATURE), \
930
(NO_PERIPHERAL_FEATURE), \
931
(NO_PERIPHERAL_FEATURE), \
932
(NO_PERIPHERAL_FEATURE), \
933
(NO_PERIPHERAL_FEATURE), \
934
(NO_PERIPHERAL_FEATURE), \
935
(NO_PERIPHERAL_FEATURE), \
936
(NO_PERIPHERAL_FEATURE), \
937
(NO_PERIPHERAL_FEATURE), \
938
(NO_PERIPHERAL_FEATURE), \
939
(NO_PERIPHERAL_FEATURE), \
940
(NO_PERIPHERAL_FEATURE), \
941
(NO_PERIPHERAL_FEATURE), \
942
(NO_PERIPHERAL_FEATURE), \
943
(NO_PERIPHERAL_FEATURE), \
944
(NO_PERIPHERAL_FEATURE), \
945
(NO_PERIPHERAL_FEATURE), \
946
(NO_PERIPHERAL_FEATURE), \
947
(NO_PERIPHERAL_FEATURE), \
948
(NO_PERIPHERAL_FEATURE), \
949
(NO_PERIPHERAL_FEATURE), \
950
(NO_PERIPHERAL_FEATURE), \
951
(NO_PERIPHERAL_FEATURE), \
952
(NO_PERIPHERAL_FEATURE), \
953
(NO_PERIPHERAL_FEATURE), \
954
(NO_PERIPHERAL_FEATURE), \
955
(NO_PERIPHERAL_FEATURE), \
956
(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
957
(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
958
(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
959
(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
960
(HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
961
(NO_PERIPHERAL_FEATURE), \
962
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
963
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
964
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
965
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
966
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
967
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
968
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
969
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
970
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
971
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
972
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
973
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
974
(HAS_INT_CLOCK_FROM_BUS_CLOCK), \
975
(NO_PERIPHERAL_FEATURE), \
976
(HAS_INT_CLOCK_FROM_SYS_CLOCK), \
977
(HAS_INT_CLOCK_FROM_SYS_CLOCK), \
978
(HAS_INT_CLOCK_FROM_SYS_CLOCK), \
979
(HAS_INT_CLOCK_FROM_SYS_CLOCK), \
980
(HAS_INT_CLOCK_FROM_SYS_CLOCK), \
981
(NO_PERIPHERAL_FEATURE), \
982
(HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
983
(NO_PERIPHERAL_FEATURE), \
984
(HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
985
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
986
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
987
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
988
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
989
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
990
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
991
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
992
(HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
993
(NO_PERIPHERAL_FEATURE), \
994
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
995
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
996
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
997
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
998
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
999
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1000
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1001
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1002
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1003
(HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1004
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1005
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1006
(HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1007
(NO_PERIPHERAL_FEATURE), \
1008
(NO_PERIPHERAL_FEATURE), \
1009
}
1010
1011
/* Time to wait for SIRC to stabilize (number of
1012
* cycles when core runs at maximum speed - 112 MHz */
1013
#define SIRC_STABILIZATION_TIMEOUT 26U;
1014
1015
/* Time to wait for FIRC to stabilize (number of
1016
* cycles when core runs at maximum speed - 112 MHz */
1017
#define FIRC_STABILIZATION_TIMEOUT 10U;
1018
1019
/* Time to wait for SOSC to stabilize (number of
1020
* cycles when core runs at maximum speed - 112 MHz */
1021
#define SOSC_STABILIZATION_TIMEOUT 3205000U;
1022
1023
/* Time to wait for SPLL to stabilize (number of
1024
* cycles when core runs at maximum speed - 112 MHz */
1025
#define SPLL_STABILIZATION_TIMEOUT 1000U;
1026
1037
#define MAX_FREQ_VLPR 0U
1038
#define MAX_FREQ_RUN 1U
1039
#define MAX_FREQ_HSRUN 2U
1040
1041
#define MAX_FREQ_SYS_CLK 0U
1042
#define MAX_FREQ_BUS_CLK 1U
1043
#define MAX_FREQ_SLOW_CLK 2U
1044
1045
#define MAX_FREQ_MODES_NO 3U
1046
#define MAX_FREQ_CLK_NO 3U
1047
1048
#define CLOCK_MAX_FREQUENCIES \
1049
{
/* SYS_CLK BUS_CLK SLOW_CLK */
\
1050
{ 4000000, 4000000, 1000000}, \
1051
{ 80000000,40000000,26670000}, \
1052
{112000000,56000000,28000000}, \
1053
}
1054
1055
1066
#define TMP_SIRC_CLK 0U
1067
#define TMP_FIRC_CLK 1U
1068
#define TMP_SOSC_CLK 2U
1069
#define TMP_SPLL_CLK 3U
1070
1071
#define TMP_SYS_DIV 0U
1072
#define TMP_BUS_DIV 1U
1073
#define TMP_SLOW_DIV 2U
1074
1075
#define TMP_SYS_CLK_NO 4U
1076
#define TMP_SYS_DIV_NO 3U
1077
1078
#define TMP_SYSTEM_CLOCK_CONFIGS \
1079
{
/* SYS_CLK BUS_CLK SLOW_CLK */
\
1080
{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1}, \
1081
{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
1082
{ SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
1083
{ SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
1084
}
1085
1086
/* Do not use the old names of the renamed symbols */
1087
/* #define DO_NOT_USE_DEPRECATED_SYMBOLS */
1088
1094
#if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS)
1095
#define CORE_CLOCK CORE_CLK
1096
#define BUS_CLOCK BUS_CLK
1097
#define SLOW_CLOCK SLOW_CLK
1098
#define CLKOUT_CLOCK CLKOUT_CLK
1099
#define SIRC_CLOCK SIRC_CLK
1100
#define FIRC_CLOCK FIRC_CLK
1101
#define SOSC_CLOCK SOSC_CLK
1102
#define SPLL_CLOCK SPLL_CLK
1103
#define RTC_CLKIN_CLOCK RTC_CLKIN_CLK
1104
#define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK
1105
#define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK
1106
#define SIM_LPO_CLOCK SIM_LPO_CLK
1107
#define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK
1108
#define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK
1109
#define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK
1110
#define SIM_EIM_CLOCK SIM_EIM_CLK
1111
#define SIM_ERM_CLOCK SIM_ERM_CLK
1112
#define SIM_DMA_CLOCK SIM_DMA_CLK
1113
#define SIM_MPU_CLOCK SIM_MPU_CLK
1114
#define SIM_MSCM_CLOCK SIM_MSCM_CLK
1115
#define PCC_DMAMUX0_CLOCK DMAMUX0_CLK
1116
#define PCC_CRC0_CLOCK CRC0_CLK
1117
#define PCC_RTC0_CLOCK RTC0_CLK
1118
#define PCC_PORTA_CLOCK PORTA_CLK
1119
#define PCC_PORTB_CLOCK PORTB_CLK
1120
#define PCC_PORTC_CLOCK PORTC_CLK
1121
#define PCC_PORTD_CLOCK PORTD_CLK
1122
#define PCC_PORTE_CLOCK PORTE_CLK
1123
#define PCC_EWM0_CLOCK EWM0_CLK
1124
#define PCC_CMP0_CLOCK CMP0_CLK
1125
#define PCC_FlexCAN0_CLOCK FlexCAN0_CLK
1126
#define PCC_FlexCAN1_CLOCK FlexCAN1_CLK
1127
#define PCC_FlexCAN2_CLOCK FlexCAN2_CLK
1128
#define PCC_PDB1_CLOCK PDB1_CLK
1129
#define PCC_PDB0_CLOCK PDB0_CLK
1130
#define PCC_FTFC0_CLOCK FTFC0_CLK
1131
#define PCC_FTM0_CLOCK FTM0_CLK
1132
#define PCC_FTM1_CLOCK FTM1_CLK
1133
#define PCC_FTM2_CLOCK FTM2_CLK
1134
#define PCC_FTM3_CLOCK FTM3_CLK
1135
#define PCC_ADC1_CLOCK ADC1_CLK
1136
#define PCC_LPSPI0_CLOCK LPSPI0_CLK
1137
#define PCC_LPSPI1_CLOCK LPSPI1_CLK
1138
#define PCC_LPSPI2_CLOCK LPSPI2_CLK
1139
#define PCC_LPIT0_CLOCK LPIT0_CLK
1140
#define PCC_ADC0_CLOCK ADC0_CLK
1141
#define PCC_LPTMR0_CLOCK LPTMR0_CLK
1142
#define PCC_FLEXIO0_CLOCK FLEXIO0_CLK
1143
#define PCC_LPI2C0_CLOCK LPI2C0_CLK
1144
#define PCC_LPUART0_CLOCK LPUART0_CLK
1145
#define PCC_LPUART1_CLOCK LPUART1_CLK
1146
#define PCC_LPUART2_CLOCK LPUART2_CLK
1147
#endif
/* !DO_NOT_USE_DEPRECATED_SYMBOLS */
1148
1149
1150
/* CSEc module features */
1151
1154
#define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
1155
1157
#define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
1158
1160
#define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
1161
1163
#define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
1164
1166
#define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
1167
1169
#define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
1170
1172
#define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
1173
1174
#define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
1175
1177
#define FEATURE_CSEC_SREG_OFFSET (0x2FU)
1178
1180
#define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
1181
1182
#define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
1183
1184
#define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
1185
1186
#define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
1187
1188
#define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
1189
1190
#define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
1191
1192
#define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
1193
1194
#define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
1195
1196
1197
/* ADC module features */
1198
1201
#define FEATURE_ADC_HAS_EXTRA_NUM_REGS (1)
1202
1206
#define FEATURE_ADC_MAX_NUM_EXT_CHANS (32)
1207
1209
#if FEATURE_ADC_HAS_EXTRA_NUM_REGS
1210
#define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
1211
#else
1212
#define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
1213
#endif
/* FEATURE_ADC_HAS_EXTRA_NUM_REGS */
1214
1216
#define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
1217
1218
#define ADC_DEFAULT_USER_GAIN (0x04U)
1219
1220
/* MSCM module features */
1221
1222
/* @brief Has interrupt router control registers (IRSPRCn). */
1223
#define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
1224
/* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */
1225
#define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
1226
1227
/* SAI module features */
1228
#define SAI0_CHANNEL_COUNT 4U
1229
#define SAI1_CHANNEL_COUNT 1U
1230
#define SAI_MAX_CHANNEL_COUNT 4U
1231
1232
/* ENET module features */
1233
1235
#define FEATURE_ENET_CLOCK_NAMES { CORE_CLK }
1236
1238
#define FEATURE_ENET_TX_IRQS ENET_TX_IRQS
1239
1240
#define FEATURE_ENET_RX_IRQS ENET_RX_IRQS
1241
1242
#define FEATURE_ENET_ERR_IRQS ENET_ERR_IRQS
1243
1244
#define FEATURE_ENET_WAKE_IRQS ENET_WAKE_IRQS
1245
1247
#define FEATURE_ENET_COUNTERS_OFFSET_WORDS 0x80
1248
1250
#define FEATURE_ENET_MDC_MAX_FREQUENCY 2500000U
1251
1253
#define FEATURE_ENET_MDIO_MIN_HOLD_TIME_NS 10U
1254
1256
#define FEATURE_ENET_BUFF_ALIGNMENT (16U)
1257
1258
#define FEATURE_ENET_BUFFDESCR_ALIGNMENT (16U)
1259
1261
#define FEATURE_ENET_HAS_AVB (0)
1262
1264
#define FEATURE_ENET_HAS_RECEIVE_PARSER (0)
1265
1267
#define FEATURE_ENET_DEFAULT_PHY_IF ENET_MII_MODE
1268
1269
/* QuadSPI module features */
1270
1272
#define FEATURE_QSPI_ARDB_BASE 0x67000000U
1273
1274
#define FEATURE_QSPI_ARDB_END 0x67FFFFFFU
1275
1276
#define FEATURE_QSPI_AMBA_BASE 0x68000000U
1277
1278
#define FEATURE_QSPI_AMBA_END 0x6FFFFFFFU
1279
1280
#define FEATURE_QSPI_AHB_BUF_SIZE 1024U
1281
1283
#define FEATURE_QSPI_DMA_TX_REQ {EDMA_REQ_QUADSPI_TX}
1284
1285
#define FEATURE_QSPI_DMA_RX_REQ {EDMA_REQ_QUADSPI_RX}
1286
1287
/* OSIF module features */
1288
1289
#define FEATURE_OSIF_USE_SYSTICK (1)
1290
#define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1)
/* Cortex M device */
1291
1292
/* TRGMUX module features */
1293
1294
#define FEATURE_TRGMUX_HAS_EXTENDED_NUM_TRIGS (1)
1295
1296
/* LPSPI module features */
1297
/* @brief Initial value for state structure */
1298
#define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL, NULL}
1299
1300
#endif
/* S32K148_FEATURES_H */
1301
1302
/*******************************************************************************
1303
* EOF
1304
******************************************************************************/
EDMA_REQ_FLEXCAN0
Definition:
S32K148_features.h:645
LPI2C1_CLK
Definition:
S32K148_features.h:789
PORTB_CLK
Definition:
S32K148_features.h:758
EDMA_REQ_FTM1_CHANNEL_2
Definition:
S32K148_features.h:613
dma_request_source_t
dma_request_source_t
Structure for the DMA hardware request.
Definition:
S32K148_features.h:590
PCC_END_OF_SYS_CLOCKS
Definition:
S32K148_features.h:772
SAI1_CLK
Definition:
S32K148_features.h:765
PORTD_CLK
Definition:
S32K148_features.h:760
EDMA_REQ_PDB1
Definition:
S32K148_features.h:638
EDMA_REQ_LPUART1_RX
Definition:
S32K148_features.h:595
EDMA_REQ_FTM2_CHANNEL_1
Definition:
S32K148_features.h:620
FLEXCAN_CLK_SOURCE_SOSCDIV2
Definition:
S32K148_features.h:360
SIM_FTM2_CLOCKSEL
Definition:
S32K148_features.h:733
FTM5_CLK
Definition:
S32K148_features.h:781
FTM3_CLK
Definition:
S32K148_features.h:779
SIRCDIV1_CLK
Definition:
S32K148_features.h:720
SAI0_CLK
Definition:
S32K148_features.h:764
SOSC_CLK
Definition:
S32K148_features.h:716
SIM_ERM_CLK
Definition:
S32K148_features.h:746
ENET0_CLK
Definition:
S32K148_features.h:775
CORE_CLK
Definition:
S32K148_features.h:708
EWM0_CLK
Definition:
S32K148_features.h:756
EDMA_REQ_PORTC
Definition:
S32K148_features.h:642
EDMA_REQ_PDB0
Definition:
S32K148_features.h:637
EDMA_REQ_ADC1
Definition:
S32K148_features.h:634
FTM2_CLK
Definition:
S32K148_features.h:778
EDMA_REQ_FTM2_CHANNEL_4
Definition:
S32K148_features.h:623
FTM1_CLK
Definition:
S32K148_features.h:777
FLEXCAN_CLK_SOURCE_SYS
Definition:
S32K148_features.h:361
SIM_LPO_32K_CLK
Definition:
S32K148_features.h:743
SIM_LPO_1K_CLK
Definition:
S32K148_features.h:742
PORTC_CLK
Definition:
S32K148_features.h:759
PORTE_CLK
Definition:
S32K148_features.h:761
SIM_RTCCLK_CLK
Definition:
S32K148_features.h:740
EDMA_REQ_PORTA
Definition:
S32K148_features.h:640
EDMA_REQ_LPI2C0_TX
Definition:
S32K148_features.h:636
BUS_CLK
Definition:
S32K148_features.h:709
EDMA_REQ_QUADSPI_TX
Definition:
S32K148_features.h:652
SIM_FTM6_CLOCKSEL
Definition:
S32K148_features.h:737
EDMA_REQ_DMAMUX_ALWAYS_ENABLED0
Definition:
S32K148_features.h:653
LPUART1_CLK
Definition:
S32K148_features.h:796
EDMA_REQ_FTM1_CHANNEL_3
Definition:
S32K148_features.h:614
EDMA_REQ_SAI0_TX
Definition:
S32K148_features.h:649
FTM4_CLK
Definition:
S32K148_features.h:780
EDMA_REQ_LPSPI1_RX
Definition:
S32K148_features.h:607
EDMA_REQ_FLEXIO_SHIFTER2_SAI1_RX
Definition:
S32K148_features.h:603
SOSCDIV2_CLK
Definition:
S32K148_features.h:725
PCC_END_OF_ASYNCH_DIV1_CLOCKS
Definition:
S32K148_features.h:784
PCC_END_OF_BUS_CLOCKS
Definition:
S32K148_features.h:766
SIM_MSCM_CLK
Definition:
S32K148_features.h:749
EDMA_REQ_PORTE
Definition:
S32K148_features.h:644
EDMA_REQ_FTM2_CHANNEL_7
Definition:
S32K148_features.h:626
EDMA_REQ_DMAMUX_ALWAYS_ENABLED1
Definition:
S32K148_features.h:654
EDMA_REQ_PORTB
Definition:
S32K148_features.h:641
SIM_FTM4_CLOCKSEL
Definition:
S32K148_features.h:735
ENET_MAC0_TIMER_OR_CH0_CH3
Definition:
S32K148_features.h:592
EDMA_REQ_FTM3_OR_CH0_CH7
Definition:
S32K148_features.h:628
FlexCAN1_CLK
Definition:
S32K148_features.h:768
EDMA_REQ_LPSPI2_RX
Definition:
S32K148_features.h:609
RTC_CLKIN_CLK
Definition:
S32K148_features.h:718
EDMA_REQ_LPUART2_TX
Definition:
S32K148_features.h:598
SIM_END_OF_CLOCKS
Definition:
S32K148_features.h:750
EDMA_REQ_LPI2C0_RX
Definition:
S32K148_features.h:635
SIM_FTM7_CLOCKSEL
Definition:
S32K148_features.h:738
EDMA_REQ_FLEXCAN2
Definition:
S32K148_features.h:647
FTFC0_CLK
Definition:
S32K148_features.h:773
EDMA_REQ_FTM6_OR_CH0_CH7
Definition:
S32K148_features.h:631
EDMA_REQ_FTM1_CHANNEL_7
Definition:
S32K148_features.h:618
FIRCDIV1_CLK
Definition:
S32K148_features.h:722
EDMA_REQ_LPSPI1_TX
Definition:
S32K148_features.h:608
CLOCK_NAME_COUNT
Definition:
S32K148_features.h:800
LPUART2_CLK
Definition:
S32K148_features.h:797
SIRC_CLK
Definition:
S32K148_features.h:714
EDMA_REQ_SAI0_RX
Definition:
S32K148_features.h:648
FTM0_CLK
Definition:
S32K148_features.h:776
PDB0_CLK
Definition:
S32K148_features.h:770
LPSPI2_CLK
Definition:
S32K148_features.h:793
EDMA_REQ_FLEXIO_SHIFTER0
Definition:
S32K148_features.h:601
PCC_END_OF_SLOW_CLOCKS
Definition:
S32K148_features.h:774
FlexCAN0_CLK
Definition:
S32K148_features.h:767
EDMA_REQ_FTM1_CHANNEL_6
Definition:
S32K148_features.h:617
clock_names_t
clock_names_t
Clock names.
Definition:
S32K148_features.h:705
SPLLDIV1_CLK
Definition:
S32K148_features.h:726
SPLLDIV2_CLK
Definition:
S32K148_features.h:727
LPI2C0_CLK
Definition:
S32K148_features.h:788
FLEXIO0_CLK
Definition:
S32K148_features.h:787
PCC_END_OF_CLOCKS
Definition:
S32K148_features.h:799
EDMA_REQ_QUADSPI_RX
Definition:
S32K148_features.h:651
SIM_FTM5_CLOCKSEL
Definition:
S32K148_features.h:736
SIM_DMA_CLK
Definition:
S32K148_features.h:747
EDMA_REQ_LPSPI0_TX
Definition:
S32K148_features.h:606
EDMA_REQ_FTM0_OR_CH0_CH7
Definition:
S32K148_features.h:627
PCC_END_OF_ASYNCH_DIV2_CLOCKS
Definition:
S32K148_features.h:798
EDMA_REQ_LPUART0_RX
Definition:
S32K148_features.h:593
SIM_FTM1_CLOCKSEL
Definition:
S32K148_features.h:732
SIM_LPO_CLK
Definition:
S32K148_features.h:741
EDMA_REQ_FTM7_OR_CH0_CH7
Definition:
S32K148_features.h:632
EDMA_REQ_LPI2C1_RX
Definition:
S32K148_features.h:599
LPSPI0_CLK
Definition:
S32K148_features.h:791
DMAMUX0_CLK
Definition:
S32K148_features.h:755
ADC1_CLK
Definition:
S32K148_features.h:786
SIM_FTM3_CLOCKSEL
Definition:
S32K148_features.h:734
EDMA_REQ_PORTD
Definition:
S32K148_features.h:643
FTM6_CLK
Definition:
S32K148_features.h:782
CMP0_CLK
Definition:
S32K148_features.h:753
EDMA_REQ_LPUART2_RX
Definition:
S32K148_features.h:597
SIM_MPU_CLK
Definition:
S32K148_features.h:748
EDMA_REQ_FTM2_CHANNEL_0
Definition:
S32K148_features.h:619
EDMA_REQ_FTM4_OR_CH0_CH7
Definition:
S32K148_features.h:629
LPIT0_CLK
Definition:
S32K148_features.h:790
SPLL_CLK
Definition:
S32K148_features.h:717
EDMA_REQ_ADC0
Definition:
S32K148_features.h:633
EDMA_REQ_FLEXIO_SHIFTER3_SAI1_TX
Definition:
S32K148_features.h:604
EDMA_REQ_FTM5_OR_CH0_CH7
Definition:
S32K148_features.h:630
FlexCAN2_CLK
Definition:
S32K148_features.h:769
SCG_CLKOUT_CLK
Definition:
S32K148_features.h:719
EDMA_REQ_FTM2_CHANNEL_5
Definition:
S32K148_features.h:624
FIRC_CLK
Definition:
S32K148_features.h:715
EDMA_REQ_FTM2_CHANNEL_2
Definition:
S32K148_features.h:621
EDMA_REQ_LPSPI0_RX
Definition:
S32K148_features.h:605
ADC0_CLK
Definition:
S32K148_features.h:785
EDMA_REQ_DISABLED
Definition:
S32K148_features.h:591
SIM_LPO_128K_CLK
Definition:
S32K148_features.h:744
RTC0_CLK
Definition:
S32K148_features.h:763
PDB1_CLK
Definition:
S32K148_features.h:771
EDMA_REQ_FTM2_CHANNEL_3
Definition:
S32K148_features.h:622
EDMA_REQ_CMP0
Definition:
S32K148_features.h:639
CRC0_CLK
Definition:
S32K148_features.h:754
EDMA_REQ_FLEXCAN1
Definition:
S32K148_features.h:646
EDMA_REQ_FLEXIO_SHIFTER1
Definition:
S32K148_features.h:602
SIM_EIM_CLK
Definition:
S32K148_features.h:745
FIRCDIV2_CLK
Definition:
S32K148_features.h:723
CLKOUT_CLK
Definition:
S32K148_features.h:711
EDMA_REQ_FTM2_CHANNEL_6
Definition:
S32K148_features.h:625
EDMA_REQ_FTM1_CHANNEL_5
Definition:
S32K148_features.h:616
flexcan_clk_source_t
flexcan_clk_source_t
Definition:
S32K148_features.h:359
FTM7_CLK
Definition:
S32K148_features.h:783
SLOW_CLK
Definition:
S32K148_features.h:710
LPTMR0_CLK
Definition:
S32K148_features.h:794
SIM_CLKOUTSELL
Definition:
S32K148_features.h:739
SCG_END_OF_CLOCKS
Definition:
S32K148_features.h:728
SIRCDIV2_CLK
Definition:
S32K148_features.h:721
EDMA_REQ_LPSPI2_TX
Definition:
S32K148_features.h:610
EDMA_REQ_FTM1_CHANNEL_0
Definition:
S32K148_features.h:611
SOSCDIV1_CLK
Definition:
S32K148_features.h:724
EDMA_REQ_LPTMR0
Definition:
S32K148_features.h:650
EDMA_REQ_FTM1_CHANNEL_1
Definition:
S32K148_features.h:612
LPSPI1_CLK
Definition:
S32K148_features.h:792
SIM_FTM0_CLOCKSEL
Definition:
S32K148_features.h:731
LPUART0_CLK
Definition:
S32K148_features.h:795
EDMA_REQ_LPUART0_TX
Definition:
S32K148_features.h:594
EDMA_REQ_LPI2C1_TX
Definition:
S32K148_features.h:600
QSPI0_CLK
Definition:
S32K148_features.h:762
EDMA_REQ_LPUART1_TX
Definition:
S32K148_features.h:596
PORTA_CLK
Definition:
S32K148_features.h:757
EDMA_REQ_FTM1_CHANNEL_4
Definition:
S32K148_features.h:615
platform
devices
S32K148
include
S32K148_features.h
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