S32 SDK
S32K144.h
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1 /*
2 ** ###################################################################
3 ** Processor: S32K144_100
4 ** Reference manual: S32K14XRM Rev. 2, 02/2017
5 ** Version: rev. 2.8, 2017-03-27
6 ** Build: b170328
7 **
8 ** Abstract:
9 ** Peripheral Access Layer for S32K144
10 **
11 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
12 ** Copyright 2016-2017 NXP
13 ** All rights reserved.
14 **
15 ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
16 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
19 ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
25 ** THE POSSIBILITY OF SUCH DAMAGE.
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2015-04-09) - Iulian Talpiga
32 ** Initial version.
33 ** - rev. 1.1 (2015-05-19) - Bogdan Nitu
34 ** Updated interrupts table
35 ** Removed SIM_CHIPCTL_DAC2CMP
36 ** Compacted PORT_PCR registers
37 ** Compacted PCC registers
38 ** - rev. 1.2 (2015-06-02) - Bogdan Nitu
39 ** Added 'U' suffix to all integer constants
40 ** Use "" instead of <> for Platform type inclusion
41 ** CNT register from WDOG module is RW
42 ** - rev. 1.3 (2015-08-05) - Iulian Talpiga
43 ** Synchronized with latest RDP
44 ** Removed OSC32 module
45 ** Removed reserved registers
46 ** Incorporated bit band acces macros
47 ** Switched to standard C99 data types
48 ** Added 'u' to constants
49 ** Added size defines for register arrays
50 ** Define peripheral instance count
51 ** - rev. 1.4 (2015-08-10) - Iulian Talpiga
52 ** Compacted TRGMUX registers
53 ** Defined array index offsets for PCC and TRGMUX
54 ** Added FPU registers
55 ** Group FTM channel registers
56 ** Added interrupt information to peripherals
57 ** Renamed CAN interrupts according to the reference manual
58 ** Added author information to revisions
59 ** - rev. 1.5 (2015-09-16) - Iulian Talpiga
60 ** Renamed NVIC and SCB to avoid conflict
61 ** Compacted CAN Wake-up Message buffers
62 ** Added CAN embedded RAM
63 ** Updated interrupts: LPIT, FTFE, LPUART,ACMP
64 ** Corrected ADC_SC1_ADCH_WIDTH
65 ** Compacted PDB registers
66 ** Corrected CAN, FTM, and PDB count defines
67 ** Guarding register acces macro against redefintion
68 ** - rev. 1.6 (2015-09-29) - Iulian Talpiga
69 ** Added WATER and FIFO registers to LPUART.
70 ** - rev. 1.7 (2015-10-21) - Iulian Talpiga
71 ** Updated ADC, AIPS, CMP, LMEM, LPTMR, PMC, PORT, RCM, RTC, SCG, SIM
72 ** Compacted MPU and LPIT
73 ** Added FSL_SysTick
74 ** Updated doxygen documentation grouping
75 ** Updated interrupts: RCM
76 ** - rev. 1.8 (2016-01-06) - Iulian Talpiga
77 ** Updated DMA, compacted TCD registers
78 ** Updated SCG, removed SC2P - SC16P
79 ** Added 8 and 16 bit access to DATA register, CRC module
80 ** - rev. 1.9 (2016-02-15) - Iulian Talpiga
81 ** Updated CRC, renamed DATA union
82 ** Updated PMC, added CLKBIASDIS bitfield
83 ** Added FSL_NVIC registers to SVD
84 ** - rev. 2.0 (2016-04-07) - Iulian Talpiga
85 ** Updated support for Rev2.0 silicon (0N47T)
86 ** Updated ADC, AIPS, DMA, FlexIO, FTM, GPIO, LPI2C, LPIT, LPSPI, MCM, MPU, MSCM, PMC, RTC, RCM, PCC, RTC, SCG, SIM, TRGMUX and WDOG module
87 ** Updated interrupts
88 ** Added EIM and ERM modules
89 ** Added EIM and ERM modules
90 ** - rev. 2.1 (2016-06-10) - Iulian Talpiga
91 ** Updated to latest RM
92 ** Minor changes to: CAN, EIM, LPI2C, MPU, PCC, PMC, RTC, SIM and TRGMUX
93 ** - rev. 2.2 (2016-08-02) - Iulian Talpiga
94 ** Updated to latest RM
95 ** Minor changes to: ADC, CAN, CRC, FTFC, LMEM, LPI2C, MCM, MSCM, PCC, RTC, SIM
96 ** Added CSE_PRAM
97 ** - rev. 2.3 (2016-09-09) - Iulian Talpiga
98 ** Updated to latest RM
99 ** Minor changes to: PCC, FSL_NVIC and FTM
100 ** - rev. 2.4 (2016-09-28) - Iulian Talpiga
101 ** Fix RAMn array size in FlexCAN
102 ** Fix FCSESTAT bit order
103 ** Added CP0CFG0, CP0CFG1,CP0CFG2 and CP0CFG3 in MSCM
104 ** Fixed STIR register in FSL_NVIC
105 ** Fixed SHPR3 and ACTLR registers in FSL_SCB
106 ** - rev. 2.5 (2016-11-25) - Iulian Talpiga
107 ** Fix FRAC bit-field in PCC module
108 ** Removed BITBAND_ACCESS macros
109 ** Added MISRA declarations
110 ** Updated copyright
111 ** Changed prefix of NVIC, SCB and SysTick to S32_
112 ** - rev. 2.6 (2017-01-09) - Iulian Talpiga
113 ** Fix interrupts for CAN, LPUART, FTFC
114 ** - rev. 2.7 (2017-02-22) - Iulian Talpiga
115 ** Update header as per rev S32K14XRM Rev. 2, 02/2017
116 ** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM
117 ** - rev. 2.8 (2017-03-27) - Iulian Talpiga
118 ** Synchronized PCC_FlexIO on S32K Family
119 **
120 ** ###################################################################
121 */
122 
171 /* ----------------------------------------------------------------------------
172  -- MCU activation
173  ---------------------------------------------------------------------------- */
174 
175 /* Prevention from multiple including the same memory map */
176 #if !defined(S32K144_H_) /* Check if memory map has not been already included */
177 #define S32K144_H_
178 #define MCU_S32K144
179 
180 /* Check if another memory map has not been also included */
181 #if (defined(MCU_ACTIVE))
182  #error S32K144 memory map: There is already included another memory map. Only one memory map can be included.
183 #endif /* (defined(MCU_ACTIVE)) */
184 #define MCU_ACTIVE
185 
186 #include <stdint.h>
187 
190 #define MCU_MEM_MAP_VERSION 0x0200u
191 
192 #define MCU_MEM_MAP_VERSION_MINOR 0x0008u
193 
194 /* ----------------------------------------------------------------------------
195  -- Generic macros
196  ---------------------------------------------------------------------------- */
197 
198 /* IO definitions (access restrictions to peripheral registers) */
204 #ifndef __IO
205 #ifdef __cplusplus
206  #define __I volatile
207 #else
208  #define __I volatile const
209 #endif
210 #define __O volatile
211 #define __IO volatile
212 #endif
213 
214 
218 #if !defined(REG_READ32)
219  #define REG_READ32(address) (*(volatile uint32_t*)(address))
220 #endif
221 
225 #if !defined(REG_WRITE32)
226  #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value))
227 #endif
228 
232 #if !defined(REG_BIT_SET32)
233  #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask))
234 #endif
235 
239 #if !defined(REG_BIT_CLEAR32)
240  #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask))))
241 #endif
242 
247 #if !defined(REG_RMW32)
248  #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value)))))
249 #endif
250 
251 
252 /* ----------------------------------------------------------------------------
253  -- Interrupt vector numbers for S32K144
254  ---------------------------------------------------------------------------- */
255 
262 #define NUMBER_OF_INT_VECTORS 139u
271 typedef enum
272 {
273  /* Auxiliary constants */
274  NotAvail_IRQn = -128,
276  /* Core interrupts */
282  SVCall_IRQn = -5,
284  PendSV_IRQn = -2,
287  /* Device specific interrupts */
288  DMA0_IRQn = 0u,
289  DMA1_IRQn = 1u,
290  DMA2_IRQn = 2u,
291  DMA3_IRQn = 3u,
292  DMA4_IRQn = 4u,
293  DMA5_IRQn = 5u,
294  DMA6_IRQn = 6u,
295  DMA7_IRQn = 7u,
296  DMA8_IRQn = 8u,
297  DMA9_IRQn = 9u,
298  DMA10_IRQn = 10u,
299  DMA11_IRQn = 11u,
300  DMA12_IRQn = 12u,
301  DMA13_IRQn = 13u,
302  DMA14_IRQn = 14u,
303  DMA15_IRQn = 15u,
305  MCM_IRQn = 17u,
306  FTFC_IRQn = 18u,
308  LVD_LVW_IRQn = 20u,
311  RCM_IRQn = 23u,
314  LPSPI0_IRQn = 26u,
315  LPSPI1_IRQn = 27u,
316  LPSPI2_IRQn = 28u,
320  ADC0_IRQn = 39u,
321  ADC1_IRQn = 40u,
322  CMP0_IRQn = 41u,
325  RTC_IRQn = 46u,
331  PDB0_IRQn = 52u,
332  SCG_IRQn = 57u,
333  LPTMR0_IRQn = 58u,
334  PORTA_IRQn = 59u,
335  PORTB_IRQn = 60u,
336  PORTC_IRQn = 61u,
337  PORTD_IRQn = 62u,
338  PORTE_IRQn = 63u,
339  SWI_IRQn = 64u,
340  PDB1_IRQn = 68u,
341  FLEXIO_IRQn = 69u,
377 } IRQn_Type;
378  /* end of group Interrupt_vector_numbers_S32K144 */
382 
383 
384 /* ----------------------------------------------------------------------------
385  -- Device Peripheral Access Layer for S32K144
386  ---------------------------------------------------------------------------- */
387 
393 /* @brief This module covers memory mapped registers available on SoC */
394 
395 /* ----------------------------------------------------------------------------
396  -- ADC Peripheral Access Layer
397  ---------------------------------------------------------------------------- */
398 
406 #define ADC_SC1_COUNT 16u
407 #define ADC_R_COUNT 16u
408 #define ADC_CV_COUNT 2u
409 
411 typedef struct {
412  __IO uint32_t SC1[ADC_SC1_COUNT];
413  __IO uint32_t CFG1;
414  __IO uint32_t CFG2;
415  __I uint32_t R[ADC_R_COUNT];
416  __IO uint32_t CV[ADC_CV_COUNT];
417  __IO uint32_t SC2;
418  __IO uint32_t SC3;
419  __IO uint32_t BASE_OFS;
420  __IO uint32_t OFS;
421  __IO uint32_t USR_OFS;
422  __IO uint32_t XOFS;
423  __IO uint32_t YOFS;
424  __IO uint32_t G;
425  __IO uint32_t UG;
426  __IO uint32_t CLPS;
427  __IO uint32_t CLP3;
428  __IO uint32_t CLP2;
429  __IO uint32_t CLP1;
430  __IO uint32_t CLP0;
431  __IO uint32_t CLPX;
432  __IO uint32_t CLP9;
433  __IO uint32_t CLPS_OFS;
434  __IO uint32_t CLP3_OFS;
435  __IO uint32_t CLP2_OFS;
436  __IO uint32_t CLP1_OFS;
437  __IO uint32_t CLP0_OFS;
438  __IO uint32_t CLPX_OFS;
439  __IO uint32_t CLP9_OFS;
441 
443 #define ADC_INSTANCE_COUNT (2u)
444 
445 
446 /* ADC - Peripheral instance base addresses */
448 #define ADC0_BASE (0x4003B000u)
449 
450 #define ADC0 ((ADC_Type *)ADC0_BASE)
451 
452 #define ADC1_BASE (0x40027000u)
453 
454 #define ADC1 ((ADC_Type *)ADC1_BASE)
455 
456 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
457 
458 #define ADC_BASE_PTRS { ADC0, ADC1 }
459 
460 #define ADC_IRQS_ARR_COUNT (1u)
461 
462 #define ADC_IRQS_CH_COUNT (1u)
463 
464 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
465 
466 /* ----------------------------------------------------------------------------
467  -- ADC Register Masks
468  ---------------------------------------------------------------------------- */
469 
475 /* SC1 Bit Fields */
476 #define ADC_SC1_ADCH_MASK 0x1Fu
477 #define ADC_SC1_ADCH_SHIFT 0u
478 #define ADC_SC1_ADCH_WIDTH 5u
479 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
480 #define ADC_SC1_AIEN_MASK 0x40u
481 #define ADC_SC1_AIEN_SHIFT 6u
482 #define ADC_SC1_AIEN_WIDTH 1u
483 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
484 #define ADC_SC1_COCO_MASK 0x80u
485 #define ADC_SC1_COCO_SHIFT 7u
486 #define ADC_SC1_COCO_WIDTH 1u
487 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
488 /* CFG1 Bit Fields */
489 #define ADC_CFG1_ADICLK_MASK 0x3u
490 #define ADC_CFG1_ADICLK_SHIFT 0u
491 #define ADC_CFG1_ADICLK_WIDTH 2u
492 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
493 #define ADC_CFG1_MODE_MASK 0xCu
494 #define ADC_CFG1_MODE_SHIFT 2u
495 #define ADC_CFG1_MODE_WIDTH 2u
496 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
497 #define ADC_CFG1_ADIV_MASK 0x60u
498 #define ADC_CFG1_ADIV_SHIFT 5u
499 #define ADC_CFG1_ADIV_WIDTH 2u
500 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
501 #define ADC_CFG1_CLRLTRG_MASK 0x100u
502 #define ADC_CFG1_CLRLTRG_SHIFT 8u
503 #define ADC_CFG1_CLRLTRG_WIDTH 1u
504 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_CLRLTRG_SHIFT))&ADC_CFG1_CLRLTRG_MASK)
505 /* CFG2 Bit Fields */
506 #define ADC_CFG2_SMPLTS_MASK 0xFFu
507 #define ADC_CFG2_SMPLTS_SHIFT 0u
508 #define ADC_CFG2_SMPLTS_WIDTH 8u
509 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_SMPLTS_SHIFT))&ADC_CFG2_SMPLTS_MASK)
510 /* R Bit Fields */
511 #define ADC_R_D_MASK 0xFFFu
512 #define ADC_R_D_SHIFT 0u
513 #define ADC_R_D_WIDTH 12u
514 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
515 /* CV Bit Fields */
516 #define ADC_CV_CV_MASK 0xFFFFu
517 #define ADC_CV_CV_SHIFT 0u
518 #define ADC_CV_CV_WIDTH 16u
519 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
520 /* SC2 Bit Fields */
521 #define ADC_SC2_REFSEL_MASK 0x3u
522 #define ADC_SC2_REFSEL_SHIFT 0u
523 #define ADC_SC2_REFSEL_WIDTH 2u
524 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
525 #define ADC_SC2_DMAEN_MASK 0x4u
526 #define ADC_SC2_DMAEN_SHIFT 2u
527 #define ADC_SC2_DMAEN_WIDTH 1u
528 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
529 #define ADC_SC2_ACREN_MASK 0x8u
530 #define ADC_SC2_ACREN_SHIFT 3u
531 #define ADC_SC2_ACREN_WIDTH 1u
532 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
533 #define ADC_SC2_ACFGT_MASK 0x10u
534 #define ADC_SC2_ACFGT_SHIFT 4u
535 #define ADC_SC2_ACFGT_WIDTH 1u
536 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
537 #define ADC_SC2_ACFE_MASK 0x20u
538 #define ADC_SC2_ACFE_SHIFT 5u
539 #define ADC_SC2_ACFE_WIDTH 1u
540 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
541 #define ADC_SC2_ADTRG_MASK 0x40u
542 #define ADC_SC2_ADTRG_SHIFT 6u
543 #define ADC_SC2_ADTRG_WIDTH 1u
544 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
545 #define ADC_SC2_ADACT_MASK 0x80u
546 #define ADC_SC2_ADACT_SHIFT 7u
547 #define ADC_SC2_ADACT_WIDTH 1u
548 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
549 #define ADC_SC2_TRGPRNUM_MASK 0x6000u
550 #define ADC_SC2_TRGPRNUM_SHIFT 13u
551 #define ADC_SC2_TRGPRNUM_WIDTH 2u
552 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGPRNUM_SHIFT))&ADC_SC2_TRGPRNUM_MASK)
553 #define ADC_SC2_TRGSTLAT_MASK 0xF0000u
554 #define ADC_SC2_TRGSTLAT_SHIFT 16u
555 #define ADC_SC2_TRGSTLAT_WIDTH 4u
556 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTLAT_SHIFT))&ADC_SC2_TRGSTLAT_MASK)
557 #define ADC_SC2_TRGSTERR_MASK 0xF000000u
558 #define ADC_SC2_TRGSTERR_SHIFT 24u
559 #define ADC_SC2_TRGSTERR_WIDTH 4u
560 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTERR_SHIFT))&ADC_SC2_TRGSTERR_MASK)
561 /* SC3 Bit Fields */
562 #define ADC_SC3_AVGS_MASK 0x3u
563 #define ADC_SC3_AVGS_SHIFT 0u
564 #define ADC_SC3_AVGS_WIDTH 2u
565 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
566 #define ADC_SC3_AVGE_MASK 0x4u
567 #define ADC_SC3_AVGE_SHIFT 2u
568 #define ADC_SC3_AVGE_WIDTH 1u
569 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
570 #define ADC_SC3_ADCO_MASK 0x8u
571 #define ADC_SC3_ADCO_SHIFT 3u
572 #define ADC_SC3_ADCO_WIDTH 1u
573 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
574 #define ADC_SC3_CAL_MASK 0x80u
575 #define ADC_SC3_CAL_SHIFT 7u
576 #define ADC_SC3_CAL_WIDTH 1u
577 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
578 /* BASE_OFS Bit Fields */
579 #define ADC_BASE_OFS_BA_OFS_MASK 0xFFu
580 #define ADC_BASE_OFS_BA_OFS_SHIFT 0u
581 #define ADC_BASE_OFS_BA_OFS_WIDTH 8u
582 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_BASE_OFS_BA_OFS_SHIFT))&ADC_BASE_OFS_BA_OFS_MASK)
583 /* OFS Bit Fields */
584 #define ADC_OFS_OFS_MASK 0xFFFFu
585 #define ADC_OFS_OFS_SHIFT 0u
586 #define ADC_OFS_OFS_WIDTH 16u
587 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
588 /* USR_OFS Bit Fields */
589 #define ADC_USR_OFS_USR_OFS_MASK 0xFFu
590 #define ADC_USR_OFS_USR_OFS_SHIFT 0u
591 #define ADC_USR_OFS_USR_OFS_WIDTH 8u
592 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_USR_OFS_USR_OFS_SHIFT))&ADC_USR_OFS_USR_OFS_MASK)
593 /* XOFS Bit Fields */
594 #define ADC_XOFS_XOFS_MASK 0x3Fu
595 #define ADC_XOFS_XOFS_SHIFT 0u
596 #define ADC_XOFS_XOFS_WIDTH 6u
597 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_XOFS_XOFS_SHIFT))&ADC_XOFS_XOFS_MASK)
598 /* YOFS Bit Fields */
599 #define ADC_YOFS_YOFS_MASK 0xFFu
600 #define ADC_YOFS_YOFS_SHIFT 0u
601 #define ADC_YOFS_YOFS_WIDTH 8u
602 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_YOFS_YOFS_SHIFT))&ADC_YOFS_YOFS_MASK)
603 /* G Bit Fields */
604 #define ADC_G_G_MASK 0x7FFu
605 #define ADC_G_G_SHIFT 0u
606 #define ADC_G_G_WIDTH 11u
607 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x))<<ADC_G_G_SHIFT))&ADC_G_G_MASK)
608 /* UG Bit Fields */
609 #define ADC_UG_UG_MASK 0x3FFu
610 #define ADC_UG_UG_SHIFT 0u
611 #define ADC_UG_UG_WIDTH 10u
612 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x))<<ADC_UG_UG_SHIFT))&ADC_UG_UG_MASK)
613 /* CLPS Bit Fields */
614 #define ADC_CLPS_CLPS_MASK 0x7Fu
615 #define ADC_CLPS_CLPS_SHIFT 0u
616 #define ADC_CLPS_CLPS_WIDTH 7u
617 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
618 /* CLP3 Bit Fields */
619 #define ADC_CLP3_CLP3_MASK 0x3FFu
620 #define ADC_CLP3_CLP3_SHIFT 0u
621 #define ADC_CLP3_CLP3_WIDTH 10u
622 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
623 /* CLP2 Bit Fields */
624 #define ADC_CLP2_CLP2_MASK 0x3FFu
625 #define ADC_CLP2_CLP2_SHIFT 0u
626 #define ADC_CLP2_CLP2_WIDTH 10u
627 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
628 /* CLP1 Bit Fields */
629 #define ADC_CLP1_CLP1_MASK 0x1FFu
630 #define ADC_CLP1_CLP1_SHIFT 0u
631 #define ADC_CLP1_CLP1_WIDTH 9u
632 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
633 /* CLP0 Bit Fields */
634 #define ADC_CLP0_CLP0_MASK 0xFFu
635 #define ADC_CLP0_CLP0_SHIFT 0u
636 #define ADC_CLP0_CLP0_WIDTH 8u
637 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
638 /* CLPX Bit Fields */
639 #define ADC_CLPX_CLPX_MASK 0x7Fu
640 #define ADC_CLPX_CLPX_SHIFT 0u
641 #define ADC_CLPX_CLPX_WIDTH 7u
642 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_CLPX_SHIFT))&ADC_CLPX_CLPX_MASK)
643 /* CLP9 Bit Fields */
644 #define ADC_CLP9_CLP9_MASK 0x7Fu
645 #define ADC_CLP9_CLP9_SHIFT 0u
646 #define ADC_CLP9_CLP9_WIDTH 7u
647 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_CLP9_SHIFT))&ADC_CLP9_CLP9_MASK)
648 /* CLPS_OFS Bit Fields */
649 #define ADC_CLPS_OFS_CLPS_OFS_MASK 0xFu
650 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT 0u
651 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH 4u
652 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_OFS_CLPS_OFS_SHIFT))&ADC_CLPS_OFS_CLPS_OFS_MASK)
653 /* CLP3_OFS Bit Fields */
654 #define ADC_CLP3_OFS_CLP3_OFS_MASK 0xFu
655 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT 0u
656 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH 4u
657 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_OFS_CLP3_OFS_SHIFT))&ADC_CLP3_OFS_CLP3_OFS_MASK)
658 /* CLP2_OFS Bit Fields */
659 #define ADC_CLP2_OFS_CLP2_OFS_MASK 0xFu
660 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT 0u
661 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH 4u
662 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_OFS_CLP2_OFS_SHIFT))&ADC_CLP2_OFS_CLP2_OFS_MASK)
663 /* CLP1_OFS Bit Fields */
664 #define ADC_CLP1_OFS_CLP1_OFS_MASK 0xFu
665 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT 0u
666 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH 4u
667 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_OFS_CLP1_OFS_SHIFT))&ADC_CLP1_OFS_CLP1_OFS_MASK)
668 /* CLP0_OFS Bit Fields */
669 #define ADC_CLP0_OFS_CLP0_OFS_MASK 0xFu
670 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT 0u
671 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH 4u
672 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_OFS_CLP0_OFS_SHIFT))&ADC_CLP0_OFS_CLP0_OFS_MASK)
673 /* CLPX_OFS Bit Fields */
674 #define ADC_CLPX_OFS_CLPX_OFS_MASK 0xFFFu
675 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT 0u
676 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH 12u
677 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_OFS_CLPX_OFS_SHIFT))&ADC_CLPX_OFS_CLPX_OFS_MASK)
678 /* CLP9_OFS Bit Fields */
679 #define ADC_CLP9_OFS_CLP9_OFS_MASK 0xFFFu
680 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT 0u
681 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH 12u
682 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_OFS_CLP9_OFS_SHIFT))&ADC_CLP9_OFS_CLP9_OFS_MASK)
683  /* end of group ADC_Register_Masks */
687 
688  /* end of group ADC_Peripheral_Access_Layer */
692 
693 
694 /* ----------------------------------------------------------------------------
695  -- AIPS Peripheral Access Layer
696  ---------------------------------------------------------------------------- */
697 
705 #define AIPS_PACR_COUNT 4u
706 #define AIPS_OPACR_COUNT 12u
707 
709 typedef struct {
710  __IO uint32_t MPRA;
711  uint8_t RESERVED_0[28];
712  __IO uint32_t PACR[AIPS_PACR_COUNT];
713  uint8_t RESERVED_1[16];
714  __IO uint32_t OPACR[AIPS_OPACR_COUNT];
716 
718 #define AIPS_INSTANCE_COUNT (1u)
719 
720 
721 /* AIPS - Peripheral instance base addresses */
723 #define AIPS_BASE (0x40000000u)
724 
725 #define AIPS ((AIPS_Type *)AIPS_BASE)
726 
727 #define AIPS_BASE_ADDRS { AIPS_BASE }
728 
729 #define AIPS_BASE_PTRS { AIPS }
730 
731 /* ----------------------------------------------------------------------------
732  -- AIPS Register Masks
733  ---------------------------------------------------------------------------- */
734 
740 /* MPRA Bit Fields */
741 #define AIPS_MPRA_MPL2_MASK 0x100000u
742 #define AIPS_MPRA_MPL2_SHIFT 20u
743 #define AIPS_MPRA_MPL2_WIDTH 1u
744 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
745 #define AIPS_MPRA_MTW2_MASK 0x200000u
746 #define AIPS_MPRA_MTW2_SHIFT 21u
747 #define AIPS_MPRA_MTW2_WIDTH 1u
748 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
749 #define AIPS_MPRA_MTR2_MASK 0x400000u
750 #define AIPS_MPRA_MTR2_SHIFT 22u
751 #define AIPS_MPRA_MTR2_WIDTH 1u
752 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
753 #define AIPS_MPRA_MPL1_MASK 0x1000000u
754 #define AIPS_MPRA_MPL1_SHIFT 24u
755 #define AIPS_MPRA_MPL1_WIDTH 1u
756 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
757 #define AIPS_MPRA_MTW1_MASK 0x2000000u
758 #define AIPS_MPRA_MTW1_SHIFT 25u
759 #define AIPS_MPRA_MTW1_WIDTH 1u
760 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
761 #define AIPS_MPRA_MTR1_MASK 0x4000000u
762 #define AIPS_MPRA_MTR1_SHIFT 26u
763 #define AIPS_MPRA_MTR1_WIDTH 1u
764 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
765 #define AIPS_MPRA_MPL0_MASK 0x10000000u
766 #define AIPS_MPRA_MPL0_SHIFT 28u
767 #define AIPS_MPRA_MPL0_WIDTH 1u
768 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
769 #define AIPS_MPRA_MTW0_MASK 0x20000000u
770 #define AIPS_MPRA_MTW0_SHIFT 29u
771 #define AIPS_MPRA_MTW0_WIDTH 1u
772 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
773 #define AIPS_MPRA_MTR0_MASK 0x40000000u
774 #define AIPS_MPRA_MTR0_SHIFT 30u
775 #define AIPS_MPRA_MTR0_WIDTH 1u
776 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
777 /* PACR Bit Fields */
778 #define AIPS_PACR_TP5_MASK 0x100u
779 #define AIPS_PACR_TP5_SHIFT 8u
780 #define AIPS_PACR_TP5_WIDTH 1u
781 #define AIPS_PACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP5_SHIFT))&AIPS_PACR_TP5_MASK)
782 #define AIPS_PACR_WP5_MASK 0x200u
783 #define AIPS_PACR_WP5_SHIFT 9u
784 #define AIPS_PACR_WP5_WIDTH 1u
785 #define AIPS_PACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP5_SHIFT))&AIPS_PACR_WP5_MASK)
786 #define AIPS_PACR_SP5_MASK 0x400u
787 #define AIPS_PACR_SP5_SHIFT 10u
788 #define AIPS_PACR_SP5_WIDTH 1u
789 #define AIPS_PACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP5_SHIFT))&AIPS_PACR_SP5_MASK)
790 #define AIPS_PACR_TP1_MASK 0x1000000u
791 #define AIPS_PACR_TP1_SHIFT 24u
792 #define AIPS_PACR_TP1_WIDTH 1u
793 #define AIPS_PACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP1_SHIFT))&AIPS_PACR_TP1_MASK)
794 #define AIPS_PACR_WP1_MASK 0x2000000u
795 #define AIPS_PACR_WP1_SHIFT 25u
796 #define AIPS_PACR_WP1_WIDTH 1u
797 #define AIPS_PACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP1_SHIFT))&AIPS_PACR_WP1_MASK)
798 #define AIPS_PACR_SP1_MASK 0x4000000u
799 #define AIPS_PACR_SP1_SHIFT 26u
800 #define AIPS_PACR_SP1_WIDTH 1u
801 #define AIPS_PACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP1_SHIFT))&AIPS_PACR_SP1_MASK)
802 #define AIPS_PACR_TP0_MASK 0x10000000u
803 #define AIPS_PACR_TP0_SHIFT 28u
804 #define AIPS_PACR_TP0_WIDTH 1u
805 #define AIPS_PACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP0_SHIFT))&AIPS_PACR_TP0_MASK)
806 #define AIPS_PACR_WP0_MASK 0x20000000u
807 #define AIPS_PACR_WP0_SHIFT 29u
808 #define AIPS_PACR_WP0_WIDTH 1u
809 #define AIPS_PACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP0_SHIFT))&AIPS_PACR_WP0_MASK)
810 #define AIPS_PACR_SP0_MASK 0x40000000u
811 #define AIPS_PACR_SP0_SHIFT 30u
812 #define AIPS_PACR_SP0_WIDTH 1u
813 #define AIPS_PACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP0_SHIFT))&AIPS_PACR_SP0_MASK)
814 /* OPACR Bit Fields */
815 #define AIPS_OPACR_TP7_MASK 0x1u
816 #define AIPS_OPACR_TP7_SHIFT 0u
817 #define AIPS_OPACR_TP7_WIDTH 1u
818 #define AIPS_OPACR_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP7_SHIFT))&AIPS_OPACR_TP7_MASK)
819 #define AIPS_OPACR_WP7_MASK 0x2u
820 #define AIPS_OPACR_WP7_SHIFT 1u
821 #define AIPS_OPACR_WP7_WIDTH 1u
822 #define AIPS_OPACR_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP7_SHIFT))&AIPS_OPACR_WP7_MASK)
823 #define AIPS_OPACR_SP7_MASK 0x4u
824 #define AIPS_OPACR_SP7_SHIFT 2u
825 #define AIPS_OPACR_SP7_WIDTH 1u
826 #define AIPS_OPACR_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP7_SHIFT))&AIPS_OPACR_SP7_MASK)
827 #define AIPS_OPACR_TP6_MASK 0x10u
828 #define AIPS_OPACR_TP6_SHIFT 4u
829 #define AIPS_OPACR_TP6_WIDTH 1u
830 #define AIPS_OPACR_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP6_SHIFT))&AIPS_OPACR_TP6_MASK)
831 #define AIPS_OPACR_WP6_MASK 0x20u
832 #define AIPS_OPACR_WP6_SHIFT 5u
833 #define AIPS_OPACR_WP6_WIDTH 1u
834 #define AIPS_OPACR_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP6_SHIFT))&AIPS_OPACR_WP6_MASK)
835 #define AIPS_OPACR_SP6_MASK 0x40u
836 #define AIPS_OPACR_SP6_SHIFT 6u
837 #define AIPS_OPACR_SP6_WIDTH 1u
838 #define AIPS_OPACR_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP6_SHIFT))&AIPS_OPACR_SP6_MASK)
839 #define AIPS_OPACR_TP5_MASK 0x100u
840 #define AIPS_OPACR_TP5_SHIFT 8u
841 #define AIPS_OPACR_TP5_WIDTH 1u
842 #define AIPS_OPACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP5_SHIFT))&AIPS_OPACR_TP5_MASK)
843 #define AIPS_OPACR_WP5_MASK 0x200u
844 #define AIPS_OPACR_WP5_SHIFT 9u
845 #define AIPS_OPACR_WP5_WIDTH 1u
846 #define AIPS_OPACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP5_SHIFT))&AIPS_OPACR_WP5_MASK)
847 #define AIPS_OPACR_SP5_MASK 0x400u
848 #define AIPS_OPACR_SP5_SHIFT 10u
849 #define AIPS_OPACR_SP5_WIDTH 1u
850 #define AIPS_OPACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP5_SHIFT))&AIPS_OPACR_SP5_MASK)
851 #define AIPS_OPACR_TP4_MASK 0x1000u
852 #define AIPS_OPACR_TP4_SHIFT 12u
853 #define AIPS_OPACR_TP4_WIDTH 1u
854 #define AIPS_OPACR_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP4_SHIFT))&AIPS_OPACR_TP4_MASK)
855 #define AIPS_OPACR_WP4_MASK 0x2000u
856 #define AIPS_OPACR_WP4_SHIFT 13u
857 #define AIPS_OPACR_WP4_WIDTH 1u
858 #define AIPS_OPACR_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP4_SHIFT))&AIPS_OPACR_WP4_MASK)
859 #define AIPS_OPACR_SP4_MASK 0x4000u
860 #define AIPS_OPACR_SP4_SHIFT 14u
861 #define AIPS_OPACR_SP4_WIDTH 1u
862 #define AIPS_OPACR_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP4_SHIFT))&AIPS_OPACR_SP4_MASK)
863 #define AIPS_OPACR_TP3_MASK 0x10000u
864 #define AIPS_OPACR_TP3_SHIFT 16u
865 #define AIPS_OPACR_TP3_WIDTH 1u
866 #define AIPS_OPACR_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP3_SHIFT))&AIPS_OPACR_TP3_MASK)
867 #define AIPS_OPACR_WP3_MASK 0x20000u
868 #define AIPS_OPACR_WP3_SHIFT 17u
869 #define AIPS_OPACR_WP3_WIDTH 1u
870 #define AIPS_OPACR_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP3_SHIFT))&AIPS_OPACR_WP3_MASK)
871 #define AIPS_OPACR_SP3_MASK 0x40000u
872 #define AIPS_OPACR_SP3_SHIFT 18u
873 #define AIPS_OPACR_SP3_WIDTH 1u
874 #define AIPS_OPACR_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP3_SHIFT))&AIPS_OPACR_SP3_MASK)
875 #define AIPS_OPACR_TP2_MASK 0x100000u
876 #define AIPS_OPACR_TP2_SHIFT 20u
877 #define AIPS_OPACR_TP2_WIDTH 1u
878 #define AIPS_OPACR_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP2_SHIFT))&AIPS_OPACR_TP2_MASK)
879 #define AIPS_OPACR_WP2_MASK 0x200000u
880 #define AIPS_OPACR_WP2_SHIFT 21u
881 #define AIPS_OPACR_WP2_WIDTH 1u
882 #define AIPS_OPACR_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP2_SHIFT))&AIPS_OPACR_WP2_MASK)
883 #define AIPS_OPACR_SP2_MASK 0x400000u
884 #define AIPS_OPACR_SP2_SHIFT 22u
885 #define AIPS_OPACR_SP2_WIDTH 1u
886 #define AIPS_OPACR_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP2_SHIFT))&AIPS_OPACR_SP2_MASK)
887 #define AIPS_OPACR_TP1_MASK 0x1000000u
888 #define AIPS_OPACR_TP1_SHIFT 24u
889 #define AIPS_OPACR_TP1_WIDTH 1u
890 #define AIPS_OPACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP1_SHIFT))&AIPS_OPACR_TP1_MASK)
891 #define AIPS_OPACR_WP1_MASK 0x2000000u
892 #define AIPS_OPACR_WP1_SHIFT 25u
893 #define AIPS_OPACR_WP1_WIDTH 1u
894 #define AIPS_OPACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP1_SHIFT))&AIPS_OPACR_WP1_MASK)
895 #define AIPS_OPACR_SP1_MASK 0x4000000u
896 #define AIPS_OPACR_SP1_SHIFT 26u
897 #define AIPS_OPACR_SP1_WIDTH 1u
898 #define AIPS_OPACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP1_SHIFT))&AIPS_OPACR_SP1_MASK)
899 #define AIPS_OPACR_TP0_MASK 0x10000000u
900 #define AIPS_OPACR_TP0_SHIFT 28u
901 #define AIPS_OPACR_TP0_WIDTH 1u
902 #define AIPS_OPACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP0_SHIFT))&AIPS_OPACR_TP0_MASK)
903 #define AIPS_OPACR_WP0_MASK 0x20000000u
904 #define AIPS_OPACR_WP0_SHIFT 29u
905 #define AIPS_OPACR_WP0_WIDTH 1u
906 #define AIPS_OPACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP0_SHIFT))&AIPS_OPACR_WP0_MASK)
907 #define AIPS_OPACR_SP0_MASK 0x40000000u
908 #define AIPS_OPACR_SP0_SHIFT 30u
909 #define AIPS_OPACR_SP0_WIDTH 1u
910 #define AIPS_OPACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP0_SHIFT))&AIPS_OPACR_SP0_MASK)
911  /* end of group AIPS_Register_Masks */
915 
916  /* end of group AIPS_Peripheral_Access_Layer */
920 
921 
922 /* ----------------------------------------------------------------------------
923  -- CAN Peripheral Access Layer
924  ---------------------------------------------------------------------------- */
925 
933 #define CAN_RAMn_COUNT 128u
934 #define CAN_RXIMR_COUNT 16u
935 #define CAN_WMB_COUNT 4u
936 
938 typedef struct {
939  __IO uint32_t MCR;
940  __IO uint32_t CTRL1;
941  __IO uint32_t TIMER;
942  uint8_t RESERVED_0[4];
943  __IO uint32_t RXMGMASK;
944  __IO uint32_t RX14MASK;
945  __IO uint32_t RX15MASK;
946  __IO uint32_t ECR;
947  __IO uint32_t ESR1;
948  uint8_t RESERVED_1[4];
949  __IO uint32_t IMASK1;
950  uint8_t RESERVED_2[4];
951  __IO uint32_t IFLAG1;
952  __IO uint32_t CTRL2;
953  __I uint32_t ESR2;
954  uint8_t RESERVED_3[8];
955  __I uint32_t CRCR;
956  __IO uint32_t RXFGMASK;
957  __I uint32_t RXFIR;
958  __IO uint32_t CBT;
959  uint8_t RESERVED_4[44];
960  __IO uint32_t RAMn[CAN_RAMn_COUNT];
961  uint8_t RESERVED_5[1536];
962  __IO uint32_t RXIMR[CAN_RXIMR_COUNT];
963  uint8_t RESERVED_6[576];
964  __IO uint32_t CTRL1_PN;
965  __IO uint32_t CTRL2_PN;
966  __IO uint32_t WU_MTC;
967  __IO uint32_t FLT_ID1;
968  __IO uint32_t FLT_DLC;
969  __IO uint32_t PL1_LO;
970  __IO uint32_t PL1_HI;
971  __IO uint32_t FLT_ID2_IDMASK;
972  __IO uint32_t PL2_PLMASK_LO;
973  __IO uint32_t PL2_PLMASK_HI;
974  uint8_t RESERVED_7[24];
975  struct { /* offset: 0xB40, array step: 0x10 */
976  __I uint32_t WMBn_CS;
977  __I uint32_t WMBn_ID;
978  __I uint32_t WMBn_D03;
979  __I uint32_t WMBn_D47;
980  } WMB[CAN_WMB_COUNT];
981  uint8_t RESERVED_8[128];
982  __IO uint32_t FDCTRL;
983  __IO uint32_t FDCBT;
984  __I uint32_t FDCRC;
986 
988 #define CAN_INSTANCE_COUNT (3u)
989 
990 
991 /* CAN - Peripheral instance base addresses */
993 #define CAN0_BASE (0x40024000u)
994 
995 #define CAN0 ((CAN_Type *)CAN0_BASE)
996 
997 #define CAN1_BASE (0x40025000u)
998 
999 #define CAN1 ((CAN_Type *)CAN1_BASE)
1000 
1001 #define CAN2_BASE (0x4002B000u)
1002 
1003 #define CAN2 ((CAN_Type *)CAN2_BASE)
1004 
1005 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE }
1006 
1007 #define CAN_BASE_PTRS { CAN0, CAN1, CAN2 }
1008 
1009 #define CAN_IRQS_ARR_COUNT (7u)
1010 
1011 #define CAN_Rx_Warning_IRQS_CH_COUNT (1u)
1012 
1013 #define CAN_Tx_Warning_IRQS_CH_COUNT (1u)
1014 
1015 #define CAN_Wake_Up_IRQS_CH_COUNT (1u)
1016 
1017 #define CAN_Error_IRQS_CH_COUNT (1u)
1018 
1019 #define CAN_Bus_Off_IRQS_CH_COUNT (1u)
1020 
1021 #define CAN_ORed_0_15_MB_IRQS_CH_COUNT (1u)
1022 
1023 #define CAN_ORed_16_31_MB_IRQS_CH_COUNT (1u)
1024 
1025 #define CAN_Rx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
1026 #define CAN_Tx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
1027 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, NotAvail_IRQn, NotAvail_IRQn }
1028 #define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn, CAN2_Error_IRQn }
1029 #define CAN_Bus_Off_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
1030 #define CAN_ORed_0_15_MB_IRQS { CAN0_ORed_0_15_MB_IRQn, CAN1_ORed_0_15_MB_IRQn, CAN2_ORed_0_15_MB_IRQn }
1031 #define CAN_ORed_16_31_MB_IRQS { CAN0_ORed_16_31_MB_IRQn, NotAvail_IRQn, NotAvail_IRQn }
1032 
1033 /* ----------------------------------------------------------------------------
1034  -- CAN Register Masks
1035  ---------------------------------------------------------------------------- */
1036 
1042 /* MCR Bit Fields */
1043 #define CAN_MCR_MAXMB_MASK 0x7Fu
1044 #define CAN_MCR_MAXMB_SHIFT 0u
1045 #define CAN_MCR_MAXMB_WIDTH 7u
1046 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
1047 #define CAN_MCR_IDAM_MASK 0x300u
1048 #define CAN_MCR_IDAM_SHIFT 8u
1049 #define CAN_MCR_IDAM_WIDTH 2u
1050 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
1051 #define CAN_MCR_FDEN_MASK 0x800u
1052 #define CAN_MCR_FDEN_SHIFT 11u
1053 #define CAN_MCR_FDEN_WIDTH 1u
1054 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FDEN_SHIFT))&CAN_MCR_FDEN_MASK)
1055 #define CAN_MCR_AEN_MASK 0x1000u
1056 #define CAN_MCR_AEN_SHIFT 12u
1057 #define CAN_MCR_AEN_WIDTH 1u
1058 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
1059 #define CAN_MCR_LPRIOEN_MASK 0x2000u
1060 #define CAN_MCR_LPRIOEN_SHIFT 13u
1061 #define CAN_MCR_LPRIOEN_WIDTH 1u
1062 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
1063 #define CAN_MCR_PNET_EN_MASK 0x4000u
1064 #define CAN_MCR_PNET_EN_SHIFT 14u
1065 #define CAN_MCR_PNET_EN_WIDTH 1u
1066 #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_PNET_EN_SHIFT))&CAN_MCR_PNET_EN_MASK)
1067 #define CAN_MCR_DMA_MASK 0x8000u
1068 #define CAN_MCR_DMA_SHIFT 15u
1069 #define CAN_MCR_DMA_WIDTH 1u
1070 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
1071 #define CAN_MCR_IRMQ_MASK 0x10000u
1072 #define CAN_MCR_IRMQ_SHIFT 16u
1073 #define CAN_MCR_IRMQ_WIDTH 1u
1074 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
1075 #define CAN_MCR_SRXDIS_MASK 0x20000u
1076 #define CAN_MCR_SRXDIS_SHIFT 17u
1077 #define CAN_MCR_SRXDIS_WIDTH 1u
1078 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
1079 #define CAN_MCR_LPMACK_MASK 0x100000u
1080 #define CAN_MCR_LPMACK_SHIFT 20u
1081 #define CAN_MCR_LPMACK_WIDTH 1u
1082 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
1083 #define CAN_MCR_WRNEN_MASK 0x200000u
1084 #define CAN_MCR_WRNEN_SHIFT 21u
1085 #define CAN_MCR_WRNEN_WIDTH 1u
1086 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
1087 #define CAN_MCR_SUPV_MASK 0x800000u
1088 #define CAN_MCR_SUPV_SHIFT 23u
1089 #define CAN_MCR_SUPV_WIDTH 1u
1090 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
1091 #define CAN_MCR_FRZACK_MASK 0x1000000u
1092 #define CAN_MCR_FRZACK_SHIFT 24u
1093 #define CAN_MCR_FRZACK_WIDTH 1u
1094 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
1095 #define CAN_MCR_SOFTRST_MASK 0x2000000u
1096 #define CAN_MCR_SOFTRST_SHIFT 25u
1097 #define CAN_MCR_SOFTRST_WIDTH 1u
1098 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
1099 #define CAN_MCR_NOTRDY_MASK 0x8000000u
1100 #define CAN_MCR_NOTRDY_SHIFT 27u
1101 #define CAN_MCR_NOTRDY_WIDTH 1u
1102 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
1103 #define CAN_MCR_HALT_MASK 0x10000000u
1104 #define CAN_MCR_HALT_SHIFT 28u
1105 #define CAN_MCR_HALT_WIDTH 1u
1106 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
1107 #define CAN_MCR_RFEN_MASK 0x20000000u
1108 #define CAN_MCR_RFEN_SHIFT 29u
1109 #define CAN_MCR_RFEN_WIDTH 1u
1110 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
1111 #define CAN_MCR_FRZ_MASK 0x40000000u
1112 #define CAN_MCR_FRZ_SHIFT 30u
1113 #define CAN_MCR_FRZ_WIDTH 1u
1114 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
1115 #define CAN_MCR_MDIS_MASK 0x80000000u
1116 #define CAN_MCR_MDIS_SHIFT 31u
1117 #define CAN_MCR_MDIS_WIDTH 1u
1118 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
1119 /* CTRL1 Bit Fields */
1120 #define CAN_CTRL1_PROPSEG_MASK 0x7u
1121 #define CAN_CTRL1_PROPSEG_SHIFT 0u
1122 #define CAN_CTRL1_PROPSEG_WIDTH 3u
1123 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
1124 #define CAN_CTRL1_LOM_MASK 0x8u
1125 #define CAN_CTRL1_LOM_SHIFT 3u
1126 #define CAN_CTRL1_LOM_WIDTH 1u
1127 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
1128 #define CAN_CTRL1_LBUF_MASK 0x10u
1129 #define CAN_CTRL1_LBUF_SHIFT 4u
1130 #define CAN_CTRL1_LBUF_WIDTH 1u
1131 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
1132 #define CAN_CTRL1_TSYN_MASK 0x20u
1133 #define CAN_CTRL1_TSYN_SHIFT 5u
1134 #define CAN_CTRL1_TSYN_WIDTH 1u
1135 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
1136 #define CAN_CTRL1_BOFFREC_MASK 0x40u
1137 #define CAN_CTRL1_BOFFREC_SHIFT 6u
1138 #define CAN_CTRL1_BOFFREC_WIDTH 1u
1139 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
1140 #define CAN_CTRL1_SMP_MASK 0x80u
1141 #define CAN_CTRL1_SMP_SHIFT 7u
1142 #define CAN_CTRL1_SMP_WIDTH 1u
1143 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
1144 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
1145 #define CAN_CTRL1_RWRNMSK_SHIFT 10u
1146 #define CAN_CTRL1_RWRNMSK_WIDTH 1u
1147 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
1148 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
1149 #define CAN_CTRL1_TWRNMSK_SHIFT 11u
1150 #define CAN_CTRL1_TWRNMSK_WIDTH 1u
1151 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
1152 #define CAN_CTRL1_LPB_MASK 0x1000u
1153 #define CAN_CTRL1_LPB_SHIFT 12u
1154 #define CAN_CTRL1_LPB_WIDTH 1u
1155 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
1156 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1157 #define CAN_CTRL1_CLKSRC_SHIFT 13u
1158 #define CAN_CTRL1_CLKSRC_WIDTH 1u
1159 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
1160 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1161 #define CAN_CTRL1_ERRMSK_SHIFT 14u
1162 #define CAN_CTRL1_ERRMSK_WIDTH 1u
1163 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
1164 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1165 #define CAN_CTRL1_BOFFMSK_SHIFT 15u
1166 #define CAN_CTRL1_BOFFMSK_WIDTH 1u
1167 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
1168 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1169 #define CAN_CTRL1_PSEG2_SHIFT 16u
1170 #define CAN_CTRL1_PSEG2_WIDTH 3u
1171 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1172 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1173 #define CAN_CTRL1_PSEG1_SHIFT 19u
1174 #define CAN_CTRL1_PSEG1_WIDTH 3u
1175 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1176 #define CAN_CTRL1_RJW_MASK 0xC00000u
1177 #define CAN_CTRL1_RJW_SHIFT 22u
1178 #define CAN_CTRL1_RJW_WIDTH 2u
1179 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1180 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
1181 #define CAN_CTRL1_PRESDIV_SHIFT 24u
1182 #define CAN_CTRL1_PRESDIV_WIDTH 8u
1183 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
1184 /* TIMER Bit Fields */
1185 #define CAN_TIMER_TIMER_MASK 0xFFFFu
1186 #define CAN_TIMER_TIMER_SHIFT 0u
1187 #define CAN_TIMER_TIMER_WIDTH 16u
1188 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
1189 /* RXMGMASK Bit Fields */
1190 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
1191 #define CAN_RXMGMASK_MG_SHIFT 0u
1192 #define CAN_RXMGMASK_MG_WIDTH 32u
1193 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
1194 /* RX14MASK Bit Fields */
1195 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
1196 #define CAN_RX14MASK_RX14M_SHIFT 0u
1197 #define CAN_RX14MASK_RX14M_WIDTH 32u
1198 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
1199 /* RX15MASK Bit Fields */
1200 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
1201 #define CAN_RX15MASK_RX15M_SHIFT 0u
1202 #define CAN_RX15MASK_RX15M_WIDTH 32u
1203 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
1204 /* ECR Bit Fields */
1205 #define CAN_ECR_TXERRCNT_MASK 0xFFu
1206 #define CAN_ECR_TXERRCNT_SHIFT 0u
1207 #define CAN_ECR_TXERRCNT_WIDTH 8u
1208 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
1209 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
1210 #define CAN_ECR_RXERRCNT_SHIFT 8u
1211 #define CAN_ECR_RXERRCNT_WIDTH 8u
1212 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
1213 #define CAN_ECR_TXERRCNT_FAST_MASK 0xFF0000u
1214 #define CAN_ECR_TXERRCNT_FAST_SHIFT 16u
1215 #define CAN_ECR_TXERRCNT_FAST_WIDTH 8u
1216 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_FAST_SHIFT))&CAN_ECR_TXERRCNT_FAST_MASK)
1217 #define CAN_ECR_RXERRCNT_FAST_MASK 0xFF000000u
1218 #define CAN_ECR_RXERRCNT_FAST_SHIFT 24u
1219 #define CAN_ECR_RXERRCNT_FAST_WIDTH 8u
1220 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_FAST_SHIFT))&CAN_ECR_RXERRCNT_FAST_MASK)
1221 /* ESR1 Bit Fields */
1222 #define CAN_ESR1_ERRINT_MASK 0x2u
1223 #define CAN_ESR1_ERRINT_SHIFT 1u
1224 #define CAN_ESR1_ERRINT_WIDTH 1u
1225 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
1226 #define CAN_ESR1_BOFFINT_MASK 0x4u
1227 #define CAN_ESR1_BOFFINT_SHIFT 2u
1228 #define CAN_ESR1_BOFFINT_WIDTH 1u
1229 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
1230 #define CAN_ESR1_RX_MASK 0x8u
1231 #define CAN_ESR1_RX_SHIFT 3u
1232 #define CAN_ESR1_RX_WIDTH 1u
1233 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
1234 #define CAN_ESR1_FLTCONF_MASK 0x30u
1235 #define CAN_ESR1_FLTCONF_SHIFT 4u
1236 #define CAN_ESR1_FLTCONF_WIDTH 2u
1237 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
1238 #define CAN_ESR1_TX_MASK 0x40u
1239 #define CAN_ESR1_TX_SHIFT 6u
1240 #define CAN_ESR1_TX_WIDTH 1u
1241 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
1242 #define CAN_ESR1_IDLE_MASK 0x80u
1243 #define CAN_ESR1_IDLE_SHIFT 7u
1244 #define CAN_ESR1_IDLE_WIDTH 1u
1245 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
1246 #define CAN_ESR1_RXWRN_MASK 0x100u
1247 #define CAN_ESR1_RXWRN_SHIFT 8u
1248 #define CAN_ESR1_RXWRN_WIDTH 1u
1249 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
1250 #define CAN_ESR1_TXWRN_MASK 0x200u
1251 #define CAN_ESR1_TXWRN_SHIFT 9u
1252 #define CAN_ESR1_TXWRN_WIDTH 1u
1253 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
1254 #define CAN_ESR1_STFERR_MASK 0x400u
1255 #define CAN_ESR1_STFERR_SHIFT 10u
1256 #define CAN_ESR1_STFERR_WIDTH 1u
1257 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
1258 #define CAN_ESR1_FRMERR_MASK 0x800u
1259 #define CAN_ESR1_FRMERR_SHIFT 11u
1260 #define CAN_ESR1_FRMERR_WIDTH 1u
1261 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
1262 #define CAN_ESR1_CRCERR_MASK 0x1000u
1263 #define CAN_ESR1_CRCERR_SHIFT 12u
1264 #define CAN_ESR1_CRCERR_WIDTH 1u
1265 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
1266 #define CAN_ESR1_ACKERR_MASK 0x2000u
1267 #define CAN_ESR1_ACKERR_SHIFT 13u
1268 #define CAN_ESR1_ACKERR_WIDTH 1u
1269 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
1270 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
1271 #define CAN_ESR1_BIT0ERR_SHIFT 14u
1272 #define CAN_ESR1_BIT0ERR_WIDTH 1u
1273 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
1274 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
1275 #define CAN_ESR1_BIT1ERR_SHIFT 15u
1276 #define CAN_ESR1_BIT1ERR_WIDTH 1u
1277 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
1278 #define CAN_ESR1_RWRNINT_MASK 0x10000u
1279 #define CAN_ESR1_RWRNINT_SHIFT 16u
1280 #define CAN_ESR1_RWRNINT_WIDTH 1u
1281 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
1282 #define CAN_ESR1_TWRNINT_MASK 0x20000u
1283 #define CAN_ESR1_TWRNINT_SHIFT 17u
1284 #define CAN_ESR1_TWRNINT_WIDTH 1u
1285 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
1286 #define CAN_ESR1_SYNCH_MASK 0x40000u
1287 #define CAN_ESR1_SYNCH_SHIFT 18u
1288 #define CAN_ESR1_SYNCH_WIDTH 1u
1289 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
1290 #define CAN_ESR1_BOFFDONEINT_MASK 0x80000u
1291 #define CAN_ESR1_BOFFDONEINT_SHIFT 19u
1292 #define CAN_ESR1_BOFFDONEINT_WIDTH 1u
1293 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
1294 #define CAN_ESR1_ERRINT_FAST_MASK 0x100000u
1295 #define CAN_ESR1_ERRINT_FAST_SHIFT 20u
1296 #define CAN_ESR1_ERRINT_FAST_WIDTH 1u
1297 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_FAST_SHIFT))&CAN_ESR1_ERRINT_FAST_MASK)
1298 #define CAN_ESR1_ERROVR_MASK 0x200000u
1299 #define CAN_ESR1_ERROVR_SHIFT 21u
1300 #define CAN_ESR1_ERROVR_WIDTH 1u
1301 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
1302 #define CAN_ESR1_STFERR_FAST_MASK 0x4000000u
1303 #define CAN_ESR1_STFERR_FAST_SHIFT 26u
1304 #define CAN_ESR1_STFERR_FAST_WIDTH 1u
1305 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_FAST_SHIFT))&CAN_ESR1_STFERR_FAST_MASK)
1306 #define CAN_ESR1_FRMERR_FAST_MASK 0x8000000u
1307 #define CAN_ESR1_FRMERR_FAST_SHIFT 27u
1308 #define CAN_ESR1_FRMERR_FAST_WIDTH 1u
1309 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_FAST_SHIFT))&CAN_ESR1_FRMERR_FAST_MASK)
1310 #define CAN_ESR1_CRCERR_FAST_MASK 0x10000000u
1311 #define CAN_ESR1_CRCERR_FAST_SHIFT 28u
1312 #define CAN_ESR1_CRCERR_FAST_WIDTH 1u
1313 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_FAST_SHIFT))&CAN_ESR1_CRCERR_FAST_MASK)
1314 #define CAN_ESR1_BIT0ERR_FAST_MASK 0x40000000u
1315 #define CAN_ESR1_BIT0ERR_FAST_SHIFT 30u
1316 #define CAN_ESR1_BIT0ERR_FAST_WIDTH 1u
1317 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_FAST_SHIFT))&CAN_ESR1_BIT0ERR_FAST_MASK)
1318 #define CAN_ESR1_BIT1ERR_FAST_MASK 0x80000000u
1319 #define CAN_ESR1_BIT1ERR_FAST_SHIFT 31u
1320 #define CAN_ESR1_BIT1ERR_FAST_WIDTH 1u
1321 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_FAST_SHIFT))&CAN_ESR1_BIT1ERR_FAST_MASK)
1322 /* IMASK1 Bit Fields */
1323 #define CAN_IMASK1_BUF31TO0M_MASK 0xFFFFFFFFu
1324 #define CAN_IMASK1_BUF31TO0M_SHIFT 0u
1325 #define CAN_IMASK1_BUF31TO0M_WIDTH 32u
1326 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
1327 /* IFLAG1 Bit Fields */
1328 #define CAN_IFLAG1_BUF0I_MASK 0x1u
1329 #define CAN_IFLAG1_BUF0I_SHIFT 0u
1330 #define CAN_IFLAG1_BUF0I_WIDTH 1u
1331 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
1332 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
1333 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1u
1334 #define CAN_IFLAG1_BUF4TO1I_WIDTH 4u
1335 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
1336 #define CAN_IFLAG1_BUF5I_MASK 0x20u
1337 #define CAN_IFLAG1_BUF5I_SHIFT 5u
1338 #define CAN_IFLAG1_BUF5I_WIDTH 1u
1339 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
1340 #define CAN_IFLAG1_BUF6I_MASK 0x40u
1341 #define CAN_IFLAG1_BUF6I_SHIFT 6u
1342 #define CAN_IFLAG1_BUF6I_WIDTH 1u
1343 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
1344 #define CAN_IFLAG1_BUF7I_MASK 0x80u
1345 #define CAN_IFLAG1_BUF7I_SHIFT 7u
1346 #define CAN_IFLAG1_BUF7I_WIDTH 1u
1347 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
1348 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
1349 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8u
1350 #define CAN_IFLAG1_BUF31TO8I_WIDTH 24u
1351 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
1352 /* CTRL2 Bit Fields */
1353 #define CAN_CTRL2_EDFLTDIS_MASK 0x800u
1354 #define CAN_CTRL2_EDFLTDIS_SHIFT 11u
1355 #define CAN_CTRL2_EDFLTDIS_WIDTH 1u
1356 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EDFLTDIS_SHIFT))&CAN_CTRL2_EDFLTDIS_MASK)
1357 #define CAN_CTRL2_ISOCANFDEN_MASK 0x1000u
1358 #define CAN_CTRL2_ISOCANFDEN_SHIFT 12u
1359 #define CAN_CTRL2_ISOCANFDEN_WIDTH 1u
1360 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ISOCANFDEN_SHIFT))&CAN_CTRL2_ISOCANFDEN_MASK)
1361 #define CAN_CTRL2_PREXCEN_MASK 0x4000u
1362 #define CAN_CTRL2_PREXCEN_SHIFT 14u
1363 #define CAN_CTRL2_PREXCEN_WIDTH 1u
1364 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PREXCEN_SHIFT))&CAN_CTRL2_PREXCEN_MASK)
1365 #define CAN_CTRL2_TIMER_SRC_MASK 0x8000u
1366 #define CAN_CTRL2_TIMER_SRC_SHIFT 15u
1367 #define CAN_CTRL2_TIMER_SRC_WIDTH 1u
1368 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TIMER_SRC_SHIFT))&CAN_CTRL2_TIMER_SRC_MASK)
1369 #define CAN_CTRL2_EACEN_MASK 0x10000u
1370 #define CAN_CTRL2_EACEN_SHIFT 16u
1371 #define CAN_CTRL2_EACEN_WIDTH 1u
1372 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
1373 #define CAN_CTRL2_RRS_MASK 0x20000u
1374 #define CAN_CTRL2_RRS_SHIFT 17u
1375 #define CAN_CTRL2_RRS_WIDTH 1u
1376 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
1377 #define CAN_CTRL2_MRP_MASK 0x40000u
1378 #define CAN_CTRL2_MRP_SHIFT 18u
1379 #define CAN_CTRL2_MRP_WIDTH 1u
1380 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
1381 #define CAN_CTRL2_TASD_MASK 0xF80000u
1382 #define CAN_CTRL2_TASD_SHIFT 19u
1383 #define CAN_CTRL2_TASD_WIDTH 5u
1384 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
1385 #define CAN_CTRL2_RFFN_MASK 0xF000000u
1386 #define CAN_CTRL2_RFFN_SHIFT 24u
1387 #define CAN_CTRL2_RFFN_WIDTH 4u
1388 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
1389 #define CAN_CTRL2_BOFFDONEMSK_MASK 0x40000000u
1390 #define CAN_CTRL2_BOFFDONEMSK_SHIFT 30u
1391 #define CAN_CTRL2_BOFFDONEMSK_WIDTH 1u
1392 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
1393 #define CAN_CTRL2_ERRMSK_FAST_MASK 0x80000000u
1394 #define CAN_CTRL2_ERRMSK_FAST_SHIFT 31u
1395 #define CAN_CTRL2_ERRMSK_FAST_WIDTH 1u
1396 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ERRMSK_FAST_SHIFT))&CAN_CTRL2_ERRMSK_FAST_MASK)
1397 /* ESR2 Bit Fields */
1398 #define CAN_ESR2_IMB_MASK 0x2000u
1399 #define CAN_ESR2_IMB_SHIFT 13u
1400 #define CAN_ESR2_IMB_WIDTH 1u
1401 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
1402 #define CAN_ESR2_VPS_MASK 0x4000u
1403 #define CAN_ESR2_VPS_SHIFT 14u
1404 #define CAN_ESR2_VPS_WIDTH 1u
1405 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
1406 #define CAN_ESR2_LPTM_MASK 0x7F0000u
1407 #define CAN_ESR2_LPTM_SHIFT 16u
1408 #define CAN_ESR2_LPTM_WIDTH 7u
1409 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
1410 /* CRCR Bit Fields */
1411 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
1412 #define CAN_CRCR_TXCRC_SHIFT 0u
1413 #define CAN_CRCR_TXCRC_WIDTH 15u
1414 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
1415 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
1416 #define CAN_CRCR_MBCRC_SHIFT 16u
1417 #define CAN_CRCR_MBCRC_WIDTH 7u
1418 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
1419 /* RXFGMASK Bit Fields */
1420 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
1421 #define CAN_RXFGMASK_FGM_SHIFT 0u
1422 #define CAN_RXFGMASK_FGM_WIDTH 32u
1423 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
1424 /* RXFIR Bit Fields */
1425 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
1426 #define CAN_RXFIR_IDHIT_SHIFT 0u
1427 #define CAN_RXFIR_IDHIT_WIDTH 9u
1428 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
1429 /* CBT Bit Fields */
1430 #define CAN_CBT_EPSEG2_MASK 0x1Fu
1431 #define CAN_CBT_EPSEG2_SHIFT 0u
1432 #define CAN_CBT_EPSEG2_WIDTH 5u
1433 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
1434 #define CAN_CBT_EPSEG1_MASK 0x3E0u
1435 #define CAN_CBT_EPSEG1_SHIFT 5u
1436 #define CAN_CBT_EPSEG1_WIDTH 5u
1437 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
1438 #define CAN_CBT_EPROPSEG_MASK 0xFC00u
1439 #define CAN_CBT_EPROPSEG_SHIFT 10u
1440 #define CAN_CBT_EPROPSEG_WIDTH 6u
1441 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
1442 #define CAN_CBT_ERJW_MASK 0x1F0000u
1443 #define CAN_CBT_ERJW_SHIFT 16u
1444 #define CAN_CBT_ERJW_WIDTH 5u
1445 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
1446 #define CAN_CBT_EPRESDIV_MASK 0x7FE00000u
1447 #define CAN_CBT_EPRESDIV_SHIFT 21u
1448 #define CAN_CBT_EPRESDIV_WIDTH 10u
1449 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
1450 #define CAN_CBT_BTF_MASK 0x80000000u
1451 #define CAN_CBT_BTF_SHIFT 31u
1452 #define CAN_CBT_BTF_WIDTH 1u
1453 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
1454 /* RAMn Bit Fields */
1455 #define CAN_RAMn_DATA_BYTE_3_MASK 0xFFu
1456 #define CAN_RAMn_DATA_BYTE_3_SHIFT 0u
1457 #define CAN_RAMn_DATA_BYTE_3_WIDTH 8u
1458 #define CAN_RAMn_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_3_SHIFT))&CAN_RAMn_DATA_BYTE_3_MASK)
1459 #define CAN_RAMn_DATA_BYTE_2_MASK 0xFF00u
1460 #define CAN_RAMn_DATA_BYTE_2_SHIFT 8u
1461 #define CAN_RAMn_DATA_BYTE_2_WIDTH 8u
1462 #define CAN_RAMn_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_2_SHIFT))&CAN_RAMn_DATA_BYTE_2_MASK)
1463 #define CAN_RAMn_DATA_BYTE_1_MASK 0xFF0000u
1464 #define CAN_RAMn_DATA_BYTE_1_SHIFT 16u
1465 #define CAN_RAMn_DATA_BYTE_1_WIDTH 8u
1466 #define CAN_RAMn_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_1_SHIFT))&CAN_RAMn_DATA_BYTE_1_MASK)
1467 #define CAN_RAMn_DATA_BYTE_0_MASK 0xFF000000u
1468 #define CAN_RAMn_DATA_BYTE_0_SHIFT 24u
1469 #define CAN_RAMn_DATA_BYTE_0_WIDTH 8u
1470 #define CAN_RAMn_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_0_SHIFT))&CAN_RAMn_DATA_BYTE_0_MASK)
1471 /* RXIMR Bit Fields */
1472 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
1473 #define CAN_RXIMR_MI_SHIFT 0u
1474 #define CAN_RXIMR_MI_WIDTH 32u
1475 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
1476 /* CTRL1_PN Bit Fields */
1477 #define CAN_CTRL1_PN_FCS_MASK 0x3u
1478 #define CAN_CTRL1_PN_FCS_SHIFT 0u
1479 #define CAN_CTRL1_PN_FCS_WIDTH 2u
1480 #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_FCS_SHIFT))&CAN_CTRL1_PN_FCS_MASK)
1481 #define CAN_CTRL1_PN_IDFS_MASK 0xCu
1482 #define CAN_CTRL1_PN_IDFS_SHIFT 2u
1483 #define CAN_CTRL1_PN_IDFS_WIDTH 2u
1484 #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_IDFS_SHIFT))&CAN_CTRL1_PN_IDFS_MASK)
1485 #define CAN_CTRL1_PN_PLFS_MASK 0x30u
1486 #define CAN_CTRL1_PN_PLFS_SHIFT 4u
1487 #define CAN_CTRL1_PN_PLFS_WIDTH 2u
1488 #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_PLFS_SHIFT))&CAN_CTRL1_PN_PLFS_MASK)
1489 #define CAN_CTRL1_PN_NMATCH_MASK 0xFF00u
1490 #define CAN_CTRL1_PN_NMATCH_SHIFT 8u
1491 #define CAN_CTRL1_PN_NMATCH_WIDTH 8u
1492 #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_NMATCH_SHIFT))&CAN_CTRL1_PN_NMATCH_MASK)
1493 #define CAN_CTRL1_PN_WUMF_MSK_MASK 0x10000u
1494 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT 16u
1495 #define CAN_CTRL1_PN_WUMF_MSK_WIDTH 1u
1496 #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WUMF_MSK_SHIFT))&CAN_CTRL1_PN_WUMF_MSK_MASK)
1497 #define CAN_CTRL1_PN_WTOF_MSK_MASK 0x20000u
1498 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT 17u
1499 #define CAN_CTRL1_PN_WTOF_MSK_WIDTH 1u
1500 #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WTOF_MSK_SHIFT))&CAN_CTRL1_PN_WTOF_MSK_MASK)
1501 /* CTRL2_PN Bit Fields */
1502 #define CAN_CTRL2_PN_MATCHTO_MASK 0xFFFFu
1503 #define CAN_CTRL2_PN_MATCHTO_SHIFT 0u
1504 #define CAN_CTRL2_PN_MATCHTO_WIDTH 16u
1505 #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PN_MATCHTO_SHIFT))&CAN_CTRL2_PN_MATCHTO_MASK)
1506 /* WU_MTC Bit Fields */
1507 #define CAN_WU_MTC_MCOUNTER_MASK 0xFF00u
1508 #define CAN_WU_MTC_MCOUNTER_SHIFT 8u
1509 #define CAN_WU_MTC_MCOUNTER_WIDTH 8u
1510 #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_MCOUNTER_SHIFT))&CAN_WU_MTC_MCOUNTER_MASK)
1511 #define CAN_WU_MTC_WUMF_MASK 0x10000u
1512 #define CAN_WU_MTC_WUMF_SHIFT 16u
1513 #define CAN_WU_MTC_WUMF_WIDTH 1u
1514 #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WUMF_SHIFT))&CAN_WU_MTC_WUMF_MASK)
1515 #define CAN_WU_MTC_WTOF_MASK 0x20000u
1516 #define CAN_WU_MTC_WTOF_SHIFT 17u
1517 #define CAN_WU_MTC_WTOF_WIDTH 1u
1518 #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WTOF_SHIFT))&CAN_WU_MTC_WTOF_MASK)
1519 /* FLT_ID1 Bit Fields */
1520 #define CAN_FLT_ID1_FLT_ID1_MASK 0x1FFFFFFFu
1521 #define CAN_FLT_ID1_FLT_ID1_SHIFT 0u
1522 #define CAN_FLT_ID1_FLT_ID1_WIDTH 29u
1523 #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_ID1_SHIFT))&CAN_FLT_ID1_FLT_ID1_MASK)
1524 #define CAN_FLT_ID1_FLT_RTR_MASK 0x20000000u
1525 #define CAN_FLT_ID1_FLT_RTR_SHIFT 29u
1526 #define CAN_FLT_ID1_FLT_RTR_WIDTH 1u
1527 #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_RTR_SHIFT))&CAN_FLT_ID1_FLT_RTR_MASK)
1528 #define CAN_FLT_ID1_FLT_IDE_MASK 0x40000000u
1529 #define CAN_FLT_ID1_FLT_IDE_SHIFT 30u
1530 #define CAN_FLT_ID1_FLT_IDE_WIDTH 1u
1531 #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_IDE_SHIFT))&CAN_FLT_ID1_FLT_IDE_MASK)
1532 /* FLT_DLC Bit Fields */
1533 #define CAN_FLT_DLC_FLT_DLC_HI_MASK 0xFu
1534 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT 0u
1535 #define CAN_FLT_DLC_FLT_DLC_HI_WIDTH 4u
1536 #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_HI_SHIFT))&CAN_FLT_DLC_FLT_DLC_HI_MASK)
1537 #define CAN_FLT_DLC_FLT_DLC_LO_MASK 0xF0000u
1538 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT 16u
1539 #define CAN_FLT_DLC_FLT_DLC_LO_WIDTH 4u
1540 #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_LO_SHIFT))&CAN_FLT_DLC_FLT_DLC_LO_MASK)
1541 /* PL1_LO Bit Fields */
1542 #define CAN_PL1_LO_Data_byte_3_MASK 0xFFu
1543 #define CAN_PL1_LO_Data_byte_3_SHIFT 0u
1544 #define CAN_PL1_LO_Data_byte_3_WIDTH 8u
1545 #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_3_SHIFT))&CAN_PL1_LO_Data_byte_3_MASK)
1546 #define CAN_PL1_LO_Data_byte_2_MASK 0xFF00u
1547 #define CAN_PL1_LO_Data_byte_2_SHIFT 8u
1548 #define CAN_PL1_LO_Data_byte_2_WIDTH 8u
1549 #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_2_SHIFT))&CAN_PL1_LO_Data_byte_2_MASK)
1550 #define CAN_PL1_LO_Data_byte_1_MASK 0xFF0000u
1551 #define CAN_PL1_LO_Data_byte_1_SHIFT 16u
1552 #define CAN_PL1_LO_Data_byte_1_WIDTH 8u
1553 #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_1_SHIFT))&CAN_PL1_LO_Data_byte_1_MASK)
1554 #define CAN_PL1_LO_Data_byte_0_MASK 0xFF000000u
1555 #define CAN_PL1_LO_Data_byte_0_SHIFT 24u
1556 #define CAN_PL1_LO_Data_byte_0_WIDTH 8u
1557 #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_0_SHIFT))&CAN_PL1_LO_Data_byte_0_MASK)
1558 /* PL1_HI Bit Fields */
1559 #define CAN_PL1_HI_Data_byte_7_MASK 0xFFu
1560 #define CAN_PL1_HI_Data_byte_7_SHIFT 0u
1561 #define CAN_PL1_HI_Data_byte_7_WIDTH 8u
1562 #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_7_SHIFT))&CAN_PL1_HI_Data_byte_7_MASK)
1563 #define CAN_PL1_HI_Data_byte_6_MASK 0xFF00u
1564 #define CAN_PL1_HI_Data_byte_6_SHIFT 8u
1565 #define CAN_PL1_HI_Data_byte_6_WIDTH 8u
1566 #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_6_SHIFT))&CAN_PL1_HI_Data_byte_6_MASK)
1567 #define CAN_PL1_HI_Data_byte_5_MASK 0xFF0000u
1568 #define CAN_PL1_HI_Data_byte_5_SHIFT 16u
1569 #define CAN_PL1_HI_Data_byte_5_WIDTH 8u
1570 #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_5_SHIFT))&CAN_PL1_HI_Data_byte_5_MASK)
1571 #define CAN_PL1_HI_Data_byte_4_MASK 0xFF000000u
1572 #define CAN_PL1_HI_Data_byte_4_SHIFT 24u
1573 #define CAN_PL1_HI_Data_byte_4_WIDTH 8u
1574 #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_4_SHIFT))&CAN_PL1_HI_Data_byte_4_MASK)
1575 /* FLT_ID2_IDMASK Bit Fields */
1576 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK 0x1FFFFFFFu
1577 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT 0u
1578 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH 29u
1579 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT))&CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
1580 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK 0x20000000u
1581 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT 29u
1582 #define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH 1u
1583 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
1584 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK 0x40000000u
1585 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT 30u
1586 #define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH 1u
1587 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
1588 /* PL2_PLMASK_LO Bit Fields */
1589 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK 0xFFu
1590 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT 0u
1591 #define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH 8u
1592 #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
1593 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK 0xFF00u
1594 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT 8u
1595 #define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH 8u
1596 #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
1597 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK 0xFF0000u
1598 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT 16u
1599 #define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH 8u
1600 #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
1601 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK 0xFF000000u
1602 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT 24u
1603 #define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH 8u
1604 #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
1605 /* PL2_PLMASK_HI Bit Fields */
1606 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK 0xFFu
1607 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT 0u
1608 #define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH 8u
1609 #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
1610 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK 0xFF00u
1611 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT 8u
1612 #define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH 8u
1613 #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
1614 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK 0xFF0000u
1615 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT 16u
1616 #define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH 8u
1617 #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
1618 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK 0xFF000000u
1619 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT 24u
1620 #define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH 8u
1621 #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
1622 /* WMBn_CS Bit Fields */
1623 #define CAN_WMBn_CS_DLC_MASK 0xF0000u
1624 #define CAN_WMBn_CS_DLC_SHIFT 16u
1625 #define CAN_WMBn_CS_DLC_WIDTH 4u
1626 #define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_DLC_SHIFT))&CAN_WMBn_CS_DLC_MASK)
1627 #define CAN_WMBn_CS_RTR_MASK 0x100000u
1628 #define CAN_WMBn_CS_RTR_SHIFT 20u
1629 #define CAN_WMBn_CS_RTR_WIDTH 1u
1630 #define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_RTR_SHIFT))&CAN_WMBn_CS_RTR_MASK)
1631 #define CAN_WMBn_CS_IDE_MASK 0x200000u
1632 #define CAN_WMBn_CS_IDE_SHIFT 21u
1633 #define CAN_WMBn_CS_IDE_WIDTH 1u
1634 #define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_IDE_SHIFT))&CAN_WMBn_CS_IDE_MASK)
1635 #define CAN_WMBn_CS_SRR_MASK 0x400000u
1636 #define CAN_WMBn_CS_SRR_SHIFT 22u
1637 #define CAN_WMBn_CS_SRR_WIDTH 1u
1638 #define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_SRR_SHIFT))&CAN_WMBn_CS_SRR_MASK)
1639 /* WMBn_ID Bit Fields */
1640 #define CAN_WMBn_ID_ID_MASK 0x1FFFFFFFu
1641 #define CAN_WMBn_ID_ID_SHIFT 0u
1642 #define CAN_WMBn_ID_ID_WIDTH 29u
1643 #define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_ID_ID_SHIFT))&CAN_WMBn_ID_ID_MASK)
1644 /* WMBn_D03 Bit Fields */
1645 #define CAN_WMBn_D03_Data_byte_3_MASK 0xFFu
1646 #define CAN_WMBn_D03_Data_byte_3_SHIFT 0u
1647 #define CAN_WMBn_D03_Data_byte_3_WIDTH 8u
1648 #define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_3_SHIFT))&CAN_WMBn_D03_Data_byte_3_MASK)
1649 #define CAN_WMBn_D03_Data_byte_2_MASK 0xFF00u
1650 #define CAN_WMBn_D03_Data_byte_2_SHIFT 8u
1651 #define CAN_WMBn_D03_Data_byte_2_WIDTH 8u
1652 #define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_2_SHIFT))&CAN_WMBn_D03_Data_byte_2_MASK)
1653 #define CAN_WMBn_D03_Data_byte_1_MASK 0xFF0000u
1654 #define CAN_WMBn_D03_Data_byte_1_SHIFT 16u
1655 #define CAN_WMBn_D03_Data_byte_1_WIDTH 8u
1656 #define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_1_SHIFT))&CAN_WMBn_D03_Data_byte_1_MASK)
1657 #define CAN_WMBn_D03_Data_byte_0_MASK 0xFF000000u
1658 #define CAN_WMBn_D03_Data_byte_0_SHIFT 24u
1659 #define CAN_WMBn_D03_Data_byte_0_WIDTH 8u
1660 #define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_0_SHIFT))&CAN_WMBn_D03_Data_byte_0_MASK)
1661 /* WMBn_D47 Bit Fields */
1662 #define CAN_WMBn_D47_Data_byte_7_MASK 0xFFu
1663 #define CAN_WMBn_D47_Data_byte_7_SHIFT 0u
1664 #define CAN_WMBn_D47_Data_byte_7_WIDTH 8u
1665 #define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_7_SHIFT))&CAN_WMBn_D47_Data_byte_7_MASK)
1666 #define CAN_WMBn_D47_Data_byte_6_MASK 0xFF00u
1667 #define CAN_WMBn_D47_Data_byte_6_SHIFT 8u
1668 #define CAN_WMBn_D47_Data_byte_6_WIDTH 8u
1669 #define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_6_SHIFT))&CAN_WMBn_D47_Data_byte_6_MASK)
1670 #define CAN_WMBn_D47_Data_byte_5_MASK 0xFF0000u
1671 #define CAN_WMBn_D47_Data_byte_5_SHIFT 16u
1672 #define CAN_WMBn_D47_Data_byte_5_WIDTH 8u
1673 #define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_5_SHIFT))&CAN_WMBn_D47_Data_byte_5_MASK)
1674 #define CAN_WMBn_D47_Data_byte_4_MASK 0xFF000000u
1675 #define CAN_WMBn_D47_Data_byte_4_SHIFT 24u
1676 #define CAN_WMBn_D47_Data_byte_4_WIDTH 8u
1677 #define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_4_SHIFT))&CAN_WMBn_D47_Data_byte_4_MASK)
1678 /* FDCTRL Bit Fields */
1679 #define CAN_FDCTRL_TDCVAL_MASK 0x3Fu
1680 #define CAN_FDCTRL_TDCVAL_SHIFT 0u
1681 #define CAN_FDCTRL_TDCVAL_WIDTH 6u
1682 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCVAL_SHIFT))&CAN_FDCTRL_TDCVAL_MASK)
1683 #define CAN_FDCTRL_TDCOFF_MASK 0x1F00u
1684 #define CAN_FDCTRL_TDCOFF_SHIFT 8u
1685 #define CAN_FDCTRL_TDCOFF_WIDTH 5u
1686 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCOFF_SHIFT))&CAN_FDCTRL_TDCOFF_MASK)
1687 #define CAN_FDCTRL_TDCFAIL_MASK 0x4000u
1688 #define CAN_FDCTRL_TDCFAIL_SHIFT 14u
1689 #define CAN_FDCTRL_TDCFAIL_WIDTH 1u
1690 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCFAIL_SHIFT))&CAN_FDCTRL_TDCFAIL_MASK)
1691 #define CAN_FDCTRL_TDCEN_MASK 0x8000u
1692 #define CAN_FDCTRL_TDCEN_SHIFT 15u
1693 #define CAN_FDCTRL_TDCEN_WIDTH 1u
1694 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCEN_SHIFT))&CAN_FDCTRL_TDCEN_MASK)
1695 #define CAN_FDCTRL_MBDSR0_MASK 0x30000u
1696 #define CAN_FDCTRL_MBDSR0_SHIFT 16u
1697 #define CAN_FDCTRL_MBDSR0_WIDTH 2u
1698 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_MBDSR0_SHIFT))&CAN_FDCTRL_MBDSR0_MASK)
1699 #define CAN_FDCTRL_FDRATE_MASK 0x80000000u
1700 #define CAN_FDCTRL_FDRATE_SHIFT 31u
1701 #define CAN_FDCTRL_FDRATE_WIDTH 1u
1702 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_FDRATE_SHIFT))&CAN_FDCTRL_FDRATE_MASK)
1703 /* FDCBT Bit Fields */
1704 #define CAN_FDCBT_FPSEG2_MASK 0x7u
1705 #define CAN_FDCBT_FPSEG2_SHIFT 0u
1706 #define CAN_FDCBT_FPSEG2_WIDTH 3u
1707 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG2_SHIFT))&CAN_FDCBT_FPSEG2_MASK)
1708 #define CAN_FDCBT_FPSEG1_MASK 0xE0u
1709 #define CAN_FDCBT_FPSEG1_SHIFT 5u
1710 #define CAN_FDCBT_FPSEG1_WIDTH 3u
1711 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG1_SHIFT))&CAN_FDCBT_FPSEG1_MASK)
1712 #define CAN_FDCBT_FPROPSEG_MASK 0x7C00u
1713 #define CAN_FDCBT_FPROPSEG_SHIFT 10u
1714 #define CAN_FDCBT_FPROPSEG_WIDTH 5u
1715 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPROPSEG_SHIFT))&CAN_FDCBT_FPROPSEG_MASK)
1716 #define CAN_FDCBT_FRJW_MASK 0x70000u
1717 #define CAN_FDCBT_FRJW_SHIFT 16u
1718 #define CAN_FDCBT_FRJW_WIDTH 3u
1719 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FRJW_SHIFT))&CAN_FDCBT_FRJW_MASK)
1720 #define CAN_FDCBT_FPRESDIV_MASK 0x3FF00000u
1721 #define CAN_FDCBT_FPRESDIV_SHIFT 20u
1722 #define CAN_FDCBT_FPRESDIV_WIDTH 10u
1723 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPRESDIV_SHIFT))&CAN_FDCBT_FPRESDIV_MASK)
1724 /* FDCRC Bit Fields */
1725 #define CAN_FDCRC_FD_TXCRC_MASK 0x1FFFFFu
1726 #define CAN_FDCRC_FD_TXCRC_SHIFT 0u
1727 #define CAN_FDCRC_FD_TXCRC_WIDTH 21u
1728 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_TXCRC_SHIFT))&CAN_FDCRC_FD_TXCRC_MASK)
1729 #define CAN_FDCRC_FD_MBCRC_MASK 0x7F000000u
1730 #define CAN_FDCRC_FD_MBCRC_SHIFT 24u
1731 #define CAN_FDCRC_FD_MBCRC_WIDTH 7u
1732 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_MBCRC_SHIFT))&CAN_FDCRC_FD_MBCRC_MASK)
1733  /* end of group CAN_Register_Masks */
1737 
1738  /* end of group CAN_Peripheral_Access_Layer */
1742 
1743 
1744 /* ----------------------------------------------------------------------------
1745  -- CMP Peripheral Access Layer
1746  ---------------------------------------------------------------------------- */
1747 
1757 typedef struct {
1758  __IO uint32_t C0;
1759  __IO uint32_t C1;
1760  __IO uint32_t C2;
1762 
1764 #define CMP_INSTANCE_COUNT (1u)
1765 
1766 
1767 /* CMP - Peripheral instance base addresses */
1769 #define CMP0_BASE (0x40073000u)
1770 
1771 #define CMP0 ((CMP_Type *)CMP0_BASE)
1772 
1773 #define CMP_BASE_ADDRS { CMP0_BASE }
1774 
1775 #define CMP_BASE_PTRS { CMP0 }
1776 
1777 #define CMP_IRQS_ARR_COUNT (1u)
1778 
1779 #define CMP_IRQS_CH_COUNT (1u)
1780 
1781 #define CMP_IRQS { CMP0_IRQn }
1782 
1783 /* ----------------------------------------------------------------------------
1784  -- CMP Register Masks
1785  ---------------------------------------------------------------------------- */
1786 
1792 /* C0 Bit Fields */
1793 #define CMP_C0_HYSTCTR_MASK 0x3u
1794 #define CMP_C0_HYSTCTR_SHIFT 0u
1795 #define CMP_C0_HYSTCTR_WIDTH 2u
1796 #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_HYSTCTR_SHIFT))&CMP_C0_HYSTCTR_MASK)
1797 #define CMP_C0_OFFSET_MASK 0x4u
1798 #define CMP_C0_OFFSET_SHIFT 2u
1799 #define CMP_C0_OFFSET_WIDTH 1u
1800 #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OFFSET_SHIFT))&CMP_C0_OFFSET_MASK)
1801 #define CMP_C0_FILTER_CNT_MASK 0x70u
1802 #define CMP_C0_FILTER_CNT_SHIFT 4u
1803 #define CMP_C0_FILTER_CNT_WIDTH 3u
1804 #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FILTER_CNT_SHIFT))&CMP_C0_FILTER_CNT_MASK)
1805 #define CMP_C0_EN_MASK 0x100u
1806 #define CMP_C0_EN_SHIFT 8u
1807 #define CMP_C0_EN_WIDTH 1u
1808 #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_EN_SHIFT))&CMP_C0_EN_MASK)
1809 #define CMP_C0_OPE_MASK 0x200u
1810 #define CMP_C0_OPE_SHIFT 9u
1811 #define CMP_C0_OPE_WIDTH 1u
1812 #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OPE_SHIFT))&CMP_C0_OPE_MASK)
1813 #define CMP_C0_COS_MASK 0x400u
1814 #define CMP_C0_COS_SHIFT 10u
1815 #define CMP_C0_COS_WIDTH 1u
1816 #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COS_SHIFT))&CMP_C0_COS_MASK)
1817 #define CMP_C0_INVT_MASK 0x800u
1818 #define CMP_C0_INVT_SHIFT 11u
1819 #define CMP_C0_INVT_WIDTH 1u
1820 #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_INVT_SHIFT))&CMP_C0_INVT_MASK)
1821 #define CMP_C0_PMODE_MASK 0x1000u
1822 #define CMP_C0_PMODE_SHIFT 12u
1823 #define CMP_C0_PMODE_WIDTH 1u
1824 #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_PMODE_SHIFT))&CMP_C0_PMODE_MASK)
1825 #define CMP_C0_WE_MASK 0x4000u
1826 #define CMP_C0_WE_SHIFT 14u
1827 #define CMP_C0_WE_WIDTH 1u
1828 #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_WE_SHIFT))&CMP_C0_WE_MASK)
1829 #define CMP_C0_SE_MASK 0x8000u
1830 #define CMP_C0_SE_SHIFT 15u
1831 #define CMP_C0_SE_WIDTH 1u
1832 #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_SE_SHIFT))&CMP_C0_SE_MASK)
1833 #define CMP_C0_FPR_MASK 0xFF0000u
1834 #define CMP_C0_FPR_SHIFT 16u
1835 #define CMP_C0_FPR_WIDTH 8u
1836 #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FPR_SHIFT))&CMP_C0_FPR_MASK)
1837 #define CMP_C0_COUT_MASK 0x1000000u
1838 #define CMP_C0_COUT_SHIFT 24u
1839 #define CMP_C0_COUT_WIDTH 1u
1840 #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COUT_SHIFT))&CMP_C0_COUT_MASK)
1841 #define CMP_C0_CFF_MASK 0x2000000u
1842 #define CMP_C0_CFF_SHIFT 25u
1843 #define CMP_C0_CFF_WIDTH 1u
1844 #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFF_SHIFT))&CMP_C0_CFF_MASK)
1845 #define CMP_C0_CFR_MASK 0x4000000u
1846 #define CMP_C0_CFR_SHIFT 26u
1847 #define CMP_C0_CFR_WIDTH 1u
1848 #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFR_SHIFT))&CMP_C0_CFR_MASK)
1849 #define CMP_C0_IEF_MASK 0x8000000u
1850 #define CMP_C0_IEF_SHIFT 27u
1851 #define CMP_C0_IEF_WIDTH 1u
1852 #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IEF_SHIFT))&CMP_C0_IEF_MASK)
1853 #define CMP_C0_IER_MASK 0x10000000u
1854 #define CMP_C0_IER_SHIFT 28u
1855 #define CMP_C0_IER_WIDTH 1u
1856 #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IER_SHIFT))&CMP_C0_IER_MASK)
1857 #define CMP_C0_DMAEN_MASK 0x40000000u
1858 #define CMP_C0_DMAEN_SHIFT 30u
1859 #define CMP_C0_DMAEN_WIDTH 1u
1860 #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_DMAEN_SHIFT))&CMP_C0_DMAEN_MASK)
1861 /* C1 Bit Fields */
1862 #define CMP_C1_VOSEL_MASK 0xFFu
1863 #define CMP_C1_VOSEL_SHIFT 0u
1864 #define CMP_C1_VOSEL_WIDTH 8u
1865 #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VOSEL_SHIFT))&CMP_C1_VOSEL_MASK)
1866 #define CMP_C1_MSEL_MASK 0x700u
1867 #define CMP_C1_MSEL_SHIFT 8u
1868 #define CMP_C1_MSEL_WIDTH 3u
1869 #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_MSEL_SHIFT))&CMP_C1_MSEL_MASK)
1870 #define CMP_C1_PSEL_MASK 0x3800u
1871 #define CMP_C1_PSEL_SHIFT 11u
1872 #define CMP_C1_PSEL_WIDTH 3u
1873 #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_PSEL_SHIFT))&CMP_C1_PSEL_MASK)
1874 #define CMP_C1_VRSEL_MASK 0x4000u
1875 #define CMP_C1_VRSEL_SHIFT 14u
1876 #define CMP_C1_VRSEL_WIDTH 1u
1877 #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VRSEL_SHIFT))&CMP_C1_VRSEL_MASK)
1878 #define CMP_C1_DACEN_MASK 0x8000u
1879 #define CMP_C1_DACEN_SHIFT 15u
1880 #define CMP_C1_DACEN_WIDTH 1u
1881 #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_DACEN_SHIFT))&CMP_C1_DACEN_MASK)
1882 #define CMP_C1_CHN0_MASK 0x10000u
1883 #define CMP_C1_CHN0_SHIFT 16u
1884 #define CMP_C1_CHN0_WIDTH 1u
1885 #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN0_SHIFT))&CMP_C1_CHN0_MASK)
1886 #define CMP_C1_CHN1_MASK 0x20000u
1887 #define CMP_C1_CHN1_SHIFT 17u
1888 #define CMP_C1_CHN1_WIDTH 1u
1889 #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN1_SHIFT))&CMP_C1_CHN1_MASK)
1890 #define CMP_C1_CHN2_MASK 0x40000u
1891 #define CMP_C1_CHN2_SHIFT 18u
1892 #define CMP_C1_CHN2_WIDTH 1u
1893 #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN2_SHIFT))&CMP_C1_CHN2_MASK)
1894 #define CMP_C1_CHN3_MASK 0x80000u
1895 #define CMP_C1_CHN3_SHIFT 19u
1896 #define CMP_C1_CHN3_WIDTH 1u
1897 #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN3_SHIFT))&CMP_C1_CHN3_MASK)
1898 #define CMP_C1_CHN4_MASK 0x100000u
1899 #define CMP_C1_CHN4_SHIFT 20u
1900 #define CMP_C1_CHN4_WIDTH 1u
1901 #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN4_SHIFT))&CMP_C1_CHN4_MASK)
1902 #define CMP_C1_CHN5_MASK 0x200000u
1903 #define CMP_C1_CHN5_SHIFT 21u
1904 #define CMP_C1_CHN5_WIDTH 1u
1905 #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN5_SHIFT))&CMP_C1_CHN5_MASK)
1906 #define CMP_C1_CHN6_MASK 0x400000u
1907 #define CMP_C1_CHN6_SHIFT 22u
1908 #define CMP_C1_CHN6_WIDTH 1u
1909 #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN6_SHIFT))&CMP_C1_CHN6_MASK)
1910 #define CMP_C1_CHN7_MASK 0x800000u
1911 #define CMP_C1_CHN7_SHIFT 23u
1912 #define CMP_C1_CHN7_WIDTH 1u
1913 #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN7_SHIFT))&CMP_C1_CHN7_MASK)
1914 #define CMP_C1_INNSEL_MASK 0x3000000u
1915 #define CMP_C1_INNSEL_SHIFT 24u
1916 #define CMP_C1_INNSEL_WIDTH 2u
1917 #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INNSEL_SHIFT))&CMP_C1_INNSEL_MASK)
1918 #define CMP_C1_INPSEL_MASK 0x18000000u
1919 #define CMP_C1_INPSEL_SHIFT 27u
1920 #define CMP_C1_INPSEL_WIDTH 2u
1921 #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INPSEL_SHIFT))&CMP_C1_INPSEL_MASK)
1922 /* C2 Bit Fields */
1923 #define CMP_C2_ACOn_MASK 0xFFu
1924 #define CMP_C2_ACOn_SHIFT 0u
1925 #define CMP_C2_ACOn_WIDTH 8u
1926 #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_ACOn_SHIFT))&CMP_C2_ACOn_MASK)
1927 #define CMP_C2_INITMOD_MASK 0x3F00u
1928 #define CMP_C2_INITMOD_SHIFT 8u
1929 #define CMP_C2_INITMOD_WIDTH 6u
1930 #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_INITMOD_SHIFT))&CMP_C2_INITMOD_MASK)
1931 #define CMP_C2_NSAM_MASK 0xC000u
1932 #define CMP_C2_NSAM_SHIFT 14u
1933 #define CMP_C2_NSAM_WIDTH 2u
1934 #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_NSAM_SHIFT))&CMP_C2_NSAM_MASK)
1935 #define CMP_C2_CH0F_MASK 0x10000u
1936 #define CMP_C2_CH0F_SHIFT 16u
1937 #define CMP_C2_CH0F_WIDTH 1u
1938 #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH0F_SHIFT))&CMP_C2_CH0F_MASK)
1939 #define CMP_C2_CH1F_MASK 0x20000u
1940 #define CMP_C2_CH1F_SHIFT 17u
1941 #define CMP_C2_CH1F_WIDTH 1u
1942 #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH1F_SHIFT))&CMP_C2_CH1F_MASK)
1943 #define CMP_C2_CH2F_MASK 0x40000u
1944 #define CMP_C2_CH2F_SHIFT 18u
1945 #define CMP_C2_CH2F_WIDTH 1u
1946 #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH2F_SHIFT))&CMP_C2_CH2F_MASK)
1947 #define CMP_C2_CH3F_MASK 0x80000u
1948 #define CMP_C2_CH3F_SHIFT 19u
1949 #define CMP_C2_CH3F_WIDTH 1u
1950 #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH3F_SHIFT))&CMP_C2_CH3F_MASK)
1951 #define CMP_C2_CH4F_MASK 0x100000u
1952 #define CMP_C2_CH4F_SHIFT 20u
1953 #define CMP_C2_CH4F_WIDTH 1u
1954 #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH4F_SHIFT))&CMP_C2_CH4F_MASK)
1955 #define CMP_C2_CH5F_MASK 0x200000u
1956 #define CMP_C2_CH5F_SHIFT 21u
1957 #define CMP_C2_CH5F_WIDTH 1u
1958 #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH5F_SHIFT))&CMP_C2_CH5F_MASK)
1959 #define CMP_C2_CH6F_MASK 0x400000u
1960 #define CMP_C2_CH6F_SHIFT 22u
1961 #define CMP_C2_CH6F_WIDTH 1u
1962 #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH6F_SHIFT))&CMP_C2_CH6F_MASK)
1963 #define CMP_C2_CH7F_MASK 0x800000u
1964 #define CMP_C2_CH7F_SHIFT 23u
1965 #define CMP_C2_CH7F_WIDTH 1u
1966 #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH7F_SHIFT))&CMP_C2_CH7F_MASK)
1967 #define CMP_C2_FXMXCH_MASK 0xE000000u
1968 #define CMP_C2_FXMXCH_SHIFT 25u
1969 #define CMP_C2_FXMXCH_WIDTH 3u
1970 #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMXCH_SHIFT))&CMP_C2_FXMXCH_MASK)
1971 #define CMP_C2_FXMP_MASK 0x20000000u
1972 #define CMP_C2_FXMP_SHIFT 29u
1973 #define CMP_C2_FXMP_WIDTH 1u
1974 #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMP_SHIFT))&CMP_C2_FXMP_MASK)
1975 #define CMP_C2_RRIE_MASK 0x40000000u
1976 #define CMP_C2_RRIE_SHIFT 30u
1977 #define CMP_C2_RRIE_WIDTH 1u
1978 #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRIE_SHIFT))&CMP_C2_RRIE_MASK)
1979 #define CMP_C2_RRE_MASK 0x80000000u
1980 #define CMP_C2_RRE_SHIFT 31u
1981 #define CMP_C2_RRE_WIDTH 1u
1982 #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRE_SHIFT))&CMP_C2_RRE_MASK)
1983  /* end of group CMP_Register_Masks */
1987 
1988  /* end of group CMP_Peripheral_Access_Layer */
1992 
1993 
1994 /* ----------------------------------------------------------------------------
1995  -- CRC Peripheral Access Layer
1996  ---------------------------------------------------------------------------- */
1997 
2007 typedef struct {
2008  union { /* offset: 0x0 */
2009  __IO uint32_t DATA;
2010  struct { /* offset: 0x0 */
2011  __IO uint16_t L;
2012  __IO uint16_t H;
2013  } DATA_16;
2014  struct { /* offset: 0x0 */
2015  __IO uint8_t LL;
2016  __IO uint8_t LU;
2017  __IO uint8_t HL;
2018  __IO uint8_t HU;
2019  } DATA_8;
2020  } DATAu;
2021  __IO uint32_t GPOLY;
2022  __IO uint32_t CTRL;
2024 
2026 #define CRC_INSTANCE_COUNT (1u)
2027 
2028 
2029 /* CRC - Peripheral instance base addresses */
2031 #define CRC_BASE (0x40032000u)
2032 
2033 #define CRC ((CRC_Type *)CRC_BASE)
2034 
2035 #define CRC_BASE_ADDRS { CRC_BASE }
2036 
2037 #define CRC_BASE_PTRS { CRC }
2038 
2039 /* ----------------------------------------------------------------------------
2040  -- CRC Register Masks
2041  ---------------------------------------------------------------------------- */
2042 
2048 /* DATAu_DATA Bit Fields */
2049 #define CRC_DATAu_DATA_LL_MASK 0xFFu
2050 #define CRC_DATAu_DATA_LL_SHIFT 0u
2051 #define CRC_DATAu_DATA_LL_WIDTH 8u
2052 #define CRC_DATAu_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LL_SHIFT))&CRC_DATAu_DATA_LL_MASK)
2053 #define CRC_DATAu_DATA_LU_MASK 0xFF00u
2054 #define CRC_DATAu_DATA_LU_SHIFT 8u
2055 #define CRC_DATAu_DATA_LU_WIDTH 8u
2056 #define CRC_DATAu_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LU_SHIFT))&CRC_DATAu_DATA_LU_MASK)
2057 #define CRC_DATAu_DATA_HL_MASK 0xFF0000u
2058 #define CRC_DATAu_DATA_HL_SHIFT 16u
2059 #define CRC_DATAu_DATA_HL_WIDTH 8u
2060 #define CRC_DATAu_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HL_SHIFT))&CRC_DATAu_DATA_HL_MASK)
2061 #define CRC_DATAu_DATA_HU_MASK 0xFF000000u
2062 #define CRC_DATAu_DATA_HU_SHIFT 24u
2063 #define CRC_DATAu_DATA_HU_WIDTH 8u
2064 #define CRC_DATAu_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HU_SHIFT))&CRC_DATAu_DATA_HU_MASK)
2065 /* DATAu_DATA_16_L Bit Fields */
2066 #define CRC_DATAu_DATA_16_L_DATAL_MASK 0xFFFFu
2067 #define CRC_DATAu_DATA_16_L_DATAL_SHIFT 0u
2068 #define CRC_DATAu_DATA_16_L_DATAL_WIDTH 16u
2069 #define CRC_DATAu_DATA_16_L_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_L_DATAL_SHIFT))&CRC_DATAu_DATA_16_L_DATAL_MASK)
2070 /* DATAu_DATA_16_H Bit Fields */
2071 #define CRC_DATAu_DATA_16_H_DATAH_MASK 0xFFFFu
2072 #define CRC_DATAu_DATA_16_H_DATAH_SHIFT 0u
2073 #define CRC_DATAu_DATA_16_H_DATAH_WIDTH 16u
2074 #define CRC_DATAu_DATA_16_H_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_H_DATAH_SHIFT))&CRC_DATAu_DATA_16_H_DATAH_MASK)
2075 /* DATAu_DATA_8_LL Bit Fields */
2076 #define CRC_DATAu_DATA_8_LL_DATALL_MASK 0xFFu
2077 #define CRC_DATAu_DATA_8_LL_DATALL_SHIFT 0u
2078 #define CRC_DATAu_DATA_8_LL_DATALL_WIDTH 8u
2079 #define CRC_DATAu_DATA_8_LL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LL_DATALL_SHIFT))&CRC_DATAu_DATA_8_LL_DATALL_MASK)
2080 /* DATAu_DATA_8_LU Bit Fields */
2081 #define CRC_DATAu_DATA_8_LU_DATALU_MASK 0xFFu
2082 #define CRC_DATAu_DATA_8_LU_DATALU_SHIFT 0u
2083 #define CRC_DATAu_DATA_8_LU_DATALU_WIDTH 8u
2084 #define CRC_DATAu_DATA_8_LU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LU_DATALU_SHIFT))&CRC_DATAu_DATA_8_LU_DATALU_MASK)
2085 /* DATAu_DATA_8_HL Bit Fields */
2086 #define CRC_DATAu_DATA_8_HL_DATAHL_MASK 0xFFu
2087 #define CRC_DATAu_DATA_8_HL_DATAHL_SHIFT 0u
2088 #define CRC_DATAu_DATA_8_HL_DATAHL_WIDTH 8u
2089 #define CRC_DATAu_DATA_8_HL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HL_DATAHL_SHIFT))&CRC_DATAu_DATA_8_HL_DATAHL_MASK)
2090 /* DATAu_DATA_8_HU Bit Fields */
2091 #define CRC_DATAu_DATA_8_HU_DATAHU_MASK 0xFFu
2092 #define CRC_DATAu_DATA_8_HU_DATAHU_SHIFT 0u
2093 #define CRC_DATAu_DATA_8_HU_DATAHU_WIDTH 8u
2094 #define CRC_DATAu_DATA_8_HU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HU_DATAHU_SHIFT))&CRC_DATAu_DATA_8_HU_DATAHU_MASK)
2095 /* GPOLY Bit Fields */
2096 #define CRC_GPOLY_LOW_MASK 0xFFFFu
2097 #define CRC_GPOLY_LOW_SHIFT 0u
2098 #define CRC_GPOLY_LOW_WIDTH 16u
2099 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
2100 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
2101 #define CRC_GPOLY_HIGH_SHIFT 16u
2102 #define CRC_GPOLY_HIGH_WIDTH 16u
2103 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
2104 /* CTRL Bit Fields */
2105 #define CRC_CTRL_TCRC_MASK 0x1000000u
2106 #define CRC_CTRL_TCRC_SHIFT 24u
2107 #define CRC_CTRL_TCRC_WIDTH 1u
2108 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
2109 #define CRC_CTRL_WAS_MASK 0x2000000u
2110 #define CRC_CTRL_WAS_SHIFT 25u
2111 #define CRC_CTRL_WAS_WIDTH 1u
2112 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
2113 #define CRC_CTRL_FXOR_MASK 0x4000000u
2114 #define CRC_CTRL_FXOR_SHIFT 26u
2115 #define CRC_CTRL_FXOR_WIDTH 1u
2116 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
2117 #define CRC_CTRL_TOTR_MASK 0x30000000u
2118 #define CRC_CTRL_TOTR_SHIFT 28u
2119 #define CRC_CTRL_TOTR_WIDTH 2u
2120 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
2121 #define CRC_CTRL_TOT_MASK 0xC0000000u
2122 #define CRC_CTRL_TOT_SHIFT 30u
2123 #define CRC_CTRL_TOT_WIDTH 2u
2124 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
2125  /* end of group CRC_Register_Masks */
2129 
2130  /* end of group CRC_Peripheral_Access_Layer */
2134 
2135 
2136 /* ----------------------------------------------------------------------------
2137  -- CSE_PRAM Peripheral Access Layer
2138  ---------------------------------------------------------------------------- */
2139 
2147 #define CSE_PRAM_RAMn_COUNT 32u
2148 
2150 typedef struct {
2151  union { /* offset: 0x0, array step: 0x4 */
2152  __IO uint32_t DATA_32;
2153  struct { /* offset: 0x0, array step: 0x4 */
2154  __IO uint8_t DATA_8LL;
2155  __IO uint8_t DATA_8LU;
2156  __IO uint8_t DATA_8HL;
2157  __IO uint8_t DATA_8HU;
2158  } ACCESS8BIT;
2159  } RAMn[CSE_PRAM_RAMn_COUNT];
2161 
2163 #define CSE_PRAM_INSTANCE_COUNT (1u)
2164 
2165 
2166 /* CSE_PRAM - Peripheral instance base addresses */
2168 #define CSE_PRAM_BASE (0x14001000u)
2169 
2170 #define CSE_PRAM ((CSE_PRAM_Type *)CSE_PRAM_BASE)
2171 
2172 #define CSE_PRAM_BASE_ADDRS { CSE_PRAM_BASE }
2173 
2174 #define CSE_PRAM_BASE_PTRS { CSE_PRAM }
2175 
2176 /* ----------------------------------------------------------------------------
2177  -- CSE_PRAM Register Masks
2178  ---------------------------------------------------------------------------- */
2179 
2185 /* RAMn_DATA_32 Bit Fields */
2186 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK 0xFFu
2187 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT 0u
2188 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_WIDTH 8u
2189 #define CSE_PRAM_RAMn_DATA_32_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK)
2190 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK 0xFF00u
2191 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT 8u
2192 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_WIDTH 8u
2193 #define CSE_PRAM_RAMn_DATA_32_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK)
2194 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK 0xFF0000u
2195 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT 16u
2196 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_WIDTH 8u
2197 #define CSE_PRAM_RAMn_DATA_32_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK)
2198 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK 0xFF000000u
2199 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT 24u
2200 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_WIDTH 8u
2201 #define CSE_PRAM_RAMn_DATA_32_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK)
2202 /* RAMn_ACCESS8BIT_DATA_8LL Bit Fields */
2203 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK 0xFFu
2204 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT 0u
2205 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_WIDTH 8u
2206 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK)
2207 /* RAMn_ACCESS8BIT_DATA_8LU Bit Fields */
2208 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK 0xFFu
2209 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT 0u
2210 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_WIDTH 8u
2211 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK)
2212 /* RAMn_ACCESS8BIT_DATA_8HL Bit Fields */
2213 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK 0xFFu
2214 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT 0u
2215 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_WIDTH 8u
2216 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK)
2217 /* RAMn_ACCESS8BIT_DATA_8HU Bit Fields */
2218 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK 0xFFu
2219 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT 0u
2220 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_WIDTH 8u
2221 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK)
2222  /* end of group CSE_PRAM_Register_Masks */
2226 
2227  /* end of group CSE_PRAM_Peripheral_Access_Layer */
2231 
2232 
2233 /* ----------------------------------------------------------------------------
2234  -- DMA Peripheral Access Layer
2235  ---------------------------------------------------------------------------- */
2236 
2244 #define DMA_DCHPRI_COUNT 16u
2245 #define DMA_TCD_COUNT 16u
2246 
2248 typedef struct {
2249  __IO uint32_t CR;
2250  __I uint32_t ES;
2251  uint8_t RESERVED_0[4];
2252  __IO uint32_t ERQ;
2253  uint8_t RESERVED_1[4];
2254  __IO uint32_t EEI;
2255  __O uint8_t CEEI;
2256  __O uint8_t SEEI;
2257  __O uint8_t CERQ;
2258  __O uint8_t SERQ;
2259  __O uint8_t CDNE;
2260  __O uint8_t SSRT;
2261  __O uint8_t CERR;
2262  __O uint8_t CINT;
2263  uint8_t RESERVED_2[4];
2264  __IO uint32_t INT;
2265  uint8_t RESERVED_3[4];
2266  __IO uint32_t ERR;
2267  uint8_t RESERVED_4[4];
2268  __I uint32_t HRS;
2269  uint8_t RESERVED_5[12];
2270  __IO uint32_t EARS;
2271  uint8_t RESERVED_6[184];
2272  __IO uint8_t DCHPRI[DMA_DCHPRI_COUNT];
2273  uint8_t RESERVED_7[3824];
2274  struct { /* offset: 0x1000, array step: 0x20 */
2275  __IO uint32_t SADDR;
2276  __IO uint16_t SOFF;
2277  __IO uint16_t ATTR;
2278  union { /* offset: 0x1008, array step: 0x20 */
2279  __IO uint32_t MLNO;
2280  __IO uint32_t MLOFFNO;
2281  __IO uint32_t MLOFFYES;
2282  } NBYTES;
2283  __IO uint32_t SLAST;
2284  __IO uint32_t DADDR;
2285  __IO uint16_t DOFF;
2286  union { /* offset: 0x1016, array step: 0x20 */
2287  __IO uint16_t ELINKNO;
2288  __IO uint16_t ELINKYES;
2289  } CITER;
2290  __IO uint32_t DLASTSGA;
2291  __IO uint16_t CSR;
2292  union { /* offset: 0x101E, array step: 0x20 */
2293  __IO uint16_t ELINKNO;
2294  __IO uint16_t ELINKYES;
2295  } BITER;
2296  } TCD[DMA_TCD_COUNT];
2298 
2300 #define DMA_INSTANCE_COUNT (1u)
2301 
2302 
2303 /* DMA - Peripheral instance base addresses */
2305 #define DMA_BASE (0x40008000u)
2306 
2307 #define DMA ((DMA_Type *)DMA_BASE)
2308 
2309 #define DMA_BASE_ADDRS { DMA_BASE }
2310 
2311 #define DMA_BASE_PTRS { DMA }
2312 
2313 #define DMA_IRQS_ARR_COUNT (2u)
2314 
2315 #define DMA_CHN_IRQS_CH_COUNT (16u)
2316 
2317 #define DMA_ERROR_IRQS_CH_COUNT (1u)
2318 
2319 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
2320 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
2321 
2322 /* ----------------------------------------------------------------------------
2323  -- DMA Register Masks
2324  ---------------------------------------------------------------------------- */
2325 
2331 /* CR Bit Fields */
2332 #define DMA_CR_EDBG_MASK 0x2u
2333 #define DMA_CR_EDBG_SHIFT 1u
2334 #define DMA_CR_EDBG_WIDTH 1u
2335 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
2336 #define DMA_CR_ERCA_MASK 0x4u
2337 #define DMA_CR_ERCA_SHIFT 2u
2338 #define DMA_CR_ERCA_WIDTH 1u
2339 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
2340 #define DMA_CR_HOE_MASK 0x10u
2341 #define DMA_CR_HOE_SHIFT 4u
2342 #define DMA_CR_HOE_WIDTH 1u
2343 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
2344 #define DMA_CR_HALT_MASK 0x20u
2345 #define DMA_CR_HALT_SHIFT 5u
2346 #define DMA_CR_HALT_WIDTH 1u
2347 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
2348 #define DMA_CR_CLM_MASK 0x40u
2349 #define DMA_CR_CLM_SHIFT 6u
2350 #define DMA_CR_CLM_WIDTH 1u
2351 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
2352 #define DMA_CR_EMLM_MASK 0x80u
2353 #define DMA_CR_EMLM_SHIFT 7u
2354 #define DMA_CR_EMLM_WIDTH 1u
2355 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
2356 #define DMA_CR_ECX_MASK 0x10000u
2357 #define DMA_CR_ECX_SHIFT 16u
2358 #define DMA_CR_ECX_WIDTH 1u
2359 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
2360 #define DMA_CR_CX_MASK 0x20000u
2361 #define DMA_CR_CX_SHIFT 17u
2362 #define DMA_CR_CX_WIDTH 1u
2363 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
2364 /* ES Bit Fields */
2365 #define DMA_ES_DBE_MASK 0x1u
2366 #define DMA_ES_DBE_SHIFT 0u
2367 #define DMA_ES_DBE_WIDTH 1u
2368 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
2369 #define DMA_ES_SBE_MASK 0x2u
2370 #define DMA_ES_SBE_SHIFT 1u
2371 #define DMA_ES_SBE_WIDTH 1u
2372 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
2373 #define DMA_ES_SGE_MASK 0x4u
2374 #define DMA_ES_SGE_SHIFT 2u
2375 #define DMA_ES_SGE_WIDTH 1u
2376 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
2377 #define DMA_ES_NCE_MASK 0x8u
2378 #define DMA_ES_NCE_SHIFT 3u
2379 #define DMA_ES_NCE_WIDTH 1u
2380 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
2381 #define DMA_ES_DOE_MASK 0x10u
2382 #define DMA_ES_DOE_SHIFT 4u
2383 #define DMA_ES_DOE_WIDTH 1u
2384 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
2385 #define DMA_ES_DAE_MASK 0x20u
2386 #define DMA_ES_DAE_SHIFT 5u
2387 #define DMA_ES_DAE_WIDTH 1u
2388 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
2389 #define DMA_ES_SOE_MASK 0x40u
2390 #define DMA_ES_SOE_SHIFT 6u
2391 #define DMA_ES_SOE_WIDTH 1u
2392 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
2393 #define DMA_ES_SAE_MASK 0x80u
2394 #define DMA_ES_SAE_SHIFT 7u
2395 #define DMA_ES_SAE_WIDTH 1u
2396 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
2397 #define DMA_ES_ERRCHN_MASK 0xF00u
2398 #define DMA_ES_ERRCHN_SHIFT 8u
2399 #define DMA_ES_ERRCHN_WIDTH 4u
2400 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
2401 #define DMA_ES_CPE_MASK 0x4000u
2402 #define DMA_ES_CPE_SHIFT 14u
2403 #define DMA_ES_CPE_WIDTH 1u
2404 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
2405 #define DMA_ES_ECX_MASK 0x10000u
2406 #define DMA_ES_ECX_SHIFT 16u
2407 #define DMA_ES_ECX_WIDTH 1u
2408 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
2409 #define DMA_ES_VLD_MASK 0x80000000u
2410 #define DMA_ES_VLD_SHIFT 31u
2411 #define DMA_ES_VLD_WIDTH 1u
2412 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
2413 /* ERQ Bit Fields */
2414 #define DMA_ERQ_ERQ0_MASK 0x1u
2415 #define DMA_ERQ_ERQ0_SHIFT 0u
2416 #define DMA_ERQ_ERQ0_WIDTH 1u
2417 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
2418 #define DMA_ERQ_ERQ1_MASK 0x2u
2419 #define DMA_ERQ_ERQ1_SHIFT 1u
2420 #define DMA_ERQ_ERQ1_WIDTH 1u
2421 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
2422 #define DMA_ERQ_ERQ2_MASK 0x4u
2423 #define DMA_ERQ_ERQ2_SHIFT 2u
2424 #define DMA_ERQ_ERQ2_WIDTH 1u
2425 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
2426 #define DMA_ERQ_ERQ3_MASK 0x8u
2427 #define DMA_ERQ_ERQ3_SHIFT 3u
2428 #define DMA_ERQ_ERQ3_WIDTH 1u
2429 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
2430 #define DMA_ERQ_ERQ4_MASK 0x10u
2431 #define DMA_ERQ_ERQ4_SHIFT 4u
2432 #define DMA_ERQ_ERQ4_WIDTH 1u
2433 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
2434 #define DMA_ERQ_ERQ5_MASK 0x20u
2435 #define DMA_ERQ_ERQ5_SHIFT 5u
2436 #define DMA_ERQ_ERQ5_WIDTH 1u
2437 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
2438 #define DMA_ERQ_ERQ6_MASK 0x40u
2439 #define DMA_ERQ_ERQ6_SHIFT 6u
2440 #define DMA_ERQ_ERQ6_WIDTH 1u
2441 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
2442 #define DMA_ERQ_ERQ7_MASK 0x80u
2443 #define DMA_ERQ_ERQ7_SHIFT 7u
2444 #define DMA_ERQ_ERQ7_WIDTH 1u
2445 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
2446 #define DMA_ERQ_ERQ8_MASK 0x100u
2447 #define DMA_ERQ_ERQ8_SHIFT 8u
2448 #define DMA_ERQ_ERQ8_WIDTH 1u
2449 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
2450 #define DMA_ERQ_ERQ9_MASK 0x200u
2451 #define DMA_ERQ_ERQ9_SHIFT 9u
2452 #define DMA_ERQ_ERQ9_WIDTH 1u
2453 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
2454 #define DMA_ERQ_ERQ10_MASK 0x400u
2455 #define DMA_ERQ_ERQ10_SHIFT 10u
2456 #define DMA_ERQ_ERQ10_WIDTH 1u
2457 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
2458 #define DMA_ERQ_ERQ11_MASK 0x800u
2459 #define DMA_ERQ_ERQ11_SHIFT 11u
2460 #define DMA_ERQ_ERQ11_WIDTH 1u
2461 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
2462 #define DMA_ERQ_ERQ12_MASK 0x1000u
2463 #define DMA_ERQ_ERQ12_SHIFT 12u
2464 #define DMA_ERQ_ERQ12_WIDTH 1u
2465 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
2466 #define DMA_ERQ_ERQ13_MASK 0x2000u
2467 #define DMA_ERQ_ERQ13_SHIFT 13u
2468 #define DMA_ERQ_ERQ13_WIDTH 1u
2469 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
2470 #define DMA_ERQ_ERQ14_MASK 0x4000u
2471 #define DMA_ERQ_ERQ14_SHIFT 14u
2472 #define DMA_ERQ_ERQ14_WIDTH 1u
2473 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
2474 #define DMA_ERQ_ERQ15_MASK 0x8000u
2475 #define DMA_ERQ_ERQ15_SHIFT 15u
2476 #define DMA_ERQ_ERQ15_WIDTH 1u
2477 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
2478 /* EEI Bit Fields */
2479 #define DMA_EEI_EEI0_MASK 0x1u
2480 #define DMA_EEI_EEI0_SHIFT 0u
2481 #define DMA_EEI_EEI0_WIDTH 1u
2482 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
2483 #define DMA_EEI_EEI1_MASK 0x2u
2484 #define DMA_EEI_EEI1_SHIFT 1u
2485 #define DMA_EEI_EEI1_WIDTH 1u
2486 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
2487 #define DMA_EEI_EEI2_MASK 0x4u
2488 #define DMA_EEI_EEI2_SHIFT 2u
2489 #define DMA_EEI_EEI2_WIDTH 1u
2490 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
2491 #define DMA_EEI_EEI3_MASK 0x8u
2492 #define DMA_EEI_EEI3_SHIFT 3u
2493 #define DMA_EEI_EEI3_WIDTH 1u
2494 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
2495 #define DMA_EEI_EEI4_MASK 0x10u
2496 #define DMA_EEI_EEI4_SHIFT 4u
2497 #define DMA_EEI_EEI4_WIDTH 1u
2498 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
2499 #define DMA_EEI_EEI5_MASK 0x20u
2500 #define DMA_EEI_EEI5_SHIFT 5u
2501 #define DMA_EEI_EEI5_WIDTH 1u
2502 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
2503 #define DMA_EEI_EEI6_MASK 0x40u
2504 #define DMA_EEI_EEI6_SHIFT 6u
2505 #define DMA_EEI_EEI6_WIDTH 1u
2506 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
2507 #define DMA_EEI_EEI7_MASK 0x80u
2508 #define DMA_EEI_EEI7_SHIFT 7u
2509 #define DMA_EEI_EEI7_WIDTH 1u
2510 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
2511 #define DMA_EEI_EEI8_MASK 0x100u
2512 #define DMA_EEI_EEI8_SHIFT 8u
2513 #define DMA_EEI_EEI8_WIDTH 1u
2514 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
2515 #define DMA_EEI_EEI9_MASK 0x200u
2516 #define DMA_EEI_EEI9_SHIFT 9u
2517 #define DMA_EEI_EEI9_WIDTH 1u
2518 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
2519 #define DMA_EEI_EEI10_MASK 0x400u
2520 #define DMA_EEI_EEI10_SHIFT 10u
2521 #define DMA_EEI_EEI10_WIDTH 1u
2522 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
2523 #define DMA_EEI_EEI11_MASK 0x800u
2524 #define DMA_EEI_EEI11_SHIFT 11u
2525 #define DMA_EEI_EEI11_WIDTH 1u
2526 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
2527 #define DMA_EEI_EEI12_MASK 0x1000u
2528 #define DMA_EEI_EEI12_SHIFT 12u
2529 #define DMA_EEI_EEI12_WIDTH 1u
2530 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
2531 #define DMA_EEI_EEI13_MASK 0x2000u
2532 #define DMA_EEI_EEI13_SHIFT 13u
2533 #define DMA_EEI_EEI13_WIDTH 1u
2534 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
2535 #define DMA_EEI_EEI14_MASK 0x4000u
2536 #define DMA_EEI_EEI14_SHIFT 14u
2537 #define DMA_EEI_EEI14_WIDTH 1u
2538 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
2539 #define DMA_EEI_EEI15_MASK 0x8000u
2540 #define DMA_EEI_EEI15_SHIFT 15u
2541 #define DMA_EEI_EEI15_WIDTH 1u
2542 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
2543 /* CEEI Bit Fields */
2544 #define DMA_CEEI_CEEI_MASK 0xFu
2545 #define DMA_CEEI_CEEI_SHIFT 0u
2546 #define DMA_CEEI_CEEI_WIDTH 4u
2547 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
2548 #define DMA_CEEI_CAEE_MASK 0x40u
2549 #define DMA_CEEI_CAEE_SHIFT 6u
2550 #define DMA_CEEI_CAEE_WIDTH 1u
2551 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
2552 #define DMA_CEEI_NOP_MASK 0x80u
2553 #define DMA_CEEI_NOP_SHIFT 7u
2554 #define DMA_CEEI_NOP_WIDTH 1u
2555 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
2556 /* SEEI Bit Fields */
2557 #define DMA_SEEI_SEEI_MASK 0xFu
2558 #define DMA_SEEI_SEEI_SHIFT 0u
2559 #define DMA_SEEI_SEEI_WIDTH 4u
2560 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
2561 #define DMA_SEEI_SAEE_MASK 0x40u
2562 #define DMA_SEEI_SAEE_SHIFT 6u
2563 #define DMA_SEEI_SAEE_WIDTH 1u
2564 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
2565 #define DMA_SEEI_NOP_MASK 0x80u
2566 #define DMA_SEEI_NOP_SHIFT 7u
2567 #define DMA_SEEI_NOP_WIDTH 1u
2568 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
2569 /* CERQ Bit Fields */
2570 #define DMA_CERQ_CERQ_MASK 0xFu
2571 #define DMA_CERQ_CERQ_SHIFT 0u
2572 #define DMA_CERQ_CERQ_WIDTH 4u
2573 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
2574 #define DMA_CERQ_CAER_MASK 0x40u
2575 #define DMA_CERQ_CAER_SHIFT 6u
2576 #define DMA_CERQ_CAER_WIDTH 1u
2577 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
2578 #define DMA_CERQ_NOP_MASK 0x80u
2579 #define DMA_CERQ_NOP_SHIFT 7u
2580 #define DMA_CERQ_NOP_WIDTH 1u
2581 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
2582 /* SERQ Bit Fields */
2583 #define DMA_SERQ_SERQ_MASK 0xFu
2584 #define DMA_SERQ_SERQ_SHIFT 0u
2585 #define DMA_SERQ_SERQ_WIDTH 4u
2586 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
2587 #define DMA_SERQ_SAER_MASK 0x40u
2588 #define DMA_SERQ_SAER_SHIFT 6u
2589 #define DMA_SERQ_SAER_WIDTH 1u
2590 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
2591 #define DMA_SERQ_NOP_MASK 0x80u
2592 #define DMA_SERQ_NOP_SHIFT 7u
2593 #define DMA_SERQ_NOP_WIDTH 1u
2594 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
2595 /* CDNE Bit Fields */
2596 #define DMA_CDNE_CDNE_MASK 0xFu
2597 #define DMA_CDNE_CDNE_SHIFT 0u
2598 #define DMA_CDNE_CDNE_WIDTH 4u
2599 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
2600 #define DMA_CDNE_CADN_MASK 0x40u
2601 #define DMA_CDNE_CADN_SHIFT 6u
2602 #define DMA_CDNE_CADN_WIDTH 1u
2603 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
2604 #define DMA_CDNE_NOP_MASK 0x80u
2605 #define DMA_CDNE_NOP_SHIFT 7u
2606 #define DMA_CDNE_NOP_WIDTH 1u
2607 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
2608 /* SSRT Bit Fields */
2609 #define DMA_SSRT_SSRT_MASK 0xFu
2610 #define DMA_SSRT_SSRT_SHIFT 0u
2611 #define DMA_SSRT_SSRT_WIDTH 4u
2612 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
2613 #define DMA_SSRT_SAST_MASK 0x40u
2614 #define DMA_SSRT_SAST_SHIFT 6u
2615 #define DMA_SSRT_SAST_WIDTH 1u
2616 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
2617 #define DMA_SSRT_NOP_MASK 0x80u
2618 #define DMA_SSRT_NOP_SHIFT 7u
2619 #define DMA_SSRT_NOP_WIDTH 1u
2620 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
2621 /* CERR Bit Fields */
2622 #define DMA_CERR_CERR_MASK 0xFu
2623 #define DMA_CERR_CERR_SHIFT 0u
2624 #define DMA_CERR_CERR_WIDTH 4u
2625 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
2626 #define DMA_CERR_CAEI_MASK 0x40u
2627 #define DMA_CERR_CAEI_SHIFT 6u
2628 #define DMA_CERR_CAEI_WIDTH 1u
2629 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
2630 #define DMA_CERR_NOP_MASK 0x80u
2631 #define DMA_CERR_NOP_SHIFT 7u
2632 #define DMA_CERR_NOP_WIDTH 1u
2633 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
2634 /* CINT Bit Fields */
2635 #define DMA_CINT_CINT_MASK 0xFu
2636 #define DMA_CINT_CINT_SHIFT 0u
2637 #define DMA_CINT_CINT_WIDTH 4u
2638 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
2639 #define DMA_CINT_CAIR_MASK 0x40u
2640 #define DMA_CINT_CAIR_SHIFT 6u
2641 #define DMA_CINT_CAIR_WIDTH 1u
2642 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
2643 #define DMA_CINT_NOP_MASK 0x80u
2644 #define DMA_CINT_NOP_SHIFT 7u
2645 #define DMA_CINT_NOP_WIDTH 1u
2646 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
2647 /* INT Bit Fields */
2648 #define DMA_INT_INT0_MASK 0x1u
2649 #define DMA_INT_INT0_SHIFT 0u
2650 #define DMA_INT_INT0_WIDTH 1u
2651 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
2652 #define DMA_INT_INT1_MASK 0x2u
2653 #define DMA_INT_INT1_SHIFT 1u
2654 #define DMA_INT_INT1_WIDTH 1u
2655 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
2656 #define DMA_INT_INT2_MASK 0x4u
2657 #define DMA_INT_INT2_SHIFT 2u
2658 #define DMA_INT_INT2_WIDTH 1u
2659 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
2660 #define DMA_INT_INT3_MASK 0x8u
2661 #define DMA_INT_INT3_SHIFT 3u
2662 #define DMA_INT_INT3_WIDTH 1u
2663 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
2664 #define DMA_INT_INT4_MASK 0x10u
2665 #define DMA_INT_INT4_SHIFT 4u
2666 #define DMA_INT_INT4_WIDTH 1u
2667 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
2668 #define DMA_INT_INT5_MASK 0x20u
2669 #define DMA_INT_INT5_SHIFT 5u
2670 #define DMA_INT_INT5_WIDTH 1u
2671 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
2672 #define DMA_INT_INT6_MASK 0x40u
2673 #define DMA_INT_INT6_SHIFT 6u
2674 #define DMA_INT_INT6_WIDTH 1u
2675 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
2676 #define DMA_INT_INT7_MASK 0x80u
2677 #define DMA_INT_INT7_SHIFT 7u
2678 #define DMA_INT_INT7_WIDTH 1u
2679 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
2680 #define DMA_INT_INT8_MASK 0x100u
2681 #define DMA_INT_INT8_SHIFT 8u
2682 #define DMA_INT_INT8_WIDTH 1u
2683 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
2684 #define DMA_INT_INT9_MASK 0x200u
2685 #define DMA_INT_INT9_SHIFT 9u
2686 #define DMA_INT_INT9_WIDTH 1u
2687 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
2688 #define DMA_INT_INT10_MASK 0x400u
2689 #define DMA_INT_INT10_SHIFT 10u
2690 #define DMA_INT_INT10_WIDTH 1u
2691 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
2692 #define DMA_INT_INT11_MASK 0x800u
2693 #define DMA_INT_INT11_SHIFT 11u
2694 #define DMA_INT_INT11_WIDTH 1u
2695 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
2696 #define DMA_INT_INT12_MASK 0x1000u
2697 #define DMA_INT_INT12_SHIFT 12u
2698 #define DMA_INT_INT12_WIDTH 1u
2699 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
2700 #define DMA_INT_INT13_MASK 0x2000u
2701 #define DMA_INT_INT13_SHIFT 13u
2702 #define DMA_INT_INT13_WIDTH 1u
2703 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
2704 #define DMA_INT_INT14_MASK 0x4000u
2705 #define DMA_INT_INT14_SHIFT 14u
2706 #define DMA_INT_INT14_WIDTH 1u
2707 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
2708 #define DMA_INT_INT15_MASK 0x8000u
2709 #define DMA_INT_INT15_SHIFT 15u
2710 #define DMA_INT_INT15_WIDTH 1u
2711 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
2712 /* ERR Bit Fields */
2713 #define DMA_ERR_ERR0_MASK 0x1u
2714 #define DMA_ERR_ERR0_SHIFT 0u
2715 #define DMA_ERR_ERR0_WIDTH 1u
2716 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
2717 #define DMA_ERR_ERR1_MASK 0x2u
2718 #define DMA_ERR_ERR1_SHIFT 1u
2719 #define DMA_ERR_ERR1_WIDTH 1u
2720 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
2721 #define DMA_ERR_ERR2_MASK 0x4u
2722 #define DMA_ERR_ERR2_SHIFT 2u
2723 #define DMA_ERR_ERR2_WIDTH 1u
2724 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
2725 #define DMA_ERR_ERR3_MASK 0x8u
2726 #define DMA_ERR_ERR3_SHIFT 3u
2727 #define DMA_ERR_ERR3_WIDTH 1u
2728 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
2729 #define DMA_ERR_ERR4_MASK 0x10u
2730 #define DMA_ERR_ERR4_SHIFT 4u
2731 #define DMA_ERR_ERR4_WIDTH 1u
2732 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
2733 #define DMA_ERR_ERR5_MASK 0x20u
2734 #define DMA_ERR_ERR5_SHIFT 5u
2735 #define DMA_ERR_ERR5_WIDTH 1u
2736 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
2737 #define DMA_ERR_ERR6_MASK 0x40u
2738 #define DMA_ERR_ERR6_SHIFT 6u
2739 #define DMA_ERR_ERR6_WIDTH 1u
2740 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
2741 #define DMA_ERR_ERR7_MASK 0x80u
2742 #define DMA_ERR_ERR7_SHIFT 7u
2743 #define DMA_ERR_ERR7_WIDTH 1u
2744 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
2745 #define DMA_ERR_ERR8_MASK 0x100u
2746 #define DMA_ERR_ERR8_SHIFT 8u
2747 #define DMA_ERR_ERR8_WIDTH 1u
2748 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
2749 #define DMA_ERR_ERR9_MASK 0x200u
2750 #define DMA_ERR_ERR9_SHIFT 9u
2751 #define DMA_ERR_ERR9_WIDTH 1u
2752 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
2753 #define DMA_ERR_ERR10_MASK 0x400u
2754 #define DMA_ERR_ERR10_SHIFT 10u
2755 #define DMA_ERR_ERR10_WIDTH 1u
2756 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
2757 #define DMA_ERR_ERR11_MASK 0x800u
2758 #define DMA_ERR_ERR11_SHIFT 11u
2759 #define DMA_ERR_ERR11_WIDTH 1u
2760 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
2761 #define DMA_ERR_ERR12_MASK 0x1000u
2762 #define DMA_ERR_ERR12_SHIFT 12u
2763 #define DMA_ERR_ERR12_WIDTH 1u
2764 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
2765 #define DMA_ERR_ERR13_MASK 0x2000u
2766 #define DMA_ERR_ERR13_SHIFT 13u
2767 #define DMA_ERR_ERR13_WIDTH 1u
2768 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
2769 #define DMA_ERR_ERR14_MASK 0x4000u
2770 #define DMA_ERR_ERR14_SHIFT 14u
2771 #define DMA_ERR_ERR14_WIDTH 1u
2772 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
2773 #define DMA_ERR_ERR15_MASK 0x8000u
2774 #define DMA_ERR_ERR15_SHIFT 15u
2775 #define DMA_ERR_ERR15_WIDTH 1u
2776 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
2777 /* HRS Bit Fields */
2778 #define DMA_HRS_HRS0_MASK 0x1u
2779 #define DMA_HRS_HRS0_SHIFT 0u
2780 #define DMA_HRS_HRS0_WIDTH 1u
2781 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
2782 #define DMA_HRS_HRS1_MASK 0x2u
2783 #define DMA_HRS_HRS1_SHIFT 1u
2784 #define DMA_HRS_HRS1_WIDTH 1u
2785 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
2786 #define DMA_HRS_HRS2_MASK 0x4u
2787 #define DMA_HRS_HRS2_SHIFT 2u
2788 #define DMA_HRS_HRS2_WIDTH 1u
2789 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
2790 #define DMA_HRS_HRS3_MASK 0x8u
2791 #define DMA_HRS_HRS3_SHIFT 3u
2792 #define DMA_HRS_HRS3_WIDTH 1u
2793 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
2794 #define DMA_HRS_HRS4_MASK 0x10u
2795 #define DMA_HRS_HRS4_SHIFT 4u
2796 #define DMA_HRS_HRS4_WIDTH 1u
2797 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
2798 #define DMA_HRS_HRS5_MASK 0x20u
2799 #define DMA_HRS_HRS5_SHIFT 5u
2800 #define DMA_HRS_HRS5_WIDTH 1u
2801 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
2802 #define DMA_HRS_HRS6_MASK 0x40u
2803 #define DMA_HRS_HRS6_SHIFT 6u
2804 #define DMA_HRS_HRS6_WIDTH 1u
2805 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
2806 #define DMA_HRS_HRS7_MASK 0x80u
2807 #define DMA_HRS_HRS7_SHIFT 7u
2808 #define DMA_HRS_HRS7_WIDTH 1u
2809 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
2810 #define DMA_HRS_HRS8_MASK 0x100u
2811 #define DMA_HRS_HRS8_SHIFT 8u
2812 #define DMA_HRS_HRS8_WIDTH 1u
2813 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
2814 #define DMA_HRS_HRS9_MASK 0x200u
2815 #define DMA_HRS_HRS9_SHIFT 9u
2816 #define DMA_HRS_HRS9_WIDTH 1u
2817 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
2818 #define DMA_HRS_HRS10_MASK 0x400u
2819 #define DMA_HRS_HRS10_SHIFT 10u
2820 #define DMA_HRS_HRS10_WIDTH 1u
2821 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
2822 #define DMA_HRS_HRS11_MASK 0x800u
2823 #define DMA_HRS_HRS11_SHIFT 11u
2824 #define DMA_HRS_HRS11_WIDTH 1u
2825 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
2826 #define DMA_HRS_HRS12_MASK 0x1000u
2827 #define DMA_HRS_HRS12_SHIFT 12u
2828 #define DMA_HRS_HRS12_WIDTH 1u
2829 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
2830 #define DMA_HRS_HRS13_MASK 0x2000u
2831 #define DMA_HRS_HRS13_SHIFT 13u
2832 #define DMA_HRS_HRS13_WIDTH 1u
2833 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
2834 #define DMA_HRS_HRS14_MASK 0x4000u
2835 #define DMA_HRS_HRS14_SHIFT 14u
2836 #define DMA_HRS_HRS14_WIDTH 1u
2837 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
2838 #define DMA_HRS_HRS15_MASK 0x8000u
2839 #define DMA_HRS_HRS15_SHIFT 15u
2840 #define DMA_HRS_HRS15_WIDTH 1u
2841 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
2842 /* EARS Bit Fields */
2843 #define DMA_EARS_EDREQ_0_MASK 0x1u
2844 #define DMA_EARS_EDREQ_0_SHIFT 0u
2845 #define DMA_EARS_EDREQ_0_WIDTH 1u
2846 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
2847 #define DMA_EARS_EDREQ_1_MASK 0x2u
2848 #define DMA_EARS_EDREQ_1_SHIFT 1u
2849 #define DMA_EARS_EDREQ_1_WIDTH 1u
2850 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
2851 #define DMA_EARS_EDREQ_2_MASK 0x4u
2852 #define DMA_EARS_EDREQ_2_SHIFT 2u
2853 #define DMA_EARS_EDREQ_2_WIDTH 1u
2854 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
2855 #define DMA_EARS_EDREQ_3_MASK 0x8u
2856 #define DMA_EARS_EDREQ_3_SHIFT 3u
2857 #define DMA_EARS_EDREQ_3_WIDTH 1u
2858 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
2859 #define DMA_EARS_EDREQ_4_MASK 0x10u
2860 #define DMA_EARS_EDREQ_4_SHIFT 4u
2861 #define DMA_EARS_EDREQ_4_WIDTH 1u
2862 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
2863 #define DMA_EARS_EDREQ_5_MASK 0x20u
2864 #define DMA_EARS_EDREQ_5_SHIFT 5u
2865 #define DMA_EARS_EDREQ_5_WIDTH 1u
2866 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
2867 #define DMA_EARS_EDREQ_6_MASK 0x40u
2868 #define DMA_EARS_EDREQ_6_SHIFT 6u
2869 #define DMA_EARS_EDREQ_6_WIDTH 1u
2870 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
2871 #define DMA_EARS_EDREQ_7_MASK 0x80u
2872 #define DMA_EARS_EDREQ_7_SHIFT 7u
2873 #define DMA_EARS_EDREQ_7_WIDTH 1u
2874 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
2875 #define DMA_EARS_EDREQ_8_MASK 0x100u
2876 #define DMA_EARS_EDREQ_8_SHIFT 8u
2877 #define DMA_EARS_EDREQ_8_WIDTH 1u
2878 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
2879 #define DMA_EARS_EDREQ_9_MASK 0x200u
2880 #define DMA_EARS_EDREQ_9_SHIFT 9u
2881 #define DMA_EARS_EDREQ_9_WIDTH 1u
2882 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
2883 #define DMA_EARS_EDREQ_10_MASK 0x400u
2884 #define DMA_EARS_EDREQ_10_SHIFT 10u
2885 #define DMA_EARS_EDREQ_10_WIDTH 1u
2886 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
2887 #define DMA_EARS_EDREQ_11_MASK 0x800u
2888 #define DMA_EARS_EDREQ_11_SHIFT 11u
2889 #define DMA_EARS_EDREQ_11_WIDTH 1u
2890 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
2891 #define DMA_EARS_EDREQ_12_MASK 0x1000u
2892 #define DMA_EARS_EDREQ_12_SHIFT 12u
2893 #define DMA_EARS_EDREQ_12_WIDTH 1u
2894 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
2895 #define DMA_EARS_EDREQ_13_MASK 0x2000u
2896 #define DMA_EARS_EDREQ_13_SHIFT 13u
2897 #define DMA_EARS_EDREQ_13_WIDTH 1u
2898 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
2899 #define DMA_EARS_EDREQ_14_MASK 0x4000u
2900 #define DMA_EARS_EDREQ_14_SHIFT 14u
2901 #define DMA_EARS_EDREQ_14_WIDTH 1u
2902 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
2903 #define DMA_EARS_EDREQ_15_MASK 0x8000u
2904 #define DMA_EARS_EDREQ_15_SHIFT 15u
2905 #define DMA_EARS_EDREQ_15_WIDTH 1u
2906 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
2907 /* DCHPRI Bit Fields */
2908 #define DMA_DCHPRI_CHPRI_MASK 0xFu
2909 #define DMA_DCHPRI_CHPRI_SHIFT 0u
2910 #define DMA_DCHPRI_CHPRI_WIDTH 4u
2911 #define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_CHPRI_SHIFT))&DMA_DCHPRI_CHPRI_MASK)
2912 #define DMA_DCHPRI_DPA_MASK 0x40u
2913 #define DMA_DCHPRI_DPA_SHIFT 6u
2914 #define DMA_DCHPRI_DPA_WIDTH 1u
2915 #define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_DPA_SHIFT))&DMA_DCHPRI_DPA_MASK)
2916 #define DMA_DCHPRI_ECP_MASK 0x80u
2917 #define DMA_DCHPRI_ECP_SHIFT 7u
2918 #define DMA_DCHPRI_ECP_WIDTH 1u
2919 #define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_ECP_SHIFT))&DMA_DCHPRI_ECP_MASK)
2920 /* TCD_SADDR Bit Fields */
2921 #define DMA_TCD_SADDR_SADDR_MASK 0xFFFFFFFFu
2922 #define DMA_TCD_SADDR_SADDR_SHIFT 0u
2923 #define DMA_TCD_SADDR_SADDR_WIDTH 32u
2924 #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SADDR_SADDR_SHIFT))&DMA_TCD_SADDR_SADDR_MASK)
2925 /* TCD_SOFF Bit Fields */
2926 #define DMA_TCD_SOFF_SOFF_MASK 0xFFFFu
2927 #define DMA_TCD_SOFF_SOFF_SHIFT 0u
2928 #define DMA_TCD_SOFF_SOFF_WIDTH 16u
2929 #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_SOFF_SOFF_SHIFT))&DMA_TCD_SOFF_SOFF_MASK)
2930 /* TCD_ATTR Bit Fields */
2931 #define DMA_TCD_ATTR_DSIZE_MASK 0x7u
2932 #define DMA_TCD_ATTR_DSIZE_SHIFT 0u
2933 #define DMA_TCD_ATTR_DSIZE_WIDTH 3u
2934 #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DSIZE_SHIFT))&DMA_TCD_ATTR_DSIZE_MASK)
2935 #define DMA_TCD_ATTR_DMOD_MASK 0xF8u
2936 #define DMA_TCD_ATTR_DMOD_SHIFT 3u
2937 #define DMA_TCD_ATTR_DMOD_WIDTH 5u
2938 #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DMOD_SHIFT))&DMA_TCD_ATTR_DMOD_MASK)
2939 #define DMA_TCD_ATTR_SSIZE_MASK 0x700u
2940 #define DMA_TCD_ATTR_SSIZE_SHIFT 8u
2941 #define DMA_TCD_ATTR_SSIZE_WIDTH 3u
2942 #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SSIZE_SHIFT))&DMA_TCD_ATTR_SSIZE_MASK)
2943 #define DMA_TCD_ATTR_SMOD_MASK 0xF800u
2944 #define DMA_TCD_ATTR_SMOD_SHIFT 11u
2945 #define DMA_TCD_ATTR_SMOD_WIDTH 5u
2946 #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SMOD_SHIFT))&DMA_TCD_ATTR_SMOD_MASK)
2947 /* TCD_NBYTES_MLNO Bit Fields */
2948 #define DMA_TCD_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
2949 #define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT 0u
2950 #define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH 32u
2951 #define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLNO_NBYTES_MASK)
2952 /* TCD_NBYTES_MLOFFNO Bit Fields */
2953 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
2954 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT 0u
2955 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH 30u
2956 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
2957 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
2958 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT 30u
2959 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH 1u
2960 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
2961 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
2962 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT 31u
2963 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH 1u
2964 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
2965 /* TCD_NBYTES_MLOFFYES Bit Fields */
2966 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
2967 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT 0u
2968 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH 10u
2969 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
2970 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
2971 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT 10u
2972 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH 20u
2973 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
2974 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
2975 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT 30u
2976 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH 1u
2977 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
2978 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
2979 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT 31u
2980 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH 1u
2981 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
2982 /* TCD_SLAST Bit Fields */
2983 #define DMA_TCD_SLAST_SLAST_MASK 0xFFFFFFFFu
2984 #define DMA_TCD_SLAST_SLAST_SHIFT 0u
2985 #define DMA_TCD_SLAST_SLAST_WIDTH 32u
2986 #define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SLAST_SLAST_SHIFT))&DMA_TCD_SLAST_SLAST_MASK)
2987 /* TCD_DADDR Bit Fields */
2988 #define DMA_TCD_DADDR_DADDR_MASK 0xFFFFFFFFu
2989 #define DMA_TCD_DADDR_DADDR_SHIFT 0u
2990 #define DMA_TCD_DADDR_DADDR_WIDTH 32u
2991 #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DADDR_DADDR_SHIFT))&DMA_TCD_DADDR_DADDR_MASK)
2992 /* TCD_DOFF Bit Fields */
2993 #define DMA_TCD_DOFF_DOFF_MASK 0xFFFFu
2994 #define DMA_TCD_DOFF_DOFF_SHIFT 0u
2995 #define DMA_TCD_DOFF_DOFF_WIDTH 16u
2996 #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_DOFF_DOFF_SHIFT))&DMA_TCD_DOFF_DOFF_MASK)
2997 /* TCD_CITER_ELINKNO Bit Fields */
2998 #define DMA_TCD_CITER_ELINKNO_CITER_MASK 0x7FFFu
2999 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT 0u
3000 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH 15u
3001 #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_CITER_SHIFT))&DMA_TCD_CITER_ELINKNO_CITER_MASK)
3002 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK 0x8000u
3003 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT 15u
3004 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH 1u
3005 #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_CITER_ELINKNO_ELINK_MASK)
3006 /* TCD_CITER_ELINKYES Bit Fields */
3007 #define DMA_TCD_CITER_ELINKYES_CITER_LE_MASK 0x1FFu
3008 #define DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT 0u
3009 #define DMA_TCD_CITER_ELINKYES_CITER_LE_WIDTH 9u
3010 #define DMA_TCD_CITER_ELINKYES_CITER_LE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT))&DMA_TCD_CITER_ELINKYES_CITER_LE_MASK)
3011 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00u
3012 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT 9u
3013 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH 4u
3014 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
3015 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK 0x8000u
3016 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT 15u
3017 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH 1u
3018 #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_CITER_ELINKYES_ELINK_MASK)
3019 /* TCD_DLASTSGA Bit Fields */
3020 #define DMA_TCD_DLASTSGA_DLASTSGA_MASK 0xFFFFFFFFu
3021 #define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT 0u
3022 #define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH 32u
3023 #define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DLASTSGA_DLASTSGA_SHIFT))&DMA_TCD_DLASTSGA_DLASTSGA_MASK)
3024 /* TCD_CSR Bit Fields */
3025 #define DMA_TCD_CSR_START_MASK 0x1u
3026 #define DMA_TCD_CSR_START_SHIFT 0u
3027 #define DMA_TCD_CSR_START_WIDTH 1u
3028 #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_START_SHIFT))&DMA_TCD_CSR_START_MASK)
3029 #define DMA_TCD_CSR_INTMAJOR_MASK 0x2u
3030 #define DMA_TCD_CSR_INTMAJOR_SHIFT 1u
3031 #define DMA_TCD_CSR_INTMAJOR_WIDTH 1u
3032 #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTMAJOR_SHIFT))&DMA_TCD_CSR_INTMAJOR_MASK)
3033 #define DMA_TCD_CSR_INTHALF_MASK 0x4u
3034 #define DMA_TCD_CSR_INTHALF_SHIFT 2u
3035 #define DMA_TCD_CSR_INTHALF_WIDTH 1u
3036 #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTHALF_SHIFT))&DMA_TCD_CSR_INTHALF_MASK)
3037 #define DMA_TCD_CSR_DREQ_MASK 0x8u
3038 #define DMA_TCD_CSR_DREQ_SHIFT 3u
3039 #define DMA_TCD_CSR_DREQ_WIDTH 1u
3040 #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DREQ_SHIFT))&DMA_TCD_CSR_DREQ_MASK)
3041 #define DMA_TCD_CSR_ESG_MASK 0x10u
3042 #define DMA_TCD_CSR_ESG_SHIFT 4u
3043 #define DMA_TCD_CSR_ESG_WIDTH 1u
3044 #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ESG_SHIFT))&DMA_TCD_CSR_ESG_MASK)
3045 #define DMA_TCD_CSR_MAJORELINK_MASK 0x20u
3046 #define DMA_TCD_CSR_MAJORELINK_SHIFT 5u
3047 #define DMA_TCD_CSR_MAJORELINK_WIDTH 1u
3048 #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORELINK_SHIFT))&DMA_TCD_CSR_MAJORELINK_MASK)
3049 #define DMA_TCD_CSR_ACTIVE_MASK 0x40u
3050 #define DMA_TCD_CSR_ACTIVE_SHIFT 6u
3051 #define DMA_TCD_CSR_ACTIVE_WIDTH 1u
3052 #define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ACTIVE_SHIFT))&DMA_TCD_CSR_ACTIVE_MASK)
3053 #define DMA_TCD_CSR_DONE_MASK 0x80u
3054 #define DMA_TCD_CSR_DONE_SHIFT 7u
3055 #define DMA_TCD_CSR_DONE_WIDTH 1u
3056 #define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DONE_SHIFT))&DMA_TCD_CSR_DONE_MASK)
3057 #define DMA_TCD_CSR_MAJORLINKCH_MASK 0xF00u
3058 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT 8u
3059 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH 4u
3060 #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORLINKCH_SHIFT))&DMA_TCD_CSR_MAJORLINKCH_MASK)
3061 #define DMA_TCD_CSR_BWC_MASK 0xC000u
3062 #define DMA_TCD_CSR_BWC_SHIFT 14u
3063 #define DMA_TCD_CSR_BWC_WIDTH 2u
3064 #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_BWC_SHIFT))&DMA_TCD_CSR_BWC_MASK)
3065 /* TCD_BITER_ELINKNO Bit Fields */
3066 #define DMA_TCD_BITER_ELINKNO_BITER_MASK 0x7FFFu
3067 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT 0u
3068 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH 15u
3069 #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_BITER_SHIFT))&DMA_TCD_BITER_ELINKNO_BITER_MASK)
3070 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK 0x8000u
3071 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT 15u
3072 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH 1u
3073 #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_BITER_ELINKNO_ELINK_MASK)
3074 /* TCD_BITER_ELINKYES Bit Fields */
3075 #define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x1FFu
3076 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT 0u
3077 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH 9u
3078 #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_BITER_SHIFT))&DMA_TCD_BITER_ELINKYES_BITER_MASK)
3079 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00u
3080 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT 9u
3081 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH 4u
3082 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
3083 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK 0x8000u
3084 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT 15u
3085 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH 1u
3086 #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_BITER_ELINKYES_ELINK_MASK)
3087  /* end of group DMA_Register_Masks */
3091 
3092  /* end of group DMA_Peripheral_Access_Layer */
3096 
3097 
3098 /* ----------------------------------------------------------------------------
3099  -- DMAMUX Peripheral Access Layer
3100  ---------------------------------------------------------------------------- */
3101 
3109 #define DMAMUX_CHCFG_COUNT 16u
3110 
3112 typedef struct {
3113  __IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT];
3115 
3117 #define DMAMUX_INSTANCE_COUNT (1u)
3118 
3119 
3120 /* DMAMUX - Peripheral instance base addresses */
3122 #define DMAMUX_BASE (0x40021000u)
3123 
3124 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3125 
3126 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
3127 
3128 #define DMAMUX_BASE_PTRS { DMAMUX }
3129 
3130 /* ----------------------------------------------------------------------------
3131  -- DMAMUX Register Masks
3132  ---------------------------------------------------------------------------- */
3133 
3139 /* CHCFG Bit Fields */
3140 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
3141 #define DMAMUX_CHCFG_SOURCE_SHIFT 0u
3142 #define DMAMUX_CHCFG_SOURCE_WIDTH 6u
3143 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
3144 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
3145 #define DMAMUX_CHCFG_TRIG_SHIFT 6u
3146 #define DMAMUX_CHCFG_TRIG_WIDTH 1u
3147 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
3148 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
3149 #define DMAMUX_CHCFG_ENBL_SHIFT 7u
3150 #define DMAMUX_CHCFG_ENBL_WIDTH 1u
3151 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
3152  /* end of group DMAMUX_Register_Masks */
3156 
3157  /* end of group DMAMUX_Peripheral_Access_Layer */
3161 
3162 
3163 /* ----------------------------------------------------------------------------
3164  -- EIM Peripheral Access Layer
3165  ---------------------------------------------------------------------------- */
3166 
3174 #define EIM_EICHDn_COUNT 2u
3175 
3177 typedef struct {
3178  __IO uint32_t EIMCR;
3179  __IO uint32_t EICHEN;
3180  uint8_t RESERVED_0[248];
3181  struct { /* offset: 0x100, array step: 0x100 */
3182  __IO uint32_t WORD0;
3183  __IO uint32_t WORD1;
3184  uint8_t RESERVED_0[248];
3185  } EICHDn[EIM_EICHDn_COUNT];
3187 
3189 #define EIM_INSTANCE_COUNT (1u)
3190 
3191 
3192 /* EIM - Peripheral instance base addresses */
3194 #define EIM_BASE (0x40019000u)
3195 
3196 #define EIM ((EIM_Type *)EIM_BASE)
3197 
3198 #define EIM_BASE_ADDRS { EIM_BASE }
3199 
3200 #define EIM_BASE_PTRS { EIM }
3201 
3202 /* ----------------------------------------------------------------------------
3203  -- EIM Register Masks
3204  ---------------------------------------------------------------------------- */
3205 
3211 /* EIMCR Bit Fields */
3212 #define EIM_EIMCR_GEIEN_MASK 0x1u
3213 #define EIM_EIMCR_GEIEN_SHIFT 0u
3214 #define EIM_EIMCR_GEIEN_WIDTH 1u
3215 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EIMCR_GEIEN_SHIFT))&EIM_EIMCR_GEIEN_MASK)
3216 /* EICHEN Bit Fields */
3217 #define EIM_EICHEN_EICH1EN_MASK 0x40000000u
3218 #define EIM_EICHEN_EICH1EN_SHIFT 30u
3219 #define EIM_EICHEN_EICH1EN_WIDTH 1u
3220 #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH1EN_SHIFT))&EIM_EICHEN_EICH1EN_MASK)
3221 #define EIM_EICHEN_EICH0EN_MASK 0x80000000u
3222 #define EIM_EICHEN_EICH0EN_SHIFT 31u
3223 #define EIM_EICHEN_EICH0EN_WIDTH 1u
3224 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH0EN_SHIFT))&EIM_EICHEN_EICH0EN_MASK)
3225 /* EICHDn_WORD0 Bit Fields */
3226 #define EIM_EICHDn_WORD0_CHKBIT_MASK_MASK 0xFE000000u
3227 #define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT 25u
3228 #define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH 7u
3229 #define EIM_EICHDn_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT))&EIM_EICHDn_WORD0_CHKBIT_MASK_MASK)
3230 /* EICHDn_WORD1 Bit Fields */
3231 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK 0xFFFFFFFFu
3232 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT 0u
3233 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_WIDTH 32u
3234 #define EIM_EICHDn_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT))&EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK)
3235  /* end of group EIM_Register_Masks */
3239 
3240  /* end of group EIM_Peripheral_Access_Layer */
3244 
3245 
3246 /* ----------------------------------------------------------------------------
3247  -- ERM Peripheral Access Layer
3248  ---------------------------------------------------------------------------- */
3249 
3257 #define ERM_EARn_COUNT 2u
3258 
3260 typedef struct {
3261  __IO uint32_t CR0;
3262  uint8_t RESERVED_0[12];
3263  __IO uint32_t SR0;
3264  uint8_t RESERVED_1[236];
3265  struct { /* offset: 0x100, array step: 0x10 */
3266  __I uint32_t EAR;
3267  uint8_t RESERVED_0[12];
3268  } EARn[ERM_EARn_COUNT];
3270 
3272 #define ERM_INSTANCE_COUNT (1u)
3273 
3274 
3275 /* ERM - Peripheral instance base addresses */
3277 #define ERM_BASE (0x40018000u)
3278 
3279 #define ERM ((ERM_Type *)ERM_BASE)
3280 
3281 #define ERM_BASE_ADDRS { ERM_BASE }
3282 
3283 #define ERM_BASE_PTRS { ERM }
3284 
3285 #define ERM_IRQS_ARR_COUNT (2u)
3286 
3287 #define ERM_SINGLE_IRQS_CH_COUNT (1u)
3288 
3289 #define ERM_DOUBLE_IRQS_CH_COUNT (1u)
3290 
3291 #define ERM_SINGLE_IRQS { ERM_single_fault_IRQn }
3292 #define ERM_DOUBLE_IRQS { ERM_double_fault_IRQn }
3293 
3294 /* ----------------------------------------------------------------------------
3295  -- ERM Register Masks
3296  ---------------------------------------------------------------------------- */
3297 
3303 /* CR0 Bit Fields */
3304 #define ERM_CR0_ENCIE1_MASK 0x4000000u
3305 #define ERM_CR0_ENCIE1_SHIFT 26u
3306 #define ERM_CR0_ENCIE1_WIDTH 1u
3307 #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE1_SHIFT))&ERM_CR0_ENCIE1_MASK)
3308 #define ERM_CR0_ESCIE1_MASK 0x8000000u
3309 #define ERM_CR0_ESCIE1_SHIFT 27u
3310 #define ERM_CR0_ESCIE1_WIDTH 1u
3311 #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE1_SHIFT))&ERM_CR0_ESCIE1_MASK)
3312 #define ERM_CR0_ENCIE0_MASK 0x40000000u
3313 #define ERM_CR0_ENCIE0_SHIFT 30u
3314 #define ERM_CR0_ENCIE0_WIDTH 1u
3315 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK)
3316 #define ERM_CR0_ESCIE0_MASK 0x80000000u
3317 #define ERM_CR0_ESCIE0_SHIFT 31u
3318 #define ERM_CR0_ESCIE0_WIDTH 1u
3319 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK)
3320 /* SR0 Bit Fields */
3321 #define ERM_SR0_NCE1_MASK 0x4000000u
3322 #define ERM_SR0_NCE1_SHIFT 26u
3323 #define ERM_SR0_NCE1_WIDTH 1u
3324 #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE1_SHIFT))&ERM_SR0_NCE1_MASK)
3325 #define ERM_SR0_SBC1_MASK 0x8000000u
3326 #define ERM_SR0_SBC1_SHIFT 27u
3327 #define ERM_SR0_SBC1_WIDTH 1u
3328 #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC1_SHIFT))&ERM_SR0_SBC1_MASK)
3329 #define ERM_SR0_NCE0_MASK 0x40000000u
3330 #define ERM_SR0_NCE0_SHIFT 30u
3331 #define ERM_SR0_NCE0_WIDTH 1u
3332 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK)
3333 #define ERM_SR0_SBC0_MASK 0x80000000u
3334 #define ERM_SR0_SBC0_SHIFT 31u
3335 #define ERM_SR0_SBC0_WIDTH 1u
3336 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK)
3337 /* EARn_EAR Bit Fields */
3338 #define ERM_EARn_EAR_EAR_MASK 0xFFFFFFFFu
3339 #define ERM_EARn_EAR_EAR_SHIFT 0u
3340 #define ERM_EARn_EAR_EAR_WIDTH 32u
3341 #define ERM_EARn_EAR_EAR(x) (((uint32_t)(((uint32_t)(x))<<ERM_EARn_EAR_EAR_SHIFT))&ERM_EARn_EAR_EAR_MASK)
3342  /* end of group ERM_Register_Masks */
3346 
3347  /* end of group ERM_Peripheral_Access_Layer */
3351 
3352 
3353 /* ----------------------------------------------------------------------------
3354  -- EWM Peripheral Access Layer
3355  ---------------------------------------------------------------------------- */
3356 
3366 typedef struct {
3367  __IO uint8_t CTRL;
3368  __O uint8_t SERV;
3369  __IO uint8_t CMPL;
3370  __IO uint8_t CMPH;
3371  uint8_t RESERVED_0[1];
3372  __IO uint8_t CLKPRESCALER;
3374 
3376 #define EWM_INSTANCE_COUNT (1u)
3377 
3378 
3379 /* EWM - Peripheral instance base addresses */
3381 #define EWM_BASE (0x40061000u)
3382 
3383 #define EWM ((EWM_Type *)EWM_BASE)
3384 
3385 #define EWM_BASE_ADDRS { EWM_BASE }
3386 
3387 #define EWM_BASE_PTRS { EWM }
3388 
3389 #define EWM_IRQS_ARR_COUNT (1u)
3390 
3391 #define EWM_IRQS_CH_COUNT (1u)
3392 
3393 #define EWM_IRQS { WDOG_EWM_IRQn }
3394 
3395 /* ----------------------------------------------------------------------------
3396  -- EWM Register Masks
3397  ---------------------------------------------------------------------------- */
3398 
3404 /* CTRL Bit Fields */
3405 #define EWM_CTRL_EWMEN_MASK 0x1u
3406 #define EWM_CTRL_EWMEN_SHIFT 0u
3407 #define EWM_CTRL_EWMEN_WIDTH 1u
3408 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
3409 #define EWM_CTRL_ASSIN_MASK 0x2u
3410 #define EWM_CTRL_ASSIN_SHIFT 1u
3411 #define EWM_CTRL_ASSIN_WIDTH 1u
3412 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
3413 #define EWM_CTRL_INEN_MASK 0x4u
3414 #define EWM_CTRL_INEN_SHIFT 2u
3415 #define EWM_CTRL_INEN_WIDTH 1u
3416 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
3417 #define EWM_CTRL_INTEN_MASK 0x8u
3418 #define EWM_CTRL_INTEN_SHIFT 3u
3419 #define EWM_CTRL_INTEN_WIDTH 1u
3420 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
3421 /* SERV Bit Fields */
3422 #define EWM_SERV_SERVICE_MASK 0xFFu
3423 #define EWM_SERV_SERVICE_SHIFT 0u
3424 #define EWM_SERV_SERVICE_WIDTH 8u
3425 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
3426 /* CMPL Bit Fields */
3427 #define EWM_CMPL_COMPAREL_MASK 0xFFu
3428 #define EWM_CMPL_COMPAREL_SHIFT 0u
3429 #define EWM_CMPL_COMPAREL_WIDTH 8u
3430 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
3431 /* CMPH Bit Fields */
3432 #define EWM_CMPH_COMPAREH_MASK 0xFFu
3433 #define EWM_CMPH_COMPAREH_SHIFT 0u
3434 #define EWM_CMPH_COMPAREH_WIDTH 8u
3435 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
3436 /* CLKPRESCALER Bit Fields */
3437 #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
3438 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0u
3439 #define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8u
3440 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
3441  /* end of group EWM_Register_Masks */
3445 
3446  /* end of group EWM_Peripheral_Access_Layer */
3450 
3451 
3452 /* ----------------------------------------------------------------------------
3453  -- FLEXIO Peripheral Access Layer
3454  ---------------------------------------------------------------------------- */
3455 
3463 #define FLEXIO_SHIFTCTL_COUNT 4u
3464 #define FLEXIO_SHIFTCFG_COUNT 4u
3465 #define FLEXIO_SHIFTBUF_COUNT 4u
3466 #define FLEXIO_SHIFTBUFBIS_COUNT 4u
3467 #define FLEXIO_SHIFTBUFBYS_COUNT 4u
3468 #define FLEXIO_SHIFTBUFBBS_COUNT 4u
3469 #define FLEXIO_TIMCTL_COUNT 4u
3470 #define FLEXIO_TIMCFG_COUNT 4u
3471 #define FLEXIO_TIMCMP_COUNT 4u
3472 
3474 typedef struct {
3475  __I uint32_t VERID;
3476  __I uint32_t PARAM;
3477  __IO uint32_t CTRL;
3478  __I uint32_t PIN;
3479  __IO uint32_t SHIFTSTAT;
3480  __IO uint32_t SHIFTERR;
3481  __IO uint32_t TIMSTAT;
3482  uint8_t RESERVED_0[4];
3483  __IO uint32_t SHIFTSIEN;
3484  __IO uint32_t SHIFTEIEN;
3485  __IO uint32_t TIMIEN;
3486  uint8_t RESERVED_1[4];
3487  __IO uint32_t SHIFTSDEN;
3488  uint8_t RESERVED_2[76];
3489  __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT];
3490  uint8_t RESERVED_3[112];
3491  __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT];
3492  uint8_t RESERVED_4[240];
3493  __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT];
3494  uint8_t RESERVED_5[112];
3495  __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT];
3496  uint8_t RESERVED_6[112];
3497  __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT];
3498  uint8_t RESERVED_7[112];
3499  __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT];
3500  uint8_t RESERVED_8[112];
3501  __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT];
3502  uint8_t RESERVED_9[112];
3503  __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT];
3504  uint8_t RESERVED_10[112];
3505  __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT];
3507 
3509 #define FLEXIO_INSTANCE_COUNT (1u)
3510 
3511 
3512 /* FLEXIO - Peripheral instance base addresses */
3514 #define FLEXIO_BASE (0x4005A000u)
3515 
3516 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
3517 
3518 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
3519 
3520 #define FLEXIO_BASE_PTRS { FLEXIO }
3521 
3522 #define FLEXIO_IRQS_ARR_COUNT (1u)
3523 
3524 #define FLEXIO_IRQS_CH_COUNT (1u)
3525 
3526 #define FLEXIO_IRQS { FLEXIO_IRQn }
3527 
3528 /* ----------------------------------------------------------------------------
3529  -- FLEXIO Register Masks
3530  ---------------------------------------------------------------------------- */
3531 
3537 /* VERID Bit Fields */
3538 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
3539 #define FLEXIO_VERID_FEATURE_SHIFT 0u
3540 #define FLEXIO_VERID_FEATURE_WIDTH 16u
3541 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
3542 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
3543 #define FLEXIO_VERID_MINOR_SHIFT 16u
3544 #define FLEXIO_VERID_MINOR_WIDTH 8u
3545 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
3546 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
3547 #define FLEXIO_VERID_MAJOR_SHIFT 24u
3548 #define FLEXIO_VERID_MAJOR_WIDTH 8u
3549 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
3550 /* PARAM Bit Fields */
3551 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
3552 #define FLEXIO_PARAM_SHIFTER_SHIFT 0u
3553 #define FLEXIO_PARAM_SHIFTER_WIDTH 8u
3554 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
3555 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
3556 #define FLEXIO_PARAM_TIMER_SHIFT 8u
3557 #define FLEXIO_PARAM_TIMER_WIDTH 8u
3558 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
3559 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
3560 #define FLEXIO_PARAM_PIN_SHIFT 16u
3561 #define FLEXIO_PARAM_PIN_WIDTH 8u
3562 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
3563 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
3564 #define FLEXIO_PARAM_TRIGGER_SHIFT 24u
3565 #define FLEXIO_PARAM_TRIGGER_WIDTH 8u
3566 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
3567 /* CTRL Bit Fields */
3568 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
3569 #define FLEXIO_CTRL_FLEXEN_SHIFT 0u
3570 #define FLEXIO_CTRL_FLEXEN_WIDTH 1u
3571 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
3572 #define FLEXIO_CTRL_SWRST_MASK 0x2u
3573 #define FLEXIO_CTRL_SWRST_SHIFT 1u
3574 #define FLEXIO_CTRL_SWRST_WIDTH 1u
3575 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
3576 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
3577 #define FLEXIO_CTRL_FASTACC_SHIFT 2u
3578 #define FLEXIO_CTRL_FASTACC_WIDTH 1u
3579 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
3580 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
3581 #define FLEXIO_CTRL_DBGE_SHIFT 30u
3582 #define FLEXIO_CTRL_DBGE_WIDTH 1u
3583 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
3584 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
3585 #define FLEXIO_CTRL_DOZEN_SHIFT 31u
3586 #define FLEXIO_CTRL_DOZEN_WIDTH 1u
3587 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
3588 /* PIN Bit Fields */
3589 #define FLEXIO_PIN_PDI_MASK 0xFFu
3590 #define FLEXIO_PIN_PDI_SHIFT 0u
3591 #define FLEXIO_PIN_PDI_WIDTH 8u
3592 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
3593 /* SHIFTSTAT Bit Fields */
3594 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
3595 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0u
3596 #define FLEXIO_SHIFTSTAT_SSF_WIDTH 4u
3597 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
3598 /* SHIFTERR Bit Fields */
3599 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
3600 #define FLEXIO_SHIFTERR_SEF_SHIFT 0u
3601 #define FLEXIO_SHIFTERR_SEF_WIDTH 4u
3602 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
3603 /* TIMSTAT Bit Fields */
3604 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
3605 #define FLEXIO_TIMSTAT_TSF_SHIFT 0u
3606 #define FLEXIO_TIMSTAT_TSF_WIDTH 4u
3607 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
3608 /* SHIFTSIEN Bit Fields */
3609 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
3610 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0u
3611 #define FLEXIO_SHIFTSIEN_SSIE_WIDTH 4u
3612 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
3613 /* SHIFTEIEN Bit Fields */
3614 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
3615 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0u
3616 #define FLEXIO_SHIFTEIEN_SEIE_WIDTH 4u
3617 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
3618 /* TIMIEN Bit Fields */
3619 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
3620 #define FLEXIO_TIMIEN_TEIE_SHIFT 0u
3621 #define FLEXIO_TIMIEN_TEIE_WIDTH 4u
3622 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
3623 /* SHIFTSDEN Bit Fields */
3624 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
3625 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0u
3626 #define FLEXIO_SHIFTSDEN_SSDE_WIDTH 4u
3627 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
3628 /* SHIFTCTL Bit Fields */
3629 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
3630 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0u
3631 #define FLEXIO_SHIFTCTL_SMOD_WIDTH 3u
3632 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
3633 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
3634 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7u
3635 #define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1u
3636 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
3637 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
3638 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8u
3639 #define FLEXIO_SHIFTCTL_PINSEL_WIDTH 3u
3640 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
3641 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
3642 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16u
3643 #define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2u
3644 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
3645 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
3646 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23u
3647 #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1u
3648 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
3649 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
3650 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24u
3651 #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 2u
3652 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
3653 /* SHIFTCFG Bit Fields */
3654 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
3655 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0u
3656 #define FLEXIO_SHIFTCFG_SSTART_WIDTH 2u
3657 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
3658 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
3659 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4u
3660 #define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2u
3661 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
3662 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
3663 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8u
3664 #define FLEXIO_SHIFTCFG_INSRC_WIDTH 1u
3665 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
3666 /* SHIFTBUF Bit Fields */
3667 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
3668 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0u
3669 #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32u
3670 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
3671 /* SHIFTBUFBIS Bit Fields */
3672 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
3673 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0u
3674 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32u
3675 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
3676 /* SHIFTBUFBYS Bit Fields */
3677 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
3678 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0u
3679 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32u
3680 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
3681 /* SHIFTBUFBBS Bit Fields */
3682 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
3683 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0u
3684 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32u
3685 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
3686 /* TIMCTL Bit Fields */
3687 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
3688 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0u
3689 #define FLEXIO_TIMCTL_TIMOD_WIDTH 2u
3690 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
3691 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
3692 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7u
3693 #define FLEXIO_TIMCTL_PINPOL_WIDTH 1u
3694 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
3695 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
3696 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8u
3697 #define FLEXIO_TIMCTL_PINSEL_WIDTH 3u
3698 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
3699 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
3700 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16u
3701 #define FLEXIO_TIMCTL_PINCFG_WIDTH 2u
3702 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
3703 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
3704 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22u
3705 #define FLEXIO_TIMCTL_TRGSRC_WIDTH 1u
3706 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
3707 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
3708 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23u
3709 #define FLEXIO_TIMCTL_TRGPOL_WIDTH 1u
3710 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
3711 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
3712 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24u
3713 #define FLEXIO_TIMCTL_TRGSEL_WIDTH 4u
3714 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
3715 /* TIMCFG Bit Fields */
3716 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
3717 #define FLEXIO_TIMCFG_TSTART_SHIFT 1u
3718 #define FLEXIO_TIMCFG_TSTART_WIDTH 1u
3719 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
3720 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
3721 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4u
3722 #define FLEXIO_TIMCFG_TSTOP_WIDTH 2u
3723 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
3724 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
3725 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8u
3726 #define FLEXIO_TIMCFG_TIMENA_WIDTH 3u
3727 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
3728 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
3729 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12u
3730 #define FLEXIO_TIMCFG_TIMDIS_WIDTH 3u
3731 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
3732 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
3733 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16u
3734 #define FLEXIO_TIMCFG_TIMRST_WIDTH 3u
3735 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
3736 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
3737 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20u
3738 #define FLEXIO_TIMCFG_TIMDEC_WIDTH 2u
3739 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
3740 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
3741 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24u
3742 #define FLEXIO_TIMCFG_TIMOUT_WIDTH 2u
3743 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
3744 /* TIMCMP Bit Fields */
3745 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
3746 #define FLEXIO_TIMCMP_CMP_SHIFT 0u
3747 #define FLEXIO_TIMCMP_CMP_WIDTH 16u
3748 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
3749  /* end of group FLEXIO_Register_Masks */
3753 
3754  /* end of group FLEXIO_Peripheral_Access_Layer */
3758 
3759 
3760 /* ----------------------------------------------------------------------------
3761  -- FTFC Peripheral Access Layer
3762  ---------------------------------------------------------------------------- */
3763 
3771 #define FTFC_FCCOB_COUNT 12u
3772 #define FTFC_FPROT_COUNT 4u
3773 
3775 typedef struct {
3776  __IO uint8_t FSTAT;
3777  __IO uint8_t FCNFG;
3778  __I uint8_t FSEC;
3779  __I uint8_t FOPT;
3780  __IO uint8_t FCCOB[FTFC_FCCOB_COUNT];
3781  __IO uint8_t FPROT[FTFC_FPROT_COUNT];
3782  uint8_t RESERVED_0[2];
3783  __IO uint8_t FEPROT;
3784  __IO uint8_t FDPROT;
3785  uint8_t RESERVED_1[20];
3786  __I uint8_t FCSESTAT;
3787  uint8_t RESERVED_2[1];
3788  __IO uint8_t FERSTAT;
3789  __IO uint8_t FERCNFG;
3791 
3793 #define FTFC_INSTANCE_COUNT (1u)
3794 
3795 
3796 /* FTFC - Peripheral instance base addresses */
3798 #define FTFC_BASE (0x40020000u)
3799 
3800 #define FTFC ((FTFC_Type *)FTFC_BASE)
3801 
3802 #define FTFC_BASE_ADDRS { FTFC_BASE }
3803 
3804 #define FTFC_BASE_PTRS { FTFC }
3805 
3806 #define FTFC_IRQS_ARR_COUNT (2u)
3807 
3808 #define FTFC_COMMAND_COMPLETE_IRQS_CH_COUNT (1u)
3809 
3810 #define FTFC_READ_COLLISION_IRQS_CH_COUNT (1u)
3811 
3812 #define FTFC_COMMAND_COMPLETE_IRQS { FTFC_IRQn }
3813 #define FTFC_READ_COLLISION_IRQS { Read_Collision_IRQn }
3814 
3815 /* ----------------------------------------------------------------------------
3816  -- FTFC Register Masks
3817  ---------------------------------------------------------------------------- */
3818 
3824 /* FSTAT Bit Fields */
3825 #define FTFC_FSTAT_MGSTAT0_MASK 0x1u
3826 #define FTFC_FSTAT_MGSTAT0_SHIFT 0u
3827 #define FTFC_FSTAT_MGSTAT0_WIDTH 1u
3828 #define FTFC_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_MGSTAT0_SHIFT))&FTFC_FSTAT_MGSTAT0_MASK)
3829 #define FTFC_FSTAT_FPVIOL_MASK 0x10u
3830 #define FTFC_FSTAT_FPVIOL_SHIFT 4u
3831 #define FTFC_FSTAT_FPVIOL_WIDTH 1u
3832 #define FTFC_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_FPVIOL_SHIFT))&FTFC_FSTAT_FPVIOL_MASK)
3833 #define FTFC_FSTAT_ACCERR_MASK 0x20u
3834 #define FTFC_FSTAT_ACCERR_SHIFT 5u
3835 #define FTFC_FSTAT_ACCERR_WIDTH 1u
3836 #define FTFC_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_ACCERR_SHIFT))&FTFC_FSTAT_ACCERR_MASK)
3837 #define FTFC_FSTAT_RDCOLERR_MASK 0x40u
3838 #define FTFC_FSTAT_RDCOLERR_SHIFT 6u
3839 #define FTFC_FSTAT_RDCOLERR_WIDTH 1u
3840 #define FTFC_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_RDCOLERR_SHIFT))&FTFC_FSTAT_RDCOLERR_MASK)
3841 #define FTFC_FSTAT_CCIF_MASK 0x80u
3842 #define FTFC_FSTAT_CCIF_SHIFT 7u
3843 #define FTFC_FSTAT_CCIF_WIDTH 1u
3844 #define FTFC_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_CCIF_SHIFT))&FTFC_FSTAT_CCIF_MASK)
3845 /* FCNFG Bit Fields */
3846 #define FTFC_FCNFG_EEERDY_MASK 0x1u
3847 #define FTFC_FCNFG_EEERDY_SHIFT 0u
3848 #define FTFC_FCNFG_EEERDY_WIDTH 1u
3849 #define FTFC_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_EEERDY_SHIFT))&FTFC_FCNFG_EEERDY_MASK)
3850 #define FTFC_FCNFG_RAMRDY_MASK 0x2u
3851 #define FTFC_FCNFG_RAMRDY_SHIFT 1u
3852 #define FTFC_FCNFG_RAMRDY_WIDTH 1u
3853 #define FTFC_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RAMRDY_SHIFT))&FTFC_FCNFG_RAMRDY_MASK)
3854 #define FTFC_FCNFG_ERSSUSP_MASK 0x10u
3855 #define FTFC_FCNFG_ERSSUSP_SHIFT 4u
3856 #define FTFC_FCNFG_ERSSUSP_WIDTH 1u
3857 #define FTFC_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSSUSP_SHIFT))&FTFC_FCNFG_ERSSUSP_MASK)
3858 #define FTFC_FCNFG_ERSAREQ_MASK 0x20u
3859 #define FTFC_FCNFG_ERSAREQ_SHIFT 5u
3860 #define FTFC_FCNFG_ERSAREQ_WIDTH 1u
3861 #define FTFC_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSAREQ_SHIFT))&FTFC_FCNFG_ERSAREQ_MASK)
3862 #define FTFC_FCNFG_RDCOLLIE_MASK 0x40u
3863 #define FTFC_FCNFG_RDCOLLIE_SHIFT 6u
3864 #define FTFC_FCNFG_RDCOLLIE_WIDTH 1u
3865 #define FTFC_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RDCOLLIE_SHIFT))&FTFC_FCNFG_RDCOLLIE_MASK)
3866 #define FTFC_FCNFG_CCIE_MASK 0x80u
3867 #define FTFC_FCNFG_CCIE_SHIFT 7u
3868 #define FTFC_FCNFG_CCIE_WIDTH 1u
3869 #define FTFC_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_CCIE_SHIFT))&FTFC_FCNFG_CCIE_MASK)
3870 /* FSEC Bit Fields */
3871 #define FTFC_FSEC_SEC_MASK 0x3u
3872 #define FTFC_FSEC_SEC_SHIFT 0u
3873 #define FTFC_FSEC_SEC_WIDTH 2u
3874 #define FTFC_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_SEC_SHIFT))&FTFC_FSEC_SEC_MASK)
3875 #define FTFC_FSEC_FSLACC_MASK 0xCu
3876 #define FTFC_FSEC_FSLACC_SHIFT 2u
3877 #define FTFC_FSEC_FSLACC_WIDTH 2u
3878 #define FTFC_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_FSLACC_SHIFT))&FTFC_FSEC_FSLACC_MASK)
3879 #define FTFC_FSEC_MEEN_MASK 0x30u
3880 #define FTFC_FSEC_MEEN_SHIFT 4u
3881 #define FTFC_FSEC_MEEN_WIDTH 2u
3882 #define FTFC_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_MEEN_SHIFT))&FTFC_FSEC_MEEN_MASK)
3883 #define FTFC_FSEC_KEYEN_MASK 0xC0u
3884 #define FTFC_FSEC_KEYEN_SHIFT 6u
3885 #define FTFC_FSEC_KEYEN_WIDTH 2u
3886 #define FTFC_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_KEYEN_SHIFT))&FTFC_FSEC_KEYEN_MASK)
3887 /* FOPT Bit Fields */
3888 #define FTFC_FOPT_OPT_MASK 0xFFu
3889 #define FTFC_FOPT_OPT_SHIFT 0u
3890 #define FTFC_FOPT_OPT_WIDTH 8u
3891 #define FTFC_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FOPT_OPT_SHIFT))&FTFC_FOPT_OPT_MASK)
3892 /* FCCOB Bit Fields */
3893 #define FTFC_FCCOB_CCOBn_MASK 0xFFu
3894 #define FTFC_FCCOB_CCOBn_SHIFT 0u
3895 #define FTFC_FCCOB_CCOBn_WIDTH 8u
3896 #define FTFC_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCCOB_CCOBn_SHIFT))&FTFC_FCCOB_CCOBn_MASK)
3897 /* FPROT Bit Fields */
3898 #define FTFC_FPROT_PROT_MASK 0xFFu
3899 #define FTFC_FPROT_PROT_SHIFT 0u
3900 #define FTFC_FPROT_PROT_WIDTH 8u
3901 #define FTFC_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FPROT_PROT_SHIFT))&FTFC_FPROT_PROT_MASK)
3902 /* FEPROT Bit Fields */
3903 #define FTFC_FEPROT_EPROT_MASK 0xFFu
3904 #define FTFC_FEPROT_EPROT_SHIFT 0u
3905 #define FTFC_FEPROT_EPROT_WIDTH 8u
3906 #define FTFC_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FEPROT_EPROT_SHIFT))&FTFC_FEPROT_EPROT_MASK)
3907 /* FDPROT Bit Fields */
3908 #define FTFC_FDPROT_DPROT_MASK 0xFFu
3909 #define FTFC_FDPROT_DPROT_SHIFT 0u
3910 #define FTFC_FDPROT_DPROT_WIDTH 8u
3911 #define FTFC_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FDPROT_DPROT_SHIFT))&FTFC_FDPROT_DPROT_MASK)
3912 /* FCSESTAT Bit Fields */
3913 #define FTFC_FCSESTAT_BSY_MASK 0x1u
3914 #define FTFC_FCSESTAT_BSY_SHIFT 0u
3915 #define FTFC_FCSESTAT_BSY_WIDTH 1u
3916 #define FTFC_FCSESTAT_BSY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BSY_SHIFT))&FTFC_FCSESTAT_BSY_MASK)
3917 #define FTFC_FCSESTAT_SB_MASK 0x2u
3918 #define FTFC_FCSESTAT_SB_SHIFT 1u
3919 #define FTFC_FCSESTAT_SB_WIDTH 1u
3920 #define FTFC_FCSESTAT_SB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_SB_SHIFT))&FTFC_FCSESTAT_SB_MASK)
3921 #define FTFC_FCSESTAT_BIN_MASK 0x4u
3922 #define FTFC_FCSESTAT_BIN_SHIFT 2u
3923 #define FTFC_FCSESTAT_BIN_WIDTH 1u
3924 #define FTFC_FCSESTAT_BIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BIN_SHIFT))&FTFC_FCSESTAT_BIN_MASK)
3925 #define FTFC_FCSESTAT_BFN_MASK 0x8u
3926 #define FTFC_FCSESTAT_BFN_SHIFT 3u
3927 #define FTFC_FCSESTAT_BFN_WIDTH 1u
3928 #define FTFC_FCSESTAT_BFN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BFN_SHIFT))&FTFC_FCSESTAT_BFN_MASK)
3929 #define FTFC_FCSESTAT_BOK_MASK 0x10u
3930 #define FTFC_FCSESTAT_BOK_SHIFT 4u
3931 #define FTFC_FCSESTAT_BOK_WIDTH 1u
3932 #define FTFC_FCSESTAT_BOK(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BOK_SHIFT))&FTFC_FCSESTAT_BOK_MASK)
3933 #define FTFC_FCSESTAT_RIN_MASK 0x20u
3934 #define FTFC_FCSESTAT_RIN_SHIFT 5u
3935 #define FTFC_FCSESTAT_RIN_WIDTH 1u
3936 #define FTFC_FCSESTAT_RIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_RIN_SHIFT))&FTFC_FCSESTAT_RIN_MASK)
3937 #define FTFC_FCSESTAT_EDB_MASK 0x40u
3938 #define FTFC_FCSESTAT_EDB_SHIFT 6u
3939 #define FTFC_FCSESTAT_EDB_WIDTH 1u
3940 #define FTFC_FCSESTAT_EDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_EDB_SHIFT))&FTFC_FCSESTAT_EDB_MASK)
3941 #define FTFC_FCSESTAT_IDB_MASK 0x80u
3942 #define FTFC_FCSESTAT_IDB_SHIFT 7u
3943 #define FTFC_FCSESTAT_IDB_WIDTH 1u
3944 #define FTFC_FCSESTAT_IDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_IDB_SHIFT))&FTFC_FCSESTAT_IDB_MASK)
3945 /* FERSTAT Bit Fields */
3946 #define FTFC_FERSTAT_DFDIF_MASK 0x2u
3947 #define FTFC_FERSTAT_DFDIF_SHIFT 1u
3948 #define FTFC_FERSTAT_DFDIF_WIDTH 1u
3949 #define FTFC_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERSTAT_DFDIF_SHIFT))&FTFC_FERSTAT_DFDIF_MASK)
3950 /* FERCNFG Bit Fields */
3951 #define FTFC_FERCNFG_DFDIE_MASK 0x2u
3952 #define FTFC_FERCNFG_DFDIE_SHIFT 1u
3953 #define FTFC_FERCNFG_DFDIE_WIDTH 1u
3954 #define FTFC_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_DFDIE_SHIFT))&FTFC_FERCNFG_DFDIE_MASK)
3955 #define FTFC_FERCNFG_FDFD_MASK 0x20u
3956 #define FTFC_FERCNFG_FDFD_SHIFT 5u
3957 #define FTFC_FERCNFG_FDFD_WIDTH 1u
3958 #define FTFC_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_FDFD_SHIFT))&FTFC_FERCNFG_FDFD_MASK)
3959  /* end of group FTFC_Register_Masks */
3963 
3964  /* end of group FTFC_Peripheral_Access_Layer */
3968 
3969 
3970 /* ----------------------------------------------------------------------------
3971  -- FTM Peripheral Access Layer
3972  ---------------------------------------------------------------------------- */
3973 
3981 #define FTM_CONTROLS_COUNT 8u
3982 
3984 typedef struct {
3985  __IO uint32_t SC;
3986  __IO uint32_t CNT;
3987  __IO uint32_t MOD;
3988  struct { /* offset: 0xC, array step: 0x8 */
3989  __IO uint32_t CnSC;
3990  __IO uint32_t CnV;
3991  } CONTROLS[FTM_CONTROLS_COUNT];
3992  __IO uint32_t CNTIN;
3993  __IO uint32_t STATUS;
3994  __IO uint32_t MODE;
3995  __IO uint32_t SYNC;
3996  __IO uint32_t OUTINIT;
3997  __IO uint32_t OUTMASK;
3998  __IO uint32_t COMBINE;
3999  __IO uint32_t DEADTIME;
4000  __IO uint32_t EXTTRIG;
4001  __IO uint32_t POL;
4002  __IO uint32_t FMS;
4003  __IO uint32_t FILTER;
4004  __IO uint32_t FLTCTRL;
4005  __IO uint32_t QDCTRL;
4006  __IO uint32_t CONF;
4007  __IO uint32_t FLTPOL;
4008  __IO uint32_t SYNCONF;
4009  __IO uint32_t INVCTRL;
4010  __IO uint32_t SWOCTRL;
4011  __IO uint32_t PWMLOAD;
4012  __IO uint32_t HCR;
4013  __IO uint32_t PAIR0DEADTIME;
4014  uint8_t RESERVED_0[4];
4015  __IO uint32_t PAIR1DEADTIME;
4016  uint8_t RESERVED_1[4];
4017  __IO uint32_t PAIR2DEADTIME;
4018  uint8_t RESERVED_2[4];
4019  __IO uint32_t PAIR3DEADTIME;
4021 
4023 #define FTM_INSTANCE_COUNT (4u)
4024 
4025 
4026 /* FTM - Peripheral instance base addresses */
4028 #define FTM0_BASE (0x40038000u)
4029 
4030 #define FTM0 ((FTM_Type *)FTM0_BASE)
4031 
4032 #define FTM1_BASE (0x40039000u)
4033 
4034 #define FTM1 ((FTM_Type *)FTM1_BASE)
4035 
4036 #define FTM2_BASE (0x4003A000u)
4037 
4038 #define FTM2 ((FTM_Type *)FTM2_BASE)
4039 
4040 #define FTM3_BASE (0x40026000u)
4041 
4042 #define FTM3 ((FTM_Type *)FTM3_BASE)
4043 
4044 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
4045 
4046 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
4047 
4048 #define FTM_IRQS_ARR_COUNT (4u)
4049 
4050 #define FTM_IRQS_CH_COUNT (8u)
4051 
4052 #define FTM_Fault_IRQS_CH_COUNT (1u)
4053 
4054 #define FTM_Overflow_IRQS_CH_COUNT (1u)
4055 
4056 #define FTM_Reload_IRQS_CH_COUNT (1u)
4057 
4058 #define FTM_IRQS { { FTM0_Ch0_Ch1_IRQn, FTM0_Ch0_Ch1_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch6_Ch7_IRQn, FTM0_Ch6_Ch7_IRQn }, \
4059  { FTM1_Ch0_Ch1_IRQn, FTM1_Ch0_Ch1_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch6_Ch7_IRQn, FTM1_Ch6_Ch7_IRQn }, \
4060  { FTM2_Ch0_Ch1_IRQn, FTM2_Ch0_Ch1_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch6_Ch7_IRQn, FTM2_Ch6_Ch7_IRQn }, \
4061  { FTM3_Ch0_Ch1_IRQn, FTM3_Ch0_Ch1_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch6_Ch7_IRQn, FTM3_Ch6_Ch7_IRQn } }
4062 #define FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn, FTM2_Fault_IRQn, FTM3_Fault_IRQn }
4063 #define FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn }
4064 #define FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn }
4065 
4066 /* ----------------------------------------------------------------------------
4067  -- FTM Register Masks
4068  ---------------------------------------------------------------------------- */
4069 
4075 /* SC Bit Fields */
4076 #define FTM_SC_PS_MASK 0x7u
4077 #define FTM_SC_PS_SHIFT 0u
4078 #define FTM_SC_PS_WIDTH 3u
4079 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
4080 #define FTM_SC_CLKS_MASK 0x18u
4081 #define FTM_SC_CLKS_SHIFT 3u
4082 #define FTM_SC_CLKS_WIDTH 2u
4083 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
4084 #define FTM_SC_CPWMS_MASK 0x20u
4085 #define FTM_SC_CPWMS_SHIFT 5u
4086 #define FTM_SC_CPWMS_WIDTH 1u
4087 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
4088 #define FTM_SC_RIE_MASK 0x40u
4089 #define FTM_SC_RIE_SHIFT 6u
4090 #define FTM_SC_RIE_WIDTH 1u
4091 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RIE_SHIFT))&FTM_SC_RIE_MASK)
4092 #define FTM_SC_RF_MASK 0x80u
4093 #define FTM_SC_RF_SHIFT 7u
4094 #define FTM_SC_RF_WIDTH 1u
4095 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RF_SHIFT))&FTM_SC_RF_MASK)
4096 #define FTM_SC_TOIE_MASK 0x100u
4097 #define FTM_SC_TOIE_SHIFT 8u
4098 #define FTM_SC_TOIE_WIDTH 1u
4099 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
4100 #define FTM_SC_TOF_MASK 0x200u
4101 #define FTM_SC_TOF_SHIFT 9u
4102 #define FTM_SC_TOF_WIDTH 1u
4103 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
4104 #define FTM_SC_PWMEN0_MASK 0x10000u
4105 #define FTM_SC_PWMEN0_SHIFT 16u
4106 #define FTM_SC_PWMEN0_WIDTH 1u
4107 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN0_SHIFT))&FTM_SC_PWMEN0_MASK)
4108 #define FTM_SC_PWMEN1_MASK 0x20000u
4109 #define FTM_SC_PWMEN1_SHIFT 17u
4110 #define FTM_SC_PWMEN1_WIDTH 1u
4111 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN1_SHIFT))&FTM_SC_PWMEN1_MASK)
4112 #define FTM_SC_PWMEN2_MASK 0x40000u
4113 #define FTM_SC_PWMEN2_SHIFT 18u
4114 #define FTM_SC_PWMEN2_WIDTH 1u
4115 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN2_SHIFT))&FTM_SC_PWMEN2_MASK)
4116 #define FTM_SC_PWMEN3_MASK 0x80000u
4117 #define FTM_SC_PWMEN3_SHIFT 19u
4118 #define FTM_SC_PWMEN3_WIDTH 1u
4119 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN3_SHIFT))&FTM_SC_PWMEN3_MASK)
4120 #define FTM_SC_PWMEN4_MASK 0x100000u
4121 #define FTM_SC_PWMEN4_SHIFT 20u
4122 #define FTM_SC_PWMEN4_WIDTH 1u
4123 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN4_SHIFT))&FTM_SC_PWMEN4_MASK)
4124 #define FTM_SC_PWMEN5_MASK 0x200000u
4125 #define FTM_SC_PWMEN5_SHIFT 21u
4126 #define FTM_SC_PWMEN5_WIDTH 1u
4127 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN5_SHIFT))&FTM_SC_PWMEN5_MASK)
4128 #define FTM_SC_PWMEN6_MASK 0x400000u
4129 #define FTM_SC_PWMEN6_SHIFT 22u
4130 #define FTM_SC_PWMEN6_WIDTH 1u
4131 #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN6_SHIFT))&FTM_SC_PWMEN6_MASK)
4132 #define FTM_SC_PWMEN7_MASK 0x800000u
4133 #define FTM_SC_PWMEN7_SHIFT 23u
4134 #define FTM_SC_PWMEN7_WIDTH 1u
4135 #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN7_SHIFT))&FTM_SC_PWMEN7_MASK)
4136 #define FTM_SC_FLTPS_MASK 0xF000000u
4137 #define FTM_SC_FLTPS_SHIFT 24u
4138 #define FTM_SC_FLTPS_WIDTH 4u
4139 #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_FLTPS_SHIFT))&FTM_SC_FLTPS_MASK)
4140 /* CNT Bit Fields */
4141 #define FTM_CNT_COUNT_MASK 0xFFFFu
4142 #define FTM_CNT_COUNT_SHIFT 0u
4143 #define FTM_CNT_COUNT_WIDTH 16u
4144 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
4145 /* MOD Bit Fields */
4146 #define FTM_MOD_MOD_MASK 0xFFFFu
4147 #define FTM_MOD_MOD_SHIFT 0u
4148 #define FTM_MOD_MOD_WIDTH 16u
4149 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
4150 /* CnSC Bit Fields */
4151 #define FTM_CnSC_DMA_MASK 0x1u
4152 #define FTM_CnSC_DMA_SHIFT 0u
4153 #define FTM_CnSC_DMA_WIDTH 1u
4154 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
4155 #define FTM_CnSC_ICRST_MASK 0x2u
4156 #define FTM_CnSC_ICRST_SHIFT 1u
4157 #define FTM_CnSC_ICRST_WIDTH 1u
4158 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
4159 #define FTM_CnSC_ELSA_MASK 0x4u
4160 #define FTM_CnSC_ELSA_SHIFT 2u
4161 #define FTM_CnSC_ELSA_WIDTH 1u
4162 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
4163 #define FTM_CnSC_ELSB_MASK 0x8u
4164 #define FTM_CnSC_ELSB_SHIFT 3u
4165 #define FTM_CnSC_ELSB_WIDTH 1u
4166 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
4167 #define FTM_CnSC_MSA_MASK 0x10u
4168 #define FTM_CnSC_MSA_SHIFT 4u
4169 #define FTM_CnSC_MSA_WIDTH 1u
4170 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
4171 #define FTM_CnSC_MSB_MASK 0x20u
4172 #define FTM_CnSC_MSB_SHIFT 5u
4173 #define FTM_CnSC_MSB_WIDTH 1u
4174 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
4175 #define FTM_CnSC_CHIE_MASK 0x40u
4176 #define FTM_CnSC_CHIE_SHIFT 6u
4177 #define FTM_CnSC_CHIE_WIDTH 1u
4178 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
4179 #define FTM_CnSC_CHF_MASK 0x80u
4180 #define FTM_CnSC_CHF_SHIFT 7u
4181 #define FTM_CnSC_CHF_WIDTH 1u
4182 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
4183 #define FTM_CnSC_TRIGMODE_MASK 0x100u
4184 #define FTM_CnSC_TRIGMODE_SHIFT 8u
4185 #define FTM_CnSC_TRIGMODE_WIDTH 1u
4186 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_TRIGMODE_SHIFT))&FTM_CnSC_TRIGMODE_MASK)
4187 #define FTM_CnSC_CHIS_MASK 0x200u
4188 #define FTM_CnSC_CHIS_SHIFT 9u
4189 #define FTM_CnSC_CHIS_WIDTH 1u
4190 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIS_SHIFT))&FTM_CnSC_CHIS_MASK)
4191 #define FTM_CnSC_CHOV_MASK 0x400u
4192 #define FTM_CnSC_CHOV_SHIFT 10u
4193 #define FTM_CnSC_CHOV_WIDTH 1u
4194 #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHOV_SHIFT))&FTM_CnSC_CHOV_MASK)
4195 /* CnV Bit Fields */
4196 #define FTM_CnV_VAL_MASK 0xFFFFu
4197 #define FTM_CnV_VAL_SHIFT 0u
4198 #define FTM_CnV_VAL_WIDTH 16u
4199 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
4200 /* CNTIN Bit Fields */
4201 #define FTM_CNTIN_INIT_MASK 0xFFFFu
4202 #define FTM_CNTIN_INIT_SHIFT 0u
4203 #define FTM_CNTIN_INIT_WIDTH 16u
4204 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
4205 /* STATUS Bit Fields */
4206 #define FTM_STATUS_CH0F_MASK 0x1u
4207 #define FTM_STATUS_CH0F_SHIFT 0u
4208 #define FTM_STATUS_CH0F_WIDTH 1u
4209 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
4210 #define FTM_STATUS_CH1F_MASK 0x2u
4211 #define FTM_STATUS_CH1F_SHIFT 1u
4212 #define FTM_STATUS_CH1F_WIDTH 1u
4213 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
4214 #define FTM_STATUS_CH2F_MASK 0x4u
4215 #define FTM_STATUS_CH2F_SHIFT 2u
4216 #define FTM_STATUS_CH2F_WIDTH 1u
4217 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
4218 #define FTM_STATUS_CH3F_MASK 0x8u
4219 #define FTM_STATUS_CH3F_SHIFT 3u
4220 #define FTM_STATUS_CH3F_WIDTH 1u
4221 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
4222 #define FTM_STATUS_CH4F_MASK 0x10u
4223 #define FTM_STATUS_CH4F_SHIFT 4u
4224 #define FTM_STATUS_CH4F_WIDTH 1u
4225 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
4226 #define FTM_STATUS_CH5F_MASK 0x20u
4227 #define FTM_STATUS_CH5F_SHIFT 5u
4228 #define FTM_STATUS_CH5F_WIDTH 1u
4229 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
4230 #define FTM_STATUS_CH6F_MASK 0x40u
4231 #define FTM_STATUS_CH6F_SHIFT 6u
4232 #define FTM_STATUS_CH6F_WIDTH 1u
4233 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
4234 #define FTM_STATUS_CH7F_MASK 0x80u
4235 #define FTM_STATUS_CH7F_SHIFT 7u
4236 #define FTM_STATUS_CH7F_WIDTH 1u
4237 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
4238 /* MODE Bit Fields */
4239 #define FTM_MODE_FTMEN_MASK 0x1u
4240 #define FTM_MODE_FTMEN_SHIFT 0u
4241 #define FTM_MODE_FTMEN_WIDTH 1u
4242 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
4243 #define FTM_MODE_INIT_MASK 0x2u
4244 #define FTM_MODE_INIT_SHIFT 1u
4245 #define FTM_MODE_INIT_WIDTH 1u
4246 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
4247 #define FTM_MODE_WPDIS_MASK 0x4u
4248 #define FTM_MODE_WPDIS_SHIFT 2u
4249 #define FTM_MODE_WPDIS_WIDTH 1u
4250 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
4251 #define FTM_MODE_PWMSYNC_MASK 0x8u
4252 #define FTM_MODE_PWMSYNC_SHIFT 3u
4253 #define FTM_MODE_PWMSYNC_WIDTH 1u
4254 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
4255 #define FTM_MODE_CAPTEST_MASK 0x10u
4256 #define FTM_MODE_CAPTEST_SHIFT 4u
4257 #define FTM_MODE_CAPTEST_WIDTH 1u
4258 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
4259 #define FTM_MODE_FAULTM_MASK 0x60u
4260 #define FTM_MODE_FAULTM_SHIFT 5u
4261 #define FTM_MODE_FAULTM_WIDTH 2u
4262 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
4263 #define FTM_MODE_FAULTIE_MASK 0x80u
4264 #define FTM_MODE_FAULTIE_SHIFT 7u
4265 #define FTM_MODE_FAULTIE_WIDTH 1u
4266 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
4267 /* SYNC Bit Fields */
4268 #define FTM_SYNC_CNTMIN_MASK 0x1u
4269 #define FTM_SYNC_CNTMIN_SHIFT 0u
4270 #define FTM_SYNC_CNTMIN_WIDTH 1u
4271 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
4272 #define FTM_SYNC_CNTMAX_MASK 0x2u
4273 #define FTM_SYNC_CNTMAX_SHIFT 1u
4274 #define FTM_SYNC_CNTMAX_WIDTH 1u
4275 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
4276 #define FTM_SYNC_REINIT_MASK 0x4u
4277 #define FTM_SYNC_REINIT_SHIFT 2u
4278 #define FTM_SYNC_REINIT_WIDTH 1u
4279 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
4280 #define FTM_SYNC_SYNCHOM_MASK 0x8u
4281 #define FTM_SYNC_SYNCHOM_SHIFT 3u
4282 #define FTM_SYNC_SYNCHOM_WIDTH 1u
4283 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
4284 #define FTM_SYNC_TRIG0_MASK 0x10u
4285 #define FTM_SYNC_TRIG0_SHIFT 4u
4286 #define FTM_SYNC_TRIG0_WIDTH 1u
4287 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
4288 #define FTM_SYNC_TRIG1_MASK 0x20u
4289 #define FTM_SYNC_TRIG1_SHIFT 5u
4290 #define FTM_SYNC_TRIG1_WIDTH 1u
4291 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
4292 #define FTM_SYNC_TRIG2_MASK 0x40u
4293 #define FTM_SYNC_TRIG2_SHIFT 6u
4294 #define FTM_SYNC_TRIG2_WIDTH 1u
4295 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
4296 #define FTM_SYNC_SWSYNC_MASK 0x80u
4297 #define FTM_SYNC_SWSYNC_SHIFT 7u
4298 #define FTM_SYNC_SWSYNC_WIDTH 1u
4299 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
4300 /* OUTINIT Bit Fields */
4301 #define FTM_OUTINIT_CH0OI_MASK 0x1u
4302 #define FTM_OUTINIT_CH0OI_SHIFT 0u
4303 #define FTM_OUTINIT_CH0OI_WIDTH 1u
4304 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
4305 #define FTM_OUTINIT_CH1OI_MASK 0x2u
4306 #define FTM_OUTINIT_CH1OI_SHIFT 1u
4307 #define FTM_OUTINIT_CH1OI_WIDTH 1u
4308 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
4309 #define FTM_OUTINIT_CH2OI_MASK 0x4u
4310 #define FTM_OUTINIT_CH2OI_SHIFT 2u
4311 #define FTM_OUTINIT_CH2OI_WIDTH 1u
4312 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
4313 #define FTM_OUTINIT_CH3OI_MASK 0x8u
4314 #define FTM_OUTINIT_CH3OI_SHIFT 3u
4315 #define FTM_OUTINIT_CH3OI_WIDTH 1u
4316 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
4317 #define FTM_OUTINIT_CH4OI_MASK 0x10u
4318 #define FTM_OUTINIT_CH4OI_SHIFT 4u
4319 #define FTM_OUTINIT_CH4OI_WIDTH 1u
4320 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
4321 #define FTM_OUTINIT_CH5OI_MASK 0x20u
4322 #define FTM_OUTINIT_CH5OI_SHIFT 5u
4323 #define FTM_OUTINIT_CH5OI_WIDTH 1u
4324 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
4325 #define FTM_OUTINIT_CH6OI_MASK 0x40u
4326 #define FTM_OUTINIT_CH6OI_SHIFT 6u
4327 #define FTM_OUTINIT_CH6OI_WIDTH 1u
4328 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
4329 #define FTM_OUTINIT_CH7OI_MASK 0x80u
4330 #define FTM_OUTINIT_CH7OI_SHIFT 7u
4331 #define FTM_OUTINIT_CH7OI_WIDTH 1u
4332 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
4333 /* OUTMASK Bit Fields */
4334 #define FTM_OUTMASK_CH0OM_MASK 0x1u
4335 #define FTM_OUTMASK_CH0OM_SHIFT 0u
4336 #define FTM_OUTMASK_CH0OM_WIDTH 1u
4337 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
4338 #define FTM_OUTMASK_CH1OM_MASK 0x2u
4339 #define FTM_OUTMASK_CH1OM_SHIFT 1u
4340 #define FTM_OUTMASK_CH1OM_WIDTH 1u
4341 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
4342 #define FTM_OUTMASK_CH2OM_MASK 0x4u
4343 #define FTM_OUTMASK_CH2OM_SHIFT 2u
4344 #define FTM_OUTMASK_CH2OM_WIDTH 1u
4345 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
4346 #define FTM_OUTMASK_CH3OM_MASK 0x8u
4347 #define FTM_OUTMASK_CH3OM_SHIFT 3u
4348 #define FTM_OUTMASK_CH3OM_WIDTH 1u
4349 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
4350 #define FTM_OUTMASK_CH4OM_MASK 0x10u
4351 #define FTM_OUTMASK_CH4OM_SHIFT 4u
4352 #define FTM_OUTMASK_CH4OM_WIDTH 1u
4353 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
4354 #define FTM_OUTMASK_CH5OM_MASK 0x20u
4355 #define FTM_OUTMASK_CH5OM_SHIFT 5u
4356 #define FTM_OUTMASK_CH5OM_WIDTH 1u
4357 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
4358 #define FTM_OUTMASK_CH6OM_MASK 0x40u
4359 #define FTM_OUTMASK_CH6OM_SHIFT 6u
4360 #define FTM_OUTMASK_CH6OM_WIDTH 1u
4361 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
4362 #define FTM_OUTMASK_CH7OM_MASK 0x80u
4363 #define FTM_OUTMASK_CH7OM_SHIFT 7u
4364 #define FTM_OUTMASK_CH7OM_WIDTH 1u
4365 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
4366 /* COMBINE Bit Fields */
4367 #define FTM_COMBINE_COMBINE0_MASK 0x1u
4368 #define FTM_COMBINE_COMBINE0_SHIFT 0u
4369 #define FTM_COMBINE_COMBINE0_WIDTH 1u
4370 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
4371 #define FTM_COMBINE_COMP0_MASK 0x2u
4372 #define FTM_COMBINE_COMP0_SHIFT 1u
4373 #define FTM_COMBINE_COMP0_WIDTH 1u
4374 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
4375 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
4376 #define FTM_COMBINE_DECAPEN0_SHIFT 2u
4377 #define FTM_COMBINE_DECAPEN0_WIDTH 1u
4378 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
4379 #define FTM_COMBINE_DECAP0_MASK 0x8u
4380 #define FTM_COMBINE_DECAP0_SHIFT 3u
4381 #define FTM_COMBINE_DECAP0_WIDTH 1u
4382 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
4383 #define FTM_COMBINE_DTEN0_MASK 0x10u
4384 #define FTM_COMBINE_DTEN0_SHIFT 4u
4385 #define FTM_COMBINE_DTEN0_WIDTH 1u
4386 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
4387 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
4388 #define FTM_COMBINE_SYNCEN0_SHIFT 5u
4389 #define FTM_COMBINE_SYNCEN0_WIDTH 1u
4390 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
4391 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
4392 #define FTM_COMBINE_FAULTEN0_SHIFT 6u
4393 #define FTM_COMBINE_FAULTEN0_WIDTH 1u
4394 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
4395 #define FTM_COMBINE_MCOMBINE0_MASK 0x80u
4396 #define FTM_COMBINE_MCOMBINE0_SHIFT 7u
4397 #define FTM_COMBINE_MCOMBINE0_WIDTH 1u
4398 #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE0_SHIFT))&FTM_COMBINE_MCOMBINE0_MASK)
4399 #define FTM_COMBINE_COMBINE1_MASK 0x100u
4400 #define FTM_COMBINE_COMBINE1_SHIFT 8u
4401 #define FTM_COMBINE_COMBINE1_WIDTH 1u
4402 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
4403 #define FTM_COMBINE_COMP1_MASK 0x200u
4404 #define FTM_COMBINE_COMP1_SHIFT 9u
4405 #define FTM_COMBINE_COMP1_WIDTH 1u
4406 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
4407 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
4408 #define FTM_COMBINE_DECAPEN1_SHIFT 10u
4409 #define FTM_COMBINE_DECAPEN1_WIDTH 1u
4410 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
4411 #define FTM_COMBINE_DECAP1_MASK 0x800u
4412 #define FTM_COMBINE_DECAP1_SHIFT 11u
4413 #define FTM_COMBINE_DECAP1_WIDTH 1u
4414 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
4415 #define FTM_COMBINE_DTEN1_MASK 0x1000u
4416 #define FTM_COMBINE_DTEN1_SHIFT 12u
4417 #define FTM_COMBINE_DTEN1_WIDTH 1u
4418 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
4419 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
4420 #define FTM_COMBINE_SYNCEN1_SHIFT 13u
4421 #define FTM_COMBINE_SYNCEN1_WIDTH 1u
4422 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
4423 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
4424 #define FTM_COMBINE_FAULTEN1_SHIFT 14u
4425 #define FTM_COMBINE_FAULTEN1_WIDTH 1u
4426 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
4427 #define FTM_COMBINE_MCOMBINE1_MASK 0x8000u
4428 #define FTM_COMBINE_MCOMBINE1_SHIFT 15u
4429 #define FTM_COMBINE_MCOMBINE1_WIDTH 1u
4430 #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE1_SHIFT))&FTM_COMBINE_MCOMBINE1_MASK)
4431 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
4432 #define FTM_COMBINE_COMBINE2_SHIFT 16u
4433 #define FTM_COMBINE_COMBINE2_WIDTH 1u
4434 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
4435 #define FTM_COMBINE_COMP2_MASK 0x20000u
4436 #define FTM_COMBINE_COMP2_SHIFT 17u
4437 #define FTM_COMBINE_COMP2_WIDTH 1u
4438 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
4439 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
4440 #define FTM_COMBINE_DECAPEN2_SHIFT 18u
4441 #define FTM_COMBINE_DECAPEN2_WIDTH 1u
4442 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
4443 #define FTM_COMBINE_DECAP2_MASK 0x80000u
4444 #define FTM_COMBINE_DECAP2_SHIFT 19u
4445 #define FTM_COMBINE_DECAP2_WIDTH 1u
4446 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
4447 #define FTM_COMBINE_DTEN2_MASK 0x100000u
4448 #define FTM_COMBINE_DTEN2_SHIFT 20u
4449 #define FTM_COMBINE_DTEN2_WIDTH 1u
4450 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
4451 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
4452 #define FTM_COMBINE_SYNCEN2_SHIFT 21u
4453 #define FTM_COMBINE_SYNCEN2_WIDTH 1u
4454 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
4455 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
4456 #define FTM_COMBINE_FAULTEN2_SHIFT 22u
4457 #define FTM_COMBINE_FAULTEN2_WIDTH 1u
4458 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
4459 #define FTM_COMBINE_MCOMBINE2_MASK 0x800000u
4460 #define FTM_COMBINE_MCOMBINE2_SHIFT 23u
4461 #define FTM_COMBINE_MCOMBINE2_WIDTH 1u
4462 #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE2_SHIFT))&FTM_COMBINE_MCOMBINE2_MASK)
4463 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
4464 #define FTM_COMBINE_COMBINE3_SHIFT 24u
4465 #define FTM_COMBINE_COMBINE3_WIDTH 1u
4466 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
4467 #define FTM_COMBINE_COMP3_MASK 0x2000000u
4468 #define FTM_COMBINE_COMP3_SHIFT 25u
4469 #define FTM_COMBINE_COMP3_WIDTH 1u
4470 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
4471 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
4472 #define FTM_COMBINE_DECAPEN3_SHIFT 26u
4473 #define FTM_COMBINE_DECAPEN3_WIDTH 1u
4474 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
4475 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
4476 #define FTM_COMBINE_DECAP3_SHIFT 27u
4477 #define FTM_COMBINE_DECAP3_WIDTH 1u
4478 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
4479 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
4480 #define FTM_COMBINE_DTEN3_SHIFT 28u
4481 #define FTM_COMBINE_DTEN3_WIDTH 1u
4482 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
4483 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
4484 #define FTM_COMBINE_SYNCEN3_SHIFT 29u
4485 #define FTM_COMBINE_SYNCEN3_WIDTH 1u
4486 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
4487 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
4488 #define FTM_COMBINE_FAULTEN3_SHIFT 30u
4489 #define FTM_COMBINE_FAULTEN3_WIDTH 1u
4490 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
4491 #define FTM_COMBINE_MCOMBINE3_MASK 0x80000000u
4492 #define FTM_COMBINE_MCOMBINE3_SHIFT 31u
4493 #define FTM_COMBINE_MCOMBINE3_WIDTH 1u
4494 #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE3_SHIFT))&FTM_COMBINE_MCOMBINE3_MASK)
4495 /* DEADTIME Bit Fields */
4496 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
4497 #define FTM_DEADTIME_DTVAL_SHIFT 0u
4498 #define FTM_DEADTIME_DTVAL_WIDTH 6u
4499 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
4500 #define FTM_DEADTIME_DTPS_MASK 0xC0u
4501 #define FTM_DEADTIME_DTPS_SHIFT 6u
4502 #define FTM_DEADTIME_DTPS_WIDTH 2u
4503 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
4504 #define FTM_DEADTIME_DTVALEX_MASK 0xF0000u
4505 #define FTM_DEADTIME_DTVALEX_SHIFT 16u
4506 #define FTM_DEADTIME_DTVALEX_WIDTH 4u
4507 #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVALEX_SHIFT))&FTM_DEADTIME_DTVALEX_MASK)
4508 /* EXTTRIG Bit Fields */
4509 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
4510 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0u
4511 #define FTM_EXTTRIG_CH2TRIG_WIDTH 1u
4512 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
4513 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
4514 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1u
4515 #define FTM_EXTTRIG_CH3TRIG_WIDTH 1u
4516 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
4517 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
4518 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2u
4519 #define FTM_EXTTRIG_CH4TRIG_WIDTH 1u
4520 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
4521 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
4522 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3u
4523 #define FTM_EXTTRIG_CH5TRIG_WIDTH 1u
4524 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
4525 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
4526 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4u
4527 #define FTM_EXTTRIG_CH0TRIG_WIDTH 1u
4528 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
4529 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
4530 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5u
4531 #define FTM_EXTTRIG_CH1TRIG_WIDTH 1u
4532 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
4533 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
4534 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6u
4535 #define FTM_EXTTRIG_INITTRIGEN_WIDTH 1u
4536 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
4537 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
4538 #define FTM_EXTTRIG_TRIGF_SHIFT 7u
4539 #define FTM_EXTTRIG_TRIGF_WIDTH 1u
4540 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
4541 #define FTM_EXTTRIG_CH6TRIG_MASK 0x100u
4542 #define FTM_EXTTRIG_CH6TRIG_SHIFT 8u
4543 #define FTM_EXTTRIG_CH6TRIG_WIDTH 1u
4544 #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH6TRIG_SHIFT))&FTM_EXTTRIG_CH6TRIG_MASK)
4545 #define FTM_EXTTRIG_CH7TRIG_MASK 0x200u
4546 #define FTM_EXTTRIG_CH7TRIG_SHIFT 9u
4547 #define FTM_EXTTRIG_CH7TRIG_WIDTH 1u
4548 #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH7TRIG_SHIFT))&FTM_EXTTRIG_CH7TRIG_MASK)
4549 /* POL Bit Fields */
4550 #define FTM_POL_POL0_MASK 0x1u
4551 #define FTM_POL_POL0_SHIFT 0u
4552 #define FTM_POL_POL0_WIDTH 1u
4553 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
4554 #define FTM_POL_POL1_MASK 0x2u
4555 #define FTM_POL_POL1_SHIFT 1u
4556 #define FTM_POL_POL1_WIDTH 1u
4557 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
4558 #define FTM_POL_POL2_MASK 0x4u
4559 #define FTM_POL_POL2_SHIFT 2u
4560 #define FTM_POL_POL2_WIDTH 1u
4561 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
4562 #define FTM_POL_POL3_MASK 0x8u
4563 #define FTM_POL_POL3_SHIFT 3u
4564 #define FTM_POL_POL3_WIDTH 1u
4565 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
4566 #define FTM_POL_POL4_MASK 0x10u
4567 #define FTM_POL_POL4_SHIFT 4u
4568 #define FTM_POL_POL4_WIDTH 1u
4569 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
4570 #define FTM_POL_POL5_MASK 0x20u
4571 #define FTM_POL_POL5_SHIFT 5u
4572 #define FTM_POL_POL5_WIDTH 1u
4573 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
4574 #define FTM_POL_POL6_MASK 0x40u
4575 #define FTM_POL_POL6_SHIFT 6u
4576 #define FTM_POL_POL6_WIDTH 1u
4577 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
4578 #define FTM_POL_POL7_MASK 0x80u
4579 #define FTM_POL_POL7_SHIFT 7u
4580 #define FTM_POL_POL7_WIDTH 1u
4581 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
4582 /* FMS Bit Fields */
4583 #define FTM_FMS_FAULTF0_MASK 0x1u
4584 #define FTM_FMS_FAULTF0_SHIFT 0u
4585 #define FTM_FMS_FAULTF0_WIDTH 1u
4586 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
4587 #define FTM_FMS_FAULTF1_MASK 0x2u
4588 #define FTM_FMS_FAULTF1_SHIFT 1u
4589 #define FTM_FMS_FAULTF1_WIDTH 1u
4590 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
4591 #define FTM_FMS_FAULTF2_MASK 0x4u
4592 #define FTM_FMS_FAULTF2_SHIFT 2u
4593 #define FTM_FMS_FAULTF2_WIDTH 1u
4594 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
4595 #define FTM_FMS_FAULTF3_MASK 0x8u
4596 #define FTM_FMS_FAULTF3_SHIFT 3u
4597 #define FTM_FMS_FAULTF3_WIDTH 1u
4598 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
4599 #define FTM_FMS_FAULTIN_MASK 0x20u
4600 #define FTM_FMS_FAULTIN_SHIFT 5u
4601 #define FTM_FMS_FAULTIN_WIDTH 1u
4602 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
4603 #define FTM_FMS_WPEN_MASK 0x40u
4604 #define FTM_FMS_WPEN_SHIFT 6u
4605 #define FTM_FMS_WPEN_WIDTH 1u
4606 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
4607 #define FTM_FMS_FAULTF_MASK 0x80u
4608 #define FTM_FMS_FAULTF_SHIFT 7u
4609 #define FTM_FMS_FAULTF_WIDTH 1u
4610 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
4611 /* FILTER Bit Fields */
4612 #define FTM_FILTER_CH0FVAL_MASK 0xFu
4613 #define FTM_FILTER_CH0FVAL_SHIFT 0u
4614 #define FTM_FILTER_CH0FVAL_WIDTH 4u
4615 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
4616 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
4617 #define FTM_FILTER_CH1FVAL_SHIFT 4u
4618 #define FTM_FILTER_CH1FVAL_WIDTH 4u
4619 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
4620 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
4621 #define FTM_FILTER_CH2FVAL_SHIFT 8u
4622 #define FTM_FILTER_CH2FVAL_WIDTH 4u
4623 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
4624 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
4625 #define FTM_FILTER_CH3FVAL_SHIFT 12u
4626 #define FTM_FILTER_CH3FVAL_WIDTH 4u
4627 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
4628 /* FLTCTRL Bit Fields */
4629 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
4630 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0u
4631 #define FTM_FLTCTRL_FAULT0EN_WIDTH 1u
4632 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
4633 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
4634 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1u
4635 #define FTM_FLTCTRL_FAULT1EN_WIDTH 1u
4636 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
4637 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
4638 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2u
4639 #define FTM_FLTCTRL_FAULT2EN_WIDTH 1u
4640 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
4641 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
4642 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3u
4643 #define FTM_FLTCTRL_FAULT3EN_WIDTH 1u
4644 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
4645 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
4646 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4u
4647 #define FTM_FLTCTRL_FFLTR0EN_WIDTH 1u
4648 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
4649 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
4650 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5u
4651 #define FTM_FLTCTRL_FFLTR1EN_WIDTH 1u
4652 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
4653 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
4654 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6u
4655 #define FTM_FLTCTRL_FFLTR2EN_WIDTH 1u
4656 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
4657 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
4658 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7u
4659 #define FTM_FLTCTRL_FFLTR3EN_WIDTH 1u
4660 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
4661 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
4662 #define FTM_FLTCTRL_FFVAL_SHIFT 8u
4663 #define FTM_FLTCTRL_FFVAL_WIDTH 4u
4664 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
4665 #define FTM_FLTCTRL_FSTATE_MASK 0x8000u
4666 #define FTM_FLTCTRL_FSTATE_SHIFT 15u
4667 #define FTM_FLTCTRL_FSTATE_WIDTH 1u
4668 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FSTATE_SHIFT))&FTM_FLTCTRL_FSTATE_MASK)
4669 /* QDCTRL Bit Fields */
4670 #define FTM_QDCTRL_QUADEN_MASK 0x1u
4671 #define FTM_QDCTRL_QUADEN_SHIFT 0u
4672 #define FTM_QDCTRL_QUADEN_WIDTH 1u
4673 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
4674 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
4675 #define FTM_QDCTRL_TOFDIR_SHIFT 1u
4676 #define FTM_QDCTRL_TOFDIR_WIDTH 1u
4677 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
4678 #define FTM_QDCTRL_QUADIR_MASK 0x4u
4679 #define FTM_QDCTRL_QUADIR_SHIFT 2u
4680 #define FTM_QDCTRL_QUADIR_WIDTH 1u
4681 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
4682 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
4683 #define FTM_QDCTRL_QUADMODE_SHIFT 3u
4684 #define FTM_QDCTRL_QUADMODE_WIDTH 1u
4685 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
4686 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
4687 #define FTM_QDCTRL_PHBPOL_SHIFT 4u
4688 #define FTM_QDCTRL_PHBPOL_WIDTH 1u
4689 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
4690 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
4691 #define FTM_QDCTRL_PHAPOL_SHIFT 5u
4692 #define FTM_QDCTRL_PHAPOL_WIDTH 1u
4693 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
4694 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
4695 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6u
4696 #define FTM_QDCTRL_PHBFLTREN_WIDTH 1u
4697 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
4698 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
4699 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7u
4700 #define FTM_QDCTRL_PHAFLTREN_WIDTH 1u
4701 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
4702 /* CONF Bit Fields */
4703 #define FTM_CONF_LDFQ_MASK 0x1Fu
4704 #define FTM_CONF_LDFQ_SHIFT 0u
4705 #define FTM_CONF_LDFQ_WIDTH 5u
4706 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_LDFQ_SHIFT))&FTM_CONF_LDFQ_MASK)
4707 #define FTM_CONF_BDMMODE_MASK 0xC0u
4708 #define FTM_CONF_BDMMODE_SHIFT 6u
4709 #define FTM_CONF_BDMMODE_WIDTH 2u
4710 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
4711 #define FTM_CONF_GTBEEN_MASK 0x200u
4712 #define FTM_CONF_GTBEEN_SHIFT 9u
4713 #define FTM_CONF_GTBEEN_WIDTH 1u
4714 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
4715 #define FTM_CONF_GTBEOUT_MASK 0x400u
4716 #define FTM_CONF_GTBEOUT_SHIFT 10u
4717 #define FTM_CONF_GTBEOUT_WIDTH 1u
4718 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
4719 #define FTM_CONF_ITRIGR_MASK 0x800u
4720 #define FTM_CONF_ITRIGR_SHIFT 11u
4721 #define FTM_CONF_ITRIGR_WIDTH 1u
4722 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_ITRIGR_SHIFT))&FTM_CONF_ITRIGR_MASK)
4723 /* FLTPOL Bit Fields */
4724 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
4725 #define FTM_FLTPOL_FLT0POL_SHIFT 0u
4726 #define FTM_FLTPOL_FLT0POL_WIDTH 1u
4727 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
4728 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
4729 #define FTM_FLTPOL_FLT1POL_SHIFT 1u
4730 #define FTM_FLTPOL_FLT1POL_WIDTH 1u
4731 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
4732 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
4733 #define FTM_FLTPOL_FLT2POL_SHIFT 2u
4734 #define FTM_FLTPOL_FLT2POL_WIDTH 1u
4735 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
4736 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
4737 #define FTM_FLTPOL_FLT3POL_SHIFT 3u
4738 #define FTM_FLTPOL_FLT3POL_WIDTH 1u
4739 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
4740 /* SYNCONF Bit Fields */
4741 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
4742 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0u
4743 #define FTM_SYNCONF_HWTRIGMODE_WIDTH 1u
4744 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
4745 #define FTM_SYNCONF_CNTINC_MASK 0x4u
4746 #define FTM_SYNCONF_CNTINC_SHIFT 2u
4747 #define FTM_SYNCONF_CNTINC_WIDTH 1u
4748 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
4749 #define FTM_SYNCONF_INVC_MASK 0x10u
4750 #define FTM_SYNCONF_INVC_SHIFT 4u
4751 #define FTM_SYNCONF_INVC_WIDTH 1u
4752 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
4753 #define FTM_SYNCONF_SWOC_MASK 0x20u
4754 #define FTM_SYNCONF_SWOC_SHIFT 5u
4755 #define FTM_SYNCONF_SWOC_WIDTH 1u
4756 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
4757 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
4758 #define FTM_SYNCONF_SYNCMODE_SHIFT 7u
4759 #define FTM_SYNCONF_SYNCMODE_WIDTH 1u
4760 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
4761 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
4762 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8u
4763 #define FTM_SYNCONF_SWRSTCNT_WIDTH 1u
4764 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
4765 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
4766 #define FTM_SYNCONF_SWWRBUF_SHIFT 9u
4767 #define FTM_SYNCONF_SWWRBUF_WIDTH 1u
4768 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
4769 #define FTM_SYNCONF_SWOM_MASK 0x400u
4770 #define FTM_SYNCONF_SWOM_SHIFT 10u
4771 #define FTM_SYNCONF_SWOM_WIDTH 1u
4772 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
4773 #define FTM_SYNCONF_SWINVC_MASK 0x800u
4774 #define FTM_SYNCONF_SWINVC_SHIFT 11u
4775 #define FTM_SYNCONF_SWINVC_WIDTH 1u
4776 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
4777 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
4778 #define FTM_SYNCONF_SWSOC_SHIFT 12u
4779 #define FTM_SYNCONF_SWSOC_WIDTH 1u
4780 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
4781 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
4782 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16u
4783 #define FTM_SYNCONF_HWRSTCNT_WIDTH 1u
4784 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
4785 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
4786 #define FTM_SYNCONF_HWWRBUF_SHIFT 17u
4787 #define FTM_SYNCONF_HWWRBUF_WIDTH 1u
4788 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
4789 #define FTM_SYNCONF_HWOM_MASK 0x40000u
4790 #define FTM_SYNCONF_HWOM_SHIFT 18u
4791 #define FTM_SYNCONF_HWOM_WIDTH 1u
4792 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
4793 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
4794 #define FTM_SYNCONF_HWINVC_SHIFT 19u
4795 #define FTM_SYNCONF_HWINVC_WIDTH 1u
4796 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
4797 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
4798 #define FTM_SYNCONF_HWSOC_SHIFT 20u
4799 #define FTM_SYNCONF_HWSOC_WIDTH 1u
4800 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
4801 /* INVCTRL Bit Fields */
4802 #define FTM_INVCTRL_INV0EN_MASK 0x1u
4803 #define FTM_INVCTRL_INV0EN_SHIFT 0u
4804 #define FTM_INVCTRL_INV0EN_WIDTH 1u
4805 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
4806 #define FTM_INVCTRL_INV1EN_MASK 0x2u
4807 #define FTM_INVCTRL_INV1EN_SHIFT 1u
4808 #define FTM_INVCTRL_INV1EN_WIDTH 1u
4809 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
4810 #define FTM_INVCTRL_INV2EN_MASK 0x4u
4811 #define FTM_INVCTRL_INV2EN_SHIFT 2u
4812 #define FTM_INVCTRL_INV2EN_WIDTH 1u
4813 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
4814 #define FTM_INVCTRL_INV3EN_MASK 0x8u
4815 #define FTM_INVCTRL_INV3EN_SHIFT 3u
4816 #define FTM_INVCTRL_INV3EN_WIDTH 1u
4817 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
4818 /* SWOCTRL Bit Fields */
4819 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
4820 #define FTM_SWOCTRL_CH0OC_SHIFT 0u
4821 #define FTM_SWOCTRL_CH0OC_WIDTH 1u
4822 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
4823 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
4824 #define FTM_SWOCTRL_CH1OC_SHIFT 1u
4825 #define FTM_SWOCTRL_CH1OC_WIDTH 1u
4826 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
4827 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
4828 #define FTM_SWOCTRL_CH2OC_SHIFT 2u
4829 #define FTM_SWOCTRL_CH2OC_WIDTH 1u
4830 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
4831 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
4832 #define FTM_SWOCTRL_CH3OC_SHIFT 3u
4833 #define FTM_SWOCTRL_CH3OC_WIDTH 1u
4834 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
4835 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
4836 #define FTM_SWOCTRL_CH4OC_SHIFT 4u
4837 #define FTM_SWOCTRL_CH4OC_WIDTH 1u
4838 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
4839 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
4840 #define FTM_SWOCTRL_CH5OC_SHIFT 5u
4841 #define FTM_SWOCTRL_CH5OC_WIDTH 1u
4842 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
4843 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
4844 #define FTM_SWOCTRL_CH6OC_SHIFT 6u
4845 #define FTM_SWOCTRL_CH6OC_WIDTH 1u
4846 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
4847 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
4848 #define FTM_SWOCTRL_CH7OC_SHIFT 7u
4849 #define FTM_SWOCTRL_CH7OC_WIDTH 1u
4850 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
4851 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
4852 #define FTM_SWOCTRL_CH0OCV_SHIFT 8u
4853 #define FTM_SWOCTRL_CH0OCV_WIDTH 1u
4854 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
4855 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
4856 #define FTM_SWOCTRL_CH1OCV_SHIFT 9u
4857 #define FTM_SWOCTRL_CH1OCV_WIDTH 1u
4858 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
4859 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
4860 #define FTM_SWOCTRL_CH2OCV_SHIFT 10u
4861 #define FTM_SWOCTRL_CH2OCV_WIDTH 1u
4862 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
4863 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
4864 #define FTM_SWOCTRL_CH3OCV_SHIFT 11u
4865 #define FTM_SWOCTRL_CH3OCV_WIDTH 1u
4866 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
4867 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
4868 #define FTM_SWOCTRL_CH4OCV_SHIFT 12u
4869 #define FTM_SWOCTRL_CH4OCV_WIDTH 1u
4870 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
4871 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
4872 #define FTM_SWOCTRL_CH5OCV_SHIFT 13u
4873 #define FTM_SWOCTRL_CH5OCV_WIDTH 1u
4874 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
4875 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
4876 #define FTM_SWOCTRL_CH6OCV_SHIFT 14u
4877 #define FTM_SWOCTRL_CH6OCV_WIDTH 1u
4878 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
4879 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
4880 #define FTM_SWOCTRL_CH7OCV_SHIFT 15u
4881 #define FTM_SWOCTRL_CH7OCV_WIDTH 1u
4882 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
4883 /* PWMLOAD Bit Fields */
4884 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
4885 #define FTM_PWMLOAD_CH0SEL_SHIFT 0u
4886 #define FTM_PWMLOAD_CH0SEL_WIDTH 1u
4887 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
4888 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
4889 #define FTM_PWMLOAD_CH1SEL_SHIFT 1u
4890 #define FTM_PWMLOAD_CH1SEL_WIDTH 1u
4891 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
4892 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
4893 #define FTM_PWMLOAD_CH2SEL_SHIFT 2u
4894 #define FTM_PWMLOAD_CH2SEL_WIDTH 1u
4895 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
4896 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
4897 #define FTM_PWMLOAD_CH3SEL_SHIFT 3u
4898 #define FTM_PWMLOAD_CH3SEL_WIDTH 1u
4899 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
4900 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
4901 #define FTM_PWMLOAD_CH4SEL_SHIFT 4u
4902 #define FTM_PWMLOAD_CH4SEL_WIDTH 1u
4903 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
4904 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
4905 #define FTM_PWMLOAD_CH5SEL_SHIFT 5u
4906 #define FTM_PWMLOAD_CH5SEL_WIDTH 1u
4907 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
4908 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
4909 #define FTM_PWMLOAD_CH6SEL_SHIFT 6u
4910 #define FTM_PWMLOAD_CH6SEL_WIDTH 1u
4911 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
4912 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
4913 #define FTM_PWMLOAD_CH7SEL_SHIFT 7u
4914 #define FTM_PWMLOAD_CH7SEL_WIDTH 1u
4915 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
4916 #define FTM_PWMLOAD_HCSEL_MASK 0x100u
4917 #define FTM_PWMLOAD_HCSEL_SHIFT 8u
4918 #define FTM_PWMLOAD_HCSEL_WIDTH 1u
4919 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_HCSEL_SHIFT))&FTM_PWMLOAD_HCSEL_MASK)
4920 #define FTM_PWMLOAD_LDOK_MASK 0x200u
4921 #define FTM_PWMLOAD_LDOK_SHIFT 9u
4922 #define FTM_PWMLOAD_LDOK_WIDTH 1u
4923 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
4924 #define FTM_PWMLOAD_GLEN_MASK 0x400u
4925 #define FTM_PWMLOAD_GLEN_SHIFT 10u
4926 #define FTM_PWMLOAD_GLEN_WIDTH 1u
4927 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLEN_SHIFT))&FTM_PWMLOAD_GLEN_MASK)
4928 #define FTM_PWMLOAD_GLDOK_MASK 0x800u
4929 #define FTM_PWMLOAD_GLDOK_SHIFT 11u
4930 #define FTM_PWMLOAD_GLDOK_WIDTH 1u
4931 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLDOK_SHIFT))&FTM_PWMLOAD_GLDOK_MASK)
4932 /* HCR Bit Fields */
4933 #define FTM_HCR_HCVAL_MASK 0xFFFFu
4934 #define FTM_HCR_HCVAL_SHIFT 0u
4935 #define FTM_HCR_HCVAL_WIDTH 16u
4936 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_HCR_HCVAL_SHIFT))&FTM_HCR_HCVAL_MASK)
4937 /* PAIR0DEADTIME Bit Fields */
4938 #define FTM_PAIR0DEADTIME_DTVAL_MASK 0x3Fu
4939 #define FTM_PAIR0DEADTIME_DTVAL_SHIFT 0u
4940 #define FTM_PAIR0DEADTIME_DTVAL_WIDTH 6u
4941 #define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVAL_SHIFT))&FTM_PAIR0DEADTIME_DTVAL_MASK)
4942 #define FTM_PAIR0DEADTIME_DTPS_MASK 0xC0u
4943 #define FTM_PAIR0DEADTIME_DTPS_SHIFT 6u
4944 #define FTM_PAIR0DEADTIME_DTPS_WIDTH 2u
4945 #define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTPS_SHIFT))&FTM_PAIR0DEADTIME_DTPS_MASK)
4946 #define FTM_PAIR0DEADTIME_DTVALEX_MASK 0xF0000u
4947 #define FTM_PAIR0DEADTIME_DTVALEX_SHIFT 16u
4948 #define FTM_PAIR0DEADTIME_DTVALEX_WIDTH 4u
4949 #define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVALEX_SHIFT))&FTM_PAIR0DEADTIME_DTVALEX_MASK)
4950 /* PAIR1DEADTIME Bit Fields */
4951 #define FTM_PAIR1DEADTIME_DTVAL_MASK 0x3Fu
4952 #define FTM_PAIR1DEADTIME_DTVAL_SHIFT 0u
4953 #define FTM_PAIR1DEADTIME_DTVAL_WIDTH 6u
4954 #define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVAL_SHIFT))&FTM_PAIR1DEADTIME_DTVAL_MASK)
4955 #define FTM_PAIR1DEADTIME_DTPS_MASK 0xC0u
4956 #define FTM_PAIR1DEADTIME_DTPS_SHIFT 6u
4957 #define FTM_PAIR1DEADTIME_DTPS_WIDTH 2u
4958 #define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTPS_SHIFT))&FTM_PAIR1DEADTIME_DTPS_MASK)
4959 #define FTM_PAIR1DEADTIME_DTVALEX_MASK 0xF0000u
4960 #define FTM_PAIR1DEADTIME_DTVALEX_SHIFT 16u
4961 #define FTM_PAIR1DEADTIME_DTVALEX_WIDTH 4u
4962 #define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVALEX_SHIFT))&FTM_PAIR1DEADTIME_DTVALEX_MASK)
4963 /* PAIR2DEADTIME Bit Fields */
4964 #define FTM_PAIR2DEADTIME_DTVAL_MASK 0x3Fu
4965 #define FTM_PAIR2DEADTIME_DTVAL_SHIFT 0u
4966 #define FTM_PAIR2DEADTIME_DTVAL_WIDTH 6u
4967 #define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVAL_SHIFT))&FTM_PAIR2DEADTIME_DTVAL_MASK)
4968 #define FTM_PAIR2DEADTIME_DTPS_MASK 0xC0u
4969 #define FTM_PAIR2DEADTIME_DTPS_SHIFT 6u
4970 #define FTM_PAIR2DEADTIME_DTPS_WIDTH 2u
4971 #define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTPS_SHIFT))&FTM_PAIR2DEADTIME_DTPS_MASK)
4972 #define FTM_PAIR2DEADTIME_DTVALEX_MASK 0xF0000u
4973 #define FTM_PAIR2DEADTIME_DTVALEX_SHIFT 16u
4974 #define FTM_PAIR2DEADTIME_DTVALEX_WIDTH 4u
4975 #define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVALEX_SHIFT))&FTM_PAIR2DEADTIME_DTVALEX_MASK)
4976 /* PAIR3DEADTIME Bit Fields */
4977 #define FTM_PAIR3DEADTIME_DTVAL_MASK 0x3Fu
4978 #define FTM_PAIR3DEADTIME_DTVAL_SHIFT 0u
4979 #define FTM_PAIR3DEADTIME_DTVAL_WIDTH 6u
4980 #define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVAL_SHIFT))&FTM_PAIR3DEADTIME_DTVAL_MASK)
4981 #define FTM_PAIR3DEADTIME_DTPS_MASK 0xC0u
4982 #define FTM_PAIR3DEADTIME_DTPS_SHIFT 6u
4983 #define FTM_PAIR3DEADTIME_DTPS_WIDTH 2u
4984 #define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTPS_SHIFT))&FTM_PAIR3DEADTIME_DTPS_MASK)
4985 #define FTM_PAIR3DEADTIME_DTVALEX_MASK 0xF0000u
4986 #define FTM_PAIR3DEADTIME_DTVALEX_SHIFT 16u
4987 #define FTM_PAIR3DEADTIME_DTVALEX_WIDTH 4u
4988 #define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVALEX_SHIFT))&FTM_PAIR3DEADTIME_DTVALEX_MASK)
4989  /* end of group FTM_Register_Masks */
4993 
4994  /* end of group FTM_Peripheral_Access_Layer */
4998 
4999 
5000 /* ----------------------------------------------------------------------------
5001  -- GPIO Peripheral Access Layer
5002  ---------------------------------------------------------------------------- */
5003 
5013 typedef struct {
5014  __IO uint32_t PDOR;
5015  __O uint32_t PSOR;
5016  __O uint32_t PCOR;
5017  __O uint32_t PTOR;
5018  __I uint32_t PDIR;
5019  __IO uint32_t PDDR;
5020  __IO uint32_t PIDR;
5022 
5024 #define GPIO_INSTANCE_COUNT (5u)
5025 
5026 
5027 /* GPIO - Peripheral instance base addresses */
5029 #define PTA_BASE (0x400FF000u)
5030 
5031 #define PTA ((GPIO_Type *)PTA_BASE)
5032 
5033 #define PTB_BASE (0x400FF040u)
5034 
5035 #define PTB ((GPIO_Type *)PTB_BASE)
5036 
5037 #define PTC_BASE (0x400FF080u)
5038 
5039 #define PTC ((GPIO_Type *)PTC_BASE)
5040 
5041 #define PTD_BASE (0x400FF0C0u)
5042 
5043 #define PTD ((GPIO_Type *)PTD_BASE)
5044 
5045 #define PTE_BASE (0x400FF100u)
5046 
5047 #define PTE ((GPIO_Type *)PTE_BASE)
5048 
5049 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
5050 
5051 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
5052 
5053 /* ----------------------------------------------------------------------------
5054  -- GPIO Register Masks
5055  ---------------------------------------------------------------------------- */
5056 
5062 /* PDOR Bit Fields */
5063 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
5064 #define GPIO_PDOR_PDO_SHIFT 0u
5065 #define GPIO_PDOR_PDO_WIDTH 32u
5066 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
5067 /* PSOR Bit Fields */
5068 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
5069 #define GPIO_PSOR_PTSO_SHIFT 0u
5070 #define GPIO_PSOR_PTSO_WIDTH 32u
5071 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
5072 /* PCOR Bit Fields */
5073 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
5074 #define GPIO_PCOR_PTCO_SHIFT 0u
5075 #define GPIO_PCOR_PTCO_WIDTH 32u
5076 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
5077 /* PTOR Bit Fields */
5078 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
5079 #define GPIO_PTOR_PTTO_SHIFT 0u
5080 #define GPIO_PTOR_PTTO_WIDTH 32u
5081 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
5082 /* PDIR Bit Fields */
5083 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
5084 #define GPIO_PDIR_PDI_SHIFT 0u
5085 #define GPIO_PDIR_PDI_WIDTH 32u
5086 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
5087 /* PDDR Bit Fields */
5088 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
5089 #define GPIO_PDDR_PDD_SHIFT 0u
5090 #define GPIO_PDDR_PDD_WIDTH 32u
5091 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
5092 /* PIDR Bit Fields */
5093 #define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
5094 #define GPIO_PIDR_PID_SHIFT 0u
5095 #define GPIO_PIDR_PID_WIDTH 32u
5096 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
5097  /* end of group GPIO_Register_Masks */
5101 
5102  /* end of group GPIO_Peripheral_Access_Layer */
5106 
5107 
5108 /* ----------------------------------------------------------------------------
5109  -- LMEM Peripheral Access Layer
5110  ---------------------------------------------------------------------------- */
5111 
5121 typedef struct {
5122  __IO uint32_t PCCCR;
5123  __IO uint32_t PCCLCR;
5124  __IO uint32_t PCCSAR;
5125  __IO uint32_t PCCCVR;
5126  uint8_t RESERVED_0[16];
5127  __IO uint32_t PCCRMR;
5129 
5131 #define LMEM_INSTANCE_COUNT (1u)
5132 
5133 
5134 /* LMEM - Peripheral instance base addresses */
5136 #define LMEM_BASE (0xE0082000u)
5137 
5138 #define LMEM ((LMEM_Type *)LMEM_BASE)
5139 
5140 #define LMEM_BASE_ADDRS { LMEM_BASE }
5141 
5142 #define LMEM_BASE_PTRS { LMEM }
5143 
5144 /* ----------------------------------------------------------------------------
5145  -- LMEM Register Masks
5146  ---------------------------------------------------------------------------- */
5147 
5153 /* PCCCR Bit Fields */
5154 #define LMEM_PCCCR_ENCACHE_MASK 0x1u
5155 #define LMEM_PCCCR_ENCACHE_SHIFT 0u
5156 #define LMEM_PCCCR_ENCACHE_WIDTH 1u
5157 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_ENCACHE_SHIFT))&LMEM_PCCCR_ENCACHE_MASK)
5158 #define LMEM_PCCCR_PCCR2_MASK 0x4u
5159 #define LMEM_PCCCR_PCCR2_SHIFT 2u
5160 #define LMEM_PCCCR_PCCR2_WIDTH 1u
5161 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR2_SHIFT))&LMEM_PCCCR_PCCR2_MASK)
5162 #define LMEM_PCCCR_PCCR3_MASK 0x8u
5163 #define LMEM_PCCCR_PCCR3_SHIFT 3u
5164 #define LMEM_PCCCR_PCCR3_WIDTH 1u
5165 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR3_SHIFT))&LMEM_PCCCR_PCCR3_MASK)
5166 #define LMEM_PCCCR_INVW0_MASK 0x1000000u
5167 #define LMEM_PCCCR_INVW0_SHIFT 24u
5168 #define LMEM_PCCCR_INVW0_WIDTH 1u
5169 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW0_SHIFT))&LMEM_PCCCR_INVW0_MASK)
5170 #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u
5171 #define LMEM_PCCCR_PUSHW0_SHIFT 25u
5172 #define LMEM_PCCCR_PUSHW0_WIDTH 1u
5173 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW0_SHIFT))&LMEM_PCCCR_PUSHW0_MASK)
5174 #define LMEM_PCCCR_INVW1_MASK 0x4000000u
5175 #define LMEM_PCCCR_INVW1_SHIFT 26u
5176 #define LMEM_PCCCR_INVW1_WIDTH 1u
5177 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW1_SHIFT))&LMEM_PCCCR_INVW1_MASK)
5178 #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u
5179 #define LMEM_PCCCR_PUSHW1_SHIFT 27u
5180 #define LMEM_PCCCR_PUSHW1_WIDTH 1u
5181 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW1_SHIFT))&LMEM_PCCCR_PUSHW1_MASK)
5182 #define LMEM_PCCCR_GO_MASK 0x80000000u
5183 #define LMEM_PCCCR_GO_SHIFT 31u
5184 #define LMEM_PCCCR_GO_WIDTH 1u
5185 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_GO_SHIFT))&LMEM_PCCCR_GO_MASK)
5186 /* PCCLCR Bit Fields */
5187 #define LMEM_PCCLCR_LGO_MASK 0x1u
5188 #define LMEM_PCCLCR_LGO_SHIFT 0u
5189 #define LMEM_PCCLCR_LGO_WIDTH 1u
5190 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LGO_SHIFT))&LMEM_PCCLCR_LGO_MASK)
5191 #define LMEM_PCCLCR_CACHEADDR_MASK 0x3FFCu
5192 #define LMEM_PCCLCR_CACHEADDR_SHIFT 2u
5193 #define LMEM_PCCLCR_CACHEADDR_WIDTH 12u
5194 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
5195 #define LMEM_PCCLCR_WSEL_MASK 0x4000u
5196 #define LMEM_PCCLCR_WSEL_SHIFT 14u
5197 #define LMEM_PCCLCR_WSEL_WIDTH 1u
5198 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_WSEL_SHIFT))&LMEM_PCCLCR_WSEL_MASK)
5199 #define LMEM_PCCLCR_TDSEL_MASK 0x10000u
5200 #define LMEM_PCCLCR_TDSEL_SHIFT 16u
5201 #define LMEM_PCCLCR_TDSEL_WIDTH 1u
5202 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_TDSEL_SHIFT))&LMEM_PCCLCR_TDSEL_MASK)
5203 #define LMEM_PCCLCR_LCIVB_MASK 0x100000u
5204 #define LMEM_PCCLCR_LCIVB_SHIFT 20u
5205 #define LMEM_PCCLCR_LCIVB_WIDTH 1u
5206 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIVB_SHIFT))&LMEM_PCCLCR_LCIVB_MASK)
5207 #define LMEM_PCCLCR_LCIMB_MASK 0x200000u
5208 #define LMEM_PCCLCR_LCIMB_SHIFT 21u
5209 #define LMEM_PCCLCR_LCIMB_WIDTH 1u
5210 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIMB_SHIFT))&LMEM_PCCLCR_LCIMB_MASK)
5211 #define LMEM_PCCLCR_LCWAY_MASK 0x400000u
5212 #define LMEM_PCCLCR_LCWAY_SHIFT 22u
5213 #define LMEM_PCCLCR_LCWAY_WIDTH 1u
5214 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCWAY_SHIFT))&LMEM_PCCLCR_LCWAY_MASK)
5215 #define LMEM_PCCLCR_LCMD_MASK 0x3000000u
5216 #define LMEM_PCCLCR_LCMD_SHIFT 24u
5217 #define LMEM_PCCLCR_LCMD_WIDTH 2u
5218 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
5219 #define LMEM_PCCLCR_LADSEL_MASK 0x4000000u
5220 #define LMEM_PCCLCR_LADSEL_SHIFT 26u
5221 #define LMEM_PCCLCR_LADSEL_WIDTH 1u
5222 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LADSEL_SHIFT))&LMEM_PCCLCR_LADSEL_MASK)
5223 #define LMEM_PCCLCR_LACC_MASK 0x8000000u
5224 #define LMEM_PCCLCR_LACC_SHIFT 27u
5225 #define LMEM_PCCLCR_LACC_WIDTH 1u
5226 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LACC_SHIFT))&LMEM_PCCLCR_LACC_MASK)
5227 /* PCCSAR Bit Fields */
5228 #define LMEM_PCCSAR_LGO_MASK 0x1u
5229 #define LMEM_PCCSAR_LGO_SHIFT 0u
5230 #define LMEM_PCCSAR_LGO_WIDTH 1u
5231 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_LGO_SHIFT))&LMEM_PCCSAR_LGO_MASK)
5232 #define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu
5233 #define LMEM_PCCSAR_PHYADDR_SHIFT 2u
5234 #define LMEM_PCCSAR_PHYADDR_WIDTH 30u
5235 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
5236 /* PCCCVR Bit Fields */
5237 #define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu
5238 #define LMEM_PCCCVR_DATA_SHIFT 0u
5239 #define LMEM_PCCCVR_DATA_WIDTH 32u
5240 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
5241 /* PCCRMR Bit Fields */
5242 #define LMEM_PCCRMR_R15_MASK 0x3u
5243 #define LMEM_PCCRMR_R15_SHIFT 0u
5244 #define LMEM_PCCRMR_R15_WIDTH 2u
5245 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R15_SHIFT))&LMEM_PCCRMR_R15_MASK)
5246 #define LMEM_PCCRMR_R14_MASK 0xCu
5247 #define LMEM_PCCRMR_R14_SHIFT 2u
5248 #define LMEM_PCCRMR_R14_WIDTH 2u
5249 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R14_SHIFT))&LMEM_PCCRMR_R14_MASK)
5250 #define LMEM_PCCRMR_R13_MASK 0x30u
5251 #define LMEM_PCCRMR_R13_SHIFT 4u
5252 #define LMEM_PCCRMR_R13_WIDTH 2u
5253 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R13_SHIFT))&LMEM_PCCRMR_R13_MASK)
5254 #define LMEM_PCCRMR_R12_MASK 0xC0u
5255 #define LMEM_PCCRMR_R12_SHIFT 6u
5256 #define LMEM_PCCRMR_R12_WIDTH 2u
5257 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R12_SHIFT))&LMEM_PCCRMR_R12_MASK)
5258 #define LMEM_PCCRMR_R11_MASK 0x300u
5259 #define LMEM_PCCRMR_R11_SHIFT 8u
5260 #define LMEM_PCCRMR_R11_WIDTH 2u
5261 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R11_SHIFT))&LMEM_PCCRMR_R11_MASK)
5262 #define LMEM_PCCRMR_R10_MASK 0xC00u
5263 #define LMEM_PCCRMR_R10_SHIFT 10u
5264 #define LMEM_PCCRMR_R10_WIDTH 2u
5265 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R10_SHIFT))&LMEM_PCCRMR_R10_MASK)
5266 #define LMEM_PCCRMR_R9_MASK 0x3000u
5267 #define LMEM_PCCRMR_R9_SHIFT 12u
5268 #define LMEM_PCCRMR_R9_WIDTH 2u
5269 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R9_SHIFT))&LMEM_PCCRMR_R9_MASK)
5270 #define LMEM_PCCRMR_R8_MASK 0xC000u
5271 #define LMEM_PCCRMR_R8_SHIFT 14u
5272 #define LMEM_PCCRMR_R8_WIDTH 2u
5273 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R8_SHIFT))&LMEM_PCCRMR_R8_MASK)
5274 #define LMEM_PCCRMR_R7_MASK 0x30000u
5275 #define LMEM_PCCRMR_R7_SHIFT 16u
5276 #define LMEM_PCCRMR_R7_WIDTH 2u
5277 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R7_SHIFT))&LMEM_PCCRMR_R7_MASK)
5278 #define LMEM_PCCRMR_R6_MASK 0xC0000u
5279 #define LMEM_PCCRMR_R6_SHIFT 18u
5280 #define LMEM_PCCRMR_R6_WIDTH 2u
5281 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R6_SHIFT))&LMEM_PCCRMR_R6_MASK)
5282 #define LMEM_PCCRMR_R5_MASK 0x300000u
5283 #define LMEM_PCCRMR_R5_SHIFT 20u
5284 #define LMEM_PCCRMR_R5_WIDTH 2u
5285 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R5_SHIFT))&LMEM_PCCRMR_R5_MASK)
5286 #define LMEM_PCCRMR_R4_MASK 0xC00000u
5287 #define LMEM_PCCRMR_R4_SHIFT 22u
5288 #define LMEM_PCCRMR_R4_WIDTH 2u
5289 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R4_SHIFT))&LMEM_PCCRMR_R4_MASK)
5290 #define LMEM_PCCRMR_R3_MASK 0x3000000u
5291 #define LMEM_PCCRMR_R3_SHIFT 24u
5292 #define LMEM_PCCRMR_R3_WIDTH 2u
5293 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R3_SHIFT))&LMEM_PCCRMR_R3_MASK)
5294 #define LMEM_PCCRMR_R2_MASK 0xC000000u
5295 #define LMEM_PCCRMR_R2_SHIFT 26u
5296 #define LMEM_PCCRMR_R2_WIDTH 2u
5297 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R2_SHIFT))&LMEM_PCCRMR_R2_MASK)
5298 #define LMEM_PCCRMR_R1_MASK 0x30000000u
5299 #define LMEM_PCCRMR_R1_SHIFT 28u
5300 #define LMEM_PCCRMR_R1_WIDTH 2u
5301 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R1_SHIFT))&LMEM_PCCRMR_R1_MASK)
5302 #define LMEM_PCCRMR_R0_MASK 0xC0000000u
5303 #define LMEM_PCCRMR_R0_SHIFT 30u
5304 #define LMEM_PCCRMR_R0_WIDTH 2u
5305 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R0_SHIFT))&LMEM_PCCRMR_R0_MASK)
5306  /* end of group LMEM_Register_Masks */
5310 
5311  /* end of group LMEM_Peripheral_Access_Layer */
5315 
5316 
5317 /* ----------------------------------------------------------------------------
5318  -- LPI2C Peripheral Access Layer
5319  ---------------------------------------------------------------------------- */
5320 
5330 typedef struct {
5331  __I uint32_t VERID;
5332  __I uint32_t PARAM;
5333  uint8_t RESERVED_0[8];
5334  __IO uint32_t MCR;
5335  __IO uint32_t MSR;
5336  __IO uint32_t MIER;
5337  __IO uint32_t MDER;
5338  __IO uint32_t MCFGR0;
5339  __IO uint32_t MCFGR1;
5340  __IO uint32_t MCFGR2;
5341  __IO uint32_t MCFGR3;
5342  uint8_t RESERVED_1[16];
5343  __IO uint32_t MDMR;
5344  uint8_t RESERVED_2[4];
5345  __IO uint32_t MCCR0;
5346  uint8_t RESERVED_3[4];
5347  __IO uint32_t MCCR1;
5348  uint8_t RESERVED_4[4];
5349  __IO uint32_t MFCR;
5350  __I uint32_t MFSR;
5351  __IO uint32_t MTDR;
5352  uint8_t RESERVED_5[12];
5353  __I uint32_t MRDR;
5354  uint8_t RESERVED_6[156];
5355  __IO uint32_t SCR;
5356  __IO uint32_t SSR;
5357  __IO uint32_t SIER;
5358  __IO uint32_t SDER;
5359  uint8_t RESERVED_7[4];
5360  __IO uint32_t SCFGR1;
5361  __IO uint32_t SCFGR2;
5362  uint8_t RESERVED_8[20];
5363  __IO uint32_t SAMR;
5364  uint8_t RESERVED_9[12];
5365  __I uint32_t SASR;
5366  __IO uint32_t STAR;
5367  uint8_t RESERVED_10[8];
5368  __IO uint32_t STDR;
5369  uint8_t RESERVED_11[12];
5370  __I uint32_t SRDR;
5372 
5374 #define LPI2C_INSTANCE_COUNT (1u)
5375 
5376 
5377 /* LPI2C - Peripheral instance base addresses */
5379 #define LPI2C0_BASE (0x40066000u)
5380 
5381 #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
5382 
5383 #define LPI2C_BASE_ADDRS { LPI2C0_BASE }
5384 
5385 #define LPI2C_BASE_PTRS { LPI2C0 }
5386 
5387 #define LPI2C_IRQS_ARR_COUNT (2u)
5388 
5389 #define LPI2C_MASTER_IRQS_CH_COUNT (1u)
5390 
5391 #define LPI2C_SLAVE_IRQS_CH_COUNT (1u)
5392 
5393 #define LPI2C_MASTER_IRQS { LPI2C0_Master_IRQn }
5394 #define LPI2C_SLAVE_IRQS { LPI2C0_Slave_IRQn }
5395 
5396 /* ----------------------------------------------------------------------------
5397  -- LPI2C Register Masks
5398  ---------------------------------------------------------------------------- */
5399 
5405 /* VERID Bit Fields */
5406 #define LPI2C_VERID_FEATURE_MASK 0xFFFFu
5407 #define LPI2C_VERID_FEATURE_SHIFT 0u
5408 #define LPI2C_VERID_FEATURE_WIDTH 16u
5409 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
5410 #define LPI2C_VERID_MINOR_MASK 0xFF0000u
5411 #define LPI2C_VERID_MINOR_SHIFT 16u
5412 #define LPI2C_VERID_MINOR_WIDTH 8u
5413 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
5414 #define LPI2C_VERID_MAJOR_MASK 0xFF000000u
5415 #define LPI2C_VERID_MAJOR_SHIFT 24u
5416 #define LPI2C_VERID_MAJOR_WIDTH 8u
5417 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
5418 /* PARAM Bit Fields */
5419 #define LPI2C_PARAM_MTXFIFO_MASK 0xFu
5420 #define LPI2C_PARAM_MTXFIFO_SHIFT 0u
5421 #define LPI2C_PARAM_MTXFIFO_WIDTH 4u
5422 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
5423 #define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
5424 #define LPI2C_PARAM_MRXFIFO_SHIFT 8u
5425 #define LPI2C_PARAM_MRXFIFO_WIDTH 4u
5426 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
5427 /* MCR Bit Fields */
5428 #define LPI2C_MCR_MEN_MASK 0x1u
5429 #define LPI2C_MCR_MEN_SHIFT 0u
5430 #define LPI2C_MCR_MEN_WIDTH 1u
5431 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
5432 #define LPI2C_MCR_RST_MASK 0x2u
5433 #define LPI2C_MCR_RST_SHIFT 1u
5434 #define LPI2C_MCR_RST_WIDTH 1u
5435 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
5436 #define LPI2C_MCR_DOZEN_MASK 0x4u
5437 #define LPI2C_MCR_DOZEN_SHIFT 2u
5438 #define LPI2C_MCR_DOZEN_WIDTH 1u
5439 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
5440 #define LPI2C_MCR_DBGEN_MASK 0x8u
5441 #define LPI2C_MCR_DBGEN_SHIFT 3u
5442 #define LPI2C_MCR_DBGEN_WIDTH 1u
5443 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
5444 #define LPI2C_MCR_RTF_MASK 0x100u
5445 #define LPI2C_MCR_RTF_SHIFT 8u
5446 #define LPI2C_MCR_RTF_WIDTH 1u
5447 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
5448 #define LPI2C_MCR_RRF_MASK 0x200u
5449 #define LPI2C_MCR_RRF_SHIFT 9u
5450 #define LPI2C_MCR_RRF_WIDTH 1u
5451 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
5452 /* MSR Bit Fields */
5453 #define LPI2C_MSR_TDF_MASK 0x1u
5454 #define LPI2C_MSR_TDF_SHIFT 0u
5455 #define LPI2C_MSR_TDF_WIDTH 1u
5456 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
5457 #define LPI2C_MSR_RDF_MASK 0x2u
5458 #define LPI2C_MSR_RDF_SHIFT 1u
5459 #define LPI2C_MSR_RDF_WIDTH 1u
5460 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
5461 #define LPI2C_MSR_EPF_MASK 0x100u
5462 #define LPI2C_MSR_EPF_SHIFT 8u
5463 #define LPI2C_MSR_EPF_WIDTH 1u
5464 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
5465 #define LPI2C_MSR_SDF_MASK 0x200u
5466 #define LPI2C_MSR_SDF_SHIFT 9u
5467 #define LPI2C_MSR_SDF_WIDTH 1u
5468 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
5469 #define LPI2C_MSR_NDF_MASK 0x400u
5470 #define LPI2C_MSR_NDF_SHIFT 10u
5471 #define LPI2C_MSR_NDF_WIDTH 1u
5472 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
5473 #define LPI2C_MSR_ALF_MASK 0x800u
5474 #define LPI2C_MSR_ALF_SHIFT 11u
5475 #define LPI2C_MSR_ALF_WIDTH 1u
5476 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
5477 #define LPI2C_MSR_FEF_MASK 0x1000u
5478 #define LPI2C_MSR_FEF_SHIFT 12u
5479 #define LPI2C_MSR_FEF_WIDTH 1u
5480 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
5481 #define LPI2C_MSR_PLTF_MASK 0x2000u
5482 #define LPI2C_MSR_PLTF_SHIFT 13u
5483 #define LPI2C_MSR_PLTF_WIDTH 1u
5484 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
5485 #define LPI2C_MSR_DMF_MASK 0x4000u
5486 #define LPI2C_MSR_DMF_SHIFT 14u
5487 #define LPI2C_MSR_DMF_WIDTH 1u
5488 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
5489 #define LPI2C_MSR_MBF_MASK 0x1000000u
5490 #define LPI2C_MSR_MBF_SHIFT 24u
5491 #define LPI2C_MSR_MBF_WIDTH 1u
5492 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
5493 #define LPI2C_MSR_BBF_MASK 0x2000000u
5494 #define LPI2C_MSR_BBF_SHIFT 25u
5495 #define LPI2C_MSR_BBF_WIDTH 1u
5496 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
5497 /* MIER Bit Fields */
5498 #define LPI2C_MIER_TDIE_MASK 0x1u
5499 #define LPI2C_MIER_TDIE_SHIFT 0u
5500 #define LPI2C_MIER_TDIE_WIDTH 1u
5501 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
5502 #define LPI2C_MIER_RDIE_MASK 0x2u
5503 #define LPI2C_MIER_RDIE_SHIFT 1u
5504 #define LPI2C_MIER_RDIE_WIDTH 1u
5505 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
5506 #define LPI2C_MIER_EPIE_MASK 0x100u
5507 #define LPI2C_MIER_EPIE_SHIFT 8u
5508 #define LPI2C_MIER_EPIE_WIDTH 1u
5509 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
5510 #define LPI2C_MIER_SDIE_MASK 0x200u
5511 #define LPI2C_MIER_SDIE_SHIFT 9u
5512 #define LPI2C_MIER_SDIE_WIDTH 1u
5513 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
5514 #define LPI2C_MIER_NDIE_MASK 0x400u
5515 #define LPI2C_MIER_NDIE_SHIFT 10u
5516 #define LPI2C_MIER_NDIE_WIDTH 1u
5517 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
5518 #define LPI2C_MIER_ALIE_MASK 0x800u
5519 #define LPI2C_MIER_ALIE_SHIFT 11u
5520 #define LPI2C_MIER_ALIE_WIDTH 1u
5521 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
5522 #define LPI2C_MIER_FEIE_MASK 0x1000u
5523 #define LPI2C_MIER_FEIE_SHIFT 12u
5524 #define LPI2C_MIER_FEIE_WIDTH 1u
5525 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
5526 #define LPI2C_MIER_PLTIE_MASK 0x2000u
5527 #define LPI2C_MIER_PLTIE_SHIFT 13u
5528 #define LPI2C_MIER_PLTIE_WIDTH 1u
5529 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
5530 #define LPI2C_MIER_DMIE_MASK 0x4000u
5531 #define LPI2C_MIER_DMIE_SHIFT 14u
5532 #define LPI2C_MIER_DMIE_WIDTH 1u
5533 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
5534 /* MDER Bit Fields */
5535 #define LPI2C_MDER_TDDE_MASK 0x1u
5536 #define LPI2C_MDER_TDDE_SHIFT 0u
5537 #define LPI2C_MDER_TDDE_WIDTH 1u
5538 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
5539 #define LPI2C_MDER_RDDE_MASK 0x2u
5540 #define LPI2C_MDER_RDDE_SHIFT 1u
5541 #define LPI2C_MDER_RDDE_WIDTH 1u
5542 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
5543 /* MCFGR0 Bit Fields */
5544 #define LPI2C_MCFGR0_HREN_MASK 0x1u
5545 #define LPI2C_MCFGR0_HREN_SHIFT 0u
5546 #define LPI2C_MCFGR0_HREN_WIDTH 1u
5547 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
5548 #define LPI2C_MCFGR0_HRPOL_MASK 0x2u
5549 #define LPI2C_MCFGR0_HRPOL_SHIFT 1u
5550 #define LPI2C_MCFGR0_HRPOL_WIDTH 1u
5551 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
5552 #define LPI2C_MCFGR0_HRSEL_MASK 0x4u
5553 #define LPI2C_MCFGR0_HRSEL_SHIFT 2u
5554 #define LPI2C_MCFGR0_HRSEL_WIDTH 1u
5555 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
5556 #define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
5557 #define LPI2C_MCFGR0_CIRFIFO_SHIFT 8u
5558 #define LPI2C_MCFGR0_CIRFIFO_WIDTH 1u
5559 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
5560 #define LPI2C_MCFGR0_RDMO_MASK 0x200u
5561 #define LPI2C_MCFGR0_RDMO_SHIFT 9u
5562 #define LPI2C_MCFGR0_RDMO_WIDTH 1u
5563 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
5564 /* MCFGR1 Bit Fields */
5565 #define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
5566 #define LPI2C_MCFGR1_PRESCALE_SHIFT 0u
5567 #define LPI2C_MCFGR1_PRESCALE_WIDTH 3u
5568 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
5569 #define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
5570 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8u
5571 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1u
5572 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
5573 #define LPI2C_MCFGR1_IGNACK_MASK 0x200u
5574 #define LPI2C_MCFGR1_IGNACK_SHIFT 9u
5575 #define LPI2C_MCFGR1_IGNACK_WIDTH 1u
5576 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
5577 #define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
5578 #define LPI2C_MCFGR1_TIMECFG_SHIFT 10u
5579 #define LPI2C_MCFGR1_TIMECFG_WIDTH 1u
5580 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
5581 #define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
5582 #define LPI2C_MCFGR1_MATCFG_SHIFT 16u
5583 #define LPI2C_MCFGR1_MATCFG_WIDTH 3u
5584 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
5585 #define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
5586 #define LPI2C_MCFGR1_PINCFG_SHIFT 24u
5587 #define LPI2C_MCFGR1_PINCFG_WIDTH 3u
5588 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
5589 /* MCFGR2 Bit Fields */
5590 #define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
5591 #define LPI2C_MCFGR2_BUSIDLE_SHIFT 0u
5592 #define LPI2C_MCFGR2_BUSIDLE_WIDTH 12u
5593 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
5594 #define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
5595 #define LPI2C_MCFGR2_FILTSCL_SHIFT 16u
5596 #define LPI2C_MCFGR2_FILTSCL_WIDTH 4u
5597 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
5598 #define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
5599 #define LPI2C_MCFGR2_FILTSDA_SHIFT 24u
5600 #define LPI2C_MCFGR2_FILTSDA_WIDTH 4u
5601 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
5602 /* MCFGR3 Bit Fields */
5603 #define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
5604 #define LPI2C_MCFGR3_PINLOW_SHIFT 8u
5605 #define LPI2C_MCFGR3_PINLOW_WIDTH 12u
5606 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
5607 /* MDMR Bit Fields */
5608 #define LPI2C_MDMR_MATCH0_MASK 0xFFu
5609 #define LPI2C_MDMR_MATCH0_SHIFT 0u
5610 #define LPI2C_MDMR_MATCH0_WIDTH 8u
5611 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
5612 #define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
5613 #define LPI2C_MDMR_MATCH1_SHIFT 16u
5614 #define LPI2C_MDMR_MATCH1_WIDTH 8u
5615 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
5616 /* MCCR0 Bit Fields */
5617 #define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
5618 #define LPI2C_MCCR0_CLKLO_SHIFT 0u
5619 #define LPI2C_MCCR0_CLKLO_WIDTH 6u
5620 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
5621 #define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
5622 #define LPI2C_MCCR0_CLKHI_SHIFT 8u
5623 #define LPI2C_MCCR0_CLKHI_WIDTH 6u
5624 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
5625 #define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
5626 #define LPI2C_MCCR0_SETHOLD_SHIFT 16u
5627 #define LPI2C_MCCR0_SETHOLD_WIDTH 6u
5628 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
5629 #define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
5630 #define LPI2C_MCCR0_DATAVD_SHIFT 24u
5631 #define LPI2C_MCCR0_DATAVD_WIDTH 6u
5632 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
5633 /* MCCR1 Bit Fields */
5634 #define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
5635 #define LPI2C_MCCR1_CLKLO_SHIFT 0u
5636 #define LPI2C_MCCR1_CLKLO_WIDTH 6u
5637 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
5638 #define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
5639 #define LPI2C_MCCR1_CLKHI_SHIFT 8u
5640 #define LPI2C_MCCR1_CLKHI_WIDTH 6u
5641 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
5642 #define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
5643 #define LPI2C_MCCR1_SETHOLD_SHIFT 16u
5644 #define LPI2C_MCCR1_SETHOLD_WIDTH 6u
5645 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
5646 #define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
5647 #define LPI2C_MCCR1_DATAVD_SHIFT 24u
5648 #define LPI2C_MCCR1_DATAVD_WIDTH 6u
5649 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
5650 /* MFCR Bit Fields */
5651 #define LPI2C_MFCR_TXWATER_MASK 0x3u
5652 #define LPI2C_MFCR_TXWATER_SHIFT 0u
5653 #define LPI2C_MFCR_TXWATER_WIDTH 2u
5654 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
5655 #define LPI2C_MFCR_RXWATER_MASK 0x30000u
5656 #define LPI2C_MFCR_RXWATER_SHIFT 16u
5657 #define LPI2C_MFCR_RXWATER_WIDTH 2u
5658 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
5659 /* MFSR Bit Fields */
5660 #define LPI2C_MFSR_TXCOUNT_MASK 0x7u
5661 #define LPI2C_MFSR_TXCOUNT_SHIFT 0u
5662 #define LPI2C_MFSR_TXCOUNT_WIDTH 3u
5663 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
5664 #define LPI2C_MFSR_RXCOUNT_MASK 0x70000u
5665 #define LPI2C_MFSR_RXCOUNT_SHIFT 16u
5666 #define LPI2C_MFSR_RXCOUNT_WIDTH 3u
5667 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
5668 /* MTDR Bit Fields */
5669 #define LPI2C_MTDR_DATA_MASK 0xFFu
5670 #define LPI2C_MTDR_DATA_SHIFT 0u
5671 #define LPI2C_MTDR_DATA_WIDTH 8u
5672 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
5673 #define LPI2C_MTDR_CMD_MASK 0x700u
5674 #define LPI2C_MTDR_CMD_SHIFT 8u
5675 #define LPI2C_MTDR_CMD_WIDTH 3u
5676 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
5677 /* MRDR Bit Fields */
5678 #define LPI2C_MRDR_DATA_MASK 0xFFu
5679 #define LPI2C_MRDR_DATA_SHIFT 0u
5680 #define LPI2C_MRDR_DATA_WIDTH 8u
5681 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
5682 #define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
5683 #define LPI2C_MRDR_RXEMPTY_SHIFT 14u
5684 #define LPI2C_MRDR_RXEMPTY_WIDTH 1u
5685 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
5686 /* SCR Bit Fields */
5687 #define LPI2C_SCR_SEN_MASK 0x1u
5688 #define LPI2C_SCR_SEN_SHIFT 0u
5689 #define LPI2C_SCR_SEN_WIDTH 1u
5690 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
5691 #define LPI2C_SCR_RST_MASK 0x2u
5692 #define LPI2C_SCR_RST_SHIFT 1u
5693 #define LPI2C_SCR_RST_WIDTH 1u
5694 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
5695 #define LPI2C_SCR_FILTEN_MASK 0x10u
5696 #define LPI2C_SCR_FILTEN_SHIFT 4u
5697 #define LPI2C_SCR_FILTEN_WIDTH 1u
5698 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
5699 #define LPI2C_SCR_FILTDZ_MASK 0x20u
5700 #define LPI2C_SCR_FILTDZ_SHIFT 5u
5701 #define LPI2C_SCR_FILTDZ_WIDTH 1u
5702 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
5703 /* SSR Bit Fields */
5704 #define LPI2C_SSR_TDF_MASK 0x1u
5705 #define LPI2C_SSR_TDF_SHIFT 0u
5706 #define LPI2C_SSR_TDF_WIDTH 1u
5707 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
5708 #define LPI2C_SSR_RDF_MASK 0x2u
5709 #define LPI2C_SSR_RDF_SHIFT 1u
5710 #define LPI2C_SSR_RDF_WIDTH 1u
5711 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
5712 #define LPI2C_SSR_AVF_MASK 0x4u
5713 #define LPI2C_SSR_AVF_SHIFT 2u
5714 #define LPI2C_SSR_AVF_WIDTH 1u
5715 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
5716 #define LPI2C_SSR_TAF_MASK 0x8u
5717 #define LPI2C_SSR_TAF_SHIFT 3u
5718 #define LPI2C_SSR_TAF_WIDTH 1u
5719 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
5720 #define LPI2C_SSR_RSF_MASK 0x100u
5721 #define LPI2C_SSR_RSF_SHIFT 8u
5722 #define LPI2C_SSR_RSF_WIDTH 1u
5723 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
5724 #define LPI2C_SSR_SDF_MASK 0x200u
5725 #define LPI2C_SSR_SDF_SHIFT 9u
5726 #define LPI2C_SSR_SDF_WIDTH 1u
5727 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
5728 #define LPI2C_SSR_BEF_MASK 0x400u
5729 #define LPI2C_SSR_BEF_SHIFT 10u
5730 #define LPI2C_SSR_BEF_WIDTH 1u
5731 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
5732 #define LPI2C_SSR_FEF_MASK 0x800u
5733 #define LPI2C_SSR_FEF_SHIFT 11u
5734 #define LPI2C_SSR_FEF_WIDTH 1u
5735 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
5736 #define LPI2C_SSR_AM0F_MASK 0x1000u
5737 #define LPI2C_SSR_AM0F_SHIFT 12u
5738 #define LPI2C_SSR_AM0F_WIDTH 1u
5739 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
5740 #define LPI2C_SSR_AM1F_MASK 0x2000u
5741 #define LPI2C_SSR_AM1F_SHIFT 13u
5742 #define LPI2C_SSR_AM1F_WIDTH 1u
5743 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
5744 #define LPI2C_SSR_GCF_MASK 0x4000u
5745 #define LPI2C_SSR_GCF_SHIFT 14u
5746 #define LPI2C_SSR_GCF_WIDTH 1u
5747 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
5748 #define LPI2C_SSR_SARF_MASK 0x8000u
5749 #define LPI2C_SSR_SARF_SHIFT 15u
5750 #define LPI2C_SSR_SARF_WIDTH 1u
5751 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
5752 #define LPI2C_SSR_SBF_MASK 0x1000000u
5753 #define LPI2C_SSR_SBF_SHIFT 24u
5754 #define LPI2C_SSR_SBF_WIDTH 1u
5755 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
5756 #define LPI2C_SSR_BBF_MASK 0x2000000u
5757 #define LPI2C_SSR_BBF_SHIFT 25u
5758 #define LPI2C_SSR_BBF_WIDTH 1u
5759 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
5760 /* SIER Bit Fields */
5761 #define LPI2C_SIER_TDIE_MASK 0x1u
5762 #define LPI2C_SIER_TDIE_SHIFT 0u
5763 #define LPI2C_SIER_TDIE_WIDTH 1u
5764 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
5765 #define LPI2C_SIER_RDIE_MASK 0x2u
5766 #define LPI2C_SIER_RDIE_SHIFT 1u
5767 #define LPI2C_SIER_RDIE_WIDTH 1u
5768 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
5769 #define LPI2C_SIER_AVIE_MASK 0x4u
5770 #define LPI2C_SIER_AVIE_SHIFT 2u
5771 #define LPI2C_SIER_AVIE_WIDTH 1u
5772 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
5773 #define LPI2C_SIER_TAIE_MASK 0x8u
5774 #define LPI2C_SIER_TAIE_SHIFT 3u
5775 #define LPI2C_SIER_TAIE_WIDTH 1u
5776 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
5777 #define LPI2C_SIER_RSIE_MASK 0x100u
5778 #define LPI2C_SIER_RSIE_SHIFT 8u
5779 #define LPI2C_SIER_RSIE_WIDTH 1u
5780 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
5781 #define LPI2C_SIER_SDIE_MASK 0x200u
5782 #define LPI2C_SIER_SDIE_SHIFT 9u
5783 #define LPI2C_SIER_SDIE_WIDTH 1u
5784 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
5785 #define LPI2C_SIER_BEIE_MASK 0x400u
5786 #define LPI2C_SIER_BEIE_SHIFT 10u
5787 #define LPI2C_SIER_BEIE_WIDTH 1u
5788 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
5789 #define LPI2C_SIER_FEIE_MASK 0x800u
5790 #define LPI2C_SIER_FEIE_SHIFT 11u
5791 #define LPI2C_SIER_FEIE_WIDTH 1u
5792 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
5793 #define LPI2C_SIER_AM0IE_MASK 0x1000u
5794 #define LPI2C_SIER_AM0IE_SHIFT 12u
5795 #define LPI2C_SIER_AM0IE_WIDTH 1u
5796 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
5797 #define LPI2C_SIER_AM1F_MASK 0x2000u
5798 #define LPI2C_SIER_AM1F_SHIFT 13u
5799 #define LPI2C_SIER_AM1F_WIDTH 1u
5800 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
5801 #define LPI2C_SIER_GCIE_MASK 0x4000u
5802 #define LPI2C_SIER_GCIE_SHIFT 14u
5803 #define LPI2C_SIER_GCIE_WIDTH 1u
5804 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
5805 #define LPI2C_SIER_SARIE_MASK 0x8000u
5806 #define LPI2C_SIER_SARIE_SHIFT 15u
5807 #define LPI2C_SIER_SARIE_WIDTH 1u
5808 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
5809 /* SDER Bit Fields */
5810 #define LPI2C_SDER_TDDE_MASK 0x1u
5811 #define LPI2C_SDER_TDDE_SHIFT 0u
5812 #define LPI2C_SDER_TDDE_WIDTH 1u
5813 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
5814 #define LPI2C_SDER_RDDE_MASK 0x2u
5815 #define LPI2C_SDER_RDDE_SHIFT 1u
5816 #define LPI2C_SDER_RDDE_WIDTH 1u
5817 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
5818 #define LPI2C_SDER_AVDE_MASK 0x4u
5819 #define LPI2C_SDER_AVDE_SHIFT 2u
5820 #define LPI2C_SDER_AVDE_WIDTH 1u
5821 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
5822 /* SCFGR1 Bit Fields */
5823 #define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
5824 #define LPI2C_SCFGR1_ADRSTALL_SHIFT 0u
5825 #define LPI2C_SCFGR1_ADRSTALL_WIDTH 1u
5826 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
5827 #define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
5828 #define LPI2C_SCFGR1_RXSTALL_SHIFT 1u
5829 #define LPI2C_SCFGR1_RXSTALL_WIDTH 1u
5830 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
5831 #define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
5832 #define LPI2C_SCFGR1_TXDSTALL_SHIFT 2u
5833 #define LPI2C_SCFGR1_TXDSTALL_WIDTH 1u
5834 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
5835 #define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
5836 #define LPI2C_SCFGR1_ACKSTALL_SHIFT 3u
5837 #define LPI2C_SCFGR1_ACKSTALL_WIDTH 1u
5838 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
5839 #define LPI2C_SCFGR1_GCEN_MASK 0x100u
5840 #define LPI2C_SCFGR1_GCEN_SHIFT 8u
5841 #define LPI2C_SCFGR1_GCEN_WIDTH 1u
5842 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
5843 #define LPI2C_SCFGR1_SAEN_MASK 0x200u
5844 #define LPI2C_SCFGR1_SAEN_SHIFT 9u
5845 #define LPI2C_SCFGR1_SAEN_WIDTH 1u
5846 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
5847 #define LPI2C_SCFGR1_TXCFG_MASK 0x400u
5848 #define LPI2C_SCFGR1_TXCFG_SHIFT 10u
5849 #define LPI2C_SCFGR1_TXCFG_WIDTH 1u
5850 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
5851 #define LPI2C_SCFGR1_RXCFG_MASK 0x800u
5852 #define LPI2C_SCFGR1_RXCFG_SHIFT 11u
5853 #define LPI2C_SCFGR1_RXCFG_WIDTH 1u
5854 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
5855 #define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
5856 #define LPI2C_SCFGR1_IGNACK_SHIFT 12u
5857 #define LPI2C_SCFGR1_IGNACK_WIDTH 1u
5858 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
5859 #define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
5860 #define LPI2C_SCFGR1_HSMEN_SHIFT 13u
5861 #define LPI2C_SCFGR1_HSMEN_WIDTH 1u
5862 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
5863 #define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
5864 #define LPI2C_SCFGR1_ADDRCFG_SHIFT 16u
5865 #define LPI2C_SCFGR1_ADDRCFG_WIDTH 3u
5866 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
5867 /* SCFGR2 Bit Fields */
5868 #define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
5869 #define LPI2C_SCFGR2_CLKHOLD_SHIFT 0u
5870 #define LPI2C_SCFGR2_CLKHOLD_WIDTH 4u
5871 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
5872 #define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
5873 #define LPI2C_SCFGR2_DATAVD_SHIFT 8u
5874 #define LPI2C_SCFGR2_DATAVD_WIDTH 6u
5875 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
5876 #define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
5877 #define LPI2C_SCFGR2_FILTSCL_SHIFT 16u
5878 #define LPI2C_SCFGR2_FILTSCL_WIDTH 4u
5879 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
5880 #define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
5881 #define LPI2C_SCFGR2_FILTSDA_SHIFT 24u
5882 #define LPI2C_SCFGR2_FILTSDA_WIDTH 4u
5883 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
5884 /* SAMR Bit Fields */
5885 #define LPI2C_SAMR_ADDR0_MASK 0x7FEu
5886 #define LPI2C_SAMR_ADDR0_SHIFT 1u
5887 #define LPI2C_SAMR_ADDR0_WIDTH 10u
5888 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
5889 #define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
5890 #define LPI2C_SAMR_ADDR1_SHIFT 17u
5891 #define LPI2C_SAMR_ADDR1_WIDTH 10u
5892 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
5893 /* SASR Bit Fields */
5894 #define LPI2C_SASR_RADDR_MASK 0x7FFu
5895 #define LPI2C_SASR_RADDR_SHIFT 0u
5896 #define LPI2C_SASR_RADDR_WIDTH 11u
5897 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
5898 #define LPI2C_SASR_ANV_MASK 0x4000u
5899 #define LPI2C_SASR_ANV_SHIFT 14u
5900 #define LPI2C_SASR_ANV_WIDTH 1u
5901 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
5902 /* STAR Bit Fields */
5903 #define LPI2C_STAR_TXNACK_MASK 0x1u
5904 #define LPI2C_STAR_TXNACK_SHIFT 0u
5905 #define LPI2C_STAR_TXNACK_WIDTH 1u
5906 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
5907 /* STDR Bit Fields */
5908 #define LPI2C_STDR_DATA_MASK 0xFFu
5909 #define LPI2C_STDR_DATA_SHIFT 0u
5910 #define LPI2C_STDR_DATA_WIDTH 8u
5911 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
5912 /* SRDR Bit Fields */
5913 #define LPI2C_SRDR_DATA_MASK 0xFFu
5914 #define LPI2C_SRDR_DATA_SHIFT 0u
5915 #define LPI2C_SRDR_DATA_WIDTH 8u
5916 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
5917 #define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
5918 #define LPI2C_SRDR_RXEMPTY_SHIFT 14u
5919 #define LPI2C_SRDR_RXEMPTY_WIDTH 1u
5920 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
5921 #define LPI2C_SRDR_SOF_MASK 0x8000u
5922 #define LPI2C_SRDR_SOF_SHIFT 15u
5923 #define LPI2C_SRDR_SOF_WIDTH 1u
5924 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
5925  /* end of group LPI2C_Register_Masks */
5929 
5930  /* end of group LPI2C_Peripheral_Access_Layer */
5934 
5935 
5936 /* ----------------------------------------------------------------------------
5937  -- LPIT Peripheral Access Layer
5938  ---------------------------------------------------------------------------- */
5939 
5947 #define LPIT_TMR_COUNT 4u
5948 
5950 typedef struct {
5951  __I uint32_t VERID;
5952  __I uint32_t PARAM;
5953  __IO uint32_t MCR;
5954  __IO uint32_t MSR;
5955  __IO uint32_t MIER;
5956  __IO uint32_t SETTEN;
5957  __IO uint32_t CLRTEN;
5958  uint8_t RESERVED_0[4];
5959  struct { /* offset: 0x20, array step: 0x10 */
5960  __IO uint32_t TVAL;
5961  __I uint32_t CVAL;
5962  __IO uint32_t TCTRL;
5963  uint8_t RESERVED_0[4];
5964  } TMR[LPIT_TMR_COUNT];
5966 
5968 #define LPIT_INSTANCE_COUNT (1u)
5969 
5970 
5971 /* LPIT - Peripheral instance base addresses */
5973 #define LPIT0_BASE (0x40037000u)
5974 
5975 #define LPIT0 ((LPIT_Type *)LPIT0_BASE)
5976 
5977 #define LPIT_BASE_ADDRS { LPIT0_BASE }
5978 
5979 #define LPIT_BASE_PTRS { LPIT0 }
5980 
5981 #define LPIT_IRQS_ARR_COUNT (1u)
5982 
5983 #define LPIT_IRQS_CH_COUNT (4u)
5984 
5985 #define LPIT_IRQS { LPIT0_Ch0_IRQn, LPIT0_Ch1_IRQn, LPIT0_Ch2_IRQn, LPIT0_Ch3_IRQn }
5986 
5987 /* ----------------------------------------------------------------------------
5988  -- LPIT Register Masks
5989  ---------------------------------------------------------------------------- */
5990 
5996 /* VERID Bit Fields */
5997 #define LPIT_VERID_FEATURE_MASK 0xFFFFu
5998 #define LPIT_VERID_FEATURE_SHIFT 0u
5999 #define LPIT_VERID_FEATURE_WIDTH 16u
6000 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_FEATURE_SHIFT))&LPIT_VERID_FEATURE_MASK)
6001 #define LPIT_VERID_MINOR_MASK 0xFF0000u
6002 #define LPIT_VERID_MINOR_SHIFT 16u
6003 #define LPIT_VERID_MINOR_WIDTH 8u
6004 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MINOR_SHIFT))&LPIT_VERID_MINOR_MASK)
6005 #define LPIT_VERID_MAJOR_MASK 0xFF000000u
6006 #define LPIT_VERID_MAJOR_SHIFT 24u
6007 #define LPIT_VERID_MAJOR_WIDTH 8u
6008 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MAJOR_SHIFT))&LPIT_VERID_MAJOR_MASK)
6009 /* PARAM Bit Fields */
6010 #define LPIT_PARAM_CHANNEL_MASK 0xFFu
6011 #define LPIT_PARAM_CHANNEL_SHIFT 0u
6012 #define LPIT_PARAM_CHANNEL_WIDTH 8u
6013 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_CHANNEL_SHIFT))&LPIT_PARAM_CHANNEL_MASK)
6014 #define LPIT_PARAM_EXT_TRIG_MASK 0xFF00u
6015 #define LPIT_PARAM_EXT_TRIG_SHIFT 8u
6016 #define LPIT_PARAM_EXT_TRIG_WIDTH 8u
6017 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_EXT_TRIG_SHIFT))&LPIT_PARAM_EXT_TRIG_MASK)
6018 /* MCR Bit Fields */
6019 #define LPIT_MCR_M_CEN_MASK 0x1u
6020 #define LPIT_MCR_M_CEN_SHIFT 0u
6021 #define LPIT_MCR_M_CEN_WIDTH 1u
6022 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_M_CEN_SHIFT))&LPIT_MCR_M_CEN_MASK)
6023 #define LPIT_MCR_SW_RST_MASK 0x2u
6024 #define LPIT_MCR_SW_RST_SHIFT 1u
6025 #define LPIT_MCR_SW_RST_WIDTH 1u
6026 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_SW_RST_SHIFT))&LPIT_MCR_SW_RST_MASK)
6027 #define LPIT_MCR_DOZE_EN_MASK 0x4u
6028 #define LPIT_MCR_DOZE_EN_SHIFT 2u
6029 #define LPIT_MCR_DOZE_EN_WIDTH 1u
6030 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DOZE_EN_SHIFT))&LPIT_MCR_DOZE_EN_MASK)
6031 #define LPIT_MCR_DBG_EN_MASK 0x8u
6032 #define LPIT_MCR_DBG_EN_SHIFT 3u
6033 #define LPIT_MCR_DBG_EN_WIDTH 1u
6034 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DBG_EN_SHIFT))&LPIT_MCR_DBG_EN_MASK)
6035 /* MSR Bit Fields */
6036 #define LPIT_MSR_TIF0_MASK 0x1u
6037 #define LPIT_MSR_TIF0_SHIFT 0u
6038 #define LPIT_MSR_TIF0_WIDTH 1u
6039 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF0_SHIFT))&LPIT_MSR_TIF0_MASK)
6040 #define LPIT_MSR_TIF1_MASK 0x2u
6041 #define LPIT_MSR_TIF1_SHIFT 1u
6042 #define LPIT_MSR_TIF1_WIDTH 1u
6043 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF1_SHIFT))&LPIT_MSR_TIF1_MASK)
6044 #define LPIT_MSR_TIF2_MASK 0x4u
6045 #define LPIT_MSR_TIF2_SHIFT 2u
6046 #define LPIT_MSR_TIF2_WIDTH 1u
6047 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF2_SHIFT))&LPIT_MSR_TIF2_MASK)
6048 #define LPIT_MSR_TIF3_MASK 0x8u
6049 #define LPIT_MSR_TIF3_SHIFT 3u
6050 #define LPIT_MSR_TIF3_WIDTH 1u
6051 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF3_SHIFT))&LPIT_MSR_TIF3_MASK)
6052 /* MIER Bit Fields */
6053 #define LPIT_MIER_TIE0_MASK 0x1u
6054 #define LPIT_MIER_TIE0_SHIFT 0u
6055 #define LPIT_MIER_TIE0_WIDTH 1u
6056 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE0_SHIFT))&LPIT_MIER_TIE0_MASK)
6057 #define LPIT_MIER_TIE1_MASK 0x2u
6058 #define LPIT_MIER_TIE1_SHIFT 1u
6059 #define LPIT_MIER_TIE1_WIDTH 1u
6060 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE1_SHIFT))&LPIT_MIER_TIE1_MASK)
6061 #define LPIT_MIER_TIE2_MASK 0x4u
6062 #define LPIT_MIER_TIE2_SHIFT 2u
6063 #define LPIT_MIER_TIE2_WIDTH 1u
6064 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE2_SHIFT))&LPIT_MIER_TIE2_MASK)
6065 #define LPIT_MIER_TIE3_MASK 0x8u
6066 #define LPIT_MIER_TIE3_SHIFT 3u
6067 #define LPIT_MIER_TIE3_WIDTH 1u
6068 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE3_SHIFT))&LPIT_MIER_TIE3_MASK)
6069 /* SETTEN Bit Fields */
6070 #define LPIT_SETTEN_SET_T_EN_0_MASK 0x1u
6071 #define LPIT_SETTEN_SET_T_EN_0_SHIFT 0u
6072 #define LPIT_SETTEN_SET_T_EN_0_WIDTH 1u
6073 #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_0_SHIFT))&LPIT_SETTEN_SET_T_EN_0_MASK)
6074 #define LPIT_SETTEN_SET_T_EN_1_MASK 0x2u
6075 #define LPIT_SETTEN_SET_T_EN_1_SHIFT 1u
6076 #define LPIT_SETTEN_SET_T_EN_1_WIDTH 1u
6077 #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_1_SHIFT))&LPIT_SETTEN_SET_T_EN_1_MASK)
6078 #define LPIT_SETTEN_SET_T_EN_2_MASK 0x4u
6079 #define LPIT_SETTEN_SET_T_EN_2_SHIFT 2u
6080 #define LPIT_SETTEN_SET_T_EN_2_WIDTH 1u
6081 #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_2_SHIFT))&LPIT_SETTEN_SET_T_EN_2_MASK)
6082 #define LPIT_SETTEN_SET_T_EN_3_MASK 0x8u
6083 #define LPIT_SETTEN_SET_T_EN_3_SHIFT 3u
6084 #define LPIT_SETTEN_SET_T_EN_3_WIDTH 1u
6085 #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_3_SHIFT))&LPIT_SETTEN_SET_T_EN_3_MASK)
6086 /* CLRTEN Bit Fields */
6087 #define LPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
6088 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
6089 #define LPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
6090 #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_0_SHIFT))&LPIT_CLRTEN_CLR_T_EN_0_MASK)
6091 #define LPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
6092 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
6093 #define LPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
6094 #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_1_SHIFT))&LPIT_CLRTEN_CLR_T_EN_1_MASK)
6095 #define LPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
6096 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
6097 #define LPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
6098 #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_2_SHIFT))&LPIT_CLRTEN_CLR_T_EN_2_MASK)
6099 #define LPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
6100 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
6101 #define LPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
6102 #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_3_SHIFT))&LPIT_CLRTEN_CLR_T_EN_3_MASK)
6103 /* TMR_TVAL Bit Fields */
6104 #define LPIT_TMR_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
6105 #define LPIT_TMR_TVAL_TMR_VAL_SHIFT 0u
6106 #define LPIT_TMR_TVAL_TMR_VAL_WIDTH 32u
6107 #define LPIT_TMR_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TVAL_TMR_VAL_SHIFT))&LPIT_TMR_TVAL_TMR_VAL_MASK)
6108 /* TMR_CVAL Bit Fields */
6109 #define LPIT_TMR_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
6110 #define LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT 0u
6111 #define LPIT_TMR_CVAL_TMR_CUR_VAL_WIDTH 32u
6112 #define LPIT_TMR_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT))&LPIT_TMR_CVAL_TMR_CUR_VAL_MASK)
6113 /* TMR_TCTRL Bit Fields */
6114 #define LPIT_TMR_TCTRL_T_EN_MASK 0x1u
6115 #define LPIT_TMR_TCTRL_T_EN_SHIFT 0u
6116 #define LPIT_TMR_TCTRL_T_EN_WIDTH 1u
6117 #define LPIT_TMR_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_T_EN_SHIFT))&LPIT_TMR_TCTRL_T_EN_MASK)
6118 #define LPIT_TMR_TCTRL_CHAIN_MASK 0x2u
6119 #define LPIT_TMR_TCTRL_CHAIN_SHIFT 1u
6120 #define LPIT_TMR_TCTRL_CHAIN_WIDTH 1u
6121 #define LPIT_TMR_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_CHAIN_SHIFT))&LPIT_TMR_TCTRL_CHAIN_MASK)
6122 #define LPIT_TMR_TCTRL_MODE_MASK 0xCu
6123 #define LPIT_TMR_TCTRL_MODE_SHIFT 2u
6124 #define LPIT_TMR_TCTRL_MODE_WIDTH 2u
6125 #define LPIT_TMR_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_MODE_SHIFT))&LPIT_TMR_TCTRL_MODE_MASK)
6126 #define LPIT_TMR_TCTRL_TSOT_MASK 0x10000u
6127 #define LPIT_TMR_TCTRL_TSOT_SHIFT 16u
6128 #define LPIT_TMR_TCTRL_TSOT_WIDTH 1u
6129 #define LPIT_TMR_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOT_SHIFT))&LPIT_TMR_TCTRL_TSOT_MASK)
6130 #define LPIT_TMR_TCTRL_TSOI_MASK 0x20000u
6131 #define LPIT_TMR_TCTRL_TSOI_SHIFT 17u
6132 #define LPIT_TMR_TCTRL_TSOI_WIDTH 1u
6133 #define LPIT_TMR_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOI_SHIFT))&LPIT_TMR_TCTRL_TSOI_MASK)
6134 #define LPIT_TMR_TCTRL_TROT_MASK 0x40000u
6135 #define LPIT_TMR_TCTRL_TROT_SHIFT 18u
6136 #define LPIT_TMR_TCTRL_TROT_WIDTH 1u
6137 #define LPIT_TMR_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TROT_SHIFT))&LPIT_TMR_TCTRL_TROT_MASK)
6138 #define LPIT_TMR_TCTRL_TRG_SRC_MASK 0x800000u
6139 #define LPIT_TMR_TCTRL_TRG_SRC_SHIFT 23u
6140 #define LPIT_TMR_TCTRL_TRG_SRC_WIDTH 1u
6141 #define LPIT_TMR_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SRC_SHIFT))&LPIT_TMR_TCTRL_TRG_SRC_MASK)
6142 #define LPIT_TMR_TCTRL_TRG_SEL_MASK 0xF000000u
6143 #define LPIT_TMR_TCTRL_TRG_SEL_SHIFT 24u
6144 #define LPIT_TMR_TCTRL_TRG_SEL_WIDTH 4u
6145 #define LPIT_TMR_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SEL_SHIFT))&LPIT_TMR_TCTRL_TRG_SEL_MASK)
6146  /* end of group LPIT_Register_Masks */
6150 
6151  /* end of group LPIT_Peripheral_Access_Layer */
6155 
6156 
6157 /* ----------------------------------------------------------------------------
6158  -- LPSPI Peripheral Access Layer
6159  ---------------------------------------------------------------------------- */
6160 
6170 typedef struct {
6171  __I uint32_t VERID;
6172  __I uint32_t PARAM;
6173  uint8_t RESERVED_0[8];
6174  __IO uint32_t CR;
6175  __IO uint32_t SR;
6176  __IO uint32_t IER;
6177  __IO uint32_t DER;
6178  __IO uint32_t CFGR0;
6179  __IO uint32_t CFGR1;
6180  uint8_t RESERVED_1[8];
6181  __IO uint32_t DMR0;
6182  __IO uint32_t DMR1;
6183  uint8_t RESERVED_2[8];
6184  __IO uint32_t CCR;
6185  uint8_t RESERVED_3[20];
6186  __IO uint32_t FCR;
6187  __I uint32_t FSR;
6188  __IO uint32_t TCR;
6189  __O uint32_t TDR;
6190  uint8_t RESERVED_4[8];
6191  __I uint32_t RSR;
6192  __I uint32_t RDR;
6194 
6196 #define LPSPI_INSTANCE_COUNT (3u)
6197 
6198 
6199 /* LPSPI - Peripheral instance base addresses */
6201 #define LPSPI0_BASE (0x4002C000u)
6202 
6203 #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
6204 
6205 #define LPSPI1_BASE (0x4002D000u)
6206 
6207 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
6208 
6209 #define LPSPI2_BASE (0x4002E000u)
6210 
6211 #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
6212 
6213 #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE }
6214 
6215 #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2 }
6216 
6217 #define LPSPI_IRQS_ARR_COUNT (1u)
6218 
6219 #define LPSPI_IRQS_CH_COUNT (1u)
6220 
6221 #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn }
6222 
6223 /* ----------------------------------------------------------------------------
6224  -- LPSPI Register Masks
6225  ---------------------------------------------------------------------------- */
6226 
6232 /* VERID Bit Fields */
6233 #define LPSPI_VERID_FEATURE_MASK 0xFFFFu
6234 #define LPSPI_VERID_FEATURE_SHIFT 0u
6235 #define LPSPI_VERID_FEATURE_WIDTH 16u
6236 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_FEATURE_SHIFT))&LPSPI_VERID_FEATURE_MASK)
6237 #define LPSPI_VERID_MINOR_MASK 0xFF0000u
6238 #define LPSPI_VERID_MINOR_SHIFT 16u
6239 #define LPSPI_VERID_MINOR_WIDTH 8u
6240 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MINOR_SHIFT))&LPSPI_VERID_MINOR_MASK)
6241 #define LPSPI_VERID_MAJOR_MASK 0xFF000000u
6242 #define LPSPI_VERID_MAJOR_SHIFT 24u
6243 #define LPSPI_VERID_MAJOR_WIDTH 8u
6244 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MAJOR_SHIFT))&LPSPI_VERID_MAJOR_MASK)
6245 /* PARAM Bit Fields */
6246 #define LPSPI_PARAM_TXFIFO_MASK 0xFFu
6247 #define LPSPI_PARAM_TXFIFO_SHIFT 0u
6248 #define LPSPI_PARAM_TXFIFO_WIDTH 8u
6249 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_TXFIFO_SHIFT))&LPSPI_PARAM_TXFIFO_MASK)
6250 #define LPSPI_PARAM_RXFIFO_MASK 0xFF00u
6251 #define LPSPI_PARAM_RXFIFO_SHIFT 8u
6252 #define LPSPI_PARAM_RXFIFO_WIDTH 8u
6253 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_RXFIFO_SHIFT))&LPSPI_PARAM_RXFIFO_MASK)
6254 /* CR Bit Fields */
6255 #define LPSPI_CR_MEN_MASK 0x1u
6256 #define LPSPI_CR_MEN_SHIFT 0u
6257 #define LPSPI_CR_MEN_WIDTH 1u
6258 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_MEN_SHIFT))&LPSPI_CR_MEN_MASK)
6259 #define LPSPI_CR_RST_MASK 0x2u
6260 #define LPSPI_CR_RST_SHIFT 1u
6261 #define LPSPI_CR_RST_WIDTH 1u
6262 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RST_SHIFT))&LPSPI_CR_RST_MASK)
6263 #define LPSPI_CR_DOZEN_MASK 0x4u
6264 #define LPSPI_CR_DOZEN_SHIFT 2u
6265 #define LPSPI_CR_DOZEN_WIDTH 1u
6266 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DOZEN_SHIFT))&LPSPI_CR_DOZEN_MASK)
6267 #define LPSPI_CR_DBGEN_MASK 0x8u
6268 #define LPSPI_CR_DBGEN_SHIFT 3u
6269 #define LPSPI_CR_DBGEN_WIDTH 1u
6270 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DBGEN_SHIFT))&LPSPI_CR_DBGEN_MASK)
6271 #define LPSPI_CR_RTF_MASK 0x100u
6272 #define LPSPI_CR_RTF_SHIFT 8u
6273 #define LPSPI_CR_RTF_WIDTH 1u
6274 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RTF_SHIFT))&LPSPI_CR_RTF_MASK)
6275 #define LPSPI_CR_RRF_MASK 0x200u
6276 #define LPSPI_CR_RRF_SHIFT 9u
6277 #define LPSPI_CR_RRF_WIDTH 1u
6278 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RRF_SHIFT))&LPSPI_CR_RRF_MASK)
6279 /* SR Bit Fields */
6280 #define LPSPI_SR_TDF_MASK 0x1u
6281 #define LPSPI_SR_TDF_SHIFT 0u
6282 #define LPSPI_SR_TDF_WIDTH 1u
6283 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TDF_SHIFT))&LPSPI_SR_TDF_MASK)
6284 #define LPSPI_SR_RDF_MASK 0x2u
6285 #define LPSPI_SR_RDF_SHIFT 1u
6286 #define LPSPI_SR_RDF_WIDTH 1u
6287 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_RDF_SHIFT))&LPSPI_SR_RDF_MASK)
6288 #define LPSPI_SR_WCF_MASK 0x100u
6289 #define LPSPI_SR_WCF_SHIFT 8u
6290 #define LPSPI_SR_WCF_WIDTH 1u
6291 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_WCF_SHIFT))&LPSPI_SR_WCF_MASK)
6292 #define LPSPI_SR_FCF_MASK 0x200u
6293 #define LPSPI_SR_FCF_SHIFT 9u
6294 #define LPSPI_SR_FCF_WIDTH 1u
6295 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_FCF_SHIFT))&LPSPI_SR_FCF_MASK)
6296 #define LPSPI_SR_TCF_MASK 0x400u
6297 #define LPSPI_SR_TCF_SHIFT 10u
6298 #define LPSPI_SR_TCF_WIDTH 1u
6299 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TCF_SHIFT))&LPSPI_SR_TCF_MASK)
6300 #define LPSPI_SR_TEF_MASK 0x800u
6301 #define LPSPI_SR_TEF_SHIFT 11u
6302 #define LPSPI_SR_TEF_WIDTH 1u
6303 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TEF_SHIFT))&LPSPI_SR_TEF_MASK)
6304 #define LPSPI_SR_REF_MASK 0x1000u
6305 #define LPSPI_SR_REF_SHIFT 12u
6306 #define LPSPI_SR_REF_WIDTH 1u
6307 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_REF_SHIFT))&LPSPI_SR_REF_MASK)
6308 #define LPSPI_SR_DMF_MASK 0x2000u
6309 #define LPSPI_SR_DMF_SHIFT 13u
6310 #define LPSPI_SR_DMF_WIDTH 1u
6311 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_DMF_SHIFT))&LPSPI_SR_DMF_MASK)
6312 #define LPSPI_SR_MBF_MASK 0x1000000u
6313 #define LPSPI_SR_MBF_SHIFT 24u
6314 #define LPSPI_SR_MBF_WIDTH 1u
6315 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_MBF_SHIFT))&LPSPI_SR_MBF_MASK)
6316 /* IER Bit Fields */
6317 #define LPSPI_IER_TDIE_MASK 0x1u
6318 #define LPSPI_IER_TDIE_SHIFT 0u
6319 #define LPSPI_IER_TDIE_WIDTH 1u
6320 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TDIE_SHIFT))&LPSPI_IER_TDIE_MASK)
6321 #define LPSPI_IER_RDIE_MASK 0x2u
6322 #define LPSPI_IER_RDIE_SHIFT 1u
6323 #define LPSPI_IER_RDIE_WIDTH 1u
6324 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_RDIE_SHIFT))&LPSPI_IER_RDIE_MASK)
6325 #define LPSPI_IER_WCIE_MASK 0x100u
6326 #define LPSPI_IER_WCIE_SHIFT 8u
6327 #define LPSPI_IER_WCIE_WIDTH 1u
6328 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_WCIE_SHIFT))&LPSPI_IER_WCIE_MASK)
6329 #define LPSPI_IER_FCIE_MASK 0x200u
6330 #define LPSPI_IER_FCIE_SHIFT 9u
6331 #define LPSPI_IER_FCIE_WIDTH 1u
6332 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_FCIE_SHIFT))&LPSPI_IER_FCIE_MASK)
6333 #define LPSPI_IER_TCIE_MASK 0x400u
6334 #define LPSPI_IER_TCIE_SHIFT 10u
6335 #define LPSPI_IER_TCIE_WIDTH 1u
6336 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TCIE_SHIFT))&LPSPI_IER_TCIE_MASK)
6337 #define LPSPI_IER_TEIE_MASK 0x800u
6338 #define LPSPI_IER_TEIE_SHIFT 11u
6339 #define LPSPI_IER_TEIE_WIDTH 1u
6340 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TEIE_SHIFT))&LPSPI_IER_TEIE_MASK)
6341 #define LPSPI_IER_REIE_MASK 0x1000u
6342 #define LPSPI_IER_REIE_SHIFT 12u
6343 #define LPSPI_IER_REIE_WIDTH 1u
6344 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_REIE_SHIFT))&LPSPI_IER_REIE_MASK)
6345 #define LPSPI_IER_DMIE_MASK 0x2000u
6346 #define LPSPI_IER_DMIE_SHIFT 13u
6347 #define LPSPI_IER_DMIE_WIDTH 1u
6348 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_DMIE_SHIFT))&LPSPI_IER_DMIE_MASK)
6349 /* DER Bit Fields */
6350 #define LPSPI_DER_TDDE_MASK 0x1u
6351 #define LPSPI_DER_TDDE_SHIFT 0u
6352 #define LPSPI_DER_TDDE_WIDTH 1u
6353 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_TDDE_SHIFT))&LPSPI_DER_TDDE_MASK)
6354 #define LPSPI_DER_RDDE_MASK 0x2u
6355 #define LPSPI_DER_RDDE_SHIFT 1u
6356 #define LPSPI_DER_RDDE_WIDTH 1u
6357 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_RDDE_SHIFT))&LPSPI_DER_RDDE_MASK)
6358 /* CFGR0 Bit Fields */
6359 #define LPSPI_CFGR0_HREN_MASK 0x1u
6360 #define LPSPI_CFGR0_HREN_SHIFT 0u
6361 #define LPSPI_CFGR0_HREN_WIDTH 1u
6362 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HREN_SHIFT))&LPSPI_CFGR0_HREN_MASK)
6363 #define LPSPI_CFGR0_HRPOL_MASK 0x2u
6364 #define LPSPI_CFGR0_HRPOL_SHIFT 1u
6365 #define LPSPI_CFGR0_HRPOL_WIDTH 1u
6366 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRPOL_SHIFT))&LPSPI_CFGR0_HRPOL_MASK)
6367 #define LPSPI_CFGR0_HRSEL_MASK 0x4u
6368 #define LPSPI_CFGR0_HRSEL_SHIFT 2u
6369 #define LPSPI_CFGR0_HRSEL_WIDTH 1u
6370 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRSEL_SHIFT))&LPSPI_CFGR0_HRSEL_MASK)
6371 #define LPSPI_CFGR0_CIRFIFO_MASK 0x100u
6372 #define LPSPI_CFGR0_CIRFIFO_SHIFT 8u
6373 #define LPSPI_CFGR0_CIRFIFO_WIDTH 1u
6374 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_CIRFIFO_SHIFT))&LPSPI_CFGR0_CIRFIFO_MASK)
6375 #define LPSPI_CFGR0_RDMO_MASK 0x200u
6376 #define LPSPI_CFGR0_RDMO_SHIFT 9u
6377 #define LPSPI_CFGR0_RDMO_WIDTH 1u
6378 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_RDMO_SHIFT))&LPSPI_CFGR0_RDMO_MASK)
6379 /* CFGR1 Bit Fields */
6380 #define LPSPI_CFGR1_MASTER_MASK 0x1u
6381 #define LPSPI_CFGR1_MASTER_SHIFT 0u
6382 #define LPSPI_CFGR1_MASTER_WIDTH 1u
6383 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MASTER_SHIFT))&LPSPI_CFGR1_MASTER_MASK)
6384 #define LPSPI_CFGR1_SAMPLE_MASK 0x2u
6385 #define LPSPI_CFGR1_SAMPLE_SHIFT 1u
6386 #define LPSPI_CFGR1_SAMPLE_WIDTH 1u
6387 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_SAMPLE_SHIFT))&LPSPI_CFGR1_SAMPLE_MASK)
6388 #define LPSPI_CFGR1_AUTOPCS_MASK 0x4u
6389 #define LPSPI_CFGR1_AUTOPCS_SHIFT 2u
6390 #define LPSPI_CFGR1_AUTOPCS_WIDTH 1u
6391 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_AUTOPCS_SHIFT))&LPSPI_CFGR1_AUTOPCS_MASK)
6392 #define LPSPI_CFGR1_NOSTALL_MASK 0x8u
6393 #define LPSPI_CFGR1_NOSTALL_SHIFT 3u
6394 #define LPSPI_CFGR1_NOSTALL_WIDTH 1u
6395 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_NOSTALL_SHIFT))&LPSPI_CFGR1_NOSTALL_MASK)
6396 #define LPSPI_CFGR1_PCSPOL_MASK 0xF00u
6397 #define LPSPI_CFGR1_PCSPOL_SHIFT 8u
6398 #define LPSPI_CFGR1_PCSPOL_WIDTH 4u
6399 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSPOL_SHIFT))&LPSPI_CFGR1_PCSPOL_MASK)
6400 #define LPSPI_CFGR1_MATCFG_MASK 0x70000u
6401 #define LPSPI_CFGR1_MATCFG_SHIFT 16u
6402 #define LPSPI_CFGR1_MATCFG_WIDTH 3u
6403 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MATCFG_SHIFT))&LPSPI_CFGR1_MATCFG_MASK)
6404 #define LPSPI_CFGR1_PINCFG_MASK 0x3000000u
6405 #define LPSPI_CFGR1_PINCFG_SHIFT 24u
6406 #define LPSPI_CFGR1_PINCFG_WIDTH 2u
6407 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PINCFG_SHIFT))&LPSPI_CFGR1_PINCFG_MASK)
6408 #define LPSPI_CFGR1_OUTCFG_MASK 0x4000000u
6409 #define LPSPI_CFGR1_OUTCFG_SHIFT 26u
6410 #define LPSPI_CFGR1_OUTCFG_WIDTH 1u
6411 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_OUTCFG_SHIFT))&LPSPI_CFGR1_OUTCFG_MASK)
6412 #define LPSPI_CFGR1_PCSCFG_MASK 0x8000000u
6413 #define LPSPI_CFGR1_PCSCFG_SHIFT 27u
6414 #define LPSPI_CFGR1_PCSCFG_WIDTH 1u
6415 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSCFG_SHIFT))&LPSPI_CFGR1_PCSCFG_MASK)
6416 /* DMR0 Bit Fields */
6417 #define LPSPI_DMR0_MATCH0_MASK 0xFFFFFFFFu
6418 #define LPSPI_DMR0_MATCH0_SHIFT 0u
6419 #define LPSPI_DMR0_MATCH0_WIDTH 32u
6420 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR0_MATCH0_SHIFT))&LPSPI_DMR0_MATCH0_MASK)
6421 /* DMR1 Bit Fields */
6422 #define LPSPI_DMR1_MATCH1_MASK 0xFFFFFFFFu
6423 #define LPSPI_DMR1_MATCH1_SHIFT 0u
6424 #define LPSPI_DMR1_MATCH1_WIDTH 32u
6425 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR1_MATCH1_SHIFT))&LPSPI_DMR1_MATCH1_MASK)
6426 /* CCR Bit Fields */
6427 #define LPSPI_CCR_SCKDIV_MASK 0xFFu
6428 #define LPSPI_CCR_SCKDIV_SHIFT 0u
6429 #define LPSPI_CCR_SCKDIV_WIDTH 8u
6430 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKDIV_SHIFT))&LPSPI_CCR_SCKDIV_MASK)
6431 #define LPSPI_CCR_DBT_MASK 0xFF00u
6432 #define LPSPI_CCR_DBT_SHIFT 8u
6433 #define LPSPI_CCR_DBT_WIDTH 8u
6434 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_DBT_SHIFT))&LPSPI_CCR_DBT_MASK)
6435 #define LPSPI_CCR_PCSSCK_MASK 0xFF0000u
6436 #define LPSPI_CCR_PCSSCK_SHIFT 16u
6437 #define LPSPI_CCR_PCSSCK_WIDTH 8u
6438 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_PCSSCK_SHIFT))&LPSPI_CCR_PCSSCK_MASK)
6439 #define LPSPI_CCR_SCKPCS_MASK 0xFF000000u
6440 #define LPSPI_CCR_SCKPCS_SHIFT 24u
6441 #define LPSPI_CCR_SCKPCS_WIDTH 8u
6442 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKPCS_SHIFT))&LPSPI_CCR_SCKPCS_MASK)
6443 /* FCR Bit Fields */
6444 #define LPSPI_FCR_TXWATER_MASK 0x3u
6445 #define LPSPI_FCR_TXWATER_SHIFT 0u
6446 #define LPSPI_FCR_TXWATER_WIDTH 2u
6447 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_TXWATER_SHIFT))&LPSPI_FCR_TXWATER_MASK)
6448 #define LPSPI_FCR_RXWATER_MASK 0x30000u
6449 #define LPSPI_FCR_RXWATER_SHIFT 16u
6450 #define LPSPI_FCR_RXWATER_WIDTH 2u
6451 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_RXWATER_SHIFT))&LPSPI_FCR_RXWATER_MASK)
6452 /* FSR Bit Fields */
6453 #define LPSPI_FSR_TXCOUNT_MASK 0x7u
6454 #define LPSPI_FSR_TXCOUNT_SHIFT 0u
6455 #define LPSPI_FSR_TXCOUNT_WIDTH 3u
6456 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_TXCOUNT_SHIFT))&LPSPI_FSR_TXCOUNT_MASK)
6457 #define LPSPI_FSR_RXCOUNT_MASK 0x70000u
6458 #define LPSPI_FSR_RXCOUNT_SHIFT 16u
6459 #define LPSPI_FSR_RXCOUNT_WIDTH 3u
6460 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_RXCOUNT_SHIFT))&LPSPI_FSR_RXCOUNT_MASK)
6461 /* TCR Bit Fields */
6462 #define LPSPI_TCR_FRAMESZ_MASK 0xFFFu
6463 #define LPSPI_TCR_FRAMESZ_SHIFT 0u
6464 #define LPSPI_TCR_FRAMESZ_WIDTH 12u
6465 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_FRAMESZ_SHIFT))&LPSPI_TCR_FRAMESZ_MASK)
6466 #define LPSPI_TCR_WIDTH_MASK 0x30000u
6467 #define LPSPI_TCR_WIDTH_SHIFT 16u
6468 #define LPSPI_TCR_WIDTH_WIDTH 2u
6469 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_WIDTH_SHIFT))&LPSPI_TCR_WIDTH_MASK)
6470 #define LPSPI_TCR_TXMSK_MASK 0x40000u
6471 #define LPSPI_TCR_TXMSK_SHIFT 18u
6472 #define LPSPI_TCR_TXMSK_WIDTH 1u
6473 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_TXMSK_SHIFT))&LPSPI_TCR_TXMSK_MASK)
6474 #define LPSPI_TCR_RXMSK_MASK 0x80000u
6475 #define LPSPI_TCR_RXMSK_SHIFT 19u
6476 #define LPSPI_TCR_RXMSK_WIDTH 1u
6477 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_RXMSK_SHIFT))&LPSPI_TCR_RXMSK_MASK)
6478 #define LPSPI_TCR_CONTC_MASK 0x100000u
6479 #define LPSPI_TCR_CONTC_SHIFT 20u
6480 #define LPSPI_TCR_CONTC_WIDTH 1u
6481 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONTC_SHIFT))&LPSPI_TCR_CONTC_MASK)
6482 #define LPSPI_TCR_CONT_MASK 0x200000u
6483 #define LPSPI_TCR_CONT_SHIFT 21u
6484 #define LPSPI_TCR_CONT_WIDTH 1u
6485 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONT_SHIFT))&LPSPI_TCR_CONT_MASK)
6486 #define LPSPI_TCR_BYSW_MASK 0x400000u
6487 #define LPSPI_TCR_BYSW_SHIFT 22u
6488 #define LPSPI_TCR_BYSW_WIDTH 1u
6489 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_BYSW_SHIFT))&LPSPI_TCR_BYSW_MASK)
6490 #define LPSPI_TCR_LSBF_MASK 0x800000u
6491 #define LPSPI_TCR_LSBF_SHIFT 23u
6492 #define LPSPI_TCR_LSBF_WIDTH 1u
6493 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_LSBF_SHIFT))&LPSPI_TCR_LSBF_MASK)
6494 #define LPSPI_TCR_PCS_MASK 0x3000000u
6495 #define LPSPI_TCR_PCS_SHIFT 24u
6496 #define LPSPI_TCR_PCS_WIDTH 2u
6497 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PCS_SHIFT))&LPSPI_TCR_PCS_MASK)
6498 #define LPSPI_TCR_PRESCALE_MASK 0x38000000u
6499 #define LPSPI_TCR_PRESCALE_SHIFT 27u
6500 #define LPSPI_TCR_PRESCALE_WIDTH 3u
6501 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PRESCALE_SHIFT))&LPSPI_TCR_PRESCALE_MASK)
6502 #define LPSPI_TCR_CPHA_MASK 0x40000000u
6503 #define LPSPI_TCR_CPHA_SHIFT 30u
6504 #define LPSPI_TCR_CPHA_WIDTH 1u
6505 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPHA_SHIFT))&LPSPI_TCR_CPHA_MASK)
6506 #define LPSPI_TCR_CPOL_MASK 0x80000000u
6507 #define LPSPI_TCR_CPOL_SHIFT 31u
6508 #define LPSPI_TCR_CPOL_WIDTH 1u
6509 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPOL_SHIFT))&LPSPI_TCR_CPOL_MASK)
6510 /* TDR Bit Fields */
6511 #define LPSPI_TDR_DATA_MASK 0xFFFFFFFFu
6512 #define LPSPI_TDR_DATA_SHIFT 0u
6513 #define LPSPI_TDR_DATA_WIDTH 32u
6514 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TDR_DATA_SHIFT))&LPSPI_TDR_DATA_MASK)
6515 /* RSR Bit Fields */
6516 #define LPSPI_RSR_SOF_MASK 0x1u
6517 #define LPSPI_RSR_SOF_SHIFT 0u
6518 #define LPSPI_RSR_SOF_WIDTH 1u
6519 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_SOF_SHIFT))&LPSPI_RSR_SOF_MASK)
6520 #define LPSPI_RSR_RXEMPTY_MASK 0x2u
6521 #define LPSPI_RSR_RXEMPTY_SHIFT 1u
6522 #define LPSPI_RSR_RXEMPTY_WIDTH 1u
6523 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_RXEMPTY_SHIFT))&LPSPI_RSR_RXEMPTY_MASK)
6524 /* RDR Bit Fields */
6525 #define LPSPI_RDR_DATA_MASK 0xFFFFFFFFu
6526 #define LPSPI_RDR_DATA_SHIFT 0u
6527 #define LPSPI_RDR_DATA_WIDTH 32u
6528 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RDR_DATA_SHIFT))&LPSPI_RDR_DATA_MASK)
6529  /* end of group LPSPI_Register_Masks */
6533 
6534  /* end of group LPSPI_Peripheral_Access_Layer */
6538 
6539 
6540 /* ----------------------------------------------------------------------------
6541  -- LPTMR Peripheral Access Layer
6542  ---------------------------------------------------------------------------- */
6543 
6553 typedef struct {
6554  __IO uint32_t CSR;
6555  __IO uint32_t PSR;
6556  __IO uint32_t CMR;
6557  __IO uint32_t CNR;
6559 
6561 #define LPTMR_INSTANCE_COUNT (1u)
6562 
6563 
6564 /* LPTMR - Peripheral instance base addresses */
6566 #define LPTMR0_BASE (0x40040000u)
6567 
6568 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
6569 
6570 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
6571 
6572 #define LPTMR_BASE_PTRS { LPTMR0 }
6573 
6574 #define LPTMR_IRQS_ARR_COUNT (1u)
6575 
6576 #define LPTMR_IRQS_CH_COUNT (1u)
6577 
6578 #define LPTMR_IRQS { LPTMR0_IRQn }
6579 
6580 /* ----------------------------------------------------------------------------
6581  -- LPTMR Register Masks
6582  ---------------------------------------------------------------------------- */
6583 
6589 /* CSR Bit Fields */
6590 #define LPTMR_CSR_TEN_MASK 0x1u
6591 #define LPTMR_CSR_TEN_SHIFT 0u
6592 #define LPTMR_CSR_TEN_WIDTH 1u
6593 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
6594 #define LPTMR_CSR_TMS_MASK 0x2u
6595 #define LPTMR_CSR_TMS_SHIFT 1u
6596 #define LPTMR_CSR_TMS_WIDTH 1u
6597 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
6598 #define LPTMR_CSR_TFC_MASK 0x4u
6599 #define LPTMR_CSR_TFC_SHIFT 2u
6600 #define LPTMR_CSR_TFC_WIDTH 1u
6601 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
6602 #define LPTMR_CSR_TPP_MASK 0x8u
6603 #define LPTMR_CSR_TPP_SHIFT 3u
6604 #define LPTMR_CSR_TPP_WIDTH 1u
6605 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
6606 #define LPTMR_CSR_TPS_MASK 0x30u
6607 #define LPTMR_CSR_TPS_SHIFT 4u
6608 #define LPTMR_CSR_TPS_WIDTH 2u
6609 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
6610 #define LPTMR_CSR_TIE_MASK 0x40u
6611 #define LPTMR_CSR_TIE_SHIFT 6u
6612 #define LPTMR_CSR_TIE_WIDTH 1u
6613 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
6614 #define LPTMR_CSR_TCF_MASK 0x80u
6615 #define LPTMR_CSR_TCF_SHIFT 7u
6616 #define LPTMR_CSR_TCF_WIDTH 1u
6617 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
6618 #define LPTMR_CSR_TDRE_MASK 0x100u
6619 #define LPTMR_CSR_TDRE_SHIFT 8u
6620 #define LPTMR_CSR_TDRE_WIDTH 1u
6621 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TDRE_SHIFT))&LPTMR_CSR_TDRE_MASK)
6622 /* PSR Bit Fields */
6623 #define LPTMR_PSR_PCS_MASK 0x3u
6624 #define LPTMR_PSR_PCS_SHIFT 0u
6625 #define LPTMR_PSR_PCS_WIDTH 2u
6626 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
6627 #define LPTMR_PSR_PBYP_MASK 0x4u
6628 #define LPTMR_PSR_PBYP_SHIFT 2u
6629 #define LPTMR_PSR_PBYP_WIDTH 1u
6630 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
6631 #define LPTMR_PSR_PRESCALE_MASK 0x78u
6632 #define LPTMR_PSR_PRESCALE_SHIFT 3u
6633 #define LPTMR_PSR_PRESCALE_WIDTH 4u
6634 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
6635 /* CMR Bit Fields */
6636 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
6637 #define LPTMR_CMR_COMPARE_SHIFT 0u
6638 #define LPTMR_CMR_COMPARE_WIDTH 16u
6639 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
6640 /* CNR Bit Fields */
6641 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
6642 #define LPTMR_CNR_COUNTER_SHIFT 0u
6643 #define LPTMR_CNR_COUNTER_WIDTH 16u
6644 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
6645  /* end of group LPTMR_Register_Masks */
6649 
6650  /* end of group LPTMR_Peripheral_Access_Layer */
6654 
6655 
6656 /* ----------------------------------------------------------------------------
6657  -- LPUART Peripheral Access Layer
6658  ---------------------------------------------------------------------------- */
6659 
6669 typedef struct {
6670  __I uint32_t VERID;
6671  __I uint32_t PARAM;
6672  __IO uint32_t GLOBAL;
6673  __IO uint32_t PINCFG;
6674  __IO uint32_t BAUD;
6675  __IO uint32_t STAT;
6676  __IO uint32_t CTRL;
6677  __IO uint32_t DATA;
6678  __IO uint32_t MATCH;
6679  __IO uint32_t MODIR;
6680  __IO uint32_t FIFO;
6681  __IO uint32_t WATER;
6683 
6685 #define LPUART_INSTANCE_COUNT (3u)
6686 
6687 
6688 /* LPUART - Peripheral instance base addresses */
6690 #define LPUART0_BASE (0x4006A000u)
6691 
6692 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
6693 
6694 #define LPUART1_BASE (0x4006B000u)
6695 
6696 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
6697 
6698 #define LPUART2_BASE (0x4006C000u)
6699 
6700 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
6701 
6702 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
6703 
6704 #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 }
6705 
6706 #define LPUART_IRQS_ARR_COUNT (1u)
6707 
6708 #define LPUART_RX_TX_IRQS_CH_COUNT (1u)
6709 
6710 #define LPUART_RX_TX_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn, LPUART2_RxTx_IRQn }
6711 
6712 /* ----------------------------------------------------------------------------
6713  -- LPUART Register Masks
6714  ---------------------------------------------------------------------------- */
6715 
6721 /* VERID Bit Fields */
6722 #define LPUART_VERID_FEATURE_MASK 0xFFFFu
6723 #define LPUART_VERID_FEATURE_SHIFT 0u
6724 #define LPUART_VERID_FEATURE_WIDTH 16u
6725 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_FEATURE_SHIFT))&LPUART_VERID_FEATURE_MASK)
6726 #define LPUART_VERID_MINOR_MASK 0xFF0000u
6727 #define LPUART_VERID_MINOR_SHIFT 16u
6728 #define LPUART_VERID_MINOR_WIDTH 8u
6729 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MINOR_SHIFT))&LPUART_VERID_MINOR_MASK)
6730 #define LPUART_VERID_MAJOR_MASK 0xFF000000u
6731 #define LPUART_VERID_MAJOR_SHIFT 24u
6732 #define LPUART_VERID_MAJOR_WIDTH 8u
6733 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MAJOR_SHIFT))&LPUART_VERID_MAJOR_MASK)
6734 /* PARAM Bit Fields */
6735 #define LPUART_PARAM_TXFIFO_MASK 0xFFu
6736 #define LPUART_PARAM_TXFIFO_SHIFT 0u
6737 #define LPUART_PARAM_TXFIFO_WIDTH 8u
6738 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_TXFIFO_SHIFT))&LPUART_PARAM_TXFIFO_MASK)
6739 #define LPUART_PARAM_RXFIFO_MASK 0xFF00u
6740 #define LPUART_PARAM_RXFIFO_SHIFT 8u
6741 #define LPUART_PARAM_RXFIFO_WIDTH 8u
6742 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_RXFIFO_SHIFT))&LPUART_PARAM_RXFIFO_MASK)
6743 /* GLOBAL Bit Fields */
6744 #define LPUART_GLOBAL_RST_MASK 0x2u
6745 #define LPUART_GLOBAL_RST_SHIFT 1u
6746 #define LPUART_GLOBAL_RST_WIDTH 1u
6747 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<LPUART_GLOBAL_RST_SHIFT))&LPUART_GLOBAL_RST_MASK)
6748 /* PINCFG Bit Fields */
6749 #define LPUART_PINCFG_TRGSEL_MASK 0x3u
6750 #define LPUART_PINCFG_TRGSEL_SHIFT 0u
6751 #define LPUART_PINCFG_TRGSEL_WIDTH 2u
6752 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PINCFG_TRGSEL_SHIFT))&LPUART_PINCFG_TRGSEL_MASK)
6753 /* BAUD Bit Fields */
6754 #define LPUART_BAUD_SBR_MASK 0x1FFFu
6755 #define LPUART_BAUD_SBR_SHIFT 0u
6756 #define LPUART_BAUD_SBR_WIDTH 13u
6757 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
6758 #define LPUART_BAUD_SBNS_MASK 0x2000u
6759 #define LPUART_BAUD_SBNS_SHIFT 13u
6760 #define LPUART_BAUD_SBNS_WIDTH 1u
6761 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
6762 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
6763 #define LPUART_BAUD_RXEDGIE_SHIFT 14u
6764 #define LPUART_BAUD_RXEDGIE_WIDTH 1u
6765 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
6766 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
6767 #define LPUART_BAUD_LBKDIE_SHIFT 15u
6768 #define LPUART_BAUD_LBKDIE_WIDTH 1u
6769 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
6770 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
6771 #define LPUART_BAUD_RESYNCDIS_SHIFT 16u
6772 #define LPUART_BAUD_RESYNCDIS_WIDTH 1u
6773 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
6774 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
6775 #define LPUART_BAUD_BOTHEDGE_SHIFT 17u
6776 #define LPUART_BAUD_BOTHEDGE_WIDTH 1u
6777 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
6778 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
6779 #define LPUART_BAUD_MATCFG_SHIFT 18u
6780 #define LPUART_BAUD_MATCFG_WIDTH 2u
6781 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
6782 #define LPUART_BAUD_RIDMAE_MASK 0x100000u
6783 #define LPUART_BAUD_RIDMAE_SHIFT 20u
6784 #define LPUART_BAUD_RIDMAE_WIDTH 1u
6785 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RIDMAE_SHIFT))&LPUART_BAUD_RIDMAE_MASK)
6786 #define LPUART_BAUD_RDMAE_MASK 0x200000u
6787 #define LPUART_BAUD_RDMAE_SHIFT 21u
6788 #define LPUART_BAUD_RDMAE_WIDTH 1u
6789 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
6790 #define LPUART_BAUD_TDMAE_MASK 0x800000u
6791 #define LPUART_BAUD_TDMAE_SHIFT 23u
6792 #define LPUART_BAUD_TDMAE_WIDTH 1u
6793 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
6794 #define LPUART_BAUD_OSR_MASK 0x1F000000u
6795 #define LPUART_BAUD_OSR_SHIFT 24u
6796 #define LPUART_BAUD_OSR_WIDTH 5u
6797 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
6798 #define LPUART_BAUD_M10_MASK 0x20000000u
6799 #define LPUART_BAUD_M10_SHIFT 29u
6800 #define LPUART_BAUD_M10_WIDTH 1u
6801 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
6802 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
6803 #define LPUART_BAUD_MAEN2_SHIFT 30u
6804 #define LPUART_BAUD_MAEN2_WIDTH 1u
6805 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
6806 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
6807 #define LPUART_BAUD_MAEN1_SHIFT 31u
6808 #define LPUART_BAUD_MAEN1_WIDTH 1u
6809 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
6810 /* STAT Bit Fields */
6811 #define LPUART_STAT_MA2F_MASK 0x4000u
6812 #define LPUART_STAT_MA2F_SHIFT 14u
6813 #define LPUART_STAT_MA2F_WIDTH 1u
6814 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
6815 #define LPUART_STAT_MA1F_MASK 0x8000u
6816 #define LPUART_STAT_MA1F_SHIFT 15u
6817 #define LPUART_STAT_MA1F_WIDTH 1u
6818 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
6819 #define LPUART_STAT_PF_MASK 0x10000u
6820 #define LPUART_STAT_PF_SHIFT 16u
6821 #define LPUART_STAT_PF_WIDTH 1u
6822 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
6823 #define LPUART_STAT_FE_MASK 0x20000u
6824 #define LPUART_STAT_FE_SHIFT 17u
6825 #define LPUART_STAT_FE_WIDTH 1u
6826 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
6827 #define LPUART_STAT_NF_MASK 0x40000u
6828 #define LPUART_STAT_NF_SHIFT 18u
6829 #define LPUART_STAT_NF_WIDTH 1u
6830 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
6831 #define LPUART_STAT_OR_MASK 0x80000u
6832 #define LPUART_STAT_OR_SHIFT 19u
6833 #define LPUART_STAT_OR_WIDTH 1u
6834 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
6835 #define LPUART_STAT_IDLE_MASK 0x100000u
6836 #define LPUART_STAT_IDLE_SHIFT 20u
6837 #define LPUART_STAT_IDLE_WIDTH 1u
6838 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
6839 #define LPUART_STAT_RDRF_MASK 0x200000u
6840 #define LPUART_STAT_RDRF_SHIFT 21u
6841 #define LPUART_STAT_RDRF_WIDTH 1u
6842 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
6843 #define LPUART_STAT_TC_MASK 0x400000u
6844 #define LPUART_STAT_TC_SHIFT 22u
6845 #define LPUART_STAT_TC_WIDTH 1u
6846 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
6847 #define LPUART_STAT_TDRE_MASK 0x800000u
6848 #define LPUART_STAT_TDRE_SHIFT 23u
6849 #define LPUART_STAT_TDRE_WIDTH 1u
6850 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
6851 #define LPUART_STAT_RAF_MASK 0x1000000u
6852 #define LPUART_STAT_RAF_SHIFT 24u
6853 #define LPUART_STAT_RAF_WIDTH 1u
6854 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
6855 #define LPUART_STAT_LBKDE_MASK 0x2000000u
6856 #define LPUART_STAT_LBKDE_SHIFT 25u
6857 #define LPUART_STAT_LBKDE_WIDTH 1u
6858 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
6859 #define LPUART_STAT_BRK13_MASK 0x4000000u
6860 #define LPUART_STAT_BRK13_SHIFT 26u
6861 #define LPUART_STAT_BRK13_WIDTH 1u
6862 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
6863 #define LPUART_STAT_RWUID_MASK 0x8000000u
6864 #define LPUART_STAT_RWUID_SHIFT 27u
6865 #define LPUART_STAT_RWUID_WIDTH 1u
6866 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
6867 #define LPUART_STAT_RXINV_MASK 0x10000000u
6868 #define LPUART_STAT_RXINV_SHIFT 28u
6869 #define LPUART_STAT_RXINV_WIDTH 1u
6870 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
6871 #define LPUART_STAT_MSBF_MASK 0x20000000u
6872 #define LPUART_STAT_MSBF_SHIFT 29u
6873 #define LPUART_STAT_MSBF_WIDTH 1u
6874 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
6875 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
6876 #define LPUART_STAT_RXEDGIF_SHIFT 30u
6877 #define LPUART_STAT_RXEDGIF_WIDTH 1u
6878 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
6879 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
6880 #define LPUART_STAT_LBKDIF_SHIFT 31u
6881 #define LPUART_STAT_LBKDIF_WIDTH 1u
6882 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
6883 /* CTRL Bit Fields */
6884 #define LPUART_CTRL_PT_MASK 0x1u
6885 #define LPUART_CTRL_PT_SHIFT 0u
6886 #define LPUART_CTRL_PT_WIDTH 1u
6887 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
6888 #define LPUART_CTRL_PE_MASK 0x2u
6889 #define LPUART_CTRL_PE_SHIFT 1u
6890 #define LPUART_CTRL_PE_WIDTH 1u
6891 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
6892 #define LPUART_CTRL_ILT_MASK 0x4u
6893 #define LPUART_CTRL_ILT_SHIFT 2u
6894 #define LPUART_CTRL_ILT_WIDTH 1u
6895 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
6896 #define LPUART_CTRL_WAKE_MASK 0x8u
6897 #define LPUART_CTRL_WAKE_SHIFT 3u
6898 #define LPUART_CTRL_WAKE_WIDTH 1u
6899 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
6900 #define LPUART_CTRL_M_MASK 0x10u
6901 #define LPUART_CTRL_M_SHIFT 4u
6902 #define LPUART_CTRL_M_WIDTH 1u
6903 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
6904 #define LPUART_CTRL_RSRC_MASK 0x20u
6905 #define LPUART_CTRL_RSRC_SHIFT 5u
6906 #define LPUART_CTRL_RSRC_WIDTH 1u
6907 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
6908 #define LPUART_CTRL_DOZEEN_MASK 0x40u
6909 #define LPUART_CTRL_DOZEEN_SHIFT 6u
6910 #define LPUART_CTRL_DOZEEN_WIDTH 1u
6911 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
6912 #define LPUART_CTRL_LOOPS_MASK 0x80u
6913 #define LPUART_CTRL_LOOPS_SHIFT 7u
6914 #define LPUART_CTRL_LOOPS_WIDTH 1u
6915 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
6916 #define LPUART_CTRL_IDLECFG_MASK 0x700u
6917 #define LPUART_CTRL_IDLECFG_SHIFT 8u
6918 #define LPUART_CTRL_IDLECFG_WIDTH 3u
6919 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
6920 #define LPUART_CTRL_M7_MASK 0x800u
6921 #define LPUART_CTRL_M7_SHIFT 11u
6922 #define LPUART_CTRL_M7_WIDTH 1u
6923 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M7_SHIFT))&LPUART_CTRL_M7_MASK)
6924 #define LPUART_CTRL_MA2IE_MASK 0x4000u
6925 #define LPUART_CTRL_MA2IE_SHIFT 14u
6926 #define LPUART_CTRL_MA2IE_WIDTH 1u
6927 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
6928 #define LPUART_CTRL_MA1IE_MASK 0x8000u
6929 #define LPUART_CTRL_MA1IE_SHIFT 15u
6930 #define LPUART_CTRL_MA1IE_WIDTH 1u
6931 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
6932 #define LPUART_CTRL_SBK_MASK 0x10000u
6933 #define LPUART_CTRL_SBK_SHIFT 16u
6934 #define LPUART_CTRL_SBK_WIDTH 1u
6935 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
6936 #define LPUART_CTRL_RWU_MASK 0x20000u
6937 #define LPUART_CTRL_RWU_SHIFT 17u
6938 #define LPUART_CTRL_RWU_WIDTH 1u
6939 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
6940 #define LPUART_CTRL_RE_MASK 0x40000u
6941 #define LPUART_CTRL_RE_SHIFT 18u
6942 #define LPUART_CTRL_RE_WIDTH 1u
6943 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
6944 #define LPUART_CTRL_TE_MASK 0x80000u
6945 #define LPUART_CTRL_TE_SHIFT 19u
6946 #define LPUART_CTRL_TE_WIDTH 1u
6947 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
6948 #define LPUART_CTRL_ILIE_MASK 0x100000u
6949 #define LPUART_CTRL_ILIE_SHIFT 20u
6950 #define LPUART_CTRL_ILIE_WIDTH 1u
6951 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
6952 #define LPUART_CTRL_RIE_MASK 0x200000u
6953 #define LPUART_CTRL_RIE_SHIFT 21u
6954 #define LPUART_CTRL_RIE_WIDTH 1u
6955 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
6956 #define LPUART_CTRL_TCIE_MASK 0x400000u
6957 #define LPUART_CTRL_TCIE_SHIFT 22u
6958 #define LPUART_CTRL_TCIE_WIDTH 1u
6959 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
6960 #define LPUART_CTRL_TIE_MASK 0x800000u
6961 #define LPUART_CTRL_TIE_SHIFT 23u
6962 #define LPUART_CTRL_TIE_WIDTH 1u
6963 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
6964 #define LPUART_CTRL_PEIE_MASK 0x1000000u
6965 #define LPUART_CTRL_PEIE_SHIFT 24u
6966 #define LPUART_CTRL_PEIE_WIDTH 1u
6967 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
6968 #define LPUART_CTRL_FEIE_MASK 0x2000000u
6969 #define LPUART_CTRL_FEIE_SHIFT 25u
6970 #define LPUART_CTRL_FEIE_WIDTH 1u
6971 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
6972 #define LPUART_CTRL_NEIE_MASK 0x4000000u
6973 #define LPUART_CTRL_NEIE_SHIFT 26u
6974 #define LPUART_CTRL_NEIE_WIDTH 1u
6975 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
6976 #define LPUART_CTRL_ORIE_MASK 0x8000000u
6977 #define LPUART_CTRL_ORIE_SHIFT 27u
6978 #define LPUART_CTRL_ORIE_WIDTH 1u
6979 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
6980 #define LPUART_CTRL_TXINV_MASK 0x10000000u
6981 #define LPUART_CTRL_TXINV_SHIFT 28u
6982 #define LPUART_CTRL_TXINV_WIDTH 1u
6983 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
6984 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
6985 #define LPUART_CTRL_TXDIR_SHIFT 29u
6986 #define LPUART_CTRL_TXDIR_WIDTH 1u
6987 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
6988 #define LPUART_CTRL_R9T8_MASK 0x40000000u
6989 #define LPUART_CTRL_R9T8_SHIFT 30u
6990 #define LPUART_CTRL_R9T8_WIDTH 1u
6991 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
6992 #define LPUART_CTRL_R8T9_MASK 0x80000000u
6993 #define LPUART_CTRL_R8T9_SHIFT 31u
6994 #define LPUART_CTRL_R8T9_WIDTH 1u
6995 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
6996 /* DATA Bit Fields */
6997 #define LPUART_DATA_R0T0_MASK 0x1u
6998 #define LPUART_DATA_R0T0_SHIFT 0u
6999 #define LPUART_DATA_R0T0_WIDTH 1u
7000 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
7001 #define LPUART_DATA_R1T1_MASK 0x2u
7002 #define LPUART_DATA_R1T1_SHIFT 1u
7003 #define LPUART_DATA_R1T1_WIDTH 1u
7004 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
7005 #define LPUART_DATA_R2T2_MASK 0x4u
7006 #define LPUART_DATA_R2T2_SHIFT 2u
7007 #define LPUART_DATA_R2T2_WIDTH 1u
7008 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
7009 #define LPUART_DATA_R3T3_MASK 0x8u
7010 #define LPUART_DATA_R3T3_SHIFT 3u
7011 #define LPUART_DATA_R3T3_WIDTH 1u
7012 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
7013 #define LPUART_DATA_R4T4_MASK 0x10u
7014 #define LPUART_DATA_R4T4_SHIFT 4u
7015 #define LPUART_DATA_R4T4_WIDTH 1u
7016 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
7017 #define LPUART_DATA_R5T5_MASK 0x20u
7018 #define LPUART_DATA_R5T5_SHIFT 5u
7019 #define LPUART_DATA_R5T5_WIDTH 1u
7020 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
7021 #define LPUART_DATA_R6T6_MASK 0x40u
7022 #define LPUART_DATA_R6T6_SHIFT 6u
7023 #define LPUART_DATA_R6T6_WIDTH 1u
7024 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
7025 #define LPUART_DATA_R7T7_MASK 0x80u
7026 #define LPUART_DATA_R7T7_SHIFT 7u
7027 #define LPUART_DATA_R7T7_WIDTH 1u
7028 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
7029 #define LPUART_DATA_R8T8_MASK 0x100u
7030 #define LPUART_DATA_R8T8_SHIFT 8u
7031 #define LPUART_DATA_R8T8_WIDTH 1u
7032 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
7033 #define LPUART_DATA_R9T9_MASK 0x200u
7034 #define LPUART_DATA_R9T9_SHIFT 9u
7035 #define LPUART_DATA_R9T9_WIDTH 1u
7036 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
7037 #define LPUART_DATA_IDLINE_MASK 0x800u
7038 #define LPUART_DATA_IDLINE_SHIFT 11u
7039 #define LPUART_DATA_IDLINE_WIDTH 1u
7040 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
7041 #define LPUART_DATA_RXEMPT_MASK 0x1000u
7042 #define LPUART_DATA_RXEMPT_SHIFT 12u
7043 #define LPUART_DATA_RXEMPT_WIDTH 1u
7044 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
7045 #define LPUART_DATA_FRETSC_MASK 0x2000u
7046 #define LPUART_DATA_FRETSC_SHIFT 13u
7047 #define LPUART_DATA_FRETSC_WIDTH 1u
7048 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
7049 #define LPUART_DATA_PARITYE_MASK 0x4000u
7050 #define LPUART_DATA_PARITYE_SHIFT 14u
7051 #define LPUART_DATA_PARITYE_WIDTH 1u
7052 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
7053 #define LPUART_DATA_NOISY_MASK 0x8000u
7054 #define LPUART_DATA_NOISY_SHIFT 15u
7055 #define LPUART_DATA_NOISY_WIDTH 1u
7056 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
7057 /* MATCH Bit Fields */
7058 #define LPUART_MATCH_MA1_MASK 0x3FFu
7059 #define LPUART_MATCH_MA1_SHIFT 0u
7060 #define LPUART_MATCH_MA1_WIDTH 10u
7061 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
7062 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
7063 #define LPUART_MATCH_MA2_SHIFT 16u
7064 #define LPUART_MATCH_MA2_WIDTH 10u
7065 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
7066 /* MODIR Bit Fields */
7067 #define LPUART_MODIR_TXCTSE_MASK 0x1u
7068 #define LPUART_MODIR_TXCTSE_SHIFT 0u
7069 #define LPUART_MODIR_TXCTSE_WIDTH 1u
7070 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
7071 #define LPUART_MODIR_TXRTSE_MASK 0x2u
7072 #define LPUART_MODIR_TXRTSE_SHIFT 1u
7073 #define LPUART_MODIR_TXRTSE_WIDTH 1u
7074 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
7075 #define LPUART_MODIR_TXRTSPOL_MASK 0x4u
7076 #define LPUART_MODIR_TXRTSPOL_SHIFT 2u
7077 #define LPUART_MODIR_TXRTSPOL_WIDTH 1u
7078 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
7079 #define LPUART_MODIR_RXRTSE_MASK 0x8u
7080 #define LPUART_MODIR_RXRTSE_SHIFT 3u
7081 #define LPUART_MODIR_RXRTSE_WIDTH 1u
7082 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
7083 #define LPUART_MODIR_TXCTSC_MASK 0x10u
7084 #define LPUART_MODIR_TXCTSC_SHIFT 4u
7085 #define LPUART_MODIR_TXCTSC_WIDTH 1u
7086 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
7087 #define LPUART_MODIR_TXCTSSRC_MASK 0x20u
7088 #define LPUART_MODIR_TXCTSSRC_SHIFT 5u
7089 #define LPUART_MODIR_TXCTSSRC_WIDTH 1u
7090 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
7091 #define LPUART_MODIR_RTSWATER_MASK 0x300u
7092 #define LPUART_MODIR_RTSWATER_SHIFT 8u
7093 #define LPUART_MODIR_RTSWATER_WIDTH 2u
7094 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RTSWATER_SHIFT))&LPUART_MODIR_RTSWATER_MASK)
7095 #define LPUART_MODIR_TNP_MASK 0x30000u
7096 #define LPUART_MODIR_TNP_SHIFT 16u
7097 #define LPUART_MODIR_TNP_WIDTH 2u
7098 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
7099 #define LPUART_MODIR_IREN_MASK 0x40000u
7100 #define LPUART_MODIR_IREN_SHIFT 18u
7101 #define LPUART_MODIR_IREN_WIDTH 1u
7102 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
7103 /* FIFO Bit Fields */
7104 #define LPUART_FIFO_RXFIFOSIZE_MASK 0x7u
7105 #define LPUART_FIFO_RXFIFOSIZE_SHIFT 0u
7106 #define LPUART_FIFO_RXFIFOSIZE_WIDTH 3u
7107 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFIFOSIZE_SHIFT))&LPUART_FIFO_RXFIFOSIZE_MASK)
7108 #define LPUART_FIFO_RXFE_MASK 0x8u
7109 #define LPUART_FIFO_RXFE_SHIFT 3u
7110 #define LPUART_FIFO_RXFE_WIDTH 1u
7111 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFE_SHIFT))&LPUART_FIFO_RXFE_MASK)
7112 #define LPUART_FIFO_TXFIFOSIZE_MASK 0x70u
7113 #define LPUART_FIFO_TXFIFOSIZE_SHIFT 4u
7114 #define LPUART_FIFO_TXFIFOSIZE_WIDTH 3u
7115 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFIFOSIZE_SHIFT))&LPUART_FIFO_TXFIFOSIZE_MASK)
7116 #define LPUART_FIFO_TXFE_MASK 0x80u
7117 #define LPUART_FIFO_TXFE_SHIFT 7u
7118 #define LPUART_FIFO_TXFE_WIDTH 1u
7119 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFE_SHIFT))&LPUART_FIFO_TXFE_MASK)
7120 #define LPUART_FIFO_RXUFE_MASK 0x100u
7121 #define LPUART_FIFO_RXUFE_SHIFT 8u
7122 #define LPUART_FIFO_RXUFE_WIDTH 1u
7123 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUFE_SHIFT))&LPUART_FIFO_RXUFE_MASK)
7124 #define LPUART_FIFO_TXOFE_MASK 0x200u
7125 #define LPUART_FIFO_TXOFE_SHIFT 9u
7126 #define LPUART_FIFO_TXOFE_WIDTH 1u
7127 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOFE_SHIFT))&LPUART_FIFO_TXOFE_MASK)
7128 #define LPUART_FIFO_RXIDEN_MASK 0x1C00u
7129 #define LPUART_FIFO_RXIDEN_SHIFT 10u
7130 #define LPUART_FIFO_RXIDEN_WIDTH 3u
7131 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXIDEN_SHIFT))&LPUART_FIFO_RXIDEN_MASK)
7132 #define LPUART_FIFO_RXFLUSH_MASK 0x4000u
7133 #define LPUART_FIFO_RXFLUSH_SHIFT 14u
7134 #define LPUART_FIFO_RXFLUSH_WIDTH 1u
7135 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFLUSH_SHIFT))&LPUART_FIFO_RXFLUSH_MASK)
7136 #define LPUART_FIFO_TXFLUSH_MASK 0x8000u
7137 #define LPUART_FIFO_TXFLUSH_SHIFT 15u
7138 #define LPUART_FIFO_TXFLUSH_WIDTH 1u
7139 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFLUSH_SHIFT))&LPUART_FIFO_TXFLUSH_MASK)
7140 #define LPUART_FIFO_RXUF_MASK 0x10000u
7141 #define LPUART_FIFO_RXUF_SHIFT 16u
7142 #define LPUART_FIFO_RXUF_WIDTH 1u
7143 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUF_SHIFT))&LPUART_FIFO_RXUF_MASK)
7144 #define LPUART_FIFO_TXOF_MASK 0x20000u
7145 #define LPUART_FIFO_TXOF_SHIFT 17u
7146 #define LPUART_FIFO_TXOF_WIDTH 1u
7147 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOF_SHIFT))&LPUART_FIFO_TXOF_MASK)
7148 #define LPUART_FIFO_RXEMPT_MASK 0x400000u
7149 #define LPUART_FIFO_RXEMPT_SHIFT 22u
7150 #define LPUART_FIFO_RXEMPT_WIDTH 1u
7151 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXEMPT_SHIFT))&LPUART_FIFO_RXEMPT_MASK)
7152 #define LPUART_FIFO_TXEMPT_MASK 0x800000u
7153 #define LPUART_FIFO_TXEMPT_SHIFT 23u
7154 #define LPUART_FIFO_TXEMPT_WIDTH 1u
7155 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXEMPT_SHIFT))&LPUART_FIFO_TXEMPT_MASK)
7156 /* WATER Bit Fields */
7157 #define LPUART_WATER_TXWATER_MASK 0x3u
7158 #define LPUART_WATER_TXWATER_SHIFT 0u
7159 #define LPUART_WATER_TXWATER_WIDTH 2u
7160 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXWATER_SHIFT))&LPUART_WATER_TXWATER_MASK)
7161 #define LPUART_WATER_TXCOUNT_MASK 0x700u
7162 #define LPUART_WATER_TXCOUNT_SHIFT 8u
7163 #define LPUART_WATER_TXCOUNT_WIDTH 3u
7164 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXCOUNT_SHIFT))&LPUART_WATER_TXCOUNT_MASK)
7165 #define LPUART_WATER_RXWATER_MASK 0x30000u
7166 #define LPUART_WATER_RXWATER_SHIFT 16u
7167 #define LPUART_WATER_RXWATER_WIDTH 2u
7168 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXWATER_SHIFT))&LPUART_WATER_RXWATER_MASK)
7169 #define LPUART_WATER_RXCOUNT_MASK 0x7000000u
7170 #define LPUART_WATER_RXCOUNT_SHIFT 24u
7171 #define LPUART_WATER_RXCOUNT_WIDTH 3u
7172 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXCOUNT_SHIFT))&LPUART_WATER_RXCOUNT_MASK)
7173  /* end of group LPUART_Register_Masks */
7177 
7178  /* end of group LPUART_Peripheral_Access_Layer */
7182 
7183 
7184 /* ----------------------------------------------------------------------------
7185  -- MCM Peripheral Access Layer
7186  ---------------------------------------------------------------------------- */
7187 
7195 #define MCM_LMDR_COUNT 2u
7196 
7198 typedef struct {
7199  uint8_t RESERVED_0[8];
7200  __I uint16_t PLASC;
7201  __I uint16_t PLAMC;
7202  __IO uint32_t CPCR;
7203  __IO uint32_t ISCR;
7204  uint8_t RESERVED_1[28];
7205  __IO uint32_t PID;
7206  uint8_t RESERVED_2[12];
7207  __IO uint32_t CPO;
7208  uint8_t RESERVED_3[956];
7209  __IO uint32_t LMDR[MCM_LMDR_COUNT];
7210  __IO uint32_t LMDR2;
7211  uint8_t RESERVED_4[116];
7212  __IO uint32_t LMPECR;
7213  uint8_t RESERVED_5[4];
7214  __IO uint32_t LMPEIR;
7215  uint8_t RESERVED_6[4];
7216  __I uint32_t LMFAR;
7217  __I uint32_t LMFATR;
7218  uint8_t RESERVED_7[8];
7219  __I uint32_t LMFDHR;
7220  __I uint32_t LMFDLR;
7222 
7224 #define MCM_INSTANCE_COUNT (1u)
7225 
7226 
7227 /* MCM - Peripheral instance base addresses */
7229 #define MCM_BASE (0xE0080000u)
7230 
7231 #define MCM ((MCM_Type *)MCM_BASE)
7232 
7233 #define MCM_BASE_ADDRS { MCM_BASE }
7234 
7235 #define MCM_BASE_PTRS { MCM }
7236 
7237 #define MCM_IRQS_ARR_COUNT (1u)
7238 
7239 #define MCM_IRQS_CH_COUNT (1u)
7240 
7241 #define MCM_IRQS { MCM_IRQn }
7242 
7243 /* ----------------------------------------------------------------------------
7244  -- MCM Register Masks
7245  ---------------------------------------------------------------------------- */
7246 
7252 /* PLASC Bit Fields */
7253 #define MCM_PLASC_ASC_MASK 0xFFu
7254 #define MCM_PLASC_ASC_SHIFT 0u
7255 #define MCM_PLASC_ASC_WIDTH 8u
7256 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
7257 /* PLAMC Bit Fields */
7258 #define MCM_PLAMC_AMC_MASK 0xFFu
7259 #define MCM_PLAMC_AMC_SHIFT 0u
7260 #define MCM_PLAMC_AMC_WIDTH 8u
7261 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
7262 /* CPCR Bit Fields */
7263 #define MCM_CPCR_HLT_FSM_ST_MASK 0x3u
7264 #define MCM_CPCR_HLT_FSM_ST_SHIFT 0u
7265 #define MCM_CPCR_HLT_FSM_ST_WIDTH 2u
7266 #define MCM_CPCR_HLT_FSM_ST(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_HLT_FSM_ST_SHIFT))&MCM_CPCR_HLT_FSM_ST_MASK)
7267 #define MCM_CPCR_AXBS_HLT_REQ_MASK 0x4u
7268 #define MCM_CPCR_AXBS_HLT_REQ_SHIFT 2u
7269 #define MCM_CPCR_AXBS_HLT_REQ_WIDTH 1u
7270 #define MCM_CPCR_AXBS_HLT_REQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLT_REQ_SHIFT))&MCM_CPCR_AXBS_HLT_REQ_MASK)
7271 #define MCM_CPCR_AXBS_HLTD_MASK 0x8u
7272 #define MCM_CPCR_AXBS_HLTD_SHIFT 3u
7273 #define MCM_CPCR_AXBS_HLTD_WIDTH 1u
7274 #define MCM_CPCR_AXBS_HLTD(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLTD_SHIFT))&MCM_CPCR_AXBS_HLTD_MASK)
7275 #define MCM_CPCR_FMC_PF_IDLE_MASK 0x10u
7276 #define MCM_CPCR_FMC_PF_IDLE_SHIFT 4u
7277 #define MCM_CPCR_FMC_PF_IDLE_WIDTH 1u
7278 #define MCM_CPCR_FMC_PF_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_FMC_PF_IDLE_SHIFT))&MCM_CPCR_FMC_PF_IDLE_MASK)
7279 #define MCM_CPCR_PBRIDGE_IDLE_MASK 0x40u
7280 #define MCM_CPCR_PBRIDGE_IDLE_SHIFT 6u
7281 #define MCM_CPCR_PBRIDGE_IDLE_WIDTH 1u
7282 #define MCM_CPCR_PBRIDGE_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_PBRIDGE_IDLE_SHIFT))&MCM_CPCR_PBRIDGE_IDLE_MASK)
7283 #define MCM_CPCR_CBRR_MASK 0x200u
7284 #define MCM_CPCR_CBRR_SHIFT 9u
7285 #define MCM_CPCR_CBRR_WIDTH 1u
7286 #define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_CBRR_SHIFT))&MCM_CPCR_CBRR_MASK)
7287 #define MCM_CPCR_SRAMUAP_MASK 0x3000000u
7288 #define MCM_CPCR_SRAMUAP_SHIFT 24u
7289 #define MCM_CPCR_SRAMUAP_WIDTH 2u
7290 #define MCM_CPCR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUAP_SHIFT))&MCM_CPCR_SRAMUAP_MASK)
7291 #define MCM_CPCR_SRAMUWP_MASK 0x4000000u
7292 #define MCM_CPCR_SRAMUWP_SHIFT 26u
7293 #define MCM_CPCR_SRAMUWP_WIDTH 1u
7294 #define MCM_CPCR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUWP_SHIFT))&MCM_CPCR_SRAMUWP_MASK)
7295 #define MCM_CPCR_SRAMLAP_MASK 0x30000000u
7296 #define MCM_CPCR_SRAMLAP_SHIFT 28u
7297 #define MCM_CPCR_SRAMLAP_WIDTH 2u
7298 #define MCM_CPCR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLAP_SHIFT))&MCM_CPCR_SRAMLAP_MASK)
7299 #define MCM_CPCR_SRAMLWP_MASK 0x40000000u
7300 #define MCM_CPCR_SRAMLWP_SHIFT 30u
7301 #define MCM_CPCR_SRAMLWP_WIDTH 1u
7302 #define MCM_CPCR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLWP_SHIFT))&MCM_CPCR_SRAMLWP_MASK)
7303 /* ISCR Bit Fields */
7304 #define MCM_ISCR_FIOC_MASK 0x100u
7305 #define MCM_ISCR_FIOC_SHIFT 8u
7306 #define MCM_ISCR_FIOC_WIDTH 1u
7307 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
7308 #define MCM_ISCR_FDZC_MASK 0x200u
7309 #define MCM_ISCR_FDZC_SHIFT 9u
7310 #define MCM_ISCR_FDZC_WIDTH 1u
7311 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
7312 #define MCM_ISCR_FOFC_MASK 0x400u
7313 #define MCM_ISCR_FOFC_SHIFT 10u
7314 #define MCM_ISCR_FOFC_WIDTH 1u
7315 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
7316 #define MCM_ISCR_FUFC_MASK 0x800u
7317 #define MCM_ISCR_FUFC_SHIFT 11u
7318 #define MCM_ISCR_FUFC_WIDTH 1u
7319 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
7320 #define MCM_ISCR_FIXC_MASK 0x1000u
7321 #define MCM_ISCR_FIXC_SHIFT 12u
7322 #define MCM_ISCR_FIXC_WIDTH 1u
7323 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
7324 #define MCM_ISCR_FIDC_MASK 0x8000u
7325 #define MCM_ISCR_FIDC_SHIFT 15u
7326 #define MCM_ISCR_FIDC_WIDTH 1u
7327 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
7328 #define MCM_ISCR_FIOCE_MASK 0x1000000u
7329 #define MCM_ISCR_FIOCE_SHIFT 24u
7330 #define MCM_ISCR_FIOCE_WIDTH 1u
7331 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
7332 #define MCM_ISCR_FDZCE_MASK 0x2000000u
7333 #define MCM_ISCR_FDZCE_SHIFT 25u
7334 #define MCM_ISCR_FDZCE_WIDTH 1u
7335 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
7336 #define MCM_ISCR_FOFCE_MASK 0x4000000u
7337 #define MCM_ISCR_FOFCE_SHIFT 26u
7338 #define MCM_ISCR_FOFCE_WIDTH 1u
7339 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
7340 #define MCM_ISCR_FUFCE_MASK 0x8000000u
7341 #define MCM_ISCR_FUFCE_SHIFT 27u
7342 #define MCM_ISCR_FUFCE_WIDTH 1u
7343 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
7344 #define MCM_ISCR_FIXCE_MASK 0x10000000u
7345 #define MCM_ISCR_FIXCE_SHIFT 28u
7346 #define MCM_ISCR_FIXCE_WIDTH 1u
7347 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
7348 #define MCM_ISCR_FIDCE_MASK 0x80000000u
7349 #define MCM_ISCR_FIDCE_SHIFT 31u
7350 #define MCM_ISCR_FIDCE_WIDTH 1u
7351 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
7352 /* PID Bit Fields */
7353 #define MCM_PID_PID_MASK 0xFFu
7354 #define MCM_PID_PID_SHIFT 0u
7355 #define MCM_PID_PID_WIDTH 8u
7356 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
7357 /* CPO Bit Fields */
7358 #define MCM_CPO_CPOREQ_MASK 0x1u
7359 #define MCM_CPO_CPOREQ_SHIFT 0u
7360 #define MCM_CPO_CPOREQ_WIDTH 1u
7361 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
7362 #define MCM_CPO_CPOACK_MASK 0x2u
7363 #define MCM_CPO_CPOACK_SHIFT 1u
7364 #define MCM_CPO_CPOACK_WIDTH 1u
7365 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
7366 #define MCM_CPO_CPOWOI_MASK 0x4u
7367 #define MCM_CPO_CPOWOI_SHIFT 2u
7368 #define MCM_CPO_CPOWOI_WIDTH 1u
7369 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
7370 /* LMDR Bit Fields */
7371 #define MCM_LMDR_CF0_MASK 0xFu
7372 #define MCM_LMDR_CF0_SHIFT 0u
7373 #define MCM_LMDR_CF0_WIDTH 4u
7374 #define MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF0_SHIFT))&MCM_LMDR_CF0_MASK)
7375 #define MCM_LMDR_CF1_MASK 0xF0u
7376 #define MCM_LMDR_CF1_SHIFT 4u
7377 #define MCM_LMDR_CF1_WIDTH 4u
7378 #define MCM_LMDR_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF1_SHIFT))&MCM_LMDR_CF1_MASK)
7379 #define MCM_LMDR_MT_MASK 0xE000u
7380 #define MCM_LMDR_MT_SHIFT 13u
7381 #define MCM_LMDR_MT_WIDTH 3u
7382 #define MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_MT_SHIFT))&MCM_LMDR_MT_MASK)
7383 #define MCM_LMDR_LOCK_MASK 0x10000u
7384 #define MCM_LMDR_LOCK_SHIFT 16u
7385 #define MCM_LMDR_LOCK_WIDTH 1u
7386 #define MCM_LMDR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LOCK_SHIFT))&MCM_LMDR_LOCK_MASK)
7387 #define MCM_LMDR_DPW_MASK 0xE0000u
7388 #define MCM_LMDR_DPW_SHIFT 17u
7389 #define MCM_LMDR_DPW_WIDTH 3u
7390 #define MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_DPW_SHIFT))&MCM_LMDR_DPW_MASK)
7391 #define MCM_LMDR_WY_MASK 0xF00000u
7392 #define MCM_LMDR_WY_SHIFT 20u
7393 #define MCM_LMDR_WY_WIDTH 4u
7394 #define MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_WY_SHIFT))&MCM_LMDR_WY_MASK)
7395 #define MCM_LMDR_LMSZ_MASK 0xF000000u
7396 #define MCM_LMDR_LMSZ_SHIFT 24u
7397 #define MCM_LMDR_LMSZ_WIDTH 4u
7398 #define MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZ_SHIFT))&MCM_LMDR_LMSZ_MASK)
7399 #define MCM_LMDR_LMSZH_MASK 0x10000000u
7400 #define MCM_LMDR_LMSZH_SHIFT 28u
7401 #define MCM_LMDR_LMSZH_WIDTH 1u
7402 #define MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZH_SHIFT))&MCM_LMDR_LMSZH_MASK)
7403 #define MCM_LMDR_V_MASK 0x80000000u
7404 #define MCM_LMDR_V_SHIFT 31u
7405 #define MCM_LMDR_V_WIDTH 1u
7406 #define MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_V_SHIFT))&MCM_LMDR_V_MASK)
7407 /* LMDR2 Bit Fields */
7408 #define MCM_LMDR2_CF1_MASK 0xF0u
7409 #define MCM_LMDR2_CF1_SHIFT 4u
7410 #define MCM_LMDR2_CF1_WIDTH 4u
7411 #define MCM_LMDR2_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_CF1_SHIFT))&MCM_LMDR2_CF1_MASK)
7412 #define MCM_LMDR2_MT_MASK 0xE000u
7413 #define MCM_LMDR2_MT_SHIFT 13u
7414 #define MCM_LMDR2_MT_WIDTH 3u
7415 #define MCM_LMDR2_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_MT_SHIFT))&MCM_LMDR2_MT_MASK)
7416 #define MCM_LMDR2_LOCK_MASK 0x10000u
7417 #define MCM_LMDR2_LOCK_SHIFT 16u
7418 #define MCM_LMDR2_LOCK_WIDTH 1u
7419 #define MCM_LMDR2_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LOCK_SHIFT))&MCM_LMDR2_LOCK_MASK)
7420 #define MCM_LMDR2_DPW_MASK 0xE0000u
7421 #define MCM_LMDR2_DPW_SHIFT 17u
7422 #define MCM_LMDR2_DPW_WIDTH 3u
7423 #define MCM_LMDR2_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_DPW_SHIFT))&MCM_LMDR2_DPW_MASK)
7424 #define MCM_LMDR2_WY_MASK 0xF00000u
7425 #define MCM_LMDR2_WY_SHIFT 20u
7426 #define MCM_LMDR2_WY_WIDTH 4u
7427 #define MCM_LMDR2_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_WY_SHIFT))&MCM_LMDR2_WY_MASK)
7428 #define MCM_LMDR2_LMSZ_MASK 0xF000000u
7429 #define MCM_LMDR2_LMSZ_SHIFT 24u
7430 #define MCM_LMDR2_LMSZ_WIDTH 4u
7431 #define MCM_LMDR2_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZ_SHIFT))&MCM_LMDR2_LMSZ_MASK)
7432 #define MCM_LMDR2_LMSZH_MASK 0x10000000u
7433 #define MCM_LMDR2_LMSZH_SHIFT 28u
7434 #define MCM_LMDR2_LMSZH_WIDTH 1u
7435 #define MCM_LMDR2_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZH_SHIFT))&MCM_LMDR2_LMSZH_MASK)
7436 #define MCM_LMDR2_V_MASK 0x80000000u
7437 #define MCM_LMDR2_V_SHIFT 31u
7438 #define MCM_LMDR2_V_WIDTH 1u
7439 #define MCM_LMDR2_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_V_SHIFT))&MCM_LMDR2_V_MASK)
7440 /* LMPECR Bit Fields */
7441 #define MCM_LMPECR_ERNCR_MASK 0x1u
7442 #define MCM_LMPECR_ERNCR_SHIFT 0u
7443 #define MCM_LMPECR_ERNCR_WIDTH 1u
7444 #define MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ERNCR_SHIFT))&MCM_LMPECR_ERNCR_MASK)
7445 #define MCM_LMPECR_ER1BR_MASK 0x100u
7446 #define MCM_LMPECR_ER1BR_SHIFT 8u
7447 #define MCM_LMPECR_ER1BR_WIDTH 1u
7448 #define MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ER1BR_SHIFT))&MCM_LMPECR_ER1BR_MASK)
7449 #define MCM_LMPECR_ECPR_MASK 0x100000u
7450 #define MCM_LMPECR_ECPR_SHIFT 20u
7451 #define MCM_LMPECR_ECPR_WIDTH 1u
7452 #define MCM_LMPECR_ECPR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ECPR_SHIFT))&MCM_LMPECR_ECPR_MASK)
7453 /* LMPEIR Bit Fields */
7454 #define MCM_LMPEIR_ENC_MASK 0xFFu
7455 #define MCM_LMPEIR_ENC_SHIFT 0u
7456 #define MCM_LMPEIR_ENC_WIDTH 8u
7457 #define MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_ENC_SHIFT))&MCM_LMPEIR_ENC_MASK)
7458 #define MCM_LMPEIR_E1B_MASK 0xFF00u
7459 #define MCM_LMPEIR_E1B_SHIFT 8u
7460 #define MCM_LMPEIR_E1B_WIDTH 8u
7461 #define MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_E1B_SHIFT))&MCM_LMPEIR_E1B_MASK)
7462 #define MCM_LMPEIR_PE_MASK 0xFF0000u
7463 #define MCM_LMPEIR_PE_SHIFT 16u
7464 #define MCM_LMPEIR_PE_WIDTH 8u
7465 #define MCM_LMPEIR_PE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PE_SHIFT))&MCM_LMPEIR_PE_MASK)
7466 #define MCM_LMPEIR_PEELOC_MASK 0x1F000000u
7467 #define MCM_LMPEIR_PEELOC_SHIFT 24u
7468 #define MCM_LMPEIR_PEELOC_WIDTH 5u
7469 #define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PEELOC_SHIFT))&MCM_LMPEIR_PEELOC_MASK)
7470 #define MCM_LMPEIR_V_MASK 0x80000000u
7471 #define MCM_LMPEIR_V_SHIFT 31u
7472 #define MCM_LMPEIR_V_WIDTH 1u
7473 #define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_V_SHIFT))&MCM_LMPEIR_V_MASK)
7474 /* LMFAR Bit Fields */
7475 #define MCM_LMFAR_EFADD_MASK 0xFFFFFFFFu
7476 #define MCM_LMFAR_EFADD_SHIFT 0u
7477 #define MCM_LMFAR_EFADD_WIDTH 32u
7478 #define MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFAR_EFADD_SHIFT))&MCM_LMFAR_EFADD_MASK)
7479 /* LMFATR Bit Fields */
7480 #define MCM_LMFATR_PEFPRT_MASK 0xFu
7481 #define MCM_LMFATR_PEFPRT_SHIFT 0u
7482 #define MCM_LMFATR_PEFPRT_WIDTH 4u
7483 #define MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFPRT_SHIFT))&MCM_LMFATR_PEFPRT_MASK)
7484 #define MCM_LMFATR_PEFSIZE_MASK 0x70u
7485 #define MCM_LMFATR_PEFSIZE_SHIFT 4u
7486 #define MCM_LMFATR_PEFSIZE_WIDTH 3u
7487 #define MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFSIZE_SHIFT))&MCM_LMFATR_PEFSIZE_MASK)
7488 #define MCM_LMFATR_PEFW_MASK 0x80u
7489 #define MCM_LMFATR_PEFW_SHIFT 7u
7490 #define MCM_LMFATR_PEFW_WIDTH 1u
7491 #define MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFW_SHIFT))&MCM_LMFATR_PEFW_MASK)
7492 #define MCM_LMFATR_PEFMST_MASK 0xFF00u
7493 #define MCM_LMFATR_PEFMST_SHIFT 8u
7494 #define MCM_LMFATR_PEFMST_WIDTH 8u
7495 #define MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFMST_SHIFT))&MCM_LMFATR_PEFMST_MASK)
7496 #define MCM_LMFATR_OVR_MASK 0x80000000u
7497 #define MCM_LMFATR_OVR_SHIFT 31u
7498 #define MCM_LMFATR_OVR_WIDTH 1u
7499 #define MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_OVR_SHIFT))&MCM_LMFATR_OVR_MASK)
7500 /* LMFDHR Bit Fields */
7501 #define MCM_LMFDHR_PEFDH_MASK 0xFFFFFFFFu
7502 #define MCM_LMFDHR_PEFDH_SHIFT 0u
7503 #define MCM_LMFDHR_PEFDH_WIDTH 32u
7504 #define MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDHR_PEFDH_SHIFT))&MCM_LMFDHR_PEFDH_MASK)
7505 /* LMFDLR Bit Fields */
7506 #define MCM_LMFDLR_PEFDL_MASK 0xFFFFFFFFu
7507 #define MCM_LMFDLR_PEFDL_SHIFT 0u
7508 #define MCM_LMFDLR_PEFDL_WIDTH 32u
7509 #define MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDLR_PEFDL_SHIFT))&MCM_LMFDLR_PEFDL_MASK)
7510  /* end of group MCM_Register_Masks */
7514 
7515  /* end of group MCM_Peripheral_Access_Layer */
7519 
7520 
7521 /* ----------------------------------------------------------------------------
7522  -- MPU Peripheral Access Layer
7523  ---------------------------------------------------------------------------- */
7524 
7532 #define MPU_EAR_EDR_COUNT 4u
7533 #define MPU_RGD_COUNT 8u
7534 #define MPU_RGDAAC_COUNT 8u
7535 
7537 typedef struct {
7538  __IO uint32_t CESR;
7539  uint8_t RESERVED_0[12];
7540  struct { /* offset: 0x10, array step: 0x8 */
7541  __I uint32_t EAR;
7544  __I uint32_t EDR;
7547  } EAR_EDR[MPU_EAR_EDR_COUNT];
7548  uint8_t RESERVED_1[976];
7549  struct { /* offset: 0x400, array step: 0x10 */
7550  __IO uint32_t WORD0;
7551  __IO uint32_t WORD1;
7552  __IO uint32_t WORD2;
7553  __IO uint32_t WORD3;
7554  } RGD[MPU_RGD_COUNT];
7555  uint8_t RESERVED_2[896];
7556  __IO uint32_t RGDAAC[MPU_RGDAAC_COUNT];
7560 
7562 #define MPU_INSTANCE_COUNT (1u)
7563 
7564 
7565 /* MPU - Peripheral instance base addresses */
7567 #define MPU_BASE (0x4000D000u)
7568 
7569 #define MPU ((MPU_Type *)MPU_BASE)
7570 
7571 #define MPU_BASE_ADDRS { MPU_BASE }
7572 
7573 #define MPU_BASE_PTRS { MPU }
7574 
7575 /* ----------------------------------------------------------------------------
7576  -- MPU Register Masks
7577  ---------------------------------------------------------------------------- */
7578 
7584 /* CESR Bit Fields */
7585 #define MPU_CESR_VLD_MASK 0x1u
7586 #define MPU_CESR_VLD_SHIFT 0u
7587 #define MPU_CESR_VLD_WIDTH 1u
7588 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
7589 #define MPU_CESR_NRGD_MASK 0xF00u
7590 #define MPU_CESR_NRGD_SHIFT 8u
7591 #define MPU_CESR_NRGD_WIDTH 4u
7592 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
7593 #define MPU_CESR_NSP_MASK 0xF000u
7594 #define MPU_CESR_NSP_SHIFT 12u
7595 #define MPU_CESR_NSP_WIDTH 4u
7596 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
7597 #define MPU_CESR_HRL_MASK 0xF0000u
7598 #define MPU_CESR_HRL_SHIFT 16u
7599 #define MPU_CESR_HRL_WIDTH 4u
7600 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
7601 #define MPU_CESR_SPERR3_MASK 0x10000000u
7602 #define MPU_CESR_SPERR3_SHIFT 28u
7603 #define MPU_CESR_SPERR3_WIDTH 1u
7604 #define MPU_CESR_SPERR3(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR3_SHIFT))&MPU_CESR_SPERR3_MASK)
7605 #define MPU_CESR_SPERR2_MASK 0x20000000u
7606 #define MPU_CESR_SPERR2_SHIFT 29u
7607 #define MPU_CESR_SPERR2_WIDTH 1u
7608 #define MPU_CESR_SPERR2(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR2_SHIFT))&MPU_CESR_SPERR2_MASK)
7609 #define MPU_CESR_SPERR1_MASK 0x40000000u
7610 #define MPU_CESR_SPERR1_SHIFT 30u
7611 #define MPU_CESR_SPERR1_WIDTH 1u
7612 #define MPU_CESR_SPERR1(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR1_SHIFT))&MPU_CESR_SPERR1_MASK)
7613 #define MPU_CESR_SPERR0_MASK 0x80000000u
7614 #define MPU_CESR_SPERR0_SHIFT 31u
7615 #define MPU_CESR_SPERR0_WIDTH 1u
7616 #define MPU_CESR_SPERR0(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR0_SHIFT))&MPU_CESR_SPERR0_MASK)
7617 /* EAR Bit Fields */
7618 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
7619 #define MPU_EAR_EADDR_SHIFT 0u
7620 #define MPU_EAR_EADDR_WIDTH 32u
7621 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
7622 /* EDR Bit Fields */
7623 #define MPU_EDR_ERW_MASK 0x1u
7624 #define MPU_EDR_ERW_SHIFT 0u
7625 #define MPU_EDR_ERW_WIDTH 1u
7626 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
7627 #define MPU_EDR_EATTR_MASK 0xEu
7628 #define MPU_EDR_EATTR_SHIFT 1u
7629 #define MPU_EDR_EATTR_WIDTH 3u
7630 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
7631 #define MPU_EDR_EMN_MASK 0xF0u
7632 #define MPU_EDR_EMN_SHIFT 4u
7633 #define MPU_EDR_EMN_WIDTH 4u
7634 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
7635 #define MPU_EDR_EPID_MASK 0xFF00u
7636 #define MPU_EDR_EPID_SHIFT 8u
7637 #define MPU_EDR_EPID_WIDTH 8u
7638 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
7639 #define MPU_EDR_EACD_MASK 0xFFFF0000u
7640 #define MPU_EDR_EACD_SHIFT 16u
7641 #define MPU_EDR_EACD_WIDTH 16u
7642 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
7643 /* RGD_WORD0 Bit Fields */
7644 #define MPU_RGD_WORD0_SRTADDR_MASK 0xFFFFFFE0u
7645 #define MPU_RGD_WORD0_SRTADDR_SHIFT 5u
7646 #define MPU_RGD_WORD0_SRTADDR_WIDTH 27u
7647 #define MPU_RGD_WORD0_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD0_SRTADDR_SHIFT))&MPU_RGD_WORD0_SRTADDR_MASK)
7648 /* RGD_WORD1 Bit Fields */
7649 #define MPU_RGD_WORD1_ENDADDR_MASK 0xFFFFFFE0u
7650 #define MPU_RGD_WORD1_ENDADDR_SHIFT 5u
7651 #define MPU_RGD_WORD1_ENDADDR_WIDTH 27u
7652 #define MPU_RGD_WORD1_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD1_ENDADDR_SHIFT))&MPU_RGD_WORD1_ENDADDR_MASK)
7653 /* RGD_WORD2 Bit Fields */
7654 #define MPU_RGD_WORD2_M0UM_MASK 0x7u
7655 #define MPU_RGD_WORD2_M0UM_SHIFT 0u
7656 #define MPU_RGD_WORD2_M0UM_WIDTH 3u
7657 #define MPU_RGD_WORD2_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0UM_SHIFT))&MPU_RGD_WORD2_M0UM_MASK)
7658 #define MPU_RGD_WORD2_M0SM_MASK 0x18u
7659 #define MPU_RGD_WORD2_M0SM_SHIFT 3u
7660 #define MPU_RGD_WORD2_M0SM_WIDTH 2u
7661 #define MPU_RGD_WORD2_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0SM_SHIFT))&MPU_RGD_WORD2_M0SM_MASK)
7662 #define MPU_RGD_WORD2_M0PE_MASK 0x20u
7663 #define MPU_RGD_WORD2_M0PE_SHIFT 5u
7664 #define MPU_RGD_WORD2_M0PE_WIDTH 1u
7665 #define MPU_RGD_WORD2_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0PE_SHIFT))&MPU_RGD_WORD2_M0PE_MASK)
7666 #define MPU_RGD_WORD2_M1UM_MASK 0x1C0u
7667 #define MPU_RGD_WORD2_M1UM_SHIFT 6u
7668 #define MPU_RGD_WORD2_M1UM_WIDTH 3u
7669 #define MPU_RGD_WORD2_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1UM_SHIFT))&MPU_RGD_WORD2_M1UM_MASK)
7670 #define MPU_RGD_WORD2_M1SM_MASK 0x600u
7671 #define MPU_RGD_WORD2_M1SM_SHIFT 9u
7672 #define MPU_RGD_WORD2_M1SM_WIDTH 2u
7673 #define MPU_RGD_WORD2_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1SM_SHIFT))&MPU_RGD_WORD2_M1SM_MASK)
7674 #define MPU_RGD_WORD2_M1PE_MASK 0x800u
7675 #define MPU_RGD_WORD2_M1PE_SHIFT 11u
7676 #define MPU_RGD_WORD2_M1PE_WIDTH 1u
7677 #define MPU_RGD_WORD2_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1PE_SHIFT))&MPU_RGD_WORD2_M1PE_MASK)
7678 #define MPU_RGD_WORD2_M2UM_MASK 0x7000u
7679 #define MPU_RGD_WORD2_M2UM_SHIFT 12u
7680 #define MPU_RGD_WORD2_M2UM_WIDTH 3u
7681 #define MPU_RGD_WORD2_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2UM_SHIFT))&MPU_RGD_WORD2_M2UM_MASK)
7682 #define MPU_RGD_WORD2_M2SM_MASK 0x18000u
7683 #define MPU_RGD_WORD2_M2SM_SHIFT 15u
7684 #define MPU_RGD_WORD2_M2SM_WIDTH 2u
7685 #define MPU_RGD_WORD2_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2SM_SHIFT))&MPU_RGD_WORD2_M2SM_MASK)
7686 #define MPU_RGD_WORD2_M3UM_MASK 0x1C0000u
7687 #define MPU_RGD_WORD2_M3UM_SHIFT 18u
7688 #define MPU_RGD_WORD2_M3UM_WIDTH 3u
7689 #define MPU_RGD_WORD2_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3UM_SHIFT))&MPU_RGD_WORD2_M3UM_MASK)
7690 #define MPU_RGD_WORD2_M3SM_MASK 0x600000u
7691 #define MPU_RGD_WORD2_M3SM_SHIFT 21u
7692 #define MPU_RGD_WORD2_M3SM_WIDTH 2u
7693 #define MPU_RGD_WORD2_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3SM_SHIFT))&MPU_RGD_WORD2_M3SM_MASK)
7694 #define MPU_RGD_WORD2_M4WE_MASK 0x1000000u
7695 #define MPU_RGD_WORD2_M4WE_SHIFT 24u
7696 #define MPU_RGD_WORD2_M4WE_WIDTH 1u
7697 #define MPU_RGD_WORD2_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4WE_SHIFT))&MPU_RGD_WORD2_M4WE_MASK)
7698 #define MPU_RGD_WORD2_M4RE_MASK 0x2000000u
7699 #define MPU_RGD_WORD2_M4RE_SHIFT 25u
7700 #define MPU_RGD_WORD2_M4RE_WIDTH 1u
7701 #define MPU_RGD_WORD2_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4RE_SHIFT))&MPU_RGD_WORD2_M4RE_MASK)
7702 #define MPU_RGD_WORD2_M5WE_MASK 0x4000000u
7703 #define MPU_RGD_WORD2_M5WE_SHIFT 26u
7704 #define MPU_RGD_WORD2_M5WE_WIDTH 1u
7705 #define MPU_RGD_WORD2_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5WE_SHIFT))&MPU_RGD_WORD2_M5WE_MASK)
7706 #define MPU_RGD_WORD2_M5RE_MASK 0x8000000u
7707 #define MPU_RGD_WORD2_M5RE_SHIFT 27u
7708 #define MPU_RGD_WORD2_M5RE_WIDTH 1u
7709 #define MPU_RGD_WORD2_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5RE_SHIFT))&MPU_RGD_WORD2_M5RE_MASK)
7710 #define MPU_RGD_WORD2_M6WE_MASK 0x10000000u
7711 #define MPU_RGD_WORD2_M6WE_SHIFT 28u
7712 #define MPU_RGD_WORD2_M6WE_WIDTH 1u
7713 #define MPU_RGD_WORD2_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6WE_SHIFT))&MPU_RGD_WORD2_M6WE_MASK)
7714 #define MPU_RGD_WORD2_M6RE_MASK 0x20000000u
7715 #define MPU_RGD_WORD2_M6RE_SHIFT 29u
7716 #define MPU_RGD_WORD2_M6RE_WIDTH 1u
7717 #define MPU_RGD_WORD2_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6RE_SHIFT))&MPU_RGD_WORD2_M6RE_MASK)
7718 #define MPU_RGD_WORD2_M7WE_MASK 0x40000000u
7719 #define MPU_RGD_WORD2_M7WE_SHIFT 30u
7720 #define MPU_RGD_WORD2_M7WE_WIDTH 1u
7721 #define MPU_RGD_WORD2_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7WE_SHIFT))&MPU_RGD_WORD2_M7WE_MASK)
7722 #define MPU_RGD_WORD2_M7RE_MASK 0x80000000u
7723 #define MPU_RGD_WORD2_M7RE_SHIFT 31u
7724 #define MPU_RGD_WORD2_M7RE_WIDTH 1u
7725 #define MPU_RGD_WORD2_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7RE_SHIFT))&MPU_RGD_WORD2_M7RE_MASK)
7726 /* RGD_WORD3 Bit Fields */
7727 #define MPU_RGD_WORD3_VLD_MASK 0x1u
7728 #define MPU_RGD_WORD3_VLD_SHIFT 0u
7729 #define MPU_RGD_WORD3_VLD_WIDTH 1u
7730 #define MPU_RGD_WORD3_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_VLD_SHIFT))&MPU_RGD_WORD3_VLD_MASK)
7731 #define MPU_RGD_WORD3_PIDMASK_MASK 0xFF0000u
7732 #define MPU_RGD_WORD3_PIDMASK_SHIFT 16u
7733 #define MPU_RGD_WORD3_PIDMASK_WIDTH 8u
7734 #define MPU_RGD_WORD3_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PIDMASK_SHIFT))&MPU_RGD_WORD3_PIDMASK_MASK)
7735 #define MPU_RGD_WORD3_PID_MASK 0xFF000000u
7736 #define MPU_RGD_WORD3_PID_SHIFT 24u
7737 #define MPU_RGD_WORD3_PID_WIDTH 8u
7738 #define MPU_RGD_WORD3_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PID_SHIFT))&MPU_RGD_WORD3_PID_MASK)
7739 /* RGDAAC Bit Fields */
7740 #define MPU_RGDAAC_M0UM_MASK 0x7u
7741 #define MPU_RGDAAC_M0UM_SHIFT 0u
7742 #define MPU_RGDAAC_M0UM_WIDTH 3u
7743 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
7744 #define MPU_RGDAAC_M0SM_MASK 0x18u
7745 #define MPU_RGDAAC_M0SM_SHIFT 3u
7746 #define MPU_RGDAAC_M0SM_WIDTH 2u
7747 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
7748 #define MPU_RGDAAC_M0PE_MASK 0x20u
7749 #define MPU_RGDAAC_M0PE_SHIFT 5u
7750 #define MPU_RGDAAC_M0PE_WIDTH 1u
7751 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
7752 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
7753 #define MPU_RGDAAC_M1UM_SHIFT 6u
7754 #define MPU_RGDAAC_M1UM_WIDTH 3u
7755 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
7756 #define MPU_RGDAAC_M1SM_MASK 0x600u
7757 #define MPU_RGDAAC_M1SM_SHIFT 9u
7758 #define MPU_RGDAAC_M1SM_WIDTH 2u
7759 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
7760 #define MPU_RGDAAC_M1PE_MASK 0x800u
7761 #define MPU_RGDAAC_M1PE_SHIFT 11u
7762 #define MPU_RGDAAC_M1PE_WIDTH 1u
7763 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
7764 #define MPU_RGDAAC_M2UM_MASK 0x7000u
7765 #define MPU_RGDAAC_M2UM_SHIFT 12u
7766 #define MPU_RGDAAC_M2UM_WIDTH 3u
7767 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
7768 #define MPU_RGDAAC_M2SM_MASK 0x18000u
7769 #define MPU_RGDAAC_M2SM_SHIFT 15u
7770 #define MPU_RGDAAC_M2SM_WIDTH 2u
7771 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
7772 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
7773 #define MPU_RGDAAC_M3UM_SHIFT 18u
7774 #define MPU_RGDAAC_M3UM_WIDTH 3u
7775 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
7776 #define MPU_RGDAAC_M3SM_MASK 0x600000u
7777 #define MPU_RGDAAC_M3SM_SHIFT 21u
7778 #define MPU_RGDAAC_M3SM_WIDTH 2u
7779 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
7780 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
7781 #define MPU_RGDAAC_M4WE_SHIFT 24u
7782 #define MPU_RGDAAC_M4WE_WIDTH 1u
7783 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
7784 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
7785 #define MPU_RGDAAC_M4RE_SHIFT 25u
7786 #define MPU_RGDAAC_M4RE_WIDTH 1u
7787 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
7788 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
7789 #define MPU_RGDAAC_M5WE_SHIFT 26u
7790 #define MPU_RGDAAC_M5WE_WIDTH 1u
7791 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
7792 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
7793 #define MPU_RGDAAC_M5RE_SHIFT 27u
7794 #define MPU_RGDAAC_M5RE_WIDTH 1u
7795 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
7796 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
7797 #define MPU_RGDAAC_M6WE_SHIFT 28u
7798 #define MPU_RGDAAC_M6WE_WIDTH 1u
7799 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
7800 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
7801 #define MPU_RGDAAC_M6RE_SHIFT 29u
7802 #define MPU_RGDAAC_M6RE_WIDTH 1u
7803 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
7804 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
7805 #define MPU_RGDAAC_M7WE_SHIFT 30u
7806 #define MPU_RGDAAC_M7WE_WIDTH 1u
7807 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
7808 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
7809 #define MPU_RGDAAC_M7RE_SHIFT 31u
7810 #define MPU_RGDAAC_M7RE_WIDTH 1u
7811 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
7812  /* end of group MPU_Register_Masks */
7816 
7817  /* end of group MPU_Peripheral_Access_Layer */
7821 
7822 
7823 /* ----------------------------------------------------------------------------
7824  -- MSCM Peripheral Access Layer
7825  ---------------------------------------------------------------------------- */
7826 
7834 #define MSCM_OCMDR_COUNT 4u
7835 
7837 typedef struct {
7838  __I uint32_t CPxTYPE;
7839  __I uint32_t CPxNUM;
7840  __I uint32_t CPxMASTER;
7841  __I uint32_t CPxCOUNT;
7842  __I uint32_t CPxCFG0;
7843  __I uint32_t CPxCFG1;
7844  __I uint32_t CPxCFG2;
7845  __I uint32_t CPxCFG3;
7846  __I uint32_t CP0TYPE;
7847  __I uint32_t CP0NUM;
7848  __I uint32_t CP0MASTER;
7849  __I uint32_t CP0COUNT;
7850  __I uint32_t CP0CFG0;
7851  __I uint32_t CP0CFG1;
7852  __I uint32_t CP0CFG2;
7853  __I uint32_t CP0CFG3;
7854  uint8_t RESERVED_0[960];
7855  __IO uint32_t OCMDR[MSCM_OCMDR_COUNT];
7857 
7859 #define MSCM_INSTANCE_COUNT (1u)
7860 
7861 
7862 /* MSCM - Peripheral instance base addresses */
7864 #define MSCM_BASE (0x40001000u)
7865 
7866 #define MSCM ((MSCM_Type *)MSCM_BASE)
7867 
7868 #define MSCM_BASE_ADDRS { MSCM_BASE }
7869 
7870 #define MSCM_BASE_PTRS { MSCM }
7871 
7872 /* ----------------------------------------------------------------------------
7873  -- MSCM Register Masks
7874  ---------------------------------------------------------------------------- */
7875 
7881 /* CPxTYPE Bit Fields */
7882 #define MSCM_CPxTYPE_RYPZ_MASK 0xFFu
7883 #define MSCM_CPxTYPE_RYPZ_SHIFT 0u
7884 #define MSCM_CPxTYPE_RYPZ_WIDTH 8u
7885 #define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_RYPZ_SHIFT))&MSCM_CPxTYPE_RYPZ_MASK)
7886 #define MSCM_CPxTYPE_PERSONALITY_MASK 0xFFFFFF00u
7887 #define MSCM_CPxTYPE_PERSONALITY_SHIFT 8u
7888 #define MSCM_CPxTYPE_PERSONALITY_WIDTH 24u
7889 #define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_PERSONALITY_SHIFT))&MSCM_CPxTYPE_PERSONALITY_MASK)
7890 /* CPxNUM Bit Fields */
7891 #define MSCM_CPxNUM_CPN_MASK 0x1u
7892 #define MSCM_CPxNUM_CPN_SHIFT 0u
7893 #define MSCM_CPxNUM_CPN_WIDTH 1u
7894 #define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxNUM_CPN_SHIFT))&MSCM_CPxNUM_CPN_MASK)
7895 /* CPxMASTER Bit Fields */
7896 #define MSCM_CPxMASTER_PPMN_MASK 0x3Fu
7897 #define MSCM_CPxMASTER_PPMN_SHIFT 0u
7898 #define MSCM_CPxMASTER_PPMN_WIDTH 6u
7899 #define MSCM_CPxMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxMASTER_PPMN_SHIFT))&MSCM_CPxMASTER_PPMN_MASK)
7900 /* CPxCOUNT Bit Fields */
7901 #define MSCM_CPxCOUNT_PCNT_MASK 0x3u
7902 #define MSCM_CPxCOUNT_PCNT_SHIFT 0u
7903 #define MSCM_CPxCOUNT_PCNT_WIDTH 2u
7904 #define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCOUNT_PCNT_SHIFT))&MSCM_CPxCOUNT_PCNT_MASK)
7905 /* CPxCFG0 Bit Fields */
7906 #define MSCM_CPxCFG0_DCWY_MASK 0xFFu
7907 #define MSCM_CPxCFG0_DCWY_SHIFT 0u
7908 #define MSCM_CPxCFG0_DCWY_WIDTH 8u
7909 #define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCWY_SHIFT))&MSCM_CPxCFG0_DCWY_MASK)
7910 #define MSCM_CPxCFG0_DCSZ_MASK 0xFF00u
7911 #define MSCM_CPxCFG0_DCSZ_SHIFT 8u
7912 #define MSCM_CPxCFG0_DCSZ_WIDTH 8u
7913 #define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCSZ_SHIFT))&MSCM_CPxCFG0_DCSZ_MASK)
7914 #define MSCM_CPxCFG0_ICWY_MASK 0xFF0000u
7915 #define MSCM_CPxCFG0_ICWY_SHIFT 16u
7916 #define MSCM_CPxCFG0_ICWY_WIDTH 8u
7917 #define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICWY_SHIFT))&MSCM_CPxCFG0_ICWY_MASK)
7918 #define MSCM_CPxCFG0_ICSZ_MASK 0xFF000000u
7919 #define MSCM_CPxCFG0_ICSZ_SHIFT 24u
7920 #define MSCM_CPxCFG0_ICSZ_WIDTH 8u
7921 #define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICSZ_SHIFT))&MSCM_CPxCFG0_ICSZ_MASK)
7922 /* CPxCFG1 Bit Fields */
7923 #define MSCM_CPxCFG1_L2WY_MASK 0xFF0000u
7924 #define MSCM_CPxCFG1_L2WY_SHIFT 16u
7925 #define MSCM_CPxCFG1_L2WY_WIDTH 8u
7926 #define MSCM_CPxCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2WY_SHIFT))&MSCM_CPxCFG1_L2WY_MASK)
7927 #define MSCM_CPxCFG1_L2SZ_MASK 0xFF000000u
7928 #define MSCM_CPxCFG1_L2SZ_SHIFT 24u
7929 #define MSCM_CPxCFG1_L2SZ_WIDTH 8u
7930 #define MSCM_CPxCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2SZ_SHIFT))&MSCM_CPxCFG1_L2SZ_MASK)
7931 /* CPxCFG2 Bit Fields */
7932 #define MSCM_CPxCFG2_TMUSZ_MASK 0xFF00u
7933 #define MSCM_CPxCFG2_TMUSZ_SHIFT 8u
7934 #define MSCM_CPxCFG2_TMUSZ_WIDTH 8u
7935 #define MSCM_CPxCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMUSZ_SHIFT))&MSCM_CPxCFG2_TMUSZ_MASK)
7936 #define MSCM_CPxCFG2_TMLSZ_MASK 0xFF000000u
7937 #define MSCM_CPxCFG2_TMLSZ_SHIFT 24u
7938 #define MSCM_CPxCFG2_TMLSZ_WIDTH 8u
7939 #define MSCM_CPxCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMLSZ_SHIFT))&MSCM_CPxCFG2_TMLSZ_MASK)
7940 /* CPxCFG3 Bit Fields */
7941 #define MSCM_CPxCFG3_FPU_MASK 0x1u
7942 #define MSCM_CPxCFG3_FPU_SHIFT 0u
7943 #define MSCM_CPxCFG3_FPU_WIDTH 1u
7944 #define MSCM_CPxCFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_FPU_SHIFT))&MSCM_CPxCFG3_FPU_MASK)
7945 #define MSCM_CPxCFG3_SIMD_MASK 0x2u
7946 #define MSCM_CPxCFG3_SIMD_SHIFT 1u
7947 #define MSCM_CPxCFG3_SIMD_WIDTH 1u
7948 #define MSCM_CPxCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SIMD_SHIFT))&MSCM_CPxCFG3_SIMD_MASK)
7949 #define MSCM_CPxCFG3_JAZ_MASK 0x4u
7950 #define MSCM_CPxCFG3_JAZ_SHIFT 2u
7951 #define MSCM_CPxCFG3_JAZ_WIDTH 1u
7952 #define MSCM_CPxCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_JAZ_SHIFT))&MSCM_CPxCFG3_JAZ_MASK)
7953 #define MSCM_CPxCFG3_MMU_MASK 0x8u
7954 #define MSCM_CPxCFG3_MMU_SHIFT 3u
7955 #define MSCM_CPxCFG3_MMU_WIDTH 1u
7956 #define MSCM_CPxCFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_MMU_SHIFT))&MSCM_CPxCFG3_MMU_MASK)
7957 #define MSCM_CPxCFG3_TZ_MASK 0x10u
7958 #define MSCM_CPxCFG3_TZ_SHIFT 4u
7959 #define MSCM_CPxCFG3_TZ_WIDTH 1u
7960 #define MSCM_CPxCFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_TZ_SHIFT))&MSCM_CPxCFG3_TZ_MASK)
7961 #define MSCM_CPxCFG3_CMP_MASK 0x20u
7962 #define MSCM_CPxCFG3_CMP_SHIFT 5u
7963 #define MSCM_CPxCFG3_CMP_WIDTH 1u
7964 #define MSCM_CPxCFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_CMP_SHIFT))&MSCM_CPxCFG3_CMP_MASK)
7965 #define MSCM_CPxCFG3_BB_MASK 0x40u
7966 #define MSCM_CPxCFG3_BB_SHIFT 6u
7967 #define MSCM_CPxCFG3_BB_WIDTH 1u
7968 #define MSCM_CPxCFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_BB_SHIFT))&MSCM_CPxCFG3_BB_MASK)
7969 #define MSCM_CPxCFG3_SBP_MASK 0x300u
7970 #define MSCM_CPxCFG3_SBP_SHIFT 8u
7971 #define MSCM_CPxCFG3_SBP_WIDTH 2u
7972 #define MSCM_CPxCFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SBP_SHIFT))&MSCM_CPxCFG3_SBP_MASK)
7973 /* CP0TYPE Bit Fields */
7974 #define MSCM_CP0TYPE_RYPZ_MASK 0xFFu
7975 #define MSCM_CP0TYPE_RYPZ_SHIFT 0u
7976 #define MSCM_CP0TYPE_RYPZ_WIDTH 8u
7977 #define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_RYPZ_SHIFT))&MSCM_CP0TYPE_RYPZ_MASK)
7978 #define MSCM_CP0TYPE_PERSONALITY_MASK 0xFFFFFF00u
7979 #define MSCM_CP0TYPE_PERSONALITY_SHIFT 8u
7980 #define MSCM_CP0TYPE_PERSONALITY_WIDTH 24u
7981 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_PERSONALITY_SHIFT))&MSCM_CP0TYPE_PERSONALITY_MASK)
7982 /* CP0NUM Bit Fields */
7983 #define MSCM_CP0NUM_CPN_MASK 0x1u
7984 #define MSCM_CP0NUM_CPN_SHIFT 0u
7985 #define MSCM_CP0NUM_CPN_WIDTH 1u
7986 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0NUM_CPN_SHIFT))&MSCM_CP0NUM_CPN_MASK)
7987 /* CP0MASTER Bit Fields */
7988 #define MSCM_CP0MASTER_PPMN_MASK 0x3Fu
7989 #define MSCM_CP0MASTER_PPMN_SHIFT 0u
7990 #define MSCM_CP0MASTER_PPMN_WIDTH 6u
7991 #define MSCM_CP0MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0MASTER_PPMN_SHIFT))&MSCM_CP0MASTER_PPMN_MASK)
7992 /* CP0COUNT Bit Fields */
7993 #define MSCM_CP0COUNT_PCNT_MASK 0x3u
7994 #define MSCM_CP0COUNT_PCNT_SHIFT 0u
7995 #define MSCM_CP0COUNT_PCNT_WIDTH 2u
7996 #define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0COUNT_PCNT_SHIFT))&MSCM_CP0COUNT_PCNT_MASK)
7997 /* CP0CFG0 Bit Fields */
7998 #define MSCM_CP0CFG0_DCWY_MASK 0xFFu
7999 #define MSCM_CP0CFG0_DCWY_SHIFT 0u
8000 #define MSCM_CP0CFG0_DCWY_WIDTH 8u
8001 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCWY_SHIFT))&MSCM_CP0CFG0_DCWY_MASK)
8002 #define MSCM_CP0CFG0_DCSZ_MASK 0xFF00u
8003 #define MSCM_CP0CFG0_DCSZ_SHIFT 8u
8004 #define MSCM_CP0CFG0_DCSZ_WIDTH 8u
8005 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCSZ_SHIFT))&MSCM_CP0CFG0_DCSZ_MASK)
8006 #define MSCM_CP0CFG0_ICWY_MASK 0xFF0000u
8007 #define MSCM_CP0CFG0_ICWY_SHIFT 16u
8008 #define MSCM_CP0CFG0_ICWY_WIDTH 8u
8009 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICWY_SHIFT))&MSCM_CP0CFG0_ICWY_MASK)
8010 #define MSCM_CP0CFG0_ICSZ_MASK 0xFF000000u
8011 #define MSCM_CP0CFG0_ICSZ_SHIFT 24u
8012 #define MSCM_CP0CFG0_ICSZ_WIDTH 8u
8013 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICSZ_SHIFT))&MSCM_CP0CFG0_ICSZ_MASK)
8014 /* CP0CFG1 Bit Fields */
8015 #define MSCM_CP0CFG1_L2WY_MASK 0xFF0000u
8016 #define MSCM_CP0CFG1_L2WY_SHIFT 16u
8017 #define MSCM_CP0CFG1_L2WY_WIDTH 8u
8018 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2WY_SHIFT))&MSCM_CP0CFG1_L2WY_MASK)
8019 #define MSCM_CP0CFG1_L2SZ_MASK 0xFF000000u
8020 #define MSCM_CP0CFG1_L2SZ_SHIFT 24u
8021 #define MSCM_CP0CFG1_L2SZ_WIDTH 8u
8022 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2SZ_SHIFT))&MSCM_CP0CFG1_L2SZ_MASK)
8023 /* CP0CFG2 Bit Fields */
8024 #define MSCM_CP0CFG2_TMUSZ_MASK 0xFF00u
8025 #define MSCM_CP0CFG2_TMUSZ_SHIFT 8u
8026 #define MSCM_CP0CFG2_TMUSZ_WIDTH 8u
8027 #define MSCM_CP0CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMUSZ_SHIFT))&MSCM_CP0CFG2_TMUSZ_MASK)
8028 #define MSCM_CP0CFG2_TMLSZ_MASK 0xFF000000u
8029 #define MSCM_CP0CFG2_TMLSZ_SHIFT 24u
8030 #define MSCM_CP0CFG2_TMLSZ_WIDTH 8u
8031 #define MSCM_CP0CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMLSZ_SHIFT))&MSCM_CP0CFG2_TMLSZ_MASK)
8032 /* CP0CFG3 Bit Fields */
8033 #define MSCM_CP0CFG3_FPU_MASK 0x1u
8034 #define MSCM_CP0CFG3_FPU_SHIFT 0u
8035 #define MSCM_CP0CFG3_FPU_WIDTH 1u
8036 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_FPU_SHIFT))&MSCM_CP0CFG3_FPU_MASK)
8037 #define MSCM_CP0CFG3_SIMD_MASK 0x2u
8038 #define MSCM_CP0CFG3_SIMD_SHIFT 1u
8039 #define MSCM_CP0CFG3_SIMD_WIDTH 1u
8040 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SIMD_SHIFT))&MSCM_CP0CFG3_SIMD_MASK)
8041 #define MSCM_CP0CFG3_JAZ_MASK 0x4u
8042 #define MSCM_CP0CFG3_JAZ_SHIFT 2u
8043 #define MSCM_CP0CFG3_JAZ_WIDTH 1u
8044 #define MSCM_CP0CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_JAZ_SHIFT))&MSCM_CP0CFG3_JAZ_MASK)
8045 #define MSCM_CP0CFG3_MMU_MASK 0x8u
8046 #define MSCM_CP0CFG3_MMU_SHIFT 3u
8047 #define MSCM_CP0CFG3_MMU_WIDTH 1u
8048 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_MMU_SHIFT))&MSCM_CP0CFG3_MMU_MASK)
8049 #define MSCM_CP0CFG3_TZ_MASK 0x10u
8050 #define MSCM_CP0CFG3_TZ_SHIFT 4u
8051 #define MSCM_CP0CFG3_TZ_WIDTH 1u
8052 #define MSCM_CP0CFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_TZ_SHIFT))&MSCM_CP0CFG3_TZ_MASK)
8053 #define MSCM_CP0CFG3_CMP_MASK 0x20u
8054 #define MSCM_CP0CFG3_CMP_SHIFT 5u
8055 #define MSCM_CP0CFG3_CMP_WIDTH 1u
8056 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_CMP_SHIFT))&MSCM_CP0CFG3_CMP_MASK)
8057 #define MSCM_CP0CFG3_BB_MASK 0x40u
8058 #define MSCM_CP0CFG3_BB_SHIFT 6u
8059 #define MSCM_CP0CFG3_BB_WIDTH 1u
8060 #define MSCM_CP0CFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_BB_SHIFT))&MSCM_CP0CFG3_BB_MASK)
8061 #define MSCM_CP0CFG3_SBP_MASK 0x300u
8062 #define MSCM_CP0CFG3_SBP_SHIFT 8u
8063 #define MSCM_CP0CFG3_SBP_WIDTH 2u
8064 #define MSCM_CP0CFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SBP_SHIFT))&MSCM_CP0CFG3_SBP_MASK)
8065 /* OCMDR Bit Fields */
8066 #define MSCM_OCMDR_OCM0_MASK 0xFu
8067 #define MSCM_OCMDR_OCM0_SHIFT 0u
8068 #define MSCM_OCMDR_OCM0_WIDTH 4u
8069 #define MSCM_OCMDR_OCM0(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM0_SHIFT))&MSCM_OCMDR_OCM0_MASK)
8070 #define MSCM_OCMDR_OCM1_MASK 0xF0u
8071 #define MSCM_OCMDR_OCM1_SHIFT 4u
8072 #define MSCM_OCMDR_OCM1_WIDTH 4u
8073 #define MSCM_OCMDR_OCM1(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM1_SHIFT))&MSCM_OCMDR_OCM1_MASK)
8074 #define MSCM_OCMDR_OCM2_MASK 0xF00u
8075 #define MSCM_OCMDR_OCM2_SHIFT 8u
8076 #define MSCM_OCMDR_OCM2_WIDTH 4u
8077 #define MSCM_OCMDR_OCM2(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM2_SHIFT))&MSCM_OCMDR_OCM2_MASK)
8078 #define MSCM_OCMDR_OCMPU_MASK 0x1000u
8079 #define MSCM_OCMDR_OCMPU_SHIFT 12u
8080 #define MSCM_OCMDR_OCMPU_WIDTH 1u
8081 #define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMPU_SHIFT))&MSCM_OCMDR_OCMPU_MASK)
8082 #define MSCM_OCMDR_OCMT_MASK 0xE000u
8083 #define MSCM_OCMDR_OCMT_SHIFT 13u
8084 #define MSCM_OCMDR_OCMT_WIDTH 3u
8085 #define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMT_SHIFT))&MSCM_OCMDR_OCMT_MASK)
8086 #define MSCM_OCMDR_RO_MASK 0x10000u
8087 #define MSCM_OCMDR_RO_SHIFT 16u
8088 #define MSCM_OCMDR_RO_WIDTH 1u
8089 #define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_RO_SHIFT))&MSCM_OCMDR_RO_MASK)
8090 #define MSCM_OCMDR_OCMW_MASK 0xE0000u
8091 #define MSCM_OCMDR_OCMW_SHIFT 17u
8092 #define MSCM_OCMDR_OCMW_WIDTH 3u
8093 #define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMW_SHIFT))&MSCM_OCMDR_OCMW_MASK)
8094 #define MSCM_OCMDR_OCMSZ_MASK 0xF000000u
8095 #define MSCM_OCMDR_OCMSZ_SHIFT 24u
8096 #define MSCM_OCMDR_OCMSZ_WIDTH 4u
8097 #define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZ_SHIFT))&MSCM_OCMDR_OCMSZ_MASK)
8098 #define MSCM_OCMDR_OCMSZH_MASK 0x10000000u
8099 #define MSCM_OCMDR_OCMSZH_SHIFT 28u
8100 #define MSCM_OCMDR_OCMSZH_WIDTH 1u
8101 #define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZH_SHIFT))&MSCM_OCMDR_OCMSZH_MASK)
8102 #define MSCM_OCMDR_V_MASK 0x80000000u
8103 #define MSCM_OCMDR_V_SHIFT 31u
8104 #define MSCM_OCMDR_V_WIDTH 1u
8105 #define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_V_SHIFT))&MSCM_OCMDR_V_MASK)
8106  /* end of group MSCM_Register_Masks */
8110 
8111  /* end of group MSCM_Peripheral_Access_Layer */
8115 
8116 
8117 /* ----------------------------------------------------------------------------
8118  -- PCC Peripheral Access Layer
8119  ---------------------------------------------------------------------------- */
8120 
8128 #define PCC_PCCn_COUNT 116u
8129 
8131 typedef struct {
8132  __IO uint32_t PCCn[PCC_PCCn_COUNT];
8134 
8136 #define PCC_INSTANCE_COUNT (1u)
8137 
8138 
8139 /* PCC - Peripheral instance base addresses */
8141 #define PCC_BASE (0x40065000u)
8142 
8143 #define PCC ((PCC_Type *)PCC_BASE)
8144 
8145 #define PCC_BASE_ADDRS { PCC_BASE }
8146 
8147 #define PCC_BASE_PTRS { PCC }
8148 
8149 /* PCC index offsets */
8150 #define PCC_FTFC_INDEX 32
8151 #define PCC_DMAMUX_INDEX 33
8152 #define PCC_FlexCAN0_INDEX 36
8153 #define PCC_FlexCAN1_INDEX 37
8154 #define PCC_FTM3_INDEX 38
8155 #define PCC_ADC1_INDEX 39
8156 #define PCC_FlexCAN2_INDEX 43
8157 #define PCC_LPSPI0_INDEX 44
8158 #define PCC_LPSPI1_INDEX 45
8159 #define PCC_LPSPI2_INDEX 46
8160 #define PCC_PDB1_INDEX 49
8161 #define PCC_CRC_INDEX 50
8162 #define PCC_PDB0_INDEX 54
8163 #define PCC_LPIT_INDEX 55
8164 #define PCC_FTM0_INDEX 56
8165 #define PCC_FTM1_INDEX 57
8166 #define PCC_FTM2_INDEX 58
8167 #define PCC_ADC0_INDEX 59
8168 #define PCC_RTC_INDEX 61
8169 #define PCC_LPTMR0_INDEX 64
8170 #define PCC_PORTA_INDEX 73
8171 #define PCC_PORTB_INDEX 74
8172 #define PCC_PORTC_INDEX 75
8173 #define PCC_PORTD_INDEX 76
8174 #define PCC_PORTE_INDEX 77
8175 #define PCC_FlexIO_INDEX 90
8176 #define PCC_EWM_INDEX 97
8177 #define PCC_LPI2C0_INDEX 102
8178 #define PCC_LPUART0_INDEX 106
8179 #define PCC_LPUART1_INDEX 107
8180 #define PCC_LPUART2_INDEX 108
8181 #define PCC_CMP0_INDEX 115
8182 
8183 /* ----------------------------------------------------------------------------
8184  -- PCC Register Masks
8185  ---------------------------------------------------------------------------- */
8186 
8192 /* PCCn Bit Fields */
8193 #define PCC_PCCn_PCD_MASK 0x7u
8194 #define PCC_PCCn_PCD_SHIFT 0u
8195 #define PCC_PCCn_PCD_WIDTH 3u
8196 #define PCC_PCCn_PCD(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCD_SHIFT))&PCC_PCCn_PCD_MASK)
8197 #define PCC_PCCn_FRAC_MASK 0x8u
8198 #define PCC_PCCn_FRAC_SHIFT 3u
8199 #define PCC_PCCn_FRAC_WIDTH 1u
8200 #define PCC_PCCn_FRAC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_FRAC_SHIFT))&PCC_PCCn_FRAC_MASK)
8201 #define PCC_PCCn_PCS_MASK 0x7000000u
8202 #define PCC_PCCn_PCS_SHIFT 24u
8203 #define PCC_PCCn_PCS_WIDTH 3u
8204 #define PCC_PCCn_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCS_SHIFT))&PCC_PCCn_PCS_MASK)
8205 #define PCC_PCCn_CGC_MASK 0x40000000u
8206 #define PCC_PCCn_CGC_SHIFT 30u
8207 #define PCC_PCCn_CGC_WIDTH 1u
8208 #define PCC_PCCn_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_CGC_SHIFT))&PCC_PCCn_CGC_MASK)
8209 #define PCC_PCCn_PR_MASK 0x80000000u
8210 #define PCC_PCCn_PR_SHIFT 31u
8211 #define PCC_PCCn_PR_WIDTH 1u
8212 #define PCC_PCCn_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PR_SHIFT))&PCC_PCCn_PR_MASK)
8213  /* end of group PCC_Register_Masks */
8217 
8218  /* end of group PCC_Peripheral_Access_Layer */
8222 
8223 
8224 /* ----------------------------------------------------------------------------
8225  -- PDB Peripheral Access Layer
8226  ---------------------------------------------------------------------------- */
8227 
8235 #define PDB_CH_COUNT 2u
8236 #define PDB_DLY_COUNT 8u
8237 #define PDB_POnDLY_COUNT 1u
8238 
8240 typedef struct {
8241  __IO uint32_t SC;
8242  __IO uint32_t MOD;
8243  __I uint32_t CNT;
8244  __IO uint32_t IDLY;
8245  struct { /* offset: 0x10, array step: 0x28 */
8246  __IO uint32_t C1;
8247  __IO uint32_t S;
8248  __IO uint32_t DLY[PDB_DLY_COUNT];
8249  } CH[PDB_CH_COUNT];
8250  uint8_t RESERVED_0[304];
8251  __IO uint32_t POEN;
8252  union { /* offset: 0x194, array step: 0x4 */
8253  __IO uint32_t PODLY;
8254  struct { /* offset: 0x194, array step: 0x4 */
8255  __IO uint16_t DLY2;
8256  __IO uint16_t DLY1;
8257  } ACCESS16BIT;
8258  } POnDLY[PDB_POnDLY_COUNT];
8260 
8262 #define PDB_INSTANCE_COUNT (2u)
8263 
8264 
8265 /* PDB - Peripheral instance base addresses */
8267 #define PDB0_BASE (0x40036000u)
8268 
8269 #define PDB0 ((PDB_Type *)PDB0_BASE)
8270 
8271 #define PDB1_BASE (0x40031000u)
8272 
8273 #define PDB1 ((PDB_Type *)PDB1_BASE)
8274 
8275 #define PDB_BASE_ADDRS { PDB0_BASE, PDB1_BASE }
8276 
8277 #define PDB_BASE_PTRS { PDB0, PDB1 }
8278 
8279 #define PDB_IRQS_ARR_COUNT (1u)
8280 
8281 #define PDB_IRQS_CH_COUNT (1u)
8282 
8283 #define PDB_IRQS { PDB0_IRQn, PDB1_IRQn }
8284 
8285 /* ----------------------------------------------------------------------------
8286  -- PDB Register Masks
8287  ---------------------------------------------------------------------------- */
8288 
8294 /* SC Bit Fields */
8295 #define PDB_SC_LDOK_MASK 0x1u
8296 #define PDB_SC_LDOK_SHIFT 0u
8297 #define PDB_SC_LDOK_WIDTH 1u
8298 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
8299 #define PDB_SC_CONT_MASK 0x2u
8300 #define PDB_SC_CONT_SHIFT 1u
8301 #define PDB_SC_CONT_WIDTH 1u
8302 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
8303 #define PDB_SC_MULT_MASK 0xCu
8304 #define PDB_SC_MULT_SHIFT 2u
8305 #define PDB_SC_MULT_WIDTH 2u
8306 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
8307 #define PDB_SC_PDBIE_MASK 0x20u
8308 #define PDB_SC_PDBIE_SHIFT 5u
8309 #define PDB_SC_PDBIE_WIDTH 1u
8310 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
8311 #define PDB_SC_PDBIF_MASK 0x40u
8312 #define PDB_SC_PDBIF_SHIFT 6u
8313 #define PDB_SC_PDBIF_WIDTH 1u
8314 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
8315 #define PDB_SC_PDBEN_MASK 0x80u
8316 #define PDB_SC_PDBEN_SHIFT 7u
8317 #define PDB_SC_PDBEN_WIDTH 1u
8318 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
8319 #define PDB_SC_TRGSEL_MASK 0xF00u
8320 #define PDB_SC_TRGSEL_SHIFT 8u
8321 #define PDB_SC_TRGSEL_WIDTH 4u
8322 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
8323 #define PDB_SC_PRESCALER_MASK 0x7000u
8324 #define PDB_SC_PRESCALER_SHIFT 12u
8325 #define PDB_SC_PRESCALER_WIDTH 3u
8326 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
8327 #define PDB_SC_DMAEN_MASK 0x8000u
8328 #define PDB_SC_DMAEN_SHIFT 15u
8329 #define PDB_SC_DMAEN_WIDTH 1u
8330 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
8331 #define PDB_SC_SWTRIG_MASK 0x10000u
8332 #define PDB_SC_SWTRIG_SHIFT 16u
8333 #define PDB_SC_SWTRIG_WIDTH 1u
8334 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
8335 #define PDB_SC_PDBEIE_MASK 0x20000u
8336 #define PDB_SC_PDBEIE_SHIFT 17u
8337 #define PDB_SC_PDBEIE_WIDTH 1u
8338 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
8339 #define PDB_SC_LDMOD_MASK 0xC0000u
8340 #define PDB_SC_LDMOD_SHIFT 18u
8341 #define PDB_SC_LDMOD_WIDTH 2u
8342 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
8343 /* MOD Bit Fields */
8344 #define PDB_MOD_MOD_MASK 0xFFFFu
8345 #define PDB_MOD_MOD_SHIFT 0u
8346 #define PDB_MOD_MOD_WIDTH 16u
8347 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
8348 /* CNT Bit Fields */
8349 #define PDB_CNT_CNT_MASK 0xFFFFu
8350 #define PDB_CNT_CNT_SHIFT 0u
8351 #define PDB_CNT_CNT_WIDTH 16u
8352 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
8353 /* IDLY Bit Fields */
8354 #define PDB_IDLY_IDLY_MASK 0xFFFFu
8355 #define PDB_IDLY_IDLY_SHIFT 0u
8356 #define PDB_IDLY_IDLY_WIDTH 16u
8357 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
8358 /* C1 Bit Fields */
8359 #define PDB_C1_EN_MASK 0xFFu
8360 #define PDB_C1_EN_SHIFT 0u
8361 #define PDB_C1_EN_WIDTH 8u
8362 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
8363 #define PDB_C1_TOS_MASK 0xFF00u
8364 #define PDB_C1_TOS_SHIFT 8u
8365 #define PDB_C1_TOS_WIDTH 8u
8366 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
8367 #define PDB_C1_BB_MASK 0xFF0000u
8368 #define PDB_C1_BB_SHIFT 16u
8369 #define PDB_C1_BB_WIDTH 8u
8370 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
8371 /* S Bit Fields */
8372 #define PDB_S_ERR_MASK 0xFFu
8373 #define PDB_S_ERR_SHIFT 0u
8374 #define PDB_S_ERR_WIDTH 8u
8375 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
8376 #define PDB_S_CF_MASK 0xFF0000u
8377 #define PDB_S_CF_SHIFT 16u
8378 #define PDB_S_CF_WIDTH 8u
8379 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
8380 /* DLY Bit Fields */
8381 #define PDB_DLY_DLY_MASK 0xFFFFu
8382 #define PDB_DLY_DLY_SHIFT 0u
8383 #define PDB_DLY_DLY_WIDTH 16u
8384 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
8385 /* POEN Bit Fields */
8386 #define PDB_POEN_POEN_MASK 0xFFu
8387 #define PDB_POEN_POEN_SHIFT 0u
8388 #define PDB_POEN_POEN_WIDTH 8u
8389 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
8390 /* POnDLY_PODLY Bit Fields */
8391 #define PDB_POnDLY_PODLY_DLY2_MASK 0xFFFFu
8392 #define PDB_POnDLY_PODLY_DLY2_SHIFT 0u
8393 #define PDB_POnDLY_PODLY_DLY2_WIDTH 16u
8394 #define PDB_POnDLY_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY2_SHIFT))&PDB_POnDLY_PODLY_DLY2_MASK)
8395 #define PDB_POnDLY_PODLY_DLY1_MASK 0xFFFF0000u
8396 #define PDB_POnDLY_PODLY_DLY1_SHIFT 16u
8397 #define PDB_POnDLY_PODLY_DLY1_WIDTH 16u
8398 #define PDB_POnDLY_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY1_SHIFT))&PDB_POnDLY_PODLY_DLY1_MASK)
8399 /* POnDLY_ACCESS16BIT_DLY2 Bit Fields */
8400 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK 0xFFFFu
8401 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT 0u
8402 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_WIDTH 16u
8403 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK)
8404 /* POnDLY_ACCESS16BIT_DLY1 Bit Fields */
8405 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK 0xFFFFu
8406 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT 0u
8407 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_WIDTH 16u
8408 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK)
8409  /* end of group PDB_Register_Masks */
8413 
8414  /* end of group PDB_Peripheral_Access_Layer */
8418 
8419 
8420 /* ----------------------------------------------------------------------------
8421  -- PMC Peripheral Access Layer
8422  ---------------------------------------------------------------------------- */
8423 
8433 typedef struct {
8434  __IO uint8_t LVDSC1;
8435  __IO uint8_t LVDSC2;
8436  __IO uint8_t REGSC;
8437  uint8_t RESERVED_0[1];
8438  __IO uint8_t LPOTRIM;
8440 
8442 #define PMC_INSTANCE_COUNT (1u)
8443 
8444 
8445 /* PMC - Peripheral instance base addresses */
8447 #define PMC_BASE (0x4007D000u)
8448 
8449 #define PMC ((PMC_Type *)PMC_BASE)
8450 
8451 #define PMC_BASE_ADDRS { PMC_BASE }
8452 
8453 #define PMC_BASE_PTRS { PMC }
8454 
8455 #define PMC_IRQS_ARR_COUNT (1u)
8456 
8457 #define PMC_IRQS_CH_COUNT (1u)
8458 
8459 #define PMC_IRQS { LVD_LVW_IRQn }
8460 
8461 /* ----------------------------------------------------------------------------
8462  -- PMC Register Masks
8463  ---------------------------------------------------------------------------- */
8464 
8470 /* LVDSC1 Bit Fields */
8471 #define PMC_LVDSC1_LVDRE_MASK 0x10u
8472 #define PMC_LVDSC1_LVDRE_SHIFT 4u
8473 #define PMC_LVDSC1_LVDRE_WIDTH 1u
8474 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
8475 #define PMC_LVDSC1_LVDIE_MASK 0x20u
8476 #define PMC_LVDSC1_LVDIE_SHIFT 5u
8477 #define PMC_LVDSC1_LVDIE_WIDTH 1u
8478 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
8479 #define PMC_LVDSC1_LVDACK_MASK 0x40u
8480 #define PMC_LVDSC1_LVDACK_SHIFT 6u
8481 #define PMC_LVDSC1_LVDACK_WIDTH 1u
8482 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
8483 #define PMC_LVDSC1_LVDF_MASK 0x80u
8484 #define PMC_LVDSC1_LVDF_SHIFT 7u
8485 #define PMC_LVDSC1_LVDF_WIDTH 1u
8486 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
8487 /* LVDSC2 Bit Fields */
8488 #define PMC_LVDSC2_LVWIE_MASK 0x20u
8489 #define PMC_LVDSC2_LVWIE_SHIFT 5u
8490 #define PMC_LVDSC2_LVWIE_WIDTH 1u
8491 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
8492 #define PMC_LVDSC2_LVWACK_MASK 0x40u
8493 #define PMC_LVDSC2_LVWACK_SHIFT 6u
8494 #define PMC_LVDSC2_LVWACK_WIDTH 1u
8495 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
8496 #define PMC_LVDSC2_LVWF_MASK 0x80u
8497 #define PMC_LVDSC2_LVWF_SHIFT 7u
8498 #define PMC_LVDSC2_LVWF_WIDTH 1u
8499 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
8500 /* REGSC Bit Fields */
8501 #define PMC_REGSC_BIASEN_MASK 0x1u
8502 #define PMC_REGSC_BIASEN_SHIFT 0u
8503 #define PMC_REGSC_BIASEN_WIDTH 1u
8504 #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BIASEN_SHIFT))&PMC_REGSC_BIASEN_MASK)
8505 #define PMC_REGSC_CLKBIASDIS_MASK 0x2u
8506 #define PMC_REGSC_CLKBIASDIS_SHIFT 1u
8507 #define PMC_REGSC_CLKBIASDIS_WIDTH 1u
8508 #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_CLKBIASDIS_SHIFT))&PMC_REGSC_CLKBIASDIS_MASK)
8509 #define PMC_REGSC_REGFPM_MASK 0x4u
8510 #define PMC_REGSC_REGFPM_SHIFT 2u
8511 #define PMC_REGSC_REGFPM_WIDTH 1u
8512 #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGFPM_SHIFT))&PMC_REGSC_REGFPM_MASK)
8513 #define PMC_REGSC_LPOSTAT_MASK 0x40u
8514 #define PMC_REGSC_LPOSTAT_SHIFT 6u
8515 #define PMC_REGSC_LPOSTAT_WIDTH 1u
8516 #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPOSTAT_SHIFT))&PMC_REGSC_LPOSTAT_MASK)
8517 #define PMC_REGSC_LPODIS_MASK 0x80u
8518 #define PMC_REGSC_LPODIS_SHIFT 7u
8519 #define PMC_REGSC_LPODIS_WIDTH 1u
8520 #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPODIS_SHIFT))&PMC_REGSC_LPODIS_MASK)
8521 /* LPOTRIM Bit Fields */
8522 #define PMC_LPOTRIM_LPOTRIM_MASK 0x1Fu
8523 #define PMC_LPOTRIM_LPOTRIM_SHIFT 0u
8524 #define PMC_LPOTRIM_LPOTRIM_WIDTH 5u
8525 #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x))<<PMC_LPOTRIM_LPOTRIM_SHIFT))&PMC_LPOTRIM_LPOTRIM_MASK)
8526  /* end of group PMC_Register_Masks */
8530 
8531  /* end of group PMC_Peripheral_Access_Layer */
8535 
8536 
8537 /* ----------------------------------------------------------------------------
8538  -- PORT Peripheral Access Layer
8539  ---------------------------------------------------------------------------- */
8540 
8548 #define PORT_PCR_COUNT 32u
8549 
8551 typedef struct {
8552  __IO uint32_t PCR[PORT_PCR_COUNT];
8553  __O uint32_t GPCLR;
8554  __O uint32_t GPCHR;
8555  uint8_t RESERVED_0[24];
8556  __IO uint32_t ISFR;
8557  uint8_t RESERVED_1[28];
8558  __IO uint32_t DFER;
8559  __IO uint32_t DFCR;
8560  __IO uint32_t DFWR;
8562 
8564 #define PORT_INSTANCE_COUNT (5u)
8565 
8566 
8567 /* PORT - Peripheral instance base addresses */
8569 #define PORTA_BASE (0x40049000u)
8570 
8571 #define PORTA ((PORT_Type *)PORTA_BASE)
8572 
8573 #define PORTB_BASE (0x4004A000u)
8574 
8575 #define PORTB ((PORT_Type *)PORTB_BASE)
8576 
8577 #define PORTC_BASE (0x4004B000u)
8578 
8579 #define PORTC ((PORT_Type *)PORTC_BASE)
8580 
8581 #define PORTD_BASE (0x4004C000u)
8582 
8583 #define PORTD ((PORT_Type *)PORTD_BASE)
8584 
8585 #define PORTE_BASE (0x4004D000u)
8586 
8587 #define PORTE ((PORT_Type *)PORTE_BASE)
8588 
8589 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
8590 
8591 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
8592 
8593 #define PORT_IRQS_ARR_COUNT (1u)
8594 
8595 #define PORT_IRQS_CH_COUNT (1u)
8596 
8597 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
8598 
8599 /* ----------------------------------------------------------------------------
8600  -- PORT Register Masks
8601  ---------------------------------------------------------------------------- */
8602 
8608 /* PCR Bit Fields */
8609 #define PORT_PCR_PS_MASK 0x1u
8610 #define PORT_PCR_PS_SHIFT 0u
8611 #define PORT_PCR_PS_WIDTH 1u
8612 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
8613 #define PORT_PCR_PE_MASK 0x2u
8614 #define PORT_PCR_PE_SHIFT 1u
8615 #define PORT_PCR_PE_WIDTH 1u
8616 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
8617 #define PORT_PCR_PFE_MASK 0x10u
8618 #define PORT_PCR_PFE_SHIFT 4u
8619 #define PORT_PCR_PFE_WIDTH 1u
8620 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
8621 #define PORT_PCR_DSE_MASK 0x40u
8622 #define PORT_PCR_DSE_SHIFT 6u
8623 #define PORT_PCR_DSE_WIDTH 1u
8624 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
8625 #define PORT_PCR_MUX_MASK 0x700u
8626 #define PORT_PCR_MUX_SHIFT 8u
8627 #define PORT_PCR_MUX_WIDTH 3u
8628 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
8629 #define PORT_PCR_LK_MASK 0x8000u
8630 #define PORT_PCR_LK_SHIFT 15u
8631 #define PORT_PCR_LK_WIDTH 1u
8632 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
8633 #define PORT_PCR_IRQC_MASK 0xF0000u
8634 #define PORT_PCR_IRQC_SHIFT 16u
8635 #define PORT_PCR_IRQC_WIDTH 4u
8636 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
8637 #define PORT_PCR_ISF_MASK 0x1000000u
8638 #define PORT_PCR_ISF_SHIFT 24u
8639 #define PORT_PCR_ISF_WIDTH 1u
8640 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
8641 /* GPCLR Bit Fields */
8642 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
8643 #define PORT_GPCLR_GPWD_SHIFT 0u
8644 #define PORT_GPCLR_GPWD_WIDTH 16u
8645 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
8646 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
8647 #define PORT_GPCLR_GPWE_SHIFT 16u
8648 #define PORT_GPCLR_GPWE_WIDTH 16u
8649 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
8650 /* GPCHR Bit Fields */
8651 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
8652 #define PORT_GPCHR_GPWD_SHIFT 0u
8653 #define PORT_GPCHR_GPWD_WIDTH 16u
8654 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
8655 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
8656 #define PORT_GPCHR_GPWE_SHIFT 16u
8657 #define PORT_GPCHR_GPWE_WIDTH 16u
8658 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
8659 /* ISFR Bit Fields */
8660 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
8661 #define PORT_ISFR_ISF_SHIFT 0u
8662 #define PORT_ISFR_ISF_WIDTH 32u
8663 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
8664 /* DFER Bit Fields */
8665 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
8666 #define PORT_DFER_DFE_SHIFT 0u
8667 #define PORT_DFER_DFE_WIDTH 32u
8668 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
8669 /* DFCR Bit Fields */
8670 #define PORT_DFCR_CS_MASK 0x1u
8671 #define PORT_DFCR_CS_SHIFT 0u
8672 #define PORT_DFCR_CS_WIDTH 1u
8673 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
8674 /* DFWR Bit Fields */
8675 #define PORT_DFWR_FILT_MASK 0x1Fu
8676 #define PORT_DFWR_FILT_SHIFT 0u
8677 #define PORT_DFWR_FILT_WIDTH 5u
8678 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
8679  /* end of group PORT_Register_Masks */
8683 
8684  /* end of group PORT_Peripheral_Access_Layer */
8688 
8689 
8690 /* ----------------------------------------------------------------------------
8691  -- RCM Peripheral Access Layer
8692  ---------------------------------------------------------------------------- */
8693 
8703 typedef struct {
8704  __I uint32_t VERID;
8705  __I uint32_t PARAM;
8706  __I uint32_t SRS;
8707  __IO uint32_t RPC;
8708  uint8_t RESERVED_0[8];
8709  __IO uint32_t SSRS;
8710  __IO uint32_t SRIE;
8712 
8714 #define RCM_INSTANCE_COUNT (1u)
8715 
8716 
8717 /* RCM - Peripheral instance base addresses */
8719 #define RCM_BASE (0x4007F000u)
8720 
8721 #define RCM ((RCM_Type *)RCM_BASE)
8722 
8723 #define RCM_BASE_ADDRS { RCM_BASE }
8724 
8725 #define RCM_BASE_PTRS { RCM }
8726 
8727 #define RCM_IRQS_ARR_COUNT (1u)
8728 
8729 #define RCM_IRQS_CH_COUNT (1u)
8730 
8731 #define RCM_IRQS { RCM_IRQn }
8732 
8733 /* ----------------------------------------------------------------------------
8734  -- RCM Register Masks
8735  ---------------------------------------------------------------------------- */
8736 
8742 /* VERID Bit Fields */
8743 #define RCM_VERID_FEATURE_MASK 0xFFFFu
8744 #define RCM_VERID_FEATURE_SHIFT 0u
8745 #define RCM_VERID_FEATURE_WIDTH 16u
8746 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_FEATURE_SHIFT))&RCM_VERID_FEATURE_MASK)
8747 #define RCM_VERID_MINOR_MASK 0xFF0000u
8748 #define RCM_VERID_MINOR_SHIFT 16u
8749 #define RCM_VERID_MINOR_WIDTH 8u
8750 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MINOR_SHIFT))&RCM_VERID_MINOR_MASK)
8751 #define RCM_VERID_MAJOR_MASK 0xFF000000u
8752 #define RCM_VERID_MAJOR_SHIFT 24u
8753 #define RCM_VERID_MAJOR_WIDTH 8u
8754 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MAJOR_SHIFT))&RCM_VERID_MAJOR_MASK)
8755 /* PARAM Bit Fields */
8756 #define RCM_PARAM_EWAKEUP_MASK 0x1u
8757 #define RCM_PARAM_EWAKEUP_SHIFT 0u
8758 #define RCM_PARAM_EWAKEUP_WIDTH 1u
8759 #define RCM_PARAM_EWAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWAKEUP_SHIFT))&RCM_PARAM_EWAKEUP_MASK)
8760 #define RCM_PARAM_ELVD_MASK 0x2u
8761 #define RCM_PARAM_ELVD_SHIFT 1u
8762 #define RCM_PARAM_ELVD_WIDTH 1u
8763 #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELVD_SHIFT))&RCM_PARAM_ELVD_MASK)
8764 #define RCM_PARAM_ELOC_MASK 0x4u
8765 #define RCM_PARAM_ELOC_SHIFT 2u
8766 #define RCM_PARAM_ELOC_WIDTH 1u
8767 #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOC_SHIFT))&RCM_PARAM_ELOC_MASK)
8768 #define RCM_PARAM_ELOL_MASK 0x8u
8769 #define RCM_PARAM_ELOL_SHIFT 3u
8770 #define RCM_PARAM_ELOL_WIDTH 1u
8771 #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOL_SHIFT))&RCM_PARAM_ELOL_MASK)
8772 #define RCM_PARAM_EWDOG_MASK 0x20u
8773 #define RCM_PARAM_EWDOG_SHIFT 5u
8774 #define RCM_PARAM_EWDOG_WIDTH 1u
8775 #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWDOG_SHIFT))&RCM_PARAM_EWDOG_MASK)
8776 #define RCM_PARAM_EPIN_MASK 0x40u
8777 #define RCM_PARAM_EPIN_SHIFT 6u
8778 #define RCM_PARAM_EPIN_WIDTH 1u
8779 #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPIN_SHIFT))&RCM_PARAM_EPIN_MASK)
8780 #define RCM_PARAM_EPOR_MASK 0x80u
8781 #define RCM_PARAM_EPOR_SHIFT 7u
8782 #define RCM_PARAM_EPOR_WIDTH 1u
8783 #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPOR_SHIFT))&RCM_PARAM_EPOR_MASK)
8784 #define RCM_PARAM_EJTAG_MASK 0x100u
8785 #define RCM_PARAM_EJTAG_SHIFT 8u
8786 #define RCM_PARAM_EJTAG_WIDTH 1u
8787 #define RCM_PARAM_EJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EJTAG_SHIFT))&RCM_PARAM_EJTAG_MASK)
8788 #define RCM_PARAM_ELOCKUP_MASK 0x200u
8789 #define RCM_PARAM_ELOCKUP_SHIFT 9u
8790 #define RCM_PARAM_ELOCKUP_WIDTH 1u
8791 #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOCKUP_SHIFT))&RCM_PARAM_ELOCKUP_MASK)
8792 #define RCM_PARAM_ESW_MASK 0x400u
8793 #define RCM_PARAM_ESW_SHIFT 10u
8794 #define RCM_PARAM_ESW_WIDTH 1u
8795 #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESW_SHIFT))&RCM_PARAM_ESW_MASK)
8796 #define RCM_PARAM_EMDM_AP_MASK 0x800u
8797 #define RCM_PARAM_EMDM_AP_SHIFT 11u
8798 #define RCM_PARAM_EMDM_AP_WIDTH 1u
8799 #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EMDM_AP_SHIFT))&RCM_PARAM_EMDM_AP_MASK)
8800 #define RCM_PARAM_ESACKERR_MASK 0x2000u
8801 #define RCM_PARAM_ESACKERR_SHIFT 13u
8802 #define RCM_PARAM_ESACKERR_WIDTH 1u
8803 #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESACKERR_SHIFT))&RCM_PARAM_ESACKERR_MASK)
8804 #define RCM_PARAM_ETAMPER_MASK 0x8000u
8805 #define RCM_PARAM_ETAMPER_SHIFT 15u
8806 #define RCM_PARAM_ETAMPER_WIDTH 1u
8807 #define RCM_PARAM_ETAMPER(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ETAMPER_SHIFT))&RCM_PARAM_ETAMPER_MASK)
8808 #define RCM_PARAM_ECORE1_MASK 0x10000u
8809 #define RCM_PARAM_ECORE1_SHIFT 16u
8810 #define RCM_PARAM_ECORE1_WIDTH 1u
8811 #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ECORE1_SHIFT))&RCM_PARAM_ECORE1_MASK)
8812 /* SRS Bit Fields */
8813 #define RCM_SRS_LVD_MASK 0x2u
8814 #define RCM_SRS_LVD_SHIFT 1u
8815 #define RCM_SRS_LVD_WIDTH 1u
8816 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LVD_SHIFT))&RCM_SRS_LVD_MASK)
8817 #define RCM_SRS_LOC_MASK 0x4u
8818 #define RCM_SRS_LOC_SHIFT 2u
8819 #define RCM_SRS_LOC_WIDTH 1u
8820 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOC_SHIFT))&RCM_SRS_LOC_MASK)
8821 #define RCM_SRS_LOL_MASK 0x8u
8822 #define RCM_SRS_LOL_SHIFT 3u
8823 #define RCM_SRS_LOL_WIDTH 1u
8824 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOL_SHIFT))&RCM_SRS_LOL_MASK)
8825 #define RCM_SRS_WDOG_MASK 0x20u
8826 #define RCM_SRS_WDOG_SHIFT 5u
8827 #define RCM_SRS_WDOG_WIDTH 1u
8828 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_WDOG_SHIFT))&RCM_SRS_WDOG_MASK)
8829 #define RCM_SRS_PIN_MASK 0x40u
8830 #define RCM_SRS_PIN_SHIFT 6u
8831 #define RCM_SRS_PIN_WIDTH 1u
8832 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_PIN_SHIFT))&RCM_SRS_PIN_MASK)
8833 #define RCM_SRS_POR_MASK 0x80u
8834 #define RCM_SRS_POR_SHIFT 7u
8835 #define RCM_SRS_POR_WIDTH 1u
8836 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_POR_SHIFT))&RCM_SRS_POR_MASK)
8837 #define RCM_SRS_JTAG_MASK 0x100u
8838 #define RCM_SRS_JTAG_SHIFT 8u
8839 #define RCM_SRS_JTAG_WIDTH 1u
8840 #define RCM_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_JTAG_SHIFT))&RCM_SRS_JTAG_MASK)
8841 #define RCM_SRS_LOCKUP_MASK 0x200u
8842 #define RCM_SRS_LOCKUP_SHIFT 9u
8843 #define RCM_SRS_LOCKUP_WIDTH 1u
8844 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOCKUP_SHIFT))&RCM_SRS_LOCKUP_MASK)
8845 #define RCM_SRS_SW_MASK 0x400u
8846 #define RCM_SRS_SW_SHIFT 10u
8847 #define RCM_SRS_SW_WIDTH 1u
8848 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SW_SHIFT))&RCM_SRS_SW_MASK)
8849 #define RCM_SRS_MDM_AP_MASK 0x800u
8850 #define RCM_SRS_MDM_AP_SHIFT 11u
8851 #define RCM_SRS_MDM_AP_WIDTH 1u
8852 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_MDM_AP_SHIFT))&RCM_SRS_MDM_AP_MASK)
8853 #define RCM_SRS_SACKERR_MASK 0x2000u
8854 #define RCM_SRS_SACKERR_SHIFT 13u
8855 #define RCM_SRS_SACKERR_WIDTH 1u
8856 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SACKERR_SHIFT))&RCM_SRS_SACKERR_MASK)
8857 /* RPC Bit Fields */
8858 #define RCM_RPC_RSTFLTSRW_MASK 0x3u
8859 #define RCM_RPC_RSTFLTSRW_SHIFT 0u
8860 #define RCM_RPC_RSTFLTSRW_WIDTH 2u
8861 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSRW_SHIFT))&RCM_RPC_RSTFLTSRW_MASK)
8862 #define RCM_RPC_RSTFLTSS_MASK 0x4u
8863 #define RCM_RPC_RSTFLTSS_SHIFT 2u
8864 #define RCM_RPC_RSTFLTSS_WIDTH 1u
8865 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSS_SHIFT))&RCM_RPC_RSTFLTSS_MASK)
8866 #define RCM_RPC_RSTFLTSEL_MASK 0x1F00u
8867 #define RCM_RPC_RSTFLTSEL_SHIFT 8u
8868 #define RCM_RPC_RSTFLTSEL_WIDTH 5u
8869 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSEL_SHIFT))&RCM_RPC_RSTFLTSEL_MASK)
8870 /* SSRS Bit Fields */
8871 #define RCM_SSRS_SLVD_MASK 0x2u
8872 #define RCM_SSRS_SLVD_SHIFT 1u
8873 #define RCM_SSRS_SLVD_WIDTH 1u
8874 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLVD_SHIFT))&RCM_SSRS_SLVD_MASK)
8875 #define RCM_SSRS_SLOC_MASK 0x4u
8876 #define RCM_SSRS_SLOC_SHIFT 2u
8877 #define RCM_SSRS_SLOC_WIDTH 1u
8878 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOC_SHIFT))&RCM_SSRS_SLOC_MASK)
8879 #define RCM_SSRS_SLOL_MASK 0x8u
8880 #define RCM_SSRS_SLOL_SHIFT 3u
8881 #define RCM_SSRS_SLOL_WIDTH 1u
8882 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOL_SHIFT))&RCM_SSRS_SLOL_MASK)
8883 #define RCM_SSRS_SWDOG_MASK 0x20u
8884 #define RCM_SSRS_SWDOG_SHIFT 5u
8885 #define RCM_SSRS_SWDOG_WIDTH 1u
8886 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SWDOG_SHIFT))&RCM_SSRS_SWDOG_MASK)
8887 #define RCM_SSRS_SPIN_MASK 0x40u
8888 #define RCM_SSRS_SPIN_SHIFT 6u
8889 #define RCM_SSRS_SPIN_WIDTH 1u
8890 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPIN_SHIFT))&RCM_SSRS_SPIN_MASK)
8891 #define RCM_SSRS_SPOR_MASK 0x80u
8892 #define RCM_SSRS_SPOR_SHIFT 7u
8893 #define RCM_SSRS_SPOR_WIDTH 1u
8894 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPOR_SHIFT))&RCM_SSRS_SPOR_MASK)
8895 #define RCM_SSRS_SJTAG_MASK 0x100u
8896 #define RCM_SSRS_SJTAG_SHIFT 8u
8897 #define RCM_SSRS_SJTAG_WIDTH 1u
8898 #define RCM_SSRS_SJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SJTAG_SHIFT))&RCM_SSRS_SJTAG_MASK)
8899 #define RCM_SSRS_SLOCKUP_MASK 0x200u
8900 #define RCM_SSRS_SLOCKUP_SHIFT 9u
8901 #define RCM_SSRS_SLOCKUP_WIDTH 1u
8902 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOCKUP_SHIFT))&RCM_SSRS_SLOCKUP_MASK)
8903 #define RCM_SSRS_SSW_MASK 0x400u
8904 #define RCM_SSRS_SSW_SHIFT 10u
8905 #define RCM_SSRS_SSW_WIDTH 1u
8906 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSW_SHIFT))&RCM_SSRS_SSW_MASK)
8907 #define RCM_SSRS_SMDM_AP_MASK 0x800u
8908 #define RCM_SSRS_SMDM_AP_SHIFT 11u
8909 #define RCM_SSRS_SMDM_AP_WIDTH 1u
8910 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SMDM_AP_SHIFT))&RCM_SSRS_SMDM_AP_MASK)
8911 #define RCM_SSRS_SSACKERR_MASK 0x2000u
8912 #define RCM_SSRS_SSACKERR_SHIFT 13u
8913 #define RCM_SSRS_SSACKERR_WIDTH 1u
8914 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSACKERR_SHIFT))&RCM_SSRS_SSACKERR_MASK)
8915 /* SRIE Bit Fields */
8916 #define RCM_SRIE_DELAY_MASK 0x3u
8917 #define RCM_SRIE_DELAY_SHIFT 0u
8918 #define RCM_SRIE_DELAY_WIDTH 2u
8919 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_DELAY_SHIFT))&RCM_SRIE_DELAY_MASK)
8920 #define RCM_SRIE_LOC_MASK 0x4u
8921 #define RCM_SRIE_LOC_SHIFT 2u
8922 #define RCM_SRIE_LOC_WIDTH 1u
8923 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOC_SHIFT))&RCM_SRIE_LOC_MASK)
8924 #define RCM_SRIE_LOL_MASK 0x8u
8925 #define RCM_SRIE_LOL_SHIFT 3u
8926 #define RCM_SRIE_LOL_WIDTH 1u
8927 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOL_SHIFT))&RCM_SRIE_LOL_MASK)
8928 #define RCM_SRIE_WDOG_MASK 0x20u
8929 #define RCM_SRIE_WDOG_SHIFT 5u
8930 #define RCM_SRIE_WDOG_WIDTH 1u
8931 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_WDOG_SHIFT))&RCM_SRIE_WDOG_MASK)
8932 #define RCM_SRIE_PIN_MASK 0x40u
8933 #define RCM_SRIE_PIN_SHIFT 6u
8934 #define RCM_SRIE_PIN_WIDTH 1u
8935 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_PIN_SHIFT))&RCM_SRIE_PIN_MASK)
8936 #define RCM_SRIE_GIE_MASK 0x80u
8937 #define RCM_SRIE_GIE_SHIFT 7u
8938 #define RCM_SRIE_GIE_WIDTH 1u
8939 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_GIE_SHIFT))&RCM_SRIE_GIE_MASK)
8940 #define RCM_SRIE_JTAG_MASK 0x100u
8941 #define RCM_SRIE_JTAG_SHIFT 8u
8942 #define RCM_SRIE_JTAG_WIDTH 1u
8943 #define RCM_SRIE_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_JTAG_SHIFT))&RCM_SRIE_JTAG_MASK)
8944 #define RCM_SRIE_LOCKUP_MASK 0x200u
8945 #define RCM_SRIE_LOCKUP_SHIFT 9u
8946 #define RCM_SRIE_LOCKUP_WIDTH 1u
8947 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOCKUP_SHIFT))&RCM_SRIE_LOCKUP_MASK)
8948 #define RCM_SRIE_SW_MASK 0x400u
8949 #define RCM_SRIE_SW_SHIFT 10u
8950 #define RCM_SRIE_SW_WIDTH 1u
8951 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SW_SHIFT))&RCM_SRIE_SW_MASK)
8952 #define RCM_SRIE_MDM_AP_MASK 0x800u
8953 #define RCM_SRIE_MDM_AP_SHIFT 11u
8954 #define RCM_SRIE_MDM_AP_WIDTH 1u
8955 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_MDM_AP_SHIFT))&RCM_SRIE_MDM_AP_MASK)
8956 #define RCM_SRIE_SACKERR_MASK 0x2000u
8957 #define RCM_SRIE_SACKERR_SHIFT 13u
8958 #define RCM_SRIE_SACKERR_WIDTH 1u
8959 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SACKERR_SHIFT))&RCM_SRIE_SACKERR_MASK)
8960  /* end of group RCM_Register_Masks */
8964 
8965  /* end of group RCM_Peripheral_Access_Layer */
8969 
8970 
8971 /* ----------------------------------------------------------------------------
8972  -- RTC Peripheral Access Layer
8973  ---------------------------------------------------------------------------- */
8974 
8984 typedef struct {
8985  __IO uint32_t TSR;
8986  __IO uint32_t TPR;
8987  __IO uint32_t TAR;
8988  __IO uint32_t TCR;
8989  __IO uint32_t CR;
8990  __IO uint32_t SR;
8991  __IO uint32_t LR;
8992  __IO uint32_t IER;
8994 
8996 #define RTC_INSTANCE_COUNT (1u)
8997 
8998 
8999 /* RTC - Peripheral instance base addresses */
9001 #define RTC_BASE (0x4003D000u)
9002 
9003 #define RTC ((RTC_Type *)RTC_BASE)
9004 
9005 #define RTC_BASE_ADDRS { RTC_BASE }
9006 
9007 #define RTC_BASE_PTRS { RTC }
9008 
9009 #define RTC_IRQS_ARR_COUNT (2u)
9010 
9011 #define RTC_IRQS_CH_COUNT (1u)
9012 
9013 #define RTC_SECONDS_IRQS_CH_COUNT (1u)
9014 
9015 #define RTC_IRQS { RTC_IRQn }
9016 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
9017 
9018 /* ----------------------------------------------------------------------------
9019  -- RTC Register Masks
9020  ---------------------------------------------------------------------------- */
9021 
9027 /* TSR Bit Fields */
9028 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
9029 #define RTC_TSR_TSR_SHIFT 0u
9030 #define RTC_TSR_TSR_WIDTH 32u
9031 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
9032 /* TPR Bit Fields */
9033 #define RTC_TPR_TPR_MASK 0xFFFFu
9034 #define RTC_TPR_TPR_SHIFT 0u
9035 #define RTC_TPR_TPR_WIDTH 16u
9036 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
9037 /* TAR Bit Fields */
9038 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
9039 #define RTC_TAR_TAR_SHIFT 0u
9040 #define RTC_TAR_TAR_WIDTH 32u
9041 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
9042 /* TCR Bit Fields */
9043 #define RTC_TCR_TCR_MASK 0xFFu
9044 #define RTC_TCR_TCR_SHIFT 0u
9045 #define RTC_TCR_TCR_WIDTH 8u
9046 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
9047 #define RTC_TCR_CIR_MASK 0xFF00u
9048 #define RTC_TCR_CIR_SHIFT 8u
9049 #define RTC_TCR_CIR_WIDTH 8u
9050 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
9051 #define RTC_TCR_TCV_MASK 0xFF0000u
9052 #define RTC_TCR_TCV_SHIFT 16u
9053 #define RTC_TCR_TCV_WIDTH 8u
9054 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
9055 #define RTC_TCR_CIC_MASK 0xFF000000u
9056 #define RTC_TCR_CIC_SHIFT 24u
9057 #define RTC_TCR_CIC_WIDTH 8u
9058 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
9059 /* CR Bit Fields */
9060 #define RTC_CR_SWR_MASK 0x1u
9061 #define RTC_CR_SWR_SHIFT 0u
9062 #define RTC_CR_SWR_WIDTH 1u
9063 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
9064 #define RTC_CR_SUP_MASK 0x4u
9065 #define RTC_CR_SUP_SHIFT 2u
9066 #define RTC_CR_SUP_WIDTH 1u
9067 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
9068 #define RTC_CR_UM_MASK 0x8u
9069 #define RTC_CR_UM_SHIFT 3u
9070 #define RTC_CR_UM_WIDTH 1u
9071 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
9072 #define RTC_CR_CPS_MASK 0x20u
9073 #define RTC_CR_CPS_SHIFT 5u
9074 #define RTC_CR_CPS_WIDTH 1u
9075 #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPS_SHIFT))&RTC_CR_CPS_MASK)
9076 #define RTC_CR_LPOS_MASK 0x80u
9077 #define RTC_CR_LPOS_SHIFT 7u
9078 #define RTC_CR_LPOS_WIDTH 1u
9079 #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_LPOS_SHIFT))&RTC_CR_LPOS_MASK)
9080 #define RTC_CR_CPE_MASK 0x1000000u
9081 #define RTC_CR_CPE_SHIFT 24u
9082 #define RTC_CR_CPE_WIDTH 1u
9083 #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPE_SHIFT))&RTC_CR_CPE_MASK)
9084 /* SR Bit Fields */
9085 #define RTC_SR_TIF_MASK 0x1u
9086 #define RTC_SR_TIF_SHIFT 0u
9087 #define RTC_SR_TIF_WIDTH 1u
9088 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
9089 #define RTC_SR_TOF_MASK 0x2u
9090 #define RTC_SR_TOF_SHIFT 1u
9091 #define RTC_SR_TOF_WIDTH 1u
9092 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
9093 #define RTC_SR_TAF_MASK 0x4u
9094 #define RTC_SR_TAF_SHIFT 2u
9095 #define RTC_SR_TAF_WIDTH 1u
9096 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
9097 #define RTC_SR_TCE_MASK 0x10u
9098 #define RTC_SR_TCE_SHIFT 4u
9099 #define RTC_SR_TCE_WIDTH 1u
9100 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
9101 /* LR Bit Fields */
9102 #define RTC_LR_TCL_MASK 0x8u
9103 #define RTC_LR_TCL_SHIFT 3u
9104 #define RTC_LR_TCL_WIDTH 1u
9105 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
9106 #define RTC_LR_CRL_MASK 0x10u
9107 #define RTC_LR_CRL_SHIFT 4u
9108 #define RTC_LR_CRL_WIDTH 1u
9109 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
9110 #define RTC_LR_SRL_MASK 0x20u
9111 #define RTC_LR_SRL_SHIFT 5u
9112 #define RTC_LR_SRL_WIDTH 1u
9113 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
9114 #define RTC_LR_LRL_MASK 0x40u
9115 #define RTC_LR_LRL_SHIFT 6u
9116 #define RTC_LR_LRL_WIDTH 1u
9117 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
9118 /* IER Bit Fields */
9119 #define RTC_IER_TIIE_MASK 0x1u
9120 #define RTC_IER_TIIE_SHIFT 0u
9121 #define RTC_IER_TIIE_WIDTH 1u
9122 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
9123 #define RTC_IER_TOIE_MASK 0x2u
9124 #define RTC_IER_TOIE_SHIFT 1u
9125 #define RTC_IER_TOIE_WIDTH 1u
9126 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
9127 #define RTC_IER_TAIE_MASK 0x4u
9128 #define RTC_IER_TAIE_SHIFT 2u
9129 #define RTC_IER_TAIE_WIDTH 1u
9130 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
9131 #define RTC_IER_TSIE_MASK 0x10u
9132 #define RTC_IER_TSIE_SHIFT 4u
9133 #define RTC_IER_TSIE_WIDTH 1u
9134 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
9135 #define RTC_IER_TSIC_MASK 0x70000u
9136 #define RTC_IER_TSIC_SHIFT 16u
9137 #define RTC_IER_TSIC_WIDTH 3u
9138 #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
9139  /* end of group RTC_Register_Masks */
9143 
9144  /* end of group RTC_Peripheral_Access_Layer */
9148 
9149 
9150 /* ----------------------------------------------------------------------------
9151  -- S32_NVIC Peripheral Access Layer
9152  ---------------------------------------------------------------------------- */
9153 
9161 #define S32_NVIC_ISER_COUNT 4u
9162 #define S32_NVIC_ICER_COUNT 4u
9163 #define S32_NVIC_ISPR_COUNT 4u
9164 #define S32_NVIC_ICPR_COUNT 4u
9165 #define S32_NVIC_IABR_COUNT 4u
9166 #define S32_NVIC_IP_COUNT 123u
9167 
9169 typedef struct {
9170  __IO uint32_t ISER[S32_NVIC_ISER_COUNT];
9171  uint8_t RESERVED_0[112];
9172  __IO uint32_t ICER[S32_NVIC_ICER_COUNT];
9173  uint8_t RESERVED_1[112];
9174  __IO uint32_t ISPR[S32_NVIC_ISPR_COUNT];
9175  uint8_t RESERVED_2[112];
9176  __IO uint32_t ICPR[S32_NVIC_ICPR_COUNT];
9177  uint8_t RESERVED_3[112];
9178  __IO uint32_t IABR[S32_NVIC_IABR_COUNT];
9179  uint8_t RESERVED_4[240];
9180  __IO uint8_t IP[S32_NVIC_IP_COUNT];
9181  uint8_t RESERVED_5[2693];
9182  __O uint32_t STIR;
9184 
9186 #define S32_NVIC_INSTANCE_COUNT (1u)
9187 
9188 
9189 /* S32_NVIC - Peripheral instance base addresses */
9191 #define S32_NVIC_BASE (0xE000E100u)
9192 
9193 #define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE)
9194 
9195 #define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE }
9196 
9197 #define S32_NVIC_BASE_PTRS { S32_NVIC }
9198 
9199 #define S32_NVIC_IRQS_ARR_COUNT (1u)
9200 
9201 #define S32_NVIC_IRQS_CH_COUNT (1u)
9202 
9203 #define S32_NVIC_IRQS { SWI_IRQn }
9204 
9205 /* ----------------------------------------------------------------------------
9206  -- S32_NVIC Register Masks
9207  ---------------------------------------------------------------------------- */
9208 
9214 /* ISER Bit Fields */
9215 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
9216 #define S32_NVIC_ISER_SETENA_SHIFT 0u
9217 #define S32_NVIC_ISER_SETENA_WIDTH 32u
9218 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK)
9219 /* ICER Bit Fields */
9220 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu
9221 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
9222 #define S32_NVIC_ICER_CLRENA_WIDTH 32u
9223 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK)
9224 /* ISPR Bit Fields */
9225 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu
9226 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
9227 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u
9228 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK)
9229 /* ICPR Bit Fields */
9230 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu
9231 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
9232 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u
9233 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK)
9234 /* IABR Bit Fields */
9235 #define S32_NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu
9236 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
9237 #define S32_NVIC_IABR_ACTIVE_WIDTH 32u
9238 #define S32_NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IABR_ACTIVE_SHIFT))&S32_NVIC_IABR_ACTIVE_MASK)
9239 /* IP Bit Fields */
9240 #define S32_NVIC_IP_PRI0_MASK 0xFFu
9241 #define S32_NVIC_IP_PRI0_SHIFT 0u
9242 #define S32_NVIC_IP_PRI0_WIDTH 8u
9243 #define S32_NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI0_SHIFT))&S32_NVIC_IP_PRI0_MASK)
9244 #define S32_NVIC_IP_PRI1_MASK 0xFFu
9245 #define S32_NVIC_IP_PRI1_SHIFT 0u
9246 #define S32_NVIC_IP_PRI1_WIDTH 8u
9247 #define S32_NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI1_SHIFT))&S32_NVIC_IP_PRI1_MASK)
9248 #define S32_NVIC_IP_PRI2_MASK 0xFFu
9249 #define S32_NVIC_IP_PRI2_SHIFT 0u
9250 #define S32_NVIC_IP_PRI2_WIDTH 8u
9251 #define S32_NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI2_SHIFT))&S32_NVIC_IP_PRI2_MASK)
9252 #define S32_NVIC_IP_PRI3_MASK 0xFFu
9253 #define S32_NVIC_IP_PRI3_SHIFT 0u
9254 #define S32_NVIC_IP_PRI3_WIDTH 8u
9255 #define S32_NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI3_SHIFT))&S32_NVIC_IP_PRI3_MASK)
9256 #define S32_NVIC_IP_PRI4_MASK 0xFFu
9257 #define S32_NVIC_IP_PRI4_SHIFT 0u
9258 #define S32_NVIC_IP_PRI4_WIDTH 8u
9259 #define S32_NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI4_SHIFT))&S32_NVIC_IP_PRI4_MASK)
9260 #define S32_NVIC_IP_PRI5_MASK 0xFFu
9261 #define S32_NVIC_IP_PRI5_SHIFT 0u
9262 #define S32_NVIC_IP_PRI5_WIDTH 8u
9263 #define S32_NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI5_SHIFT))&S32_NVIC_IP_PRI5_MASK)
9264 #define S32_NVIC_IP_PRI6_MASK 0xFFu
9265 #define S32_NVIC_IP_PRI6_SHIFT 0u
9266 #define S32_NVIC_IP_PRI6_WIDTH 8u
9267 #define S32_NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI6_SHIFT))&S32_NVIC_IP_PRI6_MASK)
9268 #define S32_NVIC_IP_PRI7_MASK 0xFFu
9269 #define S32_NVIC_IP_PRI7_SHIFT 0u
9270 #define S32_NVIC_IP_PRI7_WIDTH 8u
9271 #define S32_NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI7_SHIFT))&S32_NVIC_IP_PRI7_MASK)
9272 #define S32_NVIC_IP_PRI8_MASK 0xFFu
9273 #define S32_NVIC_IP_PRI8_SHIFT 0u
9274 #define S32_NVIC_IP_PRI8_WIDTH 8u
9275 #define S32_NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI8_SHIFT))&S32_NVIC_IP_PRI8_MASK)
9276 #define S32_NVIC_IP_PRI9_MASK 0xFFu
9277 #define S32_NVIC_IP_PRI9_SHIFT 0u
9278 #define S32_NVIC_IP_PRI9_WIDTH 8u
9279 #define S32_NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI9_SHIFT))&S32_NVIC_IP_PRI9_MASK)
9280 #define S32_NVIC_IP_PRI10_MASK 0xFFu
9281 #define S32_NVIC_IP_PRI10_SHIFT 0u
9282 #define S32_NVIC_IP_PRI10_WIDTH 8u
9283 #define S32_NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI10_SHIFT))&S32_NVIC_IP_PRI10_MASK)
9284 #define S32_NVIC_IP_PRI11_MASK 0xFFu
9285 #define S32_NVIC_IP_PRI11_SHIFT 0u
9286 #define S32_NVIC_IP_PRI11_WIDTH 8u
9287 #define S32_NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI11_SHIFT))&S32_NVIC_IP_PRI11_MASK)
9288 #define S32_NVIC_IP_PRI12_MASK 0xFFu
9289 #define S32_NVIC_IP_PRI12_SHIFT 0u
9290 #define S32_NVIC_IP_PRI12_WIDTH 8u
9291 #define S32_NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI12_SHIFT))&S32_NVIC_IP_PRI12_MASK)
9292 #define S32_NVIC_IP_PRI13_MASK 0xFFu
9293 #define S32_NVIC_IP_PRI13_SHIFT 0u
9294 #define S32_NVIC_IP_PRI13_WIDTH 8u
9295 #define S32_NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI13_SHIFT))&S32_NVIC_IP_PRI13_MASK)
9296 #define S32_NVIC_IP_PRI14_MASK 0xFFu
9297 #define S32_NVIC_IP_PRI14_SHIFT 0u
9298 #define S32_NVIC_IP_PRI14_WIDTH 8u
9299 #define S32_NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI14_SHIFT))&S32_NVIC_IP_PRI14_MASK)
9300 #define S32_NVIC_IP_PRI15_MASK 0xFFu
9301 #define S32_NVIC_IP_PRI15_SHIFT 0u
9302 #define S32_NVIC_IP_PRI15_WIDTH 8u
9303 #define S32_NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI15_SHIFT))&S32_NVIC_IP_PRI15_MASK)
9304 #define S32_NVIC_IP_PRI16_MASK 0xFFu
9305 #define S32_NVIC_IP_PRI16_SHIFT 0u
9306 #define S32_NVIC_IP_PRI16_WIDTH 8u
9307 #define S32_NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI16_SHIFT))&S32_NVIC_IP_PRI16_MASK)
9308 #define S32_NVIC_IP_PRI17_MASK 0xFFu
9309 #define S32_NVIC_IP_PRI17_SHIFT 0u
9310 #define S32_NVIC_IP_PRI17_WIDTH 8u
9311 #define S32_NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI17_SHIFT))&S32_NVIC_IP_PRI17_MASK)
9312 #define S32_NVIC_IP_PRI18_MASK 0xFFu
9313 #define S32_NVIC_IP_PRI18_SHIFT 0u
9314 #define S32_NVIC_IP_PRI18_WIDTH 8u
9315 #define S32_NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI18_SHIFT))&S32_NVIC_IP_PRI18_MASK)
9316 #define S32_NVIC_IP_PRI19_MASK 0xFFu
9317 #define S32_NVIC_IP_PRI19_SHIFT 0u
9318 #define S32_NVIC_IP_PRI19_WIDTH 8u
9319 #define S32_NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI19_SHIFT))&S32_NVIC_IP_PRI19_MASK)
9320 #define S32_NVIC_IP_PRI20_MASK 0xFFu
9321 #define S32_NVIC_IP_PRI20_SHIFT 0u
9322 #define S32_NVIC_IP_PRI20_WIDTH 8u
9323 #define S32_NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI20_SHIFT))&S32_NVIC_IP_PRI20_MASK)
9324 #define S32_NVIC_IP_PRI21_MASK 0xFFu
9325 #define S32_NVIC_IP_PRI21_SHIFT 0u
9326 #define S32_NVIC_IP_PRI21_WIDTH 8u
9327 #define S32_NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI21_SHIFT))&S32_NVIC_IP_PRI21_MASK)
9328 #define S32_NVIC_IP_PRI22_MASK 0xFFu
9329 #define S32_NVIC_IP_PRI22_SHIFT 0u
9330 #define S32_NVIC_IP_PRI22_WIDTH 8u
9331 #define S32_NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI22_SHIFT))&S32_NVIC_IP_PRI22_MASK)
9332 #define S32_NVIC_IP_PRI23_MASK 0xFFu
9333 #define S32_NVIC_IP_PRI23_SHIFT 0u
9334 #define S32_NVIC_IP_PRI23_WIDTH 8u
9335 #define S32_NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI23_SHIFT))&S32_NVIC_IP_PRI23_MASK)
9336 #define S32_NVIC_IP_PRI24_MASK 0xFFu
9337 #define S32_NVIC_IP_PRI24_SHIFT 0u
9338 #define S32_NVIC_IP_PRI24_WIDTH 8u
9339 #define S32_NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI24_SHIFT))&S32_NVIC_IP_PRI24_MASK)
9340 #define S32_NVIC_IP_PRI25_MASK 0xFFu
9341 #define S32_NVIC_IP_PRI25_SHIFT 0u
9342 #define S32_NVIC_IP_PRI25_WIDTH 8u
9343 #define S32_NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI25_SHIFT))&S32_NVIC_IP_PRI25_MASK)
9344 #define S32_NVIC_IP_PRI26_MASK 0xFFu
9345 #define S32_NVIC_IP_PRI26_SHIFT 0u
9346 #define S32_NVIC_IP_PRI26_WIDTH 8u
9347 #define S32_NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI26_SHIFT))&S32_NVIC_IP_PRI26_MASK)
9348 #define S32_NVIC_IP_PRI27_MASK 0xFFu
9349 #define S32_NVIC_IP_PRI27_SHIFT 0u
9350 #define S32_NVIC_IP_PRI27_WIDTH 8u
9351 #define S32_NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI27_SHIFT))&S32_NVIC_IP_PRI27_MASK)
9352 #define S32_NVIC_IP_PRI28_MASK 0xFFu
9353 #define S32_NVIC_IP_PRI28_SHIFT 0u
9354 #define S32_NVIC_IP_PRI28_WIDTH 8u
9355 #define S32_NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI28_SHIFT))&S32_NVIC_IP_PRI28_MASK)
9356 #define S32_NVIC_IP_PRI29_MASK 0xFFu
9357 #define S32_NVIC_IP_PRI29_SHIFT 0u
9358 #define S32_NVIC_IP_PRI29_WIDTH 8u
9359 #define S32_NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI29_SHIFT))&S32_NVIC_IP_PRI29_MASK)
9360 #define S32_NVIC_IP_PRI30_MASK 0xFFu
9361 #define S32_NVIC_IP_PRI30_SHIFT 0u
9362 #define S32_NVIC_IP_PRI30_WIDTH 8u
9363 #define S32_NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI30_SHIFT))&S32_NVIC_IP_PRI30_MASK)
9364 #define S32_NVIC_IP_PRI31_MASK 0xFFu
9365 #define S32_NVIC_IP_PRI31_SHIFT 0u
9366 #define S32_NVIC_IP_PRI31_WIDTH 8u
9367 #define S32_NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI31_SHIFT))&S32_NVIC_IP_PRI31_MASK)
9368 #define S32_NVIC_IP_PRI32_MASK 0xFFu
9369 #define S32_NVIC_IP_PRI32_SHIFT 0u
9370 #define S32_NVIC_IP_PRI32_WIDTH 8u
9371 #define S32_NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI32_SHIFT))&S32_NVIC_IP_PRI32_MASK)
9372 #define S32_NVIC_IP_PRI33_MASK 0xFFu
9373 #define S32_NVIC_IP_PRI33_SHIFT 0u
9374 #define S32_NVIC_IP_PRI33_WIDTH 8u
9375 #define S32_NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI33_SHIFT))&S32_NVIC_IP_PRI33_MASK)
9376 #define S32_NVIC_IP_PRI34_MASK 0xFFu
9377 #define S32_NVIC_IP_PRI34_SHIFT 0u
9378 #define S32_NVIC_IP_PRI34_WIDTH 8u
9379 #define S32_NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI34_SHIFT))&S32_NVIC_IP_PRI34_MASK)
9380 #define S32_NVIC_IP_PRI35_MASK 0xFFu
9381 #define S32_NVIC_IP_PRI35_SHIFT 0u
9382 #define S32_NVIC_IP_PRI35_WIDTH 8u
9383 #define S32_NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI35_SHIFT))&S32_NVIC_IP_PRI35_MASK)
9384 #define S32_NVIC_IP_PRI36_MASK 0xFFu
9385 #define S32_NVIC_IP_PRI36_SHIFT 0u
9386 #define S32_NVIC_IP_PRI36_WIDTH 8u
9387 #define S32_NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI36_SHIFT))&S32_NVIC_IP_PRI36_MASK)
9388 #define S32_NVIC_IP_PRI37_MASK 0xFFu
9389 #define S32_NVIC_IP_PRI37_SHIFT 0u
9390 #define S32_NVIC_IP_PRI37_WIDTH 8u
9391 #define S32_NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI37_SHIFT))&S32_NVIC_IP_PRI37_MASK)
9392 #define S32_NVIC_IP_PRI38_MASK 0xFFu
9393 #define S32_NVIC_IP_PRI38_SHIFT 0u
9394 #define S32_NVIC_IP_PRI38_WIDTH 8u
9395 #define S32_NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI38_SHIFT))&S32_NVIC_IP_PRI38_MASK)
9396 #define S32_NVIC_IP_PRI39_MASK 0xFFu
9397 #define S32_NVIC_IP_PRI39_SHIFT 0u
9398 #define S32_NVIC_IP_PRI39_WIDTH 8u
9399 #define S32_NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI39_SHIFT))&S32_NVIC_IP_PRI39_MASK)
9400 #define S32_NVIC_IP_PRI40_MASK 0xFFu
9401 #define S32_NVIC_IP_PRI40_SHIFT 0u
9402 #define S32_NVIC_IP_PRI40_WIDTH 8u
9403 #define S32_NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI40_SHIFT))&S32_NVIC_IP_PRI40_MASK)
9404 #define S32_NVIC_IP_PRI41_MASK 0xFFu
9405 #define S32_NVIC_IP_PRI41_SHIFT 0u
9406 #define S32_NVIC_IP_PRI41_WIDTH 8u
9407 #define S32_NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI41_SHIFT))&S32_NVIC_IP_PRI41_MASK)
9408 #define S32_NVIC_IP_PRI42_MASK 0xFFu
9409 #define S32_NVIC_IP_PRI42_SHIFT 0u
9410 #define S32_NVIC_IP_PRI42_WIDTH 8u
9411 #define S32_NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI42_SHIFT))&S32_NVIC_IP_PRI42_MASK)
9412 #define S32_NVIC_IP_PRI43_MASK 0xFFu
9413 #define S32_NVIC_IP_PRI43_SHIFT 0u
9414 #define S32_NVIC_IP_PRI43_WIDTH 8u
9415 #define S32_NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI43_SHIFT))&S32_NVIC_IP_PRI43_MASK)
9416 #define S32_NVIC_IP_PRI44_MASK 0xFFu
9417 #define S32_NVIC_IP_PRI44_SHIFT 0u
9418 #define S32_NVIC_IP_PRI44_WIDTH 8u
9419 #define S32_NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI44_SHIFT))&S32_NVIC_IP_PRI44_MASK)
9420 #define S32_NVIC_IP_PRI45_MASK 0xFFu
9421 #define S32_NVIC_IP_PRI45_SHIFT 0u
9422 #define S32_NVIC_IP_PRI45_WIDTH 8u
9423 #define S32_NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI45_SHIFT))&S32_NVIC_IP_PRI45_MASK)
9424 #define S32_NVIC_IP_PRI46_MASK 0xFFu
9425 #define S32_NVIC_IP_PRI46_SHIFT 0u
9426 #define S32_NVIC_IP_PRI46_WIDTH 8u
9427 #define S32_NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI46_SHIFT))&S32_NVIC_IP_PRI46_MASK)
9428 #define S32_NVIC_IP_PRI47_MASK 0xFFu
9429 #define S32_NVIC_IP_PRI47_SHIFT 0u
9430 #define S32_NVIC_IP_PRI47_WIDTH 8u
9431 #define S32_NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI47_SHIFT))&S32_NVIC_IP_PRI47_MASK)
9432 #define S32_NVIC_IP_PRI48_MASK 0xFFu
9433 #define S32_NVIC_IP_PRI48_SHIFT 0u
9434 #define S32_NVIC_IP_PRI48_WIDTH 8u
9435 #define S32_NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI48_SHIFT))&S32_NVIC_IP_PRI48_MASK)
9436 #define S32_NVIC_IP_PRI49_MASK 0xFFu
9437 #define S32_NVIC_IP_PRI49_SHIFT 0u
9438 #define S32_NVIC_IP_PRI49_WIDTH 8u
9439 #define S32_NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI49_SHIFT))&S32_NVIC_IP_PRI49_MASK)
9440 #define S32_NVIC_IP_PRI50_MASK 0xFFu
9441 #define S32_NVIC_IP_PRI50_SHIFT 0u
9442 #define S32_NVIC_IP_PRI50_WIDTH 8u
9443 #define S32_NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI50_SHIFT))&S32_NVIC_IP_PRI50_MASK)
9444 #define S32_NVIC_IP_PRI51_MASK 0xFFu
9445 #define S32_NVIC_IP_PRI51_SHIFT 0u
9446 #define S32_NVIC_IP_PRI51_WIDTH 8u
9447 #define S32_NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI51_SHIFT))&S32_NVIC_IP_PRI51_MASK)
9448 #define S32_NVIC_IP_PRI52_MASK 0xFFu
9449 #define S32_NVIC_IP_PRI52_SHIFT 0u
9450 #define S32_NVIC_IP_PRI52_WIDTH 8u
9451 #define S32_NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI52_SHIFT))&S32_NVIC_IP_PRI52_MASK)
9452 #define S32_NVIC_IP_PRI53_MASK 0xFFu
9453 #define S32_NVIC_IP_PRI53_SHIFT 0u
9454 #define S32_NVIC_IP_PRI53_WIDTH 8u
9455 #define S32_NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI53_SHIFT))&S32_NVIC_IP_PRI53_MASK)
9456 #define S32_NVIC_IP_PRI54_MASK 0xFFu
9457 #define S32_NVIC_IP_PRI54_SHIFT 0u
9458 #define S32_NVIC_IP_PRI54_WIDTH 8u
9459 #define S32_NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI54_SHIFT))&S32_NVIC_IP_PRI54_MASK)
9460 #define S32_NVIC_IP_PRI55_MASK 0xFFu
9461 #define S32_NVIC_IP_PRI55_SHIFT 0u
9462 #define S32_NVIC_IP_PRI55_WIDTH 8u
9463 #define S32_NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI55_SHIFT))&S32_NVIC_IP_PRI55_MASK)
9464 #define S32_NVIC_IP_PRI56_MASK 0xFFu
9465 #define S32_NVIC_IP_PRI56_SHIFT 0u
9466 #define S32_NVIC_IP_PRI56_WIDTH 8u
9467 #define S32_NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI56_SHIFT))&S32_NVIC_IP_PRI56_MASK)
9468 #define S32_NVIC_IP_PRI57_MASK 0xFFu
9469 #define S32_NVIC_IP_PRI57_SHIFT 0u
9470 #define S32_NVIC_IP_PRI57_WIDTH 8u
9471 #define S32_NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI57_SHIFT))&S32_NVIC_IP_PRI57_MASK)
9472 #define S32_NVIC_IP_PRI58_MASK 0xFFu
9473 #define S32_NVIC_IP_PRI58_SHIFT 0u
9474 #define S32_NVIC_IP_PRI58_WIDTH 8u
9475 #define S32_NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI58_SHIFT))&S32_NVIC_IP_PRI58_MASK)
9476 #define S32_NVIC_IP_PRI59_MASK 0xFFu
9477 #define S32_NVIC_IP_PRI59_SHIFT 0u
9478 #define S32_NVIC_IP_PRI59_WIDTH 8u
9479 #define S32_NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI59_SHIFT))&S32_NVIC_IP_PRI59_MASK)
9480 #define S32_NVIC_IP_PRI60_MASK 0xFFu
9481 #define S32_NVIC_IP_PRI60_SHIFT 0u
9482 #define S32_NVIC_IP_PRI60_WIDTH 8u
9483 #define S32_NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI60_SHIFT))&S32_NVIC_IP_PRI60_MASK)
9484 #define S32_NVIC_IP_PRI61_MASK 0xFFu
9485 #define S32_NVIC_IP_PRI61_SHIFT 0u
9486 #define S32_NVIC_IP_PRI61_WIDTH 8u
9487 #define S32_NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI61_SHIFT))&S32_NVIC_IP_PRI61_MASK)
9488 #define S32_NVIC_IP_PRI62_MASK 0xFFu
9489 #define S32_NVIC_IP_PRI62_SHIFT 0u
9490 #define S32_NVIC_IP_PRI62_WIDTH 8u
9491 #define S32_NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI62_SHIFT))&S32_NVIC_IP_PRI62_MASK)
9492 #define S32_NVIC_IP_PRI63_MASK 0xFFu
9493 #define S32_NVIC_IP_PRI63_SHIFT 0u
9494 #define S32_NVIC_IP_PRI63_WIDTH 8u
9495 #define S32_NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI63_SHIFT))&S32_NVIC_IP_PRI63_MASK)
9496 #define S32_NVIC_IP_PRI64_MASK 0xFFu
9497 #define S32_NVIC_IP_PRI64_SHIFT 0u
9498 #define S32_NVIC_IP_PRI64_WIDTH 8u
9499 #define S32_NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI64_SHIFT))&S32_NVIC_IP_PRI64_MASK)
9500 #define S32_NVIC_IP_PRI65_MASK 0xFFu
9501 #define S32_NVIC_IP_PRI65_SHIFT 0u
9502 #define S32_NVIC_IP_PRI65_WIDTH 8u
9503 #define S32_NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI65_SHIFT))&S32_NVIC_IP_PRI65_MASK)
9504 #define S32_NVIC_IP_PRI66_MASK 0xFFu
9505 #define S32_NVIC_IP_PRI66_SHIFT 0u
9506 #define S32_NVIC_IP_PRI66_WIDTH 8u
9507 #define S32_NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI66_SHIFT))&S32_NVIC_IP_PRI66_MASK)
9508 #define S32_NVIC_IP_PRI67_MASK 0xFFu
9509 #define S32_NVIC_IP_PRI67_SHIFT 0u
9510 #define S32_NVIC_IP_PRI67_WIDTH 8u
9511 #define S32_NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI67_SHIFT))&S32_NVIC_IP_PRI67_MASK)
9512 #define S32_NVIC_IP_PRI68_MASK 0xFFu
9513 #define S32_NVIC_IP_PRI68_SHIFT 0u
9514 #define S32_NVIC_IP_PRI68_WIDTH 8u
9515 #define S32_NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI68_SHIFT))&S32_NVIC_IP_PRI68_MASK)
9516 #define S32_NVIC_IP_PRI69_MASK 0xFFu
9517 #define S32_NVIC_IP_PRI69_SHIFT 0u
9518 #define S32_NVIC_IP_PRI69_WIDTH 8u
9519 #define S32_NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI69_SHIFT))&S32_NVIC_IP_PRI69_MASK)
9520 #define S32_NVIC_IP_PRI70_MASK 0xFFu
9521 #define S32_NVIC_IP_PRI70_SHIFT 0u
9522 #define S32_NVIC_IP_PRI70_WIDTH 8u
9523 #define S32_NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI70_SHIFT))&S32_NVIC_IP_PRI70_MASK)
9524 #define S32_NVIC_IP_PRI71_MASK 0xFFu
9525 #define S32_NVIC_IP_PRI71_SHIFT 0u
9526 #define S32_NVIC_IP_PRI71_WIDTH 8u
9527 #define S32_NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI71_SHIFT))&S32_NVIC_IP_PRI71_MASK)
9528 #define S32_NVIC_IP_PRI72_MASK 0xFFu
9529 #define S32_NVIC_IP_PRI72_SHIFT 0u
9530 #define S32_NVIC_IP_PRI72_WIDTH 8u
9531 #define S32_NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI72_SHIFT))&S32_NVIC_IP_PRI72_MASK)
9532 #define S32_NVIC_IP_PRI73_MASK 0xFFu
9533 #define S32_NVIC_IP_PRI73_SHIFT 0u
9534 #define S32_NVIC_IP_PRI73_WIDTH 8u
9535 #define S32_NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI73_SHIFT))&S32_NVIC_IP_PRI73_MASK)
9536 #define S32_NVIC_IP_PRI74_MASK 0xFFu
9537 #define S32_NVIC_IP_PRI74_SHIFT 0u
9538 #define S32_NVIC_IP_PRI74_WIDTH 8u
9539 #define S32_NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI74_SHIFT))&S32_NVIC_IP_PRI74_MASK)
9540 #define S32_NVIC_IP_PRI75_MASK 0xFFu
9541 #define S32_NVIC_IP_PRI75_SHIFT 0u
9542 #define S32_NVIC_IP_PRI75_WIDTH 8u
9543 #define S32_NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI75_SHIFT))&S32_NVIC_IP_PRI75_MASK)
9544 #define S32_NVIC_IP_PRI76_MASK 0xFFu
9545 #define S32_NVIC_IP_PRI76_SHIFT 0u
9546 #define S32_NVIC_IP_PRI76_WIDTH 8u
9547 #define S32_NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI76_SHIFT))&S32_NVIC_IP_PRI76_MASK)
9548 #define S32_NVIC_IP_PRI77_MASK 0xFFu
9549 #define S32_NVIC_IP_PRI77_SHIFT 0u
9550 #define S32_NVIC_IP_PRI77_WIDTH 8u
9551 #define S32_NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI77_SHIFT))&S32_NVIC_IP_PRI77_MASK)
9552 #define S32_NVIC_IP_PRI78_MASK 0xFFu
9553 #define S32_NVIC_IP_PRI78_SHIFT 0u
9554 #define S32_NVIC_IP_PRI78_WIDTH 8u
9555 #define S32_NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI78_SHIFT))&S32_NVIC_IP_PRI78_MASK)
9556 #define S32_NVIC_IP_PRI79_MASK 0xFFu
9557 #define S32_NVIC_IP_PRI79_SHIFT 0u
9558 #define S32_NVIC_IP_PRI79_WIDTH 8u
9559 #define S32_NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI79_SHIFT))&S32_NVIC_IP_PRI79_MASK)
9560 #define S32_NVIC_IP_PRI80_MASK 0xFFu
9561 #define S32_NVIC_IP_PRI80_SHIFT 0u
9562 #define S32_NVIC_IP_PRI80_WIDTH 8u
9563 #define S32_NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI80_SHIFT))&S32_NVIC_IP_PRI80_MASK)
9564 #define S32_NVIC_IP_PRI81_MASK 0xFFu
9565 #define S32_NVIC_IP_PRI81_SHIFT 0u
9566 #define S32_NVIC_IP_PRI81_WIDTH 8u
9567 #define S32_NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI81_SHIFT))&S32_NVIC_IP_PRI81_MASK)
9568 #define S32_NVIC_IP_PRI82_MASK 0xFFu
9569 #define S32_NVIC_IP_PRI82_SHIFT 0u
9570 #define S32_NVIC_IP_PRI82_WIDTH 8u
9571 #define S32_NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI82_SHIFT))&S32_NVIC_IP_PRI82_MASK)
9572 #define S32_NVIC_IP_PRI83_MASK 0xFFu
9573 #define S32_NVIC_IP_PRI83_SHIFT 0u
9574 #define S32_NVIC_IP_PRI83_WIDTH 8u
9575 #define S32_NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI83_SHIFT))&S32_NVIC_IP_PRI83_MASK)
9576 #define S32_NVIC_IP_PRI84_MASK 0xFFu
9577 #define S32_NVIC_IP_PRI84_SHIFT 0u
9578 #define S32_NVIC_IP_PRI84_WIDTH 8u
9579 #define S32_NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI84_SHIFT))&S32_NVIC_IP_PRI84_MASK)
9580 #define S32_NVIC_IP_PRI85_MASK 0xFFu
9581 #define S32_NVIC_IP_PRI85_SHIFT 0u
9582 #define S32_NVIC_IP_PRI85_WIDTH 8u
9583 #define S32_NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI85_SHIFT))&S32_NVIC_IP_PRI85_MASK)
9584 #define S32_NVIC_IP_PRI86_MASK 0xFFu
9585 #define S32_NVIC_IP_PRI86_SHIFT 0u
9586 #define S32_NVIC_IP_PRI86_WIDTH 8u
9587 #define S32_NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI86_SHIFT))&S32_NVIC_IP_PRI86_MASK)
9588 #define S32_NVIC_IP_PRI87_MASK 0xFFu
9589 #define S32_NVIC_IP_PRI87_SHIFT 0u
9590 #define S32_NVIC_IP_PRI87_WIDTH 8u
9591 #define S32_NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI87_SHIFT))&S32_NVIC_IP_PRI87_MASK)
9592 #define S32_NVIC_IP_PRI88_MASK 0xFFu
9593 #define S32_NVIC_IP_PRI88_SHIFT 0u
9594 #define S32_NVIC_IP_PRI88_WIDTH 8u
9595 #define S32_NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI88_SHIFT))&S32_NVIC_IP_PRI88_MASK)
9596 #define S32_NVIC_IP_PRI89_MASK 0xFFu
9597 #define S32_NVIC_IP_PRI89_SHIFT 0u
9598 #define S32_NVIC_IP_PRI89_WIDTH 8u
9599 #define S32_NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI89_SHIFT))&S32_NVIC_IP_PRI89_MASK)
9600 #define S32_NVIC_IP_PRI90_MASK 0xFFu
9601 #define S32_NVIC_IP_PRI90_SHIFT 0u
9602 #define S32_NVIC_IP_PRI90_WIDTH 8u
9603 #define S32_NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI90_SHIFT))&S32_NVIC_IP_PRI90_MASK)
9604 #define S32_NVIC_IP_PRI91_MASK 0xFFu
9605 #define S32_NVIC_IP_PRI91_SHIFT 0u
9606 #define S32_NVIC_IP_PRI91_WIDTH 8u
9607 #define S32_NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI91_SHIFT))&S32_NVIC_IP_PRI91_MASK)
9608 #define S32_NVIC_IP_PRI92_MASK 0xFFu
9609 #define S32_NVIC_IP_PRI92_SHIFT 0u
9610 #define S32_NVIC_IP_PRI92_WIDTH 8u
9611 #define S32_NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI92_SHIFT))&S32_NVIC_IP_PRI92_MASK)
9612 #define S32_NVIC_IP_PRI93_MASK 0xFFu
9613 #define S32_NVIC_IP_PRI93_SHIFT 0u
9614 #define S32_NVIC_IP_PRI93_WIDTH 8u
9615 #define S32_NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI93_SHIFT))&S32_NVIC_IP_PRI93_MASK)
9616 #define S32_NVIC_IP_PRI94_MASK 0xFFu
9617 #define S32_NVIC_IP_PRI94_SHIFT 0u
9618 #define S32_NVIC_IP_PRI94_WIDTH 8u
9619 #define S32_NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI94_SHIFT))&S32_NVIC_IP_PRI94_MASK)
9620 #define S32_NVIC_IP_PRI95_MASK 0xFFu
9621 #define S32_NVIC_IP_PRI95_SHIFT 0u
9622 #define S32_NVIC_IP_PRI95_WIDTH 8u
9623 #define S32_NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI95_SHIFT))&S32_NVIC_IP_PRI95_MASK)
9624 #define S32_NVIC_IP_PRI96_MASK 0xFFu
9625 #define S32_NVIC_IP_PRI96_SHIFT 0u
9626 #define S32_NVIC_IP_PRI96_WIDTH 8u
9627 #define S32_NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI96_SHIFT))&S32_NVIC_IP_PRI96_MASK)
9628 #define S32_NVIC_IP_PRI97_MASK 0xFFu
9629 #define S32_NVIC_IP_PRI97_SHIFT 0u
9630 #define S32_NVIC_IP_PRI97_WIDTH 8u
9631 #define S32_NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI97_SHIFT))&S32_NVIC_IP_PRI97_MASK)
9632 #define S32_NVIC_IP_PRI98_MASK 0xFFu
9633 #define S32_NVIC_IP_PRI98_SHIFT 0u
9634 #define S32_NVIC_IP_PRI98_WIDTH 8u
9635 #define S32_NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI98_SHIFT))&S32_NVIC_IP_PRI98_MASK)
9636 #define S32_NVIC_IP_PRI99_MASK 0xFFu
9637 #define S32_NVIC_IP_PRI99_SHIFT 0u
9638 #define S32_NVIC_IP_PRI99_WIDTH 8u
9639 #define S32_NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI99_SHIFT))&S32_NVIC_IP_PRI99_MASK)
9640 #define S32_NVIC_IP_PRI100_MASK 0xFFu
9641 #define S32_NVIC_IP_PRI100_SHIFT 0u
9642 #define S32_NVIC_IP_PRI100_WIDTH 8u
9643 #define S32_NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI100_SHIFT))&S32_NVIC_IP_PRI100_MASK)
9644 #define S32_NVIC_IP_PRI101_MASK 0xFFu
9645 #define S32_NVIC_IP_PRI101_SHIFT 0u
9646 #define S32_NVIC_IP_PRI101_WIDTH 8u
9647 #define S32_NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI101_SHIFT))&S32_NVIC_IP_PRI101_MASK)
9648 #define S32_NVIC_IP_PRI102_MASK 0xFFu
9649 #define S32_NVIC_IP_PRI102_SHIFT 0u
9650 #define S32_NVIC_IP_PRI102_WIDTH 8u
9651 #define S32_NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI102_SHIFT))&S32_NVIC_IP_PRI102_MASK)
9652 #define S32_NVIC_IP_PRI103_MASK 0xFFu
9653 #define S32_NVIC_IP_PRI103_SHIFT 0u
9654 #define S32_NVIC_IP_PRI103_WIDTH 8u
9655 #define S32_NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI103_SHIFT))&S32_NVIC_IP_PRI103_MASK)
9656 #define S32_NVIC_IP_PRI104_MASK 0xFFu
9657 #define S32_NVIC_IP_PRI104_SHIFT 0u
9658 #define S32_NVIC_IP_PRI104_WIDTH 8u
9659 #define S32_NVIC_IP_PRI104(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI104_SHIFT))&S32_NVIC_IP_PRI104_MASK)
9660 #define S32_NVIC_IP_PRI105_MASK 0xFFu
9661 #define S32_NVIC_IP_PRI105_SHIFT 0u
9662 #define S32_NVIC_IP_PRI105_WIDTH 8u
9663 #define S32_NVIC_IP_PRI105(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI105_SHIFT))&S32_NVIC_IP_PRI105_MASK)
9664 #define S32_NVIC_IP_PRI106_MASK 0xFFu
9665 #define S32_NVIC_IP_PRI106_SHIFT 0u
9666 #define S32_NVIC_IP_PRI106_WIDTH 8u
9667 #define S32_NVIC_IP_PRI106(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI106_SHIFT))&S32_NVIC_IP_PRI106_MASK)
9668 #define S32_NVIC_IP_PRI107_MASK 0xFFu
9669 #define S32_NVIC_IP_PRI107_SHIFT 0u
9670 #define S32_NVIC_IP_PRI107_WIDTH 8u
9671 #define S32_NVIC_IP_PRI107(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI107_SHIFT))&S32_NVIC_IP_PRI107_MASK)
9672 #define S32_NVIC_IP_PRI108_MASK 0xFFu
9673 #define S32_NVIC_IP_PRI108_SHIFT 0u
9674 #define S32_NVIC_IP_PRI108_WIDTH 8u
9675 #define S32_NVIC_IP_PRI108(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI108_SHIFT))&S32_NVIC_IP_PRI108_MASK)
9676 #define S32_NVIC_IP_PRI109_MASK 0xFFu
9677 #define S32_NVIC_IP_PRI109_SHIFT 0u
9678 #define S32_NVIC_IP_PRI109_WIDTH 8u
9679 #define S32_NVIC_IP_PRI109(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI109_SHIFT))&S32_NVIC_IP_PRI109_MASK)
9680 #define S32_NVIC_IP_PRI110_MASK 0xFFu
9681 #define S32_NVIC_IP_PRI110_SHIFT 0u
9682 #define S32_NVIC_IP_PRI110_WIDTH 8u
9683 #define S32_NVIC_IP_PRI110(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI110_SHIFT))&S32_NVIC_IP_PRI110_MASK)
9684 #define S32_NVIC_IP_PRI111_MASK 0xFFu
9685 #define S32_NVIC_IP_PRI111_SHIFT 0u
9686 #define S32_NVIC_IP_PRI111_WIDTH 8u
9687 #define S32_NVIC_IP_PRI111(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI111_SHIFT))&S32_NVIC_IP_PRI111_MASK)
9688 #define S32_NVIC_IP_PRI112_MASK 0xFFu
9689 #define S32_NVIC_IP_PRI112_SHIFT 0u
9690 #define S32_NVIC_IP_PRI112_WIDTH 8u
9691 #define S32_NVIC_IP_PRI112(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI112_SHIFT))&S32_NVIC_IP_PRI112_MASK)
9692 #define S32_NVIC_IP_PRI113_MASK 0xFFu
9693 #define S32_NVIC_IP_PRI113_SHIFT 0u
9694 #define S32_NVIC_IP_PRI113_WIDTH 8u
9695 #define S32_NVIC_IP_PRI113(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI113_SHIFT))&S32_NVIC_IP_PRI113_MASK)
9696 #define S32_NVIC_IP_PRI114_MASK 0xFFu
9697 #define S32_NVIC_IP_PRI114_SHIFT 0u
9698 #define S32_NVIC_IP_PRI114_WIDTH 8u
9699 #define S32_NVIC_IP_PRI114(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI114_SHIFT))&S32_NVIC_IP_PRI114_MASK)
9700 #define S32_NVIC_IP_PRI115_MASK 0xFFu
9701 #define S32_NVIC_IP_PRI115_SHIFT 0u
9702 #define S32_NVIC_IP_PRI115_WIDTH 8u
9703 #define S32_NVIC_IP_PRI115(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI115_SHIFT))&S32_NVIC_IP_PRI115_MASK)
9704 #define S32_NVIC_IP_PRI116_MASK 0xFFu
9705 #define S32_NVIC_IP_PRI116_SHIFT 0u
9706 #define S32_NVIC_IP_PRI116_WIDTH 8u
9707 #define S32_NVIC_IP_PRI116(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI116_SHIFT))&S32_NVIC_IP_PRI116_MASK)
9708 #define S32_NVIC_IP_PRI117_MASK 0xFFu
9709 #define S32_NVIC_IP_PRI117_SHIFT 0u
9710 #define S32_NVIC_IP_PRI117_WIDTH 8u
9711 #define S32_NVIC_IP_PRI117(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI117_SHIFT))&S32_NVIC_IP_PRI117_MASK)
9712 #define S32_NVIC_IP_PRI118_MASK 0xFFu
9713 #define S32_NVIC_IP_PRI118_SHIFT 0u
9714 #define S32_NVIC_IP_PRI118_WIDTH 8u
9715 #define S32_NVIC_IP_PRI118(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI118_SHIFT))&S32_NVIC_IP_PRI118_MASK)
9716 #define S32_NVIC_IP_PRI119_MASK 0xFFu
9717 #define S32_NVIC_IP_PRI119_SHIFT 0u
9718 #define S32_NVIC_IP_PRI119_WIDTH 8u
9719 #define S32_NVIC_IP_PRI119(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI119_SHIFT))&S32_NVIC_IP_PRI119_MASK)
9720 #define S32_NVIC_IP_PRI120_MASK 0xFFu
9721 #define S32_NVIC_IP_PRI120_SHIFT 0u
9722 #define S32_NVIC_IP_PRI120_WIDTH 8u
9723 #define S32_NVIC_IP_PRI120(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI120_SHIFT))&S32_NVIC_IP_PRI120_MASK)
9724 #define S32_NVIC_IP_PRI121_MASK 0xFFu
9725 #define S32_NVIC_IP_PRI121_SHIFT 0u
9726 #define S32_NVIC_IP_PRI121_WIDTH 8u
9727 #define S32_NVIC_IP_PRI121(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI121_SHIFT))&S32_NVIC_IP_PRI121_MASK)
9728 #define S32_NVIC_IP_PRI122_MASK 0xFFu
9729 #define S32_NVIC_IP_PRI122_SHIFT 0u
9730 #define S32_NVIC_IP_PRI122_WIDTH 8u
9731 #define S32_NVIC_IP_PRI122(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI122_SHIFT))&S32_NVIC_IP_PRI122_MASK)
9732 /* STIR Bit Fields */
9733 #define S32_NVIC_STIR_INTID_MASK 0x1FFu
9734 #define S32_NVIC_STIR_INTID_SHIFT 0u
9735 #define S32_NVIC_STIR_INTID_WIDTH 9u
9736 #define S32_NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_STIR_INTID_SHIFT))&S32_NVIC_STIR_INTID_MASK)
9737  /* end of group S32_NVIC_Register_Masks */
9741 
9742  /* end of group S32_NVIC_Peripheral_Access_Layer */
9746 
9747 
9748 /* ----------------------------------------------------------------------------
9749  -- S32_SCB Peripheral Access Layer
9750  ---------------------------------------------------------------------------- */
9751 
9761 typedef struct {
9762  uint8_t RESERVED_0[8];
9763  __IO uint32_t ACTLR;
9764  uint8_t RESERVED_1[3316];
9765  __I uint32_t CPUID;
9766  __IO uint32_t ICSR;
9767  __IO uint32_t VTOR;
9768  __IO uint32_t AIRCR;
9769  __IO uint32_t SCR;
9770  __IO uint32_t CCR;
9771  __IO uint32_t SHPR1;
9772  __IO uint32_t SHPR2;
9773  __IO uint32_t SHPR3;
9774  __IO uint32_t SHCSR;
9775  __IO uint32_t CFSR;
9776  __IO uint32_t HFSR;
9777  __IO uint32_t DFSR;
9778  __IO uint32_t MMFAR;
9779  __IO uint32_t BFAR;
9780  __IO uint32_t AFSR;
9781  uint8_t RESERVED_2[72];
9782  __IO uint32_t CPACR;
9783  uint8_t RESERVED_3[424];
9784  __IO uint32_t FPCCR;
9785  __IO uint32_t FPCAR;
9786  __IO uint32_t FPDSCR;
9788 
9790 #define S32_SCB_INSTANCE_COUNT (1u)
9791 
9792 
9793 /* S32_SCB - Peripheral instance base addresses */
9795 #define S32_SCB_BASE (0xE000E000u)
9796 
9797 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE)
9798 
9799 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE }
9800 
9801 #define S32_SCB_BASE_PTRS { S32_SCB }
9802 
9803 /* ----------------------------------------------------------------------------
9804  -- S32_SCB Register Masks
9805  ---------------------------------------------------------------------------- */
9806 
9812 /* ACTLR Bit Fields */
9813 #define S32_SCB_ACTLR_DISMCYCINT_MASK 0x1u
9814 #define S32_SCB_ACTLR_DISMCYCINT_SHIFT 0u
9815 #define S32_SCB_ACTLR_DISMCYCINT_WIDTH 1u
9816 #define S32_SCB_ACTLR_DISMCYCINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISMCYCINT_SHIFT))&S32_SCB_ACTLR_DISMCYCINT_MASK)
9817 #define S32_SCB_ACTLR_DISDEFWBUF_MASK 0x2u
9818 #define S32_SCB_ACTLR_DISDEFWBUF_SHIFT 1u
9819 #define S32_SCB_ACTLR_DISDEFWBUF_WIDTH 1u
9820 #define S32_SCB_ACTLR_DISDEFWBUF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISDEFWBUF_SHIFT))&S32_SCB_ACTLR_DISDEFWBUF_MASK)
9821 #define S32_SCB_ACTLR_DISFOLD_MASK 0x4u
9822 #define S32_SCB_ACTLR_DISFOLD_SHIFT 2u
9823 #define S32_SCB_ACTLR_DISFOLD_WIDTH 1u
9824 #define S32_SCB_ACTLR_DISFOLD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFOLD_SHIFT))&S32_SCB_ACTLR_DISFOLD_MASK)
9825 #define S32_SCB_ACTLR_DISFPCA_MASK 0x100u
9826 #define S32_SCB_ACTLR_DISFPCA_SHIFT 8u
9827 #define S32_SCB_ACTLR_DISFPCA_WIDTH 1u
9828 #define S32_SCB_ACTLR_DISFPCA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFPCA_SHIFT))&S32_SCB_ACTLR_DISFPCA_MASK)
9829 #define S32_SCB_ACTLR_DISOOFP_MASK 0x200u
9830 #define S32_SCB_ACTLR_DISOOFP_SHIFT 9u
9831 #define S32_SCB_ACTLR_DISOOFP_WIDTH 1u
9832 #define S32_SCB_ACTLR_DISOOFP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISOOFP_SHIFT))&S32_SCB_ACTLR_DISOOFP_MASK)
9833 /* CPUID Bit Fields */
9834 #define S32_SCB_CPUID_REVISION_MASK 0xFu
9835 #define S32_SCB_CPUID_REVISION_SHIFT 0u
9836 #define S32_SCB_CPUID_REVISION_WIDTH 4u
9837 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK)
9838 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u
9839 #define S32_SCB_CPUID_PARTNO_SHIFT 4u
9840 #define S32_SCB_CPUID_PARTNO_WIDTH 12u
9841 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK)
9842 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u
9843 #define S32_SCB_CPUID_VARIANT_SHIFT 20u
9844 #define S32_SCB_CPUID_VARIANT_WIDTH 4u
9845 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK)
9846 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u
9847 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u
9848 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u
9849 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK)
9850 /* ICSR Bit Fields */
9851 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x1FFu
9852 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
9853 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 9u
9854 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK)
9855 #define S32_SCB_ICSR_RETTOBASE_MASK 0x800u
9856 #define S32_SCB_ICSR_RETTOBASE_SHIFT 11u
9857 #define S32_SCB_ICSR_RETTOBASE_WIDTH 1u
9858 #define S32_SCB_ICSR_RETTOBASE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_RETTOBASE_SHIFT))&S32_SCB_ICSR_RETTOBASE_MASK)
9859 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u
9860 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u
9861 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u
9862 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK)
9863 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u
9864 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u
9865 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u
9866 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK)
9867 #define S32_SCB_ICSR_ISRPREEMPT_MASK 0x800000u
9868 #define S32_SCB_ICSR_ISRPREEMPT_SHIFT 23u
9869 #define S32_SCB_ICSR_ISRPREEMPT_WIDTH 1u
9870 #define S32_SCB_ICSR_ISRPREEMPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPREEMPT_SHIFT))&S32_SCB_ICSR_ISRPREEMPT_MASK)
9871 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u
9872 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u
9873 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u
9874 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK)
9875 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u
9876 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u
9877 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u
9878 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK)
9879 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u
9880 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u
9881 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u
9882 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK)
9883 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u
9884 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u
9885 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u
9886 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK)
9887 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u
9888 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u
9889 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u
9890 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK)
9891 /* VTOR Bit Fields */
9892 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u
9893 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u
9894 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u
9895 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK)
9896 /* AIRCR Bit Fields */
9897 #define S32_SCB_AIRCR_VECTRESET_MASK 0x1u
9898 #define S32_SCB_AIRCR_VECTRESET_SHIFT 0u
9899 #define S32_SCB_AIRCR_VECTRESET_WIDTH 1u
9900 #define S32_SCB_AIRCR_VECTRESET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTRESET_SHIFT))&S32_SCB_AIRCR_VECTRESET_MASK)
9901 #define S32_SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u
9902 #define S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT 1u
9903 #define S32_SCB_AIRCR_VECTCLRACTIVE_WIDTH 1u
9904 #define S32_SCB_AIRCR_VECTCLRACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK)
9905 #define S32_SCB_AIRCR_SYSRESETREQ_MASK 0x4u
9906 #define S32_SCB_AIRCR_SYSRESETREQ_SHIFT 2u
9907 #define S32_SCB_AIRCR_SYSRESETREQ_WIDTH 1u
9908 #define S32_SCB_AIRCR_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK)
9909 #define S32_SCB_AIRCR_PRIGROUP_MASK 0x700u
9910 #define S32_SCB_AIRCR_PRIGROUP_SHIFT 8u
9911 #define S32_SCB_AIRCR_PRIGROUP_WIDTH 3u
9912 #define S32_SCB_AIRCR_PRIGROUP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_PRIGROUP_SHIFT))&S32_SCB_AIRCR_PRIGROUP_MASK)
9913 #define S32_SCB_AIRCR_ENDIANNESS_MASK 0x8000u
9914 #define S32_SCB_AIRCR_ENDIANNESS_SHIFT 15u
9915 #define S32_SCB_AIRCR_ENDIANNESS_WIDTH 1u
9916 #define S32_SCB_AIRCR_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK)
9917 #define S32_SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u
9918 #define S32_SCB_AIRCR_VECTKEY_SHIFT 16u
9919 #define S32_SCB_AIRCR_VECTKEY_WIDTH 16u
9920 #define S32_SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK)
9921 /* SCR Bit Fields */
9922 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u
9923 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u
9924 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u
9925 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK)
9926 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u
9927 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u
9928 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u
9929 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK)
9930 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u
9931 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u
9932 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u
9933 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK)
9934 /* CCR Bit Fields */
9935 #define S32_SCB_CCR_NONBASETHRDENA_MASK 0x1u
9936 #define S32_SCB_CCR_NONBASETHRDENA_SHIFT 0u
9937 #define S32_SCB_CCR_NONBASETHRDENA_WIDTH 1u
9938 #define S32_SCB_CCR_NONBASETHRDENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_NONBASETHRDENA_SHIFT))&S32_SCB_CCR_NONBASETHRDENA_MASK)
9939 #define S32_SCB_CCR_USERSETMPEND_MASK 0x2u
9940 #define S32_SCB_CCR_USERSETMPEND_SHIFT 1u
9941 #define S32_SCB_CCR_USERSETMPEND_WIDTH 1u
9942 #define S32_SCB_CCR_USERSETMPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_USERSETMPEND_SHIFT))&S32_SCB_CCR_USERSETMPEND_MASK)
9943 #define S32_SCB_CCR_UNALIGN_TRP_MASK 0x8u
9944 #define S32_SCB_CCR_UNALIGN_TRP_SHIFT 3u
9945 #define S32_SCB_CCR_UNALIGN_TRP_WIDTH 1u
9946 #define S32_SCB_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK)
9947 #define S32_SCB_CCR_DIV_0_TRP_MASK 0x10u
9948 #define S32_SCB_CCR_DIV_0_TRP_SHIFT 4u
9949 #define S32_SCB_CCR_DIV_0_TRP_WIDTH 1u
9950 #define S32_SCB_CCR_DIV_0_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_DIV_0_TRP_SHIFT))&S32_SCB_CCR_DIV_0_TRP_MASK)
9951 #define S32_SCB_CCR_BFHFNMIGN_MASK 0x100u
9952 #define S32_SCB_CCR_BFHFNMIGN_SHIFT 8u
9953 #define S32_SCB_CCR_BFHFNMIGN_WIDTH 1u
9954 #define S32_SCB_CCR_BFHFNMIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_BFHFNMIGN_SHIFT))&S32_SCB_CCR_BFHFNMIGN_MASK)
9955 #define S32_SCB_CCR_STKALIGN_MASK 0x200u
9956 #define S32_SCB_CCR_STKALIGN_SHIFT 9u
9957 #define S32_SCB_CCR_STKALIGN_WIDTH 1u
9958 #define S32_SCB_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK)
9959 /* SHPR1 Bit Fields */
9960 #define S32_SCB_SHPR1_PRI_4_MASK 0xFFu
9961 #define S32_SCB_SHPR1_PRI_4_SHIFT 0u
9962 #define S32_SCB_SHPR1_PRI_4_WIDTH 8u
9963 #define S32_SCB_SHPR1_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_4_SHIFT))&S32_SCB_SHPR1_PRI_4_MASK)
9964 #define S32_SCB_SHPR1_PRI_5_MASK 0xFF00u
9965 #define S32_SCB_SHPR1_PRI_5_SHIFT 8u
9966 #define S32_SCB_SHPR1_PRI_5_WIDTH 8u
9967 #define S32_SCB_SHPR1_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_5_SHIFT))&S32_SCB_SHPR1_PRI_5_MASK)
9968 #define S32_SCB_SHPR1_PRI_6_MASK 0xFF0000u
9969 #define S32_SCB_SHPR1_PRI_6_SHIFT 16u
9970 #define S32_SCB_SHPR1_PRI_6_WIDTH 8u
9971 #define S32_SCB_SHPR1_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_6_SHIFT))&S32_SCB_SHPR1_PRI_6_MASK)
9972 /* SHPR2 Bit Fields */
9973 #define S32_SCB_SHPR2_PRI_11_MASK 0xFF000000u
9974 #define S32_SCB_SHPR2_PRI_11_SHIFT 24u
9975 #define S32_SCB_SHPR2_PRI_11_WIDTH 8u
9976 #define S32_SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK)
9977 /* SHPR3 Bit Fields */
9978 #define S32_SCB_SHPR3_PRI_12_MASK 0xFFu
9979 #define S32_SCB_SHPR3_PRI_12_SHIFT 0u
9980 #define S32_SCB_SHPR3_PRI_12_WIDTH 8u
9981 #define S32_SCB_SHPR3_PRI_12(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_12_SHIFT))&S32_SCB_SHPR3_PRI_12_MASK)
9982 #define S32_SCB_SHPR3_PRI_14_MASK 0xFF0000u
9983 #define S32_SCB_SHPR3_PRI_14_SHIFT 16u
9984 #define S32_SCB_SHPR3_PRI_14_WIDTH 8u
9985 #define S32_SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK)
9986 #define S32_SCB_SHPR3_PRI_15_MASK 0xFF000000u
9987 #define S32_SCB_SHPR3_PRI_15_SHIFT 24u
9988 #define S32_SCB_SHPR3_PRI_15_WIDTH 8u
9989 #define S32_SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK)
9990 /* SHCSR Bit Fields */
9991 #define S32_SCB_SHCSR_MEMFAULTACT_MASK 0x1u
9992 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
9993 #define S32_SCB_SHCSR_MEMFAULTACT_WIDTH 1u
9994 #define S32_SCB_SHCSR_MEMFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTACT_SHIFT))&S32_SCB_SHCSR_MEMFAULTACT_MASK)
9995 #define S32_SCB_SHCSR_BUSFAULTACT_MASK 0x2u
9996 #define S32_SCB_SHCSR_BUSFAULTACT_SHIFT 1u
9997 #define S32_SCB_SHCSR_BUSFAULTACT_WIDTH 1u
9998 #define S32_SCB_SHCSR_BUSFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTACT_SHIFT))&S32_SCB_SHCSR_BUSFAULTACT_MASK)
9999 #define S32_SCB_SHCSR_USGFAULTACT_MASK 0x8u
10000 #define S32_SCB_SHCSR_USGFAULTACT_SHIFT 3u
10001 #define S32_SCB_SHCSR_USGFAULTACT_WIDTH 1u
10002 #define S32_SCB_SHCSR_USGFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTACT_SHIFT))&S32_SCB_SHCSR_USGFAULTACT_MASK)
10003 #define S32_SCB_SHCSR_SVCALLACT_MASK 0x80u
10004 #define S32_SCB_SHCSR_SVCALLACT_SHIFT 7u
10005 #define S32_SCB_SHCSR_SVCALLACT_WIDTH 1u
10006 #define S32_SCB_SHCSR_SVCALLACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLACT_SHIFT))&S32_SCB_SHCSR_SVCALLACT_MASK)
10007 #define S32_SCB_SHCSR_MONITORACT_MASK 0x100u
10008 #define S32_SCB_SHCSR_MONITORACT_SHIFT 8u
10009 #define S32_SCB_SHCSR_MONITORACT_WIDTH 1u
10010 #define S32_SCB_SHCSR_MONITORACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MONITORACT_SHIFT))&S32_SCB_SHCSR_MONITORACT_MASK)
10011 #define S32_SCB_SHCSR_PENDSVACT_MASK 0x400u
10012 #define S32_SCB_SHCSR_PENDSVACT_SHIFT 10u
10013 #define S32_SCB_SHCSR_PENDSVACT_WIDTH 1u
10014 #define S32_SCB_SHCSR_PENDSVACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_PENDSVACT_SHIFT))&S32_SCB_SHCSR_PENDSVACT_MASK)
10015 #define S32_SCB_SHCSR_SYSTICKACT_MASK 0x800u
10016 #define S32_SCB_SHCSR_SYSTICKACT_SHIFT 11u
10017 #define S32_SCB_SHCSR_SYSTICKACT_WIDTH 1u
10018 #define S32_SCB_SHCSR_SYSTICKACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SYSTICKACT_SHIFT))&S32_SCB_SHCSR_SYSTICKACT_MASK)
10019 #define S32_SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u
10020 #define S32_SCB_SHCSR_USGFAULTPENDED_SHIFT 12u
10021 #define S32_SCB_SHCSR_USGFAULTPENDED_WIDTH 1u
10022 #define S32_SCB_SHCSR_USGFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTPENDED_SHIFT))&S32_SCB_SHCSR_USGFAULTPENDED_MASK)
10023 #define S32_SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u
10024 #define S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT 13u
10025 #define S32_SCB_SHCSR_MEMFAULTPENDED_WIDTH 1u
10026 #define S32_SCB_SHCSR_MEMFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT))&S32_SCB_SHCSR_MEMFAULTPENDED_MASK)
10027 #define S32_SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u
10028 #define S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT 14u
10029 #define S32_SCB_SHCSR_BUSFAULTPENDED_WIDTH 1u
10030 #define S32_SCB_SHCSR_BUSFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT))&S32_SCB_SHCSR_BUSFAULTPENDED_MASK)
10031 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u
10032 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u
10033 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u
10034 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK)
10035 #define S32_SCB_SHCSR_MEMFAULTENA_MASK 0x10000u
10036 #define S32_SCB_SHCSR_MEMFAULTENA_SHIFT 16u
10037 #define S32_SCB_SHCSR_MEMFAULTENA_WIDTH 1u
10038 #define S32_SCB_SHCSR_MEMFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTENA_SHIFT))&S32_SCB_SHCSR_MEMFAULTENA_MASK)
10039 #define S32_SCB_SHCSR_BUSFAULTENA_MASK 0x20000u
10040 #define S32_SCB_SHCSR_BUSFAULTENA_SHIFT 17u
10041 #define S32_SCB_SHCSR_BUSFAULTENA_WIDTH 1u
10042 #define S32_SCB_SHCSR_BUSFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTENA_SHIFT))&S32_SCB_SHCSR_BUSFAULTENA_MASK)
10043 #define S32_SCB_SHCSR_USGFAULTENA_MASK 0x40000u
10044 #define S32_SCB_SHCSR_USGFAULTENA_SHIFT 18u
10045 #define S32_SCB_SHCSR_USGFAULTENA_WIDTH 1u
10046 #define S32_SCB_SHCSR_USGFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTENA_SHIFT))&S32_SCB_SHCSR_USGFAULTENA_MASK)
10047 /* CFSR Bit Fields */
10048 #define S32_SCB_CFSR_IACCVIOL_MASK 0x1u
10049 #define S32_SCB_CFSR_IACCVIOL_SHIFT 0u
10050 #define S32_SCB_CFSR_IACCVIOL_WIDTH 1u
10051 #define S32_SCB_CFSR_IACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IACCVIOL_SHIFT))&S32_SCB_CFSR_IACCVIOL_MASK)
10052 #define S32_SCB_CFSR_DACCVIOL_MASK 0x2u
10053 #define S32_SCB_CFSR_DACCVIOL_SHIFT 1u
10054 #define S32_SCB_CFSR_DACCVIOL_WIDTH 1u
10055 #define S32_SCB_CFSR_DACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DACCVIOL_SHIFT))&S32_SCB_CFSR_DACCVIOL_MASK)
10056 #define S32_SCB_CFSR_MUNSTKERR_MASK 0x8u
10057 #define S32_SCB_CFSR_MUNSTKERR_SHIFT 3u
10058 #define S32_SCB_CFSR_MUNSTKERR_WIDTH 1u
10059 #define S32_SCB_CFSR_MUNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MUNSTKERR_SHIFT))&S32_SCB_CFSR_MUNSTKERR_MASK)
10060 #define S32_SCB_CFSR_MSTKERR_MASK 0x10u
10061 #define S32_SCB_CFSR_MSTKERR_SHIFT 4u
10062 #define S32_SCB_CFSR_MSTKERR_WIDTH 1u
10063 #define S32_SCB_CFSR_MSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MSTKERR_SHIFT))&S32_SCB_CFSR_MSTKERR_MASK)
10064 #define S32_SCB_CFSR_MLSPERR_MASK 0x20u
10065 #define S32_SCB_CFSR_MLSPERR_SHIFT 5u
10066 #define S32_SCB_CFSR_MLSPERR_WIDTH 1u
10067 #define S32_SCB_CFSR_MLSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MLSPERR_SHIFT))&S32_SCB_CFSR_MLSPERR_MASK)
10068 #define S32_SCB_CFSR_MMARVALID_MASK 0x80u
10069 #define S32_SCB_CFSR_MMARVALID_SHIFT 7u
10070 #define S32_SCB_CFSR_MMARVALID_WIDTH 1u
10071 #define S32_SCB_CFSR_MMARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMARVALID_SHIFT))&S32_SCB_CFSR_MMARVALID_MASK)
10072 #define S32_SCB_CFSR_IBUSERR_MASK 0x100u
10073 #define S32_SCB_CFSR_IBUSERR_SHIFT 8u
10074 #define S32_SCB_CFSR_IBUSERR_WIDTH 1u
10075 #define S32_SCB_CFSR_IBUSERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IBUSERR_SHIFT))&S32_SCB_CFSR_IBUSERR_MASK)
10076 #define S32_SCB_CFSR_PRECISERR_MASK 0x200u
10077 #define S32_SCB_CFSR_PRECISERR_SHIFT 9u
10078 #define S32_SCB_CFSR_PRECISERR_WIDTH 1u
10079 #define S32_SCB_CFSR_PRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_PRECISERR_SHIFT))&S32_SCB_CFSR_PRECISERR_MASK)
10080 #define S32_SCB_CFSR_IMPRECISERR_MASK 0x400u
10081 #define S32_SCB_CFSR_IMPRECISERR_SHIFT 10u
10082 #define S32_SCB_CFSR_IMPRECISERR_WIDTH 1u
10083 #define S32_SCB_CFSR_IMPRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IMPRECISERR_SHIFT))&S32_SCB_CFSR_IMPRECISERR_MASK)
10084 #define S32_SCB_CFSR_UNSTKERR_MASK 0x800u
10085 #define S32_SCB_CFSR_UNSTKERR_SHIFT 11u
10086 #define S32_SCB_CFSR_UNSTKERR_WIDTH 1u
10087 #define S32_SCB_CFSR_UNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNSTKERR_SHIFT))&S32_SCB_CFSR_UNSTKERR_MASK)
10088 #define S32_SCB_CFSR_STKERR_MASK 0x1000u
10089 #define S32_SCB_CFSR_STKERR_SHIFT 12u
10090 #define S32_SCB_CFSR_STKERR_WIDTH 1u
10091 #define S32_SCB_CFSR_STKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_STKERR_SHIFT))&S32_SCB_CFSR_STKERR_MASK)
10092 #define S32_SCB_CFSR_LSPERR_MASK 0x2000u
10093 #define S32_SCB_CFSR_LSPERR_SHIFT 13u
10094 #define S32_SCB_CFSR_LSPERR_WIDTH 1u
10095 #define S32_SCB_CFSR_LSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_LSPERR_SHIFT))&S32_SCB_CFSR_LSPERR_MASK)
10096 #define S32_SCB_CFSR_BFARVALID_MASK 0x8000u
10097 #define S32_SCB_CFSR_BFARVALID_SHIFT 15u
10098 #define S32_SCB_CFSR_BFARVALID_WIDTH 1u
10099 #define S32_SCB_CFSR_BFARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFARVALID_SHIFT))&S32_SCB_CFSR_BFARVALID_MASK)
10100 #define S32_SCB_CFSR_UNDEFINSTR_MASK 0x10000u
10101 #define S32_SCB_CFSR_UNDEFINSTR_SHIFT 16u
10102 #define S32_SCB_CFSR_UNDEFINSTR_WIDTH 1u
10103 #define S32_SCB_CFSR_UNDEFINSTR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNDEFINSTR_SHIFT))&S32_SCB_CFSR_UNDEFINSTR_MASK)
10104 #define S32_SCB_CFSR_INVSTATE_MASK 0x20000u
10105 #define S32_SCB_CFSR_INVSTATE_SHIFT 17u
10106 #define S32_SCB_CFSR_INVSTATE_WIDTH 1u
10107 #define S32_SCB_CFSR_INVSTATE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVSTATE_SHIFT))&S32_SCB_CFSR_INVSTATE_MASK)
10108 #define S32_SCB_CFSR_INVPC_MASK 0x40000u
10109 #define S32_SCB_CFSR_INVPC_SHIFT 18u
10110 #define S32_SCB_CFSR_INVPC_WIDTH 1u
10111 #define S32_SCB_CFSR_INVPC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVPC_SHIFT))&S32_SCB_CFSR_INVPC_MASK)
10112 #define S32_SCB_CFSR_NOCP_MASK 0x80000u
10113 #define S32_SCB_CFSR_NOCP_SHIFT 19u
10114 #define S32_SCB_CFSR_NOCP_WIDTH 1u
10115 #define S32_SCB_CFSR_NOCP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_NOCP_SHIFT))&S32_SCB_CFSR_NOCP_MASK)
10116 #define S32_SCB_CFSR_UNALIGNED_MASK 0x1000000u
10117 #define S32_SCB_CFSR_UNALIGNED_SHIFT 24u
10118 #define S32_SCB_CFSR_UNALIGNED_WIDTH 1u
10119 #define S32_SCB_CFSR_UNALIGNED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNALIGNED_SHIFT))&S32_SCB_CFSR_UNALIGNED_MASK)
10120 #define S32_SCB_CFSR_DIVBYZERO_MASK 0x2000000u
10121 #define S32_SCB_CFSR_DIVBYZERO_SHIFT 25u
10122 #define S32_SCB_CFSR_DIVBYZERO_WIDTH 1u
10123 #define S32_SCB_CFSR_DIVBYZERO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DIVBYZERO_SHIFT))&S32_SCB_CFSR_DIVBYZERO_MASK)
10124 /* HFSR Bit Fields */
10125 #define S32_SCB_HFSR_VECTTBL_MASK 0x2u
10126 #define S32_SCB_HFSR_VECTTBL_SHIFT 1u
10127 #define S32_SCB_HFSR_VECTTBL_WIDTH 1u
10128 #define S32_SCB_HFSR_VECTTBL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_VECTTBL_SHIFT))&S32_SCB_HFSR_VECTTBL_MASK)
10129 #define S32_SCB_HFSR_FORCED_MASK 0x40000000u
10130 #define S32_SCB_HFSR_FORCED_SHIFT 30u
10131 #define S32_SCB_HFSR_FORCED_WIDTH 1u
10132 #define S32_SCB_HFSR_FORCED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_FORCED_SHIFT))&S32_SCB_HFSR_FORCED_MASK)
10133 #define S32_SCB_HFSR_DEBUGEVT_MASK 0x80000000u
10134 #define S32_SCB_HFSR_DEBUGEVT_SHIFT 31u
10135 #define S32_SCB_HFSR_DEBUGEVT_WIDTH 1u
10136 #define S32_SCB_HFSR_DEBUGEVT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_DEBUGEVT_SHIFT))&S32_SCB_HFSR_DEBUGEVT_MASK)
10137 /* DFSR Bit Fields */
10138 #define S32_SCB_DFSR_HALTED_MASK 0x1u
10139 #define S32_SCB_DFSR_HALTED_SHIFT 0u
10140 #define S32_SCB_DFSR_HALTED_WIDTH 1u
10141 #define S32_SCB_DFSR_HALTED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK)
10142 #define S32_SCB_DFSR_BKPT_MASK 0x2u
10143 #define S32_SCB_DFSR_BKPT_SHIFT 1u
10144 #define S32_SCB_DFSR_BKPT_WIDTH 1u
10145 #define S32_SCB_DFSR_BKPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK)
10146 #define S32_SCB_DFSR_DWTTRAP_MASK 0x4u
10147 #define S32_SCB_DFSR_DWTTRAP_SHIFT 2u
10148 #define S32_SCB_DFSR_DWTTRAP_WIDTH 1u
10149 #define S32_SCB_DFSR_DWTTRAP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK)
10150 #define S32_SCB_DFSR_VCATCH_MASK 0x8u
10151 #define S32_SCB_DFSR_VCATCH_SHIFT 3u
10152 #define S32_SCB_DFSR_VCATCH_WIDTH 1u
10153 #define S32_SCB_DFSR_VCATCH(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK)
10154 #define S32_SCB_DFSR_EXTERNAL_MASK 0x10u
10155 #define S32_SCB_DFSR_EXTERNAL_SHIFT 4u
10156 #define S32_SCB_DFSR_EXTERNAL_WIDTH 1u
10157 #define S32_SCB_DFSR_EXTERNAL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK)
10158 /* MMFAR Bit Fields */
10159 #define S32_SCB_MMFAR_ADDRESS_MASK 0xFFFFFFFFu
10160 #define S32_SCB_MMFAR_ADDRESS_SHIFT 0u
10161 #define S32_SCB_MMFAR_ADDRESS_WIDTH 32u
10162 #define S32_SCB_MMFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_MMFAR_ADDRESS_SHIFT))&S32_SCB_MMFAR_ADDRESS_MASK)
10163 /* BFAR Bit Fields */
10164 #define S32_SCB_BFAR_ADDRESS_MASK 0xFFFFFFFFu
10165 #define S32_SCB_BFAR_ADDRESS_SHIFT 0u
10166 #define S32_SCB_BFAR_ADDRESS_WIDTH 32u
10167 #define S32_SCB_BFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_BFAR_ADDRESS_SHIFT))&S32_SCB_BFAR_ADDRESS_MASK)
10168 /* AFSR Bit Fields */
10169 #define S32_SCB_AFSR_AUXFAULT_MASK 0xFFFFFFFFu
10170 #define S32_SCB_AFSR_AUXFAULT_SHIFT 0u
10171 #define S32_SCB_AFSR_AUXFAULT_WIDTH 32u
10172 #define S32_SCB_AFSR_AUXFAULT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AFSR_AUXFAULT_SHIFT))&S32_SCB_AFSR_AUXFAULT_MASK)
10173 /* CPACR Bit Fields */
10174 #define S32_SCB_CPACR_CP10_MASK 0x300000u
10175 #define S32_SCB_CPACR_CP10_SHIFT 20u
10176 #define S32_SCB_CPACR_CP10_WIDTH 2u
10177 #define S32_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP10_SHIFT))&S32_SCB_CPACR_CP10_MASK)
10178 #define S32_SCB_CPACR_CP11_MASK 0xC00000u
10179 #define S32_SCB_CPACR_CP11_SHIFT 22u
10180 #define S32_SCB_CPACR_CP11_WIDTH 2u
10181 #define S32_SCB_CPACR_CP11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP11_SHIFT))&S32_SCB_CPACR_CP11_MASK)
10182 /* FPCCR Bit Fields */
10183 #define S32_SCB_FPCCR_LSPACT_MASK 0x1u
10184 #define S32_SCB_FPCCR_LSPACT_SHIFT 0u
10185 #define S32_SCB_FPCCR_LSPACT_WIDTH 1u
10186 #define S32_SCB_FPCCR_LSPACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPACT_SHIFT))&S32_SCB_FPCCR_LSPACT_MASK)
10187 #define S32_SCB_FPCCR_USER_MASK 0x2u
10188 #define S32_SCB_FPCCR_USER_SHIFT 1u
10189 #define S32_SCB_FPCCR_USER_WIDTH 1u
10190 #define S32_SCB_FPCCR_USER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_USER_SHIFT))&S32_SCB_FPCCR_USER_MASK)
10191 #define S32_SCB_FPCCR_THREAD_MASK 0x8u
10192 #define S32_SCB_FPCCR_THREAD_SHIFT 3u
10193 #define S32_SCB_FPCCR_THREAD_WIDTH 1u
10194 #define S32_SCB_FPCCR_THREAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_THREAD_SHIFT))&S32_SCB_FPCCR_THREAD_MASK)
10195 #define S32_SCB_FPCCR_HFRDY_MASK 0x10u
10196 #define S32_SCB_FPCCR_HFRDY_SHIFT 4u
10197 #define S32_SCB_FPCCR_HFRDY_WIDTH 1u
10198 #define S32_SCB_FPCCR_HFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_HFRDY_SHIFT))&S32_SCB_FPCCR_HFRDY_MASK)
10199 #define S32_SCB_FPCCR_MMRDY_MASK 0x20u
10200 #define S32_SCB_FPCCR_MMRDY_SHIFT 5u
10201 #define S32_SCB_FPCCR_MMRDY_WIDTH 1u
10202 #define S32_SCB_FPCCR_MMRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MMRDY_SHIFT))&S32_SCB_FPCCR_MMRDY_MASK)
10203 #define S32_SCB_FPCCR_BFRDY_MASK 0x40u
10204 #define S32_SCB_FPCCR_BFRDY_SHIFT 6u
10205 #define S32_SCB_FPCCR_BFRDY_WIDTH 1u
10206 #define S32_SCB_FPCCR_BFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_BFRDY_SHIFT))&S32_SCB_FPCCR_BFRDY_MASK)
10207 #define S32_SCB_FPCCR_MONRDY_MASK 0x100u
10208 #define S32_SCB_FPCCR_MONRDY_SHIFT 8u
10209 #define S32_SCB_FPCCR_MONRDY_WIDTH 1u
10210 #define S32_SCB_FPCCR_MONRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MONRDY_SHIFT))&S32_SCB_FPCCR_MONRDY_MASK)
10211 #define S32_SCB_FPCCR_LSPEN_MASK 0x40000000u
10212 #define S32_SCB_FPCCR_LSPEN_SHIFT 30u
10213 #define S32_SCB_FPCCR_LSPEN_WIDTH 1u
10214 #define S32_SCB_FPCCR_LSPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPEN_SHIFT))&S32_SCB_FPCCR_LSPEN_MASK)
10215 #define S32_SCB_FPCCR_ASPEN_MASK 0x80000000u
10216 #define S32_SCB_FPCCR_ASPEN_SHIFT 31u
10217 #define S32_SCB_FPCCR_ASPEN_WIDTH 1u
10218 #define S32_SCB_FPCCR_ASPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_ASPEN_SHIFT))&S32_SCB_FPCCR_ASPEN_MASK)
10219 /* FPCAR Bit Fields */
10220 #define S32_SCB_FPCAR_ADDRESS_MASK 0xFFFFFFF8u
10221 #define S32_SCB_FPCAR_ADDRESS_SHIFT 3u
10222 #define S32_SCB_FPCAR_ADDRESS_WIDTH 29u
10223 #define S32_SCB_FPCAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCAR_ADDRESS_SHIFT))&S32_SCB_FPCAR_ADDRESS_MASK)
10224 /* FPDSCR Bit Fields */
10225 #define S32_SCB_FPDSCR_RMode_MASK 0xC00000u
10226 #define S32_SCB_FPDSCR_RMode_SHIFT 22u
10227 #define S32_SCB_FPDSCR_RMode_WIDTH 2u
10228 #define S32_SCB_FPDSCR_RMode(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_RMode_SHIFT))&S32_SCB_FPDSCR_RMode_MASK)
10229 #define S32_SCB_FPDSCR_FZ_MASK 0x1000000u
10230 #define S32_SCB_FPDSCR_FZ_SHIFT 24u
10231 #define S32_SCB_FPDSCR_FZ_WIDTH 1u
10232 #define S32_SCB_FPDSCR_FZ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_FZ_SHIFT))&S32_SCB_FPDSCR_FZ_MASK)
10233 #define S32_SCB_FPDSCR_DN_MASK 0x2000000u
10234 #define S32_SCB_FPDSCR_DN_SHIFT 25u
10235 #define S32_SCB_FPDSCR_DN_WIDTH 1u
10236 #define S32_SCB_FPDSCR_DN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_DN_SHIFT))&S32_SCB_FPDSCR_DN_MASK)
10237 #define S32_SCB_FPDSCR_AHP_MASK 0x4000000u
10238 #define S32_SCB_FPDSCR_AHP_SHIFT 26u
10239 #define S32_SCB_FPDSCR_AHP_WIDTH 1u
10240 #define S32_SCB_FPDSCR_AHP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_AHP_SHIFT))&S32_SCB_FPDSCR_AHP_MASK)
10241  /* end of group S32_SCB_Register_Masks */
10245 
10246  /* end of group S32_SCB_Peripheral_Access_Layer */
10250 
10251 
10252 /* ----------------------------------------------------------------------------
10253  -- S32_SysTick Peripheral Access Layer
10254  ---------------------------------------------------------------------------- */
10255 
10265 typedef struct {
10266  __IO uint32_t CSR;
10267  __IO uint32_t RVR;
10268  __IO uint32_t CVR;
10269  __I uint32_t CALIB;
10271 
10273 #define S32_SysTick_INSTANCE_COUNT (1u)
10274 
10275 
10276 /* S32_SysTick - Peripheral instance base addresses */
10278 #define S32_SysTick_BASE (0xE000E010u)
10279 
10280 #define S32_SysTick ((S32_SysTick_Type *)S32_SysTick_BASE)
10281 
10282 #define S32_SysTick_BASE_ADDRS { S32_SysTick_BASE }
10283 
10284 #define S32_SysTick_BASE_PTRS { S32_SysTick }
10285 
10286 #define S32_SysTick_IRQS_ARR_COUNT (1u)
10287 
10288 #define S32_SysTick_IRQS_CH_COUNT (1u)
10289 
10290 #define S32_SysTick_IRQS { SysTick_IRQn }
10291 
10292 /* ----------------------------------------------------------------------------
10293  -- S32_SysTick Register Masks
10294  ---------------------------------------------------------------------------- */
10295 
10301 /* CSR Bit Fields */
10302 #define S32_SysTick_CSR_ENABLE_MASK 0x1u
10303 #define S32_SysTick_CSR_ENABLE_SHIFT 0u
10304 #define S32_SysTick_CSR_ENABLE_WIDTH 1u
10305 #define S32_SysTick_CSR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_ENABLE_SHIFT))&S32_SysTick_CSR_ENABLE_MASK)
10306 #define S32_SysTick_CSR_TICKINT_MASK 0x2u
10307 #define S32_SysTick_CSR_TICKINT_SHIFT 1u
10308 #define S32_SysTick_CSR_TICKINT_WIDTH 1u
10309 #define S32_SysTick_CSR_TICKINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_TICKINT_SHIFT))&S32_SysTick_CSR_TICKINT_MASK)
10310 #define S32_SysTick_CSR_CLKSOURCE_MASK 0x4u
10311 #define S32_SysTick_CSR_CLKSOURCE_SHIFT 2u
10312 #define S32_SysTick_CSR_CLKSOURCE_WIDTH 1u
10313 #define S32_SysTick_CSR_CLKSOURCE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_CLKSOURCE_SHIFT))&S32_SysTick_CSR_CLKSOURCE_MASK)
10314 #define S32_SysTick_CSR_COUNTFLAG_MASK 0x10000u
10315 #define S32_SysTick_CSR_COUNTFLAG_SHIFT 16u
10316 #define S32_SysTick_CSR_COUNTFLAG_WIDTH 1u
10317 #define S32_SysTick_CSR_COUNTFLAG(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_COUNTFLAG_SHIFT))&S32_SysTick_CSR_COUNTFLAG_MASK)
10318 /* RVR Bit Fields */
10319 #define S32_SysTick_RVR_RELOAD_MASK 0xFFFFFFu
10320 #define S32_SysTick_RVR_RELOAD_SHIFT 0u
10321 #define S32_SysTick_RVR_RELOAD_WIDTH 24u
10322 #define S32_SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_RVR_RELOAD_SHIFT))&S32_SysTick_RVR_RELOAD_MASK)
10323 /* CVR Bit Fields */
10324 #define S32_SysTick_CVR_CURRENT_MASK 0xFFFFFFu
10325 #define S32_SysTick_CVR_CURRENT_SHIFT 0u
10326 #define S32_SysTick_CVR_CURRENT_WIDTH 24u
10327 #define S32_SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CVR_CURRENT_SHIFT))&S32_SysTick_CVR_CURRENT_MASK)
10328 /* CALIB Bit Fields */
10329 #define S32_SysTick_CALIB_TENMS_MASK 0xFFFFFFu
10330 #define S32_SysTick_CALIB_TENMS_SHIFT 0u
10331 #define S32_SysTick_CALIB_TENMS_WIDTH 24u
10332 #define S32_SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_TENMS_SHIFT))&S32_SysTick_CALIB_TENMS_MASK)
10333 #define S32_SysTick_CALIB_SKEW_MASK 0x40000000u
10334 #define S32_SysTick_CALIB_SKEW_SHIFT 30u
10335 #define S32_SysTick_CALIB_SKEW_WIDTH 1u
10336 #define S32_SysTick_CALIB_SKEW(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_SKEW_SHIFT))&S32_SysTick_CALIB_SKEW_MASK)
10337 #define S32_SysTick_CALIB_NOREF_MASK 0x80000000u
10338 #define S32_SysTick_CALIB_NOREF_SHIFT 31u
10339 #define S32_SysTick_CALIB_NOREF_WIDTH 1u
10340 #define S32_SysTick_CALIB_NOREF(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_NOREF_SHIFT))&S32_SysTick_CALIB_NOREF_MASK)
10341  /* end of group S32_SysTick_Register_Masks */
10345 
10346  /* end of group S32_SysTick_Peripheral_Access_Layer */
10350 
10351 
10352 /* ----------------------------------------------------------------------------
10353  -- SCG Peripheral Access Layer
10354  ---------------------------------------------------------------------------- */
10355 
10365 typedef struct {
10366  __I uint32_t VERID;
10367  __I uint32_t PARAM;
10368  uint8_t RESERVED_0[8];
10369  __I uint32_t CSR;
10370  __IO uint32_t RCCR;
10371  __IO uint32_t VCCR;
10372  __IO uint32_t HCCR;
10373  __IO uint32_t CLKOUTCNFG;
10374  uint8_t RESERVED_1[220];
10375  __IO uint32_t SOSCCSR;
10376  __IO uint32_t SOSCDIV;
10377  __IO uint32_t SOSCCFG;
10378  uint8_t RESERVED_2[244];
10379  __IO uint32_t SIRCCSR;
10380  __IO uint32_t SIRCDIV;
10381  __IO uint32_t SIRCCFG;
10382  uint8_t RESERVED_3[244];
10383  __IO uint32_t FIRCCSR;
10384  __IO uint32_t FIRCDIV;
10385  __IO uint32_t FIRCCFG;
10386  uint8_t RESERVED_4[756];
10387  __IO uint32_t SPLLCSR;
10388  __IO uint32_t SPLLDIV;
10389  __IO uint32_t SPLLCFG;
10391 
10393 #define SCG_INSTANCE_COUNT (1u)
10394 
10395 
10396 /* SCG - Peripheral instance base addresses */
10398 #define SCG_BASE (0x40064000u)
10399 
10400 #define SCG ((SCG_Type *)SCG_BASE)
10401 
10402 #define SCG_BASE_ADDRS { SCG_BASE }
10403 
10404 #define SCG_BASE_PTRS { SCG }
10405 
10406 #define SCG_IRQS_ARR_COUNT (1u)
10407 
10408 #define SCG_IRQS_CH_COUNT (1u)
10409 
10410 #define SCG_IRQS { SCG_IRQn }
10411 
10412 /* ----------------------------------------------------------------------------
10413  -- SCG Register Masks
10414  ---------------------------------------------------------------------------- */
10415 
10421 /* VERID Bit Fields */
10422 #define SCG_VERID_VERSION_MASK 0xFFFFFFFFu
10423 #define SCG_VERID_VERSION_SHIFT 0u
10424 #define SCG_VERID_VERSION_WIDTH 32u
10425 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x))<<SCG_VERID_VERSION_SHIFT))&SCG_VERID_VERSION_MASK)
10426 /* PARAM Bit Fields */
10427 #define SCG_PARAM_CLKPRES_MASK 0xFFu
10428 #define SCG_PARAM_CLKPRES_SHIFT 0u
10429 #define SCG_PARAM_CLKPRES_WIDTH 8u
10430 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_CLKPRES_SHIFT))&SCG_PARAM_CLKPRES_MASK)
10431 #define SCG_PARAM_DIVPRES_MASK 0xF8000000u
10432 #define SCG_PARAM_DIVPRES_SHIFT 27u
10433 #define SCG_PARAM_DIVPRES_WIDTH 5u
10434 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_DIVPRES_SHIFT))&SCG_PARAM_DIVPRES_MASK)
10435 /* CSR Bit Fields */
10436 #define SCG_CSR_DIVSLOW_MASK 0xFu
10437 #define SCG_CSR_DIVSLOW_SHIFT 0u
10438 #define SCG_CSR_DIVSLOW_WIDTH 4u
10439 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVSLOW_SHIFT))&SCG_CSR_DIVSLOW_MASK)
10440 #define SCG_CSR_DIVBUS_MASK 0xF0u
10441 #define SCG_CSR_DIVBUS_SHIFT 4u
10442 #define SCG_CSR_DIVBUS_WIDTH 4u
10443 #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVBUS_SHIFT))&SCG_CSR_DIVBUS_MASK)
10444 #define SCG_CSR_DIVCORE_MASK 0xF0000u
10445 #define SCG_CSR_DIVCORE_SHIFT 16u
10446 #define SCG_CSR_DIVCORE_WIDTH 4u
10447 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVCORE_SHIFT))&SCG_CSR_DIVCORE_MASK)
10448 #define SCG_CSR_SCS_MASK 0xF000000u
10449 #define SCG_CSR_SCS_SHIFT 24u
10450 #define SCG_CSR_SCS_WIDTH 4u
10451 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_SCS_SHIFT))&SCG_CSR_SCS_MASK)
10452 /* RCCR Bit Fields */
10453 #define SCG_RCCR_DIVSLOW_MASK 0xFu
10454 #define SCG_RCCR_DIVSLOW_SHIFT 0u
10455 #define SCG_RCCR_DIVSLOW_WIDTH 4u
10456 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVSLOW_SHIFT))&SCG_RCCR_DIVSLOW_MASK)
10457 #define SCG_RCCR_DIVBUS_MASK 0xF0u
10458 #define SCG_RCCR_DIVBUS_SHIFT 4u
10459 #define SCG_RCCR_DIVBUS_WIDTH 4u
10460 #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVBUS_SHIFT))&SCG_RCCR_DIVBUS_MASK)
10461 #define SCG_RCCR_DIVCORE_MASK 0xF0000u
10462 #define SCG_RCCR_DIVCORE_SHIFT 16u
10463 #define SCG_RCCR_DIVCORE_WIDTH 4u
10464 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVCORE_SHIFT))&SCG_RCCR_DIVCORE_MASK)
10465 #define SCG_RCCR_SCS_MASK 0xF000000u
10466 #define SCG_RCCR_SCS_SHIFT 24u
10467 #define SCG_RCCR_SCS_WIDTH 4u
10468 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_SCS_SHIFT))&SCG_RCCR_SCS_MASK)
10469 /* VCCR Bit Fields */
10470 #define SCG_VCCR_DIVSLOW_MASK 0xFu
10471 #define SCG_VCCR_DIVSLOW_SHIFT 0u
10472 #define SCG_VCCR_DIVSLOW_WIDTH 4u
10473 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVSLOW_SHIFT))&SCG_VCCR_DIVSLOW_MASK)
10474 #define SCG_VCCR_DIVBUS_MASK 0xF0u
10475 #define SCG_VCCR_DIVBUS_SHIFT 4u
10476 #define SCG_VCCR_DIVBUS_WIDTH 4u
10477 #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVBUS_SHIFT))&SCG_VCCR_DIVBUS_MASK)
10478 #define SCG_VCCR_DIVCORE_MASK 0xF0000u
10479 #define SCG_VCCR_DIVCORE_SHIFT 16u
10480 #define SCG_VCCR_DIVCORE_WIDTH 4u
10481 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVCORE_SHIFT))&SCG_VCCR_DIVCORE_MASK)
10482 #define SCG_VCCR_SCS_MASK 0xF000000u
10483 #define SCG_VCCR_SCS_SHIFT 24u
10484 #define SCG_VCCR_SCS_WIDTH 4u
10485 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_SCS_SHIFT))&SCG_VCCR_SCS_MASK)
10486 /* HCCR Bit Fields */
10487 #define SCG_HCCR_DIVSLOW_MASK 0xFu
10488 #define SCG_HCCR_DIVSLOW_SHIFT 0u
10489 #define SCG_HCCR_DIVSLOW_WIDTH 4u
10490 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVSLOW_SHIFT))&SCG_HCCR_DIVSLOW_MASK)
10491 #define SCG_HCCR_DIVBUS_MASK 0xF0u
10492 #define SCG_HCCR_DIVBUS_SHIFT 4u
10493 #define SCG_HCCR_DIVBUS_WIDTH 4u
10494 #define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVBUS_SHIFT))&SCG_HCCR_DIVBUS_MASK)
10495 #define SCG_HCCR_DIVCORE_MASK 0xF0000u
10496 #define SCG_HCCR_DIVCORE_SHIFT 16u
10497 #define SCG_HCCR_DIVCORE_WIDTH 4u
10498 #define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVCORE_SHIFT))&SCG_HCCR_DIVCORE_MASK)
10499 #define SCG_HCCR_SCS_MASK 0xF000000u
10500 #define SCG_HCCR_SCS_SHIFT 24u
10501 #define SCG_HCCR_SCS_WIDTH 4u
10502 #define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_SCS_SHIFT))&SCG_HCCR_SCS_MASK)
10503 /* CLKOUTCNFG Bit Fields */
10504 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK 0xF000000u
10505 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT 24u
10506 #define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH 4u
10507 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT))&SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
10508 /* SOSCCSR Bit Fields */
10509 #define SCG_SOSCCSR_SOSCEN_MASK 0x1u
10510 #define SCG_SOSCCSR_SOSCEN_SHIFT 0u
10511 #define SCG_SOSCCSR_SOSCEN_WIDTH 1u
10512 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCEN_SHIFT))&SCG_SOSCCSR_SOSCEN_MASK)
10513 #define SCG_SOSCCSR_SOSCCM_MASK 0x10000u
10514 #define SCG_SOSCCSR_SOSCCM_SHIFT 16u
10515 #define SCG_SOSCCSR_SOSCCM_WIDTH 1u
10516 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCM_SHIFT))&SCG_SOSCCSR_SOSCCM_MASK)
10517 #define SCG_SOSCCSR_SOSCCMRE_MASK 0x20000u
10518 #define SCG_SOSCCSR_SOSCCMRE_SHIFT 17u
10519 #define SCG_SOSCCSR_SOSCCMRE_WIDTH 1u
10520 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCMRE_SHIFT))&SCG_SOSCCSR_SOSCCMRE_MASK)
10521 #define SCG_SOSCCSR_LK_MASK 0x800000u
10522 #define SCG_SOSCCSR_LK_SHIFT 23u
10523 #define SCG_SOSCCSR_LK_WIDTH 1u
10524 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_LK_SHIFT))&SCG_SOSCCSR_LK_MASK)
10525 #define SCG_SOSCCSR_SOSCVLD_MASK 0x1000000u
10526 #define SCG_SOSCCSR_SOSCVLD_SHIFT 24u
10527 #define SCG_SOSCCSR_SOSCVLD_WIDTH 1u
10528 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCVLD_SHIFT))&SCG_SOSCCSR_SOSCVLD_MASK)
10529 #define SCG_SOSCCSR_SOSCSEL_MASK 0x2000000u
10530 #define SCG_SOSCCSR_SOSCSEL_SHIFT 25u
10531 #define SCG_SOSCCSR_SOSCSEL_WIDTH 1u
10532 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSEL_SHIFT))&SCG_SOSCCSR_SOSCSEL_MASK)
10533 #define SCG_SOSCCSR_SOSCERR_MASK 0x4000000u
10534 #define SCG_SOSCCSR_SOSCERR_SHIFT 26u
10535 #define SCG_SOSCCSR_SOSCERR_WIDTH 1u
10536 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERR_SHIFT))&SCG_SOSCCSR_SOSCERR_MASK)
10537 /* SOSCDIV Bit Fields */
10538 #define SCG_SOSCDIV_SOSCDIV1_MASK 0x7u
10539 #define SCG_SOSCDIV_SOSCDIV1_SHIFT 0u
10540 #define SCG_SOSCDIV_SOSCDIV1_WIDTH 3u
10541 #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV1_SHIFT))&SCG_SOSCDIV_SOSCDIV1_MASK)
10542 #define SCG_SOSCDIV_SOSCDIV2_MASK 0x700u
10543 #define SCG_SOSCDIV_SOSCDIV2_SHIFT 8u
10544 #define SCG_SOSCDIV_SOSCDIV2_WIDTH 3u
10545 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV2_SHIFT))&SCG_SOSCDIV_SOSCDIV2_MASK)
10546 /* SOSCCFG Bit Fields */
10547 #define SCG_SOSCCFG_EREFS_MASK 0x4u
10548 #define SCG_SOSCCFG_EREFS_SHIFT 2u
10549 #define SCG_SOSCCFG_EREFS_WIDTH 1u
10550 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_EREFS_SHIFT))&SCG_SOSCCFG_EREFS_MASK)
10551 #define SCG_SOSCCFG_HGO_MASK 0x8u
10552 #define SCG_SOSCCFG_HGO_SHIFT 3u
10553 #define SCG_SOSCCFG_HGO_WIDTH 1u
10554 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_HGO_SHIFT))&SCG_SOSCCFG_HGO_MASK)
10555 #define SCG_SOSCCFG_RANGE_MASK 0x30u
10556 #define SCG_SOSCCFG_RANGE_SHIFT 4u
10557 #define SCG_SOSCCFG_RANGE_WIDTH 2u
10558 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_RANGE_SHIFT))&SCG_SOSCCFG_RANGE_MASK)
10559 /* SIRCCSR Bit Fields */
10560 #define SCG_SIRCCSR_SIRCEN_MASK 0x1u
10561 #define SCG_SIRCCSR_SIRCEN_SHIFT 0u
10562 #define SCG_SIRCCSR_SIRCEN_WIDTH 1u
10563 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCEN_SHIFT))&SCG_SIRCCSR_SIRCEN_MASK)
10564 #define SCG_SIRCCSR_SIRCSTEN_MASK 0x2u
10565 #define SCG_SIRCCSR_SIRCSTEN_SHIFT 1u
10566 #define SCG_SIRCCSR_SIRCSTEN_WIDTH 1u
10567 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSTEN_SHIFT))&SCG_SIRCCSR_SIRCSTEN_MASK)
10568 #define SCG_SIRCCSR_SIRCLPEN_MASK 0x4u
10569 #define SCG_SIRCCSR_SIRCLPEN_SHIFT 2u
10570 #define SCG_SIRCCSR_SIRCLPEN_WIDTH 1u
10571 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCLPEN_SHIFT))&SCG_SIRCCSR_SIRCLPEN_MASK)
10572 #define SCG_SIRCCSR_LK_MASK 0x800000u
10573 #define SCG_SIRCCSR_LK_SHIFT 23u
10574 #define SCG_SIRCCSR_LK_WIDTH 1u
10575 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_LK_SHIFT))&SCG_SIRCCSR_LK_MASK)
10576 #define SCG_SIRCCSR_SIRCVLD_MASK 0x1000000u
10577 #define SCG_SIRCCSR_SIRCVLD_SHIFT 24u
10578 #define SCG_SIRCCSR_SIRCVLD_WIDTH 1u
10579 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCVLD_SHIFT))&SCG_SIRCCSR_SIRCVLD_MASK)
10580 #define SCG_SIRCCSR_SIRCSEL_MASK 0x2000000u
10581 #define SCG_SIRCCSR_SIRCSEL_SHIFT 25u
10582 #define SCG_SIRCCSR_SIRCSEL_WIDTH 1u
10583 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSEL_SHIFT))&SCG_SIRCCSR_SIRCSEL_MASK)
10584 /* SIRCDIV Bit Fields */
10585 #define SCG_SIRCDIV_SIRCDIV1_MASK 0x7u
10586 #define SCG_SIRCDIV_SIRCDIV1_SHIFT 0u
10587 #define SCG_SIRCDIV_SIRCDIV1_WIDTH 3u
10588 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV1_SHIFT))&SCG_SIRCDIV_SIRCDIV1_MASK)
10589 #define SCG_SIRCDIV_SIRCDIV2_MASK 0x700u
10590 #define SCG_SIRCDIV_SIRCDIV2_SHIFT 8u
10591 #define SCG_SIRCDIV_SIRCDIV2_WIDTH 3u
10592 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV2_SHIFT))&SCG_SIRCDIV_SIRCDIV2_MASK)
10593 /* SIRCCFG Bit Fields */
10594 #define SCG_SIRCCFG_RANGE_MASK 0x1u
10595 #define SCG_SIRCCFG_RANGE_SHIFT 0u
10596 #define SCG_SIRCCFG_RANGE_WIDTH 1u
10597 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCFG_RANGE_SHIFT))&SCG_SIRCCFG_RANGE_MASK)
10598 /* FIRCCSR Bit Fields */
10599 #define SCG_FIRCCSR_FIRCEN_MASK 0x1u
10600 #define SCG_FIRCCSR_FIRCEN_SHIFT 0u
10601 #define SCG_FIRCCSR_FIRCEN_WIDTH 1u
10602 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCEN_SHIFT))&SCG_FIRCCSR_FIRCEN_MASK)
10603 #define SCG_FIRCCSR_FIRCREGOFF_MASK 0x8u
10604 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT 3u
10605 #define SCG_FIRCCSR_FIRCREGOFF_WIDTH 1u
10606 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCREGOFF_SHIFT))&SCG_FIRCCSR_FIRCREGOFF_MASK)
10607 #define SCG_FIRCCSR_LK_MASK 0x800000u
10608 #define SCG_FIRCCSR_LK_SHIFT 23u
10609 #define SCG_FIRCCSR_LK_WIDTH 1u
10610 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_LK_SHIFT))&SCG_FIRCCSR_LK_MASK)
10611 #define SCG_FIRCCSR_FIRCVLD_MASK 0x1000000u
10612 #define SCG_FIRCCSR_FIRCVLD_SHIFT 24u
10613 #define SCG_FIRCCSR_FIRCVLD_WIDTH 1u
10614 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCVLD_SHIFT))&SCG_FIRCCSR_FIRCVLD_MASK)
10615 #define SCG_FIRCCSR_FIRCSEL_MASK 0x2000000u
10616 #define SCG_FIRCCSR_FIRCSEL_SHIFT 25u
10617 #define SCG_FIRCCSR_FIRCSEL_WIDTH 1u
10618 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSEL_SHIFT))&SCG_FIRCCSR_FIRCSEL_MASK)
10619 #define SCG_FIRCCSR_FIRCERR_MASK 0x4000000u
10620 #define SCG_FIRCCSR_FIRCERR_SHIFT 26u
10621 #define SCG_FIRCCSR_FIRCERR_WIDTH 1u
10622 #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCERR_SHIFT))&SCG_FIRCCSR_FIRCERR_MASK)
10623 /* FIRCDIV Bit Fields */
10624 #define SCG_FIRCDIV_FIRCDIV1_MASK 0x7u
10625 #define SCG_FIRCDIV_FIRCDIV1_SHIFT 0u
10626 #define SCG_FIRCDIV_FIRCDIV1_WIDTH 3u
10627 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV1_SHIFT))&SCG_FIRCDIV_FIRCDIV1_MASK)
10628 #define SCG_FIRCDIV_FIRCDIV2_MASK 0x700u
10629 #define SCG_FIRCDIV_FIRCDIV2_SHIFT 8u
10630 #define SCG_FIRCDIV_FIRCDIV2_WIDTH 3u
10631 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV2_SHIFT))&SCG_FIRCDIV_FIRCDIV2_MASK)
10632 /* FIRCCFG Bit Fields */
10633 #define SCG_FIRCCFG_RANGE_MASK 0x3u
10634 #define SCG_FIRCCFG_RANGE_SHIFT 0u
10635 #define SCG_FIRCCFG_RANGE_WIDTH 2u
10636 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCFG_RANGE_SHIFT))&SCG_FIRCCFG_RANGE_MASK)
10637 /* SPLLCSR Bit Fields */
10638 #define SCG_SPLLCSR_SPLLEN_MASK 0x1u
10639 #define SCG_SPLLCSR_SPLLEN_SHIFT 0u
10640 #define SCG_SPLLCSR_SPLLEN_WIDTH 1u
10641 #define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLEN_SHIFT))&SCG_SPLLCSR_SPLLEN_MASK)
10642 #define SCG_SPLLCSR_SPLLCM_MASK 0x10000u
10643 #define SCG_SPLLCSR_SPLLCM_SHIFT 16u
10644 #define SCG_SPLLCSR_SPLLCM_WIDTH 1u
10645 #define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCM_SHIFT))&SCG_SPLLCSR_SPLLCM_MASK)
10646 #define SCG_SPLLCSR_SPLLCMRE_MASK 0x20000u
10647 #define SCG_SPLLCSR_SPLLCMRE_SHIFT 17u
10648 #define SCG_SPLLCSR_SPLLCMRE_WIDTH 1u
10649 #define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCMRE_SHIFT))&SCG_SPLLCSR_SPLLCMRE_MASK)
10650 #define SCG_SPLLCSR_LK_MASK 0x800000u
10651 #define SCG_SPLLCSR_LK_SHIFT 23u
10652 #define SCG_SPLLCSR_LK_WIDTH 1u
10653 #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_LK_SHIFT))&SCG_SPLLCSR_LK_MASK)
10654 #define SCG_SPLLCSR_SPLLVLD_MASK 0x1000000u
10655 #define SCG_SPLLCSR_SPLLVLD_SHIFT 24u
10656 #define SCG_SPLLCSR_SPLLVLD_WIDTH 1u
10657 #define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLVLD_SHIFT))&SCG_SPLLCSR_SPLLVLD_MASK)
10658 #define SCG_SPLLCSR_SPLLSEL_MASK 0x2000000u
10659 #define SCG_SPLLCSR_SPLLSEL_SHIFT 25u
10660 #define SCG_SPLLCSR_SPLLSEL_WIDTH 1u
10661 #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLSEL_SHIFT))&SCG_SPLLCSR_SPLLSEL_MASK)
10662 #define SCG_SPLLCSR_SPLLERR_MASK 0x4000000u
10663 #define SCG_SPLLCSR_SPLLERR_SHIFT 26u
10664 #define SCG_SPLLCSR_SPLLERR_WIDTH 1u
10665 #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLERR_SHIFT))&SCG_SPLLCSR_SPLLERR_MASK)
10666 /* SPLLDIV Bit Fields */
10667 #define SCG_SPLLDIV_SPLLDIV1_MASK 0x7u
10668 #define SCG_SPLLDIV_SPLLDIV1_SHIFT 0u
10669 #define SCG_SPLLDIV_SPLLDIV1_WIDTH 3u
10670 #define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV1_SHIFT))&SCG_SPLLDIV_SPLLDIV1_MASK)
10671 #define SCG_SPLLDIV_SPLLDIV2_MASK 0x700u
10672 #define SCG_SPLLDIV_SPLLDIV2_SHIFT 8u
10673 #define SCG_SPLLDIV_SPLLDIV2_WIDTH 3u
10674 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV2_SHIFT))&SCG_SPLLDIV_SPLLDIV2_MASK)
10675 /* SPLLCFG Bit Fields */
10676 #define SCG_SPLLCFG_PREDIV_MASK 0x700u
10677 #define SCG_SPLLCFG_PREDIV_SHIFT 8u
10678 #define SCG_SPLLCFG_PREDIV_WIDTH 3u
10679 #define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_PREDIV_SHIFT))&SCG_SPLLCFG_PREDIV_MASK)
10680 #define SCG_SPLLCFG_MULT_MASK 0x1F0000u
10681 #define SCG_SPLLCFG_MULT_SHIFT 16u
10682 #define SCG_SPLLCFG_MULT_WIDTH 5u
10683 #define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_MULT_SHIFT))&SCG_SPLLCFG_MULT_MASK)
10684  /* end of group SCG_Register_Masks */
10688 
10689  /* end of group SCG_Peripheral_Access_Layer */
10693 
10694 
10695 /* ----------------------------------------------------------------------------
10696  -- SIM Peripheral Access Layer
10697  ---------------------------------------------------------------------------- */
10698 
10708 typedef struct {
10709  uint8_t RESERVED_0[4];
10710  __IO uint32_t CHIPCTL;
10711  uint8_t RESERVED_1[4];
10712  __IO uint32_t FTMOPT0;
10713  __IO uint32_t LPOCLKS;
10714  uint8_t RESERVED_2[4];
10715  __IO uint32_t ADCOPT;
10716  __IO uint32_t FTMOPT1;
10717  __IO uint32_t MISCTRL0;
10718  __I uint32_t SDID;
10719  uint8_t RESERVED_3[24];
10720  __IO uint32_t PLATCGC;
10721  uint8_t RESERVED_4[8];
10722  __IO uint32_t FCFG1;
10723  uint8_t RESERVED_5[4];
10724  __I uint32_t UIDH;
10725  __I uint32_t UIDMH;
10726  __I uint32_t UIDML;
10727  __I uint32_t UIDL;
10728  uint8_t RESERVED_6[4];
10729  __IO uint32_t CLKDIV4;
10730  __IO uint32_t MISCTRL1;
10732 
10734 #define SIM_INSTANCE_COUNT (1u)
10735 
10736 
10737 /* SIM - Peripheral instance base addresses */
10739 #define SIM_BASE (0x40048000u)
10740 
10741 #define SIM ((SIM_Type *)SIM_BASE)
10742 
10743 #define SIM_BASE_ADDRS { SIM_BASE }
10744 
10745 #define SIM_BASE_PTRS { SIM }
10746 
10747 /* ----------------------------------------------------------------------------
10748  -- SIM Register Masks
10749  ---------------------------------------------------------------------------- */
10750 
10756 /* CHIPCTL Bit Fields */
10757 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK 0xFu
10758 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT 0u
10759 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH 4u
10760 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT))&SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK)
10761 #define SIM_CHIPCTL_CLKOUTSEL_MASK 0xF0u
10762 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT 4u
10763 #define SIM_CHIPCTL_CLKOUTSEL_WIDTH 4u
10764 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTSEL_SHIFT))&SIM_CHIPCTL_CLKOUTSEL_MASK)
10765 #define SIM_CHIPCTL_CLKOUTDIV_MASK 0x700u
10766 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT 8u
10767 #define SIM_CHIPCTL_CLKOUTDIV_WIDTH 3u
10768 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTDIV_SHIFT))&SIM_CHIPCTL_CLKOUTDIV_MASK)
10769 #define SIM_CHIPCTL_CLKOUTEN_MASK 0x800u
10770 #define SIM_CHIPCTL_CLKOUTEN_SHIFT 11u
10771 #define SIM_CHIPCTL_CLKOUTEN_WIDTH 1u
10772 #define SIM_CHIPCTL_CLKOUTEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTEN_SHIFT))&SIM_CHIPCTL_CLKOUTEN_MASK)
10773 #define SIM_CHIPCTL_TRACECLK_SEL_MASK 0x1000u
10774 #define SIM_CHIPCTL_TRACECLK_SEL_SHIFT 12u
10775 #define SIM_CHIPCTL_TRACECLK_SEL_WIDTH 1u
10776 #define SIM_CHIPCTL_TRACECLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_TRACECLK_SEL_SHIFT))&SIM_CHIPCTL_TRACECLK_SEL_MASK)
10777 #define SIM_CHIPCTL_PDB_BB_SEL_MASK 0x2000u
10778 #define SIM_CHIPCTL_PDB_BB_SEL_SHIFT 13u
10779 #define SIM_CHIPCTL_PDB_BB_SEL_WIDTH 1u
10780 #define SIM_CHIPCTL_PDB_BB_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_PDB_BB_SEL_SHIFT))&SIM_CHIPCTL_PDB_BB_SEL_MASK)
10781 #define SIM_CHIPCTL_ADC_SUPPLY_MASK 0x70000u
10782 #define SIM_CHIPCTL_ADC_SUPPLY_SHIFT 16u
10783 #define SIM_CHIPCTL_ADC_SUPPLY_WIDTH 3u
10784 #define SIM_CHIPCTL_ADC_SUPPLY(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLY_SHIFT))&SIM_CHIPCTL_ADC_SUPPLY_MASK)
10785 #define SIM_CHIPCTL_ADC_SUPPLYEN_MASK 0x80000u
10786 #define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT 19u
10787 #define SIM_CHIPCTL_ADC_SUPPLYEN_WIDTH 1u
10788 #define SIM_CHIPCTL_ADC_SUPPLYEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT))&SIM_CHIPCTL_ADC_SUPPLYEN_MASK)
10789 #define SIM_CHIPCTL_SRAMU_RETEN_MASK 0x100000u
10790 #define SIM_CHIPCTL_SRAMU_RETEN_SHIFT 20u
10791 #define SIM_CHIPCTL_SRAMU_RETEN_WIDTH 1u
10792 #define SIM_CHIPCTL_SRAMU_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAMU_RETEN_SHIFT))&SIM_CHIPCTL_SRAMU_RETEN_MASK)
10793 #define SIM_CHIPCTL_SRAML_RETEN_MASK 0x200000u
10794 #define SIM_CHIPCTL_SRAML_RETEN_SHIFT 21u
10795 #define SIM_CHIPCTL_SRAML_RETEN_WIDTH 1u
10796 #define SIM_CHIPCTL_SRAML_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAML_RETEN_SHIFT))&SIM_CHIPCTL_SRAML_RETEN_MASK)
10797 /* FTMOPT0 Bit Fields */
10798 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK 0x7u
10799 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT 0u
10800 #define SIM_FTMOPT0_FTM0FLTxSEL_WIDTH 3u
10801 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM0FLTxSEL_MASK)
10802 #define SIM_FTMOPT0_FTM1FLTxSEL_MASK 0x70u
10803 #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT 4u
10804 #define SIM_FTMOPT0_FTM1FLTxSEL_WIDTH 3u
10805 #define SIM_FTMOPT0_FTM1FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM1FLTxSEL_MASK)
10806 #define SIM_FTMOPT0_FTM2FLTxSEL_MASK 0x700u
10807 #define SIM_FTMOPT0_FTM2FLTxSEL_SHIFT 8u
10808 #define SIM_FTMOPT0_FTM2FLTxSEL_WIDTH 3u
10809 #define SIM_FTMOPT0_FTM2FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM2FLTxSEL_MASK)
10810 #define SIM_FTMOPT0_FTM3FLTxSEL_MASK 0x7000u
10811 #define SIM_FTMOPT0_FTM3FLTxSEL_SHIFT 12u
10812 #define SIM_FTMOPT0_FTM3FLTxSEL_WIDTH 3u
10813 #define SIM_FTMOPT0_FTM3FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM3FLTxSEL_MASK)
10814 #define SIM_FTMOPT0_FTM0CLKSEL_MASK 0x3000000u
10815 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT 24u
10816 #define SIM_FTMOPT0_FTM0CLKSEL_WIDTH 2u
10817 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0CLKSEL_SHIFT))&SIM_FTMOPT0_FTM0CLKSEL_MASK)
10818 #define SIM_FTMOPT0_FTM1CLKSEL_MASK 0xC000000u
10819 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT 26u
10820 #define SIM_FTMOPT0_FTM1CLKSEL_WIDTH 2u
10821 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1CLKSEL_SHIFT))&SIM_FTMOPT0_FTM1CLKSEL_MASK)
10822 #define SIM_FTMOPT0_FTM2CLKSEL_MASK 0x30000000u
10823 #define SIM_FTMOPT0_FTM2CLKSEL_SHIFT 28u
10824 #define SIM_FTMOPT0_FTM2CLKSEL_WIDTH 2u
10825 #define SIM_FTMOPT0_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2CLKSEL_SHIFT))&SIM_FTMOPT0_FTM2CLKSEL_MASK)
10826 #define SIM_FTMOPT0_FTM3CLKSEL_MASK 0xC0000000u
10827 #define SIM_FTMOPT0_FTM3CLKSEL_SHIFT 30u
10828 #define SIM_FTMOPT0_FTM3CLKSEL_WIDTH 2u
10829 #define SIM_FTMOPT0_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3CLKSEL_SHIFT))&SIM_FTMOPT0_FTM3CLKSEL_MASK)
10830 /* LPOCLKS Bit Fields */
10831 #define SIM_LPOCLKS_LPO1KCLKEN_MASK 0x1u
10832 #define SIM_LPOCLKS_LPO1KCLKEN_SHIFT 0u
10833 #define SIM_LPOCLKS_LPO1KCLKEN_WIDTH 1u
10834 #define SIM_LPOCLKS_LPO1KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO1KCLKEN_SHIFT))&SIM_LPOCLKS_LPO1KCLKEN_MASK)
10835 #define SIM_LPOCLKS_LPO32KCLKEN_MASK 0x2u
10836 #define SIM_LPOCLKS_LPO32KCLKEN_SHIFT 1u
10837 #define SIM_LPOCLKS_LPO32KCLKEN_WIDTH 1u
10838 #define SIM_LPOCLKS_LPO32KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO32KCLKEN_SHIFT))&SIM_LPOCLKS_LPO32KCLKEN_MASK)
10839 #define SIM_LPOCLKS_LPOCLKSEL_MASK 0xCu
10840 #define SIM_LPOCLKS_LPOCLKSEL_SHIFT 2u
10841 #define SIM_LPOCLKS_LPOCLKSEL_WIDTH 2u
10842 #define SIM_LPOCLKS_LPOCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPOCLKSEL_SHIFT))&SIM_LPOCLKS_LPOCLKSEL_MASK)
10843 #define SIM_LPOCLKS_RTCCLKSEL_MASK 0x30u
10844 #define SIM_LPOCLKS_RTCCLKSEL_SHIFT 4u
10845 #define SIM_LPOCLKS_RTCCLKSEL_WIDTH 2u
10846 #define SIM_LPOCLKS_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_RTCCLKSEL_SHIFT))&SIM_LPOCLKS_RTCCLKSEL_MASK)
10847 /* ADCOPT Bit Fields */
10848 #define SIM_ADCOPT_ADC0TRGSEL_MASK 0x1u
10849 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT 0u
10850 #define SIM_ADCOPT_ADC0TRGSEL_WIDTH 1u
10851 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0TRGSEL_SHIFT))&SIM_ADCOPT_ADC0TRGSEL_MASK)
10852 #define SIM_ADCOPT_ADC0SWPRETRG_MASK 0xEu
10853 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT 1u
10854 #define SIM_ADCOPT_ADC0SWPRETRG_WIDTH 3u
10855 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0SWPRETRG_SHIFT))&SIM_ADCOPT_ADC0SWPRETRG_MASK)
10856 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK 0x30u
10857 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT 4u
10858 #define SIM_ADCOPT_ADC0PRETRGSEL_WIDTH 2u
10859 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC0PRETRGSEL_MASK)
10860 #define SIM_ADCOPT_ADC1TRGSEL_MASK 0x100u
10861 #define SIM_ADCOPT_ADC1TRGSEL_SHIFT 8u
10862 #define SIM_ADCOPT_ADC1TRGSEL_WIDTH 1u
10863 #define SIM_ADCOPT_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1TRGSEL_SHIFT))&SIM_ADCOPT_ADC1TRGSEL_MASK)
10864 #define SIM_ADCOPT_ADC1SWPRETRG_MASK 0xE00u
10865 #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT 9u
10866 #define SIM_ADCOPT_ADC1SWPRETRG_WIDTH 3u
10867 #define SIM_ADCOPT_ADC1SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1SWPRETRG_SHIFT))&SIM_ADCOPT_ADC1SWPRETRG_MASK)
10868 #define SIM_ADCOPT_ADC1PRETRGSEL_MASK 0x3000u
10869 #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT 12u
10870 #define SIM_ADCOPT_ADC1PRETRGSEL_WIDTH 2u
10871 #define SIM_ADCOPT_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC1PRETRGSEL_MASK)
10872 /* FTMOPT1 Bit Fields */
10873 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK 0x1u
10874 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT 0u
10875 #define SIM_FTMOPT1_FTM0SYNCBIT_WIDTH 1u
10876 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM0SYNCBIT_MASK)
10877 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK 0x2u
10878 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT 1u
10879 #define SIM_FTMOPT1_FTM1SYNCBIT_WIDTH 1u
10880 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM1SYNCBIT_MASK)
10881 #define SIM_FTMOPT1_FTM2SYNCBIT_MASK 0x4u
10882 #define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT 2u
10883 #define SIM_FTMOPT1_FTM2SYNCBIT_WIDTH 1u
10884 #define SIM_FTMOPT1_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM2SYNCBIT_MASK)
10885 #define SIM_FTMOPT1_FTM3SYNCBIT_MASK 0x8u
10886 #define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT 3u
10887 #define SIM_FTMOPT1_FTM3SYNCBIT_WIDTH 1u
10888 #define SIM_FTMOPT1_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM3SYNCBIT_MASK)
10889 #define SIM_FTMOPT1_FTM1CH0SEL_MASK 0x30u
10890 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT 4u
10891 #define SIM_FTMOPT1_FTM1CH0SEL_WIDTH 2u
10892 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1CH0SEL_SHIFT))&SIM_FTMOPT1_FTM1CH0SEL_MASK)
10893 #define SIM_FTMOPT1_FTM2CH0SEL_MASK 0xC0u
10894 #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT 6u
10895 #define SIM_FTMOPT1_FTM2CH0SEL_WIDTH 2u
10896 #define SIM_FTMOPT1_FTM2CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH0SEL_SHIFT))&SIM_FTMOPT1_FTM2CH0SEL_MASK)
10897 #define SIM_FTMOPT1_FTM2CH1SEL_MASK 0x100u
10898 #define SIM_FTMOPT1_FTM2CH1SEL_SHIFT 8u
10899 #define SIM_FTMOPT1_FTM2CH1SEL_WIDTH 1u
10900 #define SIM_FTMOPT1_FTM2CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH1SEL_SHIFT))&SIM_FTMOPT1_FTM2CH1SEL_MASK)
10901 #define SIM_FTMOPT1_FTMGLDOK_MASK 0x8000u
10902 #define SIM_FTMOPT1_FTMGLDOK_SHIFT 15u
10903 #define SIM_FTMOPT1_FTMGLDOK_WIDTH 1u
10904 #define SIM_FTMOPT1_FTMGLDOK(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTMGLDOK_SHIFT))&SIM_FTMOPT1_FTMGLDOK_MASK)
10905 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK 0xFF0000u
10906 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT 16u
10907 #define SIM_FTMOPT1_FTM0_OUTSEL_WIDTH 8u
10908 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM0_OUTSEL_MASK)
10909 #define SIM_FTMOPT1_FTM3_OUTSEL_MASK 0xFF000000u
10910 #define SIM_FTMOPT1_FTM3_OUTSEL_SHIFT 24u
10911 #define SIM_FTMOPT1_FTM3_OUTSEL_WIDTH 8u
10912 #define SIM_FTMOPT1_FTM3_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM3_OUTSEL_MASK)
10913 /* MISCTRL0 Bit Fields */
10914 #define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK 0x10000u
10915 #define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT 16u
10916 #define SIM_MISCTRL0_FTM0_OBE_CTRL_WIDTH 1u
10917 #define SIM_MISCTRL0_FTM0_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM0_OBE_CTRL_MASK)
10918 #define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK 0x20000u
10919 #define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT 17u
10920 #define SIM_MISCTRL0_FTM1_OBE_CTRL_WIDTH 1u
10921 #define SIM_MISCTRL0_FTM1_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM1_OBE_CTRL_MASK)
10922 #define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK 0x40000u
10923 #define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT 18u
10924 #define SIM_MISCTRL0_FTM2_OBE_CTRL_WIDTH 1u
10925 #define SIM_MISCTRL0_FTM2_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM2_OBE_CTRL_MASK)
10926 #define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK 0x80000u
10927 #define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT 19u
10928 #define SIM_MISCTRL0_FTM3_OBE_CTRL_WIDTH 1u
10929 #define SIM_MISCTRL0_FTM3_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM3_OBE_CTRL_MASK)
10930 /* SDID Bit Fields */
10931 #define SIM_SDID_FEATURES_MASK 0xFFu
10932 #define SIM_SDID_FEATURES_SHIFT 0u
10933 #define SIM_SDID_FEATURES_WIDTH 8u
10934 #define SIM_SDID_FEATURES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FEATURES_SHIFT))&SIM_SDID_FEATURES_MASK)
10935 #define SIM_SDID_PACKAGE_MASK 0xF00u
10936 #define SIM_SDID_PACKAGE_SHIFT 8u
10937 #define SIM_SDID_PACKAGE_WIDTH 4u
10938 #define SIM_SDID_PACKAGE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PACKAGE_SHIFT))&SIM_SDID_PACKAGE_MASK)
10939 #define SIM_SDID_REVID_MASK 0xF000u
10940 #define SIM_SDID_REVID_SHIFT 12u
10941 #define SIM_SDID_REVID_WIDTH 4u
10942 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
10943 #define SIM_SDID_RAMSIZE_MASK 0xF0000u
10944 #define SIM_SDID_RAMSIZE_SHIFT 16u
10945 #define SIM_SDID_RAMSIZE_WIDTH 4u
10946 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_RAMSIZE_SHIFT))&SIM_SDID_RAMSIZE_MASK)
10947 #define SIM_SDID_DERIVATE_MASK 0xF00000u
10948 #define SIM_SDID_DERIVATE_SHIFT 20u
10949 #define SIM_SDID_DERIVATE_WIDTH 4u
10950 #define SIM_SDID_DERIVATE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DERIVATE_SHIFT))&SIM_SDID_DERIVATE_MASK)
10951 #define SIM_SDID_SUBSERIES_MASK 0xF000000u
10952 #define SIM_SDID_SUBSERIES_SHIFT 24u
10953 #define SIM_SDID_SUBSERIES_WIDTH 4u
10954 #define SIM_SDID_SUBSERIES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBSERIES_SHIFT))&SIM_SDID_SUBSERIES_MASK)
10955 #define SIM_SDID_GENERATION_MASK 0xF0000000u
10956 #define SIM_SDID_GENERATION_SHIFT 28u
10957 #define SIM_SDID_GENERATION_WIDTH 4u
10958 #define SIM_SDID_GENERATION(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_GENERATION_SHIFT))&SIM_SDID_GENERATION_MASK)
10959 /* PLATCGC Bit Fields */
10960 #define SIM_PLATCGC_CGCMSCM_MASK 0x1u
10961 #define SIM_PLATCGC_CGCMSCM_SHIFT 0u
10962 #define SIM_PLATCGC_CGCMSCM_WIDTH 1u
10963 #define SIM_PLATCGC_CGCMSCM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMSCM_SHIFT))&SIM_PLATCGC_CGCMSCM_MASK)
10964 #define SIM_PLATCGC_CGCMPU_MASK 0x2u
10965 #define SIM_PLATCGC_CGCMPU_SHIFT 1u
10966 #define SIM_PLATCGC_CGCMPU_WIDTH 1u
10967 #define SIM_PLATCGC_CGCMPU(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMPU_SHIFT))&SIM_PLATCGC_CGCMPU_MASK)
10968 #define SIM_PLATCGC_CGCDMA_MASK 0x4u
10969 #define SIM_PLATCGC_CGCDMA_SHIFT 2u
10970 #define SIM_PLATCGC_CGCDMA_WIDTH 1u
10971 #define SIM_PLATCGC_CGCDMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCDMA_SHIFT))&SIM_PLATCGC_CGCDMA_MASK)
10972 #define SIM_PLATCGC_CGCERM_MASK 0x8u
10973 #define SIM_PLATCGC_CGCERM_SHIFT 3u
10974 #define SIM_PLATCGC_CGCERM_WIDTH 1u
10975 #define SIM_PLATCGC_CGCERM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCERM_SHIFT))&SIM_PLATCGC_CGCERM_MASK)
10976 #define SIM_PLATCGC_CGCEIM_MASK 0x10u
10977 #define SIM_PLATCGC_CGCEIM_SHIFT 4u
10978 #define SIM_PLATCGC_CGCEIM_WIDTH 1u
10979 #define SIM_PLATCGC_CGCEIM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCEIM_SHIFT))&SIM_PLATCGC_CGCEIM_MASK)
10980 /* FCFG1 Bit Fields */
10981 #define SIM_FCFG1_DEPART_MASK 0xF000u
10982 #define SIM_FCFG1_DEPART_SHIFT 12u
10983 #define SIM_FCFG1_DEPART_WIDTH 4u
10984 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
10985 #define SIM_FCFG1_EEERAMSIZE_MASK 0xF0000u
10986 #define SIM_FCFG1_EEERAMSIZE_SHIFT 16u
10987 #define SIM_FCFG1_EEERAMSIZE_WIDTH 4u
10988 #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EEERAMSIZE_SHIFT))&SIM_FCFG1_EEERAMSIZE_MASK)
10989 /* UIDH Bit Fields */
10990 #define SIM_UIDH_UID127_96_MASK 0xFFFFFFFFu
10991 #define SIM_UIDH_UID127_96_SHIFT 0u
10992 #define SIM_UIDH_UID127_96_WIDTH 32u
10993 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID127_96_SHIFT))&SIM_UIDH_UID127_96_MASK)
10994 /* UIDMH Bit Fields */
10995 #define SIM_UIDMH_UID95_64_MASK 0xFFFFFFFFu
10996 #define SIM_UIDMH_UID95_64_SHIFT 0u
10997 #define SIM_UIDMH_UID95_64_WIDTH 32u
10998 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID95_64_SHIFT))&SIM_UIDMH_UID95_64_MASK)
10999 /* UIDML Bit Fields */
11000 #define SIM_UIDML_UID63_32_MASK 0xFFFFFFFFu
11001 #define SIM_UIDML_UID63_32_SHIFT 0u
11002 #define SIM_UIDML_UID63_32_WIDTH 32u
11003 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID63_32_SHIFT))&SIM_UIDML_UID63_32_MASK)
11004 /* UIDL Bit Fields */
11005 #define SIM_UIDL_UID31_0_MASK 0xFFFFFFFFu
11006 #define SIM_UIDL_UID31_0_SHIFT 0u
11007 #define SIM_UIDL_UID31_0_WIDTH 32u
11008 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID31_0_SHIFT))&SIM_UIDL_UID31_0_MASK)
11009 /* CLKDIV4 Bit Fields */
11010 #define SIM_CLKDIV4_TRACEFRAC_MASK 0x1u
11011 #define SIM_CLKDIV4_TRACEFRAC_SHIFT 0u
11012 #define SIM_CLKDIV4_TRACEFRAC_WIDTH 1u
11013 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEFRAC_SHIFT))&SIM_CLKDIV4_TRACEFRAC_MASK)
11014 #define SIM_CLKDIV4_TRACEDIV_MASK 0xEu
11015 #define SIM_CLKDIV4_TRACEDIV_SHIFT 1u
11016 #define SIM_CLKDIV4_TRACEDIV_WIDTH 3u
11017 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIV_SHIFT))&SIM_CLKDIV4_TRACEDIV_MASK)
11018 #define SIM_CLKDIV4_TRACEDIVEN_MASK 0x10000000u
11019 #define SIM_CLKDIV4_TRACEDIVEN_SHIFT 28u
11020 #define SIM_CLKDIV4_TRACEDIVEN_WIDTH 1u
11021 #define SIM_CLKDIV4_TRACEDIVEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIVEN_SHIFT))&SIM_CLKDIV4_TRACEDIVEN_MASK)
11022 /* MISCTRL1 Bit Fields */
11023 #define SIM_MISCTRL1_SW_TRG_MASK 0x1u
11024 #define SIM_MISCTRL1_SW_TRG_SHIFT 0u
11025 #define SIM_MISCTRL1_SW_TRG_WIDTH 1u
11026 #define SIM_MISCTRL1_SW_TRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL1_SW_TRG_SHIFT))&SIM_MISCTRL1_SW_TRG_MASK)
11027  /* end of group SIM_Register_Masks */
11031 
11032  /* end of group SIM_Peripheral_Access_Layer */
11036 
11037 
11038 /* ----------------------------------------------------------------------------
11039  -- SMC Peripheral Access Layer
11040  ---------------------------------------------------------------------------- */
11041 
11051 typedef struct {
11052  __I uint32_t VERID;
11053  __I uint32_t PARAM;
11054  __IO uint32_t PMPROT;
11055  __IO uint32_t PMCTRL;
11056  __IO uint32_t STOPCTRL;
11057  __I uint32_t PMSTAT;
11059 
11061 #define SMC_INSTANCE_COUNT (1u)
11062 
11063 
11064 /* SMC - Peripheral instance base addresses */
11066 #define SMC_BASE (0x4007E000u)
11067 
11068 #define SMC ((SMC_Type *)SMC_BASE)
11069 
11070 #define SMC_BASE_ADDRS { SMC_BASE }
11071 
11072 #define SMC_BASE_PTRS { SMC }
11073 
11074 /* ----------------------------------------------------------------------------
11075  -- SMC Register Masks
11076  ---------------------------------------------------------------------------- */
11077 
11083 /* VERID Bit Fields */
11084 #define SMC_VERID_FEATURE_MASK 0xFFFFu
11085 #define SMC_VERID_FEATURE_SHIFT 0u
11086 #define SMC_VERID_FEATURE_WIDTH 16u
11087 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_FEATURE_SHIFT))&SMC_VERID_FEATURE_MASK)
11088 #define SMC_VERID_MINOR_MASK 0xFF0000u
11089 #define SMC_VERID_MINOR_SHIFT 16u
11090 #define SMC_VERID_MINOR_WIDTH 8u
11091 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MINOR_SHIFT))&SMC_VERID_MINOR_MASK)
11092 #define SMC_VERID_MAJOR_MASK 0xFF000000u
11093 #define SMC_VERID_MAJOR_SHIFT 24u
11094 #define SMC_VERID_MAJOR_WIDTH 8u
11095 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MAJOR_SHIFT))&SMC_VERID_MAJOR_MASK)
11096 /* PARAM Bit Fields */
11097 #define SMC_PARAM_EHSRUN_MASK 0x1u
11098 #define SMC_PARAM_EHSRUN_SHIFT 0u
11099 #define SMC_PARAM_EHSRUN_WIDTH 1u
11100 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EHSRUN_SHIFT))&SMC_PARAM_EHSRUN_MASK)
11101 #define SMC_PARAM_ELLS_MASK 0x8u
11102 #define SMC_PARAM_ELLS_SHIFT 3u
11103 #define SMC_PARAM_ELLS_WIDTH 1u
11104 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS_SHIFT))&SMC_PARAM_ELLS_MASK)
11105 #define SMC_PARAM_ELLS2_MASK 0x20u
11106 #define SMC_PARAM_ELLS2_SHIFT 5u
11107 #define SMC_PARAM_ELLS2_WIDTH 1u
11108 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS2_SHIFT))&SMC_PARAM_ELLS2_MASK)
11109 #define SMC_PARAM_EVLLS0_MASK 0x40u
11110 #define SMC_PARAM_EVLLS0_SHIFT 6u
11111 #define SMC_PARAM_EVLLS0_WIDTH 1u
11112 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EVLLS0_SHIFT))&SMC_PARAM_EVLLS0_MASK)
11113 /* PMPROT Bit Fields */
11114 #define SMC_PMPROT_AVLP_MASK 0x20u
11115 #define SMC_PMPROT_AVLP_SHIFT 5u
11116 #define SMC_PMPROT_AVLP_WIDTH 1u
11117 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
11118 #define SMC_PMPROT_AHSRUN_MASK 0x80u
11119 #define SMC_PMPROT_AHSRUN_SHIFT 7u
11120 #define SMC_PMPROT_AHSRUN_WIDTH 1u
11121 #define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
11122 /* PMCTRL Bit Fields */
11123 #define SMC_PMCTRL_STOPM_MASK 0x7u
11124 #define SMC_PMCTRL_STOPM_SHIFT 0u
11125 #define SMC_PMCTRL_STOPM_WIDTH 3u
11126 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
11127 #define SMC_PMCTRL_VLPSA_MASK 0x8u
11128 #define SMC_PMCTRL_VLPSA_SHIFT 3u
11129 #define SMC_PMCTRL_VLPSA_WIDTH 1u
11130 #define SMC_PMCTRL_VLPSA(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_VLPSA_SHIFT))&SMC_PMCTRL_VLPSA_MASK)
11131 #define SMC_PMCTRL_RUNM_MASK 0x60u
11132 #define SMC_PMCTRL_RUNM_SHIFT 5u
11133 #define SMC_PMCTRL_RUNM_WIDTH 2u
11134 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
11135 /* STOPCTRL Bit Fields */
11136 #define SMC_STOPCTRL_STOPO_MASK 0xC0u
11137 #define SMC_STOPCTRL_STOPO_SHIFT 6u
11138 #define SMC_STOPCTRL_STOPO_WIDTH 2u
11139 #define SMC_STOPCTRL_STOPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_STOPO_SHIFT))&SMC_STOPCTRL_STOPO_MASK)
11140 /* PMSTAT Bit Fields */
11141 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
11142 #define SMC_PMSTAT_PMSTAT_SHIFT 0u
11143 #define SMC_PMSTAT_PMSTAT_WIDTH 8u
11144 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
11145  /* end of group SMC_Register_Masks */
11149 
11150  /* end of group SMC_Peripheral_Access_Layer */
11154 
11155 
11156 /* ----------------------------------------------------------------------------
11157  -- TRGMUX Peripheral Access Layer
11158  ---------------------------------------------------------------------------- */
11159 
11167 #define TRGMUX_TRGMUXn_COUNT 26u
11168 
11170 typedef struct {
11171  __IO uint32_t TRGMUXn[TRGMUX_TRGMUXn_COUNT];
11173 
11175 #define TRGMUX_INSTANCE_COUNT (1u)
11176 
11177 
11178 /* TRGMUX - Peripheral instance base addresses */
11180 #define TRGMUX_BASE (0x40063000u)
11181 
11182 #define TRGMUX ((TRGMUX_Type *)TRGMUX_BASE)
11183 
11184 #define TRGMUX_BASE_ADDRS { TRGMUX_BASE }
11185 
11186 #define TRGMUX_BASE_PTRS { TRGMUX }
11187 
11188 /* TRGMUX index offsets */
11189 #define TRGMUX_DMAMUX0_INDEX 0
11190 #define TRGMUX_EXTOUT0_INDEX 1
11191 #define TRGMUX_EXTOUT1_INDEX 2
11192 #define TRGMUX_ADC0_INDEX 3
11193 #define TRGMUX_ADC1_INDEX 4
11194 #define TRGMUX_CMP0_INDEX 7
11195 #define TRGMUX_FTM0_INDEX 10
11196 #define TRGMUX_FTM1_INDEX 11
11197 #define TRGMUX_FTM2_INDEX 12
11198 #define TRGMUX_FTM3_INDEX 13
11199 #define TRGMUX_PDB0_INDEX 14
11200 #define TRGMUX_PDB1_INDEX 15
11201 #define TRGMUX_FLEXIO_INDEX 17
11202 #define TRGMUX_LPIT0_INDEX 18
11203 #define TRGMUX_LPUART0_INDEX 19
11204 #define TRGMUX_LPUART1_INDEX 20
11205 #define TRGMUX_LPI2C0_INDEX 21
11206 #define TRGMUX_LPSPI0_INDEX 23
11207 #define TRGMUX_LPSPI1_INDEX 24
11208 #define TRGMUX_LPTMR0_INDEX 25
11209 
11210 /* ----------------------------------------------------------------------------
11211  -- TRGMUX Register Masks
11212  ---------------------------------------------------------------------------- */
11213 
11219 /* TRGMUXn Bit Fields */
11220 #define TRGMUX_TRGMUXn_SEL0_MASK 0x3Fu
11221 #define TRGMUX_TRGMUXn_SEL0_SHIFT 0u
11222 #define TRGMUX_TRGMUXn_SEL0_WIDTH 6u
11223 #define TRGMUX_TRGMUXn_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL0_SHIFT))&TRGMUX_TRGMUXn_SEL0_MASK)
11224 #define TRGMUX_TRGMUXn_SEL1_MASK 0x3F00u
11225 #define TRGMUX_TRGMUXn_SEL1_SHIFT 8u
11226 #define TRGMUX_TRGMUXn_SEL1_WIDTH 6u
11227 #define TRGMUX_TRGMUXn_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL1_SHIFT))&TRGMUX_TRGMUXn_SEL1_MASK)
11228 #define TRGMUX_TRGMUXn_SEL2_MASK 0x3F0000u
11229 #define TRGMUX_TRGMUXn_SEL2_SHIFT 16u
11230 #define TRGMUX_TRGMUXn_SEL2_WIDTH 6u
11231 #define TRGMUX_TRGMUXn_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL2_SHIFT))&TRGMUX_TRGMUXn_SEL2_MASK)
11232 #define TRGMUX_TRGMUXn_SEL3_MASK 0x3F000000u
11233 #define TRGMUX_TRGMUXn_SEL3_SHIFT 24u
11234 #define TRGMUX_TRGMUXn_SEL3_WIDTH 6u
11235 #define TRGMUX_TRGMUXn_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL3_SHIFT))&TRGMUX_TRGMUXn_SEL3_MASK)
11236 #define TRGMUX_TRGMUXn_LK_MASK 0x80000000u
11237 #define TRGMUX_TRGMUXn_LK_SHIFT 31u
11238 #define TRGMUX_TRGMUXn_LK_WIDTH 1u
11239 #define TRGMUX_TRGMUXn_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_LK_SHIFT))&TRGMUX_TRGMUXn_LK_MASK)
11240  /* end of group TRGMUX_Register_Masks */
11244 
11245  /* end of group TRGMUX_Peripheral_Access_Layer */
11249 
11250 
11251 /* ----------------------------------------------------------------------------
11252  -- WDOG Peripheral Access Layer
11253  ---------------------------------------------------------------------------- */
11254 
11264 typedef struct {
11265  __IO uint32_t CS;
11266  __IO uint32_t CNT;
11267  __IO uint32_t TOVAL;
11268  __IO uint32_t WIN;
11270 
11272 #define WDOG_INSTANCE_COUNT (1u)
11273 
11274 
11275 /* WDOG - Peripheral instance base addresses */
11277 #define WDOG_BASE (0x40052000u)
11278 
11279 #define WDOG ((WDOG_Type *)WDOG_BASE)
11280 
11281 #define WDOG_BASE_ADDRS { WDOG_BASE }
11282 
11283 #define WDOG_BASE_PTRS { WDOG }
11284 
11285 #define WDOG_IRQS_ARR_COUNT (1u)
11286 
11287 #define WDOG_IRQS_CH_COUNT (1u)
11288 
11289 #define WDOG_IRQS { WDOG_EWM_IRQn }
11290 
11291 /* ----------------------------------------------------------------------------
11292  -- WDOG Register Masks
11293  ---------------------------------------------------------------------------- */
11294 
11300 /* CS Bit Fields */
11301 #define WDOG_CS_STOP_MASK 0x1u
11302 #define WDOG_CS_STOP_SHIFT 0u
11303 #define WDOG_CS_STOP_WIDTH 1u
11304 #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_STOP_SHIFT))&WDOG_CS_STOP_MASK)
11305 #define WDOG_CS_WAIT_MASK 0x2u
11306 #define WDOG_CS_WAIT_SHIFT 1u
11307 #define WDOG_CS_WAIT_WIDTH 1u
11308 #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WAIT_SHIFT))&WDOG_CS_WAIT_MASK)
11309 #define WDOG_CS_DBG_MASK 0x4u
11310 #define WDOG_CS_DBG_SHIFT 2u
11311 #define WDOG_CS_DBG_WIDTH 1u
11312 #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DBG_SHIFT))&WDOG_CS_DBG_MASK)
11313 #define WDOG_CS_TST_MASK 0x18u
11314 #define WDOG_CS_TST_SHIFT 3u
11315 #define WDOG_CS_TST_WIDTH 2u
11316 #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_TST_SHIFT))&WDOG_CS_TST_MASK)
11317 #define WDOG_CS_UPDATE_MASK 0x20u
11318 #define WDOG_CS_UPDATE_SHIFT 5u
11319 #define WDOG_CS_UPDATE_WIDTH 1u
11320 #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_UPDATE_SHIFT))&WDOG_CS_UPDATE_MASK)
11321 #define WDOG_CS_INT_MASK 0x40u
11322 #define WDOG_CS_INT_SHIFT 6u
11323 #define WDOG_CS_INT_WIDTH 1u
11324 #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_INT_SHIFT))&WDOG_CS_INT_MASK)
11325 #define WDOG_CS_EN_MASK 0x80u
11326 #define WDOG_CS_EN_SHIFT 7u
11327 #define WDOG_CS_EN_WIDTH 1u
11328 #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_EN_SHIFT))&WDOG_CS_EN_MASK)
11329 #define WDOG_CS_CLK_MASK 0x300u
11330 #define WDOG_CS_CLK_SHIFT 8u
11331 #define WDOG_CS_CLK_WIDTH 2u
11332 #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CLK_SHIFT))&WDOG_CS_CLK_MASK)
11333 #define WDOG_CS_RCS_MASK 0x400u
11334 #define WDOG_CS_RCS_SHIFT 10u
11335 #define WDOG_CS_RCS_WIDTH 1u
11336 #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_RCS_SHIFT))&WDOG_CS_RCS_MASK)
11337 #define WDOG_CS_ULK_MASK 0x800u
11338 #define WDOG_CS_ULK_SHIFT 11u
11339 #define WDOG_CS_ULK_WIDTH 1u
11340 #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_ULK_SHIFT))&WDOG_CS_ULK_MASK)
11341 #define WDOG_CS_PRES_MASK 0x1000u
11342 #define WDOG_CS_PRES_SHIFT 12u
11343 #define WDOG_CS_PRES_WIDTH 1u
11344 #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_PRES_SHIFT))&WDOG_CS_PRES_MASK)
11345 #define WDOG_CS_CMD32EN_MASK 0x2000u
11346 #define WDOG_CS_CMD32EN_SHIFT 13u
11347 #define WDOG_CS_CMD32EN_WIDTH 1u
11348 #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CMD32EN_SHIFT))&WDOG_CS_CMD32EN_MASK)
11349 #define WDOG_CS_FLG_MASK 0x4000u
11350 #define WDOG_CS_FLG_SHIFT 14u
11351 #define WDOG_CS_FLG_WIDTH 1u
11352 #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_FLG_SHIFT))&WDOG_CS_FLG_MASK)
11353 #define WDOG_CS_WIN_MASK 0x8000u
11354 #define WDOG_CS_WIN_SHIFT 15u
11355 #define WDOG_CS_WIN_WIDTH 1u
11356 #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WIN_SHIFT))&WDOG_CS_WIN_MASK)
11357 /* CNT Bit Fields */
11358 #define WDOG_CNT_CNTLOW_MASK 0xFFu
11359 #define WDOG_CNT_CNTLOW_SHIFT 0u
11360 #define WDOG_CNT_CNTLOW_WIDTH 8u
11361 #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTLOW_SHIFT))&WDOG_CNT_CNTLOW_MASK)
11362 #define WDOG_CNT_CNTHIGH_MASK 0xFF00u
11363 #define WDOG_CNT_CNTHIGH_SHIFT 8u
11364 #define WDOG_CNT_CNTHIGH_WIDTH 8u
11365 #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTHIGH_SHIFT))&WDOG_CNT_CNTHIGH_MASK)
11366 /* TOVAL Bit Fields */
11367 #define WDOG_TOVAL_TOVALLOW_MASK 0xFFu
11368 #define WDOG_TOVAL_TOVALLOW_SHIFT 0u
11369 #define WDOG_TOVAL_TOVALLOW_WIDTH 8u
11370 #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALLOW_SHIFT))&WDOG_TOVAL_TOVALLOW_MASK)
11371 #define WDOG_TOVAL_TOVALHIGH_MASK 0xFF00u
11372 #define WDOG_TOVAL_TOVALHIGH_SHIFT 8u
11373 #define WDOG_TOVAL_TOVALHIGH_WIDTH 8u
11374 #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALHIGH_SHIFT))&WDOG_TOVAL_TOVALHIGH_MASK)
11375 /* WIN Bit Fields */
11376 #define WDOG_WIN_WINLOW_MASK 0xFFu
11377 #define WDOG_WIN_WINLOW_SHIFT 0u
11378 #define WDOG_WIN_WINLOW_WIDTH 8u
11379 #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINLOW_SHIFT))&WDOG_WIN_WINLOW_MASK)
11380 #define WDOG_WIN_WINHIGH_MASK 0xFF00u
11381 #define WDOG_WIN_WINHIGH_SHIFT 8u
11382 #define WDOG_WIN_WINHIGH_WIDTH 8u
11383 #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINHIGH_SHIFT))&WDOG_WIN_WINHIGH_MASK)
11384  /* end of group WDOG_Register_Masks */
11388 
11389  /* end of group WDOG_Peripheral_Access_Layer */
11393 
11394  /* end of group Peripheral_access_layer_S32K144 */
11398 
11399 
11400 /* ----------------------------------------------------------------------------
11401  -- Backward Compatibility for S32K144
11402  ---------------------------------------------------------------------------- */
11403 
11409 /* No backward compatibility issues. */
11410  /* end of group Backward_Compatibility_Symbols_S32K144 */
11414 
11415 
11416 #else /* #if !defined(S32K144_H_) */
11417  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
11418  #if (MCU_MEM_MAP_VERSION != 0x0200u)
11419  #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
11420  #warning There are included two not compatible versions of memory maps. Please check possible differences.
11421  #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
11422  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
11423 #endif /* #if !defined(S32K144_H_) */
11424 
11425 /* S32K144.h, eof. */
__IO uint32_t CnSC
Definition: S32K144.h:3989
__IO uint32_t SYNCONF
Definition: S32K144.h:4008
__O uint32_t GPCHR
Definition: S32K144.h:8554
__IO uint32_t MCFGR2
Definition: S32K144.h:5340
__IO uint32_t FILTER
Definition: S32K144.h:4003
__I uint32_t PARAM
Definition: S32K144.h:3476
__IO uint32_t WORD1
Definition: S32K144.h:3183
__IO uint32_t MISCTRL0
Definition: S32K144.h:10717
__IO uint32_t SETTEN
Definition: S32K144.h:5956
__I uint32_t FDCRC
Definition: S32K144.h:984
__I uint32_t EAR
Definition: S32K144.h:3266
__IO uint16_t ELINKYES
Definition: S32K144.h:2288
__IO uint32_t XOFS
Definition: S32K144.h:422
__IO uint32_t DFCR
Definition: S32K144.h:8559
__IO uint16_t H
Definition: S32K144.h:2012
#define __IO
Definition: S32K144.h:211
__IO uint32_t LPOCLKS
Definition: S32K144.h:10713
__I uint32_t CP0COUNT
Definition: S32K144.h:7849
__IO uint32_t CNT
Definition: S32K144.h:11266
struct RTC_Type * RTC_MemMapPtr
__I uint32_t PMSTAT
Definition: S32K144.h:11057
__IO uint32_t BAUD
Definition: S32K144.h:6674
__IO uint32_t TAR
Definition: S32K144.h:8987
struct PORT_Type * PORT_MemMapPtr
__IO uint32_t EIMCR
Definition: S32K144.h:3178
__I uint32_t SDID
Definition: S32K144.h:10718
struct DMAMUX_Type * DMAMUX_MemMapPtr
__IO uint32_t PIDR
Definition: S32K144.h:5020
#define FTM_CONTROLS_COUNT
Definition: S32K144.h:3981
__IO uint32_t FTMOPT1
Definition: S32K144.h:10716
__O uint32_t PTOR
Definition: S32K144.h:5017
__IO uint32_t IER
Definition: S32K144.h:8992
__I uint32_t PARAM
Definition: S32K144.h:11053
__I uint32_t RSR
Definition: S32K144.h:6191
__I uint32_t CPxCFG0
Definition: S32K144.h:7842
#define FLEXIO_TIMCFG_COUNT
Definition: S32K144.h:3470
__IO uint32_t SHIFTSTAT
Definition: S32K144.h:3479
__IO uint32_t CFG1
Definition: S32K144.h:413
__I uint32_t CNT
Definition: S32K144.h:8243
__IO uint32_t MODIR
Definition: S32K144.h:6679
__IO uint32_t USR_OFS
Definition: S32K144.h:421
__IO uint32_t CLPS
Definition: S32K144.h:426
struct LPUART_Type * LPUART_MemMapPtr
__IO uint32_t PINCFG
Definition: S32K144.h:6673
__IO uint32_t CnV
Definition: S32K144.h:3990
__IO uint32_t SHPR1
Definition: S32K144.h:9771
__IO uint32_t LMDR2
Definition: S32K144.h:7210
__IO uint32_t SADDR
Definition: S32K144.h:2275
__IO uint32_t ISCR
Definition: S32K144.h:7203
__I uint32_t VERID
Definition: S32K144.h:5951
__IO uint32_t CPO
Definition: S32K144.h:7207
#define EIM_EICHDn_COUNT
Definition: S32K144.h:3174
__O uint8_t SSRT
Definition: S32K144.h:2260
__IO uint32_t MOD
Definition: S32K144.h:8242
__I uint32_t CP0CFG2
Definition: S32K144.h:7852
__IO uint32_t COMBINE
Definition: S32K144.h:3998
__IO uint8_t FERSTAT
Definition: S32K144.h:3788
__IO uint32_t PL2_PLMASK_LO
Definition: S32K144.h:972
__I uint32_t PARAM
Definition: S32K144.h:8705
__IO uint32_t AFSR
Definition: S32K144.h:9780
__I uint32_t EAR
Definition: S32K144.h:7541
#define S32_NVIC_ICER_COUNT
Definition: S32K144.h:9162
#define FLEXIO_SHIFTCFG_COUNT
Definition: S32K144.h:3464
#define PORT_PCR_COUNT
Definition: S32K144.h:8548
__IO uint32_t PMCTRL
Definition: S32K144.h:11055
__O uint8_t CEEI
Definition: S32K144.h:2255
__IO uint32_t RXMGMASK
Definition: S32K144.h:943
__I uint32_t HRS
Definition: S32K144.h:2268
__IO uint32_t PCCRMR
Definition: S32K144.h:5127
struct TRGMUX_Type * TRGMUX_MemMapPtr
__IO uint32_t SRIE
Definition: S32K144.h:8710
__IO uint32_t SCR
Definition: S32K144.h:5355
__IO uint32_t CFGR0
Definition: S32K144.h:6178
__IO uint32_t PWMLOAD
Definition: S32K144.h:4011
__IO uint32_t CLP2_OFS
Definition: S32K144.h:435
__IO uint32_t DFER
Definition: S32K144.h:8558
__IO uint32_t CFSR
Definition: S32K144.h:9775
__IO uint32_t MCR
Definition: S32K144.h:5334
__IO uint32_t WU_MTC
Definition: S32K144.h:966
__IO uint32_t MCFGR3
Definition: S32K144.h:5341
__IO uint32_t TPR
Definition: S32K144.h:8986
__IO uint32_t CTRL
Definition: S32K144.h:3477
#define S32_NVIC_ISER_COUNT
Definition: S32K144.h:9161
__IO uint8_t FERCNFG
Definition: S32K144.h:3789
__IO uint32_t MOD
Definition: S32K144.h:3987
struct CAN_Type * CAN_MemMapPtr
struct DMA_Type * DMA_MemMapPtr
__IO uint32_t MFCR
Definition: S32K144.h:5349
__IO uint16_t ATTR
Definition: S32K144.h:2277
__IO uint32_t FLT_ID2_IDMASK
Definition: S32K144.h:971
__I uint32_t SASR
Definition: S32K144.h:5365
__IO uint32_t MDER
Definition: S32K144.h:5337
__I uint32_t CP0CFG0
Definition: S32K144.h:7850
__IO uint32_t SIER
Definition: S32K144.h:5357
__I uint32_t CP0CFG1
Definition: S32K144.h:7851
__IO uint16_t CSR
Definition: S32K144.h:2291
struct LPTMR_Type * LPTMR_MemMapPtr
struct ADC_Type * ADC_MemMapPtr
__IO uint32_t RX14MASK
Definition: S32K144.h:944
__IO uint32_t SSRS
Definition: S32K144.h:8709
__IO uint32_t FPDSCR
Definition: S32K144.h:9786
__IO uint32_t FIRCCFG
Definition: S32K144.h:10385
__IO uint32_t FCFG1
Definition: S32K144.h:10722
#define FTFC_FPROT_COUNT
Definition: S32K144.h:3772
struct LMEM_Type * LMEM_MemMapPtr
__IO uint32_t FDCTRL
Definition: S32K144.h:982
__I uint32_t PIN
Definition: S32K144.h:3478
__IO uint8_t DATA_8LL
Definition: S32K144.h:2154
__IO uint32_t FLTCTRL
Definition: S32K144.h:4004
__I uint16_t PLASC
Definition: S32K144.h:7200
struct FTM_Type * FTM_MemMapPtr
__IO uint32_t PCCSAR
Definition: S32K144.h:5124
__IO uint32_t CS
Definition: S32K144.h:11265
__IO uint32_t MPRA
Definition: S32K144.h:710
__I uint32_t LMFDLR
Definition: S32K144.h:7220
__IO uint32_t SHCSR
Definition: S32K144.h:9774
__I uint32_t PARAM
Definition: S32K144.h:6172
__IO uint32_t MIER
Definition: S32K144.h:5336
__IO uint32_t C1
Definition: S32K144.h:8246
__IO uint32_t RCCR
Definition: S32K144.h:10370
struct LPSPI_Type * LPSPI_MemMapPtr
#define PDB_POnDLY_COUNT
Definition: S32K144.h:8237
__IO uint32_t BFAR
Definition: S32K144.h:9779
__IO uint32_t CR
Definition: S32K144.h:6174
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K144.h:271
__IO uint32_t CR
Definition: S32K144.h:8989
__I uint32_t CSR
Definition: S32K144.h:10369
__IO uint32_t CTRL1
Definition: S32K144.h:940
__IO uint32_t CLP9
Definition: S32K144.h:432
#define FLEXIO_SHIFTBUFBYS_COUNT
Definition: S32K144.h:3467
__IO uint32_t LMPEIR
Definition: S32K144.h:7214
__IO uint32_t TVAL
Definition: S32K144.h:5960
__O uint8_t CERR
Definition: S32K144.h:2261
__I uint32_t VERID
Definition: S32K144.h:11052
struct SIM_Type * SIM_MemMapPtr
__IO uint32_t SLAST
Definition: S32K144.h:2283
__O uint8_t SEEI
Definition: S32K144.h:2256
__I uint16_t PLAMC
Definition: S32K144.h:7201
__IO uint32_t C1
Definition: S32K144.h:1759
__IO uint32_t CLP0_OFS
Definition: S32K144.h:437
__IO uint32_t CLPS_OFS
Definition: S32K144.h:433
#define FLEXIO_SHIFTBUFBIS_COUNT
Definition: S32K144.h:3466
__IO uint32_t SC3
Definition: S32K144.h:418
struct EIM_Type * EIM_MemMapPtr
struct PMC_Type * PMC_MemMapPtr
__IO uint32_t SIRCCSR
Definition: S32K144.h:10379
__IO uint32_t BASE_OFS
Definition: S32K144.h:419
__IO uint32_t CR
Definition: S32K144.h:2249
__IO uint32_t CCR
Definition: S32K144.h:9770
__IO uint32_t G
Definition: S32K144.h:424
__IO uint32_t POEN
Definition: S32K144.h:8251
__IO uint32_t IFLAG1
Definition: S32K144.h:951
#define S32_NVIC_IP_COUNT
Definition: S32K144.h:9166
__IO uint32_t HCR
Definition: S32K144.h:4012
__IO uint16_t ELINKNO
Definition: S32K144.h:2287
__IO uint32_t RPC
Definition: S32K144.h:8707
__IO uint32_t MCCR0
Definition: S32K144.h:5345
#define ADC_R_COUNT
Definition: S32K144.h:407
__IO uint8_t DATA_8HU
Definition: S32K144.h:2157
__IO uint32_t MCR
Definition: S32K144.h:939
#define ERM_EARn_COUNT
Definition: S32K144.h:3257
__I uint32_t CPxMASTER
Definition: S32K144.h:7840
__IO uint32_t WORD0
Definition: S32K144.h:7550
__IO uint32_t PCCCVR
Definition: S32K144.h:5125
__IO uint32_t CSR
Definition: S32K144.h:6554
__I uint32_t MFSR
Definition: S32K144.h:5350
__IO uint32_t CLP1_OFS
Definition: S32K144.h:436
#define MSCM_OCMDR_COUNT
Definition: S32K144.h:7834
__IO uint32_t SIRCDIV
Definition: S32K144.h:10380
struct WDOG_Type * WDOG_MemMapPtr
__IO uint32_t CPCR
Definition: S32K144.h:7202
__IO uint32_t DMR0
Definition: S32K144.h:6181
__IO uint32_t CFG2
Definition: S32K144.h:414
__I uint32_t CVAL
Definition: S32K144.h:5961
struct MPU_Type * MPU_MemMapPtr
__I uint8_t FCSESTAT
Definition: S32K144.h:3786
__IO uint32_t CR0
Definition: S32K144.h:3261
#define LPIT_TMR_COUNT
Definition: S32K144.h:5947
__I uint32_t CPxCFG2
Definition: S32K144.h:7844
__I uint32_t LMFAR
Definition: S32K144.h:7216
__IO uint32_t LR
Definition: S32K144.h:8991
__IO uint32_t CCR
Definition: S32K144.h:6184
__IO uint32_t PAIR1DEADTIME
Definition: S32K144.h:4015
#define DMA_TCD_COUNT
Definition: S32K144.h:2245
__I uint32_t WMBn_CS
Definition: S32K144.h:976
__IO uint32_t DATA_32
Definition: S32K144.h:2152
__IO uint32_t VCCR
Definition: S32K144.h:10371
__IO uint32_t FIRCCSR
Definition: S32K144.h:10383
__I uint32_t UIDL
Definition: S32K144.h:10727
__IO uint32_t LMPECR
Definition: S32K144.h:7212
__IO uint32_t ISFR
Definition: S32K144.h:8556
__IO uint32_t OFS
Definition: S32K144.h:420
__I uint32_t VERID
Definition: S32K144.h:8704
__IO uint8_t FDPROT
Definition: S32K144.h:3784
__IO uint32_t ICSR
Definition: S32K144.h:9766
__IO uint32_t SWOCTRL
Definition: S32K144.h:4010
__IO uint32_t MODE
Definition: S32K144.h:3994
__IO uint32_t SDER
Definition: S32K144.h:5358
__IO uint32_t PMPROT
Definition: S32K144.h:11054
__IO uint32_t CBT
Definition: S32K144.h:958
__IO uint32_t PODLY
Definition: S32K144.h:8253
__IO uint32_t SHPR3
Definition: S32K144.h:9773
__I uint32_t CPUID
Definition: S32K144.h:9765
struct MSCM_Type * MSCM_MemMapPtr
__I uint32_t WMBn_D03
Definition: S32K144.h:978
#define S32_NVIC_ISPR_COUNT
Definition: S32K144.h:9163
__IO uint32_t EXTTRIG
Definition: S32K144.h:4000
struct PDB_Type * PDB_MemMapPtr
__IO uint32_t CLP3
Definition: S32K144.h:427
__I uint32_t CPxCFG3
Definition: S32K144.h:7845
__IO uint32_t CNTIN
Definition: S32K144.h:3992
__IO uint32_t STATUS
Definition: S32K144.h:3993
__I uint32_t ES
Definition: S32K144.h:2250
__IO uint32_t CTRL2
Definition: S32K144.h:952
__IO uint32_t CLP0
Definition: S32K144.h:430
#define TRGMUX_TRGMUXn_COUNT
Definition: S32K144.h:11167
__IO uint8_t HL
Definition: S32K144.h:2017
__O uint32_t STIR
Definition: S32K144.h:9182
#define CAN_WMB_COUNT
Definition: S32K144.h:935
__IO uint32_t CNR
Definition: S32K144.h:6557
__IO uint8_t FSTAT
Definition: S32K144.h:3776
__IO uint32_t FLTPOL
Definition: S32K144.h:4007
__IO uint32_t SR
Definition: S32K144.h:8990
__IO uint32_t DFWR
Definition: S32K144.h:8560
__IO uint32_t STAR
Definition: S32K144.h:5366
__IO uint32_t INVCTRL
Definition: S32K144.h:4009
__IO uint32_t STAT
Definition: S32K144.h:6675
__IO uint32_t CLP2
Definition: S32K144.h:428
__IO uint32_t EEI
Definition: S32K144.h:2254
__I uint32_t LMFATR
Definition: S32K144.h:7217
__IO uint32_t MISCTRL1
Definition: S32K144.h:10730
__IO uint32_t TSR
Definition: S32K144.h:8985
__IO uint32_t FLT_DLC
Definition: S32K144.h:968
__IO uint16_t L
Definition: S32K144.h:2011
__IO uint32_t SAMR
Definition: S32K144.h:5363
__IO uint32_t MDMR
Definition: S32K144.h:5343
__IO uint32_t CLP9_OFS
Definition: S32K144.h:439
__IO uint32_t CSR
Definition: S32K144.h:10266
__IO uint32_t CTRL1_PN
Definition: S32K144.h:964
__IO uint32_t PDOR
Definition: S32K144.h:5014
__IO uint32_t WORD1
Definition: S32K144.h:7551
#define CAN_RAMn_COUNT
Definition: S32K144.h:933
__IO uint32_t SIRCCFG
Definition: S32K144.h:10381
__IO uint32_t CONF
Definition: S32K144.h:4006
#define FTFC_FCCOB_COUNT
Definition: S32K144.h:3771
struct CRC_Type * CRC_MemMapPtr
__IO uint32_t ERQ
Definition: S32K144.h:2252
#define AIPS_PACR_COUNT
Definition: S32K144.h:705
__IO uint8_t HU
Definition: S32K144.h:2018
__I uint32_t EDR
Definition: S32K144.h:7544
__IO uint32_t IER
Definition: S32K144.h:6176
__IO uint32_t MIER
Definition: S32K144.h:5955
__IO uint32_t MCFGR1
Definition: S32K144.h:5339
__IO uint16_t SOFF
Definition: S32K144.h:2276
__IO uint32_t CHIPCTL
Definition: S32K144.h:10710
__IO uint32_t PL1_HI
Definition: S32K144.h:970
__IO uint32_t TIMER
Definition: S32K144.h:941
__IO uint32_t HCCR
Definition: S32K144.h:10372
__IO uint32_t AIRCR
Definition: S32K144.h:9768
#define MPU_RGDAAC_COUNT
Definition: S32K144.h:7534
__IO uint32_t PCCLCR
Definition: S32K144.h:5123
__IO uint32_t FPCCR
Definition: S32K144.h:9784
struct GPIO_Type * GPIO_MemMapPtr
__IO uint16_t DLY1
Definition: S32K144.h:8256
struct S32_NVIC_Type * S32_NVIC_MemMapPtr
__IO uint32_t SSR
Definition: S32K144.h:5356
#define PCC_PCCn_COUNT
Definition: S32K144.h:8128
struct SCG_Type * SCG_MemMapPtr
__IO uint8_t CLKPRESCALER
Definition: S32K144.h:3372
__IO uint8_t FCNFG
Definition: S32K144.h:3777
__O uint8_t CDNE
Definition: S32K144.h:2259
__I uint32_t CP0MASTER
Definition: S32K144.h:7848
__IO uint32_t TCR
Definition: S32K144.h:6188
__IO uint32_t CLP1
Definition: S32K144.h:429
__I uint32_t UIDMH
Definition: S32K144.h:10725
struct ERM_Type * ERM_MemMapPtr
__IO uint32_t ERR
Definition: S32K144.h:2266
struct CMP_Type * CMP_MemMapPtr
__IO uint32_t DATA
Definition: S32K144.h:6677
__IO uint32_t UG
Definition: S32K144.h:425
__IO uint32_t TOVAL
Definition: S32K144.h:11267
__O uint32_t PSOR
Definition: S32K144.h:5015
__IO uint32_t ACTLR
Definition: S32K144.h:9763
__IO uint32_t SPLLDIV
Definition: S32K144.h:10388
__IO uint32_t CTRL
Definition: S32K144.h:6676
__IO uint32_t SOSCCSR
Definition: S32K144.h:10375
__IO uint32_t DADDR
Definition: S32K144.h:2284
__IO uint32_t FPCAR
Definition: S32K144.h:9785
__IO uint32_t CTRL
Definition: S32K144.h:2022
__IO uint32_t FLT_ID1
Definition: S32K144.h:967
#define MPU_RGD_COUNT
Definition: S32K144.h:7533
#define S32_NVIC_ICPR_COUNT
Definition: S32K144.h:9164
__IO uint32_t DMR1
Definition: S32K144.h:6182
__O uint8_t SERQ
Definition: S32K144.h:2258
__IO uint32_t SHIFTEIEN
Definition: S32K144.h:3484
__IO uint32_t MCR
Definition: S32K144.h:5953
__IO uint32_t PSR
Definition: S32K144.h:6555
#define DMAMUX_CHCFG_COUNT
Definition: S32K144.h:3109
#define FLEXIO_SHIFTBUF_COUNT
Definition: S32K144.h:3465
__I uint32_t PARAM
Definition: S32K144.h:6671
__IO uint16_t DLY2
Definition: S32K144.h:8255
__IO uint32_t PAIR3DEADTIME
Definition: S32K144.h:4019
__IO uint8_t REGSC
Definition: S32K144.h:8436
__O uint8_t CERQ
Definition: S32K144.h:2257
__IO uint32_t CLPX_OFS
Definition: S32K144.h:438
__IO uint32_t HFSR
Definition: S32K144.h:9776
__IO uint32_t SCFGR2
Definition: S32K144.h:5361
__IO uint8_t LU
Definition: S32K144.h:2016
__IO uint32_t EICHEN
Definition: S32K144.h:3179
__IO uint32_t CLKOUTCNFG
Definition: S32K144.h:10373
__IO uint32_t SC2
Definition: S32K144.h:417
__IO uint32_t SR
Definition: S32K144.h:6175
__O uint8_t CINT
Definition: S32K144.h:2262
struct LPIT_Type * LPIT_MemMapPtr
__I uint8_t FOPT
Definition: S32K144.h:3779
__IO uint32_t DFSR
Definition: S32K144.h:9777
__I uint32_t SRS
Definition: S32K144.h:8706
__IO uint32_t PID
Definition: S32K144.h:7205
__I uint32_t VERID
Definition: S32K144.h:10366
__IO uint32_t CLKDIV4
Definition: S32K144.h:10729
__IO uint32_t SHPR2
Definition: S32K144.h:9772
__IO uint32_t MCCR1
Definition: S32K144.h:5347
struct MCM_Type * MCM_MemMapPtr
__IO uint16_t DOFF
Definition: S32K144.h:2285
__I uint8_t FSEC
Definition: S32K144.h:3778
__IO uint32_t CLP3_OFS
Definition: S32K144.h:434
__IO uint32_t SPLLCFG
Definition: S32K144.h:10389
__IO uint32_t CLRTEN
Definition: S32K144.h:5957
__I uint32_t CPxCOUNT
Definition: S32K144.h:7841
__IO uint32_t CLPX
Definition: S32K144.h:431
__I uint32_t MRDR
Definition: S32K144.h:5353
__I uint32_t CPxCFG1
Definition: S32K144.h:7843
__IO uint32_t CTRL2_PN
Definition: S32K144.h:965
__IO uint8_t DATA_8HL
Definition: S32K144.h:2156
__I uint32_t VERID
Definition: S32K144.h:5331
__IO uint32_t INT
Definition: S32K144.h:2264
__IO uint32_t FCR
Definition: S32K144.h:6186
__IO uint32_t EARS
Definition: S32K144.h:2270
__IO uint32_t CPACR
Definition: S32K144.h:9782
__IO uint32_t FIRCDIV
Definition: S32K144.h:10384
__IO uint32_t MCFGR0
Definition: S32K144.h:5338
__IO uint32_t SYNC
Definition: S32K144.h:3995
#define FLEXIO_SHIFTBUFBBS_COUNT
Definition: S32K144.h:3468
__IO uint32_t FDCBT
Definition: S32K144.h:983
struct EWM_Type * EWM_MemMapPtr
__I uint32_t WMBn_D47
Definition: S32K144.h:979
__IO uint8_t LVDSC1
Definition: S32K144.h:8434
#define FLEXIO_TIMCTL_COUNT
Definition: S32K144.h:3469
__IO uint32_t MTDR
Definition: S32K144.h:5351
struct SMC_Type * SMC_MemMapPtr
__O uint32_t GPCLR
Definition: S32K144.h:8553
__IO uint32_t PLATCGC
Definition: S32K144.h:10720
#define FLEXIO_SHIFTCTL_COUNT
Definition: S32K144.h:3463
__I uint32_t PARAM
Definition: S32K144.h:5332
__IO uint32_t DATA
Definition: S32K144.h:2009
__IO uint32_t CMR
Definition: S32K144.h:6556
struct LPI2C_Type * LPI2C_MemMapPtr
__IO uint32_t MSR
Definition: S32K144.h:5954
__IO uint32_t IMASK1
Definition: S32K144.h:949
__IO uint32_t SHIFTSIEN
Definition: S32K144.h:3483
__I uint32_t CP0NUM
Definition: S32K144.h:7847
__I uint32_t PARAM
Definition: S32K144.h:10367
__IO uint32_t FMS
Definition: S32K144.h:4002
#define CAN_RXIMR_COUNT
Definition: S32K144.h:934
__IO uint32_t FIFO
Definition: S32K144.h:6680
__IO uint32_t DEADTIME
Definition: S32K144.h:3999
#define MPU_EAR_EDR_COUNT
Definition: S32K144.h:7532
#define __I
Definition: S32K144.h:208
__IO uint32_t SC
Definition: S32K144.h:8241
__I uint32_t CALIB
Definition: S32K144.h:10269
struct AIPS_Type * AIPS_MemMapPtr
__IO uint32_t CNT
Definition: S32K144.h:3986
__IO uint32_t RX15MASK
Definition: S32K144.h:945
__IO uint32_t OUTINIT
Definition: S32K144.h:3996
__IO uint32_t DER
Definition: S32K144.h:6177
__IO uint32_t TCR
Definition: S32K144.h:8988
__IO uint8_t DATA_8LU
Definition: S32K144.h:2155
#define AIPS_OPACR_COUNT
Definition: S32K144.h:706
__IO uint32_t MLOFFNO
Definition: S32K144.h:2280
__IO uint32_t WORD2
Definition: S32K144.h:7552
__I uint32_t VERID
Definition: S32K144.h:6670
__IO uint32_t RVR
Definition: S32K144.h:10267
__IO uint32_t RXFGMASK
Definition: S32K144.h:956
__IO uint8_t CMPL
Definition: S32K144.h:3369
__I uint32_t UIDH
Definition: S32K144.h:10724
__I uint32_t CP0CFG3
Definition: S32K144.h:7853
__O uint32_t TDR
Definition: S32K144.h:6189
#define MCM_LMDR_COUNT
Definition: S32K144.h:7195
__IO uint32_t SPLLCSR
Definition: S32K144.h:10387
struct RCM_Type * RCM_MemMapPtr
__IO uint32_t GPOLY
Definition: S32K144.h:2021
__I uint32_t LMFDHR
Definition: S32K144.h:7219
__IO uint32_t CESR
Definition: S32K144.h:7538
__I uint32_t CPxNUM
Definition: S32K144.h:7839
__IO uint32_t SOSCDIV
Definition: S32K144.h:10376
__IO uint32_t GLOBAL
Definition: S32K144.h:6672
__IO uint32_t SHIFTERR
Definition: S32K144.h:3480
__I uint32_t CP0TYPE
Definition: S32K144.h:7846
struct S32_SCB_Type * S32_SCB_MemMapPtr
__I uint32_t CPxTYPE
Definition: S32K144.h:7838
__IO uint32_t OUTMASK
Definition: S32K144.h:3997
__IO uint8_t CMPH
Definition: S32K144.h:3370
__I uint32_t PDIR
Definition: S32K144.h:5018
__IO uint32_t MATCH
Definition: S32K144.h:6678
__IO uint32_t C0
Definition: S32K144.h:1758
__O uint8_t SERV
Definition: S32K144.h:3368
struct FLEXIO_Type * FLEXIO_MemMapPtr
__IO uint32_t WATER
Definition: S32K144.h:6681
__IO uint8_t FEPROT
Definition: S32K144.h:3783
__IO uint32_t QDCTRL
Definition: S32K144.h:4005
__IO uint32_t YOFS
Definition: S32K144.h:423
struct CSE_PRAM_Type * CSE_PRAM_MemMapPtr
#define DMA_DCHPRI_COUNT
Definition: S32K144.h:2244
__IO uint8_t LL
Definition: S32K144.h:2015
__I uint32_t ESR2
Definition: S32K144.h:953
__IO uint32_t MMFAR
Definition: S32K144.h:9778
__IO uint32_t S
Definition: S32K144.h:8247
#define ADC_CV_COUNT
Definition: S32K144.h:408
__IO uint32_t MLOFFYES
Definition: S32K144.h:2281
__IO uint32_t C2
Definition: S32K144.h:1760
__IO uint32_t TIMIEN
Definition: S32K144.h:3485
__IO uint32_t ADCOPT
Definition: S32K144.h:10715
__I uint32_t PARAM
Definition: S32K144.h:5952
__I uint32_t RDR
Definition: S32K144.h:6192
__I uint32_t UIDML
Definition: S32K144.h:10726
#define __O
Definition: S32K144.h:210
__O uint32_t PCOR
Definition: S32K144.h:5016
__I uint32_t CRCR
Definition: S32K144.h:955
__IO uint32_t STOPCTRL
Definition: S32K144.h:11056
__IO uint32_t STDR
Definition: S32K144.h:5368
__I uint32_t SRDR
Definition: S32K144.h:5370
__IO uint32_t SCFGR1
Definition: S32K144.h:5360
#define S32_NVIC_IABR_COUNT
Definition: S32K144.h:9165
__IO uint32_t MSR
Definition: S32K144.h:5335
__IO uint32_t SC
Definition: S32K144.h:3985
__I uint32_t FSR
Definition: S32K144.h:6187
__IO uint32_t TIMSTAT
Definition: S32K144.h:3481
__I uint32_t WMBn_ID
Definition: S32K144.h:977
__I uint32_t VERID
Definition: S32K144.h:3475
__IO uint32_t SHIFTSDEN
Definition: S32K144.h:3487
__IO uint32_t MLNO
Definition: S32K144.h:2279
struct FTFC_Type * FTFC_MemMapPtr
__IO uint32_t SR0
Definition: S32K144.h:3263
__IO uint32_t CVR
Definition: S32K144.h:10268
__IO uint32_t PAIR0DEADTIME
Definition: S32K144.h:4013
__IO uint32_t VTOR
Definition: S32K144.h:9767
__IO uint32_t SCR
Definition: S32K144.h:9769
#define ADC_SC1_COUNT
Definition: S32K144.h:406
__IO uint32_t WIN
Definition: S32K144.h:11268
__I uint32_t VERID
Definition: S32K144.h:6171
struct S32_SysTick_Type * S32_SysTick_MemMapPtr
#define PDB_DLY_COUNT
Definition: S32K144.h:8236
__IO uint32_t PDDR
Definition: S32K144.h:5019
struct PCC_Type * PCC_MemMapPtr
#define CSE_PRAM_RAMn_COUNT
Definition: S32K144.h:2147
__IO uint32_t PL2_PLMASK_HI
Definition: S32K144.h:973
__IO uint32_t IDLY
Definition: S32K144.h:8244
__IO uint32_t CFGR1
Definition: S32K144.h:6179
__IO uint32_t WORD3
Definition: S32K144.h:7553
__IO uint32_t SOSCCFG
Definition: S32K144.h:10377
__IO uint32_t ECR
Definition: S32K144.h:946
#define FLEXIO_TIMCMP_COUNT
Definition: S32K144.h:3471
__IO uint32_t POL
Definition: S32K144.h:4001
__IO uint32_t PCCCR
Definition: S32K144.h:5122
__IO uint8_t LPOTRIM
Definition: S32K144.h:8438
__IO uint32_t FTMOPT0
Definition: S32K144.h:10712
__IO uint8_t LVDSC2
Definition: S32K144.h:8435
__IO uint32_t DLASTSGA
Definition: S32K144.h:2290
__I uint32_t RXFIR
Definition: S32K144.h:957
__IO uint8_t CTRL
Definition: S32K144.h:3367
#define PDB_CH_COUNT
Definition: S32K144.h:8235
__IO uint32_t TCTRL
Definition: S32K144.h:5962
__IO uint32_t PAIR2DEADTIME
Definition: S32K144.h:4017
__IO uint32_t WORD0
Definition: S32K144.h:3182
__IO uint32_t ESR1
Definition: S32K144.h:947
__IO uint32_t PL1_LO
Definition: S32K144.h:969