97 #if !defined(S32K148_H_)
102 #if (defined(MCU_ACTIVE))
103 #error S32K148 memory map: There is already included another memory map. Only one memory map can be included.
111 #define MCU_MEM_MAP_VERSION 0x0200u
113 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
129 #define __I volatile const
132 #define __IO volatile
139 #if !defined(REG_READ32)
140 #define REG_READ32(address) (*(volatile uint32_t*)(address))
146 #if !defined(REG_WRITE32)
147 #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value))
153 #if !defined(REG_BIT_SET32)
154 #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask))
160 #if !defined(REG_BIT_CLEAR32)
161 #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask))))
168 #if !defined(REG_RMW32)
169 #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value)))))
183 #define NUMBER_OF_INT_VECTORS 163u
366 #define ADC_SC1_COUNT 16u
367 #define ADC_R_COUNT 16u
368 #define ADC_CV_COUNT 2u
369 #define ADC_aSC1_COUNT 32u
370 #define ADC_aR_COUNT 32u
402 uint8_t RESERVED_0[28];
408 #define ADC_INSTANCE_COUNT (2u)
413 #define ADC0_BASE (0x4003B000u)
415 #define ADC0 ((ADC_Type *)ADC0_BASE)
417 #define ADC1_BASE (0x40027000u)
419 #define ADC1 ((ADC_Type *)ADC1_BASE)
421 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
423 #define ADC_BASE_PTRS { ADC0, ADC1 }
425 #define ADC_IRQS_ARR_COUNT (1u)
427 #define ADC_IRQS_CH_COUNT (1u)
429 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
441 #define ADC_SC1_ADCH_MASK 0x3Fu
442 #define ADC_SC1_ADCH_SHIFT 0u
443 #define ADC_SC1_ADCH_WIDTH 6u
444 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
445 #define ADC_SC1_AIEN_MASK 0x40u
446 #define ADC_SC1_AIEN_SHIFT 6u
447 #define ADC_SC1_AIEN_WIDTH 1u
448 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
449 #define ADC_SC1_COCO_MASK 0x80u
450 #define ADC_SC1_COCO_SHIFT 7u
451 #define ADC_SC1_COCO_WIDTH 1u
452 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
454 #define ADC_CFG1_ADICLK_MASK 0x3u
455 #define ADC_CFG1_ADICLK_SHIFT 0u
456 #define ADC_CFG1_ADICLK_WIDTH 2u
457 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
458 #define ADC_CFG1_MODE_MASK 0xCu
459 #define ADC_CFG1_MODE_SHIFT 2u
460 #define ADC_CFG1_MODE_WIDTH 2u
461 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
462 #define ADC_CFG1_ADIV_MASK 0x60u
463 #define ADC_CFG1_ADIV_SHIFT 5u
464 #define ADC_CFG1_ADIV_WIDTH 2u
465 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
466 #define ADC_CFG1_CLRLTRG_MASK 0x100u
467 #define ADC_CFG1_CLRLTRG_SHIFT 8u
468 #define ADC_CFG1_CLRLTRG_WIDTH 1u
469 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_CLRLTRG_SHIFT))&ADC_CFG1_CLRLTRG_MASK)
471 #define ADC_CFG2_SMPLTS_MASK 0xFFu
472 #define ADC_CFG2_SMPLTS_SHIFT 0u
473 #define ADC_CFG2_SMPLTS_WIDTH 8u
474 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_SMPLTS_SHIFT))&ADC_CFG2_SMPLTS_MASK)
476 #define ADC_R_D_MASK 0xFFFu
477 #define ADC_R_D_SHIFT 0u
478 #define ADC_R_D_WIDTH 12u
479 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
481 #define ADC_CV_CV_MASK 0xFFFFu
482 #define ADC_CV_CV_SHIFT 0u
483 #define ADC_CV_CV_WIDTH 16u
484 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
486 #define ADC_SC2_REFSEL_MASK 0x3u
487 #define ADC_SC2_REFSEL_SHIFT 0u
488 #define ADC_SC2_REFSEL_WIDTH 2u
489 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
490 #define ADC_SC2_DMAEN_MASK 0x4u
491 #define ADC_SC2_DMAEN_SHIFT 2u
492 #define ADC_SC2_DMAEN_WIDTH 1u
493 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
494 #define ADC_SC2_ACREN_MASK 0x8u
495 #define ADC_SC2_ACREN_SHIFT 3u
496 #define ADC_SC2_ACREN_WIDTH 1u
497 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
498 #define ADC_SC2_ACFGT_MASK 0x10u
499 #define ADC_SC2_ACFGT_SHIFT 4u
500 #define ADC_SC2_ACFGT_WIDTH 1u
501 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
502 #define ADC_SC2_ACFE_MASK 0x20u
503 #define ADC_SC2_ACFE_SHIFT 5u
504 #define ADC_SC2_ACFE_WIDTH 1u
505 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
506 #define ADC_SC2_ADTRG_MASK 0x40u
507 #define ADC_SC2_ADTRG_SHIFT 6u
508 #define ADC_SC2_ADTRG_WIDTH 1u
509 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
510 #define ADC_SC2_ADACT_MASK 0x80u
511 #define ADC_SC2_ADACT_SHIFT 7u
512 #define ADC_SC2_ADACT_WIDTH 1u
513 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
514 #define ADC_SC2_TRGPRNUM_MASK 0x6000u
515 #define ADC_SC2_TRGPRNUM_SHIFT 13u
516 #define ADC_SC2_TRGPRNUM_WIDTH 2u
517 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGPRNUM_SHIFT))&ADC_SC2_TRGPRNUM_MASK)
518 #define ADC_SC2_TRGSTLAT_MASK 0xF0000u
519 #define ADC_SC2_TRGSTLAT_SHIFT 16u
520 #define ADC_SC2_TRGSTLAT_WIDTH 4u
521 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTLAT_SHIFT))&ADC_SC2_TRGSTLAT_MASK)
522 #define ADC_SC2_TRGSTERR_MASK 0xF000000u
523 #define ADC_SC2_TRGSTERR_SHIFT 24u
524 #define ADC_SC2_TRGSTERR_WIDTH 4u
525 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTERR_SHIFT))&ADC_SC2_TRGSTERR_MASK)
527 #define ADC_SC3_AVGS_MASK 0x3u
528 #define ADC_SC3_AVGS_SHIFT 0u
529 #define ADC_SC3_AVGS_WIDTH 2u
530 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
531 #define ADC_SC3_AVGE_MASK 0x4u
532 #define ADC_SC3_AVGE_SHIFT 2u
533 #define ADC_SC3_AVGE_WIDTH 1u
534 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
535 #define ADC_SC3_ADCO_MASK 0x8u
536 #define ADC_SC3_ADCO_SHIFT 3u
537 #define ADC_SC3_ADCO_WIDTH 1u
538 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
539 #define ADC_SC3_CAL_MASK 0x80u
540 #define ADC_SC3_CAL_SHIFT 7u
541 #define ADC_SC3_CAL_WIDTH 1u
542 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
544 #define ADC_BASE_OFS_BA_OFS_MASK 0xFFu
545 #define ADC_BASE_OFS_BA_OFS_SHIFT 0u
546 #define ADC_BASE_OFS_BA_OFS_WIDTH 8u
547 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_BASE_OFS_BA_OFS_SHIFT))&ADC_BASE_OFS_BA_OFS_MASK)
549 #define ADC_OFS_OFS_MASK 0xFFFFu
550 #define ADC_OFS_OFS_SHIFT 0u
551 #define ADC_OFS_OFS_WIDTH 16u
552 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
554 #define ADC_USR_OFS_USR_OFS_MASK 0xFFu
555 #define ADC_USR_OFS_USR_OFS_SHIFT 0u
556 #define ADC_USR_OFS_USR_OFS_WIDTH 8u
557 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_USR_OFS_USR_OFS_SHIFT))&ADC_USR_OFS_USR_OFS_MASK)
559 #define ADC_XOFS_XOFS_MASK 0x3Fu
560 #define ADC_XOFS_XOFS_SHIFT 0u
561 #define ADC_XOFS_XOFS_WIDTH 6u
562 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_XOFS_XOFS_SHIFT))&ADC_XOFS_XOFS_MASK)
564 #define ADC_YOFS_YOFS_MASK 0xFFu
565 #define ADC_YOFS_YOFS_SHIFT 0u
566 #define ADC_YOFS_YOFS_WIDTH 8u
567 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_YOFS_YOFS_SHIFT))&ADC_YOFS_YOFS_MASK)
569 #define ADC_G_G_MASK 0x7FFu
570 #define ADC_G_G_SHIFT 0u
571 #define ADC_G_G_WIDTH 11u
572 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x))<<ADC_G_G_SHIFT))&ADC_G_G_MASK)
574 #define ADC_UG_UG_MASK 0x3FFu
575 #define ADC_UG_UG_SHIFT 0u
576 #define ADC_UG_UG_WIDTH 10u
577 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x))<<ADC_UG_UG_SHIFT))&ADC_UG_UG_MASK)
579 #define ADC_CLPS_CLPS_MASK 0x7Fu
580 #define ADC_CLPS_CLPS_SHIFT 0u
581 #define ADC_CLPS_CLPS_WIDTH 7u
582 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
584 #define ADC_CLP3_CLP3_MASK 0x3FFu
585 #define ADC_CLP3_CLP3_SHIFT 0u
586 #define ADC_CLP3_CLP3_WIDTH 10u
587 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
589 #define ADC_CLP2_CLP2_MASK 0x3FFu
590 #define ADC_CLP2_CLP2_SHIFT 0u
591 #define ADC_CLP2_CLP2_WIDTH 10u
592 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
594 #define ADC_CLP1_CLP1_MASK 0x1FFu
595 #define ADC_CLP1_CLP1_SHIFT 0u
596 #define ADC_CLP1_CLP1_WIDTH 9u
597 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
599 #define ADC_CLP0_CLP0_MASK 0xFFu
600 #define ADC_CLP0_CLP0_SHIFT 0u
601 #define ADC_CLP0_CLP0_WIDTH 8u
602 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
604 #define ADC_CLPX_CLPX_MASK 0x7Fu
605 #define ADC_CLPX_CLPX_SHIFT 0u
606 #define ADC_CLPX_CLPX_WIDTH 7u
607 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_CLPX_SHIFT))&ADC_CLPX_CLPX_MASK)
609 #define ADC_CLP9_CLP9_MASK 0x7Fu
610 #define ADC_CLP9_CLP9_SHIFT 0u
611 #define ADC_CLP9_CLP9_WIDTH 7u
612 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_CLP9_SHIFT))&ADC_CLP9_CLP9_MASK)
614 #define ADC_CLPS_OFS_CLPS_OFS_MASK 0xFu
615 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT 0u
616 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH 4u
617 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_OFS_CLPS_OFS_SHIFT))&ADC_CLPS_OFS_CLPS_OFS_MASK)
619 #define ADC_CLP3_OFS_CLP3_OFS_MASK 0xFu
620 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT 0u
621 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH 4u
622 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_OFS_CLP3_OFS_SHIFT))&ADC_CLP3_OFS_CLP3_OFS_MASK)
624 #define ADC_CLP2_OFS_CLP2_OFS_MASK 0xFu
625 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT 0u
626 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH 4u
627 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_OFS_CLP2_OFS_SHIFT))&ADC_CLP2_OFS_CLP2_OFS_MASK)
629 #define ADC_CLP1_OFS_CLP1_OFS_MASK 0xFu
630 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT 0u
631 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH 4u
632 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_OFS_CLP1_OFS_SHIFT))&ADC_CLP1_OFS_CLP1_OFS_MASK)
634 #define ADC_CLP0_OFS_CLP0_OFS_MASK 0xFu
635 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT 0u
636 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH 4u
637 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_OFS_CLP0_OFS_SHIFT))&ADC_CLP0_OFS_CLP0_OFS_MASK)
639 #define ADC_CLPX_OFS_CLPX_OFS_MASK 0xFFFu
640 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT 0u
641 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH 12u
642 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_OFS_CLPX_OFS_SHIFT))&ADC_CLPX_OFS_CLPX_OFS_MASK)
644 #define ADC_CLP9_OFS_CLP9_OFS_MASK 0xFFFu
645 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT 0u
646 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH 12u
647 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_OFS_CLP9_OFS_SHIFT))&ADC_CLP9_OFS_CLP9_OFS_MASK)
649 #define ADC_aSC1_ADCH_MASK 0x3Fu
650 #define ADC_aSC1_ADCH_SHIFT 0u
651 #define ADC_aSC1_ADCH_WIDTH 6u
652 #define ADC_aSC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_aSC1_ADCH_SHIFT))&ADC_aSC1_ADCH_MASK)
653 #define ADC_aSC1_AIEN_MASK 0x40u
654 #define ADC_aSC1_AIEN_SHIFT 6u
655 #define ADC_aSC1_AIEN_WIDTH 1u
656 #define ADC_aSC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_aSC1_AIEN_SHIFT))&ADC_aSC1_AIEN_MASK)
657 #define ADC_aSC1_COCO_MASK 0x80u
658 #define ADC_aSC1_COCO_SHIFT 7u
659 #define ADC_aSC1_COCO_WIDTH 1u
660 #define ADC_aSC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_aSC1_COCO_SHIFT))&ADC_aSC1_COCO_MASK)
662 #define ADC_aR_D_MASK 0xFFFu
663 #define ADC_aR_D_SHIFT 0u
664 #define ADC_aR_D_WIDTH 12u
665 #define ADC_aR_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_aR_D_SHIFT))&ADC_aR_D_MASK)
688 #define AIPS_PACR_COUNT 4u
689 #define AIPS_OPACR_COUNT 12u
694 uint8_t RESERVED_0[28];
696 uint8_t RESERVED_1[16];
701 #define AIPS_INSTANCE_COUNT (1u)
706 #define AIPS_BASE (0x40000000u)
708 #define AIPS ((AIPS_Type *)AIPS_BASE)
710 #define AIPS_BASE_ADDRS { AIPS_BASE }
712 #define AIPS_BASE_PTRS { AIPS }
724 #define AIPS_MPRA_MPL2_MASK 0x100000u
725 #define AIPS_MPRA_MPL2_SHIFT 20u
726 #define AIPS_MPRA_MPL2_WIDTH 1u
727 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
728 #define AIPS_MPRA_MTW2_MASK 0x200000u
729 #define AIPS_MPRA_MTW2_SHIFT 21u
730 #define AIPS_MPRA_MTW2_WIDTH 1u
731 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
732 #define AIPS_MPRA_MTR2_MASK 0x400000u
733 #define AIPS_MPRA_MTR2_SHIFT 22u
734 #define AIPS_MPRA_MTR2_WIDTH 1u
735 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
736 #define AIPS_MPRA_MPL1_MASK 0x1000000u
737 #define AIPS_MPRA_MPL1_SHIFT 24u
738 #define AIPS_MPRA_MPL1_WIDTH 1u
739 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
740 #define AIPS_MPRA_MTW1_MASK 0x2000000u
741 #define AIPS_MPRA_MTW1_SHIFT 25u
742 #define AIPS_MPRA_MTW1_WIDTH 1u
743 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
744 #define AIPS_MPRA_MTR1_MASK 0x4000000u
745 #define AIPS_MPRA_MTR1_SHIFT 26u
746 #define AIPS_MPRA_MTR1_WIDTH 1u
747 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
748 #define AIPS_MPRA_MPL0_MASK 0x10000000u
749 #define AIPS_MPRA_MPL0_SHIFT 28u
750 #define AIPS_MPRA_MPL0_WIDTH 1u
751 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
752 #define AIPS_MPRA_MTW0_MASK 0x20000000u
753 #define AIPS_MPRA_MTW0_SHIFT 29u
754 #define AIPS_MPRA_MTW0_WIDTH 1u
755 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
756 #define AIPS_MPRA_MTR0_MASK 0x40000000u
757 #define AIPS_MPRA_MTR0_SHIFT 30u
758 #define AIPS_MPRA_MTR0_WIDTH 1u
759 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
761 #define AIPS_PACR_TP5_MASK 0x100u
762 #define AIPS_PACR_TP5_SHIFT 8u
763 #define AIPS_PACR_TP5_WIDTH 1u
764 #define AIPS_PACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP5_SHIFT))&AIPS_PACR_TP5_MASK)
765 #define AIPS_PACR_WP5_MASK 0x200u
766 #define AIPS_PACR_WP5_SHIFT 9u
767 #define AIPS_PACR_WP5_WIDTH 1u
768 #define AIPS_PACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP5_SHIFT))&AIPS_PACR_WP5_MASK)
769 #define AIPS_PACR_SP5_MASK 0x400u
770 #define AIPS_PACR_SP5_SHIFT 10u
771 #define AIPS_PACR_SP5_WIDTH 1u
772 #define AIPS_PACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP5_SHIFT))&AIPS_PACR_SP5_MASK)
773 #define AIPS_PACR_TP1_MASK 0x1000000u
774 #define AIPS_PACR_TP1_SHIFT 24u
775 #define AIPS_PACR_TP1_WIDTH 1u
776 #define AIPS_PACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP1_SHIFT))&AIPS_PACR_TP1_MASK)
777 #define AIPS_PACR_WP1_MASK 0x2000000u
778 #define AIPS_PACR_WP1_SHIFT 25u
779 #define AIPS_PACR_WP1_WIDTH 1u
780 #define AIPS_PACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP1_SHIFT))&AIPS_PACR_WP1_MASK)
781 #define AIPS_PACR_SP1_MASK 0x4000000u
782 #define AIPS_PACR_SP1_SHIFT 26u
783 #define AIPS_PACR_SP1_WIDTH 1u
784 #define AIPS_PACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP1_SHIFT))&AIPS_PACR_SP1_MASK)
785 #define AIPS_PACR_TP0_MASK 0x10000000u
786 #define AIPS_PACR_TP0_SHIFT 28u
787 #define AIPS_PACR_TP0_WIDTH 1u
788 #define AIPS_PACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP0_SHIFT))&AIPS_PACR_TP0_MASK)
789 #define AIPS_PACR_WP0_MASK 0x20000000u
790 #define AIPS_PACR_WP0_SHIFT 29u
791 #define AIPS_PACR_WP0_WIDTH 1u
792 #define AIPS_PACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP0_SHIFT))&AIPS_PACR_WP0_MASK)
793 #define AIPS_PACR_SP0_MASK 0x40000000u
794 #define AIPS_PACR_SP0_SHIFT 30u
795 #define AIPS_PACR_SP0_WIDTH 1u
796 #define AIPS_PACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP0_SHIFT))&AIPS_PACR_SP0_MASK)
798 #define AIPS_OPACR_TP7_MASK 0x1u
799 #define AIPS_OPACR_TP7_SHIFT 0u
800 #define AIPS_OPACR_TP7_WIDTH 1u
801 #define AIPS_OPACR_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP7_SHIFT))&AIPS_OPACR_TP7_MASK)
802 #define AIPS_OPACR_WP7_MASK 0x2u
803 #define AIPS_OPACR_WP7_SHIFT 1u
804 #define AIPS_OPACR_WP7_WIDTH 1u
805 #define AIPS_OPACR_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP7_SHIFT))&AIPS_OPACR_WP7_MASK)
806 #define AIPS_OPACR_SP7_MASK 0x4u
807 #define AIPS_OPACR_SP7_SHIFT 2u
808 #define AIPS_OPACR_SP7_WIDTH 1u
809 #define AIPS_OPACR_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP7_SHIFT))&AIPS_OPACR_SP7_MASK)
810 #define AIPS_OPACR_TP6_MASK 0x10u
811 #define AIPS_OPACR_TP6_SHIFT 4u
812 #define AIPS_OPACR_TP6_WIDTH 1u
813 #define AIPS_OPACR_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP6_SHIFT))&AIPS_OPACR_TP6_MASK)
814 #define AIPS_OPACR_WP6_MASK 0x20u
815 #define AIPS_OPACR_WP6_SHIFT 5u
816 #define AIPS_OPACR_WP6_WIDTH 1u
817 #define AIPS_OPACR_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP6_SHIFT))&AIPS_OPACR_WP6_MASK)
818 #define AIPS_OPACR_SP6_MASK 0x40u
819 #define AIPS_OPACR_SP6_SHIFT 6u
820 #define AIPS_OPACR_SP6_WIDTH 1u
821 #define AIPS_OPACR_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP6_SHIFT))&AIPS_OPACR_SP6_MASK)
822 #define AIPS_OPACR_TP5_MASK 0x100u
823 #define AIPS_OPACR_TP5_SHIFT 8u
824 #define AIPS_OPACR_TP5_WIDTH 1u
825 #define AIPS_OPACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP5_SHIFT))&AIPS_OPACR_TP5_MASK)
826 #define AIPS_OPACR_WP5_MASK 0x200u
827 #define AIPS_OPACR_WP5_SHIFT 9u
828 #define AIPS_OPACR_WP5_WIDTH 1u
829 #define AIPS_OPACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP5_SHIFT))&AIPS_OPACR_WP5_MASK)
830 #define AIPS_OPACR_SP5_MASK 0x400u
831 #define AIPS_OPACR_SP5_SHIFT 10u
832 #define AIPS_OPACR_SP5_WIDTH 1u
833 #define AIPS_OPACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP5_SHIFT))&AIPS_OPACR_SP5_MASK)
834 #define AIPS_OPACR_TP4_MASK 0x1000u
835 #define AIPS_OPACR_TP4_SHIFT 12u
836 #define AIPS_OPACR_TP4_WIDTH 1u
837 #define AIPS_OPACR_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP4_SHIFT))&AIPS_OPACR_TP4_MASK)
838 #define AIPS_OPACR_WP4_MASK 0x2000u
839 #define AIPS_OPACR_WP4_SHIFT 13u
840 #define AIPS_OPACR_WP4_WIDTH 1u
841 #define AIPS_OPACR_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP4_SHIFT))&AIPS_OPACR_WP4_MASK)
842 #define AIPS_OPACR_SP4_MASK 0x4000u
843 #define AIPS_OPACR_SP4_SHIFT 14u
844 #define AIPS_OPACR_SP4_WIDTH 1u
845 #define AIPS_OPACR_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP4_SHIFT))&AIPS_OPACR_SP4_MASK)
846 #define AIPS_OPACR_TP3_MASK 0x10000u
847 #define AIPS_OPACR_TP3_SHIFT 16u
848 #define AIPS_OPACR_TP3_WIDTH 1u
849 #define AIPS_OPACR_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP3_SHIFT))&AIPS_OPACR_TP3_MASK)
850 #define AIPS_OPACR_WP3_MASK 0x20000u
851 #define AIPS_OPACR_WP3_SHIFT 17u
852 #define AIPS_OPACR_WP3_WIDTH 1u
853 #define AIPS_OPACR_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP3_SHIFT))&AIPS_OPACR_WP3_MASK)
854 #define AIPS_OPACR_SP3_MASK 0x40000u
855 #define AIPS_OPACR_SP3_SHIFT 18u
856 #define AIPS_OPACR_SP3_WIDTH 1u
857 #define AIPS_OPACR_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP3_SHIFT))&AIPS_OPACR_SP3_MASK)
858 #define AIPS_OPACR_TP2_MASK 0x100000u
859 #define AIPS_OPACR_TP2_SHIFT 20u
860 #define AIPS_OPACR_TP2_WIDTH 1u
861 #define AIPS_OPACR_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP2_SHIFT))&AIPS_OPACR_TP2_MASK)
862 #define AIPS_OPACR_WP2_MASK 0x200000u
863 #define AIPS_OPACR_WP2_SHIFT 21u
864 #define AIPS_OPACR_WP2_WIDTH 1u
865 #define AIPS_OPACR_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP2_SHIFT))&AIPS_OPACR_WP2_MASK)
866 #define AIPS_OPACR_SP2_MASK 0x400000u
867 #define AIPS_OPACR_SP2_SHIFT 22u
868 #define AIPS_OPACR_SP2_WIDTH 1u
869 #define AIPS_OPACR_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP2_SHIFT))&AIPS_OPACR_SP2_MASK)
870 #define AIPS_OPACR_TP1_MASK 0x1000000u
871 #define AIPS_OPACR_TP1_SHIFT 24u
872 #define AIPS_OPACR_TP1_WIDTH 1u
873 #define AIPS_OPACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP1_SHIFT))&AIPS_OPACR_TP1_MASK)
874 #define AIPS_OPACR_WP1_MASK 0x2000000u
875 #define AIPS_OPACR_WP1_SHIFT 25u
876 #define AIPS_OPACR_WP1_WIDTH 1u
877 #define AIPS_OPACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP1_SHIFT))&AIPS_OPACR_WP1_MASK)
878 #define AIPS_OPACR_SP1_MASK 0x4000000u
879 #define AIPS_OPACR_SP1_SHIFT 26u
880 #define AIPS_OPACR_SP1_WIDTH 1u
881 #define AIPS_OPACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP1_SHIFT))&AIPS_OPACR_SP1_MASK)
882 #define AIPS_OPACR_TP0_MASK 0x10000000u
883 #define AIPS_OPACR_TP0_SHIFT 28u
884 #define AIPS_OPACR_TP0_WIDTH 1u
885 #define AIPS_OPACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP0_SHIFT))&AIPS_OPACR_TP0_MASK)
886 #define AIPS_OPACR_WP0_MASK 0x20000000u
887 #define AIPS_OPACR_WP0_SHIFT 29u
888 #define AIPS_OPACR_WP0_WIDTH 1u
889 #define AIPS_OPACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP0_SHIFT))&AIPS_OPACR_WP0_MASK)
890 #define AIPS_OPACR_SP0_MASK 0x40000000u
891 #define AIPS_OPACR_SP0_SHIFT 30u
892 #define AIPS_OPACR_SP0_WIDTH 1u
893 #define AIPS_OPACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP0_SHIFT))&AIPS_OPACR_SP0_MASK)
916 #define CAN_RAMn_COUNT 128u
917 #define CAN_RXIMR_COUNT 16u
918 #define CAN_WMB_COUNT 4u
925 uint8_t RESERVED_0[4];
931 uint8_t RESERVED_1[4];
933 uint8_t RESERVED_2[4];
937 uint8_t RESERVED_3[8];
942 uint8_t RESERVED_4[44];
944 uint8_t RESERVED_5[1536];
946 uint8_t RESERVED_6[576];
957 uint8_t RESERVED_7[24];
964 uint8_t RESERVED_8[128];
971 #define CAN_INSTANCE_COUNT (3u)
976 #define CAN0_BASE (0x40024000u)
978 #define CAN0 ((CAN_Type *)CAN0_BASE)
980 #define CAN1_BASE (0x40025000u)
982 #define CAN1 ((CAN_Type *)CAN1_BASE)
984 #define CAN2_BASE (0x4002B000u)
986 #define CAN2 ((CAN_Type *)CAN2_BASE)
988 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE, CAN2_BASE }
990 #define CAN_BASE_PTRS { CAN0, CAN1, CAN2 }
992 #define CAN_IRQS_ARR_COUNT (7u)
994 #define CAN_Rx_Warning_IRQS_CH_COUNT (1u)
996 #define CAN_Tx_Warning_IRQS_CH_COUNT (1u)
998 #define CAN_Wake_Up_IRQS_CH_COUNT (1u)
1000 #define CAN_Error_IRQS_CH_COUNT (1u)
1002 #define CAN_Bus_Off_IRQS_CH_COUNT (1u)
1004 #define CAN_ORed_0_15_MB_IRQS_CH_COUNT (1u)
1006 #define CAN_ORed_16_31_MB_IRQS_CH_COUNT (1u)
1008 #define CAN_Rx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
1009 #define CAN_Tx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
1010 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, NotAvail_IRQn, NotAvail_IRQn }
1011 #define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn, CAN2_Error_IRQn }
1012 #define CAN_Bus_Off_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn, CAN2_ORed_IRQn }
1013 #define CAN_ORed_0_15_MB_IRQS { CAN0_ORed_0_15_MB_IRQn, CAN1_ORed_0_15_MB_IRQn, CAN2_ORed_0_15_MB_IRQn }
1014 #define CAN_ORed_16_31_MB_IRQS { CAN0_ORed_16_31_MB_IRQn, CAN1_ORed_16_31_MB_IRQn, CAN2_ORed_16_31_MB_IRQn }
1026 #define CAN_MCR_MAXMB_MASK 0x7Fu
1027 #define CAN_MCR_MAXMB_SHIFT 0u
1028 #define CAN_MCR_MAXMB_WIDTH 7u
1029 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
1030 #define CAN_MCR_IDAM_MASK 0x300u
1031 #define CAN_MCR_IDAM_SHIFT 8u
1032 #define CAN_MCR_IDAM_WIDTH 2u
1033 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
1034 #define CAN_MCR_FDEN_MASK 0x800u
1035 #define CAN_MCR_FDEN_SHIFT 11u
1036 #define CAN_MCR_FDEN_WIDTH 1u
1037 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FDEN_SHIFT))&CAN_MCR_FDEN_MASK)
1038 #define CAN_MCR_AEN_MASK 0x1000u
1039 #define CAN_MCR_AEN_SHIFT 12u
1040 #define CAN_MCR_AEN_WIDTH 1u
1041 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
1042 #define CAN_MCR_LPRIOEN_MASK 0x2000u
1043 #define CAN_MCR_LPRIOEN_SHIFT 13u
1044 #define CAN_MCR_LPRIOEN_WIDTH 1u
1045 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
1046 #define CAN_MCR_PNET_EN_MASK 0x4000u
1047 #define CAN_MCR_PNET_EN_SHIFT 14u
1048 #define CAN_MCR_PNET_EN_WIDTH 1u
1049 #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_PNET_EN_SHIFT))&CAN_MCR_PNET_EN_MASK)
1050 #define CAN_MCR_DMA_MASK 0x8000u
1051 #define CAN_MCR_DMA_SHIFT 15u
1052 #define CAN_MCR_DMA_WIDTH 1u
1053 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
1054 #define CAN_MCR_IRMQ_MASK 0x10000u
1055 #define CAN_MCR_IRMQ_SHIFT 16u
1056 #define CAN_MCR_IRMQ_WIDTH 1u
1057 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
1058 #define CAN_MCR_SRXDIS_MASK 0x20000u
1059 #define CAN_MCR_SRXDIS_SHIFT 17u
1060 #define CAN_MCR_SRXDIS_WIDTH 1u
1061 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
1062 #define CAN_MCR_LPMACK_MASK 0x100000u
1063 #define CAN_MCR_LPMACK_SHIFT 20u
1064 #define CAN_MCR_LPMACK_WIDTH 1u
1065 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
1066 #define CAN_MCR_WRNEN_MASK 0x200000u
1067 #define CAN_MCR_WRNEN_SHIFT 21u
1068 #define CAN_MCR_WRNEN_WIDTH 1u
1069 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
1070 #define CAN_MCR_SUPV_MASK 0x800000u
1071 #define CAN_MCR_SUPV_SHIFT 23u
1072 #define CAN_MCR_SUPV_WIDTH 1u
1073 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
1074 #define CAN_MCR_FRZACK_MASK 0x1000000u
1075 #define CAN_MCR_FRZACK_SHIFT 24u
1076 #define CAN_MCR_FRZACK_WIDTH 1u
1077 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
1078 #define CAN_MCR_SOFTRST_MASK 0x2000000u
1079 #define CAN_MCR_SOFTRST_SHIFT 25u
1080 #define CAN_MCR_SOFTRST_WIDTH 1u
1081 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
1082 #define CAN_MCR_NOTRDY_MASK 0x8000000u
1083 #define CAN_MCR_NOTRDY_SHIFT 27u
1084 #define CAN_MCR_NOTRDY_WIDTH 1u
1085 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
1086 #define CAN_MCR_HALT_MASK 0x10000000u
1087 #define CAN_MCR_HALT_SHIFT 28u
1088 #define CAN_MCR_HALT_WIDTH 1u
1089 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
1090 #define CAN_MCR_RFEN_MASK 0x20000000u
1091 #define CAN_MCR_RFEN_SHIFT 29u
1092 #define CAN_MCR_RFEN_WIDTH 1u
1093 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
1094 #define CAN_MCR_FRZ_MASK 0x40000000u
1095 #define CAN_MCR_FRZ_SHIFT 30u
1096 #define CAN_MCR_FRZ_WIDTH 1u
1097 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
1098 #define CAN_MCR_MDIS_MASK 0x80000000u
1099 #define CAN_MCR_MDIS_SHIFT 31u
1100 #define CAN_MCR_MDIS_WIDTH 1u
1101 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
1103 #define CAN_CTRL1_PROPSEG_MASK 0x7u
1104 #define CAN_CTRL1_PROPSEG_SHIFT 0u
1105 #define CAN_CTRL1_PROPSEG_WIDTH 3u
1106 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
1107 #define CAN_CTRL1_LOM_MASK 0x8u
1108 #define CAN_CTRL1_LOM_SHIFT 3u
1109 #define CAN_CTRL1_LOM_WIDTH 1u
1110 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
1111 #define CAN_CTRL1_LBUF_MASK 0x10u
1112 #define CAN_CTRL1_LBUF_SHIFT 4u
1113 #define CAN_CTRL1_LBUF_WIDTH 1u
1114 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
1115 #define CAN_CTRL1_TSYN_MASK 0x20u
1116 #define CAN_CTRL1_TSYN_SHIFT 5u
1117 #define CAN_CTRL1_TSYN_WIDTH 1u
1118 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
1119 #define CAN_CTRL1_BOFFREC_MASK 0x40u
1120 #define CAN_CTRL1_BOFFREC_SHIFT 6u
1121 #define CAN_CTRL1_BOFFREC_WIDTH 1u
1122 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
1123 #define CAN_CTRL1_SMP_MASK 0x80u
1124 #define CAN_CTRL1_SMP_SHIFT 7u
1125 #define CAN_CTRL1_SMP_WIDTH 1u
1126 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
1127 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
1128 #define CAN_CTRL1_RWRNMSK_SHIFT 10u
1129 #define CAN_CTRL1_RWRNMSK_WIDTH 1u
1130 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
1131 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
1132 #define CAN_CTRL1_TWRNMSK_SHIFT 11u
1133 #define CAN_CTRL1_TWRNMSK_WIDTH 1u
1134 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
1135 #define CAN_CTRL1_LPB_MASK 0x1000u
1136 #define CAN_CTRL1_LPB_SHIFT 12u
1137 #define CAN_CTRL1_LPB_WIDTH 1u
1138 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
1139 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1140 #define CAN_CTRL1_CLKSRC_SHIFT 13u
1141 #define CAN_CTRL1_CLKSRC_WIDTH 1u
1142 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
1143 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1144 #define CAN_CTRL1_ERRMSK_SHIFT 14u
1145 #define CAN_CTRL1_ERRMSK_WIDTH 1u
1146 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
1147 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1148 #define CAN_CTRL1_BOFFMSK_SHIFT 15u
1149 #define CAN_CTRL1_BOFFMSK_WIDTH 1u
1150 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
1151 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1152 #define CAN_CTRL1_PSEG2_SHIFT 16u
1153 #define CAN_CTRL1_PSEG2_WIDTH 3u
1154 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1155 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1156 #define CAN_CTRL1_PSEG1_SHIFT 19u
1157 #define CAN_CTRL1_PSEG1_WIDTH 3u
1158 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1159 #define CAN_CTRL1_RJW_MASK 0xC00000u
1160 #define CAN_CTRL1_RJW_SHIFT 22u
1161 #define CAN_CTRL1_RJW_WIDTH 2u
1162 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1163 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
1164 #define CAN_CTRL1_PRESDIV_SHIFT 24u
1165 #define CAN_CTRL1_PRESDIV_WIDTH 8u
1166 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
1168 #define CAN_TIMER_TIMER_MASK 0xFFFFu
1169 #define CAN_TIMER_TIMER_SHIFT 0u
1170 #define CAN_TIMER_TIMER_WIDTH 16u
1171 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
1173 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
1174 #define CAN_RXMGMASK_MG_SHIFT 0u
1175 #define CAN_RXMGMASK_MG_WIDTH 32u
1176 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
1178 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
1179 #define CAN_RX14MASK_RX14M_SHIFT 0u
1180 #define CAN_RX14MASK_RX14M_WIDTH 32u
1181 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
1183 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
1184 #define CAN_RX15MASK_RX15M_SHIFT 0u
1185 #define CAN_RX15MASK_RX15M_WIDTH 32u
1186 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
1188 #define CAN_ECR_TXERRCNT_MASK 0xFFu
1189 #define CAN_ECR_TXERRCNT_SHIFT 0u
1190 #define CAN_ECR_TXERRCNT_WIDTH 8u
1191 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
1192 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
1193 #define CAN_ECR_RXERRCNT_SHIFT 8u
1194 #define CAN_ECR_RXERRCNT_WIDTH 8u
1195 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
1196 #define CAN_ECR_TXERRCNT_FAST_MASK 0xFF0000u
1197 #define CAN_ECR_TXERRCNT_FAST_SHIFT 16u
1198 #define CAN_ECR_TXERRCNT_FAST_WIDTH 8u
1199 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_FAST_SHIFT))&CAN_ECR_TXERRCNT_FAST_MASK)
1200 #define CAN_ECR_RXERRCNT_FAST_MASK 0xFF000000u
1201 #define CAN_ECR_RXERRCNT_FAST_SHIFT 24u
1202 #define CAN_ECR_RXERRCNT_FAST_WIDTH 8u
1203 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_FAST_SHIFT))&CAN_ECR_RXERRCNT_FAST_MASK)
1205 #define CAN_ESR1_ERRINT_MASK 0x2u
1206 #define CAN_ESR1_ERRINT_SHIFT 1u
1207 #define CAN_ESR1_ERRINT_WIDTH 1u
1208 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
1209 #define CAN_ESR1_BOFFINT_MASK 0x4u
1210 #define CAN_ESR1_BOFFINT_SHIFT 2u
1211 #define CAN_ESR1_BOFFINT_WIDTH 1u
1212 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
1213 #define CAN_ESR1_RX_MASK 0x8u
1214 #define CAN_ESR1_RX_SHIFT 3u
1215 #define CAN_ESR1_RX_WIDTH 1u
1216 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
1217 #define CAN_ESR1_FLTCONF_MASK 0x30u
1218 #define CAN_ESR1_FLTCONF_SHIFT 4u
1219 #define CAN_ESR1_FLTCONF_WIDTH 2u
1220 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
1221 #define CAN_ESR1_TX_MASK 0x40u
1222 #define CAN_ESR1_TX_SHIFT 6u
1223 #define CAN_ESR1_TX_WIDTH 1u
1224 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
1225 #define CAN_ESR1_IDLE_MASK 0x80u
1226 #define CAN_ESR1_IDLE_SHIFT 7u
1227 #define CAN_ESR1_IDLE_WIDTH 1u
1228 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
1229 #define CAN_ESR1_RXWRN_MASK 0x100u
1230 #define CAN_ESR1_RXWRN_SHIFT 8u
1231 #define CAN_ESR1_RXWRN_WIDTH 1u
1232 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
1233 #define CAN_ESR1_TXWRN_MASK 0x200u
1234 #define CAN_ESR1_TXWRN_SHIFT 9u
1235 #define CAN_ESR1_TXWRN_WIDTH 1u
1236 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
1237 #define CAN_ESR1_STFERR_MASK 0x400u
1238 #define CAN_ESR1_STFERR_SHIFT 10u
1239 #define CAN_ESR1_STFERR_WIDTH 1u
1240 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
1241 #define CAN_ESR1_FRMERR_MASK 0x800u
1242 #define CAN_ESR1_FRMERR_SHIFT 11u
1243 #define CAN_ESR1_FRMERR_WIDTH 1u
1244 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
1245 #define CAN_ESR1_CRCERR_MASK 0x1000u
1246 #define CAN_ESR1_CRCERR_SHIFT 12u
1247 #define CAN_ESR1_CRCERR_WIDTH 1u
1248 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
1249 #define CAN_ESR1_ACKERR_MASK 0x2000u
1250 #define CAN_ESR1_ACKERR_SHIFT 13u
1251 #define CAN_ESR1_ACKERR_WIDTH 1u
1252 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
1253 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
1254 #define CAN_ESR1_BIT0ERR_SHIFT 14u
1255 #define CAN_ESR1_BIT0ERR_WIDTH 1u
1256 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
1257 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
1258 #define CAN_ESR1_BIT1ERR_SHIFT 15u
1259 #define CAN_ESR1_BIT1ERR_WIDTH 1u
1260 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
1261 #define CAN_ESR1_RWRNINT_MASK 0x10000u
1262 #define CAN_ESR1_RWRNINT_SHIFT 16u
1263 #define CAN_ESR1_RWRNINT_WIDTH 1u
1264 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
1265 #define CAN_ESR1_TWRNINT_MASK 0x20000u
1266 #define CAN_ESR1_TWRNINT_SHIFT 17u
1267 #define CAN_ESR1_TWRNINT_WIDTH 1u
1268 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
1269 #define CAN_ESR1_SYNCH_MASK 0x40000u
1270 #define CAN_ESR1_SYNCH_SHIFT 18u
1271 #define CAN_ESR1_SYNCH_WIDTH 1u
1272 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
1273 #define CAN_ESR1_BOFFDONEINT_MASK 0x80000u
1274 #define CAN_ESR1_BOFFDONEINT_SHIFT 19u
1275 #define CAN_ESR1_BOFFDONEINT_WIDTH 1u
1276 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
1277 #define CAN_ESR1_ERRINT_FAST_MASK 0x100000u
1278 #define CAN_ESR1_ERRINT_FAST_SHIFT 20u
1279 #define CAN_ESR1_ERRINT_FAST_WIDTH 1u
1280 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_FAST_SHIFT))&CAN_ESR1_ERRINT_FAST_MASK)
1281 #define CAN_ESR1_ERROVR_MASK 0x200000u
1282 #define CAN_ESR1_ERROVR_SHIFT 21u
1283 #define CAN_ESR1_ERROVR_WIDTH 1u
1284 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
1285 #define CAN_ESR1_STFERR_FAST_MASK 0x4000000u
1286 #define CAN_ESR1_STFERR_FAST_SHIFT 26u
1287 #define CAN_ESR1_STFERR_FAST_WIDTH 1u
1288 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_FAST_SHIFT))&CAN_ESR1_STFERR_FAST_MASK)
1289 #define CAN_ESR1_FRMERR_FAST_MASK 0x8000000u
1290 #define CAN_ESR1_FRMERR_FAST_SHIFT 27u
1291 #define CAN_ESR1_FRMERR_FAST_WIDTH 1u
1292 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_FAST_SHIFT))&CAN_ESR1_FRMERR_FAST_MASK)
1293 #define CAN_ESR1_CRCERR_FAST_MASK 0x10000000u
1294 #define CAN_ESR1_CRCERR_FAST_SHIFT 28u
1295 #define CAN_ESR1_CRCERR_FAST_WIDTH 1u
1296 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_FAST_SHIFT))&CAN_ESR1_CRCERR_FAST_MASK)
1297 #define CAN_ESR1_BIT0ERR_FAST_MASK 0x40000000u
1298 #define CAN_ESR1_BIT0ERR_FAST_SHIFT 30u
1299 #define CAN_ESR1_BIT0ERR_FAST_WIDTH 1u
1300 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_FAST_SHIFT))&CAN_ESR1_BIT0ERR_FAST_MASK)
1301 #define CAN_ESR1_BIT1ERR_FAST_MASK 0x80000000u
1302 #define CAN_ESR1_BIT1ERR_FAST_SHIFT 31u
1303 #define CAN_ESR1_BIT1ERR_FAST_WIDTH 1u
1304 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_FAST_SHIFT))&CAN_ESR1_BIT1ERR_FAST_MASK)
1306 #define CAN_IMASK1_BUF31TO0M_MASK 0xFFFFFFFFu
1307 #define CAN_IMASK1_BUF31TO0M_SHIFT 0u
1308 #define CAN_IMASK1_BUF31TO0M_WIDTH 32u
1309 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
1311 #define CAN_IFLAG1_BUF0I_MASK 0x1u
1312 #define CAN_IFLAG1_BUF0I_SHIFT 0u
1313 #define CAN_IFLAG1_BUF0I_WIDTH 1u
1314 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
1315 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
1316 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1u
1317 #define CAN_IFLAG1_BUF4TO1I_WIDTH 4u
1318 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
1319 #define CAN_IFLAG1_BUF5I_MASK 0x20u
1320 #define CAN_IFLAG1_BUF5I_SHIFT 5u
1321 #define CAN_IFLAG1_BUF5I_WIDTH 1u
1322 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
1323 #define CAN_IFLAG1_BUF6I_MASK 0x40u
1324 #define CAN_IFLAG1_BUF6I_SHIFT 6u
1325 #define CAN_IFLAG1_BUF6I_WIDTH 1u
1326 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
1327 #define CAN_IFLAG1_BUF7I_MASK 0x80u
1328 #define CAN_IFLAG1_BUF7I_SHIFT 7u
1329 #define CAN_IFLAG1_BUF7I_WIDTH 1u
1330 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
1331 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
1332 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8u
1333 #define CAN_IFLAG1_BUF31TO8I_WIDTH 24u
1334 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
1336 #define CAN_CTRL2_EDFLTDIS_MASK 0x800u
1337 #define CAN_CTRL2_EDFLTDIS_SHIFT 11u
1338 #define CAN_CTRL2_EDFLTDIS_WIDTH 1u
1339 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EDFLTDIS_SHIFT))&CAN_CTRL2_EDFLTDIS_MASK)
1340 #define CAN_CTRL2_ISOCANFDEN_MASK 0x1000u
1341 #define CAN_CTRL2_ISOCANFDEN_SHIFT 12u
1342 #define CAN_CTRL2_ISOCANFDEN_WIDTH 1u
1343 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ISOCANFDEN_SHIFT))&CAN_CTRL2_ISOCANFDEN_MASK)
1344 #define CAN_CTRL2_PREXCEN_MASK 0x4000u
1345 #define CAN_CTRL2_PREXCEN_SHIFT 14u
1346 #define CAN_CTRL2_PREXCEN_WIDTH 1u
1347 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PREXCEN_SHIFT))&CAN_CTRL2_PREXCEN_MASK)
1348 #define CAN_CTRL2_TIMER_SRC_MASK 0x8000u
1349 #define CAN_CTRL2_TIMER_SRC_SHIFT 15u
1350 #define CAN_CTRL2_TIMER_SRC_WIDTH 1u
1351 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TIMER_SRC_SHIFT))&CAN_CTRL2_TIMER_SRC_MASK)
1352 #define CAN_CTRL2_EACEN_MASK 0x10000u
1353 #define CAN_CTRL2_EACEN_SHIFT 16u
1354 #define CAN_CTRL2_EACEN_WIDTH 1u
1355 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
1356 #define CAN_CTRL2_RRS_MASK 0x20000u
1357 #define CAN_CTRL2_RRS_SHIFT 17u
1358 #define CAN_CTRL2_RRS_WIDTH 1u
1359 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
1360 #define CAN_CTRL2_MRP_MASK 0x40000u
1361 #define CAN_CTRL2_MRP_SHIFT 18u
1362 #define CAN_CTRL2_MRP_WIDTH 1u
1363 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
1364 #define CAN_CTRL2_TASD_MASK 0xF80000u
1365 #define CAN_CTRL2_TASD_SHIFT 19u
1366 #define CAN_CTRL2_TASD_WIDTH 5u
1367 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
1368 #define CAN_CTRL2_RFFN_MASK 0xF000000u
1369 #define CAN_CTRL2_RFFN_SHIFT 24u
1370 #define CAN_CTRL2_RFFN_WIDTH 4u
1371 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
1372 #define CAN_CTRL2_BOFFDONEMSK_MASK 0x40000000u
1373 #define CAN_CTRL2_BOFFDONEMSK_SHIFT 30u
1374 #define CAN_CTRL2_BOFFDONEMSK_WIDTH 1u
1375 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
1376 #define CAN_CTRL2_ERRMSK_FAST_MASK 0x80000000u
1377 #define CAN_CTRL2_ERRMSK_FAST_SHIFT 31u
1378 #define CAN_CTRL2_ERRMSK_FAST_WIDTH 1u
1379 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ERRMSK_FAST_SHIFT))&CAN_CTRL2_ERRMSK_FAST_MASK)
1381 #define CAN_ESR2_IMB_MASK 0x2000u
1382 #define CAN_ESR2_IMB_SHIFT 13u
1383 #define CAN_ESR2_IMB_WIDTH 1u
1384 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
1385 #define CAN_ESR2_VPS_MASK 0x4000u
1386 #define CAN_ESR2_VPS_SHIFT 14u
1387 #define CAN_ESR2_VPS_WIDTH 1u
1388 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
1389 #define CAN_ESR2_LPTM_MASK 0x7F0000u
1390 #define CAN_ESR2_LPTM_SHIFT 16u
1391 #define CAN_ESR2_LPTM_WIDTH 7u
1392 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
1394 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
1395 #define CAN_CRCR_TXCRC_SHIFT 0u
1396 #define CAN_CRCR_TXCRC_WIDTH 15u
1397 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
1398 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
1399 #define CAN_CRCR_MBCRC_SHIFT 16u
1400 #define CAN_CRCR_MBCRC_WIDTH 7u
1401 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
1403 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
1404 #define CAN_RXFGMASK_FGM_SHIFT 0u
1405 #define CAN_RXFGMASK_FGM_WIDTH 32u
1406 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
1408 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
1409 #define CAN_RXFIR_IDHIT_SHIFT 0u
1410 #define CAN_RXFIR_IDHIT_WIDTH 9u
1411 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
1413 #define CAN_CBT_EPSEG2_MASK 0x1Fu
1414 #define CAN_CBT_EPSEG2_SHIFT 0u
1415 #define CAN_CBT_EPSEG2_WIDTH 5u
1416 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
1417 #define CAN_CBT_EPSEG1_MASK 0x3E0u
1418 #define CAN_CBT_EPSEG1_SHIFT 5u
1419 #define CAN_CBT_EPSEG1_WIDTH 5u
1420 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
1421 #define CAN_CBT_EPROPSEG_MASK 0xFC00u
1422 #define CAN_CBT_EPROPSEG_SHIFT 10u
1423 #define CAN_CBT_EPROPSEG_WIDTH 6u
1424 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
1425 #define CAN_CBT_ERJW_MASK 0x1F0000u
1426 #define CAN_CBT_ERJW_SHIFT 16u
1427 #define CAN_CBT_ERJW_WIDTH 5u
1428 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
1429 #define CAN_CBT_EPRESDIV_MASK 0x7FE00000u
1430 #define CAN_CBT_EPRESDIV_SHIFT 21u
1431 #define CAN_CBT_EPRESDIV_WIDTH 10u
1432 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
1433 #define CAN_CBT_BTF_MASK 0x80000000u
1434 #define CAN_CBT_BTF_SHIFT 31u
1435 #define CAN_CBT_BTF_WIDTH 1u
1436 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
1438 #define CAN_RAMn_DATA_BYTE_3_MASK 0xFFu
1439 #define CAN_RAMn_DATA_BYTE_3_SHIFT 0u
1440 #define CAN_RAMn_DATA_BYTE_3_WIDTH 8u
1441 #define CAN_RAMn_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_3_SHIFT))&CAN_RAMn_DATA_BYTE_3_MASK)
1442 #define CAN_RAMn_DATA_BYTE_2_MASK 0xFF00u
1443 #define CAN_RAMn_DATA_BYTE_2_SHIFT 8u
1444 #define CAN_RAMn_DATA_BYTE_2_WIDTH 8u
1445 #define CAN_RAMn_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_2_SHIFT))&CAN_RAMn_DATA_BYTE_2_MASK)
1446 #define CAN_RAMn_DATA_BYTE_1_MASK 0xFF0000u
1447 #define CAN_RAMn_DATA_BYTE_1_SHIFT 16u
1448 #define CAN_RAMn_DATA_BYTE_1_WIDTH 8u
1449 #define CAN_RAMn_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_1_SHIFT))&CAN_RAMn_DATA_BYTE_1_MASK)
1450 #define CAN_RAMn_DATA_BYTE_0_MASK 0xFF000000u
1451 #define CAN_RAMn_DATA_BYTE_0_SHIFT 24u
1452 #define CAN_RAMn_DATA_BYTE_0_WIDTH 8u
1453 #define CAN_RAMn_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_0_SHIFT))&CAN_RAMn_DATA_BYTE_0_MASK)
1455 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
1456 #define CAN_RXIMR_MI_SHIFT 0u
1457 #define CAN_RXIMR_MI_WIDTH 32u
1458 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
1460 #define CAN_CTRL1_PN_FCS_MASK 0x3u
1461 #define CAN_CTRL1_PN_FCS_SHIFT 0u
1462 #define CAN_CTRL1_PN_FCS_WIDTH 2u
1463 #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_FCS_SHIFT))&CAN_CTRL1_PN_FCS_MASK)
1464 #define CAN_CTRL1_PN_IDFS_MASK 0xCu
1465 #define CAN_CTRL1_PN_IDFS_SHIFT 2u
1466 #define CAN_CTRL1_PN_IDFS_WIDTH 2u
1467 #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_IDFS_SHIFT))&CAN_CTRL1_PN_IDFS_MASK)
1468 #define CAN_CTRL1_PN_PLFS_MASK 0x30u
1469 #define CAN_CTRL1_PN_PLFS_SHIFT 4u
1470 #define CAN_CTRL1_PN_PLFS_WIDTH 2u
1471 #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_PLFS_SHIFT))&CAN_CTRL1_PN_PLFS_MASK)
1472 #define CAN_CTRL1_PN_NMATCH_MASK 0xFF00u
1473 #define CAN_CTRL1_PN_NMATCH_SHIFT 8u
1474 #define CAN_CTRL1_PN_NMATCH_WIDTH 8u
1475 #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_NMATCH_SHIFT))&CAN_CTRL1_PN_NMATCH_MASK)
1476 #define CAN_CTRL1_PN_WUMF_MSK_MASK 0x10000u
1477 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT 16u
1478 #define CAN_CTRL1_PN_WUMF_MSK_WIDTH 1u
1479 #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WUMF_MSK_SHIFT))&CAN_CTRL1_PN_WUMF_MSK_MASK)
1480 #define CAN_CTRL1_PN_WTOF_MSK_MASK 0x20000u
1481 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT 17u
1482 #define CAN_CTRL1_PN_WTOF_MSK_WIDTH 1u
1483 #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WTOF_MSK_SHIFT))&CAN_CTRL1_PN_WTOF_MSK_MASK)
1485 #define CAN_CTRL2_PN_MATCHTO_MASK 0xFFFFu
1486 #define CAN_CTRL2_PN_MATCHTO_SHIFT 0u
1487 #define CAN_CTRL2_PN_MATCHTO_WIDTH 16u
1488 #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PN_MATCHTO_SHIFT))&CAN_CTRL2_PN_MATCHTO_MASK)
1490 #define CAN_WU_MTC_MCOUNTER_MASK 0xFF00u
1491 #define CAN_WU_MTC_MCOUNTER_SHIFT 8u
1492 #define CAN_WU_MTC_MCOUNTER_WIDTH 8u
1493 #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_MCOUNTER_SHIFT))&CAN_WU_MTC_MCOUNTER_MASK)
1494 #define CAN_WU_MTC_WUMF_MASK 0x10000u
1495 #define CAN_WU_MTC_WUMF_SHIFT 16u
1496 #define CAN_WU_MTC_WUMF_WIDTH 1u
1497 #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WUMF_SHIFT))&CAN_WU_MTC_WUMF_MASK)
1498 #define CAN_WU_MTC_WTOF_MASK 0x20000u
1499 #define CAN_WU_MTC_WTOF_SHIFT 17u
1500 #define CAN_WU_MTC_WTOF_WIDTH 1u
1501 #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WTOF_SHIFT))&CAN_WU_MTC_WTOF_MASK)
1503 #define CAN_FLT_ID1_FLT_ID1_MASK 0x1FFFFFFFu
1504 #define CAN_FLT_ID1_FLT_ID1_SHIFT 0u
1505 #define CAN_FLT_ID1_FLT_ID1_WIDTH 29u
1506 #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_ID1_SHIFT))&CAN_FLT_ID1_FLT_ID1_MASK)
1507 #define CAN_FLT_ID1_FLT_RTR_MASK 0x20000000u
1508 #define CAN_FLT_ID1_FLT_RTR_SHIFT 29u
1509 #define CAN_FLT_ID1_FLT_RTR_WIDTH 1u
1510 #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_RTR_SHIFT))&CAN_FLT_ID1_FLT_RTR_MASK)
1511 #define CAN_FLT_ID1_FLT_IDE_MASK 0x40000000u
1512 #define CAN_FLT_ID1_FLT_IDE_SHIFT 30u
1513 #define CAN_FLT_ID1_FLT_IDE_WIDTH 1u
1514 #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_IDE_SHIFT))&CAN_FLT_ID1_FLT_IDE_MASK)
1516 #define CAN_FLT_DLC_FLT_DLC_HI_MASK 0xFu
1517 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT 0u
1518 #define CAN_FLT_DLC_FLT_DLC_HI_WIDTH 4u
1519 #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_HI_SHIFT))&CAN_FLT_DLC_FLT_DLC_HI_MASK)
1520 #define CAN_FLT_DLC_FLT_DLC_LO_MASK 0xF0000u
1521 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT 16u
1522 #define CAN_FLT_DLC_FLT_DLC_LO_WIDTH 4u
1523 #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_LO_SHIFT))&CAN_FLT_DLC_FLT_DLC_LO_MASK)
1525 #define CAN_PL1_LO_Data_byte_3_MASK 0xFFu
1526 #define CAN_PL1_LO_Data_byte_3_SHIFT 0u
1527 #define CAN_PL1_LO_Data_byte_3_WIDTH 8u
1528 #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_3_SHIFT))&CAN_PL1_LO_Data_byte_3_MASK)
1529 #define CAN_PL1_LO_Data_byte_2_MASK 0xFF00u
1530 #define CAN_PL1_LO_Data_byte_2_SHIFT 8u
1531 #define CAN_PL1_LO_Data_byte_2_WIDTH 8u
1532 #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_2_SHIFT))&CAN_PL1_LO_Data_byte_2_MASK)
1533 #define CAN_PL1_LO_Data_byte_1_MASK 0xFF0000u
1534 #define CAN_PL1_LO_Data_byte_1_SHIFT 16u
1535 #define CAN_PL1_LO_Data_byte_1_WIDTH 8u
1536 #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_1_SHIFT))&CAN_PL1_LO_Data_byte_1_MASK)
1537 #define CAN_PL1_LO_Data_byte_0_MASK 0xFF000000u
1538 #define CAN_PL1_LO_Data_byte_0_SHIFT 24u
1539 #define CAN_PL1_LO_Data_byte_0_WIDTH 8u
1540 #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_0_SHIFT))&CAN_PL1_LO_Data_byte_0_MASK)
1542 #define CAN_PL1_HI_Data_byte_7_MASK 0xFFu
1543 #define CAN_PL1_HI_Data_byte_7_SHIFT 0u
1544 #define CAN_PL1_HI_Data_byte_7_WIDTH 8u
1545 #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_7_SHIFT))&CAN_PL1_HI_Data_byte_7_MASK)
1546 #define CAN_PL1_HI_Data_byte_6_MASK 0xFF00u
1547 #define CAN_PL1_HI_Data_byte_6_SHIFT 8u
1548 #define CAN_PL1_HI_Data_byte_6_WIDTH 8u
1549 #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_6_SHIFT))&CAN_PL1_HI_Data_byte_6_MASK)
1550 #define CAN_PL1_HI_Data_byte_5_MASK 0xFF0000u
1551 #define CAN_PL1_HI_Data_byte_5_SHIFT 16u
1552 #define CAN_PL1_HI_Data_byte_5_WIDTH 8u
1553 #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_5_SHIFT))&CAN_PL1_HI_Data_byte_5_MASK)
1554 #define CAN_PL1_HI_Data_byte_4_MASK 0xFF000000u
1555 #define CAN_PL1_HI_Data_byte_4_SHIFT 24u
1556 #define CAN_PL1_HI_Data_byte_4_WIDTH 8u
1557 #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_4_SHIFT))&CAN_PL1_HI_Data_byte_4_MASK)
1559 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK 0x1FFFFFFFu
1560 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT 0u
1561 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH 29u
1562 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT))&CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
1563 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK 0x20000000u
1564 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT 29u
1565 #define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH 1u
1566 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
1567 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK 0x40000000u
1568 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT 30u
1569 #define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH 1u
1570 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
1572 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK 0xFFu
1573 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT 0u
1574 #define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH 8u
1575 #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
1576 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK 0xFF00u
1577 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT 8u
1578 #define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH 8u
1579 #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
1580 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK 0xFF0000u
1581 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT 16u
1582 #define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH 8u
1583 #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
1584 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK 0xFF000000u
1585 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT 24u
1586 #define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH 8u
1587 #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
1589 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK 0xFFu
1590 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT 0u
1591 #define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH 8u
1592 #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
1593 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK 0xFF00u
1594 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT 8u
1595 #define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH 8u
1596 #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
1597 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK 0xFF0000u
1598 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT 16u
1599 #define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH 8u
1600 #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
1601 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK 0xFF000000u
1602 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT 24u
1603 #define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH 8u
1604 #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
1606 #define CAN_WMBn_CS_DLC_MASK 0xF0000u
1607 #define CAN_WMBn_CS_DLC_SHIFT 16u
1608 #define CAN_WMBn_CS_DLC_WIDTH 4u
1609 #define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_DLC_SHIFT))&CAN_WMBn_CS_DLC_MASK)
1610 #define CAN_WMBn_CS_RTR_MASK 0x100000u
1611 #define CAN_WMBn_CS_RTR_SHIFT 20u
1612 #define CAN_WMBn_CS_RTR_WIDTH 1u
1613 #define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_RTR_SHIFT))&CAN_WMBn_CS_RTR_MASK)
1614 #define CAN_WMBn_CS_IDE_MASK 0x200000u
1615 #define CAN_WMBn_CS_IDE_SHIFT 21u
1616 #define CAN_WMBn_CS_IDE_WIDTH 1u
1617 #define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_IDE_SHIFT))&CAN_WMBn_CS_IDE_MASK)
1618 #define CAN_WMBn_CS_SRR_MASK 0x400000u
1619 #define CAN_WMBn_CS_SRR_SHIFT 22u
1620 #define CAN_WMBn_CS_SRR_WIDTH 1u
1621 #define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_SRR_SHIFT))&CAN_WMBn_CS_SRR_MASK)
1623 #define CAN_WMBn_ID_ID_MASK 0x1FFFFFFFu
1624 #define CAN_WMBn_ID_ID_SHIFT 0u
1625 #define CAN_WMBn_ID_ID_WIDTH 29u
1626 #define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_ID_ID_SHIFT))&CAN_WMBn_ID_ID_MASK)
1628 #define CAN_WMBn_D03_Data_byte_3_MASK 0xFFu
1629 #define CAN_WMBn_D03_Data_byte_3_SHIFT 0u
1630 #define CAN_WMBn_D03_Data_byte_3_WIDTH 8u
1631 #define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_3_SHIFT))&CAN_WMBn_D03_Data_byte_3_MASK)
1632 #define CAN_WMBn_D03_Data_byte_2_MASK 0xFF00u
1633 #define CAN_WMBn_D03_Data_byte_2_SHIFT 8u
1634 #define CAN_WMBn_D03_Data_byte_2_WIDTH 8u
1635 #define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_2_SHIFT))&CAN_WMBn_D03_Data_byte_2_MASK)
1636 #define CAN_WMBn_D03_Data_byte_1_MASK 0xFF0000u
1637 #define CAN_WMBn_D03_Data_byte_1_SHIFT 16u
1638 #define CAN_WMBn_D03_Data_byte_1_WIDTH 8u
1639 #define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_1_SHIFT))&CAN_WMBn_D03_Data_byte_1_MASK)
1640 #define CAN_WMBn_D03_Data_byte_0_MASK 0xFF000000u
1641 #define CAN_WMBn_D03_Data_byte_0_SHIFT 24u
1642 #define CAN_WMBn_D03_Data_byte_0_WIDTH 8u
1643 #define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_0_SHIFT))&CAN_WMBn_D03_Data_byte_0_MASK)
1645 #define CAN_WMBn_D47_Data_byte_7_MASK 0xFFu
1646 #define CAN_WMBn_D47_Data_byte_7_SHIFT 0u
1647 #define CAN_WMBn_D47_Data_byte_7_WIDTH 8u
1648 #define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_7_SHIFT))&CAN_WMBn_D47_Data_byte_7_MASK)
1649 #define CAN_WMBn_D47_Data_byte_6_MASK 0xFF00u
1650 #define CAN_WMBn_D47_Data_byte_6_SHIFT 8u
1651 #define CAN_WMBn_D47_Data_byte_6_WIDTH 8u
1652 #define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_6_SHIFT))&CAN_WMBn_D47_Data_byte_6_MASK)
1653 #define CAN_WMBn_D47_Data_byte_5_MASK 0xFF0000u
1654 #define CAN_WMBn_D47_Data_byte_5_SHIFT 16u
1655 #define CAN_WMBn_D47_Data_byte_5_WIDTH 8u
1656 #define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_5_SHIFT))&CAN_WMBn_D47_Data_byte_5_MASK)
1657 #define CAN_WMBn_D47_Data_byte_4_MASK 0xFF000000u
1658 #define CAN_WMBn_D47_Data_byte_4_SHIFT 24u
1659 #define CAN_WMBn_D47_Data_byte_4_WIDTH 8u
1660 #define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_4_SHIFT))&CAN_WMBn_D47_Data_byte_4_MASK)
1662 #define CAN_FDCTRL_TDCVAL_MASK 0x3Fu
1663 #define CAN_FDCTRL_TDCVAL_SHIFT 0u
1664 #define CAN_FDCTRL_TDCVAL_WIDTH 6u
1665 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCVAL_SHIFT))&CAN_FDCTRL_TDCVAL_MASK)
1666 #define CAN_FDCTRL_TDCOFF_MASK 0x1F00u
1667 #define CAN_FDCTRL_TDCOFF_SHIFT 8u
1668 #define CAN_FDCTRL_TDCOFF_WIDTH 5u
1669 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCOFF_SHIFT))&CAN_FDCTRL_TDCOFF_MASK)
1670 #define CAN_FDCTRL_TDCFAIL_MASK 0x4000u
1671 #define CAN_FDCTRL_TDCFAIL_SHIFT 14u
1672 #define CAN_FDCTRL_TDCFAIL_WIDTH 1u
1673 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCFAIL_SHIFT))&CAN_FDCTRL_TDCFAIL_MASK)
1674 #define CAN_FDCTRL_TDCEN_MASK 0x8000u
1675 #define CAN_FDCTRL_TDCEN_SHIFT 15u
1676 #define CAN_FDCTRL_TDCEN_WIDTH 1u
1677 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCEN_SHIFT))&CAN_FDCTRL_TDCEN_MASK)
1678 #define CAN_FDCTRL_MBDSR0_MASK 0x30000u
1679 #define CAN_FDCTRL_MBDSR0_SHIFT 16u
1680 #define CAN_FDCTRL_MBDSR0_WIDTH 2u
1681 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_MBDSR0_SHIFT))&CAN_FDCTRL_MBDSR0_MASK)
1682 #define CAN_FDCTRL_FDRATE_MASK 0x80000000u
1683 #define CAN_FDCTRL_FDRATE_SHIFT 31u
1684 #define CAN_FDCTRL_FDRATE_WIDTH 1u
1685 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_FDRATE_SHIFT))&CAN_FDCTRL_FDRATE_MASK)
1687 #define CAN_FDCBT_FPSEG2_MASK 0x7u
1688 #define CAN_FDCBT_FPSEG2_SHIFT 0u
1689 #define CAN_FDCBT_FPSEG2_WIDTH 3u
1690 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG2_SHIFT))&CAN_FDCBT_FPSEG2_MASK)
1691 #define CAN_FDCBT_FPSEG1_MASK 0xE0u
1692 #define CAN_FDCBT_FPSEG1_SHIFT 5u
1693 #define CAN_FDCBT_FPSEG1_WIDTH 3u
1694 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG1_SHIFT))&CAN_FDCBT_FPSEG1_MASK)
1695 #define CAN_FDCBT_FPROPSEG_MASK 0x7C00u
1696 #define CAN_FDCBT_FPROPSEG_SHIFT 10u
1697 #define CAN_FDCBT_FPROPSEG_WIDTH 5u
1698 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPROPSEG_SHIFT))&CAN_FDCBT_FPROPSEG_MASK)
1699 #define CAN_FDCBT_FRJW_MASK 0x70000u
1700 #define CAN_FDCBT_FRJW_SHIFT 16u
1701 #define CAN_FDCBT_FRJW_WIDTH 3u
1702 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FRJW_SHIFT))&CAN_FDCBT_FRJW_MASK)
1703 #define CAN_FDCBT_FPRESDIV_MASK 0x3FF00000u
1704 #define CAN_FDCBT_FPRESDIV_SHIFT 20u
1705 #define CAN_FDCBT_FPRESDIV_WIDTH 10u
1706 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPRESDIV_SHIFT))&CAN_FDCBT_FPRESDIV_MASK)
1708 #define CAN_FDCRC_FD_TXCRC_MASK 0x1FFFFFu
1709 #define CAN_FDCRC_FD_TXCRC_SHIFT 0u
1710 #define CAN_FDCRC_FD_TXCRC_WIDTH 21u
1711 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_TXCRC_SHIFT))&CAN_FDCRC_FD_TXCRC_MASK)
1712 #define CAN_FDCRC_FD_MBCRC_MASK 0x7F000000u
1713 #define CAN_FDCRC_FD_MBCRC_SHIFT 24u
1714 #define CAN_FDCRC_FD_MBCRC_WIDTH 7u
1715 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_MBCRC_SHIFT))&CAN_FDCRC_FD_MBCRC_MASK)
1747 #define CMP_INSTANCE_COUNT (1u)
1752 #define CMP0_BASE (0x40073000u)
1754 #define CMP0 ((CMP_Type *)CMP0_BASE)
1756 #define CMP_BASE_ADDRS { CMP0_BASE }
1758 #define CMP_BASE_PTRS { CMP0 }
1760 #define CMP_IRQS_ARR_COUNT (1u)
1762 #define CMP_IRQS_CH_COUNT (1u)
1764 #define CMP_IRQS { CMP0_IRQn }
1776 #define CMP_C0_HYSTCTR_MASK 0x3u
1777 #define CMP_C0_HYSTCTR_SHIFT 0u
1778 #define CMP_C0_HYSTCTR_WIDTH 2u
1779 #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_HYSTCTR_SHIFT))&CMP_C0_HYSTCTR_MASK)
1780 #define CMP_C0_OFFSET_MASK 0x4u
1781 #define CMP_C0_OFFSET_SHIFT 2u
1782 #define CMP_C0_OFFSET_WIDTH 1u
1783 #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OFFSET_SHIFT))&CMP_C0_OFFSET_MASK)
1784 #define CMP_C0_FILTER_CNT_MASK 0x70u
1785 #define CMP_C0_FILTER_CNT_SHIFT 4u
1786 #define CMP_C0_FILTER_CNT_WIDTH 3u
1787 #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FILTER_CNT_SHIFT))&CMP_C0_FILTER_CNT_MASK)
1788 #define CMP_C0_EN_MASK 0x100u
1789 #define CMP_C0_EN_SHIFT 8u
1790 #define CMP_C0_EN_WIDTH 1u
1791 #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_EN_SHIFT))&CMP_C0_EN_MASK)
1792 #define CMP_C0_OPE_MASK 0x200u
1793 #define CMP_C0_OPE_SHIFT 9u
1794 #define CMP_C0_OPE_WIDTH 1u
1795 #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OPE_SHIFT))&CMP_C0_OPE_MASK)
1796 #define CMP_C0_COS_MASK 0x400u
1797 #define CMP_C0_COS_SHIFT 10u
1798 #define CMP_C0_COS_WIDTH 1u
1799 #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COS_SHIFT))&CMP_C0_COS_MASK)
1800 #define CMP_C0_INVT_MASK 0x800u
1801 #define CMP_C0_INVT_SHIFT 11u
1802 #define CMP_C0_INVT_WIDTH 1u
1803 #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_INVT_SHIFT))&CMP_C0_INVT_MASK)
1804 #define CMP_C0_PMODE_MASK 0x1000u
1805 #define CMP_C0_PMODE_SHIFT 12u
1806 #define CMP_C0_PMODE_WIDTH 1u
1807 #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_PMODE_SHIFT))&CMP_C0_PMODE_MASK)
1808 #define CMP_C0_WE_MASK 0x4000u
1809 #define CMP_C0_WE_SHIFT 14u
1810 #define CMP_C0_WE_WIDTH 1u
1811 #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_WE_SHIFT))&CMP_C0_WE_MASK)
1812 #define CMP_C0_SE_MASK 0x8000u
1813 #define CMP_C0_SE_SHIFT 15u
1814 #define CMP_C0_SE_WIDTH 1u
1815 #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_SE_SHIFT))&CMP_C0_SE_MASK)
1816 #define CMP_C0_FPR_MASK 0xFF0000u
1817 #define CMP_C0_FPR_SHIFT 16u
1818 #define CMP_C0_FPR_WIDTH 8u
1819 #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FPR_SHIFT))&CMP_C0_FPR_MASK)
1820 #define CMP_C0_COUT_MASK 0x1000000u
1821 #define CMP_C0_COUT_SHIFT 24u
1822 #define CMP_C0_COUT_WIDTH 1u
1823 #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COUT_SHIFT))&CMP_C0_COUT_MASK)
1824 #define CMP_C0_CFF_MASK 0x2000000u
1825 #define CMP_C0_CFF_SHIFT 25u
1826 #define CMP_C0_CFF_WIDTH 1u
1827 #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFF_SHIFT))&CMP_C0_CFF_MASK)
1828 #define CMP_C0_CFR_MASK 0x4000000u
1829 #define CMP_C0_CFR_SHIFT 26u
1830 #define CMP_C0_CFR_WIDTH 1u
1831 #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFR_SHIFT))&CMP_C0_CFR_MASK)
1832 #define CMP_C0_IEF_MASK 0x8000000u
1833 #define CMP_C0_IEF_SHIFT 27u
1834 #define CMP_C0_IEF_WIDTH 1u
1835 #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IEF_SHIFT))&CMP_C0_IEF_MASK)
1836 #define CMP_C0_IER_MASK 0x10000000u
1837 #define CMP_C0_IER_SHIFT 28u
1838 #define CMP_C0_IER_WIDTH 1u
1839 #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IER_SHIFT))&CMP_C0_IER_MASK)
1840 #define CMP_C0_DMAEN_MASK 0x40000000u
1841 #define CMP_C0_DMAEN_SHIFT 30u
1842 #define CMP_C0_DMAEN_WIDTH 1u
1843 #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_DMAEN_SHIFT))&CMP_C0_DMAEN_MASK)
1845 #define CMP_C1_VOSEL_MASK 0xFFu
1846 #define CMP_C1_VOSEL_SHIFT 0u
1847 #define CMP_C1_VOSEL_WIDTH 8u
1848 #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VOSEL_SHIFT))&CMP_C1_VOSEL_MASK)
1849 #define CMP_C1_MSEL_MASK 0x700u
1850 #define CMP_C1_MSEL_SHIFT 8u
1851 #define CMP_C1_MSEL_WIDTH 3u
1852 #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_MSEL_SHIFT))&CMP_C1_MSEL_MASK)
1853 #define CMP_C1_PSEL_MASK 0x3800u
1854 #define CMP_C1_PSEL_SHIFT 11u
1855 #define CMP_C1_PSEL_WIDTH 3u
1856 #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_PSEL_SHIFT))&CMP_C1_PSEL_MASK)
1857 #define CMP_C1_VRSEL_MASK 0x4000u
1858 #define CMP_C1_VRSEL_SHIFT 14u
1859 #define CMP_C1_VRSEL_WIDTH 1u
1860 #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VRSEL_SHIFT))&CMP_C1_VRSEL_MASK)
1861 #define CMP_C1_DACEN_MASK 0x8000u
1862 #define CMP_C1_DACEN_SHIFT 15u
1863 #define CMP_C1_DACEN_WIDTH 1u
1864 #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_DACEN_SHIFT))&CMP_C1_DACEN_MASK)
1865 #define CMP_C1_CHN0_MASK 0x10000u
1866 #define CMP_C1_CHN0_SHIFT 16u
1867 #define CMP_C1_CHN0_WIDTH 1u
1868 #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN0_SHIFT))&CMP_C1_CHN0_MASK)
1869 #define CMP_C1_CHN1_MASK 0x20000u
1870 #define CMP_C1_CHN1_SHIFT 17u
1871 #define CMP_C1_CHN1_WIDTH 1u
1872 #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN1_SHIFT))&CMP_C1_CHN1_MASK)
1873 #define CMP_C1_CHN2_MASK 0x40000u
1874 #define CMP_C1_CHN2_SHIFT 18u
1875 #define CMP_C1_CHN2_WIDTH 1u
1876 #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN2_SHIFT))&CMP_C1_CHN2_MASK)
1877 #define CMP_C1_CHN3_MASK 0x80000u
1878 #define CMP_C1_CHN3_SHIFT 19u
1879 #define CMP_C1_CHN3_WIDTH 1u
1880 #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN3_SHIFT))&CMP_C1_CHN3_MASK)
1881 #define CMP_C1_CHN4_MASK 0x100000u
1882 #define CMP_C1_CHN4_SHIFT 20u
1883 #define CMP_C1_CHN4_WIDTH 1u
1884 #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN4_SHIFT))&CMP_C1_CHN4_MASK)
1885 #define CMP_C1_CHN5_MASK 0x200000u
1886 #define CMP_C1_CHN5_SHIFT 21u
1887 #define CMP_C1_CHN5_WIDTH 1u
1888 #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN5_SHIFT))&CMP_C1_CHN5_MASK)
1889 #define CMP_C1_CHN6_MASK 0x400000u
1890 #define CMP_C1_CHN6_SHIFT 22u
1891 #define CMP_C1_CHN6_WIDTH 1u
1892 #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN6_SHIFT))&CMP_C1_CHN6_MASK)
1893 #define CMP_C1_CHN7_MASK 0x800000u
1894 #define CMP_C1_CHN7_SHIFT 23u
1895 #define CMP_C1_CHN7_WIDTH 1u
1896 #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN7_SHIFT))&CMP_C1_CHN7_MASK)
1897 #define CMP_C1_INNSEL_MASK 0x3000000u
1898 #define CMP_C1_INNSEL_SHIFT 24u
1899 #define CMP_C1_INNSEL_WIDTH 2u
1900 #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INNSEL_SHIFT))&CMP_C1_INNSEL_MASK)
1901 #define CMP_C1_INPSEL_MASK 0x18000000u
1902 #define CMP_C1_INPSEL_SHIFT 27u
1903 #define CMP_C1_INPSEL_WIDTH 2u
1904 #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INPSEL_SHIFT))&CMP_C1_INPSEL_MASK)
1906 #define CMP_C2_ACOn_MASK 0xFFu
1907 #define CMP_C2_ACOn_SHIFT 0u
1908 #define CMP_C2_ACOn_WIDTH 8u
1909 #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_ACOn_SHIFT))&CMP_C2_ACOn_MASK)
1910 #define CMP_C2_INITMOD_MASK 0x3F00u
1911 #define CMP_C2_INITMOD_SHIFT 8u
1912 #define CMP_C2_INITMOD_WIDTH 6u
1913 #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_INITMOD_SHIFT))&CMP_C2_INITMOD_MASK)
1914 #define CMP_C2_NSAM_MASK 0xC000u
1915 #define CMP_C2_NSAM_SHIFT 14u
1916 #define CMP_C2_NSAM_WIDTH 2u
1917 #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_NSAM_SHIFT))&CMP_C2_NSAM_MASK)
1918 #define CMP_C2_CH0F_MASK 0x10000u
1919 #define CMP_C2_CH0F_SHIFT 16u
1920 #define CMP_C2_CH0F_WIDTH 1u
1921 #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH0F_SHIFT))&CMP_C2_CH0F_MASK)
1922 #define CMP_C2_CH1F_MASK 0x20000u
1923 #define CMP_C2_CH1F_SHIFT 17u
1924 #define CMP_C2_CH1F_WIDTH 1u
1925 #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH1F_SHIFT))&CMP_C2_CH1F_MASK)
1926 #define CMP_C2_CH2F_MASK 0x40000u
1927 #define CMP_C2_CH2F_SHIFT 18u
1928 #define CMP_C2_CH2F_WIDTH 1u
1929 #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH2F_SHIFT))&CMP_C2_CH2F_MASK)
1930 #define CMP_C2_CH3F_MASK 0x80000u
1931 #define CMP_C2_CH3F_SHIFT 19u
1932 #define CMP_C2_CH3F_WIDTH 1u
1933 #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH3F_SHIFT))&CMP_C2_CH3F_MASK)
1934 #define CMP_C2_CH4F_MASK 0x100000u
1935 #define CMP_C2_CH4F_SHIFT 20u
1936 #define CMP_C2_CH4F_WIDTH 1u
1937 #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH4F_SHIFT))&CMP_C2_CH4F_MASK)
1938 #define CMP_C2_CH5F_MASK 0x200000u
1939 #define CMP_C2_CH5F_SHIFT 21u
1940 #define CMP_C2_CH5F_WIDTH 1u
1941 #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH5F_SHIFT))&CMP_C2_CH5F_MASK)
1942 #define CMP_C2_CH6F_MASK 0x400000u
1943 #define CMP_C2_CH6F_SHIFT 22u
1944 #define CMP_C2_CH6F_WIDTH 1u
1945 #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH6F_SHIFT))&CMP_C2_CH6F_MASK)
1946 #define CMP_C2_CH7F_MASK 0x800000u
1947 #define CMP_C2_CH7F_SHIFT 23u
1948 #define CMP_C2_CH7F_WIDTH 1u
1949 #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH7F_SHIFT))&CMP_C2_CH7F_MASK)
1950 #define CMP_C2_FXMXCH_MASK 0xE000000u
1951 #define CMP_C2_FXMXCH_SHIFT 25u
1952 #define CMP_C2_FXMXCH_WIDTH 3u
1953 #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMXCH_SHIFT))&CMP_C2_FXMXCH_MASK)
1954 #define CMP_C2_FXMP_MASK 0x20000000u
1955 #define CMP_C2_FXMP_SHIFT 29u
1956 #define CMP_C2_FXMP_WIDTH 1u
1957 #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMP_SHIFT))&CMP_C2_FXMP_MASK)
1958 #define CMP_C2_RRIE_MASK 0x40000000u
1959 #define CMP_C2_RRIE_SHIFT 30u
1960 #define CMP_C2_RRIE_WIDTH 1u
1961 #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRIE_SHIFT))&CMP_C2_RRIE_MASK)
1962 #define CMP_C2_RRE_MASK 0x80000000u
1963 #define CMP_C2_RRE_SHIFT 31u
1964 #define CMP_C2_RRE_WIDTH 1u
1965 #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRE_SHIFT))&CMP_C2_RRE_MASK)
2009 #define CRC_INSTANCE_COUNT (1u)
2014 #define CRC_BASE (0x40032000u)
2016 #define CRC ((CRC_Type *)CRC_BASE)
2018 #define CRC_BASE_ADDRS { CRC_BASE }
2020 #define CRC_BASE_PTRS { CRC }
2032 #define CRC_DATAu_DATA_LL_MASK 0xFFu
2033 #define CRC_DATAu_DATA_LL_SHIFT 0u
2034 #define CRC_DATAu_DATA_LL_WIDTH 8u
2035 #define CRC_DATAu_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LL_SHIFT))&CRC_DATAu_DATA_LL_MASK)
2036 #define CRC_DATAu_DATA_LU_MASK 0xFF00u
2037 #define CRC_DATAu_DATA_LU_SHIFT 8u
2038 #define CRC_DATAu_DATA_LU_WIDTH 8u
2039 #define CRC_DATAu_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LU_SHIFT))&CRC_DATAu_DATA_LU_MASK)
2040 #define CRC_DATAu_DATA_HL_MASK 0xFF0000u
2041 #define CRC_DATAu_DATA_HL_SHIFT 16u
2042 #define CRC_DATAu_DATA_HL_WIDTH 8u
2043 #define CRC_DATAu_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HL_SHIFT))&CRC_DATAu_DATA_HL_MASK)
2044 #define CRC_DATAu_DATA_HU_MASK 0xFF000000u
2045 #define CRC_DATAu_DATA_HU_SHIFT 24u
2046 #define CRC_DATAu_DATA_HU_WIDTH 8u
2047 #define CRC_DATAu_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HU_SHIFT))&CRC_DATAu_DATA_HU_MASK)
2049 #define CRC_DATAu_DATA_16_L_DATAL_MASK 0xFFFFu
2050 #define CRC_DATAu_DATA_16_L_DATAL_SHIFT 0u
2051 #define CRC_DATAu_DATA_16_L_DATAL_WIDTH 16u
2052 #define CRC_DATAu_DATA_16_L_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_L_DATAL_SHIFT))&CRC_DATAu_DATA_16_L_DATAL_MASK)
2054 #define CRC_DATAu_DATA_16_H_DATAH_MASK 0xFFFFu
2055 #define CRC_DATAu_DATA_16_H_DATAH_SHIFT 0u
2056 #define CRC_DATAu_DATA_16_H_DATAH_WIDTH 16u
2057 #define CRC_DATAu_DATA_16_H_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_H_DATAH_SHIFT))&CRC_DATAu_DATA_16_H_DATAH_MASK)
2059 #define CRC_DATAu_DATA_8_LL_DATALL_MASK 0xFFu
2060 #define CRC_DATAu_DATA_8_LL_DATALL_SHIFT 0u
2061 #define CRC_DATAu_DATA_8_LL_DATALL_WIDTH 8u
2062 #define CRC_DATAu_DATA_8_LL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LL_DATALL_SHIFT))&CRC_DATAu_DATA_8_LL_DATALL_MASK)
2064 #define CRC_DATAu_DATA_8_LU_DATALU_MASK 0xFFu
2065 #define CRC_DATAu_DATA_8_LU_DATALU_SHIFT 0u
2066 #define CRC_DATAu_DATA_8_LU_DATALU_WIDTH 8u
2067 #define CRC_DATAu_DATA_8_LU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LU_DATALU_SHIFT))&CRC_DATAu_DATA_8_LU_DATALU_MASK)
2069 #define CRC_DATAu_DATA_8_HL_DATAHL_MASK 0xFFu
2070 #define CRC_DATAu_DATA_8_HL_DATAHL_SHIFT 0u
2071 #define CRC_DATAu_DATA_8_HL_DATAHL_WIDTH 8u
2072 #define CRC_DATAu_DATA_8_HL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HL_DATAHL_SHIFT))&CRC_DATAu_DATA_8_HL_DATAHL_MASK)
2074 #define CRC_DATAu_DATA_8_HU_DATAHU_MASK 0xFFu
2075 #define CRC_DATAu_DATA_8_HU_DATAHU_SHIFT 0u
2076 #define CRC_DATAu_DATA_8_HU_DATAHU_WIDTH 8u
2077 #define CRC_DATAu_DATA_8_HU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HU_DATAHU_SHIFT))&CRC_DATAu_DATA_8_HU_DATAHU_MASK)
2079 #define CRC_GPOLY_LOW_MASK 0xFFFFu
2080 #define CRC_GPOLY_LOW_SHIFT 0u
2081 #define CRC_GPOLY_LOW_WIDTH 16u
2082 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
2083 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
2084 #define CRC_GPOLY_HIGH_SHIFT 16u
2085 #define CRC_GPOLY_HIGH_WIDTH 16u
2086 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
2088 #define CRC_CTRL_TCRC_MASK 0x1000000u
2089 #define CRC_CTRL_TCRC_SHIFT 24u
2090 #define CRC_CTRL_TCRC_WIDTH 1u
2091 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
2092 #define CRC_CTRL_WAS_MASK 0x2000000u
2093 #define CRC_CTRL_WAS_SHIFT 25u
2094 #define CRC_CTRL_WAS_WIDTH 1u
2095 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
2096 #define CRC_CTRL_FXOR_MASK 0x4000000u
2097 #define CRC_CTRL_FXOR_SHIFT 26u
2098 #define CRC_CTRL_FXOR_WIDTH 1u
2099 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
2100 #define CRC_CTRL_TOTR_MASK 0x30000000u
2101 #define CRC_CTRL_TOTR_SHIFT 28u
2102 #define CRC_CTRL_TOTR_WIDTH 2u
2103 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
2104 #define CRC_CTRL_TOT_MASK 0xC0000000u
2105 #define CRC_CTRL_TOT_SHIFT 30u
2106 #define CRC_CTRL_TOT_WIDTH 2u
2107 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
2130 #define CSE_PRAM_RAMn_COUNT 32u
2146 #define CSE_PRAM_INSTANCE_COUNT (1u)
2151 #define CSE_PRAM_BASE (0x14001000u)
2153 #define CSE_PRAM ((CSE_PRAM_Type *)CSE_PRAM_BASE)
2155 #define CSE_PRAM_BASE_ADDRS { CSE_PRAM_BASE }
2157 #define CSE_PRAM_BASE_PTRS { CSE_PRAM }
2169 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK 0xFFu
2170 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT 0u
2171 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_WIDTH 8u
2172 #define CSE_PRAM_RAMn_DATA_32_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK)
2173 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK 0xFF00u
2174 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT 8u
2175 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_WIDTH 8u
2176 #define CSE_PRAM_RAMn_DATA_32_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK)
2177 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK 0xFF0000u
2178 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT 16u
2179 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_WIDTH 8u
2180 #define CSE_PRAM_RAMn_DATA_32_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK)
2181 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK 0xFF000000u
2182 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT 24u
2183 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_WIDTH 8u
2184 #define CSE_PRAM_RAMn_DATA_32_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK)
2186 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK 0xFFu
2187 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT 0u
2188 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_WIDTH 8u
2189 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK)
2191 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK 0xFFu
2192 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT 0u
2193 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_WIDTH 8u
2194 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK)
2196 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK 0xFFu
2197 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT 0u
2198 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_WIDTH 8u
2199 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK)
2201 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK 0xFFu
2202 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT 0u
2203 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_WIDTH 8u
2204 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK)
2227 #define DMA_DCHPRI_COUNT 16u
2228 #define DMA_TCD_COUNT 16u
2234 uint8_t RESERVED_0[4];
2236 uint8_t RESERVED_1[4];
2246 uint8_t RESERVED_2[4];
2248 uint8_t RESERVED_3[4];
2250 uint8_t RESERVED_4[4];
2252 uint8_t RESERVED_5[12];
2254 uint8_t RESERVED_6[184];
2256 uint8_t RESERVED_7[3824];
2276 __IO uint16_t ELINKNO;
2277 __IO uint16_t ELINKYES;
2283 #define DMA_INSTANCE_COUNT (1u)
2288 #define DMA_BASE (0x40008000u)
2290 #define DMA ((DMA_Type *)DMA_BASE)
2292 #define DMA_BASE_ADDRS { DMA_BASE }
2294 #define DMA_BASE_PTRS { DMA }
2296 #define DMA_IRQS_ARR_COUNT (2u)
2298 #define DMA_CHN_IRQS_CH_COUNT (16u)
2300 #define DMA_ERROR_IRQS_CH_COUNT (1u)
2302 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
2303 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
2315 #define DMA_CR_EDBG_MASK 0x2u
2316 #define DMA_CR_EDBG_SHIFT 1u
2317 #define DMA_CR_EDBG_WIDTH 1u
2318 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
2319 #define DMA_CR_ERCA_MASK 0x4u
2320 #define DMA_CR_ERCA_SHIFT 2u
2321 #define DMA_CR_ERCA_WIDTH 1u
2322 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
2323 #define DMA_CR_HOE_MASK 0x10u
2324 #define DMA_CR_HOE_SHIFT 4u
2325 #define DMA_CR_HOE_WIDTH 1u
2326 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
2327 #define DMA_CR_HALT_MASK 0x20u
2328 #define DMA_CR_HALT_SHIFT 5u
2329 #define DMA_CR_HALT_WIDTH 1u
2330 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
2331 #define DMA_CR_CLM_MASK 0x40u
2332 #define DMA_CR_CLM_SHIFT 6u
2333 #define DMA_CR_CLM_WIDTH 1u
2334 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
2335 #define DMA_CR_EMLM_MASK 0x80u
2336 #define DMA_CR_EMLM_SHIFT 7u
2337 #define DMA_CR_EMLM_WIDTH 1u
2338 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
2339 #define DMA_CR_ECX_MASK 0x10000u
2340 #define DMA_CR_ECX_SHIFT 16u
2341 #define DMA_CR_ECX_WIDTH 1u
2342 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
2343 #define DMA_CR_CX_MASK 0x20000u
2344 #define DMA_CR_CX_SHIFT 17u
2345 #define DMA_CR_CX_WIDTH 1u
2346 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
2348 #define DMA_ES_DBE_MASK 0x1u
2349 #define DMA_ES_DBE_SHIFT 0u
2350 #define DMA_ES_DBE_WIDTH 1u
2351 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
2352 #define DMA_ES_SBE_MASK 0x2u
2353 #define DMA_ES_SBE_SHIFT 1u
2354 #define DMA_ES_SBE_WIDTH 1u
2355 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
2356 #define DMA_ES_SGE_MASK 0x4u
2357 #define DMA_ES_SGE_SHIFT 2u
2358 #define DMA_ES_SGE_WIDTH 1u
2359 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
2360 #define DMA_ES_NCE_MASK 0x8u
2361 #define DMA_ES_NCE_SHIFT 3u
2362 #define DMA_ES_NCE_WIDTH 1u
2363 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
2364 #define DMA_ES_DOE_MASK 0x10u
2365 #define DMA_ES_DOE_SHIFT 4u
2366 #define DMA_ES_DOE_WIDTH 1u
2367 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
2368 #define DMA_ES_DAE_MASK 0x20u
2369 #define DMA_ES_DAE_SHIFT 5u
2370 #define DMA_ES_DAE_WIDTH 1u
2371 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
2372 #define DMA_ES_SOE_MASK 0x40u
2373 #define DMA_ES_SOE_SHIFT 6u
2374 #define DMA_ES_SOE_WIDTH 1u
2375 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
2376 #define DMA_ES_SAE_MASK 0x80u
2377 #define DMA_ES_SAE_SHIFT 7u
2378 #define DMA_ES_SAE_WIDTH 1u
2379 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
2380 #define DMA_ES_ERRCHN_MASK 0xF00u
2381 #define DMA_ES_ERRCHN_SHIFT 8u
2382 #define DMA_ES_ERRCHN_WIDTH 4u
2383 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
2384 #define DMA_ES_CPE_MASK 0x4000u
2385 #define DMA_ES_CPE_SHIFT 14u
2386 #define DMA_ES_CPE_WIDTH 1u
2387 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
2388 #define DMA_ES_ECX_MASK 0x10000u
2389 #define DMA_ES_ECX_SHIFT 16u
2390 #define DMA_ES_ECX_WIDTH 1u
2391 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
2392 #define DMA_ES_VLD_MASK 0x80000000u
2393 #define DMA_ES_VLD_SHIFT 31u
2394 #define DMA_ES_VLD_WIDTH 1u
2395 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
2397 #define DMA_ERQ_ERQ0_MASK 0x1u
2398 #define DMA_ERQ_ERQ0_SHIFT 0u
2399 #define DMA_ERQ_ERQ0_WIDTH 1u
2400 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
2401 #define DMA_ERQ_ERQ1_MASK 0x2u
2402 #define DMA_ERQ_ERQ1_SHIFT 1u
2403 #define DMA_ERQ_ERQ1_WIDTH 1u
2404 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
2405 #define DMA_ERQ_ERQ2_MASK 0x4u
2406 #define DMA_ERQ_ERQ2_SHIFT 2u
2407 #define DMA_ERQ_ERQ2_WIDTH 1u
2408 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
2409 #define DMA_ERQ_ERQ3_MASK 0x8u
2410 #define DMA_ERQ_ERQ3_SHIFT 3u
2411 #define DMA_ERQ_ERQ3_WIDTH 1u
2412 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
2413 #define DMA_ERQ_ERQ4_MASK 0x10u
2414 #define DMA_ERQ_ERQ4_SHIFT 4u
2415 #define DMA_ERQ_ERQ4_WIDTH 1u
2416 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
2417 #define DMA_ERQ_ERQ5_MASK 0x20u
2418 #define DMA_ERQ_ERQ5_SHIFT 5u
2419 #define DMA_ERQ_ERQ5_WIDTH 1u
2420 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
2421 #define DMA_ERQ_ERQ6_MASK 0x40u
2422 #define DMA_ERQ_ERQ6_SHIFT 6u
2423 #define DMA_ERQ_ERQ6_WIDTH 1u
2424 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
2425 #define DMA_ERQ_ERQ7_MASK 0x80u
2426 #define DMA_ERQ_ERQ7_SHIFT 7u
2427 #define DMA_ERQ_ERQ7_WIDTH 1u
2428 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
2429 #define DMA_ERQ_ERQ8_MASK 0x100u
2430 #define DMA_ERQ_ERQ8_SHIFT 8u
2431 #define DMA_ERQ_ERQ8_WIDTH 1u
2432 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
2433 #define DMA_ERQ_ERQ9_MASK 0x200u
2434 #define DMA_ERQ_ERQ9_SHIFT 9u
2435 #define DMA_ERQ_ERQ9_WIDTH 1u
2436 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
2437 #define DMA_ERQ_ERQ10_MASK 0x400u
2438 #define DMA_ERQ_ERQ10_SHIFT 10u
2439 #define DMA_ERQ_ERQ10_WIDTH 1u
2440 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
2441 #define DMA_ERQ_ERQ11_MASK 0x800u
2442 #define DMA_ERQ_ERQ11_SHIFT 11u
2443 #define DMA_ERQ_ERQ11_WIDTH 1u
2444 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
2445 #define DMA_ERQ_ERQ12_MASK 0x1000u
2446 #define DMA_ERQ_ERQ12_SHIFT 12u
2447 #define DMA_ERQ_ERQ12_WIDTH 1u
2448 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
2449 #define DMA_ERQ_ERQ13_MASK 0x2000u
2450 #define DMA_ERQ_ERQ13_SHIFT 13u
2451 #define DMA_ERQ_ERQ13_WIDTH 1u
2452 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
2453 #define DMA_ERQ_ERQ14_MASK 0x4000u
2454 #define DMA_ERQ_ERQ14_SHIFT 14u
2455 #define DMA_ERQ_ERQ14_WIDTH 1u
2456 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
2457 #define DMA_ERQ_ERQ15_MASK 0x8000u
2458 #define DMA_ERQ_ERQ15_SHIFT 15u
2459 #define DMA_ERQ_ERQ15_WIDTH 1u
2460 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
2462 #define DMA_EEI_EEI0_MASK 0x1u
2463 #define DMA_EEI_EEI0_SHIFT 0u
2464 #define DMA_EEI_EEI0_WIDTH 1u
2465 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
2466 #define DMA_EEI_EEI1_MASK 0x2u
2467 #define DMA_EEI_EEI1_SHIFT 1u
2468 #define DMA_EEI_EEI1_WIDTH 1u
2469 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
2470 #define DMA_EEI_EEI2_MASK 0x4u
2471 #define DMA_EEI_EEI2_SHIFT 2u
2472 #define DMA_EEI_EEI2_WIDTH 1u
2473 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
2474 #define DMA_EEI_EEI3_MASK 0x8u
2475 #define DMA_EEI_EEI3_SHIFT 3u
2476 #define DMA_EEI_EEI3_WIDTH 1u
2477 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
2478 #define DMA_EEI_EEI4_MASK 0x10u
2479 #define DMA_EEI_EEI4_SHIFT 4u
2480 #define DMA_EEI_EEI4_WIDTH 1u
2481 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
2482 #define DMA_EEI_EEI5_MASK 0x20u
2483 #define DMA_EEI_EEI5_SHIFT 5u
2484 #define DMA_EEI_EEI5_WIDTH 1u
2485 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
2486 #define DMA_EEI_EEI6_MASK 0x40u
2487 #define DMA_EEI_EEI6_SHIFT 6u
2488 #define DMA_EEI_EEI6_WIDTH 1u
2489 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
2490 #define DMA_EEI_EEI7_MASK 0x80u
2491 #define DMA_EEI_EEI7_SHIFT 7u
2492 #define DMA_EEI_EEI7_WIDTH 1u
2493 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
2494 #define DMA_EEI_EEI8_MASK 0x100u
2495 #define DMA_EEI_EEI8_SHIFT 8u
2496 #define DMA_EEI_EEI8_WIDTH 1u
2497 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
2498 #define DMA_EEI_EEI9_MASK 0x200u
2499 #define DMA_EEI_EEI9_SHIFT 9u
2500 #define DMA_EEI_EEI9_WIDTH 1u
2501 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
2502 #define DMA_EEI_EEI10_MASK 0x400u
2503 #define DMA_EEI_EEI10_SHIFT 10u
2504 #define DMA_EEI_EEI10_WIDTH 1u
2505 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
2506 #define DMA_EEI_EEI11_MASK 0x800u
2507 #define DMA_EEI_EEI11_SHIFT 11u
2508 #define DMA_EEI_EEI11_WIDTH 1u
2509 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
2510 #define DMA_EEI_EEI12_MASK 0x1000u
2511 #define DMA_EEI_EEI12_SHIFT 12u
2512 #define DMA_EEI_EEI12_WIDTH 1u
2513 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
2514 #define DMA_EEI_EEI13_MASK 0x2000u
2515 #define DMA_EEI_EEI13_SHIFT 13u
2516 #define DMA_EEI_EEI13_WIDTH 1u
2517 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
2518 #define DMA_EEI_EEI14_MASK 0x4000u
2519 #define DMA_EEI_EEI14_SHIFT 14u
2520 #define DMA_EEI_EEI14_WIDTH 1u
2521 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
2522 #define DMA_EEI_EEI15_MASK 0x8000u
2523 #define DMA_EEI_EEI15_SHIFT 15u
2524 #define DMA_EEI_EEI15_WIDTH 1u
2525 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
2527 #define DMA_CEEI_CEEI_MASK 0xFu
2528 #define DMA_CEEI_CEEI_SHIFT 0u
2529 #define DMA_CEEI_CEEI_WIDTH 4u
2530 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
2531 #define DMA_CEEI_CAEE_MASK 0x40u
2532 #define DMA_CEEI_CAEE_SHIFT 6u
2533 #define DMA_CEEI_CAEE_WIDTH 1u
2534 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
2535 #define DMA_CEEI_NOP_MASK 0x80u
2536 #define DMA_CEEI_NOP_SHIFT 7u
2537 #define DMA_CEEI_NOP_WIDTH 1u
2538 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
2540 #define DMA_SEEI_SEEI_MASK 0xFu
2541 #define DMA_SEEI_SEEI_SHIFT 0u
2542 #define DMA_SEEI_SEEI_WIDTH 4u
2543 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
2544 #define DMA_SEEI_SAEE_MASK 0x40u
2545 #define DMA_SEEI_SAEE_SHIFT 6u
2546 #define DMA_SEEI_SAEE_WIDTH 1u
2547 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
2548 #define DMA_SEEI_NOP_MASK 0x80u
2549 #define DMA_SEEI_NOP_SHIFT 7u
2550 #define DMA_SEEI_NOP_WIDTH 1u
2551 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
2553 #define DMA_CERQ_CERQ_MASK 0xFu
2554 #define DMA_CERQ_CERQ_SHIFT 0u
2555 #define DMA_CERQ_CERQ_WIDTH 4u
2556 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
2557 #define DMA_CERQ_CAER_MASK 0x40u
2558 #define DMA_CERQ_CAER_SHIFT 6u
2559 #define DMA_CERQ_CAER_WIDTH 1u
2560 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
2561 #define DMA_CERQ_NOP_MASK 0x80u
2562 #define DMA_CERQ_NOP_SHIFT 7u
2563 #define DMA_CERQ_NOP_WIDTH 1u
2564 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
2566 #define DMA_SERQ_SERQ_MASK 0xFu
2567 #define DMA_SERQ_SERQ_SHIFT 0u
2568 #define DMA_SERQ_SERQ_WIDTH 4u
2569 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
2570 #define DMA_SERQ_SAER_MASK 0x40u
2571 #define DMA_SERQ_SAER_SHIFT 6u
2572 #define DMA_SERQ_SAER_WIDTH 1u
2573 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
2574 #define DMA_SERQ_NOP_MASK 0x80u
2575 #define DMA_SERQ_NOP_SHIFT 7u
2576 #define DMA_SERQ_NOP_WIDTH 1u
2577 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
2579 #define DMA_CDNE_CDNE_MASK 0xFu
2580 #define DMA_CDNE_CDNE_SHIFT 0u
2581 #define DMA_CDNE_CDNE_WIDTH 4u
2582 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
2583 #define DMA_CDNE_CADN_MASK 0x40u
2584 #define DMA_CDNE_CADN_SHIFT 6u
2585 #define DMA_CDNE_CADN_WIDTH 1u
2586 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
2587 #define DMA_CDNE_NOP_MASK 0x80u
2588 #define DMA_CDNE_NOP_SHIFT 7u
2589 #define DMA_CDNE_NOP_WIDTH 1u
2590 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
2592 #define DMA_SSRT_SSRT_MASK 0xFu
2593 #define DMA_SSRT_SSRT_SHIFT 0u
2594 #define DMA_SSRT_SSRT_WIDTH 4u
2595 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
2596 #define DMA_SSRT_SAST_MASK 0x40u
2597 #define DMA_SSRT_SAST_SHIFT 6u
2598 #define DMA_SSRT_SAST_WIDTH 1u
2599 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
2600 #define DMA_SSRT_NOP_MASK 0x80u
2601 #define DMA_SSRT_NOP_SHIFT 7u
2602 #define DMA_SSRT_NOP_WIDTH 1u
2603 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
2605 #define DMA_CERR_CERR_MASK 0xFu
2606 #define DMA_CERR_CERR_SHIFT 0u
2607 #define DMA_CERR_CERR_WIDTH 4u
2608 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
2609 #define DMA_CERR_CAEI_MASK 0x40u
2610 #define DMA_CERR_CAEI_SHIFT 6u
2611 #define DMA_CERR_CAEI_WIDTH 1u
2612 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
2613 #define DMA_CERR_NOP_MASK 0x80u
2614 #define DMA_CERR_NOP_SHIFT 7u
2615 #define DMA_CERR_NOP_WIDTH 1u
2616 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
2618 #define DMA_CINT_CINT_MASK 0xFu
2619 #define DMA_CINT_CINT_SHIFT 0u
2620 #define DMA_CINT_CINT_WIDTH 4u
2621 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
2622 #define DMA_CINT_CAIR_MASK 0x40u
2623 #define DMA_CINT_CAIR_SHIFT 6u
2624 #define DMA_CINT_CAIR_WIDTH 1u
2625 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
2626 #define DMA_CINT_NOP_MASK 0x80u
2627 #define DMA_CINT_NOP_SHIFT 7u
2628 #define DMA_CINT_NOP_WIDTH 1u
2629 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
2631 #define DMA_INT_INT0_MASK 0x1u
2632 #define DMA_INT_INT0_SHIFT 0u
2633 #define DMA_INT_INT0_WIDTH 1u
2634 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
2635 #define DMA_INT_INT1_MASK 0x2u
2636 #define DMA_INT_INT1_SHIFT 1u
2637 #define DMA_INT_INT1_WIDTH 1u
2638 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
2639 #define DMA_INT_INT2_MASK 0x4u
2640 #define DMA_INT_INT2_SHIFT 2u
2641 #define DMA_INT_INT2_WIDTH 1u
2642 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
2643 #define DMA_INT_INT3_MASK 0x8u
2644 #define DMA_INT_INT3_SHIFT 3u
2645 #define DMA_INT_INT3_WIDTH 1u
2646 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
2647 #define DMA_INT_INT4_MASK 0x10u
2648 #define DMA_INT_INT4_SHIFT 4u
2649 #define DMA_INT_INT4_WIDTH 1u
2650 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
2651 #define DMA_INT_INT5_MASK 0x20u
2652 #define DMA_INT_INT5_SHIFT 5u
2653 #define DMA_INT_INT5_WIDTH 1u
2654 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
2655 #define DMA_INT_INT6_MASK 0x40u
2656 #define DMA_INT_INT6_SHIFT 6u
2657 #define DMA_INT_INT6_WIDTH 1u
2658 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
2659 #define DMA_INT_INT7_MASK 0x80u
2660 #define DMA_INT_INT7_SHIFT 7u
2661 #define DMA_INT_INT7_WIDTH 1u
2662 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
2663 #define DMA_INT_INT8_MASK 0x100u
2664 #define DMA_INT_INT8_SHIFT 8u
2665 #define DMA_INT_INT8_WIDTH 1u
2666 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
2667 #define DMA_INT_INT9_MASK 0x200u
2668 #define DMA_INT_INT9_SHIFT 9u
2669 #define DMA_INT_INT9_WIDTH 1u
2670 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
2671 #define DMA_INT_INT10_MASK 0x400u
2672 #define DMA_INT_INT10_SHIFT 10u
2673 #define DMA_INT_INT10_WIDTH 1u
2674 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
2675 #define DMA_INT_INT11_MASK 0x800u
2676 #define DMA_INT_INT11_SHIFT 11u
2677 #define DMA_INT_INT11_WIDTH 1u
2678 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
2679 #define DMA_INT_INT12_MASK 0x1000u
2680 #define DMA_INT_INT12_SHIFT 12u
2681 #define DMA_INT_INT12_WIDTH 1u
2682 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
2683 #define DMA_INT_INT13_MASK 0x2000u
2684 #define DMA_INT_INT13_SHIFT 13u
2685 #define DMA_INT_INT13_WIDTH 1u
2686 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
2687 #define DMA_INT_INT14_MASK 0x4000u
2688 #define DMA_INT_INT14_SHIFT 14u
2689 #define DMA_INT_INT14_WIDTH 1u
2690 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
2691 #define DMA_INT_INT15_MASK 0x8000u
2692 #define DMA_INT_INT15_SHIFT 15u
2693 #define DMA_INT_INT15_WIDTH 1u
2694 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
2696 #define DMA_ERR_ERR0_MASK 0x1u
2697 #define DMA_ERR_ERR0_SHIFT 0u
2698 #define DMA_ERR_ERR0_WIDTH 1u
2699 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
2700 #define DMA_ERR_ERR1_MASK 0x2u
2701 #define DMA_ERR_ERR1_SHIFT 1u
2702 #define DMA_ERR_ERR1_WIDTH 1u
2703 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
2704 #define DMA_ERR_ERR2_MASK 0x4u
2705 #define DMA_ERR_ERR2_SHIFT 2u
2706 #define DMA_ERR_ERR2_WIDTH 1u
2707 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
2708 #define DMA_ERR_ERR3_MASK 0x8u
2709 #define DMA_ERR_ERR3_SHIFT 3u
2710 #define DMA_ERR_ERR3_WIDTH 1u
2711 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
2712 #define DMA_ERR_ERR4_MASK 0x10u
2713 #define DMA_ERR_ERR4_SHIFT 4u
2714 #define DMA_ERR_ERR4_WIDTH 1u
2715 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
2716 #define DMA_ERR_ERR5_MASK 0x20u
2717 #define DMA_ERR_ERR5_SHIFT 5u
2718 #define DMA_ERR_ERR5_WIDTH 1u
2719 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
2720 #define DMA_ERR_ERR6_MASK 0x40u
2721 #define DMA_ERR_ERR6_SHIFT 6u
2722 #define DMA_ERR_ERR6_WIDTH 1u
2723 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
2724 #define DMA_ERR_ERR7_MASK 0x80u
2725 #define DMA_ERR_ERR7_SHIFT 7u
2726 #define DMA_ERR_ERR7_WIDTH 1u
2727 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
2728 #define DMA_ERR_ERR8_MASK 0x100u
2729 #define DMA_ERR_ERR8_SHIFT 8u
2730 #define DMA_ERR_ERR8_WIDTH 1u
2731 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
2732 #define DMA_ERR_ERR9_MASK 0x200u
2733 #define DMA_ERR_ERR9_SHIFT 9u
2734 #define DMA_ERR_ERR9_WIDTH 1u
2735 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
2736 #define DMA_ERR_ERR10_MASK 0x400u
2737 #define DMA_ERR_ERR10_SHIFT 10u
2738 #define DMA_ERR_ERR10_WIDTH 1u
2739 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
2740 #define DMA_ERR_ERR11_MASK 0x800u
2741 #define DMA_ERR_ERR11_SHIFT 11u
2742 #define DMA_ERR_ERR11_WIDTH 1u
2743 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
2744 #define DMA_ERR_ERR12_MASK 0x1000u
2745 #define DMA_ERR_ERR12_SHIFT 12u
2746 #define DMA_ERR_ERR12_WIDTH 1u
2747 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
2748 #define DMA_ERR_ERR13_MASK 0x2000u
2749 #define DMA_ERR_ERR13_SHIFT 13u
2750 #define DMA_ERR_ERR13_WIDTH 1u
2751 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
2752 #define DMA_ERR_ERR14_MASK 0x4000u
2753 #define DMA_ERR_ERR14_SHIFT 14u
2754 #define DMA_ERR_ERR14_WIDTH 1u
2755 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
2756 #define DMA_ERR_ERR15_MASK 0x8000u
2757 #define DMA_ERR_ERR15_SHIFT 15u
2758 #define DMA_ERR_ERR15_WIDTH 1u
2759 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
2761 #define DMA_HRS_HRS0_MASK 0x1u
2762 #define DMA_HRS_HRS0_SHIFT 0u
2763 #define DMA_HRS_HRS0_WIDTH 1u
2764 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
2765 #define DMA_HRS_HRS1_MASK 0x2u
2766 #define DMA_HRS_HRS1_SHIFT 1u
2767 #define DMA_HRS_HRS1_WIDTH 1u
2768 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
2769 #define DMA_HRS_HRS2_MASK 0x4u
2770 #define DMA_HRS_HRS2_SHIFT 2u
2771 #define DMA_HRS_HRS2_WIDTH 1u
2772 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
2773 #define DMA_HRS_HRS3_MASK 0x8u
2774 #define DMA_HRS_HRS3_SHIFT 3u
2775 #define DMA_HRS_HRS3_WIDTH 1u
2776 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
2777 #define DMA_HRS_HRS4_MASK 0x10u
2778 #define DMA_HRS_HRS4_SHIFT 4u
2779 #define DMA_HRS_HRS4_WIDTH 1u
2780 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
2781 #define DMA_HRS_HRS5_MASK 0x20u
2782 #define DMA_HRS_HRS5_SHIFT 5u
2783 #define DMA_HRS_HRS5_WIDTH 1u
2784 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
2785 #define DMA_HRS_HRS6_MASK 0x40u
2786 #define DMA_HRS_HRS6_SHIFT 6u
2787 #define DMA_HRS_HRS6_WIDTH 1u
2788 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
2789 #define DMA_HRS_HRS7_MASK 0x80u
2790 #define DMA_HRS_HRS7_SHIFT 7u
2791 #define DMA_HRS_HRS7_WIDTH 1u
2792 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
2793 #define DMA_HRS_HRS8_MASK 0x100u
2794 #define DMA_HRS_HRS8_SHIFT 8u
2795 #define DMA_HRS_HRS8_WIDTH 1u
2796 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
2797 #define DMA_HRS_HRS9_MASK 0x200u
2798 #define DMA_HRS_HRS9_SHIFT 9u
2799 #define DMA_HRS_HRS9_WIDTH 1u
2800 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
2801 #define DMA_HRS_HRS10_MASK 0x400u
2802 #define DMA_HRS_HRS10_SHIFT 10u
2803 #define DMA_HRS_HRS10_WIDTH 1u
2804 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
2805 #define DMA_HRS_HRS11_MASK 0x800u
2806 #define DMA_HRS_HRS11_SHIFT 11u
2807 #define DMA_HRS_HRS11_WIDTH 1u
2808 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
2809 #define DMA_HRS_HRS12_MASK 0x1000u
2810 #define DMA_HRS_HRS12_SHIFT 12u
2811 #define DMA_HRS_HRS12_WIDTH 1u
2812 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
2813 #define DMA_HRS_HRS13_MASK 0x2000u
2814 #define DMA_HRS_HRS13_SHIFT 13u
2815 #define DMA_HRS_HRS13_WIDTH 1u
2816 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
2817 #define DMA_HRS_HRS14_MASK 0x4000u
2818 #define DMA_HRS_HRS14_SHIFT 14u
2819 #define DMA_HRS_HRS14_WIDTH 1u
2820 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
2821 #define DMA_HRS_HRS15_MASK 0x8000u
2822 #define DMA_HRS_HRS15_SHIFT 15u
2823 #define DMA_HRS_HRS15_WIDTH 1u
2824 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
2826 #define DMA_EARS_EDREQ_0_MASK 0x1u
2827 #define DMA_EARS_EDREQ_0_SHIFT 0u
2828 #define DMA_EARS_EDREQ_0_WIDTH 1u
2829 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
2830 #define DMA_EARS_EDREQ_1_MASK 0x2u
2831 #define DMA_EARS_EDREQ_1_SHIFT 1u
2832 #define DMA_EARS_EDREQ_1_WIDTH 1u
2833 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
2834 #define DMA_EARS_EDREQ_2_MASK 0x4u
2835 #define DMA_EARS_EDREQ_2_SHIFT 2u
2836 #define DMA_EARS_EDREQ_2_WIDTH 1u
2837 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
2838 #define DMA_EARS_EDREQ_3_MASK 0x8u
2839 #define DMA_EARS_EDREQ_3_SHIFT 3u
2840 #define DMA_EARS_EDREQ_3_WIDTH 1u
2841 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
2842 #define DMA_EARS_EDREQ_4_MASK 0x10u
2843 #define DMA_EARS_EDREQ_4_SHIFT 4u
2844 #define DMA_EARS_EDREQ_4_WIDTH 1u
2845 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
2846 #define DMA_EARS_EDREQ_5_MASK 0x20u
2847 #define DMA_EARS_EDREQ_5_SHIFT 5u
2848 #define DMA_EARS_EDREQ_5_WIDTH 1u
2849 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
2850 #define DMA_EARS_EDREQ_6_MASK 0x40u
2851 #define DMA_EARS_EDREQ_6_SHIFT 6u
2852 #define DMA_EARS_EDREQ_6_WIDTH 1u
2853 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
2854 #define DMA_EARS_EDREQ_7_MASK 0x80u
2855 #define DMA_EARS_EDREQ_7_SHIFT 7u
2856 #define DMA_EARS_EDREQ_7_WIDTH 1u
2857 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
2858 #define DMA_EARS_EDREQ_8_MASK 0x100u
2859 #define DMA_EARS_EDREQ_8_SHIFT 8u
2860 #define DMA_EARS_EDREQ_8_WIDTH 1u
2861 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
2862 #define DMA_EARS_EDREQ_9_MASK 0x200u
2863 #define DMA_EARS_EDREQ_9_SHIFT 9u
2864 #define DMA_EARS_EDREQ_9_WIDTH 1u
2865 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
2866 #define DMA_EARS_EDREQ_10_MASK 0x400u
2867 #define DMA_EARS_EDREQ_10_SHIFT 10u
2868 #define DMA_EARS_EDREQ_10_WIDTH 1u
2869 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
2870 #define DMA_EARS_EDREQ_11_MASK 0x800u
2871 #define DMA_EARS_EDREQ_11_SHIFT 11u
2872 #define DMA_EARS_EDREQ_11_WIDTH 1u
2873 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
2874 #define DMA_EARS_EDREQ_12_MASK 0x1000u
2875 #define DMA_EARS_EDREQ_12_SHIFT 12u
2876 #define DMA_EARS_EDREQ_12_WIDTH 1u
2877 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
2878 #define DMA_EARS_EDREQ_13_MASK 0x2000u
2879 #define DMA_EARS_EDREQ_13_SHIFT 13u
2880 #define DMA_EARS_EDREQ_13_WIDTH 1u
2881 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
2882 #define DMA_EARS_EDREQ_14_MASK 0x4000u
2883 #define DMA_EARS_EDREQ_14_SHIFT 14u
2884 #define DMA_EARS_EDREQ_14_WIDTH 1u
2885 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
2886 #define DMA_EARS_EDREQ_15_MASK 0x8000u
2887 #define DMA_EARS_EDREQ_15_SHIFT 15u
2888 #define DMA_EARS_EDREQ_15_WIDTH 1u
2889 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
2891 #define DMA_DCHPRI_CHPRI_MASK 0xFu
2892 #define DMA_DCHPRI_CHPRI_SHIFT 0u
2893 #define DMA_DCHPRI_CHPRI_WIDTH 4u
2894 #define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_CHPRI_SHIFT))&DMA_DCHPRI_CHPRI_MASK)
2895 #define DMA_DCHPRI_DPA_MASK 0x40u
2896 #define DMA_DCHPRI_DPA_SHIFT 6u
2897 #define DMA_DCHPRI_DPA_WIDTH 1u
2898 #define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_DPA_SHIFT))&DMA_DCHPRI_DPA_MASK)
2899 #define DMA_DCHPRI_ECP_MASK 0x80u
2900 #define DMA_DCHPRI_ECP_SHIFT 7u
2901 #define DMA_DCHPRI_ECP_WIDTH 1u
2902 #define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_ECP_SHIFT))&DMA_DCHPRI_ECP_MASK)
2904 #define DMA_TCD_SADDR_SADDR_MASK 0xFFFFFFFFu
2905 #define DMA_TCD_SADDR_SADDR_SHIFT 0u
2906 #define DMA_TCD_SADDR_SADDR_WIDTH 32u
2907 #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SADDR_SADDR_SHIFT))&DMA_TCD_SADDR_SADDR_MASK)
2909 #define DMA_TCD_SOFF_SOFF_MASK 0xFFFFu
2910 #define DMA_TCD_SOFF_SOFF_SHIFT 0u
2911 #define DMA_TCD_SOFF_SOFF_WIDTH 16u
2912 #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_SOFF_SOFF_SHIFT))&DMA_TCD_SOFF_SOFF_MASK)
2914 #define DMA_TCD_ATTR_DSIZE_MASK 0x7u
2915 #define DMA_TCD_ATTR_DSIZE_SHIFT 0u
2916 #define DMA_TCD_ATTR_DSIZE_WIDTH 3u
2917 #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DSIZE_SHIFT))&DMA_TCD_ATTR_DSIZE_MASK)
2918 #define DMA_TCD_ATTR_DMOD_MASK 0xF8u
2919 #define DMA_TCD_ATTR_DMOD_SHIFT 3u
2920 #define DMA_TCD_ATTR_DMOD_WIDTH 5u
2921 #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DMOD_SHIFT))&DMA_TCD_ATTR_DMOD_MASK)
2922 #define DMA_TCD_ATTR_SSIZE_MASK 0x700u
2923 #define DMA_TCD_ATTR_SSIZE_SHIFT 8u
2924 #define DMA_TCD_ATTR_SSIZE_WIDTH 3u
2925 #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SSIZE_SHIFT))&DMA_TCD_ATTR_SSIZE_MASK)
2926 #define DMA_TCD_ATTR_SMOD_MASK 0xF800u
2927 #define DMA_TCD_ATTR_SMOD_SHIFT 11u
2928 #define DMA_TCD_ATTR_SMOD_WIDTH 5u
2929 #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SMOD_SHIFT))&DMA_TCD_ATTR_SMOD_MASK)
2931 #define DMA_TCD_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
2932 #define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT 0u
2933 #define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH 32u
2934 #define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLNO_NBYTES_MASK)
2936 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
2937 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT 0u
2938 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH 30u
2939 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
2940 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
2941 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT 30u
2942 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH 1u
2943 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
2944 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
2945 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT 31u
2946 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH 1u
2947 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
2949 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
2950 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT 0u
2951 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH 10u
2952 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
2953 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
2954 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT 10u
2955 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH 20u
2956 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
2957 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
2958 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT 30u
2959 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH 1u
2960 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
2961 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
2962 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT 31u
2963 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH 1u
2964 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
2966 #define DMA_TCD_SLAST_SLAST_MASK 0xFFFFFFFFu
2967 #define DMA_TCD_SLAST_SLAST_SHIFT 0u
2968 #define DMA_TCD_SLAST_SLAST_WIDTH 32u
2969 #define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SLAST_SLAST_SHIFT))&DMA_TCD_SLAST_SLAST_MASK)
2971 #define DMA_TCD_DADDR_DADDR_MASK 0xFFFFFFFFu
2972 #define DMA_TCD_DADDR_DADDR_SHIFT 0u
2973 #define DMA_TCD_DADDR_DADDR_WIDTH 32u
2974 #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DADDR_DADDR_SHIFT))&DMA_TCD_DADDR_DADDR_MASK)
2976 #define DMA_TCD_DOFF_DOFF_MASK 0xFFFFu
2977 #define DMA_TCD_DOFF_DOFF_SHIFT 0u
2978 #define DMA_TCD_DOFF_DOFF_WIDTH 16u
2979 #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_DOFF_DOFF_SHIFT))&DMA_TCD_DOFF_DOFF_MASK)
2981 #define DMA_TCD_CITER_ELINKNO_CITER_MASK 0x7FFFu
2982 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT 0u
2983 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH 15u
2984 #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_CITER_SHIFT))&DMA_TCD_CITER_ELINKNO_CITER_MASK)
2985 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK 0x8000u
2986 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT 15u
2987 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH 1u
2988 #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_CITER_ELINKNO_ELINK_MASK)
2990 #define DMA_TCD_CITER_ELINKYES_CITER_LE_MASK 0x1FFu
2991 #define DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT 0u
2992 #define DMA_TCD_CITER_ELINKYES_CITER_LE_WIDTH 9u
2993 #define DMA_TCD_CITER_ELINKYES_CITER_LE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT))&DMA_TCD_CITER_ELINKYES_CITER_LE_MASK)
2994 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00u
2995 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT 9u
2996 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH 4u
2997 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
2998 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK 0x8000u
2999 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT 15u
3000 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH 1u
3001 #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_CITER_ELINKYES_ELINK_MASK)
3003 #define DMA_TCD_DLASTSGA_DLASTSGA_MASK 0xFFFFFFFFu
3004 #define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT 0u
3005 #define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH 32u
3006 #define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DLASTSGA_DLASTSGA_SHIFT))&DMA_TCD_DLASTSGA_DLASTSGA_MASK)
3008 #define DMA_TCD_CSR_START_MASK 0x1u
3009 #define DMA_TCD_CSR_START_SHIFT 0u
3010 #define DMA_TCD_CSR_START_WIDTH 1u
3011 #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_START_SHIFT))&DMA_TCD_CSR_START_MASK)
3012 #define DMA_TCD_CSR_INTMAJOR_MASK 0x2u
3013 #define DMA_TCD_CSR_INTMAJOR_SHIFT 1u
3014 #define DMA_TCD_CSR_INTMAJOR_WIDTH 1u
3015 #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTMAJOR_SHIFT))&DMA_TCD_CSR_INTMAJOR_MASK)
3016 #define DMA_TCD_CSR_INTHALF_MASK 0x4u
3017 #define DMA_TCD_CSR_INTHALF_SHIFT 2u
3018 #define DMA_TCD_CSR_INTHALF_WIDTH 1u
3019 #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTHALF_SHIFT))&DMA_TCD_CSR_INTHALF_MASK)
3020 #define DMA_TCD_CSR_DREQ_MASK 0x8u
3021 #define DMA_TCD_CSR_DREQ_SHIFT 3u
3022 #define DMA_TCD_CSR_DREQ_WIDTH 1u
3023 #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DREQ_SHIFT))&DMA_TCD_CSR_DREQ_MASK)
3024 #define DMA_TCD_CSR_ESG_MASK 0x10u
3025 #define DMA_TCD_CSR_ESG_SHIFT 4u
3026 #define DMA_TCD_CSR_ESG_WIDTH 1u
3027 #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ESG_SHIFT))&DMA_TCD_CSR_ESG_MASK)
3028 #define DMA_TCD_CSR_MAJORELINK_MASK 0x20u
3029 #define DMA_TCD_CSR_MAJORELINK_SHIFT 5u
3030 #define DMA_TCD_CSR_MAJORELINK_WIDTH 1u
3031 #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORELINK_SHIFT))&DMA_TCD_CSR_MAJORELINK_MASK)
3032 #define DMA_TCD_CSR_ACTIVE_MASK 0x40u
3033 #define DMA_TCD_CSR_ACTIVE_SHIFT 6u
3034 #define DMA_TCD_CSR_ACTIVE_WIDTH 1u
3035 #define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ACTIVE_SHIFT))&DMA_TCD_CSR_ACTIVE_MASK)
3036 #define DMA_TCD_CSR_DONE_MASK 0x80u
3037 #define DMA_TCD_CSR_DONE_SHIFT 7u
3038 #define DMA_TCD_CSR_DONE_WIDTH 1u
3039 #define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DONE_SHIFT))&DMA_TCD_CSR_DONE_MASK)
3040 #define DMA_TCD_CSR_MAJORLINKCH_MASK 0xF00u
3041 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT 8u
3042 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH 4u
3043 #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORLINKCH_SHIFT))&DMA_TCD_CSR_MAJORLINKCH_MASK)
3044 #define DMA_TCD_CSR_BWC_MASK 0xC000u
3045 #define DMA_TCD_CSR_BWC_SHIFT 14u
3046 #define DMA_TCD_CSR_BWC_WIDTH 2u
3047 #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_BWC_SHIFT))&DMA_TCD_CSR_BWC_MASK)
3049 #define DMA_TCD_BITER_ELINKNO_BITER_MASK 0x7FFFu
3050 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT 0u
3051 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH 15u
3052 #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_BITER_SHIFT))&DMA_TCD_BITER_ELINKNO_BITER_MASK)
3053 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK 0x8000u
3054 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT 15u
3055 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH 1u
3056 #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_BITER_ELINKNO_ELINK_MASK)
3058 #define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x1FFu
3059 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT 0u
3060 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH 9u
3061 #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_BITER_SHIFT))&DMA_TCD_BITER_ELINKYES_BITER_MASK)
3062 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00u
3063 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT 9u
3064 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH 4u
3065 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
3066 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK 0x8000u
3067 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT 15u
3068 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH 1u
3069 #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_BITER_ELINKYES_ELINK_MASK)
3092 #define DMAMUX_CHCFG_COUNT 16u
3100 #define DMAMUX_INSTANCE_COUNT (1u)
3105 #define DMAMUX_BASE (0x40021000u)
3107 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3109 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
3111 #define DMAMUX_BASE_PTRS { DMAMUX }
3123 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
3124 #define DMAMUX_CHCFG_SOURCE_SHIFT 0u
3125 #define DMAMUX_CHCFG_SOURCE_WIDTH 6u
3126 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
3127 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
3128 #define DMAMUX_CHCFG_TRIG_SHIFT 6u
3129 #define DMAMUX_CHCFG_TRIG_WIDTH 1u
3130 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
3131 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
3132 #define DMAMUX_CHCFG_ENBL_SHIFT 7u
3133 #define DMAMUX_CHCFG_ENBL_WIDTH 1u
3134 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
3157 #define EIM_EICHDn_COUNT 2u
3163 uint8_t RESERVED_0[248];
3167 uint8_t RESERVED_0[248];
3172 #define EIM_INSTANCE_COUNT (1u)
3177 #define EIM_BASE (0x40019000u)
3179 #define EIM ((EIM_Type *)EIM_BASE)
3181 #define EIM_BASE_ADDRS { EIM_BASE }
3183 #define EIM_BASE_PTRS { EIM }
3195 #define EIM_EIMCR_GEIEN_MASK 0x1u
3196 #define EIM_EIMCR_GEIEN_SHIFT 0u
3197 #define EIM_EIMCR_GEIEN_WIDTH 1u
3198 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EIMCR_GEIEN_SHIFT))&EIM_EIMCR_GEIEN_MASK)
3200 #define EIM_EICHEN_EICH1EN_MASK 0x40000000u
3201 #define EIM_EICHEN_EICH1EN_SHIFT 30u
3202 #define EIM_EICHEN_EICH1EN_WIDTH 1u
3203 #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH1EN_SHIFT))&EIM_EICHEN_EICH1EN_MASK)
3204 #define EIM_EICHEN_EICH0EN_MASK 0x80000000u
3205 #define EIM_EICHEN_EICH0EN_SHIFT 31u
3206 #define EIM_EICHEN_EICH0EN_WIDTH 1u
3207 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH0EN_SHIFT))&EIM_EICHEN_EICH0EN_MASK)
3209 #define EIM_EICHDn_WORD0_CHKBIT_MASK_MASK 0xFE000000u
3210 #define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT 25u
3211 #define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH 7u
3212 #define EIM_EICHDn_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT))&EIM_EICHDn_WORD0_CHKBIT_MASK_MASK)
3214 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK 0xFFFFFFFFu
3215 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT 0u
3216 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_WIDTH 32u
3217 #define EIM_EICHDn_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT))&EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK)
3240 #define ENET_CHANNEL_COUNT 4u
3244 uint8_t RESERVED_0[4];
3247 uint8_t RESERVED_1[4];
3250 uint8_t RESERVED_2[12];
3252 uint8_t RESERVED_3[24];
3255 uint8_t RESERVED_4[28];
3257 uint8_t RESERVED_5[28];
3259 uint8_t RESERVED_6[60];
3261 uint8_t RESERVED_7[28];
3265 uint8_t RESERVED_8[40];
3270 uint8_t RESERVED_9[28];
3272 uint8_t RESERVED_10[56];
3276 uint8_t RESERVED_11[4];
3286 uint8_t RESERVED_12[12];
3289 uint8_t RESERVED_13[56];
3320 uint8_t RESERVED_14[12];
3345 uint8_t RESERVED_15[284];
3353 uint8_t RESERVED_16[488];
3362 #define ENET_INSTANCE_COUNT (1u)
3367 #define ENET_BASE (0x40079000u)
3369 #define ENET ((ENET_Type *)ENET_BASE)
3371 #define ENET_BASE_ADDRS { ENET_BASE }
3373 #define ENET_BASE_PTRS { ENET }
3375 #define ENET_IRQS_ARR_COUNT (6u)
3377 #define ENET_TIMER_IRQS_CH_COUNT (1u)
3379 #define ENET_TX_IRQS_CH_COUNT (1u)
3381 #define ENET_RX_IRQS_CH_COUNT (1u)
3383 #define ENET_ERR_IRQS_CH_COUNT (1u)
3385 #define ENET_STOP_IRQS_CH_COUNT (1u)
3387 #define ENET_WAKE_IRQS_CH_COUNT (1u)
3389 #define ENET_TIMER_IRQS { ENET_TIMER_IRQn }
3390 #define ENET_TX_IRQS { ENET_TX_IRQn }
3391 #define ENET_RX_IRQS { ENET_RX_IRQn }
3392 #define ENET_ERR_IRQS { ENET_ERR_IRQn }
3393 #define ENET_STOP_IRQS { ENET_STOP_IRQn }
3394 #define ENET_WAKE_IRQS { ENET_WAKE_IRQn }
3406 #define ENET_EIR_TS_TIMER_MASK 0x8000u
3407 #define ENET_EIR_TS_TIMER_SHIFT 15u
3408 #define ENET_EIR_TS_TIMER_WIDTH 1u
3409 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_TIMER_SHIFT))&ENET_EIR_TS_TIMER_MASK)
3410 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
3411 #define ENET_EIR_TS_AVAIL_SHIFT 16u
3412 #define ENET_EIR_TS_AVAIL_WIDTH 1u
3413 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TS_AVAIL_SHIFT))&ENET_EIR_TS_AVAIL_MASK)
3414 #define ENET_EIR_WAKEUP_MASK 0x20000u
3415 #define ENET_EIR_WAKEUP_SHIFT 17u
3416 #define ENET_EIR_WAKEUP_WIDTH 1u
3417 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_WAKEUP_SHIFT))&ENET_EIR_WAKEUP_MASK)
3418 #define ENET_EIR_PLR_MASK 0x40000u
3419 #define ENET_EIR_PLR_SHIFT 18u
3420 #define ENET_EIR_PLR_WIDTH 1u
3421 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_PLR_SHIFT))&ENET_EIR_PLR_MASK)
3422 #define ENET_EIR_UN_MASK 0x80000u
3423 #define ENET_EIR_UN_SHIFT 19u
3424 #define ENET_EIR_UN_WIDTH 1u
3425 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_UN_SHIFT))&ENET_EIR_UN_MASK)
3426 #define ENET_EIR_RL_MASK 0x100000u
3427 #define ENET_EIR_RL_SHIFT 20u
3428 #define ENET_EIR_RL_WIDTH 1u
3429 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RL_SHIFT))&ENET_EIR_RL_MASK)
3430 #define ENET_EIR_LC_MASK 0x200000u
3431 #define ENET_EIR_LC_SHIFT 21u
3432 #define ENET_EIR_LC_WIDTH 1u
3433 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_LC_SHIFT))&ENET_EIR_LC_MASK)
3434 #define ENET_EIR_EBERR_MASK 0x400000u
3435 #define ENET_EIR_EBERR_SHIFT 22u
3436 #define ENET_EIR_EBERR_WIDTH 1u
3437 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_EBERR_SHIFT))&ENET_EIR_EBERR_MASK)
3438 #define ENET_EIR_MII_MASK 0x800000u
3439 #define ENET_EIR_MII_SHIFT 23u
3440 #define ENET_EIR_MII_WIDTH 1u
3441 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_MII_SHIFT))&ENET_EIR_MII_MASK)
3442 #define ENET_EIR_RXB_MASK 0x1000000u
3443 #define ENET_EIR_RXB_SHIFT 24u
3444 #define ENET_EIR_RXB_WIDTH 1u
3445 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXB_SHIFT))&ENET_EIR_RXB_MASK)
3446 #define ENET_EIR_RXF_MASK 0x2000000u
3447 #define ENET_EIR_RXF_SHIFT 25u
3448 #define ENET_EIR_RXF_WIDTH 1u
3449 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_RXF_SHIFT))&ENET_EIR_RXF_MASK)
3450 #define ENET_EIR_TXB_MASK 0x4000000u
3451 #define ENET_EIR_TXB_SHIFT 26u
3452 #define ENET_EIR_TXB_WIDTH 1u
3453 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXB_SHIFT))&ENET_EIR_TXB_MASK)
3454 #define ENET_EIR_TXF_MASK 0x8000000u
3455 #define ENET_EIR_TXF_SHIFT 27u
3456 #define ENET_EIR_TXF_WIDTH 1u
3457 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_TXF_SHIFT))&ENET_EIR_TXF_MASK)
3458 #define ENET_EIR_GRA_MASK 0x10000000u
3459 #define ENET_EIR_GRA_SHIFT 28u
3460 #define ENET_EIR_GRA_WIDTH 1u
3461 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_GRA_SHIFT))&ENET_EIR_GRA_MASK)
3462 #define ENET_EIR_BABT_MASK 0x20000000u
3463 #define ENET_EIR_BABT_SHIFT 29u
3464 #define ENET_EIR_BABT_WIDTH 1u
3465 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABT_SHIFT))&ENET_EIR_BABT_MASK)
3466 #define ENET_EIR_BABR_MASK 0x40000000u
3467 #define ENET_EIR_BABR_SHIFT 30u
3468 #define ENET_EIR_BABR_WIDTH 1u
3469 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIR_BABR_SHIFT))&ENET_EIR_BABR_MASK)
3471 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
3472 #define ENET_EIMR_TS_TIMER_SHIFT 15u
3473 #define ENET_EIMR_TS_TIMER_WIDTH 1u
3474 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_TIMER_SHIFT))&ENET_EIMR_TS_TIMER_MASK)
3475 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
3476 #define ENET_EIMR_TS_AVAIL_SHIFT 16u
3477 #define ENET_EIMR_TS_AVAIL_WIDTH 1u
3478 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TS_AVAIL_SHIFT))&ENET_EIMR_TS_AVAIL_MASK)
3479 #define ENET_EIMR_WAKEUP_MASK 0x20000u
3480 #define ENET_EIMR_WAKEUP_SHIFT 17u
3481 #define ENET_EIMR_WAKEUP_WIDTH 1u
3482 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_WAKEUP_SHIFT))&ENET_EIMR_WAKEUP_MASK)
3483 #define ENET_EIMR_PLR_MASK 0x40000u
3484 #define ENET_EIMR_PLR_SHIFT 18u
3485 #define ENET_EIMR_PLR_WIDTH 1u
3486 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_PLR_SHIFT))&ENET_EIMR_PLR_MASK)
3487 #define ENET_EIMR_UN_MASK 0x80000u
3488 #define ENET_EIMR_UN_SHIFT 19u
3489 #define ENET_EIMR_UN_WIDTH 1u
3490 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_UN_SHIFT))&ENET_EIMR_UN_MASK)
3491 #define ENET_EIMR_RL_MASK 0x100000u
3492 #define ENET_EIMR_RL_SHIFT 20u
3493 #define ENET_EIMR_RL_WIDTH 1u
3494 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RL_SHIFT))&ENET_EIMR_RL_MASK)
3495 #define ENET_EIMR_LC_MASK 0x200000u
3496 #define ENET_EIMR_LC_SHIFT 21u
3497 #define ENET_EIMR_LC_WIDTH 1u
3498 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_LC_SHIFT))&ENET_EIMR_LC_MASK)
3499 #define ENET_EIMR_EBERR_MASK 0x400000u
3500 #define ENET_EIMR_EBERR_SHIFT 22u
3501 #define ENET_EIMR_EBERR_WIDTH 1u
3502 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_EBERR_SHIFT))&ENET_EIMR_EBERR_MASK)
3503 #define ENET_EIMR_MII_MASK 0x800000u
3504 #define ENET_EIMR_MII_SHIFT 23u
3505 #define ENET_EIMR_MII_WIDTH 1u
3506 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_MII_SHIFT))&ENET_EIMR_MII_MASK)
3507 #define ENET_EIMR_RXB_MASK 0x1000000u
3508 #define ENET_EIMR_RXB_SHIFT 24u
3509 #define ENET_EIMR_RXB_WIDTH 1u
3510 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXB_SHIFT))&ENET_EIMR_RXB_MASK)
3511 #define ENET_EIMR_RXF_MASK 0x2000000u
3512 #define ENET_EIMR_RXF_SHIFT 25u
3513 #define ENET_EIMR_RXF_WIDTH 1u
3514 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_RXF_SHIFT))&ENET_EIMR_RXF_MASK)
3515 #define ENET_EIMR_TXB_MASK 0x4000000u
3516 #define ENET_EIMR_TXB_SHIFT 26u
3517 #define ENET_EIMR_TXB_WIDTH 1u
3518 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXB_SHIFT))&ENET_EIMR_TXB_MASK)
3519 #define ENET_EIMR_TXF_MASK 0x8000000u
3520 #define ENET_EIMR_TXF_SHIFT 27u
3521 #define ENET_EIMR_TXF_WIDTH 1u
3522 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_TXF_SHIFT))&ENET_EIMR_TXF_MASK)
3523 #define ENET_EIMR_GRA_MASK 0x10000000u
3524 #define ENET_EIMR_GRA_SHIFT 28u
3525 #define ENET_EIMR_GRA_WIDTH 1u
3526 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_GRA_SHIFT))&ENET_EIMR_GRA_MASK)
3527 #define ENET_EIMR_BABT_MASK 0x20000000u
3528 #define ENET_EIMR_BABT_SHIFT 29u
3529 #define ENET_EIMR_BABT_WIDTH 1u
3530 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABT_SHIFT))&ENET_EIMR_BABT_MASK)
3531 #define ENET_EIMR_BABR_MASK 0x40000000u
3532 #define ENET_EIMR_BABR_SHIFT 30u
3533 #define ENET_EIMR_BABR_WIDTH 1u
3534 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x))<<ENET_EIMR_BABR_SHIFT))&ENET_EIMR_BABR_MASK)
3536 #define ENET_RDAR_RDAR_MASK 0x1000000u
3537 #define ENET_RDAR_RDAR_SHIFT 24u
3538 #define ENET_RDAR_RDAR_WIDTH 1u
3539 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDAR_RDAR_SHIFT))&ENET_RDAR_RDAR_MASK)
3541 #define ENET_TDAR_TDAR_MASK 0x1000000u
3542 #define ENET_TDAR_TDAR_SHIFT 24u
3543 #define ENET_TDAR_TDAR_WIDTH 1u
3544 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDAR_TDAR_SHIFT))&ENET_TDAR_TDAR_MASK)
3546 #define ENET_ECR_RESET_MASK 0x1u
3547 #define ENET_ECR_RESET_SHIFT 0u
3548 #define ENET_ECR_RESET_WIDTH 1u
3549 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_RESET_SHIFT))&ENET_ECR_RESET_MASK)
3550 #define ENET_ECR_ETHEREN_MASK 0x2u
3551 #define ENET_ECR_ETHEREN_SHIFT 1u
3552 #define ENET_ECR_ETHEREN_WIDTH 1u
3553 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_ETHEREN_SHIFT))&ENET_ECR_ETHEREN_MASK)
3554 #define ENET_ECR_MAGICEN_MASK 0x4u
3555 #define ENET_ECR_MAGICEN_SHIFT 2u
3556 #define ENET_ECR_MAGICEN_WIDTH 1u
3557 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_MAGICEN_SHIFT))&ENET_ECR_MAGICEN_MASK)
3558 #define ENET_ECR_SLEEP_MASK 0x8u
3559 #define ENET_ECR_SLEEP_SHIFT 3u
3560 #define ENET_ECR_SLEEP_WIDTH 1u
3561 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_SLEEP_SHIFT))&ENET_ECR_SLEEP_MASK)
3562 #define ENET_ECR_EN1588_MASK 0x10u
3563 #define ENET_ECR_EN1588_SHIFT 4u
3564 #define ENET_ECR_EN1588_WIDTH 1u
3565 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_EN1588_SHIFT))&ENET_ECR_EN1588_MASK)
3566 #define ENET_ECR_DBGEN_MASK 0x40u
3567 #define ENET_ECR_DBGEN_SHIFT 6u
3568 #define ENET_ECR_DBGEN_WIDTH 1u
3569 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBGEN_SHIFT))&ENET_ECR_DBGEN_MASK)
3570 #define ENET_ECR_DBSWP_MASK 0x100u
3571 #define ENET_ECR_DBSWP_SHIFT 8u
3572 #define ENET_ECR_DBSWP_WIDTH 1u
3573 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ECR_DBSWP_SHIFT))&ENET_ECR_DBSWP_MASK)
3575 #define ENET_MMFR_DATA_MASK 0xFFFFu
3576 #define ENET_MMFR_DATA_SHIFT 0u
3577 #define ENET_MMFR_DATA_WIDTH 16u
3578 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
3579 #define ENET_MMFR_TA_MASK 0x30000u
3580 #define ENET_MMFR_TA_SHIFT 16u
3581 #define ENET_MMFR_TA_WIDTH 2u
3582 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
3583 #define ENET_MMFR_RA_MASK 0x7C0000u
3584 #define ENET_MMFR_RA_SHIFT 18u
3585 #define ENET_MMFR_RA_WIDTH 5u
3586 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
3587 #define ENET_MMFR_PA_MASK 0xF800000u
3588 #define ENET_MMFR_PA_SHIFT 23u
3589 #define ENET_MMFR_PA_WIDTH 5u
3590 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
3591 #define ENET_MMFR_OP_MASK 0x30000000u
3592 #define ENET_MMFR_OP_SHIFT 28u
3593 #define ENET_MMFR_OP_WIDTH 2u
3594 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
3595 #define ENET_MMFR_ST_MASK 0xC0000000u
3596 #define ENET_MMFR_ST_SHIFT 30u
3597 #define ENET_MMFR_ST_WIDTH 2u
3598 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
3600 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
3601 #define ENET_MSCR_MII_SPEED_SHIFT 1u
3602 #define ENET_MSCR_MII_SPEED_WIDTH 6u
3603 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
3604 #define ENET_MSCR_DIS_PRE_MASK 0x80u
3605 #define ENET_MSCR_DIS_PRE_SHIFT 7u
3606 #define ENET_MSCR_DIS_PRE_WIDTH 1u
3607 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_DIS_PRE_SHIFT))&ENET_MSCR_DIS_PRE_MASK)
3608 #define ENET_MSCR_HOLDTIME_MASK 0x700u
3609 #define ENET_MSCR_HOLDTIME_SHIFT 8u
3610 #define ENET_MSCR_HOLDTIME_WIDTH 3u
3611 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
3613 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
3614 #define ENET_MIBC_MIB_CLEAR_SHIFT 29u
3615 #define ENET_MIBC_MIB_CLEAR_WIDTH 1u
3616 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_CLEAR_SHIFT))&ENET_MIBC_MIB_CLEAR_MASK)
3617 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
3618 #define ENET_MIBC_MIB_IDLE_SHIFT 30u
3619 #define ENET_MIBC_MIB_IDLE_WIDTH 1u
3620 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_IDLE_SHIFT))&ENET_MIBC_MIB_IDLE_MASK)
3621 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
3622 #define ENET_MIBC_MIB_DIS_SHIFT 31u
3623 #define ENET_MIBC_MIB_DIS_WIDTH 1u
3624 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_MIBC_MIB_DIS_SHIFT))&ENET_MIBC_MIB_DIS_MASK)
3626 #define ENET_RCR_LOOP_MASK 0x1u
3627 #define ENET_RCR_LOOP_SHIFT 0u
3628 #define ENET_RCR_LOOP_WIDTH 1u
3629 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_LOOP_SHIFT))&ENET_RCR_LOOP_MASK)
3630 #define ENET_RCR_DRT_MASK 0x2u
3631 #define ENET_RCR_DRT_SHIFT 1u
3632 #define ENET_RCR_DRT_WIDTH 1u
3633 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_DRT_SHIFT))&ENET_RCR_DRT_MASK)
3634 #define ENET_RCR_MII_MODE_MASK 0x4u
3635 #define ENET_RCR_MII_MODE_SHIFT 2u
3636 #define ENET_RCR_MII_MODE_WIDTH 1u
3637 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MII_MODE_SHIFT))&ENET_RCR_MII_MODE_MASK)
3638 #define ENET_RCR_PROM_MASK 0x8u
3639 #define ENET_RCR_PROM_SHIFT 3u
3640 #define ENET_RCR_PROM_WIDTH 1u
3641 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PROM_SHIFT))&ENET_RCR_PROM_MASK)
3642 #define ENET_RCR_BC_REJ_MASK 0x10u
3643 #define ENET_RCR_BC_REJ_SHIFT 4u
3644 #define ENET_RCR_BC_REJ_WIDTH 1u
3645 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_BC_REJ_SHIFT))&ENET_RCR_BC_REJ_MASK)
3646 #define ENET_RCR_FCE_MASK 0x20u
3647 #define ENET_RCR_FCE_SHIFT 5u
3648 #define ENET_RCR_FCE_WIDTH 1u
3649 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_FCE_SHIFT))&ENET_RCR_FCE_MASK)
3650 #define ENET_RCR_RMII_MODE_MASK 0x100u
3651 #define ENET_RCR_RMII_MODE_SHIFT 8u
3652 #define ENET_RCR_RMII_MODE_WIDTH 1u
3653 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_MODE_SHIFT))&ENET_RCR_RMII_MODE_MASK)
3654 #define ENET_RCR_RMII_10T_MASK 0x200u
3655 #define ENET_RCR_RMII_10T_SHIFT 9u
3656 #define ENET_RCR_RMII_10T_WIDTH 1u
3657 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_RMII_10T_SHIFT))&ENET_RCR_RMII_10T_MASK)
3658 #define ENET_RCR_PADEN_MASK 0x1000u
3659 #define ENET_RCR_PADEN_SHIFT 12u
3660 #define ENET_RCR_PADEN_WIDTH 1u
3661 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PADEN_SHIFT))&ENET_RCR_PADEN_MASK)
3662 #define ENET_RCR_PAUFWD_MASK 0x2000u
3663 #define ENET_RCR_PAUFWD_SHIFT 13u
3664 #define ENET_RCR_PAUFWD_WIDTH 1u
3665 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_PAUFWD_SHIFT))&ENET_RCR_PAUFWD_MASK)
3666 #define ENET_RCR_CRCFWD_MASK 0x4000u
3667 #define ENET_RCR_CRCFWD_SHIFT 14u
3668 #define ENET_RCR_CRCFWD_WIDTH 1u
3669 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CRCFWD_SHIFT))&ENET_RCR_CRCFWD_MASK)
3670 #define ENET_RCR_CFEN_MASK 0x8000u
3671 #define ENET_RCR_CFEN_SHIFT 15u
3672 #define ENET_RCR_CFEN_WIDTH 1u
3673 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_CFEN_SHIFT))&ENET_RCR_CFEN_MASK)
3674 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
3675 #define ENET_RCR_MAX_FL_SHIFT 16u
3676 #define ENET_RCR_MAX_FL_WIDTH 14u
3677 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
3678 #define ENET_RCR_NLC_MASK 0x40000000u
3679 #define ENET_RCR_NLC_SHIFT 30u
3680 #define ENET_RCR_NLC_WIDTH 1u
3681 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_NLC_SHIFT))&ENET_RCR_NLC_MASK)
3682 #define ENET_RCR_GRS_MASK 0x80000000u
3683 #define ENET_RCR_GRS_SHIFT 31u
3684 #define ENET_RCR_GRS_WIDTH 1u
3685 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_GRS_SHIFT))&ENET_RCR_GRS_MASK)
3687 #define ENET_TCR_GTS_MASK 0x1u
3688 #define ENET_TCR_GTS_SHIFT 0u
3689 #define ENET_TCR_GTS_WIDTH 1u
3690 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_GTS_SHIFT))&ENET_TCR_GTS_MASK)
3691 #define ENET_TCR_FDEN_MASK 0x4u
3692 #define ENET_TCR_FDEN_SHIFT 2u
3693 #define ENET_TCR_FDEN_WIDTH 1u
3694 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_FDEN_SHIFT))&ENET_TCR_FDEN_MASK)
3695 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
3696 #define ENET_TCR_TFC_PAUSE_SHIFT 3u
3697 #define ENET_TCR_TFC_PAUSE_WIDTH 1u
3698 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_TFC_PAUSE_SHIFT))&ENET_TCR_TFC_PAUSE_MASK)
3699 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
3700 #define ENET_TCR_RFC_PAUSE_SHIFT 4u
3701 #define ENET_TCR_RFC_PAUSE_WIDTH 1u
3702 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_RFC_PAUSE_SHIFT))&ENET_TCR_RFC_PAUSE_MASK)
3703 #define ENET_TCR_ADDSEL_MASK 0xE0u
3704 #define ENET_TCR_ADDSEL_SHIFT 5u
3705 #define ENET_TCR_ADDSEL_WIDTH 3u
3706 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
3707 #define ENET_TCR_ADDINS_MASK 0x100u
3708 #define ENET_TCR_ADDINS_SHIFT 8u
3709 #define ENET_TCR_ADDINS_WIDTH 1u
3710 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDINS_SHIFT))&ENET_TCR_ADDINS_MASK)
3711 #define ENET_TCR_CRCFWD_MASK 0x200u
3712 #define ENET_TCR_CRCFWD_SHIFT 9u
3713 #define ENET_TCR_CRCFWD_WIDTH 1u
3714 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_CRCFWD_SHIFT))&ENET_TCR_CRCFWD_MASK)
3716 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
3717 #define ENET_PALR_PADDR1_SHIFT 0u
3718 #define ENET_PALR_PADDR1_WIDTH 32u
3719 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
3721 #define ENET_PAUR_TYPE_MASK 0xFFFFu
3722 #define ENET_PAUR_TYPE_SHIFT 0u
3723 #define ENET_PAUR_TYPE_WIDTH 16u
3724 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
3725 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
3726 #define ENET_PAUR_PADDR2_SHIFT 16u
3727 #define ENET_PAUR_PADDR2_WIDTH 16u
3728 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
3730 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
3731 #define ENET_OPD_PAUSE_DUR_SHIFT 0u
3732 #define ENET_OPD_PAUSE_DUR_WIDTH 16u
3733 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
3734 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
3735 #define ENET_OPD_OPCODE_SHIFT 16u
3736 #define ENET_OPD_OPCODE_WIDTH 16u
3737 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
3739 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
3740 #define ENET_IAUR_IADDR1_SHIFT 0u
3741 #define ENET_IAUR_IADDR1_WIDTH 32u
3742 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
3744 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
3745 #define ENET_IALR_IADDR2_SHIFT 0u
3746 #define ENET_IALR_IADDR2_WIDTH 32u
3747 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
3749 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
3750 #define ENET_GAUR_GADDR1_SHIFT 0u
3751 #define ENET_GAUR_GADDR1_WIDTH 32u
3752 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
3754 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
3755 #define ENET_GALR_GADDR2_SHIFT 0u
3756 #define ENET_GALR_GADDR2_WIDTH 32u
3757 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
3759 #define ENET_TFWR_TFWR_MASK 0x3Fu
3760 #define ENET_TFWR_TFWR_SHIFT 0u
3761 #define ENET_TFWR_TFWR_WIDTH 6u
3762 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
3763 #define ENET_TFWR_STRFWD_MASK 0x100u
3764 #define ENET_TFWR_STRFWD_SHIFT 8u
3765 #define ENET_TFWR_STRFWD_WIDTH 1u
3766 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_STRFWD_SHIFT))&ENET_TFWR_STRFWD_MASK)
3768 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
3769 #define ENET_RDSR_R_DES_START_SHIFT 3u
3770 #define ENET_RDSR_R_DES_START_WIDTH 29u
3771 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
3773 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
3774 #define ENET_TDSR_X_DES_START_SHIFT 3u
3775 #define ENET_TDSR_X_DES_START_WIDTH 29u
3776 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
3778 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
3779 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4u
3780 #define ENET_MRBR_R_BUF_SIZE_WIDTH 10u
3781 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
3783 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
3784 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0u
3785 #define ENET_RSFL_RX_SECTION_FULL_WIDTH 8u
3786 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
3788 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
3789 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0u
3790 #define ENET_RSEM_RX_SECTION_EMPTY_WIDTH 8u
3791 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
3792 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
3793 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16u
3794 #define ENET_RSEM_STAT_SECTION_EMPTY_WIDTH 5u
3795 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
3797 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
3798 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0u
3799 #define ENET_RAEM_RX_ALMOST_EMPTY_WIDTH 8u
3800 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
3802 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
3803 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0u
3804 #define ENET_RAFL_RX_ALMOST_FULL_WIDTH 8u
3805 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
3807 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
3808 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0u
3809 #define ENET_TSEM_TX_SECTION_EMPTY_WIDTH 8u
3810 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
3812 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
3813 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0u
3814 #define ENET_TAEM_TX_ALMOST_EMPTY_WIDTH 8u
3815 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
3817 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
3818 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0u
3819 #define ENET_TAFL_TX_ALMOST_FULL_WIDTH 8u
3820 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
3822 #define ENET_TIPG_IPG_MASK 0x1Fu
3823 #define ENET_TIPG_IPG_SHIFT 0u
3824 #define ENET_TIPG_IPG_WIDTH 5u
3825 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
3827 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
3828 #define ENET_FTRL_TRUNC_FL_SHIFT 0u
3829 #define ENET_FTRL_TRUNC_FL_WIDTH 14u
3830 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
3832 #define ENET_TACC_SHIFT16_MASK 0x1u
3833 #define ENET_TACC_SHIFT16_SHIFT 0u
3834 #define ENET_TACC_SHIFT16_WIDTH 1u
3835 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x))<<ENET_TACC_SHIFT16_SHIFT))&ENET_TACC_SHIFT16_MASK)
3836 #define ENET_TACC_IPCHK_MASK 0x8u
3837 #define ENET_TACC_IPCHK_SHIFT 3u
3838 #define ENET_TACC_IPCHK_WIDTH 1u
3839 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x))<<ENET_TACC_IPCHK_SHIFT))&ENET_TACC_IPCHK_MASK)
3840 #define ENET_TACC_PROCHK_MASK 0x10u
3841 #define ENET_TACC_PROCHK_SHIFT 4u
3842 #define ENET_TACC_PROCHK_WIDTH 1u
3843 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x))<<ENET_TACC_PROCHK_SHIFT))&ENET_TACC_PROCHK_MASK)
3845 #define ENET_RACC_PADREM_MASK 0x1u
3846 #define ENET_RACC_PADREM_SHIFT 0u
3847 #define ENET_RACC_PADREM_WIDTH 1u
3848 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PADREM_SHIFT))&ENET_RACC_PADREM_MASK)
3849 #define ENET_RACC_IPDIS_MASK 0x2u
3850 #define ENET_RACC_IPDIS_SHIFT 1u
3851 #define ENET_RACC_IPDIS_WIDTH 1u
3852 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_IPDIS_SHIFT))&ENET_RACC_IPDIS_MASK)
3853 #define ENET_RACC_PRODIS_MASK 0x4u
3854 #define ENET_RACC_PRODIS_SHIFT 2u
3855 #define ENET_RACC_PRODIS_WIDTH 1u
3856 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_PRODIS_SHIFT))&ENET_RACC_PRODIS_MASK)
3857 #define ENET_RACC_LINEDIS_MASK 0x40u
3858 #define ENET_RACC_LINEDIS_SHIFT 6u
3859 #define ENET_RACC_LINEDIS_WIDTH 1u
3860 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_LINEDIS_SHIFT))&ENET_RACC_LINEDIS_MASK)
3861 #define ENET_RACC_SHIFT16_MASK 0x80u
3862 #define ENET_RACC_SHIFT16_SHIFT 7u
3863 #define ENET_RACC_SHIFT16_WIDTH 1u
3864 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x))<<ENET_RACC_SHIFT16_SHIFT))&ENET_RACC_SHIFT16_MASK)
3866 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
3867 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0u
3868 #define ENET_RMON_T_PACKETS_TXPKTS_WIDTH 16u
3869 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
3871 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
3872 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0u
3873 #define ENET_RMON_T_BC_PKT_TXPKTS_WIDTH 16u
3874 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
3876 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
3877 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0u
3878 #define ENET_RMON_T_MC_PKT_TXPKTS_WIDTH 16u
3879 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
3881 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
3882 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0u
3883 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_WIDTH 16u
3884 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
3886 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
3887 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0u
3888 #define ENET_RMON_T_UNDERSIZE_TXPKTS_WIDTH 16u
3889 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
3891 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
3892 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0u
3893 #define ENET_RMON_T_OVERSIZE_TXPKTS_WIDTH 16u
3894 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
3896 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
3897 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0u
3898 #define ENET_RMON_T_FRAG_TXPKTS_WIDTH 16u
3899 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
3901 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
3902 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0u
3903 #define ENET_RMON_T_JAB_TXPKTS_WIDTH 16u
3904 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
3906 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
3907 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0u
3908 #define ENET_RMON_T_COL_TXPKTS_WIDTH 16u
3909 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
3911 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
3912 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0u
3913 #define ENET_RMON_T_P64_TXPKTS_WIDTH 16u
3914 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
3916 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
3917 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0u
3918 #define ENET_RMON_T_P65TO127_TXPKTS_WIDTH 16u
3919 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
3921 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
3922 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0u
3923 #define ENET_RMON_T_P128TO255_TXPKTS_WIDTH 16u
3924 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
3926 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
3927 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0u
3928 #define ENET_RMON_T_P256TO511_TXPKTS_WIDTH 16u
3929 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
3931 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
3932 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0u
3933 #define ENET_RMON_T_P512TO1023_TXPKTS_WIDTH 16u
3934 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
3936 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
3937 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0u
3938 #define ENET_RMON_T_P1024TO2047_TXPKTS_WIDTH 16u
3939 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
3941 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
3942 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0u
3943 #define ENET_RMON_T_P_GTE2048_TXPKTS_WIDTH 16u
3944 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
3946 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
3947 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0u
3948 #define ENET_RMON_T_OCTETS_TXOCTS_WIDTH 32u
3949 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
3951 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
3952 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0u
3953 #define ENET_IEEE_T_FRAME_OK_COUNT_WIDTH 16u
3954 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
3956 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
3957 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0u
3958 #define ENET_IEEE_T_1COL_COUNT_WIDTH 16u
3959 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
3961 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
3962 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0u
3963 #define ENET_IEEE_T_MCOL_COUNT_WIDTH 16u
3964 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
3966 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
3967 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0u
3968 #define ENET_IEEE_T_DEF_COUNT_WIDTH 16u
3969 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
3971 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
3972 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0u
3973 #define ENET_IEEE_T_LCOL_COUNT_WIDTH 16u
3974 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
3976 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
3977 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0u
3978 #define ENET_IEEE_T_EXCOL_COUNT_WIDTH 16u
3979 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
3981 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
3982 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0u
3983 #define ENET_IEEE_T_MACERR_COUNT_WIDTH 16u
3984 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
3986 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
3987 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0u
3988 #define ENET_IEEE_T_CSERR_COUNT_WIDTH 16u
3989 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
3991 #define ENET_IEEE_T_SQE_COUNT_MASK 0xFFFFu
3992 #define ENET_IEEE_T_SQE_COUNT_SHIFT 0u
3993 #define ENET_IEEE_T_SQE_COUNT_WIDTH 16u
3994 #define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_SQE_COUNT_SHIFT))&ENET_IEEE_T_SQE_COUNT_MASK)
3996 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
3997 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0u
3998 #define ENET_IEEE_T_FDXFC_COUNT_WIDTH 16u
3999 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
4001 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
4002 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0u
4003 #define ENET_IEEE_T_OCTETS_OK_COUNT_WIDTH 32u
4004 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
4006 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
4007 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0u
4008 #define ENET_RMON_R_PACKETS_COUNT_WIDTH 16u
4009 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
4011 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
4012 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0u
4013 #define ENET_RMON_R_BC_PKT_COUNT_WIDTH 16u
4014 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
4016 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
4017 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0u
4018 #define ENET_RMON_R_MC_PKT_COUNT_WIDTH 16u
4019 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
4021 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
4022 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0u
4023 #define ENET_RMON_R_CRC_ALIGN_COUNT_WIDTH 16u
4024 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
4026 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
4027 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0u
4028 #define ENET_RMON_R_UNDERSIZE_COUNT_WIDTH 16u
4029 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
4031 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
4032 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0u
4033 #define ENET_RMON_R_OVERSIZE_COUNT_WIDTH 16u
4034 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
4036 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
4037 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0u
4038 #define ENET_RMON_R_FRAG_COUNT_WIDTH 16u
4039 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
4041 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
4042 #define ENET_RMON_R_JAB_COUNT_SHIFT 0u
4043 #define ENET_RMON_R_JAB_COUNT_WIDTH 16u
4044 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
4046 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
4047 #define ENET_RMON_R_P64_COUNT_SHIFT 0u
4048 #define ENET_RMON_R_P64_COUNT_WIDTH 16u
4049 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
4051 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
4052 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0u
4053 #define ENET_RMON_R_P65TO127_COUNT_WIDTH 16u
4054 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
4056 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
4057 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0u
4058 #define ENET_RMON_R_P128TO255_COUNT_WIDTH 16u
4059 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
4061 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
4062 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0u
4063 #define ENET_RMON_R_P256TO511_COUNT_WIDTH 16u
4064 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
4066 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
4067 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0u
4068 #define ENET_RMON_R_P512TO1023_COUNT_WIDTH 16u
4069 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
4071 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
4072 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0u
4073 #define ENET_RMON_R_P1024TO2047_COUNT_WIDTH 16u
4074 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
4076 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
4077 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0u
4078 #define ENET_RMON_R_P_GTE2048_COUNT_WIDTH 16u
4079 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
4081 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
4082 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0u
4083 #define ENET_RMON_R_OCTETS_COUNT_WIDTH 32u
4084 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
4086 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
4087 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0u
4088 #define ENET_IEEE_R_DROP_COUNT_WIDTH 16u
4089 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
4091 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
4092 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0u
4093 #define ENET_IEEE_R_FRAME_OK_COUNT_WIDTH 16u
4094 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
4096 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
4097 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0u
4098 #define ENET_IEEE_R_CRC_COUNT_WIDTH 16u
4099 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
4101 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
4102 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0u
4103 #define ENET_IEEE_R_ALIGN_COUNT_WIDTH 16u
4104 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
4106 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
4107 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0u
4108 #define ENET_IEEE_R_MACERR_COUNT_WIDTH 16u
4109 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
4111 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
4112 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0u
4113 #define ENET_IEEE_R_FDXFC_COUNT_WIDTH 16u
4114 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
4116 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
4117 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0u
4118 #define ENET_IEEE_R_OCTETS_OK_COUNT_WIDTH 32u
4119 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
4121 #define ENET_ATCR_EN_MASK 0x1u
4122 #define ENET_ATCR_EN_SHIFT 0u
4123 #define ENET_ATCR_EN_WIDTH 1u
4124 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_EN_SHIFT))&ENET_ATCR_EN_MASK)
4125 #define ENET_ATCR_OFFEN_MASK 0x4u
4126 #define ENET_ATCR_OFFEN_SHIFT 2u
4127 #define ENET_ATCR_OFFEN_WIDTH 1u
4128 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFEN_SHIFT))&ENET_ATCR_OFFEN_MASK)
4129 #define ENET_ATCR_OFFRST_MASK 0x8u
4130 #define ENET_ATCR_OFFRST_SHIFT 3u
4131 #define ENET_ATCR_OFFRST_WIDTH 1u
4132 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_OFFRST_SHIFT))&ENET_ATCR_OFFRST_MASK)
4133 #define ENET_ATCR_PEREN_MASK 0x10u
4134 #define ENET_ATCR_PEREN_SHIFT 4u
4135 #define ENET_ATCR_PEREN_WIDTH 1u
4136 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PEREN_SHIFT))&ENET_ATCR_PEREN_MASK)
4137 #define ENET_ATCR_PINPER_MASK 0x80u
4138 #define ENET_ATCR_PINPER_SHIFT 7u
4139 #define ENET_ATCR_PINPER_WIDTH 1u
4140 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_PINPER_SHIFT))&ENET_ATCR_PINPER_MASK)
4141 #define ENET_ATCR_RESTART_MASK 0x200u
4142 #define ENET_ATCR_RESTART_SHIFT 9u
4143 #define ENET_ATCR_RESTART_WIDTH 1u
4144 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_RESTART_SHIFT))&ENET_ATCR_RESTART_MASK)
4145 #define ENET_ATCR_CAPTURE_MASK 0x800u
4146 #define ENET_ATCR_CAPTURE_SHIFT 11u
4147 #define ENET_ATCR_CAPTURE_WIDTH 1u
4148 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_CAPTURE_SHIFT))&ENET_ATCR_CAPTURE_MASK)
4149 #define ENET_ATCR_SLAVE_MASK 0x2000u
4150 #define ENET_ATCR_SLAVE_SHIFT 13u
4151 #define ENET_ATCR_SLAVE_WIDTH 1u
4152 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCR_SLAVE_SHIFT))&ENET_ATCR_SLAVE_MASK)
4154 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
4155 #define ENET_ATVR_ATIME_SHIFT 0u
4156 #define ENET_ATVR_ATIME_WIDTH 32u
4157 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
4159 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
4160 #define ENET_ATOFF_OFFSET_SHIFT 0u
4161 #define ENET_ATOFF_OFFSET_WIDTH 32u
4162 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
4164 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
4165 #define ENET_ATPER_PERIOD_SHIFT 0u
4166 #define ENET_ATPER_PERIOD_WIDTH 32u
4167 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
4169 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
4170 #define ENET_ATCOR_COR_SHIFT 0u
4171 #define ENET_ATCOR_COR_WIDTH 31u
4172 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
4174 #define ENET_ATINC_INC_MASK 0x7Fu
4175 #define ENET_ATINC_INC_SHIFT 0u
4176 #define ENET_ATINC_INC_WIDTH 7u
4177 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
4178 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
4179 #define ENET_ATINC_INC_CORR_SHIFT 8u
4180 #define ENET_ATINC_INC_CORR_WIDTH 7u
4181 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
4183 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
4184 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0u
4185 #define ENET_ATSTMP_TIMESTAMP_WIDTH 32u
4186 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
4188 #define ENET_TGSR_TF0_MASK 0x1u
4189 #define ENET_TGSR_TF0_SHIFT 0u
4190 #define ENET_TGSR_TF0_WIDTH 1u
4191 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF0_SHIFT))&ENET_TGSR_TF0_MASK)
4192 #define ENET_TGSR_TF1_MASK 0x2u
4193 #define ENET_TGSR_TF1_SHIFT 1u
4194 #define ENET_TGSR_TF1_WIDTH 1u
4195 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF1_SHIFT))&ENET_TGSR_TF1_MASK)
4196 #define ENET_TGSR_TF2_MASK 0x4u
4197 #define ENET_TGSR_TF2_SHIFT 2u
4198 #define ENET_TGSR_TF2_WIDTH 1u
4199 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF2_SHIFT))&ENET_TGSR_TF2_MASK)
4200 #define ENET_TGSR_TF3_MASK 0x8u
4201 #define ENET_TGSR_TF3_SHIFT 3u
4202 #define ENET_TGSR_TF3_WIDTH 1u
4203 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x))<<ENET_TGSR_TF3_SHIFT))&ENET_TGSR_TF3_MASK)
4205 #define ENET_TCSR_TDRE_MASK 0x1u
4206 #define ENET_TCSR_TDRE_SHIFT 0u
4207 #define ENET_TCSR_TDRE_WIDTH 1u
4208 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TDRE_SHIFT))&ENET_TCSR_TDRE_MASK)
4209 #define ENET_TCSR_TMODE_MASK 0x3Cu
4210 #define ENET_TCSR_TMODE_SHIFT 2u
4211 #define ENET_TCSR_TMODE_WIDTH 4u
4212 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
4213 #define ENET_TCSR_TIE_MASK 0x40u
4214 #define ENET_TCSR_TIE_SHIFT 6u
4215 #define ENET_TCSR_TIE_WIDTH 1u
4216 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TIE_SHIFT))&ENET_TCSR_TIE_MASK)
4217 #define ENET_TCSR_TF_MASK 0x80u
4218 #define ENET_TCSR_TF_SHIFT 7u
4219 #define ENET_TCSR_TF_WIDTH 1u
4220 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TF_SHIFT))&ENET_TCSR_TF_MASK)
4222 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
4223 #define ENET_TCCR_TCC_SHIFT 0u
4224 #define ENET_TCCR_TCC_WIDTH 32u
4225 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
4248 #define ERM_EARn_COUNT 2u
4253 uint8_t RESERVED_0[12];
4255 uint8_t RESERVED_1[236];
4258 uint8_t RESERVED_0[12];
4263 #define ERM_INSTANCE_COUNT (1u)
4268 #define ERM_BASE (0x40018000u)
4270 #define ERM ((ERM_Type *)ERM_BASE)
4272 #define ERM_BASE_ADDRS { ERM_BASE }
4274 #define ERM_BASE_PTRS { ERM }
4276 #define ERM_IRQS_ARR_COUNT (2u)
4278 #define ERM_SINGLE_IRQS_CH_COUNT (1u)
4280 #define ERM_DOUBLE_IRQS_CH_COUNT (1u)
4282 #define ERM_SINGLE_IRQS { ERM_single_fault_IRQn }
4283 #define ERM_DOUBLE_IRQS { ERM_double_fault_IRQn }
4295 #define ERM_CR0_ENCIE1_MASK 0x4000000u
4296 #define ERM_CR0_ENCIE1_SHIFT 26u
4297 #define ERM_CR0_ENCIE1_WIDTH 1u
4298 #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE1_SHIFT))&ERM_CR0_ENCIE1_MASK)
4299 #define ERM_CR0_ESCIE1_MASK 0x8000000u
4300 #define ERM_CR0_ESCIE1_SHIFT 27u
4301 #define ERM_CR0_ESCIE1_WIDTH 1u
4302 #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE1_SHIFT))&ERM_CR0_ESCIE1_MASK)
4303 #define ERM_CR0_ENCIE0_MASK 0x40000000u
4304 #define ERM_CR0_ENCIE0_SHIFT 30u
4305 #define ERM_CR0_ENCIE0_WIDTH 1u
4306 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK)
4307 #define ERM_CR0_ESCIE0_MASK 0x80000000u
4308 #define ERM_CR0_ESCIE0_SHIFT 31u
4309 #define ERM_CR0_ESCIE0_WIDTH 1u
4310 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK)
4312 #define ERM_SR0_NCE1_MASK 0x4000000u
4313 #define ERM_SR0_NCE1_SHIFT 26u
4314 #define ERM_SR0_NCE1_WIDTH 1u
4315 #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE1_SHIFT))&ERM_SR0_NCE1_MASK)
4316 #define ERM_SR0_SBC1_MASK 0x8000000u
4317 #define ERM_SR0_SBC1_SHIFT 27u
4318 #define ERM_SR0_SBC1_WIDTH 1u
4319 #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC1_SHIFT))&ERM_SR0_SBC1_MASK)
4320 #define ERM_SR0_NCE0_MASK 0x40000000u
4321 #define ERM_SR0_NCE0_SHIFT 30u
4322 #define ERM_SR0_NCE0_WIDTH 1u
4323 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK)
4324 #define ERM_SR0_SBC0_MASK 0x80000000u
4325 #define ERM_SR0_SBC0_SHIFT 31u
4326 #define ERM_SR0_SBC0_WIDTH 1u
4327 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK)
4329 #define ERM_EARn_EAR_EAR_MASK 0xFFFFFFFFu
4330 #define ERM_EARn_EAR_EAR_SHIFT 0u
4331 #define ERM_EARn_EAR_EAR_WIDTH 32u
4332 #define ERM_EARn_EAR_EAR(x) (((uint32_t)(((uint32_t)(x))<<ERM_EARn_EAR_EAR_SHIFT))&ERM_EARn_EAR_EAR_MASK)
4362 uint8_t RESERVED_0[1];
4367 #define EWM_INSTANCE_COUNT (1u)
4372 #define EWM_BASE (0x40061000u)
4374 #define EWM ((EWM_Type *)EWM_BASE)
4376 #define EWM_BASE_ADDRS { EWM_BASE }
4378 #define EWM_BASE_PTRS { EWM }
4380 #define EWM_IRQS_ARR_COUNT (1u)
4382 #define EWM_IRQS_CH_COUNT (1u)
4384 #define EWM_IRQS { WDOG_EWM_IRQn }
4396 #define EWM_CTRL_EWMEN_MASK 0x1u
4397 #define EWM_CTRL_EWMEN_SHIFT 0u
4398 #define EWM_CTRL_EWMEN_WIDTH 1u
4399 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
4400 #define EWM_CTRL_ASSIN_MASK 0x2u
4401 #define EWM_CTRL_ASSIN_SHIFT 1u
4402 #define EWM_CTRL_ASSIN_WIDTH 1u
4403 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
4404 #define EWM_CTRL_INEN_MASK 0x4u
4405 #define EWM_CTRL_INEN_SHIFT 2u
4406 #define EWM_CTRL_INEN_WIDTH 1u
4407 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
4408 #define EWM_CTRL_INTEN_MASK 0x8u
4409 #define EWM_CTRL_INTEN_SHIFT 3u
4410 #define EWM_CTRL_INTEN_WIDTH 1u
4411 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
4413 #define EWM_SERV_SERVICE_MASK 0xFFu
4414 #define EWM_SERV_SERVICE_SHIFT 0u
4415 #define EWM_SERV_SERVICE_WIDTH 8u
4416 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
4418 #define EWM_CMPL_COMPAREL_MASK 0xFFu
4419 #define EWM_CMPL_COMPAREL_SHIFT 0u
4420 #define EWM_CMPL_COMPAREL_WIDTH 8u
4421 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
4423 #define EWM_CMPH_COMPAREH_MASK 0xFFu
4424 #define EWM_CMPH_COMPAREH_SHIFT 0u
4425 #define EWM_CMPH_COMPAREH_WIDTH 8u
4426 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
4428 #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
4429 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0u
4430 #define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8u
4431 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
4454 #define FLEXIO_SHIFTCTL_COUNT 4u
4455 #define FLEXIO_SHIFTCFG_COUNT 4u
4456 #define FLEXIO_SHIFTBUF_COUNT 4u
4457 #define FLEXIO_SHIFTBUFBIS_COUNT 4u
4458 #define FLEXIO_SHIFTBUFBYS_COUNT 4u
4459 #define FLEXIO_SHIFTBUFBBS_COUNT 4u
4460 #define FLEXIO_TIMCTL_COUNT 4u
4461 #define FLEXIO_TIMCFG_COUNT 4u
4462 #define FLEXIO_TIMCMP_COUNT 4u
4473 uint8_t RESERVED_0[4];
4477 uint8_t RESERVED_1[4];
4479 uint8_t RESERVED_2[76];
4481 uint8_t RESERVED_3[112];
4483 uint8_t RESERVED_4[240];
4485 uint8_t RESERVED_5[112];
4487 uint8_t RESERVED_6[112];
4489 uint8_t RESERVED_7[112];
4491 uint8_t RESERVED_8[112];
4493 uint8_t RESERVED_9[112];
4495 uint8_t RESERVED_10[112];
4500 #define FLEXIO_INSTANCE_COUNT (1u)
4505 #define FLEXIO_BASE (0x4005A000u)
4507 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
4509 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
4511 #define FLEXIO_BASE_PTRS { FLEXIO }
4513 #define FLEXIO_IRQS_ARR_COUNT (1u)
4515 #define FLEXIO_IRQS_CH_COUNT (1u)
4517 #define FLEXIO_IRQS { FLEXIO_IRQn }
4529 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
4530 #define FLEXIO_VERID_FEATURE_SHIFT 0u
4531 #define FLEXIO_VERID_FEATURE_WIDTH 16u
4532 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
4533 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
4534 #define FLEXIO_VERID_MINOR_SHIFT 16u
4535 #define FLEXIO_VERID_MINOR_WIDTH 8u
4536 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
4537 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
4538 #define FLEXIO_VERID_MAJOR_SHIFT 24u
4539 #define FLEXIO_VERID_MAJOR_WIDTH 8u
4540 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
4542 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
4543 #define FLEXIO_PARAM_SHIFTER_SHIFT 0u
4544 #define FLEXIO_PARAM_SHIFTER_WIDTH 8u
4545 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
4546 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
4547 #define FLEXIO_PARAM_TIMER_SHIFT 8u
4548 #define FLEXIO_PARAM_TIMER_WIDTH 8u
4549 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
4550 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
4551 #define FLEXIO_PARAM_PIN_SHIFT 16u
4552 #define FLEXIO_PARAM_PIN_WIDTH 8u
4553 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
4554 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
4555 #define FLEXIO_PARAM_TRIGGER_SHIFT 24u
4556 #define FLEXIO_PARAM_TRIGGER_WIDTH 8u
4557 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
4559 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
4560 #define FLEXIO_CTRL_FLEXEN_SHIFT 0u
4561 #define FLEXIO_CTRL_FLEXEN_WIDTH 1u
4562 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
4563 #define FLEXIO_CTRL_SWRST_MASK 0x2u
4564 #define FLEXIO_CTRL_SWRST_SHIFT 1u
4565 #define FLEXIO_CTRL_SWRST_WIDTH 1u
4566 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
4567 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
4568 #define FLEXIO_CTRL_FASTACC_SHIFT 2u
4569 #define FLEXIO_CTRL_FASTACC_WIDTH 1u
4570 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
4571 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
4572 #define FLEXIO_CTRL_DBGE_SHIFT 30u
4573 #define FLEXIO_CTRL_DBGE_WIDTH 1u
4574 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
4575 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
4576 #define FLEXIO_CTRL_DOZEN_SHIFT 31u
4577 #define FLEXIO_CTRL_DOZEN_WIDTH 1u
4578 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
4580 #define FLEXIO_PIN_PDI_MASK 0xFFu
4581 #define FLEXIO_PIN_PDI_SHIFT 0u
4582 #define FLEXIO_PIN_PDI_WIDTH 8u
4583 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
4585 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
4586 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0u
4587 #define FLEXIO_SHIFTSTAT_SSF_WIDTH 4u
4588 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
4590 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
4591 #define FLEXIO_SHIFTERR_SEF_SHIFT 0u
4592 #define FLEXIO_SHIFTERR_SEF_WIDTH 4u
4593 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
4595 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
4596 #define FLEXIO_TIMSTAT_TSF_SHIFT 0u
4597 #define FLEXIO_TIMSTAT_TSF_WIDTH 4u
4598 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
4600 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
4601 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0u
4602 #define FLEXIO_SHIFTSIEN_SSIE_WIDTH 4u
4603 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
4605 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
4606 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0u
4607 #define FLEXIO_SHIFTEIEN_SEIE_WIDTH 4u
4608 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
4610 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
4611 #define FLEXIO_TIMIEN_TEIE_SHIFT 0u
4612 #define FLEXIO_TIMIEN_TEIE_WIDTH 4u
4613 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
4615 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
4616 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0u
4617 #define FLEXIO_SHIFTSDEN_SSDE_WIDTH 4u
4618 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
4620 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
4621 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0u
4622 #define FLEXIO_SHIFTCTL_SMOD_WIDTH 3u
4623 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
4624 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
4625 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7u
4626 #define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1u
4627 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
4628 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
4629 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8u
4630 #define FLEXIO_SHIFTCTL_PINSEL_WIDTH 3u
4631 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
4632 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
4633 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16u
4634 #define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2u
4635 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
4636 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
4637 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23u
4638 #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1u
4639 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
4640 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
4641 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24u
4642 #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 2u
4643 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
4645 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
4646 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0u
4647 #define FLEXIO_SHIFTCFG_SSTART_WIDTH 2u
4648 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
4649 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
4650 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4u
4651 #define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2u
4652 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
4653 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
4654 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8u
4655 #define FLEXIO_SHIFTCFG_INSRC_WIDTH 1u
4656 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
4658 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
4659 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0u
4660 #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32u
4661 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
4663 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
4664 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0u
4665 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32u
4666 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
4668 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
4669 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0u
4670 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32u
4671 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
4673 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
4674 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0u
4675 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32u
4676 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
4678 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
4679 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0u
4680 #define FLEXIO_TIMCTL_TIMOD_WIDTH 2u
4681 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
4682 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
4683 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7u
4684 #define FLEXIO_TIMCTL_PINPOL_WIDTH 1u
4685 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
4686 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
4687 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8u
4688 #define FLEXIO_TIMCTL_PINSEL_WIDTH 3u
4689 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
4690 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
4691 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16u
4692 #define FLEXIO_TIMCTL_PINCFG_WIDTH 2u
4693 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
4694 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
4695 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22u
4696 #define FLEXIO_TIMCTL_TRGSRC_WIDTH 1u
4697 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
4698 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
4699 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23u
4700 #define FLEXIO_TIMCTL_TRGPOL_WIDTH 1u
4701 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
4702 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
4703 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24u
4704 #define FLEXIO_TIMCTL_TRGSEL_WIDTH 4u
4705 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
4707 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
4708 #define FLEXIO_TIMCFG_TSTART_SHIFT 1u
4709 #define FLEXIO_TIMCFG_TSTART_WIDTH 1u
4710 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
4711 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
4712 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4u
4713 #define FLEXIO_TIMCFG_TSTOP_WIDTH 2u
4714 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
4715 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
4716 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8u
4717 #define FLEXIO_TIMCFG_TIMENA_WIDTH 3u
4718 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
4719 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
4720 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12u
4721 #define FLEXIO_TIMCFG_TIMDIS_WIDTH 3u
4722 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
4723 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
4724 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16u
4725 #define FLEXIO_TIMCFG_TIMRST_WIDTH 3u
4726 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
4727 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
4728 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20u
4729 #define FLEXIO_TIMCFG_TIMDEC_WIDTH 2u
4730 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
4731 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
4732 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24u
4733 #define FLEXIO_TIMCFG_TIMOUT_WIDTH 2u
4734 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
4736 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
4737 #define FLEXIO_TIMCMP_CMP_SHIFT 0u
4738 #define FLEXIO_TIMCMP_CMP_WIDTH 16u
4739 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
4762 #define FTFC_FCCOB_COUNT 12u
4763 #define FTFC_FPROT_COUNT 4u
4773 uint8_t RESERVED_0[2];
4776 uint8_t RESERVED_1[20];
4778 uint8_t RESERVED_2[1];
4784 #define FTFC_INSTANCE_COUNT (1u)
4789 #define FTFC_BASE (0x40020000u)
4791 #define FTFC ((FTFC_Type *)FTFC_BASE)
4793 #define FTFC_BASE_ADDRS { FTFC_BASE }
4795 #define FTFC_BASE_PTRS { FTFC }
4797 #define FTFC_IRQS_ARR_COUNT (2u)
4799 #define FTFC_COMMAND_COMPLETE_IRQS_CH_COUNT (1u)
4801 #define FTFC_READ_COLLISION_IRQS_CH_COUNT (1u)
4803 #define FTFC_COMMAND_COMPLETE_IRQS { FTFC_IRQn }
4804 #define FTFC_READ_COLLISION_IRQS { Read_Collision_IRQn }
4816 #define FTFC_FSTAT_MGSTAT0_MASK 0x1u
4817 #define FTFC_FSTAT_MGSTAT0_SHIFT 0u
4818 #define FTFC_FSTAT_MGSTAT0_WIDTH 1u
4819 #define FTFC_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_MGSTAT0_SHIFT))&FTFC_FSTAT_MGSTAT0_MASK)
4820 #define FTFC_FSTAT_FPVIOL_MASK 0x10u
4821 #define FTFC_FSTAT_FPVIOL_SHIFT 4u
4822 #define FTFC_FSTAT_FPVIOL_WIDTH 1u
4823 #define FTFC_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_FPVIOL_SHIFT))&FTFC_FSTAT_FPVIOL_MASK)
4824 #define FTFC_FSTAT_ACCERR_MASK 0x20u
4825 #define FTFC_FSTAT_ACCERR_SHIFT 5u
4826 #define FTFC_FSTAT_ACCERR_WIDTH 1u
4827 #define FTFC_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_ACCERR_SHIFT))&FTFC_FSTAT_ACCERR_MASK)
4828 #define FTFC_FSTAT_RDCOLERR_MASK 0x40u
4829 #define FTFC_FSTAT_RDCOLERR_SHIFT 6u
4830 #define FTFC_FSTAT_RDCOLERR_WIDTH 1u
4831 #define FTFC_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_RDCOLERR_SHIFT))&FTFC_FSTAT_RDCOLERR_MASK)
4832 #define FTFC_FSTAT_CCIF_MASK 0x80u
4833 #define FTFC_FSTAT_CCIF_SHIFT 7u
4834 #define FTFC_FSTAT_CCIF_WIDTH 1u
4835 #define FTFC_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_CCIF_SHIFT))&FTFC_FSTAT_CCIF_MASK)
4837 #define FTFC_FCNFG_EEERDY_MASK 0x1u
4838 #define FTFC_FCNFG_EEERDY_SHIFT 0u
4839 #define FTFC_FCNFG_EEERDY_WIDTH 1u
4840 #define FTFC_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_EEERDY_SHIFT))&FTFC_FCNFG_EEERDY_MASK)
4841 #define FTFC_FCNFG_RAMRDY_MASK 0x2u
4842 #define FTFC_FCNFG_RAMRDY_SHIFT 1u
4843 #define FTFC_FCNFG_RAMRDY_WIDTH 1u
4844 #define FTFC_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RAMRDY_SHIFT))&FTFC_FCNFG_RAMRDY_MASK)
4845 #define FTFC_FCNFG_ERSSUSP_MASK 0x10u
4846 #define FTFC_FCNFG_ERSSUSP_SHIFT 4u
4847 #define FTFC_FCNFG_ERSSUSP_WIDTH 1u
4848 #define FTFC_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSSUSP_SHIFT))&FTFC_FCNFG_ERSSUSP_MASK)
4849 #define FTFC_FCNFG_ERSAREQ_MASK 0x20u
4850 #define FTFC_FCNFG_ERSAREQ_SHIFT 5u
4851 #define FTFC_FCNFG_ERSAREQ_WIDTH 1u
4852 #define FTFC_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSAREQ_SHIFT))&FTFC_FCNFG_ERSAREQ_MASK)
4853 #define FTFC_FCNFG_RDCOLLIE_MASK 0x40u
4854 #define FTFC_FCNFG_RDCOLLIE_SHIFT 6u
4855 #define FTFC_FCNFG_RDCOLLIE_WIDTH 1u
4856 #define FTFC_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RDCOLLIE_SHIFT))&FTFC_FCNFG_RDCOLLIE_MASK)
4857 #define FTFC_FCNFG_CCIE_MASK 0x80u
4858 #define FTFC_FCNFG_CCIE_SHIFT 7u
4859 #define FTFC_FCNFG_CCIE_WIDTH 1u
4860 #define FTFC_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_CCIE_SHIFT))&FTFC_FCNFG_CCIE_MASK)
4862 #define FTFC_FSEC_SEC_MASK 0x3u
4863 #define FTFC_FSEC_SEC_SHIFT 0u
4864 #define FTFC_FSEC_SEC_WIDTH 2u
4865 #define FTFC_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_SEC_SHIFT))&FTFC_FSEC_SEC_MASK)
4866 #define FTFC_FSEC_FSLACC_MASK 0xCu
4867 #define FTFC_FSEC_FSLACC_SHIFT 2u
4868 #define FTFC_FSEC_FSLACC_WIDTH 2u
4869 #define FTFC_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_FSLACC_SHIFT))&FTFC_FSEC_FSLACC_MASK)
4870 #define FTFC_FSEC_MEEN_MASK 0x30u
4871 #define FTFC_FSEC_MEEN_SHIFT 4u
4872 #define FTFC_FSEC_MEEN_WIDTH 2u
4873 #define FTFC_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_MEEN_SHIFT))&FTFC_FSEC_MEEN_MASK)
4874 #define FTFC_FSEC_KEYEN_MASK 0xC0u
4875 #define FTFC_FSEC_KEYEN_SHIFT 6u
4876 #define FTFC_FSEC_KEYEN_WIDTH 2u
4877 #define FTFC_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_KEYEN_SHIFT))&FTFC_FSEC_KEYEN_MASK)
4879 #define FTFC_FOPT_OPT_MASK 0xFFu
4880 #define FTFC_FOPT_OPT_SHIFT 0u
4881 #define FTFC_FOPT_OPT_WIDTH 8u
4882 #define FTFC_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FOPT_OPT_SHIFT))&FTFC_FOPT_OPT_MASK)
4884 #define FTFC_FCCOB_CCOBn_MASK 0xFFu
4885 #define FTFC_FCCOB_CCOBn_SHIFT 0u
4886 #define FTFC_FCCOB_CCOBn_WIDTH 8u
4887 #define FTFC_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCCOB_CCOBn_SHIFT))&FTFC_FCCOB_CCOBn_MASK)
4889 #define FTFC_FPROT_PROT_MASK 0xFFu
4890 #define FTFC_FPROT_PROT_SHIFT 0u
4891 #define FTFC_FPROT_PROT_WIDTH 8u
4892 #define FTFC_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FPROT_PROT_SHIFT))&FTFC_FPROT_PROT_MASK)
4894 #define FTFC_FEPROT_EPROT_MASK 0xFFu
4895 #define FTFC_FEPROT_EPROT_SHIFT 0u
4896 #define FTFC_FEPROT_EPROT_WIDTH 8u
4897 #define FTFC_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FEPROT_EPROT_SHIFT))&FTFC_FEPROT_EPROT_MASK)
4899 #define FTFC_FDPROT_DPROT_MASK 0xFFu
4900 #define FTFC_FDPROT_DPROT_SHIFT 0u
4901 #define FTFC_FDPROT_DPROT_WIDTH 8u
4902 #define FTFC_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FDPROT_DPROT_SHIFT))&FTFC_FDPROT_DPROT_MASK)
4904 #define FTFC_FCSESTAT_BSY_MASK 0x1u
4905 #define FTFC_FCSESTAT_BSY_SHIFT 0u
4906 #define FTFC_FCSESTAT_BSY_WIDTH 1u
4907 #define FTFC_FCSESTAT_BSY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BSY_SHIFT))&FTFC_FCSESTAT_BSY_MASK)
4908 #define FTFC_FCSESTAT_SB_MASK 0x2u
4909 #define FTFC_FCSESTAT_SB_SHIFT 1u
4910 #define FTFC_FCSESTAT_SB_WIDTH 1u
4911 #define FTFC_FCSESTAT_SB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_SB_SHIFT))&FTFC_FCSESTAT_SB_MASK)
4912 #define FTFC_FCSESTAT_BIN_MASK 0x4u
4913 #define FTFC_FCSESTAT_BIN_SHIFT 2u
4914 #define FTFC_FCSESTAT_BIN_WIDTH 1u
4915 #define FTFC_FCSESTAT_BIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BIN_SHIFT))&FTFC_FCSESTAT_BIN_MASK)
4916 #define FTFC_FCSESTAT_BFN_MASK 0x8u
4917 #define FTFC_FCSESTAT_BFN_SHIFT 3u
4918 #define FTFC_FCSESTAT_BFN_WIDTH 1u
4919 #define FTFC_FCSESTAT_BFN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BFN_SHIFT))&FTFC_FCSESTAT_BFN_MASK)
4920 #define FTFC_FCSESTAT_BOK_MASK 0x10u
4921 #define FTFC_FCSESTAT_BOK_SHIFT 4u
4922 #define FTFC_FCSESTAT_BOK_WIDTH 1u
4923 #define FTFC_FCSESTAT_BOK(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BOK_SHIFT))&FTFC_FCSESTAT_BOK_MASK)
4924 #define FTFC_FCSESTAT_RIN_MASK 0x20u
4925 #define FTFC_FCSESTAT_RIN_SHIFT 5u
4926 #define FTFC_FCSESTAT_RIN_WIDTH 1u
4927 #define FTFC_FCSESTAT_RIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_RIN_SHIFT))&FTFC_FCSESTAT_RIN_MASK)
4928 #define FTFC_FCSESTAT_EDB_MASK 0x40u
4929 #define FTFC_FCSESTAT_EDB_SHIFT 6u
4930 #define FTFC_FCSESTAT_EDB_WIDTH 1u
4931 #define FTFC_FCSESTAT_EDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_EDB_SHIFT))&FTFC_FCSESTAT_EDB_MASK)
4932 #define FTFC_FCSESTAT_IDB_MASK 0x80u
4933 #define FTFC_FCSESTAT_IDB_SHIFT 7u
4934 #define FTFC_FCSESTAT_IDB_WIDTH 1u
4935 #define FTFC_FCSESTAT_IDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_IDB_SHIFT))&FTFC_FCSESTAT_IDB_MASK)
4937 #define FTFC_FERSTAT_DFDIF_MASK 0x2u
4938 #define FTFC_FERSTAT_DFDIF_SHIFT 1u
4939 #define FTFC_FERSTAT_DFDIF_WIDTH 1u
4940 #define FTFC_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERSTAT_DFDIF_SHIFT))&FTFC_FERSTAT_DFDIF_MASK)
4942 #define FTFC_FERCNFG_DFDIE_MASK 0x2u
4943 #define FTFC_FERCNFG_DFDIE_SHIFT 1u
4944 #define FTFC_FERCNFG_DFDIE_WIDTH 1u
4945 #define FTFC_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_DFDIE_SHIFT))&FTFC_FERCNFG_DFDIE_MASK)
4946 #define FTFC_FERCNFG_FDFD_MASK 0x20u
4947 #define FTFC_FERCNFG_FDFD_SHIFT 5u
4948 #define FTFC_FERCNFG_FDFD_WIDTH 1u
4949 #define FTFC_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_FDFD_SHIFT))&FTFC_FERCNFG_FDFD_MASK)
4972 #define FTM_CONTROLS_COUNT 8u
4973 #define FTM_CV_MIRROR_COUNT 8u
5006 uint8_t RESERVED_0[4];
5008 uint8_t RESERVED_1[4];
5010 uint8_t RESERVED_2[4];
5012 uint8_t RESERVED_3[324];
5018 #define FTM_INSTANCE_COUNT (8u)
5023 #define FTM0_BASE (0x40038000u)
5025 #define FTM0 ((FTM_Type *)FTM0_BASE)
5027 #define FTM1_BASE (0x40039000u)
5029 #define FTM1 ((FTM_Type *)FTM1_BASE)
5031 #define FTM2_BASE (0x4003A000u)
5033 #define FTM2 ((FTM_Type *)FTM2_BASE)
5035 #define FTM3_BASE (0x40026000u)
5037 #define FTM3 ((FTM_Type *)FTM3_BASE)
5039 #define FTM4_BASE (0x4006E000u)
5041 #define FTM4 ((FTM_Type *)FTM4_BASE)
5043 #define FTM5_BASE (0x4006F000u)
5045 #define FTM5 ((FTM_Type *)FTM5_BASE)
5047 #define FTM6_BASE (0x40070000u)
5049 #define FTM6 ((FTM_Type *)FTM6_BASE)
5051 #define FTM7_BASE (0x40071000u)
5053 #define FTM7 ((FTM_Type *)FTM7_BASE)
5055 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE, FTM4_BASE, FTM5_BASE, FTM6_BASE, FTM7_BASE }
5057 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3, FTM4, FTM5, FTM6, FTM7 }
5059 #define FTM_IRQS_ARR_COUNT (4u)
5061 #define FTM_IRQS_CH_COUNT (8u)
5063 #define FTM_Fault_IRQS_CH_COUNT (1u)
5065 #define FTM_Overflow_IRQS_CH_COUNT (1u)
5067 #define FTM_Reload_IRQS_CH_COUNT (1u)
5069 #define FTM_IRQS { { FTM0_Ch0_Ch1_IRQn, FTM0_Ch0_Ch1_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch6_Ch7_IRQn, FTM0_Ch6_Ch7_IRQn }, \
5070 { FTM1_Ch0_Ch1_IRQn, FTM1_Ch0_Ch1_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch6_Ch7_IRQn, FTM1_Ch6_Ch7_IRQn }, \
5071 { FTM2_Ch0_Ch1_IRQn, FTM2_Ch0_Ch1_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch6_Ch7_IRQn, FTM2_Ch6_Ch7_IRQn }, \
5072 { FTM3_Ch0_Ch1_IRQn, FTM3_Ch0_Ch1_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch6_Ch7_IRQn, FTM3_Ch6_Ch7_IRQn }, \
5073 { FTM4_Ch0_Ch1_IRQn, FTM4_Ch0_Ch1_IRQn, FTM4_Ch2_Ch3_IRQn, FTM4_Ch2_Ch3_IRQn, FTM4_Ch4_Ch5_IRQn, FTM4_Ch4_Ch5_IRQn, FTM4_Ch6_Ch7_IRQn, FTM4_Ch6_Ch7_IRQn }, \
5074 { FTM5_Ch0_Ch1_IRQn, FTM5_Ch0_Ch1_IRQn, FTM5_Ch2_Ch3_IRQn, FTM5_Ch2_Ch3_IRQn, FTM5_Ch4_Ch5_IRQn, FTM5_Ch4_Ch5_IRQn, FTM5_Ch6_Ch7_IRQn, FTM5_Ch6_Ch7_IRQn }, \
5075 { FTM6_Ch0_Ch1_IRQn, FTM6_Ch0_Ch1_IRQn, FTM6_Ch2_Ch3_IRQn, FTM6_Ch2_Ch3_IRQn, FTM6_Ch4_Ch5_IRQn, FTM6_Ch4_Ch5_IRQn, FTM6_Ch6_Ch7_IRQn, FTM6_Ch6_Ch7_IRQn }, \
5076 { FTM7_Ch0_Ch1_IRQn, FTM7_Ch0_Ch1_IRQn, FTM7_Ch2_Ch3_IRQn, FTM7_Ch2_Ch3_IRQn, FTM7_Ch4_Ch5_IRQn, FTM7_Ch4_Ch5_IRQn, FTM7_Ch6_Ch7_IRQn, FTM7_Ch6_Ch7_IRQn } }
5077 #define FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn, FTM2_Fault_IRQn, FTM3_Fault_IRQn, FTM4_Fault_IRQn, FTM5_Fault_IRQn, FTM6_Fault_IRQn, FTM7_Fault_IRQn }
5078 #define FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn, FTM4_Ovf_Reload_IRQn, FTM5_Ovf_Reload_IRQn, FTM6_Ovf_Reload_IRQn, FTM7_Ovf_Reload_IRQn }
5079 #define FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn, FTM4_Ovf_Reload_IRQn, FTM5_Ovf_Reload_IRQn, FTM6_Ovf_Reload_IRQn, FTM7_Ovf_Reload_IRQn }
5091 #define FTM_SC_PS_MASK 0x7u
5092 #define FTM_SC_PS_SHIFT 0u
5093 #define FTM_SC_PS_WIDTH 3u
5094 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
5095 #define FTM_SC_CLKS_MASK 0x18u
5096 #define FTM_SC_CLKS_SHIFT 3u
5097 #define FTM_SC_CLKS_WIDTH 2u
5098 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
5099 #define FTM_SC_CPWMS_MASK 0x20u
5100 #define FTM_SC_CPWMS_SHIFT 5u
5101 #define FTM_SC_CPWMS_WIDTH 1u
5102 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
5103 #define FTM_SC_RIE_MASK 0x40u
5104 #define FTM_SC_RIE_SHIFT 6u
5105 #define FTM_SC_RIE_WIDTH 1u
5106 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RIE_SHIFT))&FTM_SC_RIE_MASK)
5107 #define FTM_SC_RF_MASK 0x80u
5108 #define FTM_SC_RF_SHIFT 7u
5109 #define FTM_SC_RF_WIDTH 1u
5110 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RF_SHIFT))&FTM_SC_RF_MASK)
5111 #define FTM_SC_TOIE_MASK 0x100u
5112 #define FTM_SC_TOIE_SHIFT 8u
5113 #define FTM_SC_TOIE_WIDTH 1u
5114 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
5115 #define FTM_SC_TOF_MASK 0x200u
5116 #define FTM_SC_TOF_SHIFT 9u
5117 #define FTM_SC_TOF_WIDTH 1u
5118 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
5119 #define FTM_SC_PWMEN0_MASK 0x10000u
5120 #define FTM_SC_PWMEN0_SHIFT 16u
5121 #define FTM_SC_PWMEN0_WIDTH 1u
5122 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN0_SHIFT))&FTM_SC_PWMEN0_MASK)
5123 #define FTM_SC_PWMEN1_MASK 0x20000u
5124 #define FTM_SC_PWMEN1_SHIFT 17u
5125 #define FTM_SC_PWMEN1_WIDTH 1u
5126 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN1_SHIFT))&FTM_SC_PWMEN1_MASK)
5127 #define FTM_SC_PWMEN2_MASK 0x40000u
5128 #define FTM_SC_PWMEN2_SHIFT 18u
5129 #define FTM_SC_PWMEN2_WIDTH 1u
5130 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN2_SHIFT))&FTM_SC_PWMEN2_MASK)
5131 #define FTM_SC_PWMEN3_MASK 0x80000u
5132 #define FTM_SC_PWMEN3_SHIFT 19u
5133 #define FTM_SC_PWMEN3_WIDTH 1u
5134 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN3_SHIFT))&FTM_SC_PWMEN3_MASK)
5135 #define FTM_SC_PWMEN4_MASK 0x100000u
5136 #define FTM_SC_PWMEN4_SHIFT 20u
5137 #define FTM_SC_PWMEN4_WIDTH 1u
5138 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN4_SHIFT))&FTM_SC_PWMEN4_MASK)
5139 #define FTM_SC_PWMEN5_MASK 0x200000u
5140 #define FTM_SC_PWMEN5_SHIFT 21u
5141 #define FTM_SC_PWMEN5_WIDTH 1u
5142 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN5_SHIFT))&FTM_SC_PWMEN5_MASK)
5143 #define FTM_SC_PWMEN6_MASK 0x400000u
5144 #define FTM_SC_PWMEN6_SHIFT 22u
5145 #define FTM_SC_PWMEN6_WIDTH 1u
5146 #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN6_SHIFT))&FTM_SC_PWMEN6_MASK)
5147 #define FTM_SC_PWMEN7_MASK 0x800000u
5148 #define FTM_SC_PWMEN7_SHIFT 23u
5149 #define FTM_SC_PWMEN7_WIDTH 1u
5150 #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN7_SHIFT))&FTM_SC_PWMEN7_MASK)
5151 #define FTM_SC_FLTPS_MASK 0xF000000u
5152 #define FTM_SC_FLTPS_SHIFT 24u
5153 #define FTM_SC_FLTPS_WIDTH 4u
5154 #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_FLTPS_SHIFT))&FTM_SC_FLTPS_MASK)
5156 #define FTM_CNT_COUNT_MASK 0xFFFFu
5157 #define FTM_CNT_COUNT_SHIFT 0u
5158 #define FTM_CNT_COUNT_WIDTH 16u
5159 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
5161 #define FTM_MOD_MOD_MASK 0xFFFFu
5162 #define FTM_MOD_MOD_SHIFT 0u
5163 #define FTM_MOD_MOD_WIDTH 16u
5164 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
5166 #define FTM_CnSC_DMA_MASK 0x1u
5167 #define FTM_CnSC_DMA_SHIFT 0u
5168 #define FTM_CnSC_DMA_WIDTH 1u
5169 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
5170 #define FTM_CnSC_ICRST_MASK 0x2u
5171 #define FTM_CnSC_ICRST_SHIFT 1u
5172 #define FTM_CnSC_ICRST_WIDTH 1u
5173 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
5174 #define FTM_CnSC_ELSA_MASK 0x4u
5175 #define FTM_CnSC_ELSA_SHIFT 2u
5176 #define FTM_CnSC_ELSA_WIDTH 1u
5177 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
5178 #define FTM_CnSC_ELSB_MASK 0x8u
5179 #define FTM_CnSC_ELSB_SHIFT 3u
5180 #define FTM_CnSC_ELSB_WIDTH 1u
5181 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
5182 #define FTM_CnSC_MSA_MASK 0x10u
5183 #define FTM_CnSC_MSA_SHIFT 4u
5184 #define FTM_CnSC_MSA_WIDTH 1u
5185 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
5186 #define FTM_CnSC_MSB_MASK 0x20u
5187 #define FTM_CnSC_MSB_SHIFT 5u
5188 #define FTM_CnSC_MSB_WIDTH 1u
5189 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
5190 #define FTM_CnSC_CHIE_MASK 0x40u
5191 #define FTM_CnSC_CHIE_SHIFT 6u
5192 #define FTM_CnSC_CHIE_WIDTH 1u
5193 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
5194 #define FTM_CnSC_CHF_MASK 0x80u
5195 #define FTM_CnSC_CHF_SHIFT 7u
5196 #define FTM_CnSC_CHF_WIDTH 1u
5197 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
5198 #define FTM_CnSC_TRIGMODE_MASK 0x100u
5199 #define FTM_CnSC_TRIGMODE_SHIFT 8u
5200 #define FTM_CnSC_TRIGMODE_WIDTH 1u
5201 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_TRIGMODE_SHIFT))&FTM_CnSC_TRIGMODE_MASK)
5202 #define FTM_CnSC_CHIS_MASK 0x200u
5203 #define FTM_CnSC_CHIS_SHIFT 9u
5204 #define FTM_CnSC_CHIS_WIDTH 1u
5205 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIS_SHIFT))&FTM_CnSC_CHIS_MASK)
5206 #define FTM_CnSC_CHOV_MASK 0x400u
5207 #define FTM_CnSC_CHOV_SHIFT 10u
5208 #define FTM_CnSC_CHOV_WIDTH 1u
5209 #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHOV_SHIFT))&FTM_CnSC_CHOV_MASK)
5211 #define FTM_CnV_VAL_MASK 0xFFFFu
5212 #define FTM_CnV_VAL_SHIFT 0u
5213 #define FTM_CnV_VAL_WIDTH 16u
5214 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
5216 #define FTM_CNTIN_INIT_MASK 0xFFFFu
5217 #define FTM_CNTIN_INIT_SHIFT 0u
5218 #define FTM_CNTIN_INIT_WIDTH 16u
5219 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
5221 #define FTM_STATUS_CH0F_MASK 0x1u
5222 #define FTM_STATUS_CH0F_SHIFT 0u
5223 #define FTM_STATUS_CH0F_WIDTH 1u
5224 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
5225 #define FTM_STATUS_CH1F_MASK 0x2u
5226 #define FTM_STATUS_CH1F_SHIFT 1u
5227 #define FTM_STATUS_CH1F_WIDTH 1u
5228 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
5229 #define FTM_STATUS_CH2F_MASK 0x4u
5230 #define FTM_STATUS_CH2F_SHIFT 2u
5231 #define FTM_STATUS_CH2F_WIDTH 1u
5232 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
5233 #define FTM_STATUS_CH3F_MASK 0x8u
5234 #define FTM_STATUS_CH3F_SHIFT 3u
5235 #define FTM_STATUS_CH3F_WIDTH 1u
5236 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
5237 #define FTM_STATUS_CH4F_MASK 0x10u
5238 #define FTM_STATUS_CH4F_SHIFT 4u
5239 #define FTM_STATUS_CH4F_WIDTH 1u
5240 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
5241 #define FTM_STATUS_CH5F_MASK 0x20u
5242 #define FTM_STATUS_CH5F_SHIFT 5u
5243 #define FTM_STATUS_CH5F_WIDTH 1u
5244 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
5245 #define FTM_STATUS_CH6F_MASK 0x40u
5246 #define FTM_STATUS_CH6F_SHIFT 6u
5247 #define FTM_STATUS_CH6F_WIDTH 1u
5248 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
5249 #define FTM_STATUS_CH7F_MASK 0x80u
5250 #define FTM_STATUS_CH7F_SHIFT 7u
5251 #define FTM_STATUS_CH7F_WIDTH 1u
5252 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
5254 #define FTM_MODE_FTMEN_MASK 0x1u
5255 #define FTM_MODE_FTMEN_SHIFT 0u
5256 #define FTM_MODE_FTMEN_WIDTH 1u
5257 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
5258 #define FTM_MODE_INIT_MASK 0x2u
5259 #define FTM_MODE_INIT_SHIFT 1u
5260 #define FTM_MODE_INIT_WIDTH 1u
5261 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
5262 #define FTM_MODE_WPDIS_MASK 0x4u
5263 #define FTM_MODE_WPDIS_SHIFT 2u
5264 #define FTM_MODE_WPDIS_WIDTH 1u
5265 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
5266 #define FTM_MODE_PWMSYNC_MASK 0x8u
5267 #define FTM_MODE_PWMSYNC_SHIFT 3u
5268 #define FTM_MODE_PWMSYNC_WIDTH 1u
5269 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
5270 #define FTM_MODE_CAPTEST_MASK 0x10u
5271 #define FTM_MODE_CAPTEST_SHIFT 4u
5272 #define FTM_MODE_CAPTEST_WIDTH 1u
5273 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
5274 #define FTM_MODE_FAULTM_MASK 0x60u
5275 #define FTM_MODE_FAULTM_SHIFT 5u
5276 #define FTM_MODE_FAULTM_WIDTH 2u
5277 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
5278 #define FTM_MODE_FAULTIE_MASK 0x80u
5279 #define FTM_MODE_FAULTIE_SHIFT 7u
5280 #define FTM_MODE_FAULTIE_WIDTH 1u
5281 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
5283 #define FTM_SYNC_CNTMIN_MASK 0x1u
5284 #define FTM_SYNC_CNTMIN_SHIFT 0u
5285 #define FTM_SYNC_CNTMIN_WIDTH 1u
5286 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
5287 #define FTM_SYNC_CNTMAX_MASK 0x2u
5288 #define FTM_SYNC_CNTMAX_SHIFT 1u
5289 #define FTM_SYNC_CNTMAX_WIDTH 1u
5290 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
5291 #define FTM_SYNC_REINIT_MASK 0x4u
5292 #define FTM_SYNC_REINIT_SHIFT 2u
5293 #define FTM_SYNC_REINIT_WIDTH 1u
5294 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
5295 #define FTM_SYNC_SYNCHOM_MASK 0x8u
5296 #define FTM_SYNC_SYNCHOM_SHIFT 3u
5297 #define FTM_SYNC_SYNCHOM_WIDTH 1u
5298 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
5299 #define FTM_SYNC_TRIG0_MASK 0x10u
5300 #define FTM_SYNC_TRIG0_SHIFT 4u
5301 #define FTM_SYNC_TRIG0_WIDTH 1u
5302 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
5303 #define FTM_SYNC_TRIG1_MASK 0x20u
5304 #define FTM_SYNC_TRIG1_SHIFT 5u
5305 #define FTM_SYNC_TRIG1_WIDTH 1u
5306 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
5307 #define FTM_SYNC_TRIG2_MASK 0x40u
5308 #define FTM_SYNC_TRIG2_SHIFT 6u
5309 #define FTM_SYNC_TRIG2_WIDTH 1u
5310 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
5311 #define FTM_SYNC_SWSYNC_MASK 0x80u
5312 #define FTM_SYNC_SWSYNC_SHIFT 7u
5313 #define FTM_SYNC_SWSYNC_WIDTH 1u
5314 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
5316 #define FTM_OUTINIT_CH0OI_MASK 0x1u
5317 #define FTM_OUTINIT_CH0OI_SHIFT 0u
5318 #define FTM_OUTINIT_CH0OI_WIDTH 1u
5319 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
5320 #define FTM_OUTINIT_CH1OI_MASK 0x2u
5321 #define FTM_OUTINIT_CH1OI_SHIFT 1u
5322 #define FTM_OUTINIT_CH1OI_WIDTH 1u
5323 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
5324 #define FTM_OUTINIT_CH2OI_MASK 0x4u
5325 #define FTM_OUTINIT_CH2OI_SHIFT 2u
5326 #define FTM_OUTINIT_CH2OI_WIDTH 1u
5327 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
5328 #define FTM_OUTINIT_CH3OI_MASK 0x8u
5329 #define FTM_OUTINIT_CH3OI_SHIFT 3u
5330 #define FTM_OUTINIT_CH3OI_WIDTH 1u
5331 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
5332 #define FTM_OUTINIT_CH4OI_MASK 0x10u
5333 #define FTM_OUTINIT_CH4OI_SHIFT 4u
5334 #define FTM_OUTINIT_CH4OI_WIDTH 1u
5335 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
5336 #define FTM_OUTINIT_CH5OI_MASK 0x20u
5337 #define FTM_OUTINIT_CH5OI_SHIFT 5u
5338 #define FTM_OUTINIT_CH5OI_WIDTH 1u
5339 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
5340 #define FTM_OUTINIT_CH6OI_MASK 0x40u
5341 #define FTM_OUTINIT_CH6OI_SHIFT 6u
5342 #define FTM_OUTINIT_CH6OI_WIDTH 1u
5343 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
5344 #define FTM_OUTINIT_CH7OI_MASK 0x80u
5345 #define FTM_OUTINIT_CH7OI_SHIFT 7u
5346 #define FTM_OUTINIT_CH7OI_WIDTH 1u
5347 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
5349 #define FTM_OUTMASK_CH0OM_MASK 0x1u
5350 #define FTM_OUTMASK_CH0OM_SHIFT 0u
5351 #define FTM_OUTMASK_CH0OM_WIDTH 1u
5352 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
5353 #define FTM_OUTMASK_CH1OM_MASK 0x2u
5354 #define FTM_OUTMASK_CH1OM_SHIFT 1u
5355 #define FTM_OUTMASK_CH1OM_WIDTH 1u
5356 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
5357 #define FTM_OUTMASK_CH2OM_MASK 0x4u
5358 #define FTM_OUTMASK_CH2OM_SHIFT 2u
5359 #define FTM_OUTMASK_CH2OM_WIDTH 1u
5360 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
5361 #define FTM_OUTMASK_CH3OM_MASK 0x8u
5362 #define FTM_OUTMASK_CH3OM_SHIFT 3u
5363 #define FTM_OUTMASK_CH3OM_WIDTH 1u
5364 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
5365 #define FTM_OUTMASK_CH4OM_MASK 0x10u
5366 #define FTM_OUTMASK_CH4OM_SHIFT 4u
5367 #define FTM_OUTMASK_CH4OM_WIDTH 1u
5368 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
5369 #define FTM_OUTMASK_CH5OM_MASK 0x20u
5370 #define FTM_OUTMASK_CH5OM_SHIFT 5u
5371 #define FTM_OUTMASK_CH5OM_WIDTH 1u
5372 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
5373 #define FTM_OUTMASK_CH6OM_MASK 0x40u
5374 #define FTM_OUTMASK_CH6OM_SHIFT 6u
5375 #define FTM_OUTMASK_CH6OM_WIDTH 1u
5376 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
5377 #define FTM_OUTMASK_CH7OM_MASK 0x80u
5378 #define FTM_OUTMASK_CH7OM_SHIFT 7u
5379 #define FTM_OUTMASK_CH7OM_WIDTH 1u
5380 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
5382 #define FTM_COMBINE_COMBINE0_MASK 0x1u
5383 #define FTM_COMBINE_COMBINE0_SHIFT 0u
5384 #define FTM_COMBINE_COMBINE0_WIDTH 1u
5385 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
5386 #define FTM_COMBINE_COMP0_MASK 0x2u
5387 #define FTM_COMBINE_COMP0_SHIFT 1u
5388 #define FTM_COMBINE_COMP0_WIDTH 1u
5389 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
5390 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
5391 #define FTM_COMBINE_DECAPEN0_SHIFT 2u
5392 #define FTM_COMBINE_DECAPEN0_WIDTH 1u
5393 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
5394 #define FTM_COMBINE_DECAP0_MASK 0x8u
5395 #define FTM_COMBINE_DECAP0_SHIFT 3u
5396 #define FTM_COMBINE_DECAP0_WIDTH 1u
5397 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
5398 #define FTM_COMBINE_DTEN0_MASK 0x10u
5399 #define FTM_COMBINE_DTEN0_SHIFT 4u
5400 #define FTM_COMBINE_DTEN0_WIDTH 1u
5401 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
5402 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
5403 #define FTM_COMBINE_SYNCEN0_SHIFT 5u
5404 #define FTM_COMBINE_SYNCEN0_WIDTH 1u
5405 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
5406 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
5407 #define FTM_COMBINE_FAULTEN0_SHIFT 6u
5408 #define FTM_COMBINE_FAULTEN0_WIDTH 1u
5409 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
5410 #define FTM_COMBINE_MCOMBINE0_MASK 0x80u
5411 #define FTM_COMBINE_MCOMBINE0_SHIFT 7u
5412 #define FTM_COMBINE_MCOMBINE0_WIDTH 1u
5413 #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE0_SHIFT))&FTM_COMBINE_MCOMBINE0_MASK)
5414 #define FTM_COMBINE_COMBINE1_MASK 0x100u
5415 #define FTM_COMBINE_COMBINE1_SHIFT 8u
5416 #define FTM_COMBINE_COMBINE1_WIDTH 1u
5417 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
5418 #define FTM_COMBINE_COMP1_MASK 0x200u
5419 #define FTM_COMBINE_COMP1_SHIFT 9u
5420 #define FTM_COMBINE_COMP1_WIDTH 1u
5421 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
5422 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
5423 #define FTM_COMBINE_DECAPEN1_SHIFT 10u
5424 #define FTM_COMBINE_DECAPEN1_WIDTH 1u
5425 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
5426 #define FTM_COMBINE_DECAP1_MASK 0x800u
5427 #define FTM_COMBINE_DECAP1_SHIFT 11u
5428 #define FTM_COMBINE_DECAP1_WIDTH 1u
5429 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
5430 #define FTM_COMBINE_DTEN1_MASK 0x1000u
5431 #define FTM_COMBINE_DTEN1_SHIFT 12u
5432 #define FTM_COMBINE_DTEN1_WIDTH 1u
5433 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
5434 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
5435 #define FTM_COMBINE_SYNCEN1_SHIFT 13u
5436 #define FTM_COMBINE_SYNCEN1_WIDTH 1u
5437 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
5438 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
5439 #define FTM_COMBINE_FAULTEN1_SHIFT 14u
5440 #define FTM_COMBINE_FAULTEN1_WIDTH 1u
5441 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
5442 #define FTM_COMBINE_MCOMBINE1_MASK 0x8000u
5443 #define FTM_COMBINE_MCOMBINE1_SHIFT 15u
5444 #define FTM_COMBINE_MCOMBINE1_WIDTH 1u
5445 #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE1_SHIFT))&FTM_COMBINE_MCOMBINE1_MASK)
5446 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
5447 #define FTM_COMBINE_COMBINE2_SHIFT 16u
5448 #define FTM_COMBINE_COMBINE2_WIDTH 1u
5449 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
5450 #define FTM_COMBINE_COMP2_MASK 0x20000u
5451 #define FTM_COMBINE_COMP2_SHIFT 17u
5452 #define FTM_COMBINE_COMP2_WIDTH 1u
5453 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
5454 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
5455 #define FTM_COMBINE_DECAPEN2_SHIFT 18u
5456 #define FTM_COMBINE_DECAPEN2_WIDTH 1u
5457 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
5458 #define FTM_COMBINE_DECAP2_MASK 0x80000u
5459 #define FTM_COMBINE_DECAP2_SHIFT 19u
5460 #define FTM_COMBINE_DECAP2_WIDTH 1u
5461 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
5462 #define FTM_COMBINE_DTEN2_MASK 0x100000u
5463 #define FTM_COMBINE_DTEN2_SHIFT 20u
5464 #define FTM_COMBINE_DTEN2_WIDTH 1u
5465 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
5466 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
5467 #define FTM_COMBINE_SYNCEN2_SHIFT 21u
5468 #define FTM_COMBINE_SYNCEN2_WIDTH 1u
5469 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
5470 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
5471 #define FTM_COMBINE_FAULTEN2_SHIFT 22u
5472 #define FTM_COMBINE_FAULTEN2_WIDTH 1u
5473 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
5474 #define FTM_COMBINE_MCOMBINE2_MASK 0x800000u
5475 #define FTM_COMBINE_MCOMBINE2_SHIFT 23u
5476 #define FTM_COMBINE_MCOMBINE2_WIDTH 1u
5477 #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE2_SHIFT))&FTM_COMBINE_MCOMBINE2_MASK)
5478 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
5479 #define FTM_COMBINE_COMBINE3_SHIFT 24u
5480 #define FTM_COMBINE_COMBINE3_WIDTH 1u
5481 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
5482 #define FTM_COMBINE_COMP3_MASK 0x2000000u
5483 #define FTM_COMBINE_COMP3_SHIFT 25u
5484 #define FTM_COMBINE_COMP3_WIDTH 1u
5485 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
5486 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
5487 #define FTM_COMBINE_DECAPEN3_SHIFT 26u
5488 #define FTM_COMBINE_DECAPEN3_WIDTH 1u
5489 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
5490 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
5491 #define FTM_COMBINE_DECAP3_SHIFT 27u
5492 #define FTM_COMBINE_DECAP3_WIDTH 1u
5493 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
5494 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
5495 #define FTM_COMBINE_DTEN3_SHIFT 28u
5496 #define FTM_COMBINE_DTEN3_WIDTH 1u
5497 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
5498 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
5499 #define FTM_COMBINE_SYNCEN3_SHIFT 29u
5500 #define FTM_COMBINE_SYNCEN3_WIDTH 1u
5501 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
5502 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
5503 #define FTM_COMBINE_FAULTEN3_SHIFT 30u
5504 #define FTM_COMBINE_FAULTEN3_WIDTH 1u
5505 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
5506 #define FTM_COMBINE_MCOMBINE3_MASK 0x80000000u
5507 #define FTM_COMBINE_MCOMBINE3_SHIFT 31u
5508 #define FTM_COMBINE_MCOMBINE3_WIDTH 1u
5509 #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE3_SHIFT))&FTM_COMBINE_MCOMBINE3_MASK)
5511 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
5512 #define FTM_DEADTIME_DTVAL_SHIFT 0u
5513 #define FTM_DEADTIME_DTVAL_WIDTH 6u
5514 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
5515 #define FTM_DEADTIME_DTPS_MASK 0xC0u
5516 #define FTM_DEADTIME_DTPS_SHIFT 6u
5517 #define FTM_DEADTIME_DTPS_WIDTH 2u
5518 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
5519 #define FTM_DEADTIME_DTVALEX_MASK 0xF0000u
5520 #define FTM_DEADTIME_DTVALEX_SHIFT 16u
5521 #define FTM_DEADTIME_DTVALEX_WIDTH 4u
5522 #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVALEX_SHIFT))&FTM_DEADTIME_DTVALEX_MASK)
5524 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
5525 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0u
5526 #define FTM_EXTTRIG_CH2TRIG_WIDTH 1u
5527 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
5528 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
5529 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1u
5530 #define FTM_EXTTRIG_CH3TRIG_WIDTH 1u
5531 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
5532 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
5533 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2u
5534 #define FTM_EXTTRIG_CH4TRIG_WIDTH 1u
5535 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
5536 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
5537 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3u
5538 #define FTM_EXTTRIG_CH5TRIG_WIDTH 1u
5539 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
5540 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
5541 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4u
5542 #define FTM_EXTTRIG_CH0TRIG_WIDTH 1u
5543 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
5544 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
5545 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5u
5546 #define FTM_EXTTRIG_CH1TRIG_WIDTH 1u
5547 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
5548 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
5549 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6u
5550 #define FTM_EXTTRIG_INITTRIGEN_WIDTH 1u
5551 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
5552 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
5553 #define FTM_EXTTRIG_TRIGF_SHIFT 7u
5554 #define FTM_EXTTRIG_TRIGF_WIDTH 1u
5555 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
5556 #define FTM_EXTTRIG_CH6TRIG_MASK 0x100u
5557 #define FTM_EXTTRIG_CH6TRIG_SHIFT 8u
5558 #define FTM_EXTTRIG_CH6TRIG_WIDTH 1u
5559 #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH6TRIG_SHIFT))&FTM_EXTTRIG_CH6TRIG_MASK)
5560 #define FTM_EXTTRIG_CH7TRIG_MASK 0x200u
5561 #define FTM_EXTTRIG_CH7TRIG_SHIFT 9u
5562 #define FTM_EXTTRIG_CH7TRIG_WIDTH 1u
5563 #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH7TRIG_SHIFT))&FTM_EXTTRIG_CH7TRIG_MASK)
5565 #define FTM_POL_POL0_MASK 0x1u
5566 #define FTM_POL_POL0_SHIFT 0u
5567 #define FTM_POL_POL0_WIDTH 1u
5568 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
5569 #define FTM_POL_POL1_MASK 0x2u
5570 #define FTM_POL_POL1_SHIFT 1u
5571 #define FTM_POL_POL1_WIDTH 1u
5572 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
5573 #define FTM_POL_POL2_MASK 0x4u
5574 #define FTM_POL_POL2_SHIFT 2u
5575 #define FTM_POL_POL2_WIDTH 1u
5576 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
5577 #define FTM_POL_POL3_MASK 0x8u
5578 #define FTM_POL_POL3_SHIFT 3u
5579 #define FTM_POL_POL3_WIDTH 1u
5580 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
5581 #define FTM_POL_POL4_MASK 0x10u
5582 #define FTM_POL_POL4_SHIFT 4u
5583 #define FTM_POL_POL4_WIDTH 1u
5584 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
5585 #define FTM_POL_POL5_MASK 0x20u
5586 #define FTM_POL_POL5_SHIFT 5u
5587 #define FTM_POL_POL5_WIDTH 1u
5588 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
5589 #define FTM_POL_POL6_MASK 0x40u
5590 #define FTM_POL_POL6_SHIFT 6u
5591 #define FTM_POL_POL6_WIDTH 1u
5592 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
5593 #define FTM_POL_POL7_MASK 0x80u
5594 #define FTM_POL_POL7_SHIFT 7u
5595 #define FTM_POL_POL7_WIDTH 1u
5596 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
5598 #define FTM_FMS_FAULTF0_MASK 0x1u
5599 #define FTM_FMS_FAULTF0_SHIFT 0u
5600 #define FTM_FMS_FAULTF0_WIDTH 1u
5601 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
5602 #define FTM_FMS_FAULTF1_MASK 0x2u
5603 #define FTM_FMS_FAULTF1_SHIFT 1u
5604 #define FTM_FMS_FAULTF1_WIDTH 1u
5605 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
5606 #define FTM_FMS_FAULTF2_MASK 0x4u
5607 #define FTM_FMS_FAULTF2_SHIFT 2u
5608 #define FTM_FMS_FAULTF2_WIDTH 1u
5609 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
5610 #define FTM_FMS_FAULTF3_MASK 0x8u
5611 #define FTM_FMS_FAULTF3_SHIFT 3u
5612 #define FTM_FMS_FAULTF3_WIDTH 1u
5613 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
5614 #define FTM_FMS_FAULTIN_MASK 0x20u
5615 #define FTM_FMS_FAULTIN_SHIFT 5u
5616 #define FTM_FMS_FAULTIN_WIDTH 1u
5617 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
5618 #define FTM_FMS_WPEN_MASK 0x40u
5619 #define FTM_FMS_WPEN_SHIFT 6u
5620 #define FTM_FMS_WPEN_WIDTH 1u
5621 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
5622 #define FTM_FMS_FAULTF_MASK 0x80u
5623 #define FTM_FMS_FAULTF_SHIFT 7u
5624 #define FTM_FMS_FAULTF_WIDTH 1u
5625 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
5627 #define FTM_FILTER_CH0FVAL_MASK 0xFu
5628 #define FTM_FILTER_CH0FVAL_SHIFT 0u
5629 #define FTM_FILTER_CH0FVAL_WIDTH 4u
5630 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
5631 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
5632 #define FTM_FILTER_CH1FVAL_SHIFT 4u
5633 #define FTM_FILTER_CH1FVAL_WIDTH 4u
5634 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
5635 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
5636 #define FTM_FILTER_CH2FVAL_SHIFT 8u
5637 #define FTM_FILTER_CH2FVAL_WIDTH 4u
5638 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
5639 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
5640 #define FTM_FILTER_CH3FVAL_SHIFT 12u
5641 #define FTM_FILTER_CH3FVAL_WIDTH 4u
5642 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
5644 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
5645 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0u
5646 #define FTM_FLTCTRL_FAULT0EN_WIDTH 1u
5647 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
5648 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
5649 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1u
5650 #define FTM_FLTCTRL_FAULT1EN_WIDTH 1u
5651 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
5652 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
5653 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2u
5654 #define FTM_FLTCTRL_FAULT2EN_WIDTH 1u
5655 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
5656 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
5657 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3u
5658 #define FTM_FLTCTRL_FAULT3EN_WIDTH 1u
5659 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
5660 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
5661 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4u
5662 #define FTM_FLTCTRL_FFLTR0EN_WIDTH 1u
5663 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
5664 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
5665 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5u
5666 #define FTM_FLTCTRL_FFLTR1EN_WIDTH 1u
5667 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
5668 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
5669 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6u
5670 #define FTM_FLTCTRL_FFLTR2EN_WIDTH 1u
5671 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
5672 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
5673 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7u
5674 #define FTM_FLTCTRL_FFLTR3EN_WIDTH 1u
5675 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
5676 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
5677 #define FTM_FLTCTRL_FFVAL_SHIFT 8u
5678 #define FTM_FLTCTRL_FFVAL_WIDTH 4u
5679 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
5680 #define FTM_FLTCTRL_FSTATE_MASK 0x8000u
5681 #define FTM_FLTCTRL_FSTATE_SHIFT 15u
5682 #define FTM_FLTCTRL_FSTATE_WIDTH 1u
5683 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FSTATE_SHIFT))&FTM_FLTCTRL_FSTATE_MASK)
5685 #define FTM_QDCTRL_QUADEN_MASK 0x1u
5686 #define FTM_QDCTRL_QUADEN_SHIFT 0u
5687 #define FTM_QDCTRL_QUADEN_WIDTH 1u
5688 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
5689 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
5690 #define FTM_QDCTRL_TOFDIR_SHIFT 1u
5691 #define FTM_QDCTRL_TOFDIR_WIDTH 1u
5692 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
5693 #define FTM_QDCTRL_QUADIR_MASK 0x4u
5694 #define FTM_QDCTRL_QUADIR_SHIFT 2u
5695 #define FTM_QDCTRL_QUADIR_WIDTH 1u
5696 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
5697 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
5698 #define FTM_QDCTRL_QUADMODE_SHIFT 3u
5699 #define FTM_QDCTRL_QUADMODE_WIDTH 1u
5700 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
5701 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
5702 #define FTM_QDCTRL_PHBPOL_SHIFT 4u
5703 #define FTM_QDCTRL_PHBPOL_WIDTH 1u
5704 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
5705 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
5706 #define FTM_QDCTRL_PHAPOL_SHIFT 5u
5707 #define FTM_QDCTRL_PHAPOL_WIDTH 1u
5708 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
5709 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
5710 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6u
5711 #define FTM_QDCTRL_PHBFLTREN_WIDTH 1u
5712 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
5713 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
5714 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7u
5715 #define FTM_QDCTRL_PHAFLTREN_WIDTH 1u
5716 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
5718 #define FTM_CONF_LDFQ_MASK 0x1Fu
5719 #define FTM_CONF_LDFQ_SHIFT 0u
5720 #define FTM_CONF_LDFQ_WIDTH 5u
5721 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_LDFQ_SHIFT))&FTM_CONF_LDFQ_MASK)
5722 #define FTM_CONF_BDMMODE_MASK 0xC0u
5723 #define FTM_CONF_BDMMODE_SHIFT 6u
5724 #define FTM_CONF_BDMMODE_WIDTH 2u
5725 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
5726 #define FTM_CONF_GTBEEN_MASK 0x200u
5727 #define FTM_CONF_GTBEEN_SHIFT 9u
5728 #define FTM_CONF_GTBEEN_WIDTH 1u
5729 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
5730 #define FTM_CONF_GTBEOUT_MASK 0x400u
5731 #define FTM_CONF_GTBEOUT_SHIFT 10u
5732 #define FTM_CONF_GTBEOUT_WIDTH 1u
5733 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
5734 #define FTM_CONF_ITRIGR_MASK 0x800u
5735 #define FTM_CONF_ITRIGR_SHIFT 11u
5736 #define FTM_CONF_ITRIGR_WIDTH 1u
5737 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_ITRIGR_SHIFT))&FTM_CONF_ITRIGR_MASK)
5739 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
5740 #define FTM_FLTPOL_FLT0POL_SHIFT 0u
5741 #define FTM_FLTPOL_FLT0POL_WIDTH 1u
5742 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
5743 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
5744 #define FTM_FLTPOL_FLT1POL_SHIFT 1u
5745 #define FTM_FLTPOL_FLT1POL_WIDTH 1u
5746 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
5747 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
5748 #define FTM_FLTPOL_FLT2POL_SHIFT 2u
5749 #define FTM_FLTPOL_FLT2POL_WIDTH 1u
5750 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
5751 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
5752 #define FTM_FLTPOL_FLT3POL_SHIFT 3u
5753 #define FTM_FLTPOL_FLT3POL_WIDTH 1u
5754 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
5756 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
5757 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0u
5758 #define FTM_SYNCONF_HWTRIGMODE_WIDTH 1u
5759 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
5760 #define FTM_SYNCONF_CNTINC_MASK 0x4u
5761 #define FTM_SYNCONF_CNTINC_SHIFT 2u
5762 #define FTM_SYNCONF_CNTINC_WIDTH 1u
5763 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
5764 #define FTM_SYNCONF_INVC_MASK 0x10u
5765 #define FTM_SYNCONF_INVC_SHIFT 4u
5766 #define FTM_SYNCONF_INVC_WIDTH 1u
5767 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
5768 #define FTM_SYNCONF_SWOC_MASK 0x20u
5769 #define FTM_SYNCONF_SWOC_SHIFT 5u
5770 #define FTM_SYNCONF_SWOC_WIDTH 1u
5771 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
5772 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
5773 #define FTM_SYNCONF_SYNCMODE_SHIFT 7u
5774 #define FTM_SYNCONF_SYNCMODE_WIDTH 1u
5775 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
5776 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
5777 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8u
5778 #define FTM_SYNCONF_SWRSTCNT_WIDTH 1u
5779 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
5780 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
5781 #define FTM_SYNCONF_SWWRBUF_SHIFT 9u
5782 #define FTM_SYNCONF_SWWRBUF_WIDTH 1u
5783 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
5784 #define FTM_SYNCONF_SWOM_MASK 0x400u
5785 #define FTM_SYNCONF_SWOM_SHIFT 10u
5786 #define FTM_SYNCONF_SWOM_WIDTH 1u
5787 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
5788 #define FTM_SYNCONF_SWINVC_MASK 0x800u
5789 #define FTM_SYNCONF_SWINVC_SHIFT 11u
5790 #define FTM_SYNCONF_SWINVC_WIDTH 1u
5791 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
5792 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
5793 #define FTM_SYNCONF_SWSOC_SHIFT 12u
5794 #define FTM_SYNCONF_SWSOC_WIDTH 1u
5795 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
5796 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
5797 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16u
5798 #define FTM_SYNCONF_HWRSTCNT_WIDTH 1u
5799 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
5800 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
5801 #define FTM_SYNCONF_HWWRBUF_SHIFT 17u
5802 #define FTM_SYNCONF_HWWRBUF_WIDTH 1u
5803 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
5804 #define FTM_SYNCONF_HWOM_MASK 0x40000u
5805 #define FTM_SYNCONF_HWOM_SHIFT 18u
5806 #define FTM_SYNCONF_HWOM_WIDTH 1u
5807 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
5808 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
5809 #define FTM_SYNCONF_HWINVC_SHIFT 19u
5810 #define FTM_SYNCONF_HWINVC_WIDTH 1u
5811 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
5812 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
5813 #define FTM_SYNCONF_HWSOC_SHIFT 20u
5814 #define FTM_SYNCONF_HWSOC_WIDTH 1u
5815 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
5817 #define FTM_INVCTRL_INV0EN_MASK 0x1u
5818 #define FTM_INVCTRL_INV0EN_SHIFT 0u
5819 #define FTM_INVCTRL_INV0EN_WIDTH 1u
5820 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
5821 #define FTM_INVCTRL_INV1EN_MASK 0x2u
5822 #define FTM_INVCTRL_INV1EN_SHIFT 1u
5823 #define FTM_INVCTRL_INV1EN_WIDTH 1u
5824 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
5825 #define FTM_INVCTRL_INV2EN_MASK 0x4u
5826 #define FTM_INVCTRL_INV2EN_SHIFT 2u
5827 #define FTM_INVCTRL_INV2EN_WIDTH 1u
5828 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
5829 #define FTM_INVCTRL_INV3EN_MASK 0x8u
5830 #define FTM_INVCTRL_INV3EN_SHIFT 3u
5831 #define FTM_INVCTRL_INV3EN_WIDTH 1u
5832 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
5834 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
5835 #define FTM_SWOCTRL_CH0OC_SHIFT 0u
5836 #define FTM_SWOCTRL_CH0OC_WIDTH 1u
5837 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
5838 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
5839 #define FTM_SWOCTRL_CH1OC_SHIFT 1u
5840 #define FTM_SWOCTRL_CH1OC_WIDTH 1u
5841 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
5842 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
5843 #define FTM_SWOCTRL_CH2OC_SHIFT 2u
5844 #define FTM_SWOCTRL_CH2OC_WIDTH 1u
5845 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
5846 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
5847 #define FTM_SWOCTRL_CH3OC_SHIFT 3u
5848 #define FTM_SWOCTRL_CH3OC_WIDTH 1u
5849 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
5850 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
5851 #define FTM_SWOCTRL_CH4OC_SHIFT 4u
5852 #define FTM_SWOCTRL_CH4OC_WIDTH 1u
5853 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
5854 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
5855 #define FTM_SWOCTRL_CH5OC_SHIFT 5u
5856 #define FTM_SWOCTRL_CH5OC_WIDTH 1u
5857 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
5858 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
5859 #define FTM_SWOCTRL_CH6OC_SHIFT 6u
5860 #define FTM_SWOCTRL_CH6OC_WIDTH 1u
5861 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
5862 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
5863 #define FTM_SWOCTRL_CH7OC_SHIFT 7u
5864 #define FTM_SWOCTRL_CH7OC_WIDTH 1u
5865 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
5866 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
5867 #define FTM_SWOCTRL_CH0OCV_SHIFT 8u
5868 #define FTM_SWOCTRL_CH0OCV_WIDTH 1u
5869 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
5870 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
5871 #define FTM_SWOCTRL_CH1OCV_SHIFT 9u
5872 #define FTM_SWOCTRL_CH1OCV_WIDTH 1u
5873 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
5874 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
5875 #define FTM_SWOCTRL_CH2OCV_SHIFT 10u
5876 #define FTM_SWOCTRL_CH2OCV_WIDTH 1u
5877 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
5878 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
5879 #define FTM_SWOCTRL_CH3OCV_SHIFT 11u
5880 #define FTM_SWOCTRL_CH3OCV_WIDTH 1u
5881 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
5882 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
5883 #define FTM_SWOCTRL_CH4OCV_SHIFT 12u
5884 #define FTM_SWOCTRL_CH4OCV_WIDTH 1u
5885 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
5886 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
5887 #define FTM_SWOCTRL_CH5OCV_SHIFT 13u
5888 #define FTM_SWOCTRL_CH5OCV_WIDTH 1u
5889 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
5890 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
5891 #define FTM_SWOCTRL_CH6OCV_SHIFT 14u
5892 #define FTM_SWOCTRL_CH6OCV_WIDTH 1u
5893 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
5894 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
5895 #define FTM_SWOCTRL_CH7OCV_SHIFT 15u
5896 #define FTM_SWOCTRL_CH7OCV_WIDTH 1u
5897 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
5899 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
5900 #define FTM_PWMLOAD_CH0SEL_SHIFT 0u
5901 #define FTM_PWMLOAD_CH0SEL_WIDTH 1u
5902 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
5903 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
5904 #define FTM_PWMLOAD_CH1SEL_SHIFT 1u
5905 #define FTM_PWMLOAD_CH1SEL_WIDTH 1u
5906 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
5907 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
5908 #define FTM_PWMLOAD_CH2SEL_SHIFT 2u
5909 #define FTM_PWMLOAD_CH2SEL_WIDTH 1u
5910 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
5911 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
5912 #define FTM_PWMLOAD_CH3SEL_SHIFT 3u
5913 #define FTM_PWMLOAD_CH3SEL_WIDTH 1u
5914 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
5915 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
5916 #define FTM_PWMLOAD_CH4SEL_SHIFT 4u
5917 #define FTM_PWMLOAD_CH4SEL_WIDTH 1u
5918 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
5919 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
5920 #define FTM_PWMLOAD_CH5SEL_SHIFT 5u
5921 #define FTM_PWMLOAD_CH5SEL_WIDTH 1u
5922 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
5923 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
5924 #define FTM_PWMLOAD_CH6SEL_SHIFT 6u
5925 #define FTM_PWMLOAD_CH6SEL_WIDTH 1u
5926 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
5927 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
5928 #define FTM_PWMLOAD_CH7SEL_SHIFT 7u
5929 #define FTM_PWMLOAD_CH7SEL_WIDTH 1u
5930 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
5931 #define FTM_PWMLOAD_HCSEL_MASK 0x100u
5932 #define FTM_PWMLOAD_HCSEL_SHIFT 8u
5933 #define FTM_PWMLOAD_HCSEL_WIDTH 1u
5934 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_HCSEL_SHIFT))&FTM_PWMLOAD_HCSEL_MASK)
5935 #define FTM_PWMLOAD_LDOK_MASK 0x200u
5936 #define FTM_PWMLOAD_LDOK_SHIFT 9u
5937 #define FTM_PWMLOAD_LDOK_WIDTH 1u
5938 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
5939 #define FTM_PWMLOAD_GLEN_MASK 0x400u
5940 #define FTM_PWMLOAD_GLEN_SHIFT 10u
5941 #define FTM_PWMLOAD_GLEN_WIDTH 1u
5942 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLEN_SHIFT))&FTM_PWMLOAD_GLEN_MASK)
5943 #define FTM_PWMLOAD_GLDOK_MASK 0x800u
5944 #define FTM_PWMLOAD_GLDOK_SHIFT 11u
5945 #define FTM_PWMLOAD_GLDOK_WIDTH 1u
5946 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLDOK_SHIFT))&FTM_PWMLOAD_GLDOK_MASK)
5948 #define FTM_HCR_HCVAL_MASK 0xFFFFu
5949 #define FTM_HCR_HCVAL_SHIFT 0u
5950 #define FTM_HCR_HCVAL_WIDTH 16u
5951 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_HCR_HCVAL_SHIFT))&FTM_HCR_HCVAL_MASK)
5953 #define FTM_PAIR0DEADTIME_DTVAL_MASK 0x3Fu
5954 #define FTM_PAIR0DEADTIME_DTVAL_SHIFT 0u
5955 #define FTM_PAIR0DEADTIME_DTVAL_WIDTH 6u
5956 #define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVAL_SHIFT))&FTM_PAIR0DEADTIME_DTVAL_MASK)
5957 #define FTM_PAIR0DEADTIME_DTPS_MASK 0xC0u
5958 #define FTM_PAIR0DEADTIME_DTPS_SHIFT 6u
5959 #define FTM_PAIR0DEADTIME_DTPS_WIDTH 2u
5960 #define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTPS_SHIFT))&FTM_PAIR0DEADTIME_DTPS_MASK)
5961 #define FTM_PAIR0DEADTIME_DTVALEX_MASK 0xF0000u
5962 #define FTM_PAIR0DEADTIME_DTVALEX_SHIFT 16u
5963 #define FTM_PAIR0DEADTIME_DTVALEX_WIDTH 4u
5964 #define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVALEX_SHIFT))&FTM_PAIR0DEADTIME_DTVALEX_MASK)
5966 #define FTM_PAIR1DEADTIME_DTVAL_MASK 0x3Fu
5967 #define FTM_PAIR1DEADTIME_DTVAL_SHIFT 0u
5968 #define FTM_PAIR1DEADTIME_DTVAL_WIDTH 6u
5969 #define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVAL_SHIFT))&FTM_PAIR1DEADTIME_DTVAL_MASK)
5970 #define FTM_PAIR1DEADTIME_DTPS_MASK 0xC0u
5971 #define FTM_PAIR1DEADTIME_DTPS_SHIFT 6u
5972 #define FTM_PAIR1DEADTIME_DTPS_WIDTH 2u
5973 #define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTPS_SHIFT))&FTM_PAIR1DEADTIME_DTPS_MASK)
5974 #define FTM_PAIR1DEADTIME_DTVALEX_MASK 0xF0000u
5975 #define FTM_PAIR1DEADTIME_DTVALEX_SHIFT 16u
5976 #define FTM_PAIR1DEADTIME_DTVALEX_WIDTH 4u
5977 #define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVALEX_SHIFT))&FTM_PAIR1DEADTIME_DTVALEX_MASK)
5979 #define FTM_PAIR2DEADTIME_DTVAL_MASK 0x3Fu
5980 #define FTM_PAIR2DEADTIME_DTVAL_SHIFT 0u
5981 #define FTM_PAIR2DEADTIME_DTVAL_WIDTH 6u
5982 #define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVAL_SHIFT))&FTM_PAIR2DEADTIME_DTVAL_MASK)
5983 #define FTM_PAIR2DEADTIME_DTPS_MASK 0xC0u
5984 #define FTM_PAIR2DEADTIME_DTPS_SHIFT 6u
5985 #define FTM_PAIR2DEADTIME_DTPS_WIDTH 2u
5986 #define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTPS_SHIFT))&FTM_PAIR2DEADTIME_DTPS_MASK)
5987 #define FTM_PAIR2DEADTIME_DTVALEX_MASK 0xF0000u
5988 #define FTM_PAIR2DEADTIME_DTVALEX_SHIFT 16u
5989 #define FTM_PAIR2DEADTIME_DTVALEX_WIDTH 4u
5990 #define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVALEX_SHIFT))&FTM_PAIR2DEADTIME_DTVALEX_MASK)
5992 #define FTM_PAIR3DEADTIME_DTVAL_MASK 0x3Fu
5993 #define FTM_PAIR3DEADTIME_DTVAL_SHIFT 0u
5994 #define FTM_PAIR3DEADTIME_DTVAL_WIDTH 6u
5995 #define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVAL_SHIFT))&FTM_PAIR3DEADTIME_DTVAL_MASK)
5996 #define FTM_PAIR3DEADTIME_DTPS_MASK 0xC0u
5997 #define FTM_PAIR3DEADTIME_DTPS_SHIFT 6u
5998 #define FTM_PAIR3DEADTIME_DTPS_WIDTH 2u
5999 #define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTPS_SHIFT))&FTM_PAIR3DEADTIME_DTPS_MASK)
6000 #define FTM_PAIR3DEADTIME_DTVALEX_MASK 0xF0000u
6001 #define FTM_PAIR3DEADTIME_DTVALEX_SHIFT 16u
6002 #define FTM_PAIR3DEADTIME_DTVALEX_WIDTH 4u
6003 #define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVALEX_SHIFT))&FTM_PAIR3DEADTIME_DTVALEX_MASK)
6005 #define FTM_MOD_MIRROR_FRACMOD_MASK 0xF800u
6006 #define FTM_MOD_MIRROR_FRACMOD_SHIFT 11u
6007 #define FTM_MOD_MIRROR_FRACMOD_WIDTH 5u
6008 #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_FRACMOD_SHIFT))&FTM_MOD_MIRROR_FRACMOD_MASK)
6009 #define FTM_MOD_MIRROR_MOD_MASK 0xFFFF0000u
6010 #define FTM_MOD_MIRROR_MOD_SHIFT 16u
6011 #define FTM_MOD_MIRROR_MOD_WIDTH 16u
6012 #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_MOD_SHIFT))&FTM_MOD_MIRROR_MOD_MASK)
6014 #define FTM_CV_MIRROR_FRACVAL_MASK 0xF800u
6015 #define FTM_CV_MIRROR_FRACVAL_SHIFT 11u
6016 #define FTM_CV_MIRROR_FRACVAL_WIDTH 5u
6017 #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_FRACVAL_SHIFT))&FTM_CV_MIRROR_FRACVAL_MASK)
6018 #define FTM_CV_MIRROR_VAL_MASK 0xFFFF0000u
6019 #define FTM_CV_MIRROR_VAL_SHIFT 16u
6020 #define FTM_CV_MIRROR_VAL_WIDTH 16u
6021 #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_VAL_SHIFT))&FTM_CV_MIRROR_VAL_MASK)
6057 #define GPIO_INSTANCE_COUNT (5u)
6062 #define PTA_BASE (0x400FF000u)
6064 #define PTA ((GPIO_Type *)PTA_BASE)
6066 #define PTB_BASE (0x400FF040u)
6068 #define PTB ((GPIO_Type *)PTB_BASE)
6070 #define PTC_BASE (0x400FF080u)
6072 #define PTC ((GPIO_Type *)PTC_BASE)
6074 #define PTD_BASE (0x400FF0C0u)
6076 #define PTD ((GPIO_Type *)PTD_BASE)
6078 #define PTE_BASE (0x400FF100u)
6080 #define PTE ((GPIO_Type *)PTE_BASE)
6082 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
6084 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
6096 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
6097 #define GPIO_PDOR_PDO_SHIFT 0u
6098 #define GPIO_PDOR_PDO_WIDTH 32u
6099 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
6101 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
6102 #define GPIO_PSOR_PTSO_SHIFT 0u
6103 #define GPIO_PSOR_PTSO_WIDTH 32u
6104 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
6106 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
6107 #define GPIO_PCOR_PTCO_SHIFT 0u
6108 #define GPIO_PCOR_PTCO_WIDTH 32u
6109 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
6111 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
6112 #define GPIO_PTOR_PTTO_SHIFT 0u
6113 #define GPIO_PTOR_PTTO_WIDTH 32u
6114 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
6116 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
6117 #define GPIO_PDIR_PDI_SHIFT 0u
6118 #define GPIO_PDIR_PDI_WIDTH 32u
6119 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
6121 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
6122 #define GPIO_PDDR_PDD_SHIFT 0u
6123 #define GPIO_PDDR_PDD_WIDTH 32u
6124 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
6126 #define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
6127 #define GPIO_PIDR_PID_SHIFT 0u
6128 #define GPIO_PIDR_PID_WIDTH 32u
6129 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
6159 uint8_t RESERVED_0[16];
6164 #define LMEM_INSTANCE_COUNT (1u)
6169 #define LMEM_BASE (0xE0082000u)
6171 #define LMEM ((LMEM_Type *)LMEM_BASE)
6173 #define LMEM_BASE_ADDRS { LMEM_BASE }
6175 #define LMEM_BASE_PTRS { LMEM }
6187 #define LMEM_PCCCR_ENCACHE_MASK 0x1u
6188 #define LMEM_PCCCR_ENCACHE_SHIFT 0u
6189 #define LMEM_PCCCR_ENCACHE_WIDTH 1u
6190 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_ENCACHE_SHIFT))&LMEM_PCCCR_ENCACHE_MASK)
6191 #define LMEM_PCCCR_PCCR2_MASK 0x4u
6192 #define LMEM_PCCCR_PCCR2_SHIFT 2u
6193 #define LMEM_PCCCR_PCCR2_WIDTH 1u
6194 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR2_SHIFT))&LMEM_PCCCR_PCCR2_MASK)
6195 #define LMEM_PCCCR_PCCR3_MASK 0x8u
6196 #define LMEM_PCCCR_PCCR3_SHIFT 3u
6197 #define LMEM_PCCCR_PCCR3_WIDTH 1u
6198 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR3_SHIFT))&LMEM_PCCCR_PCCR3_MASK)
6199 #define LMEM_PCCCR_INVW0_MASK 0x1000000u
6200 #define LMEM_PCCCR_INVW0_SHIFT 24u
6201 #define LMEM_PCCCR_INVW0_WIDTH 1u
6202 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW0_SHIFT))&LMEM_PCCCR_INVW0_MASK)
6203 #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u
6204 #define LMEM_PCCCR_PUSHW0_SHIFT 25u
6205 #define LMEM_PCCCR_PUSHW0_WIDTH 1u
6206 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW0_SHIFT))&LMEM_PCCCR_PUSHW0_MASK)
6207 #define LMEM_PCCCR_INVW1_MASK 0x4000000u
6208 #define LMEM_PCCCR_INVW1_SHIFT 26u
6209 #define LMEM_PCCCR_INVW1_WIDTH 1u
6210 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW1_SHIFT))&LMEM_PCCCR_INVW1_MASK)
6211 #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u
6212 #define LMEM_PCCCR_PUSHW1_SHIFT 27u
6213 #define LMEM_PCCCR_PUSHW1_WIDTH 1u
6214 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW1_SHIFT))&LMEM_PCCCR_PUSHW1_MASK)
6215 #define LMEM_PCCCR_GO_MASK 0x80000000u
6216 #define LMEM_PCCCR_GO_SHIFT 31u
6217 #define LMEM_PCCCR_GO_WIDTH 1u
6218 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_GO_SHIFT))&LMEM_PCCCR_GO_MASK)
6220 #define LMEM_PCCLCR_LGO_MASK 0x1u
6221 #define LMEM_PCCLCR_LGO_SHIFT 0u
6222 #define LMEM_PCCLCR_LGO_WIDTH 1u
6223 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LGO_SHIFT))&LMEM_PCCLCR_LGO_MASK)
6224 #define LMEM_PCCLCR_CACHEADDR_MASK 0x3FFCu
6225 #define LMEM_PCCLCR_CACHEADDR_SHIFT 2u
6226 #define LMEM_PCCLCR_CACHEADDR_WIDTH 12u
6227 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
6228 #define LMEM_PCCLCR_WSEL_MASK 0x4000u
6229 #define LMEM_PCCLCR_WSEL_SHIFT 14u
6230 #define LMEM_PCCLCR_WSEL_WIDTH 1u
6231 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_WSEL_SHIFT))&LMEM_PCCLCR_WSEL_MASK)
6232 #define LMEM_PCCLCR_TDSEL_MASK 0x10000u
6233 #define LMEM_PCCLCR_TDSEL_SHIFT 16u
6234 #define LMEM_PCCLCR_TDSEL_WIDTH 1u
6235 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_TDSEL_SHIFT))&LMEM_PCCLCR_TDSEL_MASK)
6236 #define LMEM_PCCLCR_LCIVB_MASK 0x100000u
6237 #define LMEM_PCCLCR_LCIVB_SHIFT 20u
6238 #define LMEM_PCCLCR_LCIVB_WIDTH 1u
6239 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIVB_SHIFT))&LMEM_PCCLCR_LCIVB_MASK)
6240 #define LMEM_PCCLCR_LCIMB_MASK 0x200000u
6241 #define LMEM_PCCLCR_LCIMB_SHIFT 21u
6242 #define LMEM_PCCLCR_LCIMB_WIDTH 1u
6243 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIMB_SHIFT))&LMEM_PCCLCR_LCIMB_MASK)
6244 #define LMEM_PCCLCR_LCWAY_MASK 0x400000u
6245 #define LMEM_PCCLCR_LCWAY_SHIFT 22u
6246 #define LMEM_PCCLCR_LCWAY_WIDTH 1u
6247 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCWAY_SHIFT))&LMEM_PCCLCR_LCWAY_MASK)
6248 #define LMEM_PCCLCR_LCMD_MASK 0x3000000u
6249 #define LMEM_PCCLCR_LCMD_SHIFT 24u
6250 #define LMEM_PCCLCR_LCMD_WIDTH 2u
6251 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
6252 #define LMEM_PCCLCR_LADSEL_MASK 0x4000000u
6253 #define LMEM_PCCLCR_LADSEL_SHIFT 26u
6254 #define LMEM_PCCLCR_LADSEL_WIDTH 1u
6255 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LADSEL_SHIFT))&LMEM_PCCLCR_LADSEL_MASK)
6256 #define LMEM_PCCLCR_LACC_MASK 0x8000000u
6257 #define LMEM_PCCLCR_LACC_SHIFT 27u
6258 #define LMEM_PCCLCR_LACC_WIDTH 1u
6259 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LACC_SHIFT))&LMEM_PCCLCR_LACC_MASK)
6261 #define LMEM_PCCSAR_LGO_MASK 0x1u
6262 #define LMEM_PCCSAR_LGO_SHIFT 0u
6263 #define LMEM_PCCSAR_LGO_WIDTH 1u
6264 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_LGO_SHIFT))&LMEM_PCCSAR_LGO_MASK)
6265 #define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu
6266 #define LMEM_PCCSAR_PHYADDR_SHIFT 2u
6267 #define LMEM_PCCSAR_PHYADDR_WIDTH 30u
6268 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
6270 #define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu
6271 #define LMEM_PCCCVR_DATA_SHIFT 0u
6272 #define LMEM_PCCCVR_DATA_WIDTH 32u
6273 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
6275 #define LMEM_PCCRMR_R15_MASK 0x3u
6276 #define LMEM_PCCRMR_R15_SHIFT 0u
6277 #define LMEM_PCCRMR_R15_WIDTH 2u
6278 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R15_SHIFT))&LMEM_PCCRMR_R15_MASK)
6279 #define LMEM_PCCRMR_R14_MASK 0xCu
6280 #define LMEM_PCCRMR_R14_SHIFT 2u
6281 #define LMEM_PCCRMR_R14_WIDTH 2u
6282 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R14_SHIFT))&LMEM_PCCRMR_R14_MASK)
6283 #define LMEM_PCCRMR_R13_MASK 0x30u
6284 #define LMEM_PCCRMR_R13_SHIFT 4u
6285 #define LMEM_PCCRMR_R13_WIDTH 2u
6286 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R13_SHIFT))&LMEM_PCCRMR_R13_MASK)
6287 #define LMEM_PCCRMR_R12_MASK 0xC0u
6288 #define LMEM_PCCRMR_R12_SHIFT 6u
6289 #define LMEM_PCCRMR_R12_WIDTH 2u
6290 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R12_SHIFT))&LMEM_PCCRMR_R12_MASK)
6291 #define LMEM_PCCRMR_R11_MASK 0x300u
6292 #define LMEM_PCCRMR_R11_SHIFT 8u
6293 #define LMEM_PCCRMR_R11_WIDTH 2u
6294 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R11_SHIFT))&LMEM_PCCRMR_R11_MASK)
6295 #define LMEM_PCCRMR_R10_MASK 0xC00u
6296 #define LMEM_PCCRMR_R10_SHIFT 10u
6297 #define LMEM_PCCRMR_R10_WIDTH 2u
6298 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R10_SHIFT))&LMEM_PCCRMR_R10_MASK)
6299 #define LMEM_PCCRMR_R9_MASK 0x3000u
6300 #define LMEM_PCCRMR_R9_SHIFT 12u
6301 #define LMEM_PCCRMR_R9_WIDTH 2u
6302 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R9_SHIFT))&LMEM_PCCRMR_R9_MASK)
6303 #define LMEM_PCCRMR_R8_MASK 0xC000u
6304 #define LMEM_PCCRMR_R8_SHIFT 14u
6305 #define LMEM_PCCRMR_R8_WIDTH 2u
6306 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R8_SHIFT))&LMEM_PCCRMR_R8_MASK)
6307 #define LMEM_PCCRMR_R7_MASK 0x30000u
6308 #define LMEM_PCCRMR_R7_SHIFT 16u
6309 #define LMEM_PCCRMR_R7_WIDTH 2u
6310 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R7_SHIFT))&LMEM_PCCRMR_R7_MASK)
6311 #define LMEM_PCCRMR_R6_MASK 0xC0000u
6312 #define LMEM_PCCRMR_R6_SHIFT 18u
6313 #define LMEM_PCCRMR_R6_WIDTH 2u
6314 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R6_SHIFT))&LMEM_PCCRMR_R6_MASK)
6315 #define LMEM_PCCRMR_R5_MASK 0x300000u
6316 #define LMEM_PCCRMR_R5_SHIFT 20u
6317 #define LMEM_PCCRMR_R5_WIDTH 2u
6318 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R5_SHIFT))&LMEM_PCCRMR_R5_MASK)
6319 #define LMEM_PCCRMR_R4_MASK 0xC00000u
6320 #define LMEM_PCCRMR_R4_SHIFT 22u
6321 #define LMEM_PCCRMR_R4_WIDTH 2u
6322 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R4_SHIFT))&LMEM_PCCRMR_R4_MASK)
6323 #define LMEM_PCCRMR_R3_MASK 0x3000000u
6324 #define LMEM_PCCRMR_R3_SHIFT 24u
6325 #define LMEM_PCCRMR_R3_WIDTH 2u
6326 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R3_SHIFT))&LMEM_PCCRMR_R3_MASK)
6327 #define LMEM_PCCRMR_R2_MASK 0xC000000u
6328 #define LMEM_PCCRMR_R2_SHIFT 26u
6329 #define LMEM_PCCRMR_R2_WIDTH 2u
6330 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R2_SHIFT))&LMEM_PCCRMR_R2_MASK)
6331 #define LMEM_PCCRMR_R1_MASK 0x30000000u
6332 #define LMEM_PCCRMR_R1_SHIFT 28u
6333 #define LMEM_PCCRMR_R1_WIDTH 2u
6334 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R1_SHIFT))&LMEM_PCCRMR_R1_MASK)
6335 #define LMEM_PCCRMR_R0_MASK 0xC0000000u
6336 #define LMEM_PCCRMR_R0_SHIFT 30u
6337 #define LMEM_PCCRMR_R0_WIDTH 2u
6338 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R0_SHIFT))&LMEM_PCCRMR_R0_MASK)
6366 uint8_t RESERVED_0[8];
6375 uint8_t RESERVED_1[16];
6377 uint8_t RESERVED_2[4];
6379 uint8_t RESERVED_3[4];
6381 uint8_t RESERVED_4[4];
6385 uint8_t RESERVED_5[12];
6387 uint8_t RESERVED_6[156];
6392 uint8_t RESERVED_7[4];
6395 uint8_t RESERVED_8[20];
6397 uint8_t RESERVED_9[12];
6400 uint8_t RESERVED_10[8];
6402 uint8_t RESERVED_11[12];
6407 #define LPI2C_INSTANCE_COUNT (2u)
6412 #define LPI2C0_BASE (0x40066000u)
6414 #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
6416 #define LPI2C1_BASE (0x40067000u)
6418 #define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
6420 #define LPI2C_BASE_ADDRS { LPI2C0_BASE, LPI2C1_BASE }
6422 #define LPI2C_BASE_PTRS { LPI2C0, LPI2C1 }
6424 #define LPI2C_IRQS_ARR_COUNT (2u)
6426 #define LPI2C_MASTER_IRQS_CH_COUNT (1u)
6428 #define LPI2C_SLAVE_IRQS_CH_COUNT (1u)
6430 #define LPI2C_MASTER_IRQS { LPI2C0_Master_IRQn, LPI2C1_Master_IRQn }
6431 #define LPI2C_SLAVE_IRQS { LPI2C0_Slave_IRQn, LPI2C1_Slave_IRQn }
6443 #define LPI2C_VERID_FEATURE_MASK 0xFFFFu
6444 #define LPI2C_VERID_FEATURE_SHIFT 0u
6445 #define LPI2C_VERID_FEATURE_WIDTH 16u
6446 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
6447 #define LPI2C_VERID_MINOR_MASK 0xFF0000u
6448 #define LPI2C_VERID_MINOR_SHIFT 16u
6449 #define LPI2C_VERID_MINOR_WIDTH 8u
6450 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
6451 #define LPI2C_VERID_MAJOR_MASK 0xFF000000u
6452 #define LPI2C_VERID_MAJOR_SHIFT 24u
6453 #define LPI2C_VERID_MAJOR_WIDTH 8u
6454 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
6456 #define LPI2C_PARAM_MTXFIFO_MASK 0xFu
6457 #define LPI2C_PARAM_MTXFIFO_SHIFT 0u
6458 #define LPI2C_PARAM_MTXFIFO_WIDTH 4u
6459 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
6460 #define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
6461 #define LPI2C_PARAM_MRXFIFO_SHIFT 8u
6462 #define LPI2C_PARAM_MRXFIFO_WIDTH 4u
6463 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
6465 #define LPI2C_MCR_MEN_MASK 0x1u
6466 #define LPI2C_MCR_MEN_SHIFT 0u
6467 #define LPI2C_MCR_MEN_WIDTH 1u
6468 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
6469 #define LPI2C_MCR_RST_MASK 0x2u
6470 #define LPI2C_MCR_RST_SHIFT 1u
6471 #define LPI2C_MCR_RST_WIDTH 1u
6472 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
6473 #define LPI2C_MCR_DOZEN_MASK 0x4u
6474 #define LPI2C_MCR_DOZEN_SHIFT 2u
6475 #define LPI2C_MCR_DOZEN_WIDTH 1u
6476 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
6477 #define LPI2C_MCR_DBGEN_MASK 0x8u
6478 #define LPI2C_MCR_DBGEN_SHIFT 3u
6479 #define LPI2C_MCR_DBGEN_WIDTH 1u
6480 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
6481 #define LPI2C_MCR_RTF_MASK 0x100u
6482 #define LPI2C_MCR_RTF_SHIFT 8u
6483 #define LPI2C_MCR_RTF_WIDTH 1u
6484 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
6485 #define LPI2C_MCR_RRF_MASK 0x200u
6486 #define LPI2C_MCR_RRF_SHIFT 9u
6487 #define LPI2C_MCR_RRF_WIDTH 1u
6488 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
6490 #define LPI2C_MSR_TDF_MASK 0x1u
6491 #define LPI2C_MSR_TDF_SHIFT 0u
6492 #define LPI2C_MSR_TDF_WIDTH 1u
6493 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
6494 #define LPI2C_MSR_RDF_MASK 0x2u
6495 #define LPI2C_MSR_RDF_SHIFT 1u
6496 #define LPI2C_MSR_RDF_WIDTH 1u
6497 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
6498 #define LPI2C_MSR_EPF_MASK 0x100u
6499 #define LPI2C_MSR_EPF_SHIFT 8u
6500 #define LPI2C_MSR_EPF_WIDTH 1u
6501 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
6502 #define LPI2C_MSR_SDF_MASK 0x200u
6503 #define LPI2C_MSR_SDF_SHIFT 9u
6504 #define LPI2C_MSR_SDF_WIDTH 1u
6505 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
6506 #define LPI2C_MSR_NDF_MASK 0x400u
6507 #define LPI2C_MSR_NDF_SHIFT 10u
6508 #define LPI2C_MSR_NDF_WIDTH 1u
6509 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
6510 #define LPI2C_MSR_ALF_MASK 0x800u
6511 #define LPI2C_MSR_ALF_SHIFT 11u
6512 #define LPI2C_MSR_ALF_WIDTH 1u
6513 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
6514 #define LPI2C_MSR_FEF_MASK 0x1000u
6515 #define LPI2C_MSR_FEF_SHIFT 12u
6516 #define LPI2C_MSR_FEF_WIDTH 1u
6517 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
6518 #define LPI2C_MSR_PLTF_MASK 0x2000u
6519 #define LPI2C_MSR_PLTF_SHIFT 13u
6520 #define LPI2C_MSR_PLTF_WIDTH 1u
6521 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
6522 #define LPI2C_MSR_DMF_MASK 0x4000u
6523 #define LPI2C_MSR_DMF_SHIFT 14u
6524 #define LPI2C_MSR_DMF_WIDTH 1u
6525 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
6526 #define LPI2C_MSR_MBF_MASK 0x1000000u
6527 #define LPI2C_MSR_MBF_SHIFT 24u
6528 #define LPI2C_MSR_MBF_WIDTH 1u
6529 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
6530 #define LPI2C_MSR_BBF_MASK 0x2000000u
6531 #define LPI2C_MSR_BBF_SHIFT 25u
6532 #define LPI2C_MSR_BBF_WIDTH 1u
6533 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
6535 #define LPI2C_MIER_TDIE_MASK 0x1u
6536 #define LPI2C_MIER_TDIE_SHIFT 0u
6537 #define LPI2C_MIER_TDIE_WIDTH 1u
6538 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
6539 #define LPI2C_MIER_RDIE_MASK 0x2u
6540 #define LPI2C_MIER_RDIE_SHIFT 1u
6541 #define LPI2C_MIER_RDIE_WIDTH 1u
6542 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
6543 #define LPI2C_MIER_EPIE_MASK 0x100u
6544 #define LPI2C_MIER_EPIE_SHIFT 8u
6545 #define LPI2C_MIER_EPIE_WIDTH 1u
6546 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
6547 #define LPI2C_MIER_SDIE_MASK 0x200u
6548 #define LPI2C_MIER_SDIE_SHIFT 9u
6549 #define LPI2C_MIER_SDIE_WIDTH 1u
6550 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
6551 #define LPI2C_MIER_NDIE_MASK 0x400u
6552 #define LPI2C_MIER_NDIE_SHIFT 10u
6553 #define LPI2C_MIER_NDIE_WIDTH 1u
6554 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
6555 #define LPI2C_MIER_ALIE_MASK 0x800u
6556 #define LPI2C_MIER_ALIE_SHIFT 11u
6557 #define LPI2C_MIER_ALIE_WIDTH 1u
6558 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
6559 #define LPI2C_MIER_FEIE_MASK 0x1000u
6560 #define LPI2C_MIER_FEIE_SHIFT 12u
6561 #define LPI2C_MIER_FEIE_WIDTH 1u
6562 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
6563 #define LPI2C_MIER_PLTIE_MASK 0x2000u
6564 #define LPI2C_MIER_PLTIE_SHIFT 13u
6565 #define LPI2C_MIER_PLTIE_WIDTH 1u
6566 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
6567 #define LPI2C_MIER_DMIE_MASK 0x4000u
6568 #define LPI2C_MIER_DMIE_SHIFT 14u
6569 #define LPI2C_MIER_DMIE_WIDTH 1u
6570 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
6572 #define LPI2C_MDER_TDDE_MASK 0x1u
6573 #define LPI2C_MDER_TDDE_SHIFT 0u
6574 #define LPI2C_MDER_TDDE_WIDTH 1u
6575 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
6576 #define LPI2C_MDER_RDDE_MASK 0x2u
6577 #define LPI2C_MDER_RDDE_SHIFT 1u
6578 #define LPI2C_MDER_RDDE_WIDTH 1u
6579 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
6581 #define LPI2C_MCFGR0_HREN_MASK 0x1u
6582 #define LPI2C_MCFGR0_HREN_SHIFT 0u
6583 #define LPI2C_MCFGR0_HREN_WIDTH 1u
6584 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
6585 #define LPI2C_MCFGR0_HRPOL_MASK 0x2u
6586 #define LPI2C_MCFGR0_HRPOL_SHIFT 1u
6587 #define LPI2C_MCFGR0_HRPOL_WIDTH 1u
6588 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
6589 #define LPI2C_MCFGR0_HRSEL_MASK 0x4u
6590 #define LPI2C_MCFGR0_HRSEL_SHIFT 2u
6591 #define LPI2C_MCFGR0_HRSEL_WIDTH 1u
6592 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
6593 #define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
6594 #define LPI2C_MCFGR0_CIRFIFO_SHIFT 8u
6595 #define LPI2C_MCFGR0_CIRFIFO_WIDTH 1u
6596 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
6597 #define LPI2C_MCFGR0_RDMO_MASK 0x200u
6598 #define LPI2C_MCFGR0_RDMO_SHIFT 9u
6599 #define LPI2C_MCFGR0_RDMO_WIDTH 1u
6600 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
6602 #define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
6603 #define LPI2C_MCFGR1_PRESCALE_SHIFT 0u
6604 #define LPI2C_MCFGR1_PRESCALE_WIDTH 3u
6605 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
6606 #define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
6607 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8u
6608 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1u
6609 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
6610 #define LPI2C_MCFGR1_IGNACK_MASK 0x200u
6611 #define LPI2C_MCFGR1_IGNACK_SHIFT 9u
6612 #define LPI2C_MCFGR1_IGNACK_WIDTH 1u
6613 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
6614 #define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
6615 #define LPI2C_MCFGR1_TIMECFG_SHIFT 10u
6616 #define LPI2C_MCFGR1_TIMECFG_WIDTH 1u
6617 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
6618 #define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
6619 #define LPI2C_MCFGR1_MATCFG_SHIFT 16u
6620 #define LPI2C_MCFGR1_MATCFG_WIDTH 3u
6621 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
6622 #define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
6623 #define LPI2C_MCFGR1_PINCFG_SHIFT 24u
6624 #define LPI2C_MCFGR1_PINCFG_WIDTH 3u
6625 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
6627 #define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
6628 #define LPI2C_MCFGR2_BUSIDLE_SHIFT 0u
6629 #define LPI2C_MCFGR2_BUSIDLE_WIDTH 12u
6630 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
6631 #define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
6632 #define LPI2C_MCFGR2_FILTSCL_SHIFT 16u
6633 #define LPI2C_MCFGR2_FILTSCL_WIDTH 4u
6634 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
6635 #define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
6636 #define LPI2C_MCFGR2_FILTSDA_SHIFT 24u
6637 #define LPI2C_MCFGR2_FILTSDA_WIDTH 4u
6638 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
6640 #define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
6641 #define LPI2C_MCFGR3_PINLOW_SHIFT 8u
6642 #define LPI2C_MCFGR3_PINLOW_WIDTH 12u
6643 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
6645 #define LPI2C_MDMR_MATCH0_MASK 0xFFu
6646 #define LPI2C_MDMR_MATCH0_SHIFT 0u
6647 #define LPI2C_MDMR_MATCH0_WIDTH 8u
6648 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
6649 #define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
6650 #define LPI2C_MDMR_MATCH1_SHIFT 16u
6651 #define LPI2C_MDMR_MATCH1_WIDTH 8u
6652 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
6654 #define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
6655 #define LPI2C_MCCR0_CLKLO_SHIFT 0u
6656 #define LPI2C_MCCR0_CLKLO_WIDTH 6u
6657 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
6658 #define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
6659 #define LPI2C_MCCR0_CLKHI_SHIFT 8u
6660 #define LPI2C_MCCR0_CLKHI_WIDTH 6u
6661 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
6662 #define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
6663 #define LPI2C_MCCR0_SETHOLD_SHIFT 16u
6664 #define LPI2C_MCCR0_SETHOLD_WIDTH 6u
6665 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
6666 #define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
6667 #define LPI2C_MCCR0_DATAVD_SHIFT 24u
6668 #define LPI2C_MCCR0_DATAVD_WIDTH 6u
6669 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
6671 #define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
6672 #define LPI2C_MCCR1_CLKLO_SHIFT 0u
6673 #define LPI2C_MCCR1_CLKLO_WIDTH 6u
6674 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
6675 #define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
6676 #define LPI2C_MCCR1_CLKHI_SHIFT 8u
6677 #define LPI2C_MCCR1_CLKHI_WIDTH 6u
6678 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
6679 #define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
6680 #define LPI2C_MCCR1_SETHOLD_SHIFT 16u
6681 #define LPI2C_MCCR1_SETHOLD_WIDTH 6u
6682 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
6683 #define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
6684 #define LPI2C_MCCR1_DATAVD_SHIFT 24u
6685 #define LPI2C_MCCR1_DATAVD_WIDTH 6u
6686 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
6688 #define LPI2C_MFCR_TXWATER_MASK 0x3u
6689 #define LPI2C_MFCR_TXWATER_SHIFT 0u
6690 #define LPI2C_MFCR_TXWATER_WIDTH 2u
6691 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
6692 #define LPI2C_MFCR_RXWATER_MASK 0x30000u
6693 #define LPI2C_MFCR_RXWATER_SHIFT 16u
6694 #define LPI2C_MFCR_RXWATER_WIDTH 2u
6695 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
6697 #define LPI2C_MFSR_TXCOUNT_MASK 0x7u
6698 #define LPI2C_MFSR_TXCOUNT_SHIFT 0u
6699 #define LPI2C_MFSR_TXCOUNT_WIDTH 3u
6700 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
6701 #define LPI2C_MFSR_RXCOUNT_MASK 0x70000u
6702 #define LPI2C_MFSR_RXCOUNT_SHIFT 16u
6703 #define LPI2C_MFSR_RXCOUNT_WIDTH 3u
6704 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
6706 #define LPI2C_MTDR_DATA_MASK 0xFFu
6707 #define LPI2C_MTDR_DATA_SHIFT 0u
6708 #define LPI2C_MTDR_DATA_WIDTH 8u
6709 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
6710 #define LPI2C_MTDR_CMD_MASK 0x700u
6711 #define LPI2C_MTDR_CMD_SHIFT 8u
6712 #define LPI2C_MTDR_CMD_WIDTH 3u
6713 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
6715 #define LPI2C_MRDR_DATA_MASK 0xFFu
6716 #define LPI2C_MRDR_DATA_SHIFT 0u
6717 #define LPI2C_MRDR_DATA_WIDTH 8u
6718 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
6719 #define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
6720 #define LPI2C_MRDR_RXEMPTY_SHIFT 14u
6721 #define LPI2C_MRDR_RXEMPTY_WIDTH 1u
6722 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
6724 #define LPI2C_SCR_SEN_MASK 0x1u
6725 #define LPI2C_SCR_SEN_SHIFT 0u
6726 #define LPI2C_SCR_SEN_WIDTH 1u
6727 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
6728 #define LPI2C_SCR_RST_MASK 0x2u
6729 #define LPI2C_SCR_RST_SHIFT 1u
6730 #define LPI2C_SCR_RST_WIDTH 1u
6731 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
6732 #define LPI2C_SCR_FILTEN_MASK 0x10u
6733 #define LPI2C_SCR_FILTEN_SHIFT 4u
6734 #define LPI2C_SCR_FILTEN_WIDTH 1u
6735 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
6736 #define LPI2C_SCR_FILTDZ_MASK 0x20u
6737 #define LPI2C_SCR_FILTDZ_SHIFT 5u
6738 #define LPI2C_SCR_FILTDZ_WIDTH 1u
6739 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
6741 #define LPI2C_SSR_TDF_MASK 0x1u
6742 #define LPI2C_SSR_TDF_SHIFT 0u
6743 #define LPI2C_SSR_TDF_WIDTH 1u
6744 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
6745 #define LPI2C_SSR_RDF_MASK 0x2u
6746 #define LPI2C_SSR_RDF_SHIFT 1u
6747 #define LPI2C_SSR_RDF_WIDTH 1u
6748 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
6749 #define LPI2C_SSR_AVF_MASK 0x4u
6750 #define LPI2C_SSR_AVF_SHIFT 2u
6751 #define LPI2C_SSR_AVF_WIDTH 1u
6752 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
6753 #define LPI2C_SSR_TAF_MASK 0x8u
6754 #define LPI2C_SSR_TAF_SHIFT 3u
6755 #define LPI2C_SSR_TAF_WIDTH 1u
6756 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
6757 #define LPI2C_SSR_RSF_MASK 0x100u
6758 #define LPI2C_SSR_RSF_SHIFT 8u
6759 #define LPI2C_SSR_RSF_WIDTH 1u
6760 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
6761 #define LPI2C_SSR_SDF_MASK 0x200u
6762 #define LPI2C_SSR_SDF_SHIFT 9u
6763 #define LPI2C_SSR_SDF_WIDTH 1u
6764 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
6765 #define LPI2C_SSR_BEF_MASK 0x400u
6766 #define LPI2C_SSR_BEF_SHIFT 10u
6767 #define LPI2C_SSR_BEF_WIDTH 1u
6768 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
6769 #define LPI2C_SSR_FEF_MASK 0x800u
6770 #define LPI2C_SSR_FEF_SHIFT 11u
6771 #define LPI2C_SSR_FEF_WIDTH 1u
6772 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
6773 #define LPI2C_SSR_AM0F_MASK 0x1000u
6774 #define LPI2C_SSR_AM0F_SHIFT 12u
6775 #define LPI2C_SSR_AM0F_WIDTH 1u
6776 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
6777 #define LPI2C_SSR_AM1F_MASK 0x2000u
6778 #define LPI2C_SSR_AM1F_SHIFT 13u
6779 #define LPI2C_SSR_AM1F_WIDTH 1u
6780 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
6781 #define LPI2C_SSR_GCF_MASK 0x4000u
6782 #define LPI2C_SSR_GCF_SHIFT 14u
6783 #define LPI2C_SSR_GCF_WIDTH 1u
6784 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
6785 #define LPI2C_SSR_SARF_MASK 0x8000u
6786 #define LPI2C_SSR_SARF_SHIFT 15u
6787 #define LPI2C_SSR_SARF_WIDTH 1u
6788 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
6789 #define LPI2C_SSR_SBF_MASK 0x1000000u
6790 #define LPI2C_SSR_SBF_SHIFT 24u
6791 #define LPI2C_SSR_SBF_WIDTH 1u
6792 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
6793 #define LPI2C_SSR_BBF_MASK 0x2000000u
6794 #define LPI2C_SSR_BBF_SHIFT 25u
6795 #define LPI2C_SSR_BBF_WIDTH 1u
6796 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
6798 #define LPI2C_SIER_TDIE_MASK 0x1u
6799 #define LPI2C_SIER_TDIE_SHIFT 0u
6800 #define LPI2C_SIER_TDIE_WIDTH 1u
6801 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
6802 #define LPI2C_SIER_RDIE_MASK 0x2u
6803 #define LPI2C_SIER_RDIE_SHIFT 1u
6804 #define LPI2C_SIER_RDIE_WIDTH 1u
6805 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
6806 #define LPI2C_SIER_AVIE_MASK 0x4u
6807 #define LPI2C_SIER_AVIE_SHIFT 2u
6808 #define LPI2C_SIER_AVIE_WIDTH 1u
6809 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
6810 #define LPI2C_SIER_TAIE_MASK 0x8u
6811 #define LPI2C_SIER_TAIE_SHIFT 3u
6812 #define LPI2C_SIER_TAIE_WIDTH 1u
6813 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
6814 #define LPI2C_SIER_RSIE_MASK 0x100u
6815 #define LPI2C_SIER_RSIE_SHIFT 8u
6816 #define LPI2C_SIER_RSIE_WIDTH 1u
6817 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
6818 #define LPI2C_SIER_SDIE_MASK 0x200u
6819 #define LPI2C_SIER_SDIE_SHIFT 9u
6820 #define LPI2C_SIER_SDIE_WIDTH 1u
6821 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
6822 #define LPI2C_SIER_BEIE_MASK 0x400u
6823 #define LPI2C_SIER_BEIE_SHIFT 10u
6824 #define LPI2C_SIER_BEIE_WIDTH 1u
6825 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
6826 #define LPI2C_SIER_FEIE_MASK 0x800u
6827 #define LPI2C_SIER_FEIE_SHIFT 11u
6828 #define LPI2C_SIER_FEIE_WIDTH 1u
6829 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
6830 #define LPI2C_SIER_AM0IE_MASK 0x1000u
6831 #define LPI2C_SIER_AM0IE_SHIFT 12u
6832 #define LPI2C_SIER_AM0IE_WIDTH 1u
6833 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
6834 #define LPI2C_SIER_AM1F_MASK 0x2000u
6835 #define LPI2C_SIER_AM1F_SHIFT 13u
6836 #define LPI2C_SIER_AM1F_WIDTH 1u
6837 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
6838 #define LPI2C_SIER_GCIE_MASK 0x4000u
6839 #define LPI2C_SIER_GCIE_SHIFT 14u
6840 #define LPI2C_SIER_GCIE_WIDTH 1u
6841 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
6842 #define LPI2C_SIER_SARIE_MASK 0x8000u
6843 #define LPI2C_SIER_SARIE_SHIFT 15u
6844 #define LPI2C_SIER_SARIE_WIDTH 1u
6845 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
6847 #define LPI2C_SDER_TDDE_MASK 0x1u
6848 #define LPI2C_SDER_TDDE_SHIFT 0u
6849 #define LPI2C_SDER_TDDE_WIDTH 1u
6850 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
6851 #define LPI2C_SDER_RDDE_MASK 0x2u
6852 #define LPI2C_SDER_RDDE_SHIFT 1u
6853 #define LPI2C_SDER_RDDE_WIDTH 1u
6854 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
6855 #define LPI2C_SDER_AVDE_MASK 0x4u
6856 #define LPI2C_SDER_AVDE_SHIFT 2u
6857 #define LPI2C_SDER_AVDE_WIDTH 1u
6858 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
6860 #define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
6861 #define LPI2C_SCFGR1_ADRSTALL_SHIFT 0u
6862 #define LPI2C_SCFGR1_ADRSTALL_WIDTH 1u
6863 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
6864 #define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
6865 #define LPI2C_SCFGR1_RXSTALL_SHIFT 1u
6866 #define LPI2C_SCFGR1_RXSTALL_WIDTH 1u
6867 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
6868 #define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
6869 #define LPI2C_SCFGR1_TXDSTALL_SHIFT 2u
6870 #define LPI2C_SCFGR1_TXDSTALL_WIDTH 1u
6871 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
6872 #define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
6873 #define LPI2C_SCFGR1_ACKSTALL_SHIFT 3u
6874 #define LPI2C_SCFGR1_ACKSTALL_WIDTH 1u
6875 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
6876 #define LPI2C_SCFGR1_GCEN_MASK 0x100u
6877 #define LPI2C_SCFGR1_GCEN_SHIFT 8u
6878 #define LPI2C_SCFGR1_GCEN_WIDTH 1u
6879 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
6880 #define LPI2C_SCFGR1_SAEN_MASK 0x200u
6881 #define LPI2C_SCFGR1_SAEN_SHIFT 9u
6882 #define LPI2C_SCFGR1_SAEN_WIDTH 1u
6883 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
6884 #define LPI2C_SCFGR1_TXCFG_MASK 0x400u
6885 #define LPI2C_SCFGR1_TXCFG_SHIFT 10u
6886 #define LPI2C_SCFGR1_TXCFG_WIDTH 1u
6887 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
6888 #define LPI2C_SCFGR1_RXCFG_MASK 0x800u
6889 #define LPI2C_SCFGR1_RXCFG_SHIFT 11u
6890 #define LPI2C_SCFGR1_RXCFG_WIDTH 1u
6891 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
6892 #define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
6893 #define LPI2C_SCFGR1_IGNACK_SHIFT 12u
6894 #define LPI2C_SCFGR1_IGNACK_WIDTH 1u
6895 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
6896 #define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
6897 #define LPI2C_SCFGR1_HSMEN_SHIFT 13u
6898 #define LPI2C_SCFGR1_HSMEN_WIDTH 1u
6899 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
6900 #define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
6901 #define LPI2C_SCFGR1_ADDRCFG_SHIFT 16u
6902 #define LPI2C_SCFGR1_ADDRCFG_WIDTH 3u
6903 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
6905 #define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
6906 #define LPI2C_SCFGR2_CLKHOLD_SHIFT 0u
6907 #define LPI2C_SCFGR2_CLKHOLD_WIDTH 4u
6908 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
6909 #define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
6910 #define LPI2C_SCFGR2_DATAVD_SHIFT 8u
6911 #define LPI2C_SCFGR2_DATAVD_WIDTH 6u
6912 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
6913 #define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
6914 #define LPI2C_SCFGR2_FILTSCL_SHIFT 16u
6915 #define LPI2C_SCFGR2_FILTSCL_WIDTH 4u
6916 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
6917 #define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
6918 #define LPI2C_SCFGR2_FILTSDA_SHIFT 24u
6919 #define LPI2C_SCFGR2_FILTSDA_WIDTH 4u
6920 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
6922 #define LPI2C_SAMR_ADDR0_MASK 0x7FEu
6923 #define LPI2C_SAMR_ADDR0_SHIFT 1u
6924 #define LPI2C_SAMR_ADDR0_WIDTH 10u
6925 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
6926 #define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
6927 #define LPI2C_SAMR_ADDR1_SHIFT 17u
6928 #define LPI2C_SAMR_ADDR1_WIDTH 10u
6929 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
6931 #define LPI2C_SASR_RADDR_MASK 0x7FFu
6932 #define LPI2C_SASR_RADDR_SHIFT 0u
6933 #define LPI2C_SASR_RADDR_WIDTH 11u
6934 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
6935 #define LPI2C_SASR_ANV_MASK 0x4000u
6936 #define LPI2C_SASR_ANV_SHIFT 14u
6937 #define LPI2C_SASR_ANV_WIDTH 1u
6938 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
6940 #define LPI2C_STAR_TXNACK_MASK 0x1u
6941 #define LPI2C_STAR_TXNACK_SHIFT 0u
6942 #define LPI2C_STAR_TXNACK_WIDTH 1u
6943 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
6945 #define LPI2C_STDR_DATA_MASK 0xFFu
6946 #define LPI2C_STDR_DATA_SHIFT 0u
6947 #define LPI2C_STDR_DATA_WIDTH 8u
6948 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
6950 #define LPI2C_SRDR_DATA_MASK 0xFFu
6951 #define LPI2C_SRDR_DATA_SHIFT 0u
6952 #define LPI2C_SRDR_DATA_WIDTH 8u
6953 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
6954 #define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
6955 #define LPI2C_SRDR_RXEMPTY_SHIFT 14u
6956 #define LPI2C_SRDR_RXEMPTY_WIDTH 1u
6957 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
6958 #define LPI2C_SRDR_SOF_MASK 0x8000u
6959 #define LPI2C_SRDR_SOF_SHIFT 15u
6960 #define LPI2C_SRDR_SOF_WIDTH 1u
6961 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
6984 #define LPIT_TMR_COUNT 4u
6995 uint8_t RESERVED_0[4];
7000 uint8_t RESERVED_0[4];
7005 #define LPIT_INSTANCE_COUNT (1u)
7010 #define LPIT0_BASE (0x40037000u)
7012 #define LPIT0 ((LPIT_Type *)LPIT0_BASE)
7014 #define LPIT_BASE_ADDRS { LPIT0_BASE }
7016 #define LPIT_BASE_PTRS { LPIT0 }
7018 #define LPIT_IRQS_ARR_COUNT (1u)
7020 #define LPIT_IRQS_CH_COUNT (4u)
7022 #define LPIT_IRQS { LPIT0_Ch0_IRQn, LPIT0_Ch1_IRQn, LPIT0_Ch2_IRQn, LPIT0_Ch3_IRQn }
7034 #define LPIT_VERID_FEATURE_MASK 0xFFFFu
7035 #define LPIT_VERID_FEATURE_SHIFT 0u
7036 #define LPIT_VERID_FEATURE_WIDTH 16u
7037 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_FEATURE_SHIFT))&LPIT_VERID_FEATURE_MASK)
7038 #define LPIT_VERID_MINOR_MASK 0xFF0000u
7039 #define LPIT_VERID_MINOR_SHIFT 16u
7040 #define LPIT_VERID_MINOR_WIDTH 8u
7041 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MINOR_SHIFT))&LPIT_VERID_MINOR_MASK)
7042 #define LPIT_VERID_MAJOR_MASK 0xFF000000u
7043 #define LPIT_VERID_MAJOR_SHIFT 24u
7044 #define LPIT_VERID_MAJOR_WIDTH 8u
7045 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MAJOR_SHIFT))&LPIT_VERID_MAJOR_MASK)
7047 #define LPIT_PARAM_CHANNEL_MASK 0xFFu
7048 #define LPIT_PARAM_CHANNEL_SHIFT 0u
7049 #define LPIT_PARAM_CHANNEL_WIDTH 8u
7050 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_CHANNEL_SHIFT))&LPIT_PARAM_CHANNEL_MASK)
7051 #define LPIT_PARAM_EXT_TRIG_MASK 0xFF00u
7052 #define LPIT_PARAM_EXT_TRIG_SHIFT 8u
7053 #define LPIT_PARAM_EXT_TRIG_WIDTH 8u
7054 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_EXT_TRIG_SHIFT))&LPIT_PARAM_EXT_TRIG_MASK)
7056 #define LPIT_MCR_M_CEN_MASK 0x1u
7057 #define LPIT_MCR_M_CEN_SHIFT 0u
7058 #define LPIT_MCR_M_CEN_WIDTH 1u
7059 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_M_CEN_SHIFT))&LPIT_MCR_M_CEN_MASK)
7060 #define LPIT_MCR_SW_RST_MASK 0x2u
7061 #define LPIT_MCR_SW_RST_SHIFT 1u
7062 #define LPIT_MCR_SW_RST_WIDTH 1u
7063 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_SW_RST_SHIFT))&LPIT_MCR_SW_RST_MASK)
7064 #define LPIT_MCR_DOZE_EN_MASK 0x4u
7065 #define LPIT_MCR_DOZE_EN_SHIFT 2u
7066 #define LPIT_MCR_DOZE_EN_WIDTH 1u
7067 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DOZE_EN_SHIFT))&LPIT_MCR_DOZE_EN_MASK)
7068 #define LPIT_MCR_DBG_EN_MASK 0x8u
7069 #define LPIT_MCR_DBG_EN_SHIFT 3u
7070 #define LPIT_MCR_DBG_EN_WIDTH 1u
7071 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DBG_EN_SHIFT))&LPIT_MCR_DBG_EN_MASK)
7073 #define LPIT_MSR_TIF0_MASK 0x1u
7074 #define LPIT_MSR_TIF0_SHIFT 0u
7075 #define LPIT_MSR_TIF0_WIDTH 1u
7076 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF0_SHIFT))&LPIT_MSR_TIF0_MASK)
7077 #define LPIT_MSR_TIF1_MASK 0x2u
7078 #define LPIT_MSR_TIF1_SHIFT 1u
7079 #define LPIT_MSR_TIF1_WIDTH 1u
7080 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF1_SHIFT))&LPIT_MSR_TIF1_MASK)
7081 #define LPIT_MSR_TIF2_MASK 0x4u
7082 #define LPIT_MSR_TIF2_SHIFT 2u
7083 #define LPIT_MSR_TIF2_WIDTH 1u
7084 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF2_SHIFT))&LPIT_MSR_TIF2_MASK)
7085 #define LPIT_MSR_TIF3_MASK 0x8u
7086 #define LPIT_MSR_TIF3_SHIFT 3u
7087 #define LPIT_MSR_TIF3_WIDTH 1u
7088 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF3_SHIFT))&LPIT_MSR_TIF3_MASK)
7090 #define LPIT_MIER_TIE0_MASK 0x1u
7091 #define LPIT_MIER_TIE0_SHIFT 0u
7092 #define LPIT_MIER_TIE0_WIDTH 1u
7093 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE0_SHIFT))&LPIT_MIER_TIE0_MASK)
7094 #define LPIT_MIER_TIE1_MASK 0x2u
7095 #define LPIT_MIER_TIE1_SHIFT 1u
7096 #define LPIT_MIER_TIE1_WIDTH 1u
7097 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE1_SHIFT))&LPIT_MIER_TIE1_MASK)
7098 #define LPIT_MIER_TIE2_MASK 0x4u
7099 #define LPIT_MIER_TIE2_SHIFT 2u
7100 #define LPIT_MIER_TIE2_WIDTH 1u
7101 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE2_SHIFT))&LPIT_MIER_TIE2_MASK)
7102 #define LPIT_MIER_TIE3_MASK 0x8u
7103 #define LPIT_MIER_TIE3_SHIFT 3u
7104 #define LPIT_MIER_TIE3_WIDTH 1u
7105 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE3_SHIFT))&LPIT_MIER_TIE3_MASK)
7107 #define LPIT_SETTEN_SET_T_EN_0_MASK 0x1u
7108 #define LPIT_SETTEN_SET_T_EN_0_SHIFT 0u
7109 #define LPIT_SETTEN_SET_T_EN_0_WIDTH 1u
7110 #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_0_SHIFT))&LPIT_SETTEN_SET_T_EN_0_MASK)
7111 #define LPIT_SETTEN_SET_T_EN_1_MASK 0x2u
7112 #define LPIT_SETTEN_SET_T_EN_1_SHIFT 1u
7113 #define LPIT_SETTEN_SET_T_EN_1_WIDTH 1u
7114 #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_1_SHIFT))&LPIT_SETTEN_SET_T_EN_1_MASK)
7115 #define LPIT_SETTEN_SET_T_EN_2_MASK 0x4u
7116 #define LPIT_SETTEN_SET_T_EN_2_SHIFT 2u
7117 #define LPIT_SETTEN_SET_T_EN_2_WIDTH 1u
7118 #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_2_SHIFT))&LPIT_SETTEN_SET_T_EN_2_MASK)
7119 #define LPIT_SETTEN_SET_T_EN_3_MASK 0x8u
7120 #define LPIT_SETTEN_SET_T_EN_3_SHIFT 3u
7121 #define LPIT_SETTEN_SET_T_EN_3_WIDTH 1u
7122 #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_3_SHIFT))&LPIT_SETTEN_SET_T_EN_3_MASK)
7124 #define LPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
7125 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
7126 #define LPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
7127 #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_0_SHIFT))&LPIT_CLRTEN_CLR_T_EN_0_MASK)
7128 #define LPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
7129 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
7130 #define LPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
7131 #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_1_SHIFT))&LPIT_CLRTEN_CLR_T_EN_1_MASK)
7132 #define LPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
7133 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
7134 #define LPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
7135 #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_2_SHIFT))&LPIT_CLRTEN_CLR_T_EN_2_MASK)
7136 #define LPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
7137 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
7138 #define LPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
7139 #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_3_SHIFT))&LPIT_CLRTEN_CLR_T_EN_3_MASK)
7141 #define LPIT_TMR_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
7142 #define LPIT_TMR_TVAL_TMR_VAL_SHIFT 0u
7143 #define LPIT_TMR_TVAL_TMR_VAL_WIDTH 32u
7144 #define LPIT_TMR_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TVAL_TMR_VAL_SHIFT))&LPIT_TMR_TVAL_TMR_VAL_MASK)
7146 #define LPIT_TMR_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
7147 #define LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT 0u
7148 #define LPIT_TMR_CVAL_TMR_CUR_VAL_WIDTH 32u
7149 #define LPIT_TMR_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT))&LPIT_TMR_CVAL_TMR_CUR_VAL_MASK)
7151 #define LPIT_TMR_TCTRL_T_EN_MASK 0x1u
7152 #define LPIT_TMR_TCTRL_T_EN_SHIFT 0u
7153 #define LPIT_TMR_TCTRL_T_EN_WIDTH 1u
7154 #define LPIT_TMR_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_T_EN_SHIFT))&LPIT_TMR_TCTRL_T_EN_MASK)
7155 #define LPIT_TMR_TCTRL_CHAIN_MASK 0x2u
7156 #define LPIT_TMR_TCTRL_CHAIN_SHIFT 1u
7157 #define LPIT_TMR_TCTRL_CHAIN_WIDTH 1u
7158 #define LPIT_TMR_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_CHAIN_SHIFT))&LPIT_TMR_TCTRL_CHAIN_MASK)
7159 #define LPIT_TMR_TCTRL_MODE_MASK 0xCu
7160 #define LPIT_TMR_TCTRL_MODE_SHIFT 2u
7161 #define LPIT_TMR_TCTRL_MODE_WIDTH 2u
7162 #define LPIT_TMR_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_MODE_SHIFT))&LPIT_TMR_TCTRL_MODE_MASK)
7163 #define LPIT_TMR_TCTRL_TSOT_MASK 0x10000u
7164 #define LPIT_TMR_TCTRL_TSOT_SHIFT 16u
7165 #define LPIT_TMR_TCTRL_TSOT_WIDTH 1u
7166 #define LPIT_TMR_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOT_SHIFT))&LPIT_TMR_TCTRL_TSOT_MASK)
7167 #define LPIT_TMR_TCTRL_TSOI_MASK 0x20000u
7168 #define LPIT_TMR_TCTRL_TSOI_SHIFT 17u
7169 #define LPIT_TMR_TCTRL_TSOI_WIDTH 1u
7170 #define LPIT_TMR_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOI_SHIFT))&LPIT_TMR_TCTRL_TSOI_MASK)
7171 #define LPIT_TMR_TCTRL_TROT_MASK 0x40000u
7172 #define LPIT_TMR_TCTRL_TROT_SHIFT 18u
7173 #define LPIT_TMR_TCTRL_TROT_WIDTH 1u
7174 #define LPIT_TMR_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TROT_SHIFT))&LPIT_TMR_TCTRL_TROT_MASK)
7175 #define LPIT_TMR_TCTRL_TRG_SRC_MASK 0x800000u
7176 #define LPIT_TMR_TCTRL_TRG_SRC_SHIFT 23u
7177 #define LPIT_TMR_TCTRL_TRG_SRC_WIDTH 1u
7178 #define LPIT_TMR_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SRC_SHIFT))&LPIT_TMR_TCTRL_TRG_SRC_MASK)
7179 #define LPIT_TMR_TCTRL_TRG_SEL_MASK 0xF000000u
7180 #define LPIT_TMR_TCTRL_TRG_SEL_SHIFT 24u
7181 #define LPIT_TMR_TCTRL_TRG_SEL_WIDTH 4u
7182 #define LPIT_TMR_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SEL_SHIFT))&LPIT_TMR_TCTRL_TRG_SEL_MASK)
7210 uint8_t RESERVED_0[8];
7217 uint8_t RESERVED_1[8];
7220 uint8_t RESERVED_2[8];
7222 uint8_t RESERVED_3[20];
7227 uint8_t RESERVED_4[8];
7233 #define LPSPI_INSTANCE_COUNT (3u)
7238 #define LPSPI0_BASE (0x4002C000u)
7240 #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
7242 #define LPSPI1_BASE (0x4002D000u)
7244 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
7246 #define LPSPI2_BASE (0x4002E000u)
7248 #define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
7250 #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE, LPSPI2_BASE }
7252 #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1, LPSPI2 }
7254 #define LPSPI_IRQS_ARR_COUNT (1u)
7256 #define LPSPI_IRQS_CH_COUNT (1u)
7258 #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn, LPSPI2_IRQn }
7270 #define LPSPI_VERID_FEATURE_MASK 0xFFFFu
7271 #define LPSPI_VERID_FEATURE_SHIFT 0u
7272 #define LPSPI_VERID_FEATURE_WIDTH 16u
7273 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_FEATURE_SHIFT))&LPSPI_VERID_FEATURE_MASK)
7274 #define LPSPI_VERID_MINOR_MASK 0xFF0000u
7275 #define LPSPI_VERID_MINOR_SHIFT 16u
7276 #define LPSPI_VERID_MINOR_WIDTH 8u
7277 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MINOR_SHIFT))&LPSPI_VERID_MINOR_MASK)
7278 #define LPSPI_VERID_MAJOR_MASK 0xFF000000u
7279 #define LPSPI_VERID_MAJOR_SHIFT 24u
7280 #define LPSPI_VERID_MAJOR_WIDTH 8u
7281 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MAJOR_SHIFT))&LPSPI_VERID_MAJOR_MASK)
7283 #define LPSPI_PARAM_TXFIFO_MASK 0xFFu
7284 #define LPSPI_PARAM_TXFIFO_SHIFT 0u
7285 #define LPSPI_PARAM_TXFIFO_WIDTH 8u
7286 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_TXFIFO_SHIFT))&LPSPI_PARAM_TXFIFO_MASK)
7287 #define LPSPI_PARAM_RXFIFO_MASK 0xFF00u
7288 #define LPSPI_PARAM_RXFIFO_SHIFT 8u
7289 #define LPSPI_PARAM_RXFIFO_WIDTH 8u
7290 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_RXFIFO_SHIFT))&LPSPI_PARAM_RXFIFO_MASK)
7292 #define LPSPI_CR_MEN_MASK 0x1u
7293 #define LPSPI_CR_MEN_SHIFT 0u
7294 #define LPSPI_CR_MEN_WIDTH 1u
7295 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_MEN_SHIFT))&LPSPI_CR_MEN_MASK)
7296 #define LPSPI_CR_RST_MASK 0x2u
7297 #define LPSPI_CR_RST_SHIFT 1u
7298 #define LPSPI_CR_RST_WIDTH 1u
7299 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RST_SHIFT))&LPSPI_CR_RST_MASK)
7300 #define LPSPI_CR_DOZEN_MASK 0x4u
7301 #define LPSPI_CR_DOZEN_SHIFT 2u
7302 #define LPSPI_CR_DOZEN_WIDTH 1u
7303 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DOZEN_SHIFT))&LPSPI_CR_DOZEN_MASK)
7304 #define LPSPI_CR_DBGEN_MASK 0x8u
7305 #define LPSPI_CR_DBGEN_SHIFT 3u
7306 #define LPSPI_CR_DBGEN_WIDTH 1u
7307 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DBGEN_SHIFT))&LPSPI_CR_DBGEN_MASK)
7308 #define LPSPI_CR_RTF_MASK 0x100u
7309 #define LPSPI_CR_RTF_SHIFT 8u
7310 #define LPSPI_CR_RTF_WIDTH 1u
7311 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RTF_SHIFT))&LPSPI_CR_RTF_MASK)
7312 #define LPSPI_CR_RRF_MASK 0x200u
7313 #define LPSPI_CR_RRF_SHIFT 9u
7314 #define LPSPI_CR_RRF_WIDTH 1u
7315 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RRF_SHIFT))&LPSPI_CR_RRF_MASK)
7317 #define LPSPI_SR_TDF_MASK 0x1u
7318 #define LPSPI_SR_TDF_SHIFT 0u
7319 #define LPSPI_SR_TDF_WIDTH 1u
7320 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TDF_SHIFT))&LPSPI_SR_TDF_MASK)
7321 #define LPSPI_SR_RDF_MASK 0x2u
7322 #define LPSPI_SR_RDF_SHIFT 1u
7323 #define LPSPI_SR_RDF_WIDTH 1u
7324 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_RDF_SHIFT))&LPSPI_SR_RDF_MASK)
7325 #define LPSPI_SR_WCF_MASK 0x100u
7326 #define LPSPI_SR_WCF_SHIFT 8u
7327 #define LPSPI_SR_WCF_WIDTH 1u
7328 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_WCF_SHIFT))&LPSPI_SR_WCF_MASK)
7329 #define LPSPI_SR_FCF_MASK 0x200u
7330 #define LPSPI_SR_FCF_SHIFT 9u
7331 #define LPSPI_SR_FCF_WIDTH 1u
7332 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_FCF_SHIFT))&LPSPI_SR_FCF_MASK)
7333 #define LPSPI_SR_TCF_MASK 0x400u
7334 #define LPSPI_SR_TCF_SHIFT 10u
7335 #define LPSPI_SR_TCF_WIDTH 1u
7336 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TCF_SHIFT))&LPSPI_SR_TCF_MASK)
7337 #define LPSPI_SR_TEF_MASK 0x800u
7338 #define LPSPI_SR_TEF_SHIFT 11u
7339 #define LPSPI_SR_TEF_WIDTH 1u
7340 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TEF_SHIFT))&LPSPI_SR_TEF_MASK)
7341 #define LPSPI_SR_REF_MASK 0x1000u
7342 #define LPSPI_SR_REF_SHIFT 12u
7343 #define LPSPI_SR_REF_WIDTH 1u
7344 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_REF_SHIFT))&LPSPI_SR_REF_MASK)
7345 #define LPSPI_SR_DMF_MASK 0x2000u
7346 #define LPSPI_SR_DMF_SHIFT 13u
7347 #define LPSPI_SR_DMF_WIDTH 1u
7348 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_DMF_SHIFT))&LPSPI_SR_DMF_MASK)
7349 #define LPSPI_SR_MBF_MASK 0x1000000u
7350 #define LPSPI_SR_MBF_SHIFT 24u
7351 #define LPSPI_SR_MBF_WIDTH 1u
7352 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_MBF_SHIFT))&LPSPI_SR_MBF_MASK)
7354 #define LPSPI_IER_TDIE_MASK 0x1u
7355 #define LPSPI_IER_TDIE_SHIFT 0u
7356 #define LPSPI_IER_TDIE_WIDTH 1u
7357 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TDIE_SHIFT))&LPSPI_IER_TDIE_MASK)
7358 #define LPSPI_IER_RDIE_MASK 0x2u
7359 #define LPSPI_IER_RDIE_SHIFT 1u
7360 #define LPSPI_IER_RDIE_WIDTH 1u
7361 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_RDIE_SHIFT))&LPSPI_IER_RDIE_MASK)
7362 #define LPSPI_IER_WCIE_MASK 0x100u
7363 #define LPSPI_IER_WCIE_SHIFT 8u
7364 #define LPSPI_IER_WCIE_WIDTH 1u
7365 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_WCIE_SHIFT))&LPSPI_IER_WCIE_MASK)
7366 #define LPSPI_IER_FCIE_MASK 0x200u
7367 #define LPSPI_IER_FCIE_SHIFT 9u
7368 #define LPSPI_IER_FCIE_WIDTH 1u
7369 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_FCIE_SHIFT))&LPSPI_IER_FCIE_MASK)
7370 #define LPSPI_IER_TCIE_MASK 0x400u
7371 #define LPSPI_IER_TCIE_SHIFT 10u
7372 #define LPSPI_IER_TCIE_WIDTH 1u
7373 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TCIE_SHIFT))&LPSPI_IER_TCIE_MASK)
7374 #define LPSPI_IER_TEIE_MASK 0x800u
7375 #define LPSPI_IER_TEIE_SHIFT 11u
7376 #define LPSPI_IER_TEIE_WIDTH 1u
7377 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TEIE_SHIFT))&LPSPI_IER_TEIE_MASK)
7378 #define LPSPI_IER_REIE_MASK 0x1000u
7379 #define LPSPI_IER_REIE_SHIFT 12u
7380 #define LPSPI_IER_REIE_WIDTH 1u
7381 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_REIE_SHIFT))&LPSPI_IER_REIE_MASK)
7382 #define LPSPI_IER_DMIE_MASK 0x2000u
7383 #define LPSPI_IER_DMIE_SHIFT 13u
7384 #define LPSPI_IER_DMIE_WIDTH 1u
7385 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_DMIE_SHIFT))&LPSPI_IER_DMIE_MASK)
7387 #define LPSPI_DER_TDDE_MASK 0x1u
7388 #define LPSPI_DER_TDDE_SHIFT 0u
7389 #define LPSPI_DER_TDDE_WIDTH 1u
7390 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_TDDE_SHIFT))&LPSPI_DER_TDDE_MASK)
7391 #define LPSPI_DER_RDDE_MASK 0x2u
7392 #define LPSPI_DER_RDDE_SHIFT 1u
7393 #define LPSPI_DER_RDDE_WIDTH 1u
7394 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_RDDE_SHIFT))&LPSPI_DER_RDDE_MASK)
7396 #define LPSPI_CFGR0_HREN_MASK 0x1u
7397 #define LPSPI_CFGR0_HREN_SHIFT 0u
7398 #define LPSPI_CFGR0_HREN_WIDTH 1u
7399 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HREN_SHIFT))&LPSPI_CFGR0_HREN_MASK)
7400 #define LPSPI_CFGR0_HRPOL_MASK 0x2u
7401 #define LPSPI_CFGR0_HRPOL_SHIFT 1u
7402 #define LPSPI_CFGR0_HRPOL_WIDTH 1u
7403 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRPOL_SHIFT))&LPSPI_CFGR0_HRPOL_MASK)
7404 #define LPSPI_CFGR0_HRSEL_MASK 0x4u
7405 #define LPSPI_CFGR0_HRSEL_SHIFT 2u
7406 #define LPSPI_CFGR0_HRSEL_WIDTH 1u
7407 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRSEL_SHIFT))&LPSPI_CFGR0_HRSEL_MASK)
7408 #define LPSPI_CFGR0_CIRFIFO_MASK 0x100u
7409 #define LPSPI_CFGR0_CIRFIFO_SHIFT 8u
7410 #define LPSPI_CFGR0_CIRFIFO_WIDTH 1u
7411 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_CIRFIFO_SHIFT))&LPSPI_CFGR0_CIRFIFO_MASK)
7412 #define LPSPI_CFGR0_RDMO_MASK 0x200u
7413 #define LPSPI_CFGR0_RDMO_SHIFT 9u
7414 #define LPSPI_CFGR0_RDMO_WIDTH 1u
7415 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_RDMO_SHIFT))&LPSPI_CFGR0_RDMO_MASK)
7417 #define LPSPI_CFGR1_MASTER_MASK 0x1u
7418 #define LPSPI_CFGR1_MASTER_SHIFT 0u
7419 #define LPSPI_CFGR1_MASTER_WIDTH 1u
7420 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MASTER_SHIFT))&LPSPI_CFGR1_MASTER_MASK)
7421 #define LPSPI_CFGR1_SAMPLE_MASK 0x2u
7422 #define LPSPI_CFGR1_SAMPLE_SHIFT 1u
7423 #define LPSPI_CFGR1_SAMPLE_WIDTH 1u
7424 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_SAMPLE_SHIFT))&LPSPI_CFGR1_SAMPLE_MASK)
7425 #define LPSPI_CFGR1_AUTOPCS_MASK 0x4u
7426 #define LPSPI_CFGR1_AUTOPCS_SHIFT 2u
7427 #define LPSPI_CFGR1_AUTOPCS_WIDTH 1u
7428 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_AUTOPCS_SHIFT))&LPSPI_CFGR1_AUTOPCS_MASK)
7429 #define LPSPI_CFGR1_NOSTALL_MASK 0x8u
7430 #define LPSPI_CFGR1_NOSTALL_SHIFT 3u
7431 #define LPSPI_CFGR1_NOSTALL_WIDTH 1u
7432 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_NOSTALL_SHIFT))&LPSPI_CFGR1_NOSTALL_MASK)
7433 #define LPSPI_CFGR1_PCSPOL_MASK 0xF00u
7434 #define LPSPI_CFGR1_PCSPOL_SHIFT 8u
7435 #define LPSPI_CFGR1_PCSPOL_WIDTH 4u
7436 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSPOL_SHIFT))&LPSPI_CFGR1_PCSPOL_MASK)
7437 #define LPSPI_CFGR1_MATCFG_MASK 0x70000u
7438 #define LPSPI_CFGR1_MATCFG_SHIFT 16u
7439 #define LPSPI_CFGR1_MATCFG_WIDTH 3u
7440 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MATCFG_SHIFT))&LPSPI_CFGR1_MATCFG_MASK)
7441 #define LPSPI_CFGR1_PINCFG_MASK 0x3000000u
7442 #define LPSPI_CFGR1_PINCFG_SHIFT 24u
7443 #define LPSPI_CFGR1_PINCFG_WIDTH 2u
7444 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PINCFG_SHIFT))&LPSPI_CFGR1_PINCFG_MASK)
7445 #define LPSPI_CFGR1_OUTCFG_MASK 0x4000000u
7446 #define LPSPI_CFGR1_OUTCFG_SHIFT 26u
7447 #define LPSPI_CFGR1_OUTCFG_WIDTH 1u
7448 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_OUTCFG_SHIFT))&LPSPI_CFGR1_OUTCFG_MASK)
7449 #define LPSPI_CFGR1_PCSCFG_MASK 0x8000000u
7450 #define LPSPI_CFGR1_PCSCFG_SHIFT 27u
7451 #define LPSPI_CFGR1_PCSCFG_WIDTH 1u
7452 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSCFG_SHIFT))&LPSPI_CFGR1_PCSCFG_MASK)
7454 #define LPSPI_DMR0_MATCH0_MASK 0xFFFFFFFFu
7455 #define LPSPI_DMR0_MATCH0_SHIFT 0u
7456 #define LPSPI_DMR0_MATCH0_WIDTH 32u
7457 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR0_MATCH0_SHIFT))&LPSPI_DMR0_MATCH0_MASK)
7459 #define LPSPI_DMR1_MATCH1_MASK 0xFFFFFFFFu
7460 #define LPSPI_DMR1_MATCH1_SHIFT 0u
7461 #define LPSPI_DMR1_MATCH1_WIDTH 32u
7462 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR1_MATCH1_SHIFT))&LPSPI_DMR1_MATCH1_MASK)
7464 #define LPSPI_CCR_SCKDIV_MASK 0xFFu
7465 #define LPSPI_CCR_SCKDIV_SHIFT 0u
7466 #define LPSPI_CCR_SCKDIV_WIDTH 8u
7467 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKDIV_SHIFT))&LPSPI_CCR_SCKDIV_MASK)
7468 #define LPSPI_CCR_DBT_MASK 0xFF00u
7469 #define LPSPI_CCR_DBT_SHIFT 8u
7470 #define LPSPI_CCR_DBT_WIDTH 8u
7471 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_DBT_SHIFT))&LPSPI_CCR_DBT_MASK)
7472 #define LPSPI_CCR_PCSSCK_MASK 0xFF0000u
7473 #define LPSPI_CCR_PCSSCK_SHIFT 16u
7474 #define LPSPI_CCR_PCSSCK_WIDTH 8u
7475 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_PCSSCK_SHIFT))&LPSPI_CCR_PCSSCK_MASK)
7476 #define LPSPI_CCR_SCKPCS_MASK 0xFF000000u
7477 #define LPSPI_CCR_SCKPCS_SHIFT 24u
7478 #define LPSPI_CCR_SCKPCS_WIDTH 8u
7479 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKPCS_SHIFT))&LPSPI_CCR_SCKPCS_MASK)
7481 #define LPSPI_FCR_TXWATER_MASK 0x3u
7482 #define LPSPI_FCR_TXWATER_SHIFT 0u
7483 #define LPSPI_FCR_TXWATER_WIDTH 2u
7484 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_TXWATER_SHIFT))&LPSPI_FCR_TXWATER_MASK)
7485 #define LPSPI_FCR_RXWATER_MASK 0x30000u
7486 #define LPSPI_FCR_RXWATER_SHIFT 16u
7487 #define LPSPI_FCR_RXWATER_WIDTH 2u
7488 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_RXWATER_SHIFT))&LPSPI_FCR_RXWATER_MASK)
7490 #define LPSPI_FSR_TXCOUNT_MASK 0x7u
7491 #define LPSPI_FSR_TXCOUNT_SHIFT 0u
7492 #define LPSPI_FSR_TXCOUNT_WIDTH 3u
7493 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_TXCOUNT_SHIFT))&LPSPI_FSR_TXCOUNT_MASK)
7494 #define LPSPI_FSR_RXCOUNT_MASK 0x70000u
7495 #define LPSPI_FSR_RXCOUNT_SHIFT 16u
7496 #define LPSPI_FSR_RXCOUNT_WIDTH 3u
7497 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_RXCOUNT_SHIFT))&LPSPI_FSR_RXCOUNT_MASK)
7499 #define LPSPI_TCR_FRAMESZ_MASK 0xFFFu
7500 #define LPSPI_TCR_FRAMESZ_SHIFT 0u
7501 #define LPSPI_TCR_FRAMESZ_WIDTH 12u
7502 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_FRAMESZ_SHIFT))&LPSPI_TCR_FRAMESZ_MASK)
7503 #define LPSPI_TCR_WIDTH_MASK 0x30000u
7504 #define LPSPI_TCR_WIDTH_SHIFT 16u
7505 #define LPSPI_TCR_WIDTH_WIDTH 2u
7506 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_WIDTH_SHIFT))&LPSPI_TCR_WIDTH_MASK)
7507 #define LPSPI_TCR_TXMSK_MASK 0x40000u
7508 #define LPSPI_TCR_TXMSK_SHIFT 18u
7509 #define LPSPI_TCR_TXMSK_WIDTH 1u
7510 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_TXMSK_SHIFT))&LPSPI_TCR_TXMSK_MASK)
7511 #define LPSPI_TCR_RXMSK_MASK 0x80000u
7512 #define LPSPI_TCR_RXMSK_SHIFT 19u
7513 #define LPSPI_TCR_RXMSK_WIDTH 1u
7514 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_RXMSK_SHIFT))&LPSPI_TCR_RXMSK_MASK)
7515 #define LPSPI_TCR_CONTC_MASK 0x100000u
7516 #define LPSPI_TCR_CONTC_SHIFT 20u
7517 #define LPSPI_TCR_CONTC_WIDTH 1u
7518 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONTC_SHIFT))&LPSPI_TCR_CONTC_MASK)
7519 #define LPSPI_TCR_CONT_MASK 0x200000u
7520 #define LPSPI_TCR_CONT_SHIFT 21u
7521 #define LPSPI_TCR_CONT_WIDTH 1u
7522 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONT_SHIFT))&LPSPI_TCR_CONT_MASK)
7523 #define LPSPI_TCR_BYSW_MASK 0x400000u
7524 #define LPSPI_TCR_BYSW_SHIFT 22u
7525 #define LPSPI_TCR_BYSW_WIDTH 1u
7526 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_BYSW_SHIFT))&LPSPI_TCR_BYSW_MASK)
7527 #define LPSPI_TCR_LSBF_MASK 0x800000u
7528 #define LPSPI_TCR_LSBF_SHIFT 23u
7529 #define LPSPI_TCR_LSBF_WIDTH 1u
7530 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_LSBF_SHIFT))&LPSPI_TCR_LSBF_MASK)
7531 #define LPSPI_TCR_PCS_MASK 0x3000000u
7532 #define LPSPI_TCR_PCS_SHIFT 24u
7533 #define LPSPI_TCR_PCS_WIDTH 2u
7534 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PCS_SHIFT))&LPSPI_TCR_PCS_MASK)
7535 #define LPSPI_TCR_PRESCALE_MASK 0x38000000u
7536 #define LPSPI_TCR_PRESCALE_SHIFT 27u
7537 #define LPSPI_TCR_PRESCALE_WIDTH 3u
7538 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PRESCALE_SHIFT))&LPSPI_TCR_PRESCALE_MASK)
7539 #define LPSPI_TCR_CPHA_MASK 0x40000000u
7540 #define LPSPI_TCR_CPHA_SHIFT 30u
7541 #define LPSPI_TCR_CPHA_WIDTH 1u
7542 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPHA_SHIFT))&LPSPI_TCR_CPHA_MASK)
7543 #define LPSPI_TCR_CPOL_MASK 0x80000000u
7544 #define LPSPI_TCR_CPOL_SHIFT 31u
7545 #define LPSPI_TCR_CPOL_WIDTH 1u
7546 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPOL_SHIFT))&LPSPI_TCR_CPOL_MASK)
7548 #define LPSPI_TDR_DATA_MASK 0xFFFFFFFFu
7549 #define LPSPI_TDR_DATA_SHIFT 0u
7550 #define LPSPI_TDR_DATA_WIDTH 32u
7551 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TDR_DATA_SHIFT))&LPSPI_TDR_DATA_MASK)
7553 #define LPSPI_RSR_SOF_MASK 0x1u
7554 #define LPSPI_RSR_SOF_SHIFT 0u
7555 #define LPSPI_RSR_SOF_WIDTH 1u
7556 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_SOF_SHIFT))&LPSPI_RSR_SOF_MASK)
7557 #define LPSPI_RSR_RXEMPTY_MASK 0x2u
7558 #define LPSPI_RSR_RXEMPTY_SHIFT 1u
7559 #define LPSPI_RSR_RXEMPTY_WIDTH 1u
7560 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_RXEMPTY_SHIFT))&LPSPI_RSR_RXEMPTY_MASK)
7562 #define LPSPI_RDR_DATA_MASK 0xFFFFFFFFu
7563 #define LPSPI_RDR_DATA_SHIFT 0u
7564 #define LPSPI_RDR_DATA_WIDTH 32u
7565 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RDR_DATA_SHIFT))&LPSPI_RDR_DATA_MASK)
7598 #define LPTMR_INSTANCE_COUNT (1u)
7603 #define LPTMR0_BASE (0x40040000u)
7605 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
7607 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
7609 #define LPTMR_BASE_PTRS { LPTMR0 }
7611 #define LPTMR_IRQS_ARR_COUNT (1u)
7613 #define LPTMR_IRQS_CH_COUNT (1u)
7615 #define LPTMR_IRQS { LPTMR0_IRQn }
7627 #define LPTMR_CSR_TEN_MASK 0x1u
7628 #define LPTMR_CSR_TEN_SHIFT 0u
7629 #define LPTMR_CSR_TEN_WIDTH 1u
7630 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
7631 #define LPTMR_CSR_TMS_MASK 0x2u
7632 #define LPTMR_CSR_TMS_SHIFT 1u
7633 #define LPTMR_CSR_TMS_WIDTH 1u
7634 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
7635 #define LPTMR_CSR_TFC_MASK 0x4u
7636 #define LPTMR_CSR_TFC_SHIFT 2u
7637 #define LPTMR_CSR_TFC_WIDTH 1u
7638 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
7639 #define LPTMR_CSR_TPP_MASK 0x8u
7640 #define LPTMR_CSR_TPP_SHIFT 3u
7641 #define LPTMR_CSR_TPP_WIDTH 1u
7642 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
7643 #define LPTMR_CSR_TPS_MASK 0x30u
7644 #define LPTMR_CSR_TPS_SHIFT 4u
7645 #define LPTMR_CSR_TPS_WIDTH 2u
7646 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
7647 #define LPTMR_CSR_TIE_MASK 0x40u
7648 #define LPTMR_CSR_TIE_SHIFT 6u
7649 #define LPTMR_CSR_TIE_WIDTH 1u
7650 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
7651 #define LPTMR_CSR_TCF_MASK 0x80u
7652 #define LPTMR_CSR_TCF_SHIFT 7u
7653 #define LPTMR_CSR_TCF_WIDTH 1u
7654 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
7655 #define LPTMR_CSR_TDRE_MASK 0x100u
7656 #define LPTMR_CSR_TDRE_SHIFT 8u
7657 #define LPTMR_CSR_TDRE_WIDTH 1u
7658 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TDRE_SHIFT))&LPTMR_CSR_TDRE_MASK)
7660 #define LPTMR_PSR_PCS_MASK 0x3u
7661 #define LPTMR_PSR_PCS_SHIFT 0u
7662 #define LPTMR_PSR_PCS_WIDTH 2u
7663 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
7664 #define LPTMR_PSR_PBYP_MASK 0x4u
7665 #define LPTMR_PSR_PBYP_SHIFT 2u
7666 #define LPTMR_PSR_PBYP_WIDTH 1u
7667 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
7668 #define LPTMR_PSR_PRESCALE_MASK 0x78u
7669 #define LPTMR_PSR_PRESCALE_SHIFT 3u
7670 #define LPTMR_PSR_PRESCALE_WIDTH 4u
7671 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
7673 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
7674 #define LPTMR_CMR_COMPARE_SHIFT 0u
7675 #define LPTMR_CMR_COMPARE_WIDTH 16u
7676 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
7678 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
7679 #define LPTMR_CNR_COUNTER_SHIFT 0u
7680 #define LPTMR_CNR_COUNTER_WIDTH 16u
7681 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
7722 #define LPUART_INSTANCE_COUNT (3u)
7727 #define LPUART0_BASE (0x4006A000u)
7729 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
7731 #define LPUART1_BASE (0x4006B000u)
7733 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
7735 #define LPUART2_BASE (0x4006C000u)
7737 #define LPUART2 ((LPUART_Type *)LPUART2_BASE)
7739 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE }
7741 #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 }
7743 #define LPUART_IRQS_ARR_COUNT (1u)
7745 #define LPUART_RX_TX_IRQS_CH_COUNT (1u)
7747 #define LPUART_RX_TX_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn, LPUART2_RxTx_IRQn }
7759 #define LPUART_VERID_FEATURE_MASK 0xFFFFu
7760 #define LPUART_VERID_FEATURE_SHIFT 0u
7761 #define LPUART_VERID_FEATURE_WIDTH 16u
7762 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_FEATURE_SHIFT))&LPUART_VERID_FEATURE_MASK)
7763 #define LPUART_VERID_MINOR_MASK 0xFF0000u
7764 #define LPUART_VERID_MINOR_SHIFT 16u
7765 #define LPUART_VERID_MINOR_WIDTH 8u
7766 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MINOR_SHIFT))&LPUART_VERID_MINOR_MASK)
7767 #define LPUART_VERID_MAJOR_MASK 0xFF000000u
7768 #define LPUART_VERID_MAJOR_SHIFT 24u
7769 #define LPUART_VERID_MAJOR_WIDTH 8u
7770 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MAJOR_SHIFT))&LPUART_VERID_MAJOR_MASK)
7772 #define LPUART_PARAM_TXFIFO_MASK 0xFFu
7773 #define LPUART_PARAM_TXFIFO_SHIFT 0u
7774 #define LPUART_PARAM_TXFIFO_WIDTH 8u
7775 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_TXFIFO_SHIFT))&LPUART_PARAM_TXFIFO_MASK)
7776 #define LPUART_PARAM_RXFIFO_MASK 0xFF00u
7777 #define LPUART_PARAM_RXFIFO_SHIFT 8u
7778 #define LPUART_PARAM_RXFIFO_WIDTH 8u
7779 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_RXFIFO_SHIFT))&LPUART_PARAM_RXFIFO_MASK)
7781 #define LPUART_GLOBAL_RST_MASK 0x2u
7782 #define LPUART_GLOBAL_RST_SHIFT 1u
7783 #define LPUART_GLOBAL_RST_WIDTH 1u
7784 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<LPUART_GLOBAL_RST_SHIFT))&LPUART_GLOBAL_RST_MASK)
7786 #define LPUART_PINCFG_TRGSEL_MASK 0x3u
7787 #define LPUART_PINCFG_TRGSEL_SHIFT 0u
7788 #define LPUART_PINCFG_TRGSEL_WIDTH 2u
7789 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PINCFG_TRGSEL_SHIFT))&LPUART_PINCFG_TRGSEL_MASK)
7791 #define LPUART_BAUD_SBR_MASK 0x1FFFu
7792 #define LPUART_BAUD_SBR_SHIFT 0u
7793 #define LPUART_BAUD_SBR_WIDTH 13u
7794 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
7795 #define LPUART_BAUD_SBNS_MASK 0x2000u
7796 #define LPUART_BAUD_SBNS_SHIFT 13u
7797 #define LPUART_BAUD_SBNS_WIDTH 1u
7798 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
7799 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
7800 #define LPUART_BAUD_RXEDGIE_SHIFT 14u
7801 #define LPUART_BAUD_RXEDGIE_WIDTH 1u
7802 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
7803 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
7804 #define LPUART_BAUD_LBKDIE_SHIFT 15u
7805 #define LPUART_BAUD_LBKDIE_WIDTH 1u
7806 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
7807 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
7808 #define LPUART_BAUD_RESYNCDIS_SHIFT 16u
7809 #define LPUART_BAUD_RESYNCDIS_WIDTH 1u
7810 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
7811 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
7812 #define LPUART_BAUD_BOTHEDGE_SHIFT 17u
7813 #define LPUART_BAUD_BOTHEDGE_WIDTH 1u
7814 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
7815 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
7816 #define LPUART_BAUD_MATCFG_SHIFT 18u
7817 #define LPUART_BAUD_MATCFG_WIDTH 2u
7818 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
7819 #define LPUART_BAUD_RIDMAE_MASK 0x100000u
7820 #define LPUART_BAUD_RIDMAE_SHIFT 20u
7821 #define LPUART_BAUD_RIDMAE_WIDTH 1u
7822 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RIDMAE_SHIFT))&LPUART_BAUD_RIDMAE_MASK)
7823 #define LPUART_BAUD_RDMAE_MASK 0x200000u
7824 #define LPUART_BAUD_RDMAE_SHIFT 21u
7825 #define LPUART_BAUD_RDMAE_WIDTH 1u
7826 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
7827 #define LPUART_BAUD_TDMAE_MASK 0x800000u
7828 #define LPUART_BAUD_TDMAE_SHIFT 23u
7829 #define LPUART_BAUD_TDMAE_WIDTH 1u
7830 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
7831 #define LPUART_BAUD_OSR_MASK 0x1F000000u
7832 #define LPUART_BAUD_OSR_SHIFT 24u
7833 #define LPUART_BAUD_OSR_WIDTH 5u
7834 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
7835 #define LPUART_BAUD_M10_MASK 0x20000000u
7836 #define LPUART_BAUD_M10_SHIFT 29u
7837 #define LPUART_BAUD_M10_WIDTH 1u
7838 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
7839 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
7840 #define LPUART_BAUD_MAEN2_SHIFT 30u
7841 #define LPUART_BAUD_MAEN2_WIDTH 1u
7842 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
7843 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
7844 #define LPUART_BAUD_MAEN1_SHIFT 31u
7845 #define LPUART_BAUD_MAEN1_WIDTH 1u
7846 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
7848 #define LPUART_STAT_MA2F_MASK 0x4000u
7849 #define LPUART_STAT_MA2F_SHIFT 14u
7850 #define LPUART_STAT_MA2F_WIDTH 1u
7851 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
7852 #define LPUART_STAT_MA1F_MASK 0x8000u
7853 #define LPUART_STAT_MA1F_SHIFT 15u
7854 #define LPUART_STAT_MA1F_WIDTH 1u
7855 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
7856 #define LPUART_STAT_PF_MASK 0x10000u
7857 #define LPUART_STAT_PF_SHIFT 16u
7858 #define LPUART_STAT_PF_WIDTH 1u
7859 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
7860 #define LPUART_STAT_FE_MASK 0x20000u
7861 #define LPUART_STAT_FE_SHIFT 17u
7862 #define LPUART_STAT_FE_WIDTH 1u
7863 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
7864 #define LPUART_STAT_NF_MASK 0x40000u
7865 #define LPUART_STAT_NF_SHIFT 18u
7866 #define LPUART_STAT_NF_WIDTH 1u
7867 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
7868 #define LPUART_STAT_OR_MASK 0x80000u
7869 #define LPUART_STAT_OR_SHIFT 19u
7870 #define LPUART_STAT_OR_WIDTH 1u
7871 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
7872 #define LPUART_STAT_IDLE_MASK 0x100000u
7873 #define LPUART_STAT_IDLE_SHIFT 20u
7874 #define LPUART_STAT_IDLE_WIDTH 1u
7875 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
7876 #define LPUART_STAT_RDRF_MASK 0x200000u
7877 #define LPUART_STAT_RDRF_SHIFT 21u
7878 #define LPUART_STAT_RDRF_WIDTH 1u
7879 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
7880 #define LPUART_STAT_TC_MASK 0x400000u
7881 #define LPUART_STAT_TC_SHIFT 22u
7882 #define LPUART_STAT_TC_WIDTH 1u
7883 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
7884 #define LPUART_STAT_TDRE_MASK 0x800000u
7885 #define LPUART_STAT_TDRE_SHIFT 23u
7886 #define LPUART_STAT_TDRE_WIDTH 1u
7887 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
7888 #define LPUART_STAT_RAF_MASK 0x1000000u
7889 #define LPUART_STAT_RAF_SHIFT 24u
7890 #define LPUART_STAT_RAF_WIDTH 1u
7891 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
7892 #define LPUART_STAT_LBKDE_MASK 0x2000000u
7893 #define LPUART_STAT_LBKDE_SHIFT 25u
7894 #define LPUART_STAT_LBKDE_WIDTH 1u
7895 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
7896 #define LPUART_STAT_BRK13_MASK 0x4000000u
7897 #define LPUART_STAT_BRK13_SHIFT 26u
7898 #define LPUART_STAT_BRK13_WIDTH 1u
7899 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
7900 #define LPUART_STAT_RWUID_MASK 0x8000000u
7901 #define LPUART_STAT_RWUID_SHIFT 27u
7902 #define LPUART_STAT_RWUID_WIDTH 1u
7903 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
7904 #define LPUART_STAT_RXINV_MASK 0x10000000u
7905 #define LPUART_STAT_RXINV_SHIFT 28u
7906 #define LPUART_STAT_RXINV_WIDTH 1u
7907 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
7908 #define LPUART_STAT_MSBF_MASK 0x20000000u
7909 #define LPUART_STAT_MSBF_SHIFT 29u
7910 #define LPUART_STAT_MSBF_WIDTH 1u
7911 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
7912 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
7913 #define LPUART_STAT_RXEDGIF_SHIFT 30u
7914 #define LPUART_STAT_RXEDGIF_WIDTH 1u
7915 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
7916 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
7917 #define LPUART_STAT_LBKDIF_SHIFT 31u
7918 #define LPUART_STAT_LBKDIF_WIDTH 1u
7919 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
7921 #define LPUART_CTRL_PT_MASK 0x1u
7922 #define LPUART_CTRL_PT_SHIFT 0u
7923 #define LPUART_CTRL_PT_WIDTH 1u
7924 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
7925 #define LPUART_CTRL_PE_MASK 0x2u
7926 #define LPUART_CTRL_PE_SHIFT 1u
7927 #define LPUART_CTRL_PE_WIDTH 1u
7928 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
7929 #define LPUART_CTRL_ILT_MASK 0x4u
7930 #define LPUART_CTRL_ILT_SHIFT 2u
7931 #define LPUART_CTRL_ILT_WIDTH 1u
7932 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
7933 #define LPUART_CTRL_WAKE_MASK 0x8u
7934 #define LPUART_CTRL_WAKE_SHIFT 3u
7935 #define LPUART_CTRL_WAKE_WIDTH 1u
7936 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
7937 #define LPUART_CTRL_M_MASK 0x10u
7938 #define LPUART_CTRL_M_SHIFT 4u
7939 #define LPUART_CTRL_M_WIDTH 1u
7940 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
7941 #define LPUART_CTRL_RSRC_MASK 0x20u
7942 #define LPUART_CTRL_RSRC_SHIFT 5u
7943 #define LPUART_CTRL_RSRC_WIDTH 1u
7944 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
7945 #define LPUART_CTRL_DOZEEN_MASK 0x40u
7946 #define LPUART_CTRL_DOZEEN_SHIFT 6u
7947 #define LPUART_CTRL_DOZEEN_WIDTH 1u
7948 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
7949 #define LPUART_CTRL_LOOPS_MASK 0x80u
7950 #define LPUART_CTRL_LOOPS_SHIFT 7u
7951 #define LPUART_CTRL_LOOPS_WIDTH 1u
7952 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
7953 #define LPUART_CTRL_IDLECFG_MASK 0x700u
7954 #define LPUART_CTRL_IDLECFG_SHIFT 8u
7955 #define LPUART_CTRL_IDLECFG_WIDTH 3u
7956 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
7957 #define LPUART_CTRL_M7_MASK 0x800u
7958 #define LPUART_CTRL_M7_SHIFT 11u
7959 #define LPUART_CTRL_M7_WIDTH 1u
7960 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M7_SHIFT))&LPUART_CTRL_M7_MASK)
7961 #define LPUART_CTRL_MA2IE_MASK 0x4000u
7962 #define LPUART_CTRL_MA2IE_SHIFT 14u
7963 #define LPUART_CTRL_MA2IE_WIDTH 1u
7964 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
7965 #define LPUART_CTRL_MA1IE_MASK 0x8000u
7966 #define LPUART_CTRL_MA1IE_SHIFT 15u
7967 #define LPUART_CTRL_MA1IE_WIDTH 1u
7968 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
7969 #define LPUART_CTRL_SBK_MASK 0x10000u
7970 #define LPUART_CTRL_SBK_SHIFT 16u
7971 #define LPUART_CTRL_SBK_WIDTH 1u
7972 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
7973 #define LPUART_CTRL_RWU_MASK 0x20000u
7974 #define LPUART_CTRL_RWU_SHIFT 17u
7975 #define LPUART_CTRL_RWU_WIDTH 1u
7976 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
7977 #define LPUART_CTRL_RE_MASK 0x40000u
7978 #define LPUART_CTRL_RE_SHIFT 18u
7979 #define LPUART_CTRL_RE_WIDTH 1u
7980 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
7981 #define LPUART_CTRL_TE_MASK 0x80000u
7982 #define LPUART_CTRL_TE_SHIFT 19u
7983 #define LPUART_CTRL_TE_WIDTH 1u
7984 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
7985 #define LPUART_CTRL_ILIE_MASK 0x100000u
7986 #define LPUART_CTRL_ILIE_SHIFT 20u
7987 #define LPUART_CTRL_ILIE_WIDTH 1u
7988 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
7989 #define LPUART_CTRL_RIE_MASK 0x200000u
7990 #define LPUART_CTRL_RIE_SHIFT 21u
7991 #define LPUART_CTRL_RIE_WIDTH 1u
7992 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
7993 #define LPUART_CTRL_TCIE_MASK 0x400000u
7994 #define LPUART_CTRL_TCIE_SHIFT 22u
7995 #define LPUART_CTRL_TCIE_WIDTH 1u
7996 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
7997 #define LPUART_CTRL_TIE_MASK 0x800000u
7998 #define LPUART_CTRL_TIE_SHIFT 23u
7999 #define LPUART_CTRL_TIE_WIDTH 1u
8000 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
8001 #define LPUART_CTRL_PEIE_MASK 0x1000000u
8002 #define LPUART_CTRL_PEIE_SHIFT 24u
8003 #define LPUART_CTRL_PEIE_WIDTH 1u
8004 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
8005 #define LPUART_CTRL_FEIE_MASK 0x2000000u
8006 #define LPUART_CTRL_FEIE_SHIFT 25u
8007 #define LPUART_CTRL_FEIE_WIDTH 1u
8008 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
8009 #define LPUART_CTRL_NEIE_MASK 0x4000000u
8010 #define LPUART_CTRL_NEIE_SHIFT 26u
8011 #define LPUART_CTRL_NEIE_WIDTH 1u
8012 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
8013 #define LPUART_CTRL_ORIE_MASK 0x8000000u
8014 #define LPUART_CTRL_ORIE_SHIFT 27u
8015 #define LPUART_CTRL_ORIE_WIDTH 1u
8016 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
8017 #define LPUART_CTRL_TXINV_MASK 0x10000000u
8018 #define LPUART_CTRL_TXINV_SHIFT 28u
8019 #define LPUART_CTRL_TXINV_WIDTH 1u
8020 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
8021 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
8022 #define LPUART_CTRL_TXDIR_SHIFT 29u
8023 #define LPUART_CTRL_TXDIR_WIDTH 1u
8024 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
8025 #define LPUART_CTRL_R9T8_MASK 0x40000000u
8026 #define LPUART_CTRL_R9T8_SHIFT 30u
8027 #define LPUART_CTRL_R9T8_WIDTH 1u
8028 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
8029 #define LPUART_CTRL_R8T9_MASK 0x80000000u
8030 #define LPUART_CTRL_R8T9_SHIFT 31u
8031 #define LPUART_CTRL_R8T9_WIDTH 1u
8032 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
8034 #define LPUART_DATA_R0T0_MASK 0x1u
8035 #define LPUART_DATA_R0T0_SHIFT 0u
8036 #define LPUART_DATA_R0T0_WIDTH 1u
8037 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
8038 #define LPUART_DATA_R1T1_MASK 0x2u
8039 #define LPUART_DATA_R1T1_SHIFT 1u
8040 #define LPUART_DATA_R1T1_WIDTH 1u
8041 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
8042 #define LPUART_DATA_R2T2_MASK 0x4u
8043 #define LPUART_DATA_R2T2_SHIFT 2u
8044 #define LPUART_DATA_R2T2_WIDTH 1u
8045 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
8046 #define LPUART_DATA_R3T3_MASK 0x8u
8047 #define LPUART_DATA_R3T3_SHIFT 3u
8048 #define LPUART_DATA_R3T3_WIDTH 1u
8049 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
8050 #define LPUART_DATA_R4T4_MASK 0x10u
8051 #define LPUART_DATA_R4T4_SHIFT 4u
8052 #define LPUART_DATA_R4T4_WIDTH 1u
8053 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
8054 #define LPUART_DATA_R5T5_MASK 0x20u
8055 #define LPUART_DATA_R5T5_SHIFT 5u
8056 #define LPUART_DATA_R5T5_WIDTH 1u
8057 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
8058 #define LPUART_DATA_R6T6_MASK 0x40u
8059 #define LPUART_DATA_R6T6_SHIFT 6u
8060 #define LPUART_DATA_R6T6_WIDTH 1u
8061 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
8062 #define LPUART_DATA_R7T7_MASK 0x80u
8063 #define LPUART_DATA_R7T7_SHIFT 7u
8064 #define LPUART_DATA_R7T7_WIDTH 1u
8065 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
8066 #define LPUART_DATA_R8T8_MASK 0x100u
8067 #define LPUART_DATA_R8T8_SHIFT 8u
8068 #define LPUART_DATA_R8T8_WIDTH 1u
8069 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
8070 #define LPUART_DATA_R9T9_MASK 0x200u
8071 #define LPUART_DATA_R9T9_SHIFT 9u
8072 #define LPUART_DATA_R9T9_WIDTH 1u
8073 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
8074 #define LPUART_DATA_IDLINE_MASK 0x800u
8075 #define LPUART_DATA_IDLINE_SHIFT 11u
8076 #define LPUART_DATA_IDLINE_WIDTH 1u
8077 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
8078 #define LPUART_DATA_RXEMPT_MASK 0x1000u
8079 #define LPUART_DATA_RXEMPT_SHIFT 12u
8080 #define LPUART_DATA_RXEMPT_WIDTH 1u
8081 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
8082 #define LPUART_DATA_FRETSC_MASK 0x2000u
8083 #define LPUART_DATA_FRETSC_SHIFT 13u
8084 #define LPUART_DATA_FRETSC_WIDTH 1u
8085 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
8086 #define LPUART_DATA_PARITYE_MASK 0x4000u
8087 #define LPUART_DATA_PARITYE_SHIFT 14u
8088 #define LPUART_DATA_PARITYE_WIDTH 1u
8089 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
8090 #define LPUART_DATA_NOISY_MASK 0x8000u
8091 #define LPUART_DATA_NOISY_SHIFT 15u
8092 #define LPUART_DATA_NOISY_WIDTH 1u
8093 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
8095 #define LPUART_MATCH_MA1_MASK 0x3FFu
8096 #define LPUART_MATCH_MA1_SHIFT 0u
8097 #define LPUART_MATCH_MA1_WIDTH 10u
8098 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
8099 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
8100 #define LPUART_MATCH_MA2_SHIFT 16u
8101 #define LPUART_MATCH_MA2_WIDTH 10u
8102 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
8104 #define LPUART_MODIR_TXCTSE_MASK 0x1u
8105 #define LPUART_MODIR_TXCTSE_SHIFT 0u
8106 #define LPUART_MODIR_TXCTSE_WIDTH 1u
8107 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
8108 #define LPUART_MODIR_TXRTSE_MASK 0x2u
8109 #define LPUART_MODIR_TXRTSE_SHIFT 1u
8110 #define LPUART_MODIR_TXRTSE_WIDTH 1u
8111 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
8112 #define LPUART_MODIR_TXRTSPOL_MASK 0x4u
8113 #define LPUART_MODIR_TXRTSPOL_SHIFT 2u
8114 #define LPUART_MODIR_TXRTSPOL_WIDTH 1u
8115 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
8116 #define LPUART_MODIR_RXRTSE_MASK 0x8u
8117 #define LPUART_MODIR_RXRTSE_SHIFT 3u
8118 #define LPUART_MODIR_RXRTSE_WIDTH 1u
8119 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
8120 #define LPUART_MODIR_TXCTSC_MASK 0x10u
8121 #define LPUART_MODIR_TXCTSC_SHIFT 4u
8122 #define LPUART_MODIR_TXCTSC_WIDTH 1u
8123 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
8124 #define LPUART_MODIR_TXCTSSRC_MASK 0x20u
8125 #define LPUART_MODIR_TXCTSSRC_SHIFT 5u
8126 #define LPUART_MODIR_TXCTSSRC_WIDTH 1u
8127 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
8128 #define LPUART_MODIR_RTSWATER_MASK 0x300u
8129 #define LPUART_MODIR_RTSWATER_SHIFT 8u
8130 #define LPUART_MODIR_RTSWATER_WIDTH 2u
8131 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RTSWATER_SHIFT))&LPUART_MODIR_RTSWATER_MASK)
8132 #define LPUART_MODIR_TNP_MASK 0x30000u
8133 #define LPUART_MODIR_TNP_SHIFT 16u
8134 #define LPUART_MODIR_TNP_WIDTH 2u
8135 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
8136 #define LPUART_MODIR_IREN_MASK 0x40000u
8137 #define LPUART_MODIR_IREN_SHIFT 18u
8138 #define LPUART_MODIR_IREN_WIDTH 1u
8139 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
8141 #define LPUART_FIFO_RXFIFOSIZE_MASK 0x7u
8142 #define LPUART_FIFO_RXFIFOSIZE_SHIFT 0u
8143 #define LPUART_FIFO_RXFIFOSIZE_WIDTH 3u
8144 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFIFOSIZE_SHIFT))&LPUART_FIFO_RXFIFOSIZE_MASK)
8145 #define LPUART_FIFO_RXFE_MASK 0x8u
8146 #define LPUART_FIFO_RXFE_SHIFT 3u
8147 #define LPUART_FIFO_RXFE_WIDTH 1u
8148 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFE_SHIFT))&LPUART_FIFO_RXFE_MASK)
8149 #define LPUART_FIFO_TXFIFOSIZE_MASK 0x70u
8150 #define LPUART_FIFO_TXFIFOSIZE_SHIFT 4u
8151 #define LPUART_FIFO_TXFIFOSIZE_WIDTH 3u
8152 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFIFOSIZE_SHIFT))&LPUART_FIFO_TXFIFOSIZE_MASK)
8153 #define LPUART_FIFO_TXFE_MASK 0x80u
8154 #define LPUART_FIFO_TXFE_SHIFT 7u
8155 #define LPUART_FIFO_TXFE_WIDTH 1u
8156 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFE_SHIFT))&LPUART_FIFO_TXFE_MASK)
8157 #define LPUART_FIFO_RXUFE_MASK 0x100u
8158 #define LPUART_FIFO_RXUFE_SHIFT 8u
8159 #define LPUART_FIFO_RXUFE_WIDTH 1u
8160 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUFE_SHIFT))&LPUART_FIFO_RXUFE_MASK)
8161 #define LPUART_FIFO_TXOFE_MASK 0x200u
8162 #define LPUART_FIFO_TXOFE_SHIFT 9u
8163 #define LPUART_FIFO_TXOFE_WIDTH 1u
8164 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOFE_SHIFT))&LPUART_FIFO_TXOFE_MASK)
8165 #define LPUART_FIFO_RXIDEN_MASK 0x1C00u
8166 #define LPUART_FIFO_RXIDEN_SHIFT 10u
8167 #define LPUART_FIFO_RXIDEN_WIDTH 3u
8168 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXIDEN_SHIFT))&LPUART_FIFO_RXIDEN_MASK)
8169 #define LPUART_FIFO_RXFLUSH_MASK 0x4000u
8170 #define LPUART_FIFO_RXFLUSH_SHIFT 14u
8171 #define LPUART_FIFO_RXFLUSH_WIDTH 1u
8172 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFLUSH_SHIFT))&LPUART_FIFO_RXFLUSH_MASK)
8173 #define LPUART_FIFO_TXFLUSH_MASK 0x8000u
8174 #define LPUART_FIFO_TXFLUSH_SHIFT 15u
8175 #define LPUART_FIFO_TXFLUSH_WIDTH 1u
8176 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFLUSH_SHIFT))&LPUART_FIFO_TXFLUSH_MASK)
8177 #define LPUART_FIFO_RXUF_MASK 0x10000u
8178 #define LPUART_FIFO_RXUF_SHIFT 16u
8179 #define LPUART_FIFO_RXUF_WIDTH 1u
8180 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUF_SHIFT))&LPUART_FIFO_RXUF_MASK)
8181 #define LPUART_FIFO_TXOF_MASK 0x20000u
8182 #define LPUART_FIFO_TXOF_SHIFT 17u
8183 #define LPUART_FIFO_TXOF_WIDTH 1u
8184 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOF_SHIFT))&LPUART_FIFO_TXOF_MASK)
8185 #define LPUART_FIFO_RXEMPT_MASK 0x400000u
8186 #define LPUART_FIFO_RXEMPT_SHIFT 22u
8187 #define LPUART_FIFO_RXEMPT_WIDTH 1u
8188 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXEMPT_SHIFT))&LPUART_FIFO_RXEMPT_MASK)
8189 #define LPUART_FIFO_TXEMPT_MASK 0x800000u
8190 #define LPUART_FIFO_TXEMPT_SHIFT 23u
8191 #define LPUART_FIFO_TXEMPT_WIDTH 1u
8192 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXEMPT_SHIFT))&LPUART_FIFO_TXEMPT_MASK)
8194 #define LPUART_WATER_TXWATER_MASK 0x3u
8195 #define LPUART_WATER_TXWATER_SHIFT 0u
8196 #define LPUART_WATER_TXWATER_WIDTH 2u
8197 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXWATER_SHIFT))&LPUART_WATER_TXWATER_MASK)
8198 #define LPUART_WATER_TXCOUNT_MASK 0x700u
8199 #define LPUART_WATER_TXCOUNT_SHIFT 8u
8200 #define LPUART_WATER_TXCOUNT_WIDTH 3u
8201 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXCOUNT_SHIFT))&LPUART_WATER_TXCOUNT_MASK)
8202 #define LPUART_WATER_RXWATER_MASK 0x30000u
8203 #define LPUART_WATER_RXWATER_SHIFT 16u
8204 #define LPUART_WATER_RXWATER_WIDTH 2u
8205 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXWATER_SHIFT))&LPUART_WATER_RXWATER_MASK)
8206 #define LPUART_WATER_RXCOUNT_MASK 0x7000000u
8207 #define LPUART_WATER_RXCOUNT_SHIFT 24u
8208 #define LPUART_WATER_RXCOUNT_WIDTH 3u
8209 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXCOUNT_SHIFT))&LPUART_WATER_RXCOUNT_MASK)
8232 #define MCM_LMDR_COUNT 2u
8236 uint8_t RESERVED_0[8];
8241 uint8_t RESERVED_1[28];
8243 uint8_t RESERVED_2[12];
8245 uint8_t RESERVED_3[956];
8248 uint8_t RESERVED_4[116];
8250 uint8_t RESERVED_5[4];
8252 uint8_t RESERVED_6[4];
8255 uint8_t RESERVED_7[8];
8261 #define MCM_INSTANCE_COUNT (1u)
8266 #define MCM_BASE (0xE0080000u)
8268 #define MCM ((MCM_Type *)MCM_BASE)
8270 #define MCM_BASE_ADDRS { MCM_BASE }
8272 #define MCM_BASE_PTRS { MCM }
8274 #define MCM_IRQS_ARR_COUNT (1u)
8276 #define MCM_IRQS_CH_COUNT (1u)
8278 #define MCM_IRQS { MCM_IRQn }
8290 #define MCM_PLASC_ASC_MASK 0xFFu
8291 #define MCM_PLASC_ASC_SHIFT 0u
8292 #define MCM_PLASC_ASC_WIDTH 8u
8293 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
8295 #define MCM_PLAMC_AMC_MASK 0xFFu
8296 #define MCM_PLAMC_AMC_SHIFT 0u
8297 #define MCM_PLAMC_AMC_WIDTH 8u
8298 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
8300 #define MCM_CPCR_HLT_FSM_ST_MASK 0x3u
8301 #define MCM_CPCR_HLT_FSM_ST_SHIFT 0u
8302 #define MCM_CPCR_HLT_FSM_ST_WIDTH 2u
8303 #define MCM_CPCR_HLT_FSM_ST(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_HLT_FSM_ST_SHIFT))&MCM_CPCR_HLT_FSM_ST_MASK)
8304 #define MCM_CPCR_AXBS_HLT_REQ_MASK 0x4u
8305 #define MCM_CPCR_AXBS_HLT_REQ_SHIFT 2u
8306 #define MCM_CPCR_AXBS_HLT_REQ_WIDTH 1u
8307 #define MCM_CPCR_AXBS_HLT_REQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLT_REQ_SHIFT))&MCM_CPCR_AXBS_HLT_REQ_MASK)
8308 #define MCM_CPCR_AXBS_HLTD_MASK 0x8u
8309 #define MCM_CPCR_AXBS_HLTD_SHIFT 3u
8310 #define MCM_CPCR_AXBS_HLTD_WIDTH 1u
8311 #define MCM_CPCR_AXBS_HLTD(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLTD_SHIFT))&MCM_CPCR_AXBS_HLTD_MASK)
8312 #define MCM_CPCR_FMC_PF_IDLE_MASK 0x10u
8313 #define MCM_CPCR_FMC_PF_IDLE_SHIFT 4u
8314 #define MCM_CPCR_FMC_PF_IDLE_WIDTH 1u
8315 #define MCM_CPCR_FMC_PF_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_FMC_PF_IDLE_SHIFT))&MCM_CPCR_FMC_PF_IDLE_MASK)
8316 #define MCM_CPCR_PBRIDGE_IDLE_MASK 0x40u
8317 #define MCM_CPCR_PBRIDGE_IDLE_SHIFT 6u
8318 #define MCM_CPCR_PBRIDGE_IDLE_WIDTH 1u
8319 #define MCM_CPCR_PBRIDGE_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_PBRIDGE_IDLE_SHIFT))&MCM_CPCR_PBRIDGE_IDLE_MASK)
8320 #define MCM_CPCR_CBRR_MASK 0x200u
8321 #define MCM_CPCR_CBRR_SHIFT 9u
8322 #define MCM_CPCR_CBRR_WIDTH 1u
8323 #define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_CBRR_SHIFT))&MCM_CPCR_CBRR_MASK)
8324 #define MCM_CPCR_SRAMUAP_MASK 0x3000000u
8325 #define MCM_CPCR_SRAMUAP_SHIFT 24u
8326 #define MCM_CPCR_SRAMUAP_WIDTH 2u
8327 #define MCM_CPCR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUAP_SHIFT))&MCM_CPCR_SRAMUAP_MASK)
8328 #define MCM_CPCR_SRAMUWP_MASK 0x4000000u
8329 #define MCM_CPCR_SRAMUWP_SHIFT 26u
8330 #define MCM_CPCR_SRAMUWP_WIDTH 1u
8331 #define MCM_CPCR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUWP_SHIFT))&MCM_CPCR_SRAMUWP_MASK)
8332 #define MCM_CPCR_SRAMLAP_MASK 0x30000000u
8333 #define MCM_CPCR_SRAMLAP_SHIFT 28u
8334 #define MCM_CPCR_SRAMLAP_WIDTH 2u
8335 #define MCM_CPCR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLAP_SHIFT))&MCM_CPCR_SRAMLAP_MASK)
8336 #define MCM_CPCR_SRAMLWP_MASK 0x40000000u
8337 #define MCM_CPCR_SRAMLWP_SHIFT 30u
8338 #define MCM_CPCR_SRAMLWP_WIDTH 1u
8339 #define MCM_CPCR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLWP_SHIFT))&MCM_CPCR_SRAMLWP_MASK)
8341 #define MCM_ISCR_FIOC_MASK 0x100u
8342 #define MCM_ISCR_FIOC_SHIFT 8u
8343 #define MCM_ISCR_FIOC_WIDTH 1u
8344 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
8345 #define MCM_ISCR_FDZC_MASK 0x200u
8346 #define MCM_ISCR_FDZC_SHIFT 9u
8347 #define MCM_ISCR_FDZC_WIDTH 1u
8348 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
8349 #define MCM_ISCR_FOFC_MASK 0x400u
8350 #define MCM_ISCR_FOFC_SHIFT 10u
8351 #define MCM_ISCR_FOFC_WIDTH 1u
8352 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
8353 #define MCM_ISCR_FUFC_MASK 0x800u
8354 #define MCM_ISCR_FUFC_SHIFT 11u
8355 #define MCM_ISCR_FUFC_WIDTH 1u
8356 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
8357 #define MCM_ISCR_FIXC_MASK 0x1000u
8358 #define MCM_ISCR_FIXC_SHIFT 12u
8359 #define MCM_ISCR_FIXC_WIDTH 1u
8360 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
8361 #define MCM_ISCR_FIDC_MASK 0x8000u
8362 #define MCM_ISCR_FIDC_SHIFT 15u
8363 #define MCM_ISCR_FIDC_WIDTH 1u
8364 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
8365 #define MCM_ISCR_FIOCE_MASK 0x1000000u
8366 #define MCM_ISCR_FIOCE_SHIFT 24u
8367 #define MCM_ISCR_FIOCE_WIDTH 1u
8368 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
8369 #define MCM_ISCR_FDZCE_MASK 0x2000000u
8370 #define MCM_ISCR_FDZCE_SHIFT 25u
8371 #define MCM_ISCR_FDZCE_WIDTH 1u
8372 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
8373 #define MCM_ISCR_FOFCE_MASK 0x4000000u
8374 #define MCM_ISCR_FOFCE_SHIFT 26u
8375 #define MCM_ISCR_FOFCE_WIDTH 1u
8376 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
8377 #define MCM_ISCR_FUFCE_MASK 0x8000000u
8378 #define MCM_ISCR_FUFCE_SHIFT 27u
8379 #define MCM_ISCR_FUFCE_WIDTH 1u
8380 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
8381 #define MCM_ISCR_FIXCE_MASK 0x10000000u
8382 #define MCM_ISCR_FIXCE_SHIFT 28u
8383 #define MCM_ISCR_FIXCE_WIDTH 1u
8384 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
8385 #define MCM_ISCR_FIDCE_MASK 0x80000000u
8386 #define MCM_ISCR_FIDCE_SHIFT 31u
8387 #define MCM_ISCR_FIDCE_WIDTH 1u
8388 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
8390 #define MCM_PID_PID_MASK 0xFFu
8391 #define MCM_PID_PID_SHIFT 0u
8392 #define MCM_PID_PID_WIDTH 8u
8393 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
8395 #define MCM_CPO_CPOREQ_MASK 0x1u
8396 #define MCM_CPO_CPOREQ_SHIFT 0u
8397 #define MCM_CPO_CPOREQ_WIDTH 1u
8398 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
8399 #define MCM_CPO_CPOACK_MASK 0x2u
8400 #define MCM_CPO_CPOACK_SHIFT 1u
8401 #define MCM_CPO_CPOACK_WIDTH 1u
8402 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
8403 #define MCM_CPO_CPOWOI_MASK 0x4u
8404 #define MCM_CPO_CPOWOI_SHIFT 2u
8405 #define MCM_CPO_CPOWOI_WIDTH 1u
8406 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
8408 #define MCM_LMDR_CF0_MASK 0xFu
8409 #define MCM_LMDR_CF0_SHIFT 0u
8410 #define MCM_LMDR_CF0_WIDTH 4u
8411 #define MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF0_SHIFT))&MCM_LMDR_CF0_MASK)
8412 #define MCM_LMDR_CF1_MASK 0xF0u
8413 #define MCM_LMDR_CF1_SHIFT 4u
8414 #define MCM_LMDR_CF1_WIDTH 4u
8415 #define MCM_LMDR_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF1_SHIFT))&MCM_LMDR_CF1_MASK)
8416 #define MCM_LMDR_MT_MASK 0xE000u
8417 #define MCM_LMDR_MT_SHIFT 13u
8418 #define MCM_LMDR_MT_WIDTH 3u
8419 #define MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_MT_SHIFT))&MCM_LMDR_MT_MASK)
8420 #define MCM_LMDR_LOCK_MASK 0x10000u
8421 #define MCM_LMDR_LOCK_SHIFT 16u
8422 #define MCM_LMDR_LOCK_WIDTH 1u
8423 #define MCM_LMDR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LOCK_SHIFT))&MCM_LMDR_LOCK_MASK)
8424 #define MCM_LMDR_DPW_MASK 0xE0000u
8425 #define MCM_LMDR_DPW_SHIFT 17u
8426 #define MCM_LMDR_DPW_WIDTH 3u
8427 #define MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_DPW_SHIFT))&MCM_LMDR_DPW_MASK)
8428 #define MCM_LMDR_WY_MASK 0xF00000u
8429 #define MCM_LMDR_WY_SHIFT 20u
8430 #define MCM_LMDR_WY_WIDTH 4u
8431 #define MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_WY_SHIFT))&MCM_LMDR_WY_MASK)
8432 #define MCM_LMDR_LMSZ_MASK 0xF000000u
8433 #define MCM_LMDR_LMSZ_SHIFT 24u
8434 #define MCM_LMDR_LMSZ_WIDTH 4u
8435 #define MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZ_SHIFT))&MCM_LMDR_LMSZ_MASK)
8436 #define MCM_LMDR_LMSZH_MASK 0x10000000u
8437 #define MCM_LMDR_LMSZH_SHIFT 28u
8438 #define MCM_LMDR_LMSZH_WIDTH 1u
8439 #define MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZH_SHIFT))&MCM_LMDR_LMSZH_MASK)
8440 #define MCM_LMDR_V_MASK 0x80000000u
8441 #define MCM_LMDR_V_SHIFT 31u
8442 #define MCM_LMDR_V_WIDTH 1u
8443 #define MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_V_SHIFT))&MCM_LMDR_V_MASK)
8445 #define MCM_LMDR2_CF1_MASK 0xF0u
8446 #define MCM_LMDR2_CF1_SHIFT 4u
8447 #define MCM_LMDR2_CF1_WIDTH 4u
8448 #define MCM_LMDR2_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_CF1_SHIFT))&MCM_LMDR2_CF1_MASK)
8449 #define MCM_LMDR2_MT_MASK 0xE000u
8450 #define MCM_LMDR2_MT_SHIFT 13u
8451 #define MCM_LMDR2_MT_WIDTH 3u
8452 #define MCM_LMDR2_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_MT_SHIFT))&MCM_LMDR2_MT_MASK)
8453 #define MCM_LMDR2_LOCK_MASK 0x10000u
8454 #define MCM_LMDR2_LOCK_SHIFT 16u
8455 #define MCM_LMDR2_LOCK_WIDTH 1u
8456 #define MCM_LMDR2_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LOCK_SHIFT))&MCM_LMDR2_LOCK_MASK)
8457 #define MCM_LMDR2_DPW_MASK 0xE0000u
8458 #define MCM_LMDR2_DPW_SHIFT 17u
8459 #define MCM_LMDR2_DPW_WIDTH 3u
8460 #define MCM_LMDR2_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_DPW_SHIFT))&MCM_LMDR2_DPW_MASK)
8461 #define MCM_LMDR2_WY_MASK 0xF00000u
8462 #define MCM_LMDR2_WY_SHIFT 20u
8463 #define MCM_LMDR2_WY_WIDTH 4u
8464 #define MCM_LMDR2_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_WY_SHIFT))&MCM_LMDR2_WY_MASK)
8465 #define MCM_LMDR2_LMSZ_MASK 0xF000000u
8466 #define MCM_LMDR2_LMSZ_SHIFT 24u
8467 #define MCM_LMDR2_LMSZ_WIDTH 4u
8468 #define MCM_LMDR2_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZ_SHIFT))&MCM_LMDR2_LMSZ_MASK)
8469 #define MCM_LMDR2_LMSZH_MASK 0x10000000u
8470 #define MCM_LMDR2_LMSZH_SHIFT 28u
8471 #define MCM_LMDR2_LMSZH_WIDTH 1u
8472 #define MCM_LMDR2_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZH_SHIFT))&MCM_LMDR2_LMSZH_MASK)
8473 #define MCM_LMDR2_V_MASK 0x80000000u
8474 #define MCM_LMDR2_V_SHIFT 31u
8475 #define MCM_LMDR2_V_WIDTH 1u
8476 #define MCM_LMDR2_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_V_SHIFT))&MCM_LMDR2_V_MASK)
8478 #define MCM_LMPECR_ERNCR_MASK 0x1u
8479 #define MCM_LMPECR_ERNCR_SHIFT 0u
8480 #define MCM_LMPECR_ERNCR_WIDTH 1u
8481 #define MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ERNCR_SHIFT))&MCM_LMPECR_ERNCR_MASK)
8482 #define MCM_LMPECR_ER1BR_MASK 0x100u
8483 #define MCM_LMPECR_ER1BR_SHIFT 8u
8484 #define MCM_LMPECR_ER1BR_WIDTH 1u
8485 #define MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ER1BR_SHIFT))&MCM_LMPECR_ER1BR_MASK)
8486 #define MCM_LMPECR_ECPR_MASK 0x100000u
8487 #define MCM_LMPECR_ECPR_SHIFT 20u
8488 #define MCM_LMPECR_ECPR_WIDTH 1u
8489 #define MCM_LMPECR_ECPR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ECPR_SHIFT))&MCM_LMPECR_ECPR_MASK)
8491 #define MCM_LMPEIR_ENC_MASK 0xFFu
8492 #define MCM_LMPEIR_ENC_SHIFT 0u
8493 #define MCM_LMPEIR_ENC_WIDTH 8u
8494 #define MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_ENC_SHIFT))&MCM_LMPEIR_ENC_MASK)
8495 #define MCM_LMPEIR_E1B_MASK 0xFF00u
8496 #define MCM_LMPEIR_E1B_SHIFT 8u
8497 #define MCM_LMPEIR_E1B_WIDTH 8u
8498 #define MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_E1B_SHIFT))&MCM_LMPEIR_E1B_MASK)
8499 #define MCM_LMPEIR_PE_MASK 0xFF0000u
8500 #define MCM_LMPEIR_PE_SHIFT 16u
8501 #define MCM_LMPEIR_PE_WIDTH 8u
8502 #define MCM_LMPEIR_PE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PE_SHIFT))&MCM_LMPEIR_PE_MASK)
8503 #define MCM_LMPEIR_PEELOC_MASK 0x1F000000u
8504 #define MCM_LMPEIR_PEELOC_SHIFT 24u
8505 #define MCM_LMPEIR_PEELOC_WIDTH 5u
8506 #define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PEELOC_SHIFT))&MCM_LMPEIR_PEELOC_MASK)
8507 #define MCM_LMPEIR_V_MASK 0x80000000u
8508 #define MCM_LMPEIR_V_SHIFT 31u
8509 #define MCM_LMPEIR_V_WIDTH 1u
8510 #define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_V_SHIFT))&MCM_LMPEIR_V_MASK)
8512 #define MCM_LMFAR_EFADD_MASK 0xFFFFFFFFu
8513 #define MCM_LMFAR_EFADD_SHIFT 0u
8514 #define MCM_LMFAR_EFADD_WIDTH 32u
8515 #define MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFAR_EFADD_SHIFT))&MCM_LMFAR_EFADD_MASK)
8517 #define MCM_LMFATR_PEFPRT_MASK 0xFu
8518 #define MCM_LMFATR_PEFPRT_SHIFT 0u
8519 #define MCM_LMFATR_PEFPRT_WIDTH 4u
8520 #define MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFPRT_SHIFT))&MCM_LMFATR_PEFPRT_MASK)
8521 #define MCM_LMFATR_PEFSIZE_MASK 0x70u
8522 #define MCM_LMFATR_PEFSIZE_SHIFT 4u
8523 #define MCM_LMFATR_PEFSIZE_WIDTH 3u
8524 #define MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFSIZE_SHIFT))&MCM_LMFATR_PEFSIZE_MASK)
8525 #define MCM_LMFATR_PEFW_MASK 0x80u
8526 #define MCM_LMFATR_PEFW_SHIFT 7u
8527 #define MCM_LMFATR_PEFW_WIDTH 1u
8528 #define MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFW_SHIFT))&MCM_LMFATR_PEFW_MASK)
8529 #define MCM_LMFATR_PEFMST_MASK 0xFF00u
8530 #define MCM_LMFATR_PEFMST_SHIFT 8u
8531 #define MCM_LMFATR_PEFMST_WIDTH 8u
8532 #define MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFMST_SHIFT))&MCM_LMFATR_PEFMST_MASK)
8533 #define MCM_LMFATR_OVR_MASK 0x80000000u
8534 #define MCM_LMFATR_OVR_SHIFT 31u
8535 #define MCM_LMFATR_OVR_WIDTH 1u
8536 #define MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_OVR_SHIFT))&MCM_LMFATR_OVR_MASK)
8538 #define MCM_LMFDHR_PEFDH_MASK 0xFFFFFFFFu
8539 #define MCM_LMFDHR_PEFDH_SHIFT 0u
8540 #define MCM_LMFDHR_PEFDH_WIDTH 32u
8541 #define MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDHR_PEFDH_SHIFT))&MCM_LMFDHR_PEFDH_MASK)
8543 #define MCM_LMFDLR_PEFDL_MASK 0xFFFFFFFFu
8544 #define MCM_LMFDLR_PEFDL_SHIFT 0u
8545 #define MCM_LMFDLR_PEFDL_WIDTH 32u
8546 #define MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDLR_PEFDL_SHIFT))&MCM_LMFDLR_PEFDL_MASK)
8569 #define MPU_EAR_EDR_COUNT 5u
8570 #define MPU_RGD_COUNT 16u
8571 #define MPU_RGDAAC_COUNT 16u
8576 uint8_t RESERVED_0[12];
8585 uint8_t RESERVED_1[968];
8592 uint8_t RESERVED_2[768];
8599 #define MPU_INSTANCE_COUNT (1u)
8604 #define MPU_BASE (0x4000D000u)
8606 #define MPU ((MPU_Type *)MPU_BASE)
8608 #define MPU_BASE_ADDRS { MPU_BASE }
8610 #define MPU_BASE_PTRS { MPU }
8622 #define MPU_CESR_VLD_MASK 0x1u
8623 #define MPU_CESR_VLD_SHIFT 0u
8624 #define MPU_CESR_VLD_WIDTH 1u
8625 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
8626 #define MPU_CESR_NRGD_MASK 0xF00u
8627 #define MPU_CESR_NRGD_SHIFT 8u
8628 #define MPU_CESR_NRGD_WIDTH 4u
8629 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
8630 #define MPU_CESR_NSP_MASK 0xF000u
8631 #define MPU_CESR_NSP_SHIFT 12u
8632 #define MPU_CESR_NSP_WIDTH 4u
8633 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
8634 #define MPU_CESR_HRL_MASK 0xF0000u
8635 #define MPU_CESR_HRL_SHIFT 16u
8636 #define MPU_CESR_HRL_WIDTH 4u
8637 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
8638 #define MPU_CESR_SPERR4_MASK 0x8000000u
8639 #define MPU_CESR_SPERR4_SHIFT 27u
8640 #define MPU_CESR_SPERR4_WIDTH 1u
8641 #define MPU_CESR_SPERR4(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR4_SHIFT))&MPU_CESR_SPERR4_MASK)
8642 #define MPU_CESR_SPERR3_MASK 0x10000000u
8643 #define MPU_CESR_SPERR3_SHIFT 28u
8644 #define MPU_CESR_SPERR3_WIDTH 1u
8645 #define MPU_CESR_SPERR3(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR3_SHIFT))&MPU_CESR_SPERR3_MASK)
8646 #define MPU_CESR_SPERR2_MASK 0x20000000u
8647 #define MPU_CESR_SPERR2_SHIFT 29u
8648 #define MPU_CESR_SPERR2_WIDTH 1u
8649 #define MPU_CESR_SPERR2(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR2_SHIFT))&MPU_CESR_SPERR2_MASK)
8650 #define MPU_CESR_SPERR1_MASK 0x40000000u
8651 #define MPU_CESR_SPERR1_SHIFT 30u
8652 #define MPU_CESR_SPERR1_WIDTH 1u
8653 #define MPU_CESR_SPERR1(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR1_SHIFT))&MPU_CESR_SPERR1_MASK)
8654 #define MPU_CESR_SPERR0_MASK 0x80000000u
8655 #define MPU_CESR_SPERR0_SHIFT 31u
8656 #define MPU_CESR_SPERR0_WIDTH 1u
8657 #define MPU_CESR_SPERR0(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR0_SHIFT))&MPU_CESR_SPERR0_MASK)
8659 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
8660 #define MPU_EAR_EADDR_SHIFT 0u
8661 #define MPU_EAR_EADDR_WIDTH 32u
8662 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
8664 #define MPU_EDR_ERW_MASK 0x1u
8665 #define MPU_EDR_ERW_SHIFT 0u
8666 #define MPU_EDR_ERW_WIDTH 1u
8667 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
8668 #define MPU_EDR_EATTR_MASK 0xEu
8669 #define MPU_EDR_EATTR_SHIFT 1u
8670 #define MPU_EDR_EATTR_WIDTH 3u
8671 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
8672 #define MPU_EDR_EMN_MASK 0xF0u
8673 #define MPU_EDR_EMN_SHIFT 4u
8674 #define MPU_EDR_EMN_WIDTH 4u
8675 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
8676 #define MPU_EDR_EPID_MASK 0xFF00u
8677 #define MPU_EDR_EPID_SHIFT 8u
8678 #define MPU_EDR_EPID_WIDTH 8u
8679 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
8680 #define MPU_EDR_EACD_MASK 0xFFFF0000u
8681 #define MPU_EDR_EACD_SHIFT 16u
8682 #define MPU_EDR_EACD_WIDTH 16u
8683 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
8685 #define MPU_RGD_WORD0_SRTADDR_MASK 0xFFFFFFE0u
8686 #define MPU_RGD_WORD0_SRTADDR_SHIFT 5u
8687 #define MPU_RGD_WORD0_SRTADDR_WIDTH 27u
8688 #define MPU_RGD_WORD0_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD0_SRTADDR_SHIFT))&MPU_RGD_WORD0_SRTADDR_MASK)
8690 #define MPU_RGD_WORD1_ENDADDR_MASK 0xFFFFFFE0u
8691 #define MPU_RGD_WORD1_ENDADDR_SHIFT 5u
8692 #define MPU_RGD_WORD1_ENDADDR_WIDTH 27u
8693 #define MPU_RGD_WORD1_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD1_ENDADDR_SHIFT))&MPU_RGD_WORD1_ENDADDR_MASK)
8695 #define MPU_RGD_WORD2_M0UM_MASK 0x7u
8696 #define MPU_RGD_WORD2_M0UM_SHIFT 0u
8697 #define MPU_RGD_WORD2_M0UM_WIDTH 3u
8698 #define MPU_RGD_WORD2_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0UM_SHIFT))&MPU_RGD_WORD2_M0UM_MASK)
8699 #define MPU_RGD_WORD2_M0SM_MASK 0x18u
8700 #define MPU_RGD_WORD2_M0SM_SHIFT 3u
8701 #define MPU_RGD_WORD2_M0SM_WIDTH 2u
8702 #define MPU_RGD_WORD2_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0SM_SHIFT))&MPU_RGD_WORD2_M0SM_MASK)
8703 #define MPU_RGD_WORD2_M0PE_MASK 0x20u
8704 #define MPU_RGD_WORD2_M0PE_SHIFT 5u
8705 #define MPU_RGD_WORD2_M0PE_WIDTH 1u
8706 #define MPU_RGD_WORD2_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0PE_SHIFT))&MPU_RGD_WORD2_M0PE_MASK)
8707 #define MPU_RGD_WORD2_M1UM_MASK 0x1C0u
8708 #define MPU_RGD_WORD2_M1UM_SHIFT 6u
8709 #define MPU_RGD_WORD2_M1UM_WIDTH 3u
8710 #define MPU_RGD_WORD2_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1UM_SHIFT))&MPU_RGD_WORD2_M1UM_MASK)
8711 #define MPU_RGD_WORD2_M1SM_MASK 0x600u
8712 #define MPU_RGD_WORD2_M1SM_SHIFT 9u
8713 #define MPU_RGD_WORD2_M1SM_WIDTH 2u
8714 #define MPU_RGD_WORD2_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1SM_SHIFT))&MPU_RGD_WORD2_M1SM_MASK)
8715 #define MPU_RGD_WORD2_M1PE_MASK 0x800u
8716 #define MPU_RGD_WORD2_M1PE_SHIFT 11u
8717 #define MPU_RGD_WORD2_M1PE_WIDTH 1u
8718 #define MPU_RGD_WORD2_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1PE_SHIFT))&MPU_RGD_WORD2_M1PE_MASK)
8719 #define MPU_RGD_WORD2_M2UM_MASK 0x7000u
8720 #define MPU_RGD_WORD2_M2UM_SHIFT 12u
8721 #define MPU_RGD_WORD2_M2UM_WIDTH 3u
8722 #define MPU_RGD_WORD2_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2UM_SHIFT))&MPU_RGD_WORD2_M2UM_MASK)
8723 #define MPU_RGD_WORD2_M2SM_MASK 0x18000u
8724 #define MPU_RGD_WORD2_M2SM_SHIFT 15u
8725 #define MPU_RGD_WORD2_M2SM_WIDTH 2u
8726 #define MPU_RGD_WORD2_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2SM_SHIFT))&MPU_RGD_WORD2_M2SM_MASK)
8727 #define MPU_RGD_WORD2_M3UM_MASK 0x1C0000u
8728 #define MPU_RGD_WORD2_M3UM_SHIFT 18u
8729 #define MPU_RGD_WORD2_M3UM_WIDTH 3u
8730 #define MPU_RGD_WORD2_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3UM_SHIFT))&MPU_RGD_WORD2_M3UM_MASK)
8731 #define MPU_RGD_WORD2_M3SM_MASK 0x600000u
8732 #define MPU_RGD_WORD2_M3SM_SHIFT 21u
8733 #define MPU_RGD_WORD2_M3SM_WIDTH 2u
8734 #define MPU_RGD_WORD2_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3SM_SHIFT))&MPU_RGD_WORD2_M3SM_MASK)
8735 #define MPU_RGD_WORD2_M4WE_MASK 0x1000000u
8736 #define MPU_RGD_WORD2_M4WE_SHIFT 24u
8737 #define MPU_RGD_WORD2_M4WE_WIDTH 1u
8738 #define MPU_RGD_WORD2_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4WE_SHIFT))&MPU_RGD_WORD2_M4WE_MASK)
8739 #define MPU_RGD_WORD2_M4RE_MASK 0x2000000u
8740 #define MPU_RGD_WORD2_M4RE_SHIFT 25u
8741 #define MPU_RGD_WORD2_M4RE_WIDTH 1u
8742 #define MPU_RGD_WORD2_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4RE_SHIFT))&MPU_RGD_WORD2_M4RE_MASK)
8743 #define MPU_RGD_WORD2_M5WE_MASK 0x4000000u
8744 #define MPU_RGD_WORD2_M5WE_SHIFT 26u
8745 #define MPU_RGD_WORD2_M5WE_WIDTH 1u
8746 #define MPU_RGD_WORD2_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5WE_SHIFT))&MPU_RGD_WORD2_M5WE_MASK)
8747 #define MPU_RGD_WORD2_M5RE_MASK 0x8000000u
8748 #define MPU_RGD_WORD2_M5RE_SHIFT 27u
8749 #define MPU_RGD_WORD2_M5RE_WIDTH 1u
8750 #define MPU_RGD_WORD2_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5RE_SHIFT))&MPU_RGD_WORD2_M5RE_MASK)
8751 #define MPU_RGD_WORD2_M6WE_MASK 0x10000000u
8752 #define MPU_RGD_WORD2_M6WE_SHIFT 28u
8753 #define MPU_RGD_WORD2_M6WE_WIDTH 1u
8754 #define MPU_RGD_WORD2_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6WE_SHIFT))&MPU_RGD_WORD2_M6WE_MASK)
8755 #define MPU_RGD_WORD2_M6RE_MASK 0x20000000u
8756 #define MPU_RGD_WORD2_M6RE_SHIFT 29u
8757 #define MPU_RGD_WORD2_M6RE_WIDTH 1u
8758 #define MPU_RGD_WORD2_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6RE_SHIFT))&MPU_RGD_WORD2_M6RE_MASK)
8759 #define MPU_RGD_WORD2_M7WE_MASK 0x40000000u
8760 #define MPU_RGD_WORD2_M7WE_SHIFT 30u
8761 #define MPU_RGD_WORD2_M7WE_WIDTH 1u
8762 #define MPU_RGD_WORD2_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7WE_SHIFT))&MPU_RGD_WORD2_M7WE_MASK)
8763 #define MPU_RGD_WORD2_M7RE_MASK 0x80000000u
8764 #define MPU_RGD_WORD2_M7RE_SHIFT 31u
8765 #define MPU_RGD_WORD2_M7RE_WIDTH 1u
8766 #define MPU_RGD_WORD2_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7RE_SHIFT))&MPU_RGD_WORD2_M7RE_MASK)
8768 #define MPU_RGD_WORD3_VLD_MASK 0x1u
8769 #define MPU_RGD_WORD3_VLD_SHIFT 0u
8770 #define MPU_RGD_WORD3_VLD_WIDTH 1u
8771 #define MPU_RGD_WORD3_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_VLD_SHIFT))&MPU_RGD_WORD3_VLD_MASK)
8772 #define MPU_RGD_WORD3_PIDMASK_MASK 0xFF0000u
8773 #define MPU_RGD_WORD3_PIDMASK_SHIFT 16u
8774 #define MPU_RGD_WORD3_PIDMASK_WIDTH 8u
8775 #define MPU_RGD_WORD3_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PIDMASK_SHIFT))&MPU_RGD_WORD3_PIDMASK_MASK)
8776 #define MPU_RGD_WORD3_PID_MASK 0xFF000000u
8777 #define MPU_RGD_WORD3_PID_SHIFT 24u
8778 #define MPU_RGD_WORD3_PID_WIDTH 8u
8779 #define MPU_RGD_WORD3_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PID_SHIFT))&MPU_RGD_WORD3_PID_MASK)
8781 #define MPU_RGDAAC_M0UM_MASK 0x7u
8782 #define MPU_RGDAAC_M0UM_SHIFT 0u
8783 #define MPU_RGDAAC_M0UM_WIDTH 3u
8784 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
8785 #define MPU_RGDAAC_M0SM_MASK 0x18u
8786 #define MPU_RGDAAC_M0SM_SHIFT 3u
8787 #define MPU_RGDAAC_M0SM_WIDTH 2u
8788 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
8789 #define MPU_RGDAAC_M0PE_MASK 0x20u
8790 #define MPU_RGDAAC_M0PE_SHIFT 5u
8791 #define MPU_RGDAAC_M0PE_WIDTH 1u
8792 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
8793 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
8794 #define MPU_RGDAAC_M1UM_SHIFT 6u
8795 #define MPU_RGDAAC_M1UM_WIDTH 3u
8796 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
8797 #define MPU_RGDAAC_M1SM_MASK 0x600u
8798 #define MPU_RGDAAC_M1SM_SHIFT 9u
8799 #define MPU_RGDAAC_M1SM_WIDTH 2u
8800 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
8801 #define MPU_RGDAAC_M1PE_MASK 0x800u
8802 #define MPU_RGDAAC_M1PE_SHIFT 11u
8803 #define MPU_RGDAAC_M1PE_WIDTH 1u
8804 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
8805 #define MPU_RGDAAC_M2UM_MASK 0x7000u
8806 #define MPU_RGDAAC_M2UM_SHIFT 12u
8807 #define MPU_RGDAAC_M2UM_WIDTH 3u
8808 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
8809 #define MPU_RGDAAC_M2SM_MASK 0x18000u
8810 #define MPU_RGDAAC_M2SM_SHIFT 15u
8811 #define MPU_RGDAAC_M2SM_WIDTH 2u
8812 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
8813 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
8814 #define MPU_RGDAAC_M3UM_SHIFT 18u
8815 #define MPU_RGDAAC_M3UM_WIDTH 3u
8816 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
8817 #define MPU_RGDAAC_M3SM_MASK 0x600000u
8818 #define MPU_RGDAAC_M3SM_SHIFT 21u
8819 #define MPU_RGDAAC_M3SM_WIDTH 2u
8820 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
8821 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
8822 #define MPU_RGDAAC_M4WE_SHIFT 24u
8823 #define MPU_RGDAAC_M4WE_WIDTH 1u
8824 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
8825 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
8826 #define MPU_RGDAAC_M4RE_SHIFT 25u
8827 #define MPU_RGDAAC_M4RE_WIDTH 1u
8828 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
8829 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
8830 #define MPU_RGDAAC_M5WE_SHIFT 26u
8831 #define MPU_RGDAAC_M5WE_WIDTH 1u
8832 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
8833 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
8834 #define MPU_RGDAAC_M5RE_SHIFT 27u
8835 #define MPU_RGDAAC_M5RE_WIDTH 1u
8836 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
8837 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
8838 #define MPU_RGDAAC_M6WE_SHIFT 28u
8839 #define MPU_RGDAAC_M6WE_WIDTH 1u
8840 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
8841 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
8842 #define MPU_RGDAAC_M6RE_SHIFT 29u
8843 #define MPU_RGDAAC_M6RE_WIDTH 1u
8844 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
8845 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
8846 #define MPU_RGDAAC_M7WE_SHIFT 30u
8847 #define MPU_RGDAAC_M7WE_WIDTH 1u
8848 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
8849 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
8850 #define MPU_RGDAAC_M7RE_SHIFT 31u
8851 #define MPU_RGDAAC_M7RE_WIDTH 1u
8852 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
8875 #define MSCM_OCMDR_COUNT 4u
8895 uint8_t RESERVED_0[960];
8900 #define MSCM_INSTANCE_COUNT (1u)
8905 #define MSCM_BASE (0x40001000u)
8907 #define MSCM ((MSCM_Type *)MSCM_BASE)
8909 #define MSCM_BASE_ADDRS { MSCM_BASE }
8911 #define MSCM_BASE_PTRS { MSCM }
8923 #define MSCM_CPxTYPE_RYPZ_MASK 0xFFu
8924 #define MSCM_CPxTYPE_RYPZ_SHIFT 0u
8925 #define MSCM_CPxTYPE_RYPZ_WIDTH 8u
8926 #define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_RYPZ_SHIFT))&MSCM_CPxTYPE_RYPZ_MASK)
8927 #define MSCM_CPxTYPE_PERSONALITY_MASK 0xFFFFFF00u
8928 #define MSCM_CPxTYPE_PERSONALITY_SHIFT 8u
8929 #define MSCM_CPxTYPE_PERSONALITY_WIDTH 24u
8930 #define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_PERSONALITY_SHIFT))&MSCM_CPxTYPE_PERSONALITY_MASK)
8932 #define MSCM_CPxNUM_CPN_MASK 0x1u
8933 #define MSCM_CPxNUM_CPN_SHIFT 0u
8934 #define MSCM_CPxNUM_CPN_WIDTH 1u
8935 #define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxNUM_CPN_SHIFT))&MSCM_CPxNUM_CPN_MASK)
8937 #define MSCM_CPxMASTER_PPMN_MASK 0x3Fu
8938 #define MSCM_CPxMASTER_PPMN_SHIFT 0u
8939 #define MSCM_CPxMASTER_PPMN_WIDTH 6u
8940 #define MSCM_CPxMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxMASTER_PPMN_SHIFT))&MSCM_CPxMASTER_PPMN_MASK)
8942 #define MSCM_CPxCOUNT_PCNT_MASK 0x3u
8943 #define MSCM_CPxCOUNT_PCNT_SHIFT 0u
8944 #define MSCM_CPxCOUNT_PCNT_WIDTH 2u
8945 #define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCOUNT_PCNT_SHIFT))&MSCM_CPxCOUNT_PCNT_MASK)
8947 #define MSCM_CPxCFG0_DCWY_MASK 0xFFu
8948 #define MSCM_CPxCFG0_DCWY_SHIFT 0u
8949 #define MSCM_CPxCFG0_DCWY_WIDTH 8u
8950 #define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCWY_SHIFT))&MSCM_CPxCFG0_DCWY_MASK)
8951 #define MSCM_CPxCFG0_DCSZ_MASK 0xFF00u
8952 #define MSCM_CPxCFG0_DCSZ_SHIFT 8u
8953 #define MSCM_CPxCFG0_DCSZ_WIDTH 8u
8954 #define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCSZ_SHIFT))&MSCM_CPxCFG0_DCSZ_MASK)
8955 #define MSCM_CPxCFG0_ICWY_MASK 0xFF0000u
8956 #define MSCM_CPxCFG0_ICWY_SHIFT 16u
8957 #define MSCM_CPxCFG0_ICWY_WIDTH 8u
8958 #define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICWY_SHIFT))&MSCM_CPxCFG0_ICWY_MASK)
8959 #define MSCM_CPxCFG0_ICSZ_MASK 0xFF000000u
8960 #define MSCM_CPxCFG0_ICSZ_SHIFT 24u
8961 #define MSCM_CPxCFG0_ICSZ_WIDTH 8u
8962 #define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICSZ_SHIFT))&MSCM_CPxCFG0_ICSZ_MASK)
8964 #define MSCM_CPxCFG1_L2WY_MASK 0xFF0000u
8965 #define MSCM_CPxCFG1_L2WY_SHIFT 16u
8966 #define MSCM_CPxCFG1_L2WY_WIDTH 8u
8967 #define MSCM_CPxCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2WY_SHIFT))&MSCM_CPxCFG1_L2WY_MASK)
8968 #define MSCM_CPxCFG1_L2SZ_MASK 0xFF000000u
8969 #define MSCM_CPxCFG1_L2SZ_SHIFT 24u
8970 #define MSCM_CPxCFG1_L2SZ_WIDTH 8u
8971 #define MSCM_CPxCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2SZ_SHIFT))&MSCM_CPxCFG1_L2SZ_MASK)
8973 #define MSCM_CPxCFG2_TMUSZ_MASK 0xFF00u
8974 #define MSCM_CPxCFG2_TMUSZ_SHIFT 8u
8975 #define MSCM_CPxCFG2_TMUSZ_WIDTH 8u
8976 #define MSCM_CPxCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMUSZ_SHIFT))&MSCM_CPxCFG2_TMUSZ_MASK)
8977 #define MSCM_CPxCFG2_TMLSZ_MASK 0xFF000000u
8978 #define MSCM_CPxCFG2_TMLSZ_SHIFT 24u
8979 #define MSCM_CPxCFG2_TMLSZ_WIDTH 8u
8980 #define MSCM_CPxCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMLSZ_SHIFT))&MSCM_CPxCFG2_TMLSZ_MASK)
8982 #define MSCM_CPxCFG3_FPU_MASK 0x1u
8983 #define MSCM_CPxCFG3_FPU_SHIFT 0u
8984 #define MSCM_CPxCFG3_FPU_WIDTH 1u
8985 #define MSCM_CPxCFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_FPU_SHIFT))&MSCM_CPxCFG3_FPU_MASK)
8986 #define MSCM_CPxCFG3_SIMD_MASK 0x2u
8987 #define MSCM_CPxCFG3_SIMD_SHIFT 1u
8988 #define MSCM_CPxCFG3_SIMD_WIDTH 1u
8989 #define MSCM_CPxCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SIMD_SHIFT))&MSCM_CPxCFG3_SIMD_MASK)
8990 #define MSCM_CPxCFG3_JAZ_MASK 0x4u
8991 #define MSCM_CPxCFG3_JAZ_SHIFT 2u
8992 #define MSCM_CPxCFG3_JAZ_WIDTH 1u
8993 #define MSCM_CPxCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_JAZ_SHIFT))&MSCM_CPxCFG3_JAZ_MASK)
8994 #define MSCM_CPxCFG3_MMU_MASK 0x8u
8995 #define MSCM_CPxCFG3_MMU_SHIFT 3u
8996 #define MSCM_CPxCFG3_MMU_WIDTH 1u
8997 #define MSCM_CPxCFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_MMU_SHIFT))&MSCM_CPxCFG3_MMU_MASK)
8998 #define MSCM_CPxCFG3_TZ_MASK 0x10u
8999 #define MSCM_CPxCFG3_TZ_SHIFT 4u
9000 #define MSCM_CPxCFG3_TZ_WIDTH 1u
9001 #define MSCM_CPxCFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_TZ_SHIFT))&MSCM_CPxCFG3_TZ_MASK)
9002 #define MSCM_CPxCFG3_CMP_MASK 0x20u
9003 #define MSCM_CPxCFG3_CMP_SHIFT 5u
9004 #define MSCM_CPxCFG3_CMP_WIDTH 1u
9005 #define MSCM_CPxCFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_CMP_SHIFT))&MSCM_CPxCFG3_CMP_MASK)
9006 #define MSCM_CPxCFG3_BB_MASK 0x40u
9007 #define MSCM_CPxCFG3_BB_SHIFT 6u
9008 #define MSCM_CPxCFG3_BB_WIDTH 1u
9009 #define MSCM_CPxCFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_BB_SHIFT))&MSCM_CPxCFG3_BB_MASK)
9010 #define MSCM_CPxCFG3_SBP_MASK 0x300u
9011 #define MSCM_CPxCFG3_SBP_SHIFT 8u
9012 #define MSCM_CPxCFG3_SBP_WIDTH 2u
9013 #define MSCM_CPxCFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SBP_SHIFT))&MSCM_CPxCFG3_SBP_MASK)
9015 #define MSCM_CP0TYPE_RYPZ_MASK 0xFFu
9016 #define MSCM_CP0TYPE_RYPZ_SHIFT 0u
9017 #define MSCM_CP0TYPE_RYPZ_WIDTH 8u
9018 #define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_RYPZ_SHIFT))&MSCM_CP0TYPE_RYPZ_MASK)
9019 #define MSCM_CP0TYPE_PERSONALITY_MASK 0xFFFFFF00u
9020 #define MSCM_CP0TYPE_PERSONALITY_SHIFT 8u
9021 #define MSCM_CP0TYPE_PERSONALITY_WIDTH 24u
9022 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_PERSONALITY_SHIFT))&MSCM_CP0TYPE_PERSONALITY_MASK)
9024 #define MSCM_CP0NUM_CPN_MASK 0x1u
9025 #define MSCM_CP0NUM_CPN_SHIFT 0u
9026 #define MSCM_CP0NUM_CPN_WIDTH 1u
9027 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0NUM_CPN_SHIFT))&MSCM_CP0NUM_CPN_MASK)
9029 #define MSCM_CP0MASTER_PPMN_MASK 0x3Fu
9030 #define MSCM_CP0MASTER_PPMN_SHIFT 0u
9031 #define MSCM_CP0MASTER_PPMN_WIDTH 6u
9032 #define MSCM_CP0MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0MASTER_PPMN_SHIFT))&MSCM_CP0MASTER_PPMN_MASK)
9034 #define MSCM_CP0COUNT_PCNT_MASK 0x3u
9035 #define MSCM_CP0COUNT_PCNT_SHIFT 0u
9036 #define MSCM_CP0COUNT_PCNT_WIDTH 2u
9037 #define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0COUNT_PCNT_SHIFT))&MSCM_CP0COUNT_PCNT_MASK)
9039 #define MSCM_CP0CFG0_DCWY_MASK 0xFFu
9040 #define MSCM_CP0CFG0_DCWY_SHIFT 0u
9041 #define MSCM_CP0CFG0_DCWY_WIDTH 8u
9042 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCWY_SHIFT))&MSCM_CP0CFG0_DCWY_MASK)
9043 #define MSCM_CP0CFG0_DCSZ_MASK 0xFF00u
9044 #define MSCM_CP0CFG0_DCSZ_SHIFT 8u
9045 #define MSCM_CP0CFG0_DCSZ_WIDTH 8u
9046 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCSZ_SHIFT))&MSCM_CP0CFG0_DCSZ_MASK)
9047 #define MSCM_CP0CFG0_ICWY_MASK 0xFF0000u
9048 #define MSCM_CP0CFG0_ICWY_SHIFT 16u
9049 #define MSCM_CP0CFG0_ICWY_WIDTH 8u
9050 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICWY_SHIFT))&MSCM_CP0CFG0_ICWY_MASK)
9051 #define MSCM_CP0CFG0_ICSZ_MASK 0xFF000000u
9052 #define MSCM_CP0CFG0_ICSZ_SHIFT 24u
9053 #define MSCM_CP0CFG0_ICSZ_WIDTH 8u
9054 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICSZ_SHIFT))&MSCM_CP0CFG0_ICSZ_MASK)
9056 #define MSCM_CP0CFG1_L2WY_MASK 0xFF0000u
9057 #define MSCM_CP0CFG1_L2WY_SHIFT 16u
9058 #define MSCM_CP0CFG1_L2WY_WIDTH 8u
9059 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2WY_SHIFT))&MSCM_CP0CFG1_L2WY_MASK)
9060 #define MSCM_CP0CFG1_L2SZ_MASK 0xFF000000u
9061 #define MSCM_CP0CFG1_L2SZ_SHIFT 24u
9062 #define MSCM_CP0CFG1_L2SZ_WIDTH 8u
9063 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2SZ_SHIFT))&MSCM_CP0CFG1_L2SZ_MASK)
9065 #define MSCM_CP0CFG2_TMUSZ_MASK 0xFF00u
9066 #define MSCM_CP0CFG2_TMUSZ_SHIFT 8u
9067 #define MSCM_CP0CFG2_TMUSZ_WIDTH 8u
9068 #define MSCM_CP0CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMUSZ_SHIFT))&MSCM_CP0CFG2_TMUSZ_MASK)
9069 #define MSCM_CP0CFG2_TMLSZ_MASK 0xFF000000u
9070 #define MSCM_CP0CFG2_TMLSZ_SHIFT 24u
9071 #define MSCM_CP0CFG2_TMLSZ_WIDTH 8u
9072 #define MSCM_CP0CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMLSZ_SHIFT))&MSCM_CP0CFG2_TMLSZ_MASK)
9074 #define MSCM_CP0CFG3_FPU_MASK 0x1u
9075 #define MSCM_CP0CFG3_FPU_SHIFT 0u
9076 #define MSCM_CP0CFG3_FPU_WIDTH 1u
9077 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_FPU_SHIFT))&MSCM_CP0CFG3_FPU_MASK)
9078 #define MSCM_CP0CFG3_SIMD_MASK 0x2u
9079 #define MSCM_CP0CFG3_SIMD_SHIFT 1u
9080 #define MSCM_CP0CFG3_SIMD_WIDTH 1u
9081 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SIMD_SHIFT))&MSCM_CP0CFG3_SIMD_MASK)
9082 #define MSCM_CP0CFG3_JAZ_MASK 0x4u
9083 #define MSCM_CP0CFG3_JAZ_SHIFT 2u
9084 #define MSCM_CP0CFG3_JAZ_WIDTH 1u
9085 #define MSCM_CP0CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_JAZ_SHIFT))&MSCM_CP0CFG3_JAZ_MASK)
9086 #define MSCM_CP0CFG3_MMU_MASK 0x8u
9087 #define MSCM_CP0CFG3_MMU_SHIFT 3u
9088 #define MSCM_CP0CFG3_MMU_WIDTH 1u
9089 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_MMU_SHIFT))&MSCM_CP0CFG3_MMU_MASK)
9090 #define MSCM_CP0CFG3_TZ_MASK 0x10u
9091 #define MSCM_CP0CFG3_TZ_SHIFT 4u
9092 #define MSCM_CP0CFG3_TZ_WIDTH 1u
9093 #define MSCM_CP0CFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_TZ_SHIFT))&MSCM_CP0CFG3_TZ_MASK)
9094 #define MSCM_CP0CFG3_CMP_MASK 0x20u
9095 #define MSCM_CP0CFG3_CMP_SHIFT 5u
9096 #define MSCM_CP0CFG3_CMP_WIDTH 1u
9097 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_CMP_SHIFT))&MSCM_CP0CFG3_CMP_MASK)
9098 #define MSCM_CP0CFG3_BB_MASK 0x40u
9099 #define MSCM_CP0CFG3_BB_SHIFT 6u
9100 #define MSCM_CP0CFG3_BB_WIDTH 1u
9101 #define MSCM_CP0CFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_BB_SHIFT))&MSCM_CP0CFG3_BB_MASK)
9102 #define MSCM_CP0CFG3_SBP_MASK 0x300u
9103 #define MSCM_CP0CFG3_SBP_SHIFT 8u
9104 #define MSCM_CP0CFG3_SBP_WIDTH 2u
9105 #define MSCM_CP0CFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SBP_SHIFT))&MSCM_CP0CFG3_SBP_MASK)
9107 #define MSCM_OCMDR_OCM0_MASK 0xFu
9108 #define MSCM_OCMDR_OCM0_SHIFT 0u
9109 #define MSCM_OCMDR_OCM0_WIDTH 4u
9110 #define MSCM_OCMDR_OCM0(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM0_SHIFT))&MSCM_OCMDR_OCM0_MASK)
9111 #define MSCM_OCMDR_OCM1_MASK 0xF0u
9112 #define MSCM_OCMDR_OCM1_SHIFT 4u
9113 #define MSCM_OCMDR_OCM1_WIDTH 4u
9114 #define MSCM_OCMDR_OCM1(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM1_SHIFT))&MSCM_OCMDR_OCM1_MASK)
9115 #define MSCM_OCMDR_OCM2_MASK 0xF00u
9116 #define MSCM_OCMDR_OCM2_SHIFT 8u
9117 #define MSCM_OCMDR_OCM2_WIDTH 4u
9118 #define MSCM_OCMDR_OCM2(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM2_SHIFT))&MSCM_OCMDR_OCM2_MASK)
9119 #define MSCM_OCMDR_OCMPU_MASK 0x1000u
9120 #define MSCM_OCMDR_OCMPU_SHIFT 12u
9121 #define MSCM_OCMDR_OCMPU_WIDTH 1u
9122 #define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMPU_SHIFT))&MSCM_OCMDR_OCMPU_MASK)
9123 #define MSCM_OCMDR_OCMT_MASK 0xE000u
9124 #define MSCM_OCMDR_OCMT_SHIFT 13u
9125 #define MSCM_OCMDR_OCMT_WIDTH 3u
9126 #define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMT_SHIFT))&MSCM_OCMDR_OCMT_MASK)
9127 #define MSCM_OCMDR_RO_MASK 0x10000u
9128 #define MSCM_OCMDR_RO_SHIFT 16u
9129 #define MSCM_OCMDR_RO_WIDTH 1u
9130 #define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_RO_SHIFT))&MSCM_OCMDR_RO_MASK)
9131 #define MSCM_OCMDR_OCMW_MASK 0xE0000u
9132 #define MSCM_OCMDR_OCMW_SHIFT 17u
9133 #define MSCM_OCMDR_OCMW_WIDTH 3u
9134 #define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMW_SHIFT))&MSCM_OCMDR_OCMW_MASK)
9135 #define MSCM_OCMDR_OCMSZ_MASK 0xF000000u
9136 #define MSCM_OCMDR_OCMSZ_SHIFT 24u
9137 #define MSCM_OCMDR_OCMSZ_WIDTH 4u
9138 #define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZ_SHIFT))&MSCM_OCMDR_OCMSZ_MASK)
9139 #define MSCM_OCMDR_OCMSZH_MASK 0x10000000u
9140 #define MSCM_OCMDR_OCMSZH_SHIFT 28u
9141 #define MSCM_OCMDR_OCMSZH_WIDTH 1u
9142 #define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZH_SHIFT))&MSCM_OCMDR_OCMSZH_MASK)
9143 #define MSCM_OCMDR_V_MASK 0x80000000u
9144 #define MSCM_OCMDR_V_SHIFT 31u
9145 #define MSCM_OCMDR_V_WIDTH 1u
9146 #define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_V_SHIFT))&MSCM_OCMDR_V_MASK)
9169 #define PCC_PCCn_COUNT 122u
9177 #define PCC_INSTANCE_COUNT (1u)
9182 #define PCC_BASE (0x40065000u)
9184 #define PCC ((PCC_Type *)PCC_BASE)
9186 #define PCC_BASE_ADDRS { PCC_BASE }
9188 #define PCC_BASE_PTRS { PCC }
9191 #define PCC_FTFC_INDEX 32
9192 #define PCC_DMAMUX_INDEX 33
9193 #define PCC_FlexCAN0_INDEX 36
9194 #define PCC_FlexCAN1_INDEX 37
9195 #define PCC_FTM3_INDEX 38
9196 #define PCC_ADC1_INDEX 39
9197 #define PCC_FlexCAN2_INDEX 43
9198 #define PCC_LPSPI0_INDEX 44
9199 #define PCC_LPSPI1_INDEX 45
9200 #define PCC_LPSPI2_INDEX 46
9201 #define PCC_PDB1_INDEX 49
9202 #define PCC_CRC_INDEX 50
9203 #define PCC_PDB0_INDEX 54
9204 #define PCC_LPIT_INDEX 55
9205 #define PCC_FTM0_INDEX 56
9206 #define PCC_FTM1_INDEX 57
9207 #define PCC_FTM2_INDEX 58
9208 #define PCC_ADC0_INDEX 59
9209 #define PCC_RTC_INDEX 61
9210 #define PCC_LPTMR0_INDEX 64
9211 #define PCC_PORTA_INDEX 73
9212 #define PCC_PORTB_INDEX 74
9213 #define PCC_PORTC_INDEX 75
9214 #define PCC_PORTD_INDEX 76
9215 #define PCC_PORTE_INDEX 77
9216 #define PCC_SAI0_INDEX 84
9217 #define PCC_SAI1_INDEX 85
9218 #define PCC_FlexIO_INDEX 90
9219 #define PCC_EWM_INDEX 97
9220 #define PCC_LPI2C0_INDEX 102
9221 #define PCC_LPI2C1_INDEX 103
9222 #define PCC_LPUART0_INDEX 106
9223 #define PCC_LPUART1_INDEX 107
9224 #define PCC_LPUART2_INDEX 108
9225 #define PCC_FTM4_INDEX 110
9226 #define PCC_FTM5_INDEX 111
9227 #define PCC_FTM6_INDEX 112
9228 #define PCC_FTM7_INDEX 113
9229 #define PCC_CMP0_INDEX 115
9230 #define PCC_QSPI_INDEX 118
9231 #define PCC_ENET_INDEX 121
9243 #define PCC_PCCn_PCD_MASK 0x7u
9244 #define PCC_PCCn_PCD_SHIFT 0u
9245 #define PCC_PCCn_PCD_WIDTH 3u
9246 #define PCC_PCCn_PCD(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCD_SHIFT))&PCC_PCCn_PCD_MASK)
9247 #define PCC_PCCn_FRAC_MASK 0x8u
9248 #define PCC_PCCn_FRAC_SHIFT 3u
9249 #define PCC_PCCn_FRAC_WIDTH 1u
9250 #define PCC_PCCn_FRAC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_FRAC_SHIFT))&PCC_PCCn_FRAC_MASK)
9251 #define PCC_PCCn_PCS_MASK 0x7000000u
9252 #define PCC_PCCn_PCS_SHIFT 24u
9253 #define PCC_PCCn_PCS_WIDTH 3u
9254 #define PCC_PCCn_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCS_SHIFT))&PCC_PCCn_PCS_MASK)
9255 #define PCC_PCCn_CGC_MASK 0x40000000u
9256 #define PCC_PCCn_CGC_SHIFT 30u
9257 #define PCC_PCCn_CGC_WIDTH 1u
9258 #define PCC_PCCn_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_CGC_SHIFT))&PCC_PCCn_CGC_MASK)
9259 #define PCC_PCCn_PR_MASK 0x80000000u
9260 #define PCC_PCCn_PR_SHIFT 31u
9261 #define PCC_PCCn_PR_WIDTH 1u
9262 #define PCC_PCCn_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PR_SHIFT))&PCC_PCCn_PR_MASK)
9285 #define PDB_CH_COUNT 4u
9286 #define PDB_DLY_COUNT 8u
9287 #define PDB_POnDLY_COUNT 1u
9300 uint8_t RESERVED_0[224];
9312 #define PDB_INSTANCE_COUNT (2u)
9317 #define PDB0_BASE (0x40036000u)
9319 #define PDB0 ((PDB_Type *)PDB0_BASE)
9321 #define PDB1_BASE (0x40031000u)
9323 #define PDB1 ((PDB_Type *)PDB1_BASE)
9325 #define PDB_BASE_ADDRS { PDB0_BASE, PDB1_BASE }
9327 #define PDB_BASE_PTRS { PDB0, PDB1 }
9329 #define PDB_IRQS_ARR_COUNT (1u)
9331 #define PDB_IRQS_CH_COUNT (1u)
9333 #define PDB_IRQS { PDB0_IRQn, PDB1_IRQn }
9345 #define PDB_SC_LDOK_MASK 0x1u
9346 #define PDB_SC_LDOK_SHIFT 0u
9347 #define PDB_SC_LDOK_WIDTH 1u
9348 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
9349 #define PDB_SC_CONT_MASK 0x2u
9350 #define PDB_SC_CONT_SHIFT 1u
9351 #define PDB_SC_CONT_WIDTH 1u
9352 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
9353 #define PDB_SC_MULT_MASK 0xCu
9354 #define PDB_SC_MULT_SHIFT 2u
9355 #define PDB_SC_MULT_WIDTH 2u
9356 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
9357 #define PDB_SC_PDBIE_MASK 0x20u
9358 #define PDB_SC_PDBIE_SHIFT 5u
9359 #define PDB_SC_PDBIE_WIDTH 1u
9360 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
9361 #define PDB_SC_PDBIF_MASK 0x40u
9362 #define PDB_SC_PDBIF_SHIFT 6u
9363 #define PDB_SC_PDBIF_WIDTH 1u
9364 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
9365 #define PDB_SC_PDBEN_MASK 0x80u
9366 #define PDB_SC_PDBEN_SHIFT 7u
9367 #define PDB_SC_PDBEN_WIDTH 1u
9368 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
9369 #define PDB_SC_TRGSEL_MASK 0xF00u
9370 #define PDB_SC_TRGSEL_SHIFT 8u
9371 #define PDB_SC_TRGSEL_WIDTH 4u
9372 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
9373 #define PDB_SC_PRESCALER_MASK 0x7000u
9374 #define PDB_SC_PRESCALER_SHIFT 12u
9375 #define PDB_SC_PRESCALER_WIDTH 3u
9376 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
9377 #define PDB_SC_DMAEN_MASK 0x8000u
9378 #define PDB_SC_DMAEN_SHIFT 15u
9379 #define PDB_SC_DMAEN_WIDTH 1u
9380 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
9381 #define PDB_SC_SWTRIG_MASK 0x10000u
9382 #define PDB_SC_SWTRIG_SHIFT 16u
9383 #define PDB_SC_SWTRIG_WIDTH 1u
9384 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
9385 #define PDB_SC_PDBEIE_MASK 0x20000u
9386 #define PDB_SC_PDBEIE_SHIFT 17u
9387 #define PDB_SC_PDBEIE_WIDTH 1u
9388 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
9389 #define PDB_SC_LDMOD_MASK 0xC0000u
9390 #define PDB_SC_LDMOD_SHIFT 18u
9391 #define PDB_SC_LDMOD_WIDTH 2u
9392 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
9394 #define PDB_MOD_MOD_MASK 0xFFFFu
9395 #define PDB_MOD_MOD_SHIFT 0u
9396 #define PDB_MOD_MOD_WIDTH 16u
9397 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
9399 #define PDB_CNT_CNT_MASK 0xFFFFu
9400 #define PDB_CNT_CNT_SHIFT 0u
9401 #define PDB_CNT_CNT_WIDTH 16u
9402 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
9404 #define PDB_IDLY_IDLY_MASK 0xFFFFu
9405 #define PDB_IDLY_IDLY_SHIFT 0u
9406 #define PDB_IDLY_IDLY_WIDTH 16u
9407 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
9409 #define PDB_C1_EN_MASK 0xFFu
9410 #define PDB_C1_EN_SHIFT 0u
9411 #define PDB_C1_EN_WIDTH 8u
9412 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
9413 #define PDB_C1_TOS_MASK 0xFF00u
9414 #define PDB_C1_TOS_SHIFT 8u
9415 #define PDB_C1_TOS_WIDTH 8u
9416 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
9417 #define PDB_C1_BB_MASK 0xFF0000u
9418 #define PDB_C1_BB_SHIFT 16u
9419 #define PDB_C1_BB_WIDTH 8u
9420 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
9422 #define PDB_S_ERR_MASK 0xFFu
9423 #define PDB_S_ERR_SHIFT 0u
9424 #define PDB_S_ERR_WIDTH 8u
9425 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
9426 #define PDB_S_CF_MASK 0xFF0000u
9427 #define PDB_S_CF_SHIFT 16u
9428 #define PDB_S_CF_WIDTH 8u
9429 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
9431 #define PDB_DLY_DLY_MASK 0xFFFFu
9432 #define PDB_DLY_DLY_SHIFT 0u
9433 #define PDB_DLY_DLY_WIDTH 16u
9434 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
9436 #define PDB_POEN_POEN_MASK 0xFFu
9437 #define PDB_POEN_POEN_SHIFT 0u
9438 #define PDB_POEN_POEN_WIDTH 8u
9439 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
9441 #define PDB_POnDLY_PODLY_DLY2_MASK 0xFFFFu
9442 #define PDB_POnDLY_PODLY_DLY2_SHIFT 0u
9443 #define PDB_POnDLY_PODLY_DLY2_WIDTH 16u
9444 #define PDB_POnDLY_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY2_SHIFT))&PDB_POnDLY_PODLY_DLY2_MASK)
9445 #define PDB_POnDLY_PODLY_DLY1_MASK 0xFFFF0000u
9446 #define PDB_POnDLY_PODLY_DLY1_SHIFT 16u
9447 #define PDB_POnDLY_PODLY_DLY1_WIDTH 16u
9448 #define PDB_POnDLY_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY1_SHIFT))&PDB_POnDLY_PODLY_DLY1_MASK)
9450 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK 0xFFFFu
9451 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT 0u
9452 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_WIDTH 16u
9453 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK)
9455 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK 0xFFFFu
9456 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT 0u
9457 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_WIDTH 16u
9458 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK)
9487 uint8_t RESERVED_0[1];
9492 #define PMC_INSTANCE_COUNT (1u)
9497 #define PMC_BASE (0x4007D000u)
9499 #define PMC ((PMC_Type *)PMC_BASE)
9501 #define PMC_BASE_ADDRS { PMC_BASE }
9503 #define PMC_BASE_PTRS { PMC }
9505 #define PMC_IRQS_ARR_COUNT (1u)
9507 #define PMC_IRQS_CH_COUNT (1u)
9509 #define PMC_IRQS { LVD_LVW_IRQn }
9521 #define PMC_LVDSC1_LVDRE_MASK 0x10u
9522 #define PMC_LVDSC1_LVDRE_SHIFT 4u
9523 #define PMC_LVDSC1_LVDRE_WIDTH 1u
9524 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
9525 #define PMC_LVDSC1_LVDIE_MASK 0x20u
9526 #define PMC_LVDSC1_LVDIE_SHIFT 5u
9527 #define PMC_LVDSC1_LVDIE_WIDTH 1u
9528 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
9529 #define PMC_LVDSC1_LVDACK_MASK 0x40u
9530 #define PMC_LVDSC1_LVDACK_SHIFT 6u
9531 #define PMC_LVDSC1_LVDACK_WIDTH 1u
9532 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
9533 #define PMC_LVDSC1_LVDF_MASK 0x80u
9534 #define PMC_LVDSC1_LVDF_SHIFT 7u
9535 #define PMC_LVDSC1_LVDF_WIDTH 1u
9536 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
9538 #define PMC_LVDSC2_LVWIE_MASK 0x20u
9539 #define PMC_LVDSC2_LVWIE_SHIFT 5u
9540 #define PMC_LVDSC2_LVWIE_WIDTH 1u
9541 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
9542 #define PMC_LVDSC2_LVWACK_MASK 0x40u
9543 #define PMC_LVDSC2_LVWACK_SHIFT 6u
9544 #define PMC_LVDSC2_LVWACK_WIDTH 1u
9545 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
9546 #define PMC_LVDSC2_LVWF_MASK 0x80u
9547 #define PMC_LVDSC2_LVWF_SHIFT 7u
9548 #define PMC_LVDSC2_LVWF_WIDTH 1u
9549 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
9551 #define PMC_REGSC_BIASEN_MASK 0x1u
9552 #define PMC_REGSC_BIASEN_SHIFT 0u
9553 #define PMC_REGSC_BIASEN_WIDTH 1u
9554 #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BIASEN_SHIFT))&PMC_REGSC_BIASEN_MASK)
9555 #define PMC_REGSC_CLKBIASDIS_MASK 0x2u
9556 #define PMC_REGSC_CLKBIASDIS_SHIFT 1u
9557 #define PMC_REGSC_CLKBIASDIS_WIDTH 1u
9558 #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_CLKBIASDIS_SHIFT))&PMC_REGSC_CLKBIASDIS_MASK)
9559 #define PMC_REGSC_REGFPM_MASK 0x4u
9560 #define PMC_REGSC_REGFPM_SHIFT 2u
9561 #define PMC_REGSC_REGFPM_WIDTH 1u
9562 #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGFPM_SHIFT))&PMC_REGSC_REGFPM_MASK)
9563 #define PMC_REGSC_LPOSTAT_MASK 0x40u
9564 #define PMC_REGSC_LPOSTAT_SHIFT 6u
9565 #define PMC_REGSC_LPOSTAT_WIDTH 1u
9566 #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPOSTAT_SHIFT))&PMC_REGSC_LPOSTAT_MASK)
9567 #define PMC_REGSC_LPODIS_MASK 0x80u
9568 #define PMC_REGSC_LPODIS_SHIFT 7u
9569 #define PMC_REGSC_LPODIS_WIDTH 1u
9570 #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPODIS_SHIFT))&PMC_REGSC_LPODIS_MASK)
9572 #define PMC_LPOTRIM_LPOTRIM_MASK 0x1Fu
9573 #define PMC_LPOTRIM_LPOTRIM_SHIFT 0u
9574 #define PMC_LPOTRIM_LPOTRIM_WIDTH 5u
9575 #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x))<<PMC_LPOTRIM_LPOTRIM_SHIFT))&PMC_LPOTRIM_LPOTRIM_MASK)
9598 #define PORT_PCR_COUNT 32u
9605 uint8_t RESERVED_0[24];
9607 uint8_t RESERVED_1[28];
9614 #define PORT_INSTANCE_COUNT (5u)
9619 #define PORTA_BASE (0x40049000u)
9621 #define PORTA ((PORT_Type *)PORTA_BASE)
9623 #define PORTB_BASE (0x4004A000u)
9625 #define PORTB ((PORT_Type *)PORTB_BASE)
9627 #define PORTC_BASE (0x4004B000u)
9629 #define PORTC ((PORT_Type *)PORTC_BASE)
9631 #define PORTD_BASE (0x4004C000u)
9633 #define PORTD ((PORT_Type *)PORTD_BASE)
9635 #define PORTE_BASE (0x4004D000u)
9637 #define PORTE ((PORT_Type *)PORTE_BASE)
9639 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
9641 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
9643 #define PORT_IRQS_ARR_COUNT (1u)
9645 #define PORT_IRQS_CH_COUNT (1u)
9647 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
9659 #define PORT_PCR_PS_MASK 0x1u
9660 #define PORT_PCR_PS_SHIFT 0u
9661 #define PORT_PCR_PS_WIDTH 1u
9662 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
9663 #define PORT_PCR_PE_MASK 0x2u
9664 #define PORT_PCR_PE_SHIFT 1u
9665 #define PORT_PCR_PE_WIDTH 1u
9666 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
9667 #define PORT_PCR_PFE_MASK 0x10u
9668 #define PORT_PCR_PFE_SHIFT 4u
9669 #define PORT_PCR_PFE_WIDTH 1u
9670 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
9671 #define PORT_PCR_DSE_MASK 0x40u
9672 #define PORT_PCR_DSE_SHIFT 6u
9673 #define PORT_PCR_DSE_WIDTH 1u
9674 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
9675 #define PORT_PCR_MUX_MASK 0x700u
9676 #define PORT_PCR_MUX_SHIFT 8u
9677 #define PORT_PCR_MUX_WIDTH 3u
9678 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
9679 #define PORT_PCR_LK_MASK 0x8000u
9680 #define PORT_PCR_LK_SHIFT 15u
9681 #define PORT_PCR_LK_WIDTH 1u
9682 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
9683 #define PORT_PCR_IRQC_MASK 0xF0000u
9684 #define PORT_PCR_IRQC_SHIFT 16u
9685 #define PORT_PCR_IRQC_WIDTH 4u
9686 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
9687 #define PORT_PCR_ISF_MASK 0x1000000u
9688 #define PORT_PCR_ISF_SHIFT 24u
9689 #define PORT_PCR_ISF_WIDTH 1u
9690 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
9692 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
9693 #define PORT_GPCLR_GPWD_SHIFT 0u
9694 #define PORT_GPCLR_GPWD_WIDTH 16u
9695 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
9696 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
9697 #define PORT_GPCLR_GPWE_SHIFT 16u
9698 #define PORT_GPCLR_GPWE_WIDTH 16u
9699 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
9701 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
9702 #define PORT_GPCHR_GPWD_SHIFT 0u
9703 #define PORT_GPCHR_GPWD_WIDTH 16u
9704 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
9705 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
9706 #define PORT_GPCHR_GPWE_SHIFT 16u
9707 #define PORT_GPCHR_GPWE_WIDTH 16u
9708 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
9710 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
9711 #define PORT_ISFR_ISF_SHIFT 0u
9712 #define PORT_ISFR_ISF_WIDTH 32u
9713 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
9715 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
9716 #define PORT_DFER_DFE_SHIFT 0u
9717 #define PORT_DFER_DFE_WIDTH 32u
9718 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
9720 #define PORT_DFCR_CS_MASK 0x1u
9721 #define PORT_DFCR_CS_SHIFT 0u
9722 #define PORT_DFCR_CS_WIDTH 1u
9723 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
9725 #define PORT_DFWR_FILT_MASK 0x1Fu
9726 #define PORT_DFWR_FILT_SHIFT 0u
9727 #define PORT_DFWR_FILT_WIDTH 5u
9728 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
9751 #define QuadSPI_RBDR_COUNT 32u
9752 #define QuadSPI_LUT_COUNT 64u
9757 uint8_t RESERVED_0[4];
9766 uint8_t RESERVED_1[8];
9770 uint8_t RESERVED_2[196];
9776 uint8_t RESERVED_3[60];
9785 uint8_t RESERVED_4[16];
9790 uint8_t RESERVED_5[112];
9792 uint8_t RESERVED_6[128];
9795 uint8_t RESERVED_7[8];
9800 #define QuadSPI_INSTANCE_COUNT (1u)
9805 #define QuadSPI_BASE (0x40076000u)
9807 #define QuadSPI ((QuadSPI_Type *)QuadSPI_BASE)
9809 #define QuadSPI_BASE_ADDRS { QuadSPI_BASE }
9811 #define QuadSPI_BASE_PTRS { QuadSPI }
9813 #define QuadSPI_IRQS_ARR_COUNT (1u)
9815 #define QuadSPI_IRQS_CH_COUNT (1u)
9817 #define QuadSPI_IRQS { QSPI_IRQn }
9829 #define QuadSPI_MCR_SWRSTSD_MASK 0x1u
9830 #define QuadSPI_MCR_SWRSTSD_SHIFT 0u
9831 #define QuadSPI_MCR_SWRSTSD_WIDTH 1u
9832 #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SWRSTSD_SHIFT))&QuadSPI_MCR_SWRSTSD_MASK)
9833 #define QuadSPI_MCR_SWRSTHD_MASK 0x2u
9834 #define QuadSPI_MCR_SWRSTHD_SHIFT 1u
9835 #define QuadSPI_MCR_SWRSTHD_WIDTH 1u
9836 #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SWRSTHD_SHIFT))&QuadSPI_MCR_SWRSTHD_MASK)
9837 #define QuadSPI_MCR_END_CFG_MASK 0xCu
9838 #define QuadSPI_MCR_END_CFG_SHIFT 2u
9839 #define QuadSPI_MCR_END_CFG_WIDTH 2u
9840 #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_END_CFG_SHIFT))&QuadSPI_MCR_END_CFG_MASK)
9841 #define QuadSPI_MCR_DQS_OUT_EN_MASK 0x10u
9842 #define QuadSPI_MCR_DQS_OUT_EN_SHIFT 4u
9843 #define QuadSPI_MCR_DQS_OUT_EN_WIDTH 1u
9844 #define QuadSPI_MCR_DQS_OUT_EN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_DQS_OUT_EN_SHIFT))&QuadSPI_MCR_DQS_OUT_EN_MASK)
9845 #define QuadSPI_MCR_DQS_LAT_EN_MASK 0x20u
9846 #define QuadSPI_MCR_DQS_LAT_EN_SHIFT 5u
9847 #define QuadSPI_MCR_DQS_LAT_EN_WIDTH 1u
9848 #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_DQS_LAT_EN_SHIFT))&QuadSPI_MCR_DQS_LAT_EN_MASK)
9849 #define QuadSPI_MCR_DQS_EN_MASK 0x40u
9850 #define QuadSPI_MCR_DQS_EN_SHIFT 6u
9851 #define QuadSPI_MCR_DQS_EN_WIDTH 1u
9852 #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_DQS_EN_SHIFT))&QuadSPI_MCR_DQS_EN_MASK)
9853 #define QuadSPI_MCR_DDR_EN_MASK 0x80u
9854 #define QuadSPI_MCR_DDR_EN_SHIFT 7u
9855 #define QuadSPI_MCR_DDR_EN_WIDTH 1u
9856 #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_DDR_EN_SHIFT))&QuadSPI_MCR_DDR_EN_MASK)
9857 #define QuadSPI_MCR_VAR_LAT_EN_MASK 0x100u
9858 #define QuadSPI_MCR_VAR_LAT_EN_SHIFT 8u
9859 #define QuadSPI_MCR_VAR_LAT_EN_WIDTH 1u
9860 #define QuadSPI_MCR_VAR_LAT_EN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_VAR_LAT_EN_SHIFT))&QuadSPI_MCR_VAR_LAT_EN_MASK)
9861 #define QuadSPI_MCR_CLR_RXF_MASK 0x400u
9862 #define QuadSPI_MCR_CLR_RXF_SHIFT 10u
9863 #define QuadSPI_MCR_CLR_RXF_WIDTH 1u
9864 #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_CLR_RXF_SHIFT))&QuadSPI_MCR_CLR_RXF_MASK)
9865 #define QuadSPI_MCR_CLR_TXF_MASK 0x800u
9866 #define QuadSPI_MCR_CLR_TXF_SHIFT 11u
9867 #define QuadSPI_MCR_CLR_TXF_WIDTH 1u
9868 #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_CLR_TXF_SHIFT))&QuadSPI_MCR_CLR_TXF_MASK)
9869 #define QuadSPI_MCR_MDIS_MASK 0x4000u
9870 #define QuadSPI_MCR_MDIS_SHIFT 14u
9871 #define QuadSPI_MCR_MDIS_WIDTH 1u
9872 #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_MDIS_SHIFT))&QuadSPI_MCR_MDIS_MASK)
9873 #define QuadSPI_MCR_DOZE_MASK 0x8000u
9874 #define QuadSPI_MCR_DOZE_SHIFT 15u
9875 #define QuadSPI_MCR_DOZE_WIDTH 1u
9876 #define QuadSPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_DOZE_SHIFT))&QuadSPI_MCR_DOZE_MASK)
9877 #define QuadSPI_MCR_ISD2FA_MASK 0x10000u
9878 #define QuadSPI_MCR_ISD2FA_SHIFT 16u
9879 #define QuadSPI_MCR_ISD2FA_WIDTH 1u
9880 #define QuadSPI_MCR_ISD2FA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_ISD2FA_SHIFT))&QuadSPI_MCR_ISD2FA_MASK)
9881 #define QuadSPI_MCR_ISD3FA_MASK 0x20000u
9882 #define QuadSPI_MCR_ISD3FA_SHIFT 17u
9883 #define QuadSPI_MCR_ISD3FA_WIDTH 1u
9884 #define QuadSPI_MCR_ISD3FA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_ISD3FA_SHIFT))&QuadSPI_MCR_ISD3FA_MASK)
9885 #define QuadSPI_MCR_ISD2FB_MASK 0x40000u
9886 #define QuadSPI_MCR_ISD2FB_SHIFT 18u
9887 #define QuadSPI_MCR_ISD2FB_WIDTH 1u
9888 #define QuadSPI_MCR_ISD2FB(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_ISD2FB_SHIFT))&QuadSPI_MCR_ISD2FB_MASK)
9889 #define QuadSPI_MCR_ISD3FB_MASK 0x80000u
9890 #define QuadSPI_MCR_ISD3FB_SHIFT 19u
9891 #define QuadSPI_MCR_ISD3FB_WIDTH 1u
9892 #define QuadSPI_MCR_ISD3FB(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_ISD3FB_SHIFT))&QuadSPI_MCR_ISD3FB_MASK)
9893 #define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u
9894 #define QuadSPI_MCR_SCLKCFG_SHIFT 24u
9895 #define QuadSPI_MCR_SCLKCFG_WIDTH 8u
9896 #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_MCR_SCLKCFG_SHIFT))&QuadSPI_MCR_SCLKCFG_MASK)
9898 #define QuadSPI_IPCR_IDATSZ_MASK 0xFFFFu
9899 #define QuadSPI_IPCR_IDATSZ_SHIFT 0u
9900 #define QuadSPI_IPCR_IDATSZ_WIDTH 16u
9901 #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_IDATSZ_SHIFT))&QuadSPI_IPCR_IDATSZ_MASK)
9902 #define QuadSPI_IPCR_SEQID_MASK 0xF000000u
9903 #define QuadSPI_IPCR_SEQID_SHIFT 24u
9904 #define QuadSPI_IPCR_SEQID_WIDTH 4u
9905 #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_IPCR_SEQID_SHIFT))&QuadSPI_IPCR_SEQID_MASK)
9907 #define QuadSPI_FLSHCR_TCSS_MASK 0xFu
9908 #define QuadSPI_FLSHCR_TCSS_SHIFT 0u
9909 #define QuadSPI_FLSHCR_TCSS_WIDTH 4u
9910 #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSS_SHIFT))&QuadSPI_FLSHCR_TCSS_MASK)
9911 #define QuadSPI_FLSHCR_TCSH_MASK 0xF00u
9912 #define QuadSPI_FLSHCR_TCSH_SHIFT 8u
9913 #define QuadSPI_FLSHCR_TCSH_WIDTH 4u
9914 #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TCSH_SHIFT))&QuadSPI_FLSHCR_TCSH_MASK)
9915 #define QuadSPI_FLSHCR_TDH_MASK 0x30000u
9916 #define QuadSPI_FLSHCR_TDH_SHIFT 16u
9917 #define QuadSPI_FLSHCR_TDH_WIDTH 2u
9918 #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FLSHCR_TDH_SHIFT))&QuadSPI_FLSHCR_TDH_MASK)
9920 #define QuadSPI_BUF0CR_MSTRID_MASK 0xFu
9921 #define QuadSPI_BUF0CR_MSTRID_SHIFT 0u
9922 #define QuadSPI_BUF0CR_MSTRID_WIDTH 4u
9923 #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_MSTRID_SHIFT))&QuadSPI_BUF0CR_MSTRID_MASK)
9924 #define QuadSPI_BUF0CR_ADATSZ_MASK 0xFF00u
9925 #define QuadSPI_BUF0CR_ADATSZ_SHIFT 8u
9926 #define QuadSPI_BUF0CR_ADATSZ_WIDTH 8u
9927 #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_ADATSZ_SHIFT))&QuadSPI_BUF0CR_ADATSZ_MASK)
9928 #define QuadSPI_BUF0CR_HP_EN_MASK 0x80000000u
9929 #define QuadSPI_BUF0CR_HP_EN_SHIFT 31u
9930 #define QuadSPI_BUF0CR_HP_EN_WIDTH 1u
9931 #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0CR_HP_EN_SHIFT))&QuadSPI_BUF0CR_HP_EN_MASK)
9933 #define QuadSPI_BUF1CR_MSTRID_MASK 0xFu
9934 #define QuadSPI_BUF1CR_MSTRID_SHIFT 0u
9935 #define QuadSPI_BUF1CR_MSTRID_WIDTH 4u
9936 #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_MSTRID_SHIFT))&QuadSPI_BUF1CR_MSTRID_MASK)
9937 #define QuadSPI_BUF1CR_ADATSZ_MASK 0xFF00u
9938 #define QuadSPI_BUF1CR_ADATSZ_SHIFT 8u
9939 #define QuadSPI_BUF1CR_ADATSZ_WIDTH 8u
9940 #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1CR_ADATSZ_SHIFT))&QuadSPI_BUF1CR_ADATSZ_MASK)
9942 #define QuadSPI_BUF2CR_MSTRID_MASK 0xFu
9943 #define QuadSPI_BUF2CR_MSTRID_SHIFT 0u
9944 #define QuadSPI_BUF2CR_MSTRID_WIDTH 4u
9945 #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_MSTRID_SHIFT))&QuadSPI_BUF2CR_MSTRID_MASK)
9946 #define QuadSPI_BUF2CR_ADATSZ_MASK 0xFF00u
9947 #define QuadSPI_BUF2CR_ADATSZ_SHIFT 8u
9948 #define QuadSPI_BUF2CR_ADATSZ_WIDTH 8u
9949 #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2CR_ADATSZ_SHIFT))&QuadSPI_BUF2CR_ADATSZ_MASK)
9951 #define QuadSPI_BUF3CR_MSTRID_MASK 0xFu
9952 #define QuadSPI_BUF3CR_MSTRID_SHIFT 0u
9953 #define QuadSPI_BUF3CR_MSTRID_WIDTH 4u
9954 #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_MSTRID_SHIFT))&QuadSPI_BUF3CR_MSTRID_MASK)
9955 #define QuadSPI_BUF3CR_ADATSZ_MASK 0xFF00u
9956 #define QuadSPI_BUF3CR_ADATSZ_SHIFT 8u
9957 #define QuadSPI_BUF3CR_ADATSZ_WIDTH 8u
9958 #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ADATSZ_SHIFT))&QuadSPI_BUF3CR_ADATSZ_MASK)
9959 #define QuadSPI_BUF3CR_ALLMST_MASK 0x80000000u
9960 #define QuadSPI_BUF3CR_ALLMST_SHIFT 31u
9961 #define QuadSPI_BUF3CR_ALLMST_WIDTH 1u
9962 #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF3CR_ALLMST_SHIFT))&QuadSPI_BUF3CR_ALLMST_MASK)
9964 #define QuadSPI_BFGENCR_SEQID_MASK 0xF000u
9965 #define QuadSPI_BFGENCR_SEQID_SHIFT 12u
9966 #define QuadSPI_BFGENCR_SEQID_WIDTH 4u
9967 #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BFGENCR_SEQID_SHIFT))&QuadSPI_BFGENCR_SEQID_MASK)
9969 #define QuadSPI_SOCCR_SOCCFG_MASK 0xFFFFFFFFu
9970 #define QuadSPI_SOCCR_SOCCFG_SHIFT 0u
9971 #define QuadSPI_SOCCR_SOCCFG_WIDTH 32u
9972 #define QuadSPI_SOCCR_SOCCFG(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SOCCR_SOCCFG_SHIFT))&QuadSPI_SOCCR_SOCCFG_MASK)
9974 #define QuadSPI_BUF0IND_TPINDX0_MASK 0xFFFFFFF8u
9975 #define QuadSPI_BUF0IND_TPINDX0_SHIFT 3u
9976 #define QuadSPI_BUF0IND_TPINDX0_WIDTH 29u
9977 #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF0IND_TPINDX0_SHIFT))&QuadSPI_BUF0IND_TPINDX0_MASK)
9979 #define QuadSPI_BUF1IND_TPINDX1_MASK 0xFFFFFFF8u
9980 #define QuadSPI_BUF1IND_TPINDX1_SHIFT 3u
9981 #define QuadSPI_BUF1IND_TPINDX1_WIDTH 29u
9982 #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF1IND_TPINDX1_SHIFT))&QuadSPI_BUF1IND_TPINDX1_MASK)
9984 #define QuadSPI_BUF2IND_TPINDX2_MASK 0xFFFFFFF8u
9985 #define QuadSPI_BUF2IND_TPINDX2_SHIFT 3u
9986 #define QuadSPI_BUF2IND_TPINDX2_WIDTH 29u
9987 #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_BUF2IND_TPINDX2_SHIFT))&QuadSPI_BUF2IND_TPINDX2_MASK)
9989 #define QuadSPI_SFAR_SFADR_MASK 0xFFFFFFFFu
9990 #define QuadSPI_SFAR_SFADR_SHIFT 0u
9991 #define QuadSPI_SFAR_SFADR_WIDTH 32u
9992 #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFAR_SFADR_SHIFT))&QuadSPI_SFAR_SFADR_MASK)
9994 #define QuadSPI_SFACR_CAS_MASK 0xFu
9995 #define QuadSPI_SFACR_CAS_SHIFT 0u
9996 #define QuadSPI_SFACR_CAS_WIDTH 4u
9997 #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFACR_CAS_SHIFT))&QuadSPI_SFACR_CAS_MASK)
9998 #define QuadSPI_SFACR_WA_MASK 0x10000u
9999 #define QuadSPI_SFACR_WA_SHIFT 16u
10000 #define QuadSPI_SFACR_WA_WIDTH 1u
10001 #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFACR_WA_SHIFT))&QuadSPI_SFACR_WA_MASK)
10003 #define QuadSPI_SMPR_FSPHS_MASK 0x20u
10004 #define QuadSPI_SMPR_FSPHS_SHIFT 5u
10005 #define QuadSPI_SMPR_FSPHS_WIDTH 1u
10006 #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_FSPHS_SHIFT))&QuadSPI_SMPR_FSPHS_MASK)
10007 #define QuadSPI_SMPR_FSDLY_MASK 0x40u
10008 #define QuadSPI_SMPR_FSDLY_SHIFT 6u
10009 #define QuadSPI_SMPR_FSDLY_WIDTH 1u
10010 #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SMPR_FSDLY_SHIFT))&QuadSPI_SMPR_FSDLY_MASK)
10012 #define QuadSPI_RBSR_RDBFL_MASK 0x3F00u
10013 #define QuadSPI_RBSR_RDBFL_SHIFT 8u
10014 #define QuadSPI_RBSR_RDBFL_WIDTH 6u
10015 #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDBFL_SHIFT))&QuadSPI_RBSR_RDBFL_MASK)
10016 #define QuadSPI_RBSR_RDCTR_MASK 0xFFFF0000u
10017 #define QuadSPI_RBSR_RDCTR_SHIFT 16u
10018 #define QuadSPI_RBSR_RDCTR_WIDTH 16u
10019 #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBSR_RDCTR_SHIFT))&QuadSPI_RBSR_RDCTR_MASK)
10021 #define QuadSPI_RBCT_WMRK_MASK 0x1Fu
10022 #define QuadSPI_RBCT_WMRK_SHIFT 0u
10023 #define QuadSPI_RBCT_WMRK_WIDTH 5u
10024 #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_WMRK_SHIFT))&QuadSPI_RBCT_WMRK_MASK)
10025 #define QuadSPI_RBCT_RXBRD_MASK 0x100u
10026 #define QuadSPI_RBCT_RXBRD_SHIFT 8u
10027 #define QuadSPI_RBCT_RXBRD_WIDTH 1u
10028 #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBCT_RXBRD_SHIFT))&QuadSPI_RBCT_RXBRD_MASK)
10030 #define QuadSPI_TBSR_TRBFL_MASK 0x3F00u
10031 #define QuadSPI_TBSR_TRBFL_SHIFT 8u
10032 #define QuadSPI_TBSR_TRBFL_WIDTH 6u
10033 #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRBFL_SHIFT))&QuadSPI_TBSR_TRBFL_MASK)
10034 #define QuadSPI_TBSR_TRCTR_MASK 0xFFFF0000u
10035 #define QuadSPI_TBSR_TRCTR_SHIFT 16u
10036 #define QuadSPI_TBSR_TRCTR_WIDTH 16u
10037 #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBSR_TRCTR_SHIFT))&QuadSPI_TBSR_TRCTR_MASK)
10039 #define QuadSPI_TBDR_TXDATA_MASK 0xFFFFFFFFu
10040 #define QuadSPI_TBDR_TXDATA_SHIFT 0u
10041 #define QuadSPI_TBDR_TXDATA_WIDTH 32u
10042 #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBDR_TXDATA_SHIFT))&QuadSPI_TBDR_TXDATA_MASK)
10044 #define QuadSPI_TBCT_WMRK_MASK 0x1Fu
10045 #define QuadSPI_TBCT_WMRK_SHIFT 0u
10046 #define QuadSPI_TBCT_WMRK_WIDTH 5u
10047 #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_TBCT_WMRK_SHIFT))&QuadSPI_TBCT_WMRK_MASK)
10049 #define QuadSPI_SR_BUSY_MASK 0x1u
10050 #define QuadSPI_SR_BUSY_SHIFT 0u
10051 #define QuadSPI_SR_BUSY_WIDTH 1u
10052 #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_BUSY_SHIFT))&QuadSPI_SR_BUSY_MASK)
10053 #define QuadSPI_SR_IP_ACC_MASK 0x2u
10054 #define QuadSPI_SR_IP_ACC_SHIFT 1u
10055 #define QuadSPI_SR_IP_ACC_WIDTH 1u
10056 #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_IP_ACC_SHIFT))&QuadSPI_SR_IP_ACC_MASK)
10057 #define QuadSPI_SR_AHB_ACC_MASK 0x4u
10058 #define QuadSPI_SR_AHB_ACC_SHIFT 2u
10059 #define QuadSPI_SR_AHB_ACC_WIDTH 1u
10060 #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB_ACC_SHIFT))&QuadSPI_SR_AHB_ACC_MASK)
10061 #define QuadSPI_SR_AHBGNT_MASK 0x20u
10062 #define QuadSPI_SR_AHBGNT_SHIFT 5u
10063 #define QuadSPI_SR_AHBGNT_WIDTH 1u
10064 #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHBGNT_SHIFT))&QuadSPI_SR_AHBGNT_MASK)
10065 #define QuadSPI_SR_AHBTRN_MASK 0x40u
10066 #define QuadSPI_SR_AHBTRN_SHIFT 6u
10067 #define QuadSPI_SR_AHBTRN_WIDTH 1u
10068 #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHBTRN_SHIFT))&QuadSPI_SR_AHBTRN_MASK)
10069 #define QuadSPI_SR_AHB0NE_MASK 0x80u
10070 #define QuadSPI_SR_AHB0NE_SHIFT 7u
10071 #define QuadSPI_SR_AHB0NE_WIDTH 1u
10072 #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB0NE_SHIFT))&QuadSPI_SR_AHB0NE_MASK)
10073 #define QuadSPI_SR_AHB1NE_MASK 0x100u
10074 #define QuadSPI_SR_AHB1NE_SHIFT 8u
10075 #define QuadSPI_SR_AHB1NE_WIDTH 1u
10076 #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB1NE_SHIFT))&QuadSPI_SR_AHB1NE_MASK)
10077 #define QuadSPI_SR_AHB2NE_MASK 0x200u
10078 #define QuadSPI_SR_AHB2NE_SHIFT 9u
10079 #define QuadSPI_SR_AHB2NE_WIDTH 1u
10080 #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB2NE_SHIFT))&QuadSPI_SR_AHB2NE_MASK)
10081 #define QuadSPI_SR_AHB3NE_MASK 0x400u
10082 #define QuadSPI_SR_AHB3NE_SHIFT 10u
10083 #define QuadSPI_SR_AHB3NE_WIDTH 1u
10084 #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB3NE_SHIFT))&QuadSPI_SR_AHB3NE_MASK)
10085 #define QuadSPI_SR_AHB0FUL_MASK 0x800u
10086 #define QuadSPI_SR_AHB0FUL_SHIFT 11u
10087 #define QuadSPI_SR_AHB0FUL_WIDTH 1u
10088 #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB0FUL_SHIFT))&QuadSPI_SR_AHB0FUL_MASK)
10089 #define QuadSPI_SR_AHB1FUL_MASK 0x1000u
10090 #define QuadSPI_SR_AHB1FUL_SHIFT 12u
10091 #define QuadSPI_SR_AHB1FUL_WIDTH 1u
10092 #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB1FUL_SHIFT))&QuadSPI_SR_AHB1FUL_MASK)
10093 #define QuadSPI_SR_AHB2FUL_MASK 0x2000u
10094 #define QuadSPI_SR_AHB2FUL_SHIFT 13u
10095 #define QuadSPI_SR_AHB2FUL_WIDTH 1u
10096 #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB2FUL_SHIFT))&QuadSPI_SR_AHB2FUL_MASK)
10097 #define QuadSPI_SR_AHB3FUL_MASK 0x4000u
10098 #define QuadSPI_SR_AHB3FUL_SHIFT 14u
10099 #define QuadSPI_SR_AHB3FUL_WIDTH 1u
10100 #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_AHB3FUL_SHIFT))&QuadSPI_SR_AHB3FUL_MASK)
10101 #define QuadSPI_SR_RXWE_MASK 0x10000u
10102 #define QuadSPI_SR_RXWE_SHIFT 16u
10103 #define QuadSPI_SR_RXWE_WIDTH 1u
10104 #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_RXWE_SHIFT))&QuadSPI_SR_RXWE_MASK)
10105 #define QuadSPI_SR_RXFULL_MASK 0x80000u
10106 #define QuadSPI_SR_RXFULL_SHIFT 19u
10107 #define QuadSPI_SR_RXFULL_WIDTH 1u
10108 #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_RXFULL_SHIFT))&QuadSPI_SR_RXFULL_MASK)
10109 #define QuadSPI_SR_RXDMA_MASK 0x800000u
10110 #define QuadSPI_SR_RXDMA_SHIFT 23u
10111 #define QuadSPI_SR_RXDMA_WIDTH 1u
10112 #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_RXDMA_SHIFT))&QuadSPI_SR_RXDMA_MASK)
10113 #define QuadSPI_SR_TXEDA_MASK 0x1000000u
10114 #define QuadSPI_SR_TXEDA_SHIFT 24u
10115 #define QuadSPI_SR_TXEDA_WIDTH 1u
10116 #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_TXEDA_SHIFT))&QuadSPI_SR_TXEDA_MASK)
10117 #define QuadSPI_SR_TXWA_MASK 0x2000000u
10118 #define QuadSPI_SR_TXWA_SHIFT 25u
10119 #define QuadSPI_SR_TXWA_WIDTH 1u
10120 #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_TXWA_SHIFT))&QuadSPI_SR_TXWA_MASK)
10121 #define QuadSPI_SR_TXDMA_MASK 0x4000000u
10122 #define QuadSPI_SR_TXDMA_SHIFT 26u
10123 #define QuadSPI_SR_TXDMA_WIDTH 1u
10124 #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_TXDMA_SHIFT))&QuadSPI_SR_TXDMA_MASK)
10125 #define QuadSPI_SR_TXFULL_MASK 0x8000000u
10126 #define QuadSPI_SR_TXFULL_SHIFT 27u
10127 #define QuadSPI_SR_TXFULL_WIDTH 1u
10128 #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SR_TXFULL_SHIFT))&QuadSPI_SR_TXFULL_MASK)
10130 #define QuadSPI_FR_TFF_MASK 0x1u
10131 #define QuadSPI_FR_TFF_SHIFT 0u
10132 #define QuadSPI_FR_TFF_WIDTH 1u
10133 #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_TFF_SHIFT))&QuadSPI_FR_TFF_MASK)
10134 #define QuadSPI_FR_IPGEF_MASK 0x10u
10135 #define QuadSPI_FR_IPGEF_SHIFT 4u
10136 #define QuadSPI_FR_IPGEF_WIDTH 1u
10137 #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_IPGEF_SHIFT))&QuadSPI_FR_IPGEF_MASK)
10138 #define QuadSPI_FR_IPIEF_MASK 0x40u
10139 #define QuadSPI_FR_IPIEF_SHIFT 6u
10140 #define QuadSPI_FR_IPIEF_WIDTH 1u
10141 #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_IPIEF_SHIFT))&QuadSPI_FR_IPIEF_MASK)
10142 #define QuadSPI_FR_IPAEF_MASK 0x80u
10143 #define QuadSPI_FR_IPAEF_SHIFT 7u
10144 #define QuadSPI_FR_IPAEF_WIDTH 1u
10145 #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_IPAEF_SHIFT))&QuadSPI_FR_IPAEF_MASK)
10146 #define QuadSPI_FR_ABOF_MASK 0x1000u
10147 #define QuadSPI_FR_ABOF_SHIFT 12u
10148 #define QuadSPI_FR_ABOF_WIDTH 1u
10149 #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_ABOF_SHIFT))&QuadSPI_FR_ABOF_MASK)
10150 #define QuadSPI_FR_AIBSEF_MASK 0x2000u
10151 #define QuadSPI_FR_AIBSEF_SHIFT 13u
10152 #define QuadSPI_FR_AIBSEF_WIDTH 1u
10153 #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_AIBSEF_SHIFT))&QuadSPI_FR_AIBSEF_MASK)
10154 #define QuadSPI_FR_AITEF_MASK 0x4000u
10155 #define QuadSPI_FR_AITEF_SHIFT 14u
10156 #define QuadSPI_FR_AITEF_WIDTH 1u
10157 #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_AITEF_SHIFT))&QuadSPI_FR_AITEF_MASK)
10158 #define QuadSPI_FR_ABSEF_MASK 0x8000u
10159 #define QuadSPI_FR_ABSEF_SHIFT 15u
10160 #define QuadSPI_FR_ABSEF_WIDTH 1u
10161 #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_ABSEF_SHIFT))&QuadSPI_FR_ABSEF_MASK)
10162 #define QuadSPI_FR_RBDF_MASK 0x10000u
10163 #define QuadSPI_FR_RBDF_SHIFT 16u
10164 #define QuadSPI_FR_RBDF_WIDTH 1u
10165 #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_RBDF_SHIFT))&QuadSPI_FR_RBDF_MASK)
10166 #define QuadSPI_FR_RBOF_MASK 0x20000u
10167 #define QuadSPI_FR_RBOF_SHIFT 17u
10168 #define QuadSPI_FR_RBOF_WIDTH 1u
10169 #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_RBOF_SHIFT))&QuadSPI_FR_RBOF_MASK)
10170 #define QuadSPI_FR_ILLINE_MASK 0x800000u
10171 #define QuadSPI_FR_ILLINE_SHIFT 23u
10172 #define QuadSPI_FR_ILLINE_WIDTH 1u
10173 #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_ILLINE_SHIFT))&QuadSPI_FR_ILLINE_MASK)
10174 #define QuadSPI_FR_TBUF_MASK 0x4000000u
10175 #define QuadSPI_FR_TBUF_SHIFT 26u
10176 #define QuadSPI_FR_TBUF_WIDTH 1u
10177 #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_TBUF_SHIFT))&QuadSPI_FR_TBUF_MASK)
10178 #define QuadSPI_FR_TBFF_MASK 0x8000000u
10179 #define QuadSPI_FR_TBFF_SHIFT 27u
10180 #define QuadSPI_FR_TBFF_WIDTH 1u
10181 #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_FR_TBFF_SHIFT))&QuadSPI_FR_TBFF_MASK)
10183 #define QuadSPI_RSER_TFIE_MASK 0x1u
10184 #define QuadSPI_RSER_TFIE_SHIFT 0u
10185 #define QuadSPI_RSER_TFIE_WIDTH 1u
10186 #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_TFIE_SHIFT))&QuadSPI_RSER_TFIE_MASK)
10187 #define QuadSPI_RSER_IPGEIE_MASK 0x10u
10188 #define QuadSPI_RSER_IPGEIE_SHIFT 4u
10189 #define QuadSPI_RSER_IPGEIE_WIDTH 1u
10190 #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_IPGEIE_SHIFT))&QuadSPI_RSER_IPGEIE_MASK)
10191 #define QuadSPI_RSER_IPIEIE_MASK 0x40u
10192 #define QuadSPI_RSER_IPIEIE_SHIFT 6u
10193 #define QuadSPI_RSER_IPIEIE_WIDTH 1u
10194 #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_IPIEIE_SHIFT))&QuadSPI_RSER_IPIEIE_MASK)
10195 #define QuadSPI_RSER_IPAEIE_MASK 0x80u
10196 #define QuadSPI_RSER_IPAEIE_SHIFT 7u
10197 #define QuadSPI_RSER_IPAEIE_WIDTH 1u
10198 #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_IPAEIE_SHIFT))&QuadSPI_RSER_IPAEIE_MASK)
10199 #define QuadSPI_RSER_ABOIE_MASK 0x1000u
10200 #define QuadSPI_RSER_ABOIE_SHIFT 12u
10201 #define QuadSPI_RSER_ABOIE_WIDTH 1u
10202 #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_ABOIE_SHIFT))&QuadSPI_RSER_ABOIE_MASK)
10203 #define QuadSPI_RSER_AIBSIE_MASK 0x2000u
10204 #define QuadSPI_RSER_AIBSIE_SHIFT 13u
10205 #define QuadSPI_RSER_AIBSIE_WIDTH 1u
10206 #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_AIBSIE_SHIFT))&QuadSPI_RSER_AIBSIE_MASK)
10207 #define QuadSPI_RSER_AITIE_MASK 0x4000u
10208 #define QuadSPI_RSER_AITIE_SHIFT 14u
10209 #define QuadSPI_RSER_AITIE_WIDTH 1u
10210 #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_AITIE_SHIFT))&QuadSPI_RSER_AITIE_MASK)
10211 #define QuadSPI_RSER_ABSEIE_MASK 0x8000u
10212 #define QuadSPI_RSER_ABSEIE_SHIFT 15u
10213 #define QuadSPI_RSER_ABSEIE_WIDTH 1u
10214 #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_ABSEIE_SHIFT))&QuadSPI_RSER_ABSEIE_MASK)
10215 #define QuadSPI_RSER_RBDIE_MASK 0x10000u
10216 #define QuadSPI_RSER_RBDIE_SHIFT 16u
10217 #define QuadSPI_RSER_RBDIE_WIDTH 1u
10218 #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_RBDIE_SHIFT))&QuadSPI_RSER_RBDIE_MASK)
10219 #define QuadSPI_RSER_RBOIE_MASK 0x20000u
10220 #define QuadSPI_RSER_RBOIE_SHIFT 17u
10221 #define QuadSPI_RSER_RBOIE_WIDTH 1u
10222 #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_RBOIE_SHIFT))&QuadSPI_RSER_RBOIE_MASK)
10223 #define QuadSPI_RSER_RBDDE_MASK 0x200000u
10224 #define QuadSPI_RSER_RBDDE_SHIFT 21u
10225 #define QuadSPI_RSER_RBDDE_WIDTH 1u
10226 #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_RBDDE_SHIFT))&QuadSPI_RSER_RBDDE_MASK)
10227 #define QuadSPI_RSER_ILLINIE_MASK 0x800000u
10228 #define QuadSPI_RSER_ILLINIE_SHIFT 23u
10229 #define QuadSPI_RSER_ILLINIE_WIDTH 1u
10230 #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_ILLINIE_SHIFT))&QuadSPI_RSER_ILLINIE_MASK)
10231 #define QuadSPI_RSER_TBFDE_MASK 0x2000000u
10232 #define QuadSPI_RSER_TBFDE_SHIFT 25u
10233 #define QuadSPI_RSER_TBFDE_WIDTH 1u
10234 #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_TBFDE_SHIFT))&QuadSPI_RSER_TBFDE_MASK)
10235 #define QuadSPI_RSER_TBUIE_MASK 0x4000000u
10236 #define QuadSPI_RSER_TBUIE_SHIFT 26u
10237 #define QuadSPI_RSER_TBUIE_WIDTH 1u
10238 #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_TBUIE_SHIFT))&QuadSPI_RSER_TBUIE_MASK)
10239 #define QuadSPI_RSER_TBFIE_MASK 0x8000000u
10240 #define QuadSPI_RSER_TBFIE_SHIFT 27u
10241 #define QuadSPI_RSER_TBFIE_WIDTH 1u
10242 #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RSER_TBFIE_SHIFT))&QuadSPI_RSER_TBFIE_MASK)
10244 #define QuadSPI_SPNDST_SUSPND_MASK 0x1u
10245 #define QuadSPI_SPNDST_SUSPND_SHIFT 0u
10246 #define QuadSPI_SPNDST_SUSPND_WIDTH 1u
10247 #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SUSPND_SHIFT))&QuadSPI_SPNDST_SUSPND_MASK)
10248 #define QuadSPI_SPNDST_SPDBUF_MASK 0xC0u
10249 #define QuadSPI_SPNDST_SPDBUF_SHIFT 6u
10250 #define QuadSPI_SPNDST_SPDBUF_WIDTH 2u
10251 #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_SPDBUF_SHIFT))&QuadSPI_SPNDST_SPDBUF_MASK)
10252 #define QuadSPI_SPNDST_DATLFT_MASK 0xFE00u
10253 #define QuadSPI_SPNDST_DATLFT_SHIFT 9u
10254 #define QuadSPI_SPNDST_DATLFT_WIDTH 7u
10255 #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPNDST_DATLFT_SHIFT))&QuadSPI_SPNDST_DATLFT_MASK)
10257 #define QuadSPI_SPTRCLR_BFPTRC_MASK 0x1u
10258 #define QuadSPI_SPTRCLR_BFPTRC_SHIFT 0u
10259 #define QuadSPI_SPTRCLR_BFPTRC_WIDTH 1u
10260 #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPTRCLR_BFPTRC_SHIFT))&QuadSPI_SPTRCLR_BFPTRC_MASK)
10261 #define QuadSPI_SPTRCLR_IPPTRC_MASK 0x100u
10262 #define QuadSPI_SPTRCLR_IPPTRC_SHIFT 8u
10263 #define QuadSPI_SPTRCLR_IPPTRC_WIDTH 1u
10264 #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SPTRCLR_IPPTRC_SHIFT))&QuadSPI_SPTRCLR_IPPTRC_MASK)
10266 #define QuadSPI_SFA1AD_TPADA1_MASK 0xFFFFFC00u
10267 #define QuadSPI_SFA1AD_TPADA1_SHIFT 10u
10268 #define QuadSPI_SFA1AD_TPADA1_WIDTH 22u
10269 #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA1AD_TPADA1_SHIFT))&QuadSPI_SFA1AD_TPADA1_MASK)
10271 #define QuadSPI_SFA2AD_TPADA2_MASK 0xFFFFFC00u
10272 #define QuadSPI_SFA2AD_TPADA2_SHIFT 10u
10273 #define QuadSPI_SFA2AD_TPADA2_WIDTH 22u
10274 #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFA2AD_TPADA2_SHIFT))&QuadSPI_SFA2AD_TPADA2_MASK)
10276 #define QuadSPI_SFB1AD_TPADB1_MASK 0xFFFFFC00u
10277 #define QuadSPI_SFB1AD_TPADB1_SHIFT 10u
10278 #define QuadSPI_SFB1AD_TPADB1_WIDTH 22u
10279 #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB1AD_TPADB1_SHIFT))&QuadSPI_SFB1AD_TPADB1_MASK)
10281 #define QuadSPI_SFB2AD_TPADB2_MASK 0xFFFFFC00u
10282 #define QuadSPI_SFB2AD_TPADB2_SHIFT 10u
10283 #define QuadSPI_SFB2AD_TPADB2_WIDTH 22u
10284 #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_SFB2AD_TPADB2_SHIFT))&QuadSPI_SFB2AD_TPADB2_MASK)
10286 #define QuadSPI_RBDR_RXDATA_MASK 0xFFFFFFFFu
10287 #define QuadSPI_RBDR_RXDATA_SHIFT 0u
10288 #define QuadSPI_RBDR_RXDATA_WIDTH 32u
10289 #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_RBDR_RXDATA_SHIFT))&QuadSPI_RBDR_RXDATA_MASK)
10291 #define QuadSPI_LUTKEY_KEY_MASK 0xFFFFFFFFu
10292 #define QuadSPI_LUTKEY_KEY_SHIFT 0u
10293 #define QuadSPI_LUTKEY_KEY_WIDTH 32u
10294 #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUTKEY_KEY_SHIFT))&QuadSPI_LUTKEY_KEY_MASK)
10296 #define QuadSPI_LCKCR_LOCK_MASK 0x1u
10297 #define QuadSPI_LCKCR_LOCK_SHIFT 0u
10298 #define QuadSPI_LCKCR_LOCK_WIDTH 1u
10299 #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LCKCR_LOCK_SHIFT))&QuadSPI_LCKCR_LOCK_MASK)
10300 #define QuadSPI_LCKCR_UNLOCK_MASK 0x2u
10301 #define QuadSPI_LCKCR_UNLOCK_SHIFT 1u
10302 #define QuadSPI_LCKCR_UNLOCK_WIDTH 1u
10303 #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LCKCR_UNLOCK_SHIFT))&QuadSPI_LCKCR_UNLOCK_MASK)
10305 #define QuadSPI_LUT_OPRND0_MASK 0xFFu
10306 #define QuadSPI_LUT_OPRND0_SHIFT 0u
10307 #define QuadSPI_LUT_OPRND0_WIDTH 8u
10308 #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND0_SHIFT))&QuadSPI_LUT_OPRND0_MASK)
10309 #define QuadSPI_LUT_PAD0_MASK 0x300u
10310 #define QuadSPI_LUT_PAD0_SHIFT 8u
10311 #define QuadSPI_LUT_PAD0_WIDTH 2u
10312 #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD0_SHIFT))&QuadSPI_LUT_PAD0_MASK)
10313 #define QuadSPI_LUT_INSTR0_MASK 0xFC00u
10314 #define QuadSPI_LUT_INSTR0_SHIFT 10u
10315 #define QuadSPI_LUT_INSTR0_WIDTH 6u
10316 #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR0_SHIFT))&QuadSPI_LUT_INSTR0_MASK)
10317 #define QuadSPI_LUT_OPRND1_MASK 0xFF0000u
10318 #define QuadSPI_LUT_OPRND1_SHIFT 16u
10319 #define QuadSPI_LUT_OPRND1_WIDTH 8u
10320 #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_OPRND1_SHIFT))&QuadSPI_LUT_OPRND1_MASK)
10321 #define QuadSPI_LUT_PAD1_MASK 0x3000000u
10322 #define QuadSPI_LUT_PAD1_SHIFT 24u
10323 #define QuadSPI_LUT_PAD1_WIDTH 2u
10324 #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_PAD1_SHIFT))&QuadSPI_LUT_PAD1_MASK)
10325 #define QuadSPI_LUT_INSTR1_MASK 0xFC000000u
10326 #define QuadSPI_LUT_INSTR1_SHIFT 26u
10327 #define QuadSPI_LUT_INSTR1_WIDTH 6u
10328 #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x))<<QuadSPI_LUT_INSTR1_SHIFT))&QuadSPI_LUT_INSTR1_MASK)
10358 uint8_t RESERVED_0[8];
10364 #define RCM_INSTANCE_COUNT (1u)
10369 #define RCM_BASE (0x4007F000u)
10371 #define RCM ((RCM_Type *)RCM_BASE)
10373 #define RCM_BASE_ADDRS { RCM_BASE }
10375 #define RCM_BASE_PTRS { RCM }
10377 #define RCM_IRQS_ARR_COUNT (1u)
10379 #define RCM_IRQS_CH_COUNT (1u)
10381 #define RCM_IRQS { RCM_IRQn }
10393 #define RCM_VERID_FEATURE_MASK 0xFFFFu
10394 #define RCM_VERID_FEATURE_SHIFT 0u
10395 #define RCM_VERID_FEATURE_WIDTH 16u
10396 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_FEATURE_SHIFT))&RCM_VERID_FEATURE_MASK)
10397 #define RCM_VERID_MINOR_MASK 0xFF0000u
10398 #define RCM_VERID_MINOR_SHIFT 16u
10399 #define RCM_VERID_MINOR_WIDTH 8u
10400 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MINOR_SHIFT))&RCM_VERID_MINOR_MASK)
10401 #define RCM_VERID_MAJOR_MASK 0xFF000000u
10402 #define RCM_VERID_MAJOR_SHIFT 24u
10403 #define RCM_VERID_MAJOR_WIDTH 8u
10404 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MAJOR_SHIFT))&RCM_VERID_MAJOR_MASK)
10406 #define RCM_PARAM_EWAKEUP_MASK 0x1u
10407 #define RCM_PARAM_EWAKEUP_SHIFT 0u
10408 #define RCM_PARAM_EWAKEUP_WIDTH 1u
10409 #define RCM_PARAM_EWAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWAKEUP_SHIFT))&RCM_PARAM_EWAKEUP_MASK)
10410 #define RCM_PARAM_ELVD_MASK 0x2u
10411 #define RCM_PARAM_ELVD_SHIFT 1u
10412 #define RCM_PARAM_ELVD_WIDTH 1u
10413 #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELVD_SHIFT))&RCM_PARAM_ELVD_MASK)
10414 #define RCM_PARAM_ELOC_MASK 0x4u
10415 #define RCM_PARAM_ELOC_SHIFT 2u
10416 #define RCM_PARAM_ELOC_WIDTH 1u
10417 #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOC_SHIFT))&RCM_PARAM_ELOC_MASK)
10418 #define RCM_PARAM_ELOL_MASK 0x8u
10419 #define RCM_PARAM_ELOL_SHIFT 3u
10420 #define RCM_PARAM_ELOL_WIDTH 1u
10421 #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOL_SHIFT))&RCM_PARAM_ELOL_MASK)
10422 #define RCM_PARAM_EWDOG_MASK 0x20u
10423 #define RCM_PARAM_EWDOG_SHIFT 5u
10424 #define RCM_PARAM_EWDOG_WIDTH 1u
10425 #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWDOG_SHIFT))&RCM_PARAM_EWDOG_MASK)
10426 #define RCM_PARAM_EPIN_MASK 0x40u
10427 #define RCM_PARAM_EPIN_SHIFT 6u
10428 #define RCM_PARAM_EPIN_WIDTH 1u
10429 #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPIN_SHIFT))&RCM_PARAM_EPIN_MASK)
10430 #define RCM_PARAM_EPOR_MASK 0x80u
10431 #define RCM_PARAM_EPOR_SHIFT 7u
10432 #define RCM_PARAM_EPOR_WIDTH 1u
10433 #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPOR_SHIFT))&RCM_PARAM_EPOR_MASK)
10434 #define RCM_PARAM_EJTAG_MASK 0x100u
10435 #define RCM_PARAM_EJTAG_SHIFT 8u
10436 #define RCM_PARAM_EJTAG_WIDTH 1u
10437 #define RCM_PARAM_EJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EJTAG_SHIFT))&RCM_PARAM_EJTAG_MASK)
10438 #define RCM_PARAM_ELOCKUP_MASK 0x200u
10439 #define RCM_PARAM_ELOCKUP_SHIFT 9u
10440 #define RCM_PARAM_ELOCKUP_WIDTH 1u
10441 #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOCKUP_SHIFT))&RCM_PARAM_ELOCKUP_MASK)
10442 #define RCM_PARAM_ESW_MASK 0x400u
10443 #define RCM_PARAM_ESW_SHIFT 10u
10444 #define RCM_PARAM_ESW_WIDTH 1u
10445 #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESW_SHIFT))&RCM_PARAM_ESW_MASK)
10446 #define RCM_PARAM_EMDM_AP_MASK 0x800u
10447 #define RCM_PARAM_EMDM_AP_SHIFT 11u
10448 #define RCM_PARAM_EMDM_AP_WIDTH 1u
10449 #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EMDM_AP_SHIFT))&RCM_PARAM_EMDM_AP_MASK)
10450 #define RCM_PARAM_ESACKERR_MASK 0x2000u
10451 #define RCM_PARAM_ESACKERR_SHIFT 13u
10452 #define RCM_PARAM_ESACKERR_WIDTH 1u
10453 #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESACKERR_SHIFT))&RCM_PARAM_ESACKERR_MASK)
10454 #define RCM_PARAM_ETAMPER_MASK 0x8000u
10455 #define RCM_PARAM_ETAMPER_SHIFT 15u
10456 #define RCM_PARAM_ETAMPER_WIDTH 1u
10457 #define RCM_PARAM_ETAMPER(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ETAMPER_SHIFT))&RCM_PARAM_ETAMPER_MASK)
10458 #define RCM_PARAM_ECORE1_MASK 0x10000u
10459 #define RCM_PARAM_ECORE1_SHIFT 16u
10460 #define RCM_PARAM_ECORE1_WIDTH 1u
10461 #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ECORE1_SHIFT))&RCM_PARAM_ECORE1_MASK)
10463 #define RCM_SRS_LVD_MASK 0x2u
10464 #define RCM_SRS_LVD_SHIFT 1u
10465 #define RCM_SRS_LVD_WIDTH 1u
10466 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LVD_SHIFT))&RCM_SRS_LVD_MASK)
10467 #define RCM_SRS_LOC_MASK 0x4u
10468 #define RCM_SRS_LOC_SHIFT 2u
10469 #define RCM_SRS_LOC_WIDTH 1u
10470 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOC_SHIFT))&RCM_SRS_LOC_MASK)
10471 #define RCM_SRS_LOL_MASK 0x8u
10472 #define RCM_SRS_LOL_SHIFT 3u
10473 #define RCM_SRS_LOL_WIDTH 1u
10474 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOL_SHIFT))&RCM_SRS_LOL_MASK)
10475 #define RCM_SRS_WDOG_MASK 0x20u
10476 #define RCM_SRS_WDOG_SHIFT 5u
10477 #define RCM_SRS_WDOG_WIDTH 1u
10478 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_WDOG_SHIFT))&RCM_SRS_WDOG_MASK)
10479 #define RCM_SRS_PIN_MASK 0x40u
10480 #define RCM_SRS_PIN_SHIFT 6u
10481 #define RCM_SRS_PIN_WIDTH 1u
10482 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_PIN_SHIFT))&RCM_SRS_PIN_MASK)
10483 #define RCM_SRS_POR_MASK 0x80u
10484 #define RCM_SRS_POR_SHIFT 7u
10485 #define RCM_SRS_POR_WIDTH 1u
10486 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_POR_SHIFT))&RCM_SRS_POR_MASK)
10487 #define RCM_SRS_JTAG_MASK 0x100u
10488 #define RCM_SRS_JTAG_SHIFT 8u
10489 #define RCM_SRS_JTAG_WIDTH 1u
10490 #define RCM_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_JTAG_SHIFT))&RCM_SRS_JTAG_MASK)
10491 #define RCM_SRS_LOCKUP_MASK 0x200u
10492 #define RCM_SRS_LOCKUP_SHIFT 9u
10493 #define RCM_SRS_LOCKUP_WIDTH 1u
10494 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOCKUP_SHIFT))&RCM_SRS_LOCKUP_MASK)
10495 #define RCM_SRS_SW_MASK 0x400u
10496 #define RCM_SRS_SW_SHIFT 10u
10497 #define RCM_SRS_SW_WIDTH 1u
10498 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SW_SHIFT))&RCM_SRS_SW_MASK)
10499 #define RCM_SRS_MDM_AP_MASK 0x800u
10500 #define RCM_SRS_MDM_AP_SHIFT 11u
10501 #define RCM_SRS_MDM_AP_WIDTH 1u
10502 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_MDM_AP_SHIFT))&RCM_SRS_MDM_AP_MASK)
10503 #define RCM_SRS_SACKERR_MASK 0x2000u
10504 #define RCM_SRS_SACKERR_SHIFT 13u
10505 #define RCM_SRS_SACKERR_WIDTH 1u
10506 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SACKERR_SHIFT))&RCM_SRS_SACKERR_MASK)
10508 #define RCM_RPC_RSTFLTSRW_MASK 0x3u
10509 #define RCM_RPC_RSTFLTSRW_SHIFT 0u
10510 #define RCM_RPC_RSTFLTSRW_WIDTH 2u
10511 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSRW_SHIFT))&RCM_RPC_RSTFLTSRW_MASK)
10512 #define RCM_RPC_RSTFLTSS_MASK 0x4u
10513 #define RCM_RPC_RSTFLTSS_SHIFT 2u
10514 #define RCM_RPC_RSTFLTSS_WIDTH 1u
10515 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSS_SHIFT))&RCM_RPC_RSTFLTSS_MASK)
10516 #define RCM_RPC_RSTFLTSEL_MASK 0x1F00u
10517 #define RCM_RPC_RSTFLTSEL_SHIFT 8u
10518 #define RCM_RPC_RSTFLTSEL_WIDTH 5u
10519 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSEL_SHIFT))&RCM_RPC_RSTFLTSEL_MASK)
10521 #define RCM_SSRS_SLVD_MASK 0x2u
10522 #define RCM_SSRS_SLVD_SHIFT 1u
10523 #define RCM_SSRS_SLVD_WIDTH 1u
10524 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLVD_SHIFT))&RCM_SSRS_SLVD_MASK)
10525 #define RCM_SSRS_SLOC_MASK 0x4u
10526 #define RCM_SSRS_SLOC_SHIFT 2u
10527 #define RCM_SSRS_SLOC_WIDTH 1u
10528 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOC_SHIFT))&RCM_SSRS_SLOC_MASK)
10529 #define RCM_SSRS_SLOL_MASK 0x8u
10530 #define RCM_SSRS_SLOL_SHIFT 3u
10531 #define RCM_SSRS_SLOL_WIDTH 1u
10532 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOL_SHIFT))&RCM_SSRS_SLOL_MASK)
10533 #define RCM_SSRS_SWDOG_MASK 0x20u
10534 #define RCM_SSRS_SWDOG_SHIFT 5u
10535 #define RCM_SSRS_SWDOG_WIDTH 1u
10536 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SWDOG_SHIFT))&RCM_SSRS_SWDOG_MASK)
10537 #define RCM_SSRS_SPIN_MASK 0x40u
10538 #define RCM_SSRS_SPIN_SHIFT 6u
10539 #define RCM_SSRS_SPIN_WIDTH 1u
10540 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPIN_SHIFT))&RCM_SSRS_SPIN_MASK)
10541 #define RCM_SSRS_SPOR_MASK 0x80u
10542 #define RCM_SSRS_SPOR_SHIFT 7u
10543 #define RCM_SSRS_SPOR_WIDTH 1u
10544 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPOR_SHIFT))&RCM_SSRS_SPOR_MASK)
10545 #define RCM_SSRS_SJTAG_MASK 0x100u
10546 #define RCM_SSRS_SJTAG_SHIFT 8u
10547 #define RCM_SSRS_SJTAG_WIDTH 1u
10548 #define RCM_SSRS_SJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SJTAG_SHIFT))&RCM_SSRS_SJTAG_MASK)
10549 #define RCM_SSRS_SLOCKUP_MASK 0x200u
10550 #define RCM_SSRS_SLOCKUP_SHIFT 9u
10551 #define RCM_SSRS_SLOCKUP_WIDTH 1u
10552 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOCKUP_SHIFT))&RCM_SSRS_SLOCKUP_MASK)
10553 #define RCM_SSRS_SSW_MASK 0x400u
10554 #define RCM_SSRS_SSW_SHIFT 10u
10555 #define RCM_SSRS_SSW_WIDTH 1u
10556 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSW_SHIFT))&RCM_SSRS_SSW_MASK)
10557 #define RCM_SSRS_SMDM_AP_MASK 0x800u
10558 #define RCM_SSRS_SMDM_AP_SHIFT 11u
10559 #define RCM_SSRS_SMDM_AP_WIDTH 1u
10560 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SMDM_AP_SHIFT))&RCM_SSRS_SMDM_AP_MASK)
10561 #define RCM_SSRS_SSACKERR_MASK 0x2000u
10562 #define RCM_SSRS_SSACKERR_SHIFT 13u
10563 #define RCM_SSRS_SSACKERR_WIDTH 1u
10564 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSACKERR_SHIFT))&RCM_SSRS_SSACKERR_MASK)
10566 #define RCM_SRIE_DELAY_MASK 0x3u
10567 #define RCM_SRIE_DELAY_SHIFT 0u
10568 #define RCM_SRIE_DELAY_WIDTH 2u
10569 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_DELAY_SHIFT))&RCM_SRIE_DELAY_MASK)
10570 #define RCM_SRIE_LOC_MASK 0x4u
10571 #define RCM_SRIE_LOC_SHIFT 2u
10572 #define RCM_SRIE_LOC_WIDTH 1u
10573 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOC_SHIFT))&RCM_SRIE_LOC_MASK)
10574 #define RCM_SRIE_LOL_MASK 0x8u
10575 #define RCM_SRIE_LOL_SHIFT 3u
10576 #define RCM_SRIE_LOL_WIDTH 1u
10577 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOL_SHIFT))&RCM_SRIE_LOL_MASK)
10578 #define RCM_SRIE_WDOG_MASK 0x20u
10579 #define RCM_SRIE_WDOG_SHIFT 5u
10580 #define RCM_SRIE_WDOG_WIDTH 1u
10581 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_WDOG_SHIFT))&RCM_SRIE_WDOG_MASK)
10582 #define RCM_SRIE_PIN_MASK 0x40u
10583 #define RCM_SRIE_PIN_SHIFT 6u
10584 #define RCM_SRIE_PIN_WIDTH 1u
10585 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_PIN_SHIFT))&RCM_SRIE_PIN_MASK)
10586 #define RCM_SRIE_GIE_MASK 0x80u
10587 #define RCM_SRIE_GIE_SHIFT 7u
10588 #define RCM_SRIE_GIE_WIDTH 1u
10589 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_GIE_SHIFT))&RCM_SRIE_GIE_MASK)
10590 #define RCM_SRIE_JTAG_MASK 0x100u
10591 #define RCM_SRIE_JTAG_SHIFT 8u
10592 #define RCM_SRIE_JTAG_WIDTH 1u
10593 #define RCM_SRIE_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_JTAG_SHIFT))&RCM_SRIE_JTAG_MASK)
10594 #define RCM_SRIE_LOCKUP_MASK 0x200u
10595 #define RCM_SRIE_LOCKUP_SHIFT 9u
10596 #define RCM_SRIE_LOCKUP_WIDTH 1u
10597 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOCKUP_SHIFT))&RCM_SRIE_LOCKUP_MASK)
10598 #define RCM_SRIE_SW_MASK 0x400u
10599 #define RCM_SRIE_SW_SHIFT 10u
10600 #define RCM_SRIE_SW_WIDTH 1u
10601 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SW_SHIFT))&RCM_SRIE_SW_MASK)
10602 #define RCM_SRIE_MDM_AP_MASK 0x800u
10603 #define RCM_SRIE_MDM_AP_SHIFT 11u
10604 #define RCM_SRIE_MDM_AP_WIDTH 1u
10605 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_MDM_AP_SHIFT))&RCM_SRIE_MDM_AP_MASK)
10606 #define RCM_SRIE_SACKERR_MASK 0x2000u
10607 #define RCM_SRIE_SACKERR_SHIFT 13u
10608 #define RCM_SRIE_SACKERR_WIDTH 1u
10609 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SACKERR_SHIFT))&RCM_SRIE_SACKERR_MASK)
10646 #define RTC_INSTANCE_COUNT (1u)
10651 #define RTC_BASE (0x4003D000u)
10653 #define RTC ((RTC_Type *)RTC_BASE)
10655 #define RTC_BASE_ADDRS { RTC_BASE }
10657 #define RTC_BASE_PTRS { RTC }
10659 #define RTC_IRQS_ARR_COUNT (2u)
10661 #define RTC_IRQS_CH_COUNT (1u)
10663 #define RTC_SECONDS_IRQS_CH_COUNT (1u)
10665 #define RTC_IRQS { RTC_IRQn }
10666 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
10678 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
10679 #define RTC_TSR_TSR_SHIFT 0u
10680 #define RTC_TSR_TSR_WIDTH 32u
10681 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
10683 #define RTC_TPR_TPR_MASK 0xFFFFu
10684 #define RTC_TPR_TPR_SHIFT 0u
10685 #define RTC_TPR_TPR_WIDTH 16u
10686 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
10688 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
10689 #define RTC_TAR_TAR_SHIFT 0u
10690 #define RTC_TAR_TAR_WIDTH 32u
10691 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
10693 #define RTC_TCR_TCR_MASK 0xFFu
10694 #define RTC_TCR_TCR_SHIFT 0u
10695 #define RTC_TCR_TCR_WIDTH 8u
10696 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
10697 #define RTC_TCR_CIR_MASK 0xFF00u
10698 #define RTC_TCR_CIR_SHIFT 8u
10699 #define RTC_TCR_CIR_WIDTH 8u
10700 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
10701 #define RTC_TCR_TCV_MASK 0xFF0000u
10702 #define RTC_TCR_TCV_SHIFT 16u
10703 #define RTC_TCR_TCV_WIDTH 8u
10704 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
10705 #define RTC_TCR_CIC_MASK 0xFF000000u
10706 #define RTC_TCR_CIC_SHIFT 24u
10707 #define RTC_TCR_CIC_WIDTH 8u
10708 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
10710 #define RTC_CR_SWR_MASK 0x1u
10711 #define RTC_CR_SWR_SHIFT 0u
10712 #define RTC_CR_SWR_WIDTH 1u
10713 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
10714 #define RTC_CR_SUP_MASK 0x4u
10715 #define RTC_CR_SUP_SHIFT 2u
10716 #define RTC_CR_SUP_WIDTH 1u
10717 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
10718 #define RTC_CR_UM_MASK 0x8u
10719 #define RTC_CR_UM_SHIFT 3u
10720 #define RTC_CR_UM_WIDTH 1u
10721 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
10722 #define RTC_CR_CPS_MASK 0x20u
10723 #define RTC_CR_CPS_SHIFT 5u
10724 #define RTC_CR_CPS_WIDTH 1u
10725 #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPS_SHIFT))&RTC_CR_CPS_MASK)
10726 #define RTC_CR_LPOS_MASK 0x80u
10727 #define RTC_CR_LPOS_SHIFT 7u
10728 #define RTC_CR_LPOS_WIDTH 1u
10729 #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_LPOS_SHIFT))&RTC_CR_LPOS_MASK)
10730 #define RTC_CR_CPE_MASK 0x1000000u
10731 #define RTC_CR_CPE_SHIFT 24u
10732 #define RTC_CR_CPE_WIDTH 1u
10733 #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPE_SHIFT))&RTC_CR_CPE_MASK)
10735 #define RTC_SR_TIF_MASK 0x1u
10736 #define RTC_SR_TIF_SHIFT 0u
10737 #define RTC_SR_TIF_WIDTH 1u
10738 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
10739 #define RTC_SR_TOF_MASK 0x2u
10740 #define RTC_SR_TOF_SHIFT 1u
10741 #define RTC_SR_TOF_WIDTH 1u
10742 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
10743 #define RTC_SR_TAF_MASK 0x4u
10744 #define RTC_SR_TAF_SHIFT 2u
10745 #define RTC_SR_TAF_WIDTH 1u
10746 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
10747 #define RTC_SR_TCE_MASK 0x10u
10748 #define RTC_SR_TCE_SHIFT 4u
10749 #define RTC_SR_TCE_WIDTH 1u
10750 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
10752 #define RTC_LR_TCL_MASK 0x8u
10753 #define RTC_LR_TCL_SHIFT 3u
10754 #define RTC_LR_TCL_WIDTH 1u
10755 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
10756 #define RTC_LR_CRL_MASK 0x10u
10757 #define RTC_LR_CRL_SHIFT 4u
10758 #define RTC_LR_CRL_WIDTH 1u
10759 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
10760 #define RTC_LR_SRL_MASK 0x20u
10761 #define RTC_LR_SRL_SHIFT 5u
10762 #define RTC_LR_SRL_WIDTH 1u
10763 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
10764 #define RTC_LR_LRL_MASK 0x40u
10765 #define RTC_LR_LRL_SHIFT 6u
10766 #define RTC_LR_LRL_WIDTH 1u
10767 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
10769 #define RTC_IER_TIIE_MASK 0x1u
10770 #define RTC_IER_TIIE_SHIFT 0u
10771 #define RTC_IER_TIIE_WIDTH 1u
10772 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
10773 #define RTC_IER_TOIE_MASK 0x2u
10774 #define RTC_IER_TOIE_SHIFT 1u
10775 #define RTC_IER_TOIE_WIDTH 1u
10776 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
10777 #define RTC_IER_TAIE_MASK 0x4u
10778 #define RTC_IER_TAIE_SHIFT 2u
10779 #define RTC_IER_TAIE_WIDTH 1u
10780 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
10781 #define RTC_IER_TSIE_MASK 0x10u
10782 #define RTC_IER_TSIE_SHIFT 4u
10783 #define RTC_IER_TSIE_WIDTH 1u
10784 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
10785 #define RTC_IER_TSIC_MASK 0x70000u
10786 #define RTC_IER_TSIC_SHIFT 16u
10787 #define RTC_IER_TSIC_WIDTH 3u
10788 #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
10811 #define S32_NVIC_ISER_COUNT 4u
10812 #define S32_NVIC_ICER_COUNT 4u
10813 #define S32_NVIC_ISPR_COUNT 4u
10814 #define S32_NVIC_ICPR_COUNT 4u
10815 #define S32_NVIC_IABR_COUNT 4u
10816 #define S32_NVIC_IP_COUNT 123u
10821 uint8_t RESERVED_0[112];
10823 uint8_t RESERVED_1[112];
10825 uint8_t RESERVED_2[112];
10827 uint8_t RESERVED_3[112];
10829 uint8_t RESERVED_4[240];
10831 uint8_t RESERVED_5[2693];
10836 #define S32_NVIC_INSTANCE_COUNT (1u)
10841 #define S32_NVIC_BASE (0xE000E100u)
10843 #define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE)
10845 #define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE }
10847 #define S32_NVIC_BASE_PTRS { S32_NVIC }
10849 #define S32_NVIC_IRQS_ARR_COUNT (1u)
10851 #define S32_NVIC_IRQS_CH_COUNT (1u)
10853 #define S32_NVIC_IRQS { SWI_IRQn }
10865 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
10866 #define S32_NVIC_ISER_SETENA_SHIFT 0u
10867 #define S32_NVIC_ISER_SETENA_WIDTH 32u
10868 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK)
10870 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu
10871 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
10872 #define S32_NVIC_ICER_CLRENA_WIDTH 32u
10873 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK)
10875 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu
10876 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
10877 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u
10878 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK)
10880 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu
10881 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
10882 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u
10883 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK)
10885 #define S32_NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu
10886 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
10887 #define S32_NVIC_IABR_ACTIVE_WIDTH 32u
10888 #define S32_NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IABR_ACTIVE_SHIFT))&S32_NVIC_IABR_ACTIVE_MASK)
10890 #define S32_NVIC_IP_PRI0_MASK 0xFFu
10891 #define S32_NVIC_IP_PRI0_SHIFT 0u
10892 #define S32_NVIC_IP_PRI0_WIDTH 8u
10893 #define S32_NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI0_SHIFT))&S32_NVIC_IP_PRI0_MASK)
10894 #define S32_NVIC_IP_PRI1_MASK 0xFFu
10895 #define S32_NVIC_IP_PRI1_SHIFT 0u
10896 #define S32_NVIC_IP_PRI1_WIDTH 8u
10897 #define S32_NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI1_SHIFT))&S32_NVIC_IP_PRI1_MASK)
10898 #define S32_NVIC_IP_PRI2_MASK 0xFFu
10899 #define S32_NVIC_IP_PRI2_SHIFT 0u
10900 #define S32_NVIC_IP_PRI2_WIDTH 8u
10901 #define S32_NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI2_SHIFT))&S32_NVIC_IP_PRI2_MASK)
10902 #define S32_NVIC_IP_PRI3_MASK 0xFFu
10903 #define S32_NVIC_IP_PRI3_SHIFT 0u
10904 #define S32_NVIC_IP_PRI3_WIDTH 8u
10905 #define S32_NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI3_SHIFT))&S32_NVIC_IP_PRI3_MASK)
10906 #define S32_NVIC_IP_PRI4_MASK 0xFFu
10907 #define S32_NVIC_IP_PRI4_SHIFT 0u
10908 #define S32_NVIC_IP_PRI4_WIDTH 8u
10909 #define S32_NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI4_SHIFT))&S32_NVIC_IP_PRI4_MASK)
10910 #define S32_NVIC_IP_PRI5_MASK 0xFFu
10911 #define S32_NVIC_IP_PRI5_SHIFT 0u
10912 #define S32_NVIC_IP_PRI5_WIDTH 8u
10913 #define S32_NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI5_SHIFT))&S32_NVIC_IP_PRI5_MASK)
10914 #define S32_NVIC_IP_PRI6_MASK 0xFFu
10915 #define S32_NVIC_IP_PRI6_SHIFT 0u
10916 #define S32_NVIC_IP_PRI6_WIDTH 8u
10917 #define S32_NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI6_SHIFT))&S32_NVIC_IP_PRI6_MASK)
10918 #define S32_NVIC_IP_PRI7_MASK 0xFFu
10919 #define S32_NVIC_IP_PRI7_SHIFT 0u
10920 #define S32_NVIC_IP_PRI7_WIDTH 8u
10921 #define S32_NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI7_SHIFT))&S32_NVIC_IP_PRI7_MASK)
10922 #define S32_NVIC_IP_PRI8_MASK 0xFFu
10923 #define S32_NVIC_IP_PRI8_SHIFT 0u
10924 #define S32_NVIC_IP_PRI8_WIDTH 8u
10925 #define S32_NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI8_SHIFT))&S32_NVIC_IP_PRI8_MASK)
10926 #define S32_NVIC_IP_PRI9_MASK 0xFFu
10927 #define S32_NVIC_IP_PRI9_SHIFT 0u
10928 #define S32_NVIC_IP_PRI9_WIDTH 8u
10929 #define S32_NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI9_SHIFT))&S32_NVIC_IP_PRI9_MASK)
10930 #define S32_NVIC_IP_PRI10_MASK 0xFFu
10931 #define S32_NVIC_IP_PRI10_SHIFT 0u
10932 #define S32_NVIC_IP_PRI10_WIDTH 8u
10933 #define S32_NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI10_SHIFT))&S32_NVIC_IP_PRI10_MASK)
10934 #define S32_NVIC_IP_PRI11_MASK 0xFFu
10935 #define S32_NVIC_IP_PRI11_SHIFT 0u
10936 #define S32_NVIC_IP_PRI11_WIDTH 8u
10937 #define S32_NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI11_SHIFT))&S32_NVIC_IP_PRI11_MASK)
10938 #define S32_NVIC_IP_PRI12_MASK 0xFFu
10939 #define S32_NVIC_IP_PRI12_SHIFT 0u
10940 #define S32_NVIC_IP_PRI12_WIDTH 8u
10941 #define S32_NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI12_SHIFT))&S32_NVIC_IP_PRI12_MASK)
10942 #define S32_NVIC_IP_PRI13_MASK 0xFFu
10943 #define S32_NVIC_IP_PRI13_SHIFT 0u
10944 #define S32_NVIC_IP_PRI13_WIDTH 8u
10945 #define S32_NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI13_SHIFT))&S32_NVIC_IP_PRI13_MASK)
10946 #define S32_NVIC_IP_PRI14_MASK 0xFFu
10947 #define S32_NVIC_IP_PRI14_SHIFT 0u
10948 #define S32_NVIC_IP_PRI14_WIDTH 8u
10949 #define S32_NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI14_SHIFT))&S32_NVIC_IP_PRI14_MASK)
10950 #define S32_NVIC_IP_PRI15_MASK 0xFFu
10951 #define S32_NVIC_IP_PRI15_SHIFT 0u
10952 #define S32_NVIC_IP_PRI15_WIDTH 8u
10953 #define S32_NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI15_SHIFT))&S32_NVIC_IP_PRI15_MASK)
10954 #define S32_NVIC_IP_PRI16_MASK 0xFFu
10955 #define S32_NVIC_IP_PRI16_SHIFT 0u
10956 #define S32_NVIC_IP_PRI16_WIDTH 8u
10957 #define S32_NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI16_SHIFT))&S32_NVIC_IP_PRI16_MASK)
10958 #define S32_NVIC_IP_PRI17_MASK 0xFFu
10959 #define S32_NVIC_IP_PRI17_SHIFT 0u
10960 #define S32_NVIC_IP_PRI17_WIDTH 8u
10961 #define S32_NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI17_SHIFT))&S32_NVIC_IP_PRI17_MASK)
10962 #define S32_NVIC_IP_PRI18_MASK 0xFFu
10963 #define S32_NVIC_IP_PRI18_SHIFT 0u
10964 #define S32_NVIC_IP_PRI18_WIDTH 8u
10965 #define S32_NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI18_SHIFT))&S32_NVIC_IP_PRI18_MASK)
10966 #define S32_NVIC_IP_PRI19_MASK 0xFFu
10967 #define S32_NVIC_IP_PRI19_SHIFT 0u
10968 #define S32_NVIC_IP_PRI19_WIDTH 8u
10969 #define S32_NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI19_SHIFT))&S32_NVIC_IP_PRI19_MASK)
10970 #define S32_NVIC_IP_PRI20_MASK 0xFFu
10971 #define S32_NVIC_IP_PRI20_SHIFT 0u
10972 #define S32_NVIC_IP_PRI20_WIDTH 8u
10973 #define S32_NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI20_SHIFT))&S32_NVIC_IP_PRI20_MASK)
10974 #define S32_NVIC_IP_PRI21_MASK 0xFFu
10975 #define S32_NVIC_IP_PRI21_SHIFT 0u
10976 #define S32_NVIC_IP_PRI21_WIDTH 8u
10977 #define S32_NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI21_SHIFT))&S32_NVIC_IP_PRI21_MASK)
10978 #define S32_NVIC_IP_PRI22_MASK 0xFFu
10979 #define S32_NVIC_IP_PRI22_SHIFT 0u
10980 #define S32_NVIC_IP_PRI22_WIDTH 8u
10981 #define S32_NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI22_SHIFT))&S32_NVIC_IP_PRI22_MASK)
10982 #define S32_NVIC_IP_PRI23_MASK 0xFFu
10983 #define S32_NVIC_IP_PRI23_SHIFT 0u
10984 #define S32_NVIC_IP_PRI23_WIDTH 8u
10985 #define S32_NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI23_SHIFT))&S32_NVIC_IP_PRI23_MASK)
10986 #define S32_NVIC_IP_PRI24_MASK 0xFFu
10987 #define S32_NVIC_IP_PRI24_SHIFT 0u
10988 #define S32_NVIC_IP_PRI24_WIDTH 8u
10989 #define S32_NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI24_SHIFT))&S32_NVIC_IP_PRI24_MASK)
10990 #define S32_NVIC_IP_PRI25_MASK 0xFFu
10991 #define S32_NVIC_IP_PRI25_SHIFT 0u
10992 #define S32_NVIC_IP_PRI25_WIDTH 8u
10993 #define S32_NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI25_SHIFT))&S32_NVIC_IP_PRI25_MASK)
10994 #define S32_NVIC_IP_PRI26_MASK 0xFFu
10995 #define S32_NVIC_IP_PRI26_SHIFT 0u
10996 #define S32_NVIC_IP_PRI26_WIDTH 8u
10997 #define S32_NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI26_SHIFT))&S32_NVIC_IP_PRI26_MASK)
10998 #define S32_NVIC_IP_PRI27_MASK 0xFFu
10999 #define S32_NVIC_IP_PRI27_SHIFT 0u
11000 #define S32_NVIC_IP_PRI27_WIDTH 8u
11001 #define S32_NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI27_SHIFT))&S32_NVIC_IP_PRI27_MASK)
11002 #define S32_NVIC_IP_PRI28_MASK 0xFFu
11003 #define S32_NVIC_IP_PRI28_SHIFT 0u
11004 #define S32_NVIC_IP_PRI28_WIDTH 8u
11005 #define S32_NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI28_SHIFT))&S32_NVIC_IP_PRI28_MASK)
11006 #define S32_NVIC_IP_PRI29_MASK 0xFFu
11007 #define S32_NVIC_IP_PRI29_SHIFT 0u
11008 #define S32_NVIC_IP_PRI29_WIDTH 8u
11009 #define S32_NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI29_SHIFT))&S32_NVIC_IP_PRI29_MASK)
11010 #define S32_NVIC_IP_PRI30_MASK 0xFFu
11011 #define S32_NVIC_IP_PRI30_SHIFT 0u
11012 #define S32_NVIC_IP_PRI30_WIDTH 8u
11013 #define S32_NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI30_SHIFT))&S32_NVIC_IP_PRI30_MASK)
11014 #define S32_NVIC_IP_PRI31_MASK 0xFFu
11015 #define S32_NVIC_IP_PRI31_SHIFT 0u
11016 #define S32_NVIC_IP_PRI31_WIDTH 8u
11017 #define S32_NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI31_SHIFT))&S32_NVIC_IP_PRI31_MASK)
11018 #define S32_NVIC_IP_PRI32_MASK 0xFFu
11019 #define S32_NVIC_IP_PRI32_SHIFT 0u
11020 #define S32_NVIC_IP_PRI32_WIDTH 8u
11021 #define S32_NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI32_SHIFT))&S32_NVIC_IP_PRI32_MASK)
11022 #define S32_NVIC_IP_PRI33_MASK 0xFFu
11023 #define S32_NVIC_IP_PRI33_SHIFT 0u
11024 #define S32_NVIC_IP_PRI33_WIDTH 8u
11025 #define S32_NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI33_SHIFT))&S32_NVIC_IP_PRI33_MASK)
11026 #define S32_NVIC_IP_PRI34_MASK 0xFFu
11027 #define S32_NVIC_IP_PRI34_SHIFT 0u
11028 #define S32_NVIC_IP_PRI34_WIDTH 8u
11029 #define S32_NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI34_SHIFT))&S32_NVIC_IP_PRI34_MASK)
11030 #define S32_NVIC_IP_PRI35_MASK 0xFFu
11031 #define S32_NVIC_IP_PRI35_SHIFT 0u
11032 #define S32_NVIC_IP_PRI35_WIDTH 8u
11033 #define S32_NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI35_SHIFT))&S32_NVIC_IP_PRI35_MASK)
11034 #define S32_NVIC_IP_PRI36_MASK 0xFFu
11035 #define S32_NVIC_IP_PRI36_SHIFT 0u
11036 #define S32_NVIC_IP_PRI36_WIDTH 8u
11037 #define S32_NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI36_SHIFT))&S32_NVIC_IP_PRI36_MASK)
11038 #define S32_NVIC_IP_PRI37_MASK 0xFFu
11039 #define S32_NVIC_IP_PRI37_SHIFT 0u
11040 #define S32_NVIC_IP_PRI37_WIDTH 8u
11041 #define S32_NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI37_SHIFT))&S32_NVIC_IP_PRI37_MASK)
11042 #define S32_NVIC_IP_PRI38_MASK 0xFFu
11043 #define S32_NVIC_IP_PRI38_SHIFT 0u
11044 #define S32_NVIC_IP_PRI38_WIDTH 8u
11045 #define S32_NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI38_SHIFT))&S32_NVIC_IP_PRI38_MASK)
11046 #define S32_NVIC_IP_PRI39_MASK 0xFFu
11047 #define S32_NVIC_IP_PRI39_SHIFT 0u
11048 #define S32_NVIC_IP_PRI39_WIDTH 8u
11049 #define S32_NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI39_SHIFT))&S32_NVIC_IP_PRI39_MASK)
11050 #define S32_NVIC_IP_PRI40_MASK 0xFFu
11051 #define S32_NVIC_IP_PRI40_SHIFT 0u
11052 #define S32_NVIC_IP_PRI40_WIDTH 8u
11053 #define S32_NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI40_SHIFT))&S32_NVIC_IP_PRI40_MASK)
11054 #define S32_NVIC_IP_PRI41_MASK 0xFFu
11055 #define S32_NVIC_IP_PRI41_SHIFT 0u
11056 #define S32_NVIC_IP_PRI41_WIDTH 8u
11057 #define S32_NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI41_SHIFT))&S32_NVIC_IP_PRI41_MASK)
11058 #define S32_NVIC_IP_PRI42_MASK 0xFFu
11059 #define S32_NVIC_IP_PRI42_SHIFT 0u
11060 #define S32_NVIC_IP_PRI42_WIDTH 8u
11061 #define S32_NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI42_SHIFT))&S32_NVIC_IP_PRI42_MASK)
11062 #define S32_NVIC_IP_PRI43_MASK 0xFFu
11063 #define S32_NVIC_IP_PRI43_SHIFT 0u
11064 #define S32_NVIC_IP_PRI43_WIDTH 8u
11065 #define S32_NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI43_SHIFT))&S32_NVIC_IP_PRI43_MASK)
11066 #define S32_NVIC_IP_PRI44_MASK 0xFFu
11067 #define S32_NVIC_IP_PRI44_SHIFT 0u
11068 #define S32_NVIC_IP_PRI44_WIDTH 8u
11069 #define S32_NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI44_SHIFT))&S32_NVIC_IP_PRI44_MASK)
11070 #define S32_NVIC_IP_PRI45_MASK 0xFFu
11071 #define S32_NVIC_IP_PRI45_SHIFT 0u
11072 #define S32_NVIC_IP_PRI45_WIDTH 8u
11073 #define S32_NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI45_SHIFT))&S32_NVIC_IP_PRI45_MASK)
11074 #define S32_NVIC_IP_PRI46_MASK 0xFFu
11075 #define S32_NVIC_IP_PRI46_SHIFT 0u
11076 #define S32_NVIC_IP_PRI46_WIDTH 8u
11077 #define S32_NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI46_SHIFT))&S32_NVIC_IP_PRI46_MASK)
11078 #define S32_NVIC_IP_PRI47_MASK 0xFFu
11079 #define S32_NVIC_IP_PRI47_SHIFT 0u
11080 #define S32_NVIC_IP_PRI47_WIDTH 8u
11081 #define S32_NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI47_SHIFT))&S32_NVIC_IP_PRI47_MASK)
11082 #define S32_NVIC_IP_PRI48_MASK 0xFFu
11083 #define S32_NVIC_IP_PRI48_SHIFT 0u
11084 #define S32_NVIC_IP_PRI48_WIDTH 8u
11085 #define S32_NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI48_SHIFT))&S32_NVIC_IP_PRI48_MASK)
11086 #define S32_NVIC_IP_PRI49_MASK 0xFFu
11087 #define S32_NVIC_IP_PRI49_SHIFT 0u
11088 #define S32_NVIC_IP_PRI49_WIDTH 8u
11089 #define S32_NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI49_SHIFT))&S32_NVIC_IP_PRI49_MASK)
11090 #define S32_NVIC_IP_PRI50_MASK 0xFFu
11091 #define S32_NVIC_IP_PRI50_SHIFT 0u
11092 #define S32_NVIC_IP_PRI50_WIDTH 8u
11093 #define S32_NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI50_SHIFT))&S32_NVIC_IP_PRI50_MASK)
11094 #define S32_NVIC_IP_PRI51_MASK 0xFFu
11095 #define S32_NVIC_IP_PRI51_SHIFT 0u
11096 #define S32_NVIC_IP_PRI51_WIDTH 8u
11097 #define S32_NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI51_SHIFT))&S32_NVIC_IP_PRI51_MASK)
11098 #define S32_NVIC_IP_PRI52_MASK 0xFFu
11099 #define S32_NVIC_IP_PRI52_SHIFT 0u
11100 #define S32_NVIC_IP_PRI52_WIDTH 8u
11101 #define S32_NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI52_SHIFT))&S32_NVIC_IP_PRI52_MASK)
11102 #define S32_NVIC_IP_PRI53_MASK 0xFFu
11103 #define S32_NVIC_IP_PRI53_SHIFT 0u
11104 #define S32_NVIC_IP_PRI53_WIDTH 8u
11105 #define S32_NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI53_SHIFT))&S32_NVIC_IP_PRI53_MASK)
11106 #define S32_NVIC_IP_PRI54_MASK 0xFFu
11107 #define S32_NVIC_IP_PRI54_SHIFT 0u
11108 #define S32_NVIC_IP_PRI54_WIDTH 8u
11109 #define S32_NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI54_SHIFT))&S32_NVIC_IP_PRI54_MASK)
11110 #define S32_NVIC_IP_PRI55_MASK 0xFFu
11111 #define S32_NVIC_IP_PRI55_SHIFT 0u
11112 #define S32_NVIC_IP_PRI55_WIDTH 8u
11113 #define S32_NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI55_SHIFT))&S32_NVIC_IP_PRI55_MASK)
11114 #define S32_NVIC_IP_PRI56_MASK 0xFFu
11115 #define S32_NVIC_IP_PRI56_SHIFT 0u
11116 #define S32_NVIC_IP_PRI56_WIDTH 8u
11117 #define S32_NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI56_SHIFT))&S32_NVIC_IP_PRI56_MASK)
11118 #define S32_NVIC_IP_PRI57_MASK 0xFFu
11119 #define S32_NVIC_IP_PRI57_SHIFT 0u
11120 #define S32_NVIC_IP_PRI57_WIDTH 8u
11121 #define S32_NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI57_SHIFT))&S32_NVIC_IP_PRI57_MASK)
11122 #define S32_NVIC_IP_PRI58_MASK 0xFFu
11123 #define S32_NVIC_IP_PRI58_SHIFT 0u
11124 #define S32_NVIC_IP_PRI58_WIDTH 8u
11125 #define S32_NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI58_SHIFT))&S32_NVIC_IP_PRI58_MASK)
11126 #define S32_NVIC_IP_PRI59_MASK 0xFFu
11127 #define S32_NVIC_IP_PRI59_SHIFT 0u
11128 #define S32_NVIC_IP_PRI59_WIDTH 8u
11129 #define S32_NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI59_SHIFT))&S32_NVIC_IP_PRI59_MASK)
11130 #define S32_NVIC_IP_PRI60_MASK 0xFFu
11131 #define S32_NVIC_IP_PRI60_SHIFT 0u
11132 #define S32_NVIC_IP_PRI60_WIDTH 8u
11133 #define S32_NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI60_SHIFT))&S32_NVIC_IP_PRI60_MASK)
11134 #define S32_NVIC_IP_PRI61_MASK 0xFFu
11135 #define S32_NVIC_IP_PRI61_SHIFT 0u
11136 #define S32_NVIC_IP_PRI61_WIDTH 8u
11137 #define S32_NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI61_SHIFT))&S32_NVIC_IP_PRI61_MASK)
11138 #define S32_NVIC_IP_PRI62_MASK 0xFFu
11139 #define S32_NVIC_IP_PRI62_SHIFT 0u
11140 #define S32_NVIC_IP_PRI62_WIDTH 8u
11141 #define S32_NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI62_SHIFT))&S32_NVIC_IP_PRI62_MASK)
11142 #define S32_NVIC_IP_PRI63_MASK 0xFFu
11143 #define S32_NVIC_IP_PRI63_SHIFT 0u
11144 #define S32_NVIC_IP_PRI63_WIDTH 8u
11145 #define S32_NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI63_SHIFT))&S32_NVIC_IP_PRI63_MASK)
11146 #define S32_NVIC_IP_PRI64_MASK 0xFFu
11147 #define S32_NVIC_IP_PRI64_SHIFT 0u
11148 #define S32_NVIC_IP_PRI64_WIDTH 8u
11149 #define S32_NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI64_SHIFT))&S32_NVIC_IP_PRI64_MASK)
11150 #define S32_NVIC_IP_PRI65_MASK 0xFFu
11151 #define S32_NVIC_IP_PRI65_SHIFT 0u
11152 #define S32_NVIC_IP_PRI65_WIDTH 8u
11153 #define S32_NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI65_SHIFT))&S32_NVIC_IP_PRI65_MASK)
11154 #define S32_NVIC_IP_PRI66_MASK 0xFFu
11155 #define S32_NVIC_IP_PRI66_SHIFT 0u
11156 #define S32_NVIC_IP_PRI66_WIDTH 8u
11157 #define S32_NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI66_SHIFT))&S32_NVIC_IP_PRI66_MASK)
11158 #define S32_NVIC_IP_PRI67_MASK 0xFFu
11159 #define S32_NVIC_IP_PRI67_SHIFT 0u
11160 #define S32_NVIC_IP_PRI67_WIDTH 8u
11161 #define S32_NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI67_SHIFT))&S32_NVIC_IP_PRI67_MASK)
11162 #define S32_NVIC_IP_PRI68_MASK 0xFFu
11163 #define S32_NVIC_IP_PRI68_SHIFT 0u
11164 #define S32_NVIC_IP_PRI68_WIDTH 8u
11165 #define S32_NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI68_SHIFT))&S32_NVIC_IP_PRI68_MASK)
11166 #define S32_NVIC_IP_PRI69_MASK 0xFFu
11167 #define S32_NVIC_IP_PRI69_SHIFT 0u
11168 #define S32_NVIC_IP_PRI69_WIDTH 8u
11169 #define S32_NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI69_SHIFT))&S32_NVIC_IP_PRI69_MASK)
11170 #define S32_NVIC_IP_PRI70_MASK 0xFFu
11171 #define S32_NVIC_IP_PRI70_SHIFT 0u
11172 #define S32_NVIC_IP_PRI70_WIDTH 8u
11173 #define S32_NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI70_SHIFT))&S32_NVIC_IP_PRI70_MASK)
11174 #define S32_NVIC_IP_PRI71_MASK 0xFFu
11175 #define S32_NVIC_IP_PRI71_SHIFT 0u
11176 #define S32_NVIC_IP_PRI71_WIDTH 8u
11177 #define S32_NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI71_SHIFT))&S32_NVIC_IP_PRI71_MASK)
11178 #define S32_NVIC_IP_PRI72_MASK 0xFFu
11179 #define S32_NVIC_IP_PRI72_SHIFT 0u
11180 #define S32_NVIC_IP_PRI72_WIDTH 8u
11181 #define S32_NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI72_SHIFT))&S32_NVIC_IP_PRI72_MASK)
11182 #define S32_NVIC_IP_PRI73_MASK 0xFFu
11183 #define S32_NVIC_IP_PRI73_SHIFT 0u
11184 #define S32_NVIC_IP_PRI73_WIDTH 8u
11185 #define S32_NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI73_SHIFT))&S32_NVIC_IP_PRI73_MASK)
11186 #define S32_NVIC_IP_PRI74_MASK 0xFFu
11187 #define S32_NVIC_IP_PRI74_SHIFT 0u
11188 #define S32_NVIC_IP_PRI74_WIDTH 8u
11189 #define S32_NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI74_SHIFT))&S32_NVIC_IP_PRI74_MASK)
11190 #define S32_NVIC_IP_PRI75_MASK 0xFFu
11191 #define S32_NVIC_IP_PRI75_SHIFT 0u
11192 #define S32_NVIC_IP_PRI75_WIDTH 8u
11193 #define S32_NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI75_SHIFT))&S32_NVIC_IP_PRI75_MASK)
11194 #define S32_NVIC_IP_PRI76_MASK 0xFFu
11195 #define S32_NVIC_IP_PRI76_SHIFT 0u
11196 #define S32_NVIC_IP_PRI76_WIDTH 8u
11197 #define S32_NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI76_SHIFT))&S32_NVIC_IP_PRI76_MASK)
11198 #define S32_NVIC_IP_PRI77_MASK 0xFFu
11199 #define S32_NVIC_IP_PRI77_SHIFT 0u
11200 #define S32_NVIC_IP_PRI77_WIDTH 8u
11201 #define S32_NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI77_SHIFT))&S32_NVIC_IP_PRI77_MASK)
11202 #define S32_NVIC_IP_PRI78_MASK 0xFFu
11203 #define S32_NVIC_IP_PRI78_SHIFT 0u
11204 #define S32_NVIC_IP_PRI78_WIDTH 8u
11205 #define S32_NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI78_SHIFT))&S32_NVIC_IP_PRI78_MASK)
11206 #define S32_NVIC_IP_PRI79_MASK 0xFFu
11207 #define S32_NVIC_IP_PRI79_SHIFT 0u
11208 #define S32_NVIC_IP_PRI79_WIDTH 8u
11209 #define S32_NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI79_SHIFT))&S32_NVIC_IP_PRI79_MASK)
11210 #define S32_NVIC_IP_PRI80_MASK 0xFFu
11211 #define S32_NVIC_IP_PRI80_SHIFT 0u
11212 #define S32_NVIC_IP_PRI80_WIDTH 8u
11213 #define S32_NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI80_SHIFT))&S32_NVIC_IP_PRI80_MASK)
11214 #define S32_NVIC_IP_PRI81_MASK 0xFFu
11215 #define S32_NVIC_IP_PRI81_SHIFT 0u
11216 #define S32_NVIC_IP_PRI81_WIDTH 8u
11217 #define S32_NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI81_SHIFT))&S32_NVIC_IP_PRI81_MASK)
11218 #define S32_NVIC_IP_PRI82_MASK 0xFFu
11219 #define S32_NVIC_IP_PRI82_SHIFT 0u
11220 #define S32_NVIC_IP_PRI82_WIDTH 8u
11221 #define S32_NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI82_SHIFT))&S32_NVIC_IP_PRI82_MASK)
11222 #define S32_NVIC_IP_PRI83_MASK 0xFFu
11223 #define S32_NVIC_IP_PRI83_SHIFT 0u
11224 #define S32_NVIC_IP_PRI83_WIDTH 8u
11225 #define S32_NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI83_SHIFT))&S32_NVIC_IP_PRI83_MASK)
11226 #define S32_NVIC_IP_PRI84_MASK 0xFFu
11227 #define S32_NVIC_IP_PRI84_SHIFT 0u
11228 #define S32_NVIC_IP_PRI84_WIDTH 8u
11229 #define S32_NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI84_SHIFT))&S32_NVIC_IP_PRI84_MASK)
11230 #define S32_NVIC_IP_PRI85_MASK 0xFFu
11231 #define S32_NVIC_IP_PRI85_SHIFT 0u
11232 #define S32_NVIC_IP_PRI85_WIDTH 8u
11233 #define S32_NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI85_SHIFT))&S32_NVIC_IP_PRI85_MASK)
11234 #define S32_NVIC_IP_PRI86_MASK 0xFFu
11235 #define S32_NVIC_IP_PRI86_SHIFT 0u
11236 #define S32_NVIC_IP_PRI86_WIDTH 8u
11237 #define S32_NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI86_SHIFT))&S32_NVIC_IP_PRI86_MASK)
11238 #define S32_NVIC_IP_PRI87_MASK 0xFFu
11239 #define S32_NVIC_IP_PRI87_SHIFT 0u
11240 #define S32_NVIC_IP_PRI87_WIDTH 8u
11241 #define S32_NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI87_SHIFT))&S32_NVIC_IP_PRI87_MASK)
11242 #define S32_NVIC_IP_PRI88_MASK 0xFFu
11243 #define S32_NVIC_IP_PRI88_SHIFT 0u
11244 #define S32_NVIC_IP_PRI88_WIDTH 8u
11245 #define S32_NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI88_SHIFT))&S32_NVIC_IP_PRI88_MASK)
11246 #define S32_NVIC_IP_PRI89_MASK 0xFFu
11247 #define S32_NVIC_IP_PRI89_SHIFT 0u
11248 #define S32_NVIC_IP_PRI89_WIDTH 8u
11249 #define S32_NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI89_SHIFT))&S32_NVIC_IP_PRI89_MASK)
11250 #define S32_NVIC_IP_PRI90_MASK 0xFFu
11251 #define S32_NVIC_IP_PRI90_SHIFT 0u
11252 #define S32_NVIC_IP_PRI90_WIDTH 8u
11253 #define S32_NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI90_SHIFT))&S32_NVIC_IP_PRI90_MASK)
11254 #define S32_NVIC_IP_PRI91_MASK 0xFFu
11255 #define S32_NVIC_IP_PRI91_SHIFT 0u
11256 #define S32_NVIC_IP_PRI91_WIDTH 8u
11257 #define S32_NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI91_SHIFT))&S32_NVIC_IP_PRI91_MASK)
11258 #define S32_NVIC_IP_PRI92_MASK 0xFFu
11259 #define S32_NVIC_IP_PRI92_SHIFT 0u
11260 #define S32_NVIC_IP_PRI92_WIDTH 8u
11261 #define S32_NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI92_SHIFT))&S32_NVIC_IP_PRI92_MASK)
11262 #define S32_NVIC_IP_PRI93_MASK 0xFFu
11263 #define S32_NVIC_IP_PRI93_SHIFT 0u
11264 #define S32_NVIC_IP_PRI93_WIDTH 8u
11265 #define S32_NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI93_SHIFT))&S32_NVIC_IP_PRI93_MASK)
11266 #define S32_NVIC_IP_PRI94_MASK 0xFFu
11267 #define S32_NVIC_IP_PRI94_SHIFT 0u
11268 #define S32_NVIC_IP_PRI94_WIDTH 8u
11269 #define S32_NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI94_SHIFT))&S32_NVIC_IP_PRI94_MASK)
11270 #define S32_NVIC_IP_PRI95_MASK 0xFFu
11271 #define S32_NVIC_IP_PRI95_SHIFT 0u
11272 #define S32_NVIC_IP_PRI95_WIDTH 8u
11273 #define S32_NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI95_SHIFT))&S32_NVIC_IP_PRI95_MASK)
11274 #define S32_NVIC_IP_PRI96_MASK 0xFFu
11275 #define S32_NVIC_IP_PRI96_SHIFT 0u
11276 #define S32_NVIC_IP_PRI96_WIDTH 8u
11277 #define S32_NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI96_SHIFT))&S32_NVIC_IP_PRI96_MASK)
11278 #define S32_NVIC_IP_PRI97_MASK 0xFFu
11279 #define S32_NVIC_IP_PRI97_SHIFT 0u
11280 #define S32_NVIC_IP_PRI97_WIDTH 8u
11281 #define S32_NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI97_SHIFT))&S32_NVIC_IP_PRI97_MASK)
11282 #define S32_NVIC_IP_PRI98_MASK 0xFFu
11283 #define S32_NVIC_IP_PRI98_SHIFT 0u
11284 #define S32_NVIC_IP_PRI98_WIDTH 8u
11285 #define S32_NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI98_SHIFT))&S32_NVIC_IP_PRI98_MASK)
11286 #define S32_NVIC_IP_PRI99_MASK 0xFFu
11287 #define S32_NVIC_IP_PRI99_SHIFT 0u
11288 #define S32_NVIC_IP_PRI99_WIDTH 8u
11289 #define S32_NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI99_SHIFT))&S32_NVIC_IP_PRI99_MASK)
11290 #define S32_NVIC_IP_PRI100_MASK 0xFFu
11291 #define S32_NVIC_IP_PRI100_SHIFT 0u
11292 #define S32_NVIC_IP_PRI100_WIDTH 8u
11293 #define S32_NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI100_SHIFT))&S32_NVIC_IP_PRI100_MASK)
11294 #define S32_NVIC_IP_PRI101_MASK 0xFFu
11295 #define S32_NVIC_IP_PRI101_SHIFT 0u
11296 #define S32_NVIC_IP_PRI101_WIDTH 8u
11297 #define S32_NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI101_SHIFT))&S32_NVIC_IP_PRI101_MASK)
11298 #define S32_NVIC_IP_PRI102_MASK 0xFFu
11299 #define S32_NVIC_IP_PRI102_SHIFT 0u
11300 #define S32_NVIC_IP_PRI102_WIDTH 8u
11301 #define S32_NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI102_SHIFT))&S32_NVIC_IP_PRI102_MASK)
11302 #define S32_NVIC_IP_PRI103_MASK 0xFFu
11303 #define S32_NVIC_IP_PRI103_SHIFT 0u
11304 #define S32_NVIC_IP_PRI103_WIDTH 8u
11305 #define S32_NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI103_SHIFT))&S32_NVIC_IP_PRI103_MASK)
11306 #define S32_NVIC_IP_PRI104_MASK 0xFFu
11307 #define S32_NVIC_IP_PRI104_SHIFT 0u
11308 #define S32_NVIC_IP_PRI104_WIDTH 8u
11309 #define S32_NVIC_IP_PRI104(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI104_SHIFT))&S32_NVIC_IP_PRI104_MASK)
11310 #define S32_NVIC_IP_PRI105_MASK 0xFFu
11311 #define S32_NVIC_IP_PRI105_SHIFT 0u
11312 #define S32_NVIC_IP_PRI105_WIDTH 8u
11313 #define S32_NVIC_IP_PRI105(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI105_SHIFT))&S32_NVIC_IP_PRI105_MASK)
11314 #define S32_NVIC_IP_PRI106_MASK 0xFFu
11315 #define S32_NVIC_IP_PRI106_SHIFT 0u
11316 #define S32_NVIC_IP_PRI106_WIDTH 8u
11317 #define S32_NVIC_IP_PRI106(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI106_SHIFT))&S32_NVIC_IP_PRI106_MASK)
11318 #define S32_NVIC_IP_PRI107_MASK 0xFFu
11319 #define S32_NVIC_IP_PRI107_SHIFT 0u
11320 #define S32_NVIC_IP_PRI107_WIDTH 8u
11321 #define S32_NVIC_IP_PRI107(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI107_SHIFT))&S32_NVIC_IP_PRI107_MASK)
11322 #define S32_NVIC_IP_PRI108_MASK 0xFFu
11323 #define S32_NVIC_IP_PRI108_SHIFT 0u
11324 #define S32_NVIC_IP_PRI108_WIDTH 8u
11325 #define S32_NVIC_IP_PRI108(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI108_SHIFT))&S32_NVIC_IP_PRI108_MASK)
11326 #define S32_NVIC_IP_PRI109_MASK 0xFFu
11327 #define S32_NVIC_IP_PRI109_SHIFT 0u
11328 #define S32_NVIC_IP_PRI109_WIDTH 8u
11329 #define S32_NVIC_IP_PRI109(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI109_SHIFT))&S32_NVIC_IP_PRI109_MASK)
11330 #define S32_NVIC_IP_PRI110_MASK 0xFFu
11331 #define S32_NVIC_IP_PRI110_SHIFT 0u
11332 #define S32_NVIC_IP_PRI110_WIDTH 8u
11333 #define S32_NVIC_IP_PRI110(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI110_SHIFT))&S32_NVIC_IP_PRI110_MASK)
11334 #define S32_NVIC_IP_PRI111_MASK 0xFFu
11335 #define S32_NVIC_IP_PRI111_SHIFT 0u
11336 #define S32_NVIC_IP_PRI111_WIDTH 8u
11337 #define S32_NVIC_IP_PRI111(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI111_SHIFT))&S32_NVIC_IP_PRI111_MASK)
11338 #define S32_NVIC_IP_PRI112_MASK 0xFFu
11339 #define S32_NVIC_IP_PRI112_SHIFT 0u
11340 #define S32_NVIC_IP_PRI112_WIDTH 8u
11341 #define S32_NVIC_IP_PRI112(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI112_SHIFT))&S32_NVIC_IP_PRI112_MASK)
11342 #define S32_NVIC_IP_PRI113_MASK 0xFFu
11343 #define S32_NVIC_IP_PRI113_SHIFT 0u
11344 #define S32_NVIC_IP_PRI113_WIDTH 8u
11345 #define S32_NVIC_IP_PRI113(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI113_SHIFT))&S32_NVIC_IP_PRI113_MASK)
11346 #define S32_NVIC_IP_PRI114_MASK 0xFFu
11347 #define S32_NVIC_IP_PRI114_SHIFT 0u
11348 #define S32_NVIC_IP_PRI114_WIDTH 8u
11349 #define S32_NVIC_IP_PRI114(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI114_SHIFT))&S32_NVIC_IP_PRI114_MASK)
11350 #define S32_NVIC_IP_PRI115_MASK 0xFFu
11351 #define S32_NVIC_IP_PRI115_SHIFT 0u
11352 #define S32_NVIC_IP_PRI115_WIDTH 8u
11353 #define S32_NVIC_IP_PRI115(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI115_SHIFT))&S32_NVIC_IP_PRI115_MASK)
11354 #define S32_NVIC_IP_PRI116_MASK 0xFFu
11355 #define S32_NVIC_IP_PRI116_SHIFT 0u
11356 #define S32_NVIC_IP_PRI116_WIDTH 8u
11357 #define S32_NVIC_IP_PRI116(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI116_SHIFT))&S32_NVIC_IP_PRI116_MASK)
11358 #define S32_NVIC_IP_PRI117_MASK 0xFFu
11359 #define S32_NVIC_IP_PRI117_SHIFT 0u
11360 #define S32_NVIC_IP_PRI117_WIDTH 8u
11361 #define S32_NVIC_IP_PRI117(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI117_SHIFT))&S32_NVIC_IP_PRI117_MASK)
11362 #define S32_NVIC_IP_PRI118_MASK 0xFFu
11363 #define S32_NVIC_IP_PRI118_SHIFT 0u
11364 #define S32_NVIC_IP_PRI118_WIDTH 8u
11365 #define S32_NVIC_IP_PRI118(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI118_SHIFT))&S32_NVIC_IP_PRI118_MASK)
11366 #define S32_NVIC_IP_PRI119_MASK 0xFFu
11367 #define S32_NVIC_IP_PRI119_SHIFT 0u
11368 #define S32_NVIC_IP_PRI119_WIDTH 8u
11369 #define S32_NVIC_IP_PRI119(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI119_SHIFT))&S32_NVIC_IP_PRI119_MASK)
11370 #define S32_NVIC_IP_PRI120_MASK 0xFFu
11371 #define S32_NVIC_IP_PRI120_SHIFT 0u
11372 #define S32_NVIC_IP_PRI120_WIDTH 8u
11373 #define S32_NVIC_IP_PRI120(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI120_SHIFT))&S32_NVIC_IP_PRI120_MASK)
11374 #define S32_NVIC_IP_PRI121_MASK 0xFFu
11375 #define S32_NVIC_IP_PRI121_SHIFT 0u
11376 #define S32_NVIC_IP_PRI121_WIDTH 8u
11377 #define S32_NVIC_IP_PRI121(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI121_SHIFT))&S32_NVIC_IP_PRI121_MASK)
11378 #define S32_NVIC_IP_PRI122_MASK 0xFFu
11379 #define S32_NVIC_IP_PRI122_SHIFT 0u
11380 #define S32_NVIC_IP_PRI122_WIDTH 8u
11381 #define S32_NVIC_IP_PRI122(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI122_SHIFT))&S32_NVIC_IP_PRI122_MASK)
11383 #define S32_NVIC_STIR_INTID_MASK 0x1FFu
11384 #define S32_NVIC_STIR_INTID_SHIFT 0u
11385 #define S32_NVIC_STIR_INTID_WIDTH 9u
11386 #define S32_NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_STIR_INTID_SHIFT))&S32_NVIC_STIR_INTID_MASK)
11412 uint8_t RESERVED_0[8];
11414 uint8_t RESERVED_1[3316];
11431 uint8_t RESERVED_2[72];
11433 uint8_t RESERVED_3[424];
11440 #define S32_SCB_INSTANCE_COUNT (1u)
11445 #define S32_SCB_BASE (0xE000E000u)
11447 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE)
11449 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE }
11451 #define S32_SCB_BASE_PTRS { S32_SCB }
11463 #define S32_SCB_ACTLR_DISMCYCINT_MASK 0x1u
11464 #define S32_SCB_ACTLR_DISMCYCINT_SHIFT 0u
11465 #define S32_SCB_ACTLR_DISMCYCINT_WIDTH 1u
11466 #define S32_SCB_ACTLR_DISMCYCINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISMCYCINT_SHIFT))&S32_SCB_ACTLR_DISMCYCINT_MASK)
11467 #define S32_SCB_ACTLR_DISDEFWBUF_MASK 0x2u
11468 #define S32_SCB_ACTLR_DISDEFWBUF_SHIFT 1u
11469 #define S32_SCB_ACTLR_DISDEFWBUF_WIDTH 1u
11470 #define S32_SCB_ACTLR_DISDEFWBUF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISDEFWBUF_SHIFT))&S32_SCB_ACTLR_DISDEFWBUF_MASK)
11471 #define S32_SCB_ACTLR_DISFOLD_MASK 0x4u
11472 #define S32_SCB_ACTLR_DISFOLD_SHIFT 2u
11473 #define S32_SCB_ACTLR_DISFOLD_WIDTH 1u
11474 #define S32_SCB_ACTLR_DISFOLD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFOLD_SHIFT))&S32_SCB_ACTLR_DISFOLD_MASK)
11475 #define S32_SCB_ACTLR_DISFPCA_MASK 0x100u
11476 #define S32_SCB_ACTLR_DISFPCA_SHIFT 8u
11477 #define S32_SCB_ACTLR_DISFPCA_WIDTH 1u
11478 #define S32_SCB_ACTLR_DISFPCA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFPCA_SHIFT))&S32_SCB_ACTLR_DISFPCA_MASK)
11479 #define S32_SCB_ACTLR_DISOOFP_MASK 0x200u
11480 #define S32_SCB_ACTLR_DISOOFP_SHIFT 9u
11481 #define S32_SCB_ACTLR_DISOOFP_WIDTH 1u
11482 #define S32_SCB_ACTLR_DISOOFP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISOOFP_SHIFT))&S32_SCB_ACTLR_DISOOFP_MASK)
11484 #define S32_SCB_CPUID_REVISION_MASK 0xFu
11485 #define S32_SCB_CPUID_REVISION_SHIFT 0u
11486 #define S32_SCB_CPUID_REVISION_WIDTH 4u
11487 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK)
11488 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u
11489 #define S32_SCB_CPUID_PARTNO_SHIFT 4u
11490 #define S32_SCB_CPUID_PARTNO_WIDTH 12u
11491 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK)
11492 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u
11493 #define S32_SCB_CPUID_VARIANT_SHIFT 20u
11494 #define S32_SCB_CPUID_VARIANT_WIDTH 4u
11495 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK)
11496 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u
11497 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u
11498 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u
11499 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK)
11501 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x1FFu
11502 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
11503 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 9u
11504 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK)
11505 #define S32_SCB_ICSR_RETTOBASE_MASK 0x800u
11506 #define S32_SCB_ICSR_RETTOBASE_SHIFT 11u
11507 #define S32_SCB_ICSR_RETTOBASE_WIDTH 1u
11508 #define S32_SCB_ICSR_RETTOBASE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_RETTOBASE_SHIFT))&S32_SCB_ICSR_RETTOBASE_MASK)
11509 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u
11510 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u
11511 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u
11512 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK)
11513 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u
11514 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u
11515 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u
11516 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK)
11517 #define S32_SCB_ICSR_ISRPREEMPT_MASK 0x800000u
11518 #define S32_SCB_ICSR_ISRPREEMPT_SHIFT 23u
11519 #define S32_SCB_ICSR_ISRPREEMPT_WIDTH 1u
11520 #define S32_SCB_ICSR_ISRPREEMPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPREEMPT_SHIFT))&S32_SCB_ICSR_ISRPREEMPT_MASK)
11521 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u
11522 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u
11523 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u
11524 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK)
11525 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u
11526 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u
11527 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u
11528 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK)
11529 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u
11530 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u
11531 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u
11532 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK)
11533 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u
11534 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u
11535 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u
11536 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK)
11537 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u
11538 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u
11539 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u
11540 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK)
11542 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u
11543 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u
11544 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u
11545 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK)
11547 #define S32_SCB_AIRCR_VECTRESET_MASK 0x1u
11548 #define S32_SCB_AIRCR_VECTRESET_SHIFT 0u
11549 #define S32_SCB_AIRCR_VECTRESET_WIDTH 1u
11550 #define S32_SCB_AIRCR_VECTRESET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTRESET_SHIFT))&S32_SCB_AIRCR_VECTRESET_MASK)
11551 #define S32_SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u
11552 #define S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT 1u
11553 #define S32_SCB_AIRCR_VECTCLRACTIVE_WIDTH 1u
11554 #define S32_SCB_AIRCR_VECTCLRACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK)
11555 #define S32_SCB_AIRCR_SYSRESETREQ_MASK 0x4u
11556 #define S32_SCB_AIRCR_SYSRESETREQ_SHIFT 2u
11557 #define S32_SCB_AIRCR_SYSRESETREQ_WIDTH 1u
11558 #define S32_SCB_AIRCR_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK)
11559 #define S32_SCB_AIRCR_PRIGROUP_MASK 0x700u
11560 #define S32_SCB_AIRCR_PRIGROUP_SHIFT 8u
11561 #define S32_SCB_AIRCR_PRIGROUP_WIDTH 3u
11562 #define S32_SCB_AIRCR_PRIGROUP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_PRIGROUP_SHIFT))&S32_SCB_AIRCR_PRIGROUP_MASK)
11563 #define S32_SCB_AIRCR_ENDIANNESS_MASK 0x8000u
11564 #define S32_SCB_AIRCR_ENDIANNESS_SHIFT 15u
11565 #define S32_SCB_AIRCR_ENDIANNESS_WIDTH 1u
11566 #define S32_SCB_AIRCR_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK)
11567 #define S32_SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u
11568 #define S32_SCB_AIRCR_VECTKEY_SHIFT 16u
11569 #define S32_SCB_AIRCR_VECTKEY_WIDTH 16u
11570 #define S32_SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK)
11572 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u
11573 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u
11574 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u
11575 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK)
11576 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u
11577 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u
11578 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u
11579 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK)
11580 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u
11581 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u
11582 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u
11583 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK)
11585 #define S32_SCB_CCR_NONBASETHRDENA_MASK 0x1u
11586 #define S32_SCB_CCR_NONBASETHRDENA_SHIFT 0u
11587 #define S32_SCB_CCR_NONBASETHRDENA_WIDTH 1u
11588 #define S32_SCB_CCR_NONBASETHRDENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_NONBASETHRDENA_SHIFT))&S32_SCB_CCR_NONBASETHRDENA_MASK)
11589 #define S32_SCB_CCR_USERSETMPEND_MASK 0x2u
11590 #define S32_SCB_CCR_USERSETMPEND_SHIFT 1u
11591 #define S32_SCB_CCR_USERSETMPEND_WIDTH 1u
11592 #define S32_SCB_CCR_USERSETMPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_USERSETMPEND_SHIFT))&S32_SCB_CCR_USERSETMPEND_MASK)
11593 #define S32_SCB_CCR_UNALIGN_TRP_MASK 0x8u
11594 #define S32_SCB_CCR_UNALIGN_TRP_SHIFT 3u
11595 #define S32_SCB_CCR_UNALIGN_TRP_WIDTH 1u
11596 #define S32_SCB_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK)
11597 #define S32_SCB_CCR_DIV_0_TRP_MASK 0x10u
11598 #define S32_SCB_CCR_DIV_0_TRP_SHIFT 4u
11599 #define S32_SCB_CCR_DIV_0_TRP_WIDTH 1u
11600 #define S32_SCB_CCR_DIV_0_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_DIV_0_TRP_SHIFT))&S32_SCB_CCR_DIV_0_TRP_MASK)
11601 #define S32_SCB_CCR_BFHFNMIGN_MASK 0x100u
11602 #define S32_SCB_CCR_BFHFNMIGN_SHIFT 8u
11603 #define S32_SCB_CCR_BFHFNMIGN_WIDTH 1u
11604 #define S32_SCB_CCR_BFHFNMIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_BFHFNMIGN_SHIFT))&S32_SCB_CCR_BFHFNMIGN_MASK)
11605 #define S32_SCB_CCR_STKALIGN_MASK 0x200u
11606 #define S32_SCB_CCR_STKALIGN_SHIFT 9u
11607 #define S32_SCB_CCR_STKALIGN_WIDTH 1u
11608 #define S32_SCB_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK)
11610 #define S32_SCB_SHPR1_PRI_4_MASK 0xFFu
11611 #define S32_SCB_SHPR1_PRI_4_SHIFT 0u
11612 #define S32_SCB_SHPR1_PRI_4_WIDTH 8u
11613 #define S32_SCB_SHPR1_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_4_SHIFT))&S32_SCB_SHPR1_PRI_4_MASK)
11614 #define S32_SCB_SHPR1_PRI_5_MASK 0xFF00u
11615 #define S32_SCB_SHPR1_PRI_5_SHIFT 8u
11616 #define S32_SCB_SHPR1_PRI_5_WIDTH 8u
11617 #define S32_SCB_SHPR1_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_5_SHIFT))&S32_SCB_SHPR1_PRI_5_MASK)
11618 #define S32_SCB_SHPR1_PRI_6_MASK 0xFF0000u
11619 #define S32_SCB_SHPR1_PRI_6_SHIFT 16u
11620 #define S32_SCB_SHPR1_PRI_6_WIDTH 8u
11621 #define S32_SCB_SHPR1_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_6_SHIFT))&S32_SCB_SHPR1_PRI_6_MASK)
11623 #define S32_SCB_SHPR2_PRI_11_MASK 0xFF000000u
11624 #define S32_SCB_SHPR2_PRI_11_SHIFT 24u
11625 #define S32_SCB_SHPR2_PRI_11_WIDTH 8u
11626 #define S32_SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK)
11628 #define S32_SCB_SHPR3_PRI_12_MASK 0xFFu
11629 #define S32_SCB_SHPR3_PRI_12_SHIFT 0u
11630 #define S32_SCB_SHPR3_PRI_12_WIDTH 8u
11631 #define S32_SCB_SHPR3_PRI_12(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_12_SHIFT))&S32_SCB_SHPR3_PRI_12_MASK)
11632 #define S32_SCB_SHPR3_PRI_14_MASK 0xFF0000u
11633 #define S32_SCB_SHPR3_PRI_14_SHIFT 16u
11634 #define S32_SCB_SHPR3_PRI_14_WIDTH 8u
11635 #define S32_SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK)
11636 #define S32_SCB_SHPR3_PRI_15_MASK 0xFF000000u
11637 #define S32_SCB_SHPR3_PRI_15_SHIFT 24u
11638 #define S32_SCB_SHPR3_PRI_15_WIDTH 8u
11639 #define S32_SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK)
11641 #define S32_SCB_SHCSR_MEMFAULTACT_MASK 0x1u
11642 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
11643 #define S32_SCB_SHCSR_MEMFAULTACT_WIDTH 1u
11644 #define S32_SCB_SHCSR_MEMFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTACT_SHIFT))&S32_SCB_SHCSR_MEMFAULTACT_MASK)
11645 #define S32_SCB_SHCSR_BUSFAULTACT_MASK 0x2u
11646 #define S32_SCB_SHCSR_BUSFAULTACT_SHIFT 1u
11647 #define S32_SCB_SHCSR_BUSFAULTACT_WIDTH 1u
11648 #define S32_SCB_SHCSR_BUSFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTACT_SHIFT))&S32_SCB_SHCSR_BUSFAULTACT_MASK)
11649 #define S32_SCB_SHCSR_USGFAULTACT_MASK 0x8u
11650 #define S32_SCB_SHCSR_USGFAULTACT_SHIFT 3u
11651 #define S32_SCB_SHCSR_USGFAULTACT_WIDTH 1u
11652 #define S32_SCB_SHCSR_USGFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTACT_SHIFT))&S32_SCB_SHCSR_USGFAULTACT_MASK)
11653 #define S32_SCB_SHCSR_SVCALLACT_MASK 0x80u
11654 #define S32_SCB_SHCSR_SVCALLACT_SHIFT 7u
11655 #define S32_SCB_SHCSR_SVCALLACT_WIDTH 1u
11656 #define S32_SCB_SHCSR_SVCALLACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLACT_SHIFT))&S32_SCB_SHCSR_SVCALLACT_MASK)
11657 #define S32_SCB_SHCSR_MONITORACT_MASK 0x100u
11658 #define S32_SCB_SHCSR_MONITORACT_SHIFT 8u
11659 #define S32_SCB_SHCSR_MONITORACT_WIDTH 1u
11660 #define S32_SCB_SHCSR_MONITORACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MONITORACT_SHIFT))&S32_SCB_SHCSR_MONITORACT_MASK)
11661 #define S32_SCB_SHCSR_PENDSVACT_MASK 0x400u
11662 #define S32_SCB_SHCSR_PENDSVACT_SHIFT 10u
11663 #define S32_SCB_SHCSR_PENDSVACT_WIDTH 1u
11664 #define S32_SCB_SHCSR_PENDSVACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_PENDSVACT_SHIFT))&S32_SCB_SHCSR_PENDSVACT_MASK)
11665 #define S32_SCB_SHCSR_SYSTICKACT_MASK 0x800u
11666 #define S32_SCB_SHCSR_SYSTICKACT_SHIFT 11u
11667 #define S32_SCB_SHCSR_SYSTICKACT_WIDTH 1u
11668 #define S32_SCB_SHCSR_SYSTICKACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SYSTICKACT_SHIFT))&S32_SCB_SHCSR_SYSTICKACT_MASK)
11669 #define S32_SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u
11670 #define S32_SCB_SHCSR_USGFAULTPENDED_SHIFT 12u
11671 #define S32_SCB_SHCSR_USGFAULTPENDED_WIDTH 1u
11672 #define S32_SCB_SHCSR_USGFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTPENDED_SHIFT))&S32_SCB_SHCSR_USGFAULTPENDED_MASK)
11673 #define S32_SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u
11674 #define S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT 13u
11675 #define S32_SCB_SHCSR_MEMFAULTPENDED_WIDTH 1u
11676 #define S32_SCB_SHCSR_MEMFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT))&S32_SCB_SHCSR_MEMFAULTPENDED_MASK)
11677 #define S32_SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u
11678 #define S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT 14u
11679 #define S32_SCB_SHCSR_BUSFAULTPENDED_WIDTH 1u
11680 #define S32_SCB_SHCSR_BUSFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT))&S32_SCB_SHCSR_BUSFAULTPENDED_MASK)
11681 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u
11682 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u
11683 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u
11684 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK)
11685 #define S32_SCB_SHCSR_MEMFAULTENA_MASK 0x10000u
11686 #define S32_SCB_SHCSR_MEMFAULTENA_SHIFT 16u
11687 #define S32_SCB_SHCSR_MEMFAULTENA_WIDTH 1u
11688 #define S32_SCB_SHCSR_MEMFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTENA_SHIFT))&S32_SCB_SHCSR_MEMFAULTENA_MASK)
11689 #define S32_SCB_SHCSR_BUSFAULTENA_MASK 0x20000u
11690 #define S32_SCB_SHCSR_BUSFAULTENA_SHIFT 17u
11691 #define S32_SCB_SHCSR_BUSFAULTENA_WIDTH 1u
11692 #define S32_SCB_SHCSR_BUSFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTENA_SHIFT))&S32_SCB_SHCSR_BUSFAULTENA_MASK)
11693 #define S32_SCB_SHCSR_USGFAULTENA_MASK 0x40000u
11694 #define S32_SCB_SHCSR_USGFAULTENA_SHIFT 18u
11695 #define S32_SCB_SHCSR_USGFAULTENA_WIDTH 1u
11696 #define S32_SCB_SHCSR_USGFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTENA_SHIFT))&S32_SCB_SHCSR_USGFAULTENA_MASK)
11698 #define S32_SCB_CFSR_IACCVIOL_MASK 0x1u
11699 #define S32_SCB_CFSR_IACCVIOL_SHIFT 0u
11700 #define S32_SCB_CFSR_IACCVIOL_WIDTH 1u
11701 #define S32_SCB_CFSR_IACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IACCVIOL_SHIFT))&S32_SCB_CFSR_IACCVIOL_MASK)
11702 #define S32_SCB_CFSR_DACCVIOL_MASK 0x2u
11703 #define S32_SCB_CFSR_DACCVIOL_SHIFT 1u
11704 #define S32_SCB_CFSR_DACCVIOL_WIDTH 1u
11705 #define S32_SCB_CFSR_DACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DACCVIOL_SHIFT))&S32_SCB_CFSR_DACCVIOL_MASK)
11706 #define S32_SCB_CFSR_MUNSTKERR_MASK 0x8u
11707 #define S32_SCB_CFSR_MUNSTKERR_SHIFT 3u
11708 #define S32_SCB_CFSR_MUNSTKERR_WIDTH 1u
11709 #define S32_SCB_CFSR_MUNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MUNSTKERR_SHIFT))&S32_SCB_CFSR_MUNSTKERR_MASK)
11710 #define S32_SCB_CFSR_MSTKERR_MASK 0x10u
11711 #define S32_SCB_CFSR_MSTKERR_SHIFT 4u
11712 #define S32_SCB_CFSR_MSTKERR_WIDTH 1u
11713 #define S32_SCB_CFSR_MSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MSTKERR_SHIFT))&S32_SCB_CFSR_MSTKERR_MASK)
11714 #define S32_SCB_CFSR_MLSPERR_MASK 0x20u
11715 #define S32_SCB_CFSR_MLSPERR_SHIFT 5u
11716 #define S32_SCB_CFSR_MLSPERR_WIDTH 1u
11717 #define S32_SCB_CFSR_MLSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MLSPERR_SHIFT))&S32_SCB_CFSR_MLSPERR_MASK)
11718 #define S32_SCB_CFSR_MMARVALID_MASK 0x80u
11719 #define S32_SCB_CFSR_MMARVALID_SHIFT 7u
11720 #define S32_SCB_CFSR_MMARVALID_WIDTH 1u
11721 #define S32_SCB_CFSR_MMARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMARVALID_SHIFT))&S32_SCB_CFSR_MMARVALID_MASK)
11722 #define S32_SCB_CFSR_IBUSERR_MASK 0x100u
11723 #define S32_SCB_CFSR_IBUSERR_SHIFT 8u
11724 #define S32_SCB_CFSR_IBUSERR_WIDTH 1u
11725 #define S32_SCB_CFSR_IBUSERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IBUSERR_SHIFT))&S32_SCB_CFSR_IBUSERR_MASK)
11726 #define S32_SCB_CFSR_PRECISERR_MASK 0x200u
11727 #define S32_SCB_CFSR_PRECISERR_SHIFT 9u
11728 #define S32_SCB_CFSR_PRECISERR_WIDTH 1u
11729 #define S32_SCB_CFSR_PRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_PRECISERR_SHIFT))&S32_SCB_CFSR_PRECISERR_MASK)
11730 #define S32_SCB_CFSR_IMPRECISERR_MASK 0x400u
11731 #define S32_SCB_CFSR_IMPRECISERR_SHIFT 10u
11732 #define S32_SCB_CFSR_IMPRECISERR_WIDTH 1u
11733 #define S32_SCB_CFSR_IMPRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IMPRECISERR_SHIFT))&S32_SCB_CFSR_IMPRECISERR_MASK)
11734 #define S32_SCB_CFSR_UNSTKERR_MASK 0x800u
11735 #define S32_SCB_CFSR_UNSTKERR_SHIFT 11u
11736 #define S32_SCB_CFSR_UNSTKERR_WIDTH 1u
11737 #define S32_SCB_CFSR_UNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNSTKERR_SHIFT))&S32_SCB_CFSR_UNSTKERR_MASK)
11738 #define S32_SCB_CFSR_STKERR_MASK 0x1000u
11739 #define S32_SCB_CFSR_STKERR_SHIFT 12u
11740 #define S32_SCB_CFSR_STKERR_WIDTH 1u
11741 #define S32_SCB_CFSR_STKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_STKERR_SHIFT))&S32_SCB_CFSR_STKERR_MASK)
11742 #define S32_SCB_CFSR_LSPERR_MASK 0x2000u
11743 #define S32_SCB_CFSR_LSPERR_SHIFT 13u
11744 #define S32_SCB_CFSR_LSPERR_WIDTH 1u
11745 #define S32_SCB_CFSR_LSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_LSPERR_SHIFT))&S32_SCB_CFSR_LSPERR_MASK)
11746 #define S32_SCB_CFSR_BFARVALID_MASK 0x8000u
11747 #define S32_SCB_CFSR_BFARVALID_SHIFT 15u
11748 #define S32_SCB_CFSR_BFARVALID_WIDTH 1u
11749 #define S32_SCB_CFSR_BFARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFARVALID_SHIFT))&S32_SCB_CFSR_BFARVALID_MASK)
11750 #define S32_SCB_CFSR_UNDEFINSTR_MASK 0x10000u
11751 #define S32_SCB_CFSR_UNDEFINSTR_SHIFT 16u
11752 #define S32_SCB_CFSR_UNDEFINSTR_WIDTH 1u
11753 #define S32_SCB_CFSR_UNDEFINSTR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNDEFINSTR_SHIFT))&S32_SCB_CFSR_UNDEFINSTR_MASK)
11754 #define S32_SCB_CFSR_INVSTATE_MASK 0x20000u
11755 #define S32_SCB_CFSR_INVSTATE_SHIFT 17u
11756 #define S32_SCB_CFSR_INVSTATE_WIDTH 1u
11757 #define S32_SCB_CFSR_INVSTATE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVSTATE_SHIFT))&S32_SCB_CFSR_INVSTATE_MASK)
11758 #define S32_SCB_CFSR_INVPC_MASK 0x40000u
11759 #define S32_SCB_CFSR_INVPC_SHIFT 18u
11760 #define S32_SCB_CFSR_INVPC_WIDTH 1u
11761 #define S32_SCB_CFSR_INVPC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVPC_SHIFT))&S32_SCB_CFSR_INVPC_MASK)
11762 #define S32_SCB_CFSR_NOCP_MASK 0x80000u
11763 #define S32_SCB_CFSR_NOCP_SHIFT 19u
11764 #define S32_SCB_CFSR_NOCP_WIDTH 1u
11765 #define S32_SCB_CFSR_NOCP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_NOCP_SHIFT))&S32_SCB_CFSR_NOCP_MASK)
11766 #define S32_SCB_CFSR_UNALIGNED_MASK 0x1000000u
11767 #define S32_SCB_CFSR_UNALIGNED_SHIFT 24u
11768 #define S32_SCB_CFSR_UNALIGNED_WIDTH 1u
11769 #define S32_SCB_CFSR_UNALIGNED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNALIGNED_SHIFT))&S32_SCB_CFSR_UNALIGNED_MASK)
11770 #define S32_SCB_CFSR_DIVBYZERO_MASK 0x2000000u
11771 #define S32_SCB_CFSR_DIVBYZERO_SHIFT 25u
11772 #define S32_SCB_CFSR_DIVBYZERO_WIDTH 1u
11773 #define S32_SCB_CFSR_DIVBYZERO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DIVBYZERO_SHIFT))&S32_SCB_CFSR_DIVBYZERO_MASK)
11775 #define S32_SCB_HFSR_VECTTBL_MASK 0x2u
11776 #define S32_SCB_HFSR_VECTTBL_SHIFT 1u
11777 #define S32_SCB_HFSR_VECTTBL_WIDTH 1u
11778 #define S32_SCB_HFSR_VECTTBL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_VECTTBL_SHIFT))&S32_SCB_HFSR_VECTTBL_MASK)
11779 #define S32_SCB_HFSR_FORCED_MASK 0x40000000u
11780 #define S32_SCB_HFSR_FORCED_SHIFT 30u
11781 #define S32_SCB_HFSR_FORCED_WIDTH 1u
11782 #define S32_SCB_HFSR_FORCED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_FORCED_SHIFT))&S32_SCB_HFSR_FORCED_MASK)
11783 #define S32_SCB_HFSR_DEBUGEVT_MASK 0x80000000u
11784 #define S32_SCB_HFSR_DEBUGEVT_SHIFT 31u
11785 #define S32_SCB_HFSR_DEBUGEVT_WIDTH 1u
11786 #define S32_SCB_HFSR_DEBUGEVT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_DEBUGEVT_SHIFT))&S32_SCB_HFSR_DEBUGEVT_MASK)
11788 #define S32_SCB_DFSR_HALTED_MASK 0x1u
11789 #define S32_SCB_DFSR_HALTED_SHIFT 0u
11790 #define S32_SCB_DFSR_HALTED_WIDTH 1u
11791 #define S32_SCB_DFSR_HALTED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK)
11792 #define S32_SCB_DFSR_BKPT_MASK 0x2u
11793 #define S32_SCB_DFSR_BKPT_SHIFT 1u
11794 #define S32_SCB_DFSR_BKPT_WIDTH 1u
11795 #define S32_SCB_DFSR_BKPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK)
11796 #define S32_SCB_DFSR_DWTTRAP_MASK 0x4u
11797 #define S32_SCB_DFSR_DWTTRAP_SHIFT 2u
11798 #define S32_SCB_DFSR_DWTTRAP_WIDTH 1u
11799 #define S32_SCB_DFSR_DWTTRAP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK)
11800 #define S32_SCB_DFSR_VCATCH_MASK 0x8u
11801 #define S32_SCB_DFSR_VCATCH_SHIFT 3u
11802 #define S32_SCB_DFSR_VCATCH_WIDTH 1u
11803 #define S32_SCB_DFSR_VCATCH(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK)
11804 #define S32_SCB_DFSR_EXTERNAL_MASK 0x10u
11805 #define S32_SCB_DFSR_EXTERNAL_SHIFT 4u
11806 #define S32_SCB_DFSR_EXTERNAL_WIDTH 1u
11807 #define S32_SCB_DFSR_EXTERNAL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK)
11809 #define S32_SCB_MMFAR_ADDRESS_MASK 0xFFFFFFFFu
11810 #define S32_SCB_MMFAR_ADDRESS_SHIFT 0u
11811 #define S32_SCB_MMFAR_ADDRESS_WIDTH 32u
11812 #define S32_SCB_MMFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_MMFAR_ADDRESS_SHIFT))&S32_SCB_MMFAR_ADDRESS_MASK)
11814 #define S32_SCB_BFAR_ADDRESS_MASK 0xFFFFFFFFu
11815 #define S32_SCB_BFAR_ADDRESS_SHIFT 0u
11816 #define S32_SCB_BFAR_ADDRESS_WIDTH 32u
11817 #define S32_SCB_BFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_BFAR_ADDRESS_SHIFT))&S32_SCB_BFAR_ADDRESS_MASK)
11819 #define S32_SCB_AFSR_AUXFAULT_MASK 0xFFFFFFFFu
11820 #define S32_SCB_AFSR_AUXFAULT_SHIFT 0u
11821 #define S32_SCB_AFSR_AUXFAULT_WIDTH 32u
11822 #define S32_SCB_AFSR_AUXFAULT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AFSR_AUXFAULT_SHIFT))&S32_SCB_AFSR_AUXFAULT_MASK)
11824 #define S32_SCB_CPACR_CP10_MASK 0x300000u
11825 #define S32_SCB_CPACR_CP10_SHIFT 20u
11826 #define S32_SCB_CPACR_CP10_WIDTH 2u
11827 #define S32_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP10_SHIFT))&S32_SCB_CPACR_CP10_MASK)
11828 #define S32_SCB_CPACR_CP11_MASK 0xC00000u
11829 #define S32_SCB_CPACR_CP11_SHIFT 22u
11830 #define S32_SCB_CPACR_CP11_WIDTH 2u
11831 #define S32_SCB_CPACR_CP11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP11_SHIFT))&S32_SCB_CPACR_CP11_MASK)
11833 #define S32_SCB_FPCCR_LSPACT_MASK 0x1u
11834 #define S32_SCB_FPCCR_LSPACT_SHIFT 0u
11835 #define S32_SCB_FPCCR_LSPACT_WIDTH 1u
11836 #define S32_SCB_FPCCR_LSPACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPACT_SHIFT))&S32_SCB_FPCCR_LSPACT_MASK)
11837 #define S32_SCB_FPCCR_USER_MASK 0x2u
11838 #define S32_SCB_FPCCR_USER_SHIFT 1u
11839 #define S32_SCB_FPCCR_USER_WIDTH 1u
11840 #define S32_SCB_FPCCR_USER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_USER_SHIFT))&S32_SCB_FPCCR_USER_MASK)
11841 #define S32_SCB_FPCCR_THREAD_MASK 0x8u
11842 #define S32_SCB_FPCCR_THREAD_SHIFT 3u
11843 #define S32_SCB_FPCCR_THREAD_WIDTH 1u
11844 #define S32_SCB_FPCCR_THREAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_THREAD_SHIFT))&S32_SCB_FPCCR_THREAD_MASK)
11845 #define S32_SCB_FPCCR_HFRDY_MASK 0x10u
11846 #define S32_SCB_FPCCR_HFRDY_SHIFT 4u
11847 #define S32_SCB_FPCCR_HFRDY_WIDTH 1u
11848 #define S32_SCB_FPCCR_HFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_HFRDY_SHIFT))&S32_SCB_FPCCR_HFRDY_MASK)
11849 #define S32_SCB_FPCCR_MMRDY_MASK 0x20u
11850 #define S32_SCB_FPCCR_MMRDY_SHIFT 5u
11851 #define S32_SCB_FPCCR_MMRDY_WIDTH 1u
11852 #define S32_SCB_FPCCR_MMRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MMRDY_SHIFT))&S32_SCB_FPCCR_MMRDY_MASK)
11853 #define S32_SCB_FPCCR_BFRDY_MASK 0x40u
11854 #define S32_SCB_FPCCR_BFRDY_SHIFT 6u
11855 #define S32_SCB_FPCCR_BFRDY_WIDTH 1u
11856 #define S32_SCB_FPCCR_BFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_BFRDY_SHIFT))&S32_SCB_FPCCR_BFRDY_MASK)
11857 #define S32_SCB_FPCCR_MONRDY_MASK 0x100u
11858 #define S32_SCB_FPCCR_MONRDY_SHIFT 8u
11859 #define S32_SCB_FPCCR_MONRDY_WIDTH 1u
11860 #define S32_SCB_FPCCR_MONRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MONRDY_SHIFT))&S32_SCB_FPCCR_MONRDY_MASK)
11861 #define S32_SCB_FPCCR_LSPEN_MASK 0x40000000u
11862 #define S32_SCB_FPCCR_LSPEN_SHIFT 30u
11863 #define S32_SCB_FPCCR_LSPEN_WIDTH 1u
11864 #define S32_SCB_FPCCR_LSPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPEN_SHIFT))&S32_SCB_FPCCR_LSPEN_MASK)
11865 #define S32_SCB_FPCCR_ASPEN_MASK 0x80000000u
11866 #define S32_SCB_FPCCR_ASPEN_SHIFT 31u
11867 #define S32_SCB_FPCCR_ASPEN_WIDTH 1u
11868 #define S32_SCB_FPCCR_ASPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_ASPEN_SHIFT))&S32_SCB_FPCCR_ASPEN_MASK)
11870 #define S32_SCB_FPCAR_ADDRESS_MASK 0xFFFFFFF8u
11871 #define S32_SCB_FPCAR_ADDRESS_SHIFT 3u
11872 #define S32_SCB_FPCAR_ADDRESS_WIDTH 29u
11873 #define S32_SCB_FPCAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCAR_ADDRESS_SHIFT))&S32_SCB_FPCAR_ADDRESS_MASK)
11875 #define S32_SCB_FPDSCR_RMode_MASK 0xC00000u
11876 #define S32_SCB_FPDSCR_RMode_SHIFT 22u
11877 #define S32_SCB_FPDSCR_RMode_WIDTH 2u
11878 #define S32_SCB_FPDSCR_RMode(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_RMode_SHIFT))&S32_SCB_FPDSCR_RMode_MASK)
11879 #define S32_SCB_FPDSCR_FZ_MASK 0x1000000u
11880 #define S32_SCB_FPDSCR_FZ_SHIFT 24u
11881 #define S32_SCB_FPDSCR_FZ_WIDTH 1u
11882 #define S32_SCB_FPDSCR_FZ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_FZ_SHIFT))&S32_SCB_FPDSCR_FZ_MASK)
11883 #define S32_SCB_FPDSCR_DN_MASK 0x2000000u
11884 #define S32_SCB_FPDSCR_DN_SHIFT 25u
11885 #define S32_SCB_FPDSCR_DN_WIDTH 1u
11886 #define S32_SCB_FPDSCR_DN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_DN_SHIFT))&S32_SCB_FPDSCR_DN_MASK)
11887 #define S32_SCB_FPDSCR_AHP_MASK 0x4000000u
11888 #define S32_SCB_FPDSCR_AHP_SHIFT 26u
11889 #define S32_SCB_FPDSCR_AHP_WIDTH 1u
11890 #define S32_SCB_FPDSCR_AHP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_AHP_SHIFT))&S32_SCB_FPDSCR_AHP_MASK)
11923 #define S32_SysTick_INSTANCE_COUNT (1u)
11928 #define S32_SysTick_BASE (0xE000E010u)
11930 #define S32_SysTick ((S32_SysTick_Type *)S32_SysTick_BASE)
11932 #define S32_SysTick_BASE_ADDRS { S32_SysTick_BASE }
11934 #define S32_SysTick_BASE_PTRS { S32_SysTick }
11936 #define S32_SysTick_IRQS_ARR_COUNT (1u)
11938 #define S32_SysTick_IRQS_CH_COUNT (1u)
11940 #define S32_SysTick_IRQS { SysTick_IRQn }
11952 #define S32_SysTick_CSR_ENABLE_MASK 0x1u
11953 #define S32_SysTick_CSR_ENABLE_SHIFT 0u
11954 #define S32_SysTick_CSR_ENABLE_WIDTH 1u
11955 #define S32_SysTick_CSR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_ENABLE_SHIFT))&S32_SysTick_CSR_ENABLE_MASK)
11956 #define S32_SysTick_CSR_TICKINT_MASK 0x2u
11957 #define S32_SysTick_CSR_TICKINT_SHIFT 1u
11958 #define S32_SysTick_CSR_TICKINT_WIDTH 1u
11959 #define S32_SysTick_CSR_TICKINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_TICKINT_SHIFT))&S32_SysTick_CSR_TICKINT_MASK)
11960 #define S32_SysTick_CSR_CLKSOURCE_MASK 0x4u
11961 #define S32_SysTick_CSR_CLKSOURCE_SHIFT 2u
11962 #define S32_SysTick_CSR_CLKSOURCE_WIDTH 1u
11963 #define S32_SysTick_CSR_CLKSOURCE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_CLKSOURCE_SHIFT))&S32_SysTick_CSR_CLKSOURCE_MASK)
11964 #define S32_SysTick_CSR_COUNTFLAG_MASK 0x10000u
11965 #define S32_SysTick_CSR_COUNTFLAG_SHIFT 16u
11966 #define S32_SysTick_CSR_COUNTFLAG_WIDTH 1u
11967 #define S32_SysTick_CSR_COUNTFLAG(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_COUNTFLAG_SHIFT))&S32_SysTick_CSR_COUNTFLAG_MASK)
11969 #define S32_SysTick_RVR_RELOAD_MASK 0xFFFFFFu
11970 #define S32_SysTick_RVR_RELOAD_SHIFT 0u
11971 #define S32_SysTick_RVR_RELOAD_WIDTH 24u
11972 #define S32_SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_RVR_RELOAD_SHIFT))&S32_SysTick_RVR_RELOAD_MASK)
11974 #define S32_SysTick_CVR_CURRENT_MASK 0xFFFFFFu
11975 #define S32_SysTick_CVR_CURRENT_SHIFT 0u
11976 #define S32_SysTick_CVR_CURRENT_WIDTH 24u
11977 #define S32_SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CVR_CURRENT_SHIFT))&S32_SysTick_CVR_CURRENT_MASK)
11979 #define S32_SysTick_CALIB_TENMS_MASK 0xFFFFFFu
11980 #define S32_SysTick_CALIB_TENMS_SHIFT 0u
11981 #define S32_SysTick_CALIB_TENMS_WIDTH 24u
11982 #define S32_SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_TENMS_SHIFT))&S32_SysTick_CALIB_TENMS_MASK)
11983 #define S32_SysTick_CALIB_SKEW_MASK 0x40000000u
11984 #define S32_SysTick_CALIB_SKEW_SHIFT 30u
11985 #define S32_SysTick_CALIB_SKEW_WIDTH 1u
11986 #define S32_SysTick_CALIB_SKEW(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_SKEW_SHIFT))&S32_SysTick_CALIB_SKEW_MASK)
11987 #define S32_SysTick_CALIB_NOREF_MASK 0x80000000u
11988 #define S32_SysTick_CALIB_NOREF_SHIFT 31u
11989 #define S32_SysTick_CALIB_NOREF_WIDTH 1u
11990 #define S32_SysTick_CALIB_NOREF(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_NOREF_SHIFT))&S32_SysTick_CALIB_NOREF_MASK)
12013 #define SAI_TDR_COUNT 4u
12014 #define SAI_TFR_COUNT 4u
12015 #define SAI_RDR_COUNT 4u
12016 #define SAI_RFR_COUNT 4u
12029 uint8_t RESERVED_0[16];
12031 uint8_t RESERVED_1[16];
12033 uint8_t RESERVED_2[36];
12041 uint8_t RESERVED_3[16];
12043 uint8_t RESERVED_4[16];
12048 #define SAI_INSTANCE_COUNT (2u)
12053 #define SAI0_BASE (0x40054000u)
12055 #define SAI0 ((SAI_Type *)SAI0_BASE)
12057 #define SAI1_BASE (0x40055000u)
12059 #define SAI1 ((SAI_Type *)SAI1_BASE)
12061 #define SAI_BASE_ADDRS { SAI0_BASE, SAI1_BASE }
12063 #define SAI_BASE_PTRS { SAI0, SAI1 }
12065 #define SAI_IRQS_ARR_COUNT (2u)
12067 #define SAI_RX_IRQS_CH_COUNT (1u)
12069 #define SAI_TX_IRQS_CH_COUNT (1u)
12071 #define SAI_RX_IRQS { SAI0_Rx_IRQn, SAI1_Rx_IRQn }
12072 #define SAI_TX_IRQS { SAI0_Tx_IRQn, SAI1_Tx_IRQn }
12084 #define SAI_VERID_FEATURE_MASK 0xFFFFu
12085 #define SAI_VERID_FEATURE_SHIFT 0u
12086 #define SAI_VERID_FEATURE_WIDTH 16u
12087 #define SAI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<SAI_VERID_FEATURE_SHIFT))&SAI_VERID_FEATURE_MASK)
12088 #define SAI_VERID_MINOR_MASK 0xFF0000u
12089 #define SAI_VERID_MINOR_SHIFT 16u
12090 #define SAI_VERID_MINOR_WIDTH 8u
12091 #define SAI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<SAI_VERID_MINOR_SHIFT))&SAI_VERID_MINOR_MASK)
12092 #define SAI_VERID_MAJOR_MASK 0xFF000000u
12093 #define SAI_VERID_MAJOR_SHIFT 24u
12094 #define SAI_VERID_MAJOR_WIDTH 8u
12095 #define SAI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<SAI_VERID_MAJOR_SHIFT))&SAI_VERID_MAJOR_MASK)
12097 #define SAI_PARAM_DATALINE_MASK 0xFu
12098 #define SAI_PARAM_DATALINE_SHIFT 0u
12099 #define SAI_PARAM_DATALINE_WIDTH 4u
12100 #define SAI_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x))<<SAI_PARAM_DATALINE_SHIFT))&SAI_PARAM_DATALINE_MASK)
12101 #define SAI_PARAM_FIFO_MASK 0xF00u
12102 #define SAI_PARAM_FIFO_SHIFT 8u
12103 #define SAI_PARAM_FIFO_WIDTH 4u
12104 #define SAI_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x))<<SAI_PARAM_FIFO_SHIFT))&SAI_PARAM_FIFO_MASK)
12105 #define SAI_PARAM_FRAME_MASK 0xF0000u
12106 #define SAI_PARAM_FRAME_SHIFT 16u
12107 #define SAI_PARAM_FRAME_WIDTH 4u
12108 #define SAI_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x))<<SAI_PARAM_FRAME_SHIFT))&SAI_PARAM_FRAME_MASK)
12110 #define SAI_TCSR_FRDE_MASK 0x1u
12111 #define SAI_TCSR_FRDE_SHIFT 0u
12112 #define SAI_TCSR_FRDE_WIDTH 1u
12113 #define SAI_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FRDE_SHIFT))&SAI_TCSR_FRDE_MASK)
12114 #define SAI_TCSR_FWDE_MASK 0x2u
12115 #define SAI_TCSR_FWDE_SHIFT 1u
12116 #define SAI_TCSR_FWDE_WIDTH 1u
12117 #define SAI_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FWDE_SHIFT))&SAI_TCSR_FWDE_MASK)
12118 #define SAI_TCSR_FRIE_MASK 0x100u
12119 #define SAI_TCSR_FRIE_SHIFT 8u
12120 #define SAI_TCSR_FRIE_WIDTH 1u
12121 #define SAI_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FRIE_SHIFT))&SAI_TCSR_FRIE_MASK)
12122 #define SAI_TCSR_FWIE_MASK 0x200u
12123 #define SAI_TCSR_FWIE_SHIFT 9u
12124 #define SAI_TCSR_FWIE_WIDTH 1u
12125 #define SAI_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FWIE_SHIFT))&SAI_TCSR_FWIE_MASK)
12126 #define SAI_TCSR_FEIE_MASK 0x400u
12127 #define SAI_TCSR_FEIE_SHIFT 10u
12128 #define SAI_TCSR_FEIE_WIDTH 1u
12129 #define SAI_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FEIE_SHIFT))&SAI_TCSR_FEIE_MASK)
12130 #define SAI_TCSR_SEIE_MASK 0x800u
12131 #define SAI_TCSR_SEIE_SHIFT 11u
12132 #define SAI_TCSR_SEIE_WIDTH 1u
12133 #define SAI_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_SEIE_SHIFT))&SAI_TCSR_SEIE_MASK)
12134 #define SAI_TCSR_WSIE_MASK 0x1000u
12135 #define SAI_TCSR_WSIE_SHIFT 12u
12136 #define SAI_TCSR_WSIE_WIDTH 1u
12137 #define SAI_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_WSIE_SHIFT))&SAI_TCSR_WSIE_MASK)
12138 #define SAI_TCSR_FRF_MASK 0x10000u
12139 #define SAI_TCSR_FRF_SHIFT 16u
12140 #define SAI_TCSR_FRF_WIDTH 1u
12141 #define SAI_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FRF_SHIFT))&SAI_TCSR_FRF_MASK)
12142 #define SAI_TCSR_FWF_MASK 0x20000u
12143 #define SAI_TCSR_FWF_SHIFT 17u
12144 #define SAI_TCSR_FWF_WIDTH 1u
12145 #define SAI_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FWF_SHIFT))&SAI_TCSR_FWF_MASK)
12146 #define SAI_TCSR_FEF_MASK 0x40000u
12147 #define SAI_TCSR_FEF_SHIFT 18u
12148 #define SAI_TCSR_FEF_WIDTH 1u
12149 #define SAI_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FEF_SHIFT))&SAI_TCSR_FEF_MASK)
12150 #define SAI_TCSR_SEF_MASK 0x80000u
12151 #define SAI_TCSR_SEF_SHIFT 19u
12152 #define SAI_TCSR_SEF_WIDTH 1u
12153 #define SAI_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_SEF_SHIFT))&SAI_TCSR_SEF_MASK)
12154 #define SAI_TCSR_WSF_MASK 0x100000u
12155 #define SAI_TCSR_WSF_SHIFT 20u
12156 #define SAI_TCSR_WSF_WIDTH 1u
12157 #define SAI_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_WSF_SHIFT))&SAI_TCSR_WSF_MASK)
12158 #define SAI_TCSR_SR_MASK 0x1000000u
12159 #define SAI_TCSR_SR_SHIFT 24u
12160 #define SAI_TCSR_SR_WIDTH 1u
12161 #define SAI_TCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_SR_SHIFT))&SAI_TCSR_SR_MASK)
12162 #define SAI_TCSR_FR_MASK 0x2000000u
12163 #define SAI_TCSR_FR_SHIFT 25u
12164 #define SAI_TCSR_FR_WIDTH 1u
12165 #define SAI_TCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_FR_SHIFT))&SAI_TCSR_FR_MASK)
12166 #define SAI_TCSR_BCE_MASK 0x10000000u
12167 #define SAI_TCSR_BCE_SHIFT 28u
12168 #define SAI_TCSR_BCE_WIDTH 1u
12169 #define SAI_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_BCE_SHIFT))&SAI_TCSR_BCE_MASK)
12170 #define SAI_TCSR_DBGE_MASK 0x20000000u
12171 #define SAI_TCSR_DBGE_SHIFT 29u
12172 #define SAI_TCSR_DBGE_WIDTH 1u
12173 #define SAI_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_DBGE_SHIFT))&SAI_TCSR_DBGE_MASK)
12174 #define SAI_TCSR_TE_MASK 0x80000000u
12175 #define SAI_TCSR_TE_SHIFT 31u
12176 #define SAI_TCSR_TE_WIDTH 1u
12177 #define SAI_TCSR_TE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCSR_TE_SHIFT))&SAI_TCSR_TE_MASK)
12179 #define SAI_TCR1_TFW_MASK 0x7u
12180 #define SAI_TCR1_TFW_SHIFT 0u
12181 #define SAI_TCR1_TFW_WIDTH 3u
12182 #define SAI_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR1_TFW_SHIFT))&SAI_TCR1_TFW_MASK)
12184 #define SAI_TCR2_DIV_MASK 0xFFu
12185 #define SAI_TCR2_DIV_SHIFT 0u
12186 #define SAI_TCR2_DIV_WIDTH 8u
12187 #define SAI_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_DIV_SHIFT))&SAI_TCR2_DIV_MASK)
12188 #define SAI_TCR2_BCD_MASK 0x1000000u
12189 #define SAI_TCR2_BCD_SHIFT 24u
12190 #define SAI_TCR2_BCD_WIDTH 1u
12191 #define SAI_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_BCD_SHIFT))&SAI_TCR2_BCD_MASK)
12192 #define SAI_TCR2_BCP_MASK 0x2000000u
12193 #define SAI_TCR2_BCP_SHIFT 25u
12194 #define SAI_TCR2_BCP_WIDTH 1u
12195 #define SAI_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_BCP_SHIFT))&SAI_TCR2_BCP_MASK)
12196 #define SAI_TCR2_MSEL_MASK 0xC000000u
12197 #define SAI_TCR2_MSEL_SHIFT 26u
12198 #define SAI_TCR2_MSEL_WIDTH 2u
12199 #define SAI_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_MSEL_SHIFT))&SAI_TCR2_MSEL_MASK)
12200 #define SAI_TCR2_BCI_MASK 0x10000000u
12201 #define SAI_TCR2_BCI_SHIFT 28u
12202 #define SAI_TCR2_BCI_WIDTH 1u
12203 #define SAI_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_BCI_SHIFT))&SAI_TCR2_BCI_MASK)
12204 #define SAI_TCR2_BCS_MASK 0x20000000u
12205 #define SAI_TCR2_BCS_SHIFT 29u
12206 #define SAI_TCR2_BCS_WIDTH 1u
12207 #define SAI_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_BCS_SHIFT))&SAI_TCR2_BCS_MASK)
12208 #define SAI_TCR2_SYNC_MASK 0xC0000000u
12209 #define SAI_TCR2_SYNC_SHIFT 30u
12210 #define SAI_TCR2_SYNC_WIDTH 2u
12211 #define SAI_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR2_SYNC_SHIFT))&SAI_TCR2_SYNC_MASK)
12213 #define SAI_TCR3_WDFL_MASK 0xFu
12214 #define SAI_TCR3_WDFL_SHIFT 0u
12215 #define SAI_TCR3_WDFL_WIDTH 4u
12216 #define SAI_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR3_WDFL_SHIFT))&SAI_TCR3_WDFL_MASK)
12217 #define SAI_TCR3_TCE_MASK 0xF0000u
12218 #define SAI_TCR3_TCE_SHIFT 16u
12219 #define SAI_TCR3_TCE_WIDTH 4u
12220 #define SAI_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR3_TCE_SHIFT))&SAI_TCR3_TCE_MASK)
12221 #define SAI_TCR3_CFR_MASK 0xF000000u
12222 #define SAI_TCR3_CFR_SHIFT 24u
12223 #define SAI_TCR3_CFR_WIDTH 4u
12224 #define SAI_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR3_CFR_SHIFT))&SAI_TCR3_CFR_MASK)
12226 #define SAI_TCR4_FSD_MASK 0x1u
12227 #define SAI_TCR4_FSD_SHIFT 0u
12228 #define SAI_TCR4_FSD_WIDTH 1u
12229 #define SAI_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FSD_SHIFT))&SAI_TCR4_FSD_MASK)
12230 #define SAI_TCR4_FSP_MASK 0x2u
12231 #define SAI_TCR4_FSP_SHIFT 1u
12232 #define SAI_TCR4_FSP_WIDTH 1u
12233 #define SAI_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FSP_SHIFT))&SAI_TCR4_FSP_MASK)
12234 #define SAI_TCR4_ONDEM_MASK 0x4u
12235 #define SAI_TCR4_ONDEM_SHIFT 2u
12236 #define SAI_TCR4_ONDEM_WIDTH 1u
12237 #define SAI_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_ONDEM_SHIFT))&SAI_TCR4_ONDEM_MASK)
12238 #define SAI_TCR4_FSE_MASK 0x8u
12239 #define SAI_TCR4_FSE_SHIFT 3u
12240 #define SAI_TCR4_FSE_WIDTH 1u
12241 #define SAI_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FSE_SHIFT))&SAI_TCR4_FSE_MASK)
12242 #define SAI_TCR4_MF_MASK 0x10u
12243 #define SAI_TCR4_MF_SHIFT 4u
12244 #define SAI_TCR4_MF_WIDTH 1u
12245 #define SAI_TCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_MF_SHIFT))&SAI_TCR4_MF_MASK)
12246 #define SAI_TCR4_CHMOD_MASK 0x20u
12247 #define SAI_TCR4_CHMOD_SHIFT 5u
12248 #define SAI_TCR4_CHMOD_WIDTH 1u
12249 #define SAI_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_CHMOD_SHIFT))&SAI_TCR4_CHMOD_MASK)
12250 #define SAI_TCR4_SYWD_MASK 0x1F00u
12251 #define SAI_TCR4_SYWD_SHIFT 8u
12252 #define SAI_TCR4_SYWD_WIDTH 5u
12253 #define SAI_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_SYWD_SHIFT))&SAI_TCR4_SYWD_MASK)
12254 #define SAI_TCR4_FRSZ_MASK 0xF0000u
12255 #define SAI_TCR4_FRSZ_SHIFT 16u
12256 #define SAI_TCR4_FRSZ_WIDTH 4u
12257 #define SAI_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FRSZ_SHIFT))&SAI_TCR4_FRSZ_MASK)
12258 #define SAI_TCR4_FPACK_MASK 0x3000000u
12259 #define SAI_TCR4_FPACK_SHIFT 24u
12260 #define SAI_TCR4_FPACK_WIDTH 2u
12261 #define SAI_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FPACK_SHIFT))&SAI_TCR4_FPACK_MASK)
12262 #define SAI_TCR4_FCOMB_MASK 0xC000000u
12263 #define SAI_TCR4_FCOMB_SHIFT 26u
12264 #define SAI_TCR4_FCOMB_WIDTH 2u
12265 #define SAI_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FCOMB_SHIFT))&SAI_TCR4_FCOMB_MASK)
12266 #define SAI_TCR4_FCONT_MASK 0x10000000u
12267 #define SAI_TCR4_FCONT_SHIFT 28u
12268 #define SAI_TCR4_FCONT_WIDTH 1u
12269 #define SAI_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR4_FCONT_SHIFT))&SAI_TCR4_FCONT_MASK)
12271 #define SAI_TCR5_FBT_MASK 0x1F00u
12272 #define SAI_TCR5_FBT_SHIFT 8u
12273 #define SAI_TCR5_FBT_WIDTH 5u
12274 #define SAI_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR5_FBT_SHIFT))&SAI_TCR5_FBT_MASK)
12275 #define SAI_TCR5_W0W_MASK 0x1F0000u
12276 #define SAI_TCR5_W0W_SHIFT 16u
12277 #define SAI_TCR5_W0W_WIDTH 5u
12278 #define SAI_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR5_W0W_SHIFT))&SAI_TCR5_W0W_MASK)
12279 #define SAI_TCR5_WNW_MASK 0x1F000000u
12280 #define SAI_TCR5_WNW_SHIFT 24u
12281 #define SAI_TCR5_WNW_WIDTH 5u
12282 #define SAI_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<SAI_TCR5_WNW_SHIFT))&SAI_TCR5_WNW_MASK)
12284 #define SAI_TDR_TDR_MASK 0xFFFFFFFFu
12285 #define SAI_TDR_TDR_SHIFT 0u
12286 #define SAI_TDR_TDR_WIDTH 32u
12287 #define SAI_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<SAI_TDR_TDR_SHIFT))&SAI_TDR_TDR_MASK)
12289 #define SAI_TFR_RFP_MASK 0xFu
12290 #define SAI_TFR_RFP_SHIFT 0u
12291 #define SAI_TFR_RFP_WIDTH 4u
12292 #define SAI_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<SAI_TFR_RFP_SHIFT))&SAI_TFR_RFP_MASK)
12293 #define SAI_TFR_WFP_MASK 0xF0000u
12294 #define SAI_TFR_WFP_SHIFT 16u
12295 #define SAI_TFR_WFP_WIDTH 4u
12296 #define SAI_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<SAI_TFR_WFP_SHIFT))&SAI_TFR_WFP_MASK)
12297 #define SAI_TFR_WCP_MASK 0x80000000u
12298 #define SAI_TFR_WCP_SHIFT 31u
12299 #define SAI_TFR_WCP_WIDTH 1u
12300 #define SAI_TFR_WCP(x) (((uint32_t)(((uint32_t)(x))<<SAI_TFR_WCP_SHIFT))&SAI_TFR_WCP_MASK)
12302 #define SAI_TMR_TWM_MASK 0xFFFFu
12303 #define SAI_TMR_TWM_SHIFT 0u
12304 #define SAI_TMR_TWM_WIDTH 16u
12305 #define SAI_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<SAI_TMR_TWM_SHIFT))&SAI_TMR_TWM_MASK)
12307 #define SAI_RCSR_FRDE_MASK 0x1u
12308 #define SAI_RCSR_FRDE_SHIFT 0u
12309 #define SAI_RCSR_FRDE_WIDTH 1u
12310 #define SAI_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FRDE_SHIFT))&SAI_RCSR_FRDE_MASK)
12311 #define SAI_RCSR_FWDE_MASK 0x2u
12312 #define SAI_RCSR_FWDE_SHIFT 1u
12313 #define SAI_RCSR_FWDE_WIDTH 1u
12314 #define SAI_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FWDE_SHIFT))&SAI_RCSR_FWDE_MASK)
12315 #define SAI_RCSR_FRIE_MASK 0x100u
12316 #define SAI_RCSR_FRIE_SHIFT 8u
12317 #define SAI_RCSR_FRIE_WIDTH 1u
12318 #define SAI_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FRIE_SHIFT))&SAI_RCSR_FRIE_MASK)
12319 #define SAI_RCSR_FWIE_MASK 0x200u
12320 #define SAI_RCSR_FWIE_SHIFT 9u
12321 #define SAI_RCSR_FWIE_WIDTH 1u
12322 #define SAI_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FWIE_SHIFT))&SAI_RCSR_FWIE_MASK)
12323 #define SAI_RCSR_FEIE_MASK 0x400u
12324 #define SAI_RCSR_FEIE_SHIFT 10u
12325 #define SAI_RCSR_FEIE_WIDTH 1u
12326 #define SAI_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FEIE_SHIFT))&SAI_RCSR_FEIE_MASK)
12327 #define SAI_RCSR_SEIE_MASK 0x800u
12328 #define SAI_RCSR_SEIE_SHIFT 11u
12329 #define SAI_RCSR_SEIE_WIDTH 1u
12330 #define SAI_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_SEIE_SHIFT))&SAI_RCSR_SEIE_MASK)
12331 #define SAI_RCSR_WSIE_MASK 0x1000u
12332 #define SAI_RCSR_WSIE_SHIFT 12u
12333 #define SAI_RCSR_WSIE_WIDTH 1u
12334 #define SAI_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_WSIE_SHIFT))&SAI_RCSR_WSIE_MASK)
12335 #define SAI_RCSR_FRF_MASK 0x10000u
12336 #define SAI_RCSR_FRF_SHIFT 16u
12337 #define SAI_RCSR_FRF_WIDTH 1u
12338 #define SAI_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FRF_SHIFT))&SAI_RCSR_FRF_MASK)
12339 #define SAI_RCSR_FWF_MASK 0x20000u
12340 #define SAI_RCSR_FWF_SHIFT 17u
12341 #define SAI_RCSR_FWF_WIDTH 1u
12342 #define SAI_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FWF_SHIFT))&SAI_RCSR_FWF_MASK)
12343 #define SAI_RCSR_FEF_MASK 0x40000u
12344 #define SAI_RCSR_FEF_SHIFT 18u
12345 #define SAI_RCSR_FEF_WIDTH 1u
12346 #define SAI_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FEF_SHIFT))&SAI_RCSR_FEF_MASK)
12347 #define SAI_RCSR_SEF_MASK 0x80000u
12348 #define SAI_RCSR_SEF_SHIFT 19u
12349 #define SAI_RCSR_SEF_WIDTH 1u
12350 #define SAI_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_SEF_SHIFT))&SAI_RCSR_SEF_MASK)
12351 #define SAI_RCSR_WSF_MASK 0x100000u
12352 #define SAI_RCSR_WSF_SHIFT 20u
12353 #define SAI_RCSR_WSF_WIDTH 1u
12354 #define SAI_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_WSF_SHIFT))&SAI_RCSR_WSF_MASK)
12355 #define SAI_RCSR_SR_MASK 0x1000000u
12356 #define SAI_RCSR_SR_SHIFT 24u
12357 #define SAI_RCSR_SR_WIDTH 1u
12358 #define SAI_RCSR_SR(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_SR_SHIFT))&SAI_RCSR_SR_MASK)
12359 #define SAI_RCSR_FR_MASK 0x2000000u
12360 #define SAI_RCSR_FR_SHIFT 25u
12361 #define SAI_RCSR_FR_WIDTH 1u
12362 #define SAI_RCSR_FR(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_FR_SHIFT))&SAI_RCSR_FR_MASK)
12363 #define SAI_RCSR_BCE_MASK 0x10000000u
12364 #define SAI_RCSR_BCE_SHIFT 28u
12365 #define SAI_RCSR_BCE_WIDTH 1u
12366 #define SAI_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_BCE_SHIFT))&SAI_RCSR_BCE_MASK)
12367 #define SAI_RCSR_DBGE_MASK 0x20000000u
12368 #define SAI_RCSR_DBGE_SHIFT 29u
12369 #define SAI_RCSR_DBGE_WIDTH 1u
12370 #define SAI_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_DBGE_SHIFT))&SAI_RCSR_DBGE_MASK)
12371 #define SAI_RCSR_RE_MASK 0x80000000u
12372 #define SAI_RCSR_RE_SHIFT 31u
12373 #define SAI_RCSR_RE_WIDTH 1u
12374 #define SAI_RCSR_RE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCSR_RE_SHIFT))&SAI_RCSR_RE_MASK)
12376 #define SAI_RCR1_RFW_MASK 0x7u
12377 #define SAI_RCR1_RFW_SHIFT 0u
12378 #define SAI_RCR1_RFW_WIDTH 3u
12379 #define SAI_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR1_RFW_SHIFT))&SAI_RCR1_RFW_MASK)
12381 #define SAI_RCR2_DIV_MASK 0xFFu
12382 #define SAI_RCR2_DIV_SHIFT 0u
12383 #define SAI_RCR2_DIV_WIDTH 8u
12384 #define SAI_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_DIV_SHIFT))&SAI_RCR2_DIV_MASK)
12385 #define SAI_RCR2_BCD_MASK 0x1000000u
12386 #define SAI_RCR2_BCD_SHIFT 24u
12387 #define SAI_RCR2_BCD_WIDTH 1u
12388 #define SAI_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_BCD_SHIFT))&SAI_RCR2_BCD_MASK)
12389 #define SAI_RCR2_BCP_MASK 0x2000000u
12390 #define SAI_RCR2_BCP_SHIFT 25u
12391 #define SAI_RCR2_BCP_WIDTH 1u
12392 #define SAI_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_BCP_SHIFT))&SAI_RCR2_BCP_MASK)
12393 #define SAI_RCR2_MSEL_MASK 0xC000000u
12394 #define SAI_RCR2_MSEL_SHIFT 26u
12395 #define SAI_RCR2_MSEL_WIDTH 2u
12396 #define SAI_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_MSEL_SHIFT))&SAI_RCR2_MSEL_MASK)
12397 #define SAI_RCR2_BCI_MASK 0x10000000u
12398 #define SAI_RCR2_BCI_SHIFT 28u
12399 #define SAI_RCR2_BCI_WIDTH 1u
12400 #define SAI_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_BCI_SHIFT))&SAI_RCR2_BCI_MASK)
12401 #define SAI_RCR2_BCS_MASK 0x20000000u
12402 #define SAI_RCR2_BCS_SHIFT 29u
12403 #define SAI_RCR2_BCS_WIDTH 1u
12404 #define SAI_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_BCS_SHIFT))&SAI_RCR2_BCS_MASK)
12405 #define SAI_RCR2_SYNC_MASK 0xC0000000u
12406 #define SAI_RCR2_SYNC_SHIFT 30u
12407 #define SAI_RCR2_SYNC_WIDTH 2u
12408 #define SAI_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR2_SYNC_SHIFT))&SAI_RCR2_SYNC_MASK)
12410 #define SAI_RCR3_WDFL_MASK 0xFu
12411 #define SAI_RCR3_WDFL_SHIFT 0u
12412 #define SAI_RCR3_WDFL_WIDTH 4u
12413 #define SAI_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR3_WDFL_SHIFT))&SAI_RCR3_WDFL_MASK)
12414 #define SAI_RCR3_RCE_MASK 0xF0000u
12415 #define SAI_RCR3_RCE_SHIFT 16u
12416 #define SAI_RCR3_RCE_WIDTH 4u
12417 #define SAI_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR3_RCE_SHIFT))&SAI_RCR3_RCE_MASK)
12418 #define SAI_RCR3_CFR_MASK 0xF000000u
12419 #define SAI_RCR3_CFR_SHIFT 24u
12420 #define SAI_RCR3_CFR_WIDTH 4u
12421 #define SAI_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR3_CFR_SHIFT))&SAI_RCR3_CFR_MASK)
12423 #define SAI_RCR4_FSD_MASK 0x1u
12424 #define SAI_RCR4_FSD_SHIFT 0u
12425 #define SAI_RCR4_FSD_WIDTH 1u
12426 #define SAI_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FSD_SHIFT))&SAI_RCR4_FSD_MASK)
12427 #define SAI_RCR4_FSP_MASK 0x2u
12428 #define SAI_RCR4_FSP_SHIFT 1u
12429 #define SAI_RCR4_FSP_WIDTH 1u
12430 #define SAI_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FSP_SHIFT))&SAI_RCR4_FSP_MASK)
12431 #define SAI_RCR4_ONDEM_MASK 0x4u
12432 #define SAI_RCR4_ONDEM_SHIFT 2u
12433 #define SAI_RCR4_ONDEM_WIDTH 1u
12434 #define SAI_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_ONDEM_SHIFT))&SAI_RCR4_ONDEM_MASK)
12435 #define SAI_RCR4_FSE_MASK 0x8u
12436 #define SAI_RCR4_FSE_SHIFT 3u
12437 #define SAI_RCR4_FSE_WIDTH 1u
12438 #define SAI_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FSE_SHIFT))&SAI_RCR4_FSE_MASK)
12439 #define SAI_RCR4_MF_MASK 0x10u
12440 #define SAI_RCR4_MF_SHIFT 4u
12441 #define SAI_RCR4_MF_WIDTH 1u
12442 #define SAI_RCR4_MF(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_MF_SHIFT))&SAI_RCR4_MF_MASK)
12443 #define SAI_RCR4_SYWD_MASK 0x1F00u
12444 #define SAI_RCR4_SYWD_SHIFT 8u
12445 #define SAI_RCR4_SYWD_WIDTH 5u
12446 #define SAI_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_SYWD_SHIFT))&SAI_RCR4_SYWD_MASK)
12447 #define SAI_RCR4_FRSZ_MASK 0xF0000u
12448 #define SAI_RCR4_FRSZ_SHIFT 16u
12449 #define SAI_RCR4_FRSZ_WIDTH 4u
12450 #define SAI_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FRSZ_SHIFT))&SAI_RCR4_FRSZ_MASK)
12451 #define SAI_RCR4_FPACK_MASK 0x3000000u
12452 #define SAI_RCR4_FPACK_SHIFT 24u
12453 #define SAI_RCR4_FPACK_WIDTH 2u
12454 #define SAI_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FPACK_SHIFT))&SAI_RCR4_FPACK_MASK)
12455 #define SAI_RCR4_FCOMB_MASK 0xC000000u
12456 #define SAI_RCR4_FCOMB_SHIFT 26u
12457 #define SAI_RCR4_FCOMB_WIDTH 2u
12458 #define SAI_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FCOMB_SHIFT))&SAI_RCR4_FCOMB_MASK)
12459 #define SAI_RCR4_FCONT_MASK 0x10000000u
12460 #define SAI_RCR4_FCONT_SHIFT 28u
12461 #define SAI_RCR4_FCONT_WIDTH 1u
12462 #define SAI_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR4_FCONT_SHIFT))&SAI_RCR4_FCONT_MASK)
12464 #define SAI_RCR5_FBT_MASK 0x1F00u
12465 #define SAI_RCR5_FBT_SHIFT 8u
12466 #define SAI_RCR5_FBT_WIDTH 5u
12467 #define SAI_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR5_FBT_SHIFT))&SAI_RCR5_FBT_MASK)
12468 #define SAI_RCR5_W0W_MASK 0x1F0000u
12469 #define SAI_RCR5_W0W_SHIFT 16u
12470 #define SAI_RCR5_W0W_WIDTH 5u
12471 #define SAI_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR5_W0W_SHIFT))&SAI_RCR5_W0W_MASK)
12472 #define SAI_RCR5_WNW_MASK 0x1F000000u
12473 #define SAI_RCR5_WNW_SHIFT 24u
12474 #define SAI_RCR5_WNW_WIDTH 5u
12475 #define SAI_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<SAI_RCR5_WNW_SHIFT))&SAI_RCR5_WNW_MASK)
12477 #define SAI_RDR_RDR_MASK 0xFFFFFFFFu
12478 #define SAI_RDR_RDR_SHIFT 0u
12479 #define SAI_RDR_RDR_WIDTH 32u
12480 #define SAI_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<SAI_RDR_RDR_SHIFT))&SAI_RDR_RDR_MASK)
12482 #define SAI_RFR_RFP_MASK 0xFu
12483 #define SAI_RFR_RFP_SHIFT 0u
12484 #define SAI_RFR_RFP_WIDTH 4u
12485 #define SAI_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<SAI_RFR_RFP_SHIFT))&SAI_RFR_RFP_MASK)
12486 #define SAI_RFR_RCP_MASK 0x8000u
12487 #define SAI_RFR_RCP_SHIFT 15u
12488 #define SAI_RFR_RCP_WIDTH 1u
12489 #define SAI_RFR_RCP(x) (((uint32_t)(((uint32_t)(x))<<SAI_RFR_RCP_SHIFT))&SAI_RFR_RCP_MASK)
12490 #define SAI_RFR_WFP_MASK 0xF0000u
12491 #define SAI_RFR_WFP_SHIFT 16u
12492 #define SAI_RFR_WFP_WIDTH 4u
12493 #define SAI_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<SAI_RFR_WFP_SHIFT))&SAI_RFR_WFP_MASK)
12495 #define SAI_RMR_RWM_MASK 0xFFFFu
12496 #define SAI_RMR_RWM_SHIFT 0u
12497 #define SAI_RMR_RWM_WIDTH 16u
12498 #define SAI_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<SAI_RMR_RWM_SHIFT))&SAI_RMR_RWM_MASK)
12526 uint8_t RESERVED_0[8];
12532 uint8_t RESERVED_1[220];
12536 uint8_t RESERVED_2[244];
12540 uint8_t RESERVED_3[244];
12544 uint8_t RESERVED_4[756];
12551 #define SCG_INSTANCE_COUNT (1u)
12556 #define SCG_BASE (0x40064000u)
12558 #define SCG ((SCG_Type *)SCG_BASE)
12560 #define SCG_BASE_ADDRS { SCG_BASE }
12562 #define SCG_BASE_PTRS { SCG }
12564 #define SCG_IRQS_ARR_COUNT (1u)
12566 #define SCG_IRQS_CH_COUNT (1u)
12568 #define SCG_IRQS { SCG_IRQn }
12580 #define SCG_VERID_VERSION_MASK 0xFFFFFFFFu
12581 #define SCG_VERID_VERSION_SHIFT 0u
12582 #define SCG_VERID_VERSION_WIDTH 32u
12583 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x))<<SCG_VERID_VERSION_SHIFT))&SCG_VERID_VERSION_MASK)
12585 #define SCG_PARAM_CLKPRES_MASK 0xFFu
12586 #define SCG_PARAM_CLKPRES_SHIFT 0u
12587 #define SCG_PARAM_CLKPRES_WIDTH 8u
12588 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_CLKPRES_SHIFT))&SCG_PARAM_CLKPRES_MASK)
12589 #define SCG_PARAM_DIVPRES_MASK 0xF8000000u
12590 #define SCG_PARAM_DIVPRES_SHIFT 27u
12591 #define SCG_PARAM_DIVPRES_WIDTH 5u
12592 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_DIVPRES_SHIFT))&SCG_PARAM_DIVPRES_MASK)
12594 #define SCG_CSR_DIVSLOW_MASK 0xFu
12595 #define SCG_CSR_DIVSLOW_SHIFT 0u
12596 #define SCG_CSR_DIVSLOW_WIDTH 4u
12597 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVSLOW_SHIFT))&SCG_CSR_DIVSLOW_MASK)
12598 #define SCG_CSR_DIVBUS_MASK 0xF0u
12599 #define SCG_CSR_DIVBUS_SHIFT 4u
12600 #define SCG_CSR_DIVBUS_WIDTH 4u
12601 #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVBUS_SHIFT))&SCG_CSR_DIVBUS_MASK)
12602 #define SCG_CSR_DIVCORE_MASK 0xF0000u
12603 #define SCG_CSR_DIVCORE_SHIFT 16u
12604 #define SCG_CSR_DIVCORE_WIDTH 4u
12605 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVCORE_SHIFT))&SCG_CSR_DIVCORE_MASK)
12606 #define SCG_CSR_SCS_MASK 0xF000000u
12607 #define SCG_CSR_SCS_SHIFT 24u
12608 #define SCG_CSR_SCS_WIDTH 4u
12609 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_SCS_SHIFT))&SCG_CSR_SCS_MASK)
12611 #define SCG_RCCR_DIVSLOW_MASK 0xFu
12612 #define SCG_RCCR_DIVSLOW_SHIFT 0u
12613 #define SCG_RCCR_DIVSLOW_WIDTH 4u
12614 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVSLOW_SHIFT))&SCG_RCCR_DIVSLOW_MASK)
12615 #define SCG_RCCR_DIVBUS_MASK 0xF0u
12616 #define SCG_RCCR_DIVBUS_SHIFT 4u
12617 #define SCG_RCCR_DIVBUS_WIDTH 4u
12618 #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVBUS_SHIFT))&SCG_RCCR_DIVBUS_MASK)
12619 #define SCG_RCCR_DIVCORE_MASK 0xF0000u
12620 #define SCG_RCCR_DIVCORE_SHIFT 16u
12621 #define SCG_RCCR_DIVCORE_WIDTH 4u
12622 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVCORE_SHIFT))&SCG_RCCR_DIVCORE_MASK)
12623 #define SCG_RCCR_SCS_MASK 0xF000000u
12624 #define SCG_RCCR_SCS_SHIFT 24u
12625 #define SCG_RCCR_SCS_WIDTH 4u
12626 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_SCS_SHIFT))&SCG_RCCR_SCS_MASK)
12628 #define SCG_VCCR_DIVSLOW_MASK 0xFu
12629 #define SCG_VCCR_DIVSLOW_SHIFT 0u
12630 #define SCG_VCCR_DIVSLOW_WIDTH 4u
12631 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVSLOW_SHIFT))&SCG_VCCR_DIVSLOW_MASK)
12632 #define SCG_VCCR_DIVBUS_MASK 0xF0u
12633 #define SCG_VCCR_DIVBUS_SHIFT 4u
12634 #define SCG_VCCR_DIVBUS_WIDTH 4u
12635 #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVBUS_SHIFT))&SCG_VCCR_DIVBUS_MASK)
12636 #define SCG_VCCR_DIVCORE_MASK 0xF0000u
12637 #define SCG_VCCR_DIVCORE_SHIFT 16u
12638 #define SCG_VCCR_DIVCORE_WIDTH 4u
12639 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVCORE_SHIFT))&SCG_VCCR_DIVCORE_MASK)
12640 #define SCG_VCCR_SCS_MASK 0xF000000u
12641 #define SCG_VCCR_SCS_SHIFT 24u
12642 #define SCG_VCCR_SCS_WIDTH 4u
12643 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_SCS_SHIFT))&SCG_VCCR_SCS_MASK)
12645 #define SCG_HCCR_DIVSLOW_MASK 0xFu
12646 #define SCG_HCCR_DIVSLOW_SHIFT 0u
12647 #define SCG_HCCR_DIVSLOW_WIDTH 4u
12648 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVSLOW_SHIFT))&SCG_HCCR_DIVSLOW_MASK)
12649 #define SCG_HCCR_DIVBUS_MASK 0xF0u
12650 #define SCG_HCCR_DIVBUS_SHIFT 4u
12651 #define SCG_HCCR_DIVBUS_WIDTH 4u
12652 #define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVBUS_SHIFT))&SCG_HCCR_DIVBUS_MASK)
12653 #define SCG_HCCR_DIVCORE_MASK 0xF0000u
12654 #define SCG_HCCR_DIVCORE_SHIFT 16u
12655 #define SCG_HCCR_DIVCORE_WIDTH 4u
12656 #define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVCORE_SHIFT))&SCG_HCCR_DIVCORE_MASK)
12657 #define SCG_HCCR_SCS_MASK 0xF000000u
12658 #define SCG_HCCR_SCS_SHIFT 24u
12659 #define SCG_HCCR_SCS_WIDTH 4u
12660 #define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_SCS_SHIFT))&SCG_HCCR_SCS_MASK)
12662 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK 0xF000000u
12663 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT 24u
12664 #define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH 4u
12665 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT))&SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
12667 #define SCG_SOSCCSR_SOSCEN_MASK 0x1u
12668 #define SCG_SOSCCSR_SOSCEN_SHIFT 0u
12669 #define SCG_SOSCCSR_SOSCEN_WIDTH 1u
12670 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCEN_SHIFT))&SCG_SOSCCSR_SOSCEN_MASK)
12671 #define SCG_SOSCCSR_SOSCCM_MASK 0x10000u
12672 #define SCG_SOSCCSR_SOSCCM_SHIFT 16u
12673 #define SCG_SOSCCSR_SOSCCM_WIDTH 1u
12674 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCM_SHIFT))&SCG_SOSCCSR_SOSCCM_MASK)
12675 #define SCG_SOSCCSR_SOSCCMRE_MASK 0x20000u
12676 #define SCG_SOSCCSR_SOSCCMRE_SHIFT 17u
12677 #define SCG_SOSCCSR_SOSCCMRE_WIDTH 1u
12678 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCMRE_SHIFT))&SCG_SOSCCSR_SOSCCMRE_MASK)
12679 #define SCG_SOSCCSR_LK_MASK 0x800000u
12680 #define SCG_SOSCCSR_LK_SHIFT 23u
12681 #define SCG_SOSCCSR_LK_WIDTH 1u
12682 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_LK_SHIFT))&SCG_SOSCCSR_LK_MASK)
12683 #define SCG_SOSCCSR_SOSCVLD_MASK 0x1000000u
12684 #define SCG_SOSCCSR_SOSCVLD_SHIFT 24u
12685 #define SCG_SOSCCSR_SOSCVLD_WIDTH 1u
12686 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCVLD_SHIFT))&SCG_SOSCCSR_SOSCVLD_MASK)
12687 #define SCG_SOSCCSR_SOSCSEL_MASK 0x2000000u
12688 #define SCG_SOSCCSR_SOSCSEL_SHIFT 25u
12689 #define SCG_SOSCCSR_SOSCSEL_WIDTH 1u
12690 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSEL_SHIFT))&SCG_SOSCCSR_SOSCSEL_MASK)
12691 #define SCG_SOSCCSR_SOSCERR_MASK 0x4000000u
12692 #define SCG_SOSCCSR_SOSCERR_SHIFT 26u
12693 #define SCG_SOSCCSR_SOSCERR_WIDTH 1u
12694 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERR_SHIFT))&SCG_SOSCCSR_SOSCERR_MASK)
12696 #define SCG_SOSCDIV_SOSCDIV1_MASK 0x7u
12697 #define SCG_SOSCDIV_SOSCDIV1_SHIFT 0u
12698 #define SCG_SOSCDIV_SOSCDIV1_WIDTH 3u
12699 #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV1_SHIFT))&SCG_SOSCDIV_SOSCDIV1_MASK)
12700 #define SCG_SOSCDIV_SOSCDIV2_MASK 0x700u
12701 #define SCG_SOSCDIV_SOSCDIV2_SHIFT 8u
12702 #define SCG_SOSCDIV_SOSCDIV2_WIDTH 3u
12703 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV2_SHIFT))&SCG_SOSCDIV_SOSCDIV2_MASK)
12705 #define SCG_SOSCCFG_EREFS_MASK 0x4u
12706 #define SCG_SOSCCFG_EREFS_SHIFT 2u
12707 #define SCG_SOSCCFG_EREFS_WIDTH 1u
12708 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_EREFS_SHIFT))&SCG_SOSCCFG_EREFS_MASK)
12709 #define SCG_SOSCCFG_HGO_MASK 0x8u
12710 #define SCG_SOSCCFG_HGO_SHIFT 3u
12711 #define SCG_SOSCCFG_HGO_WIDTH 1u
12712 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_HGO_SHIFT))&SCG_SOSCCFG_HGO_MASK)
12713 #define SCG_SOSCCFG_RANGE_MASK 0x30u
12714 #define SCG_SOSCCFG_RANGE_SHIFT 4u
12715 #define SCG_SOSCCFG_RANGE_WIDTH 2u
12716 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_RANGE_SHIFT))&SCG_SOSCCFG_RANGE_MASK)
12718 #define SCG_SIRCCSR_SIRCEN_MASK 0x1u
12719 #define SCG_SIRCCSR_SIRCEN_SHIFT 0u
12720 #define SCG_SIRCCSR_SIRCEN_WIDTH 1u
12721 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCEN_SHIFT))&SCG_SIRCCSR_SIRCEN_MASK)
12722 #define SCG_SIRCCSR_SIRCSTEN_MASK 0x2u
12723 #define SCG_SIRCCSR_SIRCSTEN_SHIFT 1u
12724 #define SCG_SIRCCSR_SIRCSTEN_WIDTH 1u
12725 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSTEN_SHIFT))&SCG_SIRCCSR_SIRCSTEN_MASK)
12726 #define SCG_SIRCCSR_SIRCLPEN_MASK 0x4u
12727 #define SCG_SIRCCSR_SIRCLPEN_SHIFT 2u
12728 #define SCG_SIRCCSR_SIRCLPEN_WIDTH 1u
12729 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCLPEN_SHIFT))&SCG_SIRCCSR_SIRCLPEN_MASK)
12730 #define SCG_SIRCCSR_LK_MASK 0x800000u
12731 #define SCG_SIRCCSR_LK_SHIFT 23u
12732 #define SCG_SIRCCSR_LK_WIDTH 1u
12733 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_LK_SHIFT))&SCG_SIRCCSR_LK_MASK)
12734 #define SCG_SIRCCSR_SIRCVLD_MASK 0x1000000u
12735 #define SCG_SIRCCSR_SIRCVLD_SHIFT 24u
12736 #define SCG_SIRCCSR_SIRCVLD_WIDTH 1u
12737 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCVLD_SHIFT))&SCG_SIRCCSR_SIRCVLD_MASK)
12738 #define SCG_SIRCCSR_SIRCSEL_MASK 0x2000000u
12739 #define SCG_SIRCCSR_SIRCSEL_SHIFT 25u
12740 #define SCG_SIRCCSR_SIRCSEL_WIDTH 1u
12741 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSEL_SHIFT))&SCG_SIRCCSR_SIRCSEL_MASK)
12743 #define SCG_SIRCDIV_SIRCDIV1_MASK 0x7u
12744 #define SCG_SIRCDIV_SIRCDIV1_SHIFT 0u
12745 #define SCG_SIRCDIV_SIRCDIV1_WIDTH 3u
12746 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV1_SHIFT))&SCG_SIRCDIV_SIRCDIV1_MASK)
12747 #define SCG_SIRCDIV_SIRCDIV2_MASK 0x700u
12748 #define SCG_SIRCDIV_SIRCDIV2_SHIFT 8u
12749 #define SCG_SIRCDIV_SIRCDIV2_WIDTH 3u
12750 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV2_SHIFT))&SCG_SIRCDIV_SIRCDIV2_MASK)
12752 #define SCG_SIRCCFG_RANGE_MASK 0x1u
12753 #define SCG_SIRCCFG_RANGE_SHIFT 0u
12754 #define SCG_SIRCCFG_RANGE_WIDTH 1u
12755 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCFG_RANGE_SHIFT))&SCG_SIRCCFG_RANGE_MASK)
12757 #define SCG_FIRCCSR_FIRCEN_MASK 0x1u
12758 #define SCG_FIRCCSR_FIRCEN_SHIFT 0u
12759 #define SCG_FIRCCSR_FIRCEN_WIDTH 1u
12760 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCEN_SHIFT))&SCG_FIRCCSR_FIRCEN_MASK)
12761 #define SCG_FIRCCSR_FIRCREGOFF_MASK 0x8u
12762 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT 3u
12763 #define SCG_FIRCCSR_FIRCREGOFF_WIDTH 1u
12764 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCREGOFF_SHIFT))&SCG_FIRCCSR_FIRCREGOFF_MASK)
12765 #define SCG_FIRCCSR_LK_MASK 0x800000u
12766 #define SCG_FIRCCSR_LK_SHIFT 23u
12767 #define SCG_FIRCCSR_LK_WIDTH 1u
12768 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_LK_SHIFT))&SCG_FIRCCSR_LK_MASK)
12769 #define SCG_FIRCCSR_FIRCVLD_MASK 0x1000000u
12770 #define SCG_FIRCCSR_FIRCVLD_SHIFT 24u
12771 #define SCG_FIRCCSR_FIRCVLD_WIDTH 1u
12772 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCVLD_SHIFT))&SCG_FIRCCSR_FIRCVLD_MASK)
12773 #define SCG_FIRCCSR_FIRCSEL_MASK 0x2000000u
12774 #define SCG_FIRCCSR_FIRCSEL_SHIFT 25u
12775 #define SCG_FIRCCSR_FIRCSEL_WIDTH 1u
12776 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSEL_SHIFT))&SCG_FIRCCSR_FIRCSEL_MASK)
12777 #define SCG_FIRCCSR_FIRCERR_MASK 0x4000000u
12778 #define SCG_FIRCCSR_FIRCERR_SHIFT 26u
12779 #define SCG_FIRCCSR_FIRCERR_WIDTH 1u
12780 #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCERR_SHIFT))&SCG_FIRCCSR_FIRCERR_MASK)
12782 #define SCG_FIRCDIV_FIRCDIV1_MASK 0x7u
12783 #define SCG_FIRCDIV_FIRCDIV1_SHIFT 0u
12784 #define SCG_FIRCDIV_FIRCDIV1_WIDTH 3u
12785 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV1_SHIFT))&SCG_FIRCDIV_FIRCDIV1_MASK)
12786 #define SCG_FIRCDIV_FIRCDIV2_MASK 0x700u
12787 #define SCG_FIRCDIV_FIRCDIV2_SHIFT 8u
12788 #define SCG_FIRCDIV_FIRCDIV2_WIDTH 3u
12789 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV2_SHIFT))&SCG_FIRCDIV_FIRCDIV2_MASK)
12791 #define SCG_FIRCCFG_RANGE_MASK 0x3u
12792 #define SCG_FIRCCFG_RANGE_SHIFT 0u
12793 #define SCG_FIRCCFG_RANGE_WIDTH 2u
12794 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCFG_RANGE_SHIFT))&SCG_FIRCCFG_RANGE_MASK)
12796 #define SCG_SPLLCSR_SPLLEN_MASK 0x1u
12797 #define SCG_SPLLCSR_SPLLEN_SHIFT 0u
12798 #define SCG_SPLLCSR_SPLLEN_WIDTH 1u
12799 #define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLEN_SHIFT))&SCG_SPLLCSR_SPLLEN_MASK)
12800 #define SCG_SPLLCSR_SPLLCM_MASK 0x10000u
12801 #define SCG_SPLLCSR_SPLLCM_SHIFT 16u
12802 #define SCG_SPLLCSR_SPLLCM_WIDTH 1u
12803 #define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCM_SHIFT))&SCG_SPLLCSR_SPLLCM_MASK)
12804 #define SCG_SPLLCSR_SPLLCMRE_MASK 0x20000u
12805 #define SCG_SPLLCSR_SPLLCMRE_SHIFT 17u
12806 #define SCG_SPLLCSR_SPLLCMRE_WIDTH 1u
12807 #define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCMRE_SHIFT))&SCG_SPLLCSR_SPLLCMRE_MASK)
12808 #define SCG_SPLLCSR_LK_MASK 0x800000u
12809 #define SCG_SPLLCSR_LK_SHIFT 23u
12810 #define SCG_SPLLCSR_LK_WIDTH 1u
12811 #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_LK_SHIFT))&SCG_SPLLCSR_LK_MASK)
12812 #define SCG_SPLLCSR_SPLLVLD_MASK 0x1000000u
12813 #define SCG_SPLLCSR_SPLLVLD_SHIFT 24u
12814 #define SCG_SPLLCSR_SPLLVLD_WIDTH 1u
12815 #define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLVLD_SHIFT))&SCG_SPLLCSR_SPLLVLD_MASK)
12816 #define SCG_SPLLCSR_SPLLSEL_MASK 0x2000000u
12817 #define SCG_SPLLCSR_SPLLSEL_SHIFT 25u
12818 #define SCG_SPLLCSR_SPLLSEL_WIDTH 1u
12819 #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLSEL_SHIFT))&SCG_SPLLCSR_SPLLSEL_MASK)
12820 #define SCG_SPLLCSR_SPLLERR_MASK 0x4000000u
12821 #define SCG_SPLLCSR_SPLLERR_SHIFT 26u
12822 #define SCG_SPLLCSR_SPLLERR_WIDTH 1u
12823 #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLERR_SHIFT))&SCG_SPLLCSR_SPLLERR_MASK)
12825 #define SCG_SPLLDIV_SPLLDIV1_MASK 0x7u
12826 #define SCG_SPLLDIV_SPLLDIV1_SHIFT 0u
12827 #define SCG_SPLLDIV_SPLLDIV1_WIDTH 3u
12828 #define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV1_SHIFT))&SCG_SPLLDIV_SPLLDIV1_MASK)
12829 #define SCG_SPLLDIV_SPLLDIV2_MASK 0x700u
12830 #define SCG_SPLLDIV_SPLLDIV2_SHIFT 8u
12831 #define SCG_SPLLDIV_SPLLDIV2_WIDTH 3u
12832 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV2_SHIFT))&SCG_SPLLDIV_SPLLDIV2_MASK)
12834 #define SCG_SPLLCFG_PREDIV_MASK 0x700u
12835 #define SCG_SPLLCFG_PREDIV_SHIFT 8u
12836 #define SCG_SPLLCFG_PREDIV_WIDTH 3u
12837 #define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_PREDIV_SHIFT))&SCG_SPLLCFG_PREDIV_MASK)
12838 #define SCG_SPLLCFG_MULT_MASK 0x1F0000u
12839 #define SCG_SPLLCFG_MULT_SHIFT 16u
12840 #define SCG_SPLLCFG_MULT_WIDTH 5u
12841 #define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_MULT_SHIFT))&SCG_SPLLCFG_MULT_MASK)
12867 uint8_t RESERVED_0[4];
12869 uint8_t RESERVED_1[4];
12872 uint8_t RESERVED_2[4];
12877 uint8_t RESERVED_3[24];
12879 uint8_t RESERVED_4[8];
12881 uint8_t RESERVED_5[4];
12886 uint8_t RESERVED_6[4];
12892 #define SIM_INSTANCE_COUNT (1u)
12897 #define SIM_BASE (0x40048000u)
12899 #define SIM ((SIM_Type *)SIM_BASE)
12901 #define SIM_BASE_ADDRS { SIM_BASE }
12903 #define SIM_BASE_PTRS { SIM }
12915 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK 0xFu
12916 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT 0u
12917 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH 4u
12918 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT))&SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK)
12919 #define SIM_CHIPCTL_CLKOUTSEL_MASK 0xF0u
12920 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT 4u
12921 #define SIM_CHIPCTL_CLKOUTSEL_WIDTH 4u
12922 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTSEL_SHIFT))&SIM_CHIPCTL_CLKOUTSEL_MASK)
12923 #define SIM_CHIPCTL_CLKOUTDIV_MASK 0x700u
12924 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT 8u
12925 #define SIM_CHIPCTL_CLKOUTDIV_WIDTH 3u
12926 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTDIV_SHIFT))&SIM_CHIPCTL_CLKOUTDIV_MASK)
12927 #define SIM_CHIPCTL_CLKOUTEN_MASK 0x800u
12928 #define SIM_CHIPCTL_CLKOUTEN_SHIFT 11u
12929 #define SIM_CHIPCTL_CLKOUTEN_WIDTH 1u
12930 #define SIM_CHIPCTL_CLKOUTEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTEN_SHIFT))&SIM_CHIPCTL_CLKOUTEN_MASK)
12931 #define SIM_CHIPCTL_TRACECLK_SEL_MASK 0x1000u
12932 #define SIM_CHIPCTL_TRACECLK_SEL_SHIFT 12u
12933 #define SIM_CHIPCTL_TRACECLK_SEL_WIDTH 1u
12934 #define SIM_CHIPCTL_TRACECLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_TRACECLK_SEL_SHIFT))&SIM_CHIPCTL_TRACECLK_SEL_MASK)
12935 #define SIM_CHIPCTL_PDB_BB_SEL_MASK 0x2000u
12936 #define SIM_CHIPCTL_PDB_BB_SEL_SHIFT 13u
12937 #define SIM_CHIPCTL_PDB_BB_SEL_WIDTH 1u
12938 #define SIM_CHIPCTL_PDB_BB_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_PDB_BB_SEL_SHIFT))&SIM_CHIPCTL_PDB_BB_SEL_MASK)
12939 #define SIM_CHIPCTL_ADC_SUPPLY_MASK 0x70000u
12940 #define SIM_CHIPCTL_ADC_SUPPLY_SHIFT 16u
12941 #define SIM_CHIPCTL_ADC_SUPPLY_WIDTH 3u
12942 #define SIM_CHIPCTL_ADC_SUPPLY(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLY_SHIFT))&SIM_CHIPCTL_ADC_SUPPLY_MASK)
12943 #define SIM_CHIPCTL_ADC_SUPPLYEN_MASK 0x80000u
12944 #define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT 19u
12945 #define SIM_CHIPCTL_ADC_SUPPLYEN_WIDTH 1u
12946 #define SIM_CHIPCTL_ADC_SUPPLYEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT))&SIM_CHIPCTL_ADC_SUPPLYEN_MASK)
12947 #define SIM_CHIPCTL_SRAMU_RETEN_MASK 0x100000u
12948 #define SIM_CHIPCTL_SRAMU_RETEN_SHIFT 20u
12949 #define SIM_CHIPCTL_SRAMU_RETEN_WIDTH 1u
12950 #define SIM_CHIPCTL_SRAMU_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAMU_RETEN_SHIFT))&SIM_CHIPCTL_SRAMU_RETEN_MASK)
12951 #define SIM_CHIPCTL_SRAML_RETEN_MASK 0x200000u
12952 #define SIM_CHIPCTL_SRAML_RETEN_SHIFT 21u
12953 #define SIM_CHIPCTL_SRAML_RETEN_WIDTH 1u
12954 #define SIM_CHIPCTL_SRAML_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAML_RETEN_SHIFT))&SIM_CHIPCTL_SRAML_RETEN_MASK)
12956 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK 0x7u
12957 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT 0u
12958 #define SIM_FTMOPT0_FTM0FLTxSEL_WIDTH 3u
12959 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM0FLTxSEL_MASK)
12960 #define SIM_FTMOPT0_FTM1FLTxSEL_MASK 0x70u
12961 #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT 4u
12962 #define SIM_FTMOPT0_FTM1FLTxSEL_WIDTH 3u
12963 #define SIM_FTMOPT0_FTM1FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM1FLTxSEL_MASK)
12964 #define SIM_FTMOPT0_FTM2FLTxSEL_MASK 0x700u
12965 #define SIM_FTMOPT0_FTM2FLTxSEL_SHIFT 8u
12966 #define SIM_FTMOPT0_FTM2FLTxSEL_WIDTH 3u
12967 #define SIM_FTMOPT0_FTM2FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM2FLTxSEL_MASK)
12968 #define SIM_FTMOPT0_FTM3FLTxSEL_MASK 0x7000u
12969 #define SIM_FTMOPT0_FTM3FLTxSEL_SHIFT 12u
12970 #define SIM_FTMOPT0_FTM3FLTxSEL_WIDTH 3u
12971 #define SIM_FTMOPT0_FTM3FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM3FLTxSEL_MASK)
12972 #define SIM_FTMOPT0_FTM4CLKSEL_MASK 0x30000u
12973 #define SIM_FTMOPT0_FTM4CLKSEL_SHIFT 16u
12974 #define SIM_FTMOPT0_FTM4CLKSEL_WIDTH 2u
12975 #define SIM_FTMOPT0_FTM4CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM4CLKSEL_SHIFT))&SIM_FTMOPT0_FTM4CLKSEL_MASK)
12976 #define SIM_FTMOPT0_FTM5CLKSEL_MASK 0xC0000u
12977 #define SIM_FTMOPT0_FTM5CLKSEL_SHIFT 18u
12978 #define SIM_FTMOPT0_FTM5CLKSEL_WIDTH 2u
12979 #define SIM_FTMOPT0_FTM5CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM5CLKSEL_SHIFT))&SIM_FTMOPT0_FTM5CLKSEL_MASK)
12980 #define SIM_FTMOPT0_FTM6CLKSEL_MASK 0x300000u
12981 #define SIM_FTMOPT0_FTM6CLKSEL_SHIFT 20u
12982 #define SIM_FTMOPT0_FTM6CLKSEL_WIDTH 2u
12983 #define SIM_FTMOPT0_FTM6CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM6CLKSEL_SHIFT))&SIM_FTMOPT0_FTM6CLKSEL_MASK)
12984 #define SIM_FTMOPT0_FTM7CLKSEL_MASK 0xC00000u
12985 #define SIM_FTMOPT0_FTM7CLKSEL_SHIFT 22u
12986 #define SIM_FTMOPT0_FTM7CLKSEL_WIDTH 2u
12987 #define SIM_FTMOPT0_FTM7CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM7CLKSEL_SHIFT))&SIM_FTMOPT0_FTM7CLKSEL_MASK)
12988 #define SIM_FTMOPT0_FTM0CLKSEL_MASK 0x3000000u
12989 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT 24u
12990 #define SIM_FTMOPT0_FTM0CLKSEL_WIDTH 2u
12991 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0CLKSEL_SHIFT))&SIM_FTMOPT0_FTM0CLKSEL_MASK)
12992 #define SIM_FTMOPT0_FTM1CLKSEL_MASK 0xC000000u
12993 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT 26u
12994 #define SIM_FTMOPT0_FTM1CLKSEL_WIDTH 2u
12995 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1CLKSEL_SHIFT))&SIM_FTMOPT0_FTM1CLKSEL_MASK)
12996 #define SIM_FTMOPT0_FTM2CLKSEL_MASK 0x30000000u
12997 #define SIM_FTMOPT0_FTM2CLKSEL_SHIFT 28u
12998 #define SIM_FTMOPT0_FTM2CLKSEL_WIDTH 2u
12999 #define SIM_FTMOPT0_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2CLKSEL_SHIFT))&SIM_FTMOPT0_FTM2CLKSEL_MASK)
13000 #define SIM_FTMOPT0_FTM3CLKSEL_MASK 0xC0000000u
13001 #define SIM_FTMOPT0_FTM3CLKSEL_SHIFT 30u
13002 #define SIM_FTMOPT0_FTM3CLKSEL_WIDTH 2u
13003 #define SIM_FTMOPT0_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3CLKSEL_SHIFT))&SIM_FTMOPT0_FTM3CLKSEL_MASK)
13005 #define SIM_LPOCLKS_LPO1KCLKEN_MASK 0x1u
13006 #define SIM_LPOCLKS_LPO1KCLKEN_SHIFT 0u
13007 #define SIM_LPOCLKS_LPO1KCLKEN_WIDTH 1u
13008 #define SIM_LPOCLKS_LPO1KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO1KCLKEN_SHIFT))&SIM_LPOCLKS_LPO1KCLKEN_MASK)
13009 #define SIM_LPOCLKS_LPO32KCLKEN_MASK 0x2u
13010 #define SIM_LPOCLKS_LPO32KCLKEN_SHIFT 1u
13011 #define SIM_LPOCLKS_LPO32KCLKEN_WIDTH 1u
13012 #define SIM_LPOCLKS_LPO32KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO32KCLKEN_SHIFT))&SIM_LPOCLKS_LPO32KCLKEN_MASK)
13013 #define SIM_LPOCLKS_LPOCLKSEL_MASK 0xCu
13014 #define SIM_LPOCLKS_LPOCLKSEL_SHIFT 2u
13015 #define SIM_LPOCLKS_LPOCLKSEL_WIDTH 2u
13016 #define SIM_LPOCLKS_LPOCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPOCLKSEL_SHIFT))&SIM_LPOCLKS_LPOCLKSEL_MASK)
13017 #define SIM_LPOCLKS_RTCCLKSEL_MASK 0x30u
13018 #define SIM_LPOCLKS_RTCCLKSEL_SHIFT 4u
13019 #define SIM_LPOCLKS_RTCCLKSEL_WIDTH 2u
13020 #define SIM_LPOCLKS_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_RTCCLKSEL_SHIFT))&SIM_LPOCLKS_RTCCLKSEL_MASK)
13022 #define SIM_ADCOPT_ADC0TRGSEL_MASK 0x1u
13023 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT 0u
13024 #define SIM_ADCOPT_ADC0TRGSEL_WIDTH 1u
13025 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0TRGSEL_SHIFT))&SIM_ADCOPT_ADC0TRGSEL_MASK)
13026 #define SIM_ADCOPT_ADC0SWPRETRG_MASK 0xEu
13027 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT 1u
13028 #define SIM_ADCOPT_ADC0SWPRETRG_WIDTH 3u
13029 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0SWPRETRG_SHIFT))&SIM_ADCOPT_ADC0SWPRETRG_MASK)
13030 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK 0x30u
13031 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT 4u
13032 #define SIM_ADCOPT_ADC0PRETRGSEL_WIDTH 2u
13033 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC0PRETRGSEL_MASK)
13034 #define SIM_ADCOPT_ADC1TRGSEL_MASK 0x100u
13035 #define SIM_ADCOPT_ADC1TRGSEL_SHIFT 8u
13036 #define SIM_ADCOPT_ADC1TRGSEL_WIDTH 1u
13037 #define SIM_ADCOPT_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1TRGSEL_SHIFT))&SIM_ADCOPT_ADC1TRGSEL_MASK)
13038 #define SIM_ADCOPT_ADC1SWPRETRG_MASK 0xE00u
13039 #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT 9u
13040 #define SIM_ADCOPT_ADC1SWPRETRG_WIDTH 3u
13041 #define SIM_ADCOPT_ADC1SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1SWPRETRG_SHIFT))&SIM_ADCOPT_ADC1SWPRETRG_MASK)
13042 #define SIM_ADCOPT_ADC1PRETRGSEL_MASK 0x3000u
13043 #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT 12u
13044 #define SIM_ADCOPT_ADC1PRETRGSEL_WIDTH 2u
13045 #define SIM_ADCOPT_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC1PRETRGSEL_MASK)
13047 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK 0x1u
13048 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT 0u
13049 #define SIM_FTMOPT1_FTM0SYNCBIT_WIDTH 1u
13050 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM0SYNCBIT_MASK)
13051 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK 0x2u
13052 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT 1u
13053 #define SIM_FTMOPT1_FTM1SYNCBIT_WIDTH 1u
13054 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM1SYNCBIT_MASK)
13055 #define SIM_FTMOPT1_FTM2SYNCBIT_MASK 0x4u
13056 #define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT 2u
13057 #define SIM_FTMOPT1_FTM2SYNCBIT_WIDTH 1u
13058 #define SIM_FTMOPT1_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM2SYNCBIT_MASK)
13059 #define SIM_FTMOPT1_FTM3SYNCBIT_MASK 0x8u
13060 #define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT 3u
13061 #define SIM_FTMOPT1_FTM3SYNCBIT_WIDTH 1u
13062 #define SIM_FTMOPT1_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM3SYNCBIT_MASK)
13063 #define SIM_FTMOPT1_FTM1CH0SEL_MASK 0x30u
13064 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT 4u
13065 #define SIM_FTMOPT1_FTM1CH0SEL_WIDTH 2u
13066 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1CH0SEL_SHIFT))&SIM_FTMOPT1_FTM1CH0SEL_MASK)
13067 #define SIM_FTMOPT1_FTM2CH0SEL_MASK 0xC0u
13068 #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT 6u
13069 #define SIM_FTMOPT1_FTM2CH0SEL_WIDTH 2u
13070 #define SIM_FTMOPT1_FTM2CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH0SEL_SHIFT))&SIM_FTMOPT1_FTM2CH0SEL_MASK)
13071 #define SIM_FTMOPT1_FTM2CH1SEL_MASK 0x100u
13072 #define SIM_FTMOPT1_FTM2CH1SEL_SHIFT 8u
13073 #define SIM_FTMOPT1_FTM2CH1SEL_WIDTH 1u
13074 #define SIM_FTMOPT1_FTM2CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH1SEL_SHIFT))&SIM_FTMOPT1_FTM2CH1SEL_MASK)
13075 #define SIM_FTMOPT1_FTM4SYNCBIT_MASK 0x800u
13076 #define SIM_FTMOPT1_FTM4SYNCBIT_SHIFT 11u
13077 #define SIM_FTMOPT1_FTM4SYNCBIT_WIDTH 1u
13078 #define SIM_FTMOPT1_FTM4SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM4SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM4SYNCBIT_MASK)
13079 #define SIM_FTMOPT1_FTM5SYNCBIT_MASK 0x1000u
13080 #define SIM_FTMOPT1_FTM5SYNCBIT_SHIFT 12u
13081 #define SIM_FTMOPT1_FTM5SYNCBIT_WIDTH 1u
13082 #define SIM_FTMOPT1_FTM5SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM5SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM5SYNCBIT_MASK)
13083 #define SIM_FTMOPT1_FTM6SYNCBIT_MASK 0x2000u
13084 #define SIM_FTMOPT1_FTM6SYNCBIT_SHIFT 13u
13085 #define SIM_FTMOPT1_FTM6SYNCBIT_WIDTH 1u
13086 #define SIM_FTMOPT1_FTM6SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM6SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM6SYNCBIT_MASK)
13087 #define SIM_FTMOPT1_FTM7SYNCBIT_MASK 0x4000u
13088 #define SIM_FTMOPT1_FTM7SYNCBIT_SHIFT 14u
13089 #define SIM_FTMOPT1_FTM7SYNCBIT_WIDTH 1u
13090 #define SIM_FTMOPT1_FTM7SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM7SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM7SYNCBIT_MASK)
13091 #define SIM_FTMOPT1_FTMGLDOK_MASK 0x8000u
13092 #define SIM_FTMOPT1_FTMGLDOK_SHIFT 15u
13093 #define SIM_FTMOPT1_FTMGLDOK_WIDTH 1u
13094 #define SIM_FTMOPT1_FTMGLDOK(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTMGLDOK_SHIFT))&SIM_FTMOPT1_FTMGLDOK_MASK)
13095 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK 0xFF0000u
13096 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT 16u
13097 #define SIM_FTMOPT1_FTM0_OUTSEL_WIDTH 8u
13098 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM0_OUTSEL_MASK)
13099 #define SIM_FTMOPT1_FTM3_OUTSEL_MASK 0xFF000000u
13100 #define SIM_FTMOPT1_FTM3_OUTSEL_SHIFT 24u
13101 #define SIM_FTMOPT1_FTM3_OUTSEL_WIDTH 8u
13102 #define SIM_FTMOPT1_FTM3_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM3_OUTSEL_MASK)
13104 #define SIM_MISCTRL0_FTM_GTB_SPLIT_EN_MASK 0x4000u
13105 #define SIM_MISCTRL0_FTM_GTB_SPLIT_EN_SHIFT 14u
13106 #define SIM_MISCTRL0_FTM_GTB_SPLIT_EN_WIDTH 1u
13107 #define SIM_MISCTRL0_FTM_GTB_SPLIT_EN(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM_GTB_SPLIT_EN_SHIFT))&SIM_MISCTRL0_FTM_GTB_SPLIT_EN_MASK)
13108 #define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK 0x10000u
13109 #define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT 16u
13110 #define SIM_MISCTRL0_FTM0_OBE_CTRL_WIDTH 1u
13111 #define SIM_MISCTRL0_FTM0_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM0_OBE_CTRL_MASK)
13112 #define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK 0x20000u
13113 #define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT 17u
13114 #define SIM_MISCTRL0_FTM1_OBE_CTRL_WIDTH 1u
13115 #define SIM_MISCTRL0_FTM1_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM1_OBE_CTRL_MASK)
13116 #define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK 0x40000u
13117 #define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT 18u
13118 #define SIM_MISCTRL0_FTM2_OBE_CTRL_WIDTH 1u
13119 #define SIM_MISCTRL0_FTM2_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM2_OBE_CTRL_MASK)
13120 #define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK 0x80000u
13121 #define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT 19u
13122 #define SIM_MISCTRL0_FTM3_OBE_CTRL_WIDTH 1u
13123 #define SIM_MISCTRL0_FTM3_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM3_OBE_CTRL_MASK)
13124 #define SIM_MISCTRL0_FTM4_OBE_CTRL_MASK 0x100000u
13125 #define SIM_MISCTRL0_FTM4_OBE_CTRL_SHIFT 20u
13126 #define SIM_MISCTRL0_FTM4_OBE_CTRL_WIDTH 1u
13127 #define SIM_MISCTRL0_FTM4_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM4_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM4_OBE_CTRL_MASK)
13128 #define SIM_MISCTRL0_FTM5_OBE_CTRL_MASK 0x200000u
13129 #define SIM_MISCTRL0_FTM5_OBE_CTRL_SHIFT 21u
13130 #define SIM_MISCTRL0_FTM5_OBE_CTRL_WIDTH 1u
13131 #define SIM_MISCTRL0_FTM5_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM5_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM5_OBE_CTRL_MASK)
13132 #define SIM_MISCTRL0_FTM6_OBE_CTRL_MASK 0x400000u
13133 #define SIM_MISCTRL0_FTM6_OBE_CTRL_SHIFT 22u
13134 #define SIM_MISCTRL0_FTM6_OBE_CTRL_WIDTH 1u
13135 #define SIM_MISCTRL0_FTM6_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM6_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM6_OBE_CTRL_MASK)
13136 #define SIM_MISCTRL0_FTM7_OBE_CTRL_MASK 0x800000u
13137 #define SIM_MISCTRL0_FTM7_OBE_CTRL_SHIFT 23u
13138 #define SIM_MISCTRL0_FTM7_OBE_CTRL_WIDTH 1u
13139 #define SIM_MISCTRL0_FTM7_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM7_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM7_OBE_CTRL_MASK)
13140 #define SIM_MISCTRL0_RMII_CLK_OBE_MASK 0x1000000u
13141 #define SIM_MISCTRL0_RMII_CLK_OBE_SHIFT 24u
13142 #define SIM_MISCTRL0_RMII_CLK_OBE_WIDTH 1u
13143 #define SIM_MISCTRL0_RMII_CLK_OBE(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_RMII_CLK_OBE_SHIFT))&SIM_MISCTRL0_RMII_CLK_OBE_MASK)
13144 #define SIM_MISCTRL0_RMII_CLK_SEL_MASK 0x2000000u
13145 #define SIM_MISCTRL0_RMII_CLK_SEL_SHIFT 25u
13146 #define SIM_MISCTRL0_RMII_CLK_SEL_WIDTH 1u
13147 #define SIM_MISCTRL0_RMII_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_RMII_CLK_SEL_SHIFT))&SIM_MISCTRL0_RMII_CLK_SEL_MASK)
13148 #define SIM_MISCTRL0_QSPI_CLK_SEL_MASK 0x4000000u
13149 #define SIM_MISCTRL0_QSPI_CLK_SEL_SHIFT 26u
13150 #define SIM_MISCTRL0_QSPI_CLK_SEL_WIDTH 1u
13151 #define SIM_MISCTRL0_QSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_QSPI_CLK_SEL_SHIFT))&SIM_MISCTRL0_QSPI_CLK_SEL_MASK)
13153 #define SIM_SDID_FEATURES_MASK 0xFFu
13154 #define SIM_SDID_FEATURES_SHIFT 0u
13155 #define SIM_SDID_FEATURES_WIDTH 8u
13156 #define SIM_SDID_FEATURES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FEATURES_SHIFT))&SIM_SDID_FEATURES_MASK)
13157 #define SIM_SDID_PACKAGE_MASK 0xF00u
13158 #define SIM_SDID_PACKAGE_SHIFT 8u
13159 #define SIM_SDID_PACKAGE_WIDTH 4u
13160 #define SIM_SDID_PACKAGE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PACKAGE_SHIFT))&SIM_SDID_PACKAGE_MASK)
13161 #define SIM_SDID_REVID_MASK 0xF000u
13162 #define SIM_SDID_REVID_SHIFT 12u
13163 #define SIM_SDID_REVID_WIDTH 4u
13164 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
13165 #define SIM_SDID_RAMSIZE_MASK 0xF0000u
13166 #define SIM_SDID_RAMSIZE_SHIFT 16u
13167 #define SIM_SDID_RAMSIZE_WIDTH 4u
13168 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_RAMSIZE_SHIFT))&SIM_SDID_RAMSIZE_MASK)
13169 #define SIM_SDID_DERIVATE_MASK 0xF00000u
13170 #define SIM_SDID_DERIVATE_SHIFT 20u
13171 #define SIM_SDID_DERIVATE_WIDTH 4u
13172 #define SIM_SDID_DERIVATE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DERIVATE_SHIFT))&SIM_SDID_DERIVATE_MASK)
13173 #define SIM_SDID_SUBSERIES_MASK 0xF000000u
13174 #define SIM_SDID_SUBSERIES_SHIFT 24u
13175 #define SIM_SDID_SUBSERIES_WIDTH 4u
13176 #define SIM_SDID_SUBSERIES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBSERIES_SHIFT))&SIM_SDID_SUBSERIES_MASK)
13177 #define SIM_SDID_GENERATION_MASK 0xF0000000u
13178 #define SIM_SDID_GENERATION_SHIFT 28u
13179 #define SIM_SDID_GENERATION_WIDTH 4u
13180 #define SIM_SDID_GENERATION(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_GENERATION_SHIFT))&SIM_SDID_GENERATION_MASK)
13182 #define SIM_PLATCGC_CGCMSCM_MASK 0x1u
13183 #define SIM_PLATCGC_CGCMSCM_SHIFT 0u
13184 #define SIM_PLATCGC_CGCMSCM_WIDTH 1u
13185 #define SIM_PLATCGC_CGCMSCM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMSCM_SHIFT))&SIM_PLATCGC_CGCMSCM_MASK)
13186 #define SIM_PLATCGC_CGCMPU_MASK 0x2u
13187 #define SIM_PLATCGC_CGCMPU_SHIFT 1u
13188 #define SIM_PLATCGC_CGCMPU_WIDTH 1u
13189 #define SIM_PLATCGC_CGCMPU(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMPU_SHIFT))&SIM_PLATCGC_CGCMPU_MASK)
13190 #define SIM_PLATCGC_CGCDMA_MASK 0x4u
13191 #define SIM_PLATCGC_CGCDMA_SHIFT 2u
13192 #define SIM_PLATCGC_CGCDMA_WIDTH 1u
13193 #define SIM_PLATCGC_CGCDMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCDMA_SHIFT))&SIM_PLATCGC_CGCDMA_MASK)
13194 #define SIM_PLATCGC_CGCERM_MASK 0x8u
13195 #define SIM_PLATCGC_CGCERM_SHIFT 3u
13196 #define SIM_PLATCGC_CGCERM_WIDTH 1u
13197 #define SIM_PLATCGC_CGCERM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCERM_SHIFT))&SIM_PLATCGC_CGCERM_MASK)
13198 #define SIM_PLATCGC_CGCEIM_MASK 0x10u
13199 #define SIM_PLATCGC_CGCEIM_SHIFT 4u
13200 #define SIM_PLATCGC_CGCEIM_WIDTH 1u
13201 #define SIM_PLATCGC_CGCEIM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCEIM_SHIFT))&SIM_PLATCGC_CGCEIM_MASK)
13203 #define SIM_FCFG1_DEPART_MASK 0xF000u
13204 #define SIM_FCFG1_DEPART_SHIFT 12u
13205 #define SIM_FCFG1_DEPART_WIDTH 4u
13206 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
13207 #define SIM_FCFG1_EEERAMSIZE_MASK 0xF0000u
13208 #define SIM_FCFG1_EEERAMSIZE_SHIFT 16u
13209 #define SIM_FCFG1_EEERAMSIZE_WIDTH 4u
13210 #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EEERAMSIZE_SHIFT))&SIM_FCFG1_EEERAMSIZE_MASK)
13212 #define SIM_UIDH_UID127_96_MASK 0xFFFFFFFFu
13213 #define SIM_UIDH_UID127_96_SHIFT 0u
13214 #define SIM_UIDH_UID127_96_WIDTH 32u
13215 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID127_96_SHIFT))&SIM_UIDH_UID127_96_MASK)
13217 #define SIM_UIDMH_UID95_64_MASK 0xFFFFFFFFu
13218 #define SIM_UIDMH_UID95_64_SHIFT 0u
13219 #define SIM_UIDMH_UID95_64_WIDTH 32u
13220 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID95_64_SHIFT))&SIM_UIDMH_UID95_64_MASK)
13222 #define SIM_UIDML_UID63_32_MASK 0xFFFFFFFFu
13223 #define SIM_UIDML_UID63_32_SHIFT 0u
13224 #define SIM_UIDML_UID63_32_WIDTH 32u
13225 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID63_32_SHIFT))&SIM_UIDML_UID63_32_MASK)
13227 #define SIM_UIDL_UID31_0_MASK 0xFFFFFFFFu
13228 #define SIM_UIDL_UID31_0_SHIFT 0u
13229 #define SIM_UIDL_UID31_0_WIDTH 32u
13230 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID31_0_SHIFT))&SIM_UIDL_UID31_0_MASK)
13232 #define SIM_CLKDIV4_TRACEFRAC_MASK 0x1u
13233 #define SIM_CLKDIV4_TRACEFRAC_SHIFT 0u
13234 #define SIM_CLKDIV4_TRACEFRAC_WIDTH 1u
13235 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEFRAC_SHIFT))&SIM_CLKDIV4_TRACEFRAC_MASK)
13236 #define SIM_CLKDIV4_TRACEDIV_MASK 0xEu
13237 #define SIM_CLKDIV4_TRACEDIV_SHIFT 1u
13238 #define SIM_CLKDIV4_TRACEDIV_WIDTH 3u
13239 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIV_SHIFT))&SIM_CLKDIV4_TRACEDIV_MASK)
13240 #define SIM_CLKDIV4_TRACEDIVEN_MASK 0x10000000u
13241 #define SIM_CLKDIV4_TRACEDIVEN_SHIFT 28u
13242 #define SIM_CLKDIV4_TRACEDIVEN_WIDTH 1u
13243 #define SIM_CLKDIV4_TRACEDIVEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIVEN_SHIFT))&SIM_CLKDIV4_TRACEDIVEN_MASK)
13245 #define SIM_MISCTRL1_SW_TRG_MASK 0x1u
13246 #define SIM_MISCTRL1_SW_TRG_SHIFT 0u
13247 #define SIM_MISCTRL1_SW_TRG_WIDTH 1u
13248 #define SIM_MISCTRL1_SW_TRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL1_SW_TRG_SHIFT))&SIM_MISCTRL1_SW_TRG_MASK)
13283 #define SMC_INSTANCE_COUNT (1u)
13288 #define SMC_BASE (0x4007E000u)
13290 #define SMC ((SMC_Type *)SMC_BASE)
13292 #define SMC_BASE_ADDRS { SMC_BASE }
13294 #define SMC_BASE_PTRS { SMC }
13306 #define SMC_VERID_FEATURE_MASK 0xFFFFu
13307 #define SMC_VERID_FEATURE_SHIFT 0u
13308 #define SMC_VERID_FEATURE_WIDTH 16u
13309 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_FEATURE_SHIFT))&SMC_VERID_FEATURE_MASK)
13310 #define SMC_VERID_MINOR_MASK 0xFF0000u
13311 #define SMC_VERID_MINOR_SHIFT 16u
13312 #define SMC_VERID_MINOR_WIDTH 8u
13313 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MINOR_SHIFT))&SMC_VERID_MINOR_MASK)
13314 #define SMC_VERID_MAJOR_MASK 0xFF000000u
13315 #define SMC_VERID_MAJOR_SHIFT 24u
13316 #define SMC_VERID_MAJOR_WIDTH 8u
13317 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MAJOR_SHIFT))&SMC_VERID_MAJOR_MASK)
13319 #define SMC_PARAM_EHSRUN_MASK 0x1u
13320 #define SMC_PARAM_EHSRUN_SHIFT 0u
13321 #define SMC_PARAM_EHSRUN_WIDTH 1u
13322 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EHSRUN_SHIFT))&SMC_PARAM_EHSRUN_MASK)
13323 #define SMC_PARAM_ELLS_MASK 0x8u
13324 #define SMC_PARAM_ELLS_SHIFT 3u
13325 #define SMC_PARAM_ELLS_WIDTH 1u
13326 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS_SHIFT))&SMC_PARAM_ELLS_MASK)
13327 #define SMC_PARAM_ELLS2_MASK 0x20u
13328 #define SMC_PARAM_ELLS2_SHIFT 5u
13329 #define SMC_PARAM_ELLS2_WIDTH 1u
13330 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS2_SHIFT))&SMC_PARAM_ELLS2_MASK)
13331 #define SMC_PARAM_EVLLS0_MASK 0x40u
13332 #define SMC_PARAM_EVLLS0_SHIFT 6u
13333 #define SMC_PARAM_EVLLS0_WIDTH 1u
13334 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EVLLS0_SHIFT))&SMC_PARAM_EVLLS0_MASK)
13336 #define SMC_PMPROT_AVLP_MASK 0x20u
13337 #define SMC_PMPROT_AVLP_SHIFT 5u
13338 #define SMC_PMPROT_AVLP_WIDTH 1u
13339 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
13340 #define SMC_PMPROT_AHSRUN_MASK 0x80u
13341 #define SMC_PMPROT_AHSRUN_SHIFT 7u
13342 #define SMC_PMPROT_AHSRUN_WIDTH 1u
13343 #define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
13345 #define SMC_PMCTRL_STOPM_MASK 0x7u
13346 #define SMC_PMCTRL_STOPM_SHIFT 0u
13347 #define SMC_PMCTRL_STOPM_WIDTH 3u
13348 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
13349 #define SMC_PMCTRL_VLPSA_MASK 0x8u
13350 #define SMC_PMCTRL_VLPSA_SHIFT 3u
13351 #define SMC_PMCTRL_VLPSA_WIDTH 1u
13352 #define SMC_PMCTRL_VLPSA(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_VLPSA_SHIFT))&SMC_PMCTRL_VLPSA_MASK)
13353 #define SMC_PMCTRL_RUNM_MASK 0x60u
13354 #define SMC_PMCTRL_RUNM_SHIFT 5u
13355 #define SMC_PMCTRL_RUNM_WIDTH 2u
13356 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
13358 #define SMC_STOPCTRL_STOPO_MASK 0xC0u
13359 #define SMC_STOPCTRL_STOPO_SHIFT 6u
13360 #define SMC_STOPCTRL_STOPO_WIDTH 2u
13361 #define SMC_STOPCTRL_STOPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_STOPO_SHIFT))&SMC_STOPCTRL_STOPO_MASK)
13363 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
13364 #define SMC_PMSTAT_PMSTAT_SHIFT 0u
13365 #define SMC_PMSTAT_PMSTAT_WIDTH 8u
13366 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
13389 #define TRGMUX_TRGMUXn_COUNT 32u
13397 #define TRGMUX_INSTANCE_COUNT (1u)
13402 #define TRGMUX_BASE (0x40063000u)
13404 #define TRGMUX ((TRGMUX_Type *)TRGMUX_BASE)
13406 #define TRGMUX_BASE_ADDRS { TRGMUX_BASE }
13408 #define TRGMUX_BASE_PTRS { TRGMUX }
13411 #define TRGMUX_DMAMUX0_INDEX 0
13412 #define TRGMUX_EXTOUT0_INDEX 1
13413 #define TRGMUX_EXTOUT1_INDEX 2
13414 #define TRGMUX_ADC0_INDEX 3
13415 #define TRGMUX_ADC1_INDEX 4
13416 #define TRGMUX_CMP0_INDEX 7
13417 #define TRGMUX_FTM0_INDEX 10
13418 #define TRGMUX_FTM1_INDEX 11
13419 #define TRGMUX_FTM2_INDEX 12
13420 #define TRGMUX_FTM3_INDEX 13
13421 #define TRGMUX_PDB0_INDEX 14
13422 #define TRGMUX_PDB1_INDEX 15
13423 #define TRGMUX_FLEXIO_INDEX 17
13424 #define TRGMUX_LPIT0_INDEX 18
13425 #define TRGMUX_LPUART0_INDEX 19
13426 #define TRGMUX_LPUART1_INDEX 20
13427 #define TRGMUX_LPI2C0_INDEX 21
13428 #define TRGMUX_LPSPI0_INDEX 23
13429 #define TRGMUX_LPSPI1_INDEX 24
13430 #define TRGMUX_LPTMR0_INDEX 25
13431 #define TRGMUX_LPI2C1_INDEX 27
13432 #define TRGMUX_FTM4_INDEX 28
13433 #define TRGMUX_FTM5_INDEX 29
13434 #define TRGMUX_FTM6_INDEX 30
13435 #define TRGMUX_FTM7_INDEX 31
13447 #define TRGMUX_TRGMUXn_SEL0_MASK 0x7Fu
13448 #define TRGMUX_TRGMUXn_SEL0_SHIFT 0u
13449 #define TRGMUX_TRGMUXn_SEL0_WIDTH 7u
13450 #define TRGMUX_TRGMUXn_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL0_SHIFT))&TRGMUX_TRGMUXn_SEL0_MASK)
13451 #define TRGMUX_TRGMUXn_SEL1_MASK 0x7F00u
13452 #define TRGMUX_TRGMUXn_SEL1_SHIFT 8u
13453 #define TRGMUX_TRGMUXn_SEL1_WIDTH 7u
13454 #define TRGMUX_TRGMUXn_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL1_SHIFT))&TRGMUX_TRGMUXn_SEL1_MASK)
13455 #define TRGMUX_TRGMUXn_SEL2_MASK 0x7F0000u
13456 #define TRGMUX_TRGMUXn_SEL2_SHIFT 16u
13457 #define TRGMUX_TRGMUXn_SEL2_WIDTH 7u
13458 #define TRGMUX_TRGMUXn_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL2_SHIFT))&TRGMUX_TRGMUXn_SEL2_MASK)
13459 #define TRGMUX_TRGMUXn_SEL3_MASK 0x7F000000u
13460 #define TRGMUX_TRGMUXn_SEL3_SHIFT 24u
13461 #define TRGMUX_TRGMUXn_SEL3_WIDTH 7u
13462 #define TRGMUX_TRGMUXn_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL3_SHIFT))&TRGMUX_TRGMUXn_SEL3_MASK)
13463 #define TRGMUX_TRGMUXn_LK_MASK 0x80000000u
13464 #define TRGMUX_TRGMUXn_LK_SHIFT 31u
13465 #define TRGMUX_TRGMUXn_LK_WIDTH 1u
13466 #define TRGMUX_TRGMUXn_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_LK_SHIFT))&TRGMUX_TRGMUXn_LK_MASK)
13499 #define WDOG_INSTANCE_COUNT (1u)
13504 #define WDOG_BASE (0x40052000u)
13506 #define WDOG ((WDOG_Type *)WDOG_BASE)
13508 #define WDOG_BASE_ADDRS { WDOG_BASE }
13510 #define WDOG_BASE_PTRS { WDOG }
13512 #define WDOG_IRQS_ARR_COUNT (1u)
13514 #define WDOG_IRQS_CH_COUNT (1u)
13516 #define WDOG_IRQS { WDOG_EWM_IRQn }
13528 #define WDOG_CS_STOP_MASK 0x1u
13529 #define WDOG_CS_STOP_SHIFT 0u
13530 #define WDOG_CS_STOP_WIDTH 1u
13531 #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_STOP_SHIFT))&WDOG_CS_STOP_MASK)
13532 #define WDOG_CS_WAIT_MASK 0x2u
13533 #define WDOG_CS_WAIT_SHIFT 1u
13534 #define WDOG_CS_WAIT_WIDTH 1u
13535 #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WAIT_SHIFT))&WDOG_CS_WAIT_MASK)
13536 #define WDOG_CS_DBG_MASK 0x4u
13537 #define WDOG_CS_DBG_SHIFT 2u
13538 #define WDOG_CS_DBG_WIDTH 1u
13539 #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DBG_SHIFT))&WDOG_CS_DBG_MASK)
13540 #define WDOG_CS_TST_MASK 0x18u
13541 #define WDOG_CS_TST_SHIFT 3u
13542 #define WDOG_CS_TST_WIDTH 2u
13543 #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_TST_SHIFT))&WDOG_CS_TST_MASK)
13544 #define WDOG_CS_UPDATE_MASK 0x20u
13545 #define WDOG_CS_UPDATE_SHIFT 5u
13546 #define WDOG_CS_UPDATE_WIDTH 1u
13547 #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_UPDATE_SHIFT))&WDOG_CS_UPDATE_MASK)
13548 #define WDOG_CS_INT_MASK 0x40u
13549 #define WDOG_CS_INT_SHIFT 6u
13550 #define WDOG_CS_INT_WIDTH 1u
13551 #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_INT_SHIFT))&WDOG_CS_INT_MASK)
13552 #define WDOG_CS_EN_MASK 0x80u
13553 #define WDOG_CS_EN_SHIFT 7u
13554 #define WDOG_CS_EN_WIDTH 1u
13555 #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_EN_SHIFT))&WDOG_CS_EN_MASK)
13556 #define WDOG_CS_CLK_MASK 0x300u
13557 #define WDOG_CS_CLK_SHIFT 8u
13558 #define WDOG_CS_CLK_WIDTH 2u
13559 #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CLK_SHIFT))&WDOG_CS_CLK_MASK)
13560 #define WDOG_CS_RCS_MASK 0x400u
13561 #define WDOG_CS_RCS_SHIFT 10u
13562 #define WDOG_CS_RCS_WIDTH 1u
13563 #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_RCS_SHIFT))&WDOG_CS_RCS_MASK)
13564 #define WDOG_CS_ULK_MASK 0x800u
13565 #define WDOG_CS_ULK_SHIFT 11u
13566 #define WDOG_CS_ULK_WIDTH 1u
13567 #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_ULK_SHIFT))&WDOG_CS_ULK_MASK)
13568 #define WDOG_CS_PRES_MASK 0x1000u
13569 #define WDOG_CS_PRES_SHIFT 12u
13570 #define WDOG_CS_PRES_WIDTH 1u
13571 #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_PRES_SHIFT))&WDOG_CS_PRES_MASK)
13572 #define WDOG_CS_CMD32EN_MASK 0x2000u
13573 #define WDOG_CS_CMD32EN_SHIFT 13u
13574 #define WDOG_CS_CMD32EN_WIDTH 1u
13575 #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CMD32EN_SHIFT))&WDOG_CS_CMD32EN_MASK)
13576 #define WDOG_CS_FLG_MASK 0x4000u
13577 #define WDOG_CS_FLG_SHIFT 14u
13578 #define WDOG_CS_FLG_WIDTH 1u
13579 #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_FLG_SHIFT))&WDOG_CS_FLG_MASK)
13580 #define WDOG_CS_WIN_MASK 0x8000u
13581 #define WDOG_CS_WIN_SHIFT 15u
13582 #define WDOG_CS_WIN_WIDTH 1u
13583 #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WIN_SHIFT))&WDOG_CS_WIN_MASK)
13585 #define WDOG_CNT_CNTLOW_MASK 0xFFu
13586 #define WDOG_CNT_CNTLOW_SHIFT 0u
13587 #define WDOG_CNT_CNTLOW_WIDTH 8u
13588 #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTLOW_SHIFT))&WDOG_CNT_CNTLOW_MASK)
13589 #define WDOG_CNT_CNTHIGH_MASK 0xFF00u
13590 #define WDOG_CNT_CNTHIGH_SHIFT 8u
13591 #define WDOG_CNT_CNTHIGH_WIDTH 8u
13592 #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTHIGH_SHIFT))&WDOG_CNT_CNTHIGH_MASK)
13594 #define WDOG_TOVAL_TOVALLOW_MASK 0xFFu
13595 #define WDOG_TOVAL_TOVALLOW_SHIFT 0u
13596 #define WDOG_TOVAL_TOVALLOW_WIDTH 8u
13597 #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALLOW_SHIFT))&WDOG_TOVAL_TOVALLOW_MASK)
13598 #define WDOG_TOVAL_TOVALHIGH_MASK 0xFF00u
13599 #define WDOG_TOVAL_TOVALHIGH_SHIFT 8u
13600 #define WDOG_TOVAL_TOVALHIGH_WIDTH 8u
13601 #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALHIGH_SHIFT))&WDOG_TOVAL_TOVALHIGH_MASK)
13603 #define WDOG_WIN_WINLOW_MASK 0xFFu
13604 #define WDOG_WIN_WINLOW_SHIFT 0u
13605 #define WDOG_WIN_WINLOW_WIDTH 8u
13606 #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINLOW_SHIFT))&WDOG_WIN_WINLOW_MASK)
13607 #define WDOG_WIN_WINHIGH_MASK 0xFF00u
13608 #define WDOG_WIN_WINHIGH_SHIFT 8u
13609 #define WDOG_WIN_WINHIGH_WIDTH 8u
13610 #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINHIGH_SHIFT))&WDOG_WIN_WINHIGH_MASK)
13645 #if (MCU_MEM_MAP_VERSION != 0x0200u)
13646 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
13647 #warning There are included two not compatible versions of memory maps. Please check possible differences.
#define FTM_CV_MIRROR_COUNT
__I uint32_t RMON_T_MC_PKT
__I uint32_t RMON_R_P512TO1023
struct RTC_Type * RTC_MemMapPtr
struct PORT_Type * PORT_MemMapPtr
struct DMAMUX_Type * DMAMUX_MemMapPtr
#define FTM_CONTROLS_COUNT
__I uint32_t RMON_T_PACKETS
__I uint32_t IEEE_T_CSERR
__I uint32_t RMON_R_OCTETS
#define FLEXIO_TIMCFG_COUNT
struct LPUART_Type * LPUART_MemMapPtr
#define QuadSPI_LUT_COUNT
__I uint32_t RMON_R_P128TO255
__I uint32_t IEEE_T_FDXFC
__IO uint32_t PL2_PLMASK_LO
#define S32_NVIC_ICER_COUNT
#define FLEXIO_SHIFTCFG_COUNT
__I uint32_t RMON_R_P256TO511
__I uint32_t RMON_R_MC_PKT
struct TRGMUX_Type * TRGMUX_MemMapPtr
__I uint32_t RMON_T_UNDERSIZE
#define S32_NVIC_ISER_COUNT
struct CAN_Type * CAN_MemMapPtr
struct DMA_Type * DMA_MemMapPtr
struct SAI_Type * SAI_MemMapPtr
__IO uint32_t FLT_ID2_IDMASK
__I uint32_t RMON_R_UNDERSIZE
__I uint32_t RMON_R_P65TO127
struct LPTMR_Type * LPTMR_MemMapPtr
struct ADC_Type * ADC_MemMapPtr
__I uint32_t IEEE_R_FRAME_OK
struct LMEM_Type * LMEM_MemMapPtr
struct FTM_Type * FTM_MemMapPtr
__I uint32_t RMON_R_PACKETS
struct LPSPI_Type * LPSPI_MemMapPtr
__I uint32_t RMON_R_P_GTE2048
#define FLEXIO_SHIFTBUFBYS_COUNT
struct SIM_Type * SIM_MemMapPtr
__I uint32_t RMON_T_P65TO127
#define FLEXIO_SHIFTBUFBIS_COUNT
struct EIM_Type * EIM_MemMapPtr
struct PMC_Type * PMC_MemMapPtr
IRQn_Type
Defines the Interrupt Numbers definitions.
#define S32_NVIC_IP_COUNT
struct WDOG_Type * WDOG_MemMapPtr
__I uint32_t RMON_R_CRC_ALIGN
struct MPU_Type * MPU_MemMapPtr
__I uint32_t RMON_R_RESVD_0
__IO uint32_t PAIR1DEADTIME
struct QuadSPI_Type * QuadSPI_MemMapPtr
__I uint32_t RMON_T_P128TO255
struct MSCM_Type * MSCM_MemMapPtr
#define S32_NVIC_ISPR_COUNT
struct PDB_Type * PDB_MemMapPtr
#define TRGMUX_TRGMUXn_COUNT
__I uint32_t RMON_R_BC_PKT
struct ENET_Type * ENET_MemMapPtr
__I uint32_t RMON_T_P512TO1023
struct CRC_Type * CRC_MemMapPtr
__I uint32_t RMON_T_CRC_ALIGN
struct GPIO_Type * GPIO_MemMapPtr
struct S32_NVIC_Type * S32_NVIC_MemMapPtr
struct SCG_Type * SCG_MemMapPtr
__IO uint8_t CLKPRESCALER
struct ERM_Type * ERM_MemMapPtr
struct CMP_Type * CMP_MemMapPtr
__I uint32_t IEEE_T_FRAME_OK
__I uint32_t RMON_T_OCTETS
#define S32_NVIC_ICPR_COUNT
#define DMAMUX_CHCFG_COUNT
#define FLEXIO_SHIFTBUF_COUNT
__IO uint32_t PAIR3DEADTIME
struct LPIT_Type * LPIT_MemMapPtr
__I uint32_t RMON_T_P256TO511
__I uint32_t RMON_R_OVERSIZE
__I uint32_t IEEE_R_ALIGN
struct MCM_Type * MCM_MemMapPtr
__I uint32_t RMON_T_OVERSIZE
__I uint32_t IEEE_T_OCTETS_OK
#define FLEXIO_SHIFTBUFBBS_COUNT
__I uint32_t IEEE_R_FDXFC
struct EWM_Type * EWM_MemMapPtr
#define FLEXIO_TIMCTL_COUNT
struct SMC_Type * SMC_MemMapPtr
#define FLEXIO_SHIFTCTL_COUNT
struct LPI2C_Type * LPI2C_MemMapPtr
__I uint32_t RMON_R_P1024TO2047
#define MPU_EAR_EDR_COUNT
struct AIPS_Type * AIPS_MemMapPtr
struct RCM_Type * RCM_MemMapPtr
__I uint32_t RMON_T_BC_PKT
struct S32_SCB_Type * S32_SCB_MemMapPtr
struct FLEXIO_Type * FLEXIO_MemMapPtr
__I uint32_t IEEE_T_EXCOL
struct CSE_PRAM_Type * CSE_PRAM_MemMapPtr
__I uint32_t RMON_T_P_GTE2048
__I uint32_t IEEE_T_MACERR
__I uint32_t IEEE_R_OCTETS_OK
#define S32_NVIC_IABR_COUNT
#define QuadSPI_RBDR_COUNT
struct FTFC_Type * FTFC_MemMapPtr
__IO uint32_t PAIR0DEADTIME
__I uint32_t RMON_T_P1024TO2047
#define ENET_CHANNEL_COUNT
struct S32_SysTick_Type * S32_SysTick_MemMapPtr
struct PCC_Type * PCC_MemMapPtr
#define CSE_PRAM_RAMn_COUNT
__IO uint32_t PL2_PLMASK_HI
#define FLEXIO_TIMCMP_COUNT
__I uint32_t IEEE_R_MACERR
__IO uint32_t PAIR2DEADTIME