S32 SDK
edma_irq.c
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
45 #include "edma_irq.h"
46 
47 /*******************************************************************************
48  * Variables
49  ******************************************************************************/
50 
51 /*******************************************************************************
52  * Code
53  ******************************************************************************/
54 
55 #ifdef FEATURE_EDMA_ORED_IRQ_LINES_16_CHN
56 
57 void DMA0_15_IRQHandler(void)
58 {
59  /* Read the status flags register */
60  uint32_t mask = 0xFFFF;
61  uint32_t flags = DMA->INT;
62  uint8_t i = 0U;
63  flags &= mask;
64  /* Check all the flags from 0 to 15 and call the handler for the appropriate channel */
65  while (flags > 0U)
66  {
67  if ((flags & 1U) > 0U)
68  {
70  }
71  i++;
72  flags >>= 1U;
73  }
74 }
75 
77 void DMA16_31_IRQHandler(void)
78 {
79  /* Read the status flags register */
80  uint32_t flags = DMA->INT;
81  uint8_t i = 16U;
82  flags >>= 16U;
83  /* Check all the flags from 16 to 31 and call the handler for the appropriate channel */
84  while (flags > 0U)
85  {
86  if ((flags & 1U) > 0U)
87  {
89  }
90  i++;
91  flags >>= 1U;
92  }
93 }
94 #endif
95 
96 #ifdef FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
97 
98 void DMA0_IRQHandler(void)
99 {
101 }
102 
104 void DMA1_IRQHandler(void)
105 {
107 }
108 
110 void DMA2_IRQHandler(void)
111 {
113 }
114 
116 void DMA3_IRQHandler(void)
117 {
119 }
120 
122 void DMA4_IRQHandler(void)
123 {
125 }
126 
128 void DMA5_IRQHandler(void)
129 {
131 }
132 
134 void DMA6_IRQHandler(void)
135 {
137 }
138 
140 void DMA7_IRQHandler(void)
141 {
143 }
144 
146 void DMA8_IRQHandler(void)
147 {
149 }
150 
152 void DMA9_IRQHandler(void)
153 {
155 }
156 
158 void DMA10_IRQHandler(void)
159 {
160  EDMA_DRV_IRQHandler(10U);
161 }
162 
164 void DMA11_IRQHandler(void)
165 {
166  EDMA_DRV_IRQHandler(11U);
167 }
168 
170 void DMA12_IRQHandler(void)
171 {
172  EDMA_DRV_IRQHandler(12U);
173 }
174 
176 void DMA13_IRQHandler(void)
177 {
178  EDMA_DRV_IRQHandler(13U);
179 }
180 
182 void DMA14_IRQHandler(void)
183 {
184  EDMA_DRV_IRQHandler(14U);
185 }
186 
188 void DMA15_IRQHandler(void)
189 {
190  EDMA_DRV_IRQHandler(15U);
191 }
192 #if (FEATURE_EDMA_MODULE_CHANNELS > 16U)
193 void DMA16_IRQHandler(void)
194 {
195  EDMA_DRV_IRQHandler(16U);
196 }
197 
199 void DMA17_IRQHandler(void)
200 {
201  EDMA_DRV_IRQHandler(17U);
202 }
203 
205 void DMA18_IRQHandler(void)
206 {
207  EDMA_DRV_IRQHandler(18U);
208 }
209 
211 void DMA19_IRQHandler(void)
212 {
213  EDMA_DRV_IRQHandler(19U);
214 }
215 
217 void DMA20_IRQHandler(void)
218 {
219  EDMA_DRV_IRQHandler(20U);
220 }
221 
223 void DMA21_IRQHandler(void)
224 {
225  EDMA_DRV_IRQHandler(21U);
226 }
227 
229 void DMA22_IRQHandler(void)
230 {
231  EDMA_DRV_IRQHandler(22U);
232 }
233 
235 void DMA23_IRQHandler(void)
236 {
237  EDMA_DRV_IRQHandler(23U);
238 }
239 
241 void DMA24_IRQHandler(void)
242 {
243  EDMA_DRV_IRQHandler(24U);
244 }
245 
247 void DMA25_IRQHandler(void)
248 {
249  EDMA_DRV_IRQHandler(25U);
250 }
251 
253 void DMA26_IRQHandler(void)
254 {
255  EDMA_DRV_IRQHandler(26U);
256 }
257 
259 void DMA27_IRQHandler(void)
260 {
261  EDMA_DRV_IRQHandler(27U);
262 }
263 
265 void DMA28_IRQHandler(void)
266 {
267  EDMA_DRV_IRQHandler(28U);
268 }
269 
271 void DMA29_IRQHandler(void)
272 {
273  EDMA_DRV_IRQHandler(29U);
274 }
275 
277 void DMA30_IRQHandler(void)
278 {
279  EDMA_DRV_IRQHandler(30U);
280 }
281 
283 void DMA31_IRQHandler(void)
284 {
285  EDMA_DRV_IRQHandler(31U);
286 }
287 #endif
288 #endif
289 
290 #ifdef FEATURE_EDMA_HAS_ERROR_IRQ
291 
292 void DMA_Error_IRQHandler(void)
293 {
295 }
296 #endif
297 
298 /*******************************************************************************
299  * EOF
300  ******************************************************************************/
301 
void EDMA_DRV_IRQHandler(uint8_t channel)
eDMA channel interrupt handler, implemented in driver c file.
Definition: edma_driver.c:436
void EDMA_DRV_ErrorIRQHandler(void)
Definition: edma_driver.c:456
#define DMA
Definition: S32K142.h:2219