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S32 SDK
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Modules | |
ENET Register Masks | |
Data Structures | |
struct | ENET_Type |
Macros | |
#define | ENET_CHANNEL_COUNT 4u |
#define | ENET_INSTANCE_COUNT (1u) |
#define | ENET_BASE (0x40079000u) |
#define | ENET ((ENET_Type *)ENET_BASE) |
#define | ENET_BASE_ADDRS { ENET_BASE } |
#define | ENET_BASE_PTRS { ENET } |
#define | ENET_IRQS_ARR_COUNT (6u) |
#define | ENET_TIMER_IRQS_CH_COUNT (1u) |
#define | ENET_TX_IRQS_CH_COUNT (1u) |
#define | ENET_RX_IRQS_CH_COUNT (1u) |
#define | ENET_ERR_IRQS_CH_COUNT (1u) |
#define | ENET_STOP_IRQS_CH_COUNT (1u) |
#define | ENET_WAKE_IRQS_CH_COUNT (1u) |
#define | ENET_TIMER_IRQS { ENET_TIMER_IRQn } |
#define | ENET_TX_IRQS { ENET_TX_IRQn } |
#define | ENET_RX_IRQS { ENET_RX_IRQn } |
#define | ENET_ERR_IRQS { ENET_ERR_IRQn } |
#define | ENET_STOP_IRQS { ENET_STOP_IRQn } |
#define | ENET_WAKE_IRQS { ENET_WAKE_IRQn } |
Typedefs | |
typedef struct ENET_Type * | ENET_MemMapPtr |
#define ENET_BASE (0x40079000u) |
#define ENET_BASE_ADDRS { ENET_BASE } |
#define ENET_BASE_PTRS { ENET } |
#define ENET_CHANNEL_COUNT 4u |
#define ENET_ERR_IRQS { ENET_ERR_IRQn } |
#define ENET_ERR_IRQS_CH_COUNT (1u) |
#define ENET_INSTANCE_COUNT (1u) |
#define ENET_IRQS_ARR_COUNT (6u) |
#define ENET_RX_IRQS { ENET_RX_IRQn } |
#define ENET_RX_IRQS_CH_COUNT (1u) |
#define ENET_STOP_IRQS { ENET_STOP_IRQn } |
#define ENET_STOP_IRQS_CH_COUNT (1u) |
#define ENET_TIMER_IRQS { ENET_TIMER_IRQn } |
#define ENET_TIMER_IRQS_CH_COUNT (1u) |
#define ENET_TX_IRQS { ENET_TX_IRQn } |
#define ENET_TX_IRQS_CH_COUNT (1u) |
#define ENET_WAKE_IRQS { ENET_WAKE_IRQn } |
#define ENET_WAKE_IRQS_CH_COUNT (1u) |
typedef struct ENET_Type * ENET_MemMapPtr |