99 const isr_t newHandler,
100 isr_t*
const oldHandler)
110 if (oldHandler != (
isr_t *) 0)
115 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
117 DEV_ASSERT((uint32_t)irqNumber < MSCM_IRSPRC_COUNT);
119 uint16_t cpu_enable = (uint16_t)(1UL << (
MSCM->CPXNUM));
120 if ((
MSCM->IRSPRC[irqNumber] & cpu_enable) == 0U)
122 DEV_ASSERT((
MSCM->IRSPRC[irqNumber] & (uint16_t)(MSCM_IRSPRC_RO_MASK)) == (uint16_t)MSCM_IRSPRC_RO(0));
128 __VECTOR_RAM[((int32_t)irqNumber) + 16] = (uint32_t)newHandler;
148 S32_NVIC->ISER[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
150 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
153 uint16_t cpu_enable = (uint16_t)(1UL << (
MSCM->CPXNUM));
154 MSCM->IRSPRC[irqNumber] |= cpu_enable;
175 S32_NVIC->ICER[((uint32_t)(irqNumber) >> 5U)] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
177 #if FEATURE_MSCM_HAS_INTERRUPT_ROUTER
180 uint16_t cpu_enable = (uint16_t)(1UL << (
MSCM->CPXNUM));
181 MSCM->IRSPRC[irqNumber] &= (uint16_t)~(cpu_enable);
244 if ((int32_t)irqNumber < 0)
246 uint32_t intVectorId = ((uint32_t)(irqNumber) & 0xFU);
247 uint32_t regId = intVectorId / 4U;
249 volatile uint8_t * shpr_reg_ptr = ((regId == 1U) ? (
volatile uint8_t *)&
S32_SCB->SHPR1 : ((regId == 2U) ? (
volatile uint8_t *)&
S32_SCB->SHPR2 : (
volatile uint8_t *)&
S32_SCB->SHPR3));
251 shpr_reg_ptr[intVectorId % 4U] = (uint8_t)(((((uint32_t)priority) << shift)) & 0xffUL);
256 S32_NVIC->IP[(uint32_t)(irqNumber)] = (uint8_t)(((((uint32_t)priority) << shift)) & 0xFFUL);
274 uint8_t priority = 0U;
277 if ((int32_t)irqNumber < 0)
279 uint32_t intVectorId = ((uint32_t)(irqNumber) & 0xFU);
280 uint32_t regId = intVectorId / 4U;
283 volatile const uint8_t * shpr_reg_ptr = ((regId == 1U) ? (
volatile uint8_t *)&
S32_SCB->SHPR1 : ((regId == 2U) ? (
volatile uint8_t *)&
S32_SCB->SHPR2 : (
volatile uint8_t *)&
S32_SCB->SHPR3));
285 priority = (uint8_t)(shpr_reg_ptr[intVectorId % 4U] >> (shift));
290 priority = (uint8_t)(
S32_NVIC->IP[(uint32_t)(irqNumber)] >> shift);
296 #if FEATURE_INTERRUPT_HAS_PENDING_STATE
306 void INT_SYS_ClearPending(
IRQn_Type irqNumber)
312 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
314 if ((FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber) && (irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX))
317 switch (
MSCM->CPXNUM)
320 MSCM->IRCP0IR |= (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN));
323 MSCM->IRCP1IR |= (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN));
331 S32_NVIC->ICPR[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
342 void INT_SYS_SetPending(
IRQn_Type irqNumber)
349 S32_NVIC->ISPR[(uint32_t)(irqNumber) >> 5U] = (uint32_t)(1UL << ((uint32_t)(irqNumber) & (uint32_t)0x1FU));
361 uint32_t INT_SYS_GetPending(
IRQn_Type irqNumber)
367 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
369 if ((FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber) && (irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX))
371 return (((((
MSCM->CPXNUM != 0UL) ?
MSCM->IRCP1IR :
MSCM->IRCP0IR) &
372 (1UL << ((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN))) != 0UL) ? 1UL : 0UL);
377 return ((uint32_t)(((
S32_NVIC->ISPR[(((uint32_t)irqNumber) >> 5UL)] & (1UL << (((uint32_t)irqNumber) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
381 #if FEATURE_INTERRUPT_HAS_ACTIVE_STATE
390 uint32_t INT_SYS_GetActive(
IRQn_Type irqNumber)
397 return ((uint32_t)(((
S32_NVIC->IABR[(((uint32_t)irqNumber) >> 5UL)] & (1UL << (((uint32_t)irqNumber) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
401 #if FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER
420 void INT_SYS_GenerateDirectedCpuInterrupt(
IRQn_Type irqNumber, interrupt_manager_cpu_targets_t cpu_target)
423 DEV_ASSERT(FEATURE_DIRECTED_CPU_INT_MIN <= irqNumber);
424 DEV_ASSERT(irqNumber <= FEATURE_DIRECTED_CPU_INT_MAX);
426 uint32_t reg_val = MSCM_IRCPGIR_INTID((uint32_t)irqNumber - (uint32_t)FEATURE_DIRECTED_CPU_INT_MIN);
430 case INTERRUPT_MANAGER_TARGET_SELF:
431 reg_val |= MSCM_IRCPGIR_TLF(2);
433 case INTERRUPT_MANAGER_TARGET_OTHERS:
434 reg_val |= MSCM_IRCPGIR_TLF(1);
436 case INTERRUPT_MANAGER_TARGET_NONE:
437 case INTERRUPT_MANAGER_TARGET_CP0:
438 case INTERRUPT_MANAGER_TARGET_CP1:
439 case INTERRUPT_MANAGER_TARGET_CP0_CP1:
440 reg_val |= (MSCM_IRCPGIR_TLF(0) | MSCM_IRCPGIR_CPUTL(cpu_target));
448 MSCM->IRCPGIR = reg_val;
uint32_t __VECTOR_RAM[((uint32_t)(FEATURE_INTERRUPT_IRQ_MAX))+16U+1U]
Declaration of vector table. FEATURE_INTERRUPT_IRQ_MAX is the highest interrupt request number...
#define FEATURE_INTERRUPT_IRQ_MIN
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void INT_SYS_DisableIRQGlobal(void)
Disable system interrupt.
static int32_t g_interruptDisableCount
Counter to manage the nested callings of global disable/enable interrupt.
#define FEATURE_NVIC_PRIO_BITS
#define ENABLE_INTERRUPTS()
Enable FPU.
void INT_SYS_SetPriority(IRQn_Type irqNumber, uint8_t priority)
Set Interrupt Priority.
void INT_SYS_EnableIRQGlobal(void)
Enables system interrupt.
#define FEATURE_INTERRUPT_IRQ_MAX
uint8_t INT_SYS_GetPriority(IRQn_Type irqNumber)
Get Interrupt Priority.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
void(* isr_t)(void)
Interrupt handler type.
#define DISABLE_INTERRUPTS()
Disable interrupts.
IRQn_Type
Defines the Interrupt Numbers definitions.
void INT_SYS_InstallHandler(IRQn_Type irqNumber, const isr_t newHandler, isr_t *const oldHandler)
Installs an interrupt handler routine for a given IRQ number.