S32 SDK
flash_mx25l6433f_driver.c
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
19 #include "quadspi_driver.h"
20 #include "osif.h"
21 
22 
23 /*******************************************************************************
24  * Variables
25  ******************************************************************************/
26 
29 /* Number of attempts for flash commands */
30 #define FLASH_MX25L6433F_MAX_RETRY 1U
31 /* Wrap-around value for timeout */
32 #define FLASH_MX25L6433F_TIMEOUT_WRAP 0xFFFFFFFFU
33 /* Timeout for synchronous operations */
34 #define FLASH_MX25L6433F_TIMEOUT 1U
35 
36 /* LUT entries used for various command sequences */
37 #define FLASH_MX25L6433F_LUT_4READ 0U /* Quad read */
38 #define FLASH_MX25L6433F_LUT_WREN 1U /* Write enable */
39 #define FLASH_MX25L6433F_LUT_RDSR 2U /* Read status register */
40 #define FLASH_MX25L6433F_LUT_RDCR 3U /* Read configuration register */
41 #define FLASH_MX25L6433F_LUT_WRSR 4U /* Write status register */
42 #define FLASH_MX25L6433F_LUT_4PP 5U /* Quad program */
43 #define FLASH_MX25L6433F_LUT_SE 6U /* Sector erase */
44 #define FLASH_MX25L6433F_LUT_BE32K 7U /* Block erase (32 Kb) */
45 #define FLASH_MX25L6433F_LUT_BE 8U /* Block erase (64 Kb) */
46 #define FLASH_MX25L6433F_LUT_CE 9U /* Chip erase */
47 #define FLASH_MX25L6433F_LUT_RSTEN 10U /* Reset enable */
48 #define FLASH_MX25L6433F_LUT_RST 11U /* Reset */
49 #define FLASH_MX25L6433F_LUT_WRSCUR 12U /* Write security register */
50 #define FLASH_MX25L6433F_LUT_RDSCUR 13U /* Read security register */
51 
52 #define FLASH_MX25L6433F_LUT_OTHER 15U /* Shared LUT for less common commands */
53 
54 
55 /* Macros for serial flash status bits manipulation */
56 #define FLASH_MX25L6433F_SR_WIP_MASK 0x1u
57 #define FLASH_MX25L6433F_SR_WIP_SHIFT 0u
58 #define FLASH_MX25L6433F_SR_WIP(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SR_WIP_SHIFT))&FLASH_MX25L6433F_SR_WIP_MASK)
59 
60 #define FLASH_MX25L6433F_SR_WEL_MASK 0x2u
61 #define FLASH_MX25L6433F_SR_WEL_SHIFT 1u
62 #define FLASH_MX25L6433F_SR_WEL(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SR_WEL_SHIFT))&FLASH_MX25L6433F_SR_WEL_MASK)
63 
64 #define FLASH_MX25L6433F_SR_BP_MASK 0x3Cu
65 #define FLASH_MX25L6433F_SR_BP_SHIFT 2u
66 #define FLASH_MX25L6433F_SR_BP(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SR_BP_SHIFT))&FLASH_MX25L6433F_SR_BP_MASK)
67 
68 #define FLASH_MX25L6433F_SR_QE_MASK 0x40u
69 #define FLASH_MX25L6433F_SR_QE_SHIFT 6u
70 #define FLASH_MX25L6433F_SR_QE(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SR_QE_SHIFT))&FLASH_MX25L6433F_SR_QE_MASK)
71 
72 #define FLASH_MX25L6433F_SR_SRWD_MASK 0x80u
73 #define FLASH_MX25L6433F_SR_SRWD_SHIFT 7u
74 #define FLASH_MX25L6433F_SR_SRWD(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SR_SRWD_SHIFT))&FLASH_MX25L6433F_SR_SRWD_MASK)
75 
76 /* Macros for serial flash configuration bits manipulation */
77 #define FLASH_MX25L6433F_CFG_ODS_MASK 0x1u
78 #define FLASH_MX25L6433F_CFG_ODS_SHIFT 0u
79 #define FLASH_MX25L6433F_CFG_ODS(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_CFG_ODS_SHIFT))&FLASH_MX25L6433F_CFG_ODS_MASK)
80 
81 #define FLASH_MX25L6433F_CFG_TB_MASK 0x8u
82 #define FLASH_MX25L6433F_CFG_TB_SHIFT 3u
83 #define FLASH_MX25L6433F_CFG_TB(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_CFG_TB_SHIFT))&FLASH_MX25L6433F_CFG_TB_MASK)
84 
85 #define FLASH_MX25L6433F_CFG_DC_MASK 0x40u
86 #define FLASH_MX25L6433F_CFG_DC_SHIFT 6u
87 #define FLASH_MX25L6433F_CFG_DC(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_CFG_DC_SHIFT))&FLASH_MX25L6433F_CFG_DC_MASK)
88 
89 /* Macros for serial flash security bits manipulation */
90 #define FLASH_MX25L6433F_SEC_OTP_MASK 0x1u
91 #define FLASH_MX25L6433F_SEC_OTP_SHIFT 0u
92 #define FLASH_MX25L6433F_SEC_OTP(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SEC_OTP_SHIFT))&FLASH_MX25L6433F_SEC_OTP_MASK)
93 
94 #define FLASH_MX25L6433F_SEC_LDSO_MASK 0x2u
95 #define FLASH_MX25L6433F_SEC_LDSO_SHIFT 1u
96 #define FLASH_MX25L6433F_SEC_LDSO(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SEC_LDSO_SHIFT))&FLASH_MX25L6433F_SEC_LDSO_MASK)
97 
98 #define FLASH_MX25L6433F_SEC_PSB_MASK 0x4u
99 #define FLASH_MX25L6433F_SEC_PSB_SHIFT 2u
100 #define FLASH_MX25L6433F_SEC_PSB(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SEC_PSB_SHIFT))&FLASH_MX25L6433F_SEC_PSB_MASK)
101 
102 #define FLASH_MX25L6433F_SEC_ESB_MASK 0x8u
103 #define FLASH_MX25L6433F_SEC_ESB_SHIFT 3u
104 #define FLASH_MX25L6433F_SEC_ESB(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SEC_ESB_SHIFT))&FLASH_MX25L6433F_SEC_ESB_MASK)
105 
106 #define FLASH_MX25L6433F_SEC_P_FAIL_MASK 0x20u
107 #define FLASH_MX25L6433F_SEC_P_FAIL_SHIFT 5u
108 #define FLASH_MX25L6433F_SEC_P_FAIL(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SEC_P_FAIL_SHIFT))&FLASH_MX25L6433F_SEC_P_FAIL_MASK)
109 
110 #define FLASH_MX25L6433F_SEC_E_FAIL_MASK 0x40u
111 #define FLASH_MX25L6433F_SEC_E_FAIL_SHIFT 6u
112 #define FLASH_MX25L6433F_SEC_E_FAIL(x) (((uint32_t)(((uint32_t)(x))<<FLASH_MX25L6433F_SEC_E_FAIL_SHIFT))&FLASH_MX25L6433F_SEC_E_FAIL_MASK)
113 
114 
115 
116 
119 typedef enum
120 {
121  FLASH_MX25L6433F_READ = 0x03U,
122  FLASH_MX25L6433F_FAST_READ = 0x0BU,
123  FLASH_MX25L6433F_2READ = 0xBBU,
124  FLASH_MX25L6433F_DREAD = 0x3BU,
125  FLASH_MX25L6433F_4READ = 0xEBU,
126  FLASH_MX25L6433F_QREAD = 0x6BU,
127  FLASH_MX25L6433F_WREN = 0x06U,
128  FLASH_MX25L6433F_WRDI = 0x04U,
129  FLASH_MX25L6433F_RDSR = 0x05U,
130  FLASH_MX25L6433F_RDCR = 0x15U,
131  FLASH_MX25L6433F_WRSR = 0x01U,
132  FLASH_MX25L6433F_4PP = 0x38U,
133  FLASH_MX25L6433F_SE = 0x20U,
134  FLASH_MX25L6433F_BE32K = 0x52U,
135  FLASH_MX25L6433F_BE = 0xD8U,
136  FLASH_MX25L6433F_CE = 0x60U,
137  FLASH_MX25L6433F_PP = 0x02U,
138  FLASH_MX25L6433F_DP = 0xB9U,
139  FLASH_MX25L6433F_RDP = 0xABU,
140  FLASH_MX25L6433F_PESUS = 0x75U,
141  FLASH_MX25L6433F_PERES = 0x7AU,
142  FLASH_MX25L6433F_RDID = 0x9FU,
143  FLASH_MX25L6433F_RES = 0xABU,
144  FLASH_MX25L6433F_REMS = 0x90U,
145  FLASH_MX25L6433F_ENSO = 0xB1U,
146  FLASH_MX25L6433F_EXSO = 0xC1U,
147  FLASH_MX25L6433F_WRSCUR = 0x2FU,
148  FLASH_MX25L6433F_RDSCUR = 0x2BU,
149  FLASH_MX25L6433F_RSTEN = 0x66U,
150  FLASH_MX25L6433F_RST = 0x99U,
151  FLASH_MX25L6433F_RDSFDP = 0x5AU,
152  FLASH_MX25L6433F_SBL = 0xC0U,
153  FLASH_MX25L6433F_NOP = 0x00U,
154 } flash_mx25l6433f_commands_t;
155 
156 
157 /* Pointer to runtime state structures */
158 static flash_mx25l6433f_state_t * g_flashMx25l6433fStatePtr[QuadSPI_INSTANCE_COUNT] = {NULL};
159 
160 
161 /*******************************************************************************
162  * Private Functions
163  ******************************************************************************/
164 
165 
166  /*FUNCTION**********************************************************************
167  *
168  * Function Name : FLASH_MX25L6433F_DRV_Timeout
169  * Description : Checks for timeout condition
170  *
171  *END**************************************************************************/
172 static bool FLASH_MX25L6433F_DRV_Timeout(uint32_t startTime, uint32_t timeout)
173 {
174  uint32_t currentTime;
175  bool retVal;
176 
177  currentTime = OSIF_GetMilliseconds();
178  if (currentTime >= startTime)
179  {
180  retVal = ((currentTime - startTime) > timeout)?true:false;
181  }
182  else
183  {
184  /* wrap around */
185  retVal = ((FLASH_MX25L6433F_TIMEOUT_WRAP - startTime + currentTime) > timeout)?true:false;
186  }
187  return retVal;
188 }
189 
190 
191 /*FUNCTION**********************************************************************
192  *
193  * Function Name : FLASH_MX25L6433F_DRV_WriteEnable
194  * Description : Enables the serial flash memory for a program or erase operation
195  *
196  *END**************************************************************************/
197 static status_t FLASH_MX25L6433F_DRV_WriteEnable(uint32_t instance)
198 {
199  uint32_t retries = FLASH_MX25L6433F_MAX_RETRY + 1U;
200  status_t status = STATUS_TIMEOUT;
201  uint8_t srValue = 0U;
202 
203  while (retries > 0U)
204  {
205  /* send WREN command */
206  QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_WREN, 1U);
207  /* send RDSR command */
208  QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSR, 0U, &srValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
209  /* check WEL == 1 */
210  if (srValue & FLASH_MX25L6433F_SR_WEL_MASK)
211  {
212  status = STATUS_SUCCESS;
213  break;
214  }
215  retries--;
216  }
217 
218  return status;
219 }
220 
221 
222 /*FUNCTION**********************************************************************
223  *
224  * Function Name : FLASH_MX25L6433F_DRV_CheckLastCommand
225  * Description : Checks the outcome of the last program/erase operation
226  *
227  *END**************************************************************************/
228 static status_t FLASH_MX25L6433F_DRV_CheckLastCommand(uint32_t instance)
229 {
230  uint8_t secValue;
231  status_t status = STATUS_ERROR;
232  flash_mx25l6433f_state_t * state;
233 
234  state = g_flashMx25l6433fStatePtr[instance];
235 
236  switch ((flash_mx25l6433f_commands_t)(state->lastCommand))
237  {
238  case FLASH_MX25L6433F_4PP:
239  /* check success of program command */
240  /* read security register */
241  QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSCUR, 0U, &secValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
242  if (secValue & FLASH_MX25L6433F_SEC_P_FAIL_MASK)
243  {
244  status = STATUS_ERROR;
245  }
246  else
247  {
248  status = STATUS_SUCCESS;
249  }
250  break;
251  case FLASH_MX25L6433F_SE:
252  case FLASH_MX25L6433F_BE32K:
253  case FLASH_MX25L6433F_BE:
254  case FLASH_MX25L6433F_CE:
255  /* check success of erase command */
256  /* read security register */
257  QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSCUR, 0U, &secValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
258  if (secValue & FLASH_MX25L6433F_SEC_E_FAIL_MASK)
259  {
260  status = STATUS_ERROR;
261  }
262  else
263  {
264  status = STATUS_SUCCESS;
265  }
266  break;
267  case FLASH_MX25L6433F_WRSR:
268  default:
269  status = STATUS_SUCCESS;
270  break;
271  }
272  return status;
273 }
274 
275 
276 /*FUNCTION**********************************************************************
277  *
278  * Function Name : FLASH_MX25L6433F_DRV_InitLut
279  * Description : Initializes LUT sequences for MX25L6433F commands
280  *
281  *END**************************************************************************/
282 static inline void FLASH_MX25L6433F_DRV_InitLut(uint32_t instance)
283 {
284 /* 4 x Read Sequence */
285  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_4READ),
286  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_4READ, /* 4READ command on 1 data line */
287  QSPI_LUT_CMD_ADDR, QSPI_LUT_PADS_4, 24U); /* 24-bit address on 4 data lines */
288  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_4READ) + 1U,
289  QSPI_LUT_CMD_MODE, QSPI_LUT_PADS_4, 0xFFU, /* Performance enhance indicator: 0xFF */
290  QSPI_LUT_CMD_DUMMY, QSPI_LUT_PADS_4, 4U); /* 4 Dummy cycles (for a total of 6) */
291  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_4READ) + 2U,
292  QSPI_LUT_CMD_READ, QSPI_LUT_PADS_4, 0x10U, /* Read data on 4 data lines */
293  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
294 
295 /* WREN Sequence */
296  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_WREN),
297  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_WREN, /* WREN command on 1 data line */
298  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
299 
300 /* WRSR Sequence */
301  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_WRSR),
302  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_WRSR, /* WRSR command on 1 data line */
303  QSPI_LUT_CMD_WRITE, QSPI_LUT_PADS_1, 2U); /* Send data on 1 data line */
304  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_WRSR) + 1U,
305  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
307 
308 /* RDSR Sequence */
309  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RDSR),
310  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_RDSR, /* RDSR command on 1 data line */
311  QSPI_LUT_CMD_READ, QSPI_LUT_PADS_1, 1U); /* Read data on 1 data line */
312  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RDSR) + 1U,
313  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
315 
316 /* RDCR Sequence */
317  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RDCR),
318  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_RDCR, /* RDCR command on 1 data line */
319  QSPI_LUT_CMD_READ, QSPI_LUT_PADS_1, 1U); /* Read data on 1 data line */
320  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RDCR) + 1U,
321  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
323 
324 /* 4PP Sequence */
325  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_4PP),
326  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_4PP, /* 4PP command on 1 data line */
327  QSPI_LUT_CMD_ADDR, QSPI_LUT_PADS_4, 24U); /* 24-bit address on 4 data lines */
328  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_4PP) + 1U,
329  QSPI_LUT_CMD_WRITE, QSPI_LUT_PADS_4, 0x10U, /* Send data on 4 data lines */
331 
332 /* SE Sequence */
333  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_SE),
334  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_SE, /* SE command on 1 data line */
335  QSPI_LUT_CMD_ADDR, QSPI_LUT_PADS_1, 24U); /* 24-bit address on 1 data line */
336  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_SE) + 1U,
337  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
339 
340 /* BE Sequence */
341  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_BE),
342  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_BE, /* BE command on 1 data line */
343  QSPI_LUT_CMD_ADDR, QSPI_LUT_PADS_1, 24U); /* 24-bit address on 1 data line */
344  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_BE) + 1U,
345  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
347 
348 /* BE32K Sequence */
349  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_BE32K),
350  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_BE32K, /* BE32K command on 1 data line */
351  QSPI_LUT_CMD_ADDR, QSPI_LUT_PADS_1, 24U); /* 24-bit address on 1 data line */
352  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_BE32K) + 1U,
353  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
355 
356 /* CE Sequence */
357  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_CE),
358  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_CE, /* CE command on 1 data line */
359  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
360 
361 /* RSTEN Sequence */
362  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RSTEN),
363  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_RSTEN, /* RSTEN command on 1 data line */
364  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
365 
366 /* RST Sequence */
367  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RST),
368  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_RST, /* RST command on 1 data line */
369  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
370 
371 /* WRSCUR Sequence */
372  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_WRSCUR),
373  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_WRSCUR, /* WRSCUR command on 1 data line */
374  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
375 
376 /* RDSCUR Sequence */
377  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RDSCUR),
378  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_RDSCUR, /* RDSCUR command on 1 data line */
379  QSPI_LUT_CMD_READ, QSPI_LUT_PADS_1, 1U); /* Read data on 1 data line */
380  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_RDSCUR) + 1U,
381  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U, /* End of sequence */
383 }
384 
385 
386 /*FUNCTION**********************************************************************
387  *
388  * Function Name : FLASH_MX25L6433F_DRV_InitEnso
389  * Description : Programs the sequence for ENSO command in the last LUT sequence
390  *
391  *END**************************************************************************/
392 static inline void FLASH_MX25L6433F_DRV_InitEnso(uint32_t instance)
393 {
394 /* ENSO Sequence */
395  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_OTHER),
396  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_ENSO, /* ENSO command on 1 data line */
397  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
398 }
399 
400 
401 /*FUNCTION**********************************************************************
402  *
403  * Function Name : FLASH_MX25L6433F_DRV_InitExso
404  * Description : Programs the sequence for EXSO command in the last LUT sequence
405  *
406  *END**************************************************************************/
407 static inline void FLASH_MX25L6433F_DRV_InitExso(uint32_t instance)
408 {
409 /* EXSO Sequence */
410  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_OTHER),
411  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_EXSO, /* EXSO command on 1 data line */
412  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
413 }
414 
415 
416 /*FUNCTION**********************************************************************
417  *
418  * Function Name : FLASH_MX25L6433F_DRV_InitDp
419  * Description : Programs the sequence for DP command in the last LUT sequence
420  *
421  *END**************************************************************************/
422 static inline void FLASH_MX25L6433F_DRV_InitDp(uint32_t instance)
423 {
424 /* DP Sequence */
425  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_OTHER),
426  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_DP, /* DP command on 1 data line */
427  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
428 }
429 
430 
431 /*FUNCTION**********************************************************************
432  *
433  * Function Name : FLASH_MX25L6433F_DRV_InitRdp
434  * Description : Programs the sequence for RDP command in the last LUT sequence
435  *
436  *END**************************************************************************/
437 static inline void FLASH_MX25L6433F_DRV_InitRdp(uint32_t instance)
438 {
439 /* RDP Sequence */
440  QSPI_DRV_SetLut(instance, (4U * FLASH_MX25L6433F_LUT_OTHER),
441  QSPI_LUT_CMD_CMD, QSPI_LUT_PADS_1, FLASH_MX25L6433F_RDP, /* RDP command on 1 data line */
442  QSPI_LUT_CMD_STOP, QSPI_LUT_PADS_1, 0U); /* End of sequence */
443 }
444 
445 
446 /*FUNCTION**********************************************************************
447  *
448  * Function Name : FLASH_MX25L6433F_DRV_InitDevice
449  * Description : Initializes the MX25L6433F device
450  *
451  *END**************************************************************************/
452 static inline status_t FLASH_MX25L6433F_DRV_InitDevice(uint32_t instance,
453  const flash_mx25l6433f_user_config_t * userConfigPtr)
454 {
455  uint8_t srValue;
456  uint8_t crValue;
457  uint8_t srWrite[2U];
458  status_t status;
459  uint32_t startTime;
460 
461  /* Enable quad operations, configure drive strength, configure dummy cycles to 0 (<80MHz) */
462  /* send RDSR command */
463  status = QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSR, 0U, &srValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
464  if (status != STATUS_SUCCESS)
465  {
466  return status;
467  }
468  /* send RDCR command */
469  status = QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDCR, 0U, &crValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
470  if (status != STATUS_SUCCESS)
471  {
472  return status;
473  }
474  /* Check if current settings are ok */
475  if (((srValue & FLASH_MX25L6433F_SR_QE_MASK) == 0U) ||
476  (((crValue & FLASH_MX25L6433F_CFG_ODS_MASK) >> FLASH_MX25L6433F_CFG_ODS_SHIFT) != userConfigPtr->outputDriverStrength) ||
477  ((crValue & FLASH_MX25L6433F_CFG_DC_MASK) != 0U))
478  {
479  /* enable write before WRSR command */
480  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
481  if (status != STATUS_SUCCESS)
482  {
483  return status;
484  }
485  /* QE not set, write SR to set it */
486  srWrite[0U] = (uint8_t)(srValue | FLASH_MX25L6433F_SR_QE_MASK);
487  crValue &= (uint8_t)(~(FLASH_MX25L6433F_CFG_ODS_MASK | FLASH_MX25L6433F_CFG_DC_MASK));
488  srWrite[1U] = (uint8_t)(crValue | FLASH_MX25L6433F_CFG_ODS(userConfigPtr->outputDriverStrength));
489  status = QSPI_DRV_IpWrite(instance, FLASH_MX25L6433F_LUT_WRSR, 0U, srWrite, 2U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
490  if (status != STATUS_SUCCESS)
491  {
492  return status;
493  }
494  /* Wait for the command to complete. */
495  startTime = OSIF_GetMilliseconds();
496  do
497  {
498  status = FLASH_MX25L6433F_DRV_GetStatus(instance);
499  }
500  while ((status == STATUS_BUSY) && !FLASH_MX25L6433F_DRV_Timeout(startTime, FLASH_MX25L6433F_TIMEOUT));
501  if (status == STATUS_BUSY)
502  {
503  status = STATUS_TIMEOUT;
504  }
505  }
506  return status;
507 }
508 
511 /*******************************************************************************
512  * Code
513  ******************************************************************************/
514 
515 /*FUNCTION**********************************************************************
516  *
517  * Function Name : FLASH_MX25L6433F_DRV_Init
518  * Description : Initialize the serial flash memory driver
519  * Implements : FLASH_MX25L6433F_DRV_Init_Activity
520  *
521  *END**************************************************************************/
523  const flash_mx25l6433f_user_config_t * userConfigPtr,
524  flash_mx25l6433f_state_t * state)
525 {
526  status_t status;
527 
529  DEV_ASSERT(g_flashMx25l6433fStatePtr[instance] == NULL);
530 
531  /* Copy configuration parameters to state structure */
532  state->outputDriverStrength = userConfigPtr->outputDriverStrength;
533  state->dmaSupport = userConfigPtr->dmaSupport;
534  state->lastCommand = (uint8_t)FLASH_MX25L6433F_NOP;
535  /* QuadSPI is assumed to be already initialized by the application */
536  /* Initialize LUT */
537  FLASH_MX25L6433F_DRV_InitLut(instance);
538  /* AHB Setup */
539  QSPI_DRV_SetAhbSeqId(instance, FLASH_MX25L6433F_LUT_4READ);
540 
541  /* Initialize device */
542  status = FLASH_MX25L6433F_DRV_InitDevice(instance, userConfigPtr);
543  if (status != STATUS_SUCCESS)
544  {
545  return status;
546  }
547 
548  g_flashMx25l6433fStatePtr[instance] = state;
549 
550  return STATUS_SUCCESS;
551 }
552 
553 
554 /*FUNCTION**********************************************************************
555  *
556  * Function Name : FLASH_MX25L6433F_DRV_Deinit
557  * Description : De-initialize the MX25L6433F flash driver
558  * Implements : FLASH_MX25L6433F_DRV_Deinit_Activity
559  *
560  *END**************************************************************************/
562 {
564 
565  g_flashMx25l6433fStatePtr[instance] = NULL;
566  /* Deinitialize QuadSPI */
567  return QSPI_DRV_Deinit(instance);
568 }
569 
570 
571 /*FUNCTION**********************************************************************
572  *
573  * Function Name : FLASH_MX25L6433F_DRV_SetProtection
574  * Description : Configure protected area of the device
575  * Implements : FLASH_MX25L6433F_DRV_SetProtection_Activity
576  *
577  *END**************************************************************************/
579  flash_mx25l6433f_prot_dir_t direction,
581 {
582  uint8_t srWrite[2U]; /* status register value / configuration register value */
584  status_t status;
585  flash_mx25l6433f_state_t * state;
586 
587  state = g_flashMx25l6433fStatePtr[instance];
588 
589  /* enable write before WRSR command */
590  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
591  if (status != STATUS_SUCCESS)
592  {
593  return status;
594  }
595  /* prepare new SR value; keep QE bit set */
596  srWrite[0U] = (uint8_t)(FLASH_MX25L6433F_SR_BP(size) | FLASH_MX25L6433F_SR_QE_MASK);
597  /* prepare new CR value; preserve ODS setting */
598  srWrite[1U]= (uint8_t)(FLASH_MX25L6433F_CFG_TB(direction) | FLASH_MX25L6433F_CFG_ODS(state->outputDriverStrength));
599  /* write protection bits to SR */
600  status = QSPI_DRV_IpWrite(instance, FLASH_MX25L6433F_LUT_WRSR, 0U, srWrite, 2U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
601  state->lastCommand = (uint8_t)FLASH_MX25L6433F_WRSR;
602 
603  return status;
604 }
605 
606 
607 /*FUNCTION**********************************************************************
608  *
609  * Function Name : FLASH_MX25L6433F_DRV_GetProtection
610  * Description : Get protected area of the device
611  * Implements : FLASH_MX25L6433F_DRV_GetProtection_Activity
612  *
613  *END**************************************************************************/
615  flash_mx25l6433f_prot_dir_t * direction,
617 {
618  uint8_t srValue;
619  uint8_t crValue;
620  status_t status;
621  flash_mx25l6433f_state_t * state;
622 
624 
625  state = g_flashMx25l6433fStatePtr[instance];
626  state->lastCommand = (uint8_t)FLASH_MX25L6433F_4READ;
627  /* send RDSR command */
628  status = QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSR, 0U, &srValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
629  if (status != STATUS_SUCCESS)
630  {
631  return status;
632  }
633  /* send RDCR command */
634  status = QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDCR, 0U, &crValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
635  if (status != STATUS_SUCCESS)
636  {
637  return status;
638  }
639  /* compute protection settings */
640  srValue = (uint8_t)((srValue & FLASH_MX25L6433F_SR_BP_MASK) >> FLASH_MX25L6433F_SR_BP_SHIFT);
641  *size = (flash_mx25l6433f_prot_size_t)srValue;
642  crValue = (uint8_t)((crValue & FLASH_MX25L6433F_CFG_TB_MASK) >> FLASH_MX25L6433F_CFG_TB_SHIFT);
643  *direction = (flash_mx25l6433f_prot_dir_t)crValue;
644 
645  return STATUS_SUCCESS;
646 }
647 
648 
649 /*FUNCTION**********************************************************************
650  *
651  * Function Name : FLASH_MX25L6433F_DRV_SetSecureLock
652  * Description : Locks the customer sector of the secured OTP area
653  * Implements : FLASH_MX25L6433F_DRV_SetSecureLock_Activity
654  *
655  *END**************************************************************************/
657 {
658  status_t status;
659 
661 
662  /* enable write before programming */
663  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
664  if (status != STATUS_SUCCESS)
665  {
666  return status;
667  }
668  /* send WRSCUR command */
669  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_WRSCUR, 1U);
670 
671  return status;
672 }
673 
674 
675 /*FUNCTION**********************************************************************
676  *
677  * Function Name : FLASH_MX25L6433F_DRV_GetSecureLock
678  * Description : Get lock status of the secured OTP area
679  * Implements : FLASH_MX25L6433F_DRV_GetSecureLock_Activity
680  *
681  *END**************************************************************************/
684 {
685  status_t status;
686  uint8_t secValue;
687 
689  /* Send RDCR command */
690  status = QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSCUR, 0U, &secValue, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
691  if (status != STATUS_SUCCESS)
692  {
693  return status;
694  }
695  /* Extract lock indicators */
696  lock->userAreaLock = (bool)((secValue & FLASH_MX25L6433F_SEC_LDSO_MASK) >> FLASH_MX25L6433F_SEC_LDSO_SHIFT);
697  lock->factoryAreaLock = (bool)((secValue & FLASH_MX25L6433F_SEC_OTP_MASK) >> FLASH_MX25L6433F_SEC_OTP_SHIFT);
698  return STATUS_SUCCESS;
699 }
700 
701 
702 /*FUNCTION**********************************************************************
703  *
704  * Function Name : FLASH_MX25L6433F_DRV_Read
705  * Description : Read data from serial flash
706  * Implements : FLASH_MX25L6433F_DRV_Read_Activity
707  *
708  *END**************************************************************************/
710  uint32_t address,
711  uint8_t * data,
712  uint32_t size)
713 {
714  flash_mx25l6433f_state_t * state;
715  qspi_transfer_type_t transferType;
716 
718 
719  state = g_flashMx25l6433fStatePtr[instance];
720  if (state->dmaSupport)
721  {
722  transferType = QSPI_TRANSFER_TYPE_ASYNC_DMA;
723  }
724  else
725  {
726  transferType = QSPI_TRANSFER_TYPE_ASYNC_INT;
727  }
728  /* launch read command and return */
729  state->lastCommand = (uint8_t)FLASH_MX25L6433F_4READ;
730  return QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_4READ, address, data, NULL, size, transferType, 1U);
731 }
732 
733 
734 /*FUNCTION**********************************************************************
735  *
736  * Function Name : FLASH_MX25L6433F_DRV_Erase4K
737  * Description : Erase a 4k sector in the serial flash
738  * Implements : FLASH_MX25L6433F_DRV_Erase4K_Activity
739  *
740  *END**************************************************************************/
741 status_t FLASH_MX25L6433F_DRV_Erase4K(uint32_t instance, uint32_t address)
742 {
743  status_t status;
744  flash_mx25l6433f_state_t * state;
745 
747  state = g_flashMx25l6433fStatePtr[instance];
748 
749  /* enable write before erasing */
750  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
751  if (status != STATUS_SUCCESS)
752  {
753  return status;
754  }
755  /* launch erase command and return */
756  state->lastCommand = (uint8_t)FLASH_MX25L6433F_SE;
757  return QSPI_DRV_IpErase(instance, FLASH_MX25L6433F_LUT_SE, address);
758 }
759 
760 
761 /*FUNCTION**********************************************************************
762  *
763  * Function Name : FLASH_MX25L6433F_DRV_Erase32K
764  * Description : Erase a 32k block in the serial flash
765  * Implements : FLASH_MX25L6433F_DRV_Erase32K_Activity
766  *
767  *END**************************************************************************/
768 status_t FLASH_MX25L6433F_DRV_Erase32K(uint32_t instance, uint32_t address)
769 {
770  status_t status;
771  flash_mx25l6433f_state_t * state;
772 
774 
775  state = g_flashMx25l6433fStatePtr[instance];
776  /* enable write before erasing */
777  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
778  if (status != STATUS_SUCCESS)
779  {
780  return status;
781  }
782  /* launch erase command and return */
783  state->lastCommand = (uint8_t)FLASH_MX25L6433F_BE32K;
784  return QSPI_DRV_IpErase(instance, FLASH_MX25L6433F_LUT_BE32K, address);
785 }
786 
787 
788 /*FUNCTION**********************************************************************
789  *
790  * Function Name : FLASH_MX25L6433F_DRV_Erase64K
791  * Description : Erase a 64k block in the serial flash
792  * Implements : FLASH_MX25L6433F_DRV_Erase64K_Activity
793  *
794  *END**************************************************************************/
795 status_t FLASH_MX25L6433F_DRV_Erase64K(uint32_t instance, uint32_t address)
796 {
797  status_t status;
798  flash_mx25l6433f_state_t * state;
799 
801 
802  state = g_flashMx25l6433fStatePtr[instance];
803  /* enable write before erasing */
804  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
805  if (status != STATUS_SUCCESS)
806  {
807  return status;
808  }
809  /* launch erase command and return */
810  state->lastCommand = (uint8_t)FLASH_MX25L6433F_BE;
811  return QSPI_DRV_IpErase(instance, FLASH_MX25L6433F_LUT_BE, address);
812 }
813 
814 
815 /*FUNCTION**********************************************************************
816  *
817  * Function Name : FLASH_MX25L6433F_DRV_EraseAll
818  * Description : Erases the entire serial flash
819  * Implements : FLASH_MX25L6433F_DRV_EraseAll_Activity
820  *
821  *END**************************************************************************/
823 {
824  status_t status;
825  flash_mx25l6433f_state_t * state;
826 
828 
829  state = g_flashMx25l6433fStatePtr[instance];
830  /* enable write before erasing */
831  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
832  if (status != STATUS_SUCCESS)
833  {
834  return status;
835  }
836  /* launch erase command and return */
837  state->lastCommand = (uint8_t)FLASH_MX25L6433F_CE;
838  return QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_CE, 1U);
839 }
840 
841 
842 /*FUNCTION**********************************************************************
843  *
844  * Function Name : FLASH_MX25L6433F_DRV_EraseVerify
845  * Description : Checks whether or not an area in the serial flash is erased
846  * Implements : FLASH_MX25L6433F_DRV_EraseVerify_Activity
847  *
848  *END**************************************************************************/
849 status_t FLASH_MX25L6433F_DRV_EraseVerify(uint32_t instance, uint32_t address, uint32_t size)
850 {
851  qspi_transfer_type_t transferType;
852  flash_mx25l6433f_state_t * state;
853 
855 
856  state = g_flashMx25l6433fStatePtr[instance];
857  /* not possible to use DMA for blank check */
858  transferType = QSPI_TRANSFER_TYPE_ASYNC_INT;
859  /* launch read command and return */
860  state->lastCommand = (uint8_t)FLASH_MX25L6433F_4READ;
861  return QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_4READ, address, NULL, NULL, size, transferType, 1U);
862 }
863 
864 
865 /*FUNCTION**********************************************************************
866  *
867  * Function Name : FLASH_MX25L6433F_DRV_Program
868  * Description : Writes data in serial flash
869  * Implements : FLASH_MX25L6433F_DRV_Program_Activity
870  *
871  *END**************************************************************************/
873  uint32_t address,
874  uint8_t * data,
875  uint32_t size)
876 {
877  status_t status;
878  qspi_transfer_type_t transferType;
879  flash_mx25l6433f_state_t * state;
880 
882 
883  state = g_flashMx25l6433fStatePtr[instance];
884  /* enable write before programming */
885  status = FLASH_MX25L6433F_DRV_WriteEnable(instance);
886  if (status != STATUS_SUCCESS)
887  {
888  return status;
889  }
890  if (state->dmaSupport)
891  {
892  transferType = QSPI_TRANSFER_TYPE_ASYNC_DMA;
893  }
894  else
895  {
896  transferType = QSPI_TRANSFER_TYPE_ASYNC_INT;
897  }
898  /* launch program command and return */
899  state->lastCommand = (uint8_t)FLASH_MX25L6433F_4PP;
900  return QSPI_DRV_IpWrite(instance, FLASH_MX25L6433F_LUT_4PP, address, data, size, transferType, 1U);
901 }
902 
903 
904 /*FUNCTION**********************************************************************
905  *
906  * Function Name : FLASH_MX25L6433F_DRV_ProgramVerify
907  * Description : Verifies the correctness of the programmed data
908  * Implements : FLASH_MX25L6433F_DRV_ProgramVerify_Activity
909  *
910  *END**************************************************************************/
912  uint32_t address,
913  const uint8_t * data,
914  uint32_t size)
915 {
916  qspi_transfer_type_t transferType;
917  flash_mx25l6433f_state_t * state;
918 
920 
921  state = g_flashMx25l6433fStatePtr[instance];
922  /* not possible to use DMA for blank check */
923  transferType = QSPI_TRANSFER_TYPE_ASYNC_INT;
924  /* launch read command and return */
925  state->lastCommand = (uint8_t)FLASH_MX25L6433F_4READ;
926  return QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_4READ, address, NULL, data, size, transferType, 1U);
927 }
928 
929 
930 /*FUNCTION**********************************************************************
931  *
932  * Function Name : FLASH_MX25L6433F_DRV_GetStatus
933  * Description : Get the status of the last operation
934  * Implements : FLASH_MX25L6433F_DRV_GetStatus_Activity
935  *
936  *END**************************************************************************/
938 {
939  status_t status;
940  uint8_t srValueRead;
941  flash_mx25l6433f_state_t * state;
942 
944 
945  state = g_flashMx25l6433fStatePtr[instance];
946  /* check if the QuadSPI command is complete */
947  status = QSPI_DRV_IpGetStatus(instance);
948  if (status != STATUS_SUCCESS)
949  {
950  return status;
951  }
952  /* Check if the operation has finished in the serial flash. Skip this part for read commands. */
953  if (state->lastCommand != FLASH_MX25L6433F_4READ)
954  {
955  /* send RDSR command */
956  QSPI_DRV_IpRead(instance, FLASH_MX25L6433F_LUT_RDSR, 0U, &srValueRead, NULL, 1U, QSPI_TRANSFER_TYPE_SYNC, FLASH_MX25L6433F_TIMEOUT);
957  /* check WIP == 0 */
958  if ((srValueRead & FLASH_MX25L6433F_SR_WIP_MASK) == 1U)
959  {
960  /* write/erase in progress */
961  return STATUS_BUSY;
962  }
963  /* check operation result */
964  status = FLASH_MX25L6433F_DRV_CheckLastCommand(instance);
965  }
966  return status;
967 }
968 
969 
970 /*FUNCTION**********************************************************************
971  *
972  * Function Name : FLASH_MX25L6433F_DRV_Reset
973  * Description : Reset the serial flash device
974  * Implements : FLASH_MX25L6433F_DRV_Reset_Activity
975  *
976  *END**************************************************************************/
978 {
979  status_t status;
980 
982 
983  /* send RSTEN command */
984  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_RSTEN, 1U);
985  if (status != STATUS_SUCCESS)
986  {
987  return status;
988  }
989  /* send RST command */
990  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_RST, 1U);
991  return status;
992 }
993 
994 
995 /*FUNCTION**********************************************************************
996  *
997  * Function Name : FLASH_MX25L6433F_DRV_EnterOTP
998  * Description : Enters OTP mode
999  * Implements : FLASH_MX25L6433F_DRV_EnterOTP_Activity
1000  *
1001  *END**************************************************************************/
1003 {
1004  status_t status;
1005 
1006  DEV_ASSERT(instance < QuadSPI_INSTANCE_COUNT);
1007 
1008  /* Prepare ENSO sequence in the shared LUT entry */
1009  FLASH_MX25L6433F_DRV_InitEnso(instance);
1010  /* send ENSO command */
1011  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_OTHER, 1U);
1012  return status;
1013 }
1014 
1015 
1016 /*FUNCTION**********************************************************************
1017  *
1018  * Function Name : FLASH_MX25L6433F_DRV_ExitOTP
1019  * Description : Exits OTP mode
1020  * Implements : FLASH_MX25L6433F_DRV_ExitOTP_Activity
1021  *
1022  *END**************************************************************************/
1024 {
1025  status_t status;
1026 
1027  DEV_ASSERT(instance < QuadSPI_INSTANCE_COUNT);
1028 
1029  /* Prepare EXSO sequence in the shared LUT entry */
1030  FLASH_MX25L6433F_DRV_InitExso(instance);
1031  /* send EXSO command */
1032  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_OTHER, 1U);
1033  return status;
1034 }
1035 
1036 
1037 /*FUNCTION**********************************************************************
1038  *
1039  * Function Name : FLASH_MX25L6433F_DRV_EnterDPD
1040  * Description : Enters Deep Power Down mode
1041  * Implements : FLASH_MX25L6433F_DRV_EnterDPD_Activity
1042  *
1043  *END**************************************************************************/
1045 {
1046  status_t status;
1047 
1048  DEV_ASSERT(instance < QuadSPI_INSTANCE_COUNT);
1049 
1050  /* Prepare DP sequence in the shared LUT entry */
1051  FLASH_MX25L6433F_DRV_InitDp(instance);
1052  /* send DP command */
1053  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_OTHER, 1U);
1054  return status;
1055 }
1056 
1057 
1058 /*FUNCTION**********************************************************************
1059  *
1060  * Function Name : FLASH_MX25L6433F_DRV_ExitDPD
1061  * Description : Exits Deep Power Down mode
1062  * Implements : FLASH_MX25L6433F_DRV_ExitDPD_Activity
1063  *
1064  *END**************************************************************************/
1066 {
1067  status_t status;
1068 
1069  DEV_ASSERT(instance < QuadSPI_INSTANCE_COUNT);
1070 
1071  /* Prepare RDP sequence in the shared LUT entry */
1072  FLASH_MX25L6433F_DRV_InitRdp(instance);
1073  /* send RDP command */
1074  status = QSPI_DRV_IpCommand(instance, FLASH_MX25L6433F_LUT_OTHER, 1U);
1075  return status;
1076 }
1077 
1078 
1079 /*******************************************************************************
1080  * EOF
1081  ******************************************************************************/
status_t FLASH_MX25L6433F_DRV_Deinit(uint32_t instance)
De-initialize the MX25L6433F flash driver.
status_t QSPI_DRV_IpRead(uint32_t instance, uint8_t lut, uint32_t addr, uint8_t *dataRead, const uint8_t *dataCmp, uint32_t size, qspi_transfer_type_t transferType, uint32_t timeout)
Launches an IP read command.
status_t FLASH_MX25L6433F_DRV_SetSecureLock(uint32_t instance)
Locks the customer sector of the secured OTP area.
status_t QSPI_DRV_IpWrite(uint32_t instance, uint8_t lut, uint32_t addr, uint8_t *data, uint32_t size, qspi_transfer_type_t transferType, uint32_t timeout)
Launches an IP write command.
qspi_transfer_type_t
Driver type Implements : qspi_transfer_type_t_Class.
uint32_t OSIF_GetMilliseconds(void)
Returns the number of miliseconds elapsed since starting the internal timer or starting the scheduler...
status_t FLASH_MX25L6433F_DRV_Erase32K(uint32_t instance, uint32_t address)
Erase a 32k block in the serial flash.
status_t FLASH_MX25L6433F_DRV_Erase64K(uint32_t instance, uint32_t address)
Erase a 64k block in the serial flash.
status_t FLASH_MX25L6433F_DRV_EnterOTP(uint32_t instance)
Enters OTP mode.
status_t QSPI_DRV_Deinit(uint32_t instance)
De-initialize the qspi driver.
status_t FLASH_MX25L6433F_DRV_Reset(uint32_t instance)
Reset the serial flash device.
#define DEV_ASSERT(x)
Definition: devassert.h:77
status_t FLASH_MX25L6433F_DRV_Erase4K(uint32_t instance, uint32_t address)
Erase a 4k sector in the serial flash.
status_t QSPI_DRV_IpErase(uint32_t instance, uint8_t lut, uint32_t addr)
Launches an IP erase command.
#define QuadSPI_INSTANCE_COUNT
Definition: S32K148.h:9800
status_t FLASH_MX25L6433F_DRV_EraseAll(uint32_t instance)
Erases the entire serial flash.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
Driver internal context structure.
static void QSPI_DRV_SetAhbSeqId(uint32_t instance, uint8_t seqID)
Sets sequence ID for AHB operations.
status_t FLASH_MX25L6433F_DRV_Init(uint32_t instance, const flash_mx25l6433f_user_config_t *userConfigPtr, flash_mx25l6433f_state_t *state)
Initializes the serial flash memory driver.
status_t QSPI_DRV_IpGetStatus(uint32_t instance)
Checks the status of the currently running IP command.
status_t FLASH_MX25L6433F_DRV_ExitDPD(uint32_t instance)
Exits Deep Power Down mode.
status_t FLASH_MX25L6433F_DRV_GetSecureLock(uint32_t instance, flash_mx25l6433f_secure_lock_t *lock)
Get lock status of the secured OTP area.
status_t FLASH_MX25L6433F_DRV_EraseVerify(uint32_t instance, uint32_t address, uint32_t size)
Checks whether or not an area in the serial flash is erased.
status_t QSPI_DRV_IpCommand(uint32_t instance, uint8_t lut, uint32_t timeout)
Launches a simple IP command.
status_t FLASH_MX25L6433F_DRV_SetProtection(uint32_t instance, flash_mx25l6433f_prot_dir_t direction, flash_mx25l6433f_prot_size_t size)
Configure protected area of the device.
status_t FLASH_MX25L6433F_DRV_GetStatus(uint32_t instance)
Get the status of the last operation.
flash_mx25l6433f_drv_strength_t outputDriverStrength
static void QSPI_DRV_SetLut(uint32_t instance, uint8_t lut, qspi_lut_commands_t instr0, qspi_lut_pads_t pad0, uint8_t oprnd0, qspi_lut_commands_t instr1, qspi_lut_pads_t pad1, uint8_t oprnd1)
Configures LUT commands.
status_t FLASH_MX25L6433F_DRV_ProgramVerify(uint32_t instance, uint32_t address, const uint8_t *data, uint32_t size)
Verifies the correctness of the programmed data.
status_t FLASH_MX25L6433F_DRV_Program(uint32_t instance, uint32_t address, uint8_t *data, uint32_t size)
Writes data in serial flash.
flash_mx25l6433f_prot_size_t
Size of flash protected area Implements : flash_mx25l6433f_prot_size_t_Class.
Flash protection settings Implements : flash_mx25l6433f_secure_lock_t_Class.
status_t FLASH_MX25L6433F_DRV_GetProtection(uint32_t instance, flash_mx25l6433f_prot_dir_t *direction, flash_mx25l6433f_prot_size_t *size)
Get protected area of the device.
status_t FLASH_MX25L6433F_DRV_EnterDPD(uint32_t instance)
Enters Deep Power Down mode.
status_t FLASH_MX25L6433F_DRV_Read(uint32_t instance, uint32_t address, uint8_t *data, uint32_t size)
Read data from serial flash.
Driver configuration structure.
flash_mx25l6433f_prot_dir_t
Flash protection direction Implements : flash_mx25l6433f_prot_dir_t_Class.
status_t FLASH_MX25L6433F_DRV_ExitOTP(uint32_t instance)
Exits OTP mode.