S32 SDK
clock_S32K1xx.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #if !defined (CLOCK_S32K1xx_H)
20 #define CLOCK_S32K1xx_H
21 
26 #include "device_registers.h"
27 #include "status.h"
28 #include <stdint.h>
29 #include <stdbool.h>
30 
31 
38 /*******************************************************************************
39  * Definitions
40  ******************************************************************************/
41 
45 extern const uint8_t peripheralFeaturesList[CLOCK_NAME_COUNT];
46 
47 
48 /* @brief TClk clock frequency. */
49 #define NUMBER_OF_TCLK_INPUTS 3U
50 extern uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */
51 
52 /* @brief EXTAL0 clock frequency. */
53 extern uint32_t g_xtal0ClkFreq;
54 
55 /* @brief RTC_CLKIN clock frequency. */
56 extern uint32_t g_RtcClkInFreq;
57 
62 typedef enum
63 {
64  SIM_RTCCLK_SEL_SOSCDIV1_CLK = 0x0U, /* SOSCDIV1 clock */
65  SIM_RTCCLK_SEL_LPO_32K = 0x1U, /* 32 kHz LPO clock */
66  SIM_RTCCLK_SEL_RTC_CLKIN = 0x2U, /* RTC_CLKIN clock */
67  SIM_RTCCLK_SEL_FIRCDIV1_CLK = 0x3U, /* FIRCDIV1 clock */
69 
74 typedef enum
75 {
76  SIM_LPO_CLK_SEL_LPO_128K = 0x0, /* 128 kHz LPO clock */
77  SIM_LPO_CLK_SEL_NO_CLOCK = 0x1, /* No clock */
78  SIM_LPO_CLK_SEL_LPO_32K = 0x2, /* 32 kHz LPO clock which is divided by the 128 kHz LPO clock */
79  SIM_LPO_CLK_SEL_LPO_1K = 0x3, /* 1 kHz LPO clock which is divided by the 128 kHz LPO clock */
81 
85 typedef enum
86 {
98 
102 typedef enum
103 {
113 
114 
119 typedef struct
120 {
121  bool initialize;
122  bool enable;
126 
127 
132 typedef struct
133 {
134  bool initialize;
138  bool enableLpo1k;
140 
145 typedef struct
146 {
147  bool initialize;
148  uint32_t tclkFreq[NUMBER_OF_TCLK_INPUTS];
150 
155 typedef struct
156 {
157  bool initialize;
158  bool enableMscm;
159  bool enableMpu;
160  bool enableDma;
161  bool enableErm;
162  bool enableEim;
164 
169 typedef struct
170 {
173 
174 
179 typedef enum
180 {
184 
185 
190 typedef struct
191 {
192  bool initialize;
193  bool divEnable;
195  uint8_t divider;
196  bool divFraction;
198 
203 typedef struct
204 {
212 
213 
218 typedef enum
219 {
226 
231 typedef enum
232 {
250 
255 typedef struct
256 {
262 
263 /* @} */
273 typedef enum
274 {
281 /* @} */
282 
283 
287 typedef enum
288 {
298 
299 
304 typedef enum
305 {
310 
315 typedef enum
316 {
321 
326 typedef enum
327 {
328  SCG_SOSC_GAIN_LOW = 0x0, /* Configure crystal oscillator for low-power operation */
329  SCG_SOSC_GAIN_HIGH = 0x1, /* Configure crystal oscillator for high-gain operation */
331 
336 typedef enum
337 {
338  SCG_SOSC_REF_EXT = 0x0, /* External reference clock requested */
339  SCG_SOSC_REF_OSC = 0x1, /* Internal oscillator of OSC requested. */
341 
346 typedef struct
347 {
348  uint32_t freq;
363  bool locked;
365  bool initialize;
367 
372 typedef enum
373 {
377 
382 typedef struct
383 {
389  bool initialize;
393  bool locked;
395 
400 typedef enum
401 {
407 
412 typedef struct
413 {
421  bool regulator;
422  bool locked;
424  bool initialize;
426 
431 typedef enum
432 {
437 
438 
443 typedef struct
444 {
447  uint8_t prediv;
448  uint8_t mult;
449  uint8_t src;
456  bool locked;
457  bool initialize;
459 
464 typedef struct
465 {
466  uint32_t rtcClkInFreq;
467  bool initialize;
469 
474 typedef struct
475 {
480  bool initialize;
482 
487 typedef struct
488 {
490  bool initialize;
492 
497 typedef struct
498 {
506 } scg_config_t;
507 
511 typedef enum
512 {
513  CLK_SRC_OFF = 0x00U, /* Clock is off */
514  CLK_SRC_SOSC = 0x01U, /* OSCCLK - System Oscillator Bus Clock */
515  CLK_SRC_SIRC = 0x02U, /* SCGIRCLK - Slow IRC Clock */
516  CLK_SRC_FIRC = 0x03U, /* SCGFIRCLK - Fast IRC Clock */
517  CLK_SRC_SPLL = 0x06U /* SCGPCLK System PLL clock */
519 
523 typedef enum
524 {
525  MULTIPLY_BY_ONE = 0x00U, /* Fractional value is zero */
526  MULTIPLY_BY_TWO = 0x01U /* Fractional value is one */
528 
532 typedef enum
533 {
534  DIVIDE_BY_ONE = 0x00U, /* Divide by 1 (pass-through, no clock divide) */
535  DIVIDE_BY_TWO = 0x01U, /* Divide by 2 */
536  DIVIDE_BY_THREE = 0x02U, /* Divide by 3 */
537  DIVIDE_BY_FOUR = 0x03U, /* Divide by 4 */
538  DIVIDE_BY_FIVE = 0x04U, /* Divide by 5 */
539  DIVIDE_BY_SIX = 0x05U, /* Divide by 6 */
540  DIVIDE_BY_SEVEN = 0x06U, /* Divide by 7 */
541  DIVIDE_BY_EIGTH = 0x07U /* Divide by 8 */
543 
547 typedef struct
548 {
549  /* clockName is the name of the peripheral clock
550  * must be one of the following values (see the clock_names_t type from S32K1xx_clock_names.h)
551  * PCC_DMA0_CLOCK
552  * PCC_MPU0_CLOCK
553  * ...
554  * PCC_LPUART3_CLOCK
555  */
557  bool clkGate;
562 
566 typedef struct
567 {
568  uint32_t count;
570 } pcc_config_t;
571 
573 typedef struct
574 {
575  bool initialize;
576  bool enable;
577  int8_t trimValue;
579 
583 typedef struct
584 {
586 } pmc_config_t;
587 
588 
592 typedef enum
593 {
594  DO_NOT_MULTIPLY, /* Do not multiply. */
595  MUL_BY_TWO, /* Multiply by two. */
596 } periph_mul_t;
597 
601 typedef enum
602 {
603  DO_NOT_DIVIDE, /* Do no divide. */
604  DIV_BY_TWO, /* Divide by two. */
605  DIV_BY_THREE, /* Divide by three. */
606  DIV_BY_FOUR, /* Divide by four. */
607  DIV_BY_FIVE, /* Divide by five. */
608  DIV_BY_SIX, /* Divide by six. */
609  DIV_BY_SEVEN, /* Divide by seven. */
610  DIV_BY_EIGTH, /* Divide by eight. */
611 } periph_div_t;
612 
616 typedef enum
617 {
618  DISABLE_CLK, /* Do nu use functional clock. */
619  SIRC_CLK_SRC, /* Use sirc as functional clock */
620  FIRC_CLK_SRC, /* Use firc as functional clock */
621  SOSC_CLK_SRC, /* Use sosc as functional clock */
622  SPLL_CLK_SRC, /* Use spll as functional clock */
624 
625 
629 typedef struct
630 {
635 
636 
641 typedef enum
642 {
647 } sys_clk_src_t;
648 
653 typedef enum
654 {
672 } sys_clk_div_t;
673 
678 typedef struct
679 {
685 
690 typedef enum {
691 
692  NO_MODE = 0U,
693  RUN_MODE = (1U<<0U),
694  VLPR_MODE = (1U<<1U),
695  HSRUN_MODE = (1U<<2U),
696  STOP_MODE = (1U<<3U),
697  VLPS_MODE = (1U<<4U),
698  ALL_MODES = 0x7FFFFFFF
699 
700 } pwr_modes_t;
701 
706 typedef enum
707 {
711 } sirc_range_t;
712 
717 typedef struct
718 {
721 } sirc_config_t;
722 
723 
728 typedef enum
729 {
735 } firc_range_t;
736 
741 typedef struct
742 {
745  bool regulator;
746 } firc_config_t;
747 
748 
753 typedef enum
754 {
759 } sosc_range_t;
760 
765 typedef enum
766 {
767  SOSC_EXT_REF = 0U, /* Internal oscillator is bypassed, external reference clock requested. */
768  SOSC_INT_OSC = 1U, /* Internal oscillator of OSC requested. */
770 } sosc_ref_t;
771 
772 
777 typedef struct
778 {
779  uint32_t freq;
783 } sosc_config_t;
784 
785 
790 typedef enum
791 {
801 
806 typedef enum
807 {
841 
842 typedef struct
843 {
847 } spll_config_t;
848 
849 /*******************************************************************************
850  * API
851  ******************************************************************************/
852 
853 #if defined (__cplusplus)
854 extern "C" {
855 #endif /* __cplusplus*/
856 
867 
876 void CLOCK_SYS_SetPccConfiguration(const pcc_config_t * peripheralClockConfig);
877 
886 void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t * simClockConfig);
887 
896 void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t * pmcConfig);
897 
908  const periph_clk_config_t * periphClkConfig);
909 
918 
929  const sys_clk_config_t * sysClkConfig);
930 
946 status_t CLOCK_DRV_SetSirc(bool enable,
947  const sirc_config_t * sircConfig);
948 
964 status_t CLOCK_DRV_SetFirc(bool enable,
965  const firc_config_t * fircConfig);
966 
982 status_t CLOCK_DRV_SetSosc(bool enable,
983  const sosc_config_t * soscConfig);
984 
1000 status_t CLOCK_DRV_SetSpll(bool enable,
1001  const spll_config_t * spllConfig);
1002 
1009 status_t CLOCK_DRV_SetLpo(bool enable);
1010 
1011 #if defined (__cplusplus)
1012 }
1013 #endif /* __cplusplus*/
1014 
1017 #endif /* CLOCK_S32K1xx_H */
1018 /*******************************************************************************
1019  * EOF
1020  ******************************************************************************/
clock_trace_src_t
Debug trace clock source select Implements clock_trace_src_t_Class.
PCC peripheral instance clock configuration. Implements peripheral_clock_config_t_Class.
sys_clk_src_t src
status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
Configures the system clocks.
SIM LPO Clocks configuration. Implements sim_lpo_clock_config_t_Class.
scg_async_clock_div_t div1
scg_async_clock_div_t div2
pwr_modes_t modes
scg_async_clock_div_t div1
sim_tclk_config_t tclkConfig
SCG ClockOut Configuration structure. Implements scg_clockout_config_t_Class.
sosc_ref_t
OSC reference clock select (internal oscillator is bypassed or not) Implements sosc_ext_ref_t_Class.
scg_async_clock_div_t div2
pwr_modes_t modes
scg_rtc_config_t rtcConfig
pwr_modes_t
Power mode. Implements pwr_modes_t_Class.
pwr_modes_t modes
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
Definition: clock_S32K1xx.c:69
sim_rtc_clk_sel_src_t
SIM CLK32KSEL clock source select Implements sim_rtc_clk_sel_src_t_Class.
Definition: clock_S32K1xx.h:62
sim_clkout_div_t
SIM CLKOUT divider.
sim_clkout_src_t
SIM CLKOUT select.
Definition: clock_S32K1xx.h:85
peripheral_clock_source_t
PCC clock source select Implements peripheral_clock_source_t_Class.
SCG configure structure. Implements scg_config_t_Class.
scg_firc_range_t range
sim_lpoclk_sel_src_t
SIM LPOCLKSEL clock source select Implements sim_lpoclk_sel_src_t_Class.
Definition: clock_S32K1xx.h:74
scg_system_clock_config_t vccrConfig
sys_clk_div_t slow
scg_async_clock_div_t
SCG asynchronous clock divider value.
sirc_range_t range
scg_sirc_range_t range
uint32_t rtcClkInFreq
void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t *pmcConfig)
Configures PMC module.
scg_spll_monitor_mode_t monitorMode
void CLOCK_DRV_EnablePeripheralClock(clock_names_t clockName, const periph_clk_config_t *periphClkConfig)
Enables peripheral clock.
scg_async_clock_div_t div2
peripheral_clock_source_t clkSrc
SIM QSPI reference clock gating. Implements sim_qspi_ref_clk_gating_t_Class.
peripheral instance clock configuration. Implements periph_clk_config_t_Class
SIM configure structure. Implements sim_clock_config_t_Class.
scg_sosc_monitor_mode_t
SCG system OSC monitor mode. Implements scg_sosc_monitor_mode_t_Class.
scg_firc_range_t
SCG fast IRC clock frequency range. Implements scg_firc_range_t_Class.
SCG Clock Mode Configuration structure. Implements scg_clock_mode_config_t_Class. ...
scg_firc_config_t fircConfig
void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t *simClockConfig)
Configures SIM module.
sim_clkout_div_t divider
scg_sosc_config_t soscConfig
scg_sosc_ext_ref_t extRef
spll_clock_mul_t mult
periph_div_t divider
sim_trace_clock_config_t traceClockConfig
periph_div_t
Peripheral divider value Implements periph_div_t_Class.
uint32_t g_RtcClkInFreq
Definition: clock_S32K1xx.c:72
sim_rtc_clk_sel_src_t sourceRtcClk
peripheral_clock_config_t * peripheralClocks
SCG system PLL configuration. Implements scg_spll_config_t_Class.
sys_clk_div_t core
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
sim_plat_gate_config_t platGateConfig
clock_names_t
Clock names.
status_t CLOCK_SYS_SetScgConfiguration(const scg_config_t *scgConfig)
Configures SCG module.
sys_clk_div_t
system clock divider value. Implements sys_clk_div_t_Class
status_t CLOCK_DRV_SetLpo(bool enable)
This function enables or disables LPO clock source.
scg_clockout_config_t clockOutConfig
status_t CLOCK_DRV_SetSpll(bool enable, const spll_config_t *spllConfig)
This function enables or disables SPLL clock source.
peripheral_clock_frac_t
PCC fractional value select Implements peripheral_clock_frac_t_Class.
status_t CLOCK_DRV_SetSirc(bool enable, const sirc_config_t *sircConfig)
This function enables or disables SIRC clock source.
sim_clkout_src_t source
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
periph_clk_src_t
Peripheral clock source value Implements periph_clk_src_t_Class.
scg_spll_config_t spllConfig
scg_clockout_src_t source
pwr_modes_t modes
spll_clock_div_t
SPLL clock divider value. Implements spll_clock_div_t_Class.
scg_clock_mode_config_t clockModeConfig
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
void CLOCK_DRV_DisablePeripheralClock(clock_names_t clockName)
Disables peripheral clock.
scg_sirc_config_t sircConfig
SCG RTC configuration. Implements scg_rtc_config_t_Class.
sosc_range_t
OSC frequency range select Implements sosc_range_t_Class.
scg_sosc_gain_t gain
pmc_lpo_clock_config_t lpoClockConfig
scg_async_clock_div_t div1
spll_clock_div_t prediv
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
scg_sirc_range_t
SCG slow IRC clock frequency range. Implements scg_sirc_range_t_Class.
sosc_range_t range
scg_system_clock_div_t divCore
scg_async_clock_div_t div2
scg_clockout_src_t
SCG ClockOut type. Implements scg_clockout_src_t_Class.
scg_system_clock_div_t divSlow
scg_sosc_range_t
SCG OSC frequency range select Implements scg_sosc_range_t_Class.
sim_clock_out_config_t clockOutConfig
#define NUMBER_OF_TCLK_INPUTS
Definition: clock_S32K1xx.h:49
scg_sosc_gain_t
SCG OSC high gain oscillator select. Implements scg_sosc_gain_t_Class.
scg_async_clock_div_t div1
uint32_t count
sys_clk_src_t
system clock source. Implements sys_clk_src_t_Class
scg_sosc_range_t range
periph_clk_src_t source
SIM Platform Gate Clock configuration. Implements sim_plat_gate_config_t_Class.
sim_qspi_ref_clk_gating_t qspiRefClkGating
scg_sosc_monitor_mode_t monitorMode
SCG slow IRC clock configuration. Implements sirc_config_t_Class.
SIM ClockOut configuration. Implements sim_clock_out_config_t_Class.
peripheral_clock_divider_t divider
void CLOCK_SYS_SetPccConfiguration(const pcc_config_t *peripheralClockConfig)
Configures PCC module.
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
sim_lpo_clock_config_t lpoClockConfig
scg_spll_monitor_mode_t
SCG system PLL monitor mode. Implements scg_spll_monitor_mode_t_Class.
periph_mul_t
Peripheral multiplier value Implements periph_mul_t_Class.
sim_lpoclk_sel_src_t sourceLpoClk
PMC configure structure.
sosc_ref_t ref
uint32_t g_xtal0ClkFreq
Definition: clock_S32K1xx.c:75
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
const uint8_t peripheralFeaturesList[CLOCK_NAME_COUNT]
Peripheral features list Constant array storing the mappings between clock names of the peripherals a...
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
clock_trace_src_t source
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
scg_system_clock_config_t rccrConfig
status_t CLOCK_DRV_SetFirc(bool enable, const firc_config_t *fircConfig)
This function enables or disables FIRC clock source.
scg_system_clock_src_t src
sys_clk_div_t bus
scg_system_clock_src_t alternateClock
firc_range_t
SCG fast IRC clock frequency range. Implements firc_range_t_Class.
status_t CLOCK_DRV_SetSosc(bool enable, const sosc_config_t *soscConfig)
This function enables or disables SOSC clock source.
SIM Platform Gate Clock configuration. Implements sim_tclk_config_t_Class.
peripheral_clock_frac_t frac
PMC LPO configuration.
scg_sosc_ext_ref_t
SCG OSC external reference clock select. Implements scg_sosc_ext_ref_t_Class.
peripheral_clock_divider_t
PCC divider value select Implements peripheral_clock_divider_t_Class.
firc_range_t range
sirc_range_t
Slow IRC clock frequency range. Implements sirc_range_t_Class.
scg_system_clock_config_t hccrConfig
periph_mul_t multiplier
spll_clock_mul_t
SPLL clock multiplier value. Implements spll_clock_mul_t_Class.
scg_system_clock_div_t divBus
SIM Debug Trace clock configuration. Implements sim_trace_clock_config_t_Class.
system clock configuration. Implements sys_clk_config_t_Class
PCC configuration. Implements pcc_config_t_Class.