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S32 SDK
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#define MCM_CPCR_AXBS_HLT_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLT_REQ_SHIFT))&MCM_CPCR_AXBS_HLT_REQ_MASK) |
#define MCM_CPCR_AXBS_HLTD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLTD_SHIFT))&MCM_CPCR_AXBS_HLTD_MASK) |
#define MCM_CPCR_CBRR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_CBRR_SHIFT))&MCM_CPCR_CBRR_MASK) |
#define MCM_CPCR_FMC_PF_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_FMC_PF_IDLE_SHIFT))&MCM_CPCR_FMC_PF_IDLE_MASK) |
#define MCM_CPCR_HLT_FSM_ST | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_HLT_FSM_ST_SHIFT))&MCM_CPCR_HLT_FSM_ST_MASK) |
#define MCM_CPCR_PBRIDGE_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_PBRIDGE_IDLE_SHIFT))&MCM_CPCR_PBRIDGE_IDLE_MASK) |
#define MCM_CPCR_SRAMLAP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLAP_SHIFT))&MCM_CPCR_SRAMLAP_MASK) |
#define MCM_CPCR_SRAMLWP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLWP_SHIFT))&MCM_CPCR_SRAMLWP_MASK) |
#define MCM_CPCR_SRAMUAP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUAP_SHIFT))&MCM_CPCR_SRAMUAP_MASK) |
#define MCM_CPCR_SRAMUWP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUWP_SHIFT))&MCM_CPCR_SRAMUWP_MASK) |
#define MCM_CPO_CPOACK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK) |
#define MCM_CPO_CPOREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK) |
#define MCM_CPO_CPOWOI | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK) |
#define MCM_ISCR_FDZC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK) |
#define MCM_ISCR_FDZCE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK) |
#define MCM_ISCR_FIDC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK) |
#define MCM_ISCR_FIDCE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK) |
#define MCM_ISCR_FIOC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK) |
#define MCM_ISCR_FIOCE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK) |
#define MCM_ISCR_FIXC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK) |
#define MCM_ISCR_FIXCE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK) |
#define MCM_ISCR_FOFC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK) |
#define MCM_ISCR_FOFCE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK) |
#define MCM_ISCR_FUFC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK) |
#define MCM_ISCR_FUFCE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK) |
#define MCM_LMDR2_CF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_CF1_SHIFT))&MCM_LMDR2_CF1_MASK) |
#define MCM_LMDR2_DPW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_DPW_SHIFT))&MCM_LMDR2_DPW_MASK) |
#define MCM_LMDR2_LMSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZ_SHIFT))&MCM_LMDR2_LMSZ_MASK) |
#define MCM_LMDR2_LMSZH | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZH_SHIFT))&MCM_LMDR2_LMSZH_MASK) |
#define MCM_LMDR2_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LOCK_SHIFT))&MCM_LMDR2_LOCK_MASK) |
#define MCM_LMDR2_MT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_MT_SHIFT))&MCM_LMDR2_MT_MASK) |
#define MCM_LMDR2_V | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_V_SHIFT))&MCM_LMDR2_V_MASK) |
#define MCM_LMDR2_WY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_WY_SHIFT))&MCM_LMDR2_WY_MASK) |
#define MCM_LMDR_CF0 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF0_SHIFT))&MCM_LMDR_CF0_MASK) |
#define MCM_LMDR_CF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF1_SHIFT))&MCM_LMDR_CF1_MASK) |
#define MCM_LMDR_DPW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_DPW_SHIFT))&MCM_LMDR_DPW_MASK) |
#define MCM_LMDR_LMSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZ_SHIFT))&MCM_LMDR_LMSZ_MASK) |
#define MCM_LMDR_LMSZH | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZH_SHIFT))&MCM_LMDR_LMSZH_MASK) |
#define MCM_LMDR_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LOCK_SHIFT))&MCM_LMDR_LOCK_MASK) |
#define MCM_LMDR_MT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_MT_SHIFT))&MCM_LMDR_MT_MASK) |
#define MCM_LMDR_V | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_V_SHIFT))&MCM_LMDR_V_MASK) |
#define MCM_LMDR_WY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_WY_SHIFT))&MCM_LMDR_WY_MASK) |
#define MCM_LMFAR_EFADD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFAR_EFADD_SHIFT))&MCM_LMFAR_EFADD_MASK) |
#define MCM_LMFATR_OVR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_OVR_SHIFT))&MCM_LMFATR_OVR_MASK) |
#define MCM_LMFATR_PEFMST | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFMST_SHIFT))&MCM_LMFATR_PEFMST_MASK) |
#define MCM_LMFATR_PEFPRT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFPRT_SHIFT))&MCM_LMFATR_PEFPRT_MASK) |
#define MCM_LMFATR_PEFSIZE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFSIZE_SHIFT))&MCM_LMFATR_PEFSIZE_MASK) |
#define MCM_LMFATR_PEFW | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFW_SHIFT))&MCM_LMFATR_PEFW_MASK) |
#define MCM_LMFDHR_PEFDH | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFDHR_PEFDH_SHIFT))&MCM_LMFDHR_PEFDH_MASK) |
#define MCM_LMFDLR_PEFDL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMFDLR_PEFDL_SHIFT))&MCM_LMFDLR_PEFDL_MASK) |
#define MCM_LMPECR_ECPR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ECPR_SHIFT))&MCM_LMPECR_ECPR_MASK) |
#define MCM_LMPECR_ER1BR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ER1BR_SHIFT))&MCM_LMPECR_ER1BR_MASK) |
#define MCM_LMPECR_ERNCR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ERNCR_SHIFT))&MCM_LMPECR_ERNCR_MASK) |
#define MCM_LMPEIR_E1B | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_E1B_SHIFT))&MCM_LMPEIR_E1B_MASK) |
#define MCM_LMPEIR_ENC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_ENC_SHIFT))&MCM_LMPEIR_ENC_MASK) |
#define MCM_LMPEIR_PE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PE_SHIFT))&MCM_LMPEIR_PE_MASK) |
#define MCM_LMPEIR_PEELOC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PEELOC_SHIFT))&MCM_LMPEIR_PEELOC_MASK) |
#define MCM_LMPEIR_V | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_V_SHIFT))&MCM_LMPEIR_V_MASK) |
#define MCM_PID_PID | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK) |
#define MCM_PLAMC_AMC | ( | x | ) | (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) |
#define MCM_PLASC_ASC | ( | x | ) | (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) |