S32 SDK
system_S32K148.c
Go to the documentation of this file.
1 /*
2 ** ###################################################################
3 ** Processor: S32K148
4 ** Abstract:
5 ** Provides a system configuration function and a global variable that
6 ** contains the system frequency. It configures the device and initializes
7 ** the oscillator (PLL) that is part of the microcontroller device.
8 **
9 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
10 ** Copyright 2016-2017 NXP
11 ** All rights reserved.
12 **
13 ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
14 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
17 ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
22 ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
23 ** THE POSSIBILITY OF SUCH DAMAGE.
24 **
25 ** ###################################################################
26 */
27 
63 #include "device_registers.h"
64 #include "system_S32K148.h"
65 #include "stdbool.h"
66 
67 /* ----------------------------------------------------------------------------
68  -- Core clock
69  ---------------------------------------------------------------------------- */
70 
72 
73 /*FUNCTION**********************************************************************
74  *
75  * Function Name : SystemInit
76  * Description : Typically this function configures the oscillator that is part
77  * of the microcontroller device. For systems with variable clock speed it also
78  * updates the variable SystemCoreClock. SystemInit is called from startup_device file.
79  *
80  * Implements : SystemInit_Activity
81  *END**************************************************************************/
82 void SystemInit(void)
83 {
84 /**************************************************************************/
85  /* FPU ENABLE*/
86 /**************************************************************************/
87 #ifdef ENABLE_FPU
88  /* Enable CP10 and CP11 coprocessors */
90 #ifdef ERRATA_E6940
91  /* Disable lazy context save of floating point state by clearing LSPEN bit
92  * Workaround for errata e6940 */
93  S32_SCB->FPCCR &= ~(S32_SCB_FPCCR_LSPEN_MASK);
94 #endif
95 #endif /* ENABLE_FPU */
96 
97 /**************************************************************************/
98  /* WDOG DISABLE*/
99 /**************************************************************************/
100 
101 #if (DISABLE_WDOG)
102  /* Write of the WDOG unlock key to CNT register, must be done in order to allow any modifications*/
103  WDOG->CNT = (uint32_t ) FEATURE_WDOG_UNLOCK_VALUE;
104  /* The dummy read is used in order to make sure that the WDOG registers will be configured only
105  * after the write of the unlock value was completed. */
106  (void)WDOG->CNT;
107 
108  /* Initial write of WDOG configuration register:
109  * enables support for 32-bit refresh/unlock command write words,
110  * clock select from LPO, update enable, watchdog disabled */
111  WDOG->CS = (uint32_t ) ( (1UL << WDOG_CS_CMD32EN_SHIFT) |
113  (0U << WDOG_CS_EN_SHIFT) |
114  (1U << WDOG_CS_UPDATE_SHIFT) );
115 
116  /* Configure timeout */
117  WDOG->TOVAL = (uint32_t )0xFFFF;
118 #endif /* (DISABLE_WDOG) */
119 
120 /**************************************************************************/
121  /* Power mode protection */
122 /**************************************************************************/
123 #ifdef SYSTEM_SMC_PMPROT_VALUE
124  /* Power mode protection initialization */
125  SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
126 #endif
127 }
128 
129 /*FUNCTION**********************************************************************
130  *
131  * Function Name : SystemCoreClockUpdate
132  * Description : This function must be called whenever the core clock is changed
133  * during program execution. It evaluates the clock register settings and calculates
134  * the current core clock.
135  *
136  * Implements : SystemCoreClockUpdate_Activity
137  *END**************************************************************************/
139 {
140  uint32_t SCGOUTClock = 0U; /* Variable to store output clock frequency of the SCG module */
141  uint32_t regValue; /* Temporary variable */
142  uint32_t divider, prediv, multi;
143  bool validSystemClockSource = true;
144  static const uint32_t fircFreq[] = {
149  };
150 
151  divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U;
152 
153  switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
154  case 0x1:
155  /* System OSC */
156  SCGOUTClock = CPU_XTAL_CLK_HZ;
157  break;
158  case 0x2:
159  /* Slow IRC */
160  regValue = (SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT;
161  SCGOUTClock = (regValue != 0U) ?
163  break;
164  case 0x3:
165  /* Fast IRC */
166  regValue = (SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT;
167  SCGOUTClock= fircFreq[regValue];
168  break;
169  case 0x6:
170  /* System PLL */
171  SCGOUTClock = CPU_XTAL_CLK_HZ;
172  prediv = ((SCG->SPLLCFG & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1U;
173  multi = ((SCG->SPLLCFG & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16U;
174  SCGOUTClock = SCGOUTClock * multi / (prediv * 2U);
175  break;
176  default:
177  validSystemClockSource = false;
178  break;
179  }
180 
181  if (validSystemClockSource == true) {
182  SystemCoreClock = (SCGOUTClock / divider);
183  }
184 }
185 
186 /*FUNCTION**********************************************************************
187  *
188  * Function Name : SystemSoftwareReset
189  * Description : This function is used to software reset the microcontroller.
190  *
191  * Implements : SystemSoftwareReset_Activity
192  *END**************************************************************************/
194 {
195  uint32_t regValue;
196 
197  /* Read Application Interrupt and Reset Control Register */
198  regValue = S32_SCB->AIRCR;
199 
200  /* Clear register key */
201  regValue &= ~( S32_SCB_AIRCR_VECTKEY_MASK);
202 
203  /* Configure System reset request bit and Register Key */
205  regValue |= S32_SCB_AIRCR_SYSRESETREQ(0x1u);
206 
207  /* Write computed register value */
208  S32_SCB->AIRCR = regValue;
209 }
210 
211 /*******************************************************************************
212  * EOF
213  ******************************************************************************/
#define FEATURE_SCB_VECTKEY
#define SMC
Definition: S32K148.h:13290
#define SCG_SPLLCFG_MULT_MASK
Definition: S32K148.h:12838
#define FEATURE_SCG_FIRC_FREQ2
#define FEATURE_SCG_FIRC_FREQ1
#define SCG_FIRCCFG_RANGE_SHIFT
Definition: S32K148.h:12792
#define WDOG_CS_CMD32EN_SHIFT
Definition: S32K148.h:13573
#define WDOG_CS_CLK_SHIFT
Definition: S32K148.h:13557
#define SCG_CSR_SCS_MASK
Definition: S32K148.h:12606
#define FEATURE_WDOG_UNLOCK_VALUE
#define S32_SCB_AIRCR_SYSRESETREQ(x)
Definition: S32K148.h:11558
#define SCG_FIRCCFG_RANGE_MASK
Definition: S32K148.h:12791
#define S32_SCB_CPACR_CP10_MASK
Definition: S32K148.h:11824
#define SCG_CSR_DIVCORE_SHIFT
Definition: S32K148.h:12603
#define SCG_CSR_DIVCORE_MASK
Definition: S32K148.h:12602
#define S32_SCB_AIRCR_VECTKEY(x)
Definition: S32K148.h:11570
#define DEFAULT_SYSTEM_CLOCK
#define S32_SCB
Definition: S32K148.h:11447
#define SCG_CSR_SCS_SHIFT
Definition: S32K148.h:12607
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock variable.
#define FEATURE_SCG_FIRC_FREQ0
#define SCG_SPLLCFG_PREDIV_MASK
Definition: S32K148.h:12834
#define FEATURE_WDOG_CLK_FROM_LPO
#define S32_SCB_FPCCR_LSPEN_MASK
Definition: S32K148.h:11861
#define CPU_XTAL_CLK_HZ
#define SCG
Definition: S32K148.h:12558
#define S32_SCB_AIRCR_VECTKEY_MASK
Definition: S32K148.h:11567
#define SCG_SIRCCFG_RANGE_SHIFT
Definition: S32K148.h:12753
#define SCG_SPLLCFG_MULT_SHIFT
Definition: S32K148.h:12839
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
uint32_t SystemCoreClock
System clock frequency (core clock)
void SystemInit(void)
Setup the microcontroller system.
#define SCG_SPLLCFG_PREDIV_SHIFT
Definition: S32K148.h:12835
#define S32_SCB_CPACR_CP11_MASK
Definition: S32K148.h:11828
#define FEATURE_SCG_FIRC_FREQ3
#define SCG_SIRCCFG_RANGE_MASK
Definition: S32K148.h:12752
#define WDOG_CS_UPDATE_SHIFT
Definition: S32K148.h:13545
#define WDOG_CS_EN_SHIFT
Definition: S32K148.h:13553
#define WDOG
Definition: S32K148.h:13506
void SystemSoftwareReset(void)
Software Resets the microcontroller system.