67 #if defined FEATURE_EDMA_HAS_ERROR_IRQ
85 #ifdef DEV_ERROR_DETECT
109 #ifdef DEV_ERROR_DETECT
115 DEV_ASSERT((edmaState != NULL) && (userConfig != NULL));
120 #ifdef DEV_ERROR_DETECT
136 volatile uint8_t *clearStructPtr = (
volatile uint8_t *)s_edma;
138 while (clearSize > 0U)
145 edmaRegBase = s_edmaBase[0U];
148 EDMA_Init(edmaRegBase);
151 EDMA_SetChannelArbitrationMode(edmaRegBase, userConfig->
chnArbitration);
152 #if (FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U)
153 EDMA_SetGroupArbitrationMode(edmaRegBase, userConfig->groupArbitration);
154 EDMA_SetGroupPriority(edmaRegBase, userConfig->groupPriority);
160 #if defined FEATURE_EDMA_HAS_ERROR_IRQ
165 irqNumber = s_edmaErrIrqId[i];
181 DMAMUX_Init(s_dmamuxBase[i]);
185 if ((chnStateArray != NULL) && (chnConfigArray != NULL))
187 for (i = 0U; i < chnCount; i++)
192 edmaStatus = chnInitStatus;
214 #if defined FEATURE_EDMA_HAS_ERROR_IRQ
219 irqNumber = s_edmaErrIrqId[i];
228 chn = s_edma->
chn[i];
256 DMA_Type * edmaRegBase = s_edmaBase[0U];
260 DEV_ASSERT((edmaChannelState != NULL) && (edmaChannelConfig != NULL));
275 EDMA_SetChannelPriority(edmaRegBase, edmaChannelConfig->
channel, edmaChannelConfig->
priority);
324 DMA_Type * edmaRegBase = s_edmaBase[0U];
325 DMAMUX_Type * dmamuxRegBase = s_dmamuxBase[dmamuxInstance];
331 s_edma->
chn[requestedChannel] = chn;
334 uint8_t *clearStructPtr = (uint8_t *)chn;
336 while (clearSize > 0U)
344 chn->
channel = requestedChannel;
347 EDMA_SetErrorIntCmd(edmaRegBase, requestedChannel,
true);
350 DMAMUX_SetChannelCmd(dmamuxRegBase, dmamuxChannel,
false);
351 DMAMUX_SetChannelSource(dmamuxRegBase, dmamuxChannel, sourceDmamuxChannel);
352 DMAMUX_SetChannelCmd(dmamuxRegBase, dmamuxChannel,
true);
355 EDMA_TCDClearReg(edmaRegBase, requestedChannel);
380 DMA_Type * edmaRegBase = s_edmaBase[0U];
383 EDMA_SetDmaRequestCmd(edmaRegBase, channel,
false);
386 uint8_t *clearStructPtr = (uint8_t *)chnState;
388 while (clearSize > 0U)
395 s_edma->
chn[channel] = NULL;
408 DMA_Type * edmaRegBase = s_edmaBase[0U];
409 EDMA_ClearDoneStatusFlag(edmaRegBase, channel);
410 EDMA_ClearIntStatusFlag(edmaRegBase, channel);
421 uint8_t *byteAccess = (uint8_t *)stcd;
422 size_t clearSize =
sizeof(edma_software_tcd_t);
423 while (clearSize > 0U)
458 uint8_t channel = 0U;
460 DMA_Type * edmaRegBase = s_edmaBase[0U];
463 error = EDMA_GetErrorIntStatusFlag(edmaRegBase);
469 EDMA_SetDmaRequestCmd(edmaRegBase, channel,
false);
470 chn = s_edma->
chn[channel];
474 EDMA_ClearErrorIntStatusFlag(edmaRegBase, channel);
485 EDMA_SetHaltCmd(edmaRegBase,
false);
496 uint32_t srcAddr, uint32_t destAddr,
508 #ifdef DEV_ERROR_DETECT
510 DEV_ASSERT(EDMA_DRV_ValidTransferSize(transferSize));
513 DMA_Type * edmaRegBase = s_edmaBase[0U];
514 uint8_t transferOffset;
523 transferOffset = (uint8_t) (1U << ((uint8_t)transferSize));
528 if ((dataBufferSize % transferOffset) != 0U)
536 EDMA_TCDClearReg(edmaRegBase, channel);
539 EDMA_TCDSetSrcAddr(edmaRegBase, channel, srcAddr);
540 EDMA_TCDSetDestAddr(edmaRegBase, channel, destAddr);
549 EDMA_TCDSetSrcOffset(edmaRegBase, channel, 0);
550 EDMA_TCDSetDestOffset(edmaRegBase, channel, (int8_t) transferOffset);
553 EDMA_TCDSetSrcOffset(edmaRegBase, channel, (int8_t) transferOffset);
554 EDMA_TCDSetDestOffset(edmaRegBase, channel, 0);
557 EDMA_TCDSetSrcOffset(edmaRegBase, channel, (int8_t) transferOffset);
558 EDMA_TCDSetDestOffset(edmaRegBase, channel, (int8_t) transferOffset);
561 EDMA_TCDSetSrcOffset(edmaRegBase, channel, 0);
562 EDMA_TCDSetDestOffset(edmaRegBase, channel, 0);
570 EDMA_TCDSetNbytes(edmaRegBase, channel, dataBufferSize);
573 EDMA_TCDSetMajorCount(edmaRegBase, channel, 1U);
576 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, channel,
true);
590 uint32_t srcAddr, uint32_t destAddr,
592 uint32_t blockCount,
bool disableReqOnCompletion)
601 DMA_Type * edmaRegBase = s_edmaBase[0U];
604 EDMA_TCDSetMajorCount(edmaRegBase, channel, blockCount);
607 EDMA_TCDSetDisableDmaRequestAfterTCDDoneCmd(edmaRegBase, channel, disableReqOnCompletion);
637 DMA_Type * edmaRegBase = s_edmaBase[0U];
638 EDMA_SetMinorLoopMappingCmd(edmaRegBase,
true);
644 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, channel,
true);
671 DEV_ASSERT((stcd != NULL) && (srcList != NULL) && (destList != NULL));
673 #ifdef DEV_ERROR_DETECT
675 DEV_ASSERT(EDMA_DRV_ValidTransferSize(transferSize));
679 uint16_t transferOffset;
680 uint32_t stcdAlignedAddr =
STCD_ADDR(stcd);
681 edma_software_tcd_t *stcdAddr = (edma_software_tcd_t *)stcdAlignedAddr;
692 transferOffset = (uint16_t) (1UL << ((uint16_t)transferSize));
697 if ((bytesOnEachRequest % transferOffset) != 0U)
703 uint8_t *clearStructPtr = (uint8_t *)(&config);
705 while (clearSize > 0U)
712 clearStructPtr = (uint8_t *)(&loopConfig);
714 while (clearSize > 0U)
742 if ((srcList[i].length != destList[i].length) || (srcList[i].
type != destList[i].
type))
749 switch (srcList[i].type)
759 config.
srcOffset = (int16_t) transferOffset;
765 config.
srcOffset = (int16_t) transferOffset;
781 if (i == ((uint8_t)(tcdCount - 1U)))
787 edma_software_tcd_t *nextAddr = &stcdAddr[i];
825 DMA_Type * edmaRegBase = s_edmaBase[0U];
826 EDMA_SetDmaRequestCmd(edmaRegBase, channel,
true);
850 DMA_Type * edmaRegBase = s_edmaBase[0U];
851 EDMA_SetDmaRequestCmd(edmaRegBase, channel,
false);
876 DMAMUX_SetChannelSource(dmamuxRegBase, channel, req);
900 DMA_Type * edmaRegBase = s_edmaBase[0U];
901 EDMA_TCDClearReg(edmaRegBase, channel);
923 DMA_Type * edmaRegBase = s_edmaBase[0U];
924 EDMA_TCDSetSrcAddr(edmaRegBase, channel, address);
946 DMA_Type * edmaRegBase = s_edmaBase[0U];
947 EDMA_TCDSetSrcOffset(edmaRegBase, channel, offset);
969 DMA_Type * edmaRegBase = s_edmaBase[0U];
970 EDMA_TCDSetSrcTransferSize(edmaRegBase, channel, size);
992 DMA_Type * edmaRegBase = s_edmaBase[0U];
993 EDMA_TCDSetSrcLastAdjust(edmaRegBase, channel, adjust);
1015 DMA_Type * edmaRegBase = s_edmaBase[0U];
1016 EDMA_TCDSetDestLastAdjust(edmaRegBase, channel, adjust);
1038 DMA_Type * edmaRegBase = s_edmaBase[0U];
1039 EDMA_TCDSetDestAddr(edmaRegBase, channel, address);
1061 DMA_Type * edmaRegBase = s_edmaBase[0U];
1062 EDMA_TCDSetDestOffset(edmaRegBase, channel, offset);
1084 DMA_Type * edmaRegBase = s_edmaBase[0U];
1085 EDMA_TCDSetDestTransferSize(edmaRegBase, channel, size);
1107 DMA_Type * edmaRegBase = s_edmaBase[0U];
1108 EDMA_TCDSetNbytes(edmaRegBase, channel, nbytes);
1130 DMA_Type * edmaRegBase = s_edmaBase[0U];
1131 EDMA_TCDSetMajorCount(edmaRegBase, channel, majorLoopCount);
1155 const DMA_Type * edmaRegBase = s_edmaBase[0U];
1156 count = EDMA_TCDGetCurrentMajorCount(edmaRegBase, channel);
1180 DMA_Type * edmaRegBase = s_edmaBase[0U];
1181 EDMA_TCDSetScatterGatherLink(edmaRegBase, channel, nextTCDAddr);
1203 DMA_Type * edmaRegBase = s_edmaBase[0U];
1204 EDMA_TCDSetDisableDmaRequestAfterTCDDoneCmd(edmaRegBase, channel, disable);
1226 DMA_Type * edmaRegBase = s_edmaBase[0U];
1231 EDMA_SetErrorIntCmd(edmaRegBase, channel, enable);
1235 EDMA_TCDSetMajorHalfCompleteIntCmd(edmaRegBase, channel, enable);
1239 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, channel, enable);
1260 DMA_Type * edmaRegBase = s_edmaBase[0U];
1264 EDMA_CancelTransferWithError(edmaRegBase);
1268 EDMA_CancelTransfer(edmaRegBase);
1291 DMA_Type * edmaRegBase = s_edmaBase[0U];
1292 EDMA_TriggerChannelStart(edmaRegBase, channel);
1304 if ((config != NULL) && (stcd != NULL))
1312 stcd->SADDR = config->
srcAddr;
1354 DMA_Type * edmaRegBase = s_edmaBase[0U];
1356 EDMA_TCDClearReg(edmaRegBase, channel);
1359 EDMA_TCDSetSrcAddr(edmaRegBase, channel, tcd->
srcAddr);
1360 EDMA_TCDSetDestAddr(edmaRegBase, channel, tcd->
destAddr);
1368 EDMA_TCDSetSrcOffset(edmaRegBase, channel, tcd->
srcOffset);
1369 EDMA_TCDSetDestOffset(edmaRegBase, channel, tcd->
destOffset);
1373 EDMA_TCDSetScatterGatherCmd(edmaRegBase, channel,
true);
1378 EDMA_TCDSetScatterGatherCmd(edmaRegBase, channel,
false);
1383 EDMA_TCDSetMajorCompleteIntCmd(edmaRegBase, channel, tcd->
interruptEnable);
1406 #ifdef DEV_ERROR_DETECT
void EDMA_DRV_PushConfigToSTCD(const edma_transfer_config_t *config, edma_software_tcd_t *stcd)
Copies the channel configuration to the software TCD structure.
edma_chn_state_t *volatile chn[FEATURE_EDMA_MODULE_CHANNELS]
void EDMA_DRV_SetDestLastAddrAdjustment(uint8_t channel, int32_t adjust)
Configures the destination address last adjustment.
uint32_t minorByteTransferCount
#define DMAMUX_INSTANCE_COUNT
#define DMA_INSTANCE_COUNT
void EDMA_DRV_SetSrcReadChunkSize(uint8_t channel, edma_transfer_size_t size)
Configures the source data chunk size (transferred in a read sequence).
static status_t EDMA_DRV_RequestChannel(uint8_t requestedChannel, dma_request_source_t source, edma_chn_state_t *chn)
uint32_t EDMA_DRV_GetRemainingMajorIterationsCount(uint8_t channel)
Returns the remaining major loop iteration count.
uint8_t minorLoopChnLinkNumber
The user configuration structure for the eDMA driver.
edma_transfer_type_t
A type for the DMA transfer. Implements : edma_transfer_type_t_Class.
The user configuration structure for the an eDMA driver channel.
status_t EDMA_DRV_ReleaseChannel(uint8_t channel)
Releases an eDMA channel.
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
uint8_t majorLoopChnLinkNumber
void EDMA_DRV_SetDestOffset(uint8_t channel, int16_t offset)
Configures the destination address signed offset for the eDMA channel.
status_t EDMA_DRV_Deinit(void)
De-initializes the eDMA module.
status_t EDMA_DRV_Init(edma_state_t *edmaState, const edma_user_config_t *userConfig, edma_chn_state_t *const chnStateArray[], const edma_channel_config_t *const chnConfigArray[], uint8_t chnCount)
Initializes the eDMA module.
edma_channel_priority_t priority
void EDMA_DRV_IRQHandler(uint8_t channel)
eDMA channel interrupt handler, implemented in driver c file.
void EDMA_DRV_SetMinorLoopBlockSize(uint8_t channel, uint32_t nbytes)
Configures the number of bytes to be transferred in each service request of the channel.
status_t EDMA_DRV_SetChannelRequest(uint8_t channel, uint8_t req)
Configures the DMA request for the eDMA channel.
#define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x)
dma_request_source_t
Structure for the DMA hardware request.
void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t channel, int32_t adjust)
Configures the source address last adjustment.
void EDMA_DRV_SetScatterGatherLink(uint8_t channel, uint32_t nextTCDAddr)
Configures the memory address of the next TCD, in scatter/gather mode.
edma_channel_interrupt_t
eDMA channel interrupts. Implements : edma_channel_interrupt_t_Class
uint32_t scatterGatherNextDescAddr
status_t EDMA_DRV_ConfigLoopTransfer(uint8_t channel, const edma_transfer_config_t *transferConfig)
Configures the DMA transfer in loop mode.
#define STCD_ADDR(address)
status_t EDMA_DRV_ChannelInit(edma_chn_state_t *edmaChannelState, const edma_channel_config_t *edmaChannelConfig)
Initializes an eDMA channel.
void EDMA_DRV_ErrorIRQHandler(void)
Runtime state structure for the eDMA driver.
edma_chn_status_t
Channel status for eDMA channel.
clock_names_t
Clock names.
edma_transfer_size_t destTransferSize
#define DMA_TCD_ATTR_DMOD_SHIFT
bool majorLoopChnLinkEnable
int32_t srcLastAddrAdjust
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
#define DMA_TCD_CSR_ESG_SHIFT
void EDMA_DRV_PushConfigToReg(uint8_t channel, const edma_transfer_config_t *tcd)
Copies the channel configuration to the TCD registers.
void EDMA_DRV_SetSrcAddr(uint8_t channel, uint32_t address)
Configures the source address for the eDMA channel.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
static edma_state_t * s_edma
EDMA global structure to maintain eDMA state.
edma_arbitration_algorithm_t chnArbitration
uint32_t majorLoopIterationCount
#define FEATURE_ERROR_INTERRUPT_LINES
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
static void EDMA_DRV_ClearIntStatus(uint8_t channel)
status_t EDMA_DRV_ConfigScatterGatherTransfer(uint8_t channel, edma_software_tcd_t *stcd, edma_transfer_size_t transferSize, uint32_t bytesOnEachRequest, const edma_scatter_gather_list_t *srcList, const edma_scatter_gather_list_t *destList, uint8_t tcdCount)
Configures the DMA transfer in a scatter-gather mode.
#define FEATURE_CHANNEL_INTERRUPT_LINES
#define DMA_TCD_ATTR_SMOD_SHIFT
#define EDMA_ERR_LSB_MASK
Macro for accessing the least significant bit of the ERR register.
edma_transfer_size_t srcTransferSize
Data structure for configuring a discrete memory transfer. Implements : edma_scatter_gather_list_t_Cl...
void EDMA_DRV_SetMajorLoopIterationCount(uint8_t channel, uint32_t majorLoopCount)
Configures the number of major loop iterations.
volatile edma_chn_status_t status
void EDMA_DRV_SetDestAddr(uint8_t channel, uint32_t address)
Configures the destination address for the eDMA channel.
edma_chn_status_t EDMA_DRV_GetChannelStatus(uint8_t channel)
Gets the eDMA channel status.
edma_transfer_type_t type
void EDMA_DRV_SetDestWriteChunkSize(uint8_t channel, edma_transfer_size_t size)
Configures the destination data chunk size (transferred in a write sequence).
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
static const IRQn_Type s_edmaIrqId[FEATURE_CHANNEL_INTERRUPT_LINES]
Array of default DMA channel interrupt handlers.
void EDMA_DRV_SetSrcOffset(uint8_t channel, int16_t offset)
Configures the source address signed offset for the eDMA channel.
void EDMA_DRV_TriggerSwRequest(uint8_t channel)
Triggers a sw request for the current channel.
void EDMA_DRV_ClearTCD(uint8_t channel)
Clears all registers to 0 for the channel's TCD.
int32_t destLastAddrAdjust
#define DMAMUX_CLOCK_NAMES
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
#define DMA_TCD_CSR_INTMAJOR_SHIFT
static DMAMUX_Type *const s_dmamuxBase[DMAMUX_INSTANCE_COUNT]
Array of base addresses for DMAMUX instances.
#define DMA_TCD_ATTR_SSIZE_SHIFT
void EDMA_DRV_CancelTransfer(bool error)
Cancel the running transfer.
static const clock_names_t s_dmamuxClockNames[DMAMUX_INSTANCE_COUNT]
bool minorLoopChnLinkEnable
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
dma_request_source_t source
status_t EDMA_DRV_ConfigSingleBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t dataBufferSize)
Configures a simple single block data transfer with DMA.
static void EDMA_DRV_ClearSoftwareTCD(edma_software_tcd_t *stcd)
eDMA loop transfer configuration.
static const clock_names_t s_edmaClockNames[DMA_INSTANCE_COUNT]
Array of default DMA error interrupt handlers.
#define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x)
void EDMA_DRV_ConfigureInterrupt(uint8_t channel, edma_channel_interrupt_t intSrc, bool enable)
Disables/Enables the channel interrupt requests.
eDMA transfer size configuration.
edma_loop_transfer_config_t * loopTransferConfig
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
static DMA_Type *const s_edmaBase[DMA_INSTANCE_COUNT]
Array of base addresses for DMA instances.
#define FEATURE_EDMA_MODULE_CHANNELS
#define DMA_TCD_ATTR_DSIZE_SHIFT
#define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x)
IRQn_Type
Defines the Interrupt Numbers definitions.
Data structure for the eDMA channel state. Implements : edma_chn_state_t_Class.