User manual
 

Processor Expert Priority System

Some CPUs support selectable interrupts priorities. The user may select a priority for each interrupt vector. The interrupt with a higher priority number can interrupt a service routine with the lower one.

Processor Expert supports the following settings in design-time: interrupt priority and priority of the event code.
Priority can also be changed in the user code. The user may use a CPU component method to adjust the priority to a requested value.

Interrupt Priority

The user may select interrupt priority in the component properties, just below the interrupt vector name. Processor Expert offers the following values, which are supported for all microcontrollers:

  • minimum priority
  • low priority
  • medium priority
  • high priority
  • maximum priority

The selected value is automatically mapped to the priority supported by the target microcontroller. It is indicated in the third column of the Component Inspector.
The user may also select a target-specific numeric value (such as priority 255), if portability of the application to another architecture is not required.
Peripheral Initialization components on some platforms also allow to set the value default that means that the user doesn't have any requirement on it so the priority value will be the default after-reset value.

Version specific information for HCS08 derivatives with IPC (Interrupt Priority Controller)

The HCS08 derivatives with IPC module offer an interrupt priority configuration. There are four interrupt priority levels 0 to 3 available, where 0 is the lowest priority and 3 is the highest one.
The platform-independent interrupt priority values in Processor Expert described on top of this section are mapped to these values.

Version specific information for RS08 without interrupt support and HC(S)08 derivatives without IPC (Interrupt Priority Controller)

These derivatives do not support interrupt priorities. The interrupt priority settings, for example imported from a project for another CPU, are ignored.

Version specific information for RS08 with interrupt support

On these RS08 derivatives, the interrupts are handled through single interrupt vector. The priority of each individual "emulated interrupt" is determined by order in which the SIPx registers are polled in the sofware handler. The priority can be in the range 0 ..number_of_interrupts-1 (e.g. 0 .. 15). The lower is the number the higher is the priority. The platform independent interrupt priority values in Processor Expert described on top of this section are mapped to these values.
The default priority depends on the position of an associated bit in a SIPx register. The interrupt priority can be changed to any value within the allowed range. Interrupts with lower priority number (higher priority of execution) are polled first. If two interrupts have assigned the same priority number then the order in which they are polled depends on the default priority. For more details on interrupts on RS08 please see the chapter Version Specific Information for RS08.

Version specific information for ColdFire V1 derivatives

On the ColdFire V1 platform, an interrupt priority of an interrupt is determined by an Interrupt Level (1-7) and a Priority within Level (0-7). Please see the CPU data sheet for interrupt priority system details.

The applied interrupt priority value (the value displayed in the third column of the Component Inspector) contains both values - e.g. Level 4, priority within level 6. The target-independent values of interrupt priority (e.g. minimum, maximum etc...) are mapped either to the default priority of the selected interrupt or to Level 6, Priority within level 6 or level 6, Priority within level 7.

Priority of Event Code

Version specific information for Kinetis and ColdFire+ derivatives
Priority of event code is not supported for Kinetis and ColdFire+.

The user can also select a priority for the processing of the event code. This setting is available for the events that are invoked from the Interrupt Service Routines. This priority may be different from the interrupt priority. However, the meaning of the number is the same - the event may be interrupted only by the interrupts with the higher priority. Processor Expert offers the following architecture independent values:

  • same as interrupt - default value which means that Processor Expert doesn't generate any code affecting the priority of the event - the priority is in the state determined by the default hardware behavior.
  • minimum priority
  • low priority
  • medium priority
  • high priority
  • maximum priority
  • interrupts disabled - For example the highest priority supported by the microcontroller, which may be interrupted only by non-maskable interrupts.

The selected value is automatically mapped to the priority supported by the target microcontroller and the selected value is displayed in the third column of the Component Inspector.
Please see version specific information below. The user may also select a target-specific value, if portability of the application to another architecture is not required.

Note: Some events do not support priorities, because their invocation is not caused by the interrupt processing.

Warning: Please note that Processor Expert does not allow the user decrease an event code priority (with the exception of 'Interrupts enabled' value on some platforms, please see below). This is because Processor Expert event routines are not generally reentrant so there is a risk that the interrupt would be able to interrupt itself during the processing. If there is such functionality requested, the user has to do it manually (e.g. by calling a appropriate CPU component method setting a priority) and carefully check possible problems.

Version specific information for HCS08 derivatives with IPC (Interrupt Priority Controller)

Processor Expert offers the following event priority options:

  • interrupts enabled - Interrupts are enabled and the priority of the event routine stays at the same level as the interrupt. The interrupts with the higher priority than the current interrupt priority can interrupt the event code.
  • interrupts disabled - All maskable interrupts are disabled.
  • 1..3 - Priorities from lowest (1) to highest (3). The code generated by Processor Expert before the event invocation sets the event code priority to the specified value.
  • 4 - Same as 'interrupts disabled'
  • same as interrupt - Default behavior of the architecture - no interrupts can interrupt the event. It is same as interrupts disabled.
  • Other values are mapped to the priorities 1..4.
Version specific information for HC(S)08 derivatives without IPC (Interrupt Priority Controller)

Processor Expert offers the following event priority options:

  • interrupts disabled - All maskable interrupts are disabled.
  • interrupts enabled - All maskable interrupts are enabled. Please note that this settings might lead to possible problems, see the warning within this chapter.
  • same as interrupt - Default behavior of the architecture - no interrupts can interrupt the event. It is same as "interrupts disabled".
Version specific information for RS08 with interrupt support

Because of architecture limitations, the Processor Expert allows only interrupts disabled value so the interrupt is always disabled within the event routines. The same as interrupt value is mapped to interrupts disabled.

Version specific information for ColdFire V1 derivatives

Processor Expert offers the following event priority options:

  • interrupts disabled - All maskable interrupts are disabled within the event routine.
  • 0..7 - Priorities from the lowest (0) to the highest (7). The code generated by Processor Expert before the event invocation sets interrupt priority mask to the specified value. The event routine may be then interrupted only by an interrupt with higher priority than the specified number.
  • same as interrupt - The priority of the event routine stays on the level set for the interrupt. The event routine can be interrupted only by a higher priority interrupt then the value set for the interrupt.

Version specific information for 56800 derivatives

Processor Expert offers the following event priority options:

  • interrupts enabled - Interrupts are enabled so the event routine can be interrupted by another interrupt. Please note that this settings might lead to possible problems, see the warning within this chapter.
  • interrupts disabled - All maskable interrupts are disabled.
  • same as interrupt - Default behavior of the architecture within interrupts service routines - interrupts are disabled.
Version specific information for 56800E derivatives

Processor Expert offers the following event priority options:

  • interrupts disabled - All maskable interrupts are disabled within the event routine.
  • 1..3 - Priorities from the lowest (1) to the highest (3). The code generated by Processor Expert before the event invocation sets the event code priority to the specified value. The event routine can be interrupted only by a higher priority interrupt than the specified number.
  • same as interrupt - The priority of the event routine stays on the level set for the interrupt. The event routine can be interrupted only by a higher priority interrupt then the value set for the interrupt.
  • Other values are mapped to the priorities 1..3.