57 #if !defined(S32K142_FEATURES_H)
58 #define S32K142_FEATURES_H
90 #define FEATURE_PINS_DRIVER_USING_PORT (1)
92 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
94 #define FEATURE_PINS_HAS_OPEN_DRAIN (0)
96 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
98 #define FEATURE_PORT_HAS_DMA_REQUEST (1)
100 #define FEATURE_PINS_HAS_PULL_SELECTION (1)
102 #define FEATURE_PINS_HAS_SLEW_RATE (0)
104 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
106 #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
108 #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
113 #define FEATURE_SOC_PORT_COUNT (5)
115 #define FEATURE_SOC_SCG_COUNT (1)
117 #define FEATURE_SCG_SIRC_LOW_RANGE_FREQ (2000000U)
119 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
122 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
124 #define FEATURE_SCG_FIRC_FREQ1 (52000000U)
126 #define FEATURE_SCG_FIRC_FREQ2 (56000000U)
128 #define FEATURE_SCG_FIRC_FREQ3 (60000000U)
133 #define FEATURE_FLS_IS_FTFA (0u)
135 #define FEATURE_FLS_IS_FTFC (1u)
137 #define FEATURE_FLS_IS_FTFE (0u)
139 #define FEATURE_FLS_IS_FTFL (0u)
141 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
143 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
145 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
147 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
149 #define FEATURE_FLS_PF_BLOCK_COUNT (1u)
151 #define FEATURE_FLS_PF_BLOCK_SIZE (262144u)
153 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (2048u)
155 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
157 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
159 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
161 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
163 #define FEATURE_FLS_DF_BLOCK_SIZE (65536u)
165 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u)
167 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
169 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
171 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
173 #define FEATURE_FLS_FLEX_RAM_SIZE (4096u)
175 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
177 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
179 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
181 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
183 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
185 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
187 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
189 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
191 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
193 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
195 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
197 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
199 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
201 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
203 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
205 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
207 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
209 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
211 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
213 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
215 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
217 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
219 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
221 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
223 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
225 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
227 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
229 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
231 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
233 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
235 #define FEATURE_FLS_DF_SIZE_0000 (0x00010000u)
237 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
239 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
241 #define FEATURE_FLS_DF_SIZE_0011 (0x00008000u)
243 #define FEATURE_FLS_DF_SIZE_0100 (0x00000000u)
245 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
247 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
249 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
251 #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u)
253 #define FEATURE_FLS_DF_SIZE_1001 (0xFFFFFFFFu)
255 #define FEATURE_FLS_DF_SIZE_1010 (0x00004000u)
257 #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u)
259 #define FEATURE_FLS_DF_SIZE_1100 (0x00010000u)
261 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
263 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
265 #define FEATURE_FLS_DF_SIZE_1111 (0x00010000u)
267 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
269 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
271 #define FEATURE_FLS_EE_SIZE_0010 (0x1000u)
273 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
275 #define FEATURE_FLS_EE_SIZE_0100 (0x0400u)
277 #define FEATURE_FLS_EE_SIZE_0101 (0x0200u)
279 #define FEATURE_FLS_EE_SIZE_0110 (0x0100u)
281 #define FEATURE_FLS_EE_SIZE_0111 (0x0080u)
283 #define FEATURE_FLS_EE_SIZE_1000 (0x0040u)
285 #define FEATURE_FLS_EE_SIZE_1001 (0x0020u)
287 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
289 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
291 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
293 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
295 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
297 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
302 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
304 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
306 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
308 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
310 #define FEATURE_LPUART_FIFO_SIZE (4U)
312 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
314 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
316 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
318 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
320 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
322 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
324 #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK}
329 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
331 #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
332 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
333 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2
334 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3
339 #define LPI2C_DMA_INSTANCE 0U
342 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
344 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
347 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
348 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
349 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
354 #define FEATURE_PDB_ADC_CHANNEL_COUNT (2U)
356 #define FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (8U)
358 #define FEATURE_PDB_PODLY_COUNT (1U)
362 #define FEATURE_SCB_VECTKEY (0x05FAU)
368 #define FEATURE_SMC_HAS_STOPO (1)
370 #define FEATURE_SMC_HAS_PSTOPO (0)
372 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
374 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
380 #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
382 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
384 #define FEATURE_MPU_MASTER_COUNT (3U)
388 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
392 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
398 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
402 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
405 #define FEATURE_MPU_MASTER_CORE (0U)
407 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
409 #define FEATURE_MPU_MASTER_DMA (2U)
411 #define FEATURE_MPU_MASTER \
413 FEATURE_MPU_MASTER_CORE, \
414 FEATURE_MPU_MASTER_DEBUGGER, \
415 FEATURE_MPU_MASTER_DMA, \
419 #define FEATURE_MPU_SLAVE_COUNT (4U)
421 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
423 #define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U)
425 #define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U)
427 #define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U)
429 #define FEATURE_MPU_SLAVE_MASK (0xF0000000U)
430 #define FEATURE_MPU_SLAVE_SHIFT (28u)
431 #define FEATURE_MPU_SLAVE_WIDTH (4u)
432 #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
438 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
440 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
442 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
444 #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
446 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
448 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
450 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
452 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
454 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
456 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
458 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
463 #define FEATURE_FTM_CHANNEL_COUNT (8U)
465 #define FTM_FEATURE_FAULT_CHANNELS (4U)
467 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
469 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
471 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
473 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
475 #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U)
480 #define FEATURE_CRC_DRIVER_S32K1xx (1)
482 #define CRC_DEFAULT_WIDTH CRC_BITS_16
484 #define CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
486 #define CRC_DEFAULT_POLYNOMIAL (0x1021U)
491 #define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U)
493 #define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU)
495 #define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU)
497 #define FEATURE_EWM_CMPL_MIN_VALUE (0x00U)
586 #define PCC_INVALID_INDEX 0
593 #define PCC_CLOCK_NAME_MAPPINGS \
647 PCC_FlexCAN0_INDEX, \
648 PCC_FlexCAN1_INDEX, \
676 #define NO_PERIPHERAL_FEATURE (0U)
677 #define HAS_CLOCK_GATING_IN_SIM (1U << 0U)
678 #define HAS_MULTIPLIER (1U << 1U)
679 #define HAS_DIVIDER (1U << 2U)
680 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U)
681 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U)
682 #define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U)
683 #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U)
684 #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U)
690 #define PERIPHERAL_FEATURES \
692 (NO_PERIPHERAL_FEATURE), \
693 (NO_PERIPHERAL_FEATURE), \
694 (NO_PERIPHERAL_FEATURE), \
695 (NO_PERIPHERAL_FEATURE), \
696 (NO_PERIPHERAL_FEATURE), \
697 (NO_PERIPHERAL_FEATURE), \
698 (NO_PERIPHERAL_FEATURE), \
699 (NO_PERIPHERAL_FEATURE), \
700 (NO_PERIPHERAL_FEATURE), \
701 (NO_PERIPHERAL_FEATURE), \
702 (NO_PERIPHERAL_FEATURE), \
703 (NO_PERIPHERAL_FEATURE), \
704 (NO_PERIPHERAL_FEATURE), \
705 (NO_PERIPHERAL_FEATURE), \
706 (NO_PERIPHERAL_FEATURE), \
707 (NO_PERIPHERAL_FEATURE), \
708 (NO_PERIPHERAL_FEATURE), \
709 (NO_PERIPHERAL_FEATURE), \
710 (NO_PERIPHERAL_FEATURE), \
711 (NO_PERIPHERAL_FEATURE), \
712 (NO_PERIPHERAL_FEATURE), \
713 (NO_PERIPHERAL_FEATURE), \
714 (NO_PERIPHERAL_FEATURE), \
715 (NO_PERIPHERAL_FEATURE), \
716 (NO_PERIPHERAL_FEATURE), \
717 (NO_PERIPHERAL_FEATURE), \
718 (NO_PERIPHERAL_FEATURE), \
719 (NO_PERIPHERAL_FEATURE), \
720 (NO_PERIPHERAL_FEATURE), \
721 (NO_PERIPHERAL_FEATURE), \
722 (NO_PERIPHERAL_FEATURE), \
723 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
724 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
725 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
726 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
727 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
728 (NO_PERIPHERAL_FEATURE), \
729 (NO_PERIPHERAL_FEATURE), \
730 (NO_PERIPHERAL_FEATURE), \
731 (NO_PERIPHERAL_FEATURE), \
732 (NO_PERIPHERAL_FEATURE), \
733 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
734 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
735 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
736 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
737 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
738 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
739 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
740 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
741 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
742 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
743 (NO_PERIPHERAL_FEATURE), \
744 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
745 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
746 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
747 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
748 (NO_PERIPHERAL_FEATURE), \
749 (HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
750 (NO_PERIPHERAL_FEATURE), \
751 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
752 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
753 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
754 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
755 (NO_PERIPHERAL_FEATURE), \
756 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
757 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
758 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
759 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
760 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
761 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
762 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
763 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
764 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
765 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
766 (NO_PERIPHERAL_FEATURE), \
767 (NO_PERIPHERAL_FEATURE), \
773 #define SIRC_STABILIZATION_TIMEOUT 26U;
777 #define FIRC_STABILIZATION_TIMEOUT 10U;
781 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
785 #define SPLL_STABILIZATION_TIMEOUT 1000U;
797 #define MAX_FREQ_VLPR 0U
798 #define MAX_FREQ_RUN 1U
799 #define MAX_FREQ_HSRUN 2U
801 #define MAX_FREQ_SYS_CLK 0U
802 #define MAX_FREQ_BUS_CLK 1U
803 #define MAX_FREQ_SLOW_CLK 2U
805 #define MAX_FREQ_MODES_NO 3U
806 #define MAX_FREQ_CLK_NO 3U
808 #define CLOCK_MAX_FREQUENCIES \
810 { 4000000, 4000000, 1000000}, \
811 { 80000000,40000000,26670000}, \
812 {112000000,56000000,28000000}, \
826 #define TMP_SIRC_CLK 0U
827 #define TMP_FIRC_CLK 1U
828 #define TMP_SOSC_CLK 2U
829 #define TMP_SPLL_CLK 3U
831 #define TMP_SYS_DIV 0U
832 #define TMP_BUS_DIV 1U
833 #define TMP_SLOW_DIV 2U
835 #define TMP_SYS_CLK_NO 4U
836 #define TMP_SYS_DIV_NO 3U
838 #define TMP_SYSTEM_CLOCK_CONFIGS \
840 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1}, \
841 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
842 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
843 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
854 #if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS)
855 #define CORE_CLOCK CORE_CLK
856 #define BUS_CLOCK BUS_CLK
857 #define SLOW_CLOCK SLOW_CLK
858 #define CLKOUT_CLOCK CLKOUT_CLK
859 #define SIRC_CLOCK SIRC_CLK
860 #define FIRC_CLOCK FIRC_CLK
861 #define SOSC_CLOCK SOSC_CLK
862 #define SPLL_CLOCK SPLL_CLK
863 #define RTC_CLKIN_CLOCK RTC_CLKIN_CLK
864 #define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK
865 #define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK
866 #define SIM_LPO_CLOCK SIM_LPO_CLK
867 #define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK
868 #define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK
869 #define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK
870 #define SIM_EIM_CLOCK SIM_EIM_CLK
871 #define SIM_ERM_CLOCK SIM_ERM_CLK
872 #define SIM_DMA_CLOCK SIM_DMA_CLK
873 #define SIM_MPU_CLOCK SIM_MPU_CLK
874 #define SIM_MSCM_CLOCK SIM_MSCM_CLK
875 #define PCC_DMAMUX0_CLOCK DMAMUX0_CLK
876 #define PCC_CRC0_CLOCK CRC0_CLK
877 #define PCC_RTC0_CLOCK RTC0_CLK
878 #define PCC_PORTA_CLOCK PORTA_CLK
879 #define PCC_PORTB_CLOCK PORTB_CLK
880 #define PCC_PORTC_CLOCK PORTC_CLK
881 #define PCC_PORTD_CLOCK PORTD_CLK
882 #define PCC_PORTE_CLOCK PORTE_CLK
883 #define PCC_EWM0_CLOCK EWM0_CLK
884 #define PCC_CMP0_CLOCK CMP0_CLK
885 #define PCC_FlexCAN0_CLOCK FlexCAN0_CLK
886 #define PCC_FlexCAN1_CLOCK FlexCAN1_CLK
887 #define PCC_FlexCAN2_CLOCK FlexCAN2_CLK
888 #define PCC_PDB1_CLOCK PDB1_CLK
889 #define PCC_PDB0_CLOCK PDB0_CLK
890 #define PCC_FTFC0_CLOCK FTFC0_CLK
891 #define PCC_FTM0_CLOCK FTM0_CLK
892 #define PCC_FTM1_CLOCK FTM1_CLK
893 #define PCC_FTM2_CLOCK FTM2_CLK
894 #define PCC_FTM3_CLOCK FTM3_CLK
895 #define PCC_ADC1_CLOCK ADC1_CLK
896 #define PCC_LPSPI0_CLOCK LPSPI0_CLK
897 #define PCC_LPSPI1_CLOCK LPSPI1_CLK
898 #define PCC_LPSPI2_CLOCK LPSPI2_CLK
899 #define PCC_LPIT0_CLOCK LPIT0_CLK
900 #define PCC_ADC0_CLOCK ADC0_CLK
901 #define PCC_LPTMR0_CLOCK LPTMR0_CLK
902 #define PCC_FLEXIO0_CLOCK FLEXIO0_CLK
903 #define PCC_LPI2C0_CLOCK LPI2C0_CLK
904 #define PCC_LPUART0_CLOCK LPUART0_CLK
905 #define PCC_LPUART1_CLOCK LPUART1_CLK
906 #define PCC_LPUART2_CLOCK LPUART2_CLK
913 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
915 #define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn)
917 #define FEATURE_NVIC_PRIO_BITS (4U)
919 #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
921 #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
923 #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u)
930 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
933 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
936 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
939 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
942 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
945 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
948 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
950 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
953 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
956 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
958 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
960 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
962 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
964 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
966 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
968 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
970 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
977 #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0)
982 #define FEATURE_ADC_MAX_NUM_EXT_CHANS (16)
985 #if FEATURE_ADC_HAS_EXTRA_NUM_REGS
986 #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
988 #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
992 #define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
994 #define ADC_DEFAULT_USER_GAIN (0x04U)
1000 #define FEATURE_EDMA_MODULE_CHANNELS (16U)
1002 #define FEATURE_CHANNEL_INTERRUPT_LINES (16U)
1004 #define FEATURE_ERROR_INTERRUPT_LINES (1U)
1006 #define FEATURE_EDMA_HAS_ERROR_IRQ
1008 #define FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
1010 #define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
1012 #define FEATURE_EDMA_CHANNEL_GROUP_COUNT (1U)
1014 #define FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16U)
1016 #define EDMA_CLOCK_NAMES {SIM_DMA_CLK}
1022 #define FEATURE_DMAMUX_MODULE_CHANNELS (16U)
1024 #define FEATURE_DMAMUX_HAS_TRIG (1)
1026 #define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x) (x)
1028 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
1030 #define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x) (x)
1032 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
1034 #define DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
1098 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
1100 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
1105 #define FEATURE_OSIF_USE_SYSTICK (1)
1106 #define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1)
1111 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
1113 #define FEATURE_CAN_RXFIFO_WARNING (6U)
1115 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
1117 #define FEATURE_CAN0_HAS_FD (1)
1119 #define FEATURE_CAN1_HAS_FD (0)
1121 #define FEATURE_CAN0_MAX_MB_NUM (32U)
1123 #define FEATURE_CAN1_MAX_MB_NUM (16U)
1125 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
1127 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
1129 #define FEATURE_CAN_MAX_MB_NUM (32U)
1131 #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM, \
1132 FEATURE_CAN1_MAX_MB_NUM }
1134 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
1136 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
1138 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
1140 #define FEATURE_CAN_HAS_MBDSR1 (0)
1142 #define FEATURE_CAN_HAS_MBDSR2 (0)
1144 #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0, \
1148 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
1150 #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
1151 CAN_ORed_16_31_MB_IRQS }
1153 #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1)
1155 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
1157 #define FEATURE_CAN_PE_CLK_NUM 2U
1164 #define FLEXCAN_PE_CLOCK_NAMES { FLEXCAN_CLK_SOURCE_SOSCDIV2, FLEXCAN_CLK_SOURCE_SYS }
1167 #define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
1170 #define FEATURE_TRGMUX_HAS_EXTENDED_NUM_TRIGS (0)
1174 #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL}
dma_request_source_t
Structure for the DMA hardware request.
clock_names_t
Clock names.