S32 SDK
S32K142.h
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1 /*
2 ** ###################################################################
3 ** Processor: S32K142
4 ** Reference manual: S32K14XRM Rev. 2, 02/2017
5 ** Version: rev. 2.1, 2017-06-08
6 ** Build: b170608
7 **
8 ** Abstract:
9 ** Peripheral Access Layer for S32K142
10 **
11 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
12 ** Copyright 2016-2017 NXP
13 ** All rights reserved.
14 **
15 ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
16 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
19 ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
24 ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
25 ** THE POSSIBILITY OF SUCH DAMAGE.
26 **
27 ** http: www.nxp.com
28 ** mail: support@nxp.com
29 **
30 ** Revisions:
31 ** - rev. 1.0 (2016-11-24) - Iulian Talpiga
32 ** Initial version.
33 ** - rev. 1.1 (2017-01-09) - Iulian Talpiga
34 ** Fix interrupts
35 ** - rev. 2.0 (2017-02-23) - Iulian Talpiga
36 ** Update header as per rev S32K14XRM Rev. 2, 02/2017
37 ** Updated modules AIPS, CAN, LPI2C, LPSPI, MCM, MPU, SCG and SIM
38 ** - rev. 2.1 (2017-06-08) - Iulian Talpiga
39 ** Correct FTM module - add dithering registers.
40 **
41 ** ###################################################################
42 */
43 
92 /* ----------------------------------------------------------------------------
93  -- MCU activation
94  ---------------------------------------------------------------------------- */
95 
96 /* Prevention from multiple including the same memory map */
97 #if !defined(S32K142_H_) /* Check if memory map has not been already included */
98 #define S32K142_H_
99 #define MCU_S32K142
100 
101 /* Check if another memory map has not been also included */
102 #if (defined(MCU_ACTIVE))
103  #error S32K142 memory map: There is already included another memory map. Only one memory map can be included.
104 #endif /* (defined(MCU_ACTIVE)) */
105 #define MCU_ACTIVE
106 
107 #include <stdint.h>
108 
111 #define MCU_MEM_MAP_VERSION 0x0200u
112 
113 #define MCU_MEM_MAP_VERSION_MINOR 0x0001u
114 
115 /* ----------------------------------------------------------------------------
116  -- Generic macros
117  ---------------------------------------------------------------------------- */
118 
119 /* IO definitions (access restrictions to peripheral registers) */
125 #ifndef __IO
126 #ifdef __cplusplus
127  #define __I volatile
128 #else
129  #define __I volatile const
130 #endif
131 #define __O volatile
132 #define __IO volatile
133 #endif
134 
135 
139 #if !defined(REG_READ32)
140  #define REG_READ32(address) (*(volatile uint32_t*)(address))
141 #endif
142 
146 #if !defined(REG_WRITE32)
147  #define REG_WRITE32(address, value) ((*(volatile uint32_t*)(address))= (uint32_t)(value))
148 #endif
149 
153 #if !defined(REG_BIT_SET32)
154  #define REG_BIT_SET32(address, mask) ((*(volatile uint32_t*)(address))|= (uint32_t)(mask))
155 #endif
156 
160 #if !defined(REG_BIT_CLEAR32)
161  #define REG_BIT_CLEAR32(address, mask) ((*(volatile uint32_t*)(address))&= ((uint32_t)~((uint32_t)(mask))))
162 #endif
163 
168 #if !defined(REG_RMW32)
169  #define REG_RMW32(address, mask, value) (REG_WRITE32((address), ((REG_READ32(address)& ((uint32_t)~((uint32_t)(mask))))| ((uint32_t)(value)))))
170 #endif
171 
172 
173 /* ----------------------------------------------------------------------------
174  -- Interrupt vector numbers for S32K142
175  ---------------------------------------------------------------------------- */
176 
183 #define NUMBER_OF_INT_VECTORS 139u
192 typedef enum
193 {
194  /* Auxiliary constants */
195  NotAvail_IRQn = -128,
197  /* Core interrupts */
203  SVCall_IRQn = -5,
205  PendSV_IRQn = -2,
208  /* Device specific interrupts */
209  DMA0_IRQn = 0u,
210  DMA1_IRQn = 1u,
211  DMA2_IRQn = 2u,
212  DMA3_IRQn = 3u,
213  DMA4_IRQn = 4u,
214  DMA5_IRQn = 5u,
215  DMA6_IRQn = 6u,
216  DMA7_IRQn = 7u,
217  DMA8_IRQn = 8u,
218  DMA9_IRQn = 9u,
219  DMA10_IRQn = 10u,
220  DMA11_IRQn = 11u,
221  DMA12_IRQn = 12u,
222  DMA13_IRQn = 13u,
223  DMA14_IRQn = 14u,
224  DMA15_IRQn = 15u,
226  MCM_IRQn = 17u,
227  FTFC_IRQn = 18u,
229  LVD_LVW_IRQn = 20u,
232  RCM_IRQn = 23u,
235  LPSPI0_IRQn = 26u,
236  LPSPI1_IRQn = 27u,
239  ADC0_IRQn = 39u,
240  ADC1_IRQn = 40u,
241  CMP0_IRQn = 41u,
244  RTC_IRQn = 46u,
250  PDB0_IRQn = 52u,
251  SCG_IRQn = 57u,
252  LPTMR0_IRQn = 58u,
253  PORTA_IRQn = 59u,
254  PORTB_IRQn = 60u,
255  PORTC_IRQn = 61u,
256  PORTD_IRQn = 62u,
257  PORTE_IRQn = 63u,
258  SWI_IRQn = 64u,
259  PDB1_IRQn = 68u,
260  FLEXIO_IRQn = 69u,
293 } IRQn_Type;
294  /* end of group Interrupt_vector_numbers_S32K142 */
298 
299 
300 /* ----------------------------------------------------------------------------
301  -- Device Peripheral Access Layer for S32K142
302  ---------------------------------------------------------------------------- */
303 
309 /* @brief This module covers memory mapped registers available on SoC */
310 
311 /* ----------------------------------------------------------------------------
312  -- ADC Peripheral Access Layer
313  ---------------------------------------------------------------------------- */
314 
322 #define ADC_SC1_COUNT 16u
323 #define ADC_R_COUNT 16u
324 #define ADC_CV_COUNT 2u
325 
327 typedef struct {
328  __IO uint32_t SC1[ADC_SC1_COUNT];
329  __IO uint32_t CFG1;
330  __IO uint32_t CFG2;
331  __I uint32_t R[ADC_R_COUNT];
332  __IO uint32_t CV[ADC_CV_COUNT];
333  __IO uint32_t SC2;
334  __IO uint32_t SC3;
335  __IO uint32_t BASE_OFS;
336  __IO uint32_t OFS;
337  __IO uint32_t USR_OFS;
338  __IO uint32_t XOFS;
339  __IO uint32_t YOFS;
340  __IO uint32_t G;
341  __IO uint32_t UG;
342  __IO uint32_t CLPS;
343  __IO uint32_t CLP3;
344  __IO uint32_t CLP2;
345  __IO uint32_t CLP1;
346  __IO uint32_t CLP0;
347  __IO uint32_t CLPX;
348  __IO uint32_t CLP9;
349  __IO uint32_t CLPS_OFS;
350  __IO uint32_t CLP3_OFS;
351  __IO uint32_t CLP2_OFS;
352  __IO uint32_t CLP1_OFS;
353  __IO uint32_t CLP0_OFS;
354  __IO uint32_t CLPX_OFS;
355  __IO uint32_t CLP9_OFS;
357 
359 #define ADC_INSTANCE_COUNT (2u)
360 
361 
362 /* ADC - Peripheral instance base addresses */
364 #define ADC0_BASE (0x4003B000u)
365 
366 #define ADC0 ((ADC_Type *)ADC0_BASE)
367 
368 #define ADC1_BASE (0x40027000u)
369 
370 #define ADC1 ((ADC_Type *)ADC1_BASE)
371 
372 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
373 
374 #define ADC_BASE_PTRS { ADC0, ADC1 }
375 
376 #define ADC_IRQS_ARR_COUNT (1u)
377 
378 #define ADC_IRQS_CH_COUNT (1u)
379 
380 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
381 
382 /* ----------------------------------------------------------------------------
383  -- ADC Register Masks
384  ---------------------------------------------------------------------------- */
385 
391 /* SC1 Bit Fields */
392 #define ADC_SC1_ADCH_MASK 0x1Fu
393 #define ADC_SC1_ADCH_SHIFT 0u
394 #define ADC_SC1_ADCH_WIDTH 5u
395 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
396 #define ADC_SC1_AIEN_MASK 0x40u
397 #define ADC_SC1_AIEN_SHIFT 6u
398 #define ADC_SC1_AIEN_WIDTH 1u
399 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_AIEN_SHIFT))&ADC_SC1_AIEN_MASK)
400 #define ADC_SC1_COCO_MASK 0x80u
401 #define ADC_SC1_COCO_SHIFT 7u
402 #define ADC_SC1_COCO_WIDTH 1u
403 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_COCO_SHIFT))&ADC_SC1_COCO_MASK)
404 /* CFG1 Bit Fields */
405 #define ADC_CFG1_ADICLK_MASK 0x3u
406 #define ADC_CFG1_ADICLK_SHIFT 0u
407 #define ADC_CFG1_ADICLK_WIDTH 2u
408 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
409 #define ADC_CFG1_MODE_MASK 0xCu
410 #define ADC_CFG1_MODE_SHIFT 2u
411 #define ADC_CFG1_MODE_WIDTH 2u
412 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
413 #define ADC_CFG1_ADIV_MASK 0x60u
414 #define ADC_CFG1_ADIV_SHIFT 5u
415 #define ADC_CFG1_ADIV_WIDTH 2u
416 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
417 #define ADC_CFG1_CLRLTRG_MASK 0x100u
418 #define ADC_CFG1_CLRLTRG_SHIFT 8u
419 #define ADC_CFG1_CLRLTRG_WIDTH 1u
420 #define ADC_CFG1_CLRLTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_CLRLTRG_SHIFT))&ADC_CFG1_CLRLTRG_MASK)
421 /* CFG2 Bit Fields */
422 #define ADC_CFG2_SMPLTS_MASK 0xFFu
423 #define ADC_CFG2_SMPLTS_SHIFT 0u
424 #define ADC_CFG2_SMPLTS_WIDTH 8u
425 #define ADC_CFG2_SMPLTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_SMPLTS_SHIFT))&ADC_CFG2_SMPLTS_MASK)
426 /* R Bit Fields */
427 #define ADC_R_D_MASK 0xFFFu
428 #define ADC_R_D_SHIFT 0u
429 #define ADC_R_D_WIDTH 12u
430 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
431 /* CV Bit Fields */
432 #define ADC_CV_CV_MASK 0xFFFFu
433 #define ADC_CV_CV_SHIFT 0u
434 #define ADC_CV_CV_WIDTH 16u
435 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV_CV_SHIFT))&ADC_CV_CV_MASK)
436 /* SC2 Bit Fields */
437 #define ADC_SC2_REFSEL_MASK 0x3u
438 #define ADC_SC2_REFSEL_SHIFT 0u
439 #define ADC_SC2_REFSEL_WIDTH 2u
440 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
441 #define ADC_SC2_DMAEN_MASK 0x4u
442 #define ADC_SC2_DMAEN_SHIFT 2u
443 #define ADC_SC2_DMAEN_WIDTH 1u
444 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_DMAEN_SHIFT))&ADC_SC2_DMAEN_MASK)
445 #define ADC_SC2_ACREN_MASK 0x8u
446 #define ADC_SC2_ACREN_SHIFT 3u
447 #define ADC_SC2_ACREN_WIDTH 1u
448 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACREN_SHIFT))&ADC_SC2_ACREN_MASK)
449 #define ADC_SC2_ACFGT_MASK 0x10u
450 #define ADC_SC2_ACFGT_SHIFT 4u
451 #define ADC_SC2_ACFGT_WIDTH 1u
452 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFGT_SHIFT))&ADC_SC2_ACFGT_MASK)
453 #define ADC_SC2_ACFE_MASK 0x20u
454 #define ADC_SC2_ACFE_SHIFT 5u
455 #define ADC_SC2_ACFE_WIDTH 1u
456 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ACFE_SHIFT))&ADC_SC2_ACFE_MASK)
457 #define ADC_SC2_ADTRG_MASK 0x40u
458 #define ADC_SC2_ADTRG_SHIFT 6u
459 #define ADC_SC2_ADTRG_WIDTH 1u
460 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADTRG_SHIFT))&ADC_SC2_ADTRG_MASK)
461 #define ADC_SC2_ADACT_MASK 0x80u
462 #define ADC_SC2_ADACT_SHIFT 7u
463 #define ADC_SC2_ADACT_WIDTH 1u
464 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_ADACT_SHIFT))&ADC_SC2_ADACT_MASK)
465 #define ADC_SC2_TRGPRNUM_MASK 0x6000u
466 #define ADC_SC2_TRGPRNUM_SHIFT 13u
467 #define ADC_SC2_TRGPRNUM_WIDTH 2u
468 #define ADC_SC2_TRGPRNUM(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGPRNUM_SHIFT))&ADC_SC2_TRGPRNUM_MASK)
469 #define ADC_SC2_TRGSTLAT_MASK 0xF0000u
470 #define ADC_SC2_TRGSTLAT_SHIFT 16u
471 #define ADC_SC2_TRGSTLAT_WIDTH 4u
472 #define ADC_SC2_TRGSTLAT(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTLAT_SHIFT))&ADC_SC2_TRGSTLAT_MASK)
473 #define ADC_SC2_TRGSTERR_MASK 0xF000000u
474 #define ADC_SC2_TRGSTERR_SHIFT 24u
475 #define ADC_SC2_TRGSTERR_WIDTH 4u
476 #define ADC_SC2_TRGSTERR(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_TRGSTERR_SHIFT))&ADC_SC2_TRGSTERR_MASK)
477 /* SC3 Bit Fields */
478 #define ADC_SC3_AVGS_MASK 0x3u
479 #define ADC_SC3_AVGS_SHIFT 0u
480 #define ADC_SC3_AVGS_WIDTH 2u
481 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
482 #define ADC_SC3_AVGE_MASK 0x4u
483 #define ADC_SC3_AVGE_SHIFT 2u
484 #define ADC_SC3_AVGE_WIDTH 1u
485 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGE_SHIFT))&ADC_SC3_AVGE_MASK)
486 #define ADC_SC3_ADCO_MASK 0x8u
487 #define ADC_SC3_ADCO_SHIFT 3u
488 #define ADC_SC3_ADCO_WIDTH 1u
489 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_ADCO_SHIFT))&ADC_SC3_ADCO_MASK)
490 #define ADC_SC3_CAL_MASK 0x80u
491 #define ADC_SC3_CAL_SHIFT 7u
492 #define ADC_SC3_CAL_WIDTH 1u
493 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_CAL_SHIFT))&ADC_SC3_CAL_MASK)
494 /* BASE_OFS Bit Fields */
495 #define ADC_BASE_OFS_BA_OFS_MASK 0xFFu
496 #define ADC_BASE_OFS_BA_OFS_SHIFT 0u
497 #define ADC_BASE_OFS_BA_OFS_WIDTH 8u
498 #define ADC_BASE_OFS_BA_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_BASE_OFS_BA_OFS_SHIFT))&ADC_BASE_OFS_BA_OFS_MASK)
499 /* OFS Bit Fields */
500 #define ADC_OFS_OFS_MASK 0xFFFFu
501 #define ADC_OFS_OFS_SHIFT 0u
502 #define ADC_OFS_OFS_WIDTH 16u
503 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
504 /* USR_OFS Bit Fields */
505 #define ADC_USR_OFS_USR_OFS_MASK 0xFFu
506 #define ADC_USR_OFS_USR_OFS_SHIFT 0u
507 #define ADC_USR_OFS_USR_OFS_WIDTH 8u
508 #define ADC_USR_OFS_USR_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_USR_OFS_USR_OFS_SHIFT))&ADC_USR_OFS_USR_OFS_MASK)
509 /* XOFS Bit Fields */
510 #define ADC_XOFS_XOFS_MASK 0x3Fu
511 #define ADC_XOFS_XOFS_SHIFT 0u
512 #define ADC_XOFS_XOFS_WIDTH 6u
513 #define ADC_XOFS_XOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_XOFS_XOFS_SHIFT))&ADC_XOFS_XOFS_MASK)
514 /* YOFS Bit Fields */
515 #define ADC_YOFS_YOFS_MASK 0xFFu
516 #define ADC_YOFS_YOFS_SHIFT 0u
517 #define ADC_YOFS_YOFS_WIDTH 8u
518 #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_YOFS_YOFS_SHIFT))&ADC_YOFS_YOFS_MASK)
519 /* G Bit Fields */
520 #define ADC_G_G_MASK 0x7FFu
521 #define ADC_G_G_SHIFT 0u
522 #define ADC_G_G_WIDTH 11u
523 #define ADC_G_G(x) (((uint32_t)(((uint32_t)(x))<<ADC_G_G_SHIFT))&ADC_G_G_MASK)
524 /* UG Bit Fields */
525 #define ADC_UG_UG_MASK 0x3FFu
526 #define ADC_UG_UG_SHIFT 0u
527 #define ADC_UG_UG_WIDTH 10u
528 #define ADC_UG_UG(x) (((uint32_t)(((uint32_t)(x))<<ADC_UG_UG_SHIFT))&ADC_UG_UG_MASK)
529 /* CLPS Bit Fields */
530 #define ADC_CLPS_CLPS_MASK 0x7Fu
531 #define ADC_CLPS_CLPS_SHIFT 0u
532 #define ADC_CLPS_CLPS_WIDTH 7u
533 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
534 /* CLP3 Bit Fields */
535 #define ADC_CLP3_CLP3_MASK 0x3FFu
536 #define ADC_CLP3_CLP3_SHIFT 0u
537 #define ADC_CLP3_CLP3_WIDTH 10u
538 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
539 /* CLP2 Bit Fields */
540 #define ADC_CLP2_CLP2_MASK 0x3FFu
541 #define ADC_CLP2_CLP2_SHIFT 0u
542 #define ADC_CLP2_CLP2_WIDTH 10u
543 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
544 /* CLP1 Bit Fields */
545 #define ADC_CLP1_CLP1_MASK 0x1FFu
546 #define ADC_CLP1_CLP1_SHIFT 0u
547 #define ADC_CLP1_CLP1_WIDTH 9u
548 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
549 /* CLP0 Bit Fields */
550 #define ADC_CLP0_CLP0_MASK 0xFFu
551 #define ADC_CLP0_CLP0_SHIFT 0u
552 #define ADC_CLP0_CLP0_WIDTH 8u
553 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
554 /* CLPX Bit Fields */
555 #define ADC_CLPX_CLPX_MASK 0x7Fu
556 #define ADC_CLPX_CLPX_SHIFT 0u
557 #define ADC_CLPX_CLPX_WIDTH 7u
558 #define ADC_CLPX_CLPX(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_CLPX_SHIFT))&ADC_CLPX_CLPX_MASK)
559 /* CLP9 Bit Fields */
560 #define ADC_CLP9_CLP9_MASK 0x7Fu
561 #define ADC_CLP9_CLP9_SHIFT 0u
562 #define ADC_CLP9_CLP9_WIDTH 7u
563 #define ADC_CLP9_CLP9(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_CLP9_SHIFT))&ADC_CLP9_CLP9_MASK)
564 /* CLPS_OFS Bit Fields */
565 #define ADC_CLPS_OFS_CLPS_OFS_MASK 0xFu
566 #define ADC_CLPS_OFS_CLPS_OFS_SHIFT 0u
567 #define ADC_CLPS_OFS_CLPS_OFS_WIDTH 4u
568 #define ADC_CLPS_OFS_CLPS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_OFS_CLPS_OFS_SHIFT))&ADC_CLPS_OFS_CLPS_OFS_MASK)
569 /* CLP3_OFS Bit Fields */
570 #define ADC_CLP3_OFS_CLP3_OFS_MASK 0xFu
571 #define ADC_CLP3_OFS_CLP3_OFS_SHIFT 0u
572 #define ADC_CLP3_OFS_CLP3_OFS_WIDTH 4u
573 #define ADC_CLP3_OFS_CLP3_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_OFS_CLP3_OFS_SHIFT))&ADC_CLP3_OFS_CLP3_OFS_MASK)
574 /* CLP2_OFS Bit Fields */
575 #define ADC_CLP2_OFS_CLP2_OFS_MASK 0xFu
576 #define ADC_CLP2_OFS_CLP2_OFS_SHIFT 0u
577 #define ADC_CLP2_OFS_CLP2_OFS_WIDTH 4u
578 #define ADC_CLP2_OFS_CLP2_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_OFS_CLP2_OFS_SHIFT))&ADC_CLP2_OFS_CLP2_OFS_MASK)
579 /* CLP1_OFS Bit Fields */
580 #define ADC_CLP1_OFS_CLP1_OFS_MASK 0xFu
581 #define ADC_CLP1_OFS_CLP1_OFS_SHIFT 0u
582 #define ADC_CLP1_OFS_CLP1_OFS_WIDTH 4u
583 #define ADC_CLP1_OFS_CLP1_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_OFS_CLP1_OFS_SHIFT))&ADC_CLP1_OFS_CLP1_OFS_MASK)
584 /* CLP0_OFS Bit Fields */
585 #define ADC_CLP0_OFS_CLP0_OFS_MASK 0xFu
586 #define ADC_CLP0_OFS_CLP0_OFS_SHIFT 0u
587 #define ADC_CLP0_OFS_CLP0_OFS_WIDTH 4u
588 #define ADC_CLP0_OFS_CLP0_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_OFS_CLP0_OFS_SHIFT))&ADC_CLP0_OFS_CLP0_OFS_MASK)
589 /* CLPX_OFS Bit Fields */
590 #define ADC_CLPX_OFS_CLPX_OFS_MASK 0xFFFu
591 #define ADC_CLPX_OFS_CLPX_OFS_SHIFT 0u
592 #define ADC_CLPX_OFS_CLPX_OFS_WIDTH 12u
593 #define ADC_CLPX_OFS_CLPX_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPX_OFS_CLPX_OFS_SHIFT))&ADC_CLPX_OFS_CLPX_OFS_MASK)
594 /* CLP9_OFS Bit Fields */
595 #define ADC_CLP9_OFS_CLP9_OFS_MASK 0xFFFu
596 #define ADC_CLP9_OFS_CLP9_OFS_SHIFT 0u
597 #define ADC_CLP9_OFS_CLP9_OFS_WIDTH 12u
598 #define ADC_CLP9_OFS_CLP9_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP9_OFS_CLP9_OFS_SHIFT))&ADC_CLP9_OFS_CLP9_OFS_MASK)
599  /* end of group ADC_Register_Masks */
603 
604  /* end of group ADC_Peripheral_Access_Layer */
608 
609 
610 /* ----------------------------------------------------------------------------
611  -- AIPS Peripheral Access Layer
612  ---------------------------------------------------------------------------- */
613 
621 #define AIPS_PACR_COUNT 4u
622 #define AIPS_OPACR_COUNT 12u
623 
625 typedef struct {
626  __IO uint32_t MPRA;
627  uint8_t RESERVED_0[28];
628  __IO uint32_t PACR[AIPS_PACR_COUNT];
629  uint8_t RESERVED_1[16];
630  __IO uint32_t OPACR[AIPS_OPACR_COUNT];
632 
634 #define AIPS_INSTANCE_COUNT (1u)
635 
636 
637 /* AIPS - Peripheral instance base addresses */
639 #define AIPS_BASE (0x40000000u)
640 
641 #define AIPS ((AIPS_Type *)AIPS_BASE)
642 
643 #define AIPS_BASE_ADDRS { AIPS_BASE }
644 
645 #define AIPS_BASE_PTRS { AIPS }
646 
647 /* ----------------------------------------------------------------------------
648  -- AIPS Register Masks
649  ---------------------------------------------------------------------------- */
650 
656 /* MPRA Bit Fields */
657 #define AIPS_MPRA_MPL2_MASK 0x100000u
658 #define AIPS_MPRA_MPL2_SHIFT 20u
659 #define AIPS_MPRA_MPL2_WIDTH 1u
660 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL2_SHIFT))&AIPS_MPRA_MPL2_MASK)
661 #define AIPS_MPRA_MTW2_MASK 0x200000u
662 #define AIPS_MPRA_MTW2_SHIFT 21u
663 #define AIPS_MPRA_MTW2_WIDTH 1u
664 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW2_SHIFT))&AIPS_MPRA_MTW2_MASK)
665 #define AIPS_MPRA_MTR2_MASK 0x400000u
666 #define AIPS_MPRA_MTR2_SHIFT 22u
667 #define AIPS_MPRA_MTR2_WIDTH 1u
668 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR2_SHIFT))&AIPS_MPRA_MTR2_MASK)
669 #define AIPS_MPRA_MPL1_MASK 0x1000000u
670 #define AIPS_MPRA_MPL1_SHIFT 24u
671 #define AIPS_MPRA_MPL1_WIDTH 1u
672 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL1_SHIFT))&AIPS_MPRA_MPL1_MASK)
673 #define AIPS_MPRA_MTW1_MASK 0x2000000u
674 #define AIPS_MPRA_MTW1_SHIFT 25u
675 #define AIPS_MPRA_MTW1_WIDTH 1u
676 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW1_SHIFT))&AIPS_MPRA_MTW1_MASK)
677 #define AIPS_MPRA_MTR1_MASK 0x4000000u
678 #define AIPS_MPRA_MTR1_SHIFT 26u
679 #define AIPS_MPRA_MTR1_WIDTH 1u
680 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR1_SHIFT))&AIPS_MPRA_MTR1_MASK)
681 #define AIPS_MPRA_MPL0_MASK 0x10000000u
682 #define AIPS_MPRA_MPL0_SHIFT 28u
683 #define AIPS_MPRA_MPL0_WIDTH 1u
684 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MPL0_SHIFT))&AIPS_MPRA_MPL0_MASK)
685 #define AIPS_MPRA_MTW0_MASK 0x20000000u
686 #define AIPS_MPRA_MTW0_SHIFT 29u
687 #define AIPS_MPRA_MTW0_WIDTH 1u
688 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTW0_SHIFT))&AIPS_MPRA_MTW0_MASK)
689 #define AIPS_MPRA_MTR0_MASK 0x40000000u
690 #define AIPS_MPRA_MTR0_SHIFT 30u
691 #define AIPS_MPRA_MTR0_WIDTH 1u
692 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_MPRA_MTR0_SHIFT))&AIPS_MPRA_MTR0_MASK)
693 /* PACR Bit Fields */
694 #define AIPS_PACR_TP5_MASK 0x100u
695 #define AIPS_PACR_TP5_SHIFT 8u
696 #define AIPS_PACR_TP5_WIDTH 1u
697 #define AIPS_PACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP5_SHIFT))&AIPS_PACR_TP5_MASK)
698 #define AIPS_PACR_WP5_MASK 0x200u
699 #define AIPS_PACR_WP5_SHIFT 9u
700 #define AIPS_PACR_WP5_WIDTH 1u
701 #define AIPS_PACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP5_SHIFT))&AIPS_PACR_WP5_MASK)
702 #define AIPS_PACR_SP5_MASK 0x400u
703 #define AIPS_PACR_SP5_SHIFT 10u
704 #define AIPS_PACR_SP5_WIDTH 1u
705 #define AIPS_PACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP5_SHIFT))&AIPS_PACR_SP5_MASK)
706 #define AIPS_PACR_TP1_MASK 0x1000000u
707 #define AIPS_PACR_TP1_SHIFT 24u
708 #define AIPS_PACR_TP1_WIDTH 1u
709 #define AIPS_PACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP1_SHIFT))&AIPS_PACR_TP1_MASK)
710 #define AIPS_PACR_WP1_MASK 0x2000000u
711 #define AIPS_PACR_WP1_SHIFT 25u
712 #define AIPS_PACR_WP1_WIDTH 1u
713 #define AIPS_PACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP1_SHIFT))&AIPS_PACR_WP1_MASK)
714 #define AIPS_PACR_SP1_MASK 0x4000000u
715 #define AIPS_PACR_SP1_SHIFT 26u
716 #define AIPS_PACR_SP1_WIDTH 1u
717 #define AIPS_PACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP1_SHIFT))&AIPS_PACR_SP1_MASK)
718 #define AIPS_PACR_TP0_MASK 0x10000000u
719 #define AIPS_PACR_TP0_SHIFT 28u
720 #define AIPS_PACR_TP0_WIDTH 1u
721 #define AIPS_PACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_TP0_SHIFT))&AIPS_PACR_TP0_MASK)
722 #define AIPS_PACR_WP0_MASK 0x20000000u
723 #define AIPS_PACR_WP0_SHIFT 29u
724 #define AIPS_PACR_WP0_WIDTH 1u
725 #define AIPS_PACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_WP0_SHIFT))&AIPS_PACR_WP0_MASK)
726 #define AIPS_PACR_SP0_MASK 0x40000000u
727 #define AIPS_PACR_SP0_SHIFT 30u
728 #define AIPS_PACR_SP0_WIDTH 1u
729 #define AIPS_PACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_PACR_SP0_SHIFT))&AIPS_PACR_SP0_MASK)
730 /* OPACR Bit Fields */
731 #define AIPS_OPACR_TP7_MASK 0x1u
732 #define AIPS_OPACR_TP7_SHIFT 0u
733 #define AIPS_OPACR_TP7_WIDTH 1u
734 #define AIPS_OPACR_TP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP7_SHIFT))&AIPS_OPACR_TP7_MASK)
735 #define AIPS_OPACR_WP7_MASK 0x2u
736 #define AIPS_OPACR_WP7_SHIFT 1u
737 #define AIPS_OPACR_WP7_WIDTH 1u
738 #define AIPS_OPACR_WP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP7_SHIFT))&AIPS_OPACR_WP7_MASK)
739 #define AIPS_OPACR_SP7_MASK 0x4u
740 #define AIPS_OPACR_SP7_SHIFT 2u
741 #define AIPS_OPACR_SP7_WIDTH 1u
742 #define AIPS_OPACR_SP7(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP7_SHIFT))&AIPS_OPACR_SP7_MASK)
743 #define AIPS_OPACR_TP6_MASK 0x10u
744 #define AIPS_OPACR_TP6_SHIFT 4u
745 #define AIPS_OPACR_TP6_WIDTH 1u
746 #define AIPS_OPACR_TP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP6_SHIFT))&AIPS_OPACR_TP6_MASK)
747 #define AIPS_OPACR_WP6_MASK 0x20u
748 #define AIPS_OPACR_WP6_SHIFT 5u
749 #define AIPS_OPACR_WP6_WIDTH 1u
750 #define AIPS_OPACR_WP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP6_SHIFT))&AIPS_OPACR_WP6_MASK)
751 #define AIPS_OPACR_SP6_MASK 0x40u
752 #define AIPS_OPACR_SP6_SHIFT 6u
753 #define AIPS_OPACR_SP6_WIDTH 1u
754 #define AIPS_OPACR_SP6(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP6_SHIFT))&AIPS_OPACR_SP6_MASK)
755 #define AIPS_OPACR_TP5_MASK 0x100u
756 #define AIPS_OPACR_TP5_SHIFT 8u
757 #define AIPS_OPACR_TP5_WIDTH 1u
758 #define AIPS_OPACR_TP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP5_SHIFT))&AIPS_OPACR_TP5_MASK)
759 #define AIPS_OPACR_WP5_MASK 0x200u
760 #define AIPS_OPACR_WP5_SHIFT 9u
761 #define AIPS_OPACR_WP5_WIDTH 1u
762 #define AIPS_OPACR_WP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP5_SHIFT))&AIPS_OPACR_WP5_MASK)
763 #define AIPS_OPACR_SP5_MASK 0x400u
764 #define AIPS_OPACR_SP5_SHIFT 10u
765 #define AIPS_OPACR_SP5_WIDTH 1u
766 #define AIPS_OPACR_SP5(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP5_SHIFT))&AIPS_OPACR_SP5_MASK)
767 #define AIPS_OPACR_TP4_MASK 0x1000u
768 #define AIPS_OPACR_TP4_SHIFT 12u
769 #define AIPS_OPACR_TP4_WIDTH 1u
770 #define AIPS_OPACR_TP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP4_SHIFT))&AIPS_OPACR_TP4_MASK)
771 #define AIPS_OPACR_WP4_MASK 0x2000u
772 #define AIPS_OPACR_WP4_SHIFT 13u
773 #define AIPS_OPACR_WP4_WIDTH 1u
774 #define AIPS_OPACR_WP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP4_SHIFT))&AIPS_OPACR_WP4_MASK)
775 #define AIPS_OPACR_SP4_MASK 0x4000u
776 #define AIPS_OPACR_SP4_SHIFT 14u
777 #define AIPS_OPACR_SP4_WIDTH 1u
778 #define AIPS_OPACR_SP4(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP4_SHIFT))&AIPS_OPACR_SP4_MASK)
779 #define AIPS_OPACR_TP3_MASK 0x10000u
780 #define AIPS_OPACR_TP3_SHIFT 16u
781 #define AIPS_OPACR_TP3_WIDTH 1u
782 #define AIPS_OPACR_TP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP3_SHIFT))&AIPS_OPACR_TP3_MASK)
783 #define AIPS_OPACR_WP3_MASK 0x20000u
784 #define AIPS_OPACR_WP3_SHIFT 17u
785 #define AIPS_OPACR_WP3_WIDTH 1u
786 #define AIPS_OPACR_WP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP3_SHIFT))&AIPS_OPACR_WP3_MASK)
787 #define AIPS_OPACR_SP3_MASK 0x40000u
788 #define AIPS_OPACR_SP3_SHIFT 18u
789 #define AIPS_OPACR_SP3_WIDTH 1u
790 #define AIPS_OPACR_SP3(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP3_SHIFT))&AIPS_OPACR_SP3_MASK)
791 #define AIPS_OPACR_TP2_MASK 0x100000u
792 #define AIPS_OPACR_TP2_SHIFT 20u
793 #define AIPS_OPACR_TP2_WIDTH 1u
794 #define AIPS_OPACR_TP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP2_SHIFT))&AIPS_OPACR_TP2_MASK)
795 #define AIPS_OPACR_WP2_MASK 0x200000u
796 #define AIPS_OPACR_WP2_SHIFT 21u
797 #define AIPS_OPACR_WP2_WIDTH 1u
798 #define AIPS_OPACR_WP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP2_SHIFT))&AIPS_OPACR_WP2_MASK)
799 #define AIPS_OPACR_SP2_MASK 0x400000u
800 #define AIPS_OPACR_SP2_SHIFT 22u
801 #define AIPS_OPACR_SP2_WIDTH 1u
802 #define AIPS_OPACR_SP2(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP2_SHIFT))&AIPS_OPACR_SP2_MASK)
803 #define AIPS_OPACR_TP1_MASK 0x1000000u
804 #define AIPS_OPACR_TP1_SHIFT 24u
805 #define AIPS_OPACR_TP1_WIDTH 1u
806 #define AIPS_OPACR_TP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP1_SHIFT))&AIPS_OPACR_TP1_MASK)
807 #define AIPS_OPACR_WP1_MASK 0x2000000u
808 #define AIPS_OPACR_WP1_SHIFT 25u
809 #define AIPS_OPACR_WP1_WIDTH 1u
810 #define AIPS_OPACR_WP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP1_SHIFT))&AIPS_OPACR_WP1_MASK)
811 #define AIPS_OPACR_SP1_MASK 0x4000000u
812 #define AIPS_OPACR_SP1_SHIFT 26u
813 #define AIPS_OPACR_SP1_WIDTH 1u
814 #define AIPS_OPACR_SP1(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP1_SHIFT))&AIPS_OPACR_SP1_MASK)
815 #define AIPS_OPACR_TP0_MASK 0x10000000u
816 #define AIPS_OPACR_TP0_SHIFT 28u
817 #define AIPS_OPACR_TP0_WIDTH 1u
818 #define AIPS_OPACR_TP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_TP0_SHIFT))&AIPS_OPACR_TP0_MASK)
819 #define AIPS_OPACR_WP0_MASK 0x20000000u
820 #define AIPS_OPACR_WP0_SHIFT 29u
821 #define AIPS_OPACR_WP0_WIDTH 1u
822 #define AIPS_OPACR_WP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_WP0_SHIFT))&AIPS_OPACR_WP0_MASK)
823 #define AIPS_OPACR_SP0_MASK 0x40000000u
824 #define AIPS_OPACR_SP0_SHIFT 30u
825 #define AIPS_OPACR_SP0_WIDTH 1u
826 #define AIPS_OPACR_SP0(x) (((uint32_t)(((uint32_t)(x))<<AIPS_OPACR_SP0_SHIFT))&AIPS_OPACR_SP0_MASK)
827  /* end of group AIPS_Register_Masks */
831 
832  /* end of group AIPS_Peripheral_Access_Layer */
836 
837 
838 /* ----------------------------------------------------------------------------
839  -- CAN Peripheral Access Layer
840  ---------------------------------------------------------------------------- */
841 
849 #define CAN_RAMn_COUNT 128u
850 #define CAN_RXIMR_COUNT 16u
851 #define CAN_WMB_COUNT 4u
852 
854 typedef struct {
855  __IO uint32_t MCR;
856  __IO uint32_t CTRL1;
857  __IO uint32_t TIMER;
858  uint8_t RESERVED_0[4];
859  __IO uint32_t RXMGMASK;
860  __IO uint32_t RX14MASK;
861  __IO uint32_t RX15MASK;
862  __IO uint32_t ECR;
863  __IO uint32_t ESR1;
864  uint8_t RESERVED_1[4];
865  __IO uint32_t IMASK1;
866  uint8_t RESERVED_2[4];
867  __IO uint32_t IFLAG1;
868  __IO uint32_t CTRL2;
869  __I uint32_t ESR2;
870  uint8_t RESERVED_3[8];
871  __I uint32_t CRCR;
872  __IO uint32_t RXFGMASK;
873  __I uint32_t RXFIR;
874  __IO uint32_t CBT;
875  uint8_t RESERVED_4[44];
876  __IO uint32_t RAMn[CAN_RAMn_COUNT];
877  uint8_t RESERVED_5[1536];
878  __IO uint32_t RXIMR[CAN_RXIMR_COUNT];
879  uint8_t RESERVED_6[576];
880  __IO uint32_t CTRL1_PN;
881  __IO uint32_t CTRL2_PN;
882  __IO uint32_t WU_MTC;
883  __IO uint32_t FLT_ID1;
884  __IO uint32_t FLT_DLC;
885  __IO uint32_t PL1_LO;
886  __IO uint32_t PL1_HI;
887  __IO uint32_t FLT_ID2_IDMASK;
888  __IO uint32_t PL2_PLMASK_LO;
889  __IO uint32_t PL2_PLMASK_HI;
890  uint8_t RESERVED_7[24];
891  struct { /* offset: 0xB40, array step: 0x10 */
892  __I uint32_t WMBn_CS;
893  __I uint32_t WMBn_ID;
894  __I uint32_t WMBn_D03;
895  __I uint32_t WMBn_D47;
896  } WMB[CAN_WMB_COUNT];
897  uint8_t RESERVED_8[128];
898  __IO uint32_t FDCTRL;
899  __IO uint32_t FDCBT;
900  __I uint32_t FDCRC;
902 
904 #define CAN_INSTANCE_COUNT (2u)
905 
906 
907 /* CAN - Peripheral instance base addresses */
909 #define CAN0_BASE (0x40024000u)
910 
911 #define CAN0 ((CAN_Type *)CAN0_BASE)
912 
913 #define CAN1_BASE (0x40025000u)
914 
915 #define CAN1 ((CAN_Type *)CAN1_BASE)
916 
917 #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
918 
919 #define CAN_BASE_PTRS { CAN0, CAN1 }
920 
921 #define CAN_IRQS_ARR_COUNT (7u)
922 
923 #define CAN_Rx_Warning_IRQS_CH_COUNT (1u)
924 
925 #define CAN_Tx_Warning_IRQS_CH_COUNT (1u)
926 
927 #define CAN_Wake_Up_IRQS_CH_COUNT (1u)
928 
929 #define CAN_Error_IRQS_CH_COUNT (1u)
930 
931 #define CAN_Bus_Off_IRQS_CH_COUNT (1u)
932 
933 #define CAN_ORed_0_15_MB_IRQS_CH_COUNT (1u)
934 
935 #define CAN_ORed_16_31_MB_IRQS_CH_COUNT (1u)
936 
937 #define CAN_Rx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn }
938 #define CAN_Tx_Warning_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn }
939 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, NotAvail_IRQn }
940 #define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
941 #define CAN_Bus_Off_IRQS { CAN0_ORed_IRQn, CAN1_ORed_IRQn }
942 #define CAN_ORed_0_15_MB_IRQS { CAN0_ORed_0_15_MB_IRQn, CAN1_ORed_0_15_MB_IRQn }
943 #define CAN_ORed_16_31_MB_IRQS { CAN0_ORed_16_31_MB_IRQn, NotAvail_IRQn }
944 
945 /* ----------------------------------------------------------------------------
946  -- CAN Register Masks
947  ---------------------------------------------------------------------------- */
948 
954 /* MCR Bit Fields */
955 #define CAN_MCR_MAXMB_MASK 0x7Fu
956 #define CAN_MCR_MAXMB_SHIFT 0u
957 #define CAN_MCR_MAXMB_WIDTH 7u
958 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
959 #define CAN_MCR_IDAM_MASK 0x300u
960 #define CAN_MCR_IDAM_SHIFT 8u
961 #define CAN_MCR_IDAM_WIDTH 2u
962 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
963 #define CAN_MCR_FDEN_MASK 0x800u
964 #define CAN_MCR_FDEN_SHIFT 11u
965 #define CAN_MCR_FDEN_WIDTH 1u
966 #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FDEN_SHIFT))&CAN_MCR_FDEN_MASK)
967 #define CAN_MCR_AEN_MASK 0x1000u
968 #define CAN_MCR_AEN_SHIFT 12u
969 #define CAN_MCR_AEN_WIDTH 1u
970 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_AEN_SHIFT))&CAN_MCR_AEN_MASK)
971 #define CAN_MCR_LPRIOEN_MASK 0x2000u
972 #define CAN_MCR_LPRIOEN_SHIFT 13u
973 #define CAN_MCR_LPRIOEN_WIDTH 1u
974 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPRIOEN_SHIFT))&CAN_MCR_LPRIOEN_MASK)
975 #define CAN_MCR_PNET_EN_MASK 0x4000u
976 #define CAN_MCR_PNET_EN_SHIFT 14u
977 #define CAN_MCR_PNET_EN_WIDTH 1u
978 #define CAN_MCR_PNET_EN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_PNET_EN_SHIFT))&CAN_MCR_PNET_EN_MASK)
979 #define CAN_MCR_DMA_MASK 0x8000u
980 #define CAN_MCR_DMA_SHIFT 15u
981 #define CAN_MCR_DMA_WIDTH 1u
982 #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_DMA_SHIFT))&CAN_MCR_DMA_MASK)
983 #define CAN_MCR_IRMQ_MASK 0x10000u
984 #define CAN_MCR_IRMQ_SHIFT 16u
985 #define CAN_MCR_IRMQ_WIDTH 1u
986 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IRMQ_SHIFT))&CAN_MCR_IRMQ_MASK)
987 #define CAN_MCR_SRXDIS_MASK 0x20000u
988 #define CAN_MCR_SRXDIS_SHIFT 17u
989 #define CAN_MCR_SRXDIS_WIDTH 1u
990 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SRXDIS_SHIFT))&CAN_MCR_SRXDIS_MASK)
991 #define CAN_MCR_LPMACK_MASK 0x100000u
992 #define CAN_MCR_LPMACK_SHIFT 20u
993 #define CAN_MCR_LPMACK_WIDTH 1u
994 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_LPMACK_SHIFT))&CAN_MCR_LPMACK_MASK)
995 #define CAN_MCR_WRNEN_MASK 0x200000u
996 #define CAN_MCR_WRNEN_SHIFT 21u
997 #define CAN_MCR_WRNEN_WIDTH 1u
998 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_WRNEN_SHIFT))&CAN_MCR_WRNEN_MASK)
999 #define CAN_MCR_SUPV_MASK 0x800000u
1000 #define CAN_MCR_SUPV_SHIFT 23u
1001 #define CAN_MCR_SUPV_WIDTH 1u
1002 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SUPV_SHIFT))&CAN_MCR_SUPV_MASK)
1003 #define CAN_MCR_FRZACK_MASK 0x1000000u
1004 #define CAN_MCR_FRZACK_SHIFT 24u
1005 #define CAN_MCR_FRZACK_WIDTH 1u
1006 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZACK_SHIFT))&CAN_MCR_FRZACK_MASK)
1007 #define CAN_MCR_SOFTRST_MASK 0x2000000u
1008 #define CAN_MCR_SOFTRST_SHIFT 25u
1009 #define CAN_MCR_SOFTRST_WIDTH 1u
1010 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_SOFTRST_SHIFT))&CAN_MCR_SOFTRST_MASK)
1011 #define CAN_MCR_NOTRDY_MASK 0x8000000u
1012 #define CAN_MCR_NOTRDY_SHIFT 27u
1013 #define CAN_MCR_NOTRDY_WIDTH 1u
1014 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_NOTRDY_SHIFT))&CAN_MCR_NOTRDY_MASK)
1015 #define CAN_MCR_HALT_MASK 0x10000000u
1016 #define CAN_MCR_HALT_SHIFT 28u
1017 #define CAN_MCR_HALT_WIDTH 1u
1018 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_HALT_SHIFT))&CAN_MCR_HALT_MASK)
1019 #define CAN_MCR_RFEN_MASK 0x20000000u
1020 #define CAN_MCR_RFEN_SHIFT 29u
1021 #define CAN_MCR_RFEN_WIDTH 1u
1022 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_RFEN_SHIFT))&CAN_MCR_RFEN_MASK)
1023 #define CAN_MCR_FRZ_MASK 0x40000000u
1024 #define CAN_MCR_FRZ_SHIFT 30u
1025 #define CAN_MCR_FRZ_WIDTH 1u
1026 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_FRZ_SHIFT))&CAN_MCR_FRZ_MASK)
1027 #define CAN_MCR_MDIS_MASK 0x80000000u
1028 #define CAN_MCR_MDIS_SHIFT 31u
1029 #define CAN_MCR_MDIS_WIDTH 1u
1030 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MDIS_SHIFT))&CAN_MCR_MDIS_MASK)
1031 /* CTRL1 Bit Fields */
1032 #define CAN_CTRL1_PROPSEG_MASK 0x7u
1033 #define CAN_CTRL1_PROPSEG_SHIFT 0u
1034 #define CAN_CTRL1_PROPSEG_WIDTH 3u
1035 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
1036 #define CAN_CTRL1_LOM_MASK 0x8u
1037 #define CAN_CTRL1_LOM_SHIFT 3u
1038 #define CAN_CTRL1_LOM_WIDTH 1u
1039 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LOM_SHIFT))&CAN_CTRL1_LOM_MASK)
1040 #define CAN_CTRL1_LBUF_MASK 0x10u
1041 #define CAN_CTRL1_LBUF_SHIFT 4u
1042 #define CAN_CTRL1_LBUF_WIDTH 1u
1043 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LBUF_SHIFT))&CAN_CTRL1_LBUF_MASK)
1044 #define CAN_CTRL1_TSYN_MASK 0x20u
1045 #define CAN_CTRL1_TSYN_SHIFT 5u
1046 #define CAN_CTRL1_TSYN_WIDTH 1u
1047 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TSYN_SHIFT))&CAN_CTRL1_TSYN_MASK)
1048 #define CAN_CTRL1_BOFFREC_MASK 0x40u
1049 #define CAN_CTRL1_BOFFREC_SHIFT 6u
1050 #define CAN_CTRL1_BOFFREC_WIDTH 1u
1051 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFREC_SHIFT))&CAN_CTRL1_BOFFREC_MASK)
1052 #define CAN_CTRL1_SMP_MASK 0x80u
1053 #define CAN_CTRL1_SMP_SHIFT 7u
1054 #define CAN_CTRL1_SMP_WIDTH 1u
1055 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_SMP_SHIFT))&CAN_CTRL1_SMP_MASK)
1056 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
1057 #define CAN_CTRL1_RWRNMSK_SHIFT 10u
1058 #define CAN_CTRL1_RWRNMSK_WIDTH 1u
1059 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RWRNMSK_SHIFT))&CAN_CTRL1_RWRNMSK_MASK)
1060 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
1061 #define CAN_CTRL1_TWRNMSK_SHIFT 11u
1062 #define CAN_CTRL1_TWRNMSK_WIDTH 1u
1063 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_TWRNMSK_SHIFT))&CAN_CTRL1_TWRNMSK_MASK)
1064 #define CAN_CTRL1_LPB_MASK 0x1000u
1065 #define CAN_CTRL1_LPB_SHIFT 12u
1066 #define CAN_CTRL1_LPB_WIDTH 1u
1067 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_LPB_SHIFT))&CAN_CTRL1_LPB_MASK)
1068 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1069 #define CAN_CTRL1_CLKSRC_SHIFT 13u
1070 #define CAN_CTRL1_CLKSRC_WIDTH 1u
1071 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_CLKSRC_SHIFT))&CAN_CTRL1_CLKSRC_MASK)
1072 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1073 #define CAN_CTRL1_ERRMSK_SHIFT 14u
1074 #define CAN_CTRL1_ERRMSK_WIDTH 1u
1075 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_ERRMSK_SHIFT))&CAN_CTRL1_ERRMSK_MASK)
1076 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1077 #define CAN_CTRL1_BOFFMSK_SHIFT 15u
1078 #define CAN_CTRL1_BOFFMSK_WIDTH 1u
1079 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_BOFFMSK_SHIFT))&CAN_CTRL1_BOFFMSK_MASK)
1080 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1081 #define CAN_CTRL1_PSEG2_SHIFT 16u
1082 #define CAN_CTRL1_PSEG2_WIDTH 3u
1083 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1084 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1085 #define CAN_CTRL1_PSEG1_SHIFT 19u
1086 #define CAN_CTRL1_PSEG1_WIDTH 3u
1087 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1088 #define CAN_CTRL1_RJW_MASK 0xC00000u
1089 #define CAN_CTRL1_RJW_SHIFT 22u
1090 #define CAN_CTRL1_RJW_WIDTH 2u
1091 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1092 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
1093 #define CAN_CTRL1_PRESDIV_SHIFT 24u
1094 #define CAN_CTRL1_PRESDIV_WIDTH 8u
1095 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
1096 /* TIMER Bit Fields */
1097 #define CAN_TIMER_TIMER_MASK 0xFFFFu
1098 #define CAN_TIMER_TIMER_SHIFT 0u
1099 #define CAN_TIMER_TIMER_WIDTH 16u
1100 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
1101 /* RXMGMASK Bit Fields */
1102 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
1103 #define CAN_RXMGMASK_MG_SHIFT 0u
1104 #define CAN_RXMGMASK_MG_WIDTH 32u
1105 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
1106 /* RX14MASK Bit Fields */
1107 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
1108 #define CAN_RX14MASK_RX14M_SHIFT 0u
1109 #define CAN_RX14MASK_RX14M_WIDTH 32u
1110 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
1111 /* RX15MASK Bit Fields */
1112 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
1113 #define CAN_RX15MASK_RX15M_SHIFT 0u
1114 #define CAN_RX15MASK_RX15M_WIDTH 32u
1115 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
1116 /* ECR Bit Fields */
1117 #define CAN_ECR_TXERRCNT_MASK 0xFFu
1118 #define CAN_ECR_TXERRCNT_SHIFT 0u
1119 #define CAN_ECR_TXERRCNT_WIDTH 8u
1120 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
1121 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
1122 #define CAN_ECR_RXERRCNT_SHIFT 8u
1123 #define CAN_ECR_RXERRCNT_WIDTH 8u
1124 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
1125 #define CAN_ECR_TXERRCNT_FAST_MASK 0xFF0000u
1126 #define CAN_ECR_TXERRCNT_FAST_SHIFT 16u
1127 #define CAN_ECR_TXERRCNT_FAST_WIDTH 8u
1128 #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_FAST_SHIFT))&CAN_ECR_TXERRCNT_FAST_MASK)
1129 #define CAN_ECR_RXERRCNT_FAST_MASK 0xFF000000u
1130 #define CAN_ECR_RXERRCNT_FAST_SHIFT 24u
1131 #define CAN_ECR_RXERRCNT_FAST_WIDTH 8u
1132 #define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_FAST_SHIFT))&CAN_ECR_RXERRCNT_FAST_MASK)
1133 /* ESR1 Bit Fields */
1134 #define CAN_ESR1_ERRINT_MASK 0x2u
1135 #define CAN_ESR1_ERRINT_SHIFT 1u
1136 #define CAN_ESR1_ERRINT_WIDTH 1u
1137 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_SHIFT))&CAN_ESR1_ERRINT_MASK)
1138 #define CAN_ESR1_BOFFINT_MASK 0x4u
1139 #define CAN_ESR1_BOFFINT_SHIFT 2u
1140 #define CAN_ESR1_BOFFINT_WIDTH 1u
1141 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFINT_SHIFT))&CAN_ESR1_BOFFINT_MASK)
1142 #define CAN_ESR1_RX_MASK 0x8u
1143 #define CAN_ESR1_RX_SHIFT 3u
1144 #define CAN_ESR1_RX_WIDTH 1u
1145 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RX_SHIFT))&CAN_ESR1_RX_MASK)
1146 #define CAN_ESR1_FLTCONF_MASK 0x30u
1147 #define CAN_ESR1_FLTCONF_SHIFT 4u
1148 #define CAN_ESR1_FLTCONF_WIDTH 2u
1149 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
1150 #define CAN_ESR1_TX_MASK 0x40u
1151 #define CAN_ESR1_TX_SHIFT 6u
1152 #define CAN_ESR1_TX_WIDTH 1u
1153 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TX_SHIFT))&CAN_ESR1_TX_MASK)
1154 #define CAN_ESR1_IDLE_MASK 0x80u
1155 #define CAN_ESR1_IDLE_SHIFT 7u
1156 #define CAN_ESR1_IDLE_WIDTH 1u
1157 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_IDLE_SHIFT))&CAN_ESR1_IDLE_MASK)
1158 #define CAN_ESR1_RXWRN_MASK 0x100u
1159 #define CAN_ESR1_RXWRN_SHIFT 8u
1160 #define CAN_ESR1_RXWRN_WIDTH 1u
1161 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RXWRN_SHIFT))&CAN_ESR1_RXWRN_MASK)
1162 #define CAN_ESR1_TXWRN_MASK 0x200u
1163 #define CAN_ESR1_TXWRN_SHIFT 9u
1164 #define CAN_ESR1_TXWRN_WIDTH 1u
1165 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TXWRN_SHIFT))&CAN_ESR1_TXWRN_MASK)
1166 #define CAN_ESR1_STFERR_MASK 0x400u
1167 #define CAN_ESR1_STFERR_SHIFT 10u
1168 #define CAN_ESR1_STFERR_WIDTH 1u
1169 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_SHIFT))&CAN_ESR1_STFERR_MASK)
1170 #define CAN_ESR1_FRMERR_MASK 0x800u
1171 #define CAN_ESR1_FRMERR_SHIFT 11u
1172 #define CAN_ESR1_FRMERR_WIDTH 1u
1173 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_SHIFT))&CAN_ESR1_FRMERR_MASK)
1174 #define CAN_ESR1_CRCERR_MASK 0x1000u
1175 #define CAN_ESR1_CRCERR_SHIFT 12u
1176 #define CAN_ESR1_CRCERR_WIDTH 1u
1177 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_SHIFT))&CAN_ESR1_CRCERR_MASK)
1178 #define CAN_ESR1_ACKERR_MASK 0x2000u
1179 #define CAN_ESR1_ACKERR_SHIFT 13u
1180 #define CAN_ESR1_ACKERR_WIDTH 1u
1181 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ACKERR_SHIFT))&CAN_ESR1_ACKERR_MASK)
1182 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
1183 #define CAN_ESR1_BIT0ERR_SHIFT 14u
1184 #define CAN_ESR1_BIT0ERR_WIDTH 1u
1185 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_SHIFT))&CAN_ESR1_BIT0ERR_MASK)
1186 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
1187 #define CAN_ESR1_BIT1ERR_SHIFT 15u
1188 #define CAN_ESR1_BIT1ERR_WIDTH 1u
1189 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_SHIFT))&CAN_ESR1_BIT1ERR_MASK)
1190 #define CAN_ESR1_RWRNINT_MASK 0x10000u
1191 #define CAN_ESR1_RWRNINT_SHIFT 16u
1192 #define CAN_ESR1_RWRNINT_WIDTH 1u
1193 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_RWRNINT_SHIFT))&CAN_ESR1_RWRNINT_MASK)
1194 #define CAN_ESR1_TWRNINT_MASK 0x20000u
1195 #define CAN_ESR1_TWRNINT_SHIFT 17u
1196 #define CAN_ESR1_TWRNINT_WIDTH 1u
1197 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_TWRNINT_SHIFT))&CAN_ESR1_TWRNINT_MASK)
1198 #define CAN_ESR1_SYNCH_MASK 0x40000u
1199 #define CAN_ESR1_SYNCH_SHIFT 18u
1200 #define CAN_ESR1_SYNCH_WIDTH 1u
1201 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_SYNCH_SHIFT))&CAN_ESR1_SYNCH_MASK)
1202 #define CAN_ESR1_BOFFDONEINT_MASK 0x80000u
1203 #define CAN_ESR1_BOFFDONEINT_SHIFT 19u
1204 #define CAN_ESR1_BOFFDONEINT_WIDTH 1u
1205 #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BOFFDONEINT_SHIFT))&CAN_ESR1_BOFFDONEINT_MASK)
1206 #define CAN_ESR1_ERRINT_FAST_MASK 0x100000u
1207 #define CAN_ESR1_ERRINT_FAST_SHIFT 20u
1208 #define CAN_ESR1_ERRINT_FAST_WIDTH 1u
1209 #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERRINT_FAST_SHIFT))&CAN_ESR1_ERRINT_FAST_MASK)
1210 #define CAN_ESR1_ERROVR_MASK 0x200000u
1211 #define CAN_ESR1_ERROVR_SHIFT 21u
1212 #define CAN_ESR1_ERROVR_WIDTH 1u
1213 #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_ERROVR_SHIFT))&CAN_ESR1_ERROVR_MASK)
1214 #define CAN_ESR1_STFERR_FAST_MASK 0x4000000u
1215 #define CAN_ESR1_STFERR_FAST_SHIFT 26u
1216 #define CAN_ESR1_STFERR_FAST_WIDTH 1u
1217 #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_STFERR_FAST_SHIFT))&CAN_ESR1_STFERR_FAST_MASK)
1218 #define CAN_ESR1_FRMERR_FAST_MASK 0x8000000u
1219 #define CAN_ESR1_FRMERR_FAST_SHIFT 27u
1220 #define CAN_ESR1_FRMERR_FAST_WIDTH 1u
1221 #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FRMERR_FAST_SHIFT))&CAN_ESR1_FRMERR_FAST_MASK)
1222 #define CAN_ESR1_CRCERR_FAST_MASK 0x10000000u
1223 #define CAN_ESR1_CRCERR_FAST_SHIFT 28u
1224 #define CAN_ESR1_CRCERR_FAST_WIDTH 1u
1225 #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_CRCERR_FAST_SHIFT))&CAN_ESR1_CRCERR_FAST_MASK)
1226 #define CAN_ESR1_BIT0ERR_FAST_MASK 0x40000000u
1227 #define CAN_ESR1_BIT0ERR_FAST_SHIFT 30u
1228 #define CAN_ESR1_BIT0ERR_FAST_WIDTH 1u
1229 #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT0ERR_FAST_SHIFT))&CAN_ESR1_BIT0ERR_FAST_MASK)
1230 #define CAN_ESR1_BIT1ERR_FAST_MASK 0x80000000u
1231 #define CAN_ESR1_BIT1ERR_FAST_SHIFT 31u
1232 #define CAN_ESR1_BIT1ERR_FAST_WIDTH 1u
1233 #define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_BIT1ERR_FAST_SHIFT))&CAN_ESR1_BIT1ERR_FAST_MASK)
1234 /* IMASK1 Bit Fields */
1235 #define CAN_IMASK1_BUF31TO0M_MASK 0xFFFFFFFFu
1236 #define CAN_IMASK1_BUF31TO0M_SHIFT 0u
1237 #define CAN_IMASK1_BUF31TO0M_WIDTH 32u
1238 #define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUF31TO0M_SHIFT))&CAN_IMASK1_BUF31TO0M_MASK)
1239 /* IFLAG1 Bit Fields */
1240 #define CAN_IFLAG1_BUF0I_MASK 0x1u
1241 #define CAN_IFLAG1_BUF0I_SHIFT 0u
1242 #define CAN_IFLAG1_BUF0I_WIDTH 1u
1243 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF0I_SHIFT))&CAN_IFLAG1_BUF0I_MASK)
1244 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
1245 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1u
1246 #define CAN_IFLAG1_BUF4TO1I_WIDTH 4u
1247 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
1248 #define CAN_IFLAG1_BUF5I_MASK 0x20u
1249 #define CAN_IFLAG1_BUF5I_SHIFT 5u
1250 #define CAN_IFLAG1_BUF5I_WIDTH 1u
1251 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF5I_SHIFT))&CAN_IFLAG1_BUF5I_MASK)
1252 #define CAN_IFLAG1_BUF6I_MASK 0x40u
1253 #define CAN_IFLAG1_BUF6I_SHIFT 6u
1254 #define CAN_IFLAG1_BUF6I_WIDTH 1u
1255 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF6I_SHIFT))&CAN_IFLAG1_BUF6I_MASK)
1256 #define CAN_IFLAG1_BUF7I_MASK 0x80u
1257 #define CAN_IFLAG1_BUF7I_SHIFT 7u
1258 #define CAN_IFLAG1_BUF7I_WIDTH 1u
1259 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF7I_SHIFT))&CAN_IFLAG1_BUF7I_MASK)
1260 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
1261 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8u
1262 #define CAN_IFLAG1_BUF31TO8I_WIDTH 24u
1263 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
1264 /* CTRL2 Bit Fields */
1265 #define CAN_CTRL2_EDFLTDIS_MASK 0x800u
1266 #define CAN_CTRL2_EDFLTDIS_SHIFT 11u
1267 #define CAN_CTRL2_EDFLTDIS_WIDTH 1u
1268 #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EDFLTDIS_SHIFT))&CAN_CTRL2_EDFLTDIS_MASK)
1269 #define CAN_CTRL2_ISOCANFDEN_MASK 0x1000u
1270 #define CAN_CTRL2_ISOCANFDEN_SHIFT 12u
1271 #define CAN_CTRL2_ISOCANFDEN_WIDTH 1u
1272 #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ISOCANFDEN_SHIFT))&CAN_CTRL2_ISOCANFDEN_MASK)
1273 #define CAN_CTRL2_PREXCEN_MASK 0x4000u
1274 #define CAN_CTRL2_PREXCEN_SHIFT 14u
1275 #define CAN_CTRL2_PREXCEN_WIDTH 1u
1276 #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PREXCEN_SHIFT))&CAN_CTRL2_PREXCEN_MASK)
1277 #define CAN_CTRL2_TIMER_SRC_MASK 0x8000u
1278 #define CAN_CTRL2_TIMER_SRC_SHIFT 15u
1279 #define CAN_CTRL2_TIMER_SRC_WIDTH 1u
1280 #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TIMER_SRC_SHIFT))&CAN_CTRL2_TIMER_SRC_MASK)
1281 #define CAN_CTRL2_EACEN_MASK 0x10000u
1282 #define CAN_CTRL2_EACEN_SHIFT 16u
1283 #define CAN_CTRL2_EACEN_WIDTH 1u
1284 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_EACEN_SHIFT))&CAN_CTRL2_EACEN_MASK)
1285 #define CAN_CTRL2_RRS_MASK 0x20000u
1286 #define CAN_CTRL2_RRS_SHIFT 17u
1287 #define CAN_CTRL2_RRS_WIDTH 1u
1288 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RRS_SHIFT))&CAN_CTRL2_RRS_MASK)
1289 #define CAN_CTRL2_MRP_MASK 0x40000u
1290 #define CAN_CTRL2_MRP_SHIFT 18u
1291 #define CAN_CTRL2_MRP_WIDTH 1u
1292 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_MRP_SHIFT))&CAN_CTRL2_MRP_MASK)
1293 #define CAN_CTRL2_TASD_MASK 0xF80000u
1294 #define CAN_CTRL2_TASD_SHIFT 19u
1295 #define CAN_CTRL2_TASD_WIDTH 5u
1296 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
1297 #define CAN_CTRL2_RFFN_MASK 0xF000000u
1298 #define CAN_CTRL2_RFFN_SHIFT 24u
1299 #define CAN_CTRL2_RFFN_WIDTH 4u
1300 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
1301 #define CAN_CTRL2_BOFFDONEMSK_MASK 0x40000000u
1302 #define CAN_CTRL2_BOFFDONEMSK_SHIFT 30u
1303 #define CAN_CTRL2_BOFFDONEMSK_WIDTH 1u
1304 #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_BOFFDONEMSK_SHIFT))&CAN_CTRL2_BOFFDONEMSK_MASK)
1305 #define CAN_CTRL2_ERRMSK_FAST_MASK 0x80000000u
1306 #define CAN_CTRL2_ERRMSK_FAST_SHIFT 31u
1307 #define CAN_CTRL2_ERRMSK_FAST_WIDTH 1u
1308 #define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_ERRMSK_FAST_SHIFT))&CAN_CTRL2_ERRMSK_FAST_MASK)
1309 /* ESR2 Bit Fields */
1310 #define CAN_ESR2_IMB_MASK 0x2000u
1311 #define CAN_ESR2_IMB_SHIFT 13u
1312 #define CAN_ESR2_IMB_WIDTH 1u
1313 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_IMB_SHIFT))&CAN_ESR2_IMB_MASK)
1314 #define CAN_ESR2_VPS_MASK 0x4000u
1315 #define CAN_ESR2_VPS_SHIFT 14u
1316 #define CAN_ESR2_VPS_WIDTH 1u
1317 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_VPS_SHIFT))&CAN_ESR2_VPS_MASK)
1318 #define CAN_ESR2_LPTM_MASK 0x7F0000u
1319 #define CAN_ESR2_LPTM_SHIFT 16u
1320 #define CAN_ESR2_LPTM_WIDTH 7u
1321 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
1322 /* CRCR Bit Fields */
1323 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
1324 #define CAN_CRCR_TXCRC_SHIFT 0u
1325 #define CAN_CRCR_TXCRC_WIDTH 15u
1326 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
1327 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
1328 #define CAN_CRCR_MBCRC_SHIFT 16u
1329 #define CAN_CRCR_MBCRC_WIDTH 7u
1330 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
1331 /* RXFGMASK Bit Fields */
1332 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
1333 #define CAN_RXFGMASK_FGM_SHIFT 0u
1334 #define CAN_RXFGMASK_FGM_WIDTH 32u
1335 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
1336 /* RXFIR Bit Fields */
1337 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
1338 #define CAN_RXFIR_IDHIT_SHIFT 0u
1339 #define CAN_RXFIR_IDHIT_WIDTH 9u
1340 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
1341 /* CBT Bit Fields */
1342 #define CAN_CBT_EPSEG2_MASK 0x1Fu
1343 #define CAN_CBT_EPSEG2_SHIFT 0u
1344 #define CAN_CBT_EPSEG2_WIDTH 5u
1345 #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG2_SHIFT))&CAN_CBT_EPSEG2_MASK)
1346 #define CAN_CBT_EPSEG1_MASK 0x3E0u
1347 #define CAN_CBT_EPSEG1_SHIFT 5u
1348 #define CAN_CBT_EPSEG1_WIDTH 5u
1349 #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPSEG1_SHIFT))&CAN_CBT_EPSEG1_MASK)
1350 #define CAN_CBT_EPROPSEG_MASK 0xFC00u
1351 #define CAN_CBT_EPROPSEG_SHIFT 10u
1352 #define CAN_CBT_EPROPSEG_WIDTH 6u
1353 #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPROPSEG_SHIFT))&CAN_CBT_EPROPSEG_MASK)
1354 #define CAN_CBT_ERJW_MASK 0x1F0000u
1355 #define CAN_CBT_ERJW_SHIFT 16u
1356 #define CAN_CBT_ERJW_WIDTH 5u
1357 #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_ERJW_SHIFT))&CAN_CBT_ERJW_MASK)
1358 #define CAN_CBT_EPRESDIV_MASK 0x7FE00000u
1359 #define CAN_CBT_EPRESDIV_SHIFT 21u
1360 #define CAN_CBT_EPRESDIV_WIDTH 10u
1361 #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_EPRESDIV_SHIFT))&CAN_CBT_EPRESDIV_MASK)
1362 #define CAN_CBT_BTF_MASK 0x80000000u
1363 #define CAN_CBT_BTF_SHIFT 31u
1364 #define CAN_CBT_BTF_WIDTH 1u
1365 #define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x))<<CAN_CBT_BTF_SHIFT))&CAN_CBT_BTF_MASK)
1366 /* RAMn Bit Fields */
1367 #define CAN_RAMn_DATA_BYTE_3_MASK 0xFFu
1368 #define CAN_RAMn_DATA_BYTE_3_SHIFT 0u
1369 #define CAN_RAMn_DATA_BYTE_3_WIDTH 8u
1370 #define CAN_RAMn_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_3_SHIFT))&CAN_RAMn_DATA_BYTE_3_MASK)
1371 #define CAN_RAMn_DATA_BYTE_2_MASK 0xFF00u
1372 #define CAN_RAMn_DATA_BYTE_2_SHIFT 8u
1373 #define CAN_RAMn_DATA_BYTE_2_WIDTH 8u
1374 #define CAN_RAMn_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_2_SHIFT))&CAN_RAMn_DATA_BYTE_2_MASK)
1375 #define CAN_RAMn_DATA_BYTE_1_MASK 0xFF0000u
1376 #define CAN_RAMn_DATA_BYTE_1_SHIFT 16u
1377 #define CAN_RAMn_DATA_BYTE_1_WIDTH 8u
1378 #define CAN_RAMn_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_1_SHIFT))&CAN_RAMn_DATA_BYTE_1_MASK)
1379 #define CAN_RAMn_DATA_BYTE_0_MASK 0xFF000000u
1380 #define CAN_RAMn_DATA_BYTE_0_SHIFT 24u
1381 #define CAN_RAMn_DATA_BYTE_0_WIDTH 8u
1382 #define CAN_RAMn_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_RAMn_DATA_BYTE_0_SHIFT))&CAN_RAMn_DATA_BYTE_0_MASK)
1383 /* RXIMR Bit Fields */
1384 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
1385 #define CAN_RXIMR_MI_SHIFT 0u
1386 #define CAN_RXIMR_MI_WIDTH 32u
1387 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
1388 /* CTRL1_PN Bit Fields */
1389 #define CAN_CTRL1_PN_FCS_MASK 0x3u
1390 #define CAN_CTRL1_PN_FCS_SHIFT 0u
1391 #define CAN_CTRL1_PN_FCS_WIDTH 2u
1392 #define CAN_CTRL1_PN_FCS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_FCS_SHIFT))&CAN_CTRL1_PN_FCS_MASK)
1393 #define CAN_CTRL1_PN_IDFS_MASK 0xCu
1394 #define CAN_CTRL1_PN_IDFS_SHIFT 2u
1395 #define CAN_CTRL1_PN_IDFS_WIDTH 2u
1396 #define CAN_CTRL1_PN_IDFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_IDFS_SHIFT))&CAN_CTRL1_PN_IDFS_MASK)
1397 #define CAN_CTRL1_PN_PLFS_MASK 0x30u
1398 #define CAN_CTRL1_PN_PLFS_SHIFT 4u
1399 #define CAN_CTRL1_PN_PLFS_WIDTH 2u
1400 #define CAN_CTRL1_PN_PLFS(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_PLFS_SHIFT))&CAN_CTRL1_PN_PLFS_MASK)
1401 #define CAN_CTRL1_PN_NMATCH_MASK 0xFF00u
1402 #define CAN_CTRL1_PN_NMATCH_SHIFT 8u
1403 #define CAN_CTRL1_PN_NMATCH_WIDTH 8u
1404 #define CAN_CTRL1_PN_NMATCH(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_NMATCH_SHIFT))&CAN_CTRL1_PN_NMATCH_MASK)
1405 #define CAN_CTRL1_PN_WUMF_MSK_MASK 0x10000u
1406 #define CAN_CTRL1_PN_WUMF_MSK_SHIFT 16u
1407 #define CAN_CTRL1_PN_WUMF_MSK_WIDTH 1u
1408 #define CAN_CTRL1_PN_WUMF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WUMF_MSK_SHIFT))&CAN_CTRL1_PN_WUMF_MSK_MASK)
1409 #define CAN_CTRL1_PN_WTOF_MSK_MASK 0x20000u
1410 #define CAN_CTRL1_PN_WTOF_MSK_SHIFT 17u
1411 #define CAN_CTRL1_PN_WTOF_MSK_WIDTH 1u
1412 #define CAN_CTRL1_PN_WTOF_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PN_WTOF_MSK_SHIFT))&CAN_CTRL1_PN_WTOF_MSK_MASK)
1413 /* CTRL2_PN Bit Fields */
1414 #define CAN_CTRL2_PN_MATCHTO_MASK 0xFFFFu
1415 #define CAN_CTRL2_PN_MATCHTO_SHIFT 0u
1416 #define CAN_CTRL2_PN_MATCHTO_WIDTH 16u
1417 #define CAN_CTRL2_PN_MATCHTO(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_PN_MATCHTO_SHIFT))&CAN_CTRL2_PN_MATCHTO_MASK)
1418 /* WU_MTC Bit Fields */
1419 #define CAN_WU_MTC_MCOUNTER_MASK 0xFF00u
1420 #define CAN_WU_MTC_MCOUNTER_SHIFT 8u
1421 #define CAN_WU_MTC_MCOUNTER_WIDTH 8u
1422 #define CAN_WU_MTC_MCOUNTER(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_MCOUNTER_SHIFT))&CAN_WU_MTC_MCOUNTER_MASK)
1423 #define CAN_WU_MTC_WUMF_MASK 0x10000u
1424 #define CAN_WU_MTC_WUMF_SHIFT 16u
1425 #define CAN_WU_MTC_WUMF_WIDTH 1u
1426 #define CAN_WU_MTC_WUMF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WUMF_SHIFT))&CAN_WU_MTC_WUMF_MASK)
1427 #define CAN_WU_MTC_WTOF_MASK 0x20000u
1428 #define CAN_WU_MTC_WTOF_SHIFT 17u
1429 #define CAN_WU_MTC_WTOF_WIDTH 1u
1430 #define CAN_WU_MTC_WTOF(x) (((uint32_t)(((uint32_t)(x))<<CAN_WU_MTC_WTOF_SHIFT))&CAN_WU_MTC_WTOF_MASK)
1431 /* FLT_ID1 Bit Fields */
1432 #define CAN_FLT_ID1_FLT_ID1_MASK 0x1FFFFFFFu
1433 #define CAN_FLT_ID1_FLT_ID1_SHIFT 0u
1434 #define CAN_FLT_ID1_FLT_ID1_WIDTH 29u
1435 #define CAN_FLT_ID1_FLT_ID1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_ID1_SHIFT))&CAN_FLT_ID1_FLT_ID1_MASK)
1436 #define CAN_FLT_ID1_FLT_RTR_MASK 0x20000000u
1437 #define CAN_FLT_ID1_FLT_RTR_SHIFT 29u
1438 #define CAN_FLT_ID1_FLT_RTR_WIDTH 1u
1439 #define CAN_FLT_ID1_FLT_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_RTR_SHIFT))&CAN_FLT_ID1_FLT_RTR_MASK)
1440 #define CAN_FLT_ID1_FLT_IDE_MASK 0x40000000u
1441 #define CAN_FLT_ID1_FLT_IDE_SHIFT 30u
1442 #define CAN_FLT_ID1_FLT_IDE_WIDTH 1u
1443 #define CAN_FLT_ID1_FLT_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID1_FLT_IDE_SHIFT))&CAN_FLT_ID1_FLT_IDE_MASK)
1444 /* FLT_DLC Bit Fields */
1445 #define CAN_FLT_DLC_FLT_DLC_HI_MASK 0xFu
1446 #define CAN_FLT_DLC_FLT_DLC_HI_SHIFT 0u
1447 #define CAN_FLT_DLC_FLT_DLC_HI_WIDTH 4u
1448 #define CAN_FLT_DLC_FLT_DLC_HI(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_HI_SHIFT))&CAN_FLT_DLC_FLT_DLC_HI_MASK)
1449 #define CAN_FLT_DLC_FLT_DLC_LO_MASK 0xF0000u
1450 #define CAN_FLT_DLC_FLT_DLC_LO_SHIFT 16u
1451 #define CAN_FLT_DLC_FLT_DLC_LO_WIDTH 4u
1452 #define CAN_FLT_DLC_FLT_DLC_LO(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_DLC_FLT_DLC_LO_SHIFT))&CAN_FLT_DLC_FLT_DLC_LO_MASK)
1453 /* PL1_LO Bit Fields */
1454 #define CAN_PL1_LO_Data_byte_3_MASK 0xFFu
1455 #define CAN_PL1_LO_Data_byte_3_SHIFT 0u
1456 #define CAN_PL1_LO_Data_byte_3_WIDTH 8u
1457 #define CAN_PL1_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_3_SHIFT))&CAN_PL1_LO_Data_byte_3_MASK)
1458 #define CAN_PL1_LO_Data_byte_2_MASK 0xFF00u
1459 #define CAN_PL1_LO_Data_byte_2_SHIFT 8u
1460 #define CAN_PL1_LO_Data_byte_2_WIDTH 8u
1461 #define CAN_PL1_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_2_SHIFT))&CAN_PL1_LO_Data_byte_2_MASK)
1462 #define CAN_PL1_LO_Data_byte_1_MASK 0xFF0000u
1463 #define CAN_PL1_LO_Data_byte_1_SHIFT 16u
1464 #define CAN_PL1_LO_Data_byte_1_WIDTH 8u
1465 #define CAN_PL1_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_1_SHIFT))&CAN_PL1_LO_Data_byte_1_MASK)
1466 #define CAN_PL1_LO_Data_byte_0_MASK 0xFF000000u
1467 #define CAN_PL1_LO_Data_byte_0_SHIFT 24u
1468 #define CAN_PL1_LO_Data_byte_0_WIDTH 8u
1469 #define CAN_PL1_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_LO_Data_byte_0_SHIFT))&CAN_PL1_LO_Data_byte_0_MASK)
1470 /* PL1_HI Bit Fields */
1471 #define CAN_PL1_HI_Data_byte_7_MASK 0xFFu
1472 #define CAN_PL1_HI_Data_byte_7_SHIFT 0u
1473 #define CAN_PL1_HI_Data_byte_7_WIDTH 8u
1474 #define CAN_PL1_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_7_SHIFT))&CAN_PL1_HI_Data_byte_7_MASK)
1475 #define CAN_PL1_HI_Data_byte_6_MASK 0xFF00u
1476 #define CAN_PL1_HI_Data_byte_6_SHIFT 8u
1477 #define CAN_PL1_HI_Data_byte_6_WIDTH 8u
1478 #define CAN_PL1_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_6_SHIFT))&CAN_PL1_HI_Data_byte_6_MASK)
1479 #define CAN_PL1_HI_Data_byte_5_MASK 0xFF0000u
1480 #define CAN_PL1_HI_Data_byte_5_SHIFT 16u
1481 #define CAN_PL1_HI_Data_byte_5_WIDTH 8u
1482 #define CAN_PL1_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_5_SHIFT))&CAN_PL1_HI_Data_byte_5_MASK)
1483 #define CAN_PL1_HI_Data_byte_4_MASK 0xFF000000u
1484 #define CAN_PL1_HI_Data_byte_4_SHIFT 24u
1485 #define CAN_PL1_HI_Data_byte_4_WIDTH 8u
1486 #define CAN_PL1_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL1_HI_Data_byte_4_SHIFT))&CAN_PL1_HI_Data_byte_4_MASK)
1487 /* FLT_ID2_IDMASK Bit Fields */
1488 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK 0x1FFFFFFFu
1489 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT 0u
1490 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_WIDTH 29u
1491 #define CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_SHIFT))&CAN_FLT_ID2_IDMASK_FLT_ID2_IDMASK_MASK)
1492 #define CAN_FLT_ID2_IDMASK_RTR_MSK_MASK 0x20000000u
1493 #define CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT 29u
1494 #define CAN_FLT_ID2_IDMASK_RTR_MSK_WIDTH 1u
1495 #define CAN_FLT_ID2_IDMASK_RTR_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_RTR_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_RTR_MSK_MASK)
1496 #define CAN_FLT_ID2_IDMASK_IDE_MSK_MASK 0x40000000u
1497 #define CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT 30u
1498 #define CAN_FLT_ID2_IDMASK_IDE_MSK_WIDTH 1u
1499 #define CAN_FLT_ID2_IDMASK_IDE_MSK(x) (((uint32_t)(((uint32_t)(x))<<CAN_FLT_ID2_IDMASK_IDE_MSK_SHIFT))&CAN_FLT_ID2_IDMASK_IDE_MSK_MASK)
1500 /* PL2_PLMASK_LO Bit Fields */
1501 #define CAN_PL2_PLMASK_LO_Data_byte_3_MASK 0xFFu
1502 #define CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT 0u
1503 #define CAN_PL2_PLMASK_LO_Data_byte_3_WIDTH 8u
1504 #define CAN_PL2_PLMASK_LO_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_3_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_3_MASK)
1505 #define CAN_PL2_PLMASK_LO_Data_byte_2_MASK 0xFF00u
1506 #define CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT 8u
1507 #define CAN_PL2_PLMASK_LO_Data_byte_2_WIDTH 8u
1508 #define CAN_PL2_PLMASK_LO_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_2_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_2_MASK)
1509 #define CAN_PL2_PLMASK_LO_Data_byte_1_MASK 0xFF0000u
1510 #define CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT 16u
1511 #define CAN_PL2_PLMASK_LO_Data_byte_1_WIDTH 8u
1512 #define CAN_PL2_PLMASK_LO_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_1_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_1_MASK)
1513 #define CAN_PL2_PLMASK_LO_Data_byte_0_MASK 0xFF000000u
1514 #define CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT 24u
1515 #define CAN_PL2_PLMASK_LO_Data_byte_0_WIDTH 8u
1516 #define CAN_PL2_PLMASK_LO_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_LO_Data_byte_0_SHIFT))&CAN_PL2_PLMASK_LO_Data_byte_0_MASK)
1517 /* PL2_PLMASK_HI Bit Fields */
1518 #define CAN_PL2_PLMASK_HI_Data_byte_7_MASK 0xFFu
1519 #define CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT 0u
1520 #define CAN_PL2_PLMASK_HI_Data_byte_7_WIDTH 8u
1521 #define CAN_PL2_PLMASK_HI_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_7_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_7_MASK)
1522 #define CAN_PL2_PLMASK_HI_Data_byte_6_MASK 0xFF00u
1523 #define CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT 8u
1524 #define CAN_PL2_PLMASK_HI_Data_byte_6_WIDTH 8u
1525 #define CAN_PL2_PLMASK_HI_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_6_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_6_MASK)
1526 #define CAN_PL2_PLMASK_HI_Data_byte_5_MASK 0xFF0000u
1527 #define CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT 16u
1528 #define CAN_PL2_PLMASK_HI_Data_byte_5_WIDTH 8u
1529 #define CAN_PL2_PLMASK_HI_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_5_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_5_MASK)
1530 #define CAN_PL2_PLMASK_HI_Data_byte_4_MASK 0xFF000000u
1531 #define CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT 24u
1532 #define CAN_PL2_PLMASK_HI_Data_byte_4_WIDTH 8u
1533 #define CAN_PL2_PLMASK_HI_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_PL2_PLMASK_HI_Data_byte_4_SHIFT))&CAN_PL2_PLMASK_HI_Data_byte_4_MASK)
1534 /* WMBn_CS Bit Fields */
1535 #define CAN_WMBn_CS_DLC_MASK 0xF0000u
1536 #define CAN_WMBn_CS_DLC_SHIFT 16u
1537 #define CAN_WMBn_CS_DLC_WIDTH 4u
1538 #define CAN_WMBn_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_DLC_SHIFT))&CAN_WMBn_CS_DLC_MASK)
1539 #define CAN_WMBn_CS_RTR_MASK 0x100000u
1540 #define CAN_WMBn_CS_RTR_SHIFT 20u
1541 #define CAN_WMBn_CS_RTR_WIDTH 1u
1542 #define CAN_WMBn_CS_RTR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_RTR_SHIFT))&CAN_WMBn_CS_RTR_MASK)
1543 #define CAN_WMBn_CS_IDE_MASK 0x200000u
1544 #define CAN_WMBn_CS_IDE_SHIFT 21u
1545 #define CAN_WMBn_CS_IDE_WIDTH 1u
1546 #define CAN_WMBn_CS_IDE(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_IDE_SHIFT))&CAN_WMBn_CS_IDE_MASK)
1547 #define CAN_WMBn_CS_SRR_MASK 0x400000u
1548 #define CAN_WMBn_CS_SRR_SHIFT 22u
1549 #define CAN_WMBn_CS_SRR_WIDTH 1u
1550 #define CAN_WMBn_CS_SRR(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_CS_SRR_SHIFT))&CAN_WMBn_CS_SRR_MASK)
1551 /* WMBn_ID Bit Fields */
1552 #define CAN_WMBn_ID_ID_MASK 0x1FFFFFFFu
1553 #define CAN_WMBn_ID_ID_SHIFT 0u
1554 #define CAN_WMBn_ID_ID_WIDTH 29u
1555 #define CAN_WMBn_ID_ID(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_ID_ID_SHIFT))&CAN_WMBn_ID_ID_MASK)
1556 /* WMBn_D03 Bit Fields */
1557 #define CAN_WMBn_D03_Data_byte_3_MASK 0xFFu
1558 #define CAN_WMBn_D03_Data_byte_3_SHIFT 0u
1559 #define CAN_WMBn_D03_Data_byte_3_WIDTH 8u
1560 #define CAN_WMBn_D03_Data_byte_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_3_SHIFT))&CAN_WMBn_D03_Data_byte_3_MASK)
1561 #define CAN_WMBn_D03_Data_byte_2_MASK 0xFF00u
1562 #define CAN_WMBn_D03_Data_byte_2_SHIFT 8u
1563 #define CAN_WMBn_D03_Data_byte_2_WIDTH 8u
1564 #define CAN_WMBn_D03_Data_byte_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_2_SHIFT))&CAN_WMBn_D03_Data_byte_2_MASK)
1565 #define CAN_WMBn_D03_Data_byte_1_MASK 0xFF0000u
1566 #define CAN_WMBn_D03_Data_byte_1_SHIFT 16u
1567 #define CAN_WMBn_D03_Data_byte_1_WIDTH 8u
1568 #define CAN_WMBn_D03_Data_byte_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_1_SHIFT))&CAN_WMBn_D03_Data_byte_1_MASK)
1569 #define CAN_WMBn_D03_Data_byte_0_MASK 0xFF000000u
1570 #define CAN_WMBn_D03_Data_byte_0_SHIFT 24u
1571 #define CAN_WMBn_D03_Data_byte_0_WIDTH 8u
1572 #define CAN_WMBn_D03_Data_byte_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D03_Data_byte_0_SHIFT))&CAN_WMBn_D03_Data_byte_0_MASK)
1573 /* WMBn_D47 Bit Fields */
1574 #define CAN_WMBn_D47_Data_byte_7_MASK 0xFFu
1575 #define CAN_WMBn_D47_Data_byte_7_SHIFT 0u
1576 #define CAN_WMBn_D47_Data_byte_7_WIDTH 8u
1577 #define CAN_WMBn_D47_Data_byte_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_7_SHIFT))&CAN_WMBn_D47_Data_byte_7_MASK)
1578 #define CAN_WMBn_D47_Data_byte_6_MASK 0xFF00u
1579 #define CAN_WMBn_D47_Data_byte_6_SHIFT 8u
1580 #define CAN_WMBn_D47_Data_byte_6_WIDTH 8u
1581 #define CAN_WMBn_D47_Data_byte_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_6_SHIFT))&CAN_WMBn_D47_Data_byte_6_MASK)
1582 #define CAN_WMBn_D47_Data_byte_5_MASK 0xFF0000u
1583 #define CAN_WMBn_D47_Data_byte_5_SHIFT 16u
1584 #define CAN_WMBn_D47_Data_byte_5_WIDTH 8u
1585 #define CAN_WMBn_D47_Data_byte_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_5_SHIFT))&CAN_WMBn_D47_Data_byte_5_MASK)
1586 #define CAN_WMBn_D47_Data_byte_4_MASK 0xFF000000u
1587 #define CAN_WMBn_D47_Data_byte_4_SHIFT 24u
1588 #define CAN_WMBn_D47_Data_byte_4_WIDTH 8u
1589 #define CAN_WMBn_D47_Data_byte_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WMBn_D47_Data_byte_4_SHIFT))&CAN_WMBn_D47_Data_byte_4_MASK)
1590 /* FDCTRL Bit Fields */
1591 #define CAN_FDCTRL_TDCVAL_MASK 0x3Fu
1592 #define CAN_FDCTRL_TDCVAL_SHIFT 0u
1593 #define CAN_FDCTRL_TDCVAL_WIDTH 6u
1594 #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCVAL_SHIFT))&CAN_FDCTRL_TDCVAL_MASK)
1595 #define CAN_FDCTRL_TDCOFF_MASK 0x1F00u
1596 #define CAN_FDCTRL_TDCOFF_SHIFT 8u
1597 #define CAN_FDCTRL_TDCOFF_WIDTH 5u
1598 #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCOFF_SHIFT))&CAN_FDCTRL_TDCOFF_MASK)
1599 #define CAN_FDCTRL_TDCFAIL_MASK 0x4000u
1600 #define CAN_FDCTRL_TDCFAIL_SHIFT 14u
1601 #define CAN_FDCTRL_TDCFAIL_WIDTH 1u
1602 #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCFAIL_SHIFT))&CAN_FDCTRL_TDCFAIL_MASK)
1603 #define CAN_FDCTRL_TDCEN_MASK 0x8000u
1604 #define CAN_FDCTRL_TDCEN_SHIFT 15u
1605 #define CAN_FDCTRL_TDCEN_WIDTH 1u
1606 #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_TDCEN_SHIFT))&CAN_FDCTRL_TDCEN_MASK)
1607 #define CAN_FDCTRL_MBDSR0_MASK 0x30000u
1608 #define CAN_FDCTRL_MBDSR0_SHIFT 16u
1609 #define CAN_FDCTRL_MBDSR0_WIDTH 2u
1610 #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_MBDSR0_SHIFT))&CAN_FDCTRL_MBDSR0_MASK)
1611 #define CAN_FDCTRL_FDRATE_MASK 0x80000000u
1612 #define CAN_FDCTRL_FDRATE_SHIFT 31u
1613 #define CAN_FDCTRL_FDRATE_WIDTH 1u
1614 #define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCTRL_FDRATE_SHIFT))&CAN_FDCTRL_FDRATE_MASK)
1615 /* FDCBT Bit Fields */
1616 #define CAN_FDCBT_FPSEG2_MASK 0x7u
1617 #define CAN_FDCBT_FPSEG2_SHIFT 0u
1618 #define CAN_FDCBT_FPSEG2_WIDTH 3u
1619 #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG2_SHIFT))&CAN_FDCBT_FPSEG2_MASK)
1620 #define CAN_FDCBT_FPSEG1_MASK 0xE0u
1621 #define CAN_FDCBT_FPSEG1_SHIFT 5u
1622 #define CAN_FDCBT_FPSEG1_WIDTH 3u
1623 #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPSEG1_SHIFT))&CAN_FDCBT_FPSEG1_MASK)
1624 #define CAN_FDCBT_FPROPSEG_MASK 0x7C00u
1625 #define CAN_FDCBT_FPROPSEG_SHIFT 10u
1626 #define CAN_FDCBT_FPROPSEG_WIDTH 5u
1627 #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPROPSEG_SHIFT))&CAN_FDCBT_FPROPSEG_MASK)
1628 #define CAN_FDCBT_FRJW_MASK 0x70000u
1629 #define CAN_FDCBT_FRJW_SHIFT 16u
1630 #define CAN_FDCBT_FRJW_WIDTH 3u
1631 #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FRJW_SHIFT))&CAN_FDCBT_FRJW_MASK)
1632 #define CAN_FDCBT_FPRESDIV_MASK 0x3FF00000u
1633 #define CAN_FDCBT_FPRESDIV_SHIFT 20u
1634 #define CAN_FDCBT_FPRESDIV_WIDTH 10u
1635 #define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCBT_FPRESDIV_SHIFT))&CAN_FDCBT_FPRESDIV_MASK)
1636 /* FDCRC Bit Fields */
1637 #define CAN_FDCRC_FD_TXCRC_MASK 0x1FFFFFu
1638 #define CAN_FDCRC_FD_TXCRC_SHIFT 0u
1639 #define CAN_FDCRC_FD_TXCRC_WIDTH 21u
1640 #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_TXCRC_SHIFT))&CAN_FDCRC_FD_TXCRC_MASK)
1641 #define CAN_FDCRC_FD_MBCRC_MASK 0x7F000000u
1642 #define CAN_FDCRC_FD_MBCRC_SHIFT 24u
1643 #define CAN_FDCRC_FD_MBCRC_WIDTH 7u
1644 #define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_FDCRC_FD_MBCRC_SHIFT))&CAN_FDCRC_FD_MBCRC_MASK)
1645  /* end of group CAN_Register_Masks */
1649 
1650  /* end of group CAN_Peripheral_Access_Layer */
1654 
1655 
1656 /* ----------------------------------------------------------------------------
1657  -- CMP Peripheral Access Layer
1658  ---------------------------------------------------------------------------- */
1659 
1669 typedef struct {
1670  __IO uint32_t C0;
1671  __IO uint32_t C1;
1672  __IO uint32_t C2;
1674 
1676 #define CMP_INSTANCE_COUNT (1u)
1677 
1678 
1679 /* CMP - Peripheral instance base addresses */
1681 #define CMP0_BASE (0x40073000u)
1682 
1683 #define CMP0 ((CMP_Type *)CMP0_BASE)
1684 
1685 #define CMP_BASE_ADDRS { CMP0_BASE }
1686 
1687 #define CMP_BASE_PTRS { CMP0 }
1688 
1689 #define CMP_IRQS_ARR_COUNT (1u)
1690 
1691 #define CMP_IRQS_CH_COUNT (1u)
1692 
1693 #define CMP_IRQS { CMP0_IRQn }
1694 
1695 /* ----------------------------------------------------------------------------
1696  -- CMP Register Masks
1697  ---------------------------------------------------------------------------- */
1698 
1704 /* C0 Bit Fields */
1705 #define CMP_C0_HYSTCTR_MASK 0x3u
1706 #define CMP_C0_HYSTCTR_SHIFT 0u
1707 #define CMP_C0_HYSTCTR_WIDTH 2u
1708 #define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_HYSTCTR_SHIFT))&CMP_C0_HYSTCTR_MASK)
1709 #define CMP_C0_OFFSET_MASK 0x4u
1710 #define CMP_C0_OFFSET_SHIFT 2u
1711 #define CMP_C0_OFFSET_WIDTH 1u
1712 #define CMP_C0_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OFFSET_SHIFT))&CMP_C0_OFFSET_MASK)
1713 #define CMP_C0_FILTER_CNT_MASK 0x70u
1714 #define CMP_C0_FILTER_CNT_SHIFT 4u
1715 #define CMP_C0_FILTER_CNT_WIDTH 3u
1716 #define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FILTER_CNT_SHIFT))&CMP_C0_FILTER_CNT_MASK)
1717 #define CMP_C0_EN_MASK 0x100u
1718 #define CMP_C0_EN_SHIFT 8u
1719 #define CMP_C0_EN_WIDTH 1u
1720 #define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_EN_SHIFT))&CMP_C0_EN_MASK)
1721 #define CMP_C0_OPE_MASK 0x200u
1722 #define CMP_C0_OPE_SHIFT 9u
1723 #define CMP_C0_OPE_WIDTH 1u
1724 #define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_OPE_SHIFT))&CMP_C0_OPE_MASK)
1725 #define CMP_C0_COS_MASK 0x400u
1726 #define CMP_C0_COS_SHIFT 10u
1727 #define CMP_C0_COS_WIDTH 1u
1728 #define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COS_SHIFT))&CMP_C0_COS_MASK)
1729 #define CMP_C0_INVT_MASK 0x800u
1730 #define CMP_C0_INVT_SHIFT 11u
1731 #define CMP_C0_INVT_WIDTH 1u
1732 #define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_INVT_SHIFT))&CMP_C0_INVT_MASK)
1733 #define CMP_C0_PMODE_MASK 0x1000u
1734 #define CMP_C0_PMODE_SHIFT 12u
1735 #define CMP_C0_PMODE_WIDTH 1u
1736 #define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_PMODE_SHIFT))&CMP_C0_PMODE_MASK)
1737 #define CMP_C0_WE_MASK 0x4000u
1738 #define CMP_C0_WE_SHIFT 14u
1739 #define CMP_C0_WE_WIDTH 1u
1740 #define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_WE_SHIFT))&CMP_C0_WE_MASK)
1741 #define CMP_C0_SE_MASK 0x8000u
1742 #define CMP_C0_SE_SHIFT 15u
1743 #define CMP_C0_SE_WIDTH 1u
1744 #define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_SE_SHIFT))&CMP_C0_SE_MASK)
1745 #define CMP_C0_FPR_MASK 0xFF0000u
1746 #define CMP_C0_FPR_SHIFT 16u
1747 #define CMP_C0_FPR_WIDTH 8u
1748 #define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_FPR_SHIFT))&CMP_C0_FPR_MASK)
1749 #define CMP_C0_COUT_MASK 0x1000000u
1750 #define CMP_C0_COUT_SHIFT 24u
1751 #define CMP_C0_COUT_WIDTH 1u
1752 #define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_COUT_SHIFT))&CMP_C0_COUT_MASK)
1753 #define CMP_C0_CFF_MASK 0x2000000u
1754 #define CMP_C0_CFF_SHIFT 25u
1755 #define CMP_C0_CFF_WIDTH 1u
1756 #define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFF_SHIFT))&CMP_C0_CFF_MASK)
1757 #define CMP_C0_CFR_MASK 0x4000000u
1758 #define CMP_C0_CFR_SHIFT 26u
1759 #define CMP_C0_CFR_WIDTH 1u
1760 #define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_CFR_SHIFT))&CMP_C0_CFR_MASK)
1761 #define CMP_C0_IEF_MASK 0x8000000u
1762 #define CMP_C0_IEF_SHIFT 27u
1763 #define CMP_C0_IEF_WIDTH 1u
1764 #define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IEF_SHIFT))&CMP_C0_IEF_MASK)
1765 #define CMP_C0_IER_MASK 0x10000000u
1766 #define CMP_C0_IER_SHIFT 28u
1767 #define CMP_C0_IER_WIDTH 1u
1768 #define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_IER_SHIFT))&CMP_C0_IER_MASK)
1769 #define CMP_C0_DMAEN_MASK 0x40000000u
1770 #define CMP_C0_DMAEN_SHIFT 30u
1771 #define CMP_C0_DMAEN_WIDTH 1u
1772 #define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C0_DMAEN_SHIFT))&CMP_C0_DMAEN_MASK)
1773 /* C1 Bit Fields */
1774 #define CMP_C1_VOSEL_MASK 0xFFu
1775 #define CMP_C1_VOSEL_SHIFT 0u
1776 #define CMP_C1_VOSEL_WIDTH 8u
1777 #define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VOSEL_SHIFT))&CMP_C1_VOSEL_MASK)
1778 #define CMP_C1_MSEL_MASK 0x700u
1779 #define CMP_C1_MSEL_SHIFT 8u
1780 #define CMP_C1_MSEL_WIDTH 3u
1781 #define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_MSEL_SHIFT))&CMP_C1_MSEL_MASK)
1782 #define CMP_C1_PSEL_MASK 0x3800u
1783 #define CMP_C1_PSEL_SHIFT 11u
1784 #define CMP_C1_PSEL_WIDTH 3u
1785 #define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_PSEL_SHIFT))&CMP_C1_PSEL_MASK)
1786 #define CMP_C1_VRSEL_MASK 0x4000u
1787 #define CMP_C1_VRSEL_SHIFT 14u
1788 #define CMP_C1_VRSEL_WIDTH 1u
1789 #define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_VRSEL_SHIFT))&CMP_C1_VRSEL_MASK)
1790 #define CMP_C1_DACEN_MASK 0x8000u
1791 #define CMP_C1_DACEN_SHIFT 15u
1792 #define CMP_C1_DACEN_WIDTH 1u
1793 #define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_DACEN_SHIFT))&CMP_C1_DACEN_MASK)
1794 #define CMP_C1_CHN0_MASK 0x10000u
1795 #define CMP_C1_CHN0_SHIFT 16u
1796 #define CMP_C1_CHN0_WIDTH 1u
1797 #define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN0_SHIFT))&CMP_C1_CHN0_MASK)
1798 #define CMP_C1_CHN1_MASK 0x20000u
1799 #define CMP_C1_CHN1_SHIFT 17u
1800 #define CMP_C1_CHN1_WIDTH 1u
1801 #define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN1_SHIFT))&CMP_C1_CHN1_MASK)
1802 #define CMP_C1_CHN2_MASK 0x40000u
1803 #define CMP_C1_CHN2_SHIFT 18u
1804 #define CMP_C1_CHN2_WIDTH 1u
1805 #define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN2_SHIFT))&CMP_C1_CHN2_MASK)
1806 #define CMP_C1_CHN3_MASK 0x80000u
1807 #define CMP_C1_CHN3_SHIFT 19u
1808 #define CMP_C1_CHN3_WIDTH 1u
1809 #define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN3_SHIFT))&CMP_C1_CHN3_MASK)
1810 #define CMP_C1_CHN4_MASK 0x100000u
1811 #define CMP_C1_CHN4_SHIFT 20u
1812 #define CMP_C1_CHN4_WIDTH 1u
1813 #define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN4_SHIFT))&CMP_C1_CHN4_MASK)
1814 #define CMP_C1_CHN5_MASK 0x200000u
1815 #define CMP_C1_CHN5_SHIFT 21u
1816 #define CMP_C1_CHN5_WIDTH 1u
1817 #define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN5_SHIFT))&CMP_C1_CHN5_MASK)
1818 #define CMP_C1_CHN6_MASK 0x400000u
1819 #define CMP_C1_CHN6_SHIFT 22u
1820 #define CMP_C1_CHN6_WIDTH 1u
1821 #define CMP_C1_CHN6(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN6_SHIFT))&CMP_C1_CHN6_MASK)
1822 #define CMP_C1_CHN7_MASK 0x800000u
1823 #define CMP_C1_CHN7_SHIFT 23u
1824 #define CMP_C1_CHN7_WIDTH 1u
1825 #define CMP_C1_CHN7(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_CHN7_SHIFT))&CMP_C1_CHN7_MASK)
1826 #define CMP_C1_INNSEL_MASK 0x3000000u
1827 #define CMP_C1_INNSEL_SHIFT 24u
1828 #define CMP_C1_INNSEL_WIDTH 2u
1829 #define CMP_C1_INNSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INNSEL_SHIFT))&CMP_C1_INNSEL_MASK)
1830 #define CMP_C1_INPSEL_MASK 0x18000000u
1831 #define CMP_C1_INPSEL_SHIFT 27u
1832 #define CMP_C1_INPSEL_WIDTH 2u
1833 #define CMP_C1_INPSEL(x) (((uint32_t)(((uint32_t)(x))<<CMP_C1_INPSEL_SHIFT))&CMP_C1_INPSEL_MASK)
1834 /* C2 Bit Fields */
1835 #define CMP_C2_ACOn_MASK 0xFFu
1836 #define CMP_C2_ACOn_SHIFT 0u
1837 #define CMP_C2_ACOn_WIDTH 8u
1838 #define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_ACOn_SHIFT))&CMP_C2_ACOn_MASK)
1839 #define CMP_C2_INITMOD_MASK 0x3F00u
1840 #define CMP_C2_INITMOD_SHIFT 8u
1841 #define CMP_C2_INITMOD_WIDTH 6u
1842 #define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_INITMOD_SHIFT))&CMP_C2_INITMOD_MASK)
1843 #define CMP_C2_NSAM_MASK 0xC000u
1844 #define CMP_C2_NSAM_SHIFT 14u
1845 #define CMP_C2_NSAM_WIDTH 2u
1846 #define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_NSAM_SHIFT))&CMP_C2_NSAM_MASK)
1847 #define CMP_C2_CH0F_MASK 0x10000u
1848 #define CMP_C2_CH0F_SHIFT 16u
1849 #define CMP_C2_CH0F_WIDTH 1u
1850 #define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH0F_SHIFT))&CMP_C2_CH0F_MASK)
1851 #define CMP_C2_CH1F_MASK 0x20000u
1852 #define CMP_C2_CH1F_SHIFT 17u
1853 #define CMP_C2_CH1F_WIDTH 1u
1854 #define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH1F_SHIFT))&CMP_C2_CH1F_MASK)
1855 #define CMP_C2_CH2F_MASK 0x40000u
1856 #define CMP_C2_CH2F_SHIFT 18u
1857 #define CMP_C2_CH2F_WIDTH 1u
1858 #define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH2F_SHIFT))&CMP_C2_CH2F_MASK)
1859 #define CMP_C2_CH3F_MASK 0x80000u
1860 #define CMP_C2_CH3F_SHIFT 19u
1861 #define CMP_C2_CH3F_WIDTH 1u
1862 #define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH3F_SHIFT))&CMP_C2_CH3F_MASK)
1863 #define CMP_C2_CH4F_MASK 0x100000u
1864 #define CMP_C2_CH4F_SHIFT 20u
1865 #define CMP_C2_CH4F_WIDTH 1u
1866 #define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH4F_SHIFT))&CMP_C2_CH4F_MASK)
1867 #define CMP_C2_CH5F_MASK 0x200000u
1868 #define CMP_C2_CH5F_SHIFT 21u
1869 #define CMP_C2_CH5F_WIDTH 1u
1870 #define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH5F_SHIFT))&CMP_C2_CH5F_MASK)
1871 #define CMP_C2_CH6F_MASK 0x400000u
1872 #define CMP_C2_CH6F_SHIFT 22u
1873 #define CMP_C2_CH6F_WIDTH 1u
1874 #define CMP_C2_CH6F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH6F_SHIFT))&CMP_C2_CH6F_MASK)
1875 #define CMP_C2_CH7F_MASK 0x800000u
1876 #define CMP_C2_CH7F_SHIFT 23u
1877 #define CMP_C2_CH7F_WIDTH 1u
1878 #define CMP_C2_CH7F(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_CH7F_SHIFT))&CMP_C2_CH7F_MASK)
1879 #define CMP_C2_FXMXCH_MASK 0xE000000u
1880 #define CMP_C2_FXMXCH_SHIFT 25u
1881 #define CMP_C2_FXMXCH_WIDTH 3u
1882 #define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMXCH_SHIFT))&CMP_C2_FXMXCH_MASK)
1883 #define CMP_C2_FXMP_MASK 0x20000000u
1884 #define CMP_C2_FXMP_SHIFT 29u
1885 #define CMP_C2_FXMP_WIDTH 1u
1886 #define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_FXMP_SHIFT))&CMP_C2_FXMP_MASK)
1887 #define CMP_C2_RRIE_MASK 0x40000000u
1888 #define CMP_C2_RRIE_SHIFT 30u
1889 #define CMP_C2_RRIE_WIDTH 1u
1890 #define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRIE_SHIFT))&CMP_C2_RRIE_MASK)
1891 #define CMP_C2_RRE_MASK 0x80000000u
1892 #define CMP_C2_RRE_SHIFT 31u
1893 #define CMP_C2_RRE_WIDTH 1u
1894 #define CMP_C2_RRE(x) (((uint32_t)(((uint32_t)(x))<<CMP_C2_RRE_SHIFT))&CMP_C2_RRE_MASK)
1895  /* end of group CMP_Register_Masks */
1899 
1900  /* end of group CMP_Peripheral_Access_Layer */
1904 
1905 
1906 /* ----------------------------------------------------------------------------
1907  -- CRC Peripheral Access Layer
1908  ---------------------------------------------------------------------------- */
1909 
1919 typedef struct {
1920  union { /* offset: 0x0 */
1921  __IO uint32_t DATA;
1922  struct { /* offset: 0x0 */
1923  __IO uint16_t L;
1924  __IO uint16_t H;
1925  } DATA_16;
1926  struct { /* offset: 0x0 */
1927  __IO uint8_t LL;
1928  __IO uint8_t LU;
1929  __IO uint8_t HL;
1930  __IO uint8_t HU;
1931  } DATA_8;
1932  } DATAu;
1933  __IO uint32_t GPOLY;
1934  __IO uint32_t CTRL;
1936 
1938 #define CRC_INSTANCE_COUNT (1u)
1939 
1940 
1941 /* CRC - Peripheral instance base addresses */
1943 #define CRC_BASE (0x40032000u)
1944 
1945 #define CRC ((CRC_Type *)CRC_BASE)
1946 
1947 #define CRC_BASE_ADDRS { CRC_BASE }
1948 
1949 #define CRC_BASE_PTRS { CRC }
1950 
1951 /* ----------------------------------------------------------------------------
1952  -- CRC Register Masks
1953  ---------------------------------------------------------------------------- */
1954 
1960 /* DATAu_DATA Bit Fields */
1961 #define CRC_DATAu_DATA_LL_MASK 0xFFu
1962 #define CRC_DATAu_DATA_LL_SHIFT 0u
1963 #define CRC_DATAu_DATA_LL_WIDTH 8u
1964 #define CRC_DATAu_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LL_SHIFT))&CRC_DATAu_DATA_LL_MASK)
1965 #define CRC_DATAu_DATA_LU_MASK 0xFF00u
1966 #define CRC_DATAu_DATA_LU_SHIFT 8u
1967 #define CRC_DATAu_DATA_LU_WIDTH 8u
1968 #define CRC_DATAu_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_LU_SHIFT))&CRC_DATAu_DATA_LU_MASK)
1969 #define CRC_DATAu_DATA_HL_MASK 0xFF0000u
1970 #define CRC_DATAu_DATA_HL_SHIFT 16u
1971 #define CRC_DATAu_DATA_HL_WIDTH 8u
1972 #define CRC_DATAu_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HL_SHIFT))&CRC_DATAu_DATA_HL_MASK)
1973 #define CRC_DATAu_DATA_HU_MASK 0xFF000000u
1974 #define CRC_DATAu_DATA_HU_SHIFT 24u
1975 #define CRC_DATAu_DATA_HU_WIDTH 8u
1976 #define CRC_DATAu_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATAu_DATA_HU_SHIFT))&CRC_DATAu_DATA_HU_MASK)
1977 /* DATAu_DATA_16_L Bit Fields */
1978 #define CRC_DATAu_DATA_16_L_DATAL_MASK 0xFFFFu
1979 #define CRC_DATAu_DATA_16_L_DATAL_SHIFT 0u
1980 #define CRC_DATAu_DATA_16_L_DATAL_WIDTH 16u
1981 #define CRC_DATAu_DATA_16_L_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_L_DATAL_SHIFT))&CRC_DATAu_DATA_16_L_DATAL_MASK)
1982 /* DATAu_DATA_16_H Bit Fields */
1983 #define CRC_DATAu_DATA_16_H_DATAH_MASK 0xFFFFu
1984 #define CRC_DATAu_DATA_16_H_DATAH_SHIFT 0u
1985 #define CRC_DATAu_DATA_16_H_DATAH_WIDTH 16u
1986 #define CRC_DATAu_DATA_16_H_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAu_DATA_16_H_DATAH_SHIFT))&CRC_DATAu_DATA_16_H_DATAH_MASK)
1987 /* DATAu_DATA_8_LL Bit Fields */
1988 #define CRC_DATAu_DATA_8_LL_DATALL_MASK 0xFFu
1989 #define CRC_DATAu_DATA_8_LL_DATALL_SHIFT 0u
1990 #define CRC_DATAu_DATA_8_LL_DATALL_WIDTH 8u
1991 #define CRC_DATAu_DATA_8_LL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LL_DATALL_SHIFT))&CRC_DATAu_DATA_8_LL_DATALL_MASK)
1992 /* DATAu_DATA_8_LU Bit Fields */
1993 #define CRC_DATAu_DATA_8_LU_DATALU_MASK 0xFFu
1994 #define CRC_DATAu_DATA_8_LU_DATALU_SHIFT 0u
1995 #define CRC_DATAu_DATA_8_LU_DATALU_WIDTH 8u
1996 #define CRC_DATAu_DATA_8_LU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_LU_DATALU_SHIFT))&CRC_DATAu_DATA_8_LU_DATALU_MASK)
1997 /* DATAu_DATA_8_HL Bit Fields */
1998 #define CRC_DATAu_DATA_8_HL_DATAHL_MASK 0xFFu
1999 #define CRC_DATAu_DATA_8_HL_DATAHL_SHIFT 0u
2000 #define CRC_DATAu_DATA_8_HL_DATAHL_WIDTH 8u
2001 #define CRC_DATAu_DATA_8_HL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HL_DATAHL_SHIFT))&CRC_DATAu_DATA_8_HL_DATAHL_MASK)
2002 /* DATAu_DATA_8_HU Bit Fields */
2003 #define CRC_DATAu_DATA_8_HU_DATAHU_MASK 0xFFu
2004 #define CRC_DATAu_DATA_8_HU_DATAHU_SHIFT 0u
2005 #define CRC_DATAu_DATA_8_HU_DATAHU_WIDTH 8u
2006 #define CRC_DATAu_DATA_8_HU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAu_DATA_8_HU_DATAHU_SHIFT))&CRC_DATAu_DATA_8_HU_DATAHU_MASK)
2007 /* GPOLY Bit Fields */
2008 #define CRC_GPOLY_LOW_MASK 0xFFFFu
2009 #define CRC_GPOLY_LOW_SHIFT 0u
2010 #define CRC_GPOLY_LOW_WIDTH 16u
2011 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
2012 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
2013 #define CRC_GPOLY_HIGH_SHIFT 16u
2014 #define CRC_GPOLY_HIGH_WIDTH 16u
2015 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
2016 /* CTRL Bit Fields */
2017 #define CRC_CTRL_TCRC_MASK 0x1000000u
2018 #define CRC_CTRL_TCRC_SHIFT 24u
2019 #define CRC_CTRL_TCRC_WIDTH 1u
2020 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TCRC_SHIFT))&CRC_CTRL_TCRC_MASK)
2021 #define CRC_CTRL_WAS_MASK 0x2000000u
2022 #define CRC_CTRL_WAS_SHIFT 25u
2023 #define CRC_CTRL_WAS_WIDTH 1u
2024 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_WAS_SHIFT))&CRC_CTRL_WAS_MASK)
2025 #define CRC_CTRL_FXOR_MASK 0x4000000u
2026 #define CRC_CTRL_FXOR_SHIFT 26u
2027 #define CRC_CTRL_FXOR_WIDTH 1u
2028 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_FXOR_SHIFT))&CRC_CTRL_FXOR_MASK)
2029 #define CRC_CTRL_TOTR_MASK 0x30000000u
2030 #define CRC_CTRL_TOTR_SHIFT 28u
2031 #define CRC_CTRL_TOTR_WIDTH 2u
2032 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
2033 #define CRC_CTRL_TOT_MASK 0xC0000000u
2034 #define CRC_CTRL_TOT_SHIFT 30u
2035 #define CRC_CTRL_TOT_WIDTH 2u
2036 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
2037  /* end of group CRC_Register_Masks */
2041 
2042  /* end of group CRC_Peripheral_Access_Layer */
2046 
2047 
2048 /* ----------------------------------------------------------------------------
2049  -- CSE_PRAM Peripheral Access Layer
2050  ---------------------------------------------------------------------------- */
2051 
2059 #define CSE_PRAM_RAMn_COUNT 32u
2060 
2062 typedef struct {
2063  union { /* offset: 0x0, array step: 0x4 */
2064  __IO uint32_t DATA_32;
2065  struct { /* offset: 0x0, array step: 0x4 */
2066  __IO uint8_t DATA_8LL;
2067  __IO uint8_t DATA_8LU;
2068  __IO uint8_t DATA_8HL;
2069  __IO uint8_t DATA_8HU;
2070  } ACCESS8BIT;
2071  } RAMn[CSE_PRAM_RAMn_COUNT];
2073 
2075 #define CSE_PRAM_INSTANCE_COUNT (1u)
2076 
2077 
2078 /* CSE_PRAM - Peripheral instance base addresses */
2080 #define CSE_PRAM_BASE (0x14001000u)
2081 
2082 #define CSE_PRAM ((CSE_PRAM_Type *)CSE_PRAM_BASE)
2083 
2084 #define CSE_PRAM_BASE_ADDRS { CSE_PRAM_BASE }
2085 
2086 #define CSE_PRAM_BASE_PTRS { CSE_PRAM }
2087 
2088 /* ----------------------------------------------------------------------------
2089  -- CSE_PRAM Register Masks
2090  ---------------------------------------------------------------------------- */
2091 
2097 /* RAMn_DATA_32 Bit Fields */
2098 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK 0xFFu
2099 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT 0u
2100 #define CSE_PRAM_RAMn_DATA_32_BYTE_3_WIDTH 8u
2101 #define CSE_PRAM_RAMn_DATA_32_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_3_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_3_MASK)
2102 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK 0xFF00u
2103 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT 8u
2104 #define CSE_PRAM_RAMn_DATA_32_BYTE_2_WIDTH 8u
2105 #define CSE_PRAM_RAMn_DATA_32_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_2_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_2_MASK)
2106 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK 0xFF0000u
2107 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT 16u
2108 #define CSE_PRAM_RAMn_DATA_32_BYTE_1_WIDTH 8u
2109 #define CSE_PRAM_RAMn_DATA_32_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_1_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_1_MASK)
2110 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK 0xFF000000u
2111 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT 24u
2112 #define CSE_PRAM_RAMn_DATA_32_BYTE_0_WIDTH 8u
2113 #define CSE_PRAM_RAMn_DATA_32_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CSE_PRAM_RAMn_DATA_32_BYTE_0_SHIFT))&CSE_PRAM_RAMn_DATA_32_BYTE_0_MASK)
2114 /* RAMn_ACCESS8BIT_DATA_8LL Bit Fields */
2115 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK 0xFFu
2116 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT 0u
2117 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_WIDTH 8u
2118 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LL_RAM_LL_MASK)
2119 /* RAMn_ACCESS8BIT_DATA_8LU Bit Fields */
2120 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK 0xFFu
2121 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT 0u
2122 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_WIDTH 8u
2123 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8LU_RAM_LU_MASK)
2124 /* RAMn_ACCESS8BIT_DATA_8HL Bit Fields */
2125 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK 0xFFu
2126 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT 0u
2127 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_WIDTH 8u
2128 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HL_RAM_HL_MASK)
2129 /* RAMn_ACCESS8BIT_DATA_8HU Bit Fields */
2130 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK 0xFFu
2131 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT 0u
2132 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_WIDTH 8u
2133 #define CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU(x) (((uint8_t)(((uint8_t)(x))<<CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_SHIFT))&CSE_PRAM_RAMn_ACCESS8BIT_DATA_8HU_RAM_HU_MASK)
2134  /* end of group CSE_PRAM_Register_Masks */
2138 
2139  /* end of group CSE_PRAM_Peripheral_Access_Layer */
2143 
2144 
2145 /* ----------------------------------------------------------------------------
2146  -- DMA Peripheral Access Layer
2147  ---------------------------------------------------------------------------- */
2148 
2156 #define DMA_DCHPRI_COUNT 16u
2157 #define DMA_TCD_COUNT 16u
2158 
2160 typedef struct {
2161  __IO uint32_t CR;
2162  __I uint32_t ES;
2163  uint8_t RESERVED_0[4];
2164  __IO uint32_t ERQ;
2165  uint8_t RESERVED_1[4];
2166  __IO uint32_t EEI;
2167  __O uint8_t CEEI;
2168  __O uint8_t SEEI;
2169  __O uint8_t CERQ;
2170  __O uint8_t SERQ;
2171  __O uint8_t CDNE;
2172  __O uint8_t SSRT;
2173  __O uint8_t CERR;
2174  __O uint8_t CINT;
2175  uint8_t RESERVED_2[4];
2176  __IO uint32_t INT;
2177  uint8_t RESERVED_3[4];
2178  __IO uint32_t ERR;
2179  uint8_t RESERVED_4[4];
2180  __I uint32_t HRS;
2181  uint8_t RESERVED_5[12];
2182  __IO uint32_t EARS;
2183  uint8_t RESERVED_6[184];
2184  __IO uint8_t DCHPRI[DMA_DCHPRI_COUNT];
2185  uint8_t RESERVED_7[3824];
2186  struct { /* offset: 0x1000, array step: 0x20 */
2187  __IO uint32_t SADDR;
2188  __IO uint16_t SOFF;
2189  __IO uint16_t ATTR;
2190  union { /* offset: 0x1008, array step: 0x20 */
2191  __IO uint32_t MLNO;
2192  __IO uint32_t MLOFFNO;
2193  __IO uint32_t MLOFFYES;
2194  } NBYTES;
2195  __IO uint32_t SLAST;
2196  __IO uint32_t DADDR;
2197  __IO uint16_t DOFF;
2198  union { /* offset: 0x1016, array step: 0x20 */
2199  __IO uint16_t ELINKNO;
2200  __IO uint16_t ELINKYES;
2201  } CITER;
2202  __IO uint32_t DLASTSGA;
2203  __IO uint16_t CSR;
2204  union { /* offset: 0x101E, array step: 0x20 */
2205  __IO uint16_t ELINKNO;
2206  __IO uint16_t ELINKYES;
2207  } BITER;
2208  } TCD[DMA_TCD_COUNT];
2210 
2212 #define DMA_INSTANCE_COUNT (1u)
2213 
2214 
2215 /* DMA - Peripheral instance base addresses */
2217 #define DMA_BASE (0x40008000u)
2218 
2219 #define DMA ((DMA_Type *)DMA_BASE)
2220 
2221 #define DMA_BASE_ADDRS { DMA_BASE }
2222 
2223 #define DMA_BASE_PTRS { DMA }
2224 
2225 #define DMA_IRQS_ARR_COUNT (2u)
2226 
2227 #define DMA_CHN_IRQS_CH_COUNT (16u)
2228 
2229 #define DMA_ERROR_IRQS_CH_COUNT (1u)
2230 
2231 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
2232 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
2233 
2234 /* ----------------------------------------------------------------------------
2235  -- DMA Register Masks
2236  ---------------------------------------------------------------------------- */
2237 
2243 /* CR Bit Fields */
2244 #define DMA_CR_EDBG_MASK 0x2u
2245 #define DMA_CR_EDBG_SHIFT 1u
2246 #define DMA_CR_EDBG_WIDTH 1u
2247 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EDBG_SHIFT))&DMA_CR_EDBG_MASK)
2248 #define DMA_CR_ERCA_MASK 0x4u
2249 #define DMA_CR_ERCA_SHIFT 2u
2250 #define DMA_CR_ERCA_WIDTH 1u
2251 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ERCA_SHIFT))&DMA_CR_ERCA_MASK)
2252 #define DMA_CR_HOE_MASK 0x10u
2253 #define DMA_CR_HOE_SHIFT 4u
2254 #define DMA_CR_HOE_WIDTH 1u
2255 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HOE_SHIFT))&DMA_CR_HOE_MASK)
2256 #define DMA_CR_HALT_MASK 0x20u
2257 #define DMA_CR_HALT_SHIFT 5u
2258 #define DMA_CR_HALT_WIDTH 1u
2259 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_HALT_SHIFT))&DMA_CR_HALT_MASK)
2260 #define DMA_CR_CLM_MASK 0x40u
2261 #define DMA_CR_CLM_SHIFT 6u
2262 #define DMA_CR_CLM_WIDTH 1u
2263 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CLM_SHIFT))&DMA_CR_CLM_MASK)
2264 #define DMA_CR_EMLM_MASK 0x80u
2265 #define DMA_CR_EMLM_SHIFT 7u
2266 #define DMA_CR_EMLM_WIDTH 1u
2267 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_EMLM_SHIFT))&DMA_CR_EMLM_MASK)
2268 #define DMA_CR_ECX_MASK 0x10000u
2269 #define DMA_CR_ECX_SHIFT 16u
2270 #define DMA_CR_ECX_WIDTH 1u
2271 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_ECX_SHIFT))&DMA_CR_ECX_MASK)
2272 #define DMA_CR_CX_MASK 0x20000u
2273 #define DMA_CR_CX_SHIFT 17u
2274 #define DMA_CR_CX_WIDTH 1u
2275 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x))<<DMA_CR_CX_SHIFT))&DMA_CR_CX_MASK)
2276 /* ES Bit Fields */
2277 #define DMA_ES_DBE_MASK 0x1u
2278 #define DMA_ES_DBE_SHIFT 0u
2279 #define DMA_ES_DBE_WIDTH 1u
2280 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DBE_SHIFT))&DMA_ES_DBE_MASK)
2281 #define DMA_ES_SBE_MASK 0x2u
2282 #define DMA_ES_SBE_SHIFT 1u
2283 #define DMA_ES_SBE_WIDTH 1u
2284 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SBE_SHIFT))&DMA_ES_SBE_MASK)
2285 #define DMA_ES_SGE_MASK 0x4u
2286 #define DMA_ES_SGE_SHIFT 2u
2287 #define DMA_ES_SGE_WIDTH 1u
2288 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SGE_SHIFT))&DMA_ES_SGE_MASK)
2289 #define DMA_ES_NCE_MASK 0x8u
2290 #define DMA_ES_NCE_SHIFT 3u
2291 #define DMA_ES_NCE_WIDTH 1u
2292 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_NCE_SHIFT))&DMA_ES_NCE_MASK)
2293 #define DMA_ES_DOE_MASK 0x10u
2294 #define DMA_ES_DOE_SHIFT 4u
2295 #define DMA_ES_DOE_WIDTH 1u
2296 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DOE_SHIFT))&DMA_ES_DOE_MASK)
2297 #define DMA_ES_DAE_MASK 0x20u
2298 #define DMA_ES_DAE_SHIFT 5u
2299 #define DMA_ES_DAE_WIDTH 1u
2300 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_DAE_SHIFT))&DMA_ES_DAE_MASK)
2301 #define DMA_ES_SOE_MASK 0x40u
2302 #define DMA_ES_SOE_SHIFT 6u
2303 #define DMA_ES_SOE_WIDTH 1u
2304 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SOE_SHIFT))&DMA_ES_SOE_MASK)
2305 #define DMA_ES_SAE_MASK 0x80u
2306 #define DMA_ES_SAE_SHIFT 7u
2307 #define DMA_ES_SAE_WIDTH 1u
2308 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_SAE_SHIFT))&DMA_ES_SAE_MASK)
2309 #define DMA_ES_ERRCHN_MASK 0xF00u
2310 #define DMA_ES_ERRCHN_SHIFT 8u
2311 #define DMA_ES_ERRCHN_WIDTH 4u
2312 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
2313 #define DMA_ES_CPE_MASK 0x4000u
2314 #define DMA_ES_CPE_SHIFT 14u
2315 #define DMA_ES_CPE_WIDTH 1u
2316 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_CPE_SHIFT))&DMA_ES_CPE_MASK)
2317 #define DMA_ES_ECX_MASK 0x10000u
2318 #define DMA_ES_ECX_SHIFT 16u
2319 #define DMA_ES_ECX_WIDTH 1u
2320 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ECX_SHIFT))&DMA_ES_ECX_MASK)
2321 #define DMA_ES_VLD_MASK 0x80000000u
2322 #define DMA_ES_VLD_SHIFT 31u
2323 #define DMA_ES_VLD_WIDTH 1u
2324 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_VLD_SHIFT))&DMA_ES_VLD_MASK)
2325 /* ERQ Bit Fields */
2326 #define DMA_ERQ_ERQ0_MASK 0x1u
2327 #define DMA_ERQ_ERQ0_SHIFT 0u
2328 #define DMA_ERQ_ERQ0_WIDTH 1u
2329 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ0_SHIFT))&DMA_ERQ_ERQ0_MASK)
2330 #define DMA_ERQ_ERQ1_MASK 0x2u
2331 #define DMA_ERQ_ERQ1_SHIFT 1u
2332 #define DMA_ERQ_ERQ1_WIDTH 1u
2333 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ1_SHIFT))&DMA_ERQ_ERQ1_MASK)
2334 #define DMA_ERQ_ERQ2_MASK 0x4u
2335 #define DMA_ERQ_ERQ2_SHIFT 2u
2336 #define DMA_ERQ_ERQ2_WIDTH 1u
2337 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ2_SHIFT))&DMA_ERQ_ERQ2_MASK)
2338 #define DMA_ERQ_ERQ3_MASK 0x8u
2339 #define DMA_ERQ_ERQ3_SHIFT 3u
2340 #define DMA_ERQ_ERQ3_WIDTH 1u
2341 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ3_SHIFT))&DMA_ERQ_ERQ3_MASK)
2342 #define DMA_ERQ_ERQ4_MASK 0x10u
2343 #define DMA_ERQ_ERQ4_SHIFT 4u
2344 #define DMA_ERQ_ERQ4_WIDTH 1u
2345 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ4_SHIFT))&DMA_ERQ_ERQ4_MASK)
2346 #define DMA_ERQ_ERQ5_MASK 0x20u
2347 #define DMA_ERQ_ERQ5_SHIFT 5u
2348 #define DMA_ERQ_ERQ5_WIDTH 1u
2349 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ5_SHIFT))&DMA_ERQ_ERQ5_MASK)
2350 #define DMA_ERQ_ERQ6_MASK 0x40u
2351 #define DMA_ERQ_ERQ6_SHIFT 6u
2352 #define DMA_ERQ_ERQ6_WIDTH 1u
2353 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ6_SHIFT))&DMA_ERQ_ERQ6_MASK)
2354 #define DMA_ERQ_ERQ7_MASK 0x80u
2355 #define DMA_ERQ_ERQ7_SHIFT 7u
2356 #define DMA_ERQ_ERQ7_WIDTH 1u
2357 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ7_SHIFT))&DMA_ERQ_ERQ7_MASK)
2358 #define DMA_ERQ_ERQ8_MASK 0x100u
2359 #define DMA_ERQ_ERQ8_SHIFT 8u
2360 #define DMA_ERQ_ERQ8_WIDTH 1u
2361 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ8_SHIFT))&DMA_ERQ_ERQ8_MASK)
2362 #define DMA_ERQ_ERQ9_MASK 0x200u
2363 #define DMA_ERQ_ERQ9_SHIFT 9u
2364 #define DMA_ERQ_ERQ9_WIDTH 1u
2365 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ9_SHIFT))&DMA_ERQ_ERQ9_MASK)
2366 #define DMA_ERQ_ERQ10_MASK 0x400u
2367 #define DMA_ERQ_ERQ10_SHIFT 10u
2368 #define DMA_ERQ_ERQ10_WIDTH 1u
2369 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ10_SHIFT))&DMA_ERQ_ERQ10_MASK)
2370 #define DMA_ERQ_ERQ11_MASK 0x800u
2371 #define DMA_ERQ_ERQ11_SHIFT 11u
2372 #define DMA_ERQ_ERQ11_WIDTH 1u
2373 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ11_SHIFT))&DMA_ERQ_ERQ11_MASK)
2374 #define DMA_ERQ_ERQ12_MASK 0x1000u
2375 #define DMA_ERQ_ERQ12_SHIFT 12u
2376 #define DMA_ERQ_ERQ12_WIDTH 1u
2377 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ12_SHIFT))&DMA_ERQ_ERQ12_MASK)
2378 #define DMA_ERQ_ERQ13_MASK 0x2000u
2379 #define DMA_ERQ_ERQ13_SHIFT 13u
2380 #define DMA_ERQ_ERQ13_WIDTH 1u
2381 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ13_SHIFT))&DMA_ERQ_ERQ13_MASK)
2382 #define DMA_ERQ_ERQ14_MASK 0x4000u
2383 #define DMA_ERQ_ERQ14_SHIFT 14u
2384 #define DMA_ERQ_ERQ14_WIDTH 1u
2385 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ14_SHIFT))&DMA_ERQ_ERQ14_MASK)
2386 #define DMA_ERQ_ERQ15_MASK 0x8000u
2387 #define DMA_ERQ_ERQ15_SHIFT 15u
2388 #define DMA_ERQ_ERQ15_WIDTH 1u
2389 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERQ_ERQ15_SHIFT))&DMA_ERQ_ERQ15_MASK)
2390 /* EEI Bit Fields */
2391 #define DMA_EEI_EEI0_MASK 0x1u
2392 #define DMA_EEI_EEI0_SHIFT 0u
2393 #define DMA_EEI_EEI0_WIDTH 1u
2394 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI0_SHIFT))&DMA_EEI_EEI0_MASK)
2395 #define DMA_EEI_EEI1_MASK 0x2u
2396 #define DMA_EEI_EEI1_SHIFT 1u
2397 #define DMA_EEI_EEI1_WIDTH 1u
2398 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI1_SHIFT))&DMA_EEI_EEI1_MASK)
2399 #define DMA_EEI_EEI2_MASK 0x4u
2400 #define DMA_EEI_EEI2_SHIFT 2u
2401 #define DMA_EEI_EEI2_WIDTH 1u
2402 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI2_SHIFT))&DMA_EEI_EEI2_MASK)
2403 #define DMA_EEI_EEI3_MASK 0x8u
2404 #define DMA_EEI_EEI3_SHIFT 3u
2405 #define DMA_EEI_EEI3_WIDTH 1u
2406 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI3_SHIFT))&DMA_EEI_EEI3_MASK)
2407 #define DMA_EEI_EEI4_MASK 0x10u
2408 #define DMA_EEI_EEI4_SHIFT 4u
2409 #define DMA_EEI_EEI4_WIDTH 1u
2410 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI4_SHIFT))&DMA_EEI_EEI4_MASK)
2411 #define DMA_EEI_EEI5_MASK 0x20u
2412 #define DMA_EEI_EEI5_SHIFT 5u
2413 #define DMA_EEI_EEI5_WIDTH 1u
2414 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI5_SHIFT))&DMA_EEI_EEI5_MASK)
2415 #define DMA_EEI_EEI6_MASK 0x40u
2416 #define DMA_EEI_EEI6_SHIFT 6u
2417 #define DMA_EEI_EEI6_WIDTH 1u
2418 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI6_SHIFT))&DMA_EEI_EEI6_MASK)
2419 #define DMA_EEI_EEI7_MASK 0x80u
2420 #define DMA_EEI_EEI7_SHIFT 7u
2421 #define DMA_EEI_EEI7_WIDTH 1u
2422 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI7_SHIFT))&DMA_EEI_EEI7_MASK)
2423 #define DMA_EEI_EEI8_MASK 0x100u
2424 #define DMA_EEI_EEI8_SHIFT 8u
2425 #define DMA_EEI_EEI8_WIDTH 1u
2426 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI8_SHIFT))&DMA_EEI_EEI8_MASK)
2427 #define DMA_EEI_EEI9_MASK 0x200u
2428 #define DMA_EEI_EEI9_SHIFT 9u
2429 #define DMA_EEI_EEI9_WIDTH 1u
2430 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI9_SHIFT))&DMA_EEI_EEI9_MASK)
2431 #define DMA_EEI_EEI10_MASK 0x400u
2432 #define DMA_EEI_EEI10_SHIFT 10u
2433 #define DMA_EEI_EEI10_WIDTH 1u
2434 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI10_SHIFT))&DMA_EEI_EEI10_MASK)
2435 #define DMA_EEI_EEI11_MASK 0x800u
2436 #define DMA_EEI_EEI11_SHIFT 11u
2437 #define DMA_EEI_EEI11_WIDTH 1u
2438 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI11_SHIFT))&DMA_EEI_EEI11_MASK)
2439 #define DMA_EEI_EEI12_MASK 0x1000u
2440 #define DMA_EEI_EEI12_SHIFT 12u
2441 #define DMA_EEI_EEI12_WIDTH 1u
2442 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI12_SHIFT))&DMA_EEI_EEI12_MASK)
2443 #define DMA_EEI_EEI13_MASK 0x2000u
2444 #define DMA_EEI_EEI13_SHIFT 13u
2445 #define DMA_EEI_EEI13_WIDTH 1u
2446 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI13_SHIFT))&DMA_EEI_EEI13_MASK)
2447 #define DMA_EEI_EEI14_MASK 0x4000u
2448 #define DMA_EEI_EEI14_SHIFT 14u
2449 #define DMA_EEI_EEI14_WIDTH 1u
2450 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI14_SHIFT))&DMA_EEI_EEI14_MASK)
2451 #define DMA_EEI_EEI15_MASK 0x8000u
2452 #define DMA_EEI_EEI15_SHIFT 15u
2453 #define DMA_EEI_EEI15_WIDTH 1u
2454 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EEI_EEI15_SHIFT))&DMA_EEI_EEI15_MASK)
2455 /* CEEI Bit Fields */
2456 #define DMA_CEEI_CEEI_MASK 0xFu
2457 #define DMA_CEEI_CEEI_SHIFT 0u
2458 #define DMA_CEEI_CEEI_WIDTH 4u
2459 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
2460 #define DMA_CEEI_CAEE_MASK 0x40u
2461 #define DMA_CEEI_CAEE_SHIFT 6u
2462 #define DMA_CEEI_CAEE_WIDTH 1u
2463 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CAEE_SHIFT))&DMA_CEEI_CAEE_MASK)
2464 #define DMA_CEEI_NOP_MASK 0x80u
2465 #define DMA_CEEI_NOP_SHIFT 7u
2466 #define DMA_CEEI_NOP_WIDTH 1u
2467 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_NOP_SHIFT))&DMA_CEEI_NOP_MASK)
2468 /* SEEI Bit Fields */
2469 #define DMA_SEEI_SEEI_MASK 0xFu
2470 #define DMA_SEEI_SEEI_SHIFT 0u
2471 #define DMA_SEEI_SEEI_WIDTH 4u
2472 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
2473 #define DMA_SEEI_SAEE_MASK 0x40u
2474 #define DMA_SEEI_SAEE_SHIFT 6u
2475 #define DMA_SEEI_SAEE_WIDTH 1u
2476 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SAEE_SHIFT))&DMA_SEEI_SAEE_MASK)
2477 #define DMA_SEEI_NOP_MASK 0x80u
2478 #define DMA_SEEI_NOP_SHIFT 7u
2479 #define DMA_SEEI_NOP_WIDTH 1u
2480 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_NOP_SHIFT))&DMA_SEEI_NOP_MASK)
2481 /* CERQ Bit Fields */
2482 #define DMA_CERQ_CERQ_MASK 0xFu
2483 #define DMA_CERQ_CERQ_SHIFT 0u
2484 #define DMA_CERQ_CERQ_WIDTH 4u
2485 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
2486 #define DMA_CERQ_CAER_MASK 0x40u
2487 #define DMA_CERQ_CAER_SHIFT 6u
2488 #define DMA_CERQ_CAER_WIDTH 1u
2489 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CAER_SHIFT))&DMA_CERQ_CAER_MASK)
2490 #define DMA_CERQ_NOP_MASK 0x80u
2491 #define DMA_CERQ_NOP_SHIFT 7u
2492 #define DMA_CERQ_NOP_WIDTH 1u
2493 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_NOP_SHIFT))&DMA_CERQ_NOP_MASK)
2494 /* SERQ Bit Fields */
2495 #define DMA_SERQ_SERQ_MASK 0xFu
2496 #define DMA_SERQ_SERQ_SHIFT 0u
2497 #define DMA_SERQ_SERQ_WIDTH 4u
2498 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
2499 #define DMA_SERQ_SAER_MASK 0x40u
2500 #define DMA_SERQ_SAER_SHIFT 6u
2501 #define DMA_SERQ_SAER_WIDTH 1u
2502 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SAER_SHIFT))&DMA_SERQ_SAER_MASK)
2503 #define DMA_SERQ_NOP_MASK 0x80u
2504 #define DMA_SERQ_NOP_SHIFT 7u
2505 #define DMA_SERQ_NOP_WIDTH 1u
2506 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_NOP_SHIFT))&DMA_SERQ_NOP_MASK)
2507 /* CDNE Bit Fields */
2508 #define DMA_CDNE_CDNE_MASK 0xFu
2509 #define DMA_CDNE_CDNE_SHIFT 0u
2510 #define DMA_CDNE_CDNE_WIDTH 4u
2511 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
2512 #define DMA_CDNE_CADN_MASK 0x40u
2513 #define DMA_CDNE_CADN_SHIFT 6u
2514 #define DMA_CDNE_CADN_WIDTH 1u
2515 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CADN_SHIFT))&DMA_CDNE_CADN_MASK)
2516 #define DMA_CDNE_NOP_MASK 0x80u
2517 #define DMA_CDNE_NOP_SHIFT 7u
2518 #define DMA_CDNE_NOP_WIDTH 1u
2519 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_NOP_SHIFT))&DMA_CDNE_NOP_MASK)
2520 /* SSRT Bit Fields */
2521 #define DMA_SSRT_SSRT_MASK 0xFu
2522 #define DMA_SSRT_SSRT_SHIFT 0u
2523 #define DMA_SSRT_SSRT_WIDTH 4u
2524 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
2525 #define DMA_SSRT_SAST_MASK 0x40u
2526 #define DMA_SSRT_SAST_SHIFT 6u
2527 #define DMA_SSRT_SAST_WIDTH 1u
2528 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SAST_SHIFT))&DMA_SSRT_SAST_MASK)
2529 #define DMA_SSRT_NOP_MASK 0x80u
2530 #define DMA_SSRT_NOP_SHIFT 7u
2531 #define DMA_SSRT_NOP_WIDTH 1u
2532 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_NOP_SHIFT))&DMA_SSRT_NOP_MASK)
2533 /* CERR Bit Fields */
2534 #define DMA_CERR_CERR_MASK 0xFu
2535 #define DMA_CERR_CERR_SHIFT 0u
2536 #define DMA_CERR_CERR_WIDTH 4u
2537 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
2538 #define DMA_CERR_CAEI_MASK 0x40u
2539 #define DMA_CERR_CAEI_SHIFT 6u
2540 #define DMA_CERR_CAEI_WIDTH 1u
2541 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CAEI_SHIFT))&DMA_CERR_CAEI_MASK)
2542 #define DMA_CERR_NOP_MASK 0x80u
2543 #define DMA_CERR_NOP_SHIFT 7u
2544 #define DMA_CERR_NOP_WIDTH 1u
2545 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_NOP_SHIFT))&DMA_CERR_NOP_MASK)
2546 /* CINT Bit Fields */
2547 #define DMA_CINT_CINT_MASK 0xFu
2548 #define DMA_CINT_CINT_SHIFT 0u
2549 #define DMA_CINT_CINT_WIDTH 4u
2550 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
2551 #define DMA_CINT_CAIR_MASK 0x40u
2552 #define DMA_CINT_CAIR_SHIFT 6u
2553 #define DMA_CINT_CAIR_WIDTH 1u
2554 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CAIR_SHIFT))&DMA_CINT_CAIR_MASK)
2555 #define DMA_CINT_NOP_MASK 0x80u
2556 #define DMA_CINT_NOP_SHIFT 7u
2557 #define DMA_CINT_NOP_WIDTH 1u
2558 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_NOP_SHIFT))&DMA_CINT_NOP_MASK)
2559 /* INT Bit Fields */
2560 #define DMA_INT_INT0_MASK 0x1u
2561 #define DMA_INT_INT0_SHIFT 0u
2562 #define DMA_INT_INT0_WIDTH 1u
2563 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT0_SHIFT))&DMA_INT_INT0_MASK)
2564 #define DMA_INT_INT1_MASK 0x2u
2565 #define DMA_INT_INT1_SHIFT 1u
2566 #define DMA_INT_INT1_WIDTH 1u
2567 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT1_SHIFT))&DMA_INT_INT1_MASK)
2568 #define DMA_INT_INT2_MASK 0x4u
2569 #define DMA_INT_INT2_SHIFT 2u
2570 #define DMA_INT_INT2_WIDTH 1u
2571 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT2_SHIFT))&DMA_INT_INT2_MASK)
2572 #define DMA_INT_INT3_MASK 0x8u
2573 #define DMA_INT_INT3_SHIFT 3u
2574 #define DMA_INT_INT3_WIDTH 1u
2575 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT3_SHIFT))&DMA_INT_INT3_MASK)
2576 #define DMA_INT_INT4_MASK 0x10u
2577 #define DMA_INT_INT4_SHIFT 4u
2578 #define DMA_INT_INT4_WIDTH 1u
2579 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT4_SHIFT))&DMA_INT_INT4_MASK)
2580 #define DMA_INT_INT5_MASK 0x20u
2581 #define DMA_INT_INT5_SHIFT 5u
2582 #define DMA_INT_INT5_WIDTH 1u
2583 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT5_SHIFT))&DMA_INT_INT5_MASK)
2584 #define DMA_INT_INT6_MASK 0x40u
2585 #define DMA_INT_INT6_SHIFT 6u
2586 #define DMA_INT_INT6_WIDTH 1u
2587 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT6_SHIFT))&DMA_INT_INT6_MASK)
2588 #define DMA_INT_INT7_MASK 0x80u
2589 #define DMA_INT_INT7_SHIFT 7u
2590 #define DMA_INT_INT7_WIDTH 1u
2591 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT7_SHIFT))&DMA_INT_INT7_MASK)
2592 #define DMA_INT_INT8_MASK 0x100u
2593 #define DMA_INT_INT8_SHIFT 8u
2594 #define DMA_INT_INT8_WIDTH 1u
2595 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT8_SHIFT))&DMA_INT_INT8_MASK)
2596 #define DMA_INT_INT9_MASK 0x200u
2597 #define DMA_INT_INT9_SHIFT 9u
2598 #define DMA_INT_INT9_WIDTH 1u
2599 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT9_SHIFT))&DMA_INT_INT9_MASK)
2600 #define DMA_INT_INT10_MASK 0x400u
2601 #define DMA_INT_INT10_SHIFT 10u
2602 #define DMA_INT_INT10_WIDTH 1u
2603 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT10_SHIFT))&DMA_INT_INT10_MASK)
2604 #define DMA_INT_INT11_MASK 0x800u
2605 #define DMA_INT_INT11_SHIFT 11u
2606 #define DMA_INT_INT11_WIDTH 1u
2607 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT11_SHIFT))&DMA_INT_INT11_MASK)
2608 #define DMA_INT_INT12_MASK 0x1000u
2609 #define DMA_INT_INT12_SHIFT 12u
2610 #define DMA_INT_INT12_WIDTH 1u
2611 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT12_SHIFT))&DMA_INT_INT12_MASK)
2612 #define DMA_INT_INT13_MASK 0x2000u
2613 #define DMA_INT_INT13_SHIFT 13u
2614 #define DMA_INT_INT13_WIDTH 1u
2615 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT13_SHIFT))&DMA_INT_INT13_MASK)
2616 #define DMA_INT_INT14_MASK 0x4000u
2617 #define DMA_INT_INT14_SHIFT 14u
2618 #define DMA_INT_INT14_WIDTH 1u
2619 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT14_SHIFT))&DMA_INT_INT14_MASK)
2620 #define DMA_INT_INT15_MASK 0x8000u
2621 #define DMA_INT_INT15_SHIFT 15u
2622 #define DMA_INT_INT15_WIDTH 1u
2623 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x))<<DMA_INT_INT15_SHIFT))&DMA_INT_INT15_MASK)
2624 /* ERR Bit Fields */
2625 #define DMA_ERR_ERR0_MASK 0x1u
2626 #define DMA_ERR_ERR0_SHIFT 0u
2627 #define DMA_ERR_ERR0_WIDTH 1u
2628 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR0_SHIFT))&DMA_ERR_ERR0_MASK)
2629 #define DMA_ERR_ERR1_MASK 0x2u
2630 #define DMA_ERR_ERR1_SHIFT 1u
2631 #define DMA_ERR_ERR1_WIDTH 1u
2632 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR1_SHIFT))&DMA_ERR_ERR1_MASK)
2633 #define DMA_ERR_ERR2_MASK 0x4u
2634 #define DMA_ERR_ERR2_SHIFT 2u
2635 #define DMA_ERR_ERR2_WIDTH 1u
2636 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR2_SHIFT))&DMA_ERR_ERR2_MASK)
2637 #define DMA_ERR_ERR3_MASK 0x8u
2638 #define DMA_ERR_ERR3_SHIFT 3u
2639 #define DMA_ERR_ERR3_WIDTH 1u
2640 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR3_SHIFT))&DMA_ERR_ERR3_MASK)
2641 #define DMA_ERR_ERR4_MASK 0x10u
2642 #define DMA_ERR_ERR4_SHIFT 4u
2643 #define DMA_ERR_ERR4_WIDTH 1u
2644 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR4_SHIFT))&DMA_ERR_ERR4_MASK)
2645 #define DMA_ERR_ERR5_MASK 0x20u
2646 #define DMA_ERR_ERR5_SHIFT 5u
2647 #define DMA_ERR_ERR5_WIDTH 1u
2648 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR5_SHIFT))&DMA_ERR_ERR5_MASK)
2649 #define DMA_ERR_ERR6_MASK 0x40u
2650 #define DMA_ERR_ERR6_SHIFT 6u
2651 #define DMA_ERR_ERR6_WIDTH 1u
2652 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR6_SHIFT))&DMA_ERR_ERR6_MASK)
2653 #define DMA_ERR_ERR7_MASK 0x80u
2654 #define DMA_ERR_ERR7_SHIFT 7u
2655 #define DMA_ERR_ERR7_WIDTH 1u
2656 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR7_SHIFT))&DMA_ERR_ERR7_MASK)
2657 #define DMA_ERR_ERR8_MASK 0x100u
2658 #define DMA_ERR_ERR8_SHIFT 8u
2659 #define DMA_ERR_ERR8_WIDTH 1u
2660 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR8_SHIFT))&DMA_ERR_ERR8_MASK)
2661 #define DMA_ERR_ERR9_MASK 0x200u
2662 #define DMA_ERR_ERR9_SHIFT 9u
2663 #define DMA_ERR_ERR9_WIDTH 1u
2664 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR9_SHIFT))&DMA_ERR_ERR9_MASK)
2665 #define DMA_ERR_ERR10_MASK 0x400u
2666 #define DMA_ERR_ERR10_SHIFT 10u
2667 #define DMA_ERR_ERR10_WIDTH 1u
2668 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR10_SHIFT))&DMA_ERR_ERR10_MASK)
2669 #define DMA_ERR_ERR11_MASK 0x800u
2670 #define DMA_ERR_ERR11_SHIFT 11u
2671 #define DMA_ERR_ERR11_WIDTH 1u
2672 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR11_SHIFT))&DMA_ERR_ERR11_MASK)
2673 #define DMA_ERR_ERR12_MASK 0x1000u
2674 #define DMA_ERR_ERR12_SHIFT 12u
2675 #define DMA_ERR_ERR12_WIDTH 1u
2676 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR12_SHIFT))&DMA_ERR_ERR12_MASK)
2677 #define DMA_ERR_ERR13_MASK 0x2000u
2678 #define DMA_ERR_ERR13_SHIFT 13u
2679 #define DMA_ERR_ERR13_WIDTH 1u
2680 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR13_SHIFT))&DMA_ERR_ERR13_MASK)
2681 #define DMA_ERR_ERR14_MASK 0x4000u
2682 #define DMA_ERR_ERR14_SHIFT 14u
2683 #define DMA_ERR_ERR14_WIDTH 1u
2684 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR14_SHIFT))&DMA_ERR_ERR14_MASK)
2685 #define DMA_ERR_ERR15_MASK 0x8000u
2686 #define DMA_ERR_ERR15_SHIFT 15u
2687 #define DMA_ERR_ERR15_WIDTH 1u
2688 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x))<<DMA_ERR_ERR15_SHIFT))&DMA_ERR_ERR15_MASK)
2689 /* HRS Bit Fields */
2690 #define DMA_HRS_HRS0_MASK 0x1u
2691 #define DMA_HRS_HRS0_SHIFT 0u
2692 #define DMA_HRS_HRS0_WIDTH 1u
2693 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS0_SHIFT))&DMA_HRS_HRS0_MASK)
2694 #define DMA_HRS_HRS1_MASK 0x2u
2695 #define DMA_HRS_HRS1_SHIFT 1u
2696 #define DMA_HRS_HRS1_WIDTH 1u
2697 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS1_SHIFT))&DMA_HRS_HRS1_MASK)
2698 #define DMA_HRS_HRS2_MASK 0x4u
2699 #define DMA_HRS_HRS2_SHIFT 2u
2700 #define DMA_HRS_HRS2_WIDTH 1u
2701 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS2_SHIFT))&DMA_HRS_HRS2_MASK)
2702 #define DMA_HRS_HRS3_MASK 0x8u
2703 #define DMA_HRS_HRS3_SHIFT 3u
2704 #define DMA_HRS_HRS3_WIDTH 1u
2705 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS3_SHIFT))&DMA_HRS_HRS3_MASK)
2706 #define DMA_HRS_HRS4_MASK 0x10u
2707 #define DMA_HRS_HRS4_SHIFT 4u
2708 #define DMA_HRS_HRS4_WIDTH 1u
2709 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS4_SHIFT))&DMA_HRS_HRS4_MASK)
2710 #define DMA_HRS_HRS5_MASK 0x20u
2711 #define DMA_HRS_HRS5_SHIFT 5u
2712 #define DMA_HRS_HRS5_WIDTH 1u
2713 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS5_SHIFT))&DMA_HRS_HRS5_MASK)
2714 #define DMA_HRS_HRS6_MASK 0x40u
2715 #define DMA_HRS_HRS6_SHIFT 6u
2716 #define DMA_HRS_HRS6_WIDTH 1u
2717 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS6_SHIFT))&DMA_HRS_HRS6_MASK)
2718 #define DMA_HRS_HRS7_MASK 0x80u
2719 #define DMA_HRS_HRS7_SHIFT 7u
2720 #define DMA_HRS_HRS7_WIDTH 1u
2721 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS7_SHIFT))&DMA_HRS_HRS7_MASK)
2722 #define DMA_HRS_HRS8_MASK 0x100u
2723 #define DMA_HRS_HRS8_SHIFT 8u
2724 #define DMA_HRS_HRS8_WIDTH 1u
2725 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS8_SHIFT))&DMA_HRS_HRS8_MASK)
2726 #define DMA_HRS_HRS9_MASK 0x200u
2727 #define DMA_HRS_HRS9_SHIFT 9u
2728 #define DMA_HRS_HRS9_WIDTH 1u
2729 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS9_SHIFT))&DMA_HRS_HRS9_MASK)
2730 #define DMA_HRS_HRS10_MASK 0x400u
2731 #define DMA_HRS_HRS10_SHIFT 10u
2732 #define DMA_HRS_HRS10_WIDTH 1u
2733 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS10_SHIFT))&DMA_HRS_HRS10_MASK)
2734 #define DMA_HRS_HRS11_MASK 0x800u
2735 #define DMA_HRS_HRS11_SHIFT 11u
2736 #define DMA_HRS_HRS11_WIDTH 1u
2737 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS11_SHIFT))&DMA_HRS_HRS11_MASK)
2738 #define DMA_HRS_HRS12_MASK 0x1000u
2739 #define DMA_HRS_HRS12_SHIFT 12u
2740 #define DMA_HRS_HRS12_WIDTH 1u
2741 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS12_SHIFT))&DMA_HRS_HRS12_MASK)
2742 #define DMA_HRS_HRS13_MASK 0x2000u
2743 #define DMA_HRS_HRS13_SHIFT 13u
2744 #define DMA_HRS_HRS13_WIDTH 1u
2745 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS13_SHIFT))&DMA_HRS_HRS13_MASK)
2746 #define DMA_HRS_HRS14_MASK 0x4000u
2747 #define DMA_HRS_HRS14_SHIFT 14u
2748 #define DMA_HRS_HRS14_WIDTH 1u
2749 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS14_SHIFT))&DMA_HRS_HRS14_MASK)
2750 #define DMA_HRS_HRS15_MASK 0x8000u
2751 #define DMA_HRS_HRS15_SHIFT 15u
2752 #define DMA_HRS_HRS15_WIDTH 1u
2753 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x))<<DMA_HRS_HRS15_SHIFT))&DMA_HRS_HRS15_MASK)
2754 /* EARS Bit Fields */
2755 #define DMA_EARS_EDREQ_0_MASK 0x1u
2756 #define DMA_EARS_EDREQ_0_SHIFT 0u
2757 #define DMA_EARS_EDREQ_0_WIDTH 1u
2758 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_0_SHIFT))&DMA_EARS_EDREQ_0_MASK)
2759 #define DMA_EARS_EDREQ_1_MASK 0x2u
2760 #define DMA_EARS_EDREQ_1_SHIFT 1u
2761 #define DMA_EARS_EDREQ_1_WIDTH 1u
2762 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_1_SHIFT))&DMA_EARS_EDREQ_1_MASK)
2763 #define DMA_EARS_EDREQ_2_MASK 0x4u
2764 #define DMA_EARS_EDREQ_2_SHIFT 2u
2765 #define DMA_EARS_EDREQ_2_WIDTH 1u
2766 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_2_SHIFT))&DMA_EARS_EDREQ_2_MASK)
2767 #define DMA_EARS_EDREQ_3_MASK 0x8u
2768 #define DMA_EARS_EDREQ_3_SHIFT 3u
2769 #define DMA_EARS_EDREQ_3_WIDTH 1u
2770 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_3_SHIFT))&DMA_EARS_EDREQ_3_MASK)
2771 #define DMA_EARS_EDREQ_4_MASK 0x10u
2772 #define DMA_EARS_EDREQ_4_SHIFT 4u
2773 #define DMA_EARS_EDREQ_4_WIDTH 1u
2774 #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_4_SHIFT))&DMA_EARS_EDREQ_4_MASK)
2775 #define DMA_EARS_EDREQ_5_MASK 0x20u
2776 #define DMA_EARS_EDREQ_5_SHIFT 5u
2777 #define DMA_EARS_EDREQ_5_WIDTH 1u
2778 #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_5_SHIFT))&DMA_EARS_EDREQ_5_MASK)
2779 #define DMA_EARS_EDREQ_6_MASK 0x40u
2780 #define DMA_EARS_EDREQ_6_SHIFT 6u
2781 #define DMA_EARS_EDREQ_6_WIDTH 1u
2782 #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_6_SHIFT))&DMA_EARS_EDREQ_6_MASK)
2783 #define DMA_EARS_EDREQ_7_MASK 0x80u
2784 #define DMA_EARS_EDREQ_7_SHIFT 7u
2785 #define DMA_EARS_EDREQ_7_WIDTH 1u
2786 #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_7_SHIFT))&DMA_EARS_EDREQ_7_MASK)
2787 #define DMA_EARS_EDREQ_8_MASK 0x100u
2788 #define DMA_EARS_EDREQ_8_SHIFT 8u
2789 #define DMA_EARS_EDREQ_8_WIDTH 1u
2790 #define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_8_SHIFT))&DMA_EARS_EDREQ_8_MASK)
2791 #define DMA_EARS_EDREQ_9_MASK 0x200u
2792 #define DMA_EARS_EDREQ_9_SHIFT 9u
2793 #define DMA_EARS_EDREQ_9_WIDTH 1u
2794 #define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_9_SHIFT))&DMA_EARS_EDREQ_9_MASK)
2795 #define DMA_EARS_EDREQ_10_MASK 0x400u
2796 #define DMA_EARS_EDREQ_10_SHIFT 10u
2797 #define DMA_EARS_EDREQ_10_WIDTH 1u
2798 #define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_10_SHIFT))&DMA_EARS_EDREQ_10_MASK)
2799 #define DMA_EARS_EDREQ_11_MASK 0x800u
2800 #define DMA_EARS_EDREQ_11_SHIFT 11u
2801 #define DMA_EARS_EDREQ_11_WIDTH 1u
2802 #define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_11_SHIFT))&DMA_EARS_EDREQ_11_MASK)
2803 #define DMA_EARS_EDREQ_12_MASK 0x1000u
2804 #define DMA_EARS_EDREQ_12_SHIFT 12u
2805 #define DMA_EARS_EDREQ_12_WIDTH 1u
2806 #define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_12_SHIFT))&DMA_EARS_EDREQ_12_MASK)
2807 #define DMA_EARS_EDREQ_13_MASK 0x2000u
2808 #define DMA_EARS_EDREQ_13_SHIFT 13u
2809 #define DMA_EARS_EDREQ_13_WIDTH 1u
2810 #define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_13_SHIFT))&DMA_EARS_EDREQ_13_MASK)
2811 #define DMA_EARS_EDREQ_14_MASK 0x4000u
2812 #define DMA_EARS_EDREQ_14_SHIFT 14u
2813 #define DMA_EARS_EDREQ_14_WIDTH 1u
2814 #define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_14_SHIFT))&DMA_EARS_EDREQ_14_MASK)
2815 #define DMA_EARS_EDREQ_15_MASK 0x8000u
2816 #define DMA_EARS_EDREQ_15_SHIFT 15u
2817 #define DMA_EARS_EDREQ_15_WIDTH 1u
2818 #define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x))<<DMA_EARS_EDREQ_15_SHIFT))&DMA_EARS_EDREQ_15_MASK)
2819 /* DCHPRI Bit Fields */
2820 #define DMA_DCHPRI_CHPRI_MASK 0xFu
2821 #define DMA_DCHPRI_CHPRI_SHIFT 0u
2822 #define DMA_DCHPRI_CHPRI_WIDTH 4u
2823 #define DMA_DCHPRI_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_CHPRI_SHIFT))&DMA_DCHPRI_CHPRI_MASK)
2824 #define DMA_DCHPRI_DPA_MASK 0x40u
2825 #define DMA_DCHPRI_DPA_SHIFT 6u
2826 #define DMA_DCHPRI_DPA_WIDTH 1u
2827 #define DMA_DCHPRI_DPA(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_DPA_SHIFT))&DMA_DCHPRI_DPA_MASK)
2828 #define DMA_DCHPRI_ECP_MASK 0x80u
2829 #define DMA_DCHPRI_ECP_SHIFT 7u
2830 #define DMA_DCHPRI_ECP_WIDTH 1u
2831 #define DMA_DCHPRI_ECP(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI_ECP_SHIFT))&DMA_DCHPRI_ECP_MASK)
2832 /* TCD_SADDR Bit Fields */
2833 #define DMA_TCD_SADDR_SADDR_MASK 0xFFFFFFFFu
2834 #define DMA_TCD_SADDR_SADDR_SHIFT 0u
2835 #define DMA_TCD_SADDR_SADDR_WIDTH 32u
2836 #define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SADDR_SADDR_SHIFT))&DMA_TCD_SADDR_SADDR_MASK)
2837 /* TCD_SOFF Bit Fields */
2838 #define DMA_TCD_SOFF_SOFF_MASK 0xFFFFu
2839 #define DMA_TCD_SOFF_SOFF_SHIFT 0u
2840 #define DMA_TCD_SOFF_SOFF_WIDTH 16u
2841 #define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_SOFF_SOFF_SHIFT))&DMA_TCD_SOFF_SOFF_MASK)
2842 /* TCD_ATTR Bit Fields */
2843 #define DMA_TCD_ATTR_DSIZE_MASK 0x7u
2844 #define DMA_TCD_ATTR_DSIZE_SHIFT 0u
2845 #define DMA_TCD_ATTR_DSIZE_WIDTH 3u
2846 #define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DSIZE_SHIFT))&DMA_TCD_ATTR_DSIZE_MASK)
2847 #define DMA_TCD_ATTR_DMOD_MASK 0xF8u
2848 #define DMA_TCD_ATTR_DMOD_SHIFT 3u
2849 #define DMA_TCD_ATTR_DMOD_WIDTH 5u
2850 #define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_DMOD_SHIFT))&DMA_TCD_ATTR_DMOD_MASK)
2851 #define DMA_TCD_ATTR_SSIZE_MASK 0x700u
2852 #define DMA_TCD_ATTR_SSIZE_SHIFT 8u
2853 #define DMA_TCD_ATTR_SSIZE_WIDTH 3u
2854 #define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SSIZE_SHIFT))&DMA_TCD_ATTR_SSIZE_MASK)
2855 #define DMA_TCD_ATTR_SMOD_MASK 0xF800u
2856 #define DMA_TCD_ATTR_SMOD_SHIFT 11u
2857 #define DMA_TCD_ATTR_SMOD_WIDTH 5u
2858 #define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_ATTR_SMOD_SHIFT))&DMA_TCD_ATTR_SMOD_MASK)
2859 /* TCD_NBYTES_MLNO Bit Fields */
2860 #define DMA_TCD_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
2861 #define DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT 0u
2862 #define DMA_TCD_NBYTES_MLNO_NBYTES_WIDTH 32u
2863 #define DMA_TCD_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLNO_NBYTES_MASK)
2864 /* TCD_NBYTES_MLOFFNO Bit Fields */
2865 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
2866 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT 0u
2867 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH 30u
2868 #define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
2869 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
2870 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT 30u
2871 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH 1u
2872 #define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
2873 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
2874 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT 31u
2875 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH 1u
2876 #define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
2877 /* TCD_NBYTES_MLOFFYES Bit Fields */
2878 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
2879 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT 0u
2880 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH 10u
2881 #define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
2882 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
2883 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT 10u
2884 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH 20u
2885 #define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
2886 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
2887 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT 30u
2888 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH 1u
2889 #define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
2890 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
2891 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT 31u
2892 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH 1u
2893 #define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT))&DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
2894 /* TCD_SLAST Bit Fields */
2895 #define DMA_TCD_SLAST_SLAST_MASK 0xFFFFFFFFu
2896 #define DMA_TCD_SLAST_SLAST_SHIFT 0u
2897 #define DMA_TCD_SLAST_SLAST_WIDTH 32u
2898 #define DMA_TCD_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_SLAST_SLAST_SHIFT))&DMA_TCD_SLAST_SLAST_MASK)
2899 /* TCD_DADDR Bit Fields */
2900 #define DMA_TCD_DADDR_DADDR_MASK 0xFFFFFFFFu
2901 #define DMA_TCD_DADDR_DADDR_SHIFT 0u
2902 #define DMA_TCD_DADDR_DADDR_WIDTH 32u
2903 #define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DADDR_DADDR_SHIFT))&DMA_TCD_DADDR_DADDR_MASK)
2904 /* TCD_DOFF Bit Fields */
2905 #define DMA_TCD_DOFF_DOFF_MASK 0xFFFFu
2906 #define DMA_TCD_DOFF_DOFF_SHIFT 0u
2907 #define DMA_TCD_DOFF_DOFF_WIDTH 16u
2908 #define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_DOFF_DOFF_SHIFT))&DMA_TCD_DOFF_DOFF_MASK)
2909 /* TCD_CITER_ELINKNO Bit Fields */
2910 #define DMA_TCD_CITER_ELINKNO_CITER_MASK 0x7FFFu
2911 #define DMA_TCD_CITER_ELINKNO_CITER_SHIFT 0u
2912 #define DMA_TCD_CITER_ELINKNO_CITER_WIDTH 15u
2913 #define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_CITER_SHIFT))&DMA_TCD_CITER_ELINKNO_CITER_MASK)
2914 #define DMA_TCD_CITER_ELINKNO_ELINK_MASK 0x8000u
2915 #define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT 15u
2916 #define DMA_TCD_CITER_ELINKNO_ELINK_WIDTH 1u
2917 #define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_CITER_ELINKNO_ELINK_MASK)
2918 /* TCD_CITER_ELINKYES Bit Fields */
2919 #define DMA_TCD_CITER_ELINKYES_CITER_LE_MASK 0x1FFu
2920 #define DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT 0u
2921 #define DMA_TCD_CITER_ELINKYES_CITER_LE_WIDTH 9u
2922 #define DMA_TCD_CITER_ELINKYES_CITER_LE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_CITER_LE_SHIFT))&DMA_TCD_CITER_ELINKYES_CITER_LE_MASK)
2923 #define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00u
2924 #define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT 9u
2925 #define DMA_TCD_CITER_ELINKYES_LINKCH_WIDTH 4u
2926 #define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_CITER_ELINKYES_LINKCH_MASK)
2927 #define DMA_TCD_CITER_ELINKYES_ELINK_MASK 0x8000u
2928 #define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT 15u
2929 #define DMA_TCD_CITER_ELINKYES_ELINK_WIDTH 1u
2930 #define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_CITER_ELINKYES_ELINK_MASK)
2931 /* TCD_DLASTSGA Bit Fields */
2932 #define DMA_TCD_DLASTSGA_DLASTSGA_MASK 0xFFFFFFFFu
2933 #define DMA_TCD_DLASTSGA_DLASTSGA_SHIFT 0u
2934 #define DMA_TCD_DLASTSGA_DLASTSGA_WIDTH 32u
2935 #define DMA_TCD_DLASTSGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_TCD_DLASTSGA_DLASTSGA_SHIFT))&DMA_TCD_DLASTSGA_DLASTSGA_MASK)
2936 /* TCD_CSR Bit Fields */
2937 #define DMA_TCD_CSR_START_MASK 0x1u
2938 #define DMA_TCD_CSR_START_SHIFT 0u
2939 #define DMA_TCD_CSR_START_WIDTH 1u
2940 #define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_START_SHIFT))&DMA_TCD_CSR_START_MASK)
2941 #define DMA_TCD_CSR_INTMAJOR_MASK 0x2u
2942 #define DMA_TCD_CSR_INTMAJOR_SHIFT 1u
2943 #define DMA_TCD_CSR_INTMAJOR_WIDTH 1u
2944 #define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTMAJOR_SHIFT))&DMA_TCD_CSR_INTMAJOR_MASK)
2945 #define DMA_TCD_CSR_INTHALF_MASK 0x4u
2946 #define DMA_TCD_CSR_INTHALF_SHIFT 2u
2947 #define DMA_TCD_CSR_INTHALF_WIDTH 1u
2948 #define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_INTHALF_SHIFT))&DMA_TCD_CSR_INTHALF_MASK)
2949 #define DMA_TCD_CSR_DREQ_MASK 0x8u
2950 #define DMA_TCD_CSR_DREQ_SHIFT 3u
2951 #define DMA_TCD_CSR_DREQ_WIDTH 1u
2952 #define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DREQ_SHIFT))&DMA_TCD_CSR_DREQ_MASK)
2953 #define DMA_TCD_CSR_ESG_MASK 0x10u
2954 #define DMA_TCD_CSR_ESG_SHIFT 4u
2955 #define DMA_TCD_CSR_ESG_WIDTH 1u
2956 #define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ESG_SHIFT))&DMA_TCD_CSR_ESG_MASK)
2957 #define DMA_TCD_CSR_MAJORELINK_MASK 0x20u
2958 #define DMA_TCD_CSR_MAJORELINK_SHIFT 5u
2959 #define DMA_TCD_CSR_MAJORELINK_WIDTH 1u
2960 #define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORELINK_SHIFT))&DMA_TCD_CSR_MAJORELINK_MASK)
2961 #define DMA_TCD_CSR_ACTIVE_MASK 0x40u
2962 #define DMA_TCD_CSR_ACTIVE_SHIFT 6u
2963 #define DMA_TCD_CSR_ACTIVE_WIDTH 1u
2964 #define DMA_TCD_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_ACTIVE_SHIFT))&DMA_TCD_CSR_ACTIVE_MASK)
2965 #define DMA_TCD_CSR_DONE_MASK 0x80u
2966 #define DMA_TCD_CSR_DONE_SHIFT 7u
2967 #define DMA_TCD_CSR_DONE_WIDTH 1u
2968 #define DMA_TCD_CSR_DONE(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_DONE_SHIFT))&DMA_TCD_CSR_DONE_MASK)
2969 #define DMA_TCD_CSR_MAJORLINKCH_MASK 0xF00u
2970 #define DMA_TCD_CSR_MAJORLINKCH_SHIFT 8u
2971 #define DMA_TCD_CSR_MAJORLINKCH_WIDTH 4u
2972 #define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_MAJORLINKCH_SHIFT))&DMA_TCD_CSR_MAJORLINKCH_MASK)
2973 #define DMA_TCD_CSR_BWC_MASK 0xC000u
2974 #define DMA_TCD_CSR_BWC_SHIFT 14u
2975 #define DMA_TCD_CSR_BWC_WIDTH 2u
2976 #define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_CSR_BWC_SHIFT))&DMA_TCD_CSR_BWC_MASK)
2977 /* TCD_BITER_ELINKNO Bit Fields */
2978 #define DMA_TCD_BITER_ELINKNO_BITER_MASK 0x7FFFu
2979 #define DMA_TCD_BITER_ELINKNO_BITER_SHIFT 0u
2980 #define DMA_TCD_BITER_ELINKNO_BITER_WIDTH 15u
2981 #define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_BITER_SHIFT))&DMA_TCD_BITER_ELINKNO_BITER_MASK)
2982 #define DMA_TCD_BITER_ELINKNO_ELINK_MASK 0x8000u
2983 #define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT 15u
2984 #define DMA_TCD_BITER_ELINKNO_ELINK_WIDTH 1u
2985 #define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKNO_ELINK_SHIFT))&DMA_TCD_BITER_ELINKNO_ELINK_MASK)
2986 /* TCD_BITER_ELINKYES Bit Fields */
2987 #define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x1FFu
2988 #define DMA_TCD_BITER_ELINKYES_BITER_SHIFT 0u
2989 #define DMA_TCD_BITER_ELINKYES_BITER_WIDTH 9u
2990 #define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_BITER_SHIFT))&DMA_TCD_BITER_ELINKYES_BITER_MASK)
2991 #define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00u
2992 #define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT 9u
2993 #define DMA_TCD_BITER_ELINKYES_LINKCH_WIDTH 4u
2994 #define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT))&DMA_TCD_BITER_ELINKYES_LINKCH_MASK)
2995 #define DMA_TCD_BITER_ELINKYES_ELINK_MASK 0x8000u
2996 #define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT 15u
2997 #define DMA_TCD_BITER_ELINKYES_ELINK_WIDTH 1u
2998 #define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x))<<DMA_TCD_BITER_ELINKYES_ELINK_SHIFT))&DMA_TCD_BITER_ELINKYES_ELINK_MASK)
2999  /* end of group DMA_Register_Masks */
3003 
3004  /* end of group DMA_Peripheral_Access_Layer */
3008 
3009 
3010 /* ----------------------------------------------------------------------------
3011  -- DMAMUX Peripheral Access Layer
3012  ---------------------------------------------------------------------------- */
3013 
3021 #define DMAMUX_CHCFG_COUNT 16u
3022 
3024 typedef struct {
3025  __IO uint8_t CHCFG[DMAMUX_CHCFG_COUNT];
3027 
3029 #define DMAMUX_INSTANCE_COUNT (1u)
3030 
3031 
3032 /* DMAMUX - Peripheral instance base addresses */
3034 #define DMAMUX_BASE (0x40021000u)
3035 
3036 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3037 
3038 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
3039 
3040 #define DMAMUX_BASE_PTRS { DMAMUX }
3041 
3042 /* ----------------------------------------------------------------------------
3043  -- DMAMUX Register Masks
3044  ---------------------------------------------------------------------------- */
3045 
3051 /* CHCFG Bit Fields */
3052 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
3053 #define DMAMUX_CHCFG_SOURCE_SHIFT 0u
3054 #define DMAMUX_CHCFG_SOURCE_WIDTH 6u
3055 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
3056 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
3057 #define DMAMUX_CHCFG_TRIG_SHIFT 6u
3058 #define DMAMUX_CHCFG_TRIG_WIDTH 1u
3059 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_TRIG_SHIFT))&DMAMUX_CHCFG_TRIG_MASK)
3060 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
3061 #define DMAMUX_CHCFG_ENBL_SHIFT 7u
3062 #define DMAMUX_CHCFG_ENBL_WIDTH 1u
3063 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
3064  /* end of group DMAMUX_Register_Masks */
3068 
3069  /* end of group DMAMUX_Peripheral_Access_Layer */
3073 
3074 
3075 /* ----------------------------------------------------------------------------
3076  -- EIM Peripheral Access Layer
3077  ---------------------------------------------------------------------------- */
3078 
3086 #define EIM_EICHDn_COUNT 2u
3087 
3089 typedef struct {
3090  __IO uint32_t EIMCR;
3091  __IO uint32_t EICHEN;
3092  uint8_t RESERVED_0[248];
3093  struct { /* offset: 0x100, array step: 0x100 */
3094  __IO uint32_t WORD0;
3095  __IO uint32_t WORD1;
3096  uint8_t RESERVED_0[248];
3097  } EICHDn[EIM_EICHDn_COUNT];
3099 
3101 #define EIM_INSTANCE_COUNT (1u)
3102 
3103 
3104 /* EIM - Peripheral instance base addresses */
3106 #define EIM_BASE (0x40019000u)
3107 
3108 #define EIM ((EIM_Type *)EIM_BASE)
3109 
3110 #define EIM_BASE_ADDRS { EIM_BASE }
3111 
3112 #define EIM_BASE_PTRS { EIM }
3113 
3114 /* ----------------------------------------------------------------------------
3115  -- EIM Register Masks
3116  ---------------------------------------------------------------------------- */
3117 
3123 /* EIMCR Bit Fields */
3124 #define EIM_EIMCR_GEIEN_MASK 0x1u
3125 #define EIM_EIMCR_GEIEN_SHIFT 0u
3126 #define EIM_EIMCR_GEIEN_WIDTH 1u
3127 #define EIM_EIMCR_GEIEN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EIMCR_GEIEN_SHIFT))&EIM_EIMCR_GEIEN_MASK)
3128 /* EICHEN Bit Fields */
3129 #define EIM_EICHEN_EICH1EN_MASK 0x40000000u
3130 #define EIM_EICHEN_EICH1EN_SHIFT 30u
3131 #define EIM_EICHEN_EICH1EN_WIDTH 1u
3132 #define EIM_EICHEN_EICH1EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH1EN_SHIFT))&EIM_EICHEN_EICH1EN_MASK)
3133 #define EIM_EICHEN_EICH0EN_MASK 0x80000000u
3134 #define EIM_EICHEN_EICH0EN_SHIFT 31u
3135 #define EIM_EICHEN_EICH0EN_WIDTH 1u
3136 #define EIM_EICHEN_EICH0EN(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHEN_EICH0EN_SHIFT))&EIM_EICHEN_EICH0EN_MASK)
3137 /* EICHDn_WORD0 Bit Fields */
3138 #define EIM_EICHDn_WORD0_CHKBIT_MASK_MASK 0xFE000000u
3139 #define EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT 25u
3140 #define EIM_EICHDn_WORD0_CHKBIT_MASK_WIDTH 7u
3141 #define EIM_EICHDn_WORD0_CHKBIT_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD0_CHKBIT_MASK_SHIFT))&EIM_EICHDn_WORD0_CHKBIT_MASK_MASK)
3142 /* EICHDn_WORD1 Bit Fields */
3143 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK 0xFFFFFFFFu
3144 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT 0u
3145 #define EIM_EICHDn_WORD1_B0_3DATA_MASK_WIDTH 32u
3146 #define EIM_EICHDn_WORD1_B0_3DATA_MASK(x) (((uint32_t)(((uint32_t)(x))<<EIM_EICHDn_WORD1_B0_3DATA_MASK_SHIFT))&EIM_EICHDn_WORD1_B0_3DATA_MASK_MASK)
3147  /* end of group EIM_Register_Masks */
3151 
3152  /* end of group EIM_Peripheral_Access_Layer */
3156 
3157 
3158 /* ----------------------------------------------------------------------------
3159  -- ERM Peripheral Access Layer
3160  ---------------------------------------------------------------------------- */
3161 
3169 #define ERM_EARn_COUNT 2u
3170 
3172 typedef struct {
3173  __IO uint32_t CR0;
3174  uint8_t RESERVED_0[12];
3175  __IO uint32_t SR0;
3176  uint8_t RESERVED_1[236];
3177  struct { /* offset: 0x100, array step: 0x10 */
3178  __I uint32_t EAR;
3179  uint8_t RESERVED_0[12];
3180  } EARn[ERM_EARn_COUNT];
3182 
3184 #define ERM_INSTANCE_COUNT (1u)
3185 
3186 
3187 /* ERM - Peripheral instance base addresses */
3189 #define ERM_BASE (0x40018000u)
3190 
3191 #define ERM ((ERM_Type *)ERM_BASE)
3192 
3193 #define ERM_BASE_ADDRS { ERM_BASE }
3194 
3195 #define ERM_BASE_PTRS { ERM }
3196 
3197 #define ERM_IRQS_ARR_COUNT (2u)
3198 
3199 #define ERM_SINGLE_IRQS_CH_COUNT (1u)
3200 
3201 #define ERM_DOUBLE_IRQS_CH_COUNT (1u)
3202 
3203 #define ERM_SINGLE_IRQS { ERM_single_fault_IRQn }
3204 #define ERM_DOUBLE_IRQS { ERM_double_fault_IRQn }
3205 
3206 /* ----------------------------------------------------------------------------
3207  -- ERM Register Masks
3208  ---------------------------------------------------------------------------- */
3209 
3215 /* CR0 Bit Fields */
3216 #define ERM_CR0_ENCIE1_MASK 0x4000000u
3217 #define ERM_CR0_ENCIE1_SHIFT 26u
3218 #define ERM_CR0_ENCIE1_WIDTH 1u
3219 #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE1_SHIFT))&ERM_CR0_ENCIE1_MASK)
3220 #define ERM_CR0_ESCIE1_MASK 0x8000000u
3221 #define ERM_CR0_ESCIE1_SHIFT 27u
3222 #define ERM_CR0_ESCIE1_WIDTH 1u
3223 #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE1_SHIFT))&ERM_CR0_ESCIE1_MASK)
3224 #define ERM_CR0_ENCIE0_MASK 0x40000000u
3225 #define ERM_CR0_ENCIE0_SHIFT 30u
3226 #define ERM_CR0_ENCIE0_WIDTH 1u
3227 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ENCIE0_SHIFT))&ERM_CR0_ENCIE0_MASK)
3228 #define ERM_CR0_ESCIE0_MASK 0x80000000u
3229 #define ERM_CR0_ESCIE0_SHIFT 31u
3230 #define ERM_CR0_ESCIE0_WIDTH 1u
3231 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_CR0_ESCIE0_SHIFT))&ERM_CR0_ESCIE0_MASK)
3232 /* SR0 Bit Fields */
3233 #define ERM_SR0_NCE1_MASK 0x4000000u
3234 #define ERM_SR0_NCE1_SHIFT 26u
3235 #define ERM_SR0_NCE1_WIDTH 1u
3236 #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE1_SHIFT))&ERM_SR0_NCE1_MASK)
3237 #define ERM_SR0_SBC1_MASK 0x8000000u
3238 #define ERM_SR0_SBC1_SHIFT 27u
3239 #define ERM_SR0_SBC1_WIDTH 1u
3240 #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC1_SHIFT))&ERM_SR0_SBC1_MASK)
3241 #define ERM_SR0_NCE0_MASK 0x40000000u
3242 #define ERM_SR0_NCE0_SHIFT 30u
3243 #define ERM_SR0_NCE0_WIDTH 1u
3244 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_NCE0_SHIFT))&ERM_SR0_NCE0_MASK)
3245 #define ERM_SR0_SBC0_MASK 0x80000000u
3246 #define ERM_SR0_SBC0_SHIFT 31u
3247 #define ERM_SR0_SBC0_WIDTH 1u
3248 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x))<<ERM_SR0_SBC0_SHIFT))&ERM_SR0_SBC0_MASK)
3249 /* EARn_EAR Bit Fields */
3250 #define ERM_EARn_EAR_EAR_MASK 0xFFFFFFFFu
3251 #define ERM_EARn_EAR_EAR_SHIFT 0u
3252 #define ERM_EARn_EAR_EAR_WIDTH 32u
3253 #define ERM_EARn_EAR_EAR(x) (((uint32_t)(((uint32_t)(x))<<ERM_EARn_EAR_EAR_SHIFT))&ERM_EARn_EAR_EAR_MASK)
3254  /* end of group ERM_Register_Masks */
3258 
3259  /* end of group ERM_Peripheral_Access_Layer */
3263 
3264 
3265 /* ----------------------------------------------------------------------------
3266  -- EWM Peripheral Access Layer
3267  ---------------------------------------------------------------------------- */
3268 
3278 typedef struct {
3279  __IO uint8_t CTRL;
3280  __O uint8_t SERV;
3281  __IO uint8_t CMPL;
3282  __IO uint8_t CMPH;
3283  uint8_t RESERVED_0[1];
3284  __IO uint8_t CLKPRESCALER;
3286 
3288 #define EWM_INSTANCE_COUNT (1u)
3289 
3290 
3291 /* EWM - Peripheral instance base addresses */
3293 #define EWM_BASE (0x40061000u)
3294 
3295 #define EWM ((EWM_Type *)EWM_BASE)
3296 
3297 #define EWM_BASE_ADDRS { EWM_BASE }
3298 
3299 #define EWM_BASE_PTRS { EWM }
3300 
3301 #define EWM_IRQS_ARR_COUNT (1u)
3302 
3303 #define EWM_IRQS_CH_COUNT (1u)
3304 
3305 #define EWM_IRQS { WDOG_EWM_IRQn }
3306 
3307 /* ----------------------------------------------------------------------------
3308  -- EWM Register Masks
3309  ---------------------------------------------------------------------------- */
3310 
3316 /* CTRL Bit Fields */
3317 #define EWM_CTRL_EWMEN_MASK 0x1u
3318 #define EWM_CTRL_EWMEN_SHIFT 0u
3319 #define EWM_CTRL_EWMEN_WIDTH 1u
3320 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_EWMEN_SHIFT))&EWM_CTRL_EWMEN_MASK)
3321 #define EWM_CTRL_ASSIN_MASK 0x2u
3322 #define EWM_CTRL_ASSIN_SHIFT 1u
3323 #define EWM_CTRL_ASSIN_WIDTH 1u
3324 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_ASSIN_SHIFT))&EWM_CTRL_ASSIN_MASK)
3325 #define EWM_CTRL_INEN_MASK 0x4u
3326 #define EWM_CTRL_INEN_SHIFT 2u
3327 #define EWM_CTRL_INEN_WIDTH 1u
3328 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INEN_SHIFT))&EWM_CTRL_INEN_MASK)
3329 #define EWM_CTRL_INTEN_MASK 0x8u
3330 #define EWM_CTRL_INTEN_SHIFT 3u
3331 #define EWM_CTRL_INTEN_WIDTH 1u
3332 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x))<<EWM_CTRL_INTEN_SHIFT))&EWM_CTRL_INTEN_MASK)
3333 /* SERV Bit Fields */
3334 #define EWM_SERV_SERVICE_MASK 0xFFu
3335 #define EWM_SERV_SERVICE_SHIFT 0u
3336 #define EWM_SERV_SERVICE_WIDTH 8u
3337 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
3338 /* CMPL Bit Fields */
3339 #define EWM_CMPL_COMPAREL_MASK 0xFFu
3340 #define EWM_CMPL_COMPAREL_SHIFT 0u
3341 #define EWM_CMPL_COMPAREL_WIDTH 8u
3342 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
3343 /* CMPH Bit Fields */
3344 #define EWM_CMPH_COMPAREH_MASK 0xFFu
3345 #define EWM_CMPH_COMPAREH_SHIFT 0u
3346 #define EWM_CMPH_COMPAREH_WIDTH 8u
3347 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
3348 /* CLKPRESCALER Bit Fields */
3349 #define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
3350 #define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0u
3351 #define EWM_CLKPRESCALER_CLK_DIV_WIDTH 8u
3352 #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
3353  /* end of group EWM_Register_Masks */
3357 
3358  /* end of group EWM_Peripheral_Access_Layer */
3362 
3363 
3364 /* ----------------------------------------------------------------------------
3365  -- FLEXIO Peripheral Access Layer
3366  ---------------------------------------------------------------------------- */
3367 
3375 #define FLEXIO_SHIFTCTL_COUNT 4u
3376 #define FLEXIO_SHIFTCFG_COUNT 4u
3377 #define FLEXIO_SHIFTBUF_COUNT 4u
3378 #define FLEXIO_SHIFTBUFBIS_COUNT 4u
3379 #define FLEXIO_SHIFTBUFBYS_COUNT 4u
3380 #define FLEXIO_SHIFTBUFBBS_COUNT 4u
3381 #define FLEXIO_TIMCTL_COUNT 4u
3382 #define FLEXIO_TIMCFG_COUNT 4u
3383 #define FLEXIO_TIMCMP_COUNT 4u
3384 
3386 typedef struct {
3387  __I uint32_t VERID;
3388  __I uint32_t PARAM;
3389  __IO uint32_t CTRL;
3390  __I uint32_t PIN;
3391  __IO uint32_t SHIFTSTAT;
3392  __IO uint32_t SHIFTERR;
3393  __IO uint32_t TIMSTAT;
3394  uint8_t RESERVED_0[4];
3395  __IO uint32_t SHIFTSIEN;
3396  __IO uint32_t SHIFTEIEN;
3397  __IO uint32_t TIMIEN;
3398  uint8_t RESERVED_1[4];
3399  __IO uint32_t SHIFTSDEN;
3400  uint8_t RESERVED_2[76];
3401  __IO uint32_t SHIFTCTL[FLEXIO_SHIFTCTL_COUNT];
3402  uint8_t RESERVED_3[112];
3403  __IO uint32_t SHIFTCFG[FLEXIO_SHIFTCFG_COUNT];
3404  uint8_t RESERVED_4[240];
3405  __IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT];
3406  uint8_t RESERVED_5[112];
3407  __IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT];
3408  uint8_t RESERVED_6[112];
3409  __IO uint32_t SHIFTBUFBYS[FLEXIO_SHIFTBUFBYS_COUNT];
3410  uint8_t RESERVED_7[112];
3411  __IO uint32_t SHIFTBUFBBS[FLEXIO_SHIFTBUFBBS_COUNT];
3412  uint8_t RESERVED_8[112];
3413  __IO uint32_t TIMCTL[FLEXIO_TIMCTL_COUNT];
3414  uint8_t RESERVED_9[112];
3415  __IO uint32_t TIMCFG[FLEXIO_TIMCFG_COUNT];
3416  uint8_t RESERVED_10[112];
3417  __IO uint32_t TIMCMP[FLEXIO_TIMCMP_COUNT];
3419 
3421 #define FLEXIO_INSTANCE_COUNT (1u)
3422 
3423 
3424 /* FLEXIO - Peripheral instance base addresses */
3426 #define FLEXIO_BASE (0x4005A000u)
3427 
3428 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
3429 
3430 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
3431 
3432 #define FLEXIO_BASE_PTRS { FLEXIO }
3433 
3434 #define FLEXIO_IRQS_ARR_COUNT (1u)
3435 
3436 #define FLEXIO_IRQS_CH_COUNT (1u)
3437 
3438 #define FLEXIO_IRQS { FLEXIO_IRQn }
3439 
3440 /* ----------------------------------------------------------------------------
3441  -- FLEXIO Register Masks
3442  ---------------------------------------------------------------------------- */
3443 
3449 /* VERID Bit Fields */
3450 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
3451 #define FLEXIO_VERID_FEATURE_SHIFT 0u
3452 #define FLEXIO_VERID_FEATURE_WIDTH 16u
3453 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
3454 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
3455 #define FLEXIO_VERID_MINOR_SHIFT 16u
3456 #define FLEXIO_VERID_MINOR_WIDTH 8u
3457 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
3458 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
3459 #define FLEXIO_VERID_MAJOR_SHIFT 24u
3460 #define FLEXIO_VERID_MAJOR_WIDTH 8u
3461 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
3462 /* PARAM Bit Fields */
3463 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
3464 #define FLEXIO_PARAM_SHIFTER_SHIFT 0u
3465 #define FLEXIO_PARAM_SHIFTER_WIDTH 8u
3466 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
3467 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
3468 #define FLEXIO_PARAM_TIMER_SHIFT 8u
3469 #define FLEXIO_PARAM_TIMER_WIDTH 8u
3470 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
3471 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
3472 #define FLEXIO_PARAM_PIN_SHIFT 16u
3473 #define FLEXIO_PARAM_PIN_WIDTH 8u
3474 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
3475 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
3476 #define FLEXIO_PARAM_TRIGGER_SHIFT 24u
3477 #define FLEXIO_PARAM_TRIGGER_WIDTH 8u
3478 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
3479 /* CTRL Bit Fields */
3480 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
3481 #define FLEXIO_CTRL_FLEXEN_SHIFT 0u
3482 #define FLEXIO_CTRL_FLEXEN_WIDTH 1u
3483 #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FLEXEN_SHIFT))&FLEXIO_CTRL_FLEXEN_MASK)
3484 #define FLEXIO_CTRL_SWRST_MASK 0x2u
3485 #define FLEXIO_CTRL_SWRST_SHIFT 1u
3486 #define FLEXIO_CTRL_SWRST_WIDTH 1u
3487 #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_SWRST_SHIFT))&FLEXIO_CTRL_SWRST_MASK)
3488 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
3489 #define FLEXIO_CTRL_FASTACC_SHIFT 2u
3490 #define FLEXIO_CTRL_FASTACC_WIDTH 1u
3491 #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_FASTACC_SHIFT))&FLEXIO_CTRL_FASTACC_MASK)
3492 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
3493 #define FLEXIO_CTRL_DBGE_SHIFT 30u
3494 #define FLEXIO_CTRL_DBGE_WIDTH 1u
3495 #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DBGE_SHIFT))&FLEXIO_CTRL_DBGE_MASK)
3496 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
3497 #define FLEXIO_CTRL_DOZEN_SHIFT 31u
3498 #define FLEXIO_CTRL_DOZEN_WIDTH 1u
3499 #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_CTRL_DOZEN_SHIFT))&FLEXIO_CTRL_DOZEN_MASK)
3500 /* PIN Bit Fields */
3501 #define FLEXIO_PIN_PDI_MASK 0xFFu
3502 #define FLEXIO_PIN_PDI_SHIFT 0u
3503 #define FLEXIO_PIN_PDI_WIDTH 8u
3504 #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PIN_PDI_SHIFT))&FLEXIO_PIN_PDI_MASK)
3505 /* SHIFTSTAT Bit Fields */
3506 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
3507 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0u
3508 #define FLEXIO_SHIFTSTAT_SSF_WIDTH 4u
3509 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
3510 /* SHIFTERR Bit Fields */
3511 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
3512 #define FLEXIO_SHIFTERR_SEF_SHIFT 0u
3513 #define FLEXIO_SHIFTERR_SEF_WIDTH 4u
3514 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
3515 /* TIMSTAT Bit Fields */
3516 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
3517 #define FLEXIO_TIMSTAT_TSF_SHIFT 0u
3518 #define FLEXIO_TIMSTAT_TSF_WIDTH 4u
3519 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
3520 /* SHIFTSIEN Bit Fields */
3521 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
3522 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0u
3523 #define FLEXIO_SHIFTSIEN_SSIE_WIDTH 4u
3524 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
3525 /* SHIFTEIEN Bit Fields */
3526 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
3527 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0u
3528 #define FLEXIO_SHIFTEIEN_SEIE_WIDTH 4u
3529 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
3530 /* TIMIEN Bit Fields */
3531 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
3532 #define FLEXIO_TIMIEN_TEIE_SHIFT 0u
3533 #define FLEXIO_TIMIEN_TEIE_WIDTH 4u
3534 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
3535 /* SHIFTSDEN Bit Fields */
3536 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
3537 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0u
3538 #define FLEXIO_SHIFTSDEN_SSDE_WIDTH 4u
3539 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
3540 /* SHIFTCTL Bit Fields */
3541 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
3542 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0u
3543 #define FLEXIO_SHIFTCTL_SMOD_WIDTH 3u
3544 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
3545 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
3546 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7u
3547 #define FLEXIO_SHIFTCTL_PINPOL_WIDTH 1u
3548 #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINPOL_SHIFT))&FLEXIO_SHIFTCTL_PINPOL_MASK)
3549 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
3550 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8u
3551 #define FLEXIO_SHIFTCTL_PINSEL_WIDTH 3u
3552 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
3553 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
3554 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16u
3555 #define FLEXIO_SHIFTCTL_PINCFG_WIDTH 2u
3556 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
3557 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
3558 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23u
3559 #define FLEXIO_SHIFTCTL_TIMPOL_WIDTH 1u
3560 #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMPOL_SHIFT))&FLEXIO_SHIFTCTL_TIMPOL_MASK)
3561 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
3562 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24u
3563 #define FLEXIO_SHIFTCTL_TIMSEL_WIDTH 2u
3564 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
3565 /* SHIFTCFG Bit Fields */
3566 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
3567 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0u
3568 #define FLEXIO_SHIFTCFG_SSTART_WIDTH 2u
3569 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
3570 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
3571 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4u
3572 #define FLEXIO_SHIFTCFG_SSTOP_WIDTH 2u
3573 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
3574 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
3575 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8u
3576 #define FLEXIO_SHIFTCFG_INSRC_WIDTH 1u
3577 #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_INSRC_SHIFT))&FLEXIO_SHIFTCFG_INSRC_MASK)
3578 /* SHIFTBUF Bit Fields */
3579 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
3580 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0u
3581 #define FLEXIO_SHIFTBUF_SHIFTBUF_WIDTH 32u
3582 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
3583 /* SHIFTBUFBIS Bit Fields */
3584 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
3585 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0u
3586 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_WIDTH 32u
3587 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
3588 /* SHIFTBUFBYS Bit Fields */
3589 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
3590 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0u
3591 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_WIDTH 32u
3592 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
3593 /* SHIFTBUFBBS Bit Fields */
3594 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
3595 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0u
3596 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_WIDTH 32u
3597 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
3598 /* TIMCTL Bit Fields */
3599 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
3600 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0u
3601 #define FLEXIO_TIMCTL_TIMOD_WIDTH 2u
3602 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
3603 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
3604 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7u
3605 #define FLEXIO_TIMCTL_PINPOL_WIDTH 1u
3606 #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINPOL_SHIFT))&FLEXIO_TIMCTL_PINPOL_MASK)
3607 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
3608 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8u
3609 #define FLEXIO_TIMCTL_PINSEL_WIDTH 3u
3610 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
3611 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
3612 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16u
3613 #define FLEXIO_TIMCTL_PINCFG_WIDTH 2u
3614 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
3615 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
3616 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22u
3617 #define FLEXIO_TIMCTL_TRGSRC_WIDTH 1u
3618 #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSRC_SHIFT))&FLEXIO_TIMCTL_TRGSRC_MASK)
3619 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
3620 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23u
3621 #define FLEXIO_TIMCTL_TRGPOL_WIDTH 1u
3622 #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGPOL_SHIFT))&FLEXIO_TIMCTL_TRGPOL_MASK)
3623 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
3624 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24u
3625 #define FLEXIO_TIMCTL_TRGSEL_WIDTH 4u
3626 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
3627 /* TIMCFG Bit Fields */
3628 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
3629 #define FLEXIO_TIMCFG_TSTART_SHIFT 1u
3630 #define FLEXIO_TIMCFG_TSTART_WIDTH 1u
3631 #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTART_SHIFT))&FLEXIO_TIMCFG_TSTART_MASK)
3632 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
3633 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4u
3634 #define FLEXIO_TIMCFG_TSTOP_WIDTH 2u
3635 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
3636 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
3637 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8u
3638 #define FLEXIO_TIMCFG_TIMENA_WIDTH 3u
3639 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
3640 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
3641 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12u
3642 #define FLEXIO_TIMCFG_TIMDIS_WIDTH 3u
3643 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
3644 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
3645 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16u
3646 #define FLEXIO_TIMCFG_TIMRST_WIDTH 3u
3647 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
3648 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
3649 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20u
3650 #define FLEXIO_TIMCFG_TIMDEC_WIDTH 2u
3651 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
3652 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
3653 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24u
3654 #define FLEXIO_TIMCFG_TIMOUT_WIDTH 2u
3655 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
3656 /* TIMCMP Bit Fields */
3657 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
3658 #define FLEXIO_TIMCMP_CMP_SHIFT 0u
3659 #define FLEXIO_TIMCMP_CMP_WIDTH 16u
3660 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
3661  /* end of group FLEXIO_Register_Masks */
3665 
3666  /* end of group FLEXIO_Peripheral_Access_Layer */
3670 
3671 
3672 /* ----------------------------------------------------------------------------
3673  -- FTFC Peripheral Access Layer
3674  ---------------------------------------------------------------------------- */
3675 
3683 #define FTFC_FCCOB_COUNT 12u
3684 #define FTFC_FPROT_COUNT 4u
3685 
3687 typedef struct {
3688  __IO uint8_t FSTAT;
3689  __IO uint8_t FCNFG;
3690  __I uint8_t FSEC;
3691  __I uint8_t FOPT;
3692  __IO uint8_t FCCOB[FTFC_FCCOB_COUNT];
3693  __IO uint8_t FPROT[FTFC_FPROT_COUNT];
3694  uint8_t RESERVED_0[2];
3695  __IO uint8_t FEPROT;
3696  __IO uint8_t FDPROT;
3697  uint8_t RESERVED_1[20];
3698  __I uint8_t FCSESTAT;
3699  uint8_t RESERVED_2[1];
3700  __IO uint8_t FERSTAT;
3701  __IO uint8_t FERCNFG;
3703 
3705 #define FTFC_INSTANCE_COUNT (1u)
3706 
3707 
3708 /* FTFC - Peripheral instance base addresses */
3710 #define FTFC_BASE (0x40020000u)
3711 
3712 #define FTFC ((FTFC_Type *)FTFC_BASE)
3713 
3714 #define FTFC_BASE_ADDRS { FTFC_BASE }
3715 
3716 #define FTFC_BASE_PTRS { FTFC }
3717 
3718 #define FTFC_IRQS_ARR_COUNT (2u)
3719 
3720 #define FTFC_COMMAND_COMPLETE_IRQS_CH_COUNT (1u)
3721 
3722 #define FTFC_READ_COLLISION_IRQS_CH_COUNT (1u)
3723 
3724 #define FTFC_COMMAND_COMPLETE_IRQS { FTFC_IRQn }
3725 #define FTFC_READ_COLLISION_IRQS { Read_Collision_IRQn }
3726 
3727 /* ----------------------------------------------------------------------------
3728  -- FTFC Register Masks
3729  ---------------------------------------------------------------------------- */
3730 
3736 /* FSTAT Bit Fields */
3737 #define FTFC_FSTAT_MGSTAT0_MASK 0x1u
3738 #define FTFC_FSTAT_MGSTAT0_SHIFT 0u
3739 #define FTFC_FSTAT_MGSTAT0_WIDTH 1u
3740 #define FTFC_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_MGSTAT0_SHIFT))&FTFC_FSTAT_MGSTAT0_MASK)
3741 #define FTFC_FSTAT_FPVIOL_MASK 0x10u
3742 #define FTFC_FSTAT_FPVIOL_SHIFT 4u
3743 #define FTFC_FSTAT_FPVIOL_WIDTH 1u
3744 #define FTFC_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_FPVIOL_SHIFT))&FTFC_FSTAT_FPVIOL_MASK)
3745 #define FTFC_FSTAT_ACCERR_MASK 0x20u
3746 #define FTFC_FSTAT_ACCERR_SHIFT 5u
3747 #define FTFC_FSTAT_ACCERR_WIDTH 1u
3748 #define FTFC_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_ACCERR_SHIFT))&FTFC_FSTAT_ACCERR_MASK)
3749 #define FTFC_FSTAT_RDCOLERR_MASK 0x40u
3750 #define FTFC_FSTAT_RDCOLERR_SHIFT 6u
3751 #define FTFC_FSTAT_RDCOLERR_WIDTH 1u
3752 #define FTFC_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_RDCOLERR_SHIFT))&FTFC_FSTAT_RDCOLERR_MASK)
3753 #define FTFC_FSTAT_CCIF_MASK 0x80u
3754 #define FTFC_FSTAT_CCIF_SHIFT 7u
3755 #define FTFC_FSTAT_CCIF_WIDTH 1u
3756 #define FTFC_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSTAT_CCIF_SHIFT))&FTFC_FSTAT_CCIF_MASK)
3757 /* FCNFG Bit Fields */
3758 #define FTFC_FCNFG_EEERDY_MASK 0x1u
3759 #define FTFC_FCNFG_EEERDY_SHIFT 0u
3760 #define FTFC_FCNFG_EEERDY_WIDTH 1u
3761 #define FTFC_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_EEERDY_SHIFT))&FTFC_FCNFG_EEERDY_MASK)
3762 #define FTFC_FCNFG_RAMRDY_MASK 0x2u
3763 #define FTFC_FCNFG_RAMRDY_SHIFT 1u
3764 #define FTFC_FCNFG_RAMRDY_WIDTH 1u
3765 #define FTFC_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RAMRDY_SHIFT))&FTFC_FCNFG_RAMRDY_MASK)
3766 #define FTFC_FCNFG_ERSSUSP_MASK 0x10u
3767 #define FTFC_FCNFG_ERSSUSP_SHIFT 4u
3768 #define FTFC_FCNFG_ERSSUSP_WIDTH 1u
3769 #define FTFC_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSSUSP_SHIFT))&FTFC_FCNFG_ERSSUSP_MASK)
3770 #define FTFC_FCNFG_ERSAREQ_MASK 0x20u
3771 #define FTFC_FCNFG_ERSAREQ_SHIFT 5u
3772 #define FTFC_FCNFG_ERSAREQ_WIDTH 1u
3773 #define FTFC_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_ERSAREQ_SHIFT))&FTFC_FCNFG_ERSAREQ_MASK)
3774 #define FTFC_FCNFG_RDCOLLIE_MASK 0x40u
3775 #define FTFC_FCNFG_RDCOLLIE_SHIFT 6u
3776 #define FTFC_FCNFG_RDCOLLIE_WIDTH 1u
3777 #define FTFC_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_RDCOLLIE_SHIFT))&FTFC_FCNFG_RDCOLLIE_MASK)
3778 #define FTFC_FCNFG_CCIE_MASK 0x80u
3779 #define FTFC_FCNFG_CCIE_SHIFT 7u
3780 #define FTFC_FCNFG_CCIE_WIDTH 1u
3781 #define FTFC_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCNFG_CCIE_SHIFT))&FTFC_FCNFG_CCIE_MASK)
3782 /* FSEC Bit Fields */
3783 #define FTFC_FSEC_SEC_MASK 0x3u
3784 #define FTFC_FSEC_SEC_SHIFT 0u
3785 #define FTFC_FSEC_SEC_WIDTH 2u
3786 #define FTFC_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_SEC_SHIFT))&FTFC_FSEC_SEC_MASK)
3787 #define FTFC_FSEC_FSLACC_MASK 0xCu
3788 #define FTFC_FSEC_FSLACC_SHIFT 2u
3789 #define FTFC_FSEC_FSLACC_WIDTH 2u
3790 #define FTFC_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_FSLACC_SHIFT))&FTFC_FSEC_FSLACC_MASK)
3791 #define FTFC_FSEC_MEEN_MASK 0x30u
3792 #define FTFC_FSEC_MEEN_SHIFT 4u
3793 #define FTFC_FSEC_MEEN_WIDTH 2u
3794 #define FTFC_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_MEEN_SHIFT))&FTFC_FSEC_MEEN_MASK)
3795 #define FTFC_FSEC_KEYEN_MASK 0xC0u
3796 #define FTFC_FSEC_KEYEN_SHIFT 6u
3797 #define FTFC_FSEC_KEYEN_WIDTH 2u
3798 #define FTFC_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FSEC_KEYEN_SHIFT))&FTFC_FSEC_KEYEN_MASK)
3799 /* FOPT Bit Fields */
3800 #define FTFC_FOPT_OPT_MASK 0xFFu
3801 #define FTFC_FOPT_OPT_SHIFT 0u
3802 #define FTFC_FOPT_OPT_WIDTH 8u
3803 #define FTFC_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FOPT_OPT_SHIFT))&FTFC_FOPT_OPT_MASK)
3804 /* FCCOB Bit Fields */
3805 #define FTFC_FCCOB_CCOBn_MASK 0xFFu
3806 #define FTFC_FCCOB_CCOBn_SHIFT 0u
3807 #define FTFC_FCCOB_CCOBn_WIDTH 8u
3808 #define FTFC_FCCOB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCCOB_CCOBn_SHIFT))&FTFC_FCCOB_CCOBn_MASK)
3809 /* FPROT Bit Fields */
3810 #define FTFC_FPROT_PROT_MASK 0xFFu
3811 #define FTFC_FPROT_PROT_SHIFT 0u
3812 #define FTFC_FPROT_PROT_WIDTH 8u
3813 #define FTFC_FPROT_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FPROT_PROT_SHIFT))&FTFC_FPROT_PROT_MASK)
3814 /* FEPROT Bit Fields */
3815 #define FTFC_FEPROT_EPROT_MASK 0xFFu
3816 #define FTFC_FEPROT_EPROT_SHIFT 0u
3817 #define FTFC_FEPROT_EPROT_WIDTH 8u
3818 #define FTFC_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FEPROT_EPROT_SHIFT))&FTFC_FEPROT_EPROT_MASK)
3819 /* FDPROT Bit Fields */
3820 #define FTFC_FDPROT_DPROT_MASK 0xFFu
3821 #define FTFC_FDPROT_DPROT_SHIFT 0u
3822 #define FTFC_FDPROT_DPROT_WIDTH 8u
3823 #define FTFC_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FDPROT_DPROT_SHIFT))&FTFC_FDPROT_DPROT_MASK)
3824 /* FCSESTAT Bit Fields */
3825 #define FTFC_FCSESTAT_BSY_MASK 0x1u
3826 #define FTFC_FCSESTAT_BSY_SHIFT 0u
3827 #define FTFC_FCSESTAT_BSY_WIDTH 1u
3828 #define FTFC_FCSESTAT_BSY(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BSY_SHIFT))&FTFC_FCSESTAT_BSY_MASK)
3829 #define FTFC_FCSESTAT_SB_MASK 0x2u
3830 #define FTFC_FCSESTAT_SB_SHIFT 1u
3831 #define FTFC_FCSESTAT_SB_WIDTH 1u
3832 #define FTFC_FCSESTAT_SB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_SB_SHIFT))&FTFC_FCSESTAT_SB_MASK)
3833 #define FTFC_FCSESTAT_BIN_MASK 0x4u
3834 #define FTFC_FCSESTAT_BIN_SHIFT 2u
3835 #define FTFC_FCSESTAT_BIN_WIDTH 1u
3836 #define FTFC_FCSESTAT_BIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BIN_SHIFT))&FTFC_FCSESTAT_BIN_MASK)
3837 #define FTFC_FCSESTAT_BFN_MASK 0x8u
3838 #define FTFC_FCSESTAT_BFN_SHIFT 3u
3839 #define FTFC_FCSESTAT_BFN_WIDTH 1u
3840 #define FTFC_FCSESTAT_BFN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BFN_SHIFT))&FTFC_FCSESTAT_BFN_MASK)
3841 #define FTFC_FCSESTAT_BOK_MASK 0x10u
3842 #define FTFC_FCSESTAT_BOK_SHIFT 4u
3843 #define FTFC_FCSESTAT_BOK_WIDTH 1u
3844 #define FTFC_FCSESTAT_BOK(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_BOK_SHIFT))&FTFC_FCSESTAT_BOK_MASK)
3845 #define FTFC_FCSESTAT_RIN_MASK 0x20u
3846 #define FTFC_FCSESTAT_RIN_SHIFT 5u
3847 #define FTFC_FCSESTAT_RIN_WIDTH 1u
3848 #define FTFC_FCSESTAT_RIN(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_RIN_SHIFT))&FTFC_FCSESTAT_RIN_MASK)
3849 #define FTFC_FCSESTAT_EDB_MASK 0x40u
3850 #define FTFC_FCSESTAT_EDB_SHIFT 6u
3851 #define FTFC_FCSESTAT_EDB_WIDTH 1u
3852 #define FTFC_FCSESTAT_EDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_EDB_SHIFT))&FTFC_FCSESTAT_EDB_MASK)
3853 #define FTFC_FCSESTAT_IDB_MASK 0x80u
3854 #define FTFC_FCSESTAT_IDB_SHIFT 7u
3855 #define FTFC_FCSESTAT_IDB_WIDTH 1u
3856 #define FTFC_FCSESTAT_IDB(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FCSESTAT_IDB_SHIFT))&FTFC_FCSESTAT_IDB_MASK)
3857 /* FERSTAT Bit Fields */
3858 #define FTFC_FERSTAT_DFDIF_MASK 0x2u
3859 #define FTFC_FERSTAT_DFDIF_SHIFT 1u
3860 #define FTFC_FERSTAT_DFDIF_WIDTH 1u
3861 #define FTFC_FERSTAT_DFDIF(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERSTAT_DFDIF_SHIFT))&FTFC_FERSTAT_DFDIF_MASK)
3862 /* FERCNFG Bit Fields */
3863 #define FTFC_FERCNFG_DFDIE_MASK 0x2u
3864 #define FTFC_FERCNFG_DFDIE_SHIFT 1u
3865 #define FTFC_FERCNFG_DFDIE_WIDTH 1u
3866 #define FTFC_FERCNFG_DFDIE(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_DFDIE_SHIFT))&FTFC_FERCNFG_DFDIE_MASK)
3867 #define FTFC_FERCNFG_FDFD_MASK 0x20u
3868 #define FTFC_FERCNFG_FDFD_SHIFT 5u
3869 #define FTFC_FERCNFG_FDFD_WIDTH 1u
3870 #define FTFC_FERCNFG_FDFD(x) (((uint8_t)(((uint8_t)(x))<<FTFC_FERCNFG_FDFD_SHIFT))&FTFC_FERCNFG_FDFD_MASK)
3871  /* end of group FTFC_Register_Masks */
3875 
3876  /* end of group FTFC_Peripheral_Access_Layer */
3880 
3881 
3882 /* ----------------------------------------------------------------------------
3883  -- FTM Peripheral Access Layer
3884  ---------------------------------------------------------------------------- */
3885 
3893 #define FTM_CONTROLS_COUNT 8u
3894 #define FTM_CV_MIRROR_COUNT 8u
3895 
3897 typedef struct {
3898  __IO uint32_t SC;
3899  __IO uint32_t CNT;
3900  __IO uint32_t MOD;
3901  struct { /* offset: 0xC, array step: 0x8 */
3902  __IO uint32_t CnSC;
3903  __IO uint32_t CnV;
3904  } CONTROLS[FTM_CONTROLS_COUNT];
3905  __IO uint32_t CNTIN;
3906  __IO uint32_t STATUS;
3907  __IO uint32_t MODE;
3908  __IO uint32_t SYNC;
3909  __IO uint32_t OUTINIT;
3910  __IO uint32_t OUTMASK;
3911  __IO uint32_t COMBINE;
3912  __IO uint32_t DEADTIME;
3913  __IO uint32_t EXTTRIG;
3914  __IO uint32_t POL;
3915  __IO uint32_t FMS;
3916  __IO uint32_t FILTER;
3917  __IO uint32_t FLTCTRL;
3918  __IO uint32_t QDCTRL;
3919  __IO uint32_t CONF;
3920  __IO uint32_t FLTPOL;
3921  __IO uint32_t SYNCONF;
3922  __IO uint32_t INVCTRL;
3923  __IO uint32_t SWOCTRL;
3924  __IO uint32_t PWMLOAD;
3925  __IO uint32_t HCR;
3926  __IO uint32_t PAIR0DEADTIME;
3927  uint8_t RESERVED_0[4];
3928  __IO uint32_t PAIR1DEADTIME;
3929  uint8_t RESERVED_1[4];
3930  __IO uint32_t PAIR2DEADTIME;
3931  uint8_t RESERVED_2[4];
3932  __IO uint32_t PAIR3DEADTIME;
3933  uint8_t RESERVED_3[324];
3934  __IO uint32_t MOD_MIRROR;
3935  __IO uint32_t CV_MIRROR[FTM_CV_MIRROR_COUNT];
3937 
3939 #define FTM_INSTANCE_COUNT (4u)
3940 
3941 
3942 /* FTM - Peripheral instance base addresses */
3944 #define FTM0_BASE (0x40038000u)
3945 
3946 #define FTM0 ((FTM_Type *)FTM0_BASE)
3947 
3948 #define FTM1_BASE (0x40039000u)
3949 
3950 #define FTM1 ((FTM_Type *)FTM1_BASE)
3951 
3952 #define FTM2_BASE (0x4003A000u)
3953 
3954 #define FTM2 ((FTM_Type *)FTM2_BASE)
3955 
3956 #define FTM3_BASE (0x40026000u)
3957 
3958 #define FTM3 ((FTM_Type *)FTM3_BASE)
3959 
3960 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
3961 
3962 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
3963 
3964 #define FTM_IRQS_ARR_COUNT (4u)
3965 
3966 #define FTM_IRQS_CH_COUNT (8u)
3967 
3968 #define FTM_Fault_IRQS_CH_COUNT (1u)
3969 
3970 #define FTM_Overflow_IRQS_CH_COUNT (1u)
3971 
3972 #define FTM_Reload_IRQS_CH_COUNT (1u)
3973 
3974 #define FTM_IRQS { { FTM0_Ch0_Ch1_IRQn, FTM0_Ch0_Ch1_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch2_Ch3_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch4_Ch5_IRQn, FTM0_Ch6_Ch7_IRQn, FTM0_Ch6_Ch7_IRQn }, \
3975  { FTM1_Ch0_Ch1_IRQn, FTM1_Ch0_Ch1_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch2_Ch3_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch4_Ch5_IRQn, FTM1_Ch6_Ch7_IRQn, FTM1_Ch6_Ch7_IRQn }, \
3976  { FTM2_Ch0_Ch1_IRQn, FTM2_Ch0_Ch1_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch2_Ch3_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch4_Ch5_IRQn, FTM2_Ch6_Ch7_IRQn, FTM2_Ch6_Ch7_IRQn }, \
3977  { FTM3_Ch0_Ch1_IRQn, FTM3_Ch0_Ch1_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch2_Ch3_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch4_Ch5_IRQn, FTM3_Ch6_Ch7_IRQn, FTM3_Ch6_Ch7_IRQn } }
3978 #define FTM_Fault_IRQS { FTM0_Fault_IRQn, FTM1_Fault_IRQn, FTM2_Fault_IRQn, FTM3_Fault_IRQn }
3979 #define FTM_Overflow_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn }
3980 #define FTM_Reload_IRQS { FTM0_Ovf_Reload_IRQn, FTM1_Ovf_Reload_IRQn, FTM2_Ovf_Reload_IRQn, FTM3_Ovf_Reload_IRQn }
3981 
3982 /* ----------------------------------------------------------------------------
3983  -- FTM Register Masks
3984  ---------------------------------------------------------------------------- */
3985 
3991 /* SC Bit Fields */
3992 #define FTM_SC_PS_MASK 0x7u
3993 #define FTM_SC_PS_SHIFT 0u
3994 #define FTM_SC_PS_WIDTH 3u
3995 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
3996 #define FTM_SC_CLKS_MASK 0x18u
3997 #define FTM_SC_CLKS_SHIFT 3u
3998 #define FTM_SC_CLKS_WIDTH 2u
3999 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
4000 #define FTM_SC_CPWMS_MASK 0x20u
4001 #define FTM_SC_CPWMS_SHIFT 5u
4002 #define FTM_SC_CPWMS_WIDTH 1u
4003 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CPWMS_SHIFT))&FTM_SC_CPWMS_MASK)
4004 #define FTM_SC_RIE_MASK 0x40u
4005 #define FTM_SC_RIE_SHIFT 6u
4006 #define FTM_SC_RIE_WIDTH 1u
4007 #define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RIE_SHIFT))&FTM_SC_RIE_MASK)
4008 #define FTM_SC_RF_MASK 0x80u
4009 #define FTM_SC_RF_SHIFT 7u
4010 #define FTM_SC_RF_WIDTH 1u
4011 #define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_RF_SHIFT))&FTM_SC_RF_MASK)
4012 #define FTM_SC_TOIE_MASK 0x100u
4013 #define FTM_SC_TOIE_SHIFT 8u
4014 #define FTM_SC_TOIE_WIDTH 1u
4015 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOIE_SHIFT))&FTM_SC_TOIE_MASK)
4016 #define FTM_SC_TOF_MASK 0x200u
4017 #define FTM_SC_TOF_SHIFT 9u
4018 #define FTM_SC_TOF_WIDTH 1u
4019 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_TOF_SHIFT))&FTM_SC_TOF_MASK)
4020 #define FTM_SC_PWMEN0_MASK 0x10000u
4021 #define FTM_SC_PWMEN0_SHIFT 16u
4022 #define FTM_SC_PWMEN0_WIDTH 1u
4023 #define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN0_SHIFT))&FTM_SC_PWMEN0_MASK)
4024 #define FTM_SC_PWMEN1_MASK 0x20000u
4025 #define FTM_SC_PWMEN1_SHIFT 17u
4026 #define FTM_SC_PWMEN1_WIDTH 1u
4027 #define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN1_SHIFT))&FTM_SC_PWMEN1_MASK)
4028 #define FTM_SC_PWMEN2_MASK 0x40000u
4029 #define FTM_SC_PWMEN2_SHIFT 18u
4030 #define FTM_SC_PWMEN2_WIDTH 1u
4031 #define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN2_SHIFT))&FTM_SC_PWMEN2_MASK)
4032 #define FTM_SC_PWMEN3_MASK 0x80000u
4033 #define FTM_SC_PWMEN3_SHIFT 19u
4034 #define FTM_SC_PWMEN3_WIDTH 1u
4035 #define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN3_SHIFT))&FTM_SC_PWMEN3_MASK)
4036 #define FTM_SC_PWMEN4_MASK 0x100000u
4037 #define FTM_SC_PWMEN4_SHIFT 20u
4038 #define FTM_SC_PWMEN4_WIDTH 1u
4039 #define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN4_SHIFT))&FTM_SC_PWMEN4_MASK)
4040 #define FTM_SC_PWMEN5_MASK 0x200000u
4041 #define FTM_SC_PWMEN5_SHIFT 21u
4042 #define FTM_SC_PWMEN5_WIDTH 1u
4043 #define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN5_SHIFT))&FTM_SC_PWMEN5_MASK)
4044 #define FTM_SC_PWMEN6_MASK 0x400000u
4045 #define FTM_SC_PWMEN6_SHIFT 22u
4046 #define FTM_SC_PWMEN6_WIDTH 1u
4047 #define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN6_SHIFT))&FTM_SC_PWMEN6_MASK)
4048 #define FTM_SC_PWMEN7_MASK 0x800000u
4049 #define FTM_SC_PWMEN7_SHIFT 23u
4050 #define FTM_SC_PWMEN7_WIDTH 1u
4051 #define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PWMEN7_SHIFT))&FTM_SC_PWMEN7_MASK)
4052 #define FTM_SC_FLTPS_MASK 0xF000000u
4053 #define FTM_SC_FLTPS_SHIFT 24u
4054 #define FTM_SC_FLTPS_WIDTH 4u
4055 #define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_FLTPS_SHIFT))&FTM_SC_FLTPS_MASK)
4056 /* CNT Bit Fields */
4057 #define FTM_CNT_COUNT_MASK 0xFFFFu
4058 #define FTM_CNT_COUNT_SHIFT 0u
4059 #define FTM_CNT_COUNT_WIDTH 16u
4060 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
4061 /* MOD Bit Fields */
4062 #define FTM_MOD_MOD_MASK 0xFFFFu
4063 #define FTM_MOD_MOD_SHIFT 0u
4064 #define FTM_MOD_MOD_WIDTH 16u
4065 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
4066 /* CnSC Bit Fields */
4067 #define FTM_CnSC_DMA_MASK 0x1u
4068 #define FTM_CnSC_DMA_SHIFT 0u
4069 #define FTM_CnSC_DMA_WIDTH 1u
4070 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_DMA_SHIFT))&FTM_CnSC_DMA_MASK)
4071 #define FTM_CnSC_ICRST_MASK 0x2u
4072 #define FTM_CnSC_ICRST_SHIFT 1u
4073 #define FTM_CnSC_ICRST_WIDTH 1u
4074 #define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ICRST_SHIFT))&FTM_CnSC_ICRST_MASK)
4075 #define FTM_CnSC_ELSA_MASK 0x4u
4076 #define FTM_CnSC_ELSA_SHIFT 2u
4077 #define FTM_CnSC_ELSA_WIDTH 1u
4078 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSA_SHIFT))&FTM_CnSC_ELSA_MASK)
4079 #define FTM_CnSC_ELSB_MASK 0x8u
4080 #define FTM_CnSC_ELSB_SHIFT 3u
4081 #define FTM_CnSC_ELSB_WIDTH 1u
4082 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_ELSB_SHIFT))&FTM_CnSC_ELSB_MASK)
4083 #define FTM_CnSC_MSA_MASK 0x10u
4084 #define FTM_CnSC_MSA_SHIFT 4u
4085 #define FTM_CnSC_MSA_WIDTH 1u
4086 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSA_SHIFT))&FTM_CnSC_MSA_MASK)
4087 #define FTM_CnSC_MSB_MASK 0x20u
4088 #define FTM_CnSC_MSB_SHIFT 5u
4089 #define FTM_CnSC_MSB_WIDTH 1u
4090 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_MSB_SHIFT))&FTM_CnSC_MSB_MASK)
4091 #define FTM_CnSC_CHIE_MASK 0x40u
4092 #define FTM_CnSC_CHIE_SHIFT 6u
4093 #define FTM_CnSC_CHIE_WIDTH 1u
4094 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIE_SHIFT))&FTM_CnSC_CHIE_MASK)
4095 #define FTM_CnSC_CHF_MASK 0x80u
4096 #define FTM_CnSC_CHF_SHIFT 7u
4097 #define FTM_CnSC_CHF_WIDTH 1u
4098 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHF_SHIFT))&FTM_CnSC_CHF_MASK)
4099 #define FTM_CnSC_TRIGMODE_MASK 0x100u
4100 #define FTM_CnSC_TRIGMODE_SHIFT 8u
4101 #define FTM_CnSC_TRIGMODE_WIDTH 1u
4102 #define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_TRIGMODE_SHIFT))&FTM_CnSC_TRIGMODE_MASK)
4103 #define FTM_CnSC_CHIS_MASK 0x200u
4104 #define FTM_CnSC_CHIS_SHIFT 9u
4105 #define FTM_CnSC_CHIS_WIDTH 1u
4106 #define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHIS_SHIFT))&FTM_CnSC_CHIS_MASK)
4107 #define FTM_CnSC_CHOV_MASK 0x400u
4108 #define FTM_CnSC_CHOV_SHIFT 10u
4109 #define FTM_CnSC_CHOV_WIDTH 1u
4110 #define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnSC_CHOV_SHIFT))&FTM_CnSC_CHOV_MASK)
4111 /* CnV Bit Fields */
4112 #define FTM_CnV_VAL_MASK 0xFFFFu
4113 #define FTM_CnV_VAL_SHIFT 0u
4114 #define FTM_CnV_VAL_WIDTH 16u
4115 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
4116 /* CNTIN Bit Fields */
4117 #define FTM_CNTIN_INIT_MASK 0xFFFFu
4118 #define FTM_CNTIN_INIT_SHIFT 0u
4119 #define FTM_CNTIN_INIT_WIDTH 16u
4120 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
4121 /* STATUS Bit Fields */
4122 #define FTM_STATUS_CH0F_MASK 0x1u
4123 #define FTM_STATUS_CH0F_SHIFT 0u
4124 #define FTM_STATUS_CH0F_WIDTH 1u
4125 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH0F_SHIFT))&FTM_STATUS_CH0F_MASK)
4126 #define FTM_STATUS_CH1F_MASK 0x2u
4127 #define FTM_STATUS_CH1F_SHIFT 1u
4128 #define FTM_STATUS_CH1F_WIDTH 1u
4129 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH1F_SHIFT))&FTM_STATUS_CH1F_MASK)
4130 #define FTM_STATUS_CH2F_MASK 0x4u
4131 #define FTM_STATUS_CH2F_SHIFT 2u
4132 #define FTM_STATUS_CH2F_WIDTH 1u
4133 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH2F_SHIFT))&FTM_STATUS_CH2F_MASK)
4134 #define FTM_STATUS_CH3F_MASK 0x8u
4135 #define FTM_STATUS_CH3F_SHIFT 3u
4136 #define FTM_STATUS_CH3F_WIDTH 1u
4137 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH3F_SHIFT))&FTM_STATUS_CH3F_MASK)
4138 #define FTM_STATUS_CH4F_MASK 0x10u
4139 #define FTM_STATUS_CH4F_SHIFT 4u
4140 #define FTM_STATUS_CH4F_WIDTH 1u
4141 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH4F_SHIFT))&FTM_STATUS_CH4F_MASK)
4142 #define FTM_STATUS_CH5F_MASK 0x20u
4143 #define FTM_STATUS_CH5F_SHIFT 5u
4144 #define FTM_STATUS_CH5F_WIDTH 1u
4145 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH5F_SHIFT))&FTM_STATUS_CH5F_MASK)
4146 #define FTM_STATUS_CH6F_MASK 0x40u
4147 #define FTM_STATUS_CH6F_SHIFT 6u
4148 #define FTM_STATUS_CH6F_WIDTH 1u
4149 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH6F_SHIFT))&FTM_STATUS_CH6F_MASK)
4150 #define FTM_STATUS_CH7F_MASK 0x80u
4151 #define FTM_STATUS_CH7F_SHIFT 7u
4152 #define FTM_STATUS_CH7F_WIDTH 1u
4153 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x))<<FTM_STATUS_CH7F_SHIFT))&FTM_STATUS_CH7F_MASK)
4154 /* MODE Bit Fields */
4155 #define FTM_MODE_FTMEN_MASK 0x1u
4156 #define FTM_MODE_FTMEN_SHIFT 0u
4157 #define FTM_MODE_FTMEN_WIDTH 1u
4158 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FTMEN_SHIFT))&FTM_MODE_FTMEN_MASK)
4159 #define FTM_MODE_INIT_MASK 0x2u
4160 #define FTM_MODE_INIT_SHIFT 1u
4161 #define FTM_MODE_INIT_WIDTH 1u
4162 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_INIT_SHIFT))&FTM_MODE_INIT_MASK)
4163 #define FTM_MODE_WPDIS_MASK 0x4u
4164 #define FTM_MODE_WPDIS_SHIFT 2u
4165 #define FTM_MODE_WPDIS_WIDTH 1u
4166 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_WPDIS_SHIFT))&FTM_MODE_WPDIS_MASK)
4167 #define FTM_MODE_PWMSYNC_MASK 0x8u
4168 #define FTM_MODE_PWMSYNC_SHIFT 3u
4169 #define FTM_MODE_PWMSYNC_WIDTH 1u
4170 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_PWMSYNC_SHIFT))&FTM_MODE_PWMSYNC_MASK)
4171 #define FTM_MODE_CAPTEST_MASK 0x10u
4172 #define FTM_MODE_CAPTEST_SHIFT 4u
4173 #define FTM_MODE_CAPTEST_WIDTH 1u
4174 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_CAPTEST_SHIFT))&FTM_MODE_CAPTEST_MASK)
4175 #define FTM_MODE_FAULTM_MASK 0x60u
4176 #define FTM_MODE_FAULTM_SHIFT 5u
4177 #define FTM_MODE_FAULTM_WIDTH 2u
4178 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
4179 #define FTM_MODE_FAULTIE_MASK 0x80u
4180 #define FTM_MODE_FAULTIE_SHIFT 7u
4181 #define FTM_MODE_FAULTIE_WIDTH 1u
4182 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTIE_SHIFT))&FTM_MODE_FAULTIE_MASK)
4183 /* SYNC Bit Fields */
4184 #define FTM_SYNC_CNTMIN_MASK 0x1u
4185 #define FTM_SYNC_CNTMIN_SHIFT 0u
4186 #define FTM_SYNC_CNTMIN_WIDTH 1u
4187 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMIN_SHIFT))&FTM_SYNC_CNTMIN_MASK)
4188 #define FTM_SYNC_CNTMAX_MASK 0x2u
4189 #define FTM_SYNC_CNTMAX_SHIFT 1u
4190 #define FTM_SYNC_CNTMAX_WIDTH 1u
4191 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_CNTMAX_SHIFT))&FTM_SYNC_CNTMAX_MASK)
4192 #define FTM_SYNC_REINIT_MASK 0x4u
4193 #define FTM_SYNC_REINIT_SHIFT 2u
4194 #define FTM_SYNC_REINIT_WIDTH 1u
4195 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_REINIT_SHIFT))&FTM_SYNC_REINIT_MASK)
4196 #define FTM_SYNC_SYNCHOM_MASK 0x8u
4197 #define FTM_SYNC_SYNCHOM_SHIFT 3u
4198 #define FTM_SYNC_SYNCHOM_WIDTH 1u
4199 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SYNCHOM_SHIFT))&FTM_SYNC_SYNCHOM_MASK)
4200 #define FTM_SYNC_TRIG0_MASK 0x10u
4201 #define FTM_SYNC_TRIG0_SHIFT 4u
4202 #define FTM_SYNC_TRIG0_WIDTH 1u
4203 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG0_SHIFT))&FTM_SYNC_TRIG0_MASK)
4204 #define FTM_SYNC_TRIG1_MASK 0x20u
4205 #define FTM_SYNC_TRIG1_SHIFT 5u
4206 #define FTM_SYNC_TRIG1_WIDTH 1u
4207 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG1_SHIFT))&FTM_SYNC_TRIG1_MASK)
4208 #define FTM_SYNC_TRIG2_MASK 0x40u
4209 #define FTM_SYNC_TRIG2_SHIFT 6u
4210 #define FTM_SYNC_TRIG2_WIDTH 1u
4211 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_TRIG2_SHIFT))&FTM_SYNC_TRIG2_MASK)
4212 #define FTM_SYNC_SWSYNC_MASK 0x80u
4213 #define FTM_SYNC_SWSYNC_SHIFT 7u
4214 #define FTM_SYNC_SWSYNC_WIDTH 1u
4215 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNC_SWSYNC_SHIFT))&FTM_SYNC_SWSYNC_MASK)
4216 /* OUTINIT Bit Fields */
4217 #define FTM_OUTINIT_CH0OI_MASK 0x1u
4218 #define FTM_OUTINIT_CH0OI_SHIFT 0u
4219 #define FTM_OUTINIT_CH0OI_WIDTH 1u
4220 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH0OI_SHIFT))&FTM_OUTINIT_CH0OI_MASK)
4221 #define FTM_OUTINIT_CH1OI_MASK 0x2u
4222 #define FTM_OUTINIT_CH1OI_SHIFT 1u
4223 #define FTM_OUTINIT_CH1OI_WIDTH 1u
4224 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH1OI_SHIFT))&FTM_OUTINIT_CH1OI_MASK)
4225 #define FTM_OUTINIT_CH2OI_MASK 0x4u
4226 #define FTM_OUTINIT_CH2OI_SHIFT 2u
4227 #define FTM_OUTINIT_CH2OI_WIDTH 1u
4228 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH2OI_SHIFT))&FTM_OUTINIT_CH2OI_MASK)
4229 #define FTM_OUTINIT_CH3OI_MASK 0x8u
4230 #define FTM_OUTINIT_CH3OI_SHIFT 3u
4231 #define FTM_OUTINIT_CH3OI_WIDTH 1u
4232 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH3OI_SHIFT))&FTM_OUTINIT_CH3OI_MASK)
4233 #define FTM_OUTINIT_CH4OI_MASK 0x10u
4234 #define FTM_OUTINIT_CH4OI_SHIFT 4u
4235 #define FTM_OUTINIT_CH4OI_WIDTH 1u
4236 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH4OI_SHIFT))&FTM_OUTINIT_CH4OI_MASK)
4237 #define FTM_OUTINIT_CH5OI_MASK 0x20u
4238 #define FTM_OUTINIT_CH5OI_SHIFT 5u
4239 #define FTM_OUTINIT_CH5OI_WIDTH 1u
4240 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH5OI_SHIFT))&FTM_OUTINIT_CH5OI_MASK)
4241 #define FTM_OUTINIT_CH6OI_MASK 0x40u
4242 #define FTM_OUTINIT_CH6OI_SHIFT 6u
4243 #define FTM_OUTINIT_CH6OI_WIDTH 1u
4244 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH6OI_SHIFT))&FTM_OUTINIT_CH6OI_MASK)
4245 #define FTM_OUTINIT_CH7OI_MASK 0x80u
4246 #define FTM_OUTINIT_CH7OI_SHIFT 7u
4247 #define FTM_OUTINIT_CH7OI_WIDTH 1u
4248 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTINIT_CH7OI_SHIFT))&FTM_OUTINIT_CH7OI_MASK)
4249 /* OUTMASK Bit Fields */
4250 #define FTM_OUTMASK_CH0OM_MASK 0x1u
4251 #define FTM_OUTMASK_CH0OM_SHIFT 0u
4252 #define FTM_OUTMASK_CH0OM_WIDTH 1u
4253 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH0OM_SHIFT))&FTM_OUTMASK_CH0OM_MASK)
4254 #define FTM_OUTMASK_CH1OM_MASK 0x2u
4255 #define FTM_OUTMASK_CH1OM_SHIFT 1u
4256 #define FTM_OUTMASK_CH1OM_WIDTH 1u
4257 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH1OM_SHIFT))&FTM_OUTMASK_CH1OM_MASK)
4258 #define FTM_OUTMASK_CH2OM_MASK 0x4u
4259 #define FTM_OUTMASK_CH2OM_SHIFT 2u
4260 #define FTM_OUTMASK_CH2OM_WIDTH 1u
4261 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH2OM_SHIFT))&FTM_OUTMASK_CH2OM_MASK)
4262 #define FTM_OUTMASK_CH3OM_MASK 0x8u
4263 #define FTM_OUTMASK_CH3OM_SHIFT 3u
4264 #define FTM_OUTMASK_CH3OM_WIDTH 1u
4265 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH3OM_SHIFT))&FTM_OUTMASK_CH3OM_MASK)
4266 #define FTM_OUTMASK_CH4OM_MASK 0x10u
4267 #define FTM_OUTMASK_CH4OM_SHIFT 4u
4268 #define FTM_OUTMASK_CH4OM_WIDTH 1u
4269 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH4OM_SHIFT))&FTM_OUTMASK_CH4OM_MASK)
4270 #define FTM_OUTMASK_CH5OM_MASK 0x20u
4271 #define FTM_OUTMASK_CH5OM_SHIFT 5u
4272 #define FTM_OUTMASK_CH5OM_WIDTH 1u
4273 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH5OM_SHIFT))&FTM_OUTMASK_CH5OM_MASK)
4274 #define FTM_OUTMASK_CH6OM_MASK 0x40u
4275 #define FTM_OUTMASK_CH6OM_SHIFT 6u
4276 #define FTM_OUTMASK_CH6OM_WIDTH 1u
4277 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH6OM_SHIFT))&FTM_OUTMASK_CH6OM_MASK)
4278 #define FTM_OUTMASK_CH7OM_MASK 0x80u
4279 #define FTM_OUTMASK_CH7OM_SHIFT 7u
4280 #define FTM_OUTMASK_CH7OM_WIDTH 1u
4281 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x))<<FTM_OUTMASK_CH7OM_SHIFT))&FTM_OUTMASK_CH7OM_MASK)
4282 /* COMBINE Bit Fields */
4283 #define FTM_COMBINE_COMBINE0_MASK 0x1u
4284 #define FTM_COMBINE_COMBINE0_SHIFT 0u
4285 #define FTM_COMBINE_COMBINE0_WIDTH 1u
4286 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE0_SHIFT))&FTM_COMBINE_COMBINE0_MASK)
4287 #define FTM_COMBINE_COMP0_MASK 0x2u
4288 #define FTM_COMBINE_COMP0_SHIFT 1u
4289 #define FTM_COMBINE_COMP0_WIDTH 1u
4290 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP0_SHIFT))&FTM_COMBINE_COMP0_MASK)
4291 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
4292 #define FTM_COMBINE_DECAPEN0_SHIFT 2u
4293 #define FTM_COMBINE_DECAPEN0_WIDTH 1u
4294 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN0_SHIFT))&FTM_COMBINE_DECAPEN0_MASK)
4295 #define FTM_COMBINE_DECAP0_MASK 0x8u
4296 #define FTM_COMBINE_DECAP0_SHIFT 3u
4297 #define FTM_COMBINE_DECAP0_WIDTH 1u
4298 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP0_SHIFT))&FTM_COMBINE_DECAP0_MASK)
4299 #define FTM_COMBINE_DTEN0_MASK 0x10u
4300 #define FTM_COMBINE_DTEN0_SHIFT 4u
4301 #define FTM_COMBINE_DTEN0_WIDTH 1u
4302 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN0_SHIFT))&FTM_COMBINE_DTEN0_MASK)
4303 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
4304 #define FTM_COMBINE_SYNCEN0_SHIFT 5u
4305 #define FTM_COMBINE_SYNCEN0_WIDTH 1u
4306 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN0_SHIFT))&FTM_COMBINE_SYNCEN0_MASK)
4307 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
4308 #define FTM_COMBINE_FAULTEN0_SHIFT 6u
4309 #define FTM_COMBINE_FAULTEN0_WIDTH 1u
4310 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN0_SHIFT))&FTM_COMBINE_FAULTEN0_MASK)
4311 #define FTM_COMBINE_MCOMBINE0_MASK 0x80u
4312 #define FTM_COMBINE_MCOMBINE0_SHIFT 7u
4313 #define FTM_COMBINE_MCOMBINE0_WIDTH 1u
4314 #define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE0_SHIFT))&FTM_COMBINE_MCOMBINE0_MASK)
4315 #define FTM_COMBINE_COMBINE1_MASK 0x100u
4316 #define FTM_COMBINE_COMBINE1_SHIFT 8u
4317 #define FTM_COMBINE_COMBINE1_WIDTH 1u
4318 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE1_SHIFT))&FTM_COMBINE_COMBINE1_MASK)
4319 #define FTM_COMBINE_COMP1_MASK 0x200u
4320 #define FTM_COMBINE_COMP1_SHIFT 9u
4321 #define FTM_COMBINE_COMP1_WIDTH 1u
4322 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP1_SHIFT))&FTM_COMBINE_COMP1_MASK)
4323 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
4324 #define FTM_COMBINE_DECAPEN1_SHIFT 10u
4325 #define FTM_COMBINE_DECAPEN1_WIDTH 1u
4326 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN1_SHIFT))&FTM_COMBINE_DECAPEN1_MASK)
4327 #define FTM_COMBINE_DECAP1_MASK 0x800u
4328 #define FTM_COMBINE_DECAP1_SHIFT 11u
4329 #define FTM_COMBINE_DECAP1_WIDTH 1u
4330 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP1_SHIFT))&FTM_COMBINE_DECAP1_MASK)
4331 #define FTM_COMBINE_DTEN1_MASK 0x1000u
4332 #define FTM_COMBINE_DTEN1_SHIFT 12u
4333 #define FTM_COMBINE_DTEN1_WIDTH 1u
4334 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN1_SHIFT))&FTM_COMBINE_DTEN1_MASK)
4335 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
4336 #define FTM_COMBINE_SYNCEN1_SHIFT 13u
4337 #define FTM_COMBINE_SYNCEN1_WIDTH 1u
4338 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN1_SHIFT))&FTM_COMBINE_SYNCEN1_MASK)
4339 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
4340 #define FTM_COMBINE_FAULTEN1_SHIFT 14u
4341 #define FTM_COMBINE_FAULTEN1_WIDTH 1u
4342 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN1_SHIFT))&FTM_COMBINE_FAULTEN1_MASK)
4343 #define FTM_COMBINE_MCOMBINE1_MASK 0x8000u
4344 #define FTM_COMBINE_MCOMBINE1_SHIFT 15u
4345 #define FTM_COMBINE_MCOMBINE1_WIDTH 1u
4346 #define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE1_SHIFT))&FTM_COMBINE_MCOMBINE1_MASK)
4347 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
4348 #define FTM_COMBINE_COMBINE2_SHIFT 16u
4349 #define FTM_COMBINE_COMBINE2_WIDTH 1u
4350 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE2_SHIFT))&FTM_COMBINE_COMBINE2_MASK)
4351 #define FTM_COMBINE_COMP2_MASK 0x20000u
4352 #define FTM_COMBINE_COMP2_SHIFT 17u
4353 #define FTM_COMBINE_COMP2_WIDTH 1u
4354 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP2_SHIFT))&FTM_COMBINE_COMP2_MASK)
4355 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
4356 #define FTM_COMBINE_DECAPEN2_SHIFT 18u
4357 #define FTM_COMBINE_DECAPEN2_WIDTH 1u
4358 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN2_SHIFT))&FTM_COMBINE_DECAPEN2_MASK)
4359 #define FTM_COMBINE_DECAP2_MASK 0x80000u
4360 #define FTM_COMBINE_DECAP2_SHIFT 19u
4361 #define FTM_COMBINE_DECAP2_WIDTH 1u
4362 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP2_SHIFT))&FTM_COMBINE_DECAP2_MASK)
4363 #define FTM_COMBINE_DTEN2_MASK 0x100000u
4364 #define FTM_COMBINE_DTEN2_SHIFT 20u
4365 #define FTM_COMBINE_DTEN2_WIDTH 1u
4366 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN2_SHIFT))&FTM_COMBINE_DTEN2_MASK)
4367 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
4368 #define FTM_COMBINE_SYNCEN2_SHIFT 21u
4369 #define FTM_COMBINE_SYNCEN2_WIDTH 1u
4370 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN2_SHIFT))&FTM_COMBINE_SYNCEN2_MASK)
4371 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
4372 #define FTM_COMBINE_FAULTEN2_SHIFT 22u
4373 #define FTM_COMBINE_FAULTEN2_WIDTH 1u
4374 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN2_SHIFT))&FTM_COMBINE_FAULTEN2_MASK)
4375 #define FTM_COMBINE_MCOMBINE2_MASK 0x800000u
4376 #define FTM_COMBINE_MCOMBINE2_SHIFT 23u
4377 #define FTM_COMBINE_MCOMBINE2_WIDTH 1u
4378 #define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE2_SHIFT))&FTM_COMBINE_MCOMBINE2_MASK)
4379 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
4380 #define FTM_COMBINE_COMBINE3_SHIFT 24u
4381 #define FTM_COMBINE_COMBINE3_WIDTH 1u
4382 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMBINE3_SHIFT))&FTM_COMBINE_COMBINE3_MASK)
4383 #define FTM_COMBINE_COMP3_MASK 0x2000000u
4384 #define FTM_COMBINE_COMP3_SHIFT 25u
4385 #define FTM_COMBINE_COMP3_WIDTH 1u
4386 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_COMP3_SHIFT))&FTM_COMBINE_COMP3_MASK)
4387 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
4388 #define FTM_COMBINE_DECAPEN3_SHIFT 26u
4389 #define FTM_COMBINE_DECAPEN3_WIDTH 1u
4390 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAPEN3_SHIFT))&FTM_COMBINE_DECAPEN3_MASK)
4391 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
4392 #define FTM_COMBINE_DECAP3_SHIFT 27u
4393 #define FTM_COMBINE_DECAP3_WIDTH 1u
4394 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DECAP3_SHIFT))&FTM_COMBINE_DECAP3_MASK)
4395 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
4396 #define FTM_COMBINE_DTEN3_SHIFT 28u
4397 #define FTM_COMBINE_DTEN3_WIDTH 1u
4398 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_DTEN3_SHIFT))&FTM_COMBINE_DTEN3_MASK)
4399 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
4400 #define FTM_COMBINE_SYNCEN3_SHIFT 29u
4401 #define FTM_COMBINE_SYNCEN3_WIDTH 1u
4402 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_SYNCEN3_SHIFT))&FTM_COMBINE_SYNCEN3_MASK)
4403 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
4404 #define FTM_COMBINE_FAULTEN3_SHIFT 30u
4405 #define FTM_COMBINE_FAULTEN3_WIDTH 1u
4406 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_FAULTEN3_SHIFT))&FTM_COMBINE_FAULTEN3_MASK)
4407 #define FTM_COMBINE_MCOMBINE3_MASK 0x80000000u
4408 #define FTM_COMBINE_MCOMBINE3_SHIFT 31u
4409 #define FTM_COMBINE_MCOMBINE3_WIDTH 1u
4410 #define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x))<<FTM_COMBINE_MCOMBINE3_SHIFT))&FTM_COMBINE_MCOMBINE3_MASK)
4411 /* DEADTIME Bit Fields */
4412 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
4413 #define FTM_DEADTIME_DTVAL_SHIFT 0u
4414 #define FTM_DEADTIME_DTVAL_WIDTH 6u
4415 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
4416 #define FTM_DEADTIME_DTPS_MASK 0xC0u
4417 #define FTM_DEADTIME_DTPS_SHIFT 6u
4418 #define FTM_DEADTIME_DTPS_WIDTH 2u
4419 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
4420 #define FTM_DEADTIME_DTVALEX_MASK 0xF0000u
4421 #define FTM_DEADTIME_DTVALEX_SHIFT 16u
4422 #define FTM_DEADTIME_DTVALEX_WIDTH 4u
4423 #define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVALEX_SHIFT))&FTM_DEADTIME_DTVALEX_MASK)
4424 /* EXTTRIG Bit Fields */
4425 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
4426 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0u
4427 #define FTM_EXTTRIG_CH2TRIG_WIDTH 1u
4428 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH2TRIG_SHIFT))&FTM_EXTTRIG_CH2TRIG_MASK)
4429 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
4430 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1u
4431 #define FTM_EXTTRIG_CH3TRIG_WIDTH 1u
4432 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH3TRIG_SHIFT))&FTM_EXTTRIG_CH3TRIG_MASK)
4433 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
4434 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2u
4435 #define FTM_EXTTRIG_CH4TRIG_WIDTH 1u
4436 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH4TRIG_SHIFT))&FTM_EXTTRIG_CH4TRIG_MASK)
4437 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
4438 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3u
4439 #define FTM_EXTTRIG_CH5TRIG_WIDTH 1u
4440 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH5TRIG_SHIFT))&FTM_EXTTRIG_CH5TRIG_MASK)
4441 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
4442 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4u
4443 #define FTM_EXTTRIG_CH0TRIG_WIDTH 1u
4444 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH0TRIG_SHIFT))&FTM_EXTTRIG_CH0TRIG_MASK)
4445 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
4446 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5u
4447 #define FTM_EXTTRIG_CH1TRIG_WIDTH 1u
4448 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH1TRIG_SHIFT))&FTM_EXTTRIG_CH1TRIG_MASK)
4449 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
4450 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6u
4451 #define FTM_EXTTRIG_INITTRIGEN_WIDTH 1u
4452 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_INITTRIGEN_SHIFT))&FTM_EXTTRIG_INITTRIGEN_MASK)
4453 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
4454 #define FTM_EXTTRIG_TRIGF_SHIFT 7u
4455 #define FTM_EXTTRIG_TRIGF_WIDTH 1u
4456 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_TRIGF_SHIFT))&FTM_EXTTRIG_TRIGF_MASK)
4457 #define FTM_EXTTRIG_CH6TRIG_MASK 0x100u
4458 #define FTM_EXTTRIG_CH6TRIG_SHIFT 8u
4459 #define FTM_EXTTRIG_CH6TRIG_WIDTH 1u
4460 #define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH6TRIG_SHIFT))&FTM_EXTTRIG_CH6TRIG_MASK)
4461 #define FTM_EXTTRIG_CH7TRIG_MASK 0x200u
4462 #define FTM_EXTTRIG_CH7TRIG_SHIFT 9u
4463 #define FTM_EXTTRIG_CH7TRIG_WIDTH 1u
4464 #define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x))<<FTM_EXTTRIG_CH7TRIG_SHIFT))&FTM_EXTTRIG_CH7TRIG_MASK)
4465 /* POL Bit Fields */
4466 #define FTM_POL_POL0_MASK 0x1u
4467 #define FTM_POL_POL0_SHIFT 0u
4468 #define FTM_POL_POL0_WIDTH 1u
4469 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL0_SHIFT))&FTM_POL_POL0_MASK)
4470 #define FTM_POL_POL1_MASK 0x2u
4471 #define FTM_POL_POL1_SHIFT 1u
4472 #define FTM_POL_POL1_WIDTH 1u
4473 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL1_SHIFT))&FTM_POL_POL1_MASK)
4474 #define FTM_POL_POL2_MASK 0x4u
4475 #define FTM_POL_POL2_SHIFT 2u
4476 #define FTM_POL_POL2_WIDTH 1u
4477 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL2_SHIFT))&FTM_POL_POL2_MASK)
4478 #define FTM_POL_POL3_MASK 0x8u
4479 #define FTM_POL_POL3_SHIFT 3u
4480 #define FTM_POL_POL3_WIDTH 1u
4481 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL3_SHIFT))&FTM_POL_POL3_MASK)
4482 #define FTM_POL_POL4_MASK 0x10u
4483 #define FTM_POL_POL4_SHIFT 4u
4484 #define FTM_POL_POL4_WIDTH 1u
4485 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL4_SHIFT))&FTM_POL_POL4_MASK)
4486 #define FTM_POL_POL5_MASK 0x20u
4487 #define FTM_POL_POL5_SHIFT 5u
4488 #define FTM_POL_POL5_WIDTH 1u
4489 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL5_SHIFT))&FTM_POL_POL5_MASK)
4490 #define FTM_POL_POL6_MASK 0x40u
4491 #define FTM_POL_POL6_SHIFT 6u
4492 #define FTM_POL_POL6_WIDTH 1u
4493 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL6_SHIFT))&FTM_POL_POL6_MASK)
4494 #define FTM_POL_POL7_MASK 0x80u
4495 #define FTM_POL_POL7_SHIFT 7u
4496 #define FTM_POL_POL7_WIDTH 1u
4497 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x))<<FTM_POL_POL7_SHIFT))&FTM_POL_POL7_MASK)
4498 /* FMS Bit Fields */
4499 #define FTM_FMS_FAULTF0_MASK 0x1u
4500 #define FTM_FMS_FAULTF0_SHIFT 0u
4501 #define FTM_FMS_FAULTF0_WIDTH 1u
4502 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF0_SHIFT))&FTM_FMS_FAULTF0_MASK)
4503 #define FTM_FMS_FAULTF1_MASK 0x2u
4504 #define FTM_FMS_FAULTF1_SHIFT 1u
4505 #define FTM_FMS_FAULTF1_WIDTH 1u
4506 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF1_SHIFT))&FTM_FMS_FAULTF1_MASK)
4507 #define FTM_FMS_FAULTF2_MASK 0x4u
4508 #define FTM_FMS_FAULTF2_SHIFT 2u
4509 #define FTM_FMS_FAULTF2_WIDTH 1u
4510 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF2_SHIFT))&FTM_FMS_FAULTF2_MASK)
4511 #define FTM_FMS_FAULTF3_MASK 0x8u
4512 #define FTM_FMS_FAULTF3_SHIFT 3u
4513 #define FTM_FMS_FAULTF3_WIDTH 1u
4514 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF3_SHIFT))&FTM_FMS_FAULTF3_MASK)
4515 #define FTM_FMS_FAULTIN_MASK 0x20u
4516 #define FTM_FMS_FAULTIN_SHIFT 5u
4517 #define FTM_FMS_FAULTIN_WIDTH 1u
4518 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTIN_SHIFT))&FTM_FMS_FAULTIN_MASK)
4519 #define FTM_FMS_WPEN_MASK 0x40u
4520 #define FTM_FMS_WPEN_SHIFT 6u
4521 #define FTM_FMS_WPEN_WIDTH 1u
4522 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_WPEN_SHIFT))&FTM_FMS_WPEN_MASK)
4523 #define FTM_FMS_FAULTF_MASK 0x80u
4524 #define FTM_FMS_FAULTF_SHIFT 7u
4525 #define FTM_FMS_FAULTF_WIDTH 1u
4526 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x))<<FTM_FMS_FAULTF_SHIFT))&FTM_FMS_FAULTF_MASK)
4527 /* FILTER Bit Fields */
4528 #define FTM_FILTER_CH0FVAL_MASK 0xFu
4529 #define FTM_FILTER_CH0FVAL_SHIFT 0u
4530 #define FTM_FILTER_CH0FVAL_WIDTH 4u
4531 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
4532 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
4533 #define FTM_FILTER_CH1FVAL_SHIFT 4u
4534 #define FTM_FILTER_CH1FVAL_WIDTH 4u
4535 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
4536 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
4537 #define FTM_FILTER_CH2FVAL_SHIFT 8u
4538 #define FTM_FILTER_CH2FVAL_WIDTH 4u
4539 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
4540 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
4541 #define FTM_FILTER_CH3FVAL_SHIFT 12u
4542 #define FTM_FILTER_CH3FVAL_WIDTH 4u
4543 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
4544 /* FLTCTRL Bit Fields */
4545 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
4546 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0u
4547 #define FTM_FLTCTRL_FAULT0EN_WIDTH 1u
4548 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT0EN_SHIFT))&FTM_FLTCTRL_FAULT0EN_MASK)
4549 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
4550 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1u
4551 #define FTM_FLTCTRL_FAULT1EN_WIDTH 1u
4552 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT1EN_SHIFT))&FTM_FLTCTRL_FAULT1EN_MASK)
4553 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
4554 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2u
4555 #define FTM_FLTCTRL_FAULT2EN_WIDTH 1u
4556 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT2EN_SHIFT))&FTM_FLTCTRL_FAULT2EN_MASK)
4557 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
4558 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3u
4559 #define FTM_FLTCTRL_FAULT3EN_WIDTH 1u
4560 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FAULT3EN_SHIFT))&FTM_FLTCTRL_FAULT3EN_MASK)
4561 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
4562 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4u
4563 #define FTM_FLTCTRL_FFLTR0EN_WIDTH 1u
4564 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR0EN_SHIFT))&FTM_FLTCTRL_FFLTR0EN_MASK)
4565 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
4566 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5u
4567 #define FTM_FLTCTRL_FFLTR1EN_WIDTH 1u
4568 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR1EN_SHIFT))&FTM_FLTCTRL_FFLTR1EN_MASK)
4569 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
4570 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6u
4571 #define FTM_FLTCTRL_FFLTR2EN_WIDTH 1u
4572 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR2EN_SHIFT))&FTM_FLTCTRL_FFLTR2EN_MASK)
4573 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
4574 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7u
4575 #define FTM_FLTCTRL_FFLTR3EN_WIDTH 1u
4576 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFLTR3EN_SHIFT))&FTM_FLTCTRL_FFLTR3EN_MASK)
4577 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
4578 #define FTM_FLTCTRL_FFVAL_SHIFT 8u
4579 #define FTM_FLTCTRL_FFVAL_WIDTH 4u
4580 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
4581 #define FTM_FLTCTRL_FSTATE_MASK 0x8000u
4582 #define FTM_FLTCTRL_FSTATE_SHIFT 15u
4583 #define FTM_FLTCTRL_FSTATE_WIDTH 1u
4584 #define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FSTATE_SHIFT))&FTM_FLTCTRL_FSTATE_MASK)
4585 /* QDCTRL Bit Fields */
4586 #define FTM_QDCTRL_QUADEN_MASK 0x1u
4587 #define FTM_QDCTRL_QUADEN_SHIFT 0u
4588 #define FTM_QDCTRL_QUADEN_WIDTH 1u
4589 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADEN_SHIFT))&FTM_QDCTRL_QUADEN_MASK)
4590 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
4591 #define FTM_QDCTRL_TOFDIR_SHIFT 1u
4592 #define FTM_QDCTRL_TOFDIR_WIDTH 1u
4593 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_TOFDIR_SHIFT))&FTM_QDCTRL_TOFDIR_MASK)
4594 #define FTM_QDCTRL_QUADIR_MASK 0x4u
4595 #define FTM_QDCTRL_QUADIR_SHIFT 2u
4596 #define FTM_QDCTRL_QUADIR_WIDTH 1u
4597 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADIR_SHIFT))&FTM_QDCTRL_QUADIR_MASK)
4598 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
4599 #define FTM_QDCTRL_QUADMODE_SHIFT 3u
4600 #define FTM_QDCTRL_QUADMODE_WIDTH 1u
4601 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_QUADMODE_SHIFT))&FTM_QDCTRL_QUADMODE_MASK)
4602 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
4603 #define FTM_QDCTRL_PHBPOL_SHIFT 4u
4604 #define FTM_QDCTRL_PHBPOL_WIDTH 1u
4605 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBPOL_SHIFT))&FTM_QDCTRL_PHBPOL_MASK)
4606 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
4607 #define FTM_QDCTRL_PHAPOL_SHIFT 5u
4608 #define FTM_QDCTRL_PHAPOL_WIDTH 1u
4609 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAPOL_SHIFT))&FTM_QDCTRL_PHAPOL_MASK)
4610 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
4611 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6u
4612 #define FTM_QDCTRL_PHBFLTREN_WIDTH 1u
4613 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHBFLTREN_SHIFT))&FTM_QDCTRL_PHBFLTREN_MASK)
4614 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
4615 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7u
4616 #define FTM_QDCTRL_PHAFLTREN_WIDTH 1u
4617 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x))<<FTM_QDCTRL_PHAFLTREN_SHIFT))&FTM_QDCTRL_PHAFLTREN_MASK)
4618 /* CONF Bit Fields */
4619 #define FTM_CONF_LDFQ_MASK 0x1Fu
4620 #define FTM_CONF_LDFQ_SHIFT 0u
4621 #define FTM_CONF_LDFQ_WIDTH 5u
4622 #define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_LDFQ_SHIFT))&FTM_CONF_LDFQ_MASK)
4623 #define FTM_CONF_BDMMODE_MASK 0xC0u
4624 #define FTM_CONF_BDMMODE_SHIFT 6u
4625 #define FTM_CONF_BDMMODE_WIDTH 2u
4626 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
4627 #define FTM_CONF_GTBEEN_MASK 0x200u
4628 #define FTM_CONF_GTBEEN_SHIFT 9u
4629 #define FTM_CONF_GTBEEN_WIDTH 1u
4630 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEEN_SHIFT))&FTM_CONF_GTBEEN_MASK)
4631 #define FTM_CONF_GTBEOUT_MASK 0x400u
4632 #define FTM_CONF_GTBEOUT_SHIFT 10u
4633 #define FTM_CONF_GTBEOUT_WIDTH 1u
4634 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_GTBEOUT_SHIFT))&FTM_CONF_GTBEOUT_MASK)
4635 #define FTM_CONF_ITRIGR_MASK 0x800u
4636 #define FTM_CONF_ITRIGR_SHIFT 11u
4637 #define FTM_CONF_ITRIGR_WIDTH 1u
4638 #define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_ITRIGR_SHIFT))&FTM_CONF_ITRIGR_MASK)
4639 /* FLTPOL Bit Fields */
4640 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
4641 #define FTM_FLTPOL_FLT0POL_SHIFT 0u
4642 #define FTM_FLTPOL_FLT0POL_WIDTH 1u
4643 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT0POL_SHIFT))&FTM_FLTPOL_FLT0POL_MASK)
4644 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
4645 #define FTM_FLTPOL_FLT1POL_SHIFT 1u
4646 #define FTM_FLTPOL_FLT1POL_WIDTH 1u
4647 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT1POL_SHIFT))&FTM_FLTPOL_FLT1POL_MASK)
4648 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
4649 #define FTM_FLTPOL_FLT2POL_SHIFT 2u
4650 #define FTM_FLTPOL_FLT2POL_WIDTH 1u
4651 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT2POL_SHIFT))&FTM_FLTPOL_FLT2POL_MASK)
4652 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
4653 #define FTM_FLTPOL_FLT3POL_SHIFT 3u
4654 #define FTM_FLTPOL_FLT3POL_WIDTH 1u
4655 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTPOL_FLT3POL_SHIFT))&FTM_FLTPOL_FLT3POL_MASK)
4656 /* SYNCONF Bit Fields */
4657 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
4658 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0u
4659 #define FTM_SYNCONF_HWTRIGMODE_WIDTH 1u
4660 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWTRIGMODE_SHIFT))&FTM_SYNCONF_HWTRIGMODE_MASK)
4661 #define FTM_SYNCONF_CNTINC_MASK 0x4u
4662 #define FTM_SYNCONF_CNTINC_SHIFT 2u
4663 #define FTM_SYNCONF_CNTINC_WIDTH 1u
4664 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_CNTINC_SHIFT))&FTM_SYNCONF_CNTINC_MASK)
4665 #define FTM_SYNCONF_INVC_MASK 0x10u
4666 #define FTM_SYNCONF_INVC_SHIFT 4u
4667 #define FTM_SYNCONF_INVC_WIDTH 1u
4668 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_INVC_SHIFT))&FTM_SYNCONF_INVC_MASK)
4669 #define FTM_SYNCONF_SWOC_MASK 0x20u
4670 #define FTM_SYNCONF_SWOC_SHIFT 5u
4671 #define FTM_SYNCONF_SWOC_WIDTH 1u
4672 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOC_SHIFT))&FTM_SYNCONF_SWOC_MASK)
4673 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
4674 #define FTM_SYNCONF_SYNCMODE_SHIFT 7u
4675 #define FTM_SYNCONF_SYNCMODE_WIDTH 1u
4676 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SYNCMODE_SHIFT))&FTM_SYNCONF_SYNCMODE_MASK)
4677 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
4678 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8u
4679 #define FTM_SYNCONF_SWRSTCNT_WIDTH 1u
4680 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWRSTCNT_SHIFT))&FTM_SYNCONF_SWRSTCNT_MASK)
4681 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
4682 #define FTM_SYNCONF_SWWRBUF_SHIFT 9u
4683 #define FTM_SYNCONF_SWWRBUF_WIDTH 1u
4684 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWWRBUF_SHIFT))&FTM_SYNCONF_SWWRBUF_MASK)
4685 #define FTM_SYNCONF_SWOM_MASK 0x400u
4686 #define FTM_SYNCONF_SWOM_SHIFT 10u
4687 #define FTM_SYNCONF_SWOM_WIDTH 1u
4688 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWOM_SHIFT))&FTM_SYNCONF_SWOM_MASK)
4689 #define FTM_SYNCONF_SWINVC_MASK 0x800u
4690 #define FTM_SYNCONF_SWINVC_SHIFT 11u
4691 #define FTM_SYNCONF_SWINVC_WIDTH 1u
4692 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWINVC_SHIFT))&FTM_SYNCONF_SWINVC_MASK)
4693 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
4694 #define FTM_SYNCONF_SWSOC_SHIFT 12u
4695 #define FTM_SYNCONF_SWSOC_WIDTH 1u
4696 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_SWSOC_SHIFT))&FTM_SYNCONF_SWSOC_MASK)
4697 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
4698 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16u
4699 #define FTM_SYNCONF_HWRSTCNT_WIDTH 1u
4700 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWRSTCNT_SHIFT))&FTM_SYNCONF_HWRSTCNT_MASK)
4701 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
4702 #define FTM_SYNCONF_HWWRBUF_SHIFT 17u
4703 #define FTM_SYNCONF_HWWRBUF_WIDTH 1u
4704 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWWRBUF_SHIFT))&FTM_SYNCONF_HWWRBUF_MASK)
4705 #define FTM_SYNCONF_HWOM_MASK 0x40000u
4706 #define FTM_SYNCONF_HWOM_SHIFT 18u
4707 #define FTM_SYNCONF_HWOM_WIDTH 1u
4708 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWOM_SHIFT))&FTM_SYNCONF_HWOM_MASK)
4709 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
4710 #define FTM_SYNCONF_HWINVC_SHIFT 19u
4711 #define FTM_SYNCONF_HWINVC_WIDTH 1u
4712 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWINVC_SHIFT))&FTM_SYNCONF_HWINVC_MASK)
4713 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
4714 #define FTM_SYNCONF_HWSOC_SHIFT 20u
4715 #define FTM_SYNCONF_HWSOC_WIDTH 1u
4716 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SYNCONF_HWSOC_SHIFT))&FTM_SYNCONF_HWSOC_MASK)
4717 /* INVCTRL Bit Fields */
4718 #define FTM_INVCTRL_INV0EN_MASK 0x1u
4719 #define FTM_INVCTRL_INV0EN_SHIFT 0u
4720 #define FTM_INVCTRL_INV0EN_WIDTH 1u
4721 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV0EN_SHIFT))&FTM_INVCTRL_INV0EN_MASK)
4722 #define FTM_INVCTRL_INV1EN_MASK 0x2u
4723 #define FTM_INVCTRL_INV1EN_SHIFT 1u
4724 #define FTM_INVCTRL_INV1EN_WIDTH 1u
4725 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV1EN_SHIFT))&FTM_INVCTRL_INV1EN_MASK)
4726 #define FTM_INVCTRL_INV2EN_MASK 0x4u
4727 #define FTM_INVCTRL_INV2EN_SHIFT 2u
4728 #define FTM_INVCTRL_INV2EN_WIDTH 1u
4729 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV2EN_SHIFT))&FTM_INVCTRL_INV2EN_MASK)
4730 #define FTM_INVCTRL_INV3EN_MASK 0x8u
4731 #define FTM_INVCTRL_INV3EN_SHIFT 3u
4732 #define FTM_INVCTRL_INV3EN_WIDTH 1u
4733 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x))<<FTM_INVCTRL_INV3EN_SHIFT))&FTM_INVCTRL_INV3EN_MASK)
4734 /* SWOCTRL Bit Fields */
4735 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
4736 #define FTM_SWOCTRL_CH0OC_SHIFT 0u
4737 #define FTM_SWOCTRL_CH0OC_WIDTH 1u
4738 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OC_SHIFT))&FTM_SWOCTRL_CH0OC_MASK)
4739 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
4740 #define FTM_SWOCTRL_CH1OC_SHIFT 1u
4741 #define FTM_SWOCTRL_CH1OC_WIDTH 1u
4742 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OC_SHIFT))&FTM_SWOCTRL_CH1OC_MASK)
4743 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
4744 #define FTM_SWOCTRL_CH2OC_SHIFT 2u
4745 #define FTM_SWOCTRL_CH2OC_WIDTH 1u
4746 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OC_SHIFT))&FTM_SWOCTRL_CH2OC_MASK)
4747 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
4748 #define FTM_SWOCTRL_CH3OC_SHIFT 3u
4749 #define FTM_SWOCTRL_CH3OC_WIDTH 1u
4750 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OC_SHIFT))&FTM_SWOCTRL_CH3OC_MASK)
4751 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
4752 #define FTM_SWOCTRL_CH4OC_SHIFT 4u
4753 #define FTM_SWOCTRL_CH4OC_WIDTH 1u
4754 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OC_SHIFT))&FTM_SWOCTRL_CH4OC_MASK)
4755 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
4756 #define FTM_SWOCTRL_CH5OC_SHIFT 5u
4757 #define FTM_SWOCTRL_CH5OC_WIDTH 1u
4758 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OC_SHIFT))&FTM_SWOCTRL_CH5OC_MASK)
4759 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
4760 #define FTM_SWOCTRL_CH6OC_SHIFT 6u
4761 #define FTM_SWOCTRL_CH6OC_WIDTH 1u
4762 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OC_SHIFT))&FTM_SWOCTRL_CH6OC_MASK)
4763 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
4764 #define FTM_SWOCTRL_CH7OC_SHIFT 7u
4765 #define FTM_SWOCTRL_CH7OC_WIDTH 1u
4766 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OC_SHIFT))&FTM_SWOCTRL_CH7OC_MASK)
4767 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
4768 #define FTM_SWOCTRL_CH0OCV_SHIFT 8u
4769 #define FTM_SWOCTRL_CH0OCV_WIDTH 1u
4770 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH0OCV_SHIFT))&FTM_SWOCTRL_CH0OCV_MASK)
4771 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
4772 #define FTM_SWOCTRL_CH1OCV_SHIFT 9u
4773 #define FTM_SWOCTRL_CH1OCV_WIDTH 1u
4774 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH1OCV_SHIFT))&FTM_SWOCTRL_CH1OCV_MASK)
4775 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
4776 #define FTM_SWOCTRL_CH2OCV_SHIFT 10u
4777 #define FTM_SWOCTRL_CH2OCV_WIDTH 1u
4778 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH2OCV_SHIFT))&FTM_SWOCTRL_CH2OCV_MASK)
4779 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
4780 #define FTM_SWOCTRL_CH3OCV_SHIFT 11u
4781 #define FTM_SWOCTRL_CH3OCV_WIDTH 1u
4782 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH3OCV_SHIFT))&FTM_SWOCTRL_CH3OCV_MASK)
4783 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
4784 #define FTM_SWOCTRL_CH4OCV_SHIFT 12u
4785 #define FTM_SWOCTRL_CH4OCV_WIDTH 1u
4786 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH4OCV_SHIFT))&FTM_SWOCTRL_CH4OCV_MASK)
4787 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
4788 #define FTM_SWOCTRL_CH5OCV_SHIFT 13u
4789 #define FTM_SWOCTRL_CH5OCV_WIDTH 1u
4790 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH5OCV_SHIFT))&FTM_SWOCTRL_CH5OCV_MASK)
4791 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
4792 #define FTM_SWOCTRL_CH6OCV_SHIFT 14u
4793 #define FTM_SWOCTRL_CH6OCV_WIDTH 1u
4794 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH6OCV_SHIFT))&FTM_SWOCTRL_CH6OCV_MASK)
4795 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
4796 #define FTM_SWOCTRL_CH7OCV_SHIFT 15u
4797 #define FTM_SWOCTRL_CH7OCV_WIDTH 1u
4798 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x))<<FTM_SWOCTRL_CH7OCV_SHIFT))&FTM_SWOCTRL_CH7OCV_MASK)
4799 /* PWMLOAD Bit Fields */
4800 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
4801 #define FTM_PWMLOAD_CH0SEL_SHIFT 0u
4802 #define FTM_PWMLOAD_CH0SEL_WIDTH 1u
4803 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH0SEL_SHIFT))&FTM_PWMLOAD_CH0SEL_MASK)
4804 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
4805 #define FTM_PWMLOAD_CH1SEL_SHIFT 1u
4806 #define FTM_PWMLOAD_CH1SEL_WIDTH 1u
4807 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH1SEL_SHIFT))&FTM_PWMLOAD_CH1SEL_MASK)
4808 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
4809 #define FTM_PWMLOAD_CH2SEL_SHIFT 2u
4810 #define FTM_PWMLOAD_CH2SEL_WIDTH 1u
4811 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH2SEL_SHIFT))&FTM_PWMLOAD_CH2SEL_MASK)
4812 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
4813 #define FTM_PWMLOAD_CH3SEL_SHIFT 3u
4814 #define FTM_PWMLOAD_CH3SEL_WIDTH 1u
4815 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH3SEL_SHIFT))&FTM_PWMLOAD_CH3SEL_MASK)
4816 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
4817 #define FTM_PWMLOAD_CH4SEL_SHIFT 4u
4818 #define FTM_PWMLOAD_CH4SEL_WIDTH 1u
4819 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH4SEL_SHIFT))&FTM_PWMLOAD_CH4SEL_MASK)
4820 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
4821 #define FTM_PWMLOAD_CH5SEL_SHIFT 5u
4822 #define FTM_PWMLOAD_CH5SEL_WIDTH 1u
4823 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH5SEL_SHIFT))&FTM_PWMLOAD_CH5SEL_MASK)
4824 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
4825 #define FTM_PWMLOAD_CH6SEL_SHIFT 6u
4826 #define FTM_PWMLOAD_CH6SEL_WIDTH 1u
4827 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH6SEL_SHIFT))&FTM_PWMLOAD_CH6SEL_MASK)
4828 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
4829 #define FTM_PWMLOAD_CH7SEL_SHIFT 7u
4830 #define FTM_PWMLOAD_CH7SEL_WIDTH 1u
4831 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_CH7SEL_SHIFT))&FTM_PWMLOAD_CH7SEL_MASK)
4832 #define FTM_PWMLOAD_HCSEL_MASK 0x100u
4833 #define FTM_PWMLOAD_HCSEL_SHIFT 8u
4834 #define FTM_PWMLOAD_HCSEL_WIDTH 1u
4835 #define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_HCSEL_SHIFT))&FTM_PWMLOAD_HCSEL_MASK)
4836 #define FTM_PWMLOAD_LDOK_MASK 0x200u
4837 #define FTM_PWMLOAD_LDOK_SHIFT 9u
4838 #define FTM_PWMLOAD_LDOK_WIDTH 1u
4839 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_LDOK_SHIFT))&FTM_PWMLOAD_LDOK_MASK)
4840 #define FTM_PWMLOAD_GLEN_MASK 0x400u
4841 #define FTM_PWMLOAD_GLEN_SHIFT 10u
4842 #define FTM_PWMLOAD_GLEN_WIDTH 1u
4843 #define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLEN_SHIFT))&FTM_PWMLOAD_GLEN_MASK)
4844 #define FTM_PWMLOAD_GLDOK_MASK 0x800u
4845 #define FTM_PWMLOAD_GLDOK_SHIFT 11u
4846 #define FTM_PWMLOAD_GLDOK_WIDTH 1u
4847 #define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x))<<FTM_PWMLOAD_GLDOK_SHIFT))&FTM_PWMLOAD_GLDOK_MASK)
4848 /* HCR Bit Fields */
4849 #define FTM_HCR_HCVAL_MASK 0xFFFFu
4850 #define FTM_HCR_HCVAL_SHIFT 0u
4851 #define FTM_HCR_HCVAL_WIDTH 16u
4852 #define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_HCR_HCVAL_SHIFT))&FTM_HCR_HCVAL_MASK)
4853 /* PAIR0DEADTIME Bit Fields */
4854 #define FTM_PAIR0DEADTIME_DTVAL_MASK 0x3Fu
4855 #define FTM_PAIR0DEADTIME_DTVAL_SHIFT 0u
4856 #define FTM_PAIR0DEADTIME_DTVAL_WIDTH 6u
4857 #define FTM_PAIR0DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVAL_SHIFT))&FTM_PAIR0DEADTIME_DTVAL_MASK)
4858 #define FTM_PAIR0DEADTIME_DTPS_MASK 0xC0u
4859 #define FTM_PAIR0DEADTIME_DTPS_SHIFT 6u
4860 #define FTM_PAIR0DEADTIME_DTPS_WIDTH 2u
4861 #define FTM_PAIR0DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTPS_SHIFT))&FTM_PAIR0DEADTIME_DTPS_MASK)
4862 #define FTM_PAIR0DEADTIME_DTVALEX_MASK 0xF0000u
4863 #define FTM_PAIR0DEADTIME_DTVALEX_SHIFT 16u
4864 #define FTM_PAIR0DEADTIME_DTVALEX_WIDTH 4u
4865 #define FTM_PAIR0DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR0DEADTIME_DTVALEX_SHIFT))&FTM_PAIR0DEADTIME_DTVALEX_MASK)
4866 /* PAIR1DEADTIME Bit Fields */
4867 #define FTM_PAIR1DEADTIME_DTVAL_MASK 0x3Fu
4868 #define FTM_PAIR1DEADTIME_DTVAL_SHIFT 0u
4869 #define FTM_PAIR1DEADTIME_DTVAL_WIDTH 6u
4870 #define FTM_PAIR1DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVAL_SHIFT))&FTM_PAIR1DEADTIME_DTVAL_MASK)
4871 #define FTM_PAIR1DEADTIME_DTPS_MASK 0xC0u
4872 #define FTM_PAIR1DEADTIME_DTPS_SHIFT 6u
4873 #define FTM_PAIR1DEADTIME_DTPS_WIDTH 2u
4874 #define FTM_PAIR1DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTPS_SHIFT))&FTM_PAIR1DEADTIME_DTPS_MASK)
4875 #define FTM_PAIR1DEADTIME_DTVALEX_MASK 0xF0000u
4876 #define FTM_PAIR1DEADTIME_DTVALEX_SHIFT 16u
4877 #define FTM_PAIR1DEADTIME_DTVALEX_WIDTH 4u
4878 #define FTM_PAIR1DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR1DEADTIME_DTVALEX_SHIFT))&FTM_PAIR1DEADTIME_DTVALEX_MASK)
4879 /* PAIR2DEADTIME Bit Fields */
4880 #define FTM_PAIR2DEADTIME_DTVAL_MASK 0x3Fu
4881 #define FTM_PAIR2DEADTIME_DTVAL_SHIFT 0u
4882 #define FTM_PAIR2DEADTIME_DTVAL_WIDTH 6u
4883 #define FTM_PAIR2DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVAL_SHIFT))&FTM_PAIR2DEADTIME_DTVAL_MASK)
4884 #define FTM_PAIR2DEADTIME_DTPS_MASK 0xC0u
4885 #define FTM_PAIR2DEADTIME_DTPS_SHIFT 6u
4886 #define FTM_PAIR2DEADTIME_DTPS_WIDTH 2u
4887 #define FTM_PAIR2DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTPS_SHIFT))&FTM_PAIR2DEADTIME_DTPS_MASK)
4888 #define FTM_PAIR2DEADTIME_DTVALEX_MASK 0xF0000u
4889 #define FTM_PAIR2DEADTIME_DTVALEX_SHIFT 16u
4890 #define FTM_PAIR2DEADTIME_DTVALEX_WIDTH 4u
4891 #define FTM_PAIR2DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR2DEADTIME_DTVALEX_SHIFT))&FTM_PAIR2DEADTIME_DTVALEX_MASK)
4892 /* PAIR3DEADTIME Bit Fields */
4893 #define FTM_PAIR3DEADTIME_DTVAL_MASK 0x3Fu
4894 #define FTM_PAIR3DEADTIME_DTVAL_SHIFT 0u
4895 #define FTM_PAIR3DEADTIME_DTVAL_WIDTH 6u
4896 #define FTM_PAIR3DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVAL_SHIFT))&FTM_PAIR3DEADTIME_DTVAL_MASK)
4897 #define FTM_PAIR3DEADTIME_DTPS_MASK 0xC0u
4898 #define FTM_PAIR3DEADTIME_DTPS_SHIFT 6u
4899 #define FTM_PAIR3DEADTIME_DTPS_WIDTH 2u
4900 #define FTM_PAIR3DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTPS_SHIFT))&FTM_PAIR3DEADTIME_DTPS_MASK)
4901 #define FTM_PAIR3DEADTIME_DTVALEX_MASK 0xF0000u
4902 #define FTM_PAIR3DEADTIME_DTVALEX_SHIFT 16u
4903 #define FTM_PAIR3DEADTIME_DTVALEX_WIDTH 4u
4904 #define FTM_PAIR3DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x))<<FTM_PAIR3DEADTIME_DTVALEX_SHIFT))&FTM_PAIR3DEADTIME_DTVALEX_MASK)
4905 /* MOD_MIRROR Bit Fields */
4906 #define FTM_MOD_MIRROR_FRACMOD_MASK 0xF800u
4907 #define FTM_MOD_MIRROR_FRACMOD_SHIFT 11u
4908 #define FTM_MOD_MIRROR_FRACMOD_WIDTH 5u
4909 #define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_FRACMOD_SHIFT))&FTM_MOD_MIRROR_FRACMOD_MASK)
4910 #define FTM_MOD_MIRROR_MOD_MASK 0xFFFF0000u
4911 #define FTM_MOD_MIRROR_MOD_SHIFT 16u
4912 #define FTM_MOD_MIRROR_MOD_WIDTH 16u
4913 #define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MIRROR_MOD_SHIFT))&FTM_MOD_MIRROR_MOD_MASK)
4914 /* CV_MIRROR Bit Fields */
4915 #define FTM_CV_MIRROR_FRACVAL_MASK 0xF800u
4916 #define FTM_CV_MIRROR_FRACVAL_SHIFT 11u
4917 #define FTM_CV_MIRROR_FRACVAL_WIDTH 5u
4918 #define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_FRACVAL_SHIFT))&FTM_CV_MIRROR_FRACVAL_MASK)
4919 #define FTM_CV_MIRROR_VAL_MASK 0xFFFF0000u
4920 #define FTM_CV_MIRROR_VAL_SHIFT 16u
4921 #define FTM_CV_MIRROR_VAL_WIDTH 16u
4922 #define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CV_MIRROR_VAL_SHIFT))&FTM_CV_MIRROR_VAL_MASK)
4923  /* end of group FTM_Register_Masks */
4927 
4928  /* end of group FTM_Peripheral_Access_Layer */
4932 
4933 
4934 /* ----------------------------------------------------------------------------
4935  -- GPIO Peripheral Access Layer
4936  ---------------------------------------------------------------------------- */
4937 
4947 typedef struct {
4948  __IO uint32_t PDOR;
4949  __O uint32_t PSOR;
4950  __O uint32_t PCOR;
4951  __O uint32_t PTOR;
4952  __I uint32_t PDIR;
4953  __IO uint32_t PDDR;
4954  __IO uint32_t PIDR;
4956 
4958 #define GPIO_INSTANCE_COUNT (5u)
4959 
4960 
4961 /* GPIO - Peripheral instance base addresses */
4963 #define PTA_BASE (0x400FF000u)
4964 
4965 #define PTA ((GPIO_Type *)PTA_BASE)
4966 
4967 #define PTB_BASE (0x400FF040u)
4968 
4969 #define PTB ((GPIO_Type *)PTB_BASE)
4970 
4971 #define PTC_BASE (0x400FF080u)
4972 
4973 #define PTC ((GPIO_Type *)PTC_BASE)
4974 
4975 #define PTD_BASE (0x400FF0C0u)
4976 
4977 #define PTD ((GPIO_Type *)PTD_BASE)
4978 
4979 #define PTE_BASE (0x400FF100u)
4980 
4981 #define PTE ((GPIO_Type *)PTE_BASE)
4982 
4983 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
4984 
4985 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
4986 
4987 /* ----------------------------------------------------------------------------
4988  -- GPIO Register Masks
4989  ---------------------------------------------------------------------------- */
4990 
4996 /* PDOR Bit Fields */
4997 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
4998 #define GPIO_PDOR_PDO_SHIFT 0u
4999 #define GPIO_PDOR_PDO_WIDTH 32u
5000 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
5001 /* PSOR Bit Fields */
5002 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
5003 #define GPIO_PSOR_PTSO_SHIFT 0u
5004 #define GPIO_PSOR_PTSO_WIDTH 32u
5005 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
5006 /* PCOR Bit Fields */
5007 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
5008 #define GPIO_PCOR_PTCO_SHIFT 0u
5009 #define GPIO_PCOR_PTCO_WIDTH 32u
5010 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
5011 /* PTOR Bit Fields */
5012 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
5013 #define GPIO_PTOR_PTTO_SHIFT 0u
5014 #define GPIO_PTOR_PTTO_WIDTH 32u
5015 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
5016 /* PDIR Bit Fields */
5017 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
5018 #define GPIO_PDIR_PDI_SHIFT 0u
5019 #define GPIO_PDIR_PDI_WIDTH 32u
5020 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
5021 /* PDDR Bit Fields */
5022 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
5023 #define GPIO_PDDR_PDD_SHIFT 0u
5024 #define GPIO_PDDR_PDD_WIDTH 32u
5025 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
5026 /* PIDR Bit Fields */
5027 #define GPIO_PIDR_PID_MASK 0xFFFFFFFFu
5028 #define GPIO_PIDR_PID_SHIFT 0u
5029 #define GPIO_PIDR_PID_WIDTH 32u
5030 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PIDR_PID_SHIFT))&GPIO_PIDR_PID_MASK)
5031  /* end of group GPIO_Register_Masks */
5035 
5036  /* end of group GPIO_Peripheral_Access_Layer */
5040 
5041 
5042 /* ----------------------------------------------------------------------------
5043  -- LMEM Peripheral Access Layer
5044  ---------------------------------------------------------------------------- */
5045 
5055 typedef struct {
5056  __IO uint32_t PCCCR;
5057  __IO uint32_t PCCLCR;
5058  __IO uint32_t PCCSAR;
5059  __IO uint32_t PCCCVR;
5060  uint8_t RESERVED_0[16];
5061  __IO uint32_t PCCRMR;
5063 
5065 #define LMEM_INSTANCE_COUNT (1u)
5066 
5067 
5068 /* LMEM - Peripheral instance base addresses */
5070 #define LMEM_BASE (0xE0082000u)
5071 
5072 #define LMEM ((LMEM_Type *)LMEM_BASE)
5073 
5074 #define LMEM_BASE_ADDRS { LMEM_BASE }
5075 
5076 #define LMEM_BASE_PTRS { LMEM }
5077 
5078 /* ----------------------------------------------------------------------------
5079  -- LMEM Register Masks
5080  ---------------------------------------------------------------------------- */
5081 
5087 /* PCCCR Bit Fields */
5088 #define LMEM_PCCCR_ENCACHE_MASK 0x1u
5089 #define LMEM_PCCCR_ENCACHE_SHIFT 0u
5090 #define LMEM_PCCCR_ENCACHE_WIDTH 1u
5091 #define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_ENCACHE_SHIFT))&LMEM_PCCCR_ENCACHE_MASK)
5092 #define LMEM_PCCCR_PCCR2_MASK 0x4u
5093 #define LMEM_PCCCR_PCCR2_SHIFT 2u
5094 #define LMEM_PCCCR_PCCR2_WIDTH 1u
5095 #define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR2_SHIFT))&LMEM_PCCCR_PCCR2_MASK)
5096 #define LMEM_PCCCR_PCCR3_MASK 0x8u
5097 #define LMEM_PCCCR_PCCR3_SHIFT 3u
5098 #define LMEM_PCCCR_PCCR3_WIDTH 1u
5099 #define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PCCR3_SHIFT))&LMEM_PCCCR_PCCR3_MASK)
5100 #define LMEM_PCCCR_INVW0_MASK 0x1000000u
5101 #define LMEM_PCCCR_INVW0_SHIFT 24u
5102 #define LMEM_PCCCR_INVW0_WIDTH 1u
5103 #define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW0_SHIFT))&LMEM_PCCCR_INVW0_MASK)
5104 #define LMEM_PCCCR_PUSHW0_MASK 0x2000000u
5105 #define LMEM_PCCCR_PUSHW0_SHIFT 25u
5106 #define LMEM_PCCCR_PUSHW0_WIDTH 1u
5107 #define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW0_SHIFT))&LMEM_PCCCR_PUSHW0_MASK)
5108 #define LMEM_PCCCR_INVW1_MASK 0x4000000u
5109 #define LMEM_PCCCR_INVW1_SHIFT 26u
5110 #define LMEM_PCCCR_INVW1_WIDTH 1u
5111 #define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_INVW1_SHIFT))&LMEM_PCCCR_INVW1_MASK)
5112 #define LMEM_PCCCR_PUSHW1_MASK 0x8000000u
5113 #define LMEM_PCCCR_PUSHW1_SHIFT 27u
5114 #define LMEM_PCCCR_PUSHW1_WIDTH 1u
5115 #define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_PUSHW1_SHIFT))&LMEM_PCCCR_PUSHW1_MASK)
5116 #define LMEM_PCCCR_GO_MASK 0x80000000u
5117 #define LMEM_PCCCR_GO_SHIFT 31u
5118 #define LMEM_PCCCR_GO_WIDTH 1u
5119 #define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCR_GO_SHIFT))&LMEM_PCCCR_GO_MASK)
5120 /* PCCLCR Bit Fields */
5121 #define LMEM_PCCLCR_LGO_MASK 0x1u
5122 #define LMEM_PCCLCR_LGO_SHIFT 0u
5123 #define LMEM_PCCLCR_LGO_WIDTH 1u
5124 #define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LGO_SHIFT))&LMEM_PCCLCR_LGO_MASK)
5125 #define LMEM_PCCLCR_CACHEADDR_MASK 0x3FFCu
5126 #define LMEM_PCCLCR_CACHEADDR_SHIFT 2u
5127 #define LMEM_PCCLCR_CACHEADDR_WIDTH 12u
5128 #define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_CACHEADDR_SHIFT))&LMEM_PCCLCR_CACHEADDR_MASK)
5129 #define LMEM_PCCLCR_WSEL_MASK 0x4000u
5130 #define LMEM_PCCLCR_WSEL_SHIFT 14u
5131 #define LMEM_PCCLCR_WSEL_WIDTH 1u
5132 #define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_WSEL_SHIFT))&LMEM_PCCLCR_WSEL_MASK)
5133 #define LMEM_PCCLCR_TDSEL_MASK 0x10000u
5134 #define LMEM_PCCLCR_TDSEL_SHIFT 16u
5135 #define LMEM_PCCLCR_TDSEL_WIDTH 1u
5136 #define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_TDSEL_SHIFT))&LMEM_PCCLCR_TDSEL_MASK)
5137 #define LMEM_PCCLCR_LCIVB_MASK 0x100000u
5138 #define LMEM_PCCLCR_LCIVB_SHIFT 20u
5139 #define LMEM_PCCLCR_LCIVB_WIDTH 1u
5140 #define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIVB_SHIFT))&LMEM_PCCLCR_LCIVB_MASK)
5141 #define LMEM_PCCLCR_LCIMB_MASK 0x200000u
5142 #define LMEM_PCCLCR_LCIMB_SHIFT 21u
5143 #define LMEM_PCCLCR_LCIMB_WIDTH 1u
5144 #define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCIMB_SHIFT))&LMEM_PCCLCR_LCIMB_MASK)
5145 #define LMEM_PCCLCR_LCWAY_MASK 0x400000u
5146 #define LMEM_PCCLCR_LCWAY_SHIFT 22u
5147 #define LMEM_PCCLCR_LCWAY_WIDTH 1u
5148 #define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCWAY_SHIFT))&LMEM_PCCLCR_LCWAY_MASK)
5149 #define LMEM_PCCLCR_LCMD_MASK 0x3000000u
5150 #define LMEM_PCCLCR_LCMD_SHIFT 24u
5151 #define LMEM_PCCLCR_LCMD_WIDTH 2u
5152 #define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LCMD_SHIFT))&LMEM_PCCLCR_LCMD_MASK)
5153 #define LMEM_PCCLCR_LADSEL_MASK 0x4000000u
5154 #define LMEM_PCCLCR_LADSEL_SHIFT 26u
5155 #define LMEM_PCCLCR_LADSEL_WIDTH 1u
5156 #define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LADSEL_SHIFT))&LMEM_PCCLCR_LADSEL_MASK)
5157 #define LMEM_PCCLCR_LACC_MASK 0x8000000u
5158 #define LMEM_PCCLCR_LACC_SHIFT 27u
5159 #define LMEM_PCCLCR_LACC_WIDTH 1u
5160 #define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCLCR_LACC_SHIFT))&LMEM_PCCLCR_LACC_MASK)
5161 /* PCCSAR Bit Fields */
5162 #define LMEM_PCCSAR_LGO_MASK 0x1u
5163 #define LMEM_PCCSAR_LGO_SHIFT 0u
5164 #define LMEM_PCCSAR_LGO_WIDTH 1u
5165 #define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_LGO_SHIFT))&LMEM_PCCSAR_LGO_MASK)
5166 #define LMEM_PCCSAR_PHYADDR_MASK 0xFFFFFFFCu
5167 #define LMEM_PCCSAR_PHYADDR_SHIFT 2u
5168 #define LMEM_PCCSAR_PHYADDR_WIDTH 30u
5169 #define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCSAR_PHYADDR_SHIFT))&LMEM_PCCSAR_PHYADDR_MASK)
5170 /* PCCCVR Bit Fields */
5171 #define LMEM_PCCCVR_DATA_MASK 0xFFFFFFFFu
5172 #define LMEM_PCCCVR_DATA_SHIFT 0u
5173 #define LMEM_PCCCVR_DATA_WIDTH 32u
5174 #define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCCVR_DATA_SHIFT))&LMEM_PCCCVR_DATA_MASK)
5175 /* PCCRMR Bit Fields */
5176 #define LMEM_PCCRMR_R15_MASK 0x3u
5177 #define LMEM_PCCRMR_R15_SHIFT 0u
5178 #define LMEM_PCCRMR_R15_WIDTH 2u
5179 #define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R15_SHIFT))&LMEM_PCCRMR_R15_MASK)
5180 #define LMEM_PCCRMR_R14_MASK 0xCu
5181 #define LMEM_PCCRMR_R14_SHIFT 2u
5182 #define LMEM_PCCRMR_R14_WIDTH 2u
5183 #define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R14_SHIFT))&LMEM_PCCRMR_R14_MASK)
5184 #define LMEM_PCCRMR_R13_MASK 0x30u
5185 #define LMEM_PCCRMR_R13_SHIFT 4u
5186 #define LMEM_PCCRMR_R13_WIDTH 2u
5187 #define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R13_SHIFT))&LMEM_PCCRMR_R13_MASK)
5188 #define LMEM_PCCRMR_R12_MASK 0xC0u
5189 #define LMEM_PCCRMR_R12_SHIFT 6u
5190 #define LMEM_PCCRMR_R12_WIDTH 2u
5191 #define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R12_SHIFT))&LMEM_PCCRMR_R12_MASK)
5192 #define LMEM_PCCRMR_R11_MASK 0x300u
5193 #define LMEM_PCCRMR_R11_SHIFT 8u
5194 #define LMEM_PCCRMR_R11_WIDTH 2u
5195 #define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R11_SHIFT))&LMEM_PCCRMR_R11_MASK)
5196 #define LMEM_PCCRMR_R10_MASK 0xC00u
5197 #define LMEM_PCCRMR_R10_SHIFT 10u
5198 #define LMEM_PCCRMR_R10_WIDTH 2u
5199 #define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R10_SHIFT))&LMEM_PCCRMR_R10_MASK)
5200 #define LMEM_PCCRMR_R9_MASK 0x3000u
5201 #define LMEM_PCCRMR_R9_SHIFT 12u
5202 #define LMEM_PCCRMR_R9_WIDTH 2u
5203 #define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R9_SHIFT))&LMEM_PCCRMR_R9_MASK)
5204 #define LMEM_PCCRMR_R8_MASK 0xC000u
5205 #define LMEM_PCCRMR_R8_SHIFT 14u
5206 #define LMEM_PCCRMR_R8_WIDTH 2u
5207 #define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R8_SHIFT))&LMEM_PCCRMR_R8_MASK)
5208 #define LMEM_PCCRMR_R7_MASK 0x30000u
5209 #define LMEM_PCCRMR_R7_SHIFT 16u
5210 #define LMEM_PCCRMR_R7_WIDTH 2u
5211 #define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R7_SHIFT))&LMEM_PCCRMR_R7_MASK)
5212 #define LMEM_PCCRMR_R6_MASK 0xC0000u
5213 #define LMEM_PCCRMR_R6_SHIFT 18u
5214 #define LMEM_PCCRMR_R6_WIDTH 2u
5215 #define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R6_SHIFT))&LMEM_PCCRMR_R6_MASK)
5216 #define LMEM_PCCRMR_R5_MASK 0x300000u
5217 #define LMEM_PCCRMR_R5_SHIFT 20u
5218 #define LMEM_PCCRMR_R5_WIDTH 2u
5219 #define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R5_SHIFT))&LMEM_PCCRMR_R5_MASK)
5220 #define LMEM_PCCRMR_R4_MASK 0xC00000u
5221 #define LMEM_PCCRMR_R4_SHIFT 22u
5222 #define LMEM_PCCRMR_R4_WIDTH 2u
5223 #define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R4_SHIFT))&LMEM_PCCRMR_R4_MASK)
5224 #define LMEM_PCCRMR_R3_MASK 0x3000000u
5225 #define LMEM_PCCRMR_R3_SHIFT 24u
5226 #define LMEM_PCCRMR_R3_WIDTH 2u
5227 #define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R3_SHIFT))&LMEM_PCCRMR_R3_MASK)
5228 #define LMEM_PCCRMR_R2_MASK 0xC000000u
5229 #define LMEM_PCCRMR_R2_SHIFT 26u
5230 #define LMEM_PCCRMR_R2_WIDTH 2u
5231 #define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R2_SHIFT))&LMEM_PCCRMR_R2_MASK)
5232 #define LMEM_PCCRMR_R1_MASK 0x30000000u
5233 #define LMEM_PCCRMR_R1_SHIFT 28u
5234 #define LMEM_PCCRMR_R1_WIDTH 2u
5235 #define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R1_SHIFT))&LMEM_PCCRMR_R1_MASK)
5236 #define LMEM_PCCRMR_R0_MASK 0xC0000000u
5237 #define LMEM_PCCRMR_R0_SHIFT 30u
5238 #define LMEM_PCCRMR_R0_WIDTH 2u
5239 #define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x))<<LMEM_PCCRMR_R0_SHIFT))&LMEM_PCCRMR_R0_MASK)
5240  /* end of group LMEM_Register_Masks */
5244 
5245  /* end of group LMEM_Peripheral_Access_Layer */
5249 
5250 
5251 /* ----------------------------------------------------------------------------
5252  -- LPI2C Peripheral Access Layer
5253  ---------------------------------------------------------------------------- */
5254 
5264 typedef struct {
5265  __I uint32_t VERID;
5266  __I uint32_t PARAM;
5267  uint8_t RESERVED_0[8];
5268  __IO uint32_t MCR;
5269  __IO uint32_t MSR;
5270  __IO uint32_t MIER;
5271  __IO uint32_t MDER;
5272  __IO uint32_t MCFGR0;
5273  __IO uint32_t MCFGR1;
5274  __IO uint32_t MCFGR2;
5275  __IO uint32_t MCFGR3;
5276  uint8_t RESERVED_1[16];
5277  __IO uint32_t MDMR;
5278  uint8_t RESERVED_2[4];
5279  __IO uint32_t MCCR0;
5280  uint8_t RESERVED_3[4];
5281  __IO uint32_t MCCR1;
5282  uint8_t RESERVED_4[4];
5283  __IO uint32_t MFCR;
5284  __I uint32_t MFSR;
5285  __IO uint32_t MTDR;
5286  uint8_t RESERVED_5[12];
5287  __I uint32_t MRDR;
5288  uint8_t RESERVED_6[156];
5289  __IO uint32_t SCR;
5290  __IO uint32_t SSR;
5291  __IO uint32_t SIER;
5292  __IO uint32_t SDER;
5293  uint8_t RESERVED_7[4];
5294  __IO uint32_t SCFGR1;
5295  __IO uint32_t SCFGR2;
5296  uint8_t RESERVED_8[20];
5297  __IO uint32_t SAMR;
5298  uint8_t RESERVED_9[12];
5299  __I uint32_t SASR;
5300  __IO uint32_t STAR;
5301  uint8_t RESERVED_10[8];
5302  __IO uint32_t STDR;
5303  uint8_t RESERVED_11[12];
5304  __I uint32_t SRDR;
5306 
5308 #define LPI2C_INSTANCE_COUNT (1u)
5309 
5310 
5311 /* LPI2C - Peripheral instance base addresses */
5313 #define LPI2C0_BASE (0x40066000u)
5314 
5315 #define LPI2C0 ((LPI2C_Type *)LPI2C0_BASE)
5316 
5317 #define LPI2C_BASE_ADDRS { LPI2C0_BASE }
5318 
5319 #define LPI2C_BASE_PTRS { LPI2C0 }
5320 
5321 #define LPI2C_IRQS_ARR_COUNT (2u)
5322 
5323 #define LPI2C_MASTER_IRQS_CH_COUNT (1u)
5324 
5325 #define LPI2C_SLAVE_IRQS_CH_COUNT (1u)
5326 
5327 #define LPI2C_MASTER_IRQS { LPI2C0_Master_IRQn }
5328 #define LPI2C_SLAVE_IRQS { LPI2C0_Slave_IRQn }
5329 
5330 /* ----------------------------------------------------------------------------
5331  -- LPI2C Register Masks
5332  ---------------------------------------------------------------------------- */
5333 
5339 /* VERID Bit Fields */
5340 #define LPI2C_VERID_FEATURE_MASK 0xFFFFu
5341 #define LPI2C_VERID_FEATURE_SHIFT 0u
5342 #define LPI2C_VERID_FEATURE_WIDTH 16u
5343 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_FEATURE_SHIFT))&LPI2C_VERID_FEATURE_MASK)
5344 #define LPI2C_VERID_MINOR_MASK 0xFF0000u
5345 #define LPI2C_VERID_MINOR_SHIFT 16u
5346 #define LPI2C_VERID_MINOR_WIDTH 8u
5347 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MINOR_SHIFT))&LPI2C_VERID_MINOR_MASK)
5348 #define LPI2C_VERID_MAJOR_MASK 0xFF000000u
5349 #define LPI2C_VERID_MAJOR_SHIFT 24u
5350 #define LPI2C_VERID_MAJOR_WIDTH 8u
5351 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_VERID_MAJOR_SHIFT))&LPI2C_VERID_MAJOR_MASK)
5352 /* PARAM Bit Fields */
5353 #define LPI2C_PARAM_MTXFIFO_MASK 0xFu
5354 #define LPI2C_PARAM_MTXFIFO_SHIFT 0u
5355 #define LPI2C_PARAM_MTXFIFO_WIDTH 4u
5356 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MTXFIFO_SHIFT))&LPI2C_PARAM_MTXFIFO_MASK)
5357 #define LPI2C_PARAM_MRXFIFO_MASK 0xF00u
5358 #define LPI2C_PARAM_MRXFIFO_SHIFT 8u
5359 #define LPI2C_PARAM_MRXFIFO_WIDTH 4u
5360 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_PARAM_MRXFIFO_SHIFT))&LPI2C_PARAM_MRXFIFO_MASK)
5361 /* MCR Bit Fields */
5362 #define LPI2C_MCR_MEN_MASK 0x1u
5363 #define LPI2C_MCR_MEN_SHIFT 0u
5364 #define LPI2C_MCR_MEN_WIDTH 1u
5365 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_MEN_SHIFT))&LPI2C_MCR_MEN_MASK)
5366 #define LPI2C_MCR_RST_MASK 0x2u
5367 #define LPI2C_MCR_RST_SHIFT 1u
5368 #define LPI2C_MCR_RST_WIDTH 1u
5369 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RST_SHIFT))&LPI2C_MCR_RST_MASK)
5370 #define LPI2C_MCR_DOZEN_MASK 0x4u
5371 #define LPI2C_MCR_DOZEN_SHIFT 2u
5372 #define LPI2C_MCR_DOZEN_WIDTH 1u
5373 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DOZEN_SHIFT))&LPI2C_MCR_DOZEN_MASK)
5374 #define LPI2C_MCR_DBGEN_MASK 0x8u
5375 #define LPI2C_MCR_DBGEN_SHIFT 3u
5376 #define LPI2C_MCR_DBGEN_WIDTH 1u
5377 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_DBGEN_SHIFT))&LPI2C_MCR_DBGEN_MASK)
5378 #define LPI2C_MCR_RTF_MASK 0x100u
5379 #define LPI2C_MCR_RTF_SHIFT 8u
5380 #define LPI2C_MCR_RTF_WIDTH 1u
5381 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RTF_SHIFT))&LPI2C_MCR_RTF_MASK)
5382 #define LPI2C_MCR_RRF_MASK 0x200u
5383 #define LPI2C_MCR_RRF_SHIFT 9u
5384 #define LPI2C_MCR_RRF_WIDTH 1u
5385 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCR_RRF_SHIFT))&LPI2C_MCR_RRF_MASK)
5386 /* MSR Bit Fields */
5387 #define LPI2C_MSR_TDF_MASK 0x1u
5388 #define LPI2C_MSR_TDF_SHIFT 0u
5389 #define LPI2C_MSR_TDF_WIDTH 1u
5390 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_TDF_SHIFT))&LPI2C_MSR_TDF_MASK)
5391 #define LPI2C_MSR_RDF_MASK 0x2u
5392 #define LPI2C_MSR_RDF_SHIFT 1u
5393 #define LPI2C_MSR_RDF_WIDTH 1u
5394 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_RDF_SHIFT))&LPI2C_MSR_RDF_MASK)
5395 #define LPI2C_MSR_EPF_MASK 0x100u
5396 #define LPI2C_MSR_EPF_SHIFT 8u
5397 #define LPI2C_MSR_EPF_WIDTH 1u
5398 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_EPF_SHIFT))&LPI2C_MSR_EPF_MASK)
5399 #define LPI2C_MSR_SDF_MASK 0x200u
5400 #define LPI2C_MSR_SDF_SHIFT 9u
5401 #define LPI2C_MSR_SDF_WIDTH 1u
5402 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_SDF_SHIFT))&LPI2C_MSR_SDF_MASK)
5403 #define LPI2C_MSR_NDF_MASK 0x400u
5404 #define LPI2C_MSR_NDF_SHIFT 10u
5405 #define LPI2C_MSR_NDF_WIDTH 1u
5406 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_NDF_SHIFT))&LPI2C_MSR_NDF_MASK)
5407 #define LPI2C_MSR_ALF_MASK 0x800u
5408 #define LPI2C_MSR_ALF_SHIFT 11u
5409 #define LPI2C_MSR_ALF_WIDTH 1u
5410 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_ALF_SHIFT))&LPI2C_MSR_ALF_MASK)
5411 #define LPI2C_MSR_FEF_MASK 0x1000u
5412 #define LPI2C_MSR_FEF_SHIFT 12u
5413 #define LPI2C_MSR_FEF_WIDTH 1u
5414 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_FEF_SHIFT))&LPI2C_MSR_FEF_MASK)
5415 #define LPI2C_MSR_PLTF_MASK 0x2000u
5416 #define LPI2C_MSR_PLTF_SHIFT 13u
5417 #define LPI2C_MSR_PLTF_WIDTH 1u
5418 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_PLTF_SHIFT))&LPI2C_MSR_PLTF_MASK)
5419 #define LPI2C_MSR_DMF_MASK 0x4000u
5420 #define LPI2C_MSR_DMF_SHIFT 14u
5421 #define LPI2C_MSR_DMF_WIDTH 1u
5422 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_DMF_SHIFT))&LPI2C_MSR_DMF_MASK)
5423 #define LPI2C_MSR_MBF_MASK 0x1000000u
5424 #define LPI2C_MSR_MBF_SHIFT 24u
5425 #define LPI2C_MSR_MBF_WIDTH 1u
5426 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_MBF_SHIFT))&LPI2C_MSR_MBF_MASK)
5427 #define LPI2C_MSR_BBF_MASK 0x2000000u
5428 #define LPI2C_MSR_BBF_SHIFT 25u
5429 #define LPI2C_MSR_BBF_WIDTH 1u
5430 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MSR_BBF_SHIFT))&LPI2C_MSR_BBF_MASK)
5431 /* MIER Bit Fields */
5432 #define LPI2C_MIER_TDIE_MASK 0x1u
5433 #define LPI2C_MIER_TDIE_SHIFT 0u
5434 #define LPI2C_MIER_TDIE_WIDTH 1u
5435 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_TDIE_SHIFT))&LPI2C_MIER_TDIE_MASK)
5436 #define LPI2C_MIER_RDIE_MASK 0x2u
5437 #define LPI2C_MIER_RDIE_SHIFT 1u
5438 #define LPI2C_MIER_RDIE_WIDTH 1u
5439 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_RDIE_SHIFT))&LPI2C_MIER_RDIE_MASK)
5440 #define LPI2C_MIER_EPIE_MASK 0x100u
5441 #define LPI2C_MIER_EPIE_SHIFT 8u
5442 #define LPI2C_MIER_EPIE_WIDTH 1u
5443 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_EPIE_SHIFT))&LPI2C_MIER_EPIE_MASK)
5444 #define LPI2C_MIER_SDIE_MASK 0x200u
5445 #define LPI2C_MIER_SDIE_SHIFT 9u
5446 #define LPI2C_MIER_SDIE_WIDTH 1u
5447 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_SDIE_SHIFT))&LPI2C_MIER_SDIE_MASK)
5448 #define LPI2C_MIER_NDIE_MASK 0x400u
5449 #define LPI2C_MIER_NDIE_SHIFT 10u
5450 #define LPI2C_MIER_NDIE_WIDTH 1u
5451 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_NDIE_SHIFT))&LPI2C_MIER_NDIE_MASK)
5452 #define LPI2C_MIER_ALIE_MASK 0x800u
5453 #define LPI2C_MIER_ALIE_SHIFT 11u
5454 #define LPI2C_MIER_ALIE_WIDTH 1u
5455 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_ALIE_SHIFT))&LPI2C_MIER_ALIE_MASK)
5456 #define LPI2C_MIER_FEIE_MASK 0x1000u
5457 #define LPI2C_MIER_FEIE_SHIFT 12u
5458 #define LPI2C_MIER_FEIE_WIDTH 1u
5459 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_FEIE_SHIFT))&LPI2C_MIER_FEIE_MASK)
5460 #define LPI2C_MIER_PLTIE_MASK 0x2000u
5461 #define LPI2C_MIER_PLTIE_SHIFT 13u
5462 #define LPI2C_MIER_PLTIE_WIDTH 1u
5463 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_PLTIE_SHIFT))&LPI2C_MIER_PLTIE_MASK)
5464 #define LPI2C_MIER_DMIE_MASK 0x4000u
5465 #define LPI2C_MIER_DMIE_SHIFT 14u
5466 #define LPI2C_MIER_DMIE_WIDTH 1u
5467 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MIER_DMIE_SHIFT))&LPI2C_MIER_DMIE_MASK)
5468 /* MDER Bit Fields */
5469 #define LPI2C_MDER_TDDE_MASK 0x1u
5470 #define LPI2C_MDER_TDDE_SHIFT 0u
5471 #define LPI2C_MDER_TDDE_WIDTH 1u
5472 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_TDDE_SHIFT))&LPI2C_MDER_TDDE_MASK)
5473 #define LPI2C_MDER_RDDE_MASK 0x2u
5474 #define LPI2C_MDER_RDDE_SHIFT 1u
5475 #define LPI2C_MDER_RDDE_WIDTH 1u
5476 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDER_RDDE_SHIFT))&LPI2C_MDER_RDDE_MASK)
5477 /* MCFGR0 Bit Fields */
5478 #define LPI2C_MCFGR0_HREN_MASK 0x1u
5479 #define LPI2C_MCFGR0_HREN_SHIFT 0u
5480 #define LPI2C_MCFGR0_HREN_WIDTH 1u
5481 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HREN_SHIFT))&LPI2C_MCFGR0_HREN_MASK)
5482 #define LPI2C_MCFGR0_HRPOL_MASK 0x2u
5483 #define LPI2C_MCFGR0_HRPOL_SHIFT 1u
5484 #define LPI2C_MCFGR0_HRPOL_WIDTH 1u
5485 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRPOL_SHIFT))&LPI2C_MCFGR0_HRPOL_MASK)
5486 #define LPI2C_MCFGR0_HRSEL_MASK 0x4u
5487 #define LPI2C_MCFGR0_HRSEL_SHIFT 2u
5488 #define LPI2C_MCFGR0_HRSEL_WIDTH 1u
5489 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_HRSEL_SHIFT))&LPI2C_MCFGR0_HRSEL_MASK)
5490 #define LPI2C_MCFGR0_CIRFIFO_MASK 0x100u
5491 #define LPI2C_MCFGR0_CIRFIFO_SHIFT 8u
5492 #define LPI2C_MCFGR0_CIRFIFO_WIDTH 1u
5493 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_CIRFIFO_SHIFT))&LPI2C_MCFGR0_CIRFIFO_MASK)
5494 #define LPI2C_MCFGR0_RDMO_MASK 0x200u
5495 #define LPI2C_MCFGR0_RDMO_SHIFT 9u
5496 #define LPI2C_MCFGR0_RDMO_WIDTH 1u
5497 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR0_RDMO_SHIFT))&LPI2C_MCFGR0_RDMO_MASK)
5498 /* MCFGR1 Bit Fields */
5499 #define LPI2C_MCFGR1_PRESCALE_MASK 0x7u
5500 #define LPI2C_MCFGR1_PRESCALE_SHIFT 0u
5501 #define LPI2C_MCFGR1_PRESCALE_WIDTH 3u
5502 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PRESCALE_SHIFT))&LPI2C_MCFGR1_PRESCALE_MASK)
5503 #define LPI2C_MCFGR1_AUTOSTOP_MASK 0x100u
5504 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT 8u
5505 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH 1u
5506 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_AUTOSTOP_SHIFT))&LPI2C_MCFGR1_AUTOSTOP_MASK)
5507 #define LPI2C_MCFGR1_IGNACK_MASK 0x200u
5508 #define LPI2C_MCFGR1_IGNACK_SHIFT 9u
5509 #define LPI2C_MCFGR1_IGNACK_WIDTH 1u
5510 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_IGNACK_SHIFT))&LPI2C_MCFGR1_IGNACK_MASK)
5511 #define LPI2C_MCFGR1_TIMECFG_MASK 0x400u
5512 #define LPI2C_MCFGR1_TIMECFG_SHIFT 10u
5513 #define LPI2C_MCFGR1_TIMECFG_WIDTH 1u
5514 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_TIMECFG_SHIFT))&LPI2C_MCFGR1_TIMECFG_MASK)
5515 #define LPI2C_MCFGR1_MATCFG_MASK 0x70000u
5516 #define LPI2C_MCFGR1_MATCFG_SHIFT 16u
5517 #define LPI2C_MCFGR1_MATCFG_WIDTH 3u
5518 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_MATCFG_SHIFT))&LPI2C_MCFGR1_MATCFG_MASK)
5519 #define LPI2C_MCFGR1_PINCFG_MASK 0x7000000u
5520 #define LPI2C_MCFGR1_PINCFG_SHIFT 24u
5521 #define LPI2C_MCFGR1_PINCFG_WIDTH 3u
5522 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR1_PINCFG_SHIFT))&LPI2C_MCFGR1_PINCFG_MASK)
5523 /* MCFGR2 Bit Fields */
5524 #define LPI2C_MCFGR2_BUSIDLE_MASK 0xFFFu
5525 #define LPI2C_MCFGR2_BUSIDLE_SHIFT 0u
5526 #define LPI2C_MCFGR2_BUSIDLE_WIDTH 12u
5527 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_BUSIDLE_SHIFT))&LPI2C_MCFGR2_BUSIDLE_MASK)
5528 #define LPI2C_MCFGR2_FILTSCL_MASK 0xF0000u
5529 #define LPI2C_MCFGR2_FILTSCL_SHIFT 16u
5530 #define LPI2C_MCFGR2_FILTSCL_WIDTH 4u
5531 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSCL_SHIFT))&LPI2C_MCFGR2_FILTSCL_MASK)
5532 #define LPI2C_MCFGR2_FILTSDA_MASK 0xF000000u
5533 #define LPI2C_MCFGR2_FILTSDA_SHIFT 24u
5534 #define LPI2C_MCFGR2_FILTSDA_WIDTH 4u
5535 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR2_FILTSDA_SHIFT))&LPI2C_MCFGR2_FILTSDA_MASK)
5536 /* MCFGR3 Bit Fields */
5537 #define LPI2C_MCFGR3_PINLOW_MASK 0xFFF00u
5538 #define LPI2C_MCFGR3_PINLOW_SHIFT 8u
5539 #define LPI2C_MCFGR3_PINLOW_WIDTH 12u
5540 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCFGR3_PINLOW_SHIFT))&LPI2C_MCFGR3_PINLOW_MASK)
5541 /* MDMR Bit Fields */
5542 #define LPI2C_MDMR_MATCH0_MASK 0xFFu
5543 #define LPI2C_MDMR_MATCH0_SHIFT 0u
5544 #define LPI2C_MDMR_MATCH0_WIDTH 8u
5545 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH0_SHIFT))&LPI2C_MDMR_MATCH0_MASK)
5546 #define LPI2C_MDMR_MATCH1_MASK 0xFF0000u
5547 #define LPI2C_MDMR_MATCH1_SHIFT 16u
5548 #define LPI2C_MDMR_MATCH1_WIDTH 8u
5549 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MDMR_MATCH1_SHIFT))&LPI2C_MDMR_MATCH1_MASK)
5550 /* MCCR0 Bit Fields */
5551 #define LPI2C_MCCR0_CLKLO_MASK 0x3Fu
5552 #define LPI2C_MCCR0_CLKLO_SHIFT 0u
5553 #define LPI2C_MCCR0_CLKLO_WIDTH 6u
5554 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKLO_SHIFT))&LPI2C_MCCR0_CLKLO_MASK)
5555 #define LPI2C_MCCR0_CLKHI_MASK 0x3F00u
5556 #define LPI2C_MCCR0_CLKHI_SHIFT 8u
5557 #define LPI2C_MCCR0_CLKHI_WIDTH 6u
5558 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_CLKHI_SHIFT))&LPI2C_MCCR0_CLKHI_MASK)
5559 #define LPI2C_MCCR0_SETHOLD_MASK 0x3F0000u
5560 #define LPI2C_MCCR0_SETHOLD_SHIFT 16u
5561 #define LPI2C_MCCR0_SETHOLD_WIDTH 6u
5562 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_SETHOLD_SHIFT))&LPI2C_MCCR0_SETHOLD_MASK)
5563 #define LPI2C_MCCR0_DATAVD_MASK 0x3F000000u
5564 #define LPI2C_MCCR0_DATAVD_SHIFT 24u
5565 #define LPI2C_MCCR0_DATAVD_WIDTH 6u
5566 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR0_DATAVD_SHIFT))&LPI2C_MCCR0_DATAVD_MASK)
5567 /* MCCR1 Bit Fields */
5568 #define LPI2C_MCCR1_CLKLO_MASK 0x3Fu
5569 #define LPI2C_MCCR1_CLKLO_SHIFT 0u
5570 #define LPI2C_MCCR1_CLKLO_WIDTH 6u
5571 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKLO_SHIFT))&LPI2C_MCCR1_CLKLO_MASK)
5572 #define LPI2C_MCCR1_CLKHI_MASK 0x3F00u
5573 #define LPI2C_MCCR1_CLKHI_SHIFT 8u
5574 #define LPI2C_MCCR1_CLKHI_WIDTH 6u
5575 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_CLKHI_SHIFT))&LPI2C_MCCR1_CLKHI_MASK)
5576 #define LPI2C_MCCR1_SETHOLD_MASK 0x3F0000u
5577 #define LPI2C_MCCR1_SETHOLD_SHIFT 16u
5578 #define LPI2C_MCCR1_SETHOLD_WIDTH 6u
5579 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_SETHOLD_SHIFT))&LPI2C_MCCR1_SETHOLD_MASK)
5580 #define LPI2C_MCCR1_DATAVD_MASK 0x3F000000u
5581 #define LPI2C_MCCR1_DATAVD_SHIFT 24u
5582 #define LPI2C_MCCR1_DATAVD_WIDTH 6u
5583 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MCCR1_DATAVD_SHIFT))&LPI2C_MCCR1_DATAVD_MASK)
5584 /* MFCR Bit Fields */
5585 #define LPI2C_MFCR_TXWATER_MASK 0x3u
5586 #define LPI2C_MFCR_TXWATER_SHIFT 0u
5587 #define LPI2C_MFCR_TXWATER_WIDTH 2u
5588 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_TXWATER_SHIFT))&LPI2C_MFCR_TXWATER_MASK)
5589 #define LPI2C_MFCR_RXWATER_MASK 0x30000u
5590 #define LPI2C_MFCR_RXWATER_SHIFT 16u
5591 #define LPI2C_MFCR_RXWATER_WIDTH 2u
5592 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFCR_RXWATER_SHIFT))&LPI2C_MFCR_RXWATER_MASK)
5593 /* MFSR Bit Fields */
5594 #define LPI2C_MFSR_TXCOUNT_MASK 0x7u
5595 #define LPI2C_MFSR_TXCOUNT_SHIFT 0u
5596 #define LPI2C_MFSR_TXCOUNT_WIDTH 3u
5597 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_TXCOUNT_SHIFT))&LPI2C_MFSR_TXCOUNT_MASK)
5598 #define LPI2C_MFSR_RXCOUNT_MASK 0x70000u
5599 #define LPI2C_MFSR_RXCOUNT_SHIFT 16u
5600 #define LPI2C_MFSR_RXCOUNT_WIDTH 3u
5601 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MFSR_RXCOUNT_SHIFT))&LPI2C_MFSR_RXCOUNT_MASK)
5602 /* MTDR Bit Fields */
5603 #define LPI2C_MTDR_DATA_MASK 0xFFu
5604 #define LPI2C_MTDR_DATA_SHIFT 0u
5605 #define LPI2C_MTDR_DATA_WIDTH 8u
5606 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_DATA_SHIFT))&LPI2C_MTDR_DATA_MASK)
5607 #define LPI2C_MTDR_CMD_MASK 0x700u
5608 #define LPI2C_MTDR_CMD_SHIFT 8u
5609 #define LPI2C_MTDR_CMD_WIDTH 3u
5610 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MTDR_CMD_SHIFT))&LPI2C_MTDR_CMD_MASK)
5611 /* MRDR Bit Fields */
5612 #define LPI2C_MRDR_DATA_MASK 0xFFu
5613 #define LPI2C_MRDR_DATA_SHIFT 0u
5614 #define LPI2C_MRDR_DATA_WIDTH 8u
5615 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_DATA_SHIFT))&LPI2C_MRDR_DATA_MASK)
5616 #define LPI2C_MRDR_RXEMPTY_MASK 0x4000u
5617 #define LPI2C_MRDR_RXEMPTY_SHIFT 14u
5618 #define LPI2C_MRDR_RXEMPTY_WIDTH 1u
5619 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_MRDR_RXEMPTY_SHIFT))&LPI2C_MRDR_RXEMPTY_MASK)
5620 /* SCR Bit Fields */
5621 #define LPI2C_SCR_SEN_MASK 0x1u
5622 #define LPI2C_SCR_SEN_SHIFT 0u
5623 #define LPI2C_SCR_SEN_WIDTH 1u
5624 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_SEN_SHIFT))&LPI2C_SCR_SEN_MASK)
5625 #define LPI2C_SCR_RST_MASK 0x2u
5626 #define LPI2C_SCR_RST_SHIFT 1u
5627 #define LPI2C_SCR_RST_WIDTH 1u
5628 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_RST_SHIFT))&LPI2C_SCR_RST_MASK)
5629 #define LPI2C_SCR_FILTEN_MASK 0x10u
5630 #define LPI2C_SCR_FILTEN_SHIFT 4u
5631 #define LPI2C_SCR_FILTEN_WIDTH 1u
5632 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTEN_SHIFT))&LPI2C_SCR_FILTEN_MASK)
5633 #define LPI2C_SCR_FILTDZ_MASK 0x20u
5634 #define LPI2C_SCR_FILTDZ_SHIFT 5u
5635 #define LPI2C_SCR_FILTDZ_WIDTH 1u
5636 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCR_FILTDZ_SHIFT))&LPI2C_SCR_FILTDZ_MASK)
5637 /* SSR Bit Fields */
5638 #define LPI2C_SSR_TDF_MASK 0x1u
5639 #define LPI2C_SSR_TDF_SHIFT 0u
5640 #define LPI2C_SSR_TDF_WIDTH 1u
5641 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TDF_SHIFT))&LPI2C_SSR_TDF_MASK)
5642 #define LPI2C_SSR_RDF_MASK 0x2u
5643 #define LPI2C_SSR_RDF_SHIFT 1u
5644 #define LPI2C_SSR_RDF_WIDTH 1u
5645 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RDF_SHIFT))&LPI2C_SSR_RDF_MASK)
5646 #define LPI2C_SSR_AVF_MASK 0x4u
5647 #define LPI2C_SSR_AVF_SHIFT 2u
5648 #define LPI2C_SSR_AVF_WIDTH 1u
5649 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AVF_SHIFT))&LPI2C_SSR_AVF_MASK)
5650 #define LPI2C_SSR_TAF_MASK 0x8u
5651 #define LPI2C_SSR_TAF_SHIFT 3u
5652 #define LPI2C_SSR_TAF_WIDTH 1u
5653 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_TAF_SHIFT))&LPI2C_SSR_TAF_MASK)
5654 #define LPI2C_SSR_RSF_MASK 0x100u
5655 #define LPI2C_SSR_RSF_SHIFT 8u
5656 #define LPI2C_SSR_RSF_WIDTH 1u
5657 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_RSF_SHIFT))&LPI2C_SSR_RSF_MASK)
5658 #define LPI2C_SSR_SDF_MASK 0x200u
5659 #define LPI2C_SSR_SDF_SHIFT 9u
5660 #define LPI2C_SSR_SDF_WIDTH 1u
5661 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SDF_SHIFT))&LPI2C_SSR_SDF_MASK)
5662 #define LPI2C_SSR_BEF_MASK 0x400u
5663 #define LPI2C_SSR_BEF_SHIFT 10u
5664 #define LPI2C_SSR_BEF_WIDTH 1u
5665 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BEF_SHIFT))&LPI2C_SSR_BEF_MASK)
5666 #define LPI2C_SSR_FEF_MASK 0x800u
5667 #define LPI2C_SSR_FEF_SHIFT 11u
5668 #define LPI2C_SSR_FEF_WIDTH 1u
5669 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_FEF_SHIFT))&LPI2C_SSR_FEF_MASK)
5670 #define LPI2C_SSR_AM0F_MASK 0x1000u
5671 #define LPI2C_SSR_AM0F_SHIFT 12u
5672 #define LPI2C_SSR_AM0F_WIDTH 1u
5673 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM0F_SHIFT))&LPI2C_SSR_AM0F_MASK)
5674 #define LPI2C_SSR_AM1F_MASK 0x2000u
5675 #define LPI2C_SSR_AM1F_SHIFT 13u
5676 #define LPI2C_SSR_AM1F_WIDTH 1u
5677 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_AM1F_SHIFT))&LPI2C_SSR_AM1F_MASK)
5678 #define LPI2C_SSR_GCF_MASK 0x4000u
5679 #define LPI2C_SSR_GCF_SHIFT 14u
5680 #define LPI2C_SSR_GCF_WIDTH 1u
5681 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_GCF_SHIFT))&LPI2C_SSR_GCF_MASK)
5682 #define LPI2C_SSR_SARF_MASK 0x8000u
5683 #define LPI2C_SSR_SARF_SHIFT 15u
5684 #define LPI2C_SSR_SARF_WIDTH 1u
5685 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SARF_SHIFT))&LPI2C_SSR_SARF_MASK)
5686 #define LPI2C_SSR_SBF_MASK 0x1000000u
5687 #define LPI2C_SSR_SBF_SHIFT 24u
5688 #define LPI2C_SSR_SBF_WIDTH 1u
5689 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_SBF_SHIFT))&LPI2C_SSR_SBF_MASK)
5690 #define LPI2C_SSR_BBF_MASK 0x2000000u
5691 #define LPI2C_SSR_BBF_SHIFT 25u
5692 #define LPI2C_SSR_BBF_WIDTH 1u
5693 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SSR_BBF_SHIFT))&LPI2C_SSR_BBF_MASK)
5694 /* SIER Bit Fields */
5695 #define LPI2C_SIER_TDIE_MASK 0x1u
5696 #define LPI2C_SIER_TDIE_SHIFT 0u
5697 #define LPI2C_SIER_TDIE_WIDTH 1u
5698 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TDIE_SHIFT))&LPI2C_SIER_TDIE_MASK)
5699 #define LPI2C_SIER_RDIE_MASK 0x2u
5700 #define LPI2C_SIER_RDIE_SHIFT 1u
5701 #define LPI2C_SIER_RDIE_WIDTH 1u
5702 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RDIE_SHIFT))&LPI2C_SIER_RDIE_MASK)
5703 #define LPI2C_SIER_AVIE_MASK 0x4u
5704 #define LPI2C_SIER_AVIE_SHIFT 2u
5705 #define LPI2C_SIER_AVIE_WIDTH 1u
5706 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AVIE_SHIFT))&LPI2C_SIER_AVIE_MASK)
5707 #define LPI2C_SIER_TAIE_MASK 0x8u
5708 #define LPI2C_SIER_TAIE_SHIFT 3u
5709 #define LPI2C_SIER_TAIE_WIDTH 1u
5710 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_TAIE_SHIFT))&LPI2C_SIER_TAIE_MASK)
5711 #define LPI2C_SIER_RSIE_MASK 0x100u
5712 #define LPI2C_SIER_RSIE_SHIFT 8u
5713 #define LPI2C_SIER_RSIE_WIDTH 1u
5714 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_RSIE_SHIFT))&LPI2C_SIER_RSIE_MASK)
5715 #define LPI2C_SIER_SDIE_MASK 0x200u
5716 #define LPI2C_SIER_SDIE_SHIFT 9u
5717 #define LPI2C_SIER_SDIE_WIDTH 1u
5718 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SDIE_SHIFT))&LPI2C_SIER_SDIE_MASK)
5719 #define LPI2C_SIER_BEIE_MASK 0x400u
5720 #define LPI2C_SIER_BEIE_SHIFT 10u
5721 #define LPI2C_SIER_BEIE_WIDTH 1u
5722 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_BEIE_SHIFT))&LPI2C_SIER_BEIE_MASK)
5723 #define LPI2C_SIER_FEIE_MASK 0x800u
5724 #define LPI2C_SIER_FEIE_SHIFT 11u
5725 #define LPI2C_SIER_FEIE_WIDTH 1u
5726 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_FEIE_SHIFT))&LPI2C_SIER_FEIE_MASK)
5727 #define LPI2C_SIER_AM0IE_MASK 0x1000u
5728 #define LPI2C_SIER_AM0IE_SHIFT 12u
5729 #define LPI2C_SIER_AM0IE_WIDTH 1u
5730 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM0IE_SHIFT))&LPI2C_SIER_AM0IE_MASK)
5731 #define LPI2C_SIER_AM1F_MASK 0x2000u
5732 #define LPI2C_SIER_AM1F_SHIFT 13u
5733 #define LPI2C_SIER_AM1F_WIDTH 1u
5734 #define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_AM1F_SHIFT))&LPI2C_SIER_AM1F_MASK)
5735 #define LPI2C_SIER_GCIE_MASK 0x4000u
5736 #define LPI2C_SIER_GCIE_SHIFT 14u
5737 #define LPI2C_SIER_GCIE_WIDTH 1u
5738 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_GCIE_SHIFT))&LPI2C_SIER_GCIE_MASK)
5739 #define LPI2C_SIER_SARIE_MASK 0x8000u
5740 #define LPI2C_SIER_SARIE_SHIFT 15u
5741 #define LPI2C_SIER_SARIE_WIDTH 1u
5742 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SIER_SARIE_SHIFT))&LPI2C_SIER_SARIE_MASK)
5743 /* SDER Bit Fields */
5744 #define LPI2C_SDER_TDDE_MASK 0x1u
5745 #define LPI2C_SDER_TDDE_SHIFT 0u
5746 #define LPI2C_SDER_TDDE_WIDTH 1u
5747 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_TDDE_SHIFT))&LPI2C_SDER_TDDE_MASK)
5748 #define LPI2C_SDER_RDDE_MASK 0x2u
5749 #define LPI2C_SDER_RDDE_SHIFT 1u
5750 #define LPI2C_SDER_RDDE_WIDTH 1u
5751 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_RDDE_SHIFT))&LPI2C_SDER_RDDE_MASK)
5752 #define LPI2C_SDER_AVDE_MASK 0x4u
5753 #define LPI2C_SDER_AVDE_SHIFT 2u
5754 #define LPI2C_SDER_AVDE_WIDTH 1u
5755 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SDER_AVDE_SHIFT))&LPI2C_SDER_AVDE_MASK)
5756 /* SCFGR1 Bit Fields */
5757 #define LPI2C_SCFGR1_ADRSTALL_MASK 0x1u
5758 #define LPI2C_SCFGR1_ADRSTALL_SHIFT 0u
5759 #define LPI2C_SCFGR1_ADRSTALL_WIDTH 1u
5760 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADRSTALL_SHIFT))&LPI2C_SCFGR1_ADRSTALL_MASK)
5761 #define LPI2C_SCFGR1_RXSTALL_MASK 0x2u
5762 #define LPI2C_SCFGR1_RXSTALL_SHIFT 1u
5763 #define LPI2C_SCFGR1_RXSTALL_WIDTH 1u
5764 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXSTALL_SHIFT))&LPI2C_SCFGR1_RXSTALL_MASK)
5765 #define LPI2C_SCFGR1_TXDSTALL_MASK 0x4u
5766 #define LPI2C_SCFGR1_TXDSTALL_SHIFT 2u
5767 #define LPI2C_SCFGR1_TXDSTALL_WIDTH 1u
5768 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXDSTALL_SHIFT))&LPI2C_SCFGR1_TXDSTALL_MASK)
5769 #define LPI2C_SCFGR1_ACKSTALL_MASK 0x8u
5770 #define LPI2C_SCFGR1_ACKSTALL_SHIFT 3u
5771 #define LPI2C_SCFGR1_ACKSTALL_WIDTH 1u
5772 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ACKSTALL_SHIFT))&LPI2C_SCFGR1_ACKSTALL_MASK)
5773 #define LPI2C_SCFGR1_GCEN_MASK 0x100u
5774 #define LPI2C_SCFGR1_GCEN_SHIFT 8u
5775 #define LPI2C_SCFGR1_GCEN_WIDTH 1u
5776 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_GCEN_SHIFT))&LPI2C_SCFGR1_GCEN_MASK)
5777 #define LPI2C_SCFGR1_SAEN_MASK 0x200u
5778 #define LPI2C_SCFGR1_SAEN_SHIFT 9u
5779 #define LPI2C_SCFGR1_SAEN_WIDTH 1u
5780 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_SAEN_SHIFT))&LPI2C_SCFGR1_SAEN_MASK)
5781 #define LPI2C_SCFGR1_TXCFG_MASK 0x400u
5782 #define LPI2C_SCFGR1_TXCFG_SHIFT 10u
5783 #define LPI2C_SCFGR1_TXCFG_WIDTH 1u
5784 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_TXCFG_SHIFT))&LPI2C_SCFGR1_TXCFG_MASK)
5785 #define LPI2C_SCFGR1_RXCFG_MASK 0x800u
5786 #define LPI2C_SCFGR1_RXCFG_SHIFT 11u
5787 #define LPI2C_SCFGR1_RXCFG_WIDTH 1u
5788 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_RXCFG_SHIFT))&LPI2C_SCFGR1_RXCFG_MASK)
5789 #define LPI2C_SCFGR1_IGNACK_MASK 0x1000u
5790 #define LPI2C_SCFGR1_IGNACK_SHIFT 12u
5791 #define LPI2C_SCFGR1_IGNACK_WIDTH 1u
5792 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_IGNACK_SHIFT))&LPI2C_SCFGR1_IGNACK_MASK)
5793 #define LPI2C_SCFGR1_HSMEN_MASK 0x2000u
5794 #define LPI2C_SCFGR1_HSMEN_SHIFT 13u
5795 #define LPI2C_SCFGR1_HSMEN_WIDTH 1u
5796 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_HSMEN_SHIFT))&LPI2C_SCFGR1_HSMEN_MASK)
5797 #define LPI2C_SCFGR1_ADDRCFG_MASK 0x70000u
5798 #define LPI2C_SCFGR1_ADDRCFG_SHIFT 16u
5799 #define LPI2C_SCFGR1_ADDRCFG_WIDTH 3u
5800 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR1_ADDRCFG_SHIFT))&LPI2C_SCFGR1_ADDRCFG_MASK)
5801 /* SCFGR2 Bit Fields */
5802 #define LPI2C_SCFGR2_CLKHOLD_MASK 0xFu
5803 #define LPI2C_SCFGR2_CLKHOLD_SHIFT 0u
5804 #define LPI2C_SCFGR2_CLKHOLD_WIDTH 4u
5805 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_CLKHOLD_SHIFT))&LPI2C_SCFGR2_CLKHOLD_MASK)
5806 #define LPI2C_SCFGR2_DATAVD_MASK 0x3F00u
5807 #define LPI2C_SCFGR2_DATAVD_SHIFT 8u
5808 #define LPI2C_SCFGR2_DATAVD_WIDTH 6u
5809 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_DATAVD_SHIFT))&LPI2C_SCFGR2_DATAVD_MASK)
5810 #define LPI2C_SCFGR2_FILTSCL_MASK 0xF0000u
5811 #define LPI2C_SCFGR2_FILTSCL_SHIFT 16u
5812 #define LPI2C_SCFGR2_FILTSCL_WIDTH 4u
5813 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSCL_SHIFT))&LPI2C_SCFGR2_FILTSCL_MASK)
5814 #define LPI2C_SCFGR2_FILTSDA_MASK 0xF000000u
5815 #define LPI2C_SCFGR2_FILTSDA_SHIFT 24u
5816 #define LPI2C_SCFGR2_FILTSDA_WIDTH 4u
5817 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SCFGR2_FILTSDA_SHIFT))&LPI2C_SCFGR2_FILTSDA_MASK)
5818 /* SAMR Bit Fields */
5819 #define LPI2C_SAMR_ADDR0_MASK 0x7FEu
5820 #define LPI2C_SAMR_ADDR0_SHIFT 1u
5821 #define LPI2C_SAMR_ADDR0_WIDTH 10u
5822 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR0_SHIFT))&LPI2C_SAMR_ADDR0_MASK)
5823 #define LPI2C_SAMR_ADDR1_MASK 0x7FE0000u
5824 #define LPI2C_SAMR_ADDR1_SHIFT 17u
5825 #define LPI2C_SAMR_ADDR1_WIDTH 10u
5826 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SAMR_ADDR1_SHIFT))&LPI2C_SAMR_ADDR1_MASK)
5827 /* SASR Bit Fields */
5828 #define LPI2C_SASR_RADDR_MASK 0x7FFu
5829 #define LPI2C_SASR_RADDR_SHIFT 0u
5830 #define LPI2C_SASR_RADDR_WIDTH 11u
5831 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_RADDR_SHIFT))&LPI2C_SASR_RADDR_MASK)
5832 #define LPI2C_SASR_ANV_MASK 0x4000u
5833 #define LPI2C_SASR_ANV_SHIFT 14u
5834 #define LPI2C_SASR_ANV_WIDTH 1u
5835 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SASR_ANV_SHIFT))&LPI2C_SASR_ANV_MASK)
5836 /* STAR Bit Fields */
5837 #define LPI2C_STAR_TXNACK_MASK 0x1u
5838 #define LPI2C_STAR_TXNACK_SHIFT 0u
5839 #define LPI2C_STAR_TXNACK_WIDTH 1u
5840 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STAR_TXNACK_SHIFT))&LPI2C_STAR_TXNACK_MASK)
5841 /* STDR Bit Fields */
5842 #define LPI2C_STDR_DATA_MASK 0xFFu
5843 #define LPI2C_STDR_DATA_SHIFT 0u
5844 #define LPI2C_STDR_DATA_WIDTH 8u
5845 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_STDR_DATA_SHIFT))&LPI2C_STDR_DATA_MASK)
5846 /* SRDR Bit Fields */
5847 #define LPI2C_SRDR_DATA_MASK 0xFFu
5848 #define LPI2C_SRDR_DATA_SHIFT 0u
5849 #define LPI2C_SRDR_DATA_WIDTH 8u
5850 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_DATA_SHIFT))&LPI2C_SRDR_DATA_MASK)
5851 #define LPI2C_SRDR_RXEMPTY_MASK 0x4000u
5852 #define LPI2C_SRDR_RXEMPTY_SHIFT 14u
5853 #define LPI2C_SRDR_RXEMPTY_WIDTH 1u
5854 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_RXEMPTY_SHIFT))&LPI2C_SRDR_RXEMPTY_MASK)
5855 #define LPI2C_SRDR_SOF_MASK 0x8000u
5856 #define LPI2C_SRDR_SOF_SHIFT 15u
5857 #define LPI2C_SRDR_SOF_WIDTH 1u
5858 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPI2C_SRDR_SOF_SHIFT))&LPI2C_SRDR_SOF_MASK)
5859  /* end of group LPI2C_Register_Masks */
5863 
5864  /* end of group LPI2C_Peripheral_Access_Layer */
5868 
5869 
5870 /* ----------------------------------------------------------------------------
5871  -- LPIT Peripheral Access Layer
5872  ---------------------------------------------------------------------------- */
5873 
5881 #define LPIT_TMR_COUNT 4u
5882 
5884 typedef struct {
5885  __I uint32_t VERID;
5886  __I uint32_t PARAM;
5887  __IO uint32_t MCR;
5888  __IO uint32_t MSR;
5889  __IO uint32_t MIER;
5890  __IO uint32_t SETTEN;
5891  __IO uint32_t CLRTEN;
5892  uint8_t RESERVED_0[4];
5893  struct { /* offset: 0x20, array step: 0x10 */
5894  __IO uint32_t TVAL;
5895  __I uint32_t CVAL;
5896  __IO uint32_t TCTRL;
5897  uint8_t RESERVED_0[4];
5898  } TMR[LPIT_TMR_COUNT];
5900 
5902 #define LPIT_INSTANCE_COUNT (1u)
5903 
5904 
5905 /* LPIT - Peripheral instance base addresses */
5907 #define LPIT0_BASE (0x40037000u)
5908 
5909 #define LPIT0 ((LPIT_Type *)LPIT0_BASE)
5910 
5911 #define LPIT_BASE_ADDRS { LPIT0_BASE }
5912 
5913 #define LPIT_BASE_PTRS { LPIT0 }
5914 
5915 #define LPIT_IRQS_ARR_COUNT (1u)
5916 
5917 #define LPIT_IRQS_CH_COUNT (4u)
5918 
5919 #define LPIT_IRQS { LPIT0_Ch0_IRQn, LPIT0_Ch1_IRQn, LPIT0_Ch2_IRQn, LPIT0_Ch3_IRQn }
5920 
5921 /* ----------------------------------------------------------------------------
5922  -- LPIT Register Masks
5923  ---------------------------------------------------------------------------- */
5924 
5930 /* VERID Bit Fields */
5931 #define LPIT_VERID_FEATURE_MASK 0xFFFFu
5932 #define LPIT_VERID_FEATURE_SHIFT 0u
5933 #define LPIT_VERID_FEATURE_WIDTH 16u
5934 #define LPIT_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_FEATURE_SHIFT))&LPIT_VERID_FEATURE_MASK)
5935 #define LPIT_VERID_MINOR_MASK 0xFF0000u
5936 #define LPIT_VERID_MINOR_SHIFT 16u
5937 #define LPIT_VERID_MINOR_WIDTH 8u
5938 #define LPIT_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MINOR_SHIFT))&LPIT_VERID_MINOR_MASK)
5939 #define LPIT_VERID_MAJOR_MASK 0xFF000000u
5940 #define LPIT_VERID_MAJOR_SHIFT 24u
5941 #define LPIT_VERID_MAJOR_WIDTH 8u
5942 #define LPIT_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPIT_VERID_MAJOR_SHIFT))&LPIT_VERID_MAJOR_MASK)
5943 /* PARAM Bit Fields */
5944 #define LPIT_PARAM_CHANNEL_MASK 0xFFu
5945 #define LPIT_PARAM_CHANNEL_SHIFT 0u
5946 #define LPIT_PARAM_CHANNEL_WIDTH 8u
5947 #define LPIT_PARAM_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_CHANNEL_SHIFT))&LPIT_PARAM_CHANNEL_MASK)
5948 #define LPIT_PARAM_EXT_TRIG_MASK 0xFF00u
5949 #define LPIT_PARAM_EXT_TRIG_SHIFT 8u
5950 #define LPIT_PARAM_EXT_TRIG_WIDTH 8u
5951 #define LPIT_PARAM_EXT_TRIG(x) (((uint32_t)(((uint32_t)(x))<<LPIT_PARAM_EXT_TRIG_SHIFT))&LPIT_PARAM_EXT_TRIG_MASK)
5952 /* MCR Bit Fields */
5953 #define LPIT_MCR_M_CEN_MASK 0x1u
5954 #define LPIT_MCR_M_CEN_SHIFT 0u
5955 #define LPIT_MCR_M_CEN_WIDTH 1u
5956 #define LPIT_MCR_M_CEN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_M_CEN_SHIFT))&LPIT_MCR_M_CEN_MASK)
5957 #define LPIT_MCR_SW_RST_MASK 0x2u
5958 #define LPIT_MCR_SW_RST_SHIFT 1u
5959 #define LPIT_MCR_SW_RST_WIDTH 1u
5960 #define LPIT_MCR_SW_RST(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_SW_RST_SHIFT))&LPIT_MCR_SW_RST_MASK)
5961 #define LPIT_MCR_DOZE_EN_MASK 0x4u
5962 #define LPIT_MCR_DOZE_EN_SHIFT 2u
5963 #define LPIT_MCR_DOZE_EN_WIDTH 1u
5964 #define LPIT_MCR_DOZE_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DOZE_EN_SHIFT))&LPIT_MCR_DOZE_EN_MASK)
5965 #define LPIT_MCR_DBG_EN_MASK 0x8u
5966 #define LPIT_MCR_DBG_EN_SHIFT 3u
5967 #define LPIT_MCR_DBG_EN_WIDTH 1u
5968 #define LPIT_MCR_DBG_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MCR_DBG_EN_SHIFT))&LPIT_MCR_DBG_EN_MASK)
5969 /* MSR Bit Fields */
5970 #define LPIT_MSR_TIF0_MASK 0x1u
5971 #define LPIT_MSR_TIF0_SHIFT 0u
5972 #define LPIT_MSR_TIF0_WIDTH 1u
5973 #define LPIT_MSR_TIF0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF0_SHIFT))&LPIT_MSR_TIF0_MASK)
5974 #define LPIT_MSR_TIF1_MASK 0x2u
5975 #define LPIT_MSR_TIF1_SHIFT 1u
5976 #define LPIT_MSR_TIF1_WIDTH 1u
5977 #define LPIT_MSR_TIF1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF1_SHIFT))&LPIT_MSR_TIF1_MASK)
5978 #define LPIT_MSR_TIF2_MASK 0x4u
5979 #define LPIT_MSR_TIF2_SHIFT 2u
5980 #define LPIT_MSR_TIF2_WIDTH 1u
5981 #define LPIT_MSR_TIF2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF2_SHIFT))&LPIT_MSR_TIF2_MASK)
5982 #define LPIT_MSR_TIF3_MASK 0x8u
5983 #define LPIT_MSR_TIF3_SHIFT 3u
5984 #define LPIT_MSR_TIF3_WIDTH 1u
5985 #define LPIT_MSR_TIF3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MSR_TIF3_SHIFT))&LPIT_MSR_TIF3_MASK)
5986 /* MIER Bit Fields */
5987 #define LPIT_MIER_TIE0_MASK 0x1u
5988 #define LPIT_MIER_TIE0_SHIFT 0u
5989 #define LPIT_MIER_TIE0_WIDTH 1u
5990 #define LPIT_MIER_TIE0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE0_SHIFT))&LPIT_MIER_TIE0_MASK)
5991 #define LPIT_MIER_TIE1_MASK 0x2u
5992 #define LPIT_MIER_TIE1_SHIFT 1u
5993 #define LPIT_MIER_TIE1_WIDTH 1u
5994 #define LPIT_MIER_TIE1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE1_SHIFT))&LPIT_MIER_TIE1_MASK)
5995 #define LPIT_MIER_TIE2_MASK 0x4u
5996 #define LPIT_MIER_TIE2_SHIFT 2u
5997 #define LPIT_MIER_TIE2_WIDTH 1u
5998 #define LPIT_MIER_TIE2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE2_SHIFT))&LPIT_MIER_TIE2_MASK)
5999 #define LPIT_MIER_TIE3_MASK 0x8u
6000 #define LPIT_MIER_TIE3_SHIFT 3u
6001 #define LPIT_MIER_TIE3_WIDTH 1u
6002 #define LPIT_MIER_TIE3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_MIER_TIE3_SHIFT))&LPIT_MIER_TIE3_MASK)
6003 /* SETTEN Bit Fields */
6004 #define LPIT_SETTEN_SET_T_EN_0_MASK 0x1u
6005 #define LPIT_SETTEN_SET_T_EN_0_SHIFT 0u
6006 #define LPIT_SETTEN_SET_T_EN_0_WIDTH 1u
6007 #define LPIT_SETTEN_SET_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_0_SHIFT))&LPIT_SETTEN_SET_T_EN_0_MASK)
6008 #define LPIT_SETTEN_SET_T_EN_1_MASK 0x2u
6009 #define LPIT_SETTEN_SET_T_EN_1_SHIFT 1u
6010 #define LPIT_SETTEN_SET_T_EN_1_WIDTH 1u
6011 #define LPIT_SETTEN_SET_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_1_SHIFT))&LPIT_SETTEN_SET_T_EN_1_MASK)
6012 #define LPIT_SETTEN_SET_T_EN_2_MASK 0x4u
6013 #define LPIT_SETTEN_SET_T_EN_2_SHIFT 2u
6014 #define LPIT_SETTEN_SET_T_EN_2_WIDTH 1u
6015 #define LPIT_SETTEN_SET_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_2_SHIFT))&LPIT_SETTEN_SET_T_EN_2_MASK)
6016 #define LPIT_SETTEN_SET_T_EN_3_MASK 0x8u
6017 #define LPIT_SETTEN_SET_T_EN_3_SHIFT 3u
6018 #define LPIT_SETTEN_SET_T_EN_3_WIDTH 1u
6019 #define LPIT_SETTEN_SET_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_SETTEN_SET_T_EN_3_SHIFT))&LPIT_SETTEN_SET_T_EN_3_MASK)
6020 /* CLRTEN Bit Fields */
6021 #define LPIT_CLRTEN_CLR_T_EN_0_MASK 0x1u
6022 #define LPIT_CLRTEN_CLR_T_EN_0_SHIFT 0u
6023 #define LPIT_CLRTEN_CLR_T_EN_0_WIDTH 1u
6024 #define LPIT_CLRTEN_CLR_T_EN_0(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_0_SHIFT))&LPIT_CLRTEN_CLR_T_EN_0_MASK)
6025 #define LPIT_CLRTEN_CLR_T_EN_1_MASK 0x2u
6026 #define LPIT_CLRTEN_CLR_T_EN_1_SHIFT 1u
6027 #define LPIT_CLRTEN_CLR_T_EN_1_WIDTH 1u
6028 #define LPIT_CLRTEN_CLR_T_EN_1(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_1_SHIFT))&LPIT_CLRTEN_CLR_T_EN_1_MASK)
6029 #define LPIT_CLRTEN_CLR_T_EN_2_MASK 0x4u
6030 #define LPIT_CLRTEN_CLR_T_EN_2_SHIFT 2u
6031 #define LPIT_CLRTEN_CLR_T_EN_2_WIDTH 1u
6032 #define LPIT_CLRTEN_CLR_T_EN_2(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_2_SHIFT))&LPIT_CLRTEN_CLR_T_EN_2_MASK)
6033 #define LPIT_CLRTEN_CLR_T_EN_3_MASK 0x8u
6034 #define LPIT_CLRTEN_CLR_T_EN_3_SHIFT 3u
6035 #define LPIT_CLRTEN_CLR_T_EN_3_WIDTH 1u
6036 #define LPIT_CLRTEN_CLR_T_EN_3(x) (((uint32_t)(((uint32_t)(x))<<LPIT_CLRTEN_CLR_T_EN_3_SHIFT))&LPIT_CLRTEN_CLR_T_EN_3_MASK)
6037 /* TMR_TVAL Bit Fields */
6038 #define LPIT_TMR_TVAL_TMR_VAL_MASK 0xFFFFFFFFu
6039 #define LPIT_TMR_TVAL_TMR_VAL_SHIFT 0u
6040 #define LPIT_TMR_TVAL_TMR_VAL_WIDTH 32u
6041 #define LPIT_TMR_TVAL_TMR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TVAL_TMR_VAL_SHIFT))&LPIT_TMR_TVAL_TMR_VAL_MASK)
6042 /* TMR_CVAL Bit Fields */
6043 #define LPIT_TMR_CVAL_TMR_CUR_VAL_MASK 0xFFFFFFFFu
6044 #define LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT 0u
6045 #define LPIT_TMR_CVAL_TMR_CUR_VAL_WIDTH 32u
6046 #define LPIT_TMR_CVAL_TMR_CUR_VAL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_CVAL_TMR_CUR_VAL_SHIFT))&LPIT_TMR_CVAL_TMR_CUR_VAL_MASK)
6047 /* TMR_TCTRL Bit Fields */
6048 #define LPIT_TMR_TCTRL_T_EN_MASK 0x1u
6049 #define LPIT_TMR_TCTRL_T_EN_SHIFT 0u
6050 #define LPIT_TMR_TCTRL_T_EN_WIDTH 1u
6051 #define LPIT_TMR_TCTRL_T_EN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_T_EN_SHIFT))&LPIT_TMR_TCTRL_T_EN_MASK)
6052 #define LPIT_TMR_TCTRL_CHAIN_MASK 0x2u
6053 #define LPIT_TMR_TCTRL_CHAIN_SHIFT 1u
6054 #define LPIT_TMR_TCTRL_CHAIN_WIDTH 1u
6055 #define LPIT_TMR_TCTRL_CHAIN(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_CHAIN_SHIFT))&LPIT_TMR_TCTRL_CHAIN_MASK)
6056 #define LPIT_TMR_TCTRL_MODE_MASK 0xCu
6057 #define LPIT_TMR_TCTRL_MODE_SHIFT 2u
6058 #define LPIT_TMR_TCTRL_MODE_WIDTH 2u
6059 #define LPIT_TMR_TCTRL_MODE(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_MODE_SHIFT))&LPIT_TMR_TCTRL_MODE_MASK)
6060 #define LPIT_TMR_TCTRL_TSOT_MASK 0x10000u
6061 #define LPIT_TMR_TCTRL_TSOT_SHIFT 16u
6062 #define LPIT_TMR_TCTRL_TSOT_WIDTH 1u
6063 #define LPIT_TMR_TCTRL_TSOT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOT_SHIFT))&LPIT_TMR_TCTRL_TSOT_MASK)
6064 #define LPIT_TMR_TCTRL_TSOI_MASK 0x20000u
6065 #define LPIT_TMR_TCTRL_TSOI_SHIFT 17u
6066 #define LPIT_TMR_TCTRL_TSOI_WIDTH 1u
6067 #define LPIT_TMR_TCTRL_TSOI(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TSOI_SHIFT))&LPIT_TMR_TCTRL_TSOI_MASK)
6068 #define LPIT_TMR_TCTRL_TROT_MASK 0x40000u
6069 #define LPIT_TMR_TCTRL_TROT_SHIFT 18u
6070 #define LPIT_TMR_TCTRL_TROT_WIDTH 1u
6071 #define LPIT_TMR_TCTRL_TROT(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TROT_SHIFT))&LPIT_TMR_TCTRL_TROT_MASK)
6072 #define LPIT_TMR_TCTRL_TRG_SRC_MASK 0x800000u
6073 #define LPIT_TMR_TCTRL_TRG_SRC_SHIFT 23u
6074 #define LPIT_TMR_TCTRL_TRG_SRC_WIDTH 1u
6075 #define LPIT_TMR_TCTRL_TRG_SRC(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SRC_SHIFT))&LPIT_TMR_TCTRL_TRG_SRC_MASK)
6076 #define LPIT_TMR_TCTRL_TRG_SEL_MASK 0xF000000u
6077 #define LPIT_TMR_TCTRL_TRG_SEL_SHIFT 24u
6078 #define LPIT_TMR_TCTRL_TRG_SEL_WIDTH 4u
6079 #define LPIT_TMR_TCTRL_TRG_SEL(x) (((uint32_t)(((uint32_t)(x))<<LPIT_TMR_TCTRL_TRG_SEL_SHIFT))&LPIT_TMR_TCTRL_TRG_SEL_MASK)
6080  /* end of group LPIT_Register_Masks */
6084 
6085  /* end of group LPIT_Peripheral_Access_Layer */
6089 
6090 
6091 /* ----------------------------------------------------------------------------
6092  -- LPSPI Peripheral Access Layer
6093  ---------------------------------------------------------------------------- */
6094 
6104 typedef struct {
6105  __I uint32_t VERID;
6106  __I uint32_t PARAM;
6107  uint8_t RESERVED_0[8];
6108  __IO uint32_t CR;
6109  __IO uint32_t SR;
6110  __IO uint32_t IER;
6111  __IO uint32_t DER;
6112  __IO uint32_t CFGR0;
6113  __IO uint32_t CFGR1;
6114  uint8_t RESERVED_1[8];
6115  __IO uint32_t DMR0;
6116  __IO uint32_t DMR1;
6117  uint8_t RESERVED_2[8];
6118  __IO uint32_t CCR;
6119  uint8_t RESERVED_3[20];
6120  __IO uint32_t FCR;
6121  __I uint32_t FSR;
6122  __IO uint32_t TCR;
6123  __O uint32_t TDR;
6124  uint8_t RESERVED_4[8];
6125  __I uint32_t RSR;
6126  __I uint32_t RDR;
6128 
6130 #define LPSPI_INSTANCE_COUNT (2u)
6131 
6132 
6133 /* LPSPI - Peripheral instance base addresses */
6135 #define LPSPI0_BASE (0x4002C000u)
6136 
6137 #define LPSPI0 ((LPSPI_Type *)LPSPI0_BASE)
6138 
6139 #define LPSPI1_BASE (0x4002D000u)
6140 
6141 #define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
6142 
6143 #define LPSPI_BASE_ADDRS { LPSPI0_BASE, LPSPI1_BASE }
6144 
6145 #define LPSPI_BASE_PTRS { LPSPI0, LPSPI1 }
6146 
6147 #define LPSPI_IRQS_ARR_COUNT (1u)
6148 
6149 #define LPSPI_IRQS_CH_COUNT (1u)
6150 
6151 #define LPSPI_IRQS { LPSPI0_IRQn, LPSPI1_IRQn }
6152 
6153 /* ----------------------------------------------------------------------------
6154  -- LPSPI Register Masks
6155  ---------------------------------------------------------------------------- */
6156 
6162 /* VERID Bit Fields */
6163 #define LPSPI_VERID_FEATURE_MASK 0xFFFFu
6164 #define LPSPI_VERID_FEATURE_SHIFT 0u
6165 #define LPSPI_VERID_FEATURE_WIDTH 16u
6166 #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_FEATURE_SHIFT))&LPSPI_VERID_FEATURE_MASK)
6167 #define LPSPI_VERID_MINOR_MASK 0xFF0000u
6168 #define LPSPI_VERID_MINOR_SHIFT 16u
6169 #define LPSPI_VERID_MINOR_WIDTH 8u
6170 #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MINOR_SHIFT))&LPSPI_VERID_MINOR_MASK)
6171 #define LPSPI_VERID_MAJOR_MASK 0xFF000000u
6172 #define LPSPI_VERID_MAJOR_SHIFT 24u
6173 #define LPSPI_VERID_MAJOR_WIDTH 8u
6174 #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_VERID_MAJOR_SHIFT))&LPSPI_VERID_MAJOR_MASK)
6175 /* PARAM Bit Fields */
6176 #define LPSPI_PARAM_TXFIFO_MASK 0xFFu
6177 #define LPSPI_PARAM_TXFIFO_SHIFT 0u
6178 #define LPSPI_PARAM_TXFIFO_WIDTH 8u
6179 #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_TXFIFO_SHIFT))&LPSPI_PARAM_TXFIFO_MASK)
6180 #define LPSPI_PARAM_RXFIFO_MASK 0xFF00u
6181 #define LPSPI_PARAM_RXFIFO_SHIFT 8u
6182 #define LPSPI_PARAM_RXFIFO_WIDTH 8u
6183 #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_PARAM_RXFIFO_SHIFT))&LPSPI_PARAM_RXFIFO_MASK)
6184 /* CR Bit Fields */
6185 #define LPSPI_CR_MEN_MASK 0x1u
6186 #define LPSPI_CR_MEN_SHIFT 0u
6187 #define LPSPI_CR_MEN_WIDTH 1u
6188 #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_MEN_SHIFT))&LPSPI_CR_MEN_MASK)
6189 #define LPSPI_CR_RST_MASK 0x2u
6190 #define LPSPI_CR_RST_SHIFT 1u
6191 #define LPSPI_CR_RST_WIDTH 1u
6192 #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RST_SHIFT))&LPSPI_CR_RST_MASK)
6193 #define LPSPI_CR_DOZEN_MASK 0x4u
6194 #define LPSPI_CR_DOZEN_SHIFT 2u
6195 #define LPSPI_CR_DOZEN_WIDTH 1u
6196 #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DOZEN_SHIFT))&LPSPI_CR_DOZEN_MASK)
6197 #define LPSPI_CR_DBGEN_MASK 0x8u
6198 #define LPSPI_CR_DBGEN_SHIFT 3u
6199 #define LPSPI_CR_DBGEN_WIDTH 1u
6200 #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_DBGEN_SHIFT))&LPSPI_CR_DBGEN_MASK)
6201 #define LPSPI_CR_RTF_MASK 0x100u
6202 #define LPSPI_CR_RTF_SHIFT 8u
6203 #define LPSPI_CR_RTF_WIDTH 1u
6204 #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RTF_SHIFT))&LPSPI_CR_RTF_MASK)
6205 #define LPSPI_CR_RRF_MASK 0x200u
6206 #define LPSPI_CR_RRF_SHIFT 9u
6207 #define LPSPI_CR_RRF_WIDTH 1u
6208 #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CR_RRF_SHIFT))&LPSPI_CR_RRF_MASK)
6209 /* SR Bit Fields */
6210 #define LPSPI_SR_TDF_MASK 0x1u
6211 #define LPSPI_SR_TDF_SHIFT 0u
6212 #define LPSPI_SR_TDF_WIDTH 1u
6213 #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TDF_SHIFT))&LPSPI_SR_TDF_MASK)
6214 #define LPSPI_SR_RDF_MASK 0x2u
6215 #define LPSPI_SR_RDF_SHIFT 1u
6216 #define LPSPI_SR_RDF_WIDTH 1u
6217 #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_RDF_SHIFT))&LPSPI_SR_RDF_MASK)
6218 #define LPSPI_SR_WCF_MASK 0x100u
6219 #define LPSPI_SR_WCF_SHIFT 8u
6220 #define LPSPI_SR_WCF_WIDTH 1u
6221 #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_WCF_SHIFT))&LPSPI_SR_WCF_MASK)
6222 #define LPSPI_SR_FCF_MASK 0x200u
6223 #define LPSPI_SR_FCF_SHIFT 9u
6224 #define LPSPI_SR_FCF_WIDTH 1u
6225 #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_FCF_SHIFT))&LPSPI_SR_FCF_MASK)
6226 #define LPSPI_SR_TCF_MASK 0x400u
6227 #define LPSPI_SR_TCF_SHIFT 10u
6228 #define LPSPI_SR_TCF_WIDTH 1u
6229 #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TCF_SHIFT))&LPSPI_SR_TCF_MASK)
6230 #define LPSPI_SR_TEF_MASK 0x800u
6231 #define LPSPI_SR_TEF_SHIFT 11u
6232 #define LPSPI_SR_TEF_WIDTH 1u
6233 #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_TEF_SHIFT))&LPSPI_SR_TEF_MASK)
6234 #define LPSPI_SR_REF_MASK 0x1000u
6235 #define LPSPI_SR_REF_SHIFT 12u
6236 #define LPSPI_SR_REF_WIDTH 1u
6237 #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_REF_SHIFT))&LPSPI_SR_REF_MASK)
6238 #define LPSPI_SR_DMF_MASK 0x2000u
6239 #define LPSPI_SR_DMF_SHIFT 13u
6240 #define LPSPI_SR_DMF_WIDTH 1u
6241 #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_DMF_SHIFT))&LPSPI_SR_DMF_MASK)
6242 #define LPSPI_SR_MBF_MASK 0x1000000u
6243 #define LPSPI_SR_MBF_SHIFT 24u
6244 #define LPSPI_SR_MBF_WIDTH 1u
6245 #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_SR_MBF_SHIFT))&LPSPI_SR_MBF_MASK)
6246 /* IER Bit Fields */
6247 #define LPSPI_IER_TDIE_MASK 0x1u
6248 #define LPSPI_IER_TDIE_SHIFT 0u
6249 #define LPSPI_IER_TDIE_WIDTH 1u
6250 #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TDIE_SHIFT))&LPSPI_IER_TDIE_MASK)
6251 #define LPSPI_IER_RDIE_MASK 0x2u
6252 #define LPSPI_IER_RDIE_SHIFT 1u
6253 #define LPSPI_IER_RDIE_WIDTH 1u
6254 #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_RDIE_SHIFT))&LPSPI_IER_RDIE_MASK)
6255 #define LPSPI_IER_WCIE_MASK 0x100u
6256 #define LPSPI_IER_WCIE_SHIFT 8u
6257 #define LPSPI_IER_WCIE_WIDTH 1u
6258 #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_WCIE_SHIFT))&LPSPI_IER_WCIE_MASK)
6259 #define LPSPI_IER_FCIE_MASK 0x200u
6260 #define LPSPI_IER_FCIE_SHIFT 9u
6261 #define LPSPI_IER_FCIE_WIDTH 1u
6262 #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_FCIE_SHIFT))&LPSPI_IER_FCIE_MASK)
6263 #define LPSPI_IER_TCIE_MASK 0x400u
6264 #define LPSPI_IER_TCIE_SHIFT 10u
6265 #define LPSPI_IER_TCIE_WIDTH 1u
6266 #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TCIE_SHIFT))&LPSPI_IER_TCIE_MASK)
6267 #define LPSPI_IER_TEIE_MASK 0x800u
6268 #define LPSPI_IER_TEIE_SHIFT 11u
6269 #define LPSPI_IER_TEIE_WIDTH 1u
6270 #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_TEIE_SHIFT))&LPSPI_IER_TEIE_MASK)
6271 #define LPSPI_IER_REIE_MASK 0x1000u
6272 #define LPSPI_IER_REIE_SHIFT 12u
6273 #define LPSPI_IER_REIE_WIDTH 1u
6274 #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_REIE_SHIFT))&LPSPI_IER_REIE_MASK)
6275 #define LPSPI_IER_DMIE_MASK 0x2000u
6276 #define LPSPI_IER_DMIE_SHIFT 13u
6277 #define LPSPI_IER_DMIE_WIDTH 1u
6278 #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_IER_DMIE_SHIFT))&LPSPI_IER_DMIE_MASK)
6279 /* DER Bit Fields */
6280 #define LPSPI_DER_TDDE_MASK 0x1u
6281 #define LPSPI_DER_TDDE_SHIFT 0u
6282 #define LPSPI_DER_TDDE_WIDTH 1u
6283 #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_TDDE_SHIFT))&LPSPI_DER_TDDE_MASK)
6284 #define LPSPI_DER_RDDE_MASK 0x2u
6285 #define LPSPI_DER_RDDE_SHIFT 1u
6286 #define LPSPI_DER_RDDE_WIDTH 1u
6287 #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DER_RDDE_SHIFT))&LPSPI_DER_RDDE_MASK)
6288 /* CFGR0 Bit Fields */
6289 #define LPSPI_CFGR0_HREN_MASK 0x1u
6290 #define LPSPI_CFGR0_HREN_SHIFT 0u
6291 #define LPSPI_CFGR0_HREN_WIDTH 1u
6292 #define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HREN_SHIFT))&LPSPI_CFGR0_HREN_MASK)
6293 #define LPSPI_CFGR0_HRPOL_MASK 0x2u
6294 #define LPSPI_CFGR0_HRPOL_SHIFT 1u
6295 #define LPSPI_CFGR0_HRPOL_WIDTH 1u
6296 #define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRPOL_SHIFT))&LPSPI_CFGR0_HRPOL_MASK)
6297 #define LPSPI_CFGR0_HRSEL_MASK 0x4u
6298 #define LPSPI_CFGR0_HRSEL_SHIFT 2u
6299 #define LPSPI_CFGR0_HRSEL_WIDTH 1u
6300 #define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_HRSEL_SHIFT))&LPSPI_CFGR0_HRSEL_MASK)
6301 #define LPSPI_CFGR0_CIRFIFO_MASK 0x100u
6302 #define LPSPI_CFGR0_CIRFIFO_SHIFT 8u
6303 #define LPSPI_CFGR0_CIRFIFO_WIDTH 1u
6304 #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_CIRFIFO_SHIFT))&LPSPI_CFGR0_CIRFIFO_MASK)
6305 #define LPSPI_CFGR0_RDMO_MASK 0x200u
6306 #define LPSPI_CFGR0_RDMO_SHIFT 9u
6307 #define LPSPI_CFGR0_RDMO_WIDTH 1u
6308 #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR0_RDMO_SHIFT))&LPSPI_CFGR0_RDMO_MASK)
6309 /* CFGR1 Bit Fields */
6310 #define LPSPI_CFGR1_MASTER_MASK 0x1u
6311 #define LPSPI_CFGR1_MASTER_SHIFT 0u
6312 #define LPSPI_CFGR1_MASTER_WIDTH 1u
6313 #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MASTER_SHIFT))&LPSPI_CFGR1_MASTER_MASK)
6314 #define LPSPI_CFGR1_SAMPLE_MASK 0x2u
6315 #define LPSPI_CFGR1_SAMPLE_SHIFT 1u
6316 #define LPSPI_CFGR1_SAMPLE_WIDTH 1u
6317 #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_SAMPLE_SHIFT))&LPSPI_CFGR1_SAMPLE_MASK)
6318 #define LPSPI_CFGR1_AUTOPCS_MASK 0x4u
6319 #define LPSPI_CFGR1_AUTOPCS_SHIFT 2u
6320 #define LPSPI_CFGR1_AUTOPCS_WIDTH 1u
6321 #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_AUTOPCS_SHIFT))&LPSPI_CFGR1_AUTOPCS_MASK)
6322 #define LPSPI_CFGR1_NOSTALL_MASK 0x8u
6323 #define LPSPI_CFGR1_NOSTALL_SHIFT 3u
6324 #define LPSPI_CFGR1_NOSTALL_WIDTH 1u
6325 #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_NOSTALL_SHIFT))&LPSPI_CFGR1_NOSTALL_MASK)
6326 #define LPSPI_CFGR1_PCSPOL_MASK 0xF00u
6327 #define LPSPI_CFGR1_PCSPOL_SHIFT 8u
6328 #define LPSPI_CFGR1_PCSPOL_WIDTH 4u
6329 #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSPOL_SHIFT))&LPSPI_CFGR1_PCSPOL_MASK)
6330 #define LPSPI_CFGR1_MATCFG_MASK 0x70000u
6331 #define LPSPI_CFGR1_MATCFG_SHIFT 16u
6332 #define LPSPI_CFGR1_MATCFG_WIDTH 3u
6333 #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_MATCFG_SHIFT))&LPSPI_CFGR1_MATCFG_MASK)
6334 #define LPSPI_CFGR1_PINCFG_MASK 0x3000000u
6335 #define LPSPI_CFGR1_PINCFG_SHIFT 24u
6336 #define LPSPI_CFGR1_PINCFG_WIDTH 2u
6337 #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PINCFG_SHIFT))&LPSPI_CFGR1_PINCFG_MASK)
6338 #define LPSPI_CFGR1_OUTCFG_MASK 0x4000000u
6339 #define LPSPI_CFGR1_OUTCFG_SHIFT 26u
6340 #define LPSPI_CFGR1_OUTCFG_WIDTH 1u
6341 #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_OUTCFG_SHIFT))&LPSPI_CFGR1_OUTCFG_MASK)
6342 #define LPSPI_CFGR1_PCSCFG_MASK 0x8000000u
6343 #define LPSPI_CFGR1_PCSCFG_SHIFT 27u
6344 #define LPSPI_CFGR1_PCSCFG_WIDTH 1u
6345 #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CFGR1_PCSCFG_SHIFT))&LPSPI_CFGR1_PCSCFG_MASK)
6346 /* DMR0 Bit Fields */
6347 #define LPSPI_DMR0_MATCH0_MASK 0xFFFFFFFFu
6348 #define LPSPI_DMR0_MATCH0_SHIFT 0u
6349 #define LPSPI_DMR0_MATCH0_WIDTH 32u
6350 #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR0_MATCH0_SHIFT))&LPSPI_DMR0_MATCH0_MASK)
6351 /* DMR1 Bit Fields */
6352 #define LPSPI_DMR1_MATCH1_MASK 0xFFFFFFFFu
6353 #define LPSPI_DMR1_MATCH1_SHIFT 0u
6354 #define LPSPI_DMR1_MATCH1_WIDTH 32u
6355 #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_DMR1_MATCH1_SHIFT))&LPSPI_DMR1_MATCH1_MASK)
6356 /* CCR Bit Fields */
6357 #define LPSPI_CCR_SCKDIV_MASK 0xFFu
6358 #define LPSPI_CCR_SCKDIV_SHIFT 0u
6359 #define LPSPI_CCR_SCKDIV_WIDTH 8u
6360 #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKDIV_SHIFT))&LPSPI_CCR_SCKDIV_MASK)
6361 #define LPSPI_CCR_DBT_MASK 0xFF00u
6362 #define LPSPI_CCR_DBT_SHIFT 8u
6363 #define LPSPI_CCR_DBT_WIDTH 8u
6364 #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_DBT_SHIFT))&LPSPI_CCR_DBT_MASK)
6365 #define LPSPI_CCR_PCSSCK_MASK 0xFF0000u
6366 #define LPSPI_CCR_PCSSCK_SHIFT 16u
6367 #define LPSPI_CCR_PCSSCK_WIDTH 8u
6368 #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_PCSSCK_SHIFT))&LPSPI_CCR_PCSSCK_MASK)
6369 #define LPSPI_CCR_SCKPCS_MASK 0xFF000000u
6370 #define LPSPI_CCR_SCKPCS_SHIFT 24u
6371 #define LPSPI_CCR_SCKPCS_WIDTH 8u
6372 #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_CCR_SCKPCS_SHIFT))&LPSPI_CCR_SCKPCS_MASK)
6373 /* FCR Bit Fields */
6374 #define LPSPI_FCR_TXWATER_MASK 0x3u
6375 #define LPSPI_FCR_TXWATER_SHIFT 0u
6376 #define LPSPI_FCR_TXWATER_WIDTH 2u
6377 #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_TXWATER_SHIFT))&LPSPI_FCR_TXWATER_MASK)
6378 #define LPSPI_FCR_RXWATER_MASK 0x30000u
6379 #define LPSPI_FCR_RXWATER_SHIFT 16u
6380 #define LPSPI_FCR_RXWATER_WIDTH 2u
6381 #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FCR_RXWATER_SHIFT))&LPSPI_FCR_RXWATER_MASK)
6382 /* FSR Bit Fields */
6383 #define LPSPI_FSR_TXCOUNT_MASK 0x7u
6384 #define LPSPI_FSR_TXCOUNT_SHIFT 0u
6385 #define LPSPI_FSR_TXCOUNT_WIDTH 3u
6386 #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_TXCOUNT_SHIFT))&LPSPI_FSR_TXCOUNT_MASK)
6387 #define LPSPI_FSR_RXCOUNT_MASK 0x70000u
6388 #define LPSPI_FSR_RXCOUNT_SHIFT 16u
6389 #define LPSPI_FSR_RXCOUNT_WIDTH 3u
6390 #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_FSR_RXCOUNT_SHIFT))&LPSPI_FSR_RXCOUNT_MASK)
6391 /* TCR Bit Fields */
6392 #define LPSPI_TCR_FRAMESZ_MASK 0xFFFu
6393 #define LPSPI_TCR_FRAMESZ_SHIFT 0u
6394 #define LPSPI_TCR_FRAMESZ_WIDTH 12u
6395 #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_FRAMESZ_SHIFT))&LPSPI_TCR_FRAMESZ_MASK)
6396 #define LPSPI_TCR_WIDTH_MASK 0x30000u
6397 #define LPSPI_TCR_WIDTH_SHIFT 16u
6398 #define LPSPI_TCR_WIDTH_WIDTH 2u
6399 #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_WIDTH_SHIFT))&LPSPI_TCR_WIDTH_MASK)
6400 #define LPSPI_TCR_TXMSK_MASK 0x40000u
6401 #define LPSPI_TCR_TXMSK_SHIFT 18u
6402 #define LPSPI_TCR_TXMSK_WIDTH 1u
6403 #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_TXMSK_SHIFT))&LPSPI_TCR_TXMSK_MASK)
6404 #define LPSPI_TCR_RXMSK_MASK 0x80000u
6405 #define LPSPI_TCR_RXMSK_SHIFT 19u
6406 #define LPSPI_TCR_RXMSK_WIDTH 1u
6407 #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_RXMSK_SHIFT))&LPSPI_TCR_RXMSK_MASK)
6408 #define LPSPI_TCR_CONTC_MASK 0x100000u
6409 #define LPSPI_TCR_CONTC_SHIFT 20u
6410 #define LPSPI_TCR_CONTC_WIDTH 1u
6411 #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONTC_SHIFT))&LPSPI_TCR_CONTC_MASK)
6412 #define LPSPI_TCR_CONT_MASK 0x200000u
6413 #define LPSPI_TCR_CONT_SHIFT 21u
6414 #define LPSPI_TCR_CONT_WIDTH 1u
6415 #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CONT_SHIFT))&LPSPI_TCR_CONT_MASK)
6416 #define LPSPI_TCR_BYSW_MASK 0x400000u
6417 #define LPSPI_TCR_BYSW_SHIFT 22u
6418 #define LPSPI_TCR_BYSW_WIDTH 1u
6419 #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_BYSW_SHIFT))&LPSPI_TCR_BYSW_MASK)
6420 #define LPSPI_TCR_LSBF_MASK 0x800000u
6421 #define LPSPI_TCR_LSBF_SHIFT 23u
6422 #define LPSPI_TCR_LSBF_WIDTH 1u
6423 #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_LSBF_SHIFT))&LPSPI_TCR_LSBF_MASK)
6424 #define LPSPI_TCR_PCS_MASK 0x3000000u
6425 #define LPSPI_TCR_PCS_SHIFT 24u
6426 #define LPSPI_TCR_PCS_WIDTH 2u
6427 #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PCS_SHIFT))&LPSPI_TCR_PCS_MASK)
6428 #define LPSPI_TCR_PRESCALE_MASK 0x38000000u
6429 #define LPSPI_TCR_PRESCALE_SHIFT 27u
6430 #define LPSPI_TCR_PRESCALE_WIDTH 3u
6431 #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_PRESCALE_SHIFT))&LPSPI_TCR_PRESCALE_MASK)
6432 #define LPSPI_TCR_CPHA_MASK 0x40000000u
6433 #define LPSPI_TCR_CPHA_SHIFT 30u
6434 #define LPSPI_TCR_CPHA_WIDTH 1u
6435 #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPHA_SHIFT))&LPSPI_TCR_CPHA_MASK)
6436 #define LPSPI_TCR_CPOL_MASK 0x80000000u
6437 #define LPSPI_TCR_CPOL_SHIFT 31u
6438 #define LPSPI_TCR_CPOL_WIDTH 1u
6439 #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TCR_CPOL_SHIFT))&LPSPI_TCR_CPOL_MASK)
6440 /* TDR Bit Fields */
6441 #define LPSPI_TDR_DATA_MASK 0xFFFFFFFFu
6442 #define LPSPI_TDR_DATA_SHIFT 0u
6443 #define LPSPI_TDR_DATA_WIDTH 32u
6444 #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_TDR_DATA_SHIFT))&LPSPI_TDR_DATA_MASK)
6445 /* RSR Bit Fields */
6446 #define LPSPI_RSR_SOF_MASK 0x1u
6447 #define LPSPI_RSR_SOF_SHIFT 0u
6448 #define LPSPI_RSR_SOF_WIDTH 1u
6449 #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_SOF_SHIFT))&LPSPI_RSR_SOF_MASK)
6450 #define LPSPI_RSR_RXEMPTY_MASK 0x2u
6451 #define LPSPI_RSR_RXEMPTY_SHIFT 1u
6452 #define LPSPI_RSR_RXEMPTY_WIDTH 1u
6453 #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RSR_RXEMPTY_SHIFT))&LPSPI_RSR_RXEMPTY_MASK)
6454 /* RDR Bit Fields */
6455 #define LPSPI_RDR_DATA_MASK 0xFFFFFFFFu
6456 #define LPSPI_RDR_DATA_SHIFT 0u
6457 #define LPSPI_RDR_DATA_WIDTH 32u
6458 #define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x))<<LPSPI_RDR_DATA_SHIFT))&LPSPI_RDR_DATA_MASK)
6459  /* end of group LPSPI_Register_Masks */
6463 
6464  /* end of group LPSPI_Peripheral_Access_Layer */
6468 
6469 
6470 /* ----------------------------------------------------------------------------
6471  -- LPTMR Peripheral Access Layer
6472  ---------------------------------------------------------------------------- */
6473 
6483 typedef struct {
6484  __IO uint32_t CSR;
6485  __IO uint32_t PSR;
6486  __IO uint32_t CMR;
6487  __IO uint32_t CNR;
6489 
6491 #define LPTMR_INSTANCE_COUNT (1u)
6492 
6493 
6494 /* LPTMR - Peripheral instance base addresses */
6496 #define LPTMR0_BASE (0x40040000u)
6497 
6498 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
6499 
6500 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
6501 
6502 #define LPTMR_BASE_PTRS { LPTMR0 }
6503 
6504 #define LPTMR_IRQS_ARR_COUNT (1u)
6505 
6506 #define LPTMR_IRQS_CH_COUNT (1u)
6507 
6508 #define LPTMR_IRQS { LPTMR0_IRQn }
6509 
6510 /* ----------------------------------------------------------------------------
6511  -- LPTMR Register Masks
6512  ---------------------------------------------------------------------------- */
6513 
6519 /* CSR Bit Fields */
6520 #define LPTMR_CSR_TEN_MASK 0x1u
6521 #define LPTMR_CSR_TEN_SHIFT 0u
6522 #define LPTMR_CSR_TEN_WIDTH 1u
6523 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
6524 #define LPTMR_CSR_TMS_MASK 0x2u
6525 #define LPTMR_CSR_TMS_SHIFT 1u
6526 #define LPTMR_CSR_TMS_WIDTH 1u
6527 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
6528 #define LPTMR_CSR_TFC_MASK 0x4u
6529 #define LPTMR_CSR_TFC_SHIFT 2u
6530 #define LPTMR_CSR_TFC_WIDTH 1u
6531 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TFC_SHIFT))&LPTMR_CSR_TFC_MASK)
6532 #define LPTMR_CSR_TPP_MASK 0x8u
6533 #define LPTMR_CSR_TPP_SHIFT 3u
6534 #define LPTMR_CSR_TPP_WIDTH 1u
6535 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
6536 #define LPTMR_CSR_TPS_MASK 0x30u
6537 #define LPTMR_CSR_TPS_SHIFT 4u
6538 #define LPTMR_CSR_TPS_WIDTH 2u
6539 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
6540 #define LPTMR_CSR_TIE_MASK 0x40u
6541 #define LPTMR_CSR_TIE_SHIFT 6u
6542 #define LPTMR_CSR_TIE_WIDTH 1u
6543 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TIE_SHIFT))&LPTMR_CSR_TIE_MASK)
6544 #define LPTMR_CSR_TCF_MASK 0x80u
6545 #define LPTMR_CSR_TCF_SHIFT 7u
6546 #define LPTMR_CSR_TCF_WIDTH 1u
6547 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TCF_SHIFT))&LPTMR_CSR_TCF_MASK)
6548 #define LPTMR_CSR_TDRE_MASK 0x100u
6549 #define LPTMR_CSR_TDRE_SHIFT 8u
6550 #define LPTMR_CSR_TDRE_WIDTH 1u
6551 #define LPTMR_CSR_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TDRE_SHIFT))&LPTMR_CSR_TDRE_MASK)
6552 /* PSR Bit Fields */
6553 #define LPTMR_PSR_PCS_MASK 0x3u
6554 #define LPTMR_PSR_PCS_SHIFT 0u
6555 #define LPTMR_PSR_PCS_WIDTH 2u
6556 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
6557 #define LPTMR_PSR_PBYP_MASK 0x4u
6558 #define LPTMR_PSR_PBYP_SHIFT 2u
6559 #define LPTMR_PSR_PBYP_WIDTH 1u
6560 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PBYP_SHIFT))&LPTMR_PSR_PBYP_MASK)
6561 #define LPTMR_PSR_PRESCALE_MASK 0x78u
6562 #define LPTMR_PSR_PRESCALE_SHIFT 3u
6563 #define LPTMR_PSR_PRESCALE_WIDTH 4u
6564 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
6565 /* CMR Bit Fields */
6566 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
6567 #define LPTMR_CMR_COMPARE_SHIFT 0u
6568 #define LPTMR_CMR_COMPARE_WIDTH 16u
6569 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
6570 /* CNR Bit Fields */
6571 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
6572 #define LPTMR_CNR_COUNTER_SHIFT 0u
6573 #define LPTMR_CNR_COUNTER_WIDTH 16u
6574 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
6575  /* end of group LPTMR_Register_Masks */
6579 
6580  /* end of group LPTMR_Peripheral_Access_Layer */
6584 
6585 
6586 /* ----------------------------------------------------------------------------
6587  -- LPUART Peripheral Access Layer
6588  ---------------------------------------------------------------------------- */
6589 
6599 typedef struct {
6600  __I uint32_t VERID;
6601  __I uint32_t PARAM;
6602  __IO uint32_t GLOBAL;
6603  __IO uint32_t PINCFG;
6604  __IO uint32_t BAUD;
6605  __IO uint32_t STAT;
6606  __IO uint32_t CTRL;
6607  __IO uint32_t DATA;
6608  __IO uint32_t MATCH;
6609  __IO uint32_t MODIR;
6610  __IO uint32_t FIFO;
6611  __IO uint32_t WATER;
6613 
6615 #define LPUART_INSTANCE_COUNT (2u)
6616 
6617 
6618 /* LPUART - Peripheral instance base addresses */
6620 #define LPUART0_BASE (0x4006A000u)
6621 
6622 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
6623 
6624 #define LPUART1_BASE (0x4006B000u)
6625 
6626 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
6627 
6628 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
6629 
6630 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
6631 
6632 #define LPUART_IRQS_ARR_COUNT (1u)
6633 
6634 #define LPUART_RX_TX_IRQS_CH_COUNT (1u)
6635 
6636 #define LPUART_RX_TX_IRQS { LPUART0_RxTx_IRQn, LPUART1_RxTx_IRQn }
6637 
6638 /* ----------------------------------------------------------------------------
6639  -- LPUART Register Masks
6640  ---------------------------------------------------------------------------- */
6641 
6647 /* VERID Bit Fields */
6648 #define LPUART_VERID_FEATURE_MASK 0xFFFFu
6649 #define LPUART_VERID_FEATURE_SHIFT 0u
6650 #define LPUART_VERID_FEATURE_WIDTH 16u
6651 #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_FEATURE_SHIFT))&LPUART_VERID_FEATURE_MASK)
6652 #define LPUART_VERID_MINOR_MASK 0xFF0000u
6653 #define LPUART_VERID_MINOR_SHIFT 16u
6654 #define LPUART_VERID_MINOR_WIDTH 8u
6655 #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MINOR_SHIFT))&LPUART_VERID_MINOR_MASK)
6656 #define LPUART_VERID_MAJOR_MASK 0xFF000000u
6657 #define LPUART_VERID_MAJOR_SHIFT 24u
6658 #define LPUART_VERID_MAJOR_WIDTH 8u
6659 #define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_VERID_MAJOR_SHIFT))&LPUART_VERID_MAJOR_MASK)
6660 /* PARAM Bit Fields */
6661 #define LPUART_PARAM_TXFIFO_MASK 0xFFu
6662 #define LPUART_PARAM_TXFIFO_SHIFT 0u
6663 #define LPUART_PARAM_TXFIFO_WIDTH 8u
6664 #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_TXFIFO_SHIFT))&LPUART_PARAM_TXFIFO_MASK)
6665 #define LPUART_PARAM_RXFIFO_MASK 0xFF00u
6666 #define LPUART_PARAM_RXFIFO_SHIFT 8u
6667 #define LPUART_PARAM_RXFIFO_WIDTH 8u
6668 #define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PARAM_RXFIFO_SHIFT))&LPUART_PARAM_RXFIFO_MASK)
6669 /* GLOBAL Bit Fields */
6670 #define LPUART_GLOBAL_RST_MASK 0x2u
6671 #define LPUART_GLOBAL_RST_SHIFT 1u
6672 #define LPUART_GLOBAL_RST_WIDTH 1u
6673 #define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x))<<LPUART_GLOBAL_RST_SHIFT))&LPUART_GLOBAL_RST_MASK)
6674 /* PINCFG Bit Fields */
6675 #define LPUART_PINCFG_TRGSEL_MASK 0x3u
6676 #define LPUART_PINCFG_TRGSEL_SHIFT 0u
6677 #define LPUART_PINCFG_TRGSEL_WIDTH 2u
6678 #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_PINCFG_TRGSEL_SHIFT))&LPUART_PINCFG_TRGSEL_MASK)
6679 /* BAUD Bit Fields */
6680 #define LPUART_BAUD_SBR_MASK 0x1FFFu
6681 #define LPUART_BAUD_SBR_SHIFT 0u
6682 #define LPUART_BAUD_SBR_WIDTH 13u
6683 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
6684 #define LPUART_BAUD_SBNS_MASK 0x2000u
6685 #define LPUART_BAUD_SBNS_SHIFT 13u
6686 #define LPUART_BAUD_SBNS_WIDTH 1u
6687 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBNS_SHIFT))&LPUART_BAUD_SBNS_MASK)
6688 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
6689 #define LPUART_BAUD_RXEDGIE_SHIFT 14u
6690 #define LPUART_BAUD_RXEDGIE_WIDTH 1u
6691 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RXEDGIE_SHIFT))&LPUART_BAUD_RXEDGIE_MASK)
6692 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
6693 #define LPUART_BAUD_LBKDIE_SHIFT 15u
6694 #define LPUART_BAUD_LBKDIE_WIDTH 1u
6695 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_LBKDIE_SHIFT))&LPUART_BAUD_LBKDIE_MASK)
6696 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
6697 #define LPUART_BAUD_RESYNCDIS_SHIFT 16u
6698 #define LPUART_BAUD_RESYNCDIS_WIDTH 1u
6699 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RESYNCDIS_SHIFT))&LPUART_BAUD_RESYNCDIS_MASK)
6700 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
6701 #define LPUART_BAUD_BOTHEDGE_SHIFT 17u
6702 #define LPUART_BAUD_BOTHEDGE_WIDTH 1u
6703 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_BOTHEDGE_SHIFT))&LPUART_BAUD_BOTHEDGE_MASK)
6704 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
6705 #define LPUART_BAUD_MATCFG_SHIFT 18u
6706 #define LPUART_BAUD_MATCFG_WIDTH 2u
6707 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
6708 #define LPUART_BAUD_RIDMAE_MASK 0x100000u
6709 #define LPUART_BAUD_RIDMAE_SHIFT 20u
6710 #define LPUART_BAUD_RIDMAE_WIDTH 1u
6711 #define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RIDMAE_SHIFT))&LPUART_BAUD_RIDMAE_MASK)
6712 #define LPUART_BAUD_RDMAE_MASK 0x200000u
6713 #define LPUART_BAUD_RDMAE_SHIFT 21u
6714 #define LPUART_BAUD_RDMAE_WIDTH 1u
6715 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_RDMAE_SHIFT))&LPUART_BAUD_RDMAE_MASK)
6716 #define LPUART_BAUD_TDMAE_MASK 0x800000u
6717 #define LPUART_BAUD_TDMAE_SHIFT 23u
6718 #define LPUART_BAUD_TDMAE_WIDTH 1u
6719 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_TDMAE_SHIFT))&LPUART_BAUD_TDMAE_MASK)
6720 #define LPUART_BAUD_OSR_MASK 0x1F000000u
6721 #define LPUART_BAUD_OSR_SHIFT 24u
6722 #define LPUART_BAUD_OSR_WIDTH 5u
6723 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
6724 #define LPUART_BAUD_M10_MASK 0x20000000u
6725 #define LPUART_BAUD_M10_SHIFT 29u
6726 #define LPUART_BAUD_M10_WIDTH 1u
6727 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_M10_SHIFT))&LPUART_BAUD_M10_MASK)
6728 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
6729 #define LPUART_BAUD_MAEN2_SHIFT 30u
6730 #define LPUART_BAUD_MAEN2_WIDTH 1u
6731 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN2_SHIFT))&LPUART_BAUD_MAEN2_MASK)
6732 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
6733 #define LPUART_BAUD_MAEN1_SHIFT 31u
6734 #define LPUART_BAUD_MAEN1_WIDTH 1u
6735 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MAEN1_SHIFT))&LPUART_BAUD_MAEN1_MASK)
6736 /* STAT Bit Fields */
6737 #define LPUART_STAT_MA2F_MASK 0x4000u
6738 #define LPUART_STAT_MA2F_SHIFT 14u
6739 #define LPUART_STAT_MA2F_WIDTH 1u
6740 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA2F_SHIFT))&LPUART_STAT_MA2F_MASK)
6741 #define LPUART_STAT_MA1F_MASK 0x8000u
6742 #define LPUART_STAT_MA1F_SHIFT 15u
6743 #define LPUART_STAT_MA1F_WIDTH 1u
6744 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MA1F_SHIFT))&LPUART_STAT_MA1F_MASK)
6745 #define LPUART_STAT_PF_MASK 0x10000u
6746 #define LPUART_STAT_PF_SHIFT 16u
6747 #define LPUART_STAT_PF_WIDTH 1u
6748 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_PF_SHIFT))&LPUART_STAT_PF_MASK)
6749 #define LPUART_STAT_FE_MASK 0x20000u
6750 #define LPUART_STAT_FE_SHIFT 17u
6751 #define LPUART_STAT_FE_WIDTH 1u
6752 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_FE_SHIFT))&LPUART_STAT_FE_MASK)
6753 #define LPUART_STAT_NF_MASK 0x40000u
6754 #define LPUART_STAT_NF_SHIFT 18u
6755 #define LPUART_STAT_NF_WIDTH 1u
6756 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_NF_SHIFT))&LPUART_STAT_NF_MASK)
6757 #define LPUART_STAT_OR_MASK 0x80000u
6758 #define LPUART_STAT_OR_SHIFT 19u
6759 #define LPUART_STAT_OR_WIDTH 1u
6760 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_OR_SHIFT))&LPUART_STAT_OR_MASK)
6761 #define LPUART_STAT_IDLE_MASK 0x100000u
6762 #define LPUART_STAT_IDLE_SHIFT 20u
6763 #define LPUART_STAT_IDLE_WIDTH 1u
6764 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_IDLE_SHIFT))&LPUART_STAT_IDLE_MASK)
6765 #define LPUART_STAT_RDRF_MASK 0x200000u
6766 #define LPUART_STAT_RDRF_SHIFT 21u
6767 #define LPUART_STAT_RDRF_WIDTH 1u
6768 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RDRF_SHIFT))&LPUART_STAT_RDRF_MASK)
6769 #define LPUART_STAT_TC_MASK 0x400000u
6770 #define LPUART_STAT_TC_SHIFT 22u
6771 #define LPUART_STAT_TC_WIDTH 1u
6772 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TC_SHIFT))&LPUART_STAT_TC_MASK)
6773 #define LPUART_STAT_TDRE_MASK 0x800000u
6774 #define LPUART_STAT_TDRE_SHIFT 23u
6775 #define LPUART_STAT_TDRE_WIDTH 1u
6776 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_TDRE_SHIFT))&LPUART_STAT_TDRE_MASK)
6777 #define LPUART_STAT_RAF_MASK 0x1000000u
6778 #define LPUART_STAT_RAF_SHIFT 24u
6779 #define LPUART_STAT_RAF_WIDTH 1u
6780 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RAF_SHIFT))&LPUART_STAT_RAF_MASK)
6781 #define LPUART_STAT_LBKDE_MASK 0x2000000u
6782 #define LPUART_STAT_LBKDE_SHIFT 25u
6783 #define LPUART_STAT_LBKDE_WIDTH 1u
6784 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDE_SHIFT))&LPUART_STAT_LBKDE_MASK)
6785 #define LPUART_STAT_BRK13_MASK 0x4000000u
6786 #define LPUART_STAT_BRK13_SHIFT 26u
6787 #define LPUART_STAT_BRK13_WIDTH 1u
6788 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_BRK13_SHIFT))&LPUART_STAT_BRK13_MASK)
6789 #define LPUART_STAT_RWUID_MASK 0x8000000u
6790 #define LPUART_STAT_RWUID_SHIFT 27u
6791 #define LPUART_STAT_RWUID_WIDTH 1u
6792 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RWUID_SHIFT))&LPUART_STAT_RWUID_MASK)
6793 #define LPUART_STAT_RXINV_MASK 0x10000000u
6794 #define LPUART_STAT_RXINV_SHIFT 28u
6795 #define LPUART_STAT_RXINV_WIDTH 1u
6796 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXINV_SHIFT))&LPUART_STAT_RXINV_MASK)
6797 #define LPUART_STAT_MSBF_MASK 0x20000000u
6798 #define LPUART_STAT_MSBF_SHIFT 29u
6799 #define LPUART_STAT_MSBF_WIDTH 1u
6800 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_MSBF_SHIFT))&LPUART_STAT_MSBF_MASK)
6801 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
6802 #define LPUART_STAT_RXEDGIF_SHIFT 30u
6803 #define LPUART_STAT_RXEDGIF_WIDTH 1u
6804 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_RXEDGIF_SHIFT))&LPUART_STAT_RXEDGIF_MASK)
6805 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
6806 #define LPUART_STAT_LBKDIF_SHIFT 31u
6807 #define LPUART_STAT_LBKDIF_WIDTH 1u
6808 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_STAT_LBKDIF_SHIFT))&LPUART_STAT_LBKDIF_MASK)
6809 /* CTRL Bit Fields */
6810 #define LPUART_CTRL_PT_MASK 0x1u
6811 #define LPUART_CTRL_PT_SHIFT 0u
6812 #define LPUART_CTRL_PT_WIDTH 1u
6813 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PT_SHIFT))&LPUART_CTRL_PT_MASK)
6814 #define LPUART_CTRL_PE_MASK 0x2u
6815 #define LPUART_CTRL_PE_SHIFT 1u
6816 #define LPUART_CTRL_PE_WIDTH 1u
6817 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PE_SHIFT))&LPUART_CTRL_PE_MASK)
6818 #define LPUART_CTRL_ILT_MASK 0x4u
6819 #define LPUART_CTRL_ILT_SHIFT 2u
6820 #define LPUART_CTRL_ILT_WIDTH 1u
6821 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILT_SHIFT))&LPUART_CTRL_ILT_MASK)
6822 #define LPUART_CTRL_WAKE_MASK 0x8u
6823 #define LPUART_CTRL_WAKE_SHIFT 3u
6824 #define LPUART_CTRL_WAKE_WIDTH 1u
6825 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_WAKE_SHIFT))&LPUART_CTRL_WAKE_MASK)
6826 #define LPUART_CTRL_M_MASK 0x10u
6827 #define LPUART_CTRL_M_SHIFT 4u
6828 #define LPUART_CTRL_M_WIDTH 1u
6829 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M_SHIFT))&LPUART_CTRL_M_MASK)
6830 #define LPUART_CTRL_RSRC_MASK 0x20u
6831 #define LPUART_CTRL_RSRC_SHIFT 5u
6832 #define LPUART_CTRL_RSRC_WIDTH 1u
6833 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RSRC_SHIFT))&LPUART_CTRL_RSRC_MASK)
6834 #define LPUART_CTRL_DOZEEN_MASK 0x40u
6835 #define LPUART_CTRL_DOZEEN_SHIFT 6u
6836 #define LPUART_CTRL_DOZEEN_WIDTH 1u
6837 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_DOZEEN_SHIFT))&LPUART_CTRL_DOZEEN_MASK)
6838 #define LPUART_CTRL_LOOPS_MASK 0x80u
6839 #define LPUART_CTRL_LOOPS_SHIFT 7u
6840 #define LPUART_CTRL_LOOPS_WIDTH 1u
6841 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_LOOPS_SHIFT))&LPUART_CTRL_LOOPS_MASK)
6842 #define LPUART_CTRL_IDLECFG_MASK 0x700u
6843 #define LPUART_CTRL_IDLECFG_SHIFT 8u
6844 #define LPUART_CTRL_IDLECFG_WIDTH 3u
6845 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
6846 #define LPUART_CTRL_M7_MASK 0x800u
6847 #define LPUART_CTRL_M7_SHIFT 11u
6848 #define LPUART_CTRL_M7_WIDTH 1u
6849 #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_M7_SHIFT))&LPUART_CTRL_M7_MASK)
6850 #define LPUART_CTRL_MA2IE_MASK 0x4000u
6851 #define LPUART_CTRL_MA2IE_SHIFT 14u
6852 #define LPUART_CTRL_MA2IE_WIDTH 1u
6853 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA2IE_SHIFT))&LPUART_CTRL_MA2IE_MASK)
6854 #define LPUART_CTRL_MA1IE_MASK 0x8000u
6855 #define LPUART_CTRL_MA1IE_SHIFT 15u
6856 #define LPUART_CTRL_MA1IE_WIDTH 1u
6857 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_MA1IE_SHIFT))&LPUART_CTRL_MA1IE_MASK)
6858 #define LPUART_CTRL_SBK_MASK 0x10000u
6859 #define LPUART_CTRL_SBK_SHIFT 16u
6860 #define LPUART_CTRL_SBK_WIDTH 1u
6861 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_SBK_SHIFT))&LPUART_CTRL_SBK_MASK)
6862 #define LPUART_CTRL_RWU_MASK 0x20000u
6863 #define LPUART_CTRL_RWU_SHIFT 17u
6864 #define LPUART_CTRL_RWU_WIDTH 1u
6865 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RWU_SHIFT))&LPUART_CTRL_RWU_MASK)
6866 #define LPUART_CTRL_RE_MASK 0x40000u
6867 #define LPUART_CTRL_RE_SHIFT 18u
6868 #define LPUART_CTRL_RE_WIDTH 1u
6869 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RE_SHIFT))&LPUART_CTRL_RE_MASK)
6870 #define LPUART_CTRL_TE_MASK 0x80000u
6871 #define LPUART_CTRL_TE_SHIFT 19u
6872 #define LPUART_CTRL_TE_WIDTH 1u
6873 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TE_SHIFT))&LPUART_CTRL_TE_MASK)
6874 #define LPUART_CTRL_ILIE_MASK 0x100000u
6875 #define LPUART_CTRL_ILIE_SHIFT 20u
6876 #define LPUART_CTRL_ILIE_WIDTH 1u
6877 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ILIE_SHIFT))&LPUART_CTRL_ILIE_MASK)
6878 #define LPUART_CTRL_RIE_MASK 0x200000u
6879 #define LPUART_CTRL_RIE_SHIFT 21u
6880 #define LPUART_CTRL_RIE_WIDTH 1u
6881 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_RIE_SHIFT))&LPUART_CTRL_RIE_MASK)
6882 #define LPUART_CTRL_TCIE_MASK 0x400000u
6883 #define LPUART_CTRL_TCIE_SHIFT 22u
6884 #define LPUART_CTRL_TCIE_WIDTH 1u
6885 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TCIE_SHIFT))&LPUART_CTRL_TCIE_MASK)
6886 #define LPUART_CTRL_TIE_MASK 0x800000u
6887 #define LPUART_CTRL_TIE_SHIFT 23u
6888 #define LPUART_CTRL_TIE_WIDTH 1u
6889 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TIE_SHIFT))&LPUART_CTRL_TIE_MASK)
6890 #define LPUART_CTRL_PEIE_MASK 0x1000000u
6891 #define LPUART_CTRL_PEIE_SHIFT 24u
6892 #define LPUART_CTRL_PEIE_WIDTH 1u
6893 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_PEIE_SHIFT))&LPUART_CTRL_PEIE_MASK)
6894 #define LPUART_CTRL_FEIE_MASK 0x2000000u
6895 #define LPUART_CTRL_FEIE_SHIFT 25u
6896 #define LPUART_CTRL_FEIE_WIDTH 1u
6897 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_FEIE_SHIFT))&LPUART_CTRL_FEIE_MASK)
6898 #define LPUART_CTRL_NEIE_MASK 0x4000000u
6899 #define LPUART_CTRL_NEIE_SHIFT 26u
6900 #define LPUART_CTRL_NEIE_WIDTH 1u
6901 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_NEIE_SHIFT))&LPUART_CTRL_NEIE_MASK)
6902 #define LPUART_CTRL_ORIE_MASK 0x8000000u
6903 #define LPUART_CTRL_ORIE_SHIFT 27u
6904 #define LPUART_CTRL_ORIE_WIDTH 1u
6905 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_ORIE_SHIFT))&LPUART_CTRL_ORIE_MASK)
6906 #define LPUART_CTRL_TXINV_MASK 0x10000000u
6907 #define LPUART_CTRL_TXINV_SHIFT 28u
6908 #define LPUART_CTRL_TXINV_WIDTH 1u
6909 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXINV_SHIFT))&LPUART_CTRL_TXINV_MASK)
6910 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
6911 #define LPUART_CTRL_TXDIR_SHIFT 29u
6912 #define LPUART_CTRL_TXDIR_WIDTH 1u
6913 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_TXDIR_SHIFT))&LPUART_CTRL_TXDIR_MASK)
6914 #define LPUART_CTRL_R9T8_MASK 0x40000000u
6915 #define LPUART_CTRL_R9T8_SHIFT 30u
6916 #define LPUART_CTRL_R9T8_WIDTH 1u
6917 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R9T8_SHIFT))&LPUART_CTRL_R9T8_MASK)
6918 #define LPUART_CTRL_R8T9_MASK 0x80000000u
6919 #define LPUART_CTRL_R8T9_SHIFT 31u
6920 #define LPUART_CTRL_R8T9_WIDTH 1u
6921 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_R8T9_SHIFT))&LPUART_CTRL_R8T9_MASK)
6922 /* DATA Bit Fields */
6923 #define LPUART_DATA_R0T0_MASK 0x1u
6924 #define LPUART_DATA_R0T0_SHIFT 0u
6925 #define LPUART_DATA_R0T0_WIDTH 1u
6926 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R0T0_SHIFT))&LPUART_DATA_R0T0_MASK)
6927 #define LPUART_DATA_R1T1_MASK 0x2u
6928 #define LPUART_DATA_R1T1_SHIFT 1u
6929 #define LPUART_DATA_R1T1_WIDTH 1u
6930 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R1T1_SHIFT))&LPUART_DATA_R1T1_MASK)
6931 #define LPUART_DATA_R2T2_MASK 0x4u
6932 #define LPUART_DATA_R2T2_SHIFT 2u
6933 #define LPUART_DATA_R2T2_WIDTH 1u
6934 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R2T2_SHIFT))&LPUART_DATA_R2T2_MASK)
6935 #define LPUART_DATA_R3T3_MASK 0x8u
6936 #define LPUART_DATA_R3T3_SHIFT 3u
6937 #define LPUART_DATA_R3T3_WIDTH 1u
6938 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R3T3_SHIFT))&LPUART_DATA_R3T3_MASK)
6939 #define LPUART_DATA_R4T4_MASK 0x10u
6940 #define LPUART_DATA_R4T4_SHIFT 4u
6941 #define LPUART_DATA_R4T4_WIDTH 1u
6942 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R4T4_SHIFT))&LPUART_DATA_R4T4_MASK)
6943 #define LPUART_DATA_R5T5_MASK 0x20u
6944 #define LPUART_DATA_R5T5_SHIFT 5u
6945 #define LPUART_DATA_R5T5_WIDTH 1u
6946 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R5T5_SHIFT))&LPUART_DATA_R5T5_MASK)
6947 #define LPUART_DATA_R6T6_MASK 0x40u
6948 #define LPUART_DATA_R6T6_SHIFT 6u
6949 #define LPUART_DATA_R6T6_WIDTH 1u
6950 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R6T6_SHIFT))&LPUART_DATA_R6T6_MASK)
6951 #define LPUART_DATA_R7T7_MASK 0x80u
6952 #define LPUART_DATA_R7T7_SHIFT 7u
6953 #define LPUART_DATA_R7T7_WIDTH 1u
6954 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R7T7_SHIFT))&LPUART_DATA_R7T7_MASK)
6955 #define LPUART_DATA_R8T8_MASK 0x100u
6956 #define LPUART_DATA_R8T8_SHIFT 8u
6957 #define LPUART_DATA_R8T8_WIDTH 1u
6958 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R8T8_SHIFT))&LPUART_DATA_R8T8_MASK)
6959 #define LPUART_DATA_R9T9_MASK 0x200u
6960 #define LPUART_DATA_R9T9_SHIFT 9u
6961 #define LPUART_DATA_R9T9_WIDTH 1u
6962 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_R9T9_SHIFT))&LPUART_DATA_R9T9_MASK)
6963 #define LPUART_DATA_IDLINE_MASK 0x800u
6964 #define LPUART_DATA_IDLINE_SHIFT 11u
6965 #define LPUART_DATA_IDLINE_WIDTH 1u
6966 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_IDLINE_SHIFT))&LPUART_DATA_IDLINE_MASK)
6967 #define LPUART_DATA_RXEMPT_MASK 0x1000u
6968 #define LPUART_DATA_RXEMPT_SHIFT 12u
6969 #define LPUART_DATA_RXEMPT_WIDTH 1u
6970 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_RXEMPT_SHIFT))&LPUART_DATA_RXEMPT_MASK)
6971 #define LPUART_DATA_FRETSC_MASK 0x2000u
6972 #define LPUART_DATA_FRETSC_SHIFT 13u
6973 #define LPUART_DATA_FRETSC_WIDTH 1u
6974 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_FRETSC_SHIFT))&LPUART_DATA_FRETSC_MASK)
6975 #define LPUART_DATA_PARITYE_MASK 0x4000u
6976 #define LPUART_DATA_PARITYE_SHIFT 14u
6977 #define LPUART_DATA_PARITYE_WIDTH 1u
6978 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_PARITYE_SHIFT))&LPUART_DATA_PARITYE_MASK)
6979 #define LPUART_DATA_NOISY_MASK 0x8000u
6980 #define LPUART_DATA_NOISY_SHIFT 15u
6981 #define LPUART_DATA_NOISY_WIDTH 1u
6982 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x))<<LPUART_DATA_NOISY_SHIFT))&LPUART_DATA_NOISY_MASK)
6983 /* MATCH Bit Fields */
6984 #define LPUART_MATCH_MA1_MASK 0x3FFu
6985 #define LPUART_MATCH_MA1_SHIFT 0u
6986 #define LPUART_MATCH_MA1_WIDTH 10u
6987 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
6988 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
6989 #define LPUART_MATCH_MA2_SHIFT 16u
6990 #define LPUART_MATCH_MA2_WIDTH 10u
6991 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
6992 /* MODIR Bit Fields */
6993 #define LPUART_MODIR_TXCTSE_MASK 0x1u
6994 #define LPUART_MODIR_TXCTSE_SHIFT 0u
6995 #define LPUART_MODIR_TXCTSE_WIDTH 1u
6996 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSE_SHIFT))&LPUART_MODIR_TXCTSE_MASK)
6997 #define LPUART_MODIR_TXRTSE_MASK 0x2u
6998 #define LPUART_MODIR_TXRTSE_SHIFT 1u
6999 #define LPUART_MODIR_TXRTSE_WIDTH 1u
7000 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSE_SHIFT))&LPUART_MODIR_TXRTSE_MASK)
7001 #define LPUART_MODIR_TXRTSPOL_MASK 0x4u
7002 #define LPUART_MODIR_TXRTSPOL_SHIFT 2u
7003 #define LPUART_MODIR_TXRTSPOL_WIDTH 1u
7004 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXRTSPOL_SHIFT))&LPUART_MODIR_TXRTSPOL_MASK)
7005 #define LPUART_MODIR_RXRTSE_MASK 0x8u
7006 #define LPUART_MODIR_RXRTSE_SHIFT 3u
7007 #define LPUART_MODIR_RXRTSE_WIDTH 1u
7008 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RXRTSE_SHIFT))&LPUART_MODIR_RXRTSE_MASK)
7009 #define LPUART_MODIR_TXCTSC_MASK 0x10u
7010 #define LPUART_MODIR_TXCTSC_SHIFT 4u
7011 #define LPUART_MODIR_TXCTSC_WIDTH 1u
7012 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSC_SHIFT))&LPUART_MODIR_TXCTSC_MASK)
7013 #define LPUART_MODIR_TXCTSSRC_MASK 0x20u
7014 #define LPUART_MODIR_TXCTSSRC_SHIFT 5u
7015 #define LPUART_MODIR_TXCTSSRC_WIDTH 1u
7016 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TXCTSSRC_SHIFT))&LPUART_MODIR_TXCTSSRC_MASK)
7017 #define LPUART_MODIR_RTSWATER_MASK 0x300u
7018 #define LPUART_MODIR_RTSWATER_SHIFT 8u
7019 #define LPUART_MODIR_RTSWATER_WIDTH 2u
7020 #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_RTSWATER_SHIFT))&LPUART_MODIR_RTSWATER_MASK)
7021 #define LPUART_MODIR_TNP_MASK 0x30000u
7022 #define LPUART_MODIR_TNP_SHIFT 16u
7023 #define LPUART_MODIR_TNP_WIDTH 2u
7024 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
7025 #define LPUART_MODIR_IREN_MASK 0x40000u
7026 #define LPUART_MODIR_IREN_SHIFT 18u
7027 #define LPUART_MODIR_IREN_WIDTH 1u
7028 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_IREN_SHIFT))&LPUART_MODIR_IREN_MASK)
7029 /* FIFO Bit Fields */
7030 #define LPUART_FIFO_RXFIFOSIZE_MASK 0x7u
7031 #define LPUART_FIFO_RXFIFOSIZE_SHIFT 0u
7032 #define LPUART_FIFO_RXFIFOSIZE_WIDTH 3u
7033 #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFIFOSIZE_SHIFT))&LPUART_FIFO_RXFIFOSIZE_MASK)
7034 #define LPUART_FIFO_RXFE_MASK 0x8u
7035 #define LPUART_FIFO_RXFE_SHIFT 3u
7036 #define LPUART_FIFO_RXFE_WIDTH 1u
7037 #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFE_SHIFT))&LPUART_FIFO_RXFE_MASK)
7038 #define LPUART_FIFO_TXFIFOSIZE_MASK 0x70u
7039 #define LPUART_FIFO_TXFIFOSIZE_SHIFT 4u
7040 #define LPUART_FIFO_TXFIFOSIZE_WIDTH 3u
7041 #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFIFOSIZE_SHIFT))&LPUART_FIFO_TXFIFOSIZE_MASK)
7042 #define LPUART_FIFO_TXFE_MASK 0x80u
7043 #define LPUART_FIFO_TXFE_SHIFT 7u
7044 #define LPUART_FIFO_TXFE_WIDTH 1u
7045 #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFE_SHIFT))&LPUART_FIFO_TXFE_MASK)
7046 #define LPUART_FIFO_RXUFE_MASK 0x100u
7047 #define LPUART_FIFO_RXUFE_SHIFT 8u
7048 #define LPUART_FIFO_RXUFE_WIDTH 1u
7049 #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUFE_SHIFT))&LPUART_FIFO_RXUFE_MASK)
7050 #define LPUART_FIFO_TXOFE_MASK 0x200u
7051 #define LPUART_FIFO_TXOFE_SHIFT 9u
7052 #define LPUART_FIFO_TXOFE_WIDTH 1u
7053 #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOFE_SHIFT))&LPUART_FIFO_TXOFE_MASK)
7054 #define LPUART_FIFO_RXIDEN_MASK 0x1C00u
7055 #define LPUART_FIFO_RXIDEN_SHIFT 10u
7056 #define LPUART_FIFO_RXIDEN_WIDTH 3u
7057 #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXIDEN_SHIFT))&LPUART_FIFO_RXIDEN_MASK)
7058 #define LPUART_FIFO_RXFLUSH_MASK 0x4000u
7059 #define LPUART_FIFO_RXFLUSH_SHIFT 14u
7060 #define LPUART_FIFO_RXFLUSH_WIDTH 1u
7061 #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXFLUSH_SHIFT))&LPUART_FIFO_RXFLUSH_MASK)
7062 #define LPUART_FIFO_TXFLUSH_MASK 0x8000u
7063 #define LPUART_FIFO_TXFLUSH_SHIFT 15u
7064 #define LPUART_FIFO_TXFLUSH_WIDTH 1u
7065 #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXFLUSH_SHIFT))&LPUART_FIFO_TXFLUSH_MASK)
7066 #define LPUART_FIFO_RXUF_MASK 0x10000u
7067 #define LPUART_FIFO_RXUF_SHIFT 16u
7068 #define LPUART_FIFO_RXUF_WIDTH 1u
7069 #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXUF_SHIFT))&LPUART_FIFO_RXUF_MASK)
7070 #define LPUART_FIFO_TXOF_MASK 0x20000u
7071 #define LPUART_FIFO_TXOF_SHIFT 17u
7072 #define LPUART_FIFO_TXOF_WIDTH 1u
7073 #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXOF_SHIFT))&LPUART_FIFO_TXOF_MASK)
7074 #define LPUART_FIFO_RXEMPT_MASK 0x400000u
7075 #define LPUART_FIFO_RXEMPT_SHIFT 22u
7076 #define LPUART_FIFO_RXEMPT_WIDTH 1u
7077 #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_RXEMPT_SHIFT))&LPUART_FIFO_RXEMPT_MASK)
7078 #define LPUART_FIFO_TXEMPT_MASK 0x800000u
7079 #define LPUART_FIFO_TXEMPT_SHIFT 23u
7080 #define LPUART_FIFO_TXEMPT_WIDTH 1u
7081 #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_FIFO_TXEMPT_SHIFT))&LPUART_FIFO_TXEMPT_MASK)
7082 /* WATER Bit Fields */
7083 #define LPUART_WATER_TXWATER_MASK 0x3u
7084 #define LPUART_WATER_TXWATER_SHIFT 0u
7085 #define LPUART_WATER_TXWATER_WIDTH 2u
7086 #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXWATER_SHIFT))&LPUART_WATER_TXWATER_MASK)
7087 #define LPUART_WATER_TXCOUNT_MASK 0x700u
7088 #define LPUART_WATER_TXCOUNT_SHIFT 8u
7089 #define LPUART_WATER_TXCOUNT_WIDTH 3u
7090 #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_TXCOUNT_SHIFT))&LPUART_WATER_TXCOUNT_MASK)
7091 #define LPUART_WATER_RXWATER_MASK 0x30000u
7092 #define LPUART_WATER_RXWATER_SHIFT 16u
7093 #define LPUART_WATER_RXWATER_WIDTH 2u
7094 #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXWATER_SHIFT))&LPUART_WATER_RXWATER_MASK)
7095 #define LPUART_WATER_RXCOUNT_MASK 0x7000000u
7096 #define LPUART_WATER_RXCOUNT_SHIFT 24u
7097 #define LPUART_WATER_RXCOUNT_WIDTH 3u
7098 #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x))<<LPUART_WATER_RXCOUNT_SHIFT))&LPUART_WATER_RXCOUNT_MASK)
7099  /* end of group LPUART_Register_Masks */
7103 
7104  /* end of group LPUART_Peripheral_Access_Layer */
7108 
7109 
7110 /* ----------------------------------------------------------------------------
7111  -- MCM Peripheral Access Layer
7112  ---------------------------------------------------------------------------- */
7113 
7121 #define MCM_LMDR_COUNT 2u
7122 
7124 typedef struct {
7125  uint8_t RESERVED_0[8];
7126  __I uint16_t PLASC;
7127  __I uint16_t PLAMC;
7128  __IO uint32_t CPCR;
7129  __IO uint32_t ISCR;
7130  uint8_t RESERVED_1[28];
7131  __IO uint32_t PID;
7132  uint8_t RESERVED_2[12];
7133  __IO uint32_t CPO;
7134  uint8_t RESERVED_3[956];
7135  __IO uint32_t LMDR[MCM_LMDR_COUNT];
7136  __IO uint32_t LMDR2;
7137  uint8_t RESERVED_4[116];
7138  __IO uint32_t LMPECR;
7139  uint8_t RESERVED_5[4];
7140  __IO uint32_t LMPEIR;
7141  uint8_t RESERVED_6[4];
7142  __I uint32_t LMFAR;
7143  __I uint32_t LMFATR;
7144  uint8_t RESERVED_7[8];
7145  __I uint32_t LMFDHR;
7146  __I uint32_t LMFDLR;
7148 
7150 #define MCM_INSTANCE_COUNT (1u)
7151 
7152 
7153 /* MCM - Peripheral instance base addresses */
7155 #define MCM_BASE (0xE0080000u)
7156 
7157 #define MCM ((MCM_Type *)MCM_BASE)
7158 
7159 #define MCM_BASE_ADDRS { MCM_BASE }
7160 
7161 #define MCM_BASE_PTRS { MCM }
7162 
7163 #define MCM_IRQS_ARR_COUNT (1u)
7164 
7165 #define MCM_IRQS_CH_COUNT (1u)
7166 
7167 #define MCM_IRQS { MCM_IRQn }
7168 
7169 /* ----------------------------------------------------------------------------
7170  -- MCM Register Masks
7171  ---------------------------------------------------------------------------- */
7172 
7178 /* PLASC Bit Fields */
7179 #define MCM_PLASC_ASC_MASK 0xFFu
7180 #define MCM_PLASC_ASC_SHIFT 0u
7181 #define MCM_PLASC_ASC_WIDTH 8u
7182 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
7183 /* PLAMC Bit Fields */
7184 #define MCM_PLAMC_AMC_MASK 0xFFu
7185 #define MCM_PLAMC_AMC_SHIFT 0u
7186 #define MCM_PLAMC_AMC_WIDTH 8u
7187 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
7188 /* CPCR Bit Fields */
7189 #define MCM_CPCR_HLT_FSM_ST_MASK 0x3u
7190 #define MCM_CPCR_HLT_FSM_ST_SHIFT 0u
7191 #define MCM_CPCR_HLT_FSM_ST_WIDTH 2u
7192 #define MCM_CPCR_HLT_FSM_ST(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_HLT_FSM_ST_SHIFT))&MCM_CPCR_HLT_FSM_ST_MASK)
7193 #define MCM_CPCR_AXBS_HLT_REQ_MASK 0x4u
7194 #define MCM_CPCR_AXBS_HLT_REQ_SHIFT 2u
7195 #define MCM_CPCR_AXBS_HLT_REQ_WIDTH 1u
7196 #define MCM_CPCR_AXBS_HLT_REQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLT_REQ_SHIFT))&MCM_CPCR_AXBS_HLT_REQ_MASK)
7197 #define MCM_CPCR_AXBS_HLTD_MASK 0x8u
7198 #define MCM_CPCR_AXBS_HLTD_SHIFT 3u
7199 #define MCM_CPCR_AXBS_HLTD_WIDTH 1u
7200 #define MCM_CPCR_AXBS_HLTD(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_AXBS_HLTD_SHIFT))&MCM_CPCR_AXBS_HLTD_MASK)
7201 #define MCM_CPCR_FMC_PF_IDLE_MASK 0x10u
7202 #define MCM_CPCR_FMC_PF_IDLE_SHIFT 4u
7203 #define MCM_CPCR_FMC_PF_IDLE_WIDTH 1u
7204 #define MCM_CPCR_FMC_PF_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_FMC_PF_IDLE_SHIFT))&MCM_CPCR_FMC_PF_IDLE_MASK)
7205 #define MCM_CPCR_PBRIDGE_IDLE_MASK 0x40u
7206 #define MCM_CPCR_PBRIDGE_IDLE_SHIFT 6u
7207 #define MCM_CPCR_PBRIDGE_IDLE_WIDTH 1u
7208 #define MCM_CPCR_PBRIDGE_IDLE(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_PBRIDGE_IDLE_SHIFT))&MCM_CPCR_PBRIDGE_IDLE_MASK)
7209 #define MCM_CPCR_CBRR_MASK 0x200u
7210 #define MCM_CPCR_CBRR_SHIFT 9u
7211 #define MCM_CPCR_CBRR_WIDTH 1u
7212 #define MCM_CPCR_CBRR(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_CBRR_SHIFT))&MCM_CPCR_CBRR_MASK)
7213 #define MCM_CPCR_SRAMUAP_MASK 0x3000000u
7214 #define MCM_CPCR_SRAMUAP_SHIFT 24u
7215 #define MCM_CPCR_SRAMUAP_WIDTH 2u
7216 #define MCM_CPCR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUAP_SHIFT))&MCM_CPCR_SRAMUAP_MASK)
7217 #define MCM_CPCR_SRAMUWP_MASK 0x4000000u
7218 #define MCM_CPCR_SRAMUWP_SHIFT 26u
7219 #define MCM_CPCR_SRAMUWP_WIDTH 1u
7220 #define MCM_CPCR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMUWP_SHIFT))&MCM_CPCR_SRAMUWP_MASK)
7221 #define MCM_CPCR_SRAMLAP_MASK 0x30000000u
7222 #define MCM_CPCR_SRAMLAP_SHIFT 28u
7223 #define MCM_CPCR_SRAMLAP_WIDTH 2u
7224 #define MCM_CPCR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLAP_SHIFT))&MCM_CPCR_SRAMLAP_MASK)
7225 #define MCM_CPCR_SRAMLWP_MASK 0x40000000u
7226 #define MCM_CPCR_SRAMLWP_SHIFT 30u
7227 #define MCM_CPCR_SRAMLWP_WIDTH 1u
7228 #define MCM_CPCR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPCR_SRAMLWP_SHIFT))&MCM_CPCR_SRAMLWP_MASK)
7229 /* ISCR Bit Fields */
7230 #define MCM_ISCR_FIOC_MASK 0x100u
7231 #define MCM_ISCR_FIOC_SHIFT 8u
7232 #define MCM_ISCR_FIOC_WIDTH 1u
7233 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOC_SHIFT))&MCM_ISCR_FIOC_MASK)
7234 #define MCM_ISCR_FDZC_MASK 0x200u
7235 #define MCM_ISCR_FDZC_SHIFT 9u
7236 #define MCM_ISCR_FDZC_WIDTH 1u
7237 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZC_SHIFT))&MCM_ISCR_FDZC_MASK)
7238 #define MCM_ISCR_FOFC_MASK 0x400u
7239 #define MCM_ISCR_FOFC_SHIFT 10u
7240 #define MCM_ISCR_FOFC_WIDTH 1u
7241 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFC_SHIFT))&MCM_ISCR_FOFC_MASK)
7242 #define MCM_ISCR_FUFC_MASK 0x800u
7243 #define MCM_ISCR_FUFC_SHIFT 11u
7244 #define MCM_ISCR_FUFC_WIDTH 1u
7245 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFC_SHIFT))&MCM_ISCR_FUFC_MASK)
7246 #define MCM_ISCR_FIXC_MASK 0x1000u
7247 #define MCM_ISCR_FIXC_SHIFT 12u
7248 #define MCM_ISCR_FIXC_WIDTH 1u
7249 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXC_SHIFT))&MCM_ISCR_FIXC_MASK)
7250 #define MCM_ISCR_FIDC_MASK 0x8000u
7251 #define MCM_ISCR_FIDC_SHIFT 15u
7252 #define MCM_ISCR_FIDC_WIDTH 1u
7253 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDC_SHIFT))&MCM_ISCR_FIDC_MASK)
7254 #define MCM_ISCR_FIOCE_MASK 0x1000000u
7255 #define MCM_ISCR_FIOCE_SHIFT 24u
7256 #define MCM_ISCR_FIOCE_WIDTH 1u
7257 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIOCE_SHIFT))&MCM_ISCR_FIOCE_MASK)
7258 #define MCM_ISCR_FDZCE_MASK 0x2000000u
7259 #define MCM_ISCR_FDZCE_SHIFT 25u
7260 #define MCM_ISCR_FDZCE_WIDTH 1u
7261 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FDZCE_SHIFT))&MCM_ISCR_FDZCE_MASK)
7262 #define MCM_ISCR_FOFCE_MASK 0x4000000u
7263 #define MCM_ISCR_FOFCE_SHIFT 26u
7264 #define MCM_ISCR_FOFCE_WIDTH 1u
7265 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FOFCE_SHIFT))&MCM_ISCR_FOFCE_MASK)
7266 #define MCM_ISCR_FUFCE_MASK 0x8000000u
7267 #define MCM_ISCR_FUFCE_SHIFT 27u
7268 #define MCM_ISCR_FUFCE_WIDTH 1u
7269 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FUFCE_SHIFT))&MCM_ISCR_FUFCE_MASK)
7270 #define MCM_ISCR_FIXCE_MASK 0x10000000u
7271 #define MCM_ISCR_FIXCE_SHIFT 28u
7272 #define MCM_ISCR_FIXCE_WIDTH 1u
7273 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIXCE_SHIFT))&MCM_ISCR_FIXCE_MASK)
7274 #define MCM_ISCR_FIDCE_MASK 0x80000000u
7275 #define MCM_ISCR_FIDCE_SHIFT 31u
7276 #define MCM_ISCR_FIDCE_WIDTH 1u
7277 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x))<<MCM_ISCR_FIDCE_SHIFT))&MCM_ISCR_FIDCE_MASK)
7278 /* PID Bit Fields */
7279 #define MCM_PID_PID_MASK 0xFFu
7280 #define MCM_PID_PID_SHIFT 0u
7281 #define MCM_PID_PID_WIDTH 8u
7282 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
7283 /* CPO Bit Fields */
7284 #define MCM_CPO_CPOREQ_MASK 0x1u
7285 #define MCM_CPO_CPOREQ_SHIFT 0u
7286 #define MCM_CPO_CPOREQ_WIDTH 1u
7287 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOREQ_SHIFT))&MCM_CPO_CPOREQ_MASK)
7288 #define MCM_CPO_CPOACK_MASK 0x2u
7289 #define MCM_CPO_CPOACK_SHIFT 1u
7290 #define MCM_CPO_CPOACK_WIDTH 1u
7291 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOACK_SHIFT))&MCM_CPO_CPOACK_MASK)
7292 #define MCM_CPO_CPOWOI_MASK 0x4u
7293 #define MCM_CPO_CPOWOI_SHIFT 2u
7294 #define MCM_CPO_CPOWOI_WIDTH 1u
7295 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x))<<MCM_CPO_CPOWOI_SHIFT))&MCM_CPO_CPOWOI_MASK)
7296 /* LMDR Bit Fields */
7297 #define MCM_LMDR_CF0_MASK 0xFu
7298 #define MCM_LMDR_CF0_SHIFT 0u
7299 #define MCM_LMDR_CF0_WIDTH 4u
7300 #define MCM_LMDR_CF0(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF0_SHIFT))&MCM_LMDR_CF0_MASK)
7301 #define MCM_LMDR_CF1_MASK 0xF0u
7302 #define MCM_LMDR_CF1_SHIFT 4u
7303 #define MCM_LMDR_CF1_WIDTH 4u
7304 #define MCM_LMDR_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_CF1_SHIFT))&MCM_LMDR_CF1_MASK)
7305 #define MCM_LMDR_MT_MASK 0xE000u
7306 #define MCM_LMDR_MT_SHIFT 13u
7307 #define MCM_LMDR_MT_WIDTH 3u
7308 #define MCM_LMDR_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_MT_SHIFT))&MCM_LMDR_MT_MASK)
7309 #define MCM_LMDR_LOCK_MASK 0x10000u
7310 #define MCM_LMDR_LOCK_SHIFT 16u
7311 #define MCM_LMDR_LOCK_WIDTH 1u
7312 #define MCM_LMDR_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LOCK_SHIFT))&MCM_LMDR_LOCK_MASK)
7313 #define MCM_LMDR_DPW_MASK 0xE0000u
7314 #define MCM_LMDR_DPW_SHIFT 17u
7315 #define MCM_LMDR_DPW_WIDTH 3u
7316 #define MCM_LMDR_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_DPW_SHIFT))&MCM_LMDR_DPW_MASK)
7317 #define MCM_LMDR_WY_MASK 0xF00000u
7318 #define MCM_LMDR_WY_SHIFT 20u
7319 #define MCM_LMDR_WY_WIDTH 4u
7320 #define MCM_LMDR_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_WY_SHIFT))&MCM_LMDR_WY_MASK)
7321 #define MCM_LMDR_LMSZ_MASK 0xF000000u
7322 #define MCM_LMDR_LMSZ_SHIFT 24u
7323 #define MCM_LMDR_LMSZ_WIDTH 4u
7324 #define MCM_LMDR_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZ_SHIFT))&MCM_LMDR_LMSZ_MASK)
7325 #define MCM_LMDR_LMSZH_MASK 0x10000000u
7326 #define MCM_LMDR_LMSZH_SHIFT 28u
7327 #define MCM_LMDR_LMSZH_WIDTH 1u
7328 #define MCM_LMDR_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_LMSZH_SHIFT))&MCM_LMDR_LMSZH_MASK)
7329 #define MCM_LMDR_V_MASK 0x80000000u
7330 #define MCM_LMDR_V_SHIFT 31u
7331 #define MCM_LMDR_V_WIDTH 1u
7332 #define MCM_LMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR_V_SHIFT))&MCM_LMDR_V_MASK)
7333 /* LMDR2 Bit Fields */
7334 #define MCM_LMDR2_CF1_MASK 0xF0u
7335 #define MCM_LMDR2_CF1_SHIFT 4u
7336 #define MCM_LMDR2_CF1_WIDTH 4u
7337 #define MCM_LMDR2_CF1(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_CF1_SHIFT))&MCM_LMDR2_CF1_MASK)
7338 #define MCM_LMDR2_MT_MASK 0xE000u
7339 #define MCM_LMDR2_MT_SHIFT 13u
7340 #define MCM_LMDR2_MT_WIDTH 3u
7341 #define MCM_LMDR2_MT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_MT_SHIFT))&MCM_LMDR2_MT_MASK)
7342 #define MCM_LMDR2_LOCK_MASK 0x10000u
7343 #define MCM_LMDR2_LOCK_SHIFT 16u
7344 #define MCM_LMDR2_LOCK_WIDTH 1u
7345 #define MCM_LMDR2_LOCK(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LOCK_SHIFT))&MCM_LMDR2_LOCK_MASK)
7346 #define MCM_LMDR2_DPW_MASK 0xE0000u
7347 #define MCM_LMDR2_DPW_SHIFT 17u
7348 #define MCM_LMDR2_DPW_WIDTH 3u
7349 #define MCM_LMDR2_DPW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_DPW_SHIFT))&MCM_LMDR2_DPW_MASK)
7350 #define MCM_LMDR2_WY_MASK 0xF00000u
7351 #define MCM_LMDR2_WY_SHIFT 20u
7352 #define MCM_LMDR2_WY_WIDTH 4u
7353 #define MCM_LMDR2_WY(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_WY_SHIFT))&MCM_LMDR2_WY_MASK)
7354 #define MCM_LMDR2_LMSZ_MASK 0xF000000u
7355 #define MCM_LMDR2_LMSZ_SHIFT 24u
7356 #define MCM_LMDR2_LMSZ_WIDTH 4u
7357 #define MCM_LMDR2_LMSZ(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZ_SHIFT))&MCM_LMDR2_LMSZ_MASK)
7358 #define MCM_LMDR2_LMSZH_MASK 0x10000000u
7359 #define MCM_LMDR2_LMSZH_SHIFT 28u
7360 #define MCM_LMDR2_LMSZH_WIDTH 1u
7361 #define MCM_LMDR2_LMSZH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_LMSZH_SHIFT))&MCM_LMDR2_LMSZH_MASK)
7362 #define MCM_LMDR2_V_MASK 0x80000000u
7363 #define MCM_LMDR2_V_SHIFT 31u
7364 #define MCM_LMDR2_V_WIDTH 1u
7365 #define MCM_LMDR2_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMDR2_V_SHIFT))&MCM_LMDR2_V_MASK)
7366 /* LMPECR Bit Fields */
7367 #define MCM_LMPECR_ERNCR_MASK 0x1u
7368 #define MCM_LMPECR_ERNCR_SHIFT 0u
7369 #define MCM_LMPECR_ERNCR_WIDTH 1u
7370 #define MCM_LMPECR_ERNCR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ERNCR_SHIFT))&MCM_LMPECR_ERNCR_MASK)
7371 #define MCM_LMPECR_ER1BR_MASK 0x100u
7372 #define MCM_LMPECR_ER1BR_SHIFT 8u
7373 #define MCM_LMPECR_ER1BR_WIDTH 1u
7374 #define MCM_LMPECR_ER1BR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ER1BR_SHIFT))&MCM_LMPECR_ER1BR_MASK)
7375 #define MCM_LMPECR_ECPR_MASK 0x100000u
7376 #define MCM_LMPECR_ECPR_SHIFT 20u
7377 #define MCM_LMPECR_ECPR_WIDTH 1u
7378 #define MCM_LMPECR_ECPR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPECR_ECPR_SHIFT))&MCM_LMPECR_ECPR_MASK)
7379 /* LMPEIR Bit Fields */
7380 #define MCM_LMPEIR_ENC_MASK 0xFFu
7381 #define MCM_LMPEIR_ENC_SHIFT 0u
7382 #define MCM_LMPEIR_ENC_WIDTH 8u
7383 #define MCM_LMPEIR_ENC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_ENC_SHIFT))&MCM_LMPEIR_ENC_MASK)
7384 #define MCM_LMPEIR_E1B_MASK 0xFF00u
7385 #define MCM_LMPEIR_E1B_SHIFT 8u
7386 #define MCM_LMPEIR_E1B_WIDTH 8u
7387 #define MCM_LMPEIR_E1B(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_E1B_SHIFT))&MCM_LMPEIR_E1B_MASK)
7388 #define MCM_LMPEIR_PE_MASK 0xFF0000u
7389 #define MCM_LMPEIR_PE_SHIFT 16u
7390 #define MCM_LMPEIR_PE_WIDTH 8u
7391 #define MCM_LMPEIR_PE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PE_SHIFT))&MCM_LMPEIR_PE_MASK)
7392 #define MCM_LMPEIR_PEELOC_MASK 0x1F000000u
7393 #define MCM_LMPEIR_PEELOC_SHIFT 24u
7394 #define MCM_LMPEIR_PEELOC_WIDTH 5u
7395 #define MCM_LMPEIR_PEELOC(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_PEELOC_SHIFT))&MCM_LMPEIR_PEELOC_MASK)
7396 #define MCM_LMPEIR_V_MASK 0x80000000u
7397 #define MCM_LMPEIR_V_SHIFT 31u
7398 #define MCM_LMPEIR_V_WIDTH 1u
7399 #define MCM_LMPEIR_V(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMPEIR_V_SHIFT))&MCM_LMPEIR_V_MASK)
7400 /* LMFAR Bit Fields */
7401 #define MCM_LMFAR_EFADD_MASK 0xFFFFFFFFu
7402 #define MCM_LMFAR_EFADD_SHIFT 0u
7403 #define MCM_LMFAR_EFADD_WIDTH 32u
7404 #define MCM_LMFAR_EFADD(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFAR_EFADD_SHIFT))&MCM_LMFAR_EFADD_MASK)
7405 /* LMFATR Bit Fields */
7406 #define MCM_LMFATR_PEFPRT_MASK 0xFu
7407 #define MCM_LMFATR_PEFPRT_SHIFT 0u
7408 #define MCM_LMFATR_PEFPRT_WIDTH 4u
7409 #define MCM_LMFATR_PEFPRT(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFPRT_SHIFT))&MCM_LMFATR_PEFPRT_MASK)
7410 #define MCM_LMFATR_PEFSIZE_MASK 0x70u
7411 #define MCM_LMFATR_PEFSIZE_SHIFT 4u
7412 #define MCM_LMFATR_PEFSIZE_WIDTH 3u
7413 #define MCM_LMFATR_PEFSIZE(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFSIZE_SHIFT))&MCM_LMFATR_PEFSIZE_MASK)
7414 #define MCM_LMFATR_PEFW_MASK 0x80u
7415 #define MCM_LMFATR_PEFW_SHIFT 7u
7416 #define MCM_LMFATR_PEFW_WIDTH 1u
7417 #define MCM_LMFATR_PEFW(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFW_SHIFT))&MCM_LMFATR_PEFW_MASK)
7418 #define MCM_LMFATR_PEFMST_MASK 0xFF00u
7419 #define MCM_LMFATR_PEFMST_SHIFT 8u
7420 #define MCM_LMFATR_PEFMST_WIDTH 8u
7421 #define MCM_LMFATR_PEFMST(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_PEFMST_SHIFT))&MCM_LMFATR_PEFMST_MASK)
7422 #define MCM_LMFATR_OVR_MASK 0x80000000u
7423 #define MCM_LMFATR_OVR_SHIFT 31u
7424 #define MCM_LMFATR_OVR_WIDTH 1u
7425 #define MCM_LMFATR_OVR(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFATR_OVR_SHIFT))&MCM_LMFATR_OVR_MASK)
7426 /* LMFDHR Bit Fields */
7427 #define MCM_LMFDHR_PEFDH_MASK 0xFFFFFFFFu
7428 #define MCM_LMFDHR_PEFDH_SHIFT 0u
7429 #define MCM_LMFDHR_PEFDH_WIDTH 32u
7430 #define MCM_LMFDHR_PEFDH(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDHR_PEFDH_SHIFT))&MCM_LMFDHR_PEFDH_MASK)
7431 /* LMFDLR Bit Fields */
7432 #define MCM_LMFDLR_PEFDL_MASK 0xFFFFFFFFu
7433 #define MCM_LMFDLR_PEFDL_SHIFT 0u
7434 #define MCM_LMFDLR_PEFDL_WIDTH 32u
7435 #define MCM_LMFDLR_PEFDL(x) (((uint32_t)(((uint32_t)(x))<<MCM_LMFDLR_PEFDL_SHIFT))&MCM_LMFDLR_PEFDL_MASK)
7436  /* end of group MCM_Register_Masks */
7440 
7441  /* end of group MCM_Peripheral_Access_Layer */
7445 
7446 
7447 /* ----------------------------------------------------------------------------
7448  -- MPU Peripheral Access Layer
7449  ---------------------------------------------------------------------------- */
7450 
7458 #define MPU_EAR_EDR_COUNT 4u
7459 #define MPU_RGD_COUNT 8u
7460 #define MPU_RGDAAC_COUNT 8u
7461 
7463 typedef struct {
7464  __IO uint32_t CESR;
7465  uint8_t RESERVED_0[12];
7466  struct { /* offset: 0x10, array step: 0x8 */
7467  __I uint32_t EAR;
7470  __I uint32_t EDR;
7473  } EAR_EDR[MPU_EAR_EDR_COUNT];
7474  uint8_t RESERVED_1[976];
7475  struct { /* offset: 0x400, array step: 0x10 */
7476  __IO uint32_t WORD0;
7477  __IO uint32_t WORD1;
7478  __IO uint32_t WORD2;
7479  __IO uint32_t WORD3;
7480  } RGD[MPU_RGD_COUNT];
7481  uint8_t RESERVED_2[896];
7482  __IO uint32_t RGDAAC[MPU_RGDAAC_COUNT];
7486 
7488 #define MPU_INSTANCE_COUNT (1u)
7489 
7490 
7491 /* MPU - Peripheral instance base addresses */
7493 #define MPU_BASE (0x4000D000u)
7494 
7495 #define MPU ((MPU_Type *)MPU_BASE)
7496 
7497 #define MPU_BASE_ADDRS { MPU_BASE }
7498 
7499 #define MPU_BASE_PTRS { MPU }
7500 
7501 /* ----------------------------------------------------------------------------
7502  -- MPU Register Masks
7503  ---------------------------------------------------------------------------- */
7504 
7510 /* CESR Bit Fields */
7511 #define MPU_CESR_VLD_MASK 0x1u
7512 #define MPU_CESR_VLD_SHIFT 0u
7513 #define MPU_CESR_VLD_WIDTH 1u
7514 #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_VLD_SHIFT))&MPU_CESR_VLD_MASK)
7515 #define MPU_CESR_NRGD_MASK 0xF00u
7516 #define MPU_CESR_NRGD_SHIFT 8u
7517 #define MPU_CESR_NRGD_WIDTH 4u
7518 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
7519 #define MPU_CESR_NSP_MASK 0xF000u
7520 #define MPU_CESR_NSP_SHIFT 12u
7521 #define MPU_CESR_NSP_WIDTH 4u
7522 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
7523 #define MPU_CESR_HRL_MASK 0xF0000u
7524 #define MPU_CESR_HRL_SHIFT 16u
7525 #define MPU_CESR_HRL_WIDTH 4u
7526 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
7527 #define MPU_CESR_SPERR3_MASK 0x10000000u
7528 #define MPU_CESR_SPERR3_SHIFT 28u
7529 #define MPU_CESR_SPERR3_WIDTH 1u
7530 #define MPU_CESR_SPERR3(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR3_SHIFT))&MPU_CESR_SPERR3_MASK)
7531 #define MPU_CESR_SPERR2_MASK 0x20000000u
7532 #define MPU_CESR_SPERR2_SHIFT 29u
7533 #define MPU_CESR_SPERR2_WIDTH 1u
7534 #define MPU_CESR_SPERR2(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR2_SHIFT))&MPU_CESR_SPERR2_MASK)
7535 #define MPU_CESR_SPERR1_MASK 0x40000000u
7536 #define MPU_CESR_SPERR1_SHIFT 30u
7537 #define MPU_CESR_SPERR1_WIDTH 1u
7538 #define MPU_CESR_SPERR1(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR1_SHIFT))&MPU_CESR_SPERR1_MASK)
7539 #define MPU_CESR_SPERR0_MASK 0x80000000u
7540 #define MPU_CESR_SPERR0_SHIFT 31u
7541 #define MPU_CESR_SPERR0_WIDTH 1u
7542 #define MPU_CESR_SPERR0(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR0_SHIFT))&MPU_CESR_SPERR0_MASK)
7543 /* EAR Bit Fields */
7544 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
7545 #define MPU_EAR_EADDR_SHIFT 0u
7546 #define MPU_EAR_EADDR_WIDTH 32u
7547 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
7548 /* EDR Bit Fields */
7549 #define MPU_EDR_ERW_MASK 0x1u
7550 #define MPU_EDR_ERW_SHIFT 0u
7551 #define MPU_EDR_ERW_WIDTH 1u
7552 #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_ERW_SHIFT))&MPU_EDR_ERW_MASK)
7553 #define MPU_EDR_EATTR_MASK 0xEu
7554 #define MPU_EDR_EATTR_SHIFT 1u
7555 #define MPU_EDR_EATTR_WIDTH 3u
7556 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
7557 #define MPU_EDR_EMN_MASK 0xF0u
7558 #define MPU_EDR_EMN_SHIFT 4u
7559 #define MPU_EDR_EMN_WIDTH 4u
7560 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
7561 #define MPU_EDR_EPID_MASK 0xFF00u
7562 #define MPU_EDR_EPID_SHIFT 8u
7563 #define MPU_EDR_EPID_WIDTH 8u
7564 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
7565 #define MPU_EDR_EACD_MASK 0xFFFF0000u
7566 #define MPU_EDR_EACD_SHIFT 16u
7567 #define MPU_EDR_EACD_WIDTH 16u
7568 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
7569 /* RGD_WORD0 Bit Fields */
7570 #define MPU_RGD_WORD0_SRTADDR_MASK 0xFFFFFFE0u
7571 #define MPU_RGD_WORD0_SRTADDR_SHIFT 5u
7572 #define MPU_RGD_WORD0_SRTADDR_WIDTH 27u
7573 #define MPU_RGD_WORD0_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD0_SRTADDR_SHIFT))&MPU_RGD_WORD0_SRTADDR_MASK)
7574 /* RGD_WORD1 Bit Fields */
7575 #define MPU_RGD_WORD1_ENDADDR_MASK 0xFFFFFFE0u
7576 #define MPU_RGD_WORD1_ENDADDR_SHIFT 5u
7577 #define MPU_RGD_WORD1_ENDADDR_WIDTH 27u
7578 #define MPU_RGD_WORD1_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD1_ENDADDR_SHIFT))&MPU_RGD_WORD1_ENDADDR_MASK)
7579 /* RGD_WORD2 Bit Fields */
7580 #define MPU_RGD_WORD2_M0UM_MASK 0x7u
7581 #define MPU_RGD_WORD2_M0UM_SHIFT 0u
7582 #define MPU_RGD_WORD2_M0UM_WIDTH 3u
7583 #define MPU_RGD_WORD2_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0UM_SHIFT))&MPU_RGD_WORD2_M0UM_MASK)
7584 #define MPU_RGD_WORD2_M0SM_MASK 0x18u
7585 #define MPU_RGD_WORD2_M0SM_SHIFT 3u
7586 #define MPU_RGD_WORD2_M0SM_WIDTH 2u
7587 #define MPU_RGD_WORD2_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0SM_SHIFT))&MPU_RGD_WORD2_M0SM_MASK)
7588 #define MPU_RGD_WORD2_M0PE_MASK 0x20u
7589 #define MPU_RGD_WORD2_M0PE_SHIFT 5u
7590 #define MPU_RGD_WORD2_M0PE_WIDTH 1u
7591 #define MPU_RGD_WORD2_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M0PE_SHIFT))&MPU_RGD_WORD2_M0PE_MASK)
7592 #define MPU_RGD_WORD2_M1UM_MASK 0x1C0u
7593 #define MPU_RGD_WORD2_M1UM_SHIFT 6u
7594 #define MPU_RGD_WORD2_M1UM_WIDTH 3u
7595 #define MPU_RGD_WORD2_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1UM_SHIFT))&MPU_RGD_WORD2_M1UM_MASK)
7596 #define MPU_RGD_WORD2_M1SM_MASK 0x600u
7597 #define MPU_RGD_WORD2_M1SM_SHIFT 9u
7598 #define MPU_RGD_WORD2_M1SM_WIDTH 2u
7599 #define MPU_RGD_WORD2_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1SM_SHIFT))&MPU_RGD_WORD2_M1SM_MASK)
7600 #define MPU_RGD_WORD2_M1PE_MASK 0x800u
7601 #define MPU_RGD_WORD2_M1PE_SHIFT 11u
7602 #define MPU_RGD_WORD2_M1PE_WIDTH 1u
7603 #define MPU_RGD_WORD2_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M1PE_SHIFT))&MPU_RGD_WORD2_M1PE_MASK)
7604 #define MPU_RGD_WORD2_M2UM_MASK 0x7000u
7605 #define MPU_RGD_WORD2_M2UM_SHIFT 12u
7606 #define MPU_RGD_WORD2_M2UM_WIDTH 3u
7607 #define MPU_RGD_WORD2_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2UM_SHIFT))&MPU_RGD_WORD2_M2UM_MASK)
7608 #define MPU_RGD_WORD2_M2SM_MASK 0x18000u
7609 #define MPU_RGD_WORD2_M2SM_SHIFT 15u
7610 #define MPU_RGD_WORD2_M2SM_WIDTH 2u
7611 #define MPU_RGD_WORD2_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M2SM_SHIFT))&MPU_RGD_WORD2_M2SM_MASK)
7612 #define MPU_RGD_WORD2_M3UM_MASK 0x1C0000u
7613 #define MPU_RGD_WORD2_M3UM_SHIFT 18u
7614 #define MPU_RGD_WORD2_M3UM_WIDTH 3u
7615 #define MPU_RGD_WORD2_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3UM_SHIFT))&MPU_RGD_WORD2_M3UM_MASK)
7616 #define MPU_RGD_WORD2_M3SM_MASK 0x600000u
7617 #define MPU_RGD_WORD2_M3SM_SHIFT 21u
7618 #define MPU_RGD_WORD2_M3SM_WIDTH 2u
7619 #define MPU_RGD_WORD2_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M3SM_SHIFT))&MPU_RGD_WORD2_M3SM_MASK)
7620 #define MPU_RGD_WORD2_M4WE_MASK 0x1000000u
7621 #define MPU_RGD_WORD2_M4WE_SHIFT 24u
7622 #define MPU_RGD_WORD2_M4WE_WIDTH 1u
7623 #define MPU_RGD_WORD2_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4WE_SHIFT))&MPU_RGD_WORD2_M4WE_MASK)
7624 #define MPU_RGD_WORD2_M4RE_MASK 0x2000000u
7625 #define MPU_RGD_WORD2_M4RE_SHIFT 25u
7626 #define MPU_RGD_WORD2_M4RE_WIDTH 1u
7627 #define MPU_RGD_WORD2_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M4RE_SHIFT))&MPU_RGD_WORD2_M4RE_MASK)
7628 #define MPU_RGD_WORD2_M5WE_MASK 0x4000000u
7629 #define MPU_RGD_WORD2_M5WE_SHIFT 26u
7630 #define MPU_RGD_WORD2_M5WE_WIDTH 1u
7631 #define MPU_RGD_WORD2_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5WE_SHIFT))&MPU_RGD_WORD2_M5WE_MASK)
7632 #define MPU_RGD_WORD2_M5RE_MASK 0x8000000u
7633 #define MPU_RGD_WORD2_M5RE_SHIFT 27u
7634 #define MPU_RGD_WORD2_M5RE_WIDTH 1u
7635 #define MPU_RGD_WORD2_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M5RE_SHIFT))&MPU_RGD_WORD2_M5RE_MASK)
7636 #define MPU_RGD_WORD2_M6WE_MASK 0x10000000u
7637 #define MPU_RGD_WORD2_M6WE_SHIFT 28u
7638 #define MPU_RGD_WORD2_M6WE_WIDTH 1u
7639 #define MPU_RGD_WORD2_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6WE_SHIFT))&MPU_RGD_WORD2_M6WE_MASK)
7640 #define MPU_RGD_WORD2_M6RE_MASK 0x20000000u
7641 #define MPU_RGD_WORD2_M6RE_SHIFT 29u
7642 #define MPU_RGD_WORD2_M6RE_WIDTH 1u
7643 #define MPU_RGD_WORD2_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M6RE_SHIFT))&MPU_RGD_WORD2_M6RE_MASK)
7644 #define MPU_RGD_WORD2_M7WE_MASK 0x40000000u
7645 #define MPU_RGD_WORD2_M7WE_SHIFT 30u
7646 #define MPU_RGD_WORD2_M7WE_WIDTH 1u
7647 #define MPU_RGD_WORD2_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7WE_SHIFT))&MPU_RGD_WORD2_M7WE_MASK)
7648 #define MPU_RGD_WORD2_M7RE_MASK 0x80000000u
7649 #define MPU_RGD_WORD2_M7RE_SHIFT 31u
7650 #define MPU_RGD_WORD2_M7RE_WIDTH 1u
7651 #define MPU_RGD_WORD2_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD2_M7RE_SHIFT))&MPU_RGD_WORD2_M7RE_MASK)
7652 /* RGD_WORD3 Bit Fields */
7653 #define MPU_RGD_WORD3_VLD_MASK 0x1u
7654 #define MPU_RGD_WORD3_VLD_SHIFT 0u
7655 #define MPU_RGD_WORD3_VLD_WIDTH 1u
7656 #define MPU_RGD_WORD3_VLD(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_VLD_SHIFT))&MPU_RGD_WORD3_VLD_MASK)
7657 #define MPU_RGD_WORD3_PIDMASK_MASK 0xFF0000u
7658 #define MPU_RGD_WORD3_PIDMASK_SHIFT 16u
7659 #define MPU_RGD_WORD3_PIDMASK_WIDTH 8u
7660 #define MPU_RGD_WORD3_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PIDMASK_SHIFT))&MPU_RGD_WORD3_PIDMASK_MASK)
7661 #define MPU_RGD_WORD3_PID_MASK 0xFF000000u
7662 #define MPU_RGD_WORD3_PID_SHIFT 24u
7663 #define MPU_RGD_WORD3_PID_WIDTH 8u
7664 #define MPU_RGD_WORD3_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGD_WORD3_PID_SHIFT))&MPU_RGD_WORD3_PID_MASK)
7665 /* RGDAAC Bit Fields */
7666 #define MPU_RGDAAC_M0UM_MASK 0x7u
7667 #define MPU_RGDAAC_M0UM_SHIFT 0u
7668 #define MPU_RGDAAC_M0UM_WIDTH 3u
7669 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
7670 #define MPU_RGDAAC_M0SM_MASK 0x18u
7671 #define MPU_RGDAAC_M0SM_SHIFT 3u
7672 #define MPU_RGDAAC_M0SM_WIDTH 2u
7673 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
7674 #define MPU_RGDAAC_M0PE_MASK 0x20u
7675 #define MPU_RGDAAC_M0PE_SHIFT 5u
7676 #define MPU_RGDAAC_M0PE_WIDTH 1u
7677 #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0PE_SHIFT))&MPU_RGDAAC_M0PE_MASK)
7678 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
7679 #define MPU_RGDAAC_M1UM_SHIFT 6u
7680 #define MPU_RGDAAC_M1UM_WIDTH 3u
7681 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
7682 #define MPU_RGDAAC_M1SM_MASK 0x600u
7683 #define MPU_RGDAAC_M1SM_SHIFT 9u
7684 #define MPU_RGDAAC_M1SM_WIDTH 2u
7685 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
7686 #define MPU_RGDAAC_M1PE_MASK 0x800u
7687 #define MPU_RGDAAC_M1PE_SHIFT 11u
7688 #define MPU_RGDAAC_M1PE_WIDTH 1u
7689 #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1PE_SHIFT))&MPU_RGDAAC_M1PE_MASK)
7690 #define MPU_RGDAAC_M2UM_MASK 0x7000u
7691 #define MPU_RGDAAC_M2UM_SHIFT 12u
7692 #define MPU_RGDAAC_M2UM_WIDTH 3u
7693 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
7694 #define MPU_RGDAAC_M2SM_MASK 0x18000u
7695 #define MPU_RGDAAC_M2SM_SHIFT 15u
7696 #define MPU_RGDAAC_M2SM_WIDTH 2u
7697 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
7698 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
7699 #define MPU_RGDAAC_M3UM_SHIFT 18u
7700 #define MPU_RGDAAC_M3UM_WIDTH 3u
7701 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
7702 #define MPU_RGDAAC_M3SM_MASK 0x600000u
7703 #define MPU_RGDAAC_M3SM_SHIFT 21u
7704 #define MPU_RGDAAC_M3SM_WIDTH 2u
7705 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
7706 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
7707 #define MPU_RGDAAC_M4WE_SHIFT 24u
7708 #define MPU_RGDAAC_M4WE_WIDTH 1u
7709 #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4WE_SHIFT))&MPU_RGDAAC_M4WE_MASK)
7710 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
7711 #define MPU_RGDAAC_M4RE_SHIFT 25u
7712 #define MPU_RGDAAC_M4RE_WIDTH 1u
7713 #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M4RE_SHIFT))&MPU_RGDAAC_M4RE_MASK)
7714 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
7715 #define MPU_RGDAAC_M5WE_SHIFT 26u
7716 #define MPU_RGDAAC_M5WE_WIDTH 1u
7717 #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5WE_SHIFT))&MPU_RGDAAC_M5WE_MASK)
7718 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
7719 #define MPU_RGDAAC_M5RE_SHIFT 27u
7720 #define MPU_RGDAAC_M5RE_WIDTH 1u
7721 #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M5RE_SHIFT))&MPU_RGDAAC_M5RE_MASK)
7722 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
7723 #define MPU_RGDAAC_M6WE_SHIFT 28u
7724 #define MPU_RGDAAC_M6WE_WIDTH 1u
7725 #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6WE_SHIFT))&MPU_RGDAAC_M6WE_MASK)
7726 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
7727 #define MPU_RGDAAC_M6RE_SHIFT 29u
7728 #define MPU_RGDAAC_M6RE_WIDTH 1u
7729 #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M6RE_SHIFT))&MPU_RGDAAC_M6RE_MASK)
7730 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
7731 #define MPU_RGDAAC_M7WE_SHIFT 30u
7732 #define MPU_RGDAAC_M7WE_WIDTH 1u
7733 #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7WE_SHIFT))&MPU_RGDAAC_M7WE_MASK)
7734 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
7735 #define MPU_RGDAAC_M7RE_SHIFT 31u
7736 #define MPU_RGDAAC_M7RE_WIDTH 1u
7737 #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M7RE_SHIFT))&MPU_RGDAAC_M7RE_MASK)
7738  /* end of group MPU_Register_Masks */
7742 
7743  /* end of group MPU_Peripheral_Access_Layer */
7747 
7748 
7749 /* ----------------------------------------------------------------------------
7750  -- MSCM Peripheral Access Layer
7751  ---------------------------------------------------------------------------- */
7752 
7760 #define MSCM_OCMDR_COUNT 4u
7761 
7763 typedef struct {
7764  __I uint32_t CPxTYPE;
7765  __I uint32_t CPxNUM;
7766  __I uint32_t CPxMASTER;
7767  __I uint32_t CPxCOUNT;
7768  __I uint32_t CPxCFG0;
7769  __I uint32_t CPxCFG1;
7770  __I uint32_t CPxCFG2;
7771  __I uint32_t CPxCFG3;
7772  __I uint32_t CP0TYPE;
7773  __I uint32_t CP0NUM;
7774  __I uint32_t CP0MASTER;
7775  __I uint32_t CP0COUNT;
7776  __I uint32_t CP0CFG0;
7777  __I uint32_t CP0CFG1;
7778  __I uint32_t CP0CFG2;
7779  __I uint32_t CP0CFG3;
7780  uint8_t RESERVED_0[960];
7781  __IO uint32_t OCMDR[MSCM_OCMDR_COUNT];
7783 
7785 #define MSCM_INSTANCE_COUNT (1u)
7786 
7787 
7788 /* MSCM - Peripheral instance base addresses */
7790 #define MSCM_BASE (0x40001000u)
7791 
7792 #define MSCM ((MSCM_Type *)MSCM_BASE)
7793 
7794 #define MSCM_BASE_ADDRS { MSCM_BASE }
7795 
7796 #define MSCM_BASE_PTRS { MSCM }
7797 
7798 /* ----------------------------------------------------------------------------
7799  -- MSCM Register Masks
7800  ---------------------------------------------------------------------------- */
7801 
7807 /* CPxTYPE Bit Fields */
7808 #define MSCM_CPxTYPE_RYPZ_MASK 0xFFu
7809 #define MSCM_CPxTYPE_RYPZ_SHIFT 0u
7810 #define MSCM_CPxTYPE_RYPZ_WIDTH 8u
7811 #define MSCM_CPxTYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_RYPZ_SHIFT))&MSCM_CPxTYPE_RYPZ_MASK)
7812 #define MSCM_CPxTYPE_PERSONALITY_MASK 0xFFFFFF00u
7813 #define MSCM_CPxTYPE_PERSONALITY_SHIFT 8u
7814 #define MSCM_CPxTYPE_PERSONALITY_WIDTH 24u
7815 #define MSCM_CPxTYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxTYPE_PERSONALITY_SHIFT))&MSCM_CPxTYPE_PERSONALITY_MASK)
7816 /* CPxNUM Bit Fields */
7817 #define MSCM_CPxNUM_CPN_MASK 0x1u
7818 #define MSCM_CPxNUM_CPN_SHIFT 0u
7819 #define MSCM_CPxNUM_CPN_WIDTH 1u
7820 #define MSCM_CPxNUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxNUM_CPN_SHIFT))&MSCM_CPxNUM_CPN_MASK)
7821 /* CPxMASTER Bit Fields */
7822 #define MSCM_CPxMASTER_PPMN_MASK 0x3Fu
7823 #define MSCM_CPxMASTER_PPMN_SHIFT 0u
7824 #define MSCM_CPxMASTER_PPMN_WIDTH 6u
7825 #define MSCM_CPxMASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxMASTER_PPMN_SHIFT))&MSCM_CPxMASTER_PPMN_MASK)
7826 /* CPxCOUNT Bit Fields */
7827 #define MSCM_CPxCOUNT_PCNT_MASK 0x3u
7828 #define MSCM_CPxCOUNT_PCNT_SHIFT 0u
7829 #define MSCM_CPxCOUNT_PCNT_WIDTH 2u
7830 #define MSCM_CPxCOUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCOUNT_PCNT_SHIFT))&MSCM_CPxCOUNT_PCNT_MASK)
7831 /* CPxCFG0 Bit Fields */
7832 #define MSCM_CPxCFG0_DCWY_MASK 0xFFu
7833 #define MSCM_CPxCFG0_DCWY_SHIFT 0u
7834 #define MSCM_CPxCFG0_DCWY_WIDTH 8u
7835 #define MSCM_CPxCFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCWY_SHIFT))&MSCM_CPxCFG0_DCWY_MASK)
7836 #define MSCM_CPxCFG0_DCSZ_MASK 0xFF00u
7837 #define MSCM_CPxCFG0_DCSZ_SHIFT 8u
7838 #define MSCM_CPxCFG0_DCSZ_WIDTH 8u
7839 #define MSCM_CPxCFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_DCSZ_SHIFT))&MSCM_CPxCFG0_DCSZ_MASK)
7840 #define MSCM_CPxCFG0_ICWY_MASK 0xFF0000u
7841 #define MSCM_CPxCFG0_ICWY_SHIFT 16u
7842 #define MSCM_CPxCFG0_ICWY_WIDTH 8u
7843 #define MSCM_CPxCFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICWY_SHIFT))&MSCM_CPxCFG0_ICWY_MASK)
7844 #define MSCM_CPxCFG0_ICSZ_MASK 0xFF000000u
7845 #define MSCM_CPxCFG0_ICSZ_SHIFT 24u
7846 #define MSCM_CPxCFG0_ICSZ_WIDTH 8u
7847 #define MSCM_CPxCFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG0_ICSZ_SHIFT))&MSCM_CPxCFG0_ICSZ_MASK)
7848 /* CPxCFG1 Bit Fields */
7849 #define MSCM_CPxCFG1_L2WY_MASK 0xFF0000u
7850 #define MSCM_CPxCFG1_L2WY_SHIFT 16u
7851 #define MSCM_CPxCFG1_L2WY_WIDTH 8u
7852 #define MSCM_CPxCFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2WY_SHIFT))&MSCM_CPxCFG1_L2WY_MASK)
7853 #define MSCM_CPxCFG1_L2SZ_MASK 0xFF000000u
7854 #define MSCM_CPxCFG1_L2SZ_SHIFT 24u
7855 #define MSCM_CPxCFG1_L2SZ_WIDTH 8u
7856 #define MSCM_CPxCFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG1_L2SZ_SHIFT))&MSCM_CPxCFG1_L2SZ_MASK)
7857 /* CPxCFG2 Bit Fields */
7858 #define MSCM_CPxCFG2_TMUSZ_MASK 0xFF00u
7859 #define MSCM_CPxCFG2_TMUSZ_SHIFT 8u
7860 #define MSCM_CPxCFG2_TMUSZ_WIDTH 8u
7861 #define MSCM_CPxCFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMUSZ_SHIFT))&MSCM_CPxCFG2_TMUSZ_MASK)
7862 #define MSCM_CPxCFG2_TMLSZ_MASK 0xFF000000u
7863 #define MSCM_CPxCFG2_TMLSZ_SHIFT 24u
7864 #define MSCM_CPxCFG2_TMLSZ_WIDTH 8u
7865 #define MSCM_CPxCFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG2_TMLSZ_SHIFT))&MSCM_CPxCFG2_TMLSZ_MASK)
7866 /* CPxCFG3 Bit Fields */
7867 #define MSCM_CPxCFG3_FPU_MASK 0x1u
7868 #define MSCM_CPxCFG3_FPU_SHIFT 0u
7869 #define MSCM_CPxCFG3_FPU_WIDTH 1u
7870 #define MSCM_CPxCFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_FPU_SHIFT))&MSCM_CPxCFG3_FPU_MASK)
7871 #define MSCM_CPxCFG3_SIMD_MASK 0x2u
7872 #define MSCM_CPxCFG3_SIMD_SHIFT 1u
7873 #define MSCM_CPxCFG3_SIMD_WIDTH 1u
7874 #define MSCM_CPxCFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SIMD_SHIFT))&MSCM_CPxCFG3_SIMD_MASK)
7875 #define MSCM_CPxCFG3_JAZ_MASK 0x4u
7876 #define MSCM_CPxCFG3_JAZ_SHIFT 2u
7877 #define MSCM_CPxCFG3_JAZ_WIDTH 1u
7878 #define MSCM_CPxCFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_JAZ_SHIFT))&MSCM_CPxCFG3_JAZ_MASK)
7879 #define MSCM_CPxCFG3_MMU_MASK 0x8u
7880 #define MSCM_CPxCFG3_MMU_SHIFT 3u
7881 #define MSCM_CPxCFG3_MMU_WIDTH 1u
7882 #define MSCM_CPxCFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_MMU_SHIFT))&MSCM_CPxCFG3_MMU_MASK)
7883 #define MSCM_CPxCFG3_TZ_MASK 0x10u
7884 #define MSCM_CPxCFG3_TZ_SHIFT 4u
7885 #define MSCM_CPxCFG3_TZ_WIDTH 1u
7886 #define MSCM_CPxCFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_TZ_SHIFT))&MSCM_CPxCFG3_TZ_MASK)
7887 #define MSCM_CPxCFG3_CMP_MASK 0x20u
7888 #define MSCM_CPxCFG3_CMP_SHIFT 5u
7889 #define MSCM_CPxCFG3_CMP_WIDTH 1u
7890 #define MSCM_CPxCFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_CMP_SHIFT))&MSCM_CPxCFG3_CMP_MASK)
7891 #define MSCM_CPxCFG3_BB_MASK 0x40u
7892 #define MSCM_CPxCFG3_BB_SHIFT 6u
7893 #define MSCM_CPxCFG3_BB_WIDTH 1u
7894 #define MSCM_CPxCFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_BB_SHIFT))&MSCM_CPxCFG3_BB_MASK)
7895 #define MSCM_CPxCFG3_SBP_MASK 0x300u
7896 #define MSCM_CPxCFG3_SBP_SHIFT 8u
7897 #define MSCM_CPxCFG3_SBP_WIDTH 2u
7898 #define MSCM_CPxCFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CPxCFG3_SBP_SHIFT))&MSCM_CPxCFG3_SBP_MASK)
7899 /* CP0TYPE Bit Fields */
7900 #define MSCM_CP0TYPE_RYPZ_MASK 0xFFu
7901 #define MSCM_CP0TYPE_RYPZ_SHIFT 0u
7902 #define MSCM_CP0TYPE_RYPZ_WIDTH 8u
7903 #define MSCM_CP0TYPE_RYPZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_RYPZ_SHIFT))&MSCM_CP0TYPE_RYPZ_MASK)
7904 #define MSCM_CP0TYPE_PERSONALITY_MASK 0xFFFFFF00u
7905 #define MSCM_CP0TYPE_PERSONALITY_SHIFT 8u
7906 #define MSCM_CP0TYPE_PERSONALITY_WIDTH 24u
7907 #define MSCM_CP0TYPE_PERSONALITY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0TYPE_PERSONALITY_SHIFT))&MSCM_CP0TYPE_PERSONALITY_MASK)
7908 /* CP0NUM Bit Fields */
7909 #define MSCM_CP0NUM_CPN_MASK 0x1u
7910 #define MSCM_CP0NUM_CPN_SHIFT 0u
7911 #define MSCM_CP0NUM_CPN_WIDTH 1u
7912 #define MSCM_CP0NUM_CPN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0NUM_CPN_SHIFT))&MSCM_CP0NUM_CPN_MASK)
7913 /* CP0MASTER Bit Fields */
7914 #define MSCM_CP0MASTER_PPMN_MASK 0x3Fu
7915 #define MSCM_CP0MASTER_PPMN_SHIFT 0u
7916 #define MSCM_CP0MASTER_PPMN_WIDTH 6u
7917 #define MSCM_CP0MASTER_PPMN(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0MASTER_PPMN_SHIFT))&MSCM_CP0MASTER_PPMN_MASK)
7918 /* CP0COUNT Bit Fields */
7919 #define MSCM_CP0COUNT_PCNT_MASK 0x3u
7920 #define MSCM_CP0COUNT_PCNT_SHIFT 0u
7921 #define MSCM_CP0COUNT_PCNT_WIDTH 2u
7922 #define MSCM_CP0COUNT_PCNT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0COUNT_PCNT_SHIFT))&MSCM_CP0COUNT_PCNT_MASK)
7923 /* CP0CFG0 Bit Fields */
7924 #define MSCM_CP0CFG0_DCWY_MASK 0xFFu
7925 #define MSCM_CP0CFG0_DCWY_SHIFT 0u
7926 #define MSCM_CP0CFG0_DCWY_WIDTH 8u
7927 #define MSCM_CP0CFG0_DCWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCWY_SHIFT))&MSCM_CP0CFG0_DCWY_MASK)
7928 #define MSCM_CP0CFG0_DCSZ_MASK 0xFF00u
7929 #define MSCM_CP0CFG0_DCSZ_SHIFT 8u
7930 #define MSCM_CP0CFG0_DCSZ_WIDTH 8u
7931 #define MSCM_CP0CFG0_DCSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_DCSZ_SHIFT))&MSCM_CP0CFG0_DCSZ_MASK)
7932 #define MSCM_CP0CFG0_ICWY_MASK 0xFF0000u
7933 #define MSCM_CP0CFG0_ICWY_SHIFT 16u
7934 #define MSCM_CP0CFG0_ICWY_WIDTH 8u
7935 #define MSCM_CP0CFG0_ICWY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICWY_SHIFT))&MSCM_CP0CFG0_ICWY_MASK)
7936 #define MSCM_CP0CFG0_ICSZ_MASK 0xFF000000u
7937 #define MSCM_CP0CFG0_ICSZ_SHIFT 24u
7938 #define MSCM_CP0CFG0_ICSZ_WIDTH 8u
7939 #define MSCM_CP0CFG0_ICSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG0_ICSZ_SHIFT))&MSCM_CP0CFG0_ICSZ_MASK)
7940 /* CP0CFG1 Bit Fields */
7941 #define MSCM_CP0CFG1_L2WY_MASK 0xFF0000u
7942 #define MSCM_CP0CFG1_L2WY_SHIFT 16u
7943 #define MSCM_CP0CFG1_L2WY_WIDTH 8u
7944 #define MSCM_CP0CFG1_L2WY(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2WY_SHIFT))&MSCM_CP0CFG1_L2WY_MASK)
7945 #define MSCM_CP0CFG1_L2SZ_MASK 0xFF000000u
7946 #define MSCM_CP0CFG1_L2SZ_SHIFT 24u
7947 #define MSCM_CP0CFG1_L2SZ_WIDTH 8u
7948 #define MSCM_CP0CFG1_L2SZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG1_L2SZ_SHIFT))&MSCM_CP0CFG1_L2SZ_MASK)
7949 /* CP0CFG2 Bit Fields */
7950 #define MSCM_CP0CFG2_TMUSZ_MASK 0xFF00u
7951 #define MSCM_CP0CFG2_TMUSZ_SHIFT 8u
7952 #define MSCM_CP0CFG2_TMUSZ_WIDTH 8u
7953 #define MSCM_CP0CFG2_TMUSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMUSZ_SHIFT))&MSCM_CP0CFG2_TMUSZ_MASK)
7954 #define MSCM_CP0CFG2_TMLSZ_MASK 0xFF000000u
7955 #define MSCM_CP0CFG2_TMLSZ_SHIFT 24u
7956 #define MSCM_CP0CFG2_TMLSZ_WIDTH 8u
7957 #define MSCM_CP0CFG2_TMLSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG2_TMLSZ_SHIFT))&MSCM_CP0CFG2_TMLSZ_MASK)
7958 /* CP0CFG3 Bit Fields */
7959 #define MSCM_CP0CFG3_FPU_MASK 0x1u
7960 #define MSCM_CP0CFG3_FPU_SHIFT 0u
7961 #define MSCM_CP0CFG3_FPU_WIDTH 1u
7962 #define MSCM_CP0CFG3_FPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_FPU_SHIFT))&MSCM_CP0CFG3_FPU_MASK)
7963 #define MSCM_CP0CFG3_SIMD_MASK 0x2u
7964 #define MSCM_CP0CFG3_SIMD_SHIFT 1u
7965 #define MSCM_CP0CFG3_SIMD_WIDTH 1u
7966 #define MSCM_CP0CFG3_SIMD(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SIMD_SHIFT))&MSCM_CP0CFG3_SIMD_MASK)
7967 #define MSCM_CP0CFG3_JAZ_MASK 0x4u
7968 #define MSCM_CP0CFG3_JAZ_SHIFT 2u
7969 #define MSCM_CP0CFG3_JAZ_WIDTH 1u
7970 #define MSCM_CP0CFG3_JAZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_JAZ_SHIFT))&MSCM_CP0CFG3_JAZ_MASK)
7971 #define MSCM_CP0CFG3_MMU_MASK 0x8u
7972 #define MSCM_CP0CFG3_MMU_SHIFT 3u
7973 #define MSCM_CP0CFG3_MMU_WIDTH 1u
7974 #define MSCM_CP0CFG3_MMU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_MMU_SHIFT))&MSCM_CP0CFG3_MMU_MASK)
7975 #define MSCM_CP0CFG3_TZ_MASK 0x10u
7976 #define MSCM_CP0CFG3_TZ_SHIFT 4u
7977 #define MSCM_CP0CFG3_TZ_WIDTH 1u
7978 #define MSCM_CP0CFG3_TZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_TZ_SHIFT))&MSCM_CP0CFG3_TZ_MASK)
7979 #define MSCM_CP0CFG3_CMP_MASK 0x20u
7980 #define MSCM_CP0CFG3_CMP_SHIFT 5u
7981 #define MSCM_CP0CFG3_CMP_WIDTH 1u
7982 #define MSCM_CP0CFG3_CMP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_CMP_SHIFT))&MSCM_CP0CFG3_CMP_MASK)
7983 #define MSCM_CP0CFG3_BB_MASK 0x40u
7984 #define MSCM_CP0CFG3_BB_SHIFT 6u
7985 #define MSCM_CP0CFG3_BB_WIDTH 1u
7986 #define MSCM_CP0CFG3_BB(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_BB_SHIFT))&MSCM_CP0CFG3_BB_MASK)
7987 #define MSCM_CP0CFG3_SBP_MASK 0x300u
7988 #define MSCM_CP0CFG3_SBP_SHIFT 8u
7989 #define MSCM_CP0CFG3_SBP_WIDTH 2u
7990 #define MSCM_CP0CFG3_SBP(x) (((uint32_t)(((uint32_t)(x))<<MSCM_CP0CFG3_SBP_SHIFT))&MSCM_CP0CFG3_SBP_MASK)
7991 /* OCMDR Bit Fields */
7992 #define MSCM_OCMDR_OCM0_MASK 0xFu
7993 #define MSCM_OCMDR_OCM0_SHIFT 0u
7994 #define MSCM_OCMDR_OCM0_WIDTH 4u
7995 #define MSCM_OCMDR_OCM0(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM0_SHIFT))&MSCM_OCMDR_OCM0_MASK)
7996 #define MSCM_OCMDR_OCM1_MASK 0xF0u
7997 #define MSCM_OCMDR_OCM1_SHIFT 4u
7998 #define MSCM_OCMDR_OCM1_WIDTH 4u
7999 #define MSCM_OCMDR_OCM1(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM1_SHIFT))&MSCM_OCMDR_OCM1_MASK)
8000 #define MSCM_OCMDR_OCM2_MASK 0xF00u
8001 #define MSCM_OCMDR_OCM2_SHIFT 8u
8002 #define MSCM_OCMDR_OCM2_WIDTH 4u
8003 #define MSCM_OCMDR_OCM2(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCM2_SHIFT))&MSCM_OCMDR_OCM2_MASK)
8004 #define MSCM_OCMDR_OCMPU_MASK 0x1000u
8005 #define MSCM_OCMDR_OCMPU_SHIFT 12u
8006 #define MSCM_OCMDR_OCMPU_WIDTH 1u
8007 #define MSCM_OCMDR_OCMPU(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMPU_SHIFT))&MSCM_OCMDR_OCMPU_MASK)
8008 #define MSCM_OCMDR_OCMT_MASK 0xE000u
8009 #define MSCM_OCMDR_OCMT_SHIFT 13u
8010 #define MSCM_OCMDR_OCMT_WIDTH 3u
8011 #define MSCM_OCMDR_OCMT(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMT_SHIFT))&MSCM_OCMDR_OCMT_MASK)
8012 #define MSCM_OCMDR_RO_MASK 0x10000u
8013 #define MSCM_OCMDR_RO_SHIFT 16u
8014 #define MSCM_OCMDR_RO_WIDTH 1u
8015 #define MSCM_OCMDR_RO(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_RO_SHIFT))&MSCM_OCMDR_RO_MASK)
8016 #define MSCM_OCMDR_OCMW_MASK 0xE0000u
8017 #define MSCM_OCMDR_OCMW_SHIFT 17u
8018 #define MSCM_OCMDR_OCMW_WIDTH 3u
8019 #define MSCM_OCMDR_OCMW(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMW_SHIFT))&MSCM_OCMDR_OCMW_MASK)
8020 #define MSCM_OCMDR_OCMSZ_MASK 0xF000000u
8021 #define MSCM_OCMDR_OCMSZ_SHIFT 24u
8022 #define MSCM_OCMDR_OCMSZ_WIDTH 4u
8023 #define MSCM_OCMDR_OCMSZ(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZ_SHIFT))&MSCM_OCMDR_OCMSZ_MASK)
8024 #define MSCM_OCMDR_OCMSZH_MASK 0x10000000u
8025 #define MSCM_OCMDR_OCMSZH_SHIFT 28u
8026 #define MSCM_OCMDR_OCMSZH_WIDTH 1u
8027 #define MSCM_OCMDR_OCMSZH(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_OCMSZH_SHIFT))&MSCM_OCMDR_OCMSZH_MASK)
8028 #define MSCM_OCMDR_V_MASK 0x80000000u
8029 #define MSCM_OCMDR_V_SHIFT 31u
8030 #define MSCM_OCMDR_V_WIDTH 1u
8031 #define MSCM_OCMDR_V(x) (((uint32_t)(((uint32_t)(x))<<MSCM_OCMDR_V_SHIFT))&MSCM_OCMDR_V_MASK)
8032  /* end of group MSCM_Register_Masks */
8036 
8037  /* end of group MSCM_Peripheral_Access_Layer */
8041 
8042 
8043 /* ----------------------------------------------------------------------------
8044  -- PCC Peripheral Access Layer
8045  ---------------------------------------------------------------------------- */
8046 
8054 #define PCC_PCCn_COUNT 116u
8055 
8057 typedef struct {
8058  __IO uint32_t PCCn[PCC_PCCn_COUNT];
8060 
8062 #define PCC_INSTANCE_COUNT (1u)
8063 
8064 
8065 /* PCC - Peripheral instance base addresses */
8067 #define PCC_BASE (0x40065000u)
8068 
8069 #define PCC ((PCC_Type *)PCC_BASE)
8070 
8071 #define PCC_BASE_ADDRS { PCC_BASE }
8072 
8073 #define PCC_BASE_PTRS { PCC }
8074 
8075 /* PCC index offsets */
8076 #define PCC_FTFC_INDEX 32
8077 #define PCC_DMAMUX_INDEX 33
8078 #define PCC_FlexCAN0_INDEX 36
8079 #define PCC_FlexCAN1_INDEX 37
8080 #define PCC_FTM3_INDEX 38
8081 #define PCC_ADC1_INDEX 39
8082 #define PCC_LPSPI0_INDEX 44
8083 #define PCC_LPSPI1_INDEX 45
8084 #define PCC_PDB1_INDEX 49
8085 #define PCC_CRC_INDEX 50
8086 #define PCC_PDB0_INDEX 54
8087 #define PCC_LPIT_INDEX 55
8088 #define PCC_FTM0_INDEX 56
8089 #define PCC_FTM1_INDEX 57
8090 #define PCC_FTM2_INDEX 58
8091 #define PCC_ADC0_INDEX 59
8092 #define PCC_RTC_INDEX 61
8093 #define PCC_LPTMR0_INDEX 64
8094 #define PCC_PORTA_INDEX 73
8095 #define PCC_PORTB_INDEX 74
8096 #define PCC_PORTC_INDEX 75
8097 #define PCC_PORTD_INDEX 76
8098 #define PCC_PORTE_INDEX 77
8099 #define PCC_FlexIO_INDEX 90
8100 #define PCC_EWM_INDEX 97
8101 #define PCC_LPI2C0_INDEX 102
8102 #define PCC_LPUART0_INDEX 106
8103 #define PCC_LPUART1_INDEX 107
8104 #define PCC_CMP0_INDEX 115
8105 
8106 /* ----------------------------------------------------------------------------
8107  -- PCC Register Masks
8108  ---------------------------------------------------------------------------- */
8109 
8115 /* PCCn Bit Fields */
8116 #define PCC_PCCn_PCD_MASK 0xFu
8117 #define PCC_PCCn_PCD_SHIFT 0u
8118 #define PCC_PCCn_PCD_WIDTH 4u
8119 #define PCC_PCCn_PCD(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCD_SHIFT))&PCC_PCCn_PCD_MASK)
8120 #define PCC_PCCn_FRAC_MASK 0x10u
8121 #define PCC_PCCn_FRAC_SHIFT 4u
8122 #define PCC_PCCn_FRAC_WIDTH 1u
8123 #define PCC_PCCn_FRAC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_FRAC_SHIFT))&PCC_PCCn_FRAC_MASK)
8124 #define PCC_PCCn_PCS_MASK 0x7000000u
8125 #define PCC_PCCn_PCS_SHIFT 24u
8126 #define PCC_PCCn_PCS_WIDTH 3u
8127 #define PCC_PCCn_PCS(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PCS_SHIFT))&PCC_PCCn_PCS_MASK)
8128 #define PCC_PCCn_CGC_MASK 0x40000000u
8129 #define PCC_PCCn_CGC_SHIFT 30u
8130 #define PCC_PCCn_CGC_WIDTH 1u
8131 #define PCC_PCCn_CGC(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_CGC_SHIFT))&PCC_PCCn_CGC_MASK)
8132 #define PCC_PCCn_PR_MASK 0x80000000u
8133 #define PCC_PCCn_PR_SHIFT 31u
8134 #define PCC_PCCn_PR_WIDTH 1u
8135 #define PCC_PCCn_PR(x) (((uint32_t)(((uint32_t)(x))<<PCC_PCCn_PR_SHIFT))&PCC_PCCn_PR_MASK)
8136  /* end of group PCC_Register_Masks */
8140 
8141  /* end of group PCC_Peripheral_Access_Layer */
8145 
8146 
8147 /* ----------------------------------------------------------------------------
8148  -- PDB Peripheral Access Layer
8149  ---------------------------------------------------------------------------- */
8150 
8158 #define PDB_CH_COUNT 2u
8159 #define PDB_DLY_COUNT 8u
8160 #define PDB_POnDLY_COUNT 1u
8161 
8163 typedef struct {
8164  __IO uint32_t SC;
8165  __IO uint32_t MOD;
8166  __I uint32_t CNT;
8167  __IO uint32_t IDLY;
8168  struct { /* offset: 0x10, array step: 0x28 */
8169  __IO uint32_t C1;
8170  __IO uint32_t S;
8171  __IO uint32_t DLY[PDB_DLY_COUNT];
8172  } CH[PDB_CH_COUNT];
8173  uint8_t RESERVED_0[304];
8174  __IO uint32_t POEN;
8175  union { /* offset: 0x194, array step: 0x4 */
8176  __IO uint32_t PODLY;
8177  struct { /* offset: 0x194, array step: 0x4 */
8178  __IO uint16_t DLY2;
8179  __IO uint16_t DLY1;
8180  } ACCESS16BIT;
8181  } POnDLY[PDB_POnDLY_COUNT];
8183 
8185 #define PDB_INSTANCE_COUNT (2u)
8186 
8187 
8188 /* PDB - Peripheral instance base addresses */
8190 #define PDB0_BASE (0x40036000u)
8191 
8192 #define PDB0 ((PDB_Type *)PDB0_BASE)
8193 
8194 #define PDB1_BASE (0x40031000u)
8195 
8196 #define PDB1 ((PDB_Type *)PDB1_BASE)
8197 
8198 #define PDB_BASE_ADDRS { PDB0_BASE, PDB1_BASE }
8199 
8200 #define PDB_BASE_PTRS { PDB0, PDB1 }
8201 
8202 #define PDB_IRQS_ARR_COUNT (1u)
8203 
8204 #define PDB_IRQS_CH_COUNT (1u)
8205 
8206 #define PDB_IRQS { PDB0_IRQn, PDB1_IRQn }
8207 
8208 /* ----------------------------------------------------------------------------
8209  -- PDB Register Masks
8210  ---------------------------------------------------------------------------- */
8211 
8217 /* SC Bit Fields */
8218 #define PDB_SC_LDOK_MASK 0x1u
8219 #define PDB_SC_LDOK_SHIFT 0u
8220 #define PDB_SC_LDOK_WIDTH 1u
8221 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDOK_SHIFT))&PDB_SC_LDOK_MASK)
8222 #define PDB_SC_CONT_MASK 0x2u
8223 #define PDB_SC_CONT_SHIFT 1u
8224 #define PDB_SC_CONT_WIDTH 1u
8225 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_CONT_SHIFT))&PDB_SC_CONT_MASK)
8226 #define PDB_SC_MULT_MASK 0xCu
8227 #define PDB_SC_MULT_SHIFT 2u
8228 #define PDB_SC_MULT_WIDTH 2u
8229 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
8230 #define PDB_SC_PDBIE_MASK 0x20u
8231 #define PDB_SC_PDBIE_SHIFT 5u
8232 #define PDB_SC_PDBIE_WIDTH 1u
8233 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIE_SHIFT))&PDB_SC_PDBIE_MASK)
8234 #define PDB_SC_PDBIF_MASK 0x40u
8235 #define PDB_SC_PDBIF_SHIFT 6u
8236 #define PDB_SC_PDBIF_WIDTH 1u
8237 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBIF_SHIFT))&PDB_SC_PDBIF_MASK)
8238 #define PDB_SC_PDBEN_MASK 0x80u
8239 #define PDB_SC_PDBEN_SHIFT 7u
8240 #define PDB_SC_PDBEN_WIDTH 1u
8241 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEN_SHIFT))&PDB_SC_PDBEN_MASK)
8242 #define PDB_SC_TRGSEL_MASK 0xF00u
8243 #define PDB_SC_TRGSEL_SHIFT 8u
8244 #define PDB_SC_TRGSEL_WIDTH 4u
8245 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
8246 #define PDB_SC_PRESCALER_MASK 0x7000u
8247 #define PDB_SC_PRESCALER_SHIFT 12u
8248 #define PDB_SC_PRESCALER_WIDTH 3u
8249 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
8250 #define PDB_SC_DMAEN_MASK 0x8000u
8251 #define PDB_SC_DMAEN_SHIFT 15u
8252 #define PDB_SC_DMAEN_WIDTH 1u
8253 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_DMAEN_SHIFT))&PDB_SC_DMAEN_MASK)
8254 #define PDB_SC_SWTRIG_MASK 0x10000u
8255 #define PDB_SC_SWTRIG_SHIFT 16u
8256 #define PDB_SC_SWTRIG_WIDTH 1u
8257 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_SWTRIG_SHIFT))&PDB_SC_SWTRIG_MASK)
8258 #define PDB_SC_PDBEIE_MASK 0x20000u
8259 #define PDB_SC_PDBEIE_SHIFT 17u
8260 #define PDB_SC_PDBEIE_WIDTH 1u
8261 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PDBEIE_SHIFT))&PDB_SC_PDBEIE_MASK)
8262 #define PDB_SC_LDMOD_MASK 0xC0000u
8263 #define PDB_SC_LDMOD_SHIFT 18u
8264 #define PDB_SC_LDMOD_WIDTH 2u
8265 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
8266 /* MOD Bit Fields */
8267 #define PDB_MOD_MOD_MASK 0xFFFFu
8268 #define PDB_MOD_MOD_SHIFT 0u
8269 #define PDB_MOD_MOD_WIDTH 16u
8270 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
8271 /* CNT Bit Fields */
8272 #define PDB_CNT_CNT_MASK 0xFFFFu
8273 #define PDB_CNT_CNT_SHIFT 0u
8274 #define PDB_CNT_CNT_WIDTH 16u
8275 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
8276 /* IDLY Bit Fields */
8277 #define PDB_IDLY_IDLY_MASK 0xFFFFu
8278 #define PDB_IDLY_IDLY_SHIFT 0u
8279 #define PDB_IDLY_IDLY_WIDTH 16u
8280 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
8281 /* C1 Bit Fields */
8282 #define PDB_C1_EN_MASK 0xFFu
8283 #define PDB_C1_EN_SHIFT 0u
8284 #define PDB_C1_EN_WIDTH 8u
8285 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
8286 #define PDB_C1_TOS_MASK 0xFF00u
8287 #define PDB_C1_TOS_SHIFT 8u
8288 #define PDB_C1_TOS_WIDTH 8u
8289 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
8290 #define PDB_C1_BB_MASK 0xFF0000u
8291 #define PDB_C1_BB_SHIFT 16u
8292 #define PDB_C1_BB_WIDTH 8u
8293 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
8294 /* S Bit Fields */
8295 #define PDB_S_ERR_MASK 0xFFu
8296 #define PDB_S_ERR_SHIFT 0u
8297 #define PDB_S_ERR_WIDTH 8u
8298 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
8299 #define PDB_S_CF_MASK 0xFF0000u
8300 #define PDB_S_CF_SHIFT 16u
8301 #define PDB_S_CF_WIDTH 8u
8302 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
8303 /* DLY Bit Fields */
8304 #define PDB_DLY_DLY_MASK 0xFFFFu
8305 #define PDB_DLY_DLY_SHIFT 0u
8306 #define PDB_DLY_DLY_WIDTH 16u
8307 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
8308 /* POEN Bit Fields */
8309 #define PDB_POEN_POEN_MASK 0xFFu
8310 #define PDB_POEN_POEN_SHIFT 0u
8311 #define PDB_POEN_POEN_WIDTH 8u
8312 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
8313 /* POnDLY_PODLY Bit Fields */
8314 #define PDB_POnDLY_PODLY_DLY2_MASK 0xFFFFu
8315 #define PDB_POnDLY_PODLY_DLY2_SHIFT 0u
8316 #define PDB_POnDLY_PODLY_DLY2_WIDTH 16u
8317 #define PDB_POnDLY_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY2_SHIFT))&PDB_POnDLY_PODLY_DLY2_MASK)
8318 #define PDB_POnDLY_PODLY_DLY1_MASK 0xFFFF0000u
8319 #define PDB_POnDLY_PODLY_DLY1_SHIFT 16u
8320 #define PDB_POnDLY_PODLY_DLY1_WIDTH 16u
8321 #define PDB_POnDLY_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_POnDLY_PODLY_DLY1_SHIFT))&PDB_POnDLY_PODLY_DLY1_MASK)
8322 /* POnDLY_ACCESS16BIT_DLY2 Bit Fields */
8323 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK 0xFFFFu
8324 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT 0u
8325 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_WIDTH 16u
8326 #define PDB_POnDLY_ACCESS16BIT_DLY2_DLY2(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY2_DLY2_MASK)
8327 /* POnDLY_ACCESS16BIT_DLY1 Bit Fields */
8328 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK 0xFFFFu
8329 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT 0u
8330 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_WIDTH 16u
8331 #define PDB_POnDLY_ACCESS16BIT_DLY1_DLY1(x) (((uint16_t)(((uint16_t)(x))<<PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_SHIFT))&PDB_POnDLY_ACCESS16BIT_DLY1_DLY1_MASK)
8332  /* end of group PDB_Register_Masks */
8336 
8337  /* end of group PDB_Peripheral_Access_Layer */
8341 
8342 
8343 /* ----------------------------------------------------------------------------
8344  -- PMC Peripheral Access Layer
8345  ---------------------------------------------------------------------------- */
8346 
8356 typedef struct {
8357  __IO uint8_t LVDSC1;
8358  __IO uint8_t LVDSC2;
8359  __IO uint8_t REGSC;
8360  uint8_t RESERVED_0[1];
8361  __IO uint8_t LPOTRIM;
8363 
8365 #define PMC_INSTANCE_COUNT (1u)
8366 
8367 
8368 /* PMC - Peripheral instance base addresses */
8370 #define PMC_BASE (0x4007D000u)
8371 
8372 #define PMC ((PMC_Type *)PMC_BASE)
8373 
8374 #define PMC_BASE_ADDRS { PMC_BASE }
8375 
8376 #define PMC_BASE_PTRS { PMC }
8377 
8378 #define PMC_IRQS_ARR_COUNT (1u)
8379 
8380 #define PMC_IRQS_CH_COUNT (1u)
8381 
8382 #define PMC_IRQS { LVD_LVW_IRQn }
8383 
8384 /* ----------------------------------------------------------------------------
8385  -- PMC Register Masks
8386  ---------------------------------------------------------------------------- */
8387 
8393 /* LVDSC1 Bit Fields */
8394 #define PMC_LVDSC1_LVDRE_MASK 0x10u
8395 #define PMC_LVDSC1_LVDRE_SHIFT 4u
8396 #define PMC_LVDSC1_LVDRE_WIDTH 1u
8397 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDRE_SHIFT))&PMC_LVDSC1_LVDRE_MASK)
8398 #define PMC_LVDSC1_LVDIE_MASK 0x20u
8399 #define PMC_LVDSC1_LVDIE_SHIFT 5u
8400 #define PMC_LVDSC1_LVDIE_WIDTH 1u
8401 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDIE_SHIFT))&PMC_LVDSC1_LVDIE_MASK)
8402 #define PMC_LVDSC1_LVDACK_MASK 0x40u
8403 #define PMC_LVDSC1_LVDACK_SHIFT 6u
8404 #define PMC_LVDSC1_LVDACK_WIDTH 1u
8405 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDACK_SHIFT))&PMC_LVDSC1_LVDACK_MASK)
8406 #define PMC_LVDSC1_LVDF_MASK 0x80u
8407 #define PMC_LVDSC1_LVDF_SHIFT 7u
8408 #define PMC_LVDSC1_LVDF_WIDTH 1u
8409 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDF_SHIFT))&PMC_LVDSC1_LVDF_MASK)
8410 /* LVDSC2 Bit Fields */
8411 #define PMC_LVDSC2_LVWIE_MASK 0x20u
8412 #define PMC_LVDSC2_LVWIE_SHIFT 5u
8413 #define PMC_LVDSC2_LVWIE_WIDTH 1u
8414 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWIE_SHIFT))&PMC_LVDSC2_LVWIE_MASK)
8415 #define PMC_LVDSC2_LVWACK_MASK 0x40u
8416 #define PMC_LVDSC2_LVWACK_SHIFT 6u
8417 #define PMC_LVDSC2_LVWACK_WIDTH 1u
8418 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWACK_SHIFT))&PMC_LVDSC2_LVWACK_MASK)
8419 #define PMC_LVDSC2_LVWF_MASK 0x80u
8420 #define PMC_LVDSC2_LVWF_SHIFT 7u
8421 #define PMC_LVDSC2_LVWF_WIDTH 1u
8422 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWF_SHIFT))&PMC_LVDSC2_LVWF_MASK)
8423 /* REGSC Bit Fields */
8424 #define PMC_REGSC_BIASEN_MASK 0x1u
8425 #define PMC_REGSC_BIASEN_SHIFT 0u
8426 #define PMC_REGSC_BIASEN_WIDTH 1u
8427 #define PMC_REGSC_BIASEN(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_BIASEN_SHIFT))&PMC_REGSC_BIASEN_MASK)
8428 #define PMC_REGSC_CLKBIASDIS_MASK 0x2u
8429 #define PMC_REGSC_CLKBIASDIS_SHIFT 1u
8430 #define PMC_REGSC_CLKBIASDIS_WIDTH 1u
8431 #define PMC_REGSC_CLKBIASDIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_CLKBIASDIS_SHIFT))&PMC_REGSC_CLKBIASDIS_MASK)
8432 #define PMC_REGSC_REGFPM_MASK 0x4u
8433 #define PMC_REGSC_REGFPM_SHIFT 2u
8434 #define PMC_REGSC_REGFPM_WIDTH 1u
8435 #define PMC_REGSC_REGFPM(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_REGFPM_SHIFT))&PMC_REGSC_REGFPM_MASK)
8436 #define PMC_REGSC_LPOSTAT_MASK 0x40u
8437 #define PMC_REGSC_LPOSTAT_SHIFT 6u
8438 #define PMC_REGSC_LPOSTAT_WIDTH 1u
8439 #define PMC_REGSC_LPOSTAT(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPOSTAT_SHIFT))&PMC_REGSC_LPOSTAT_MASK)
8440 #define PMC_REGSC_LPODIS_MASK 0x80u
8441 #define PMC_REGSC_LPODIS_SHIFT 7u
8442 #define PMC_REGSC_LPODIS_WIDTH 1u
8443 #define PMC_REGSC_LPODIS(x) (((uint8_t)(((uint8_t)(x))<<PMC_REGSC_LPODIS_SHIFT))&PMC_REGSC_LPODIS_MASK)
8444 /* LPOTRIM Bit Fields */
8445 #define PMC_LPOTRIM_LPOTRIM_MASK 0x1Fu
8446 #define PMC_LPOTRIM_LPOTRIM_SHIFT 0u
8447 #define PMC_LPOTRIM_LPOTRIM_WIDTH 5u
8448 #define PMC_LPOTRIM_LPOTRIM(x) (((uint8_t)(((uint8_t)(x))<<PMC_LPOTRIM_LPOTRIM_SHIFT))&PMC_LPOTRIM_LPOTRIM_MASK)
8449  /* end of group PMC_Register_Masks */
8453 
8454  /* end of group PMC_Peripheral_Access_Layer */
8458 
8459 
8460 /* ----------------------------------------------------------------------------
8461  -- PORT Peripheral Access Layer
8462  ---------------------------------------------------------------------------- */
8463 
8471 #define PORT_PCR_COUNT 32u
8472 
8474 typedef struct {
8475  __IO uint32_t PCR[PORT_PCR_COUNT];
8476  __O uint32_t GPCLR;
8477  __O uint32_t GPCHR;
8478  uint8_t RESERVED_0[24];
8479  __IO uint32_t ISFR;
8480  uint8_t RESERVED_1[28];
8481  __IO uint32_t DFER;
8482  __IO uint32_t DFCR;
8483  __IO uint32_t DFWR;
8485 
8487 #define PORT_INSTANCE_COUNT (5u)
8488 
8489 
8490 /* PORT - Peripheral instance base addresses */
8492 #define PORTA_BASE (0x40049000u)
8493 
8494 #define PORTA ((PORT_Type *)PORTA_BASE)
8495 
8496 #define PORTB_BASE (0x4004A000u)
8497 
8498 #define PORTB ((PORT_Type *)PORTB_BASE)
8499 
8500 #define PORTC_BASE (0x4004B000u)
8501 
8502 #define PORTC ((PORT_Type *)PORTC_BASE)
8503 
8504 #define PORTD_BASE (0x4004C000u)
8505 
8506 #define PORTD ((PORT_Type *)PORTD_BASE)
8507 
8508 #define PORTE_BASE (0x4004D000u)
8509 
8510 #define PORTE ((PORT_Type *)PORTE_BASE)
8511 
8512 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
8513 
8514 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
8515 
8516 #define PORT_IRQS_ARR_COUNT (1u)
8517 
8518 #define PORT_IRQS_CH_COUNT (1u)
8519 
8520 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
8521 
8522 /* ----------------------------------------------------------------------------
8523  -- PORT Register Masks
8524  ---------------------------------------------------------------------------- */
8525 
8531 /* PCR Bit Fields */
8532 #define PORT_PCR_PS_MASK 0x1u
8533 #define PORT_PCR_PS_SHIFT 0u
8534 #define PORT_PCR_PS_WIDTH 1u
8535 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PS_SHIFT))&PORT_PCR_PS_MASK)
8536 #define PORT_PCR_PE_MASK 0x2u
8537 #define PORT_PCR_PE_SHIFT 1u
8538 #define PORT_PCR_PE_WIDTH 1u
8539 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PE_SHIFT))&PORT_PCR_PE_MASK)
8540 #define PORT_PCR_PFE_MASK 0x10u
8541 #define PORT_PCR_PFE_SHIFT 4u
8542 #define PORT_PCR_PFE_WIDTH 1u
8543 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_PFE_SHIFT))&PORT_PCR_PFE_MASK)
8544 #define PORT_PCR_DSE_MASK 0x40u
8545 #define PORT_PCR_DSE_SHIFT 6u
8546 #define PORT_PCR_DSE_WIDTH 1u
8547 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_DSE_SHIFT))&PORT_PCR_DSE_MASK)
8548 #define PORT_PCR_MUX_MASK 0x700u
8549 #define PORT_PCR_MUX_SHIFT 8u
8550 #define PORT_PCR_MUX_WIDTH 3u
8551 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
8552 #define PORT_PCR_LK_MASK 0x8000u
8553 #define PORT_PCR_LK_SHIFT 15u
8554 #define PORT_PCR_LK_WIDTH 1u
8555 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_LK_SHIFT))&PORT_PCR_LK_MASK)
8556 #define PORT_PCR_IRQC_MASK 0xF0000u
8557 #define PORT_PCR_IRQC_SHIFT 16u
8558 #define PORT_PCR_IRQC_WIDTH 4u
8559 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
8560 #define PORT_PCR_ISF_MASK 0x1000000u
8561 #define PORT_PCR_ISF_SHIFT 24u
8562 #define PORT_PCR_ISF_WIDTH 1u
8563 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_ISF_SHIFT))&PORT_PCR_ISF_MASK)
8564 /* GPCLR Bit Fields */
8565 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
8566 #define PORT_GPCLR_GPWD_SHIFT 0u
8567 #define PORT_GPCLR_GPWD_WIDTH 16u
8568 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
8569 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
8570 #define PORT_GPCLR_GPWE_SHIFT 16u
8571 #define PORT_GPCLR_GPWE_WIDTH 16u
8572 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
8573 /* GPCHR Bit Fields */
8574 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
8575 #define PORT_GPCHR_GPWD_SHIFT 0u
8576 #define PORT_GPCHR_GPWD_WIDTH 16u
8577 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
8578 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
8579 #define PORT_GPCHR_GPWE_SHIFT 16u
8580 #define PORT_GPCHR_GPWE_WIDTH 16u
8581 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
8582 /* ISFR Bit Fields */
8583 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
8584 #define PORT_ISFR_ISF_SHIFT 0u
8585 #define PORT_ISFR_ISF_WIDTH 32u
8586 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
8587 /* DFER Bit Fields */
8588 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
8589 #define PORT_DFER_DFE_SHIFT 0u
8590 #define PORT_DFER_DFE_WIDTH 32u
8591 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
8592 /* DFCR Bit Fields */
8593 #define PORT_DFCR_CS_MASK 0x1u
8594 #define PORT_DFCR_CS_SHIFT 0u
8595 #define PORT_DFCR_CS_WIDTH 1u
8596 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFCR_CS_SHIFT))&PORT_DFCR_CS_MASK)
8597 /* DFWR Bit Fields */
8598 #define PORT_DFWR_FILT_MASK 0x1Fu
8599 #define PORT_DFWR_FILT_SHIFT 0u
8600 #define PORT_DFWR_FILT_WIDTH 5u
8601 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
8602  /* end of group PORT_Register_Masks */
8606 
8607  /* end of group PORT_Peripheral_Access_Layer */
8611 
8612 
8613 /* ----------------------------------------------------------------------------
8614  -- RCM Peripheral Access Layer
8615  ---------------------------------------------------------------------------- */
8616 
8626 typedef struct {
8627  __I uint32_t VERID;
8628  __I uint32_t PARAM;
8629  __I uint32_t SRS;
8630  __IO uint32_t RPC;
8631  uint8_t RESERVED_0[8];
8632  __IO uint32_t SSRS;
8633  __IO uint32_t SRIE;
8635 
8637 #define RCM_INSTANCE_COUNT (1u)
8638 
8639 
8640 /* RCM - Peripheral instance base addresses */
8642 #define RCM_BASE (0x4007F000u)
8643 
8644 #define RCM ((RCM_Type *)RCM_BASE)
8645 
8646 #define RCM_BASE_ADDRS { RCM_BASE }
8647 
8648 #define RCM_BASE_PTRS { RCM }
8649 
8650 #define RCM_IRQS_ARR_COUNT (1u)
8651 
8652 #define RCM_IRQS_CH_COUNT (1u)
8653 
8654 #define RCM_IRQS { RCM_IRQn }
8655 
8656 /* ----------------------------------------------------------------------------
8657  -- RCM Register Masks
8658  ---------------------------------------------------------------------------- */
8659 
8665 /* VERID Bit Fields */
8666 #define RCM_VERID_FEATURE_MASK 0xFFFFu
8667 #define RCM_VERID_FEATURE_SHIFT 0u
8668 #define RCM_VERID_FEATURE_WIDTH 16u
8669 #define RCM_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_FEATURE_SHIFT))&RCM_VERID_FEATURE_MASK)
8670 #define RCM_VERID_MINOR_MASK 0xFF0000u
8671 #define RCM_VERID_MINOR_SHIFT 16u
8672 #define RCM_VERID_MINOR_WIDTH 8u
8673 #define RCM_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MINOR_SHIFT))&RCM_VERID_MINOR_MASK)
8674 #define RCM_VERID_MAJOR_MASK 0xFF000000u
8675 #define RCM_VERID_MAJOR_SHIFT 24u
8676 #define RCM_VERID_MAJOR_WIDTH 8u
8677 #define RCM_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_VERID_MAJOR_SHIFT))&RCM_VERID_MAJOR_MASK)
8678 /* PARAM Bit Fields */
8679 #define RCM_PARAM_EWAKEUP_MASK 0x1u
8680 #define RCM_PARAM_EWAKEUP_SHIFT 0u
8681 #define RCM_PARAM_EWAKEUP_WIDTH 1u
8682 #define RCM_PARAM_EWAKEUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWAKEUP_SHIFT))&RCM_PARAM_EWAKEUP_MASK)
8683 #define RCM_PARAM_ELVD_MASK 0x2u
8684 #define RCM_PARAM_ELVD_SHIFT 1u
8685 #define RCM_PARAM_ELVD_WIDTH 1u
8686 #define RCM_PARAM_ELVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELVD_SHIFT))&RCM_PARAM_ELVD_MASK)
8687 #define RCM_PARAM_ELOC_MASK 0x4u
8688 #define RCM_PARAM_ELOC_SHIFT 2u
8689 #define RCM_PARAM_ELOC_WIDTH 1u
8690 #define RCM_PARAM_ELOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOC_SHIFT))&RCM_PARAM_ELOC_MASK)
8691 #define RCM_PARAM_ELOL_MASK 0x8u
8692 #define RCM_PARAM_ELOL_SHIFT 3u
8693 #define RCM_PARAM_ELOL_WIDTH 1u
8694 #define RCM_PARAM_ELOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOL_SHIFT))&RCM_PARAM_ELOL_MASK)
8695 #define RCM_PARAM_EWDOG_MASK 0x20u
8696 #define RCM_PARAM_EWDOG_SHIFT 5u
8697 #define RCM_PARAM_EWDOG_WIDTH 1u
8698 #define RCM_PARAM_EWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EWDOG_SHIFT))&RCM_PARAM_EWDOG_MASK)
8699 #define RCM_PARAM_EPIN_MASK 0x40u
8700 #define RCM_PARAM_EPIN_SHIFT 6u
8701 #define RCM_PARAM_EPIN_WIDTH 1u
8702 #define RCM_PARAM_EPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPIN_SHIFT))&RCM_PARAM_EPIN_MASK)
8703 #define RCM_PARAM_EPOR_MASK 0x80u
8704 #define RCM_PARAM_EPOR_SHIFT 7u
8705 #define RCM_PARAM_EPOR_WIDTH 1u
8706 #define RCM_PARAM_EPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EPOR_SHIFT))&RCM_PARAM_EPOR_MASK)
8707 #define RCM_PARAM_EJTAG_MASK 0x100u
8708 #define RCM_PARAM_EJTAG_SHIFT 8u
8709 #define RCM_PARAM_EJTAG_WIDTH 1u
8710 #define RCM_PARAM_EJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EJTAG_SHIFT))&RCM_PARAM_EJTAG_MASK)
8711 #define RCM_PARAM_ELOCKUP_MASK 0x200u
8712 #define RCM_PARAM_ELOCKUP_SHIFT 9u
8713 #define RCM_PARAM_ELOCKUP_WIDTH 1u
8714 #define RCM_PARAM_ELOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ELOCKUP_SHIFT))&RCM_PARAM_ELOCKUP_MASK)
8715 #define RCM_PARAM_ESW_MASK 0x400u
8716 #define RCM_PARAM_ESW_SHIFT 10u
8717 #define RCM_PARAM_ESW_WIDTH 1u
8718 #define RCM_PARAM_ESW(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESW_SHIFT))&RCM_PARAM_ESW_MASK)
8719 #define RCM_PARAM_EMDM_AP_MASK 0x800u
8720 #define RCM_PARAM_EMDM_AP_SHIFT 11u
8721 #define RCM_PARAM_EMDM_AP_WIDTH 1u
8722 #define RCM_PARAM_EMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_EMDM_AP_SHIFT))&RCM_PARAM_EMDM_AP_MASK)
8723 #define RCM_PARAM_ESACKERR_MASK 0x2000u
8724 #define RCM_PARAM_ESACKERR_SHIFT 13u
8725 #define RCM_PARAM_ESACKERR_WIDTH 1u
8726 #define RCM_PARAM_ESACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ESACKERR_SHIFT))&RCM_PARAM_ESACKERR_MASK)
8727 #define RCM_PARAM_ETAMPER_MASK 0x8000u
8728 #define RCM_PARAM_ETAMPER_SHIFT 15u
8729 #define RCM_PARAM_ETAMPER_WIDTH 1u
8730 #define RCM_PARAM_ETAMPER(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ETAMPER_SHIFT))&RCM_PARAM_ETAMPER_MASK)
8731 #define RCM_PARAM_ECORE1_MASK 0x10000u
8732 #define RCM_PARAM_ECORE1_SHIFT 16u
8733 #define RCM_PARAM_ECORE1_WIDTH 1u
8734 #define RCM_PARAM_ECORE1(x) (((uint32_t)(((uint32_t)(x))<<RCM_PARAM_ECORE1_SHIFT))&RCM_PARAM_ECORE1_MASK)
8735 /* SRS Bit Fields */
8736 #define RCM_SRS_LVD_MASK 0x2u
8737 #define RCM_SRS_LVD_SHIFT 1u
8738 #define RCM_SRS_LVD_WIDTH 1u
8739 #define RCM_SRS_LVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LVD_SHIFT))&RCM_SRS_LVD_MASK)
8740 #define RCM_SRS_LOC_MASK 0x4u
8741 #define RCM_SRS_LOC_SHIFT 2u
8742 #define RCM_SRS_LOC_WIDTH 1u
8743 #define RCM_SRS_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOC_SHIFT))&RCM_SRS_LOC_MASK)
8744 #define RCM_SRS_LOL_MASK 0x8u
8745 #define RCM_SRS_LOL_SHIFT 3u
8746 #define RCM_SRS_LOL_WIDTH 1u
8747 #define RCM_SRS_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOL_SHIFT))&RCM_SRS_LOL_MASK)
8748 #define RCM_SRS_WDOG_MASK 0x20u
8749 #define RCM_SRS_WDOG_SHIFT 5u
8750 #define RCM_SRS_WDOG_WIDTH 1u
8751 #define RCM_SRS_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_WDOG_SHIFT))&RCM_SRS_WDOG_MASK)
8752 #define RCM_SRS_PIN_MASK 0x40u
8753 #define RCM_SRS_PIN_SHIFT 6u
8754 #define RCM_SRS_PIN_WIDTH 1u
8755 #define RCM_SRS_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_PIN_SHIFT))&RCM_SRS_PIN_MASK)
8756 #define RCM_SRS_POR_MASK 0x80u
8757 #define RCM_SRS_POR_SHIFT 7u
8758 #define RCM_SRS_POR_WIDTH 1u
8759 #define RCM_SRS_POR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_POR_SHIFT))&RCM_SRS_POR_MASK)
8760 #define RCM_SRS_JTAG_MASK 0x100u
8761 #define RCM_SRS_JTAG_SHIFT 8u
8762 #define RCM_SRS_JTAG_WIDTH 1u
8763 #define RCM_SRS_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_JTAG_SHIFT))&RCM_SRS_JTAG_MASK)
8764 #define RCM_SRS_LOCKUP_MASK 0x200u
8765 #define RCM_SRS_LOCKUP_SHIFT 9u
8766 #define RCM_SRS_LOCKUP_WIDTH 1u
8767 #define RCM_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_LOCKUP_SHIFT))&RCM_SRS_LOCKUP_MASK)
8768 #define RCM_SRS_SW_MASK 0x400u
8769 #define RCM_SRS_SW_SHIFT 10u
8770 #define RCM_SRS_SW_WIDTH 1u
8771 #define RCM_SRS_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SW_SHIFT))&RCM_SRS_SW_MASK)
8772 #define RCM_SRS_MDM_AP_MASK 0x800u
8773 #define RCM_SRS_MDM_AP_SHIFT 11u
8774 #define RCM_SRS_MDM_AP_WIDTH 1u
8775 #define RCM_SRS_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_MDM_AP_SHIFT))&RCM_SRS_MDM_AP_MASK)
8776 #define RCM_SRS_SACKERR_MASK 0x2000u
8777 #define RCM_SRS_SACKERR_SHIFT 13u
8778 #define RCM_SRS_SACKERR_WIDTH 1u
8779 #define RCM_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRS_SACKERR_SHIFT))&RCM_SRS_SACKERR_MASK)
8780 /* RPC Bit Fields */
8781 #define RCM_RPC_RSTFLTSRW_MASK 0x3u
8782 #define RCM_RPC_RSTFLTSRW_SHIFT 0u
8783 #define RCM_RPC_RSTFLTSRW_WIDTH 2u
8784 #define RCM_RPC_RSTFLTSRW(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSRW_SHIFT))&RCM_RPC_RSTFLTSRW_MASK)
8785 #define RCM_RPC_RSTFLTSS_MASK 0x4u
8786 #define RCM_RPC_RSTFLTSS_SHIFT 2u
8787 #define RCM_RPC_RSTFLTSS_WIDTH 1u
8788 #define RCM_RPC_RSTFLTSS(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSS_SHIFT))&RCM_RPC_RSTFLTSS_MASK)
8789 #define RCM_RPC_RSTFLTSEL_MASK 0x1F00u
8790 #define RCM_RPC_RSTFLTSEL_SHIFT 8u
8791 #define RCM_RPC_RSTFLTSEL_WIDTH 5u
8792 #define RCM_RPC_RSTFLTSEL(x) (((uint32_t)(((uint32_t)(x))<<RCM_RPC_RSTFLTSEL_SHIFT))&RCM_RPC_RSTFLTSEL_MASK)
8793 /* SSRS Bit Fields */
8794 #define RCM_SSRS_SLVD_MASK 0x2u
8795 #define RCM_SSRS_SLVD_SHIFT 1u
8796 #define RCM_SSRS_SLVD_WIDTH 1u
8797 #define RCM_SSRS_SLVD(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLVD_SHIFT))&RCM_SSRS_SLVD_MASK)
8798 #define RCM_SSRS_SLOC_MASK 0x4u
8799 #define RCM_SSRS_SLOC_SHIFT 2u
8800 #define RCM_SSRS_SLOC_WIDTH 1u
8801 #define RCM_SSRS_SLOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOC_SHIFT))&RCM_SSRS_SLOC_MASK)
8802 #define RCM_SSRS_SLOL_MASK 0x8u
8803 #define RCM_SSRS_SLOL_SHIFT 3u
8804 #define RCM_SSRS_SLOL_WIDTH 1u
8805 #define RCM_SSRS_SLOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOL_SHIFT))&RCM_SSRS_SLOL_MASK)
8806 #define RCM_SSRS_SWDOG_MASK 0x20u
8807 #define RCM_SSRS_SWDOG_SHIFT 5u
8808 #define RCM_SSRS_SWDOG_WIDTH 1u
8809 #define RCM_SSRS_SWDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SWDOG_SHIFT))&RCM_SSRS_SWDOG_MASK)
8810 #define RCM_SSRS_SPIN_MASK 0x40u
8811 #define RCM_SSRS_SPIN_SHIFT 6u
8812 #define RCM_SSRS_SPIN_WIDTH 1u
8813 #define RCM_SSRS_SPIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPIN_SHIFT))&RCM_SSRS_SPIN_MASK)
8814 #define RCM_SSRS_SPOR_MASK 0x80u
8815 #define RCM_SSRS_SPOR_SHIFT 7u
8816 #define RCM_SSRS_SPOR_WIDTH 1u
8817 #define RCM_SSRS_SPOR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SPOR_SHIFT))&RCM_SSRS_SPOR_MASK)
8818 #define RCM_SSRS_SJTAG_MASK 0x100u
8819 #define RCM_SSRS_SJTAG_SHIFT 8u
8820 #define RCM_SSRS_SJTAG_WIDTH 1u
8821 #define RCM_SSRS_SJTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SJTAG_SHIFT))&RCM_SSRS_SJTAG_MASK)
8822 #define RCM_SSRS_SLOCKUP_MASK 0x200u
8823 #define RCM_SSRS_SLOCKUP_SHIFT 9u
8824 #define RCM_SSRS_SLOCKUP_WIDTH 1u
8825 #define RCM_SSRS_SLOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SLOCKUP_SHIFT))&RCM_SSRS_SLOCKUP_MASK)
8826 #define RCM_SSRS_SSW_MASK 0x400u
8827 #define RCM_SSRS_SSW_SHIFT 10u
8828 #define RCM_SSRS_SSW_WIDTH 1u
8829 #define RCM_SSRS_SSW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSW_SHIFT))&RCM_SSRS_SSW_MASK)
8830 #define RCM_SSRS_SMDM_AP_MASK 0x800u
8831 #define RCM_SSRS_SMDM_AP_SHIFT 11u
8832 #define RCM_SSRS_SMDM_AP_WIDTH 1u
8833 #define RCM_SSRS_SMDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SMDM_AP_SHIFT))&RCM_SSRS_SMDM_AP_MASK)
8834 #define RCM_SSRS_SSACKERR_MASK 0x2000u
8835 #define RCM_SSRS_SSACKERR_SHIFT 13u
8836 #define RCM_SSRS_SSACKERR_WIDTH 1u
8837 #define RCM_SSRS_SSACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SSRS_SSACKERR_SHIFT))&RCM_SSRS_SSACKERR_MASK)
8838 /* SRIE Bit Fields */
8839 #define RCM_SRIE_DELAY_MASK 0x3u
8840 #define RCM_SRIE_DELAY_SHIFT 0u
8841 #define RCM_SRIE_DELAY_WIDTH 2u
8842 #define RCM_SRIE_DELAY(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_DELAY_SHIFT))&RCM_SRIE_DELAY_MASK)
8843 #define RCM_SRIE_LOC_MASK 0x4u
8844 #define RCM_SRIE_LOC_SHIFT 2u
8845 #define RCM_SRIE_LOC_WIDTH 1u
8846 #define RCM_SRIE_LOC(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOC_SHIFT))&RCM_SRIE_LOC_MASK)
8847 #define RCM_SRIE_LOL_MASK 0x8u
8848 #define RCM_SRIE_LOL_SHIFT 3u
8849 #define RCM_SRIE_LOL_WIDTH 1u
8850 #define RCM_SRIE_LOL(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOL_SHIFT))&RCM_SRIE_LOL_MASK)
8851 #define RCM_SRIE_WDOG_MASK 0x20u
8852 #define RCM_SRIE_WDOG_SHIFT 5u
8853 #define RCM_SRIE_WDOG_WIDTH 1u
8854 #define RCM_SRIE_WDOG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_WDOG_SHIFT))&RCM_SRIE_WDOG_MASK)
8855 #define RCM_SRIE_PIN_MASK 0x40u
8856 #define RCM_SRIE_PIN_SHIFT 6u
8857 #define RCM_SRIE_PIN_WIDTH 1u
8858 #define RCM_SRIE_PIN(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_PIN_SHIFT))&RCM_SRIE_PIN_MASK)
8859 #define RCM_SRIE_GIE_MASK 0x80u
8860 #define RCM_SRIE_GIE_SHIFT 7u
8861 #define RCM_SRIE_GIE_WIDTH 1u
8862 #define RCM_SRIE_GIE(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_GIE_SHIFT))&RCM_SRIE_GIE_MASK)
8863 #define RCM_SRIE_JTAG_MASK 0x100u
8864 #define RCM_SRIE_JTAG_SHIFT 8u
8865 #define RCM_SRIE_JTAG_WIDTH 1u
8866 #define RCM_SRIE_JTAG(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_JTAG_SHIFT))&RCM_SRIE_JTAG_MASK)
8867 #define RCM_SRIE_LOCKUP_MASK 0x200u
8868 #define RCM_SRIE_LOCKUP_SHIFT 9u
8869 #define RCM_SRIE_LOCKUP_WIDTH 1u
8870 #define RCM_SRIE_LOCKUP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_LOCKUP_SHIFT))&RCM_SRIE_LOCKUP_MASK)
8871 #define RCM_SRIE_SW_MASK 0x400u
8872 #define RCM_SRIE_SW_SHIFT 10u
8873 #define RCM_SRIE_SW_WIDTH 1u
8874 #define RCM_SRIE_SW(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SW_SHIFT))&RCM_SRIE_SW_MASK)
8875 #define RCM_SRIE_MDM_AP_MASK 0x800u
8876 #define RCM_SRIE_MDM_AP_SHIFT 11u
8877 #define RCM_SRIE_MDM_AP_WIDTH 1u
8878 #define RCM_SRIE_MDM_AP(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_MDM_AP_SHIFT))&RCM_SRIE_MDM_AP_MASK)
8879 #define RCM_SRIE_SACKERR_MASK 0x2000u
8880 #define RCM_SRIE_SACKERR_SHIFT 13u
8881 #define RCM_SRIE_SACKERR_WIDTH 1u
8882 #define RCM_SRIE_SACKERR(x) (((uint32_t)(((uint32_t)(x))<<RCM_SRIE_SACKERR_SHIFT))&RCM_SRIE_SACKERR_MASK)
8883  /* end of group RCM_Register_Masks */
8887 
8888  /* end of group RCM_Peripheral_Access_Layer */
8892 
8893 
8894 /* ----------------------------------------------------------------------------
8895  -- RTC Peripheral Access Layer
8896  ---------------------------------------------------------------------------- */
8897 
8907 typedef struct {
8908  __IO uint32_t TSR;
8909  __IO uint32_t TPR;
8910  __IO uint32_t TAR;
8911  __IO uint32_t TCR;
8912  __IO uint32_t CR;
8913  __IO uint32_t SR;
8914  __IO uint32_t LR;
8915  __IO uint32_t IER;
8917 
8919 #define RTC_INSTANCE_COUNT (1u)
8920 
8921 
8922 /* RTC - Peripheral instance base addresses */
8924 #define RTC_BASE (0x4003D000u)
8925 
8926 #define RTC ((RTC_Type *)RTC_BASE)
8927 
8928 #define RTC_BASE_ADDRS { RTC_BASE }
8929 
8930 #define RTC_BASE_PTRS { RTC }
8931 
8932 #define RTC_IRQS_ARR_COUNT (2u)
8933 
8934 #define RTC_IRQS_CH_COUNT (1u)
8935 
8936 #define RTC_SECONDS_IRQS_CH_COUNT (1u)
8937 
8938 #define RTC_IRQS { RTC_IRQn }
8939 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
8940 
8941 /* ----------------------------------------------------------------------------
8942  -- RTC Register Masks
8943  ---------------------------------------------------------------------------- */
8944 
8950 /* TSR Bit Fields */
8951 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
8952 #define RTC_TSR_TSR_SHIFT 0u
8953 #define RTC_TSR_TSR_WIDTH 32u
8954 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
8955 /* TPR Bit Fields */
8956 #define RTC_TPR_TPR_MASK 0xFFFFu
8957 #define RTC_TPR_TPR_SHIFT 0u
8958 #define RTC_TPR_TPR_WIDTH 16u
8959 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
8960 /* TAR Bit Fields */
8961 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
8962 #define RTC_TAR_TAR_SHIFT 0u
8963 #define RTC_TAR_TAR_WIDTH 32u
8964 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
8965 /* TCR Bit Fields */
8966 #define RTC_TCR_TCR_MASK 0xFFu
8967 #define RTC_TCR_TCR_SHIFT 0u
8968 #define RTC_TCR_TCR_WIDTH 8u
8969 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
8970 #define RTC_TCR_CIR_MASK 0xFF00u
8971 #define RTC_TCR_CIR_SHIFT 8u
8972 #define RTC_TCR_CIR_WIDTH 8u
8973 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
8974 #define RTC_TCR_TCV_MASK 0xFF0000u
8975 #define RTC_TCR_TCV_SHIFT 16u
8976 #define RTC_TCR_TCV_WIDTH 8u
8977 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
8978 #define RTC_TCR_CIC_MASK 0xFF000000u
8979 #define RTC_TCR_CIC_SHIFT 24u
8980 #define RTC_TCR_CIC_WIDTH 8u
8981 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
8982 /* CR Bit Fields */
8983 #define RTC_CR_SWR_MASK 0x1u
8984 #define RTC_CR_SWR_SHIFT 0u
8985 #define RTC_CR_SWR_WIDTH 1u
8986 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SWR_SHIFT))&RTC_CR_SWR_MASK)
8987 #define RTC_CR_SUP_MASK 0x4u
8988 #define RTC_CR_SUP_SHIFT 2u
8989 #define RTC_CR_SUP_WIDTH 1u
8990 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_SUP_SHIFT))&RTC_CR_SUP_MASK)
8991 #define RTC_CR_UM_MASK 0x8u
8992 #define RTC_CR_UM_SHIFT 3u
8993 #define RTC_CR_UM_WIDTH 1u
8994 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_UM_SHIFT))&RTC_CR_UM_MASK)
8995 #define RTC_CR_CPS_MASK 0x20u
8996 #define RTC_CR_CPS_SHIFT 5u
8997 #define RTC_CR_CPS_WIDTH 1u
8998 #define RTC_CR_CPS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPS_SHIFT))&RTC_CR_CPS_MASK)
8999 #define RTC_CR_LPOS_MASK 0x80u
9000 #define RTC_CR_LPOS_SHIFT 7u
9001 #define RTC_CR_LPOS_WIDTH 1u
9002 #define RTC_CR_LPOS(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_LPOS_SHIFT))&RTC_CR_LPOS_MASK)
9003 #define RTC_CR_CPE_MASK 0x1000000u
9004 #define RTC_CR_CPE_SHIFT 24u
9005 #define RTC_CR_CPE_WIDTH 1u
9006 #define RTC_CR_CPE(x) (((uint32_t)(((uint32_t)(x))<<RTC_CR_CPE_SHIFT))&RTC_CR_CPE_MASK)
9007 /* SR Bit Fields */
9008 #define RTC_SR_TIF_MASK 0x1u
9009 #define RTC_SR_TIF_SHIFT 0u
9010 #define RTC_SR_TIF_WIDTH 1u
9011 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TIF_SHIFT))&RTC_SR_TIF_MASK)
9012 #define RTC_SR_TOF_MASK 0x2u
9013 #define RTC_SR_TOF_SHIFT 1u
9014 #define RTC_SR_TOF_WIDTH 1u
9015 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TOF_SHIFT))&RTC_SR_TOF_MASK)
9016 #define RTC_SR_TAF_MASK 0x4u
9017 #define RTC_SR_TAF_SHIFT 2u
9018 #define RTC_SR_TAF_WIDTH 1u
9019 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TAF_SHIFT))&RTC_SR_TAF_MASK)
9020 #define RTC_SR_TCE_MASK 0x10u
9021 #define RTC_SR_TCE_SHIFT 4u
9022 #define RTC_SR_TCE_WIDTH 1u
9023 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x))<<RTC_SR_TCE_SHIFT))&RTC_SR_TCE_MASK)
9024 /* LR Bit Fields */
9025 #define RTC_LR_TCL_MASK 0x8u
9026 #define RTC_LR_TCL_SHIFT 3u
9027 #define RTC_LR_TCL_WIDTH 1u
9028 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_TCL_SHIFT))&RTC_LR_TCL_MASK)
9029 #define RTC_LR_CRL_MASK 0x10u
9030 #define RTC_LR_CRL_SHIFT 4u
9031 #define RTC_LR_CRL_WIDTH 1u
9032 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_CRL_SHIFT))&RTC_LR_CRL_MASK)
9033 #define RTC_LR_SRL_MASK 0x20u
9034 #define RTC_LR_SRL_SHIFT 5u
9035 #define RTC_LR_SRL_WIDTH 1u
9036 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_SRL_SHIFT))&RTC_LR_SRL_MASK)
9037 #define RTC_LR_LRL_MASK 0x40u
9038 #define RTC_LR_LRL_SHIFT 6u
9039 #define RTC_LR_LRL_WIDTH 1u
9040 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x))<<RTC_LR_LRL_SHIFT))&RTC_LR_LRL_MASK)
9041 /* IER Bit Fields */
9042 #define RTC_IER_TIIE_MASK 0x1u
9043 #define RTC_IER_TIIE_SHIFT 0u
9044 #define RTC_IER_TIIE_WIDTH 1u
9045 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TIIE_SHIFT))&RTC_IER_TIIE_MASK)
9046 #define RTC_IER_TOIE_MASK 0x2u
9047 #define RTC_IER_TOIE_SHIFT 1u
9048 #define RTC_IER_TOIE_WIDTH 1u
9049 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TOIE_SHIFT))&RTC_IER_TOIE_MASK)
9050 #define RTC_IER_TAIE_MASK 0x4u
9051 #define RTC_IER_TAIE_SHIFT 2u
9052 #define RTC_IER_TAIE_WIDTH 1u
9053 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TAIE_SHIFT))&RTC_IER_TAIE_MASK)
9054 #define RTC_IER_TSIE_MASK 0x10u
9055 #define RTC_IER_TSIE_SHIFT 4u
9056 #define RTC_IER_TSIE_WIDTH 1u
9057 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIE_SHIFT))&RTC_IER_TSIE_MASK)
9058 #define RTC_IER_TSIC_MASK 0x70000u
9059 #define RTC_IER_TSIC_SHIFT 16u
9060 #define RTC_IER_TSIC_WIDTH 3u
9061 #define RTC_IER_TSIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_IER_TSIC_SHIFT))&RTC_IER_TSIC_MASK)
9062  /* end of group RTC_Register_Masks */
9066 
9067  /* end of group RTC_Peripheral_Access_Layer */
9071 
9072 
9073 /* ----------------------------------------------------------------------------
9074  -- S32_NVIC Peripheral Access Layer
9075  ---------------------------------------------------------------------------- */
9076 
9084 #define S32_NVIC_ISER_COUNT 4u
9085 #define S32_NVIC_ICER_COUNT 4u
9086 #define S32_NVIC_ISPR_COUNT 4u
9087 #define S32_NVIC_ICPR_COUNT 4u
9088 #define S32_NVIC_IABR_COUNT 4u
9089 #define S32_NVIC_IP_COUNT 123u
9090 
9092 typedef struct {
9093  __IO uint32_t ISER[S32_NVIC_ISER_COUNT];
9094  uint8_t RESERVED_0[112];
9095  __IO uint32_t ICER[S32_NVIC_ICER_COUNT];
9096  uint8_t RESERVED_1[112];
9097  __IO uint32_t ISPR[S32_NVIC_ISPR_COUNT];
9098  uint8_t RESERVED_2[112];
9099  __IO uint32_t ICPR[S32_NVIC_ICPR_COUNT];
9100  uint8_t RESERVED_3[112];
9101  __IO uint32_t IABR[S32_NVIC_IABR_COUNT];
9102  uint8_t RESERVED_4[240];
9103  __IO uint8_t IP[S32_NVIC_IP_COUNT];
9104  uint8_t RESERVED_5[2693];
9105  __O uint32_t STIR;
9107 
9109 #define S32_NVIC_INSTANCE_COUNT (1u)
9110 
9111 
9112 /* S32_NVIC - Peripheral instance base addresses */
9114 #define S32_NVIC_BASE (0xE000E100u)
9115 
9116 #define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE)
9117 
9118 #define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE }
9119 
9120 #define S32_NVIC_BASE_PTRS { S32_NVIC }
9121 
9122 #define S32_NVIC_IRQS_ARR_COUNT (1u)
9123 
9124 #define S32_NVIC_IRQS_CH_COUNT (1u)
9125 
9126 #define S32_NVIC_IRQS { SWI_IRQn }
9127 
9128 /* ----------------------------------------------------------------------------
9129  -- S32_NVIC Register Masks
9130  ---------------------------------------------------------------------------- */
9131 
9137 /* ISER Bit Fields */
9138 #define S32_NVIC_ISER_SETENA_MASK 0xFFFFFFFFu
9139 #define S32_NVIC_ISER_SETENA_SHIFT 0u
9140 #define S32_NVIC_ISER_SETENA_WIDTH 32u
9141 #define S32_NVIC_ISER_SETENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISER_SETENA_SHIFT))&S32_NVIC_ISER_SETENA_MASK)
9142 /* ICER Bit Fields */
9143 #define S32_NVIC_ICER_CLRENA_MASK 0xFFFFFFFFu
9144 #define S32_NVIC_ICER_CLRENA_SHIFT 0u
9145 #define S32_NVIC_ICER_CLRENA_WIDTH 32u
9146 #define S32_NVIC_ICER_CLRENA(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICER_CLRENA_SHIFT))&S32_NVIC_ICER_CLRENA_MASK)
9147 /* ISPR Bit Fields */
9148 #define S32_NVIC_ISPR_SETPEND_MASK 0xFFFFFFFFu
9149 #define S32_NVIC_ISPR_SETPEND_SHIFT 0u
9150 #define S32_NVIC_ISPR_SETPEND_WIDTH 32u
9151 #define S32_NVIC_ISPR_SETPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ISPR_SETPEND_SHIFT))&S32_NVIC_ISPR_SETPEND_MASK)
9152 /* ICPR Bit Fields */
9153 #define S32_NVIC_ICPR_CLRPEND_MASK 0xFFFFFFFFu
9154 #define S32_NVIC_ICPR_CLRPEND_SHIFT 0u
9155 #define S32_NVIC_ICPR_CLRPEND_WIDTH 32u
9156 #define S32_NVIC_ICPR_CLRPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_ICPR_CLRPEND_SHIFT))&S32_NVIC_ICPR_CLRPEND_MASK)
9157 /* IABR Bit Fields */
9158 #define S32_NVIC_IABR_ACTIVE_MASK 0xFFFFFFFFu
9159 #define S32_NVIC_IABR_ACTIVE_SHIFT 0u
9160 #define S32_NVIC_IABR_ACTIVE_WIDTH 32u
9161 #define S32_NVIC_IABR_ACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_IABR_ACTIVE_SHIFT))&S32_NVIC_IABR_ACTIVE_MASK)
9162 /* IP Bit Fields */
9163 #define S32_NVIC_IP_PRI0_MASK 0xFFu
9164 #define S32_NVIC_IP_PRI0_SHIFT 0u
9165 #define S32_NVIC_IP_PRI0_WIDTH 8u
9166 #define S32_NVIC_IP_PRI0(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI0_SHIFT))&S32_NVIC_IP_PRI0_MASK)
9167 #define S32_NVIC_IP_PRI1_MASK 0xFFu
9168 #define S32_NVIC_IP_PRI1_SHIFT 0u
9169 #define S32_NVIC_IP_PRI1_WIDTH 8u
9170 #define S32_NVIC_IP_PRI1(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI1_SHIFT))&S32_NVIC_IP_PRI1_MASK)
9171 #define S32_NVIC_IP_PRI2_MASK 0xFFu
9172 #define S32_NVIC_IP_PRI2_SHIFT 0u
9173 #define S32_NVIC_IP_PRI2_WIDTH 8u
9174 #define S32_NVIC_IP_PRI2(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI2_SHIFT))&S32_NVIC_IP_PRI2_MASK)
9175 #define S32_NVIC_IP_PRI3_MASK 0xFFu
9176 #define S32_NVIC_IP_PRI3_SHIFT 0u
9177 #define S32_NVIC_IP_PRI3_WIDTH 8u
9178 #define S32_NVIC_IP_PRI3(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI3_SHIFT))&S32_NVIC_IP_PRI3_MASK)
9179 #define S32_NVIC_IP_PRI4_MASK 0xFFu
9180 #define S32_NVIC_IP_PRI4_SHIFT 0u
9181 #define S32_NVIC_IP_PRI4_WIDTH 8u
9182 #define S32_NVIC_IP_PRI4(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI4_SHIFT))&S32_NVIC_IP_PRI4_MASK)
9183 #define S32_NVIC_IP_PRI5_MASK 0xFFu
9184 #define S32_NVIC_IP_PRI5_SHIFT 0u
9185 #define S32_NVIC_IP_PRI5_WIDTH 8u
9186 #define S32_NVIC_IP_PRI5(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI5_SHIFT))&S32_NVIC_IP_PRI5_MASK)
9187 #define S32_NVIC_IP_PRI6_MASK 0xFFu
9188 #define S32_NVIC_IP_PRI6_SHIFT 0u
9189 #define S32_NVIC_IP_PRI6_WIDTH 8u
9190 #define S32_NVIC_IP_PRI6(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI6_SHIFT))&S32_NVIC_IP_PRI6_MASK)
9191 #define S32_NVIC_IP_PRI7_MASK 0xFFu
9192 #define S32_NVIC_IP_PRI7_SHIFT 0u
9193 #define S32_NVIC_IP_PRI7_WIDTH 8u
9194 #define S32_NVIC_IP_PRI7(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI7_SHIFT))&S32_NVIC_IP_PRI7_MASK)
9195 #define S32_NVIC_IP_PRI8_MASK 0xFFu
9196 #define S32_NVIC_IP_PRI8_SHIFT 0u
9197 #define S32_NVIC_IP_PRI8_WIDTH 8u
9198 #define S32_NVIC_IP_PRI8(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI8_SHIFT))&S32_NVIC_IP_PRI8_MASK)
9199 #define S32_NVIC_IP_PRI9_MASK 0xFFu
9200 #define S32_NVIC_IP_PRI9_SHIFT 0u
9201 #define S32_NVIC_IP_PRI9_WIDTH 8u
9202 #define S32_NVIC_IP_PRI9(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI9_SHIFT))&S32_NVIC_IP_PRI9_MASK)
9203 #define S32_NVIC_IP_PRI10_MASK 0xFFu
9204 #define S32_NVIC_IP_PRI10_SHIFT 0u
9205 #define S32_NVIC_IP_PRI10_WIDTH 8u
9206 #define S32_NVIC_IP_PRI10(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI10_SHIFT))&S32_NVIC_IP_PRI10_MASK)
9207 #define S32_NVIC_IP_PRI11_MASK 0xFFu
9208 #define S32_NVIC_IP_PRI11_SHIFT 0u
9209 #define S32_NVIC_IP_PRI11_WIDTH 8u
9210 #define S32_NVIC_IP_PRI11(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI11_SHIFT))&S32_NVIC_IP_PRI11_MASK)
9211 #define S32_NVIC_IP_PRI12_MASK 0xFFu
9212 #define S32_NVIC_IP_PRI12_SHIFT 0u
9213 #define S32_NVIC_IP_PRI12_WIDTH 8u
9214 #define S32_NVIC_IP_PRI12(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI12_SHIFT))&S32_NVIC_IP_PRI12_MASK)
9215 #define S32_NVIC_IP_PRI13_MASK 0xFFu
9216 #define S32_NVIC_IP_PRI13_SHIFT 0u
9217 #define S32_NVIC_IP_PRI13_WIDTH 8u
9218 #define S32_NVIC_IP_PRI13(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI13_SHIFT))&S32_NVIC_IP_PRI13_MASK)
9219 #define S32_NVIC_IP_PRI14_MASK 0xFFu
9220 #define S32_NVIC_IP_PRI14_SHIFT 0u
9221 #define S32_NVIC_IP_PRI14_WIDTH 8u
9222 #define S32_NVIC_IP_PRI14(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI14_SHIFT))&S32_NVIC_IP_PRI14_MASK)
9223 #define S32_NVIC_IP_PRI15_MASK 0xFFu
9224 #define S32_NVIC_IP_PRI15_SHIFT 0u
9225 #define S32_NVIC_IP_PRI15_WIDTH 8u
9226 #define S32_NVIC_IP_PRI15(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI15_SHIFT))&S32_NVIC_IP_PRI15_MASK)
9227 #define S32_NVIC_IP_PRI16_MASK 0xFFu
9228 #define S32_NVIC_IP_PRI16_SHIFT 0u
9229 #define S32_NVIC_IP_PRI16_WIDTH 8u
9230 #define S32_NVIC_IP_PRI16(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI16_SHIFT))&S32_NVIC_IP_PRI16_MASK)
9231 #define S32_NVIC_IP_PRI17_MASK 0xFFu
9232 #define S32_NVIC_IP_PRI17_SHIFT 0u
9233 #define S32_NVIC_IP_PRI17_WIDTH 8u
9234 #define S32_NVIC_IP_PRI17(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI17_SHIFT))&S32_NVIC_IP_PRI17_MASK)
9235 #define S32_NVIC_IP_PRI18_MASK 0xFFu
9236 #define S32_NVIC_IP_PRI18_SHIFT 0u
9237 #define S32_NVIC_IP_PRI18_WIDTH 8u
9238 #define S32_NVIC_IP_PRI18(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI18_SHIFT))&S32_NVIC_IP_PRI18_MASK)
9239 #define S32_NVIC_IP_PRI19_MASK 0xFFu
9240 #define S32_NVIC_IP_PRI19_SHIFT 0u
9241 #define S32_NVIC_IP_PRI19_WIDTH 8u
9242 #define S32_NVIC_IP_PRI19(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI19_SHIFT))&S32_NVIC_IP_PRI19_MASK)
9243 #define S32_NVIC_IP_PRI20_MASK 0xFFu
9244 #define S32_NVIC_IP_PRI20_SHIFT 0u
9245 #define S32_NVIC_IP_PRI20_WIDTH 8u
9246 #define S32_NVIC_IP_PRI20(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI20_SHIFT))&S32_NVIC_IP_PRI20_MASK)
9247 #define S32_NVIC_IP_PRI21_MASK 0xFFu
9248 #define S32_NVIC_IP_PRI21_SHIFT 0u
9249 #define S32_NVIC_IP_PRI21_WIDTH 8u
9250 #define S32_NVIC_IP_PRI21(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI21_SHIFT))&S32_NVIC_IP_PRI21_MASK)
9251 #define S32_NVIC_IP_PRI22_MASK 0xFFu
9252 #define S32_NVIC_IP_PRI22_SHIFT 0u
9253 #define S32_NVIC_IP_PRI22_WIDTH 8u
9254 #define S32_NVIC_IP_PRI22(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI22_SHIFT))&S32_NVIC_IP_PRI22_MASK)
9255 #define S32_NVIC_IP_PRI23_MASK 0xFFu
9256 #define S32_NVIC_IP_PRI23_SHIFT 0u
9257 #define S32_NVIC_IP_PRI23_WIDTH 8u
9258 #define S32_NVIC_IP_PRI23(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI23_SHIFT))&S32_NVIC_IP_PRI23_MASK)
9259 #define S32_NVIC_IP_PRI24_MASK 0xFFu
9260 #define S32_NVIC_IP_PRI24_SHIFT 0u
9261 #define S32_NVIC_IP_PRI24_WIDTH 8u
9262 #define S32_NVIC_IP_PRI24(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI24_SHIFT))&S32_NVIC_IP_PRI24_MASK)
9263 #define S32_NVIC_IP_PRI25_MASK 0xFFu
9264 #define S32_NVIC_IP_PRI25_SHIFT 0u
9265 #define S32_NVIC_IP_PRI25_WIDTH 8u
9266 #define S32_NVIC_IP_PRI25(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI25_SHIFT))&S32_NVIC_IP_PRI25_MASK)
9267 #define S32_NVIC_IP_PRI26_MASK 0xFFu
9268 #define S32_NVIC_IP_PRI26_SHIFT 0u
9269 #define S32_NVIC_IP_PRI26_WIDTH 8u
9270 #define S32_NVIC_IP_PRI26(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI26_SHIFT))&S32_NVIC_IP_PRI26_MASK)
9271 #define S32_NVIC_IP_PRI27_MASK 0xFFu
9272 #define S32_NVIC_IP_PRI27_SHIFT 0u
9273 #define S32_NVIC_IP_PRI27_WIDTH 8u
9274 #define S32_NVIC_IP_PRI27(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI27_SHIFT))&S32_NVIC_IP_PRI27_MASK)
9275 #define S32_NVIC_IP_PRI28_MASK 0xFFu
9276 #define S32_NVIC_IP_PRI28_SHIFT 0u
9277 #define S32_NVIC_IP_PRI28_WIDTH 8u
9278 #define S32_NVIC_IP_PRI28(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI28_SHIFT))&S32_NVIC_IP_PRI28_MASK)
9279 #define S32_NVIC_IP_PRI29_MASK 0xFFu
9280 #define S32_NVIC_IP_PRI29_SHIFT 0u
9281 #define S32_NVIC_IP_PRI29_WIDTH 8u
9282 #define S32_NVIC_IP_PRI29(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI29_SHIFT))&S32_NVIC_IP_PRI29_MASK)
9283 #define S32_NVIC_IP_PRI30_MASK 0xFFu
9284 #define S32_NVIC_IP_PRI30_SHIFT 0u
9285 #define S32_NVIC_IP_PRI30_WIDTH 8u
9286 #define S32_NVIC_IP_PRI30(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI30_SHIFT))&S32_NVIC_IP_PRI30_MASK)
9287 #define S32_NVIC_IP_PRI31_MASK 0xFFu
9288 #define S32_NVIC_IP_PRI31_SHIFT 0u
9289 #define S32_NVIC_IP_PRI31_WIDTH 8u
9290 #define S32_NVIC_IP_PRI31(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI31_SHIFT))&S32_NVIC_IP_PRI31_MASK)
9291 #define S32_NVIC_IP_PRI32_MASK 0xFFu
9292 #define S32_NVIC_IP_PRI32_SHIFT 0u
9293 #define S32_NVIC_IP_PRI32_WIDTH 8u
9294 #define S32_NVIC_IP_PRI32(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI32_SHIFT))&S32_NVIC_IP_PRI32_MASK)
9295 #define S32_NVIC_IP_PRI33_MASK 0xFFu
9296 #define S32_NVIC_IP_PRI33_SHIFT 0u
9297 #define S32_NVIC_IP_PRI33_WIDTH 8u
9298 #define S32_NVIC_IP_PRI33(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI33_SHIFT))&S32_NVIC_IP_PRI33_MASK)
9299 #define S32_NVIC_IP_PRI34_MASK 0xFFu
9300 #define S32_NVIC_IP_PRI34_SHIFT 0u
9301 #define S32_NVIC_IP_PRI34_WIDTH 8u
9302 #define S32_NVIC_IP_PRI34(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI34_SHIFT))&S32_NVIC_IP_PRI34_MASK)
9303 #define S32_NVIC_IP_PRI35_MASK 0xFFu
9304 #define S32_NVIC_IP_PRI35_SHIFT 0u
9305 #define S32_NVIC_IP_PRI35_WIDTH 8u
9306 #define S32_NVIC_IP_PRI35(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI35_SHIFT))&S32_NVIC_IP_PRI35_MASK)
9307 #define S32_NVIC_IP_PRI36_MASK 0xFFu
9308 #define S32_NVIC_IP_PRI36_SHIFT 0u
9309 #define S32_NVIC_IP_PRI36_WIDTH 8u
9310 #define S32_NVIC_IP_PRI36(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI36_SHIFT))&S32_NVIC_IP_PRI36_MASK)
9311 #define S32_NVIC_IP_PRI37_MASK 0xFFu
9312 #define S32_NVIC_IP_PRI37_SHIFT 0u
9313 #define S32_NVIC_IP_PRI37_WIDTH 8u
9314 #define S32_NVIC_IP_PRI37(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI37_SHIFT))&S32_NVIC_IP_PRI37_MASK)
9315 #define S32_NVIC_IP_PRI38_MASK 0xFFu
9316 #define S32_NVIC_IP_PRI38_SHIFT 0u
9317 #define S32_NVIC_IP_PRI38_WIDTH 8u
9318 #define S32_NVIC_IP_PRI38(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI38_SHIFT))&S32_NVIC_IP_PRI38_MASK)
9319 #define S32_NVIC_IP_PRI39_MASK 0xFFu
9320 #define S32_NVIC_IP_PRI39_SHIFT 0u
9321 #define S32_NVIC_IP_PRI39_WIDTH 8u
9322 #define S32_NVIC_IP_PRI39(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI39_SHIFT))&S32_NVIC_IP_PRI39_MASK)
9323 #define S32_NVIC_IP_PRI40_MASK 0xFFu
9324 #define S32_NVIC_IP_PRI40_SHIFT 0u
9325 #define S32_NVIC_IP_PRI40_WIDTH 8u
9326 #define S32_NVIC_IP_PRI40(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI40_SHIFT))&S32_NVIC_IP_PRI40_MASK)
9327 #define S32_NVIC_IP_PRI41_MASK 0xFFu
9328 #define S32_NVIC_IP_PRI41_SHIFT 0u
9329 #define S32_NVIC_IP_PRI41_WIDTH 8u
9330 #define S32_NVIC_IP_PRI41(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI41_SHIFT))&S32_NVIC_IP_PRI41_MASK)
9331 #define S32_NVIC_IP_PRI42_MASK 0xFFu
9332 #define S32_NVIC_IP_PRI42_SHIFT 0u
9333 #define S32_NVIC_IP_PRI42_WIDTH 8u
9334 #define S32_NVIC_IP_PRI42(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI42_SHIFT))&S32_NVIC_IP_PRI42_MASK)
9335 #define S32_NVIC_IP_PRI43_MASK 0xFFu
9336 #define S32_NVIC_IP_PRI43_SHIFT 0u
9337 #define S32_NVIC_IP_PRI43_WIDTH 8u
9338 #define S32_NVIC_IP_PRI43(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI43_SHIFT))&S32_NVIC_IP_PRI43_MASK)
9339 #define S32_NVIC_IP_PRI44_MASK 0xFFu
9340 #define S32_NVIC_IP_PRI44_SHIFT 0u
9341 #define S32_NVIC_IP_PRI44_WIDTH 8u
9342 #define S32_NVIC_IP_PRI44(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI44_SHIFT))&S32_NVIC_IP_PRI44_MASK)
9343 #define S32_NVIC_IP_PRI45_MASK 0xFFu
9344 #define S32_NVIC_IP_PRI45_SHIFT 0u
9345 #define S32_NVIC_IP_PRI45_WIDTH 8u
9346 #define S32_NVIC_IP_PRI45(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI45_SHIFT))&S32_NVIC_IP_PRI45_MASK)
9347 #define S32_NVIC_IP_PRI46_MASK 0xFFu
9348 #define S32_NVIC_IP_PRI46_SHIFT 0u
9349 #define S32_NVIC_IP_PRI46_WIDTH 8u
9350 #define S32_NVIC_IP_PRI46(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI46_SHIFT))&S32_NVIC_IP_PRI46_MASK)
9351 #define S32_NVIC_IP_PRI47_MASK 0xFFu
9352 #define S32_NVIC_IP_PRI47_SHIFT 0u
9353 #define S32_NVIC_IP_PRI47_WIDTH 8u
9354 #define S32_NVIC_IP_PRI47(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI47_SHIFT))&S32_NVIC_IP_PRI47_MASK)
9355 #define S32_NVIC_IP_PRI48_MASK 0xFFu
9356 #define S32_NVIC_IP_PRI48_SHIFT 0u
9357 #define S32_NVIC_IP_PRI48_WIDTH 8u
9358 #define S32_NVIC_IP_PRI48(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI48_SHIFT))&S32_NVIC_IP_PRI48_MASK)
9359 #define S32_NVIC_IP_PRI49_MASK 0xFFu
9360 #define S32_NVIC_IP_PRI49_SHIFT 0u
9361 #define S32_NVIC_IP_PRI49_WIDTH 8u
9362 #define S32_NVIC_IP_PRI49(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI49_SHIFT))&S32_NVIC_IP_PRI49_MASK)
9363 #define S32_NVIC_IP_PRI50_MASK 0xFFu
9364 #define S32_NVIC_IP_PRI50_SHIFT 0u
9365 #define S32_NVIC_IP_PRI50_WIDTH 8u
9366 #define S32_NVIC_IP_PRI50(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI50_SHIFT))&S32_NVIC_IP_PRI50_MASK)
9367 #define S32_NVIC_IP_PRI51_MASK 0xFFu
9368 #define S32_NVIC_IP_PRI51_SHIFT 0u
9369 #define S32_NVIC_IP_PRI51_WIDTH 8u
9370 #define S32_NVIC_IP_PRI51(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI51_SHIFT))&S32_NVIC_IP_PRI51_MASK)
9371 #define S32_NVIC_IP_PRI52_MASK 0xFFu
9372 #define S32_NVIC_IP_PRI52_SHIFT 0u
9373 #define S32_NVIC_IP_PRI52_WIDTH 8u
9374 #define S32_NVIC_IP_PRI52(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI52_SHIFT))&S32_NVIC_IP_PRI52_MASK)
9375 #define S32_NVIC_IP_PRI53_MASK 0xFFu
9376 #define S32_NVIC_IP_PRI53_SHIFT 0u
9377 #define S32_NVIC_IP_PRI53_WIDTH 8u
9378 #define S32_NVIC_IP_PRI53(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI53_SHIFT))&S32_NVIC_IP_PRI53_MASK)
9379 #define S32_NVIC_IP_PRI54_MASK 0xFFu
9380 #define S32_NVIC_IP_PRI54_SHIFT 0u
9381 #define S32_NVIC_IP_PRI54_WIDTH 8u
9382 #define S32_NVIC_IP_PRI54(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI54_SHIFT))&S32_NVIC_IP_PRI54_MASK)
9383 #define S32_NVIC_IP_PRI55_MASK 0xFFu
9384 #define S32_NVIC_IP_PRI55_SHIFT 0u
9385 #define S32_NVIC_IP_PRI55_WIDTH 8u
9386 #define S32_NVIC_IP_PRI55(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI55_SHIFT))&S32_NVIC_IP_PRI55_MASK)
9387 #define S32_NVIC_IP_PRI56_MASK 0xFFu
9388 #define S32_NVIC_IP_PRI56_SHIFT 0u
9389 #define S32_NVIC_IP_PRI56_WIDTH 8u
9390 #define S32_NVIC_IP_PRI56(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI56_SHIFT))&S32_NVIC_IP_PRI56_MASK)
9391 #define S32_NVIC_IP_PRI57_MASK 0xFFu
9392 #define S32_NVIC_IP_PRI57_SHIFT 0u
9393 #define S32_NVIC_IP_PRI57_WIDTH 8u
9394 #define S32_NVIC_IP_PRI57(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI57_SHIFT))&S32_NVIC_IP_PRI57_MASK)
9395 #define S32_NVIC_IP_PRI58_MASK 0xFFu
9396 #define S32_NVIC_IP_PRI58_SHIFT 0u
9397 #define S32_NVIC_IP_PRI58_WIDTH 8u
9398 #define S32_NVIC_IP_PRI58(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI58_SHIFT))&S32_NVIC_IP_PRI58_MASK)
9399 #define S32_NVIC_IP_PRI59_MASK 0xFFu
9400 #define S32_NVIC_IP_PRI59_SHIFT 0u
9401 #define S32_NVIC_IP_PRI59_WIDTH 8u
9402 #define S32_NVIC_IP_PRI59(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI59_SHIFT))&S32_NVIC_IP_PRI59_MASK)
9403 #define S32_NVIC_IP_PRI60_MASK 0xFFu
9404 #define S32_NVIC_IP_PRI60_SHIFT 0u
9405 #define S32_NVIC_IP_PRI60_WIDTH 8u
9406 #define S32_NVIC_IP_PRI60(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI60_SHIFT))&S32_NVIC_IP_PRI60_MASK)
9407 #define S32_NVIC_IP_PRI61_MASK 0xFFu
9408 #define S32_NVIC_IP_PRI61_SHIFT 0u
9409 #define S32_NVIC_IP_PRI61_WIDTH 8u
9410 #define S32_NVIC_IP_PRI61(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI61_SHIFT))&S32_NVIC_IP_PRI61_MASK)
9411 #define S32_NVIC_IP_PRI62_MASK 0xFFu
9412 #define S32_NVIC_IP_PRI62_SHIFT 0u
9413 #define S32_NVIC_IP_PRI62_WIDTH 8u
9414 #define S32_NVIC_IP_PRI62(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI62_SHIFT))&S32_NVIC_IP_PRI62_MASK)
9415 #define S32_NVIC_IP_PRI63_MASK 0xFFu
9416 #define S32_NVIC_IP_PRI63_SHIFT 0u
9417 #define S32_NVIC_IP_PRI63_WIDTH 8u
9418 #define S32_NVIC_IP_PRI63(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI63_SHIFT))&S32_NVIC_IP_PRI63_MASK)
9419 #define S32_NVIC_IP_PRI64_MASK 0xFFu
9420 #define S32_NVIC_IP_PRI64_SHIFT 0u
9421 #define S32_NVIC_IP_PRI64_WIDTH 8u
9422 #define S32_NVIC_IP_PRI64(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI64_SHIFT))&S32_NVIC_IP_PRI64_MASK)
9423 #define S32_NVIC_IP_PRI65_MASK 0xFFu
9424 #define S32_NVIC_IP_PRI65_SHIFT 0u
9425 #define S32_NVIC_IP_PRI65_WIDTH 8u
9426 #define S32_NVIC_IP_PRI65(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI65_SHIFT))&S32_NVIC_IP_PRI65_MASK)
9427 #define S32_NVIC_IP_PRI66_MASK 0xFFu
9428 #define S32_NVIC_IP_PRI66_SHIFT 0u
9429 #define S32_NVIC_IP_PRI66_WIDTH 8u
9430 #define S32_NVIC_IP_PRI66(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI66_SHIFT))&S32_NVIC_IP_PRI66_MASK)
9431 #define S32_NVIC_IP_PRI67_MASK 0xFFu
9432 #define S32_NVIC_IP_PRI67_SHIFT 0u
9433 #define S32_NVIC_IP_PRI67_WIDTH 8u
9434 #define S32_NVIC_IP_PRI67(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI67_SHIFT))&S32_NVIC_IP_PRI67_MASK)
9435 #define S32_NVIC_IP_PRI68_MASK 0xFFu
9436 #define S32_NVIC_IP_PRI68_SHIFT 0u
9437 #define S32_NVIC_IP_PRI68_WIDTH 8u
9438 #define S32_NVIC_IP_PRI68(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI68_SHIFT))&S32_NVIC_IP_PRI68_MASK)
9439 #define S32_NVIC_IP_PRI69_MASK 0xFFu
9440 #define S32_NVIC_IP_PRI69_SHIFT 0u
9441 #define S32_NVIC_IP_PRI69_WIDTH 8u
9442 #define S32_NVIC_IP_PRI69(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI69_SHIFT))&S32_NVIC_IP_PRI69_MASK)
9443 #define S32_NVIC_IP_PRI70_MASK 0xFFu
9444 #define S32_NVIC_IP_PRI70_SHIFT 0u
9445 #define S32_NVIC_IP_PRI70_WIDTH 8u
9446 #define S32_NVIC_IP_PRI70(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI70_SHIFT))&S32_NVIC_IP_PRI70_MASK)
9447 #define S32_NVIC_IP_PRI71_MASK 0xFFu
9448 #define S32_NVIC_IP_PRI71_SHIFT 0u
9449 #define S32_NVIC_IP_PRI71_WIDTH 8u
9450 #define S32_NVIC_IP_PRI71(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI71_SHIFT))&S32_NVIC_IP_PRI71_MASK)
9451 #define S32_NVIC_IP_PRI72_MASK 0xFFu
9452 #define S32_NVIC_IP_PRI72_SHIFT 0u
9453 #define S32_NVIC_IP_PRI72_WIDTH 8u
9454 #define S32_NVIC_IP_PRI72(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI72_SHIFT))&S32_NVIC_IP_PRI72_MASK)
9455 #define S32_NVIC_IP_PRI73_MASK 0xFFu
9456 #define S32_NVIC_IP_PRI73_SHIFT 0u
9457 #define S32_NVIC_IP_PRI73_WIDTH 8u
9458 #define S32_NVIC_IP_PRI73(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI73_SHIFT))&S32_NVIC_IP_PRI73_MASK)
9459 #define S32_NVIC_IP_PRI74_MASK 0xFFu
9460 #define S32_NVIC_IP_PRI74_SHIFT 0u
9461 #define S32_NVIC_IP_PRI74_WIDTH 8u
9462 #define S32_NVIC_IP_PRI74(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI74_SHIFT))&S32_NVIC_IP_PRI74_MASK)
9463 #define S32_NVIC_IP_PRI75_MASK 0xFFu
9464 #define S32_NVIC_IP_PRI75_SHIFT 0u
9465 #define S32_NVIC_IP_PRI75_WIDTH 8u
9466 #define S32_NVIC_IP_PRI75(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI75_SHIFT))&S32_NVIC_IP_PRI75_MASK)
9467 #define S32_NVIC_IP_PRI76_MASK 0xFFu
9468 #define S32_NVIC_IP_PRI76_SHIFT 0u
9469 #define S32_NVIC_IP_PRI76_WIDTH 8u
9470 #define S32_NVIC_IP_PRI76(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI76_SHIFT))&S32_NVIC_IP_PRI76_MASK)
9471 #define S32_NVIC_IP_PRI77_MASK 0xFFu
9472 #define S32_NVIC_IP_PRI77_SHIFT 0u
9473 #define S32_NVIC_IP_PRI77_WIDTH 8u
9474 #define S32_NVIC_IP_PRI77(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI77_SHIFT))&S32_NVIC_IP_PRI77_MASK)
9475 #define S32_NVIC_IP_PRI78_MASK 0xFFu
9476 #define S32_NVIC_IP_PRI78_SHIFT 0u
9477 #define S32_NVIC_IP_PRI78_WIDTH 8u
9478 #define S32_NVIC_IP_PRI78(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI78_SHIFT))&S32_NVIC_IP_PRI78_MASK)
9479 #define S32_NVIC_IP_PRI79_MASK 0xFFu
9480 #define S32_NVIC_IP_PRI79_SHIFT 0u
9481 #define S32_NVIC_IP_PRI79_WIDTH 8u
9482 #define S32_NVIC_IP_PRI79(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI79_SHIFT))&S32_NVIC_IP_PRI79_MASK)
9483 #define S32_NVIC_IP_PRI80_MASK 0xFFu
9484 #define S32_NVIC_IP_PRI80_SHIFT 0u
9485 #define S32_NVIC_IP_PRI80_WIDTH 8u
9486 #define S32_NVIC_IP_PRI80(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI80_SHIFT))&S32_NVIC_IP_PRI80_MASK)
9487 #define S32_NVIC_IP_PRI81_MASK 0xFFu
9488 #define S32_NVIC_IP_PRI81_SHIFT 0u
9489 #define S32_NVIC_IP_PRI81_WIDTH 8u
9490 #define S32_NVIC_IP_PRI81(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI81_SHIFT))&S32_NVIC_IP_PRI81_MASK)
9491 #define S32_NVIC_IP_PRI82_MASK 0xFFu
9492 #define S32_NVIC_IP_PRI82_SHIFT 0u
9493 #define S32_NVIC_IP_PRI82_WIDTH 8u
9494 #define S32_NVIC_IP_PRI82(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI82_SHIFT))&S32_NVIC_IP_PRI82_MASK)
9495 #define S32_NVIC_IP_PRI83_MASK 0xFFu
9496 #define S32_NVIC_IP_PRI83_SHIFT 0u
9497 #define S32_NVIC_IP_PRI83_WIDTH 8u
9498 #define S32_NVIC_IP_PRI83(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI83_SHIFT))&S32_NVIC_IP_PRI83_MASK)
9499 #define S32_NVIC_IP_PRI84_MASK 0xFFu
9500 #define S32_NVIC_IP_PRI84_SHIFT 0u
9501 #define S32_NVIC_IP_PRI84_WIDTH 8u
9502 #define S32_NVIC_IP_PRI84(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI84_SHIFT))&S32_NVIC_IP_PRI84_MASK)
9503 #define S32_NVIC_IP_PRI85_MASK 0xFFu
9504 #define S32_NVIC_IP_PRI85_SHIFT 0u
9505 #define S32_NVIC_IP_PRI85_WIDTH 8u
9506 #define S32_NVIC_IP_PRI85(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI85_SHIFT))&S32_NVIC_IP_PRI85_MASK)
9507 #define S32_NVIC_IP_PRI86_MASK 0xFFu
9508 #define S32_NVIC_IP_PRI86_SHIFT 0u
9509 #define S32_NVIC_IP_PRI86_WIDTH 8u
9510 #define S32_NVIC_IP_PRI86(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI86_SHIFT))&S32_NVIC_IP_PRI86_MASK)
9511 #define S32_NVIC_IP_PRI87_MASK 0xFFu
9512 #define S32_NVIC_IP_PRI87_SHIFT 0u
9513 #define S32_NVIC_IP_PRI87_WIDTH 8u
9514 #define S32_NVIC_IP_PRI87(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI87_SHIFT))&S32_NVIC_IP_PRI87_MASK)
9515 #define S32_NVIC_IP_PRI88_MASK 0xFFu
9516 #define S32_NVIC_IP_PRI88_SHIFT 0u
9517 #define S32_NVIC_IP_PRI88_WIDTH 8u
9518 #define S32_NVIC_IP_PRI88(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI88_SHIFT))&S32_NVIC_IP_PRI88_MASK)
9519 #define S32_NVIC_IP_PRI89_MASK 0xFFu
9520 #define S32_NVIC_IP_PRI89_SHIFT 0u
9521 #define S32_NVIC_IP_PRI89_WIDTH 8u
9522 #define S32_NVIC_IP_PRI89(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI89_SHIFT))&S32_NVIC_IP_PRI89_MASK)
9523 #define S32_NVIC_IP_PRI90_MASK 0xFFu
9524 #define S32_NVIC_IP_PRI90_SHIFT 0u
9525 #define S32_NVIC_IP_PRI90_WIDTH 8u
9526 #define S32_NVIC_IP_PRI90(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI90_SHIFT))&S32_NVIC_IP_PRI90_MASK)
9527 #define S32_NVIC_IP_PRI91_MASK 0xFFu
9528 #define S32_NVIC_IP_PRI91_SHIFT 0u
9529 #define S32_NVIC_IP_PRI91_WIDTH 8u
9530 #define S32_NVIC_IP_PRI91(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI91_SHIFT))&S32_NVIC_IP_PRI91_MASK)
9531 #define S32_NVIC_IP_PRI92_MASK 0xFFu
9532 #define S32_NVIC_IP_PRI92_SHIFT 0u
9533 #define S32_NVIC_IP_PRI92_WIDTH 8u
9534 #define S32_NVIC_IP_PRI92(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI92_SHIFT))&S32_NVIC_IP_PRI92_MASK)
9535 #define S32_NVIC_IP_PRI93_MASK 0xFFu
9536 #define S32_NVIC_IP_PRI93_SHIFT 0u
9537 #define S32_NVIC_IP_PRI93_WIDTH 8u
9538 #define S32_NVIC_IP_PRI93(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI93_SHIFT))&S32_NVIC_IP_PRI93_MASK)
9539 #define S32_NVIC_IP_PRI94_MASK 0xFFu
9540 #define S32_NVIC_IP_PRI94_SHIFT 0u
9541 #define S32_NVIC_IP_PRI94_WIDTH 8u
9542 #define S32_NVIC_IP_PRI94(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI94_SHIFT))&S32_NVIC_IP_PRI94_MASK)
9543 #define S32_NVIC_IP_PRI95_MASK 0xFFu
9544 #define S32_NVIC_IP_PRI95_SHIFT 0u
9545 #define S32_NVIC_IP_PRI95_WIDTH 8u
9546 #define S32_NVIC_IP_PRI95(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI95_SHIFT))&S32_NVIC_IP_PRI95_MASK)
9547 #define S32_NVIC_IP_PRI96_MASK 0xFFu
9548 #define S32_NVIC_IP_PRI96_SHIFT 0u
9549 #define S32_NVIC_IP_PRI96_WIDTH 8u
9550 #define S32_NVIC_IP_PRI96(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI96_SHIFT))&S32_NVIC_IP_PRI96_MASK)
9551 #define S32_NVIC_IP_PRI97_MASK 0xFFu
9552 #define S32_NVIC_IP_PRI97_SHIFT 0u
9553 #define S32_NVIC_IP_PRI97_WIDTH 8u
9554 #define S32_NVIC_IP_PRI97(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI97_SHIFT))&S32_NVIC_IP_PRI97_MASK)
9555 #define S32_NVIC_IP_PRI98_MASK 0xFFu
9556 #define S32_NVIC_IP_PRI98_SHIFT 0u
9557 #define S32_NVIC_IP_PRI98_WIDTH 8u
9558 #define S32_NVIC_IP_PRI98(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI98_SHIFT))&S32_NVIC_IP_PRI98_MASK)
9559 #define S32_NVIC_IP_PRI99_MASK 0xFFu
9560 #define S32_NVIC_IP_PRI99_SHIFT 0u
9561 #define S32_NVIC_IP_PRI99_WIDTH 8u
9562 #define S32_NVIC_IP_PRI99(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI99_SHIFT))&S32_NVIC_IP_PRI99_MASK)
9563 #define S32_NVIC_IP_PRI100_MASK 0xFFu
9564 #define S32_NVIC_IP_PRI100_SHIFT 0u
9565 #define S32_NVIC_IP_PRI100_WIDTH 8u
9566 #define S32_NVIC_IP_PRI100(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI100_SHIFT))&S32_NVIC_IP_PRI100_MASK)
9567 #define S32_NVIC_IP_PRI101_MASK 0xFFu
9568 #define S32_NVIC_IP_PRI101_SHIFT 0u
9569 #define S32_NVIC_IP_PRI101_WIDTH 8u
9570 #define S32_NVIC_IP_PRI101(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI101_SHIFT))&S32_NVIC_IP_PRI101_MASK)
9571 #define S32_NVIC_IP_PRI102_MASK 0xFFu
9572 #define S32_NVIC_IP_PRI102_SHIFT 0u
9573 #define S32_NVIC_IP_PRI102_WIDTH 8u
9574 #define S32_NVIC_IP_PRI102(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI102_SHIFT))&S32_NVIC_IP_PRI102_MASK)
9575 #define S32_NVIC_IP_PRI103_MASK 0xFFu
9576 #define S32_NVIC_IP_PRI103_SHIFT 0u
9577 #define S32_NVIC_IP_PRI103_WIDTH 8u
9578 #define S32_NVIC_IP_PRI103(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI103_SHIFT))&S32_NVIC_IP_PRI103_MASK)
9579 #define S32_NVIC_IP_PRI104_MASK 0xFFu
9580 #define S32_NVIC_IP_PRI104_SHIFT 0u
9581 #define S32_NVIC_IP_PRI104_WIDTH 8u
9582 #define S32_NVIC_IP_PRI104(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI104_SHIFT))&S32_NVIC_IP_PRI104_MASK)
9583 #define S32_NVIC_IP_PRI105_MASK 0xFFu
9584 #define S32_NVIC_IP_PRI105_SHIFT 0u
9585 #define S32_NVIC_IP_PRI105_WIDTH 8u
9586 #define S32_NVIC_IP_PRI105(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI105_SHIFT))&S32_NVIC_IP_PRI105_MASK)
9587 #define S32_NVIC_IP_PRI106_MASK 0xFFu
9588 #define S32_NVIC_IP_PRI106_SHIFT 0u
9589 #define S32_NVIC_IP_PRI106_WIDTH 8u
9590 #define S32_NVIC_IP_PRI106(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI106_SHIFT))&S32_NVIC_IP_PRI106_MASK)
9591 #define S32_NVIC_IP_PRI107_MASK 0xFFu
9592 #define S32_NVIC_IP_PRI107_SHIFT 0u
9593 #define S32_NVIC_IP_PRI107_WIDTH 8u
9594 #define S32_NVIC_IP_PRI107(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI107_SHIFT))&S32_NVIC_IP_PRI107_MASK)
9595 #define S32_NVIC_IP_PRI108_MASK 0xFFu
9596 #define S32_NVIC_IP_PRI108_SHIFT 0u
9597 #define S32_NVIC_IP_PRI108_WIDTH 8u
9598 #define S32_NVIC_IP_PRI108(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI108_SHIFT))&S32_NVIC_IP_PRI108_MASK)
9599 #define S32_NVIC_IP_PRI109_MASK 0xFFu
9600 #define S32_NVIC_IP_PRI109_SHIFT 0u
9601 #define S32_NVIC_IP_PRI109_WIDTH 8u
9602 #define S32_NVIC_IP_PRI109(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI109_SHIFT))&S32_NVIC_IP_PRI109_MASK)
9603 #define S32_NVIC_IP_PRI110_MASK 0xFFu
9604 #define S32_NVIC_IP_PRI110_SHIFT 0u
9605 #define S32_NVIC_IP_PRI110_WIDTH 8u
9606 #define S32_NVIC_IP_PRI110(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI110_SHIFT))&S32_NVIC_IP_PRI110_MASK)
9607 #define S32_NVIC_IP_PRI111_MASK 0xFFu
9608 #define S32_NVIC_IP_PRI111_SHIFT 0u
9609 #define S32_NVIC_IP_PRI111_WIDTH 8u
9610 #define S32_NVIC_IP_PRI111(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI111_SHIFT))&S32_NVIC_IP_PRI111_MASK)
9611 #define S32_NVIC_IP_PRI112_MASK 0xFFu
9612 #define S32_NVIC_IP_PRI112_SHIFT 0u
9613 #define S32_NVIC_IP_PRI112_WIDTH 8u
9614 #define S32_NVIC_IP_PRI112(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI112_SHIFT))&S32_NVIC_IP_PRI112_MASK)
9615 #define S32_NVIC_IP_PRI113_MASK 0xFFu
9616 #define S32_NVIC_IP_PRI113_SHIFT 0u
9617 #define S32_NVIC_IP_PRI113_WIDTH 8u
9618 #define S32_NVIC_IP_PRI113(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI113_SHIFT))&S32_NVIC_IP_PRI113_MASK)
9619 #define S32_NVIC_IP_PRI114_MASK 0xFFu
9620 #define S32_NVIC_IP_PRI114_SHIFT 0u
9621 #define S32_NVIC_IP_PRI114_WIDTH 8u
9622 #define S32_NVIC_IP_PRI114(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI114_SHIFT))&S32_NVIC_IP_PRI114_MASK)
9623 #define S32_NVIC_IP_PRI115_MASK 0xFFu
9624 #define S32_NVIC_IP_PRI115_SHIFT 0u
9625 #define S32_NVIC_IP_PRI115_WIDTH 8u
9626 #define S32_NVIC_IP_PRI115(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI115_SHIFT))&S32_NVIC_IP_PRI115_MASK)
9627 #define S32_NVIC_IP_PRI116_MASK 0xFFu
9628 #define S32_NVIC_IP_PRI116_SHIFT 0u
9629 #define S32_NVIC_IP_PRI116_WIDTH 8u
9630 #define S32_NVIC_IP_PRI116(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI116_SHIFT))&S32_NVIC_IP_PRI116_MASK)
9631 #define S32_NVIC_IP_PRI117_MASK 0xFFu
9632 #define S32_NVIC_IP_PRI117_SHIFT 0u
9633 #define S32_NVIC_IP_PRI117_WIDTH 8u
9634 #define S32_NVIC_IP_PRI117(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI117_SHIFT))&S32_NVIC_IP_PRI117_MASK)
9635 #define S32_NVIC_IP_PRI118_MASK 0xFFu
9636 #define S32_NVIC_IP_PRI118_SHIFT 0u
9637 #define S32_NVIC_IP_PRI118_WIDTH 8u
9638 #define S32_NVIC_IP_PRI118(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI118_SHIFT))&S32_NVIC_IP_PRI118_MASK)
9639 #define S32_NVIC_IP_PRI119_MASK 0xFFu
9640 #define S32_NVIC_IP_PRI119_SHIFT 0u
9641 #define S32_NVIC_IP_PRI119_WIDTH 8u
9642 #define S32_NVIC_IP_PRI119(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI119_SHIFT))&S32_NVIC_IP_PRI119_MASK)
9643 #define S32_NVIC_IP_PRI120_MASK 0xFFu
9644 #define S32_NVIC_IP_PRI120_SHIFT 0u
9645 #define S32_NVIC_IP_PRI120_WIDTH 8u
9646 #define S32_NVIC_IP_PRI120(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI120_SHIFT))&S32_NVIC_IP_PRI120_MASK)
9647 #define S32_NVIC_IP_PRI121_MASK 0xFFu
9648 #define S32_NVIC_IP_PRI121_SHIFT 0u
9649 #define S32_NVIC_IP_PRI121_WIDTH 8u
9650 #define S32_NVIC_IP_PRI121(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI121_SHIFT))&S32_NVIC_IP_PRI121_MASK)
9651 #define S32_NVIC_IP_PRI122_MASK 0xFFu
9652 #define S32_NVIC_IP_PRI122_SHIFT 0u
9653 #define S32_NVIC_IP_PRI122_WIDTH 8u
9654 #define S32_NVIC_IP_PRI122(x) (((uint8_t)(((uint8_t)(x))<<S32_NVIC_IP_PRI122_SHIFT))&S32_NVIC_IP_PRI122_MASK)
9655 /* STIR Bit Fields */
9656 #define S32_NVIC_STIR_INTID_MASK 0x1FFu
9657 #define S32_NVIC_STIR_INTID_SHIFT 0u
9658 #define S32_NVIC_STIR_INTID_WIDTH 9u
9659 #define S32_NVIC_STIR_INTID(x) (((uint32_t)(((uint32_t)(x))<<S32_NVIC_STIR_INTID_SHIFT))&S32_NVIC_STIR_INTID_MASK)
9660  /* end of group S32_NVIC_Register_Masks */
9664 
9665  /* end of group S32_NVIC_Peripheral_Access_Layer */
9669 
9670 
9671 /* ----------------------------------------------------------------------------
9672  -- S32_SCB Peripheral Access Layer
9673  ---------------------------------------------------------------------------- */
9674 
9684 typedef struct {
9685  uint8_t RESERVED_0[8];
9686  __IO uint32_t ACTLR;
9687  uint8_t RESERVED_1[3316];
9688  __I uint32_t CPUID;
9689  __IO uint32_t ICSR;
9690  __IO uint32_t VTOR;
9691  __IO uint32_t AIRCR;
9692  __IO uint32_t SCR;
9693  __IO uint32_t CCR;
9694  __IO uint32_t SHPR1;
9695  __IO uint32_t SHPR2;
9696  __IO uint32_t SHPR3;
9697  __IO uint32_t SHCSR;
9698  __IO uint32_t CFSR;
9699  __IO uint32_t HFSR;
9700  __IO uint32_t DFSR;
9701  __IO uint32_t MMFAR;
9702  __IO uint32_t BFAR;
9703  __IO uint32_t AFSR;
9704  uint8_t RESERVED_2[72];
9705  __IO uint32_t CPACR;
9706  uint8_t RESERVED_3[424];
9707  __IO uint32_t FPCCR;
9708  __IO uint32_t FPCAR;
9709  __IO uint32_t FPDSCR;
9711 
9713 #define S32_SCB_INSTANCE_COUNT (1u)
9714 
9715 
9716 /* S32_SCB - Peripheral instance base addresses */
9718 #define S32_SCB_BASE (0xE000E000u)
9719 
9720 #define S32_SCB ((S32_SCB_Type *)S32_SCB_BASE)
9721 
9722 #define S32_SCB_BASE_ADDRS { S32_SCB_BASE }
9723 
9724 #define S32_SCB_BASE_PTRS { S32_SCB }
9725 
9726 /* ----------------------------------------------------------------------------
9727  -- S32_SCB Register Masks
9728  ---------------------------------------------------------------------------- */
9729 
9735 /* ACTLR Bit Fields */
9736 #define S32_SCB_ACTLR_DISMCYCINT_MASK 0x1u
9737 #define S32_SCB_ACTLR_DISMCYCINT_SHIFT 0u
9738 #define S32_SCB_ACTLR_DISMCYCINT_WIDTH 1u
9739 #define S32_SCB_ACTLR_DISMCYCINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISMCYCINT_SHIFT))&S32_SCB_ACTLR_DISMCYCINT_MASK)
9740 #define S32_SCB_ACTLR_DISDEFWBUF_MASK 0x2u
9741 #define S32_SCB_ACTLR_DISDEFWBUF_SHIFT 1u
9742 #define S32_SCB_ACTLR_DISDEFWBUF_WIDTH 1u
9743 #define S32_SCB_ACTLR_DISDEFWBUF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISDEFWBUF_SHIFT))&S32_SCB_ACTLR_DISDEFWBUF_MASK)
9744 #define S32_SCB_ACTLR_DISFOLD_MASK 0x4u
9745 #define S32_SCB_ACTLR_DISFOLD_SHIFT 2u
9746 #define S32_SCB_ACTLR_DISFOLD_WIDTH 1u
9747 #define S32_SCB_ACTLR_DISFOLD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFOLD_SHIFT))&S32_SCB_ACTLR_DISFOLD_MASK)
9748 #define S32_SCB_ACTLR_DISFPCA_MASK 0x100u
9749 #define S32_SCB_ACTLR_DISFPCA_SHIFT 8u
9750 #define S32_SCB_ACTLR_DISFPCA_WIDTH 1u
9751 #define S32_SCB_ACTLR_DISFPCA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFPCA_SHIFT))&S32_SCB_ACTLR_DISFPCA_MASK)
9752 #define S32_SCB_ACTLR_DISOOFP_MASK 0x200u
9753 #define S32_SCB_ACTLR_DISOOFP_SHIFT 9u
9754 #define S32_SCB_ACTLR_DISOOFP_WIDTH 1u
9755 #define S32_SCB_ACTLR_DISOOFP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISOOFP_SHIFT))&S32_SCB_ACTLR_DISOOFP_MASK)
9756 /* CPUID Bit Fields */
9757 #define S32_SCB_CPUID_REVISION_MASK 0xFu
9758 #define S32_SCB_CPUID_REVISION_SHIFT 0u
9759 #define S32_SCB_CPUID_REVISION_WIDTH 4u
9760 #define S32_SCB_CPUID_REVISION(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK)
9761 #define S32_SCB_CPUID_PARTNO_MASK 0xFFF0u
9762 #define S32_SCB_CPUID_PARTNO_SHIFT 4u
9763 #define S32_SCB_CPUID_PARTNO_WIDTH 12u
9764 #define S32_SCB_CPUID_PARTNO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK)
9765 #define S32_SCB_CPUID_VARIANT_MASK 0xF00000u
9766 #define S32_SCB_CPUID_VARIANT_SHIFT 20u
9767 #define S32_SCB_CPUID_VARIANT_WIDTH 4u
9768 #define S32_SCB_CPUID_VARIANT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK)
9769 #define S32_SCB_CPUID_IMPLEMENTER_MASK 0xFF000000u
9770 #define S32_SCB_CPUID_IMPLEMENTER_SHIFT 24u
9771 #define S32_SCB_CPUID_IMPLEMENTER_WIDTH 8u
9772 #define S32_SCB_CPUID_IMPLEMENTER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK)
9773 /* ICSR Bit Fields */
9774 #define S32_SCB_ICSR_VECTACTIVE_MASK 0x1FFu
9775 #define S32_SCB_ICSR_VECTACTIVE_SHIFT 0u
9776 #define S32_SCB_ICSR_VECTACTIVE_WIDTH 9u
9777 #define S32_SCB_ICSR_VECTACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK)
9778 #define S32_SCB_ICSR_RETTOBASE_MASK 0x800u
9779 #define S32_SCB_ICSR_RETTOBASE_SHIFT 11u
9780 #define S32_SCB_ICSR_RETTOBASE_WIDTH 1u
9781 #define S32_SCB_ICSR_RETTOBASE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_RETTOBASE_SHIFT))&S32_SCB_ICSR_RETTOBASE_MASK)
9782 #define S32_SCB_ICSR_VECTPENDING_MASK 0x3F000u
9783 #define S32_SCB_ICSR_VECTPENDING_SHIFT 12u
9784 #define S32_SCB_ICSR_VECTPENDING_WIDTH 6u
9785 #define S32_SCB_ICSR_VECTPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK)
9786 #define S32_SCB_ICSR_ISRPENDING_MASK 0x400000u
9787 #define S32_SCB_ICSR_ISRPENDING_SHIFT 22u
9788 #define S32_SCB_ICSR_ISRPENDING_WIDTH 1u
9789 #define S32_SCB_ICSR_ISRPENDING(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK)
9790 #define S32_SCB_ICSR_ISRPREEMPT_MASK 0x800000u
9791 #define S32_SCB_ICSR_ISRPREEMPT_SHIFT 23u
9792 #define S32_SCB_ICSR_ISRPREEMPT_WIDTH 1u
9793 #define S32_SCB_ICSR_ISRPREEMPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPREEMPT_SHIFT))&S32_SCB_ICSR_ISRPREEMPT_MASK)
9794 #define S32_SCB_ICSR_PENDSTCLR_MASK 0x2000000u
9795 #define S32_SCB_ICSR_PENDSTCLR_SHIFT 25u
9796 #define S32_SCB_ICSR_PENDSTCLR_WIDTH 1u
9797 #define S32_SCB_ICSR_PENDSTCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK)
9798 #define S32_SCB_ICSR_PENDSTSET_MASK 0x4000000u
9799 #define S32_SCB_ICSR_PENDSTSET_SHIFT 26u
9800 #define S32_SCB_ICSR_PENDSTSET_WIDTH 1u
9801 #define S32_SCB_ICSR_PENDSTSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK)
9802 #define S32_SCB_ICSR_PENDSVCLR_MASK 0x8000000u
9803 #define S32_SCB_ICSR_PENDSVCLR_SHIFT 27u
9804 #define S32_SCB_ICSR_PENDSVCLR_WIDTH 1u
9805 #define S32_SCB_ICSR_PENDSVCLR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK)
9806 #define S32_SCB_ICSR_PENDSVSET_MASK 0x10000000u
9807 #define S32_SCB_ICSR_PENDSVSET_SHIFT 28u
9808 #define S32_SCB_ICSR_PENDSVSET_WIDTH 1u
9809 #define S32_SCB_ICSR_PENDSVSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK)
9810 #define S32_SCB_ICSR_NMIPENDSET_MASK 0x80000000u
9811 #define S32_SCB_ICSR_NMIPENDSET_SHIFT 31u
9812 #define S32_SCB_ICSR_NMIPENDSET_WIDTH 1u
9813 #define S32_SCB_ICSR_NMIPENDSET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK)
9814 /* VTOR Bit Fields */
9815 #define S32_SCB_VTOR_TBLOFF_MASK 0xFFFFFF80u
9816 #define S32_SCB_VTOR_TBLOFF_SHIFT 7u
9817 #define S32_SCB_VTOR_TBLOFF_WIDTH 25u
9818 #define S32_SCB_VTOR_TBLOFF(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK)
9819 /* AIRCR Bit Fields */
9820 #define S32_SCB_AIRCR_VECTRESET_MASK 0x1u
9821 #define S32_SCB_AIRCR_VECTRESET_SHIFT 0u
9822 #define S32_SCB_AIRCR_VECTRESET_WIDTH 1u
9823 #define S32_SCB_AIRCR_VECTRESET(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTRESET_SHIFT))&S32_SCB_AIRCR_VECTRESET_MASK)
9824 #define S32_SCB_AIRCR_VECTCLRACTIVE_MASK 0x2u
9825 #define S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT 1u
9826 #define S32_SCB_AIRCR_VECTCLRACTIVE_WIDTH 1u
9827 #define S32_SCB_AIRCR_VECTCLRACTIVE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK)
9828 #define S32_SCB_AIRCR_SYSRESETREQ_MASK 0x4u
9829 #define S32_SCB_AIRCR_SYSRESETREQ_SHIFT 2u
9830 #define S32_SCB_AIRCR_SYSRESETREQ_WIDTH 1u
9831 #define S32_SCB_AIRCR_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK)
9832 #define S32_SCB_AIRCR_PRIGROUP_MASK 0x700u
9833 #define S32_SCB_AIRCR_PRIGROUP_SHIFT 8u
9834 #define S32_SCB_AIRCR_PRIGROUP_WIDTH 3u
9835 #define S32_SCB_AIRCR_PRIGROUP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_PRIGROUP_SHIFT))&S32_SCB_AIRCR_PRIGROUP_MASK)
9836 #define S32_SCB_AIRCR_ENDIANNESS_MASK 0x8000u
9837 #define S32_SCB_AIRCR_ENDIANNESS_SHIFT 15u
9838 #define S32_SCB_AIRCR_ENDIANNESS_WIDTH 1u
9839 #define S32_SCB_AIRCR_ENDIANNESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK)
9840 #define S32_SCB_AIRCR_VECTKEY_MASK 0xFFFF0000u
9841 #define S32_SCB_AIRCR_VECTKEY_SHIFT 16u
9842 #define S32_SCB_AIRCR_VECTKEY_WIDTH 16u
9843 #define S32_SCB_AIRCR_VECTKEY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK)
9844 /* SCR Bit Fields */
9845 #define S32_SCB_SCR_SLEEPONEXIT_MASK 0x2u
9846 #define S32_SCB_SCR_SLEEPONEXIT_SHIFT 1u
9847 #define S32_SCB_SCR_SLEEPONEXIT_WIDTH 1u
9848 #define S32_SCB_SCR_SLEEPONEXIT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK)
9849 #define S32_SCB_SCR_SLEEPDEEP_MASK 0x4u
9850 #define S32_SCB_SCR_SLEEPDEEP_SHIFT 2u
9851 #define S32_SCB_SCR_SLEEPDEEP_WIDTH 1u
9852 #define S32_SCB_SCR_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK)
9853 #define S32_SCB_SCR_SEVONPEND_MASK 0x10u
9854 #define S32_SCB_SCR_SEVONPEND_SHIFT 4u
9855 #define S32_SCB_SCR_SEVONPEND_WIDTH 1u
9856 #define S32_SCB_SCR_SEVONPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK)
9857 /* CCR Bit Fields */
9858 #define S32_SCB_CCR_NONBASETHRDENA_MASK 0x1u
9859 #define S32_SCB_CCR_NONBASETHRDENA_SHIFT 0u
9860 #define S32_SCB_CCR_NONBASETHRDENA_WIDTH 1u
9861 #define S32_SCB_CCR_NONBASETHRDENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_NONBASETHRDENA_SHIFT))&S32_SCB_CCR_NONBASETHRDENA_MASK)
9862 #define S32_SCB_CCR_USERSETMPEND_MASK 0x2u
9863 #define S32_SCB_CCR_USERSETMPEND_SHIFT 1u
9864 #define S32_SCB_CCR_USERSETMPEND_WIDTH 1u
9865 #define S32_SCB_CCR_USERSETMPEND(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_USERSETMPEND_SHIFT))&S32_SCB_CCR_USERSETMPEND_MASK)
9866 #define S32_SCB_CCR_UNALIGN_TRP_MASK 0x8u
9867 #define S32_SCB_CCR_UNALIGN_TRP_SHIFT 3u
9868 #define S32_SCB_CCR_UNALIGN_TRP_WIDTH 1u
9869 #define S32_SCB_CCR_UNALIGN_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK)
9870 #define S32_SCB_CCR_DIV_0_TRP_MASK 0x10u
9871 #define S32_SCB_CCR_DIV_0_TRP_SHIFT 4u
9872 #define S32_SCB_CCR_DIV_0_TRP_WIDTH 1u
9873 #define S32_SCB_CCR_DIV_0_TRP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_DIV_0_TRP_SHIFT))&S32_SCB_CCR_DIV_0_TRP_MASK)
9874 #define S32_SCB_CCR_BFHFNMIGN_MASK 0x100u
9875 #define S32_SCB_CCR_BFHFNMIGN_SHIFT 8u
9876 #define S32_SCB_CCR_BFHFNMIGN_WIDTH 1u
9877 #define S32_SCB_CCR_BFHFNMIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_BFHFNMIGN_SHIFT))&S32_SCB_CCR_BFHFNMIGN_MASK)
9878 #define S32_SCB_CCR_STKALIGN_MASK 0x200u
9879 #define S32_SCB_CCR_STKALIGN_SHIFT 9u
9880 #define S32_SCB_CCR_STKALIGN_WIDTH 1u
9881 #define S32_SCB_CCR_STKALIGN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK)
9882 /* SHPR1 Bit Fields */
9883 #define S32_SCB_SHPR1_PRI_4_MASK 0xFFu
9884 #define S32_SCB_SHPR1_PRI_4_SHIFT 0u
9885 #define S32_SCB_SHPR1_PRI_4_WIDTH 8u
9886 #define S32_SCB_SHPR1_PRI_4(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_4_SHIFT))&S32_SCB_SHPR1_PRI_4_MASK)
9887 #define S32_SCB_SHPR1_PRI_5_MASK 0xFF00u
9888 #define S32_SCB_SHPR1_PRI_5_SHIFT 8u
9889 #define S32_SCB_SHPR1_PRI_5_WIDTH 8u
9890 #define S32_SCB_SHPR1_PRI_5(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_5_SHIFT))&S32_SCB_SHPR1_PRI_5_MASK)
9891 #define S32_SCB_SHPR1_PRI_6_MASK 0xFF0000u
9892 #define S32_SCB_SHPR1_PRI_6_SHIFT 16u
9893 #define S32_SCB_SHPR1_PRI_6_WIDTH 8u
9894 #define S32_SCB_SHPR1_PRI_6(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_6_SHIFT))&S32_SCB_SHPR1_PRI_6_MASK)
9895 /* SHPR2 Bit Fields */
9896 #define S32_SCB_SHPR2_PRI_11_MASK 0xFF000000u
9897 #define S32_SCB_SHPR2_PRI_11_SHIFT 24u
9898 #define S32_SCB_SHPR2_PRI_11_WIDTH 8u
9899 #define S32_SCB_SHPR2_PRI_11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK)
9900 /* SHPR3 Bit Fields */
9901 #define S32_SCB_SHPR3_PRI_12_MASK 0xFFu
9902 #define S32_SCB_SHPR3_PRI_12_SHIFT 0u
9903 #define S32_SCB_SHPR3_PRI_12_WIDTH 8u
9904 #define S32_SCB_SHPR3_PRI_12(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_12_SHIFT))&S32_SCB_SHPR3_PRI_12_MASK)
9905 #define S32_SCB_SHPR3_PRI_14_MASK 0xFF0000u
9906 #define S32_SCB_SHPR3_PRI_14_SHIFT 16u
9907 #define S32_SCB_SHPR3_PRI_14_WIDTH 8u
9908 #define S32_SCB_SHPR3_PRI_14(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK)
9909 #define S32_SCB_SHPR3_PRI_15_MASK 0xFF000000u
9910 #define S32_SCB_SHPR3_PRI_15_SHIFT 24u
9911 #define S32_SCB_SHPR3_PRI_15_WIDTH 8u
9912 #define S32_SCB_SHPR3_PRI_15(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK)
9913 /* SHCSR Bit Fields */
9914 #define S32_SCB_SHCSR_MEMFAULTACT_MASK 0x1u
9915 #define S32_SCB_SHCSR_MEMFAULTACT_SHIFT 0u
9916 #define S32_SCB_SHCSR_MEMFAULTACT_WIDTH 1u
9917 #define S32_SCB_SHCSR_MEMFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTACT_SHIFT))&S32_SCB_SHCSR_MEMFAULTACT_MASK)
9918 #define S32_SCB_SHCSR_BUSFAULTACT_MASK 0x2u
9919 #define S32_SCB_SHCSR_BUSFAULTACT_SHIFT 1u
9920 #define S32_SCB_SHCSR_BUSFAULTACT_WIDTH 1u
9921 #define S32_SCB_SHCSR_BUSFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTACT_SHIFT))&S32_SCB_SHCSR_BUSFAULTACT_MASK)
9922 #define S32_SCB_SHCSR_USGFAULTACT_MASK 0x8u
9923 #define S32_SCB_SHCSR_USGFAULTACT_SHIFT 3u
9924 #define S32_SCB_SHCSR_USGFAULTACT_WIDTH 1u
9925 #define S32_SCB_SHCSR_USGFAULTACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTACT_SHIFT))&S32_SCB_SHCSR_USGFAULTACT_MASK)
9926 #define S32_SCB_SHCSR_SVCALLACT_MASK 0x80u
9927 #define S32_SCB_SHCSR_SVCALLACT_SHIFT 7u
9928 #define S32_SCB_SHCSR_SVCALLACT_WIDTH 1u
9929 #define S32_SCB_SHCSR_SVCALLACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLACT_SHIFT))&S32_SCB_SHCSR_SVCALLACT_MASK)
9930 #define S32_SCB_SHCSR_MONITORACT_MASK 0x100u
9931 #define S32_SCB_SHCSR_MONITORACT_SHIFT 8u
9932 #define S32_SCB_SHCSR_MONITORACT_WIDTH 1u
9933 #define S32_SCB_SHCSR_MONITORACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MONITORACT_SHIFT))&S32_SCB_SHCSR_MONITORACT_MASK)
9934 #define S32_SCB_SHCSR_PENDSVACT_MASK 0x400u
9935 #define S32_SCB_SHCSR_PENDSVACT_SHIFT 10u
9936 #define S32_SCB_SHCSR_PENDSVACT_WIDTH 1u
9937 #define S32_SCB_SHCSR_PENDSVACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_PENDSVACT_SHIFT))&S32_SCB_SHCSR_PENDSVACT_MASK)
9938 #define S32_SCB_SHCSR_SYSTICKACT_MASK 0x800u
9939 #define S32_SCB_SHCSR_SYSTICKACT_SHIFT 11u
9940 #define S32_SCB_SHCSR_SYSTICKACT_WIDTH 1u
9941 #define S32_SCB_SHCSR_SYSTICKACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SYSTICKACT_SHIFT))&S32_SCB_SHCSR_SYSTICKACT_MASK)
9942 #define S32_SCB_SHCSR_USGFAULTPENDED_MASK 0x1000u
9943 #define S32_SCB_SHCSR_USGFAULTPENDED_SHIFT 12u
9944 #define S32_SCB_SHCSR_USGFAULTPENDED_WIDTH 1u
9945 #define S32_SCB_SHCSR_USGFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTPENDED_SHIFT))&S32_SCB_SHCSR_USGFAULTPENDED_MASK)
9946 #define S32_SCB_SHCSR_MEMFAULTPENDED_MASK 0x2000u
9947 #define S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT 13u
9948 #define S32_SCB_SHCSR_MEMFAULTPENDED_WIDTH 1u
9949 #define S32_SCB_SHCSR_MEMFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT))&S32_SCB_SHCSR_MEMFAULTPENDED_MASK)
9950 #define S32_SCB_SHCSR_BUSFAULTPENDED_MASK 0x4000u
9951 #define S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT 14u
9952 #define S32_SCB_SHCSR_BUSFAULTPENDED_WIDTH 1u
9953 #define S32_SCB_SHCSR_BUSFAULTPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT))&S32_SCB_SHCSR_BUSFAULTPENDED_MASK)
9954 #define S32_SCB_SHCSR_SVCALLPENDED_MASK 0x8000u
9955 #define S32_SCB_SHCSR_SVCALLPENDED_SHIFT 15u
9956 #define S32_SCB_SHCSR_SVCALLPENDED_WIDTH 1u
9957 #define S32_SCB_SHCSR_SVCALLPENDED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK)
9958 #define S32_SCB_SHCSR_MEMFAULTENA_MASK 0x10000u
9959 #define S32_SCB_SHCSR_MEMFAULTENA_SHIFT 16u
9960 #define S32_SCB_SHCSR_MEMFAULTENA_WIDTH 1u
9961 #define S32_SCB_SHCSR_MEMFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTENA_SHIFT))&S32_SCB_SHCSR_MEMFAULTENA_MASK)
9962 #define S32_SCB_SHCSR_BUSFAULTENA_MASK 0x20000u
9963 #define S32_SCB_SHCSR_BUSFAULTENA_SHIFT 17u
9964 #define S32_SCB_SHCSR_BUSFAULTENA_WIDTH 1u
9965 #define S32_SCB_SHCSR_BUSFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTENA_SHIFT))&S32_SCB_SHCSR_BUSFAULTENA_MASK)
9966 #define S32_SCB_SHCSR_USGFAULTENA_MASK 0x40000u
9967 #define S32_SCB_SHCSR_USGFAULTENA_SHIFT 18u
9968 #define S32_SCB_SHCSR_USGFAULTENA_WIDTH 1u
9969 #define S32_SCB_SHCSR_USGFAULTENA(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTENA_SHIFT))&S32_SCB_SHCSR_USGFAULTENA_MASK)
9970 /* CFSR Bit Fields */
9971 #define S32_SCB_CFSR_IACCVIOL_MASK 0x1u
9972 #define S32_SCB_CFSR_IACCVIOL_SHIFT 0u
9973 #define S32_SCB_CFSR_IACCVIOL_WIDTH 1u
9974 #define S32_SCB_CFSR_IACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IACCVIOL_SHIFT))&S32_SCB_CFSR_IACCVIOL_MASK)
9975 #define S32_SCB_CFSR_DACCVIOL_MASK 0x2u
9976 #define S32_SCB_CFSR_DACCVIOL_SHIFT 1u
9977 #define S32_SCB_CFSR_DACCVIOL_WIDTH 1u
9978 #define S32_SCB_CFSR_DACCVIOL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DACCVIOL_SHIFT))&S32_SCB_CFSR_DACCVIOL_MASK)
9979 #define S32_SCB_CFSR_MUNSTKERR_MASK 0x8u
9980 #define S32_SCB_CFSR_MUNSTKERR_SHIFT 3u
9981 #define S32_SCB_CFSR_MUNSTKERR_WIDTH 1u
9982 #define S32_SCB_CFSR_MUNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MUNSTKERR_SHIFT))&S32_SCB_CFSR_MUNSTKERR_MASK)
9983 #define S32_SCB_CFSR_MSTKERR_MASK 0x10u
9984 #define S32_SCB_CFSR_MSTKERR_SHIFT 4u
9985 #define S32_SCB_CFSR_MSTKERR_WIDTH 1u
9986 #define S32_SCB_CFSR_MSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MSTKERR_SHIFT))&S32_SCB_CFSR_MSTKERR_MASK)
9987 #define S32_SCB_CFSR_MLSPERR_MASK 0x20u
9988 #define S32_SCB_CFSR_MLSPERR_SHIFT 5u
9989 #define S32_SCB_CFSR_MLSPERR_WIDTH 1u
9990 #define S32_SCB_CFSR_MLSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MLSPERR_SHIFT))&S32_SCB_CFSR_MLSPERR_MASK)
9991 #define S32_SCB_CFSR_MMARVALID_MASK 0x80u
9992 #define S32_SCB_CFSR_MMARVALID_SHIFT 7u
9993 #define S32_SCB_CFSR_MMARVALID_WIDTH 1u
9994 #define S32_SCB_CFSR_MMARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMARVALID_SHIFT))&S32_SCB_CFSR_MMARVALID_MASK)
9995 #define S32_SCB_CFSR_IBUSERR_MASK 0x100u
9996 #define S32_SCB_CFSR_IBUSERR_SHIFT 8u
9997 #define S32_SCB_CFSR_IBUSERR_WIDTH 1u
9998 #define S32_SCB_CFSR_IBUSERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IBUSERR_SHIFT))&S32_SCB_CFSR_IBUSERR_MASK)
9999 #define S32_SCB_CFSR_PRECISERR_MASK 0x200u
10000 #define S32_SCB_CFSR_PRECISERR_SHIFT 9u
10001 #define S32_SCB_CFSR_PRECISERR_WIDTH 1u
10002 #define S32_SCB_CFSR_PRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_PRECISERR_SHIFT))&S32_SCB_CFSR_PRECISERR_MASK)
10003 #define S32_SCB_CFSR_IMPRECISERR_MASK 0x400u
10004 #define S32_SCB_CFSR_IMPRECISERR_SHIFT 10u
10005 #define S32_SCB_CFSR_IMPRECISERR_WIDTH 1u
10006 #define S32_SCB_CFSR_IMPRECISERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IMPRECISERR_SHIFT))&S32_SCB_CFSR_IMPRECISERR_MASK)
10007 #define S32_SCB_CFSR_UNSTKERR_MASK 0x800u
10008 #define S32_SCB_CFSR_UNSTKERR_SHIFT 11u
10009 #define S32_SCB_CFSR_UNSTKERR_WIDTH 1u
10010 #define S32_SCB_CFSR_UNSTKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNSTKERR_SHIFT))&S32_SCB_CFSR_UNSTKERR_MASK)
10011 #define S32_SCB_CFSR_STKERR_MASK 0x1000u
10012 #define S32_SCB_CFSR_STKERR_SHIFT 12u
10013 #define S32_SCB_CFSR_STKERR_WIDTH 1u
10014 #define S32_SCB_CFSR_STKERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_STKERR_SHIFT))&S32_SCB_CFSR_STKERR_MASK)
10015 #define S32_SCB_CFSR_LSPERR_MASK 0x2000u
10016 #define S32_SCB_CFSR_LSPERR_SHIFT 13u
10017 #define S32_SCB_CFSR_LSPERR_WIDTH 1u
10018 #define S32_SCB_CFSR_LSPERR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_LSPERR_SHIFT))&S32_SCB_CFSR_LSPERR_MASK)
10019 #define S32_SCB_CFSR_BFARVALID_MASK 0x8000u
10020 #define S32_SCB_CFSR_BFARVALID_SHIFT 15u
10021 #define S32_SCB_CFSR_BFARVALID_WIDTH 1u
10022 #define S32_SCB_CFSR_BFARVALID(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFARVALID_SHIFT))&S32_SCB_CFSR_BFARVALID_MASK)
10023 #define S32_SCB_CFSR_UNDEFINSTR_MASK 0x10000u
10024 #define S32_SCB_CFSR_UNDEFINSTR_SHIFT 16u
10025 #define S32_SCB_CFSR_UNDEFINSTR_WIDTH 1u
10026 #define S32_SCB_CFSR_UNDEFINSTR(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNDEFINSTR_SHIFT))&S32_SCB_CFSR_UNDEFINSTR_MASK)
10027 #define S32_SCB_CFSR_INVSTATE_MASK 0x20000u
10028 #define S32_SCB_CFSR_INVSTATE_SHIFT 17u
10029 #define S32_SCB_CFSR_INVSTATE_WIDTH 1u
10030 #define S32_SCB_CFSR_INVSTATE(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVSTATE_SHIFT))&S32_SCB_CFSR_INVSTATE_MASK)
10031 #define S32_SCB_CFSR_INVPC_MASK 0x40000u
10032 #define S32_SCB_CFSR_INVPC_SHIFT 18u
10033 #define S32_SCB_CFSR_INVPC_WIDTH 1u
10034 #define S32_SCB_CFSR_INVPC(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVPC_SHIFT))&S32_SCB_CFSR_INVPC_MASK)
10035 #define S32_SCB_CFSR_NOCP_MASK 0x80000u
10036 #define S32_SCB_CFSR_NOCP_SHIFT 19u
10037 #define S32_SCB_CFSR_NOCP_WIDTH 1u
10038 #define S32_SCB_CFSR_NOCP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_NOCP_SHIFT))&S32_SCB_CFSR_NOCP_MASK)
10039 #define S32_SCB_CFSR_UNALIGNED_MASK 0x1000000u
10040 #define S32_SCB_CFSR_UNALIGNED_SHIFT 24u
10041 #define S32_SCB_CFSR_UNALIGNED_WIDTH 1u
10042 #define S32_SCB_CFSR_UNALIGNED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNALIGNED_SHIFT))&S32_SCB_CFSR_UNALIGNED_MASK)
10043 #define S32_SCB_CFSR_DIVBYZERO_MASK 0x2000000u
10044 #define S32_SCB_CFSR_DIVBYZERO_SHIFT 25u
10045 #define S32_SCB_CFSR_DIVBYZERO_WIDTH 1u
10046 #define S32_SCB_CFSR_DIVBYZERO(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DIVBYZERO_SHIFT))&S32_SCB_CFSR_DIVBYZERO_MASK)
10047 /* HFSR Bit Fields */
10048 #define S32_SCB_HFSR_VECTTBL_MASK 0x2u
10049 #define S32_SCB_HFSR_VECTTBL_SHIFT 1u
10050 #define S32_SCB_HFSR_VECTTBL_WIDTH 1u
10051 #define S32_SCB_HFSR_VECTTBL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_VECTTBL_SHIFT))&S32_SCB_HFSR_VECTTBL_MASK)
10052 #define S32_SCB_HFSR_FORCED_MASK 0x40000000u
10053 #define S32_SCB_HFSR_FORCED_SHIFT 30u
10054 #define S32_SCB_HFSR_FORCED_WIDTH 1u
10055 #define S32_SCB_HFSR_FORCED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_FORCED_SHIFT))&S32_SCB_HFSR_FORCED_MASK)
10056 #define S32_SCB_HFSR_DEBUGEVT_MASK 0x80000000u
10057 #define S32_SCB_HFSR_DEBUGEVT_SHIFT 31u
10058 #define S32_SCB_HFSR_DEBUGEVT_WIDTH 1u
10059 #define S32_SCB_HFSR_DEBUGEVT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_DEBUGEVT_SHIFT))&S32_SCB_HFSR_DEBUGEVT_MASK)
10060 /* DFSR Bit Fields */
10061 #define S32_SCB_DFSR_HALTED_MASK 0x1u
10062 #define S32_SCB_DFSR_HALTED_SHIFT 0u
10063 #define S32_SCB_DFSR_HALTED_WIDTH 1u
10064 #define S32_SCB_DFSR_HALTED(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK)
10065 #define S32_SCB_DFSR_BKPT_MASK 0x2u
10066 #define S32_SCB_DFSR_BKPT_SHIFT 1u
10067 #define S32_SCB_DFSR_BKPT_WIDTH 1u
10068 #define S32_SCB_DFSR_BKPT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK)
10069 #define S32_SCB_DFSR_DWTTRAP_MASK 0x4u
10070 #define S32_SCB_DFSR_DWTTRAP_SHIFT 2u
10071 #define S32_SCB_DFSR_DWTTRAP_WIDTH 1u
10072 #define S32_SCB_DFSR_DWTTRAP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK)
10073 #define S32_SCB_DFSR_VCATCH_MASK 0x8u
10074 #define S32_SCB_DFSR_VCATCH_SHIFT 3u
10075 #define S32_SCB_DFSR_VCATCH_WIDTH 1u
10076 #define S32_SCB_DFSR_VCATCH(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK)
10077 #define S32_SCB_DFSR_EXTERNAL_MASK 0x10u
10078 #define S32_SCB_DFSR_EXTERNAL_SHIFT 4u
10079 #define S32_SCB_DFSR_EXTERNAL_WIDTH 1u
10080 #define S32_SCB_DFSR_EXTERNAL(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK)
10081 /* MMFAR Bit Fields */
10082 #define S32_SCB_MMFAR_ADDRESS_MASK 0xFFFFFFFFu
10083 #define S32_SCB_MMFAR_ADDRESS_SHIFT 0u
10084 #define S32_SCB_MMFAR_ADDRESS_WIDTH 32u
10085 #define S32_SCB_MMFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_MMFAR_ADDRESS_SHIFT))&S32_SCB_MMFAR_ADDRESS_MASK)
10086 /* BFAR Bit Fields */
10087 #define S32_SCB_BFAR_ADDRESS_MASK 0xFFFFFFFFu
10088 #define S32_SCB_BFAR_ADDRESS_SHIFT 0u
10089 #define S32_SCB_BFAR_ADDRESS_WIDTH 32u
10090 #define S32_SCB_BFAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_BFAR_ADDRESS_SHIFT))&S32_SCB_BFAR_ADDRESS_MASK)
10091 /* AFSR Bit Fields */
10092 #define S32_SCB_AFSR_AUXFAULT_MASK 0xFFFFFFFFu
10093 #define S32_SCB_AFSR_AUXFAULT_SHIFT 0u
10094 #define S32_SCB_AFSR_AUXFAULT_WIDTH 32u
10095 #define S32_SCB_AFSR_AUXFAULT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_AFSR_AUXFAULT_SHIFT))&S32_SCB_AFSR_AUXFAULT_MASK)
10096 /* CPACR Bit Fields */
10097 #define S32_SCB_CPACR_CP10_MASK 0x300000u
10098 #define S32_SCB_CPACR_CP10_SHIFT 20u
10099 #define S32_SCB_CPACR_CP10_WIDTH 2u
10100 #define S32_SCB_CPACR_CP10(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP10_SHIFT))&S32_SCB_CPACR_CP10_MASK)
10101 #define S32_SCB_CPACR_CP11_MASK 0xC00000u
10102 #define S32_SCB_CPACR_CP11_SHIFT 22u
10103 #define S32_SCB_CPACR_CP11_WIDTH 2u
10104 #define S32_SCB_CPACR_CP11(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP11_SHIFT))&S32_SCB_CPACR_CP11_MASK)
10105 /* FPCCR Bit Fields */
10106 #define S32_SCB_FPCCR_LSPACT_MASK 0x1u
10107 #define S32_SCB_FPCCR_LSPACT_SHIFT 0u
10108 #define S32_SCB_FPCCR_LSPACT_WIDTH 1u
10109 #define S32_SCB_FPCCR_LSPACT(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPACT_SHIFT))&S32_SCB_FPCCR_LSPACT_MASK)
10110 #define S32_SCB_FPCCR_USER_MASK 0x2u
10111 #define S32_SCB_FPCCR_USER_SHIFT 1u
10112 #define S32_SCB_FPCCR_USER_WIDTH 1u
10113 #define S32_SCB_FPCCR_USER(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_USER_SHIFT))&S32_SCB_FPCCR_USER_MASK)
10114 #define S32_SCB_FPCCR_THREAD_MASK 0x8u
10115 #define S32_SCB_FPCCR_THREAD_SHIFT 3u
10116 #define S32_SCB_FPCCR_THREAD_WIDTH 1u
10117 #define S32_SCB_FPCCR_THREAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_THREAD_SHIFT))&S32_SCB_FPCCR_THREAD_MASK)
10118 #define S32_SCB_FPCCR_HFRDY_MASK 0x10u
10119 #define S32_SCB_FPCCR_HFRDY_SHIFT 4u
10120 #define S32_SCB_FPCCR_HFRDY_WIDTH 1u
10121 #define S32_SCB_FPCCR_HFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_HFRDY_SHIFT))&S32_SCB_FPCCR_HFRDY_MASK)
10122 #define S32_SCB_FPCCR_MMRDY_MASK 0x20u
10123 #define S32_SCB_FPCCR_MMRDY_SHIFT 5u
10124 #define S32_SCB_FPCCR_MMRDY_WIDTH 1u
10125 #define S32_SCB_FPCCR_MMRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MMRDY_SHIFT))&S32_SCB_FPCCR_MMRDY_MASK)
10126 #define S32_SCB_FPCCR_BFRDY_MASK 0x40u
10127 #define S32_SCB_FPCCR_BFRDY_SHIFT 6u
10128 #define S32_SCB_FPCCR_BFRDY_WIDTH 1u
10129 #define S32_SCB_FPCCR_BFRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_BFRDY_SHIFT))&S32_SCB_FPCCR_BFRDY_MASK)
10130 #define S32_SCB_FPCCR_MONRDY_MASK 0x100u
10131 #define S32_SCB_FPCCR_MONRDY_SHIFT 8u
10132 #define S32_SCB_FPCCR_MONRDY_WIDTH 1u
10133 #define S32_SCB_FPCCR_MONRDY(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MONRDY_SHIFT))&S32_SCB_FPCCR_MONRDY_MASK)
10134 #define S32_SCB_FPCCR_LSPEN_MASK 0x40000000u
10135 #define S32_SCB_FPCCR_LSPEN_SHIFT 30u
10136 #define S32_SCB_FPCCR_LSPEN_WIDTH 1u
10137 #define S32_SCB_FPCCR_LSPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPEN_SHIFT))&S32_SCB_FPCCR_LSPEN_MASK)
10138 #define S32_SCB_FPCCR_ASPEN_MASK 0x80000000u
10139 #define S32_SCB_FPCCR_ASPEN_SHIFT 31u
10140 #define S32_SCB_FPCCR_ASPEN_WIDTH 1u
10141 #define S32_SCB_FPCCR_ASPEN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_ASPEN_SHIFT))&S32_SCB_FPCCR_ASPEN_MASK)
10142 /* FPCAR Bit Fields */
10143 #define S32_SCB_FPCAR_ADDRESS_MASK 0xFFFFFFF8u
10144 #define S32_SCB_FPCAR_ADDRESS_SHIFT 3u
10145 #define S32_SCB_FPCAR_ADDRESS_WIDTH 29u
10146 #define S32_SCB_FPCAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCAR_ADDRESS_SHIFT))&S32_SCB_FPCAR_ADDRESS_MASK)
10147 /* FPDSCR Bit Fields */
10148 #define S32_SCB_FPDSCR_RMode_MASK 0xC00000u
10149 #define S32_SCB_FPDSCR_RMode_SHIFT 22u
10150 #define S32_SCB_FPDSCR_RMode_WIDTH 2u
10151 #define S32_SCB_FPDSCR_RMode(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_RMode_SHIFT))&S32_SCB_FPDSCR_RMode_MASK)
10152 #define S32_SCB_FPDSCR_FZ_MASK 0x1000000u
10153 #define S32_SCB_FPDSCR_FZ_SHIFT 24u
10154 #define S32_SCB_FPDSCR_FZ_WIDTH 1u
10155 #define S32_SCB_FPDSCR_FZ(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_FZ_SHIFT))&S32_SCB_FPDSCR_FZ_MASK)
10156 #define S32_SCB_FPDSCR_DN_MASK 0x2000000u
10157 #define S32_SCB_FPDSCR_DN_SHIFT 25u
10158 #define S32_SCB_FPDSCR_DN_WIDTH 1u
10159 #define S32_SCB_FPDSCR_DN(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_DN_SHIFT))&S32_SCB_FPDSCR_DN_MASK)
10160 #define S32_SCB_FPDSCR_AHP_MASK 0x4000000u
10161 #define S32_SCB_FPDSCR_AHP_SHIFT 26u
10162 #define S32_SCB_FPDSCR_AHP_WIDTH 1u
10163 #define S32_SCB_FPDSCR_AHP(x) (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_AHP_SHIFT))&S32_SCB_FPDSCR_AHP_MASK)
10164  /* end of group S32_SCB_Register_Masks */
10168 
10169  /* end of group S32_SCB_Peripheral_Access_Layer */
10173 
10174 
10175 /* ----------------------------------------------------------------------------
10176  -- S32_SysTick Peripheral Access Layer
10177  ---------------------------------------------------------------------------- */
10178 
10188 typedef struct {
10189  __IO uint32_t CSR;
10190  __IO uint32_t RVR;
10191  __IO uint32_t CVR;
10192  __I uint32_t CALIB;
10194 
10196 #define S32_SysTick_INSTANCE_COUNT (1u)
10197 
10198 
10199 /* S32_SysTick - Peripheral instance base addresses */
10201 #define S32_SysTick_BASE (0xE000E010u)
10202 
10203 #define S32_SysTick ((S32_SysTick_Type *)S32_SysTick_BASE)
10204 
10205 #define S32_SysTick_BASE_ADDRS { S32_SysTick_BASE }
10206 
10207 #define S32_SysTick_BASE_PTRS { S32_SysTick }
10208 
10209 #define S32_SysTick_IRQS_ARR_COUNT (1u)
10210 
10211 #define S32_SysTick_IRQS_CH_COUNT (1u)
10212 
10213 #define S32_SysTick_IRQS { SysTick_IRQn }
10214 
10215 /* ----------------------------------------------------------------------------
10216  -- S32_SysTick Register Masks
10217  ---------------------------------------------------------------------------- */
10218 
10224 /* CSR Bit Fields */
10225 #define S32_SysTick_CSR_ENABLE_MASK 0x1u
10226 #define S32_SysTick_CSR_ENABLE_SHIFT 0u
10227 #define S32_SysTick_CSR_ENABLE_WIDTH 1u
10228 #define S32_SysTick_CSR_ENABLE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_ENABLE_SHIFT))&S32_SysTick_CSR_ENABLE_MASK)
10229 #define S32_SysTick_CSR_TICKINT_MASK 0x2u
10230 #define S32_SysTick_CSR_TICKINT_SHIFT 1u
10231 #define S32_SysTick_CSR_TICKINT_WIDTH 1u
10232 #define S32_SysTick_CSR_TICKINT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_TICKINT_SHIFT))&S32_SysTick_CSR_TICKINT_MASK)
10233 #define S32_SysTick_CSR_CLKSOURCE_MASK 0x4u
10234 #define S32_SysTick_CSR_CLKSOURCE_SHIFT 2u
10235 #define S32_SysTick_CSR_CLKSOURCE_WIDTH 1u
10236 #define S32_SysTick_CSR_CLKSOURCE(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_CLKSOURCE_SHIFT))&S32_SysTick_CSR_CLKSOURCE_MASK)
10237 #define S32_SysTick_CSR_COUNTFLAG_MASK 0x10000u
10238 #define S32_SysTick_CSR_COUNTFLAG_SHIFT 16u
10239 #define S32_SysTick_CSR_COUNTFLAG_WIDTH 1u
10240 #define S32_SysTick_CSR_COUNTFLAG(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CSR_COUNTFLAG_SHIFT))&S32_SysTick_CSR_COUNTFLAG_MASK)
10241 /* RVR Bit Fields */
10242 #define S32_SysTick_RVR_RELOAD_MASK 0xFFFFFFu
10243 #define S32_SysTick_RVR_RELOAD_SHIFT 0u
10244 #define S32_SysTick_RVR_RELOAD_WIDTH 24u
10245 #define S32_SysTick_RVR_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_RVR_RELOAD_SHIFT))&S32_SysTick_RVR_RELOAD_MASK)
10246 /* CVR Bit Fields */
10247 #define S32_SysTick_CVR_CURRENT_MASK 0xFFFFFFu
10248 #define S32_SysTick_CVR_CURRENT_SHIFT 0u
10249 #define S32_SysTick_CVR_CURRENT_WIDTH 24u
10250 #define S32_SysTick_CVR_CURRENT(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CVR_CURRENT_SHIFT))&S32_SysTick_CVR_CURRENT_MASK)
10251 /* CALIB Bit Fields */
10252 #define S32_SysTick_CALIB_TENMS_MASK 0xFFFFFFu
10253 #define S32_SysTick_CALIB_TENMS_SHIFT 0u
10254 #define S32_SysTick_CALIB_TENMS_WIDTH 24u
10255 #define S32_SysTick_CALIB_TENMS(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_TENMS_SHIFT))&S32_SysTick_CALIB_TENMS_MASK)
10256 #define S32_SysTick_CALIB_SKEW_MASK 0x40000000u
10257 #define S32_SysTick_CALIB_SKEW_SHIFT 30u
10258 #define S32_SysTick_CALIB_SKEW_WIDTH 1u
10259 #define S32_SysTick_CALIB_SKEW(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_SKEW_SHIFT))&S32_SysTick_CALIB_SKEW_MASK)
10260 #define S32_SysTick_CALIB_NOREF_MASK 0x80000000u
10261 #define S32_SysTick_CALIB_NOREF_SHIFT 31u
10262 #define S32_SysTick_CALIB_NOREF_WIDTH 1u
10263 #define S32_SysTick_CALIB_NOREF(x) (((uint32_t)(((uint32_t)(x))<<S32_SysTick_CALIB_NOREF_SHIFT))&S32_SysTick_CALIB_NOREF_MASK)
10264  /* end of group S32_SysTick_Register_Masks */
10268 
10269  /* end of group S32_SysTick_Peripheral_Access_Layer */
10273 
10274 
10275 /* ----------------------------------------------------------------------------
10276  -- SCG Peripheral Access Layer
10277  ---------------------------------------------------------------------------- */
10278 
10288 typedef struct {
10289  __I uint32_t VERID;
10290  __I uint32_t PARAM;
10291  uint8_t RESERVED_0[8];
10292  __I uint32_t CSR;
10293  __IO uint32_t RCCR;
10294  __IO uint32_t VCCR;
10295  __IO uint32_t HCCR;
10296  __IO uint32_t CLKOUTCNFG;
10297  uint8_t RESERVED_1[220];
10298  __IO uint32_t SOSCCSR;
10299  __IO uint32_t SOSCDIV;
10300  __IO uint32_t SOSCCFG;
10301  uint8_t RESERVED_2[244];
10302  __IO uint32_t SIRCCSR;
10303  __IO uint32_t SIRCDIV;
10304  __IO uint32_t SIRCCFG;
10305  uint8_t RESERVED_3[244];
10306  __IO uint32_t FIRCCSR;
10307  __IO uint32_t FIRCDIV;
10308  __IO uint32_t FIRCCFG;
10309  uint8_t RESERVED_4[756];
10310  __IO uint32_t SPLLCSR;
10311  __IO uint32_t SPLLDIV;
10312  __IO uint32_t SPLLCFG;
10314 
10316 #define SCG_INSTANCE_COUNT (1u)
10317 
10318 
10319 /* SCG - Peripheral instance base addresses */
10321 #define SCG_BASE (0x40064000u)
10322 
10323 #define SCG ((SCG_Type *)SCG_BASE)
10324 
10325 #define SCG_BASE_ADDRS { SCG_BASE }
10326 
10327 #define SCG_BASE_PTRS { SCG }
10328 
10329 #define SCG_IRQS_ARR_COUNT (1u)
10330 
10331 #define SCG_IRQS_CH_COUNT (1u)
10332 
10333 #define SCG_IRQS { SCG_IRQn }
10334 
10335 /* ----------------------------------------------------------------------------
10336  -- SCG Register Masks
10337  ---------------------------------------------------------------------------- */
10338 
10344 /* VERID Bit Fields */
10345 #define SCG_VERID_VERSION_MASK 0xFFFFFFFFu
10346 #define SCG_VERID_VERSION_SHIFT 0u
10347 #define SCG_VERID_VERSION_WIDTH 32u
10348 #define SCG_VERID_VERSION(x) (((uint32_t)(((uint32_t)(x))<<SCG_VERID_VERSION_SHIFT))&SCG_VERID_VERSION_MASK)
10349 /* PARAM Bit Fields */
10350 #define SCG_PARAM_CLKPRES_MASK 0xFFu
10351 #define SCG_PARAM_CLKPRES_SHIFT 0u
10352 #define SCG_PARAM_CLKPRES_WIDTH 8u
10353 #define SCG_PARAM_CLKPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_CLKPRES_SHIFT))&SCG_PARAM_CLKPRES_MASK)
10354 #define SCG_PARAM_DIVPRES_MASK 0xF8000000u
10355 #define SCG_PARAM_DIVPRES_SHIFT 27u
10356 #define SCG_PARAM_DIVPRES_WIDTH 5u
10357 #define SCG_PARAM_DIVPRES(x) (((uint32_t)(((uint32_t)(x))<<SCG_PARAM_DIVPRES_SHIFT))&SCG_PARAM_DIVPRES_MASK)
10358 /* CSR Bit Fields */
10359 #define SCG_CSR_DIVSLOW_MASK 0xFu
10360 #define SCG_CSR_DIVSLOW_SHIFT 0u
10361 #define SCG_CSR_DIVSLOW_WIDTH 4u
10362 #define SCG_CSR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVSLOW_SHIFT))&SCG_CSR_DIVSLOW_MASK)
10363 #define SCG_CSR_DIVBUS_MASK 0xF0u
10364 #define SCG_CSR_DIVBUS_SHIFT 4u
10365 #define SCG_CSR_DIVBUS_WIDTH 4u
10366 #define SCG_CSR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVBUS_SHIFT))&SCG_CSR_DIVBUS_MASK)
10367 #define SCG_CSR_DIVCORE_MASK 0xF0000u
10368 #define SCG_CSR_DIVCORE_SHIFT 16u
10369 #define SCG_CSR_DIVCORE_WIDTH 4u
10370 #define SCG_CSR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_DIVCORE_SHIFT))&SCG_CSR_DIVCORE_MASK)
10371 #define SCG_CSR_SCS_MASK 0xF000000u
10372 #define SCG_CSR_SCS_SHIFT 24u
10373 #define SCG_CSR_SCS_WIDTH 4u
10374 #define SCG_CSR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_CSR_SCS_SHIFT))&SCG_CSR_SCS_MASK)
10375 /* RCCR Bit Fields */
10376 #define SCG_RCCR_DIVSLOW_MASK 0xFu
10377 #define SCG_RCCR_DIVSLOW_SHIFT 0u
10378 #define SCG_RCCR_DIVSLOW_WIDTH 4u
10379 #define SCG_RCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVSLOW_SHIFT))&SCG_RCCR_DIVSLOW_MASK)
10380 #define SCG_RCCR_DIVBUS_MASK 0xF0u
10381 #define SCG_RCCR_DIVBUS_SHIFT 4u
10382 #define SCG_RCCR_DIVBUS_WIDTH 4u
10383 #define SCG_RCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVBUS_SHIFT))&SCG_RCCR_DIVBUS_MASK)
10384 #define SCG_RCCR_DIVCORE_MASK 0xF0000u
10385 #define SCG_RCCR_DIVCORE_SHIFT 16u
10386 #define SCG_RCCR_DIVCORE_WIDTH 4u
10387 #define SCG_RCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_DIVCORE_SHIFT))&SCG_RCCR_DIVCORE_MASK)
10388 #define SCG_RCCR_SCS_MASK 0xF000000u
10389 #define SCG_RCCR_SCS_SHIFT 24u
10390 #define SCG_RCCR_SCS_WIDTH 4u
10391 #define SCG_RCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_RCCR_SCS_SHIFT))&SCG_RCCR_SCS_MASK)
10392 /* VCCR Bit Fields */
10393 #define SCG_VCCR_DIVSLOW_MASK 0xFu
10394 #define SCG_VCCR_DIVSLOW_SHIFT 0u
10395 #define SCG_VCCR_DIVSLOW_WIDTH 4u
10396 #define SCG_VCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVSLOW_SHIFT))&SCG_VCCR_DIVSLOW_MASK)
10397 #define SCG_VCCR_DIVBUS_MASK 0xF0u
10398 #define SCG_VCCR_DIVBUS_SHIFT 4u
10399 #define SCG_VCCR_DIVBUS_WIDTH 4u
10400 #define SCG_VCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVBUS_SHIFT))&SCG_VCCR_DIVBUS_MASK)
10401 #define SCG_VCCR_DIVCORE_MASK 0xF0000u
10402 #define SCG_VCCR_DIVCORE_SHIFT 16u
10403 #define SCG_VCCR_DIVCORE_WIDTH 4u
10404 #define SCG_VCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_DIVCORE_SHIFT))&SCG_VCCR_DIVCORE_MASK)
10405 #define SCG_VCCR_SCS_MASK 0xF000000u
10406 #define SCG_VCCR_SCS_SHIFT 24u
10407 #define SCG_VCCR_SCS_WIDTH 4u
10408 #define SCG_VCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_VCCR_SCS_SHIFT))&SCG_VCCR_SCS_MASK)
10409 /* HCCR Bit Fields */
10410 #define SCG_HCCR_DIVSLOW_MASK 0xFu
10411 #define SCG_HCCR_DIVSLOW_SHIFT 0u
10412 #define SCG_HCCR_DIVSLOW_WIDTH 4u
10413 #define SCG_HCCR_DIVSLOW(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVSLOW_SHIFT))&SCG_HCCR_DIVSLOW_MASK)
10414 #define SCG_HCCR_DIVBUS_MASK 0xF0u
10415 #define SCG_HCCR_DIVBUS_SHIFT 4u
10416 #define SCG_HCCR_DIVBUS_WIDTH 4u
10417 #define SCG_HCCR_DIVBUS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVBUS_SHIFT))&SCG_HCCR_DIVBUS_MASK)
10418 #define SCG_HCCR_DIVCORE_MASK 0xF0000u
10419 #define SCG_HCCR_DIVCORE_SHIFT 16u
10420 #define SCG_HCCR_DIVCORE_WIDTH 4u
10421 #define SCG_HCCR_DIVCORE(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_DIVCORE_SHIFT))&SCG_HCCR_DIVCORE_MASK)
10422 #define SCG_HCCR_SCS_MASK 0xF000000u
10423 #define SCG_HCCR_SCS_SHIFT 24u
10424 #define SCG_HCCR_SCS_WIDTH 4u
10425 #define SCG_HCCR_SCS(x) (((uint32_t)(((uint32_t)(x))<<SCG_HCCR_SCS_SHIFT))&SCG_HCCR_SCS_MASK)
10426 /* CLKOUTCNFG Bit Fields */
10427 #define SCG_CLKOUTCNFG_CLKOUTSEL_MASK 0xF000000u
10428 #define SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT 24u
10429 #define SCG_CLKOUTCNFG_CLKOUTSEL_WIDTH 4u
10430 #define SCG_CLKOUTCNFG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_CLKOUTCNFG_CLKOUTSEL_SHIFT))&SCG_CLKOUTCNFG_CLKOUTSEL_MASK)
10431 /* SOSCCSR Bit Fields */
10432 #define SCG_SOSCCSR_SOSCEN_MASK 0x1u
10433 #define SCG_SOSCCSR_SOSCEN_SHIFT 0u
10434 #define SCG_SOSCCSR_SOSCEN_WIDTH 1u
10435 #define SCG_SOSCCSR_SOSCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCEN_SHIFT))&SCG_SOSCCSR_SOSCEN_MASK)
10436 #define SCG_SOSCCSR_SOSCCM_MASK 0x10000u
10437 #define SCG_SOSCCSR_SOSCCM_SHIFT 16u
10438 #define SCG_SOSCCSR_SOSCCM_WIDTH 1u
10439 #define SCG_SOSCCSR_SOSCCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCM_SHIFT))&SCG_SOSCCSR_SOSCCM_MASK)
10440 #define SCG_SOSCCSR_SOSCCMRE_MASK 0x20000u
10441 #define SCG_SOSCCSR_SOSCCMRE_SHIFT 17u
10442 #define SCG_SOSCCSR_SOSCCMRE_WIDTH 1u
10443 #define SCG_SOSCCSR_SOSCCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCCMRE_SHIFT))&SCG_SOSCCSR_SOSCCMRE_MASK)
10444 #define SCG_SOSCCSR_LK_MASK 0x800000u
10445 #define SCG_SOSCCSR_LK_SHIFT 23u
10446 #define SCG_SOSCCSR_LK_WIDTH 1u
10447 #define SCG_SOSCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_LK_SHIFT))&SCG_SOSCCSR_LK_MASK)
10448 #define SCG_SOSCCSR_SOSCVLD_MASK 0x1000000u
10449 #define SCG_SOSCCSR_SOSCVLD_SHIFT 24u
10450 #define SCG_SOSCCSR_SOSCVLD_WIDTH 1u
10451 #define SCG_SOSCCSR_SOSCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCVLD_SHIFT))&SCG_SOSCCSR_SOSCVLD_MASK)
10452 #define SCG_SOSCCSR_SOSCSEL_MASK 0x2000000u
10453 #define SCG_SOSCCSR_SOSCSEL_SHIFT 25u
10454 #define SCG_SOSCCSR_SOSCSEL_WIDTH 1u
10455 #define SCG_SOSCCSR_SOSCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCSEL_SHIFT))&SCG_SOSCCSR_SOSCSEL_MASK)
10456 #define SCG_SOSCCSR_SOSCERR_MASK 0x4000000u
10457 #define SCG_SOSCCSR_SOSCERR_SHIFT 26u
10458 #define SCG_SOSCCSR_SOSCERR_WIDTH 1u
10459 #define SCG_SOSCCSR_SOSCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCSR_SOSCERR_SHIFT))&SCG_SOSCCSR_SOSCERR_MASK)
10460 /* SOSCDIV Bit Fields */
10461 #define SCG_SOSCDIV_SOSCDIV1_MASK 0x7u
10462 #define SCG_SOSCDIV_SOSCDIV1_SHIFT 0u
10463 #define SCG_SOSCDIV_SOSCDIV1_WIDTH 3u
10464 #define SCG_SOSCDIV_SOSCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV1_SHIFT))&SCG_SOSCDIV_SOSCDIV1_MASK)
10465 #define SCG_SOSCDIV_SOSCDIV2_MASK 0x700u
10466 #define SCG_SOSCDIV_SOSCDIV2_SHIFT 8u
10467 #define SCG_SOSCDIV_SOSCDIV2_WIDTH 3u
10468 #define SCG_SOSCDIV_SOSCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCDIV_SOSCDIV2_SHIFT))&SCG_SOSCDIV_SOSCDIV2_MASK)
10469 /* SOSCCFG Bit Fields */
10470 #define SCG_SOSCCFG_EREFS_MASK 0x4u
10471 #define SCG_SOSCCFG_EREFS_SHIFT 2u
10472 #define SCG_SOSCCFG_EREFS_WIDTH 1u
10473 #define SCG_SOSCCFG_EREFS(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_EREFS_SHIFT))&SCG_SOSCCFG_EREFS_MASK)
10474 #define SCG_SOSCCFG_HGO_MASK 0x8u
10475 #define SCG_SOSCCFG_HGO_SHIFT 3u
10476 #define SCG_SOSCCFG_HGO_WIDTH 1u
10477 #define SCG_SOSCCFG_HGO(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_HGO_SHIFT))&SCG_SOSCCFG_HGO_MASK)
10478 #define SCG_SOSCCFG_RANGE_MASK 0x30u
10479 #define SCG_SOSCCFG_RANGE_SHIFT 4u
10480 #define SCG_SOSCCFG_RANGE_WIDTH 2u
10481 #define SCG_SOSCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SOSCCFG_RANGE_SHIFT))&SCG_SOSCCFG_RANGE_MASK)
10482 /* SIRCCSR Bit Fields */
10483 #define SCG_SIRCCSR_SIRCEN_MASK 0x1u
10484 #define SCG_SIRCCSR_SIRCEN_SHIFT 0u
10485 #define SCG_SIRCCSR_SIRCEN_WIDTH 1u
10486 #define SCG_SIRCCSR_SIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCEN_SHIFT))&SCG_SIRCCSR_SIRCEN_MASK)
10487 #define SCG_SIRCCSR_SIRCSTEN_MASK 0x2u
10488 #define SCG_SIRCCSR_SIRCSTEN_SHIFT 1u
10489 #define SCG_SIRCCSR_SIRCSTEN_WIDTH 1u
10490 #define SCG_SIRCCSR_SIRCSTEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSTEN_SHIFT))&SCG_SIRCCSR_SIRCSTEN_MASK)
10491 #define SCG_SIRCCSR_SIRCLPEN_MASK 0x4u
10492 #define SCG_SIRCCSR_SIRCLPEN_SHIFT 2u
10493 #define SCG_SIRCCSR_SIRCLPEN_WIDTH 1u
10494 #define SCG_SIRCCSR_SIRCLPEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCLPEN_SHIFT))&SCG_SIRCCSR_SIRCLPEN_MASK)
10495 #define SCG_SIRCCSR_LK_MASK 0x800000u
10496 #define SCG_SIRCCSR_LK_SHIFT 23u
10497 #define SCG_SIRCCSR_LK_WIDTH 1u
10498 #define SCG_SIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_LK_SHIFT))&SCG_SIRCCSR_LK_MASK)
10499 #define SCG_SIRCCSR_SIRCVLD_MASK 0x1000000u
10500 #define SCG_SIRCCSR_SIRCVLD_SHIFT 24u
10501 #define SCG_SIRCCSR_SIRCVLD_WIDTH 1u
10502 #define SCG_SIRCCSR_SIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCVLD_SHIFT))&SCG_SIRCCSR_SIRCVLD_MASK)
10503 #define SCG_SIRCCSR_SIRCSEL_MASK 0x2000000u
10504 #define SCG_SIRCCSR_SIRCSEL_SHIFT 25u
10505 #define SCG_SIRCCSR_SIRCSEL_WIDTH 1u
10506 #define SCG_SIRCCSR_SIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCSR_SIRCSEL_SHIFT))&SCG_SIRCCSR_SIRCSEL_MASK)
10507 /* SIRCDIV Bit Fields */
10508 #define SCG_SIRCDIV_SIRCDIV1_MASK 0x7u
10509 #define SCG_SIRCDIV_SIRCDIV1_SHIFT 0u
10510 #define SCG_SIRCDIV_SIRCDIV1_WIDTH 3u
10511 #define SCG_SIRCDIV_SIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV1_SHIFT))&SCG_SIRCDIV_SIRCDIV1_MASK)
10512 #define SCG_SIRCDIV_SIRCDIV2_MASK 0x700u
10513 #define SCG_SIRCDIV_SIRCDIV2_SHIFT 8u
10514 #define SCG_SIRCDIV_SIRCDIV2_WIDTH 3u
10515 #define SCG_SIRCDIV_SIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCDIV_SIRCDIV2_SHIFT))&SCG_SIRCDIV_SIRCDIV2_MASK)
10516 /* SIRCCFG Bit Fields */
10517 #define SCG_SIRCCFG_RANGE_MASK 0x1u
10518 #define SCG_SIRCCFG_RANGE_SHIFT 0u
10519 #define SCG_SIRCCFG_RANGE_WIDTH 1u
10520 #define SCG_SIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SIRCCFG_RANGE_SHIFT))&SCG_SIRCCFG_RANGE_MASK)
10521 /* FIRCCSR Bit Fields */
10522 #define SCG_FIRCCSR_FIRCEN_MASK 0x1u
10523 #define SCG_FIRCCSR_FIRCEN_SHIFT 0u
10524 #define SCG_FIRCCSR_FIRCEN_WIDTH 1u
10525 #define SCG_FIRCCSR_FIRCEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCEN_SHIFT))&SCG_FIRCCSR_FIRCEN_MASK)
10526 #define SCG_FIRCCSR_FIRCREGOFF_MASK 0x8u
10527 #define SCG_FIRCCSR_FIRCREGOFF_SHIFT 3u
10528 #define SCG_FIRCCSR_FIRCREGOFF_WIDTH 1u
10529 #define SCG_FIRCCSR_FIRCREGOFF(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCREGOFF_SHIFT))&SCG_FIRCCSR_FIRCREGOFF_MASK)
10530 #define SCG_FIRCCSR_LK_MASK 0x800000u
10531 #define SCG_FIRCCSR_LK_SHIFT 23u
10532 #define SCG_FIRCCSR_LK_WIDTH 1u
10533 #define SCG_FIRCCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_LK_SHIFT))&SCG_FIRCCSR_LK_MASK)
10534 #define SCG_FIRCCSR_FIRCVLD_MASK 0x1000000u
10535 #define SCG_FIRCCSR_FIRCVLD_SHIFT 24u
10536 #define SCG_FIRCCSR_FIRCVLD_WIDTH 1u
10537 #define SCG_FIRCCSR_FIRCVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCVLD_SHIFT))&SCG_FIRCCSR_FIRCVLD_MASK)
10538 #define SCG_FIRCCSR_FIRCSEL_MASK 0x2000000u
10539 #define SCG_FIRCCSR_FIRCSEL_SHIFT 25u
10540 #define SCG_FIRCCSR_FIRCSEL_WIDTH 1u
10541 #define SCG_FIRCCSR_FIRCSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCSEL_SHIFT))&SCG_FIRCCSR_FIRCSEL_MASK)
10542 #define SCG_FIRCCSR_FIRCERR_MASK 0x4000000u
10543 #define SCG_FIRCCSR_FIRCERR_SHIFT 26u
10544 #define SCG_FIRCCSR_FIRCERR_WIDTH 1u
10545 #define SCG_FIRCCSR_FIRCERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCSR_FIRCERR_SHIFT))&SCG_FIRCCSR_FIRCERR_MASK)
10546 /* FIRCDIV Bit Fields */
10547 #define SCG_FIRCDIV_FIRCDIV1_MASK 0x7u
10548 #define SCG_FIRCDIV_FIRCDIV1_SHIFT 0u
10549 #define SCG_FIRCDIV_FIRCDIV1_WIDTH 3u
10550 #define SCG_FIRCDIV_FIRCDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV1_SHIFT))&SCG_FIRCDIV_FIRCDIV1_MASK)
10551 #define SCG_FIRCDIV_FIRCDIV2_MASK 0x700u
10552 #define SCG_FIRCDIV_FIRCDIV2_SHIFT 8u
10553 #define SCG_FIRCDIV_FIRCDIV2_WIDTH 3u
10554 #define SCG_FIRCDIV_FIRCDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCDIV_FIRCDIV2_SHIFT))&SCG_FIRCDIV_FIRCDIV2_MASK)
10555 /* FIRCCFG Bit Fields */
10556 #define SCG_FIRCCFG_RANGE_MASK 0x3u
10557 #define SCG_FIRCCFG_RANGE_SHIFT 0u
10558 #define SCG_FIRCCFG_RANGE_WIDTH 2u
10559 #define SCG_FIRCCFG_RANGE(x) (((uint32_t)(((uint32_t)(x))<<SCG_FIRCCFG_RANGE_SHIFT))&SCG_FIRCCFG_RANGE_MASK)
10560 /* SPLLCSR Bit Fields */
10561 #define SCG_SPLLCSR_SPLLEN_MASK 0x1u
10562 #define SCG_SPLLCSR_SPLLEN_SHIFT 0u
10563 #define SCG_SPLLCSR_SPLLEN_WIDTH 1u
10564 #define SCG_SPLLCSR_SPLLEN(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLEN_SHIFT))&SCG_SPLLCSR_SPLLEN_MASK)
10565 #define SCG_SPLLCSR_SPLLCM_MASK 0x10000u
10566 #define SCG_SPLLCSR_SPLLCM_SHIFT 16u
10567 #define SCG_SPLLCSR_SPLLCM_WIDTH 1u
10568 #define SCG_SPLLCSR_SPLLCM(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCM_SHIFT))&SCG_SPLLCSR_SPLLCM_MASK)
10569 #define SCG_SPLLCSR_SPLLCMRE_MASK 0x20000u
10570 #define SCG_SPLLCSR_SPLLCMRE_SHIFT 17u
10571 #define SCG_SPLLCSR_SPLLCMRE_WIDTH 1u
10572 #define SCG_SPLLCSR_SPLLCMRE(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLCMRE_SHIFT))&SCG_SPLLCSR_SPLLCMRE_MASK)
10573 #define SCG_SPLLCSR_LK_MASK 0x800000u
10574 #define SCG_SPLLCSR_LK_SHIFT 23u
10575 #define SCG_SPLLCSR_LK_WIDTH 1u
10576 #define SCG_SPLLCSR_LK(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_LK_SHIFT))&SCG_SPLLCSR_LK_MASK)
10577 #define SCG_SPLLCSR_SPLLVLD_MASK 0x1000000u
10578 #define SCG_SPLLCSR_SPLLVLD_SHIFT 24u
10579 #define SCG_SPLLCSR_SPLLVLD_WIDTH 1u
10580 #define SCG_SPLLCSR_SPLLVLD(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLVLD_SHIFT))&SCG_SPLLCSR_SPLLVLD_MASK)
10581 #define SCG_SPLLCSR_SPLLSEL_MASK 0x2000000u
10582 #define SCG_SPLLCSR_SPLLSEL_SHIFT 25u
10583 #define SCG_SPLLCSR_SPLLSEL_WIDTH 1u
10584 #define SCG_SPLLCSR_SPLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLSEL_SHIFT))&SCG_SPLLCSR_SPLLSEL_MASK)
10585 #define SCG_SPLLCSR_SPLLERR_MASK 0x4000000u
10586 #define SCG_SPLLCSR_SPLLERR_SHIFT 26u
10587 #define SCG_SPLLCSR_SPLLERR_WIDTH 1u
10588 #define SCG_SPLLCSR_SPLLERR(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCSR_SPLLERR_SHIFT))&SCG_SPLLCSR_SPLLERR_MASK)
10589 /* SPLLDIV Bit Fields */
10590 #define SCG_SPLLDIV_SPLLDIV1_MASK 0x7u
10591 #define SCG_SPLLDIV_SPLLDIV1_SHIFT 0u
10592 #define SCG_SPLLDIV_SPLLDIV1_WIDTH 3u
10593 #define SCG_SPLLDIV_SPLLDIV1(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV1_SHIFT))&SCG_SPLLDIV_SPLLDIV1_MASK)
10594 #define SCG_SPLLDIV_SPLLDIV2_MASK 0x700u
10595 #define SCG_SPLLDIV_SPLLDIV2_SHIFT 8u
10596 #define SCG_SPLLDIV_SPLLDIV2_WIDTH 3u
10597 #define SCG_SPLLDIV_SPLLDIV2(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLDIV_SPLLDIV2_SHIFT))&SCG_SPLLDIV_SPLLDIV2_MASK)
10598 /* SPLLCFG Bit Fields */
10599 #define SCG_SPLLCFG_PREDIV_MASK 0x700u
10600 #define SCG_SPLLCFG_PREDIV_SHIFT 8u
10601 #define SCG_SPLLCFG_PREDIV_WIDTH 3u
10602 #define SCG_SPLLCFG_PREDIV(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_PREDIV_SHIFT))&SCG_SPLLCFG_PREDIV_MASK)
10603 #define SCG_SPLLCFG_MULT_MASK 0x1F0000u
10604 #define SCG_SPLLCFG_MULT_SHIFT 16u
10605 #define SCG_SPLLCFG_MULT_WIDTH 5u
10606 #define SCG_SPLLCFG_MULT(x) (((uint32_t)(((uint32_t)(x))<<SCG_SPLLCFG_MULT_SHIFT))&SCG_SPLLCFG_MULT_MASK)
10607  /* end of group SCG_Register_Masks */
10611 
10612  /* end of group SCG_Peripheral_Access_Layer */
10616 
10617 
10618 /* ----------------------------------------------------------------------------
10619  -- SIM Peripheral Access Layer
10620  ---------------------------------------------------------------------------- */
10621 
10631 typedef struct {
10632  uint8_t RESERVED_0[4];
10633  __IO uint32_t CHIPCTL;
10634  uint8_t RESERVED_1[4];
10635  __IO uint32_t FTMOPT0;
10636  __IO uint32_t LPOCLKS;
10637  uint8_t RESERVED_2[4];
10638  __IO uint32_t ADCOPT;
10639  __IO uint32_t FTMOPT1;
10640  __IO uint32_t MISCTRL0;
10641  __I uint32_t SDID;
10642  uint8_t RESERVED_3[24];
10643  __IO uint32_t PLATCGC;
10644  uint8_t RESERVED_4[8];
10645  __IO uint32_t FCFG1;
10646  uint8_t RESERVED_5[4];
10647  __I uint32_t UIDH;
10648  __I uint32_t UIDMH;
10649  __I uint32_t UIDML;
10650  __I uint32_t UIDL;
10651  uint8_t RESERVED_6[4];
10652  __IO uint32_t CLKDIV4;
10653  __IO uint32_t MISCTRL1;
10655 
10657 #define SIM_INSTANCE_COUNT (1u)
10658 
10659 
10660 /* SIM - Peripheral instance base addresses */
10662 #define SIM_BASE (0x40048000u)
10663 
10664 #define SIM ((SIM_Type *)SIM_BASE)
10665 
10666 #define SIM_BASE_ADDRS { SIM_BASE }
10667 
10668 #define SIM_BASE_PTRS { SIM }
10669 
10670 /* ----------------------------------------------------------------------------
10671  -- SIM Register Masks
10672  ---------------------------------------------------------------------------- */
10673 
10679 /* CHIPCTL Bit Fields */
10680 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK 0xFu
10681 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT 0u
10682 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN_WIDTH 4u
10683 #define SIM_CHIPCTL_ADC_INTERLEAVE_EN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_INTERLEAVE_EN_SHIFT))&SIM_CHIPCTL_ADC_INTERLEAVE_EN_MASK)
10684 #define SIM_CHIPCTL_CLKOUTSEL_MASK 0xF0u
10685 #define SIM_CHIPCTL_CLKOUTSEL_SHIFT 4u
10686 #define SIM_CHIPCTL_CLKOUTSEL_WIDTH 4u
10687 #define SIM_CHIPCTL_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTSEL_SHIFT))&SIM_CHIPCTL_CLKOUTSEL_MASK)
10688 #define SIM_CHIPCTL_CLKOUTDIV_MASK 0x700u
10689 #define SIM_CHIPCTL_CLKOUTDIV_SHIFT 8u
10690 #define SIM_CHIPCTL_CLKOUTDIV_WIDTH 3u
10691 #define SIM_CHIPCTL_CLKOUTDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTDIV_SHIFT))&SIM_CHIPCTL_CLKOUTDIV_MASK)
10692 #define SIM_CHIPCTL_CLKOUTEN_MASK 0x800u
10693 #define SIM_CHIPCTL_CLKOUTEN_SHIFT 11u
10694 #define SIM_CHIPCTL_CLKOUTEN_WIDTH 1u
10695 #define SIM_CHIPCTL_CLKOUTEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_CLKOUTEN_SHIFT))&SIM_CHIPCTL_CLKOUTEN_MASK)
10696 #define SIM_CHIPCTL_TRACECLK_SEL_MASK 0x1000u
10697 #define SIM_CHIPCTL_TRACECLK_SEL_SHIFT 12u
10698 #define SIM_CHIPCTL_TRACECLK_SEL_WIDTH 1u
10699 #define SIM_CHIPCTL_TRACECLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_TRACECLK_SEL_SHIFT))&SIM_CHIPCTL_TRACECLK_SEL_MASK)
10700 #define SIM_CHIPCTL_PDB_BB_SEL_MASK 0x2000u
10701 #define SIM_CHIPCTL_PDB_BB_SEL_SHIFT 13u
10702 #define SIM_CHIPCTL_PDB_BB_SEL_WIDTH 1u
10703 #define SIM_CHIPCTL_PDB_BB_SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_PDB_BB_SEL_SHIFT))&SIM_CHIPCTL_PDB_BB_SEL_MASK)
10704 #define SIM_CHIPCTL_ADC_SUPPLY_MASK 0x70000u
10705 #define SIM_CHIPCTL_ADC_SUPPLY_SHIFT 16u
10706 #define SIM_CHIPCTL_ADC_SUPPLY_WIDTH 3u
10707 #define SIM_CHIPCTL_ADC_SUPPLY(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLY_SHIFT))&SIM_CHIPCTL_ADC_SUPPLY_MASK)
10708 #define SIM_CHIPCTL_ADC_SUPPLYEN_MASK 0x80000u
10709 #define SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT 19u
10710 #define SIM_CHIPCTL_ADC_SUPPLYEN_WIDTH 1u
10711 #define SIM_CHIPCTL_ADC_SUPPLYEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_ADC_SUPPLYEN_SHIFT))&SIM_CHIPCTL_ADC_SUPPLYEN_MASK)
10712 #define SIM_CHIPCTL_SRAMU_RETEN_MASK 0x100000u
10713 #define SIM_CHIPCTL_SRAMU_RETEN_SHIFT 20u
10714 #define SIM_CHIPCTL_SRAMU_RETEN_WIDTH 1u
10715 #define SIM_CHIPCTL_SRAMU_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAMU_RETEN_SHIFT))&SIM_CHIPCTL_SRAMU_RETEN_MASK)
10716 #define SIM_CHIPCTL_SRAML_RETEN_MASK 0x200000u
10717 #define SIM_CHIPCTL_SRAML_RETEN_SHIFT 21u
10718 #define SIM_CHIPCTL_SRAML_RETEN_WIDTH 1u
10719 #define SIM_CHIPCTL_SRAML_RETEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CHIPCTL_SRAML_RETEN_SHIFT))&SIM_CHIPCTL_SRAML_RETEN_MASK)
10720 /* FTMOPT0 Bit Fields */
10721 #define SIM_FTMOPT0_FTM0FLTxSEL_MASK 0x7u
10722 #define SIM_FTMOPT0_FTM0FLTxSEL_SHIFT 0u
10723 #define SIM_FTMOPT0_FTM0FLTxSEL_WIDTH 3u
10724 #define SIM_FTMOPT0_FTM0FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM0FLTxSEL_MASK)
10725 #define SIM_FTMOPT0_FTM1FLTxSEL_MASK 0x70u
10726 #define SIM_FTMOPT0_FTM1FLTxSEL_SHIFT 4u
10727 #define SIM_FTMOPT0_FTM1FLTxSEL_WIDTH 3u
10728 #define SIM_FTMOPT0_FTM1FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM1FLTxSEL_MASK)
10729 #define SIM_FTMOPT0_FTM2FLTxSEL_MASK 0x700u
10730 #define SIM_FTMOPT0_FTM2FLTxSEL_SHIFT 8u
10731 #define SIM_FTMOPT0_FTM2FLTxSEL_WIDTH 3u
10732 #define SIM_FTMOPT0_FTM2FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM2FLTxSEL_MASK)
10733 #define SIM_FTMOPT0_FTM3FLTxSEL_MASK 0x7000u
10734 #define SIM_FTMOPT0_FTM3FLTxSEL_SHIFT 12u
10735 #define SIM_FTMOPT0_FTM3FLTxSEL_WIDTH 3u
10736 #define SIM_FTMOPT0_FTM3FLTxSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3FLTxSEL_SHIFT))&SIM_FTMOPT0_FTM3FLTxSEL_MASK)
10737 #define SIM_FTMOPT0_FTM0CLKSEL_MASK 0x3000000u
10738 #define SIM_FTMOPT0_FTM0CLKSEL_SHIFT 24u
10739 #define SIM_FTMOPT0_FTM0CLKSEL_WIDTH 2u
10740 #define SIM_FTMOPT0_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM0CLKSEL_SHIFT))&SIM_FTMOPT0_FTM0CLKSEL_MASK)
10741 #define SIM_FTMOPT0_FTM1CLKSEL_MASK 0xC000000u
10742 #define SIM_FTMOPT0_FTM1CLKSEL_SHIFT 26u
10743 #define SIM_FTMOPT0_FTM1CLKSEL_WIDTH 2u
10744 #define SIM_FTMOPT0_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM1CLKSEL_SHIFT))&SIM_FTMOPT0_FTM1CLKSEL_MASK)
10745 #define SIM_FTMOPT0_FTM2CLKSEL_MASK 0x30000000u
10746 #define SIM_FTMOPT0_FTM2CLKSEL_SHIFT 28u
10747 #define SIM_FTMOPT0_FTM2CLKSEL_WIDTH 2u
10748 #define SIM_FTMOPT0_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM2CLKSEL_SHIFT))&SIM_FTMOPT0_FTM2CLKSEL_MASK)
10749 #define SIM_FTMOPT0_FTM3CLKSEL_MASK 0xC0000000u
10750 #define SIM_FTMOPT0_FTM3CLKSEL_SHIFT 30u
10751 #define SIM_FTMOPT0_FTM3CLKSEL_WIDTH 2u
10752 #define SIM_FTMOPT0_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT0_FTM3CLKSEL_SHIFT))&SIM_FTMOPT0_FTM3CLKSEL_MASK)
10753 /* LPOCLKS Bit Fields */
10754 #define SIM_LPOCLKS_LPO1KCLKEN_MASK 0x1u
10755 #define SIM_LPOCLKS_LPO1KCLKEN_SHIFT 0u
10756 #define SIM_LPOCLKS_LPO1KCLKEN_WIDTH 1u
10757 #define SIM_LPOCLKS_LPO1KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO1KCLKEN_SHIFT))&SIM_LPOCLKS_LPO1KCLKEN_MASK)
10758 #define SIM_LPOCLKS_LPO32KCLKEN_MASK 0x2u
10759 #define SIM_LPOCLKS_LPO32KCLKEN_SHIFT 1u
10760 #define SIM_LPOCLKS_LPO32KCLKEN_WIDTH 1u
10761 #define SIM_LPOCLKS_LPO32KCLKEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPO32KCLKEN_SHIFT))&SIM_LPOCLKS_LPO32KCLKEN_MASK)
10762 #define SIM_LPOCLKS_LPOCLKSEL_MASK 0xCu
10763 #define SIM_LPOCLKS_LPOCLKSEL_SHIFT 2u
10764 #define SIM_LPOCLKS_LPOCLKSEL_WIDTH 2u
10765 #define SIM_LPOCLKS_LPOCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_LPOCLKSEL_SHIFT))&SIM_LPOCLKS_LPOCLKSEL_MASK)
10766 #define SIM_LPOCLKS_RTCCLKSEL_MASK 0x30u
10767 #define SIM_LPOCLKS_RTCCLKSEL_SHIFT 4u
10768 #define SIM_LPOCLKS_RTCCLKSEL_WIDTH 2u
10769 #define SIM_LPOCLKS_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_LPOCLKS_RTCCLKSEL_SHIFT))&SIM_LPOCLKS_RTCCLKSEL_MASK)
10770 /* ADCOPT Bit Fields */
10771 #define SIM_ADCOPT_ADC0TRGSEL_MASK 0x1u
10772 #define SIM_ADCOPT_ADC0TRGSEL_SHIFT 0u
10773 #define SIM_ADCOPT_ADC0TRGSEL_WIDTH 1u
10774 #define SIM_ADCOPT_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0TRGSEL_SHIFT))&SIM_ADCOPT_ADC0TRGSEL_MASK)
10775 #define SIM_ADCOPT_ADC0SWPRETRG_MASK 0xEu
10776 #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT 1u
10777 #define SIM_ADCOPT_ADC0SWPRETRG_WIDTH 3u
10778 #define SIM_ADCOPT_ADC0SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0SWPRETRG_SHIFT))&SIM_ADCOPT_ADC0SWPRETRG_MASK)
10779 #define SIM_ADCOPT_ADC0PRETRGSEL_MASK 0x30u
10780 #define SIM_ADCOPT_ADC0PRETRGSEL_SHIFT 4u
10781 #define SIM_ADCOPT_ADC0PRETRGSEL_WIDTH 2u
10782 #define SIM_ADCOPT_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC0PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC0PRETRGSEL_MASK)
10783 #define SIM_ADCOPT_ADC1TRGSEL_MASK 0x100u
10784 #define SIM_ADCOPT_ADC1TRGSEL_SHIFT 8u
10785 #define SIM_ADCOPT_ADC1TRGSEL_WIDTH 1u
10786 #define SIM_ADCOPT_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1TRGSEL_SHIFT))&SIM_ADCOPT_ADC1TRGSEL_MASK)
10787 #define SIM_ADCOPT_ADC1SWPRETRG_MASK 0xE00u
10788 #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT 9u
10789 #define SIM_ADCOPT_ADC1SWPRETRG_WIDTH 3u
10790 #define SIM_ADCOPT_ADC1SWPRETRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1SWPRETRG_SHIFT))&SIM_ADCOPT_ADC1SWPRETRG_MASK)
10791 #define SIM_ADCOPT_ADC1PRETRGSEL_MASK 0x3000u
10792 #define SIM_ADCOPT_ADC1PRETRGSEL_SHIFT 12u
10793 #define SIM_ADCOPT_ADC1PRETRGSEL_WIDTH 2u
10794 #define SIM_ADCOPT_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_ADCOPT_ADC1PRETRGSEL_SHIFT))&SIM_ADCOPT_ADC1PRETRGSEL_MASK)
10795 /* FTMOPT1 Bit Fields */
10796 #define SIM_FTMOPT1_FTM0SYNCBIT_MASK 0x1u
10797 #define SIM_FTMOPT1_FTM0SYNCBIT_SHIFT 0u
10798 #define SIM_FTMOPT1_FTM0SYNCBIT_WIDTH 1u
10799 #define SIM_FTMOPT1_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM0SYNCBIT_MASK)
10800 #define SIM_FTMOPT1_FTM1SYNCBIT_MASK 0x2u
10801 #define SIM_FTMOPT1_FTM1SYNCBIT_SHIFT 1u
10802 #define SIM_FTMOPT1_FTM1SYNCBIT_WIDTH 1u
10803 #define SIM_FTMOPT1_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM1SYNCBIT_MASK)
10804 #define SIM_FTMOPT1_FTM2SYNCBIT_MASK 0x4u
10805 #define SIM_FTMOPT1_FTM2SYNCBIT_SHIFT 2u
10806 #define SIM_FTMOPT1_FTM2SYNCBIT_WIDTH 1u
10807 #define SIM_FTMOPT1_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM2SYNCBIT_MASK)
10808 #define SIM_FTMOPT1_FTM3SYNCBIT_MASK 0x8u
10809 #define SIM_FTMOPT1_FTM3SYNCBIT_SHIFT 3u
10810 #define SIM_FTMOPT1_FTM3SYNCBIT_WIDTH 1u
10811 #define SIM_FTMOPT1_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3SYNCBIT_SHIFT))&SIM_FTMOPT1_FTM3SYNCBIT_MASK)
10812 #define SIM_FTMOPT1_FTM1CH0SEL_MASK 0x30u
10813 #define SIM_FTMOPT1_FTM1CH0SEL_SHIFT 4u
10814 #define SIM_FTMOPT1_FTM1CH0SEL_WIDTH 2u
10815 #define SIM_FTMOPT1_FTM1CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM1CH0SEL_SHIFT))&SIM_FTMOPT1_FTM1CH0SEL_MASK)
10816 #define SIM_FTMOPT1_FTM2CH0SEL_MASK 0xC0u
10817 #define SIM_FTMOPT1_FTM2CH0SEL_SHIFT 6u
10818 #define SIM_FTMOPT1_FTM2CH0SEL_WIDTH 2u
10819 #define SIM_FTMOPT1_FTM2CH0SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH0SEL_SHIFT))&SIM_FTMOPT1_FTM2CH0SEL_MASK)
10820 #define SIM_FTMOPT1_FTM2CH1SEL_MASK 0x100u
10821 #define SIM_FTMOPT1_FTM2CH1SEL_SHIFT 8u
10822 #define SIM_FTMOPT1_FTM2CH1SEL_WIDTH 1u
10823 #define SIM_FTMOPT1_FTM2CH1SEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM2CH1SEL_SHIFT))&SIM_FTMOPT1_FTM2CH1SEL_MASK)
10824 #define SIM_FTMOPT1_FTMGLDOK_MASK 0x8000u
10825 #define SIM_FTMOPT1_FTMGLDOK_SHIFT 15u
10826 #define SIM_FTMOPT1_FTMGLDOK_WIDTH 1u
10827 #define SIM_FTMOPT1_FTMGLDOK(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTMGLDOK_SHIFT))&SIM_FTMOPT1_FTMGLDOK_MASK)
10828 #define SIM_FTMOPT1_FTM0_OUTSEL_MASK 0xFF0000u
10829 #define SIM_FTMOPT1_FTM0_OUTSEL_SHIFT 16u
10830 #define SIM_FTMOPT1_FTM0_OUTSEL_WIDTH 8u
10831 #define SIM_FTMOPT1_FTM0_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM0_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM0_OUTSEL_MASK)
10832 #define SIM_FTMOPT1_FTM3_OUTSEL_MASK 0xFF000000u
10833 #define SIM_FTMOPT1_FTM3_OUTSEL_SHIFT 24u
10834 #define SIM_FTMOPT1_FTM3_OUTSEL_WIDTH 8u
10835 #define SIM_FTMOPT1_FTM3_OUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_FTMOPT1_FTM3_OUTSEL_SHIFT))&SIM_FTMOPT1_FTM3_OUTSEL_MASK)
10836 /* MISCTRL0 Bit Fields */
10837 #define SIM_MISCTRL0_FTM0_OBE_CTRL_MASK 0x10000u
10838 #define SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT 16u
10839 #define SIM_MISCTRL0_FTM0_OBE_CTRL_WIDTH 1u
10840 #define SIM_MISCTRL0_FTM0_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM0_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM0_OBE_CTRL_MASK)
10841 #define SIM_MISCTRL0_FTM1_OBE_CTRL_MASK 0x20000u
10842 #define SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT 17u
10843 #define SIM_MISCTRL0_FTM1_OBE_CTRL_WIDTH 1u
10844 #define SIM_MISCTRL0_FTM1_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM1_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM1_OBE_CTRL_MASK)
10845 #define SIM_MISCTRL0_FTM2_OBE_CTRL_MASK 0x40000u
10846 #define SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT 18u
10847 #define SIM_MISCTRL0_FTM2_OBE_CTRL_WIDTH 1u
10848 #define SIM_MISCTRL0_FTM2_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM2_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM2_OBE_CTRL_MASK)
10849 #define SIM_MISCTRL0_FTM3_OBE_CTRL_MASK 0x80000u
10850 #define SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT 19u
10851 #define SIM_MISCTRL0_FTM3_OBE_CTRL_WIDTH 1u
10852 #define SIM_MISCTRL0_FTM3_OBE_CTRL(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL0_FTM3_OBE_CTRL_SHIFT))&SIM_MISCTRL0_FTM3_OBE_CTRL_MASK)
10853 /* SDID Bit Fields */
10854 #define SIM_SDID_FEATURES_MASK 0xFFu
10855 #define SIM_SDID_FEATURES_SHIFT 0u
10856 #define SIM_SDID_FEATURES_WIDTH 8u
10857 #define SIM_SDID_FEATURES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FEATURES_SHIFT))&SIM_SDID_FEATURES_MASK)
10858 #define SIM_SDID_PACKAGE_MASK 0xF00u
10859 #define SIM_SDID_PACKAGE_SHIFT 8u
10860 #define SIM_SDID_PACKAGE_WIDTH 4u
10861 #define SIM_SDID_PACKAGE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PACKAGE_SHIFT))&SIM_SDID_PACKAGE_MASK)
10862 #define SIM_SDID_REVID_MASK 0xF000u
10863 #define SIM_SDID_REVID_SHIFT 12u
10864 #define SIM_SDID_REVID_WIDTH 4u
10865 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
10866 #define SIM_SDID_RAMSIZE_MASK 0xF0000u
10867 #define SIM_SDID_RAMSIZE_SHIFT 16u
10868 #define SIM_SDID_RAMSIZE_WIDTH 4u
10869 #define SIM_SDID_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_RAMSIZE_SHIFT))&SIM_SDID_RAMSIZE_MASK)
10870 #define SIM_SDID_DERIVATE_MASK 0xF00000u
10871 #define SIM_SDID_DERIVATE_SHIFT 20u
10872 #define SIM_SDID_DERIVATE_WIDTH 4u
10873 #define SIM_SDID_DERIVATE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DERIVATE_SHIFT))&SIM_SDID_DERIVATE_MASK)
10874 #define SIM_SDID_SUBSERIES_MASK 0xF000000u
10875 #define SIM_SDID_SUBSERIES_SHIFT 24u
10876 #define SIM_SDID_SUBSERIES_WIDTH 4u
10877 #define SIM_SDID_SUBSERIES(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBSERIES_SHIFT))&SIM_SDID_SUBSERIES_MASK)
10878 #define SIM_SDID_GENERATION_MASK 0xF0000000u
10879 #define SIM_SDID_GENERATION_SHIFT 28u
10880 #define SIM_SDID_GENERATION_WIDTH 4u
10881 #define SIM_SDID_GENERATION(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_GENERATION_SHIFT))&SIM_SDID_GENERATION_MASK)
10882 /* PLATCGC Bit Fields */
10883 #define SIM_PLATCGC_CGCMSCM_MASK 0x1u
10884 #define SIM_PLATCGC_CGCMSCM_SHIFT 0u
10885 #define SIM_PLATCGC_CGCMSCM_WIDTH 1u
10886 #define SIM_PLATCGC_CGCMSCM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMSCM_SHIFT))&SIM_PLATCGC_CGCMSCM_MASK)
10887 #define SIM_PLATCGC_CGCMPU_MASK 0x2u
10888 #define SIM_PLATCGC_CGCMPU_SHIFT 1u
10889 #define SIM_PLATCGC_CGCMPU_WIDTH 1u
10890 #define SIM_PLATCGC_CGCMPU(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCMPU_SHIFT))&SIM_PLATCGC_CGCMPU_MASK)
10891 #define SIM_PLATCGC_CGCDMA_MASK 0x4u
10892 #define SIM_PLATCGC_CGCDMA_SHIFT 2u
10893 #define SIM_PLATCGC_CGCDMA_WIDTH 1u
10894 #define SIM_PLATCGC_CGCDMA(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCDMA_SHIFT))&SIM_PLATCGC_CGCDMA_MASK)
10895 #define SIM_PLATCGC_CGCERM_MASK 0x8u
10896 #define SIM_PLATCGC_CGCERM_SHIFT 3u
10897 #define SIM_PLATCGC_CGCERM_WIDTH 1u
10898 #define SIM_PLATCGC_CGCERM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCERM_SHIFT))&SIM_PLATCGC_CGCERM_MASK)
10899 #define SIM_PLATCGC_CGCEIM_MASK 0x10u
10900 #define SIM_PLATCGC_CGCEIM_SHIFT 4u
10901 #define SIM_PLATCGC_CGCEIM_WIDTH 1u
10902 #define SIM_PLATCGC_CGCEIM(x) (((uint32_t)(((uint32_t)(x))<<SIM_PLATCGC_CGCEIM_SHIFT))&SIM_PLATCGC_CGCEIM_MASK)
10903 /* FCFG1 Bit Fields */
10904 #define SIM_FCFG1_DEPART_MASK 0xF000u
10905 #define SIM_FCFG1_DEPART_SHIFT 12u
10906 #define SIM_FCFG1_DEPART_WIDTH 4u
10907 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
10908 #define SIM_FCFG1_EEERAMSIZE_MASK 0xF0000u
10909 #define SIM_FCFG1_EEERAMSIZE_SHIFT 16u
10910 #define SIM_FCFG1_EEERAMSIZE_WIDTH 4u
10911 #define SIM_FCFG1_EEERAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EEERAMSIZE_SHIFT))&SIM_FCFG1_EEERAMSIZE_MASK)
10912 /* UIDH Bit Fields */
10913 #define SIM_UIDH_UID127_96_MASK 0xFFFFFFFFu
10914 #define SIM_UIDH_UID127_96_SHIFT 0u
10915 #define SIM_UIDH_UID127_96_WIDTH 32u
10916 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID127_96_SHIFT))&SIM_UIDH_UID127_96_MASK)
10917 /* UIDMH Bit Fields */
10918 #define SIM_UIDMH_UID95_64_MASK 0xFFFFFFFFu
10919 #define SIM_UIDMH_UID95_64_SHIFT 0u
10920 #define SIM_UIDMH_UID95_64_WIDTH 32u
10921 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID95_64_SHIFT))&SIM_UIDMH_UID95_64_MASK)
10922 /* UIDML Bit Fields */
10923 #define SIM_UIDML_UID63_32_MASK 0xFFFFFFFFu
10924 #define SIM_UIDML_UID63_32_SHIFT 0u
10925 #define SIM_UIDML_UID63_32_WIDTH 32u
10926 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID63_32_SHIFT))&SIM_UIDML_UID63_32_MASK)
10927 /* UIDL Bit Fields */
10928 #define SIM_UIDL_UID31_0_MASK 0xFFFFFFFFu
10929 #define SIM_UIDL_UID31_0_SHIFT 0u
10930 #define SIM_UIDL_UID31_0_WIDTH 32u
10931 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID31_0_SHIFT))&SIM_UIDL_UID31_0_MASK)
10932 /* CLKDIV4 Bit Fields */
10933 #define SIM_CLKDIV4_TRACEFRAC_MASK 0x1u
10934 #define SIM_CLKDIV4_TRACEFRAC_SHIFT 0u
10935 #define SIM_CLKDIV4_TRACEFRAC_WIDTH 1u
10936 #define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEFRAC_SHIFT))&SIM_CLKDIV4_TRACEFRAC_MASK)
10937 #define SIM_CLKDIV4_TRACEDIV_MASK 0xEu
10938 #define SIM_CLKDIV4_TRACEDIV_SHIFT 1u
10939 #define SIM_CLKDIV4_TRACEDIV_WIDTH 3u
10940 #define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIV_SHIFT))&SIM_CLKDIV4_TRACEDIV_MASK)
10941 #define SIM_CLKDIV4_TRACEDIVEN_MASK 0x10000000u
10942 #define SIM_CLKDIV4_TRACEDIVEN_SHIFT 28u
10943 #define SIM_CLKDIV4_TRACEDIVEN_WIDTH 1u
10944 #define SIM_CLKDIV4_TRACEDIVEN(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV4_TRACEDIVEN_SHIFT))&SIM_CLKDIV4_TRACEDIVEN_MASK)
10945 /* MISCTRL1 Bit Fields */
10946 #define SIM_MISCTRL1_SW_TRG_MASK 0x1u
10947 #define SIM_MISCTRL1_SW_TRG_SHIFT 0u
10948 #define SIM_MISCTRL1_SW_TRG_WIDTH 1u
10949 #define SIM_MISCTRL1_SW_TRG(x) (((uint32_t)(((uint32_t)(x))<<SIM_MISCTRL1_SW_TRG_SHIFT))&SIM_MISCTRL1_SW_TRG_MASK)
10950  /* end of group SIM_Register_Masks */
10954 
10955  /* end of group SIM_Peripheral_Access_Layer */
10959 
10960 
10961 /* ----------------------------------------------------------------------------
10962  -- SMC Peripheral Access Layer
10963  ---------------------------------------------------------------------------- */
10964 
10974 typedef struct {
10975  __I uint32_t VERID;
10976  __I uint32_t PARAM;
10977  __IO uint32_t PMPROT;
10978  __IO uint32_t PMCTRL;
10979  __IO uint32_t STOPCTRL;
10980  __I uint32_t PMSTAT;
10982 
10984 #define SMC_INSTANCE_COUNT (1u)
10985 
10986 
10987 /* SMC - Peripheral instance base addresses */
10989 #define SMC_BASE (0x4007E000u)
10990 
10991 #define SMC ((SMC_Type *)SMC_BASE)
10992 
10993 #define SMC_BASE_ADDRS { SMC_BASE }
10994 
10995 #define SMC_BASE_PTRS { SMC }
10996 
10997 /* ----------------------------------------------------------------------------
10998  -- SMC Register Masks
10999  ---------------------------------------------------------------------------- */
11000 
11006 /* VERID Bit Fields */
11007 #define SMC_VERID_FEATURE_MASK 0xFFFFu
11008 #define SMC_VERID_FEATURE_SHIFT 0u
11009 #define SMC_VERID_FEATURE_WIDTH 16u
11010 #define SMC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_FEATURE_SHIFT))&SMC_VERID_FEATURE_MASK)
11011 #define SMC_VERID_MINOR_MASK 0xFF0000u
11012 #define SMC_VERID_MINOR_SHIFT 16u
11013 #define SMC_VERID_MINOR_WIDTH 8u
11014 #define SMC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MINOR_SHIFT))&SMC_VERID_MINOR_MASK)
11015 #define SMC_VERID_MAJOR_MASK 0xFF000000u
11016 #define SMC_VERID_MAJOR_SHIFT 24u
11017 #define SMC_VERID_MAJOR_WIDTH 8u
11018 #define SMC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<SMC_VERID_MAJOR_SHIFT))&SMC_VERID_MAJOR_MASK)
11019 /* PARAM Bit Fields */
11020 #define SMC_PARAM_EHSRUN_MASK 0x1u
11021 #define SMC_PARAM_EHSRUN_SHIFT 0u
11022 #define SMC_PARAM_EHSRUN_WIDTH 1u
11023 #define SMC_PARAM_EHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EHSRUN_SHIFT))&SMC_PARAM_EHSRUN_MASK)
11024 #define SMC_PARAM_ELLS_MASK 0x8u
11025 #define SMC_PARAM_ELLS_SHIFT 3u
11026 #define SMC_PARAM_ELLS_WIDTH 1u
11027 #define SMC_PARAM_ELLS(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS_SHIFT))&SMC_PARAM_ELLS_MASK)
11028 #define SMC_PARAM_ELLS2_MASK 0x20u
11029 #define SMC_PARAM_ELLS2_SHIFT 5u
11030 #define SMC_PARAM_ELLS2_WIDTH 1u
11031 #define SMC_PARAM_ELLS2(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_ELLS2_SHIFT))&SMC_PARAM_ELLS2_MASK)
11032 #define SMC_PARAM_EVLLS0_MASK 0x40u
11033 #define SMC_PARAM_EVLLS0_SHIFT 6u
11034 #define SMC_PARAM_EVLLS0_WIDTH 1u
11035 #define SMC_PARAM_EVLLS0(x) (((uint32_t)(((uint32_t)(x))<<SMC_PARAM_EVLLS0_SHIFT))&SMC_PARAM_EVLLS0_MASK)
11036 /* PMPROT Bit Fields */
11037 #define SMC_PMPROT_AVLP_MASK 0x20u
11038 #define SMC_PMPROT_AVLP_SHIFT 5u
11039 #define SMC_PMPROT_AVLP_WIDTH 1u
11040 #define SMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AVLP_SHIFT))&SMC_PMPROT_AVLP_MASK)
11041 #define SMC_PMPROT_AHSRUN_MASK 0x80u
11042 #define SMC_PMPROT_AHSRUN_SHIFT 7u
11043 #define SMC_PMPROT_AHSRUN_WIDTH 1u
11044 #define SMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMPROT_AHSRUN_SHIFT))&SMC_PMPROT_AHSRUN_MASK)
11045 /* PMCTRL Bit Fields */
11046 #define SMC_PMCTRL_STOPM_MASK 0x7u
11047 #define SMC_PMCTRL_STOPM_SHIFT 0u
11048 #define SMC_PMCTRL_STOPM_WIDTH 3u
11049 #define SMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
11050 #define SMC_PMCTRL_VLPSA_MASK 0x8u
11051 #define SMC_PMCTRL_VLPSA_SHIFT 3u
11052 #define SMC_PMCTRL_VLPSA_WIDTH 1u
11053 #define SMC_PMCTRL_VLPSA(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_VLPSA_SHIFT))&SMC_PMCTRL_VLPSA_MASK)
11054 #define SMC_PMCTRL_RUNM_MASK 0x60u
11055 #define SMC_PMCTRL_RUNM_SHIFT 5u
11056 #define SMC_PMCTRL_RUNM_WIDTH 2u
11057 #define SMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
11058 /* STOPCTRL Bit Fields */
11059 #define SMC_STOPCTRL_STOPO_MASK 0xC0u
11060 #define SMC_STOPCTRL_STOPO_SHIFT 6u
11061 #define SMC_STOPCTRL_STOPO_WIDTH 2u
11062 #define SMC_STOPCTRL_STOPO(x) (((uint32_t)(((uint32_t)(x))<<SMC_STOPCTRL_STOPO_SHIFT))&SMC_STOPCTRL_STOPO_MASK)
11063 /* PMSTAT Bit Fields */
11064 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
11065 #define SMC_PMSTAT_PMSTAT_SHIFT 0u
11066 #define SMC_PMSTAT_PMSTAT_WIDTH 8u
11067 #define SMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
11068  /* end of group SMC_Register_Masks */
11072 
11073  /* end of group SMC_Peripheral_Access_Layer */
11077 
11078 
11079 /* ----------------------------------------------------------------------------
11080  -- TRGMUX Peripheral Access Layer
11081  ---------------------------------------------------------------------------- */
11082 
11090 #define TRGMUX_TRGMUXn_COUNT 26u
11091 
11093 typedef struct {
11094  __IO uint32_t TRGMUXn[TRGMUX_TRGMUXn_COUNT];
11096 
11098 #define TRGMUX_INSTANCE_COUNT (1u)
11099 
11100 
11101 /* TRGMUX - Peripheral instance base addresses */
11103 #define TRGMUX_BASE (0x40063000u)
11104 
11105 #define TRGMUX ((TRGMUX_Type *)TRGMUX_BASE)
11106 
11107 #define TRGMUX_BASE_ADDRS { TRGMUX_BASE }
11108 
11109 #define TRGMUX_BASE_PTRS { TRGMUX }
11110 
11111 /* TRGMUX index offsets */
11112 #define TRGMUX_DMAMUX0_INDEX 0
11113 #define TRGMUX_EXTOUT0_INDEX 1
11114 #define TRGMUX_EXTOUT1_INDEX 2
11115 #define TRGMUX_ADC0_INDEX 3
11116 #define TRGMUX_ADC1_INDEX 4
11117 #define TRGMUX_CMP0_INDEX 7
11118 #define TRGMUX_FTM0_INDEX 10
11119 #define TRGMUX_FTM1_INDEX 11
11120 #define TRGMUX_FTM2_INDEX 12
11121 #define TRGMUX_FTM3_INDEX 13
11122 #define TRGMUX_PDB0_INDEX 14
11123 #define TRGMUX_PDB1_INDEX 15
11124 #define TRGMUX_FLEXIO_INDEX 17
11125 #define TRGMUX_LPIT0_INDEX 18
11126 #define TRGMUX_LPUART0_INDEX 19
11127 #define TRGMUX_LPUART1_INDEX 20
11128 #define TRGMUX_LPI2C0_INDEX 21
11129 #define TRGMUX_LPSPI0_INDEX 23
11130 #define TRGMUX_LPSPI1_INDEX 24
11131 #define TRGMUX_LPTMR0_INDEX 25
11132 
11133 /* ----------------------------------------------------------------------------
11134  -- TRGMUX Register Masks
11135  ---------------------------------------------------------------------------- */
11136 
11142 /* TRGMUXn Bit Fields */
11143 #define TRGMUX_TRGMUXn_SEL0_MASK 0x3Fu
11144 #define TRGMUX_TRGMUXn_SEL0_SHIFT 0u
11145 #define TRGMUX_TRGMUXn_SEL0_WIDTH 6u
11146 #define TRGMUX_TRGMUXn_SEL0(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL0_SHIFT))&TRGMUX_TRGMUXn_SEL0_MASK)
11147 #define TRGMUX_TRGMUXn_SEL1_MASK 0x3F00u
11148 #define TRGMUX_TRGMUXn_SEL1_SHIFT 8u
11149 #define TRGMUX_TRGMUXn_SEL1_WIDTH 6u
11150 #define TRGMUX_TRGMUXn_SEL1(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL1_SHIFT))&TRGMUX_TRGMUXn_SEL1_MASK)
11151 #define TRGMUX_TRGMUXn_SEL2_MASK 0x3F0000u
11152 #define TRGMUX_TRGMUXn_SEL2_SHIFT 16u
11153 #define TRGMUX_TRGMUXn_SEL2_WIDTH 6u
11154 #define TRGMUX_TRGMUXn_SEL2(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL2_SHIFT))&TRGMUX_TRGMUXn_SEL2_MASK)
11155 #define TRGMUX_TRGMUXn_SEL3_MASK 0x3F000000u
11156 #define TRGMUX_TRGMUXn_SEL3_SHIFT 24u
11157 #define TRGMUX_TRGMUXn_SEL3_WIDTH 6u
11158 #define TRGMUX_TRGMUXn_SEL3(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_SEL3_SHIFT))&TRGMUX_TRGMUXn_SEL3_MASK)
11159 #define TRGMUX_TRGMUXn_LK_MASK 0x80000000u
11160 #define TRGMUX_TRGMUXn_LK_SHIFT 31u
11161 #define TRGMUX_TRGMUXn_LK_WIDTH 1u
11162 #define TRGMUX_TRGMUXn_LK(x) (((uint32_t)(((uint32_t)(x))<<TRGMUX_TRGMUXn_LK_SHIFT))&TRGMUX_TRGMUXn_LK_MASK)
11163  /* end of group TRGMUX_Register_Masks */
11167 
11168  /* end of group TRGMUX_Peripheral_Access_Layer */
11172 
11173 
11174 /* ----------------------------------------------------------------------------
11175  -- WDOG Peripheral Access Layer
11176  ---------------------------------------------------------------------------- */
11177 
11187 typedef struct {
11188  __IO uint32_t CS;
11189  __IO uint32_t CNT;
11190  __IO uint32_t TOVAL;
11191  __IO uint32_t WIN;
11193 
11195 #define WDOG_INSTANCE_COUNT (1u)
11196 
11197 
11198 /* WDOG - Peripheral instance base addresses */
11200 #define WDOG_BASE (0x40052000u)
11201 
11202 #define WDOG ((WDOG_Type *)WDOG_BASE)
11203 
11204 #define WDOG_BASE_ADDRS { WDOG_BASE }
11205 
11206 #define WDOG_BASE_PTRS { WDOG }
11207 
11208 #define WDOG_IRQS_ARR_COUNT (1u)
11209 
11210 #define WDOG_IRQS_CH_COUNT (1u)
11211 
11212 #define WDOG_IRQS { WDOG_EWM_IRQn }
11213 
11214 /* ----------------------------------------------------------------------------
11215  -- WDOG Register Masks
11216  ---------------------------------------------------------------------------- */
11217 
11223 /* CS Bit Fields */
11224 #define WDOG_CS_STOP_MASK 0x1u
11225 #define WDOG_CS_STOP_SHIFT 0u
11226 #define WDOG_CS_STOP_WIDTH 1u
11227 #define WDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_STOP_SHIFT))&WDOG_CS_STOP_MASK)
11228 #define WDOG_CS_WAIT_MASK 0x2u
11229 #define WDOG_CS_WAIT_SHIFT 1u
11230 #define WDOG_CS_WAIT_WIDTH 1u
11231 #define WDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WAIT_SHIFT))&WDOG_CS_WAIT_MASK)
11232 #define WDOG_CS_DBG_MASK 0x4u
11233 #define WDOG_CS_DBG_SHIFT 2u
11234 #define WDOG_CS_DBG_WIDTH 1u
11235 #define WDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_DBG_SHIFT))&WDOG_CS_DBG_MASK)
11236 #define WDOG_CS_TST_MASK 0x18u
11237 #define WDOG_CS_TST_SHIFT 3u
11238 #define WDOG_CS_TST_WIDTH 2u
11239 #define WDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_TST_SHIFT))&WDOG_CS_TST_MASK)
11240 #define WDOG_CS_UPDATE_MASK 0x20u
11241 #define WDOG_CS_UPDATE_SHIFT 5u
11242 #define WDOG_CS_UPDATE_WIDTH 1u
11243 #define WDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_UPDATE_SHIFT))&WDOG_CS_UPDATE_MASK)
11244 #define WDOG_CS_INT_MASK 0x40u
11245 #define WDOG_CS_INT_SHIFT 6u
11246 #define WDOG_CS_INT_WIDTH 1u
11247 #define WDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_INT_SHIFT))&WDOG_CS_INT_MASK)
11248 #define WDOG_CS_EN_MASK 0x80u
11249 #define WDOG_CS_EN_SHIFT 7u
11250 #define WDOG_CS_EN_WIDTH 1u
11251 #define WDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_EN_SHIFT))&WDOG_CS_EN_MASK)
11252 #define WDOG_CS_CLK_MASK 0x300u
11253 #define WDOG_CS_CLK_SHIFT 8u
11254 #define WDOG_CS_CLK_WIDTH 2u
11255 #define WDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CLK_SHIFT))&WDOG_CS_CLK_MASK)
11256 #define WDOG_CS_RCS_MASK 0x400u
11257 #define WDOG_CS_RCS_SHIFT 10u
11258 #define WDOG_CS_RCS_WIDTH 1u
11259 #define WDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_RCS_SHIFT))&WDOG_CS_RCS_MASK)
11260 #define WDOG_CS_ULK_MASK 0x800u
11261 #define WDOG_CS_ULK_SHIFT 11u
11262 #define WDOG_CS_ULK_WIDTH 1u
11263 #define WDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_ULK_SHIFT))&WDOG_CS_ULK_MASK)
11264 #define WDOG_CS_PRES_MASK 0x1000u
11265 #define WDOG_CS_PRES_SHIFT 12u
11266 #define WDOG_CS_PRES_WIDTH 1u
11267 #define WDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_PRES_SHIFT))&WDOG_CS_PRES_MASK)
11268 #define WDOG_CS_CMD32EN_MASK 0x2000u
11269 #define WDOG_CS_CMD32EN_SHIFT 13u
11270 #define WDOG_CS_CMD32EN_WIDTH 1u
11271 #define WDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_CMD32EN_SHIFT))&WDOG_CS_CMD32EN_MASK)
11272 #define WDOG_CS_FLG_MASK 0x4000u
11273 #define WDOG_CS_FLG_SHIFT 14u
11274 #define WDOG_CS_FLG_WIDTH 1u
11275 #define WDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_FLG_SHIFT))&WDOG_CS_FLG_MASK)
11276 #define WDOG_CS_WIN_MASK 0x8000u
11277 #define WDOG_CS_WIN_SHIFT 15u
11278 #define WDOG_CS_WIN_WIDTH 1u
11279 #define WDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CS_WIN_SHIFT))&WDOG_CS_WIN_MASK)
11280 /* CNT Bit Fields */
11281 #define WDOG_CNT_CNTLOW_MASK 0xFFu
11282 #define WDOG_CNT_CNTLOW_SHIFT 0u
11283 #define WDOG_CNT_CNTLOW_WIDTH 8u
11284 #define WDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTLOW_SHIFT))&WDOG_CNT_CNTLOW_MASK)
11285 #define WDOG_CNT_CNTHIGH_MASK 0xFF00u
11286 #define WDOG_CNT_CNTHIGH_SHIFT 8u
11287 #define WDOG_CNT_CNTHIGH_WIDTH 8u
11288 #define WDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_CNT_CNTHIGH_SHIFT))&WDOG_CNT_CNTHIGH_MASK)
11289 /* TOVAL Bit Fields */
11290 #define WDOG_TOVAL_TOVALLOW_MASK 0xFFu
11291 #define WDOG_TOVAL_TOVALLOW_SHIFT 0u
11292 #define WDOG_TOVAL_TOVALLOW_WIDTH 8u
11293 #define WDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALLOW_SHIFT))&WDOG_TOVAL_TOVALLOW_MASK)
11294 #define WDOG_TOVAL_TOVALHIGH_MASK 0xFF00u
11295 #define WDOG_TOVAL_TOVALHIGH_SHIFT 8u
11296 #define WDOG_TOVAL_TOVALHIGH_WIDTH 8u
11297 #define WDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_TOVAL_TOVALHIGH_SHIFT))&WDOG_TOVAL_TOVALHIGH_MASK)
11298 /* WIN Bit Fields */
11299 #define WDOG_WIN_WINLOW_MASK 0xFFu
11300 #define WDOG_WIN_WINLOW_SHIFT 0u
11301 #define WDOG_WIN_WINLOW_WIDTH 8u
11302 #define WDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINLOW_SHIFT))&WDOG_WIN_WINLOW_MASK)
11303 #define WDOG_WIN_WINHIGH_MASK 0xFF00u
11304 #define WDOG_WIN_WINHIGH_SHIFT 8u
11305 #define WDOG_WIN_WINHIGH_WIDTH 8u
11306 #define WDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x))<<WDOG_WIN_WINHIGH_SHIFT))&WDOG_WIN_WINHIGH_MASK)
11307  /* end of group WDOG_Register_Masks */
11311 
11312  /* end of group WDOG_Peripheral_Access_Layer */
11316 
11317  /* end of group Peripheral_access_layer_S32K142 */
11321 
11322 
11323 /* ----------------------------------------------------------------------------
11324  -- Backward Compatibility for S32K142
11325  ---------------------------------------------------------------------------- */
11326 
11332 /* No backward compatibility issues. */
11333  /* end of group Backward_Compatibility_Symbols_S32K142 */
11337 
11338 
11339 #else /* #if !defined(S32K142_H_) */
11340  /* There is already included the same memory map. Check if it is compatible (has the same major version) */
11341  #if (MCU_MEM_MAP_VERSION != 0x0200u)
11342  #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
11343  #warning There are included two not compatible versions of memory maps. Please check possible differences.
11344  #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
11345  #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
11346 #endif /* #if !defined(S32K142_H_) */
11347 
11348 /* S32K142.h, eof. */
__IO uint32_t CnSC
Definition: S32K142.h:3902
#define FTM_CV_MIRROR_COUNT
Definition: S32K142.h:3894
__IO uint32_t SYNCONF
Definition: S32K142.h:3921
__O uint32_t GPCHR
Definition: S32K142.h:8477
__IO uint32_t MCFGR2
Definition: S32K142.h:5274
__IO uint32_t FILTER
Definition: S32K142.h:3916
__I uint32_t PARAM
Definition: S32K142.h:3388
__IO uint32_t WORD1
Definition: S32K142.h:3095
__IO uint32_t MISCTRL0
Definition: S32K142.h:10640
__IO uint32_t SETTEN
Definition: S32K142.h:5890
__I uint32_t FDCRC
Definition: S32K142.h:900
__I uint32_t EAR
Definition: S32K142.h:3178
__IO uint16_t ELINKYES
Definition: S32K142.h:2200
__IO uint32_t XOFS
Definition: S32K142.h:338
__IO uint32_t DFCR
Definition: S32K142.h:8482
__IO uint16_t H
Definition: S32K142.h:1924
__IO uint32_t LPOCLKS
Definition: S32K142.h:10636
__I uint32_t CP0COUNT
Definition: S32K142.h:7775
__IO uint32_t CNT
Definition: S32K142.h:11189
struct RTC_Type * RTC_MemMapPtr
__I uint32_t PMSTAT
Definition: S32K142.h:10980
__IO uint32_t BAUD
Definition: S32K142.h:6604
__IO uint32_t TAR
Definition: S32K142.h:8910
struct PORT_Type * PORT_MemMapPtr
__IO uint32_t EIMCR
Definition: S32K142.h:3090
__I uint32_t SDID
Definition: S32K142.h:10641
struct DMAMUX_Type * DMAMUX_MemMapPtr
__IO uint32_t PIDR
Definition: S32K142.h:4954
#define FTM_CONTROLS_COUNT
Definition: S32K142.h:3893
__IO uint32_t FTMOPT1
Definition: S32K142.h:10639
__O uint32_t PTOR
Definition: S32K142.h:4951
__IO uint32_t IER
Definition: S32K142.h:8915
__I uint32_t PARAM
Definition: S32K142.h:10976
__I uint32_t RSR
Definition: S32K142.h:6125
__I uint32_t CPxCFG0
Definition: S32K142.h:7768
#define FLEXIO_TIMCFG_COUNT
Definition: S32K142.h:3382
__IO uint32_t SHIFTSTAT
Definition: S32K142.h:3391
__IO uint32_t CFG1
Definition: S32K142.h:329
__I uint32_t CNT
Definition: S32K142.h:8166
__IO uint32_t MODIR
Definition: S32K142.h:6609
__IO uint32_t USR_OFS
Definition: S32K142.h:337
__IO uint32_t CLPS
Definition: S32K142.h:342
struct LPUART_Type * LPUART_MemMapPtr
__IO uint32_t PINCFG
Definition: S32K142.h:6603
__IO uint32_t CnV
Definition: S32K142.h:3903
__IO uint32_t SHPR1
Definition: S32K142.h:9694
__IO uint32_t LMDR2
Definition: S32K142.h:7136
__IO uint32_t SADDR
Definition: S32K142.h:2187
__IO uint32_t ISCR
Definition: S32K142.h:7129
__I uint32_t VERID
Definition: S32K142.h:5885
__IO uint32_t CPO
Definition: S32K142.h:7133
#define EIM_EICHDn_COUNT
Definition: S32K142.h:3086
__O uint8_t SSRT
Definition: S32K142.h:2172
__IO uint32_t MOD
Definition: S32K142.h:8165
__I uint32_t CP0CFG2
Definition: S32K142.h:7778
__IO uint32_t COMBINE
Definition: S32K142.h:3911
__IO uint8_t FERSTAT
Definition: S32K142.h:3700
__IO uint32_t PL2_PLMASK_LO
Definition: S32K142.h:888
__I uint32_t PARAM
Definition: S32K142.h:8628
__IO uint32_t AFSR
Definition: S32K142.h:9703
__I uint32_t EAR
Definition: S32K142.h:7467
#define S32_NVIC_ICER_COUNT
Definition: S32K142.h:9085
#define FLEXIO_SHIFTCFG_COUNT
Definition: S32K142.h:3376
#define PORT_PCR_COUNT
Definition: S32K142.h:8471
__IO uint32_t PMCTRL
Definition: S32K142.h:10978
#define __IO
Definition: S32K142.h:132
__O uint8_t CEEI
Definition: S32K142.h:2167
__IO uint32_t RXMGMASK
Definition: S32K142.h:859
__I uint32_t HRS
Definition: S32K142.h:2180
__IO uint32_t PCCRMR
Definition: S32K142.h:5061
struct TRGMUX_Type * TRGMUX_MemMapPtr
__IO uint32_t SRIE
Definition: S32K142.h:8633
__IO uint32_t SCR
Definition: S32K142.h:5289
__IO uint32_t CFGR0
Definition: S32K142.h:6112
__IO uint32_t PWMLOAD
Definition: S32K142.h:3924
__IO uint32_t CLP2_OFS
Definition: S32K142.h:351
__IO uint32_t DFER
Definition: S32K142.h:8481
__IO uint32_t CFSR
Definition: S32K142.h:9698
__IO uint32_t MCR
Definition: S32K142.h:5268
__IO uint32_t WU_MTC
Definition: S32K142.h:882
__IO uint32_t MCFGR3
Definition: S32K142.h:5275
__IO uint32_t TPR
Definition: S32K142.h:8909
__IO uint32_t CTRL
Definition: S32K142.h:3389
#define S32_NVIC_ISER_COUNT
Definition: S32K142.h:9084
__IO uint8_t FERCNFG
Definition: S32K142.h:3701
__IO uint32_t MOD
Definition: S32K142.h:3900
struct CAN_Type * CAN_MemMapPtr
struct DMA_Type * DMA_MemMapPtr
__IO uint32_t MFCR
Definition: S32K142.h:5283
__IO uint16_t ATTR
Definition: S32K142.h:2189
__IO uint32_t FLT_ID2_IDMASK
Definition: S32K142.h:887
__I uint32_t SASR
Definition: S32K142.h:5299
__IO uint32_t MDER
Definition: S32K142.h:5271
__I uint32_t CP0CFG0
Definition: S32K142.h:7776
__IO uint32_t SIER
Definition: S32K142.h:5291
__I uint32_t CP0CFG1
Definition: S32K142.h:7777
__IO uint16_t CSR
Definition: S32K142.h:2203
struct LPTMR_Type * LPTMR_MemMapPtr
struct ADC_Type * ADC_MemMapPtr
__IO uint32_t RX14MASK
Definition: S32K142.h:860
__IO uint32_t SSRS
Definition: S32K142.h:8632
__IO uint32_t FPDSCR
Definition: S32K142.h:9709
__IO uint32_t FIRCCFG
Definition: S32K142.h:10308
__IO uint32_t FCFG1
Definition: S32K142.h:10645
#define FTFC_FPROT_COUNT
Definition: S32K142.h:3684
struct LMEM_Type * LMEM_MemMapPtr
__IO uint32_t FDCTRL
Definition: S32K142.h:898
__I uint32_t PIN
Definition: S32K142.h:3390
__IO uint8_t DATA_8LL
Definition: S32K142.h:2066
__IO uint32_t FLTCTRL
Definition: S32K142.h:3917
__I uint16_t PLASC
Definition: S32K142.h:7126
struct FTM_Type * FTM_MemMapPtr
__IO uint32_t PCCSAR
Definition: S32K142.h:5058
__IO uint32_t CS
Definition: S32K142.h:11188
__IO uint32_t MPRA
Definition: S32K142.h:626
__I uint32_t LMFDLR
Definition: S32K142.h:7146
__IO uint32_t SHCSR
Definition: S32K142.h:9697
__I uint32_t PARAM
Definition: S32K142.h:6106
__IO uint32_t MIER
Definition: S32K142.h:5270
__IO uint32_t C1
Definition: S32K142.h:8169
__IO uint32_t RCCR
Definition: S32K142.h:10293
struct LPSPI_Type * LPSPI_MemMapPtr
#define PDB_POnDLY_COUNT
Definition: S32K142.h:8160
__IO uint32_t BFAR
Definition: S32K142.h:9702
__IO uint32_t CR
Definition: S32K142.h:6108
__IO uint32_t CR
Definition: S32K142.h:8912
__I uint32_t CSR
Definition: S32K142.h:10292
__IO uint32_t CTRL1
Definition: S32K142.h:856
__IO uint32_t CLP9
Definition: S32K142.h:348
#define FLEXIO_SHIFTBUFBYS_COUNT
Definition: S32K142.h:3379
__IO uint32_t LMPEIR
Definition: S32K142.h:7140
__IO uint32_t TVAL
Definition: S32K142.h:5894
__O uint8_t CERR
Definition: S32K142.h:2173
__I uint32_t VERID
Definition: S32K142.h:10975
struct SIM_Type * SIM_MemMapPtr
__IO uint32_t SLAST
Definition: S32K142.h:2195
__O uint8_t SEEI
Definition: S32K142.h:2168
__I uint16_t PLAMC
Definition: S32K142.h:7127
__IO uint32_t C1
Definition: S32K142.h:1671
__IO uint32_t CLP0_OFS
Definition: S32K142.h:353
__IO uint32_t CLPS_OFS
Definition: S32K142.h:349
#define FLEXIO_SHIFTBUFBIS_COUNT
Definition: S32K142.h:3378
__IO uint32_t SC3
Definition: S32K142.h:334
struct EIM_Type * EIM_MemMapPtr
struct PMC_Type * PMC_MemMapPtr
__IO uint32_t SIRCCSR
Definition: S32K142.h:10302
__IO uint32_t BASE_OFS
Definition: S32K142.h:335
__IO uint32_t CR
Definition: S32K142.h:2161
__IO uint32_t CCR
Definition: S32K142.h:9693
__IO uint32_t G
Definition: S32K142.h:340
__IO uint32_t POEN
Definition: S32K142.h:8174
__IO uint32_t IFLAG1
Definition: S32K142.h:867
#define S32_NVIC_IP_COUNT
Definition: S32K142.h:9089
__IO uint32_t HCR
Definition: S32K142.h:3925
__IO uint16_t ELINKNO
Definition: S32K142.h:2199
__IO uint32_t RPC
Definition: S32K142.h:8630
__IO uint32_t MCCR0
Definition: S32K142.h:5279
#define ADC_R_COUNT
Definition: S32K142.h:323
__IO uint8_t DATA_8HU
Definition: S32K142.h:2069
__IO uint32_t MCR
Definition: S32K142.h:855
#define ERM_EARn_COUNT
Definition: S32K142.h:3169
__I uint32_t CPxMASTER
Definition: S32K142.h:7766
__IO uint32_t WORD0
Definition: S32K142.h:7476
__IO uint32_t PCCCVR
Definition: S32K142.h:5059
__IO uint32_t CSR
Definition: S32K142.h:6484
__I uint32_t MFSR
Definition: S32K142.h:5284
__IO uint32_t CLP1_OFS
Definition: S32K142.h:352
#define MSCM_OCMDR_COUNT
Definition: S32K142.h:7760
__IO uint32_t SIRCDIV
Definition: S32K142.h:10303
struct WDOG_Type * WDOG_MemMapPtr
__IO uint32_t CPCR
Definition: S32K142.h:7128
__IO uint32_t DMR0
Definition: S32K142.h:6115
__IO uint32_t CFG2
Definition: S32K142.h:330
__I uint32_t CVAL
Definition: S32K142.h:5895
struct MPU_Type * MPU_MemMapPtr
__I uint8_t FCSESTAT
Definition: S32K142.h:3698
__IO uint32_t CR0
Definition: S32K142.h:3173
#define LPIT_TMR_COUNT
Definition: S32K142.h:5881
__I uint32_t CPxCFG2
Definition: S32K142.h:7770
__I uint32_t LMFAR
Definition: S32K142.h:7142
__IO uint32_t LR
Definition: S32K142.h:8914
__IO uint32_t CCR
Definition: S32K142.h:6118
__IO uint32_t PAIR1DEADTIME
Definition: S32K142.h:3928
#define DMA_TCD_COUNT
Definition: S32K142.h:2157
__I uint32_t WMBn_CS
Definition: S32K142.h:892
__IO uint32_t DATA_32
Definition: S32K142.h:2064
__IO uint32_t VCCR
Definition: S32K142.h:10294
__IO uint32_t FIRCCSR
Definition: S32K142.h:10306
__I uint32_t UIDL
Definition: S32K142.h:10650
__IO uint32_t LMPECR
Definition: S32K142.h:7138
__IO uint32_t ISFR
Definition: S32K142.h:8479
__IO uint32_t OFS
Definition: S32K142.h:336
__I uint32_t VERID
Definition: S32K142.h:8627
__IO uint8_t FDPROT
Definition: S32K142.h:3696
__IO uint32_t ICSR
Definition: S32K142.h:9689
__IO uint32_t SWOCTRL
Definition: S32K142.h:3923
__IO uint32_t MODE
Definition: S32K142.h:3907
__IO uint32_t SDER
Definition: S32K142.h:5292
__IO uint32_t PMPROT
Definition: S32K142.h:10977
__IO uint32_t CBT
Definition: S32K142.h:874
__IO uint32_t PODLY
Definition: S32K142.h:8176
__IO uint32_t SHPR3
Definition: S32K142.h:9696
__I uint32_t CPUID
Definition: S32K142.h:9688
struct MSCM_Type * MSCM_MemMapPtr
__I uint32_t WMBn_D03
Definition: S32K142.h:894
#define S32_NVIC_ISPR_COUNT
Definition: S32K142.h:9086
__IO uint32_t EXTTRIG
Definition: S32K142.h:3913
struct PDB_Type * PDB_MemMapPtr
__IO uint32_t CLP3
Definition: S32K142.h:343
__I uint32_t CPxCFG3
Definition: S32K142.h:7771
__IO uint32_t CNTIN
Definition: S32K142.h:3905
__IO uint32_t STATUS
Definition: S32K142.h:3906
__I uint32_t ES
Definition: S32K142.h:2162
__IO uint32_t CTRL2
Definition: S32K142.h:868
__IO uint32_t CLP0
Definition: S32K142.h:346
#define TRGMUX_TRGMUXn_COUNT
Definition: S32K142.h:11090
__IO uint8_t HL
Definition: S32K142.h:1929
__O uint32_t STIR
Definition: S32K142.h:9105
#define CAN_WMB_COUNT
Definition: S32K142.h:851
__IO uint32_t CNR
Definition: S32K142.h:6487
__IO uint8_t FSTAT
Definition: S32K142.h:3688
__IO uint32_t FLTPOL
Definition: S32K142.h:3920
__IO uint32_t SR
Definition: S32K142.h:8913
__IO uint32_t DFWR
Definition: S32K142.h:8483
__IO uint32_t STAR
Definition: S32K142.h:5300
__IO uint32_t INVCTRL
Definition: S32K142.h:3922
__IO uint32_t STAT
Definition: S32K142.h:6605
__IO uint32_t CLP2
Definition: S32K142.h:344
__IO uint32_t EEI
Definition: S32K142.h:2166
__I uint32_t LMFATR
Definition: S32K142.h:7143
__IO uint32_t MISCTRL1
Definition: S32K142.h:10653
__IO uint32_t TSR
Definition: S32K142.h:8908
__IO uint32_t FLT_DLC
Definition: S32K142.h:884
__IO uint16_t L
Definition: S32K142.h:1923
__IO uint32_t SAMR
Definition: S32K142.h:5297
__IO uint32_t MDMR
Definition: S32K142.h:5277
__IO uint32_t CLP9_OFS
Definition: S32K142.h:355
__IO uint32_t CSR
Definition: S32K142.h:10189
__IO uint32_t CTRL1_PN
Definition: S32K142.h:880
__IO uint32_t PDOR
Definition: S32K142.h:4948
__IO uint32_t WORD1
Definition: S32K142.h:7477
#define CAN_RAMn_COUNT
Definition: S32K142.h:849
__IO uint32_t SIRCCFG
Definition: S32K142.h:10304
__IO uint32_t CONF
Definition: S32K142.h:3919
#define FTFC_FCCOB_COUNT
Definition: S32K142.h:3683
struct CRC_Type * CRC_MemMapPtr
__IO uint32_t ERQ
Definition: S32K142.h:2164
#define AIPS_PACR_COUNT
Definition: S32K142.h:621
__IO uint8_t HU
Definition: S32K142.h:1930
__I uint32_t EDR
Definition: S32K142.h:7470
__IO uint32_t IER
Definition: S32K142.h:6110
__IO uint32_t MIER
Definition: S32K142.h:5889
__IO uint32_t MCFGR1
Definition: S32K142.h:5273
__IO uint16_t SOFF
Definition: S32K142.h:2188
__IO uint32_t CHIPCTL
Definition: S32K142.h:10633
__IO uint32_t PL1_HI
Definition: S32K142.h:886
__IO uint32_t TIMER
Definition: S32K142.h:857
__IO uint32_t HCCR
Definition: S32K142.h:10295
__IO uint32_t AIRCR
Definition: S32K142.h:9691
#define MPU_RGDAAC_COUNT
Definition: S32K142.h:7460
__IO uint32_t PCCLCR
Definition: S32K142.h:5057
__IO uint32_t FPCCR
Definition: S32K142.h:9707
struct GPIO_Type * GPIO_MemMapPtr
__IO uint16_t DLY1
Definition: S32K142.h:8179
__IO uint32_t MOD_MIRROR
Definition: S32K142.h:3934
struct S32_NVIC_Type * S32_NVIC_MemMapPtr
__IO uint32_t SSR
Definition: S32K142.h:5290
#define PCC_PCCn_COUNT
Definition: S32K142.h:8054
struct SCG_Type * SCG_MemMapPtr
__IO uint8_t CLKPRESCALER
Definition: S32K142.h:3284
__IO uint8_t FCNFG
Definition: S32K142.h:3689
__O uint8_t CDNE
Definition: S32K142.h:2171
__I uint32_t CP0MASTER
Definition: S32K142.h:7774
__IO uint32_t TCR
Definition: S32K142.h:6122
__IO uint32_t CLP1
Definition: S32K142.h:345
__I uint32_t UIDMH
Definition: S32K142.h:10648
struct ERM_Type * ERM_MemMapPtr
__IO uint32_t ERR
Definition: S32K142.h:2178
struct CMP_Type * CMP_MemMapPtr
__IO uint32_t DATA
Definition: S32K142.h:6607
__IO uint32_t UG
Definition: S32K142.h:341
__IO uint32_t TOVAL
Definition: S32K142.h:11190
__O uint32_t PSOR
Definition: S32K142.h:4949
__IO uint32_t ACTLR
Definition: S32K142.h:9686
__IO uint32_t SPLLDIV
Definition: S32K142.h:10311
__IO uint32_t CTRL
Definition: S32K142.h:6606
__IO uint32_t SOSCCSR
Definition: S32K142.h:10298
__IO uint32_t DADDR
Definition: S32K142.h:2196
__IO uint32_t FPCAR
Definition: S32K142.h:9708
__IO uint32_t CTRL
Definition: S32K142.h:1934
__IO uint32_t FLT_ID1
Definition: S32K142.h:883
#define MPU_RGD_COUNT
Definition: S32K142.h:7459
#define S32_NVIC_ICPR_COUNT
Definition: S32K142.h:9087
__IO uint32_t DMR1
Definition: S32K142.h:6116
__O uint8_t SERQ
Definition: S32K142.h:2170
__IO uint32_t SHIFTEIEN
Definition: S32K142.h:3396
__IO uint32_t MCR
Definition: S32K142.h:5887
__IO uint32_t PSR
Definition: S32K142.h:6485
#define DMAMUX_CHCFG_COUNT
Definition: S32K142.h:3021
#define FLEXIO_SHIFTBUF_COUNT
Definition: S32K142.h:3377
__I uint32_t PARAM
Definition: S32K142.h:6601
__IO uint16_t DLY2
Definition: S32K142.h:8178
__IO uint32_t PAIR3DEADTIME
Definition: S32K142.h:3932
__IO uint8_t REGSC
Definition: S32K142.h:8359
__O uint8_t CERQ
Definition: S32K142.h:2169
__IO uint32_t CLPX_OFS
Definition: S32K142.h:354
__IO uint32_t HFSR
Definition: S32K142.h:9699
__IO uint32_t SCFGR2
Definition: S32K142.h:5295
__IO uint8_t LU
Definition: S32K142.h:1928
__IO uint32_t EICHEN
Definition: S32K142.h:3091
__IO uint32_t CLKOUTCNFG
Definition: S32K142.h:10296
__IO uint32_t SC2
Definition: S32K142.h:333
__IO uint32_t SR
Definition: S32K142.h:6109
__O uint8_t CINT
Definition: S32K142.h:2174
struct LPIT_Type * LPIT_MemMapPtr
__I uint8_t FOPT
Definition: S32K142.h:3691
__IO uint32_t DFSR
Definition: S32K142.h:9700
__I uint32_t SRS
Definition: S32K142.h:8629
__IO uint32_t PID
Definition: S32K142.h:7131
__I uint32_t VERID
Definition: S32K142.h:10289
__IO uint32_t CLKDIV4
Definition: S32K142.h:10652
__IO uint32_t SHPR2
Definition: S32K142.h:9695
__IO uint32_t MCCR1
Definition: S32K142.h:5281
struct MCM_Type * MCM_MemMapPtr
__IO uint16_t DOFF
Definition: S32K142.h:2197
__I uint8_t FSEC
Definition: S32K142.h:3690
__IO uint32_t CLP3_OFS
Definition: S32K142.h:350
__IO uint32_t SPLLCFG
Definition: S32K142.h:10312
__IO uint32_t CLRTEN
Definition: S32K142.h:5891
__I uint32_t CPxCOUNT
Definition: S32K142.h:7767
__IO uint32_t CLPX
Definition: S32K142.h:347
__I uint32_t MRDR
Definition: S32K142.h:5287
__I uint32_t CPxCFG1
Definition: S32K142.h:7769
__IO uint32_t CTRL2_PN
Definition: S32K142.h:881
__IO uint8_t DATA_8HL
Definition: S32K142.h:2068
__I uint32_t VERID
Definition: S32K142.h:5265
__IO uint32_t INT
Definition: S32K142.h:2176
__IO uint32_t FCR
Definition: S32K142.h:6120
__IO uint32_t EARS
Definition: S32K142.h:2182
__IO uint32_t CPACR
Definition: S32K142.h:9705
__IO uint32_t FIRCDIV
Definition: S32K142.h:10307
__IO uint32_t MCFGR0
Definition: S32K142.h:5272
__IO uint32_t SYNC
Definition: S32K142.h:3908
#define FLEXIO_SHIFTBUFBBS_COUNT
Definition: S32K142.h:3380
__IO uint32_t FDCBT
Definition: S32K142.h:899
struct EWM_Type * EWM_MemMapPtr
__I uint32_t WMBn_D47
Definition: S32K142.h:895
__IO uint8_t LVDSC1
Definition: S32K142.h:8357
#define FLEXIO_TIMCTL_COUNT
Definition: S32K142.h:3381
__IO uint32_t MTDR
Definition: S32K142.h:5285
struct SMC_Type * SMC_MemMapPtr
__O uint32_t GPCLR
Definition: S32K142.h:8476
__IO uint32_t PLATCGC
Definition: S32K142.h:10643
#define FLEXIO_SHIFTCTL_COUNT
Definition: S32K142.h:3375
__I uint32_t PARAM
Definition: S32K142.h:5266
__IO uint32_t DATA
Definition: S32K142.h:1921
__IO uint32_t CMR
Definition: S32K142.h:6486
struct LPI2C_Type * LPI2C_MemMapPtr
__IO uint32_t MSR
Definition: S32K142.h:5888
__IO uint32_t IMASK1
Definition: S32K142.h:865
__IO uint32_t SHIFTSIEN
Definition: S32K142.h:3395
__I uint32_t CP0NUM
Definition: S32K142.h:7773
__I uint32_t PARAM
Definition: S32K142.h:10290
__IO uint32_t FMS
Definition: S32K142.h:3915
#define CAN_RXIMR_COUNT
Definition: S32K142.h:850
__IO uint32_t FIFO
Definition: S32K142.h:6610
__IO uint32_t DEADTIME
Definition: S32K142.h:3912
#define MPU_EAR_EDR_COUNT
Definition: S32K142.h:7458
__IO uint32_t SC
Definition: S32K142.h:8164
__I uint32_t CALIB
Definition: S32K142.h:10192
struct AIPS_Type * AIPS_MemMapPtr
__IO uint32_t CNT
Definition: S32K142.h:3899
__IO uint32_t RX15MASK
Definition: S32K142.h:861
__IO uint32_t OUTINIT
Definition: S32K142.h:3909
__IO uint32_t DER
Definition: S32K142.h:6111
__IO uint32_t TCR
Definition: S32K142.h:8911
__IO uint8_t DATA_8LU
Definition: S32K142.h:2067
#define AIPS_OPACR_COUNT
Definition: S32K142.h:622
__IO uint32_t MLOFFNO
Definition: S32K142.h:2192
__IO uint32_t WORD2
Definition: S32K142.h:7478
__I uint32_t VERID
Definition: S32K142.h:6600
__IO uint32_t RVR
Definition: S32K142.h:10190
__IO uint32_t RXFGMASK
Definition: S32K142.h:872
__IO uint8_t CMPL
Definition: S32K142.h:3281
__I uint32_t UIDH
Definition: S32K142.h:10647
__I uint32_t CP0CFG3
Definition: S32K142.h:7779
__O uint32_t TDR
Definition: S32K142.h:6123
#define MCM_LMDR_COUNT
Definition: S32K142.h:7121
__IO uint32_t SPLLCSR
Definition: S32K142.h:10310
struct RCM_Type * RCM_MemMapPtr
__IO uint32_t GPOLY
Definition: S32K142.h:1933
__I uint32_t LMFDHR
Definition: S32K142.h:7145
__IO uint32_t CESR
Definition: S32K142.h:7464
__I uint32_t CPxNUM
Definition: S32K142.h:7765
__IO uint32_t SOSCDIV
Definition: S32K142.h:10299
__IO uint32_t GLOBAL
Definition: S32K142.h:6602
__IO uint32_t SHIFTERR
Definition: S32K142.h:3392
__I uint32_t CP0TYPE
Definition: S32K142.h:7772
struct S32_SCB_Type * S32_SCB_MemMapPtr
__I uint32_t CPxTYPE
Definition: S32K142.h:7764
__IO uint32_t OUTMASK
Definition: S32K142.h:3910
__IO uint8_t CMPH
Definition: S32K142.h:3282
__I uint32_t PDIR
Definition: S32K142.h:4952
__IO uint32_t MATCH
Definition: S32K142.h:6608
__IO uint32_t C0
Definition: S32K142.h:1670
__O uint8_t SERV
Definition: S32K142.h:3280
struct FLEXIO_Type * FLEXIO_MemMapPtr
__IO uint32_t WATER
Definition: S32K142.h:6611
__IO uint8_t FEPROT
Definition: S32K142.h:3695
__IO uint32_t QDCTRL
Definition: S32K142.h:3918
__IO uint32_t YOFS
Definition: S32K142.h:339
struct CSE_PRAM_Type * CSE_PRAM_MemMapPtr
#define __I
Definition: S32K142.h:129
#define DMA_DCHPRI_COUNT
Definition: S32K142.h:2156
__IO uint8_t LL
Definition: S32K142.h:1927
__I uint32_t ESR2
Definition: S32K142.h:869
__IO uint32_t MMFAR
Definition: S32K142.h:9701
__IO uint32_t S
Definition: S32K142.h:8170
#define ADC_CV_COUNT
Definition: S32K142.h:324
__IO uint32_t MLOFFYES
Definition: S32K142.h:2193
__IO uint32_t C2
Definition: S32K142.h:1672
__IO uint32_t TIMIEN
Definition: S32K142.h:3397
__IO uint32_t ADCOPT
Definition: S32K142.h:10638
__I uint32_t PARAM
Definition: S32K142.h:5886
__I uint32_t RDR
Definition: S32K142.h:6126
__I uint32_t UIDML
Definition: S32K142.h:10649
__O uint32_t PCOR
Definition: S32K142.h:4950
__I uint32_t CRCR
Definition: S32K142.h:871
__IO uint32_t STOPCTRL
Definition: S32K142.h:10979
__IO uint32_t STDR
Definition: S32K142.h:5302
__I uint32_t SRDR
Definition: S32K142.h:5304
__IO uint32_t SCFGR1
Definition: S32K142.h:5294
#define S32_NVIC_IABR_COUNT
Definition: S32K142.h:9088
__IO uint32_t MSR
Definition: S32K142.h:5269
__IO uint32_t SC
Definition: S32K142.h:3898
__I uint32_t FSR
Definition: S32K142.h:6121
__IO uint32_t TIMSTAT
Definition: S32K142.h:3393
__I uint32_t WMBn_ID
Definition: S32K142.h:893
__I uint32_t VERID
Definition: S32K142.h:3387
__IO uint32_t SHIFTSDEN
Definition: S32K142.h:3399
__IO uint32_t MLNO
Definition: S32K142.h:2191
struct FTFC_Type * FTFC_MemMapPtr
__IO uint32_t SR0
Definition: S32K142.h:3175
__IO uint32_t CVR
Definition: S32K142.h:10191
__IO uint32_t PAIR0DEADTIME
Definition: S32K142.h:3926
__IO uint32_t VTOR
Definition: S32K142.h:9690
__IO uint32_t SCR
Definition: S32K142.h:9692
#define ADC_SC1_COUNT
Definition: S32K142.h:322
__IO uint32_t WIN
Definition: S32K142.h:11191
__I uint32_t VERID
Definition: S32K142.h:6105
struct S32_SysTick_Type * S32_SysTick_MemMapPtr
#define PDB_DLY_COUNT
Definition: S32K142.h:8159
__IO uint32_t PDDR
Definition: S32K142.h:4953
struct PCC_Type * PCC_MemMapPtr
#define CSE_PRAM_RAMn_COUNT
Definition: S32K142.h:2059
__IO uint32_t PL2_PLMASK_HI
Definition: S32K142.h:889
__IO uint32_t IDLY
Definition: S32K142.h:8167
__IO uint32_t CFGR1
Definition: S32K142.h:6113
__IO uint32_t WORD3
Definition: S32K142.h:7479
__IO uint32_t SOSCCFG
Definition: S32K142.h:10300
__IO uint32_t ECR
Definition: S32K142.h:862
#define FLEXIO_TIMCMP_COUNT
Definition: S32K142.h:3383
__IO uint32_t POL
Definition: S32K142.h:3914
__IO uint32_t PCCCR
Definition: S32K142.h:5056
__IO uint8_t LPOTRIM
Definition: S32K142.h:8361
__IO uint32_t FTMOPT0
Definition: S32K142.h:10635
__IO uint8_t LVDSC2
Definition: S32K142.h:8358
__IO uint32_t DLASTSGA
Definition: S32K142.h:2202
__I uint32_t RXFIR
Definition: S32K142.h:873
__IO uint8_t CTRL
Definition: S32K142.h:3279
#define PDB_CH_COUNT
Definition: S32K142.h:8158
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K142.h:192
__IO uint32_t TCTRL
Definition: S32K142.h:5896
__IO uint32_t PAIR2DEADTIME
Definition: S32K142.h:3930
#define __O
Definition: S32K142.h:131
__IO uint32_t WORD0
Definition: S32K142.h:3094
__IO uint32_t ESR1
Definition: S32K142.h:863
__IO uint32_t PL1_LO
Definition: S32K142.h:885