S32 SDK
sbc_uja1169_driver.h
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1 /*
2  * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
19 #ifndef SOURCES_SBC_SBC_UJA_1169_H_
20 #define SOURCES_SBC_SBC_UJA_1169_H_
21 
22 #include "UJA1169.h"
23 #include "lpspi_master_driver.h"
24 #include "status.h"
25 
32 /*******************************************************************************
33  * Definitions
34  ******************************************************************************/
35 
36 #define SBC_UJA_TIMEOUT 1000U
40 #define SBC_UJA_COUNT_ID_REG 4U
41 #define SBC_UJA_COUNT_MASK 4U
42 #define SBC_UJA_COUNT_DMASK 8U
43 /*******************************************************************************
44  * Enumerations
45  ******************************************************************************/
46 
52 typedef enum{
53  /* Primary control registers. */
54  SBC_UJA_WTDOG_CTR = 0x00U, /* Watchdog control. */
55  SBC_UJA_MODE = 0x01U, /* Mode control. */
56  SBC_UJA_FAIL_SAFE = 0x02U, /* Fail-safe control. */
57  SBC_UJA_MAIN = 0x03U, /* Main status. */
58  SBC_UJA_SYSTEM_EVNT = 0x04U, /* System event enable. */
59  SBC_UJA_WTDOG_STAT = 0x05U, /* Watchdog status. */
60  SBC_UJA_MEMORY_0 = 0x06U, /* Memory 0. */
61  SBC_UJA_MEMORY_1 = 0x07U, /* Memory 1. */
62  SBC_UJA_MEMORY_2 = 0x08U, /* Memory 2. */
63  SBC_UJA_MEMORY_3 = 0x09U, /* Memory 3. */
64  SBC_UJA_LOCK = 0x0AU, /* Lock control. */
65  /* Regulator control registers. */
66  SBC_UJA_REGULATOR = 0x10U, /* Regulator control. */
67  SBC_UJA_SUPPLY_STAT = 0x1BU, /* Supply status. */
68  SBC_UJA_SUPPLY_EVNT = 0x1CU, /* Supply event enable. */
69  /* Transceiver control and partial networking registers. */
70  SBC_UJA_CAN = 0x20U, /* CAN control. */
71  SBC_UJA_TRANS_STAT = 0x22U, /* Transceiver status. */
72  SBC_UJA_TRANS_EVNT = 0x23U, /* Transceiver event enable. */
73  SBC_UJA_DAT_RATE = 0x26U, /* Data rate. */
74  SBC_UJA_IDENTIF_0 = 0x27U, /* Identifier 0. */
75  SBC_UJA_IDENTIF_1 = 0x28U, /* Identifier 1. */
76  SBC_UJA_IDENTIF_2 = 0x29U, /* Identifier 2. */
77  SBC_UJA_IDENTIF_3 = 0x2AU, /* Identifier 3. */
78  SBC_UJA_MASK_0 = 0x2BU, /* Mask 0. */
79  SBC_UJA_MASK_1 = 0x2CU, /* Mask 1. */
80  SBC_UJA_MASK_2 = 0x2DU, /* Mask 2. */
81  SBC_UJA_MASK_3 = 0x2EU, /* Mask 3. */
82  SBC_UJA_FRAME_CTR = 0x2FU, /* Frame control. */
83  SBC_UJA_DAT_MASK_0 = 0x68U, /* Data mask 0. */
84  SBC_UJA_DAT_MASK_1 = 0x69U, /* Data mask 1. */
85  SBC_UJA_DAT_MASK_2 = 0x6AU, /* Data mask 2. */
86  SBC_UJA_DAT_MASK_3 = 0x6BU, /* Data mask 3. */
87  SBC_UJA_DAT_MASK_4 = 0x6CU, /* Data mask 4. */
88  SBC_UJA_DAT_MASK_5 = 0x6DU, /* Data mask 5. */
89  SBC_UJA_DAT_MASK_6 = 0x6EU, /* Data mask 6. */
90  SBC_UJA_DAT_MASK_7 = 0x6FU, /* Data mask 7. */
91  /* WAKE pin control and status registers. */
92  SBC_UJA_WAKE_STAT = 0x4BU, /* WAKE pin status. */
93  SBC_UJA_WAKE_EN = 0x4CU, /* WAKE pin enable. */
94  /* Event capture registers. */
95  SBC_UJA_GL_EVNT_STAT = 0x60U, /* Global event status. */
96  SBC_UJA_SYS_EVNT_STAT = 0x61U, /* System event status. */
97  SBC_UJA_SUP_EVNT_STAT = 0x62U, /* Supply event status. */
98  SBC_UJA_TRANS_EVNT_STAT = 0x63U, /* Transceiver event status. */
99  SBC_UJA_WAKE_EVNT_STAT = 0x64U, /* WAKE pin event status. */
100  /* MTPNV status register. */
101  SBC_UJA_MTPNV_STAT = 0x70U, /* MTPNV status. */
102  /* Start-up control register. */
103  SBC_UJA_START_UP = 0x73U, /* Start-up control. */
104  /* SBC configuration control. */
105  SBC_UJA_SBC = 0x74U, /* SBC configuration control. */
106  /* CRC control register. */
107  SBC_UJA_MTPNV_CRC = 0x75U, /* MTPNV CRC control. */
108  /* Identification register. */
109  SBC_UJA_IDENTIF = 0x7EU, /* Identification. */
129 typedef enum{
135 
150 typedef enum{
151  SBC_UJA_WTDOG_CTR_NWP_8 = 0x08U,
166 typedef enum{
167  SBC_UJA_MODE_MC_SLEEP = 0x01U,
184 typedef enum{
196 typedef uint8_t sbc_fail_safe_rcc_t;
197 
203 typedef enum{
209 
215 typedef enum{
221 
227 typedef enum{
228  SBC_UJA_MAIN_RSS_OFF_MODE = 0x00U,
246 
252 typedef enum{
258 
264 typedef enum{
270 
276 typedef enum{
282 
288 typedef enum{
294 
300 typedef enum{
308 
318 typedef enum{
336 }sbc_lock_t;
343 typedef enum{
355 
361 typedef enum{
371 
377 typedef enum{
387 
393 typedef enum{
403 
409 typedef enum{
415 
422 typedef enum{
428 
435 typedef enum{
441 
447 typedef enum{
453 
459 typedef enum{
465 
471 typedef enum{
477 
483 typedef enum{
489 
495 typedef enum{
511 typedef enum{
517 
523 typedef enum{
530 
536 typedef enum{
542 
548 typedef enum{
554 
560 typedef enum{
566 
572 typedef enum{
578 
584 typedef enum{
590 
596 typedef enum{
602 
608 typedef enum{
614 
620 typedef enum{
626 
634 typedef enum{
651 typedef uint8_t sbc_identifier_t;
652 
660 typedef uint8_t sbc_identif_mask_t;
661 
669 typedef enum{
675 
681 typedef enum{
687 
694 typedef uint8_t sbc_frame_ctr_dlc_t;
695 
705 typedef uint8_t sbc_data_mask_t;
706 
712 typedef enum{
718 
724 typedef enum{
730 
736 typedef enum{
742 
748 typedef enum{
754 
760 typedef enum{
766 
772 typedef enum{
778 
784 typedef enum{
790 
796 typedef enum{
802 
808 typedef enum{
815 
821 typedef enum{
829 
835 typedef enum{
845 
851 typedef enum{
857 
863 typedef enum{
869 
875 typedef enum{
883 
890 typedef enum{
896 
902 typedef enum{
909 
915 typedef enum{
922 
928 typedef enum{
934 
940 typedef enum{
946 
952 typedef enum{
958 
966 typedef uint8_t sbc_mtpnv_stat_wrcnts_t;
967 
973 typedef enum{
979 
985 typedef enum{
991 
997 typedef enum{
1007 
1013 typedef enum{
1019 
1026 typedef enum{
1036 
1042 typedef enum{
1048 
1055 typedef enum{
1061 
1068 typedef enum{
1074 
1075 /*******************************************************************************
1076  * Variables
1077  ******************************************************************************/
1078 
1085 typedef struct{
1086  sbc_wtdog_ctr_wmc_t modeControl;
1087  sbc_wtdog_ctr_nwp_t nominalPeriod;
1106 typedef struct{
1107  sbc_sbc_v1rtsuc_t v1rtsuc;
1110  sbc_sbc_sdmc_t sdmc;
1113 }sbc_sbc_t;
1122 typedef struct{
1123  sbc_start_up_rlc_t rlc;
1135 typedef struct{
1136  sbc_regulator_pdc_t pdc;
1148 typedef struct{
1149  sbc_supply_evnt_v2oe_t v2oe;
1161 typedef struct{
1162  sbc_sys_evnt_otwe_t owte;
1172 typedef struct{
1173  sbc_can_cfdc_t cfdc;
1179 }sbc_can_ctr_t;
1187 typedef struct{
1188  sbc_trans_evnt_cbse_t cbse;
1200 typedef struct{
1201  sbc_frame_ctr_ide_t ide;
1212 typedef struct{
1213  sbc_can_ctr_t canConf;
1214  sbc_trans_evnt_t canTransEvnt;
1216  sbc_dat_rate_t datRate;
1219  sbc_frame_t frame;
1235 typedef struct{
1236  sbc_wake_en_wpre_t wpre;
1246 typedef struct{
1247  sbc_regulator_t regulator;
1248  sbc_supply_evnt_t supplyEvnt;
1251 
1258 typedef struct{
1259  sbc_regulator_ctr_t regulatorCtr;
1260  sbc_wtdog_ctr_t watchdog;
1263  sbc_sys_evnt_t sysEvnt;
1265  sbc_lock_t lockMask;
1266  sbc_can_conf_t can;
1267  sbc_wake_t wakePin;
1270 
1297 typedef struct{
1298  sbc_start_up_t startUp;
1299  sbc_sbc_t control;
1303 
1313 typedef struct{
1314  sbc_main_otws_t otws;
1327 typedef struct{
1328  sbc_wtdog_stat_fnms_t fnms;
1339 typedef struct{
1340  sbc_supply_stat_v2s_t v2s;
1350 typedef struct{
1351  sbc_trans_stat_cts_t cts;
1371 typedef struct{
1387 typedef struct{
1400 typedef struct{
1411 typedef struct{
1424 typedef struct{
1436 typedef struct{
1437  sbc_gl_evnt_stat_t glEvnt;
1441  sbc_wake_evnt_stat_t wakePinEvnt;
1457 typedef struct{
1458  sbc_mtpnv_stat_wrcnts_t wrcnts;
1463 
1464 
1471 typedef struct{
1472  sbc_main_status_t mainS;
1480 /*******************************************************************************
1481  * API
1482  ******************************************************************************/
1483 
1486 /* Functions for configure registers of SBC. */
1487 
1497 status_t SBC_Init(const sbc_int_config_t *const config, const uint32_t lpspiInstance);
1498 
1507 status_t SBC_SetVreg(const sbc_regulator_ctr_t* const regulatorCtr);
1508 
1518 status_t SBC_GetVreg(sbc_regulator_ctr_t* const regulatorCtr);
1519 
1539 status_t SBC_SetWatchdog(const sbc_wtdog_ctr_t* const wtdog);
1540 
1559 
1581 status_t SBC_SetMode(const sbc_mode_mc_t mode);
1582 
1602 status_t SBC_GetMode(sbc_mode_mc_t* const mode);
1603 
1627  const sbc_fail_safe_rcc_t* const rcc);
1628 
1649  sbc_fail_safe_rcc_t * const rcc);
1650 
1660 status_t SBC_SetSystemEvents(const sbc_sys_evnt_t* const sysEvnt);
1661 
1672 
1685 status_t SBC_SetLock(const sbc_lock_t lockMask);
1686 
1699 status_t SBC_GetLock(sbc_lock_t* const lockMask);
1700 
1712 status_t SBC_SetCanConfig(const sbc_can_conf_t* const can);
1713 
1726 
1741 status_t SBC_SetWakePin(const sbc_wake_t* const wakePin);
1742 
1757 status_t SBC_GetWakePin(sbc_wake_t* const wakePin);
1758 
1759 /* Functions for reading statuses. */
1760 
1768 status_t SBC_GetMainStatus(sbc_main_status_t* const mainStatus);
1769 
1777 status_t SBC_GetWatchdogStatus(sbc_wtdog_status_t* const watchdogStatus);
1778 
1788 
1798 status_t SBC_GetCanStatus(sbc_trans_stat_t* const transStatus);
1799 
1808 
1819 
1833 status_t SBC_CleanEvents(const sbc_evn_capt_t* const events);
1834 
1845 
1861 
1862 /* Factories settings. This function read and write from non-volatile memory */
1863 
1882 
1911 
1926  const uint8_t* const sendData, uint8_t* const receiveData);
1927 
1936 void SBC_FeedWatchdog(void);
1937 
1938 #endif /* SOURCES_SBC_SBC_UJA_1169_H_ */
sbc_wake_en_wpre_t
WAKE pin event capture enable register, WAKE pin rising-edge enable (0x4C).
status_t SBC_SetLock(const sbc_lock_t lockMask)
This function writes to Lock control register (0x0A). Sections of the register address area can be wr...
#define SBC_UJA_TRANS_EVNT_CWE_F(x)
Definition: UJA1169.h:446
Init configuration structure. This structure is used for initialization of sbc.
#define SBC_UJA_COUNT_ID_REG
#define SBC_UJA_TRANS_STAT_CTS_F(x)
Definition: UJA1169.h:373
Main status register structure. The Main status register can be accessed to monitor the status of the...
sbc_fail_safe_lhc_t
Fail-safe control register, LIMP home control (0x02). The dedicated LIMP pin can be used to enable so...
sbc_mode_mc_t
Mode control register, mode control (0x01)
sbc_sys_evnt_otwe_t
System event capture enable, overtemperature warning enable (0x04).
#define SBC_UJA_TRANS_STAT_CBSS_F(x)
Definition: UJA1169.h:401
status_t SBC_GetWakeStatus(sbc_wake_stat_wpvs_t *const wakeStatus)
This functions reads WAKE pin status register. This function reads switching threshold of voltage on ...
#define SBC_UJA_SYS_EVNT_SPIFE_F(x)
Definition: UJA1169.h:148
sbc_trans_evnt_cfe_t
Transceiver event capture enable register, CAN failure enable (0x23).
#define SBC_UJA_COUNT_MASK
sbc_dat_rate_t
Data rate register, CAN data rate selection (0x26). CAN partial networking configuration registers...
#define SBC_UJA_SUP_EVNT_STAT_V2U_F(x)
Definition: UJA1169.h:726
sbc_trans_stat_cbss_t
Transceiver status register, CAN-bus silence status (0x22).
sbc_trans_stat_coscs_t
Transceiver status register, CAN oscillator status (0x22).
status_t SBC_GetFailSafe(sbc_fail_safe_lhc_t *const lhc, sbc_fail_safe_rcc_t *const rcc)
This function reads from Fail-safe control register (0x02). The dedicated LIMP pin can be used to ena...
#define SBC_UJA_FAIL_SAFE_LHC_F(x)
Definition: UJA1169.h:92
#define SBC_UJA_TRANS_STAT_VCS_F(x)
Definition: UJA1169.h:408
#define SBC_UJA_TRANS_EVNT_STAT_CF_F(x)
Definition: UJA1169.h:763
#define SBC_UJA_LOCK_LK6C_MASK
Lock control 6: address area 0x68 to 0x6F macros.
Definition: UJA1169.h:196
status_t SBC_SetCanConfig(const sbc_can_conf_t *const can)
This function configures CAN peripheral behavior. This function configures CAN peripheral behavior...
#define SBC_UJA_TRANS_STAT_CPNERR_F(x)
Definition: UJA1169.h:380
sbc_sys_evnt_stat_po_t
System event status register, power-on (0x61).
#define SBC_UJA_SYS_EVNT_STAT_PO_F(x)
Definition: UJA1169.h:683
#define SBC_UJA_SYS_EVNT_STAT_OTW_F(x)
Definition: UJA1169.h:690
#define SBC_UJA_TRANS_EVNT_CFE_F(x)
Definition: UJA1169.h:439
sbc_regulator_v2c_t
Regulator control register, V2/VEXT configuration (0x10).
sbc_wake_en_wpfe_t
WAKE pin event capture enable register, WAKE pin falling-edge enable (0x4C).
#define SBC_UJA_SUPPLY_EVNT_V1UE_F(x)
Definition: UJA1169.h:322
#define SBC_UJA_WAKE_EVNT_STAT_WPR_F(x)
Definition: UJA1169.h:785
Transceiver status register structure. There are stored CAN transceiver statuses. ...
sbc_main_nms_t
Main status register, normal mode status (0x03).
#define SBC_UJA_LOCK_LK2C_MASK
Lock control 2: address area 0x20 to 0x2F - transceiver control macros.
Definition: UJA1169.h:224
Regulator control register structure. This structure set power distribution control, V2/VEXT configuration, set V1 reset threshold.
Global event status register. The microcontroller can monitor events via the event status registers...
sbc_gl_evnt_stat_trxe_t
Global event status register, transceiver event (0x60).
sbc_sys_evnt_stat_spif_t
System event status register, SPI failure (0x61).
#define SBC_UJA_WAKE_EVNT_STAT_WPF_F(x)
Definition: UJA1169.h:792
sbc_sys_evnt_stat_otw_t
System event status register, overtemperature warning (0x61).
#define SBC_UJA_LOCK_LK1C_MASK
Lock control 1: address area 0x10 to 0x1F - regulator control macros.
Definition: UJA1169.h:231
sbc_supply_stat_v2s_t
Supply voltage status register, V2/VEXT status (0x1B).
Event capture registers structure. This structure contains Global event status, System event status...
#define SBC_UJA_MTPNV_STAT_ECCS_F(x)
Definition: UJA1169.h:813
sbc_regulator_pdc_t
Regulator control register, power distribution control (0x10).
status_t SBC_CleanEvents(const sbc_evn_capt_t *const events)
This function clears Event capture registers. It contains Global event status, System event status...
Factory configuration structure. It contains Start-up control register and SBC configuration control ...
uint8_t sbc_data_mask_t
Data mask registers. The data field indicates the nodes to be woken up. Within the data field...
status_t SBC_GetAllStatus(sbc_status_group_t *const status)
This function reads all statuses from SBC device. It reads all status registers: Main status and Watc...
status_t SBC_GetFactoriesSettings(sbc_factories_conf_t *const factoriesConf)
This function reads Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode.
#define SBC_UJA_TRANS_EVNT_STAT_CBS_F(x)
Definition: UJA1169.h:756
Supply voltage status register structure. V2/VEXT and V1 undervoltage and overvoltage status...
sbc_gl_evnt_stat_wpe_t
Global event status register, WAKE pin event (0x60).
status_t SBC_SetSystemEvents(const sbc_sys_evnt_t *const sysEvnt)
This function writes System event capture enable register (0x04). This function enables or disables o...
status_t SBC_SetWatchdog(const sbc_wtdog_ctr_t *const wtdog)
This function configures Watchdog control register (0x00).
status_t SBC_ChangeFactoriesSettings(const sbc_factories_conf_t *const newConf)
This function sets Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode. Note for default settings see sbc_factories_conf_t comment. If the device has been programmed previously, the factory presets may need to be restored before reprogramming can begin. When the factory presets have been restored successfully, a system reset is generated automatically and UJA1169 switches back to Forced Normal mode. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: -pin RSTN is held LOW -CANH is pulled up to VBAT -CANL is pulled down to GND.
sbc_supply_evnt_v1ue_t
Supply event capture enable register, V1 undervoltage enable (0x1C).
#define SBC_UJA_GL_EVNT_STAT_WPE_F(x)
Definition: UJA1169.h:647
Watchdog control register structure. Watchdog configuration structure.
#define SBC_UJA_GL_EVNT_STAT_SYSE_F(x)
Definition: UJA1169.h:668
#define SBC_UJA_SBC_SLPC_F(x)
Definition: UJA1169.h:880
#define SBC_UJA_SUPPLY_STAT_V2S_F(x)
Definition: UJA1169.h:285
uint8_t sbc_mtpnv_stat_wrcnts_t
MTPNV status register, write counter status (0x70). 6-bits - contains the number of times the MTPNV c...
sbc_frame_ctr_pndm_t
Frame control register, partial networking data mask (0x2F).
#define SBC_UJA_SUPPLY_EVNT_V2UE_F(x)
Definition: UJA1169.h:315
#define SBC_UJA_LOCK_LK3C_MASK
Lock control 3: address area 0x30 to 0x3F - unused register range macros.
Definition: UJA1169.h:217
sbc_sup_evnt_stat_v1u_t
Supply event status register, V1 undervoltage (0x62).
#define SBC_UJA_MAIN_OTWS_F(x)
Definition: UJA1169.h:113
status_t SBC_GetMode(sbc_mode_mc_t *const mode)
This function reads Mode control register. (0x01).
uint8_t sbc_identif_mask_t
ID mask registers (0x2B to 0x2E). The identifier mask is defined in the ID mask registers, where a 1 means dont care.
sbc_trans_stat_cfs_t
Transceiver status register, CAN failure status (0x22).
status_t SBC_GetEventsStatus(sbc_evn_capt_t *const events)
This functions reads Event capture registers. This function reads switching threshold of voltage on W...
sbc_trans_evnt_cwe_t
Transceiver event capture enable register, CAN wake-up enable (0x23).
#define SBC_UJA_WTDOG_STAT_SDMS_F(x)
Definition: UJA1169.h:169
#define SBC_UJA_LOCK_LK4C_MASK
Lock control 4: address area 0x40 to 0x4F - WAKE pin control macros.
Definition: UJA1169.h:210
sbc_trans_stat_cpns_t
Transceiver status register, CAN partial networking status (0x22).
#define SBC_UJA_REGULATOR_V2C_F(x)
Definition: UJA1169.h:264
void SBC_FeedWatchdog(void)
This function refreshes watchdog period by writing byte to the SBC watchdog register. This function must be called periodically according Watchdog mode control and Nominal watchdog period settings. Note: Unxpected behaviour can happend if watchdog mode is set to timeout period and watchdog is triggered exactly at 50% of period. Be sure you trigger watchdog before 50% or above 50% of watchdog period.
sbc_main_rss_t
Main status register, Reset source status (0x03).
Start-up control register structure. This structure contains settings of RSTN output reset pulse widt...
sbc_can_pncok_t
CAN control register, CAN partial networking configuration OK (0x20).
#define SBC_UJA_CAN_CPNC_F(x)
Definition: UJA1169.h:351
#define SBC_UJA_CAN_CFDC_F(x)
Definition: UJA1169.h:337
status_t SBC_GetWatchdogStatus(sbc_wtdog_status_t *const watchdogStatus)
This function reads Watchdog status register. This function will clear R/W registers automatically af...
sbc_trans_evnt_stat_cbs_t
Transceiver event status register, CAN-bus status (0x63).
MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP)...
Frame control register structure. The wake-up frame format, standard (11-bit) or extended (29-bit) id...
CAN configuration group structure. This structure configure CAN peripheral behavior.
sbc_supply_evnt_v2oe_t
Supply event capture enable register, V2/VEXT overvoltage enable (0x1C).
sbc_sup_evnt_stat_v2u_t
Supply event status register, V2/VEXT undervoltage (0x62).
status_t SBC_GetSystemEvents(sbc_sys_evnt_t *const sysEvnt)
This function reads System event capture enable register (0x04). This function reads content of overt...
sbc_trans_stat_cts_t
Transceiver status register, CAN transceiver status (0x22).
sbc_sup_evnt_stat_v2o_t
Supply event status register, V2/VEXT overvoltage (0x62).
Transceiver event capture enable register structure. Can bus silence, Can failure and Can wake-up set...
#define SBC_UJA_WTDOG_STAT_FNMS_F(x)
Definition: UJA1169.h:162
#define SBC_UJA_FRAME_CTR_PNDM_F(x)
Definition: UJA1169.h:580
System event capture enable register structure. This structure enables or disables overtemperature wa...
#define SBC_UJA_SBC_V1RTSUC_F(x)
Definition: UJA1169.h:857
#define SBC_UJA_FRAME_CTR_IDE_F(x)
Definition: UJA1169.h:573
sbc_wake_evnt_stat_wpr_t
WAKE pin event status register, WAKE pin rising edge (0x64).
#define SBC_UJA_REGULATOR_V1RTC_F(x)
Definition: UJA1169.h:271
#define SBC_UJA_WAKE_EN_WPFE_F(x)
Definition: UJA1169.h:633
#define SBC_UJA_GL_EVNT_STAT_TRXE_F(x)
Definition: UJA1169.h:654
sbc_sys_evnt_spife_t
System event capture enable, SPI failure enable (0x04).
#define SBC_UJA_SBC_SDMC_F(x)
Definition: UJA1169.h:873
#define SBC_UJA_SUP_EVNT_STAT_V2O_F(x)
Definition: UJA1169.h:719
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
Transceiver event status register.
sbc_sbc_sdmc_t
SBC configuration control register, Software Development mode control (0x74).
#define SBC_UJA_SUP_EVNT_STAT_V1U_F(x)
Definition: UJA1169.h:733
#define SBC_UJA_WAKE_STAT_WPVS_F(x)
Definition: UJA1169.h:610
Watchdog status register structure. Information on the status of the watchdog is available from the W...
sbc_wtdog_ctr_wmc_t
Watchdog control register, watchdog mode control (0x00). The UJA1169 contains a watchdog that support...
#define SBC_UJA_DAT_RATE_CDR_F(x)
Definition: UJA1169.h:461
#define SBC_UJA_LOCK_LKNC_MASK
Lock control N macros.
Definition: UJA1169.h:245
CAN control register structure. This structure configure CAN peripheral behavior. ...
sbc_gl_evnt_stat_supe_t
Global event status register, supply event (0x60).
sbc_frame_ctr_ide_t
Frame control register, identifier format (0x2F). The wake-up frame format, standard (11-bit) or exte...
#define SBC_UJA_SYS_EVNT_OTWE_F(x)
Definition: UJA1169.h:141
status_t SBC_SetFailSafe(const sbc_fail_safe_lhc_t lhc, const sbc_fail_safe_rcc_t *const rcc)
This function writes to Fail-safe control register (0x02). The dedicated LIMP pin can be used to enab...
#define SBC_UJA_COUNT_DMASK
#define SBC_UJA_START_UP_RLC_F(x)
Definition: UJA1169.h:835
WAKE pin event status register.
Supply event capture enable register structure. This structure enables or disables detection of V2/VE...
sbc_can_cmc_t
CAN control register, CAN mode control (0x20).
#define SBC_UJA_LOCK_LK5C_MASK
Lock control control 5: address area 0x50 to 0x5F - unused register range macros. ...
Definition: UJA1169.h:203
#define SBC_UJA_SYS_EVNT_STAT_WDF_F(x)
Definition: UJA1169.h:704
uint8_t sbc_identifier_t
ID registers, identifier format (0x27 to 0x2A). A valid WUF identifier is defined and stored in the I...
status_t SBC_GetVreg(sbc_regulator_ctr_t *const regulatorCtr)
This function reads Regulator control registers.
status_t SBC_SetMode(const sbc_mode_mc_t mode)
This function writes to Mode control register. (0x01).
sbc_wtdog_ctr_nwp_t
Watchdog control register, nominal watchdog period (0x00). Eight watchdog periods are supported...
sbc_trans_evnt_stat_pnfde_t
Transceiver event status register,partial networking frame detection error (0x63).
#define SBC_UJA_CAN_PNCOK_F(x)
Definition: UJA1169.h:344
uint8_t sbc_fail_safe_rcc_t
Fail-safe control register, reset counter control (0x02). incremented every time the SBC enters Reset...
#define SBC_UJA_WAKE_EN_WPRE_F(x)
Definition: UJA1169.h:625
sbc_register_t
Register map.
sbc_can_cpnc_t
CAN control register, CAN partial networking control (0x20).
sbc_lock_t
Lock control(0x0A). Sections of the register address area can be write-protected to protect against u...
#define SBC_UJA_REGULATOR_PDC_F(x)
Definition: UJA1169.h:257
sbc_main_otws_t
Main status register, Overtemperature warning status (0x03).
sbc_wtdog_stat_wds_t
Watchdog status register, watchdog status (0x05).
#define SBC_UJA_SYS_EVNT_STAT_SPIF_F(x)
Definition: UJA1169.h:697
status_t SBC_GetWatchdog(sbc_wtdog_ctr_t *const wtdog)
This function reads Watchdog control register (0x00).
status_t SBC_DataTransfer(const sbc_register_t regName, const uint8_t *const sendData, uint8_t *const receiveData)
This function sends data over LSPI to SBC device. This function sends 8 bites to SBC device register ...
status_t SBC_GetMtpnvStatus(sbc_mtpnv_stat_t *const mtpnv)
This function reads MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times...
#define SBC_UJA_SUPPLY_STAT_V1S_F(x)
Definition: UJA1169.h:292
#define SBC_UJA_TRANS_STAT_COSCS_F(x)
Definition: UJA1169.h:394
status_t SBC_SetVreg(const sbc_regulator_ctr_t *const regulatorCtr)
This function configures Regulator control registers.
Regulator control register group. This structure is group of regulator settings.
sbc_wtdog_stat_fnms_t
Watchdog status register, forced Normal mode status (0x05).
status_t SBC_GetMainStatus(sbc_main_status_t *const mainStatus)
This function reads Main status register. This function will clear R/W registers automatically after ...
#define SBC_UJA_SUPPLY_EVNT_V2OE_F(x)
Definition: UJA1169.h:307
Supply event status register.
Status group structure. All statuses of SBC are stored in this structure.
sbc_sbc_slpc_t
SBC configuration control register, Sleep control (0x74).
#define SBC_UJA_MAIN_NMS_F(x)
Definition: UJA1169.h:120
#define SBC_UJA_LOCK_LK0C_MASK
Lock control 0: address area 0x06 to 0x09 - general-purpose memory macros.
Definition: UJA1169.h:238
#define SBC_UJA_TRANS_EVNT_CBSE_F(x)
Definition: UJA1169.h:432
#define SBC_UJA_TRANS_STAT_CPNS_F(x)
Definition: UJA1169.h:387
status_t SBC_GetSupplyStatus(sbc_supply_status_t *const supStatus)
This functions reads Supply voltage status register. This function clear R/W status after reading wri...
status_t SBC_GetWakePin(sbc_wake_t *const wakePin)
This function reads WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits ...
status_t SBC_GetCanConfig(sbc_can_conf_t *const can)
This function reads CAN peripheral settings. This function configures CAN peripheral behavior...
#define SBC_UJA_TRANS_STAT_CFS_F(x)
Definition: UJA1169.h:415
sbc_sys_evnt_stat_wdf_t
System event status register, watchdog failure (0x61).
sbc_start_up_rlc_t
Start-up control register, RSTN output reset pulse width macros (0x73).
#define SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(x)
Definition: UJA1169.h:749
sbc_trans_evnt_stat_cf_t
Transceiver event status register, CAN failure (0x63).
sbc_start_up_v2suc_t
Start-up control register, V2/VEXT start-up control (0x73).
sbc_gl_evnt_stat_syse_t
Global event status register, system event (0x60).
System event status register. Wake-up and interrupt event diagnosis in the UJA1169 is intended to pro...
sbc_trans_evnt_stat_cw_t
Transceiver event status register, CAN wake-up (0x63).
SBC configuration control register structure. Two operating modes have a major impact on the operatio...
sbc_supply_stat_v1s_t
Supply voltage status register, V1 status (0x1B).
#define SBC_UJA_TRANS_EVNT_STAT_CW_F(x)
Definition: UJA1169.h:770
sbc_supply_evnt_v2ue_t
Supply event capture enable register, V2/VEXT undervoltage enable (0x1C).
#define SBC_UJA_WTDOG_CTR_WMC_F(x)
Definition: UJA1169.h:57
#define SBC_UJA_MTPNV_STAT_NVMPS_F(x)
Definition: UJA1169.h:820
status_t SBC_SetWakePin(const sbc_wake_t *const wakePin)
This function writes to WAKE pin event capture enable register (0x4C). Local wake-up is enabled via b...
sbc_trans_stat_vcs_t
Transceiver status register, VCAN status (0x22).
sbc_sbc_fnmc_t
SBC configuration control register, Forced Normal mode control (0x74).
sbc_trans_stat_cpnerr_t
Transceiver status register, CAN partial networking error (0x22).
sbc_mtpnv_stat_eccs_t
MTPNV status register, error correction code status (0x70).
WAKE pin event capture enable register structure. Local wake-up is enabled via bits WPRE and WPFE in ...
#define SBC_UJA_START_UP_V2SUC_F(x)
Definition: UJA1169.h:842
status_t SBC_GetCanStatus(sbc_trans_stat_t *const transStatus)
This functions reads Transceiver status register. It contains CAN transceiver status, CAN partial networking error, CAN partial networking status, CAN oscillator status, CAN-bus silence status, VCAN status, CAN failure status.
sbc_trans_evnt_cbse_t
Transceiver event capture enable register, CAN-bus silence enable (0x23).
#define SBC_UJA_GL_EVNT_STAT_SUPE_F(x)
Definition: UJA1169.h:661
sbc_wake_stat_wpvs_t
WAKE pin status register, WAKE pin status (0x4B).
status_t SBC_GetLock(sbc_lock_t *const lockMask)
This function reads Lock control register (0x0A). Sections of the register address area can be write-...
sbc_mtpnv_stat_nvmps_t
MTPNV status register, non-volatile memory programming status (0x70).
#define SBC_UJA_CAN_CMC_F(x)
Definition: UJA1169.h:358
sbc_regulator_v1rtc_t
Regulator control register, set V1 reset threshold (0x10).
#define SBC_UJA_WTDOG_STAT_WDS_F(x)
Definition: UJA1169.h:176
uint8_t sbc_frame_ctr_dlc_t
Frame control register, number of data bytes expected in a CAN frame (0x2F).
sbc_wtdog_stat_sdms_t
Watchdog status register, Software Development mode status (0x05).
#define SBC_UJA_SBC_FNMC_F(x)
Definition: UJA1169.h:865
sbc_can_cfdc_t
CAN control register, CAN FD control (0x20).
sbc_wake_evnt_stat_wpf_t
WAKE pin event status register, WAKE pin falling edge (0x64).
status_t SBC_Init(const sbc_int_config_t *const config, const uint32_t lpspiInstance)
This function initializes all registers. It waits 10ms and then writes to all registers.
sbc_sbc_v1rtsuc_t
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x7...