S32 SDK
FlexTimer (FTM)

Detailed Description

FlexTimer Peripheral Driver.

Hardware background

The FTM of the S32K144 is based on a 16 bits counter and supports: input capture, output compare, PWM and some instances include quadrature decoder. The main features are:

•FTM source clock is selectable (Source clock can be the system clock, the fixed frequency clock, or an external clock)

•Prescaler: 1, 2, 4, 8, 16, 32, 64, 128

•16 bit counter (up and up-down counting)

•Each channel can be configured for input capture, output compare, or edge-aligned PWM mode.

•Input Capture mode (single edge, dual edge)

•Output Compare mode (set, cleared or toggle on match)

•All channels can be configured for center-aligned PWM mode.

•Each pair of channels can be combined to generate a PWM signal with independent control of both edges of PWM signal and with dead-time insertion.

•Up to 4 fault inputs for global fault control

•Dual edge capture for pulse and period width measurement

•Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event.

How to use FTM driver in your application

For all operation modes (without Quadrature Decoder mode) the user need to configure ftm_user_config_t. This structure will be used for initialization (FTM_DRV_Init). The next functions used are specific for each operation mode.

Output compare mode

For this mode the user needs to configure maximum counter value, number of channels used and output mode for each channel (toggle/clear/set on match). This information is stored in ftm_output_cmp_param_t data type and are used in FTM_OC_DRV_InitOutputCompare. Next step is to set a value for comparison with FTM_OC_DRV_UpdateOutputCompareChannel.

Example:

/* The state structure of instance in the output compare mode */
ftm_state_t stateOutputCompare;
#define FTM_OUTPUT_COMPARE_INSTANCE 2UL
/* Channels configuration structure for PWM output compare */
ftm_output_cmp_ch_param_t PWM_OutputCompareChannelConfig[2] =
{
{
0, /* Channel id */
FTM_TOGGLE_ON_MATCH, /* Output mode */
10000U, /* Compared value */
false, /* External Trigger */
},
{
1, /* Channel id */
FTM_TOGGLE_ON_MATCH, /* Output mode */
20000U, /* Compared value */
false, /* External Trigger */
}
};
/* Output compare configuration for PWM */
ftm_output_cmp_param_t PWM_OutputCompareConfig =
{
2, /* Number of channels */
FTM_MODE_OUTPUT_COMPARE, /* FTM mode */
40000U, /* Maximum count value */
PWM_OutputCompareChannelConfig /* Channels configuration */
};
/* Timer mode configuration for PWM */
/* Global configuration of PWM */
ftm_user_config_t PWM_InitConfig =
{
{
true, /* Software trigger state */
false, /* Hardware trigger 1 state */
false, /* Hardware trigger 2 state */
false, /* Hardware trigger 3 state */
true, /* Maximum loading point state */
true, /* Min loading point state */
FTM_SYSTEM_CLOCK, /* Update mode for INVCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for SWOCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for OUTMASK register */
FTM_SYSTEM_CLOCK, /* Update mode for CNTIN register */
false, /* Auto clear trigger state for hardware trigger */
FTM_UPDATE_NOW, /* select synchronization method */
},
FTM_MODE_OUTPUT_COMPARE, /* Mode of operation for FTM */
FTM_CLOCK_DIVID_BY_4, /* FTM clock pre-scaler */
FTM_CLOCK_SOURCE_SYSTEMCLK, /* FTM clock source */
FTM_BDM_MODE_11, /* FTM debug mode */
false, /* Interrupt state */
false /* Initialization trigger */
};
FTM_DRV_Init(FTM_OUTPUT_COMPARE_INSTANCE, &PWM_InitConfig, &stateOutputCompare);
FTM_OC_DRV_InitOutputCompare(FTM_OUTPUT_COMPARE_INSTANCE, &PWM_OutputCompareConfig);
/* If you want to change compared value */
FTM_OC_DRV_UpdateOutputCompareChannel(FTM_OUTPUT_COMPARE_INSTANCE, 0UL, 15000U );

PWM mode

For this mode the user needs to configure parameters such: number of PWM channels, frequency, dead time, fault channels and duty cycle, alignment (edge or center). All this information is included in ftm_pwm_param_t data type.

FTM_PWM_DRV_UpdatePwmChannel can be used to update duty cycles at run time. If the type of update in the duty cycle when the duty cycle can have value between 0x0 (0%) and 0x8000 (100%). If the type of update in ticks when the firstEdge and secondEdge variables can have value between 0 and ftmPeriod which is stored in the state structure.

Example:

/* The state structure of instance in the PWM mode */
ftm_state_t statePwm;
#define FTM_PWM_INSTANCE 1UL
/* Fault configuration structure */
ftm_pwm_fault_param_t PWM_FaultConfig =
{
false,
true,
5U, /* Fault filter value */
FTM_FAULT_CONTROL_MAN_EVEN,
{
{
true, /* Fault channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_HIGH, /* Channel output state on fault */
},
{
false, /* Fault Channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_LOW /* Channel output state on fault */
},
{
false, /* Fault Channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_LOW /* Channel output state on fault */
},
{
false, /* Fault Channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_LOW /* Channel output state on fault */
}
}
};
/* Independent channels configuration structure for PWM */
ftm_independent_ch_param_t PWM_IndependentChannelsConfig[1] =
{
{
0U, /* hwChannelId */
FTM_POLARITY_HIGH, /* edgeMode */
10922, /* uDutyCyclePercent (0-0x8000) */
false, /* External Trigger */
}
};
/* PWM configuration for PWM */
ftm_pwm_param_t PWM_PwmConfig =
{
1U, /* Number of independent PWM channels */
0U, /* Number of combined PWM channels */
FTM_MODE_EDGE_ALIGNED_PWM, /* PWM mode */
0U, /* DeadTime Value */
FTM_DEADTIME_DIVID_BY_4, /* DeadTime clock divider */
7481U, /* PWM frequency */
PWM_IndependentChannelsConfig, /* Independent PWM channels configuration structure */
NULL, /* Combined PWM channels configuration structure */
&PWM_FaultConfig /* PWM fault configuration structure */
};
/* Timer mode configuration for PWM */
/* Global configuration of PWM */
ftm_user_config_t PWM_InitConfig =
{
{
true, /* Software trigger state */
false, /* Hardware trigger 1 state */
false, /* Hardware trigger 2 state */
false, /* Hardware trigger 3 state */
true, /* Maximum loading point state */
true, /* Min loading point state */
FTM_SYSTEM_CLOCK, /* Update mode for INVCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for SWOCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for OUTMASK register */
FTM_SYSTEM_CLOCK, /* Update mode for CNTIN register */
false, /* Auto clear trigger state for hardware trigger */
FTM_UPDATE_NOW, /* Select synchronization method */
},
FTM_MODE_EDGE_ALIGNED_PWM, /* PWM mode */
FTM_CLOCK_DIVID_BY_4, /* FTM clock pre-scaler */
FTM_CLOCK_SOURCE_SYSTEMCLK, /* FTM clock source */
FTM_BDM_MODE_11, /* FTM debug mode */
false, /* Interrupt state */
false /* Initialization trigger */
};
FTM_DRV_Init(FTM_PWM_INSTANCE, &PWM_InitConfig, &statePwm);
FTM_PWM_DRV_InitPwm(FTM_PWM_INSTANCE, &PWM_PwmConfig);
/* It's recommended to use softwareTrigger = true */
/* SECOND_EDGE value is used only when PWM is used in combined mode */
FTM_PWM_DRV_UpdatePwmChannel(FTM_PWM_INSTANCE, OUL, FTM_PWM_UPDATE_IN_DUTY_CYCLE, 0x800, 0x2000, true);

PWM in Modified Combine mode

For this mode the user needs to configure parameters such: number of PWM channels, frequency, dead time, fault channels and duty cycle, alignment (edge or center). All this information is included in ftm_pwm_param_t data type. The Modified Combine PWM mode is intended to support the generation of PWM signals where the period is not modified while the signal is being generated, but the duty cycle will be varied. FTM_PWM_DRV_UpdatePwmChannel can be used to update duty cycles at run time. If the type of update in the duty cycle when the duty cycle can have value between 0x0 (0%) and 0x8000 (100%). If the type of update in ticks when the firstEdge and secondEdge variables can have value between 0 and ftmPeriod which is stored in the state structure.In this mode, an even channel (n) and adjacent odd channel (n+1) are combined to generate a PWM signal in the channel (n) output. Thus, the channel (n) match edge is fixed and the channel (n+1) match edge can be varied.

Example:

/* The state structure of instance in the PWM mode */
ftm_state_t statePwm;
#define FTM_PWM_INSTANCE 0UL
/* Fault configuration structure */
ftm_pwm_fault_param_t PWM_FaultConfig =
{
false,
true,
5U, /* Fault filter value */
FTM_FAULT_CONTROL_MAN_EVEN,
{
{
true, /* Fault channel state (Enabled/Disabled )*/
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_HIGH, /* Channel output state on fault */
},
{
false, /* Fault Channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_LOW /* Channel output state on fault */
},
{
false, /* Fault Channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_LOW /* Channel output state on fault */
},
{
false, /* Fault Channel state (Enabled/Disabled) */
false, /* Fault channel filter state (Enabled/Disabled) */
FTM_POLARITY_LOW /* Channel output state on fault */
}
}
};
/* Combine channels configuration structure for PWM */
ftm_combined_ch_param_t flexTimer1_CombinedChannelsConfig[1] =
{
{
0U, /* Hardware channel for channel (n) */
512U, /* First edge time */
16384U, /* Second edge time */
false, /* Dead time enabled/disabled */
true, /* The modified combine mode enabled/disabled */
FTM_POLARITY_HIGH, /* Channel polarity */
true, /* Output enabled/disabled for channel (n+1) */
FTM_MAIN_DUPLICATED, /* Polarity for channel (n+1) */
false, /* External Trigger on the channel (n) */
false, /* External Trigger on the channel (n+1) */
}
};
/* PWM configuration for PWM */
ftm_pwm_param_t PWM_PwmConfig =
{
0U, /* Number of independent PWM channels */
1U, /* Number of combined PWM channels */
FTM_MODE_EDGE_ALIGNED_PWM, /* PWM mode */
0U, /* DeadTime Value */
FTM_DEADTIME_DIVID_BY_4, /* DeadTime clock divider */
7481U, /* PWM frequency */
NULL, /* Independent PWM channels configuration structure */
flexTimer1_CombinedChannelsConfig, /* Combined PWM channels configuration structure */
&PWM_FaultConfig /* PWM fault configuration structure */
};
/* Timer mode configuration for PWM */
/* Global configuration of PWM */
ftm_user_config_t PWM_InitConfig =
{
{
true, /* Software trigger state */
false, /* Hardware trigger 1 state */
false, /* Hardware trigger 2 state */
false, /* Hardware trigger 3 state */
true, /* Maximum loading point state */
true, /* Min loading point state */
FTM_SYSTEM_CLOCK, /* Update mode for INVCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for SWOCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for OUTMASK register */
FTM_SYSTEM_CLOCK, /* Update mode for CNTIN register */
false, /* Auto clear trigger state for hardware trigger */
FTM_UPDATE_NOW, /* Select synchronization method */
},
FTM_MODE_EDGE_ALIGNED_PWM, /* PWM mode */
FTM_CLOCK_DIVID_BY_4, /* FTM clock pre-scaler */
FTM_CLOCK_SOURCE_SYSTEMCLK, /* FTM clock source */
FTM_BDM_MODE_11, /* FTM debug mode */
false, /* Interrupt state */
false /* Initialization trigger */
};
FTM_DRV_Init(FTM_PWM_INSTANCE, &PWM_InitConfig, &statePwm);
FTM_PWM_DRV_InitPwm(FTM_PWM_INSTANCE, &PWM_PwmConfig);
/* It's recommended to use softwareTrigger = true */
/* SECOND_EDGE value is used only when PWM is used in combined mode */
FTM_PWM_DRV_UpdatePwmChannel(FTM_PWM_INSTANCE, OUL, FTM_PWM_UPDATE_IN_DUTY_CYCLE, 0x0, 0x2000, true);

Single edge input capture mode

For this mode the user needs to configure parameters such: maximum counter value, number of channels, input capture operation mode (for single edge input are used edge detect mode) and edge alignment. All this information is included in ftm_input_param_t.

Example:

/* The state structure of instance in the input capture mode */
ftm_state_t stateInputCapture;
#define FTM_IC_INSTANCE 0UL
/* Channels configuration structure for inputCapture input capture */
ftm_input_ch_param_t inputCapture_InputCaptureChannelConfig[1] =
{
{
0U, /* Channel id */
FTM_EDGE_DETECT, /* Input capture operation Mode */
FTM_RISING_EDGE, /* Edge alignment Mode */
FTM_NO_MEASUREMENT, /* Signal measurement operation type */
0U, /* Filter value */
false, /* Filter disabled */
true /* Continuous mode measurement */
NULL, /* Vector of callbacks parameters for channels events */
NULL /* Vector of callbacks for channels events */
}
};
/* Input capture configuration for inputCapture */
ftm_input_param_t inputCapture_InputCaptureConfig =
{
1U, /* Number of channels */
65535U, /* Maximum count value */
inputCapture_InputCaptureChannelConfig /* Channels configuration */
};
/* Timer mode configuration for inputCapture */
/* Global configuration of inputCapture */
ftm_user_config_t inputCapture_InitConfig =
{
{
false, /* Software trigger state */
false, /* Hardware trigger 1 state */
false, /* Hardware trigger 2 state */
false, /* Hardware trigger 3 state */
false, /* Maximum loading point state */
false, /* Min loading point state */
FTM_SYSTEM_CLOCK, /* Update mode for INVCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for SWOCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for OUTMASK register */
FTM_SYSTEM_CLOCK, /* Update mode for CNTIN register */
false, /* Auto clear trigger state for hardware trigger */
FTM_UPDATE_NOW, /* Select synchronization method */
},
FTM_MODE_INPUT_CAPTURE, /* Mode of operation for FTM */
FTM_CLOCK_DIVID_BY_4, /* FTM clock pre-scaler */
FTM_CLOCK_SOURCE_SYSTEMCLK, /* FTM clock source */
FTM_BDM_MODE_00, /* FTM debug mode */
false, /* Interrupt state */
false /* Initialization trigger */
};
FTM_DRV_Init(FTM_IC_INSTANCE, &inputCapture_InitConfig, &stateInputCapture);
FTM_IC_DRV_InitInputCapture(FTM_IC_INSTANCE, &inputCapture_InputCaptureConfig);
counter = FTM_IC_DRV_GetInputCaptureMeasurement(FTM_IC_INSTANCE, 0UL);

FTM_IC_DRV_GetInputCaptureMeasurement is now used in interrupt mode and this function is used to save time stamps in internal buffers.

Counter mode

For this mode the user needs to configure parameters like: counter mode (up-counting or up-down counting), maximum counter value, initial counter value. All this information is included in ftm_timer_param_t.

Example:

/* The state structure of instance in the input capture mode */
ftm_state_t stateTimer;
#define FTM_TIMER_INSTANCE 3UL
/* Timer mode configuration for Timer */
ftm_timer_param_t Timer_TimerConfig =
{
FTM_MODE_UP_TIMER, /* Counter mode */
0U, /* Initial counter value */
0x8000U /* Final counter value */
};
/* Global configuration of Timer*/
ftm_user_config_t Timer_InitConfig =
{
{
false, /* Software trigger state */
false, /* Hardware trigger 1 state */
false, /* Hardware trigger 2 state */
false, /* Hardware trigger 3 state */
false, /* Maximum loading point state */
false, /* Min loading point state */
FTM_SYSTEM_CLOCK, /* Update mode for INVCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for SWOCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for OUTMASK register */
FTM_SYSTEM_CLOCK, /* Update mode for CNTIN register */
false, /* Auto clear trigger state for hardware trigger */
FTM_UPDATE_NOW, /* Select synchronization method */
},
FTM_MODE_UP_TIMER, /* Mode of operation for FTM */
FTM_CLOCK_DIVID_BY_2, /* FTM clock pre-scaler */
FTM_CLOCK_SOURCE_SYSTEMCLK, /* FTM clock source */
FTM_BDM_MODE_11, /* FTM debug mode */
false, /* Interrupt state */
false /* Initialization trigger */
};
FTM_DRV_Init(FTM_TIMER_INSTANCE,&Timer_InitConfig, &stateTimer);
FTM_MC_DRV_InitCounter(FTM_TIMER_INSTANCE, &Timer_TimerConfig);
FTM_MC_DRV_CounterStart(FTM_TIMER_INSTANCE);

Quadrature decoder mode

For this mode the user needs to configure parameters like: maximum counter value, initial counter value, mode (Count and Direction Encoding mode, Count and Direction Encoding mode), and for both input phases polarity and filtering. All this information is included in ftm_quad_decode_config_t. In this mode the counter is clocked by the phase A and phase B. The current state of the decoder can be obtained using FTM_MC_DRV_QuadGetState.

Hardware limitation:

In count and direction mode if initial value of the PHASE_A is HIGH the counter will be incremented.

Example:

/* The state structure of instance in the quadrature mode */
ftm_state_t stateQuad;
#define FTM_QUADRATURE_INSTANCE 0UL
ftm_quad_decode_config_t quadrature_decoder_configuration =
{
FTM_QUAD_COUNT_AND_DIR, /* Quadrature decoder mode */
0U, /* Initial counter value */
32500U, /* Maximum counter value */
{
false, /* Filter state */
0U, /* Filter value */
FTM_QUAD_PHASE_NORMAL /* Phase polarity */
},
{
false, /* Filter state */
0U, /* Filter value */
FTM_QUAD_PHASE_NORMAL /* Phase polarity */
}
};
/* Timer mode configuration for Quadrature */
/* Global configuration of Quadrature */
ftm_user_config_t Quadrature_InitConfig =
{
{
false, /* Software trigger state */
false, /* Hardware trigger 1 state */
false, /* Hardware trigger 2 state */
false, /* Hardware trigger 3 state */
false, /* Maximum loading point state */
false, /* Min loading point state */
FTM_SYSTEM_CLOCK, /* Update mode for INVCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for SWOCTRL register */
FTM_SYSTEM_CLOCK, /* Update mode for OUTMASK register */
FTM_SYSTEM_CLOCK, /* Update mode for CNTIN register */
false, /* Auto clear trigger state for hardware trigger */
FTM_UPDATE_NOW, /* Select synchronization method */
},
FTM_MODE_QUADRATURE_DECODER, /* Mode of operation for FTM */
FTM_CLOCK_DIVID_BY_2, /* FTM clock pre-scaler */
FTM_CLOCK_SOURCE_SYSTEMCLK, /* FTM clock source */
FTM_BDM_MODE_11, /* FTM debug mode */
false, /* Interrupt state */
false /* Initialization trigger */
};
FTM_DRV_Init(FTM_QUADRATURE_INSTANCE, &Quadrature_InitConfig, &stateQuad);
FTM_MC_DRV_QuadDecodeStart(FTM_QUADRATURE_INSTANCE, &quadrature_decoder_configuration);
quadra_state = FTM_MC_DRV_QuadGetState(FTM_QUADRATURE_INSTANCE);

Modules

 FTM Common Driver
 FlexTimer Peripheral Common Driver.
 
 FTM Input Capture Driver
 FlexTimer Peripheral Input Capture Driver.
 
 FTM Module Counter Driver
 FlexTimer Peripheral Driver.
 
 FTM Output Compare Driver
 FlexTimer Peripheral Output Compare Driver.
 
 FTM Pulse Width Modulation Driver
 FlexTimer Peripheral Pulse Width Modulation Driver.
 
 FTM Quadrature Decoder Driver
 FlexTimer Peripheral Driver.