S32 SDK
ftm_common.h
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1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
35 #ifndef FTM_COMMON_H
36 #define FTM_COMMON_H
37 
38 #include "ftm_hw_access.h"
39 
48 /*******************************************************************************
49  * Variables
50  ******************************************************************************/
52 extern FTM_Type * const g_ftmBase[FTM_INSTANCE_COUNT];
53 
59 
60 #ifdef ERRATA_E10856
61 extern bool faultDetection;
62 #endif
63 /*******************************************************************************
64  * Definitions
65  ******************************************************************************/
66 
72 typedef enum
73 {
83 
89 typedef enum
90 {
94 
100 typedef enum
101 {
107 
114 typedef void (* ftm_channel_event_callback_t)(void * userData);
115 
121 typedef struct
122 {
123  ftm_clock_source_t ftmClockSource;
125  uint16_t ftmPeriod;
127  uint16_t measurementResults[FEATURE_FTM_CHANNEL_COUNT];
128  void * channelsCallbacksParams[FEATURE_FTM_CHANNEL_COUNT];
130 } ftm_state_t;
131 
137 typedef struct
138 {
151  ftm_reg_update_t inverterSync;
152  ftm_reg_update_t outRegSync;
153  ftm_reg_update_t maskRegSync;
154  ftm_reg_update_t initCounterSync;
156  ftm_pwm_sync_mode_t syncPoint;
159 
165 typedef struct
166 {
170  ftm_clock_ps_t ftmPrescaler;
172  ftm_clock_source_t ftmClockSource;
173  ftm_bdm_mode_t BDMMode;
179 
180 /*******************************************************************************
181  * Variables
182  ******************************************************************************/
185 
186 /*******************************************************************************
187  * API
188  ******************************************************************************/
189 
190 #if defined(__cplusplus)
191 extern "C" {
192 #endif
193 
202 static inline void FTM_DRV_SetClockFilterPs(FTM_Type * const ftmBase,
203  uint8_t filterPrescale)
204 {
205  FTM_RMW_SC(ftmBase, FTM_SC_FLTPS_MASK, FTM_SC_FLTPS(filterPrescale));
206 }
207 
217 static inline uint8_t FTM_DRV_GetClockFilterPs(const FTM_Type * ftmBase)
218 {
219  return (uint8_t)((((ftmBase)->SC) & FTM_SC_FLTPS_MASK) >> FTM_SC_FLTPS_SHIFT);
220 }
221 
235 static inline uint8_t FTM_DRV_GetClockSource(const FTM_Type * ftmBase)
236 {
237  return (uint8_t)((((ftmBase)->SC) & FTM_SC_CLKS_MASK) >> FTM_SC_CLKS_SHIFT);
238 }
239 
249 static inline uint8_t FTM_DRV_GetClockPs(const FTM_Type * ftmBase)
250 {
251  return (uint8_t)((((ftmBase)->SC) & FTM_SC_PS_MASK) >> FTM_SC_PS_SHIFT);
252 }
253 
265 static inline bool FTM_DRV_IsOverflowIntEnabled(const FTM_Type * ftmBase)
266 {
267  return ((ftmBase->SC & FTM_SC_TOIE_MASK) >> FTM_SC_TOIE_SHIFT) != 0U;
268 }
269 
281 static inline bool FTM_DRV_HasTimerOverflowed(const FTM_Type * ftmBase)
282 {
283  return ((ftmBase->SC & FTM_SC_TOF_MASK) >> FTM_SC_TOF_SHIFT) != 0U;
284 }
285 
297 static inline bool FTM_DRV_GetCpwms(const FTM_Type * ftmBase)
298 {
299  return ((ftmBase->SC & FTM_SC_CPWMS_MASK) >> FTM_SC_CPWMS_SHIFT) != 0U;
300 }
301 
311 static inline void FTM_DRV_SetReIntEnabledCmd(FTM_Type * const ftmBase,
312  bool enable)
313 {
314  FTM_RMW_SC(ftmBase, FTM_SC_RIE_MASK, FTM_SC_RIE(enable));
315 }
316 
328 static inline bool FTM_DRV_GetReloadFlag(const FTM_Type * ftmBase)
329 {
330  return ((ftmBase->SC & FTM_SC_RF_MASK) >> FTM_SC_RF_SHIFT) != 0U;
331 }
332 
340 static inline void FTM_DRV_ClearReloadFlag(FTM_Type * const ftmBase)
341 {
342  FTM_RMW_SC(ftmBase, FTM_SC_RF_MASK, FTM_SC_RF(0U));
343 #ifdef ERRATA_E9005
344  /* Read-after-write sequence to guarantee required serialization of memory operations */
345  ftmBase->SC;
346 #endif
347 }
348 
358 static inline uint16_t FTM_DRV_GetCounter(const FTM_Type * ftmBase)
359 {
360  return (uint16_t)((((ftmBase)->CNT) & FTM_CNT_COUNT_MASK) >> FTM_CNT_COUNT_SHIFT);
361 }
362 
372 static inline uint16_t FTM_DRV_GetMod(const FTM_Type * ftmBase)
373 {
374  return (uint16_t)((((ftmBase)->MOD) & FTM_MOD_MOD_MASK) >> FTM_MOD_MOD_SHIFT);
375 }
376 
386 static inline uint16_t FTM_DRV_GetCounterInitVal(const FTM_Type * ftmBase)
387 {
388  return (uint16_t)((((ftmBase)->CNTIN) & FTM_CNTIN_INIT_MASK) >> FTM_CNTIN_INIT_SHIFT);
389 }
390 
399 static inline void FTM_DRV_ClearChSC(FTM_Type * const ftmBase,
400  uint8_t channel)
401 {
403 
404  ((ftmBase)->CONTROLS[channel].CnSC) = 0U;
405 #ifdef ERRATA_E9005
406  /* Read-after-write sequence to guarantee required serialization of memory operations */
407  ftmBase->CONTROLS[channel].CnSC;
408 #endif
409 }
410 
421 static inline uint8_t FTM_DRV_GetChnMode(const FTM_Type * ftmBase,
422  uint8_t channel)
423 {
425  uint8_t retValue;
426 
427  retValue = (uint8_t)((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_MSA_MASK) >> FTM_CnSC_MSA_SHIFT);
428 
429  retValue |= (uint8_t)(((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_MSB_MASK) >> FTM_CnSC_MSB_SHIFT) << 1U);
430 
431  return retValue;
432 }
433 
444 static inline uint8_t FTM_DRV_GetChnEdgeLevel(const FTM_Type * ftmBase,
445  uint8_t channel)
446 {
448  uint8_t retValue;
449 
450  retValue = (uint8_t)((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ELSA_MASK) >> FTM_CnSC_ELSA_SHIFT);
451 
452  retValue |= (uint8_t)(((((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ELSB_MASK) >> FTM_CnSC_ELSB_SHIFT) << 1U);
453 
454  return retValue;
455 }
456 
468 static inline void FTM_DRV_SetChnIcrstCmd(FTM_Type * const ftmBase,
469  uint8_t channel,
470  bool enable)
471 {
473 
474  /* Write ICRST bit */
475  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_ICRST_MASK, FTM_CnSC_ICRST(enable));
476 }
477 
489 static inline bool FTM_DRV_IsChnIcrst(const FTM_Type * ftmBase,
490  uint8_t channel)
491 {
493 
494  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_ICRST_MASK) != 0U;
495 }
496 
508 static inline void FTM_DRV_SetChnDmaCmd(FTM_Type * const ftmBase,
509  uint8_t channel,
510  bool enable)
511 {
513 
514  /* Write DMA bit */
515  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_DMA_MASK, FTM_CnSC_DMA(enable));
516 }
517 
529 static inline bool FTM_DRV_IsChnDma(const FTM_Type * ftmBase,
530  uint8_t channel)
531 {
533 
534  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_DMA_MASK) != 0U;
535 }
536 
544 static inline bool FTM_DRV_IsChnIntEnabled(const FTM_Type * ftmBase,
545  uint8_t channel)
546 {
548 
549  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHIE_MASK) != 0U;
550 }
551 
564 static inline bool FTM_DRV_HasChnEventOccurred(const FTM_Type * ftmBase,
565  uint8_t channel)
566 {
568 
569  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHF_MASK) != 0U;
570 }
571 
583 static inline void FTM_DRV_SetTrigModeControlCmd(FTM_Type * const ftmBase,
584  uint8_t channel,
585  bool enable)
586 {
588 
589  /* Write TRIGMODE bit */
590  FTM_RMW_CnSCV_REG(ftmBase, channel, FTM_CnSC_TRIGMODE_MASK, FTM_CnSC_TRIGMODE((enable)));
591 }
592 
604 static inline bool FTM_DRV_GetTriggerControled(const FTM_Type * ftmBase,
605  uint8_t channel)
606 {
608 
609  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_TRIGMODE_MASK) != 0U;
610 }
611 
623 static inline bool FTM_DRV_GetChInputState(const FTM_Type * ftmBase,
624  uint8_t channel)
625 {
627 
628  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHIS_MASK) != 0U;
629 }
630 
642 static inline bool FTM_DRV_GetChOutputValue(const FTM_Type * ftmBase,
643  uint8_t channel)
644 {
646 
647  return (((ftmBase)->CONTROLS[channel].CnSC) & FTM_CnSC_CHOV_MASK) != 0U;
648 }
649 
660 static inline uint16_t FTM_DRV_GetChnCountVal(const FTM_Type * ftmBase,
661  uint8_t channel)
662 {
664 
665  return (uint16_t)((ftmBase)->CONTROLS[channel].CnV);
666 }
667 
680 static inline bool FTM_DRV_GetChnEventStatus(const FTM_Type * ftmBase,
681  uint8_t channel)
682 {
684 
685  return (((ftmBase)->STATUS) & (1UL << channel)) != 0U;
686 }
687 
697 static inline uint32_t FTM_DRV_GetEventStatus(const FTM_Type * ftmBase)
698 {
699  return ((ftmBase)->STATUS) & (0xFFU);
700 }
701 
710 static inline void FTM_DRV_ClearChnEventStatus(FTM_Type * const ftmBase,
711  uint8_t channel)
712 {
714 
715  ((ftmBase)->STATUS) &= (~(1UL << channel));
716 #ifdef ERRATA_E9005
717  /* Read-after-write sequence to guarantee required serialization of memory operations */
718  ftmBase->STATUS;
719 #endif
720 }
721 
733 static inline void FTM_DRV_SetChnOutputMask(FTM_Type * const ftmBase,
734  uint8_t channel,
735  bool mask)
736 {
738 
739  if (mask)
740  {
741  ((ftmBase)->OUTMASK) |= (1UL << channel);
742  }
743  else
744  {
745  ((ftmBase)->OUTMASK) &= ~(1UL << channel);
746  }
747 }
748 
760 static inline void FTM_DRV_SetChnOutputInitStateCmd(FTM_Type * const ftmBase,
761  uint8_t channel,
762  bool state)
763 {
765 
766  if (state)
767  {
768  ((ftmBase)->OUTINIT) |= (1UL << channel);
769  }
770  else
771  {
772  ((ftmBase)->OUTINIT) &= ~(1UL << channel);
773  }
774 }
775 
783 static inline void FTM_DRV_DisableFaultInt(FTM_Type * const ftmBase)
784 {
785  FTM_RMW_MODE(ftmBase, FTM_MODE_FAULTIE_MASK, FTM_MODE_FAULTIE(0U));
786 }
787 
795 static inline bool FTM_DRV_IsFaultIntEnabled(const FTM_Type * ftmBase)
796 {
797  return ((ftmBase->MODE & FTM_MODE_FAULTIE_MASK) >> FTM_MODE_FAULTIE_SHIFT) != 0U;
798 }
799 
807 static inline void FTM_DRV_ClearFaultsIsr(FTM_Type * const ftmBase)
808 {
809  FTM_RMW_FMS(ftmBase, FTM_FMS_FAULTF0_MASK | FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF0(0U) | FTM_FMS_FAULTF(0U));
810  FTM_RMW_FMS(ftmBase, FTM_FMS_FAULTF1_MASK | FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF1(0U) | FTM_FMS_FAULTF(0U));
811  FTM_RMW_FMS(ftmBase, FTM_FMS_FAULTF2_MASK | FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF2(0U) | FTM_FMS_FAULTF(0U));
812  FTM_RMW_FMS(ftmBase, FTM_FMS_FAULTF3_MASK | FTM_FMS_FAULTF_MASK, FTM_FMS_FAULTF3(0U) | FTM_FMS_FAULTF(0U));
813 #ifdef ERRATA_E9005
814  /* Read-after-write sequence to guarantee required serialization of memory operations */
815  ftmBase->FMS;
816 #endif
817 }
818 
829 static inline void FTM_DRV_SetCaptureTestCmd(FTM_Type * const ftmBase,
830  bool enable)
831 {
832  FTM_RMW_MODE(ftmBase, FTM_MODE_CAPTEST_MASK, FTM_MODE_CAPTEST(enable));
833 }
834 
845 static inline bool FTM_DRV_IsFtmEnable(const FTM_Type * ftmBase)
846 {
847  return ((ftmBase->MODE & FTM_MODE_FTMEN_MASK) >> FTM_MODE_FTMEN_SHIFT) != 0U;
848 }
849 
860 static inline void FTM_DRV_SetInitChnOutputCmd(FTM_Type * const ftmBase,
861  bool enable)
862 {
863  FTM_RMW_MODE(ftmBase, FTM_MODE_INIT_MASK, FTM_MODE_INIT(enable));
864 }
865 
877 static inline void FTM_DRV_SetCountReinitSyncCmd(FTM_Type * const ftmBase,
878  bool enable)
879 {
880  FTM_RMW_SYNC(ftmBase, FTM_SYNC_REINIT_MASK, FTM_SYNC_REINIT(enable));
881 }
882 
895 static inline bool FTM_DRV_GetDualEdgeCaptureBit(const FTM_Type * ftmBase,
896  uint8_t chnlPairNum)
897 {
898  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
899 
900  return (((ftmBase)->COMBINE) & ((uint32_t)FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH))) != 0U;
901 }
902 
915 static inline bool FTM_DRV_GetDualChnCombineCmd(const FTM_Type * ftmBase,
916  uint8_t chnlPairNum)
917 {
918  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
919 
920  return (((ftmBase)->COMBINE) & (FTM_COMBINE_COMBINE0_MASK << ((uint32_t)(chnlPairNum) * FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH))) != 0U;
921 }
922 
933 static inline bool FTM_DRV_IsChnTriggerGenerated(const FTM_Type * ftmBase)
934 {
935  return (ftmBase->EXTTRIG & FTM_EXTTRIG_TRIGF_MASK) != 0U;
936 }
937 
945 static inline void FTM_DRV_ClearChnTriggerFlag(FTM_Type * const ftmBase)
946 {
947  FTM_RMW_EXTTRIG_REG(ftmBase, FTM_EXTTRIG_TRIGF_MASK, FTM_EXTTRIG_TRIGF(0UL));
948 }
949 
950 /*Fault mode status*/
964 static inline bool FTM_DRV_GetDetectedFaultInput(const FTM_Type * ftmBase)
965 {
966  return (ftmBase->FMS & FTM_FMS_FAULTF_MASK) != 0U;
967 }
968 
980 static inline bool FTM_DRV_IsWriteProtectionEnabled(const FTM_Type * ftmBase)
981 {
982  return (ftmBase->FMS & FTM_FMS_WPEN_MASK) != 0U;
983 }
984 
996 static inline bool FTM_DRV_IsFaultInputEnabled(const FTM_Type * ftmBase)
997 {
998  return (ftmBase->FMS & FTM_FMS_FAULTIN_MASK) != 0U;
999 }
1000 
1013 static inline bool FTM_DRV_IsFaultFlagDetected(const FTM_Type * ftmBase,
1014  uint8_t channel)
1015 {
1016  DEV_ASSERT(channel < CHAN4_IDX);
1017 
1018  return (ftmBase->FMS & (FTM_FMS_FAULTF0_MASK << channel)) != 0U;
1019 }
1020 
1029 static inline void FTM_DRV_ClearFaultFlagDetected(FTM_Type * const ftmBase,
1030  uint8_t channel)
1031 {
1032  DEV_ASSERT(channel < CHAN4_IDX);
1033 
1034  ((ftmBase)->FMS) &= (~(1UL << channel));
1035 #ifdef ERRATA_E9005
1036  /* Read-after-write sequence to guarantee required serialization of memory operations */
1037  ftmBase->FMS;
1038 #endif
1039 }
1040 
1051 static inline void FTM_DRV_SetQuadPhaseBFilterCmd(FTM_Type * const ftmBase,
1052  bool enable)
1053 {
1054  if (enable)
1055  {
1056  ((ftmBase)->QDCTRL) |= (1UL << FTM_QDCTRL_PHBFLTREN_SHIFT);
1057  }
1058  else
1059  {
1060  ((ftmBase)->QDCTRL) &= ~(1UL << FTM_QDCTRL_PHBFLTREN_SHIFT);
1061  }
1062 }
1063 
1074 static inline void FTM_DRV_SetQuadPhaseAPolarity(FTM_Type * const ftmBase,
1076 {
1077  FTM_RMW_QDCTRL(ftmBase, FTM_QDCTRL_PHAPOL_MASK, FTM_QDCTRL_PHAPOL(mode));
1078 }
1079 
1090 static inline void FTM_DRV_SetQuadPhaseBPolarity(FTM_Type * const ftmBase,
1092 {
1093  FTM_RMW_QDCTRL(ftmBase, FTM_QDCTRL_PHBPOL_MASK, FTM_QDCTRL_PHBPOL(mode));
1094 }
1095 
1106 static inline void FTM_DRV_SetQuadMode(FTM_Type * const ftmBase,
1107  ftm_quad_decode_mode_t quadMode)
1108 {
1109  FTM_RMW_QDCTRL(ftmBase, FTM_QDCTRL_QUADMODE_MASK, FTM_QDCTRL_QUADMODE(quadMode));
1110 }
1111 
1123 static inline bool FTM_DRV_GetQuadDir(const FTM_Type * ftmBase)
1124 {
1125  return (ftmBase->QDCTRL & FTM_QDCTRL_QUADIR_MASK) != 0U;
1126 }
1127 
1139 static inline bool FTM_DRV_GetQuadTimerOverflowDir(const FTM_Type * ftmBase)
1140 {
1141  return (ftmBase->QDCTRL & FTM_QDCTRL_TOFDIR_MASK) != 0U;
1142 }
1143 
1155 static inline void FTM_DRV_SetDualChnInvertCmd(FTM_Type * const ftmBase,
1156  uint8_t chnlPairNum,
1157  bool enable)
1158 {
1159  DEV_ASSERT(chnlPairNum < (FEATURE_FTM_CHANNEL_COUNT >> 1U));
1160 
1161  if (enable)
1162  {
1163  ((ftmBase)->INVCTRL) |= (1UL << chnlPairNum);
1164  }
1165  else
1166  {
1167  ((ftmBase)->INVCTRL) &= ~(1UL << chnlPairNum);
1168  }
1169 }
1170 
1171 /*FTM software output control*/
1182 static inline void FTM_DRV_SetChnSoftwareCtrlCmd(FTM_Type * const ftmBase,
1183  uint8_t channel,
1184  bool enable)
1185 {
1187 
1188  if (enable)
1189  {
1190  ((ftmBase)->SWOCTRL) |= (1UL << channel);
1191  }
1192  else
1193  {
1194  ((ftmBase)->SWOCTRL) &= ~(1UL << channel);
1195  }
1196 }
1197 
1209 static inline void FTM_DRV_SetChnSoftwareCtrlVal(FTM_Type * const ftmBase,
1210  uint8_t channel,
1211  bool enable)
1212 {
1214 
1215  if (enable)
1216  {
1217  ((ftmBase)->SWOCTRL) |= (1UL << (channel + FTM_SWOCTRL_CH0OCV_SHIFT));
1218  }
1219  else
1220  {
1221  ((ftmBase)->SWOCTRL) &= ~(1UL << (channel + FTM_SWOCTRL_CH0OCV_SHIFT));
1222  }
1223 }
1224 
1225 /*FTM PWM load control*/
1235 static inline void FTM_DRV_SetGlobalLoadCmd(FTM_Type * const ftmBase)
1236 {
1237  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_GLDOK_SHIFT);
1238 }
1239 
1250 static inline void FTM_DRV_SetLoadCmd(FTM_Type * const ftmBase,
1251  bool enable)
1252 {
1253  if (enable)
1254  {
1255  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_GLEN_SHIFT);
1256  }
1257  else
1258  {
1259  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_GLEN_SHIFT);
1260  }
1261 }
1262 
1273 static inline void FTM_DRV_SetHalfCycleCmd(FTM_Type * const ftmBase,
1274  bool enable)
1275 {
1276  if (enable)
1277  {
1278  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_HCSEL_SHIFT);
1279  }
1280  else
1281  {
1282  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_HCSEL_SHIFT);
1283  }
1284 }
1285 
1296 static inline void FTM_DRV_SetPwmLoadCmd(FTM_Type * const ftmBase,
1297  bool enable)
1298 {
1299  if (enable)
1300  {
1301  ((ftmBase)->PWMLOAD) |= (1UL << FTM_PWMLOAD_LDOK_SHIFT);
1302  }
1303  else
1304  {
1305  ((ftmBase)->PWMLOAD) &= ~(1UL << FTM_PWMLOAD_LDOK_SHIFT);
1306  }
1307 }
1308 
1320 static inline void FTM_DRV_SetPwmLoadChnSelCmd(FTM_Type * const ftmBase,
1321  uint8_t channel,
1322  bool enable)
1323 {
1325 
1326  if (enable)
1327  {
1328  ((ftmBase)->PWMLOAD) |= (1UL << channel);
1329  }
1330  else
1331  {
1332  ((ftmBase)->PWMLOAD) &= ~(1UL << channel);
1333  }
1334 }
1335 
1336 /*FTM configuration*/
1347 static inline void FTM_DRV_SetInitTrigOnReloadCmd(FTM_Type * const ftmBase,
1348  bool enable)
1349 {
1350  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_ITRIGR_MASK) | FTM_CONF_ITRIGR(enable);
1351 }
1352 
1363 static inline void FTM_DRV_SetGlobalTimeBaseOutputCmd(FTM_Type * const ftmBase,
1364  bool enable)
1365 {
1366  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_GTBEOUT_MASK) | FTM_CONF_GTBEOUT(enable);
1367 }
1368 
1379 static inline void FTM_DRV_SetGlobalTimeBaseCmd(FTM_Type * const ftmBase,
1380  bool enable)
1381 {
1382  ftmBase->CONF = (ftmBase->CONF & ~FTM_CONF_GTBEEN_MASK) | FTM_CONF_GTBEEN(enable);
1383 }
1384 
1393 static inline void FTM_DRV_SetLoadFreq(FTM_Type * const ftmBase,
1394  uint8_t val)
1395 {
1396  FTM_RMW_CONF(ftmBase, FTM_CONF_LDFQ_MASK, FTM_CONF_LDFQ(val));
1397 }
1398 
1408 static inline void FTM_DRV_SetExtPairDeadtimeValue(FTM_Type * const ftmBase,
1409  uint8_t channelPair,
1410  uint8_t value)
1411 {
1412  DEV_ASSERT(value < 16U);
1413  DEV_ASSERT(channelPair < CHAN4_IDX);
1414 
1415  switch (channelPair)
1416  {
1417  case CHAN0_IDX:
1418  FTM_RMW_PAIR0DEADTIME(ftmBase, FTM_PAIR0DEADTIME_DTVALEX_MASK, FTM_PAIR0DEADTIME_DTVALEX(value));
1419  break;
1420  case CHAN1_IDX:
1421  FTM_RMW_PAIR1DEADTIME(ftmBase, FTM_PAIR1DEADTIME_DTVALEX_MASK, FTM_PAIR1DEADTIME_DTVALEX(value));
1422  break;
1423  case CHAN2_IDX:
1424  FTM_RMW_PAIR2DEADTIME(ftmBase, FTM_PAIR2DEADTIME_DTVALEX_MASK, FTM_PAIR2DEADTIME_DTVALEX(value));
1425  break;
1426  case CHAN3_IDX:
1427  FTM_RMW_PAIR3DEADTIME(ftmBase, FTM_PAIR3DEADTIME_DTVALEX_MASK, FTM_PAIR3DEADTIME_DTVALEX(value));
1428  break;
1429  default:
1430  /* Nothing to do */
1431  break;
1432  }
1433 }
1434 
1447 static inline void FTM_DRV_SetPairDeadtimePrescale(FTM_Type * const ftmBase,
1448  uint8_t channelPair,
1449  ftm_deadtime_ps_t divider)
1450 {
1451  DEV_ASSERT(channelPair < CHAN4_IDX);
1452 
1453  switch (channelPair)
1454  {
1455  case CHAN0_IDX:
1456  FTM_RMW_PAIR0DEADTIME(ftmBase, FTM_PAIR0DEADTIME_DTPS_MASK, FTM_PAIR0DEADTIME_DTPS((uint8_t)divider));
1457  break;
1458  case CHAN1_IDX:
1459  FTM_RMW_PAIR1DEADTIME(ftmBase, FTM_PAIR1DEADTIME_DTPS_MASK, FTM_PAIR1DEADTIME_DTPS((uint8_t)divider));
1460  break;
1461  case CHAN2_IDX:
1462  FTM_RMW_PAIR2DEADTIME(ftmBase, FTM_PAIR2DEADTIME_DTPS_MASK, FTM_PAIR2DEADTIME_DTPS((uint8_t)divider));
1463  break;
1464  case CHAN3_IDX:
1465  FTM_RMW_PAIR3DEADTIME(ftmBase, FTM_PAIR3DEADTIME_DTPS_MASK, FTM_PAIR3DEADTIME_DTPS((uint8_t)divider));
1466  break;
1467  default:
1468  /* Nothing to do */
1469  break;
1470  }
1471 }
1472 
1486 static inline void FTM_DRV_SetPairDeadtimeCount(FTM_Type * const ftmBase,
1487  uint8_t channelPair,
1488  uint8_t count)
1489 {
1490  DEV_ASSERT(channelPair < CHAN4_IDX);
1491  DEV_ASSERT(count < 64U);
1492 
1493  switch (channelPair)
1494  {
1495  case CHAN0_IDX:
1496  FTM_RMW_PAIR0DEADTIME(ftmBase, FTM_PAIR0DEADTIME_DTVAL_MASK, FTM_PAIR0DEADTIME_DTVAL(count));
1497  break;
1498  case CHAN1_IDX:
1499  FTM_RMW_PAIR1DEADTIME(ftmBase, FTM_PAIR1DEADTIME_DTVAL_MASK, FTM_PAIR1DEADTIME_DTVAL(count));
1500  break;
1501  case CHAN2_IDX:
1502  FTM_RMW_PAIR2DEADTIME(ftmBase, FTM_PAIR2DEADTIME_DTVAL_MASK, FTM_PAIR2DEADTIME_DTVAL(count));
1503  break;
1504  case CHAN3_IDX:
1505  FTM_RMW_PAIR3DEADTIME(ftmBase, FTM_PAIR3DEADTIME_DTVAL_MASK, FTM_PAIR3DEADTIME_DTVAL(count));
1506  break;
1507  default:
1508  /* Nothing to do */
1509  break;
1510  }
1511 }
1512 
1513 #if FEATURE_FTM_HAS_SUPPORTED_DITHERING
1514 
1522 static inline void FTM_DRV_SetMirrorMod(FTM_Type * const ftmBase,
1523  uint16_t value)
1524 {
1525  FTM_RMW_MOD_MIRROR(ftmBase, FTM_MOD_MIRROR_MOD_MASK, FTM_MOD_MIRROR_MOD(value));
1526 }
1527 
1537 static inline uint16_t FTM_DRV_GetMirrorMod(const FTM_Type * ftmBase)
1538 {
1539  return (uint16_t)((((ftmBase)->MOD_MIRROR) & FTM_MOD_MIRROR_MOD_MASK) >> FTM_MOD_MIRROR_MOD_SHIFT);
1540 }
1541 
1551 static inline uint8_t FTM_DRV_GetModFracVal(const FTM_Type * ftmBase)
1552 {
1553  return (uint8_t)((((ftmBase)->MOD_MIRROR) & FTM_MOD_MIRROR_FRACMOD_MASK) >> FTM_MOD_MIRROR_FRACMOD_SHIFT);
1554 }
1555 
1565 static inline void FTM_DRV_SetMirrorChnMatchVal(FTM_Type * const ftmBase,
1566  uint8_t channel,
1567  uint16_t value)
1568 {
1569  FTM_RMW_CnV_MIRROR(ftmBase, channel, FTM_CV_MIRROR_VAL_MASK, FTM_CV_MIRROR_VAL(value));
1570 }
1571 
1582 static inline uint16_t FTM_DRV_GetMirrorChnMatchVal(const FTM_Type * ftmBase,
1583  uint8_t channel)
1584 {
1585  return (uint16_t)((((ftmBase)->CV_MIRROR[channel]) & FTM_CV_MIRROR_VAL_MASK) >> FTM_CV_MIRROR_VAL_SHIFT);
1586 }
1587 
1598 static inline uint8_t FTM_DRV_GetChnMatchFracVal(const FTM_Type * ftmBase,
1599  uint8_t channel)
1600 {
1601  return (uint8_t)((((ftmBase)->CV_MIRROR[channel]) & FTM_CV_MIRROR_FRACVAL_MASK) >> FTM_CV_MIRROR_FRACVAL_SHIFT);
1602 }
1603 #endif
1604 
1615 status_t FTM_DRV_Init(uint32_t instance,
1616  const ftm_user_config_t * info,
1617  ftm_state_t * state);
1618 
1627 status_t FTM_DRV_Deinit(uint32_t instance);
1628 
1640 status_t FTM_DRV_MaskOutputChannels(uint32_t instance,
1641  uint32_t channelsMask,
1642  bool softwareTrigger);
1643 
1656 status_t FTM_DRV_SetInitialCounterValue(uint32_t instance,
1657  uint16_t counterValue,
1658  bool softwareTrigger);
1659 
1670 status_t FTM_DRV_SetHalfCycleReloadPoint(uint32_t instance,
1671  uint16_t reloadPoint,
1672  bool softwareTrigger);
1673 
1687 status_t FTM_DRV_SetSoftOutChnValue(uint32_t instance,
1688  uint8_t channelsValues,
1689  bool softwareTrigger);
1690 
1702  uint8_t channelsMask,
1703  bool softwareTrigger);
1704 
1715 status_t FTM_DRV_SetInvertingControl(uint32_t instance,
1716  uint8_t channelsPairMask,
1717  bool softwareTrigger);
1718 
1729 status_t FTM_DRV_SetModuloCounterValue(uint32_t instance,
1730  uint16_t counterValue,
1731  bool softwareTrigger);
1732 
1743 status_t FTM_DRV_SetSync(uint32_t instance,
1744  const ftm_pwm_sync_t * param);
1745 
1754 uint32_t FTM_DRV_GetFrequency(uint32_t instance);
1755 
1764 uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance,
1765  uint32_t freqencyHz);
1766 
1767 #if defined(__cplusplus)
1768 }
1769 #endif
1770  /* End of addtogroup ftm_common */
1774 
1775 #endif /* FTM_COMMON_H */
1776 /*******************************************************************************
1777  * EOF
1778  ******************************************************************************/
__IO uint32_t CnSC
Definition: S32K142.h:3902
const IRQn_Type g_ftmOverflowIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_common.c:75
static bool FTM_DRV_GetQuadDir(const FTM_Type *ftmBase)
Gets the FTM counter direction in quadrature mode.
Definition: ftm_common.h:1123
static uint16_t FTM_DRV_GetCounterInitVal(const FTM_Type *ftmBase)
Returns the FTM peripheral counter initial value.
Definition: ftm_common.h:386
#define FTM_QDCTRL_TOFDIR_MASK
Definition: S32K142.h:4590
#define FTM_SC_RIE_MASK
Definition: S32K142.h:4004
#define FTM_QDCTRL_QUADMODE_MASK
Definition: S32K142.h:4598
static void FTM_DRV_SetCaptureTestCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM peripheral timer capture test mode.
Definition: ftm_common.h:829
ftm_reg_update_t initCounterSync
Definition: ftm_common.h:154
static void FTM_DRV_SetChnIcrstCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Configure the feature of FTM counter reset by the selected input capture event.
Definition: ftm_common.h:468
#define FTM_FMS_FAULTF0_MASK
Definition: S32K142.h:4499
status_t FTM_DRV_SetSoftwareOutputChannelControl(uint32_t instance, uint8_t channelsMask, bool softwareTrigger)
This function will configure which output channel can be software controlled.
Definition: ftm_common.c:298
#define FTM_SC_CLKS_SHIFT
Definition: S32K142.h:3997
ftm_pwm_sync_t syncMethod
Definition: ftm_common.h:167
static void FTM_DRV_SetPwmLoadCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer.
Definition: ftm_common.h:1296
static uint16_t FTM_DRV_GetChnCountVal(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel counter value.
Definition: ftm_common.h:660
#define FTM_CONF_GTBEOUT_MASK
Definition: S32K142.h:4631
FlexTimer state structure of the driver.
Definition: ftm_common.h:121
static void FTM_DRV_SetQuadPhaseBFilterCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the phase B input filter.
Definition: ftm_common.h:1051
static bool FTM_DRV_GetChOutputValue(const FTM_Type *ftmBase, uint8_t channel)
Get the value of channel output.
Definition: ftm_common.h:642
#define FTM_SC_RF(x)
Definition: S32K142.h:4011
static void FTM_DRV_SetChnSoftwareCtrlCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the channel software output control.
Definition: ftm_common.h:1182
#define FTM_SC_TOIE_SHIFT
Definition: S32K142.h:4013
static bool FTM_DRV_IsChnIcrst(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the FTM FTM counter is reset.
Definition: ftm_common.h:489
static void FTM_DRV_ClearChnTriggerFlag(FTM_Type *const ftmBase)
Clear the channel trigger flag.
Definition: ftm_common.h:945
status_t FTM_DRV_SetSync(uint32_t instance, const ftm_pwm_sync_t *param)
This function configures sync mechanism for some FTM registers (MOD, CNINT, HCR, CnV, OUTMASK, INVCTRL, SWOCTRL).
Definition: ftm_common.c:370
#define FTM_PWMLOAD_GLEN_SHIFT
Definition: S32K142.h:4841
static void FTM_DRV_SetPwmLoadChnSelCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Includes or excludes the channel in the matching process.
Definition: ftm_common.h:1320
#define FTM_CnSC_ELSB_SHIFT
Definition: S32K142.h:4080
#define FTM_FMS_FAULTF_MASK
Definition: S32K142.h:4523
ftm_bdm_mode_t BDMMode
Definition: ftm_common.h:173
#define FTM_PAIR3DEADTIME_DTVALEX_MASK
Definition: S32K142.h:4901
bool hardwareSync2
Definition: ftm_common.h:145
#define FTM_PWMLOAD_HCSEL_SHIFT
Definition: S32K142.h:4833
static bool FTM_DRV_IsWriteProtectionEnabled(const FTM_Type *ftmBase)
Checks whether the write protection is enabled.
Definition: ftm_common.h:980
#define FTM_COMBINE_COMBINE0_MASK
Definition: S32K142.h:4283
Configuration structure that the user needs to set.
Definition: ftm_common.h:165
#define FTM_FMS_FAULTF1_MASK
Definition: S32K142.h:4503
#define FTM_MOD_MOD_MASK
Definition: S32K142.h:4062
#define FTM_MOD_MIRROR_MOD_SHIFT
Definition: S32K142.h:4911
uint16_t ftmPeriod
Definition: ftm_common.h:125
FTM_Type *const g_ftmBase[FTM_INSTANCE_COUNT]
Table of base addresses for FTM instances.
Definition: ftm_common.c:70
static uint8_t FTM_DRV_GetClockPs(const FTM_Type *ftmBase)
Reads the FTM clock divider.
Definition: ftm_common.h:249
static void FTM_DRV_SetChnOutputInitStateCmd(FTM_Type *const ftmBase, uint8_t channel, bool state)
Sets the FTM peripheral timer channel output initial state 0 or 1.
Definition: ftm_common.h:760
#define FTM_PAIR1DEADTIME_DTPS_MASK
Definition: S32K142.h:4871
static bool FTM_DRV_IsChnDma(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the FTM peripheral timer channel DMA is enabled.
Definition: ftm_common.h:529
#define FTM_SC_FLTPS_MASK
Definition: S32K142.h:4052
static bool FTM_DRV_GetCpwms(const FTM_Type *ftmBase)
Gets the FTM count direction bit.
Definition: ftm_common.h:297
FlexTimer Registers sync parameters Please don't use software and hardware trigger simultaneously Imp...
Definition: ftm_common.h:137
ftm_state_t * ftmStatePtr[FTM_INSTANCE_COUNT]
Pointer to runtime state structure.
Definition: ftm_common.c:83
#define FTM_SWOCTRL_CH0OCV_SHIFT
Definition: S32K142.h:4768
#define FTM_FMS_FAULTF3(x)
Definition: S32K142.h:4514
status_t FTM_DRV_SetInitialCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the initial counter value. The counter will get this value after an overflow ...
Definition: ftm_common.c:225
#define FTM_PAIR3DEADTIME_DTVAL(x)
Definition: S32K142.h:4896
#define FTM_MOD_MIRROR_FRACMOD_SHIFT
Definition: S32K142.h:4907
static uint8_t FTM_DRV_GetChnEdgeLevel(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel edge level.
Definition: ftm_common.h:444
#define FTM_MOD_MIRROR_FRACMOD_MASK
Definition: S32K142.h:4906
bool hardwareSync1
Definition: ftm_common.h:143
static void FTM_DRV_SetGlobalTimeBaseOutputCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM global time base signal generation to other FTM's.
Definition: ftm_common.h:1363
#define FTM_CONF_GTBEEN_MASK
Definition: S32K142.h:4627
static void FTM_DRV_ClearFaultsIsr(FTM_Type *const ftmBase)
Clears all fault interrupt flags that are active.
Definition: ftm_common.h:807
static bool FTM_DRV_HasTimerOverflowed(const FTM_Type *ftmBase)
Returns the FTM peripheral timer overflow interrupt flag.
Definition: ftm_common.h:281
#define FTM_PAIR3DEADTIME_DTPS_MASK
Definition: S32K142.h:4897
#define FTM_SC_TOF_MASK
Definition: S32K142.h:4016
#define FTM_QDCTRL_PHAPOL(x)
Definition: S32K142.h:4609
static bool FTM_DRV_IsChnIntEnabled(const FTM_Type *ftmBase, uint8_t channel)
Get FTM channel(n) interrupt enabled or not.
Definition: ftm_common.h:544
static uint8_t FTM_DRV_GetClockFilterPs(const FTM_Type *ftmBase)
Reads the FTM filter clock divider.
Definition: ftm_common.h:217
static bool FTM_DRV_IsChnTriggerGenerated(const FTM_Type *ftmBase)
Checks whether any channel trigger event has occurred.
Definition: ftm_common.h:933
status_t FTM_DRV_SetHalfCycleReloadPoint(uint32_t instance, uint16_t reloadPoint, bool softwareTrigger)
This function configure the value of the counter which will generates an reload point.
Definition: ftm_common.c:249
#define FTM_SC_CLKS_MASK
Definition: S32K142.h:3996
#define FTM_CnSC_TRIGMODE(x)
Definition: S32K142.h:4102
static void FTM_DRV_SetCountReinitSyncCmd(FTM_Type *const ftmBase, bool enable)
Determines if the FTM counter is re-initialized when the selected trigger for synchronization is dete...
Definition: ftm_common.h:877
#define FTM_SC_TOF_SHIFT
Definition: S32K142.h:4017
#define FEATURE_FTM_CHANNEL_COUNT
#define FTM_CONF_GTBEOUT(x)
Definition: S32K142.h:4634
#define FTM_CNTIN_INIT_MASK
Definition: S32K142.h:4117
static void FTM_DRV_SetInitChnOutputCmd(FTM_Type *const ftmBase, bool enable)
Initializes the channels output.
Definition: ftm_common.h:860
#define FTM_PAIR2DEADTIME_DTVALEX_MASK
Definition: S32K142.h:4888
static uint8_t FTM_DRV_GetChnMode(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel mode.
Definition: ftm_common.h:421
#define FTM_CNTIN_INIT_SHIFT
Definition: S32K142.h:4118
#define FTM_MODE_FAULTIE_MASK
Definition: S32K142.h:4179
static bool FTM_DRV_GetChnEventStatus(const FTM_Type *ftmBase, uint8_t channel)
Gets the FTM peripheral timer channel event status.
Definition: ftm_common.h:680
#define FTM_MOD_MIRROR_MOD(x)
Definition: S32K142.h:4913
static bool FTM_DRV_GetDualChnCombineCmd(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Verify if an channels pair is used in combine mode or not.
Definition: ftm_common.h:915
#define DEV_ASSERT(x)
Definition: devassert.h:77
static void FTM_DRV_ClearReloadFlag(FTM_Type *const ftmBase)
Clears the reload flag bit.
Definition: ftm_common.h:340
__IO uint32_t MODE
Definition: S32K142.h:3907
static void FTM_DRV_SetExtPairDeadtimeValue(FTM_Type *const ftmBase, uint8_t channelPair, uint8_t value)
Sets the FTM extended dead-time value for the channel pair.
Definition: ftm_common.h:1408
#define FTM_MODE_INIT_MASK
Definition: S32K142.h:4159
#define FTM_MODE_FAULTIE(x)
Definition: S32K142.h:4182
uint32_t FTM_DRV_GetFrequency(uint32_t instance)
Retrieves the frequency of the clock source feeding the FTM counter.
Definition: ftm_common.c:446
#define FTM_SC_PS_SHIFT
Definition: S32K142.h:3993
#define FTM_PAIR1DEADTIME_DTVAL(x)
Definition: S32K142.h:4870
#define FTM_PWMLOAD_GLDOK_SHIFT
Definition: S32K142.h:4845
uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance, uint32_t freqencyHz)
This function is used to covert the given frequency to period in ticks.
Definition: ftm_common.c:501
static uint8_t FTM_DRV_GetClockSource(const FTM_Type *ftmBase)
Reads the FTM clock source.
Definition: ftm_common.h:235
#define FTM_MODE_INIT(x)
Definition: S32K142.h:4162
__IO uint32_t EXTTRIG
Definition: S32K142.h:3913
#define FTM_FMS_WPEN_MASK
Definition: S32K142.h:4519
__IO uint32_t STATUS
Definition: S32K142.h:3906
#define FTM_PAIR1DEADTIME_DTPS(x)
Definition: S32K142.h:4874
#define FTM_PAIR1DEADTIME_DTVAL_MASK
Definition: S32K142.h:4867
#define FTM_CnSC_MSB_SHIFT
Definition: S32K142.h:4088
#define FTM_PAIR2DEADTIME_DTPS(x)
Definition: S32K142.h:4887
#define FTM_QDCTRL_QUADIR_MASK
Definition: S32K142.h:4594
#define FTM_CnSC_ELSA_MASK
Definition: S32K142.h:4075
static void FTM_DRV_SetLoadCmd(FTM_Type *const ftmBase, bool enable)
Enable the global load.
Definition: ftm_common.h:1250
#define FTM_QDCTRL_QUADMODE(x)
Definition: S32K142.h:4601
#define FTM_MODE_FAULTIE_SHIFT
Definition: S32K142.h:4180
static void FTM_DRV_SetQuadPhaseAPolarity(FTM_Type *const ftmBase, ftm_quad_phase_polarity_t mode)
Selects polarity for the quadrature decode phase A input.
Definition: ftm_common.h:1074
const IRQn_Type g_ftmReloadIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_common.c:76
#define FTM_FMS_FAULTF0(x)
Definition: S32K142.h:4502
ftm_clock_source_t ftmClockSource
Definition: ftm_common.h:123
static bool FTM_DRV_GetReloadFlag(const FTM_Type *ftmBase)
Get the state whether the FTM counter reached a reload point.
Definition: ftm_common.h:328
bool hardwareSync0
Definition: ftm_common.h:141
#define FTM_EXTTRIG_TRIGF_MASK
Definition: S32K142.h:4453
static bool FTM_DRV_GetQuadTimerOverflowDir(const FTM_Type *ftmBase)
Gets the Timer overflow direction in quadrature mode.
Definition: ftm_common.h:1139
#define FTM_PAIR0DEADTIME_DTVALEX_MASK
Definition: S32K142.h:4862
static void FTM_DRV_SetChnDmaCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the FTM peripheral timer channel DMA.
Definition: ftm_common.h:508
static void FTM_DRV_SetClockFilterPs(FTM_Type *const ftmBase, uint8_t filterPrescale)
Sets the filter Pre-scaler divider.
Definition: ftm_common.h:202
#define FTM_CnSC_CHF_MASK
Definition: S32K142.h:4095
__IO uint32_t CONF
Definition: S32K142.h:3919
#define FTM_QDCTRL_PHBFLTREN_SHIFT
Definition: S32K142.h:4611
ftm_pwm_sync_mode_t syncPoint
Definition: ftm_common.h:156
static void FTM_DRV_SetGlobalLoadCmd(FTM_Type *const ftmBase)
Set the global load mechanism.
Definition: ftm_common.h:1235
#define FTM_CV_MIRROR_VAL(x)
Definition: S32K142.h:4922
static void FTM_DRV_SetInitTrigOnReloadCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM initialization trigger on Reload Point.
Definition: ftm_common.h:1347
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
static void FTM_DRV_ClearChSC(FTM_Type *const ftmBase, uint8_t channel)
Clears the content of Channel (n) Status And Control.
Definition: ftm_common.h:399
#define FTM_MOD_MOD_SHIFT
Definition: S32K142.h:4063
#define FTM_CnSC_CHIE_MASK
Definition: S32K142.h:4091
#define FTM_SC_FLTPS(x)
Definition: S32K142.h:4055
#define FTM_SC_CPWMS_MASK
Definition: S32K142.h:4000
static void FTM_DRV_SetChnSoftwareCtrlVal(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Sets the channel software output control value.
Definition: ftm_common.h:1209
#define FTM_CnSC_ELSB_MASK
Definition: S32K142.h:4079
ftm_quad_phase_polarity_t
FlexTimer quadrature phase polarities, normal or inverted polarity.
Definition: ftm_common.h:100
#define FTM_SC_PS_MASK
Definition: S32K142.h:3992
struct FTM_Type::@12 CONTROLS[FTM_CONTROLS_COUNT]
#define FTM_QDCTRL_PHBPOL_MASK
Definition: S32K142.h:4602
static void FTM_DRV_SetDualChnInvertCmd(FTM_Type *const ftmBase, uint8_t chnlPairNum, bool enable)
Enables or disables the channel invert for a channel pair.
Definition: ftm_common.h:1155
bool maxLoadingPoint
Definition: ftm_common.h:147
#define FTM_MODE_CAPTEST_MASK
Definition: S32K142.h:4171
#define FTM_INSTANCE_COUNT
Definition: S32K142.h:3939
#define FTM_SC_RF_MASK
Definition: S32K142.h:4008
status_t FTM_DRV_SetInvertingControl(uint32_t instance, uint8_t channelsPairMask, bool softwareTrigger)
This function will configure if the second channel of a pair will be inverted or not.
Definition: ftm_common.c:321
#define FTM_CV_MIRROR_VAL_MASK
Definition: S32K142.h:4919
#define FTM_PAIR0DEADTIME_DTVAL_MASK
Definition: S32K142.h:4854
static bool FTM_DRV_GetDualEdgeCaptureBit(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Enables the FTM peripheral timer dual edge capture mode.
Definition: ftm_common.h:895
#define FTM_CONF_ITRIGR_MASK
Definition: S32K142.h:4635
static void FTM_DRV_SetTrigModeControlCmd(FTM_Type *const ftmBase, uint8_t channel, bool enable)
Enables or disables the trigger generation on FTM channel outputs.
Definition: ftm_common.h:583
#define FTM_PAIR3DEADTIME_DTVAL_MASK
Definition: S32K142.h:4893
ftm_quad_decode_mode_t
FlexTimer quadrature decode modes, phase encode or count and direction mode.
Definition: ftm_common.h:89
#define FTM_CnSC_ELSA_SHIFT
Definition: S32K142.h:4076
bool enableInitializationTrigger
Definition: ftm_common.h:176
#define FTM_PAIR0DEADTIME_DTPS_MASK
Definition: S32K142.h:4858
#define FTM_PAIR3DEADTIME_DTPS(x)
Definition: S32K142.h:4900
void(* ftm_channel_event_callback_t)(void *userData)
Channel event callback function.
Definition: ftm_common.h:114
#define FTM_PAIR1DEADTIME_DTVALEX(x)
Definition: S32K142.h:4878
static uint32_t FTM_DRV_GetEventStatus(const FTM_Type *ftmBase)
Gets the FTM peripheral timer status info for all channels.
Definition: ftm_common.h:697
#define FTM_SC_TOIE_MASK
Definition: S32K142.h:4012
#define FTM_QDCTRL_PHBPOL(x)
Definition: S32K142.h:4605
ftm_reg_update_t inverterSync
Definition: ftm_common.h:151
static bool FTM_DRV_IsFaultIntEnabled(const FTM_Type *ftmBase)
Return true/false whether the Fault interrupt was enabled or not.
Definition: ftm_common.h:795
#define FTM_CnSC_DMA(x)
Definition: S32K142.h:4070
#define FTM_MODE_CAPTEST(x)
Definition: S32K142.h:4174
#define FTM_CV_MIRROR_FRACVAL_MASK
Definition: S32K142.h:4915
#define FTM_PAIR3DEADTIME_DTVALEX(x)
Definition: S32K142.h:4904
#define FTM_CnSC_CHOV_MASK
Definition: S32K142.h:4107
static void FTM_DRV_SetQuadPhaseBPolarity(FTM_Type *const ftmBase, ftm_quad_phase_polarity_t mode)
Selects polarity for the quadrature decode phase B input.
Definition: ftm_common.h:1090
const IRQn_Type g_ftmFaultIrqId[FTM_INSTANCE_COUNT]
Definition: ftm_common.c:74
#define FTM_CnSC_MSA_SHIFT
Definition: S32K142.h:4084
ftm_config_mode_t ftmMode
Definition: ftm_common.h:124
#define FTM_FMS_FAULTF2(x)
Definition: S32K142.h:4510
static void FTM_DRV_SetLoadFreq(FTM_Type *const ftmBase, uint8_t val)
Sets the FTM timer TOF Frequency.
Definition: ftm_common.h:1393
#define FTM_COMBINE_DECAPEN0_MASK
Definition: S32K142.h:4291
static bool FTM_DRV_IsFtmEnable(const FTM_Type *ftmBase)
Get status of the FTMEN bit in the FTM_MODE register.
Definition: ftm_common.h:845
#define FTM_SC_CPWMS_SHIFT
Definition: S32K142.h:4001
static void FTM_DRV_SetGlobalTimeBaseCmd(FTM_Type *const ftmBase, bool enable)
Enables or disables the FTM timer global time base.
Definition: ftm_common.h:1379
static void FTM_DRV_SetHalfCycleCmd(FTM_Type *const ftmBase, bool enable)
Enable the half cycle reload.
Definition: ftm_common.h:1273
#define FTM_SYNC_REINIT_MASK
Definition: S32K142.h:4192
#define FTM_FMS_FAULTF3_MASK
Definition: S32K142.h:4511
static bool FTM_DRV_GetChInputState(const FTM_Type *ftmBase, uint8_t channel)
Get the state of channel input.
Definition: ftm_common.h:623
#define FTM_FMS_FAULTF1(x)
Definition: S32K142.h:4506
#define FTM_CnSC_CHIS_MASK
Definition: S32K142.h:4103
#define FTM_PAIR0DEADTIME_DTPS(x)
Definition: S32K142.h:4861
status_t FTM_DRV_SetModuloCounterValue(uint32_t instance, uint16_t counterValue, bool softwareTrigger)
This function configure the maximum counter value.
Definition: ftm_common.c:344
#define FTM_CONF_GTBEEN(x)
Definition: S32K142.h:4630
#define FTM_CnSC_TRIGMODE_MASK
Definition: S32K142.h:4099
__IO uint32_t FMS
Definition: S32K142.h:3915
#define FTM_CONF_ITRIGR(x)
Definition: S32K142.h:4638
ftm_config_mode_t ftmMode
Definition: ftm_common.h:169
static void FTM_DRV_SetChnOutputMask(FTM_Type *const ftmBase, uint8_t channel, bool mask)
Sets the FTM peripheral timer channel output mask.
Definition: ftm_common.h:733
#define FTM_CV_MIRROR_VAL_SHIFT
Definition: S32K142.h:4920
#define FTM_CONF_LDFQ_MASK
Definition: S32K142.h:4619
static void FTM_DRV_SetQuadMode(FTM_Type *const ftmBase, ftm_quad_decode_mode_t quadMode)
Sets the encoding mode used in quadrature decoding mode.
Definition: ftm_common.h:1106
#define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH
static void FTM_DRV_SetReIntEnabledCmd(FTM_Type *const ftmBase, bool enable)
Set the FTM reload interrupt enable.
Definition: ftm_common.h:311
status_t FTM_DRV_Deinit(uint32_t instance)
Shuts down the FTM driver.
Definition: ftm_common.c:181
#define FTM_FMS_FAULTIN_MASK
Definition: S32K142.h:4515
#define FTM_CnSC_ICRST(x)
Definition: S32K142.h:4074
static bool FTM_DRV_HasChnEventOccurred(const FTM_Type *ftmBase, uint8_t channel)
Returns whether any event for the FTM peripheral timer channel has occurred.
Definition: ftm_common.h:564
status_t FTM_DRV_MaskOutputChannels(uint32_t instance, uint32_t channelsMask, bool softwareTrigger)
This function will mask the output of the channels and at match events will be ignored by the masked ...
Definition: ftm_common.c:201
#define FTM_EXTTRIG_TRIGF(x)
Definition: S32K142.h:4456
ftm_reg_update_t maskRegSync
Definition: ftm_common.h:153
#define FTM_SC_RIE(x)
Definition: S32K142.h:4007
#define FTM_MOD_MIRROR_MOD_MASK
Definition: S32K142.h:4910
#define FTM_PAIR2DEADTIME_DTVAL(x)
Definition: S32K142.h:4883
#define FTM_SYNC_REINIT(x)
Definition: S32K142.h:4195
static void FTM_DRV_ClearChnEventStatus(FTM_Type *const ftmBase, uint8_t channel)
Clears the FTM peripheral timer all channel event status.
Definition: ftm_common.h:710
#define FTM_CnSC_ICRST_MASK
Definition: S32K142.h:4071
#define FTM_PAIR1DEADTIME_DTVALEX_MASK
Definition: S32K142.h:4875
#define FTM_MODE_FTMEN_SHIFT
Definition: S32K142.h:4156
static uint16_t FTM_DRV_GetMod(const FTM_Type *ftmBase)
Returns the FTM peripheral counter modulo value.
Definition: ftm_common.h:372
bool minLoadingPoint
Definition: ftm_common.h:149
#define FTM_CnSC_DMA_MASK
Definition: S32K142.h:4067
bool autoClearTrigger
Definition: ftm_common.h:155
static bool FTM_DRV_IsFaultFlagDetected(const FTM_Type *ftmBase, uint8_t channel)
Checks whether a fault condition is detected at the fault input.
Definition: ftm_common.h:1013
#define FTM_CnSC_MSA_MASK
Definition: S32K142.h:4083
#define FTM_SC_RF_SHIFT
Definition: S32K142.h:4009
status_t FTM_DRV_Init(uint32_t instance, const ftm_user_config_t *info, ftm_state_t *state)
Initializes the FTM driver.
Definition: ftm_common.c:112
status_t FTM_DRV_SetSoftOutChnValue(uint32_t instance, uint8_t channelsValues, bool softwareTrigger)
This function will force the output value of a channel to a specific value. Before using this functio...
Definition: ftm_common.c:275
static void FTM_DRV_SetPairDeadtimeCount(FTM_Type *const ftmBase, uint8_t channelPair, uint8_t count)
Sets the FTM dead-time value for the channel pair.
Definition: ftm_common.h:1486
__IO uint32_t QDCTRL
Definition: S32K142.h:3918
#define FTM_PAIR2DEADTIME_DTVALEX(x)
Definition: S32K142.h:4891
#define FTM_PAIR0DEADTIME_DTVAL(x)
Definition: S32K142.h:4857
#define FTM_CNT_COUNT_SHIFT
Definition: S32K142.h:4058
#define FTM_QDCTRL_PHAPOL_MASK
Definition: S32K142.h:4606
#define FTM_CONF_LDFQ(x)
Definition: S32K142.h:4622
#define FTM_PWMLOAD_LDOK_SHIFT
Definition: S32K142.h:4837
#define FTM_MODE_FTMEN_MASK
Definition: S32K142.h:4155
static void FTM_DRV_DisableFaultInt(FTM_Type *const ftmBase)
Disables the FTM peripheral timer fault interrupt.
Definition: ftm_common.h:783
static bool FTM_DRV_GetDetectedFaultInput(const FTM_Type *ftmBase)
Gets the FTM detected fault input.
Definition: ftm_common.h:964
static bool FTM_DRV_IsFaultInputEnabled(const FTM_Type *ftmBase)
Checks whether the logic OR of the fault inputs is enabled.
Definition: ftm_common.h:996
__IO uint32_t SC
Definition: S32K142.h:3898
#define FTM_PAIR2DEADTIME_DTPS_MASK
Definition: S32K142.h:4884
#define FTM_PAIR2DEADTIME_DTVAL_MASK
Definition: S32K142.h:4880
ftm_clock_source_t ftmClockSource
Definition: ftm_common.h:172
static void FTM_DRV_SetPairDeadtimePrescale(FTM_Type *const ftmBase, uint8_t channelPair, ftm_deadtime_ps_t divider)
Sets the FTM dead time divider for the channel pair.
Definition: ftm_common.h:1447
#define FTM_FMS_FAULTF(x)
Definition: S32K142.h:4526
#define FTM_CnSC_MSB_MASK
Definition: S32K142.h:4087
ftm_config_mode_t
FlexTimer operation mode.
Definition: ftm_common.h:72
#define FTM_CNT_COUNT_MASK
Definition: S32K142.h:4057
uint32_t ftmSourceClockFrequency
Definition: ftm_common.h:126
const IRQn_Type g_ftmIrqId[FTM_INSTANCE_COUNT][FEATURE_FTM_CHANNEL_COUNT]
Interrupt vectors for the FTM peripheral.
Definition: ftm_common.c:73
#define FTM_CV_MIRROR_FRACVAL_SHIFT
Definition: S32K142.h:4916
ftm_reg_update_t outRegSync
Definition: ftm_common.h:152
#define FTM_SC_FLTPS_SHIFT
Definition: S32K142.h:4053
static bool FTM_DRV_IsOverflowIntEnabled(const FTM_Type *ftmBase)
Reads the bit that controls enabling the FTM timer overflow interrupt.
Definition: ftm_common.h:265
static uint16_t FTM_DRV_GetCounter(const FTM_Type *ftmBase)
Returns the FTM peripheral current counter value.
Definition: ftm_common.h:358
static bool FTM_DRV_GetTriggerControled(const FTM_Type *ftmBase, uint8_t channel)
Returns whether the trigger mode is enabled.
Definition: ftm_common.h:604
ftm_clock_ps_t ftmPrescaler
Definition: ftm_common.h:170
IRQn_Type
Defines the Interrupt Numbers definitions.
Definition: S32K142.h:192
static void FTM_DRV_ClearFaultFlagDetected(FTM_Type *const ftmBase, uint8_t channel)
Clear a fault condition is detected at the fault input.
Definition: ftm_common.h:1029
#define FTM_FMS_FAULTF2_MASK
Definition: S32K142.h:4507
#define FTM_PAIR0DEADTIME_DTVALEX(x)
Definition: S32K142.h:4865