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S32 SDK
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#define S32_SCB_ACTLR_DISDEFWBUF | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISDEFWBUF_SHIFT))&S32_SCB_ACTLR_DISDEFWBUF_MASK) |
#define S32_SCB_ACTLR_DISFOLD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFOLD_SHIFT))&S32_SCB_ACTLR_DISFOLD_MASK) |
#define S32_SCB_ACTLR_DISFPCA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISFPCA_SHIFT))&S32_SCB_ACTLR_DISFPCA_MASK) |
#define S32_SCB_ACTLR_DISMCYCINT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISMCYCINT_SHIFT))&S32_SCB_ACTLR_DISMCYCINT_MASK) |
#define S32_SCB_ACTLR_DISOOFP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ACTLR_DISOOFP_SHIFT))&S32_SCB_ACTLR_DISOOFP_MASK) |
#define S32_SCB_AFSR_AUXFAULT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AFSR_AUXFAULT_SHIFT))&S32_SCB_AFSR_AUXFAULT_MASK) |
#define S32_SCB_AIRCR_ENDIANNESS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_ENDIANNESS_SHIFT))&S32_SCB_AIRCR_ENDIANNESS_MASK) |
#define S32_SCB_AIRCR_PRIGROUP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_PRIGROUP_SHIFT))&S32_SCB_AIRCR_PRIGROUP_MASK) |
#define S32_SCB_AIRCR_SYSRESETREQ | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_SYSRESETREQ_SHIFT))&S32_SCB_AIRCR_SYSRESETREQ_MASK) |
#define S32_SCB_AIRCR_VECTCLRACTIVE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTCLRACTIVE_SHIFT))&S32_SCB_AIRCR_VECTCLRACTIVE_MASK) |
#define S32_SCB_AIRCR_VECTKEY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTKEY_SHIFT))&S32_SCB_AIRCR_VECTKEY_MASK) |
#define S32_SCB_AIRCR_VECTRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_AIRCR_VECTRESET_SHIFT))&S32_SCB_AIRCR_VECTRESET_MASK) |
#define S32_SCB_BFAR_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_BFAR_ADDRESS_SHIFT))&S32_SCB_BFAR_ADDRESS_MASK) |
#define S32_SCB_CCR_BFHFNMIGN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_BFHFNMIGN_SHIFT))&S32_SCB_CCR_BFHFNMIGN_MASK) |
#define S32_SCB_CCR_DIV_0_TRP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_DIV_0_TRP_SHIFT))&S32_SCB_CCR_DIV_0_TRP_MASK) |
#define S32_SCB_CCR_NONBASETHRDENA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_NONBASETHRDENA_SHIFT))&S32_SCB_CCR_NONBASETHRDENA_MASK) |
#define S32_SCB_CCR_STKALIGN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_STKALIGN_SHIFT))&S32_SCB_CCR_STKALIGN_MASK) |
#define S32_SCB_CCR_UNALIGN_TRP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_UNALIGN_TRP_SHIFT))&S32_SCB_CCR_UNALIGN_TRP_MASK) |
#define S32_SCB_CCR_USERSETMPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CCR_USERSETMPEND_SHIFT))&S32_SCB_CCR_USERSETMPEND_MASK) |
#define S32_SCB_CFSR_BFARVALID | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_BFARVALID_SHIFT))&S32_SCB_CFSR_BFARVALID_MASK) |
#define S32_SCB_CFSR_DACCVIOL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DACCVIOL_SHIFT))&S32_SCB_CFSR_DACCVIOL_MASK) |
#define S32_SCB_CFSR_DIVBYZERO | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_DIVBYZERO_SHIFT))&S32_SCB_CFSR_DIVBYZERO_MASK) |
#define S32_SCB_CFSR_IACCVIOL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IACCVIOL_SHIFT))&S32_SCB_CFSR_IACCVIOL_MASK) |
#define S32_SCB_CFSR_IBUSERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IBUSERR_SHIFT))&S32_SCB_CFSR_IBUSERR_MASK) |
#define S32_SCB_CFSR_IMPRECISERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_IMPRECISERR_SHIFT))&S32_SCB_CFSR_IMPRECISERR_MASK) |
#define S32_SCB_CFSR_INVPC | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVPC_SHIFT))&S32_SCB_CFSR_INVPC_MASK) |
#define S32_SCB_CFSR_INVSTATE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_INVSTATE_SHIFT))&S32_SCB_CFSR_INVSTATE_MASK) |
#define S32_SCB_CFSR_LSPERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_LSPERR_SHIFT))&S32_SCB_CFSR_LSPERR_MASK) |
#define S32_SCB_CFSR_MLSPERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MLSPERR_SHIFT))&S32_SCB_CFSR_MLSPERR_MASK) |
#define S32_SCB_CFSR_MMARVALID | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MMARVALID_SHIFT))&S32_SCB_CFSR_MMARVALID_MASK) |
#define S32_SCB_CFSR_MSTKERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MSTKERR_SHIFT))&S32_SCB_CFSR_MSTKERR_MASK) |
#define S32_SCB_CFSR_MUNSTKERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_MUNSTKERR_SHIFT))&S32_SCB_CFSR_MUNSTKERR_MASK) |
#define S32_SCB_CFSR_NOCP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_NOCP_SHIFT))&S32_SCB_CFSR_NOCP_MASK) |
#define S32_SCB_CFSR_PRECISERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_PRECISERR_SHIFT))&S32_SCB_CFSR_PRECISERR_MASK) |
#define S32_SCB_CFSR_STKERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_STKERR_SHIFT))&S32_SCB_CFSR_STKERR_MASK) |
#define S32_SCB_CFSR_UNALIGNED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNALIGNED_SHIFT))&S32_SCB_CFSR_UNALIGNED_MASK) |
#define S32_SCB_CFSR_UNDEFINSTR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNDEFINSTR_SHIFT))&S32_SCB_CFSR_UNDEFINSTR_MASK) |
#define S32_SCB_CFSR_UNSTKERR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CFSR_UNSTKERR_SHIFT))&S32_SCB_CFSR_UNSTKERR_MASK) |
#define S32_SCB_CPACR_CP10 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP10_SHIFT))&S32_SCB_CPACR_CP10_MASK) |
#define S32_SCB_CPACR_CP11 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPACR_CP11_SHIFT))&S32_SCB_CPACR_CP11_MASK) |
#define S32_SCB_CPUID_IMPLEMENTER | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_IMPLEMENTER_SHIFT))&S32_SCB_CPUID_IMPLEMENTER_MASK) |
#define S32_SCB_CPUID_PARTNO | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_PARTNO_SHIFT))&S32_SCB_CPUID_PARTNO_MASK) |
#define S32_SCB_CPUID_REVISION | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_REVISION_SHIFT))&S32_SCB_CPUID_REVISION_MASK) |
#define S32_SCB_CPUID_VARIANT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_CPUID_VARIANT_SHIFT))&S32_SCB_CPUID_VARIANT_MASK) |
#define S32_SCB_DFSR_BKPT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_BKPT_SHIFT))&S32_SCB_DFSR_BKPT_MASK) |
#define S32_SCB_DFSR_DWTTRAP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_DWTTRAP_SHIFT))&S32_SCB_DFSR_DWTTRAP_MASK) |
#define S32_SCB_DFSR_EXTERNAL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_EXTERNAL_SHIFT))&S32_SCB_DFSR_EXTERNAL_MASK) |
#define S32_SCB_DFSR_HALTED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_HALTED_SHIFT))&S32_SCB_DFSR_HALTED_MASK) |
#define S32_SCB_DFSR_VCATCH | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_DFSR_VCATCH_SHIFT))&S32_SCB_DFSR_VCATCH_MASK) |
#define S32_SCB_FPCAR_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCAR_ADDRESS_SHIFT))&S32_SCB_FPCAR_ADDRESS_MASK) |
#define S32_SCB_FPCCR_ASPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_ASPEN_SHIFT))&S32_SCB_FPCCR_ASPEN_MASK) |
#define S32_SCB_FPCCR_BFRDY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_BFRDY_SHIFT))&S32_SCB_FPCCR_BFRDY_MASK) |
#define S32_SCB_FPCCR_HFRDY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_HFRDY_SHIFT))&S32_SCB_FPCCR_HFRDY_MASK) |
#define S32_SCB_FPCCR_LSPACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPACT_SHIFT))&S32_SCB_FPCCR_LSPACT_MASK) |
#define S32_SCB_FPCCR_LSPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_LSPEN_SHIFT))&S32_SCB_FPCCR_LSPEN_MASK) |
#define S32_SCB_FPCCR_MMRDY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MMRDY_SHIFT))&S32_SCB_FPCCR_MMRDY_MASK) |
#define S32_SCB_FPCCR_MONRDY | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_MONRDY_SHIFT))&S32_SCB_FPCCR_MONRDY_MASK) |
#define S32_SCB_FPCCR_THREAD | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_THREAD_SHIFT))&S32_SCB_FPCCR_THREAD_MASK) |
#define S32_SCB_FPCCR_USER | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPCCR_USER_SHIFT))&S32_SCB_FPCCR_USER_MASK) |
#define S32_SCB_FPDSCR_AHP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_AHP_SHIFT))&S32_SCB_FPDSCR_AHP_MASK) |
#define S32_SCB_FPDSCR_DN | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_DN_SHIFT))&S32_SCB_FPDSCR_DN_MASK) |
#define S32_SCB_FPDSCR_FZ | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_FZ_SHIFT))&S32_SCB_FPDSCR_FZ_MASK) |
#define S32_SCB_FPDSCR_RMode | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_FPDSCR_RMode_SHIFT))&S32_SCB_FPDSCR_RMode_MASK) |
#define S32_SCB_HFSR_DEBUGEVT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_DEBUGEVT_SHIFT))&S32_SCB_HFSR_DEBUGEVT_MASK) |
#define S32_SCB_HFSR_FORCED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_FORCED_SHIFT))&S32_SCB_HFSR_FORCED_MASK) |
#define S32_SCB_HFSR_VECTTBL | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_HFSR_VECTTBL_SHIFT))&S32_SCB_HFSR_VECTTBL_MASK) |
#define S32_SCB_ICSR_ISRPENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPENDING_SHIFT))&S32_SCB_ICSR_ISRPENDING_MASK) |
#define S32_SCB_ICSR_ISRPREEMPT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_ISRPREEMPT_SHIFT))&S32_SCB_ICSR_ISRPREEMPT_MASK) |
#define S32_SCB_ICSR_NMIPENDSET | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_NMIPENDSET_SHIFT))&S32_SCB_ICSR_NMIPENDSET_MASK) |
#define S32_SCB_ICSR_PENDSTCLR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTCLR_SHIFT))&S32_SCB_ICSR_PENDSTCLR_MASK) |
#define S32_SCB_ICSR_PENDSTSET | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSTSET_SHIFT))&S32_SCB_ICSR_PENDSTSET_MASK) |
#define S32_SCB_ICSR_PENDSVCLR | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVCLR_SHIFT))&S32_SCB_ICSR_PENDSVCLR_MASK) |
#define S32_SCB_ICSR_PENDSVSET | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_PENDSVSET_SHIFT))&S32_SCB_ICSR_PENDSVSET_MASK) |
#define S32_SCB_ICSR_RETTOBASE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_RETTOBASE_SHIFT))&S32_SCB_ICSR_RETTOBASE_MASK) |
#define S32_SCB_ICSR_VECTACTIVE | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTACTIVE_SHIFT))&S32_SCB_ICSR_VECTACTIVE_MASK) |
#define S32_SCB_ICSR_VECTPENDING | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_ICSR_VECTPENDING_SHIFT))&S32_SCB_ICSR_VECTPENDING_MASK) |
#define S32_SCB_MMFAR_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_MMFAR_ADDRESS_SHIFT))&S32_SCB_MMFAR_ADDRESS_MASK) |
#define S32_SCB_SCR_SEVONPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SEVONPEND_SHIFT))&S32_SCB_SCR_SEVONPEND_MASK) |
#define S32_SCB_SCR_SLEEPDEEP | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPDEEP_SHIFT))&S32_SCB_SCR_SLEEPDEEP_MASK) |
#define S32_SCB_SCR_SLEEPONEXIT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SCR_SLEEPONEXIT_SHIFT))&S32_SCB_SCR_SLEEPONEXIT_MASK) |
#define S32_SCB_SHCSR_BUSFAULTACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTACT_SHIFT))&S32_SCB_SHCSR_BUSFAULTACT_MASK) |
#define S32_SCB_SHCSR_BUSFAULTENA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTENA_SHIFT))&S32_SCB_SHCSR_BUSFAULTENA_MASK) |
#define S32_SCB_SHCSR_BUSFAULTPENDED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_BUSFAULTPENDED_SHIFT))&S32_SCB_SHCSR_BUSFAULTPENDED_MASK) |
#define S32_SCB_SHCSR_MEMFAULTACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTACT_SHIFT))&S32_SCB_SHCSR_MEMFAULTACT_MASK) |
#define S32_SCB_SHCSR_MEMFAULTENA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTENA_SHIFT))&S32_SCB_SHCSR_MEMFAULTENA_MASK) |
#define S32_SCB_SHCSR_MEMFAULTPENDED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MEMFAULTPENDED_SHIFT))&S32_SCB_SHCSR_MEMFAULTPENDED_MASK) |
#define S32_SCB_SHCSR_MONITORACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_MONITORACT_SHIFT))&S32_SCB_SHCSR_MONITORACT_MASK) |
#define S32_SCB_SHCSR_PENDSVACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_PENDSVACT_SHIFT))&S32_SCB_SHCSR_PENDSVACT_MASK) |
#define S32_SCB_SHCSR_SVCALLACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLACT_SHIFT))&S32_SCB_SHCSR_SVCALLACT_MASK) |
#define S32_SCB_SHCSR_SVCALLPENDED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SVCALLPENDED_SHIFT))&S32_SCB_SHCSR_SVCALLPENDED_MASK) |
#define S32_SCB_SHCSR_SYSTICKACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_SYSTICKACT_SHIFT))&S32_SCB_SHCSR_SYSTICKACT_MASK) |
#define S32_SCB_SHCSR_USGFAULTACT | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTACT_SHIFT))&S32_SCB_SHCSR_USGFAULTACT_MASK) |
#define S32_SCB_SHCSR_USGFAULTENA | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTENA_SHIFT))&S32_SCB_SHCSR_USGFAULTENA_MASK) |
#define S32_SCB_SHCSR_USGFAULTPENDED | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHCSR_USGFAULTPENDED_SHIFT))&S32_SCB_SHCSR_USGFAULTPENDED_MASK) |
#define S32_SCB_SHPR1_PRI_4 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_4_SHIFT))&S32_SCB_SHPR1_PRI_4_MASK) |
#define S32_SCB_SHPR1_PRI_5 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_5_SHIFT))&S32_SCB_SHPR1_PRI_5_MASK) |
#define S32_SCB_SHPR1_PRI_6 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR1_PRI_6_SHIFT))&S32_SCB_SHPR1_PRI_6_MASK) |
#define S32_SCB_SHPR2_PRI_11 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR2_PRI_11_SHIFT))&S32_SCB_SHPR2_PRI_11_MASK) |
#define S32_SCB_SHPR3_PRI_12 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_12_SHIFT))&S32_SCB_SHPR3_PRI_12_MASK) |
#define S32_SCB_SHPR3_PRI_14 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_14_SHIFT))&S32_SCB_SHPR3_PRI_14_MASK) |
#define S32_SCB_SHPR3_PRI_15 | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_SHPR3_PRI_15_SHIFT))&S32_SCB_SHPR3_PRI_15_MASK) |
#define S32_SCB_VTOR_TBLOFF | ( | x | ) | (((uint32_t)(((uint32_t)(x))<<S32_SCB_VTOR_TBLOFF_SHIFT))&S32_SCB_VTOR_TBLOFF_MASK) |