20 #include "flexio_hw_access.h"
92 #define DIVIDER_MAX_VALUE 0xFFU
96 #define TX_SHIFTER(x) (x)
97 #define RX_SHIFTER(x) (x)
98 #define TX_TIMER(x) (x)
99 #define RX_TIMER(x) (x)
121 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
123 if (tmpDiv > DIVIDER_MAX_VALUE)
125 tmpDiv = DIVIDER_MAX_VALUE;
128 *divider = (uint16_t)tmpDiv;
145 uint8_t resourceIndex;
148 resourceIndex = state->flexioCommon.resourceIndex;
151 FLEXIO_UART_DRV_ComputeBaudRateDivider(state, userConfigPtr->
baudRate, ÷r, inputClock);
155 FLEXIO_SetShifterConfig(baseAddr,
156 TX_SHIFTER(resourceIndex),
157 FLEXIO_SHIFTER_START_BIT_0,
158 FLEXIO_SHIFTER_STOP_BIT_1,
159 FLEXIO_SHIFTER_SOURCE_PIN);
160 FLEXIO_SetShifterControl(baseAddr,
161 TX_SHIFTER(resourceIndex),
162 FLEXIO_SHIFTER_MODE_TRANSMIT,
164 FLEXIO_PIN_POLARITY_HIGH,
165 FLEXIO_PIN_CONFIG_OUTPUT,
166 TX_TIMER(resourceIndex),
167 FLEXIO_TIMER_POLARITY_POSEDGE);
170 FLEXIO_SetTimerCompare(baseAddr, TX_TIMER(resourceIndex), (uint16_t)((((bits << 1U) - 1U) << 8U) + divider));
171 FLEXIO_SetTimerConfig(baseAddr,
172 TX_TIMER(resourceIndex),
173 FLEXIO_TIMER_START_BIT_ENABLED,
174 FLEXIO_TIMER_STOP_BIT_TIM_DIS,
175 FLEXIO_TIMER_ENABLE_TRG_HIGH,
176 FLEXIO_TIMER_DISABLE_TIM_CMP,
177 FLEXIO_TIMER_RESET_NEVER,
178 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
179 FLEXIO_TIMER_INITOUT_ONE);
180 FLEXIO_SetTimerControl(baseAddr,
181 TX_TIMER(resourceIndex),
182 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
183 FLEXIO_TRIGGER_POLARITY_LOW,
184 FLEXIO_TRIGGER_SOURCE_INTERNAL,
186 FLEXIO_PIN_POLARITY_HIGH,
187 FLEXIO_PIN_CONFIG_DISABLED,
188 FLEXIO_TIMER_MODE_DISABLED);
190 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
208 uint8_t resourceIndex;
211 resourceIndex = state->flexioCommon.resourceIndex;
214 FLEXIO_UART_DRV_ComputeBaudRateDivider(state, userConfigPtr->
baudRate, ÷r, inputClock);
218 FLEXIO_SetShifterConfig(baseAddr,
219 RX_SHIFTER(resourceIndex),
220 FLEXIO_SHIFTER_START_BIT_0,
221 FLEXIO_SHIFTER_STOP_BIT_1,
222 FLEXIO_SHIFTER_SOURCE_PIN);
223 FLEXIO_SetShifterControl(baseAddr,
224 RX_SHIFTER(resourceIndex),
225 FLEXIO_SHIFTER_MODE_DISABLED,
227 FLEXIO_PIN_POLARITY_HIGH,
228 FLEXIO_PIN_CONFIG_DISABLED,
229 RX_TIMER(resourceIndex),
230 FLEXIO_TIMER_POLARITY_NEGEDGE);
233 FLEXIO_SetTimerCompare(baseAddr, RX_TIMER(resourceIndex), (uint16_t)((((bits << 1U) - 1U) << 8U) + divider));
234 FLEXIO_SetTimerConfig(baseAddr,
235 RX_TIMER(resourceIndex),
236 FLEXIO_TIMER_START_BIT_ENABLED,
237 FLEXIO_TIMER_STOP_BIT_TIM_DIS,
238 FLEXIO_TIMER_ENABLE_PIN_POSEDGE,
239 FLEXIO_TIMER_DISABLE_TIM_CMP,
240 FLEXIO_TIMER_RESET_PIN_RISING,
241 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
242 FLEXIO_TIMER_INITOUT_ONE_RESET);
243 FLEXIO_SetTimerControl(baseAddr,
244 RX_TIMER(resourceIndex),
246 FLEXIO_TRIGGER_POLARITY_HIGH,
247 FLEXIO_TRIGGER_SOURCE_EXTERNAL,
249 FLEXIO_PIN_POLARITY_LOW,
250 FLEXIO_PIN_CONFIG_DISABLED,
251 FLEXIO_TIMER_MODE_DISABLED);
264 uint8_t resourceIndex;
267 resourceIndex = state->flexioCommon.resourceIndex;
270 switch (state->driverType)
274 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
275 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
277 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(resourceIndex)),
false);
284 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(resourceIndex)),
false);
288 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
295 state->driverIdle =
true;
297 if (state->blocking ==
true)
313 uint8_t resourceIndex;
315 resourceIndex = state->flexioCommon.resourceIndex;
322 FLEXIO_SetShifterStartBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_START_BIT_0);
323 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_TRANSMIT);
328 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
329 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_RECEIVE);
331 FLEXIO_SetTimerMode(baseAddr, TX_TIMER(resourceIndex), FLEXIO_TIMER_MODE_8BIT_BAUD);
344 uint8_t resourceIndex;
346 resourceIndex = state->flexioCommon.resourceIndex;
350 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
351 FLEXIO_SetTimerMode(baseAddr, TX_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
354 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
357 FLEXIO_UART_DRV_EndTransfer(state);
371 switch (state->driverType)
391 state->blocking =
false;
396 FLEXIO_UART_DRV_StopTransfer(state);
399 return state->status;
413 uint8_t resourceIndex;
419 resourceIndex = state->flexioCommon.resourceIndex;
422 data = FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_NORMAL);
423 data >>= 32U - (uint32_t)(state->bitCount);
425 if (state->bitCount <= 8U)
427 *(uint8_t *)state->data = (uint8_t)data;
430 state->remainingBytes -= 1U;
435 *(uint16_t *)state->data = (uint16_t)data;
437 state->data = &state->data[2U];
438 state->remainingBytes -= 2U;
453 uint8_t resourceIndex;
458 resourceIndex = state->flexioCommon.resourceIndex;
460 if (state->remainingBytes == 0U)
466 if (state->bitCount <= 8U)
468 data = (uint32_t)(*(uint8_t *)state->data);
470 state->remainingBytes -= 1U;
475 data = (uint32_t)(*(uint16_t *)state->data);
476 state->data = &state->data[2U];
477 state->remainingBytes -= 2U;
480 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_NORMAL);
492 static void FLEXIO_UART_DRV_CheckStatusTx(
void *stateStruct)
495 uint8_t resourceIndex;
502 resourceIndex = state->flexioCommon.resourceIndex;
506 if (state->remainingBytes == 0U)
508 if (FLEXIO_GetTimerStatus(baseAddr, TX_TIMER(resourceIndex)))
511 FLEXIO_ClearTimerStatus(baseAddr, TX_TIMER(resourceIndex));
513 if (state->txFlush == 0U)
521 FLEXIO_UART_DRV_StopTransfer(state);
523 if (state->callback != NULL)
528 else if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)))
534 FLEXIO_SetShifterStartBit(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_START_BIT_1);
535 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), 0xFFFFFFFFUL, FLEXIO_SHIFTER_RW_MODE_NORMAL);
545 else if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)) && (state->remainingBytes > 0U))
547 FLEXIO_UART_DRV_WriteData(state);
548 if (state->remainingBytes == 0U)
551 if (state->callback != NULL)
556 if (state->remainingBytes == 0U)
561 FLEXIO_ClearTimerStatus(baseAddr, TX_TIMER(resourceIndex));
565 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
567 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(resourceIndex)),
true);
586 static void FLEXIO_UART_DRV_CheckStatusRx(
void *stateStruct)
589 uint8_t resourceIndex;
596 resourceIndex = state->flexioCommon.resourceIndex;
599 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
602 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
603 state->remainingBytes = 0U;
607 else if (FLEXIO_GetShifterStatus(baseAddr, RX_SHIFTER(resourceIndex)))
609 FLEXIO_UART_DRV_ReadData(state);
610 if (state->remainingBytes == 0U)
613 if (state->callback != NULL)
624 if (state->remainingBytes == 0U)
632 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
634 FLEXIO_UART_DRV_StopTransfer(state);
636 if (state->callback != NULL)
651 static void FLEXIO_UART_DRV_CheckStatus(
void *stateStruct)
660 FLEXIO_UART_DRV_CheckStatusTx(stateStruct);
664 FLEXIO_UART_DRV_CheckStatusRx(stateStruct);
675 static void FLEXIO_UART_DRV_EndDmaTxTransfer(
void *stateStruct,
edma_chn_status_t status)
689 if (state->callback != NULL)
693 if (state->remainingBytes == 0U)
697 FLEXIO_ClearTimerStatus(baseAddr, TX_TIMER(state->flexioCommon.resourceIndex));
698 FLEXIO_SetTimerInterrupt(baseAddr, (uint8_t)(1U << TX_TIMER(state->flexioCommon.resourceIndex)),
true);
704 dmaChn = state->dmaChannel;
705 if (state->bitCount <= 8U)
716 state->remainingBytes = 0U;
729 static void FLEXIO_UART_DRV_EndDmaRxTransfer(
void *stateStruct,
edma_chn_status_t status)
741 if (state->callback != NULL)
745 if (state->remainingBytes == 0U)
749 FLEXIO_UART_DRV_StopTransfer(state);
751 if (state->callback != NULL)
760 dmaChn = state->dmaChannel;
761 if (state->bitCount <= 8U)
772 state->remainingBytes = 0U;
793 shifter = TX_SHIFTER(state->flexioCommon.resourceIndex);
794 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter]));
812 if (state->bitCount <= 8U)
821 shifter = RX_SHIFTER(state->flexioCommon.resourceIndex);
822 addr = (uint32_t)(&(baseAddr->
SHIFTBUF[shifter])) + (
sizeof(uint32_t) - byteCount);
835 uint8_t resourceIndex;
841 resourceIndex = state->flexioCommon.resourceIndex;
844 if (state->bitCount <= 8U)
856 (uint32_t)(state->data),
857 FLEXIO_UART_DRV_ComputeTxRegAddr(state),
860 state->remainingBytes / byteCount,
864 state->remainingBytes = 0U;
874 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
true);
886 uint8_t resourceIndex;
892 resourceIndex = state->flexioCommon.resourceIndex;
895 if (state->bitCount <= 8U)
907 FLEXIO_UART_DRV_ComputeRxRegAddr(state),
908 (uint32_t)(state->data),
911 state->remainingBytes / byteCount,
915 state->remainingBytes = 0U;
925 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
963 state->flexioCommon.resourceCount = 1U;
979 state->remainingBytes = 0U;
980 state->callback = userConfigPtr->
callback;
982 state->blocking =
false;
983 state->driverType = userConfigPtr->
driverType;
984 state->direction = userConfigPtr->
direction;
986 state->driverIdle =
true;
987 state->bitCount = userConfigPtr->
bitCount;
992 FLEXIO_UART_DRV_ConfigureTx(state, userConfigPtr, inputClock);
997 FLEXIO_UART_DRV_ConfigureRx(state, userConfigPtr, inputClock);
1001 switch (state->driverType)
1006 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusTx;
1010 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusRx;
1018 state->dmaChannel = userConfigPtr->
dmaChannel;
1020 dmaReq =
g_flexioDMASrc[instance][TX_SHIFTER(state->flexioCommon.resourceIndex)];
1025 state->flexioCommon.isr = FLEXIO_UART_DRV_CheckStatusTx;
1076 uint32_t inputClock;
1078 uint8_t resourceIndex;
1088 resourceIndex = state->flexioCommon.resourceIndex;
1098 FLEXIO_UART_DRV_ComputeBaudRateDivider(state, baudRate, ÷r, inputClock);
1103 FLEXIO_SetTimerCompare(baseAddr, TX_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitCount << 1U) - 1U) << 8U) + divider));
1108 FLEXIO_SetTimerCompare(baseAddr, RX_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitCount << 1U) - 1U) << 8U) + divider));
1111 state->bitCount = bitCount;
1128 uint32_t inputClock;
1132 uint8_t resourceIndex;
1137 resourceIndex = state->flexioCommon.resourceIndex;
1145 timerCmp = FLEXIO_GetTimerCompare(baseAddr, TX_TIMER(resourceIndex));
1146 divider = (uint16_t)(timerCmp & 0x00FFU);
1149 *baudRate = (inputClock + (uint32_t)divider + 1U) / (2U * ((uint32_t)divider + 1U));
1165 const uint8_t * txBuff,
1169 uint8_t resourceIndex;
1177 resourceIndex = state->flexioCommon.resourceIndex;
1182 state->data = (uint8_t *)txBuff;
1183 state->remainingBytes = txSize;
1185 state->driverIdle =
false;
1187 state->txFlush = (uint8_t)((txSize == 1U) ? 1U : 2U);
1190 FLEXIO_UART_DRV_EnableTransfer(state);
1192 switch (state->driverType)
1196 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
true);
1197 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
true);
1201 FLEXIO_UART_DRV_CheckStatus(state);
1204 FLEXIO_UART_DRV_StartTxDmaTransfer(state);
1223 const uint8_t * txBuff,
1232 state->blocking =
true;
1239 state->blocking =
false;
1244 return FLEXIO_UART_DRV_WaitTransferEnd(state, timeout);
1260 uint8_t resourceIndex;
1268 resourceIndex = state->flexioCommon.resourceIndex;
1273 state->data = rxBuff;
1274 state->remainingBytes = rxSize;
1276 state->driverIdle =
false;
1279 FLEXIO_UART_DRV_EnableTransfer(state);
1281 switch (state->driverType)
1285 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
1286 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
1290 FLEXIO_UART_DRV_CheckStatus(state);
1293 FLEXIO_UART_DRV_StartRxDmaTransfer(state);
1321 state->blocking =
true;
1328 state->blocking =
false;
1333 return FLEXIO_UART_DRV_WaitTransferEnd(state, timeout);
1349 FLEXIO_UART_DRV_StopTransfer(state);
1369 FLEXIO_UART_DRV_CheckStatus(state);
1372 if (bytesRemaining != NULL)
1374 *bytesRemaining = state->remainingBytes;
1377 if (!state->driverIdle)
1383 return state->status;
1403 state->data = rxBuff;
1404 state->remainingBytes = rxSize;
1418 const uint8_t * txBuff,
1425 state->data = (uint8_t *)txBuff;
1426 state->remainingBytes = txSize;
__IO uint32_t SHIFTBUF[FLEXIO_SHIFTBUF_COUNT]
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t FLEXIO_UART_DRV_ReceiveData(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking UART reception.
FLEXIO_Type *const g_flexioBase[FLEXIO_INSTANCE_COUNT]
status_t FLEXIO_UART_DRV_SetTxBuffer(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
#define FLEXIO_INSTANCE_COUNT
status_t FLEXIO_UART_DRV_SetConfig(flexio_uart_state_t *state, uint32_t baudRate, uint8_t bitCount)
Set the baud rate and bit width for any subsequent UART communication.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
status_t EDMA_DRV_SetChannelRequest(uint8_t channel, uint8_t req)
Configures the DMA request for the eDMA channel.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
status_t FLEXIO_UART_DRV_SendData(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking UART transmission.
status_t FLEXIO_UART_DRV_SendDataBlocking(flexio_uart_state_t *state, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking UART transmission.
edma_chn_status_t
Channel status for eDMA channel.
flexio_uart_driver_direction_t direction
status_t FLEXIO_UART_DRV_ReceiveDataBlocking(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking UART reception.
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
status_t FLEXIO_UART_DRV_GetBaudRate(flexio_uart_state_t *state, uint32_t *baudRate)
Get the currently configured baud rate.
void EDMA_DRV_SetSrcAddr(uint8_t channel, uint32_t address)
Configures the source address for the eDMA channel.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t FLEXIO_UART_DRV_GetStatus(flexio_uart_state_t *state, uint32_t *bytesRemaining)
Get the status of the current non-blocking UART transfer.
status_t FLEXIO_UART_DRV_SetRxBuffer(flexio_uart_state_t *state, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
const uint8_t g_flexioDMASrc[FLEXIO_INSTANCE_COUNT][FEATURE_FLEXIO_MAX_SHIFTER_COUNT]
Driver internal context structure.
void EDMA_DRV_SetMajorLoopIterationCount(uint8_t channel, uint32_t majorLoopCount)
Configures the number of major loop iterations.
status_t FLEXIO_UART_DRV_Deinit(flexio_uart_state_t *state)
De-initialize the FLEXIO_UART driver.
status_t FLEXIO_UART_DRV_TransferAbort(flexio_uart_state_t *state)
Aborts a non-blocking UART transfer.
void EDMA_DRV_SetDestAddr(uint8_t channel, uint32_t address)
Configures the destination address for the eDMA channel.
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_device_state_t * g_flexioDeviceStatePtr[FLEXIO_INSTANCE_COUNT]
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
const clock_names_t g_flexioClock[FLEXIO_INSTANCE_COUNT]
flexio_driver_type_t driverType
Driver configuration structure.
status_t FLEXIO_UART_DRV_Init(uint32_t instance, const flexio_uart_user_config_t *userConfigPtr, flexio_uart_state_t *state)
Initialize the FLEXIO_UART driver.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.