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Processor Expert Priority System Some CPUs support selectable interrupts priorities. The user may select a priority for each interrupt vector. The interrupt with a higher priority number can interrupt a service routine with the lower one. Processor Expert supports the following settings in design-time: interrupt priority and priority of the event code. Interrupt PriorityThe user may select interrupt priority in the component properties, just below the interrupt vector name. Processor Expert offers the following values, which are supported for all microcontrollers:
The selected value is automatically mapped to the priority supported by the target microcontroller. It is indicated in the third column of the Component Inspector. Version specific information for HCS08 derivatives with IPC (Interrupt Priority Controller) The HCS08 derivatives with IPC module offer an interrupt priority configuration. There are four interrupt priority levels 0 to 3 available, where 0 is the lowest priority and 3 is the highest one. Version specific information for RS08 without interrupt support and HC(S)08 derivatives without IPC (Interrupt Priority Controller) These derivatives do not support interrupt priorities. The interrupt priority settings, for example imported from a project for another CPU, are ignored. Version specific information for RS08 with interrupt support On these RS08 derivatives, the interrupts are handled through single interrupt vector. The priority of each individual "emulated interrupt" is determined by order in which the SIPx registers are polled in the sofware handler. The priority can be in the range 0 ..number_of_interrupts-1 (e.g. 0 .. 15). The lower is the number the higher is the priority. The platform independent interrupt priority values in Processor Expert described on top of this section are mapped to these values. Version specific information for ColdFire V1 derivatives On the ColdFire V1 platform, an interrupt priority of an interrupt is determined by an Interrupt Level (1-7) and a Priority within Level (0-7). Please see the CPU data sheet for interrupt priority system details. The applied interrupt priority value (the value displayed in the third column of the Component Inspector) contains both values - e.g. Level 4, priority within level 6. The target-independent values of interrupt priority (e.g. minimum, maximum etc...) are mapped either to the default priority of the selected interrupt or to Level 6, Priority within level 6 or level 6, Priority within level 7. Priority of Event CodeVersion specific information for Kinetis and ColdFire+ derivatives Priority of event code is not supported for Kinetis and ColdFire+. The user can also select a priority for the processing of the event code. This setting is available for the events that are invoked from the Interrupt Service Routines. This priority may be different from the interrupt priority. However, the meaning of the number is the same - the event may be interrupted only by the interrupts with the higher priority. Processor Expert offers the following architecture independent values:
The selected value is automatically mapped to the priority supported by the target microcontroller and the selected value is displayed in the third column of the Component Inspector. Note: Some events do not support priorities, because their invocation is not caused by the interrupt processing. Warning: Please note that Processor Expert does not allow the user decrease an event code priority (with the exception of 'Interrupts enabled' value on some platforms, please see below). This is because Processor Expert event routines are not generally reentrant so there is a risk that the interrupt would be able to interrupt itself during the processing. If there is such functionality requested, the user has to do it manually (e.g. by calling a appropriate CPU component method setting a priority) and carefully check possible problems. Version specific information for HCS08 derivatives with IPC (Interrupt Priority Controller) Processor Expert offers the following event priority options:
Version specific information for HC(S)08 derivatives without IPC (Interrupt Priority Controller) Processor Expert offers the following event priority options:
Version specific information for RS08 with interrupt support Because of architecture limitations, the Processor Expert allows only interrupts disabled value so the interrupt is always disabled within the event routines. The same as interrupt value is mapped to interrupts disabled. Version specific information for ColdFire V1 derivatives Processor Expert offers the following event priority options:
Version specific information for 56800 derivatives Processor Expert offers the following event priority options:
Version specific information for 56800E derivatives Processor Expert offers the following event priority options:
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