S32 SDK
S32K148_features.h
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1 /*
2 ** ###################################################################
3 ** Abstract:
4 ** Chip specific module features.
5 **
6 ** Copyright (c) 2015 Freescale Semiconductor, Inc.
7 ** Copyright 2016-2017 NXP
8 ** All rights reserved.
9 **
10 ** THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
11 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
13 ** IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
14 ** INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 ** HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 ** STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
19 ** IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
20 ** THE POSSIBILITY OF SUCH DAMAGE.
21 **
22 ** ###################################################################
23 */
24 
62 #if !defined(S32K148_FEATURES_H)
63 #define S32K148_FEATURES_H
64 
65 /* ERRATA sections*/
66 
67 /* @brief ARM Errata 838869: Store immediate overlapping exception return operation might vector to
68  * incorrect interrupt. */
69 #define ERRATA_E9005
70 
71 /* @brief ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
72  * short ISRs are used. */
73 #define ERRATA_E6940
74 
75 /* @brief Errata workaround: System clock status register may be a erroneous status during the system clock switch.
76  * Read system clock source twice. */
77 #define ERRATA_E10777
78 
79 /* @brief E10792: LPI2C: Slave Transmit Data Flag may incorrectly read as one when TXCFG is zero.
80  * Interrupts for transfer data should be enabled after the address valid event is detected and
81  * disabled at the end of the transfer. */
82 #define ERRATA_E10792
83 
84 /* LPI2C module features */
85 
86 /* @brief EDMA requests for LPI2C module */
87 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}, {(uint8_t)EDMA_REQ_LPI2C1_TX, (uint8_t)EDMA_REQ_LPI2C1_RX}}
88 /* @brief PCC clocks for LPI2C module */
89 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK, LPI2C1_CLK}
90 
91 /* PCC module features */
92 
93 /* @brief Has InUse feature (register bit PCC[INUSE]). */
94 #define FEATURE_PCC_HAS_IN_USE_FEATURE (0)
95 
96 /* PORT module features */
98 #define FEATURE_PINS_DRIVER_USING_PORT (1)
99 /* @brief Has control lock (register bit PCR[LK]). */
100 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
101 /* @brief Has open drain control (register bit PCR[ODE]). */
102 #define FEATURE_PINS_HAS_OPEN_DRAIN (0)
103 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
104 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
105 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
106 #define FEATURE_PORT_HAS_DMA_REQUEST (1)
107 /* @brief Has pull resistor selection available. */
108 #define FEATURE_PINS_HAS_PULL_SELECTION (1)
109 /* @brief Has slew rate control (register bit PCR[SRE]). */
110 #define FEATURE_PINS_HAS_SLEW_RATE (0)
111 /* @brief Has passive filter (register bit field PCR[PFE]). */
112 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
113 /* @brief Has drive strength (register bit PCR[DSE]). */
114 #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
115 /* @brief Has drive strength control bits*/
116 #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
117 
118 /* SOC module features */
119 
120 /* @brief PORT availability on the SoC. */
121 #define FEATURE_SOC_PORT_COUNT (5)
122 
123 #define FEATURE_SOC_SCG_COUNT (1)
124 /* @brief Slow IRC low range clock frequency. */
125 #define FEATURE_SCG_SIRC_LOW_RANGE_FREQ (2000000U)
126 /* @brief Slow IRC high range clock frequency. */
127 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
128 
129 /* @brief Fast IRC trimmed clock frequency(48MHz). */
130 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
131 /* @brief Fast IRC trimmed clock frequency(52MHz). */
132 #define FEATURE_SCG_FIRC_FREQ1 (52000000U)
133 /* @brief Fast IRC trimmed clock frequency(56MHz). */
134 #define FEATURE_SCG_FIRC_FREQ2 (56000000U)
135 /* @brief Fast IRC trimmed clock frequency(60MHz). */
136 #define FEATURE_SCG_FIRC_FREQ3 (60000000U)
137 
138 /* FLASH module features */
139 
140 /* @brief Is of type FTFA. */
141 #define FEATURE_FLS_IS_FTFA (0u)
142 /* @brief Is of type FTFC. */
143 #define FEATURE_FLS_IS_FTFC (1u)
144 /* @brief Is of type FTFE. */
145 #define FEATURE_FLS_IS_FTFE (0u)
146 /* @brief Is of type FTFL. */
147 #define FEATURE_FLS_IS_FTFL (0u)
148 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
149 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
150 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
151 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
152 /* @brief Has EEPROM region protection (register FEPROT). */
153 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
154 /* @brief Has data flash region protection (register FDPROT). */
155 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
156 /* @brief P-Flash block count. */
157 #define FEATURE_FLS_PF_BLOCK_COUNT (3u)
158 /* @brief P-Flash block size. */
159 #define FEATURE_FLS_PF_BLOCK_SIZE (1572864u)
160 /* @brief P-Flash sector size. */
161 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (4096u)
162 /* @brief P-Flash write unit size. */
163 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
164 /* @brief P-Flash block swap feature. */
165 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
166 /* @brief Has FlexNVM memory. */
167 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
168 /* @brief FlexNVM block count. */
169 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
170 /* @brief FlexNVM block size. */
171 #define FEATURE_FLS_DF_BLOCK_SIZE (524288u)
172 /* @brief FlexNVM sector size. */
173 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (4096u)
174 /* @brief FlexNVM write unit size. */
175 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
176 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
177 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
178 /* @brief Has FlexRAM memory. */
179 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
180 /* @brief FlexRAM size. */
181 #define FEATURE_FLS_FLEX_RAM_SIZE (4096u)
182 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
183 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
184 /* @brief Has 0x00 Read 1s Block command. */
185 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
186 /* @brief Has 0x01 Read 1s Section command. */
187 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
188 /* @brief Has 0x02 Program Check command. */
189 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
190 /* @brief Has 0x03 Read Resource command. */
191 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
192 /* @brief Has 0x06 Program Longword command. */
193 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
194 /* @brief Has 0x07 Program Phrase command. */
195 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
196 /* @brief Has 0x08 Erase Flash Block command. */
197 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
198 /* @brief Has 0x09 Erase Flash Sector command. */
199 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
200 /* @brief Has 0x0B Program Section command. */
201 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
202 /* @brief Has 0x40 Read 1s All Blocks command. */
203 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
204 /* @brief Has 0x41 Read Once command. */
205 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
206 /* @brief Has 0x43 Program Once command. */
207 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
208 /* @brief Has 0x44 Erase All Blocks command. */
209 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
210 /* @brief Has 0x45 Verify Backdoor Access Key command. */
211 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
212 /* @brief Has 0x46 Swap Control command. */
213 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
214 /* @brief Has 0x49 Erase All Blocks unsecure command. */
215 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
216 /* @brief Has 0x80 Program Partition command. */
217 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
218 /* @brief Has 0x81 Set FlexRAM Function command. */
219 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
220 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
221 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (16u)
222 /* @brief P-Flash Erase sector command address alignment. */
223 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (16u)
224 /* @brief P-Flash Program/Verify section command address alignment. */
225 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (16u)
226 /* @brief P-Flash Read resource command address alignment. */
227 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
228 /* @brief P-Flash Program check command address alignment. */
229 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
230 /* @brief P-Flash Program check command address alignment. */
231 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
232 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
233 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (16u)
234 /* @brief FlexNVM Erase sector command address alignment. */
235 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (16u)
236 /* @brief FlexNVM Program/Verify section command address alignment. */
237 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (16u)
238 /* @brief FlexNVM Read resource command address alignment. */
239 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
240 /* @brief FlexNVM Program check command address alignment. */
241 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
242 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
243 #define FEATURE_FLS_DF_SIZE_0000 (0x00080000u)
244 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
245 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
246 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
247 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
248 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
249 #define FEATURE_FLS_DF_SIZE_0011 (0xFFFFFFFFu)
250 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
251 #define FEATURE_FLS_DF_SIZE_0100 (0x000070000u)
252 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
253 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
254 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
255 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
256 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
257 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
258 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
259 #define FEATURE_FLS_DF_SIZE_1000 (0xFFFFFFFFu)
260 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
261 #define FEATURE_FLS_DF_SIZE_1001 (0xFFFFFFFFu)
262 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
263 #define FEATURE_FLS_DF_SIZE_1010 (0xFFFFFFFFu)
264 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
265 #define FEATURE_FLS_DF_SIZE_1011 (0xFFFFFFFFu)
266 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
267 #define FEATURE_FLS_DF_SIZE_1100 (0xFFFFFFFFu)
268 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
269 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
270 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
271 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
272 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
273 #define FEATURE_FLS_DF_SIZE_1111 (0x00080000u)
274 /* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
275 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
276 /* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
277 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
278 /* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
279 #define FEATURE_FLS_EE_SIZE_0010 (0x1000u)
280 /* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
281 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
282 /* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
283 #define FEATURE_FLS_EE_SIZE_0100 (0x0400u)
284 /* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
285 #define FEATURE_FLS_EE_SIZE_0101 (0x0200u)
286 /* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
287 #define FEATURE_FLS_EE_SIZE_0110 (0x0100u)
288 /* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
289 #define FEATURE_FLS_EE_SIZE_0111 (0x0080u)
290 /* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
291 #define FEATURE_FLS_EE_SIZE_1000 (0x0040u)
292 /* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
293 #define FEATURE_FLS_EE_SIZE_1001 (0x0020u)
294 /* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
295 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
296 /* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
297 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
298 /* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
299 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
300 /* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
301 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
302 /* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
303 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
304 /* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
305 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
306 
307 /* CAN module features */
308 
309 /* @brief Frames available in Rx FIFO flag shift */
310 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
311 /* @brief Rx FIFO warning flag shift */
312 #define FEATURE_CAN_RXFIFO_WARNING (6U)
313 /* @brief Rx FIFO overflow flag shift */
314 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
315 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */
316 #define FEATURE_CAN0_MAX_MB_NUM (32U)
317 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN1 */
318 #define FEATURE_CAN1_MAX_MB_NUM (32U)
319 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN2 */
320 #define FEATURE_CAN2_MAX_MB_NUM (32U)
321 /* @brief Array of maximum number of Message Buffers supported for payload size 8 for all the CAN instances */
322 #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM, \
323  FEATURE_CAN1_MAX_MB_NUM, \
324  FEATURE_CAN2_MAX_MB_NUM }
325 /* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */
326 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
327 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
328 #define FEATURE_CAN_MAX_MB_NUM (32U)
329 /* @brief Has Pretending Networking mode */
330 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
331 /* @brief Has Stuff Bit Count Enable Bit */
332 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
333 /* @brief Has ISO CAN FD Enable Bit */
334 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
335 /* @brief Has Message Buffer Data Size Region 1 */
336 #define FEATURE_CAN_HAS_MBDSR1 (0)
337 /* @brief Has Message Buffer Data Size Region 2 */
338 #define FEATURE_CAN_HAS_MBDSR2 (0)
339 /* @brief Has DMA enable (bit field MCR[DMA]). */
340 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
341 /* @brief DMA hardware requests for all FlexCAN instances */
342 #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0, \
343  EDMA_REQ_FLEXCAN1, \
344  EDMA_REQ_FLEXCAN2 }
345 /* @brief Maximum number of Message Buffers IRQs */
346 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
347 /* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */
348 #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1U)
349 /* @brief Message Buffers IRQs */
350 #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
351  CAN_ORed_16_31_MB_IRQS }
352 
353 #define FEATURE_CAN_RAM_OFFSET (0x00000080u)
354 
355 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
356 
357 #define FEATURE_CAN_PE_CLK_NUM 2U
358 /* @brief FlexCAN clock source */
359 typedef enum {
363 /* @brief Clock names for FlexCAN PE clock */
364 #define FLEXCAN_PE_CLOCK_NAMES { FLEXCAN_CLK_SOURCE_SOSCDIV2, FLEXCAN_CLK_SOURCE_SYS }
365 #endif
366 /* @brief Has Self Wake Up mode */
367 #define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
368 
369 /* LPUART module features */
370 
371 /* @brief Has extended data register ED. */
372 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
373 /* @brief Hardware flow control (RTS, CTS) is supported. */
374 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
375 /* @brief Baud rate oversampling is available. */
376 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
377 /* @brief Baud rate oversampling is available. */
378 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
379 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
380 #define FEATURE_LPUART_FIFO_SIZE (4U)
381 /* @brief Supports two match addresses to filter incoming frames. */
382 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
383 /* @brief Has transmitter/receiver DMA enable bits. */
384 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
385 /* @brief Flag clearance mask for STAT register. */
386 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
387 /* @brief Flag clearance mask for FIFO register. */
388 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
389 /* @brief Default oversampling ratio. */
390 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
391 /* @brief Default baud rate modulo divisor. */
392 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
393 /* @brief Clock names for LPUART. */
394 #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK, LPUART2_CLK}
395 
396 /* FlexIO module features */
397 
398 /* @brief Define the maximum number of shifters for any FlexIO instance. */
399 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
400 /* @brief Define DMA request names for Flexio. */
401 #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
402 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
403 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2_SAI1_RX
404 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3_SAI1_TX
405 
406 /* LPSPI module features */
407 
408 /* @brief DMA instance used for LPSPI module */
409 #define LPSPI_DMA_INSTANCE 0U
410 
411 /* @brief DMA instance used for LPI2C module */
412 #define LPI2C_DMA_INSTANCE 0U
413 
414 /* PDB module features */
415 
416 /* @brief Define the count of supporting ADC channels per each PDB. */
417 #define FEATURE_PDB_ADC_CHANNEL_COUNT (4U)
418 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
419 #define FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (8U)
420 /* @brief Define the count of supporting Pulse-Out outputs per each PDB. */
421 #define FEATURE_PDB_PODLY_COUNT (1U)
422 
423 /* Interrupt module features */
424 
425 /* @brief Lowest interrupt request number. */
426 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
427 /* @brief Highest interrupt request number. */
428 #define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn)
429 
430 #define FEATURE_NVIC_PRIO_BITS (4U)
431 /* @brief Has software interrupt. */
432 #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
433 /* @brief Has pending interrupt state. */
434 #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
435 /* @brief Has active interrupt state. */
436 #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u)
437 
438 
439 /* System Control Block module features */
440 
441 /* @brief VECTKEY value so that AIRCR register write is not ignored. */
442 #define FEATURE_SCB_VECTKEY (0x05FAU)
443 
444 
445 /* SMC module features */
446 
447 /* @brief Has stop option (register bit STOPCTRL[STOPO]). */
448 #define FEATURE_SMC_HAS_STOPO (1)
449 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
450 #define FEATURE_SMC_HAS_PSTOPO (0)
451 /* @brief Has WAIT and VLPW options. */
452 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
453 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
454 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
455 
456 
457 /* MPU module features */
458 
459 /* @brief Specifies hardware revision level. */
460 #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
461 /* @brief Has process identifier support. */
462 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
463 /* @brief Specifies total number of bus masters. */
464 #define FEATURE_MPU_MASTER_COUNT (4U)
465 /* @brief Specifies maximum number of masters which have separated
466 privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K14x).
467 */
468 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
469 /* @brief Specifies maximum number of masters which have only
470 read and write permissions (e.g. master4~7 in S32K14x).
471 */
472 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
473 
474 /* @brief Specifies number of set access control right bits for
475  masters which have separated privilege rights for user and
476  supervisor mode accesses (e.g. master0~3 in S32K14x).
477 */
478 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
479 /* @brief Specifies number of set access control right bits for
480  masters which have only read and write permissions(e.g. master4~7 in S32K14x).
481 */
482 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
483 
484 /* @brief The MPU Logical Bus Master Number for core bus master. */
485 #define FEATURE_MPU_MASTER_CORE (0U)
486 /* @brief The MPU Logical Bus Master Number for Debugger master. */
487 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
488 /* @brief The MPU Logical Bus Master Number for DMA master. */
489 #define FEATURE_MPU_MASTER_DMA (2U)
490 /* @brief The MPU Logical Bus Master Number for ENET master. */
491 #define FEATURE_MPU_MASTER_ENET (3U)
492 /* @brief Specifies master number. */
493 #define FEATURE_MPU_MASTER \
494 { \
495  FEATURE_MPU_MASTER_CORE, \
496  FEATURE_MPU_MASTER_DEBUGGER, \
497  FEATURE_MPU_MASTER_DMA, \
498  FEATURE_MPU_MASTER_ENET, \
499 }
500 
501 /* @brief Specifies total number of slave ports. */
502 #define FEATURE_MPU_SLAVE_COUNT (5U)
503 /* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */
504 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
505 /* @brief The MPU Slave Port Assignment for SRAM back door. */
506 #define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U)
507 /* @brief The MPU Slave Port Assignment for SRAM_L front door. */
508 #define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U)
509 /* @brief The MPU Slave Port Assignment for SRAM_U front door. */
510 #define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U)
511 /* @brief The MPU Slave Port Assignment for QuadSPI. */
512 #define FEATURE_MPU_SLAVE_QUADSPI (4U)
513 /* @brief The MPU Slave Port mask. */
514 #define FEATURE_MPU_SLAVE_MASK (0xF8000000U)
515 #define FEATURE_MPU_SLAVE_SHIFT (27u)
516 #define FEATURE_MPU_SLAVE_WIDTH (5u)
517 #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
518 
519 /* WDOG module features */
520 
521 /* @brief The 32-bit value used for unlocking the WDOG. */
522 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
523 /* @brief The 32-bit value used for resetting the WDOG counter. */
524 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
525 /* @brief The reset value of the timeout register. */
526 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
527 /* @brief The value minimum of the timeout register. */
528 #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
529 /* @brief The reset value of the window register. */
530 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
531 /* @brief The mask of the reserved bit in the CS register. */
532 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
533 /* @brief The value used to set WDOG source clock from LPO. */
534 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
535 /* @brief The first 16-bit value used for unlocking the WDOG. */
536 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
537 /* @brief The second 16-bit value used for unlocking the WDOG. */
538 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
539 /* @brief The first 16-bit value used for resetting the WDOG counter. */
540 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
541 /* @brief The second 16-bit value used for resetting the WDOG counter. */
542 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
543 
544 
545 /* EDMA module features */
546 
547 /* @brief Number of EDMA channels. */
548 #define FEATURE_EDMA_MODULE_CHANNELS (16U)
549 /* @brief Number of EDMA channel interrupt lines. */
550 #define FEATURE_CHANNEL_INTERRUPT_LINES (16U)
551 /* @brief Number of EDMA error interrupt lines. */
552 #define FEATURE_ERROR_INTERRUPT_LINES (1U)
553 /* @brief eDMA module has error interrupt. */
554 #define FEATURE_EDMA_HAS_ERROR_IRQ
555 /* @brief eDMA module has separate interrupt lines for each channel. */
556 #define FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
557 /* @brief Conversion from channel index to DCHPRI index. */
558 #define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
559 /* @brief eDMA channel groups count. */
560 #define FEATURE_EDMA_CHANNEL_GROUP_COUNT (1U)
561 /* @brief Number of eDMA channels with asynchronous request capability. */
562 #define FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16U)
563 /* @brief Clock names for eDMA. */
564 #define EDMA_CLOCK_NAMES {SIM_DMA_CLK}
565 
566 /* DMAMUX module features */
567 
568 /* @brief Number of DMA channels. */
569 #define FEATURE_DMAMUX_MODULE_CHANNELS (16U)
570 /* @brief Has the periodic trigger capability */
571 #define FEATURE_DMAMUX_HAS_TRIG (1)
572 /* @brief Conversion from request source to the actual DMAMUX channel */
573 #define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x) (x)
574 /* @brief Mapping between request source and DMAMUX instance */
575 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
576 /* @brief Conversion from eDMA channel index to DMAMUX channel. */
577 #define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x) (x)
578 /* @brief Conversion from DMAMUX channel DMAMUX register index. */
579 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
580 /* @brief Clock names for DMAMUX. */
581 #define DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
582 
590 typedef enum {
656 
657 /* LPI2C module features */
658 
659 /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */
660 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
661 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
662 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
663 
664 /* FTM module features */
665 /* @brief Number of PWM channels */
666 #define FEATURE_FTM_CHANNEL_COUNT (8U)
667 /* @brief Number of fault channels */
668 #define FTM_FEATURE_FAULT_CHANNELS (4U)
669 /* @brief Width of control channel */
670 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
671 /* @brief Output channel offset */
672 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
673 /* @brief Max counter value */
674 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
675 /* @brief Input capture for single shot */
676 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
677 /* @brief Dithering has supported on the generated PWM signals */
678 #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (1U)
679 
680 /* CRC module features */
681 
682 /* @brief CRC module use for S32K1xx. */
683 #define FEATURE_CRC_DRIVER_S32K1xx (1)
684 /* Default CRC bit width */
685 #define CRC_DEFAULT_WIDTH CRC_BITS_16
686 /* Default CRC read transpose */
687 #define CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
688 /* Default polynomial 0x1021U */
689 #define CRC_DEFAULT_POLYNOMIAL (0x1021U)
690 
691 /* EWM module features */
692 
693 /* @brief First byte of the EWM Service key */
694 #define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U)
695 /* @brief Second byte of the EWM Service key */
696 #define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU)
697 /* @brief EWM Compare High register maximum value */
698 #define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU)
699 /* @brief EWM Compare Low register minimum value */
700 #define FEATURE_EWM_CMPL_MIN_VALUE (0x00U)
701 
702 /* CLOCK names */
703 
705 typedef enum {
706 
707  /* Main clocks */
708  CORE_CLK = 0u,
709  BUS_CLK = 1u,
710  SLOW_CLK = 2u,
711  CLKOUT_CLK = 3u,
713  /* Other internal clocks used by peripherals. */
714  SIRC_CLK = 4u,
715  FIRC_CLK = 5u,
716  SOSC_CLK = 6u,
717  SPLL_CLK = 7u,
720  SIRCDIV1_CLK = 10u,
721  SIRCDIV2_CLK = 11u,
722  FIRCDIV1_CLK = 12u,
723  FIRCDIV2_CLK = 13u,
724  SOSCDIV1_CLK = 14u,
725  SOSCDIV2_CLK = 15u,
726  SPLLDIV1_CLK = 16u,
727  SPLLDIV2_CLK = 17u,
730  /* SIM clocks */
741  SIM_LPO_CLK = 31u,
745  SIM_EIM_CLK = 35u,
746  SIM_ERM_CLK = 36u,
747  SIM_DMA_CLK = 37u,
748  SIM_MPU_CLK = 38u,
749  SIM_MSCM_CLK = 39u,
752  /* PCC clocks */
753  CMP0_CLK = 41u,
754  CRC0_CLK = 42u,
755  DMAMUX0_CLK = 43u,
756  EWM0_CLK = 44u,
757  PORTA_CLK = 45u,
758  PORTB_CLK = 46u,
759  PORTC_CLK = 47u,
760  PORTD_CLK = 48u,
761  PORTE_CLK = 49u,
762  QSPI0_CLK = 50u,
763  RTC0_CLK = 51u,
764  SAI0_CLK = 52u,
765  SAI1_CLK = 53u,
767  FlexCAN0_CLK = 55u,
768  FlexCAN1_CLK = 56u,
769  FlexCAN2_CLK = 57u,
770  PDB0_CLK = 58u,
771  PDB1_CLK = 59u,
773  FTFC0_CLK = 61u,
775  ENET0_CLK = 63u,
776  FTM0_CLK = 64u,
777  FTM1_CLK = 65u,
778  FTM2_CLK = 66u,
779  FTM3_CLK = 67u,
780  FTM4_CLK = 68u,
781  FTM5_CLK = 69u,
782  FTM6_CLK = 70u,
783  FTM7_CLK = 71u,
785  ADC0_CLK = 73u,
786  ADC1_CLK = 74u,
787  FLEXIO0_CLK = 75u,
788  LPI2C0_CLK = 76u,
789  LPI2C1_CLK = 77u,
790  LPIT0_CLK = 78u,
791  LPSPI0_CLK = 79u,
792  LPSPI1_CLK = 80u,
793  LPSPI2_CLK = 81u,
794  LPTMR0_CLK = 82u,
795  LPUART0_CLK = 83u,
796  LPUART1_CLK = 84u,
797  LPUART2_CLK = 85u,
801 } clock_names_t;
802 
803 #define PCC_INVALID_INDEX 0
804 
810 #define PCC_CLOCK_NAME_MAPPINGS \
811 { \
812 PCC_INVALID_INDEX, \
813 PCC_INVALID_INDEX, \
814 PCC_INVALID_INDEX, \
815 PCC_INVALID_INDEX, \
816 PCC_INVALID_INDEX, \
817 PCC_INVALID_INDEX, \
818 PCC_INVALID_INDEX, \
819 PCC_INVALID_INDEX, \
820 PCC_INVALID_INDEX, \
821 PCC_INVALID_INDEX, \
822 PCC_INVALID_INDEX, \
823 PCC_INVALID_INDEX, \
824 PCC_INVALID_INDEX, \
825 PCC_INVALID_INDEX, \
826 PCC_INVALID_INDEX, \
827 PCC_INVALID_INDEX, \
828 PCC_INVALID_INDEX, \
829 PCC_INVALID_INDEX, \
830 PCC_INVALID_INDEX, \
831 PCC_INVALID_INDEX, \
832 PCC_INVALID_INDEX, \
833 PCC_INVALID_INDEX, \
834 PCC_INVALID_INDEX, \
835 PCC_INVALID_INDEX, \
836 PCC_INVALID_INDEX, \
837 PCC_INVALID_INDEX, \
838 PCC_INVALID_INDEX, \
839 PCC_INVALID_INDEX, \
840 PCC_INVALID_INDEX, \
841 PCC_INVALID_INDEX, \
842 PCC_INVALID_INDEX, \
843 PCC_INVALID_INDEX, \
844 PCC_INVALID_INDEX, \
845 PCC_INVALID_INDEX, \
846 PCC_INVALID_INDEX, \
847 PCC_INVALID_INDEX, \
848 PCC_INVALID_INDEX, \
849 PCC_INVALID_INDEX, \
850 PCC_INVALID_INDEX, \
851 PCC_INVALID_INDEX, \
852 PCC_INVALID_INDEX, \
853 PCC_CMP0_INDEX, \
854 PCC_CRC_INDEX, \
855 PCC_DMAMUX_INDEX, \
856 PCC_EWM_INDEX, \
857 PCC_PORTA_INDEX, \
858 PCC_PORTB_INDEX, \
859 PCC_PORTC_INDEX, \
860 PCC_PORTD_INDEX, \
861 PCC_PORTE_INDEX, \
862 PCC_QSPI_INDEX, \
863 PCC_RTC_INDEX, \
864 PCC_SAI0_INDEX, \
865 PCC_SAI1_INDEX, \
866 PCC_INVALID_INDEX, \
867 PCC_FlexCAN0_INDEX, \
868 PCC_FlexCAN1_INDEX, \
869 PCC_FlexCAN2_INDEX, \
870 PCC_PDB0_INDEX, \
871 PCC_PDB1_INDEX, \
872 PCC_INVALID_INDEX, \
873 PCC_FTFC_INDEX, \
874 PCC_INVALID_INDEX, \
875 PCC_ENET_INDEX, \
876 PCC_FTM0_INDEX, \
877 PCC_FTM1_INDEX, \
878 PCC_FTM2_INDEX, \
879 PCC_FTM3_INDEX, \
880 PCC_FTM4_INDEX, \
881 PCC_FTM5_INDEX, \
882 PCC_FTM6_INDEX, \
883 PCC_FTM7_INDEX, \
884 PCC_INVALID_INDEX, \
885 PCC_ADC0_INDEX, \
886 PCC_ADC1_INDEX, \
887 PCC_FlexIO_INDEX, \
888 PCC_LPI2C0_INDEX, \
889 PCC_LPI2C1_INDEX, \
890 PCC_LPIT_INDEX, \
891 PCC_LPSPI0_INDEX, \
892 PCC_LPSPI1_INDEX, \
893 PCC_LPSPI2_INDEX, \
894 PCC_LPTMR0_INDEX, \
895 PCC_LPUART0_INDEX, \
896 PCC_LPUART1_INDEX, \
897 PCC_LPUART2_INDEX, \
898 PCC_INVALID_INDEX, \
899 PCC_INVALID_INDEX, \
900 }
901 
905 #define NO_PERIPHERAL_FEATURE (0U) /* It's not a peripheral instance, there is no peripheral feature. */
906 #define HAS_CLOCK_GATING_IN_SIM (1U << 0U) /* Clock gating is implemented in SIM (it's not in PCC) */
907 #define HAS_MULTIPLIER (1U << 1U) /* Multiplier is implemented in PCC */
908 #define HAS_DIVIDER (1U << 2U) /* Divider is implemented in PCC */
909 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U) /* Functional clock source is provided by the first asynchronous clock. */
910 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U) /* Functional clock source is provided by the second asynchronous clock. */
911 #define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U) /* Interface clock is provided by the bus clock. */
912 #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U) /* Interface clock is provided by the sys clock. */
913 #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U) /* Interface clock is provided by the slow clock. */
914 
919 #define PERIPHERAL_FEATURES \
920 { \
921 (NO_PERIPHERAL_FEATURE), \
922 (NO_PERIPHERAL_FEATURE), \
923 (NO_PERIPHERAL_FEATURE), \
924 (NO_PERIPHERAL_FEATURE), \
925 (NO_PERIPHERAL_FEATURE), \
926 (NO_PERIPHERAL_FEATURE), \
927 (NO_PERIPHERAL_FEATURE), \
928 (NO_PERIPHERAL_FEATURE), \
929 (NO_PERIPHERAL_FEATURE), \
930 (NO_PERIPHERAL_FEATURE), \
931 (NO_PERIPHERAL_FEATURE), \
932 (NO_PERIPHERAL_FEATURE), \
933 (NO_PERIPHERAL_FEATURE), \
934 (NO_PERIPHERAL_FEATURE), \
935 (NO_PERIPHERAL_FEATURE), \
936 (NO_PERIPHERAL_FEATURE), \
937 (NO_PERIPHERAL_FEATURE), \
938 (NO_PERIPHERAL_FEATURE), \
939 (NO_PERIPHERAL_FEATURE), \
940 (NO_PERIPHERAL_FEATURE), \
941 (NO_PERIPHERAL_FEATURE), \
942 (NO_PERIPHERAL_FEATURE), \
943 (NO_PERIPHERAL_FEATURE), \
944 (NO_PERIPHERAL_FEATURE), \
945 (NO_PERIPHERAL_FEATURE), \
946 (NO_PERIPHERAL_FEATURE), \
947 (NO_PERIPHERAL_FEATURE), \
948 (NO_PERIPHERAL_FEATURE), \
949 (NO_PERIPHERAL_FEATURE), \
950 (NO_PERIPHERAL_FEATURE), \
951 (NO_PERIPHERAL_FEATURE), \
952 (NO_PERIPHERAL_FEATURE), \
953 (NO_PERIPHERAL_FEATURE), \
954 (NO_PERIPHERAL_FEATURE), \
955 (NO_PERIPHERAL_FEATURE), \
956 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
957 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
958 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
959 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
960 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
961 (NO_PERIPHERAL_FEATURE), \
962 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
963 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
964 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
965 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
966 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
967 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
968 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
969 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
970 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
971 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
972 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
973 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
974 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
975 (NO_PERIPHERAL_FEATURE), \
976 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
977 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
978 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
979 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
980 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
981 (NO_PERIPHERAL_FEATURE), \
982 (HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
983 (NO_PERIPHERAL_FEATURE), \
984 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
985 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
986 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
987 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
988 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
989 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
990 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
991 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
992 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
993 (NO_PERIPHERAL_FEATURE), \
994 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
995 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
996 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
997 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
998 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
999 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1000 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1001 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1002 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1003 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1004 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1005 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1006 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
1007 (NO_PERIPHERAL_FEATURE), \
1008 (NO_PERIPHERAL_FEATURE), \
1009 }
1010 
1011 /* Time to wait for SIRC to stabilize (number of
1012  * cycles when core runs at maximum speed - 112 MHz */
1013 #define SIRC_STABILIZATION_TIMEOUT 26U;
1014 
1015 /* Time to wait for FIRC to stabilize (number of
1016  * cycles when core runs at maximum speed - 112 MHz */
1017 #define FIRC_STABILIZATION_TIMEOUT 10U;
1018 
1019 /* Time to wait for SOSC to stabilize (number of
1020  * cycles when core runs at maximum speed - 112 MHz */
1021 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
1022 
1023 /* Time to wait for SPLL to stabilize (number of
1024  * cycles when core runs at maximum speed - 112 MHz */
1025 #define SPLL_STABILIZATION_TIMEOUT 1000U;
1026 
1037 #define MAX_FREQ_VLPR 0U
1038 #define MAX_FREQ_RUN 1U
1039 #define MAX_FREQ_HSRUN 2U
1040 
1041 #define MAX_FREQ_SYS_CLK 0U
1042 #define MAX_FREQ_BUS_CLK 1U
1043 #define MAX_FREQ_SLOW_CLK 2U
1044 
1045 #define MAX_FREQ_MODES_NO 3U
1046 #define MAX_FREQ_CLK_NO 3U
1047 
1048 #define CLOCK_MAX_FREQUENCIES \
1049 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
1050 { 4000000, 4000000, 1000000}, \
1051 { 80000000,40000000,26670000}, \
1052 {112000000,56000000,28000000}, \
1053 }
1054 
1055 
1066 #define TMP_SIRC_CLK 0U
1067 #define TMP_FIRC_CLK 1U
1068 #define TMP_SOSC_CLK 2U
1069 #define TMP_SPLL_CLK 3U
1070 
1071 #define TMP_SYS_DIV 0U
1072 #define TMP_BUS_DIV 1U
1073 #define TMP_SLOW_DIV 2U
1074 
1075 #define TMP_SYS_CLK_NO 4U
1076 #define TMP_SYS_DIV_NO 3U
1077 
1078 #define TMP_SYSTEM_CLOCK_CONFIGS \
1079 { /* SYS_CLK BUS_CLK SLOW_CLK */ \
1080 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1}, \
1081 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
1082 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
1083 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
1084 }
1085 
1086 /* Do not use the old names of the renamed symbols */
1087 /* #define DO_NOT_USE_DEPRECATED_SYMBOLS */
1088 
1094 #if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS)
1095 #define CORE_CLOCK CORE_CLK
1096 #define BUS_CLOCK BUS_CLK
1097 #define SLOW_CLOCK SLOW_CLK
1098 #define CLKOUT_CLOCK CLKOUT_CLK
1099 #define SIRC_CLOCK SIRC_CLK
1100 #define FIRC_CLOCK FIRC_CLK
1101 #define SOSC_CLOCK SOSC_CLK
1102 #define SPLL_CLOCK SPLL_CLK
1103 #define RTC_CLKIN_CLOCK RTC_CLKIN_CLK
1104 #define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK
1105 #define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK
1106 #define SIM_LPO_CLOCK SIM_LPO_CLK
1107 #define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK
1108 #define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK
1109 #define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK
1110 #define SIM_EIM_CLOCK SIM_EIM_CLK
1111 #define SIM_ERM_CLOCK SIM_ERM_CLK
1112 #define SIM_DMA_CLOCK SIM_DMA_CLK
1113 #define SIM_MPU_CLOCK SIM_MPU_CLK
1114 #define SIM_MSCM_CLOCK SIM_MSCM_CLK
1115 #define PCC_DMAMUX0_CLOCK DMAMUX0_CLK
1116 #define PCC_CRC0_CLOCK CRC0_CLK
1117 #define PCC_RTC0_CLOCK RTC0_CLK
1118 #define PCC_PORTA_CLOCK PORTA_CLK
1119 #define PCC_PORTB_CLOCK PORTB_CLK
1120 #define PCC_PORTC_CLOCK PORTC_CLK
1121 #define PCC_PORTD_CLOCK PORTD_CLK
1122 #define PCC_PORTE_CLOCK PORTE_CLK
1123 #define PCC_EWM0_CLOCK EWM0_CLK
1124 #define PCC_CMP0_CLOCK CMP0_CLK
1125 #define PCC_FlexCAN0_CLOCK FlexCAN0_CLK
1126 #define PCC_FlexCAN1_CLOCK FlexCAN1_CLK
1127 #define PCC_FlexCAN2_CLOCK FlexCAN2_CLK
1128 #define PCC_PDB1_CLOCK PDB1_CLK
1129 #define PCC_PDB0_CLOCK PDB0_CLK
1130 #define PCC_FTFC0_CLOCK FTFC0_CLK
1131 #define PCC_FTM0_CLOCK FTM0_CLK
1132 #define PCC_FTM1_CLOCK FTM1_CLK
1133 #define PCC_FTM2_CLOCK FTM2_CLK
1134 #define PCC_FTM3_CLOCK FTM3_CLK
1135 #define PCC_ADC1_CLOCK ADC1_CLK
1136 #define PCC_LPSPI0_CLOCK LPSPI0_CLK
1137 #define PCC_LPSPI1_CLOCK LPSPI1_CLK
1138 #define PCC_LPSPI2_CLOCK LPSPI2_CLK
1139 #define PCC_LPIT0_CLOCK LPIT0_CLK
1140 #define PCC_ADC0_CLOCK ADC0_CLK
1141 #define PCC_LPTMR0_CLOCK LPTMR0_CLK
1142 #define PCC_FLEXIO0_CLOCK FLEXIO0_CLK
1143 #define PCC_LPI2C0_CLOCK LPI2C0_CLK
1144 #define PCC_LPUART0_CLOCK LPUART0_CLK
1145 #define PCC_LPUART1_CLOCK LPUART1_CLK
1146 #define PCC_LPUART2_CLOCK LPUART2_CLK
1147 #endif /* !DO_NOT_USE_DEPRECATED_SYMBOLS */
1148 
1149 
1150 /* CSEc module features */
1151 
1154 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
1155 
1157 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
1158 
1160 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
1161 
1163 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
1164 
1166 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
1167 
1169 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
1170 
1172 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
1173 
1174 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
1175 
1177 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
1178 
1180 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
1181 
1182 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
1183 
1184 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
1185 
1186 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
1187 
1188 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
1189 
1190 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
1191 
1192 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
1193 
1194 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
1195 
1196 
1197 /* ADC module features */
1198 
1201  #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (1)
1202 
1206 #define FEATURE_ADC_MAX_NUM_EXT_CHANS (32)
1207 
1209 #if FEATURE_ADC_HAS_EXTRA_NUM_REGS
1210 #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
1211 #else
1212 #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
1213 #endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */
1214 
1216 #define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
1217 
1218 #define ADC_DEFAULT_USER_GAIN (0x04U)
1219 
1220 /* MSCM module features */
1221 
1222 /* @brief Has interrupt router control registers (IRSPRCn). */
1223 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
1224 /* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */
1225 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
1226 
1227 /* SAI module features */
1228 #define SAI0_CHANNEL_COUNT 4U
1229 #define SAI1_CHANNEL_COUNT 1U
1230 #define SAI_MAX_CHANNEL_COUNT 4U
1231 
1232 /* ENET module features */
1233 
1235 #define FEATURE_ENET_CLOCK_NAMES { CORE_CLK }
1236 
1238 #define FEATURE_ENET_TX_IRQS ENET_TX_IRQS
1239 
1240 #define FEATURE_ENET_RX_IRQS ENET_RX_IRQS
1241 
1242 #define FEATURE_ENET_ERR_IRQS ENET_ERR_IRQS
1243 
1244 #define FEATURE_ENET_WAKE_IRQS ENET_WAKE_IRQS
1245 
1247 #define FEATURE_ENET_COUNTERS_OFFSET_WORDS 0x80
1248 
1250 #define FEATURE_ENET_MDC_MAX_FREQUENCY 2500000U
1251 
1253 #define FEATURE_ENET_MDIO_MIN_HOLD_TIME_NS 10U
1254 
1256 #define FEATURE_ENET_BUFF_ALIGNMENT (16U)
1257 
1258 #define FEATURE_ENET_BUFFDESCR_ALIGNMENT (16U)
1259 
1261 #define FEATURE_ENET_HAS_AVB (0)
1262 
1264 #define FEATURE_ENET_HAS_RECEIVE_PARSER (0)
1265 
1267 #define FEATURE_ENET_DEFAULT_PHY_IF ENET_MII_MODE
1268 
1269 /* QuadSPI module features */
1270 
1272 #define FEATURE_QSPI_ARDB_BASE 0x67000000U
1273 
1274 #define FEATURE_QSPI_ARDB_END 0x67FFFFFFU
1275 
1276 #define FEATURE_QSPI_AMBA_BASE 0x68000000U
1277 
1278 #define FEATURE_QSPI_AMBA_END 0x6FFFFFFFU
1279 
1280 #define FEATURE_QSPI_AHB_BUF_SIZE 1024U
1281 
1283 #define FEATURE_QSPI_DMA_TX_REQ {EDMA_REQ_QUADSPI_TX}
1284 
1285 #define FEATURE_QSPI_DMA_RX_REQ {EDMA_REQ_QUADSPI_RX}
1286 
1287 /* OSIF module features */
1288 
1289 #define FEATURE_OSIF_USE_SYSTICK (1)
1290 #define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */
1291 
1292 /* TRGMUX module features */
1293 
1294 #define FEATURE_TRGMUX_HAS_EXTENDED_NUM_TRIGS (1)
1295 
1296 /* LPSPI module features */
1297 /* @brief Initial value for state structure */
1298 #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL, NULL}
1299 
1300 #endif /* S32K148_FEATURES_H */
1301 
1302 /*******************************************************************************
1303  * EOF
1304  ******************************************************************************/
dma_request_source_t
Structure for the DMA hardware request.
clock_names_t
Clock names.
flexcan_clk_source_t