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S32 SDK
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Data Structures | |
struct | sbc_wtdog_ctr_t |
Watchdog control register structure. Watchdog configuration structure. More... | |
struct | sbc_sbc_t |
SBC configuration control register structure. Two operating modes have a major impact on the operation of the watchdog: Forced Normal mode and Software Development mode (Software Development mode is provided for test and development purposes only and is not a dedicated SBC operating mode; the UJA1169 can be in any functional operating mode with Software Development mode enabled). These modes are enabled and disabled via bits FNMC and SDMC respectively in the SBC configuration control register. Note that this register is located in the non-volatile memory area. The watchdog is disabled in Forced Normal mode (FNM). In Software Development mode (SDM), the watchdog can be disabled or activated for test and software debugging purposes. More... | |
struct | sbc_start_up_t |
Start-up control register structure. This structure contains settings of RSTN output reset pulse width and V2/VEXT start-up control. More... | |
struct | sbc_regulator_t |
Regulator control register structure. This structure set power distribution control, V2/VEXT configuration, set V1 reset threshold. More... | |
struct | sbc_supply_evnt_t |
Supply event capture enable register structure. This structure enables or disables detection of V2/VEXT overvoltage, undervoltage and V1 undervoltage enable. More... | |
struct | sbc_sys_evnt_t |
System event capture enable register structure. This structure enables or disables overtemperature warning, SPI failure enable. More... | |
struct | sbc_can_ctr_t |
CAN control register structure. This structure configure CAN peripheral behavior. More... | |
struct | sbc_trans_evnt_t |
Transceiver event capture enable register structure. Can bus silence, Can failure and Can wake-up settings. More... | |
struct | sbc_frame_t |
Frame control register structure. The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via bit IDE in the Frame control register. More... | |
struct | sbc_can_conf_t |
CAN configuration group structure. This structure configure CAN peripheral behavior. More... | |
struct | sbc_wake_t |
WAKE pin event capture enable register structure. Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register. A wake-up event is triggered by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that do not use the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND. More... | |
struct | sbc_regulator_ctr_t |
Regulator control register group. This structure is group of regulator settings. More... | |
struct | sbc_int_config_t |
Init configuration structure. This structure is used for initialization of sbc. More... | |
struct | sbc_factories_conf_t |
Factory configuration structure. It contains Start-up control register and SBC configuration control register. This is non-volatile memory with limited write access. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP; Bit NVMPS in the MTPNV status register indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow; performing a factory reset also increments the counter). This counter is provided for information purposes only; reprogramming will not be rejected when it reaches its maximum value. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: pin RSTN is held LOW, CANH is pulled up to VBAT, CANL is pulled down to GND After the factory preset values have been restored, the SBC performs a system reset and enters Forced normal Mode. Since the CAN-bus is clamped dominant, pin RXDC is forced LOW. Pin RXD is forced HIGH during the factory preset restore process (td(MTPNV)). A falling edge on RXD caused by bit PO being set after power-on indicates that the factory preset process has been completed. Note that the write counter, WRCNTS, in the MTPNV status register is incremented every time the factory presets are restored. More... | |
struct | sbc_main_status_t |
Main status register structure. The Main status register can be accessed to monitor the status of the overtemperature warning flag and to determine whether the UJA1169 has entered Normal mode after initial power-up. It also indicates the source of the most recent reset event. More... | |
struct | sbc_wtdog_status_t |
Watchdog status register structure. Information on the status of the watchdog is available from the Watchdog status register. This register also indicates whether Forced Normal and Software Development modes are active. More... | |
struct | sbc_supply_status_t |
Supply voltage status register structure. V2/VEXT and V1 undervoltage and overvoltage status. More... | |
struct | sbc_trans_stat_t |
Transceiver status register structure. There are stored CAN transceiver statuses. More... | |
struct | sbc_gl_evnt_stat_t |
Global event status register. The microcontroller can monitor events via the event status registers. An extra status register, the Global event status register, is provided to help speed up software polling routines. By polling the Global event status register, the microcontroller can quickly determine the type of event captured (system, supply, transceiver or WAKE pin) and then query the relevant event status register. More... | |
struct | sbc_sys_evnt_stat_t |
System event status register. Wake-up and interrupt event diagnosis in the UJA1169 is intended to provide the microcontroller with information on the status of a range of features and functions. This information is stored in the event status registers and is signaled on pin RXD, if enabled. More... | |
struct | sbc_sup_evnt_stat_t |
Supply event status register. More... | |
struct | sbc_trans_evnt_stat_t |
Transceiver event status register. More... | |
struct | sbc_wake_evnt_stat_t |
WAKE pin event status register. More... | |
struct | sbc_evn_capt_t |
Event capture registers structure. This structure contains Global event status, System event status, Supply event status, Transceiver event status, WAKE pin event status. More... | |
struct | sbc_mtpnv_stat_t |
MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP). Bit NVMPS in the MTPNV status register indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow; performing a factory reset also increments the counter). This counter is provided for information purposes only; reprogramming will not be rejected when it reaches its maximum value. More... | |
struct | sbc_status_group_t |
Status group structure. All statuses of SBC are stored in this structure. More... | |
Macros | |
#define | SBC_UJA_TIMEOUT 1000U |
#define | SBC_UJA_COUNT_ID_REG 4U |
#define | SBC_UJA_COUNT_MASK 4U |
#define | SBC_UJA_COUNT_DMASK 8U |
Typedefs | |
typedef uint8_t | sbc_fail_safe_rcc_t |
Fail-safe control register, reset counter control (0x02). incremented every time the SBC enters Reset mode while FNMC = 0; RCC overflows from 11 to 00; default at power-on is 00. More... | |
typedef uint8_t | sbc_identifier_t |
ID registers, identifier format (0x27 to 0x2A). A valid WUF identifier is defined and stored in the ID registers. An ID mask can be defined to allow a group of identifiers to be recognized as valid by an individual node. More... | |
typedef uint8_t | sbc_identif_mask_t |
ID mask registers (0x2B to 0x2E). The identifier mask is defined in the ID mask registers, where a 1 means dont care. More... | |
typedef uint8_t | sbc_frame_ctr_dlc_t |
Frame control register, number of data bytes expected in a CAN frame (0x2F). More... | |
typedef uint8_t | sbc_data_mask_t |
Data mask registers. The data field indicates the nodes to be woken up. Within the data field, groups of nodes can be predefined and associated with bits in a data mask. By comparing the incoming data field with the data mask, multiple groups of nodes can be woken up simultaneously with a single wake-up message. More... | |
typedef uint8_t | sbc_mtpnv_stat_wrcnts_t |
MTPNV status register, write counter status (0x70). 6-bits - contains the number of times the MTPNV cells were reprogrammed. More... | |
Enumerations | |
enum | sbc_register_t { SBC_UJA_WTDOG_CTR = 0x00U, SBC_UJA_MODE = 0x01U, SBC_UJA_FAIL_SAFE = 0x02U, SBC_UJA_MAIN = 0x03U, SBC_UJA_SYSTEM_EVNT = 0x04U, SBC_UJA_WTDOG_STAT = 0x05U, SBC_UJA_MEMORY_0 = 0x06U, SBC_UJA_MEMORY_1 = 0x07U, SBC_UJA_MEMORY_2 = 0x08U, SBC_UJA_MEMORY_3 = 0x09U, SBC_UJA_LOCK = 0x0AU, SBC_UJA_REGULATOR = 0x10U, SBC_UJA_SUPPLY_STAT = 0x1BU, SBC_UJA_SUPPLY_EVNT = 0x1CU, SBC_UJA_CAN = 0x20U, SBC_UJA_TRANS_STAT = 0x22U, SBC_UJA_TRANS_EVNT = 0x23U, SBC_UJA_DAT_RATE = 0x26U, SBC_UJA_IDENTIF_0 = 0x27U, SBC_UJA_IDENTIF_1 = 0x28U, SBC_UJA_IDENTIF_2 = 0x29U, SBC_UJA_IDENTIF_3 = 0x2AU, SBC_UJA_MASK_0 = 0x2BU, SBC_UJA_MASK_1 = 0x2CU, SBC_UJA_MASK_2 = 0x2DU, SBC_UJA_MASK_3 = 0x2EU, SBC_UJA_FRAME_CTR = 0x2FU, SBC_UJA_DAT_MASK_0 = 0x68U, SBC_UJA_DAT_MASK_1 = 0x69U, SBC_UJA_DAT_MASK_2 = 0x6AU, SBC_UJA_DAT_MASK_3 = 0x6BU, SBC_UJA_DAT_MASK_4 = 0x6CU, SBC_UJA_DAT_MASK_5 = 0x6DU, SBC_UJA_DAT_MASK_6 = 0x6EU, SBC_UJA_DAT_MASK_7 = 0x6FU, SBC_UJA_WAKE_STAT = 0x4BU, SBC_UJA_WAKE_EN = 0x4CU, SBC_UJA_GL_EVNT_STAT = 0x60U, SBC_UJA_SYS_EVNT_STAT = 0x61U, SBC_UJA_SUP_EVNT_STAT = 0x62U, SBC_UJA_TRANS_EVNT_STAT = 0x63U, SBC_UJA_WAKE_EVNT_STAT = 0x64U, SBC_UJA_MTPNV_STAT = 0x70U, SBC_UJA_START_UP = 0x73U, SBC_UJA_SBC = 0x74U, SBC_UJA_MTPNV_CRC = 0x75U, SBC_UJA_IDENTIF = 0x7EU } |
Register map. More... | |
enum | sbc_wtdog_ctr_wmc_t { SBC_UJA_WTDOG_CTR_WMC_AUTO = SBC_UJA_WTDOG_CTR_WMC_F(1U), SBC_UJA_WTDOG_CTR_WMC_TIME = SBC_UJA_WTDOG_CTR_WMC_F(2U), SBC_UJA_WTDOG_CTR_WMC_WIND = SBC_UJA_WTDOG_CTR_WMC_F(4U) } |
Watchdog control register, watchdog mode control (0x00). The UJA1169 contains a watchdog that supports three operating modes: Window, Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a watchdog trigger event within a defined watchdog window triggers and resets the watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered and reset at any time within the watchdog period by a watchdog trigger. Watchdog time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous mode, the watchdog can be off or autonomously in Timeout mode, depending on the selected SBC mode. The watchdog mode is selected via bits WMC in the Watchdog control register. The SBC must be in Standby mode when the watchdog mode is changed. More... | |
enum | sbc_wtdog_ctr_nwp_t { SBC_UJA_WTDOG_CTR_NWP_8 = 0x08U, SBC_UJA_WTDOG_CTR_NWP_16 = 0x01U, SBC_UJA_WTDOG_CTR_NWP_32 = 0x02U, SBC_UJA_WTDOG_CTR_NWP_64 = 0x0BU, SBC_UJA_WTDOG_CTR_NWP_128 = 0x04U, SBC_UJA_WTDOG_CTR_NWP_256 = 0x0DU, SBC_UJA_WTDOG_CTR_NWP_1024 = 0x0EU, SBC_UJA_WTDOG_CTR_NWP_4096 = 0x07U } |
Watchdog control register, nominal watchdog period (0x00). Eight watchdog periods are supported, from 8 ms to 4096 ms. The watchdog period is programmed via bits NWP. The selected period is valid for both Window and Timeout modes. The default watchdog period is 128 ms. A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid write access to the Watchdog control register. If the watchdog mode or the watchdog period have changed as a result of the write access, the new values are immediately valid. More... | |
enum | sbc_mode_mc_t { SBC_UJA_MODE_MC_SLEEP = 0x01U, SBC_UJA_MODE_MC_STANDBY = 0x04U, SBC_UJA_MODE_MC_NORMAL = 0x07U } |
Mode control register, mode control (0x01) More... | |
enum | sbc_fail_safe_lhc_t { SBC_UJA_FAIL_SAFE_LHC_FLOAT = SBC_UJA_FAIL_SAFE_LHC_F(0U), SBC_UJA_FAIL_SAFE_LHC_LOW = SBC_UJA_FAIL_SAFE_LHC_F(1U) } |
Fail-safe control register, LIMP home control (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register. More... | |
enum | sbc_main_otws_t { SBC_UJA_MAIN_OTWS_BELOW = SBC_UJA_MAIN_OTWS_F(0U), SBC_UJA_MAIN_OTWS_ABOVE = SBC_UJA_MAIN_OTWS_F(1U) } |
Main status register, Overtemperature warning status (0x03). More... | |
enum | sbc_main_nms_t { SBC_UJA_MAIN_NMS_NORMAL = SBC_UJA_MAIN_NMS_F(0U), SBC_UJA_MAIN_NMS_PWR_UP = SBC_UJA_MAIN_NMS_F(1U) } |
Main status register, normal mode status (0x03). More... | |
enum | sbc_main_rss_t { SBC_UJA_MAIN_RSS_OFF_MODE = 0x00U, SBC_UJA_MAIN_RSS_CAN_WAKEUP = 0x01U, SBC_UJA_MAIN_RSS_SLP_WAKEUP = 0x04U, SBC_UJA_MAIN_RSS_OVF_SLP = 0x0CU, SBC_UJA_MAIN_RSS_DIAG_WAKEUP = 0x0DU, SBC_UJA_MAIN_RSS_WATCH_TRIG = 0x0EU, SBC_UJA_MAIN_RSS_WATCH_OVF = 0x0FU, SBC_UJA_MAIN_RSS_ILLEG_WATCH = 0x10U, SBC_UJA_MAIN_RSS_RSTN_PULDW = 0x11U, SBC_UJA_MAIN_RSS_LFT_OVERTM = 0x12U, SBC_UJA_MAIN_RSS_V1_UNDERV = 0x13U, SBC_UJA_MAIN_RSS_ILLEG_SLP = 0x14U, SBC_UJA_MAIN_RSS_WAKE_SLP = 0x16U } |
Main status register, Reset source status (0x03). More... | |
enum | sbc_sys_evnt_otwe_t { SBC_UJA_SYS_EVNT_OTWE_DIS = SBC_UJA_SYS_EVNT_OTWE_F(0U), SBC_UJA_SYS_EVNT_OTWE_EN = SBC_UJA_SYS_EVNT_OTWE_F(1U) } |
System event capture enable, overtemperature warning enable (0x04). More... | |
enum | sbc_sys_evnt_spife_t { SBC_UJA_SYS_EVNT_SPIFE_DIS = SBC_UJA_SYS_EVNT_SPIFE_F(0U), SBC_UJA_SYS_EVNT_SPIFE_EN = SBC_UJA_SYS_EVNT_SPIFE_F(1U) } |
System event capture enable, SPI failure enable (0x04). More... | |
enum | sbc_wtdog_stat_fnms_t { SBC_UJA_WTDOG_STAT_FNMS_N_NORMAL = SBC_UJA_WTDOG_STAT_FNMS_F(0U), SBC_UJA_WTDOG_STAT_FNMS_NORMAL = SBC_UJA_WTDOG_STAT_FNMS_F(1U) } |
Watchdog status register, forced Normal mode status (0x05). More... | |
enum | sbc_wtdog_stat_sdms_t { SBC_UJA_WTDOG_STAT_SDMS_N_NORMAL = SBC_UJA_WTDOG_STAT_SDMS_F(0U), SBC_UJA_WTDOG_STAT_SDMS_NORMAL = SBC_UJA_WTDOG_STAT_SDMS_F(1U) } |
Watchdog status register, Software Development mode status (0x05). More... | |
enum | sbc_wtdog_stat_wds_t { SBC_UJA_WTDOG_STAT_WDS_OFF = SBC_UJA_WTDOG_STAT_WDS_F(0U), SBC_UJA_WTDOG_STAT_WDS_FIH = SBC_UJA_WTDOG_STAT_WDS_F(1U), SBC_UJA_WTDOG_STAT_WDS_SEH = SBC_UJA_WTDOG_STAT_WDS_F(2U) } |
Watchdog status register, watchdog status (0x05). More... | |
enum | sbc_lock_t { LK0C = SBC_UJA_LOCK_LK0C_MASK, LK1C = SBC_UJA_LOCK_LK1C_MASK, LK2C = SBC_UJA_LOCK_LK2C_MASK, LK3C = SBC_UJA_LOCK_LK3C_MASK, LK4C = SBC_UJA_LOCK_LK4C_MASK, LK5C = SBC_UJA_LOCK_LK5C_MASK, LK6C = SBC_UJA_LOCK_LK6C_MASK, LKAC = SBC_UJA_LOCK_LKNC_MASK } |
Lock control(0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc. More... | |
enum | sbc_regulator_pdc_t { SBC_UJA_REGULATOR_PDC_HV = SBC_UJA_REGULATOR_PDC_F(0U), SBC_UJA_REGULATOR_PDC_LV = SBC_UJA_REGULATOR_PDC_F(1U) } |
Regulator control register, power distribution control (0x10). More... | |
enum | sbc_regulator_v2c_t { SBC_UJA_REGULATOR_V2C_OFF = SBC_UJA_REGULATOR_V2C_F(0U), SBC_UJA_REGULATOR_V2C_N = SBC_UJA_REGULATOR_V2C_F(1U), SBC_UJA_REGULATOR_V2C_N_S_R = SBC_UJA_REGULATOR_V2C_F(2U), SBC_UJA_REGULATOR_V2C_N_S_S_R = SBC_UJA_REGULATOR_V2C_F(3U) } |
Regulator control register, V2/VEXT configuration (0x10). More... | |
enum | sbc_regulator_v1rtc_t { SBC_UJA_REGULATOR_V1RTC_90 = SBC_UJA_REGULATOR_V1RTC_F(0U), SBC_UJA_REGULATOR_V1RTC_80 = SBC_UJA_REGULATOR_V1RTC_F(1U), SBC_UJA_REGULATOR_V1RTC_70 = SBC_UJA_REGULATOR_V1RTC_F(2U), SBC_UJA_REGULATOR_V1RTC_60 = SBC_UJA_REGULATOR_V1RTC_F(3U) } |
Regulator control register, set V1 reset threshold (0x10). More... | |
enum | sbc_supply_stat_v2s_t { SBC_UJA_SUPPLY_STAT_V2S_VOK = SBC_UJA_SUPPLY_STAT_V2S_F(0U), SBC_UJA_SUPPLY_STAT_V2S_VBE = SBC_UJA_SUPPLY_STAT_V2S_F(1U), SBC_UJA_SUPPLY_STAT_V2S_VAB = SBC_UJA_SUPPLY_STAT_V2S_F(2U), SBC_UJA_SUPPLY_STAT_V2S_DIS = SBC_UJA_SUPPLY_STAT_V2S_F(3U) } |
Supply voltage status register, V2/VEXT status (0x1B). More... | |
enum | sbc_supply_stat_v1s_t { SBC_UJA_SUPPLY_STAT_V1S_VAB = SBC_UJA_SUPPLY_STAT_V1S_F(0U), SBC_UJA_SUPPLY_STAT_V1S_VBE = SBC_UJA_SUPPLY_STAT_V1S_F(1U) } |
Supply voltage status register, V1 status (0x1B). More... | |
enum | sbc_supply_evnt_v2oe_t { SBC_UJA_SUPPLY_EVNT_V2OE_DIS = SBC_UJA_SUPPLY_EVNT_V2OE_F(0U), SBC_UJA_SUPPLY_EVNT_V2OE_EN = SBC_UJA_SUPPLY_EVNT_V2OE_F(1U) } |
Supply event capture enable register, V2/VEXT overvoltage enable (0x1C). More... | |
enum | sbc_supply_evnt_v2ue_t { SBC_UJA_SUPPLY_EVNT_V2UE_DIS = SBC_UJA_SUPPLY_EVNT_V2UE_F(0U), SBC_UJA_SUPPLY_EVNT_V2UE_EN = SBC_UJA_SUPPLY_EVNT_V2UE_F(1U) } |
Supply event capture enable register, V2/VEXT undervoltage enable (0x1C). More... | |
enum | sbc_supply_evnt_v1ue_t { SBC_UJA_SUPPLY_EVNT_V1UE_DIS = SBC_UJA_SUPPLY_EVNT_V1UE_F(0U), SBC_UJA_SUPPLY_EVNT_V1UE_EN = SBC_UJA_SUPPLY_EVNT_V1UE_F(1U) } |
Supply event capture enable register, V1 undervoltage enable (0x1C). More... | |
enum | sbc_can_cfdc_t { SBC_UJA_CAN_CFDC_DIS = SBC_UJA_CAN_CFDC_F(0U), SBC_UJA_CAN_CFDC_EN = SBC_UJA_CAN_CFDC_F(1U) } |
CAN control register, CAN FD control (0x20). More... | |
enum | sbc_can_pncok_t { SBC_UJA_CAN_PNCOK_DIS = SBC_UJA_CAN_PNCOK_F(0U), SBC_UJA_CAN_PNCOK_EN = SBC_UJA_CAN_PNCOK_F(1U) } |
CAN control register, CAN partial networking configuration OK (0x20). More... | |
enum | sbc_can_cpnc_t { SBC_UJA_CAN_CPNC_DIS = SBC_UJA_CAN_CPNC_F(0U), SBC_UJA_CAN_CPNC_EN = SBC_UJA_CAN_CPNC_F(1U) } |
CAN control register, CAN partial networking control (0x20). More... | |
enum | sbc_can_cmc_t { SBC_UJA_CAN_CMC_OFMODE = SBC_UJA_CAN_CMC_F(0U), SBC_UJA_CAN_CMC_ACMODE_DA = SBC_UJA_CAN_CMC_F(1U), SBC_UJA_CAN_CMC_ACMODE_DD = SBC_UJA_CAN_CMC_F(2U), SBC_UJA_CAN_CMC_LISTEN = SBC_UJA_CAN_CMC_F(3U) } |
CAN control register, CAN mode control (0x20). More... | |
enum | sbc_trans_stat_cts_t { SBC_UJA_TRANS_STAT_CTS_INACT = SBC_UJA_TRANS_STAT_CTS_F(0U), SBC_UJA_TRANS_STAT_CTS_ACT = SBC_UJA_TRANS_STAT_CTS_F(1U) } |
Transceiver status register, CAN transceiver status (0x22). More... | |
enum | sbc_trans_stat_cpnerr_t { SBC_UJA_TRANS_STAT_CPNERR_NO_DET = SBC_UJA_TRANS_STAT_CPNERR_F(0U), SBC_UJA_TRANS_STAT_CPNERR_DET = SBC_UJA_TRANS_STAT_CPNERR_F(1U) } |
Transceiver status register, CAN partial networking error (0x22). More... | |
enum | sbc_trans_stat_cpns_t { SBC_UJA_TRANS_STAT_CPNS_ERR = SBC_UJA_TRANS_STAT_CPNS_F(0U), SBC_UJA_TRANS_STAT_CPNS_OK = SBC_UJA_TRANS_STAT_CPNS_F(1U) } |
Transceiver status register, CAN partial networking status (0x22). More... | |
enum | sbc_trans_stat_coscs_t { SBC_UJA_TRANS_STAT_COSCS_NRUN = SBC_UJA_TRANS_STAT_COSCS_F(0U), SBC_UJA_TRANS_STAT_COSCS_RUN = SBC_UJA_TRANS_STAT_COSCS_F(1U) } |
Transceiver status register, CAN oscillator status (0x22). More... | |
enum | sbc_trans_stat_cbss_t { SBC_UJA_TRANS_STAT_CBSS_ACT = SBC_UJA_TRANS_STAT_CBSS_F(0U), SBC_UJA_TRANS_STAT_CBSS_INACT = SBC_UJA_TRANS_STAT_CBSS_F(1U) } |
Transceiver status register, CAN-bus silence status (0x22). More... | |
enum | sbc_trans_stat_vcs_t { SBC_UJA_TRANS_STAT_VCS_AB = SBC_UJA_TRANS_STAT_VCS_F(0U), SBC_UJA_TRANS_STAT_VCS_BE = SBC_UJA_TRANS_STAT_VCS_F(1U) } |
Transceiver status register, VCAN status (0x22). More... | |
enum | sbc_trans_stat_cfs_t { SBC_UJA_TRANS_STAT_CFS_NO_TXD = SBC_UJA_TRANS_STAT_CFS_F(0U), SBC_UJA_TRANS_STAT_CFS_TXD = SBC_UJA_TRANS_STAT_CFS_F(1U) } |
Transceiver status register, CAN failure status (0x22). More... | |
enum | sbc_trans_evnt_cbse_t { SBC_UJA_TRANS_EVNT_CBSE_DIS = SBC_UJA_TRANS_EVNT_CBSE_F(0U), SBC_UJA_TRANS_EVNT_CBSE_EN = SBC_UJA_TRANS_EVNT_CBSE_F(1U) } |
Transceiver event capture enable register, CAN-bus silence enable (0x23). More... | |
enum | sbc_trans_evnt_cfe_t { SBC_UJA_TRANS_EVNT_CFE_DIS = SBC_UJA_TRANS_EVNT_CFE_F(0U), SBC_UJA_TRANS_EVNT_CFE_EN = SBC_UJA_TRANS_EVNT_CFE_F(1U) } |
Transceiver event capture enable register, CAN failure enable (0x23). More... | |
enum | sbc_trans_evnt_cwe_t { SBC_UJA_TRANS_EVNT_CWE_DIS = SBC_UJA_TRANS_EVNT_CWE_F(0U), SBC_UJA_TRANS_EVNT_CWE_EN = SBC_UJA_TRANS_EVNT_CWE_F(1U) } |
Transceiver event capture enable register, CAN wake-up enable (0x23). More... | |
enum | sbc_dat_rate_t { SBC_UJA_DAT_RATE_CDR_50KB = SBC_UJA_DAT_RATE_CDR_F(0U), SBC_UJA_DAT_RATE_CDR_100KB = SBC_UJA_DAT_RATE_CDR_F(1U), SBC_UJA_DAT_RATE_CDR_125KB = SBC_UJA_DAT_RATE_CDR_F(2U), SBC_UJA_DAT_RATE_CDR_250KB = SBC_UJA_DAT_RATE_CDR_F(3U), SBC_UJA_DAT_RATE_CDR_500KB = SBC_UJA_DAT_RATE_CDR_F(5U), SBC_UJA_DAT_RATE_CDR_1000KB = SBC_UJA_DAT_RATE_CDR_F(7U) } |
Data rate register, CAN data rate selection (0x26). CAN partial networking configuration registers. Dedicated registers are provided for configuring CAN partial networking. More... | |
enum | sbc_frame_ctr_ide_t { SBC_UJA_FRAME_CTR_IDE_11B = SBC_UJA_FRAME_CTR_IDE_F(0U), SBC_UJA_FRAME_CTR_IDE_29B = SBC_UJA_FRAME_CTR_IDE_F(1U) } |
Frame control register, identifier format (0x2F). The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via bit IDE in the Frame control register. More... | |
enum | sbc_frame_ctr_pndm_t { SBC_UJA_FRAME_CTR_PNDM_DCARE = SBC_UJA_FRAME_CTR_PNDM_F(0U), SBC_UJA_FRAME_CTR_PNDM_EVAL = SBC_UJA_FRAME_CTR_PNDM_F(1U) } |
Frame control register, partial networking data mask (0x2F). More... | |
enum | sbc_wake_stat_wpvs_t { SBC_UJA_WAKE_STAT_WPVS_BE = SBC_UJA_WAKE_STAT_WPVS_F(0U), SBC_UJA_WAKE_STAT_WPVS_AB = SBC_UJA_WAKE_STAT_WPVS_F(1U) } |
WAKE pin status register, WAKE pin status (0x4B). More... | |
enum | sbc_wake_en_wpre_t { SBC_UJA_WAKE_EN_WPRE_DIS = SBC_UJA_WAKE_EN_WPRE_F(0U), SBC_UJA_WAKE_EN_WPRE_EN = SBC_UJA_WAKE_EN_WPRE_F(1U) } |
WAKE pin event capture enable register, WAKE pin rising-edge enable (0x4C). More... | |
enum | sbc_wake_en_wpfe_t { SBC_UJA_WAKE_EN_WPFE_DIS = SBC_UJA_WAKE_EN_WPFE_F(0U), SBC_UJA_WAKE_EN_WPFE_EN = SBC_UJA_WAKE_EN_WPFE_F(1U) } |
WAKE pin event capture enable register, WAKE pin falling-edge enable (0x4C). More... | |
enum | sbc_gl_evnt_stat_wpe_t { SBC_UJA_GL_EVNT_STAT_WPE_NO = SBC_UJA_GL_EVNT_STAT_WPE_F(0U), SBC_UJA_GL_EVNT_STAT_WPE = SBC_UJA_GL_EVNT_STAT_WPE_F(1U) } |
Global event status register, WAKE pin event (0x60). More... | |
enum | sbc_gl_evnt_stat_trxe_t { SBC_UJA_GL_EVNT_STAT_TRXE_NO = SBC_UJA_GL_EVNT_STAT_TRXE_F(0U), SBC_UJA_GL_EVNT_STAT_TRXE = SBC_UJA_GL_EVNT_STAT_TRXE_F(1U) } |
Global event status register, transceiver event (0x60). More... | |
enum | sbc_gl_evnt_stat_supe_t { SBC_UJA_GL_EVNT_STAT_SUPE_NO = SBC_UJA_GL_EVNT_STAT_SUPE_F(0U), SBC_UJA_GL_EVNT_STAT_SUPE = SBC_UJA_GL_EVNT_STAT_SUPE_F(1U) } |
Global event status register, supply event (0x60). More... | |
enum | sbc_gl_evnt_stat_syse_t { SBC_UJA_GL_EVNT_STAT_SYSE_NO = SBC_UJA_GL_EVNT_STAT_SYSE_F(0U), SBC_UJA_GL_EVNT_STAT_SYSE = SBC_UJA_GL_EVNT_STAT_SYSE_F(1U) } |
Global event status register, system event (0x60). More... | |
enum | sbc_sys_evnt_stat_po_t { SBC_UJA_SYS_EVNT_STAT_PO_NO = SBC_UJA_SYS_EVNT_STAT_PO_F(0U), SBC_UJA_SYS_EVNT_STAT_PO = SBC_UJA_SYS_EVNT_STAT_PO_F(1U) } |
System event status register, power-on (0x61). More... | |
enum | sbc_sys_evnt_stat_otw_t { SBC_UJA_SYS_EVNT_STAT_OTW_NO = SBC_UJA_SYS_EVNT_STAT_OTW_F(0U), SBC_UJA_SYS_EVNT_STAT_OTW = SBC_UJA_SYS_EVNT_STAT_OTW_F(1U) } |
System event status register, overtemperature warning (0x61). More... | |
enum | sbc_sys_evnt_stat_spif_t { SBC_UJA_SYS_EVNT_STAT_SPIF_NO = SBC_UJA_SYS_EVNT_STAT_SPIF_F(0U), SBC_UJA_SYS_EVNT_STAT_SPIF = SBC_UJA_SYS_EVNT_STAT_SPIF_F(1U) } |
System event status register, SPI failure (0x61). More... | |
enum | sbc_sys_evnt_stat_wdf_t { SBC_UJA_SYS_EVNT_STAT_WDF_NO = SBC_UJA_SYS_EVNT_STAT_WDF_F(0U), SBC_UJA_SYS_EVNT_STAT_WDF = SBC_UJA_SYS_EVNT_STAT_WDF_F(1U) } |
System event status register, watchdog failure (0x61). More... | |
enum | sbc_sup_evnt_stat_v2o_t { SBC_UJA_SUP_EVNT_STAT_V2O_NO = SBC_UJA_SUP_EVNT_STAT_V2O_F(0U), SBC_UJA_SUP_EVNT_STAT_V2O = SBC_UJA_SUP_EVNT_STAT_V2O_F(1U) } |
Supply event status register, V2/VEXT overvoltage (0x62). More... | |
enum | sbc_sup_evnt_stat_v2u_t { SBC_UJA_SUP_EVNT_STAT_V2U_NO = SBC_UJA_SUP_EVNT_STAT_V2U_F(0U), SBC_UJA_SUP_EVNT_STAT_V2U = SBC_UJA_SUP_EVNT_STAT_V2U_F(1U) } |
Supply event status register, V2/VEXT undervoltage (0x62). More... | |
enum | sbc_sup_evnt_stat_v1u_t { SBC_UJA_SUP_EVNT_STAT_V1U_NO = SBC_UJA_SUP_EVNT_STAT_V1U_F(0U), SBC_UJA_SUP_EVNT_STAT_V1U = SBC_UJA_SUP_EVNT_STAT_V1U_F(1U) } |
Supply event status register, V1 undervoltage (0x62). More... | |
enum | sbc_trans_evnt_stat_pnfde_t { SBC_UJA_TRANS_EVNT_STAT_PNFDE_NO = SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(0U), SBC_UJA_TRANS_EVNT_STAT_PNFDE = SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(1U) } |
Transceiver event status register,partial networking frame detection error (0x63). More... | |
enum | sbc_trans_evnt_stat_cbs_t { SBC_UJA_TRANS_EVNT_STAT_CBS_NO = SBC_UJA_TRANS_EVNT_STAT_CBS_F(0U), SBC_UJA_TRANS_EVNT_STAT_CBS = SBC_UJA_TRANS_EVNT_STAT_CBS_F(1U) } |
Transceiver event status register, CAN-bus status (0x63). More... | |
enum | sbc_trans_evnt_stat_cf_t { SBC_UJA_TRANS_EVNT_STAT_CF_NO = SBC_UJA_TRANS_EVNT_STAT_CF_F(0U), SBC_UJA_TRANS_EVNT_STAT_CF = SBC_UJA_TRANS_EVNT_STAT_CF_F(1U) } |
Transceiver event status register, CAN failure (0x63). More... | |
enum | sbc_trans_evnt_stat_cw_t { SBC_UJA_TRANS_EVNT_STAT_CW_NO = SBC_UJA_TRANS_EVNT_STAT_CW_F(0U), SBC_UJA_TRANS_EVNT_STAT_CW = SBC_UJA_TRANS_EVNT_STAT_CW_F(1U) } |
Transceiver event status register, CAN wake-up (0x63). More... | |
enum | sbc_wake_evnt_stat_wpr_t { SBC_UJA_WAKE_EVNT_STAT_WPR_NO = SBC_UJA_WAKE_EVNT_STAT_WPR_F(0U), SBC_UJA_WAKE_EVNT_STAT_WPR = SBC_UJA_WAKE_EVNT_STAT_WPR_F(1U) } |
WAKE pin event status register, WAKE pin rising edge (0x64). More... | |
enum | sbc_wake_evnt_stat_wpf_t { SBC_UJA_WAKE_EVNT_STAT_WPF_NO = SBC_UJA_WAKE_EVNT_STAT_WPF_F(0U), SBC_UJA_WAKE_EVNT_STAT_WPF = SBC_UJA_WAKE_EVNT_STAT_WPF_F(1U) } |
WAKE pin event status register, WAKE pin falling edge (0x64). More... | |
enum | sbc_mtpnv_stat_eccs_t { SBC_UJA_MTPNV_STAT_ECCS_NO = SBC_UJA_MTPNV_STAT_ECCS_F(0U), SBC_UJA_MTPNV_STAT_ECCS = SBC_UJA_MTPNV_STAT_ECCS_F(1U) } |
MTPNV status register, error correction code status (0x70). More... | |
enum | sbc_mtpnv_stat_nvmps_t { SBC_UJA_MTPNV_STAT_NVMPS_NO = SBC_UJA_MTPNV_STAT_NVMPS_F(0U), SBC_UJA_MTPNV_STAT_NVMPS = SBC_UJA_MTPNV_STAT_NVMPS_F(1U) } |
MTPNV status register, non-volatile memory programming status (0x70). More... | |
enum | sbc_start_up_rlc_t { SBC_UJA_START_UP_RLC_20_25p0 = SBC_UJA_START_UP_RLC_F(0U), SBC_UJA_START_UP_RLC_10_12p5 = SBC_UJA_START_UP_RLC_F(1U), SBC_UJA_START_UP_RLC_03p6_05 = SBC_UJA_START_UP_RLC_F(2U), SBC_UJA_START_UP_RLC_01_01p5 = SBC_UJA_START_UP_RLC_F(3U) } |
Start-up control register, RSTN output reset pulse width macros (0x73). More... | |
enum | sbc_start_up_v2suc_t { SBC_UJA_START_UP_V2SUC_00 = SBC_UJA_START_UP_V2SUC_F(0U), SBC_UJA_START_UP_V2SUC_11 = SBC_UJA_START_UP_V2SUC_F(1U) } |
Start-up control register, V2/VEXT start-up control (0x73). More... | |
enum | sbc_sbc_v1rtsuc_t { SBC_UJA_SBC_V1RTSUC_90 = SBC_UJA_SBC_V1RTSUC_F(0U), SBC_UJA_SBC_V1RTSUC_80 = SBC_UJA_SBC_V1RTSUC_F(1U), SBC_UJA_SBC_V1RTSUC_70 = SBC_UJA_SBC_V1RTSUC_F(2U), SBC_UJA_SBC_V1RTSUC_60 = SBC_UJA_SBC_V1RTSUC_F(3U) } |
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x74). More... | |
enum | sbc_sbc_fnmc_t { SBC_UJA_SBC_FNMC_DIS = SBC_UJA_SBC_FNMC_F(0U), SBC_UJA_SBC_FNMC_EN = SBC_UJA_SBC_FNMC_F(1U) } |
SBC configuration control register, Forced Normal mode control (0x74). More... | |
enum | sbc_sbc_sdmc_t { SBC_UJA_SBC_SDMC_DIS = SBC_UJA_SBC_SDMC_F(0U), SBC_UJA_SBC_SDMC_EN = SBC_UJA_SBC_SDMC_F(1U) } |
SBC configuration control register, Software Development mode control (0x74). More... | |
enum | sbc_sbc_slpc_t { SBC_UJA_SBC_SLPC_AC = SBC_UJA_SBC_SLPC_F(0U), SBC_UJA_SBC_SLPC_IG = SBC_UJA_SBC_SLPC_F(1U) } |
SBC configuration control register, Sleep control (0x74). More... | |
#define SBC_UJA_COUNT_DMASK 8U |
Definition at line 44 of file sbc_uja1169_driver.h.
#define SBC_UJA_COUNT_ID_REG 4U |
Definition at line 42 of file sbc_uja1169_driver.h.
#define SBC_UJA_COUNT_MASK 4U |
Definition at line 43 of file sbc_uja1169_driver.h.
#define SBC_UJA_TIMEOUT 1000U |
Timeout for the transfer in milliseconds. If the transfer takes longer than this time, the transfer is aborted and LPSPI_STATUS_SBC_UJA_TIMEOUT error is reported.
Definition at line 36 of file sbc_uja1169_driver.h.
typedef uint8_t sbc_data_mask_t |
Data mask registers. The data field indicates the nodes to be woken up. Within the data field, groups of nodes can be predefined and associated with bits in a data mask. By comparing the incoming data field with the data mask, multiple groups of nodes can be woken up simultaneously with a single wake-up message.
Implements : sbc_data_mask_t_Class
Definition at line 707 of file sbc_uja1169_driver.h.
typedef uint8_t sbc_fail_safe_rcc_t |
Fail-safe control register, reset counter control (0x02). incremented every time the SBC enters Reset mode while FNMC = 0; RCC overflows from 11 to 00; default at power-on is 00.
Implements : sbc_fail_safe_rcc_t_Class
Definition at line 198 of file sbc_uja1169_driver.h.
typedef uint8_t sbc_frame_ctr_dlc_t |
Frame control register, number of data bytes expected in a CAN frame (0x2F).
Implements : sbc_frame_ctr_dlc_t_Class
Definition at line 696 of file sbc_uja1169_driver.h.
typedef uint8_t sbc_identif_mask_t |
ID mask registers (0x2B to 0x2E). The identifier mask is defined in the ID mask registers, where a 1 means dont care.
Implements : sbc_identif_mask_t_Class
Definition at line 662 of file sbc_uja1169_driver.h.
typedef uint8_t sbc_identifier_t |
ID registers, identifier format (0x27 to 0x2A). A valid WUF identifier is defined and stored in the ID registers. An ID mask can be defined to allow a group of identifiers to be recognized as valid by an individual node.
Implements : sbc_identifier_t_Class
Definition at line 653 of file sbc_uja1169_driver.h.
typedef uint8_t sbc_mtpnv_stat_wrcnts_t |
MTPNV status register, write counter status (0x70). 6-bits - contains the number of times the MTPNV cells were reprogrammed.
Implements : sbc_mtpnv_stat_wrcnts_t_Class
Definition at line 968 of file sbc_uja1169_driver.h.
enum sbc_can_cfdc_t |
CAN control register, CAN FD control (0x20).
Implements : sbc_can_cfdc_t_Class
Enumerator | |
---|---|
SBC_UJA_CAN_CFDC_DIS |
CAN FD tolerance disabled. |
SBC_UJA_CAN_CFDC_EN |
CAN FD tolerance enabled. |
Definition at line 461 of file sbc_uja1169_driver.h.
enum sbc_can_cmc_t |
CAN control register, CAN mode control (0x20).
Implements : sbc_can_cmc_t_Class
Definition at line 497 of file sbc_uja1169_driver.h.
enum sbc_can_cpnc_t |
CAN control register, CAN partial networking control (0x20).
Implements : sbc_can_cpnc_t_Class
Enumerator | |
---|---|
SBC_UJA_CAN_CPNC_DIS |
Disable CAN selective wake-up. |
SBC_UJA_CAN_CPNC_EN |
Enable CAN selective wake-up. |
Definition at line 485 of file sbc_uja1169_driver.h.
enum sbc_can_pncok_t |
CAN control register, CAN partial networking configuration OK (0x20).
Implements : sbc_can_pncok_t_Class
Definition at line 473 of file sbc_uja1169_driver.h.
enum sbc_dat_rate_t |
Data rate register, CAN data rate selection (0x26). CAN partial networking configuration registers. Dedicated registers are provided for configuring CAN partial networking.
Implements : sbc_dat_rate_t_Class
Definition at line 636 of file sbc_uja1169_driver.h.
enum sbc_fail_safe_lhc_t |
Fail-safe control register, LIMP home control (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register.
Implements : sbc_fail_safe_lhc_t_Class
Enumerator | |
---|---|
SBC_UJA_FAIL_SAFE_LHC_FLOAT |
LIMP pin is floating. |
SBC_UJA_FAIL_SAFE_LHC_LOW |
LIMP pin is driven LOW. |
Definition at line 186 of file sbc_uja1169_driver.h.
enum sbc_frame_ctr_ide_t |
Frame control register, identifier format (0x2F). The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via bit IDE in the Frame control register.
Implements : sbc_frame_ctr_ide_t_Class
Enumerator | |
---|---|
SBC_UJA_FRAME_CTR_IDE_11B |
Standard frame format (11-bit). |
SBC_UJA_FRAME_CTR_IDE_29B |
Extended frame format (29-bit). |
Definition at line 671 of file sbc_uja1169_driver.h.
enum sbc_frame_ctr_pndm_t |
Frame control register, partial networking data mask (0x2F).
Implements : sbc_frame_ctr_pndm_t_Class
Enumerator | |
---|---|
SBC_UJA_FRAME_CTR_PNDM_DCARE |
Data length code and data field are do not care for wake-up. |
SBC_UJA_FRAME_CTR_PNDM_EVAL |
Data length code and data field are evaluated at wake-up. |
Definition at line 683 of file sbc_uja1169_driver.h.
Global event status register, supply event (0x60).
Implements : sbc_gl_evnt_stat_supe_t_Class
Enumerator | |
---|---|
SBC_UJA_GL_EVNT_STAT_SUPE_NO |
No pending supply event. |
SBC_UJA_GL_EVNT_STAT_SUPE |
Supply event pending at address 0x62 . |
Definition at line 774 of file sbc_uja1169_driver.h.
Global event status register, system event (0x60).
Implements : sbc_gl_evnt_stat_syse_t_Class
Enumerator | |
---|---|
SBC_UJA_GL_EVNT_STAT_SYSE_NO |
No pending system event. |
SBC_UJA_GL_EVNT_STAT_SYSE |
System event pending at address 0x61. |
Definition at line 786 of file sbc_uja1169_driver.h.
Global event status register, transceiver event (0x60).
Implements : sbc_gl_evnt_stat_trxe_t_Class
Enumerator | |
---|---|
SBC_UJA_GL_EVNT_STAT_TRXE_NO |
No pending transceiver event. |
SBC_UJA_GL_EVNT_STAT_TRXE |
Transceiver event pending at address 0x63. |
Definition at line 762 of file sbc_uja1169_driver.h.
Global event status register, WAKE pin event (0x60).
Implements : sbc_gl_evnt_stat_wpe_t_Class
Enumerator | |
---|---|
SBC_UJA_GL_EVNT_STAT_WPE_NO |
No pending WAKE pin event. |
SBC_UJA_GL_EVNT_STAT_WPE |
WAKE pin event pending at address 0x64. |
Definition at line 750 of file sbc_uja1169_driver.h.
enum sbc_lock_t |
Lock control(0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc.
Implements : sbc_lock_t_Class
Definition at line 320 of file sbc_uja1169_driver.h.
enum sbc_main_nms_t |
Main status register, normal mode status (0x03).
Implements : sbc_main_nms_t_Class
Enumerator | |
---|---|
SBC_UJA_MAIN_NMS_NORMAL |
UJA1169 has entered Normal mode (after power-up) |
SBC_UJA_MAIN_NMS_PWR_UP |
UJA1169 has powered up but has not yet switched to Normal mode. |
Definition at line 217 of file sbc_uja1169_driver.h.
enum sbc_main_otws_t |
Main status register, Overtemperature warning status (0x03).
Implements : sbc_main_otws_t_Class
Enumerator | |
---|---|
SBC_UJA_MAIN_OTWS_BELOW |
IC temperature below overtemperature warning threshold. |
SBC_UJA_MAIN_OTWS_ABOVE |
IC temperature above overtemperature warning threshold. |
Definition at line 205 of file sbc_uja1169_driver.h.
enum sbc_main_rss_t |
Main status register, Reset source status (0x03).
Implements : sbc_main_rss_t_Class
Definition at line 229 of file sbc_uja1169_driver.h.
enum sbc_mode_mc_t |
Mode control register, mode control (0x01)
Implements : sbc_mode_mc_t_Class
Enumerator | |
---|---|
SBC_UJA_MODE_MC_SLEEP |
Sleep mode. |
SBC_UJA_MODE_MC_STANDBY |
Standby mode. |
SBC_UJA_MODE_MC_NORMAL |
Normal mode. |
Definition at line 168 of file sbc_uja1169_driver.h.
MTPNV status register, error correction code status (0x70).
Implements : sbc_mtpnv_stat_eccs_t_Class
Enumerator | |
---|---|
SBC_UJA_MTPNV_STAT_ECCS_NO |
No bit failure detected in non-volatile memory. |
SBC_UJA_MTPNV_STAT_ECCS |
Bit failure detected and corrected in non-volatile memory. |
Definition at line 975 of file sbc_uja1169_driver.h.
MTPNV status register, non-volatile memory programming status (0x70).
Implements : sbc_mtpnv_stat_nvmps_t_Class
Enumerator | |
---|---|
SBC_UJA_MTPNV_STAT_NVMPS_NO |
MTPNV memory cannot be overwritten. |
SBC_UJA_MTPNV_STAT_NVMPS |
MTPNV memory is ready to be reprogrammed. |
Definition at line 987 of file sbc_uja1169_driver.h.
enum sbc_register_t |
Register map.
Implements : sbc_register_t_Class
Definition at line 54 of file sbc_uja1169_driver.h.
enum sbc_regulator_pdc_t |
Regulator control register, power distribution control (0x10).
Implements : sbc_regulator_pdc_t_Class
Definition at line 345 of file sbc_uja1169_driver.h.
Regulator control register, set V1 reset threshold (0x10).
Implements : sbc_regulator_v1rtc_t_Class
Definition at line 379 of file sbc_uja1169_driver.h.
enum sbc_regulator_v2c_t |
Regulator control register, V2/VEXT configuration (0x10).
Implements : sbc_regulator_v2c_t_Class
Definition at line 363 of file sbc_uja1169_driver.h.
enum sbc_sbc_fnmc_t |
SBC configuration control register, Forced Normal mode control (0x74).
Implements : sbc_sbc_fnmc_t_Class
Enumerator | |
---|---|
SBC_UJA_SBC_FNMC_DIS |
Forced Normal mode disabled. |
SBC_UJA_SBC_FNMC_EN |
Forced Normal mode enabled. |
Definition at line 1044 of file sbc_uja1169_driver.h.
enum sbc_sbc_sdmc_t |
SBC configuration control register, Software Development mode control (0x74).
Implements : sbc_sbc_sdmc_t_Class
Enumerator | |
---|---|
SBC_UJA_SBC_SDMC_DIS |
Software Development mode disabled. |
SBC_UJA_SBC_SDMC_EN |
Software Development mode enabled. |
Definition at line 1057 of file sbc_uja1169_driver.h.
enum sbc_sbc_slpc_t |
SBC configuration control register, Sleep control (0x74).
Implements : sbc_sbc_slpc_t_Class
Enumerator | |
---|---|
SBC_UJA_SBC_SLPC_AC |
Sleep mode commands accepted. Factory preset value. |
SBC_UJA_SBC_SLPC_IG |
Sleep mode commands ignored. |
Definition at line 1070 of file sbc_uja1169_driver.h.
enum sbc_sbc_v1rtsuc_t |
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x74).
Implements : sbc_sbc_v1rtsuc_t_Class
Definition at line 1028 of file sbc_uja1169_driver.h.
enum sbc_start_up_rlc_t |
Start-up control register, RSTN output reset pulse width macros (0x73).
Implements : sbc_start_up_rlc_t_Class
Definition at line 999 of file sbc_uja1169_driver.h.
enum sbc_start_up_v2suc_t |
Start-up control register, V2/VEXT start-up control (0x73).
Implements : sbc_start_up_v2suc_t_Class
Enumerator | |
---|---|
SBC_UJA_START_UP_V2SUC_00 |
bits V2C/VEXTC set to 00 at power-up. |
SBC_UJA_START_UP_V2SUC_11 |
bits V2C/VEXTC set to 11 at power-up. |
Definition at line 1015 of file sbc_uja1169_driver.h.
Supply event status register, V1 undervoltage (0x62).
Implements : sbc_sup_evnt_stat_v1u_t_Class
Definition at line 877 of file sbc_uja1169_driver.h.
Supply event status register, V2/VEXT overvoltage (0x62).
Implements : sbc_sup_evnt_stat_v2o_t_Class
Enumerator | |
---|---|
SBC_UJA_SUP_EVNT_STAT_V2O_NO |
No V2/VEXT overvoltage event captured. |
SBC_UJA_SUP_EVNT_STAT_V2O |
V2/VEXT overvoltage event captured. |
Definition at line 853 of file sbc_uja1169_driver.h.
Supply event status register, V2/VEXT undervoltage (0x62).
Implements : sbc_sup_evnt_stat_v2u_t_Class
Enumerator | |
---|---|
SBC_UJA_SUP_EVNT_STAT_V2U_NO |
No V2/VEXT undervoltage event captured. |
SBC_UJA_SUP_EVNT_STAT_V2U |
V2/VEXT undervoltage event captured. |
Definition at line 865 of file sbc_uja1169_driver.h.
Supply event capture enable register, V1 undervoltage enable (0x1C).
Implements : sbc_supply_evnt_v1ue_t_Class
Enumerator | |
---|---|
SBC_UJA_SUPPLY_EVNT_V1UE_DIS |
V1 undervoltage detection disabled. |
SBC_UJA_SUPPLY_EVNT_V1UE_EN |
V1 undervoltage detection enabled. |
Definition at line 449 of file sbc_uja1169_driver.h.
Supply event capture enable register, V2/VEXT overvoltage enable (0x1C).
Implements : sbc_supply_evnt_v2oe_t_Class
Enumerator | |
---|---|
SBC_UJA_SUPPLY_EVNT_V2OE_DIS |
V2/VEXT overvoltage detection disabled. |
SBC_UJA_SUPPLY_EVNT_V2OE_EN |
V2/VEXT overvoltage detection enabled. |
Definition at line 424 of file sbc_uja1169_driver.h.
Supply event capture enable register, V2/VEXT undervoltage enable (0x1C).
Implements : sbc_supply_evnt_v2ue_t_Class
Enumerator | |
---|---|
SBC_UJA_SUPPLY_EVNT_V2UE_DIS |
V2/VEXT undervoltage detection disabled. |
SBC_UJA_SUPPLY_EVNT_V2UE_EN |
V2/VEXT undervoltage detection enabled. |
Definition at line 437 of file sbc_uja1169_driver.h.
Supply voltage status register, V1 status (0x1B).
Implements : sbc_supply_stat_v1s_t_Class
Enumerator | |
---|---|
SBC_UJA_SUPPLY_STAT_V1S_VAB |
V1 output voltage above 90 % undervoltage threshold. |
SBC_UJA_SUPPLY_STAT_V1S_VBE |
V1 output voltage below 90 % undervoltage threshold. |
Definition at line 411 of file sbc_uja1169_driver.h.
Supply voltage status register, V2/VEXT status (0x1B).
Implements : sbc_supply_stat_v2s_t_Class
Definition at line 395 of file sbc_uja1169_driver.h.
enum sbc_sys_evnt_otwe_t |
System event capture enable, overtemperature warning enable (0x04).
Implements : sbc_sys_evnt_otwe_t_Class
Enumerator | |
---|---|
SBC_UJA_SYS_EVNT_OTWE_DIS |
Overtemperature warning disabled. |
SBC_UJA_SYS_EVNT_OTWE_EN |
Overtemperature warning enabled. |
Definition at line 254 of file sbc_uja1169_driver.h.
enum sbc_sys_evnt_spife_t |
System event capture enable, SPI failure enable (0x04).
Implements : sbc_sys_evnt_spife_t_Class
Enumerator | |
---|---|
SBC_UJA_SYS_EVNT_SPIFE_DIS |
SPI failure detection disabled. |
SBC_UJA_SYS_EVNT_SPIFE_EN |
SPI failure detection enabled. |
Definition at line 266 of file sbc_uja1169_driver.h.
System event status register, overtemperature warning (0x61).
Implements : sbc_sys_evnt_stat_otw_t_Class
Definition at line 810 of file sbc_uja1169_driver.h.
System event status register, power-on (0x61).
Implements : sbc_sys_evnt_stat_po_t_Class
Enumerator | |
---|---|
SBC_UJA_SYS_EVNT_STAT_PO_NO |
No recent battery power-on. |
SBC_UJA_SYS_EVNT_STAT_PO |
The UJA1169 has left Off mode after battery power-on. |
Definition at line 798 of file sbc_uja1169_driver.h.
System event status register, SPI failure (0x61).
Implements : sbc_sys_evnt_stat_spif_t_Class
Definition at line 823 of file sbc_uja1169_driver.h.
System event status register, watchdog failure (0x61).
Implements : sbc_sys_evnt_stat_wdf_t_Class
Definition at line 837 of file sbc_uja1169_driver.h.
Transceiver event capture enable register, CAN-bus silence enable (0x23).
Implements : sbc_trans_evnt_cbse_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_CBSE_DIS |
CAN-bus silence detection disabled. |
SBC_UJA_TRANS_EVNT_CBSE_EN |
CAN-bus silence detection enabled. |
Definition at line 598 of file sbc_uja1169_driver.h.
enum sbc_trans_evnt_cfe_t |
Transceiver event capture enable register, CAN failure enable (0x23).
Implements : sbc_trans_evnt_cfe_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_CFE_DIS |
CAN failure detection disabled. |
SBC_UJA_TRANS_EVNT_CFE_EN |
CAN failure detection enabled. |
Definition at line 610 of file sbc_uja1169_driver.h.
enum sbc_trans_evnt_cwe_t |
Transceiver event capture enable register, CAN wake-up enable (0x23).
Implements : sbc_trans_evnt_cwe_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_CWE_DIS |
CAN wake-up detection disabled. |
SBC_UJA_TRANS_EVNT_CWE_EN |
CAN wake-up detection enabled. |
Definition at line 622 of file sbc_uja1169_driver.h.
Transceiver event status register, CAN-bus status (0x63).
Implements : sbc_trans_evnt_stat_cbs_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_STAT_CBS_NO |
CAN-bus active. |
SBC_UJA_TRANS_EVNT_STAT_CBS |
No activity on CAN-bus for tto(silence) (detected only when CBSE = 1 while bus active). |
Definition at line 904 of file sbc_uja1169_driver.h.
Transceiver event status register, CAN failure (0x63).
Implements : sbc_trans_evnt_stat_cf_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_STAT_CF_NO |
No CAN failure detected. |
SBC_UJA_TRANS_EVNT_STAT_CF |
CAN transceiver deactivated due to VCAN undervoltage OR dominant clamped TXD (not in Sleep mode) |
Definition at line 917 of file sbc_uja1169_driver.h.
Transceiver event status register, CAN wake-up (0x63).
Implements : sbc_trans_evnt_stat_cw_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_STAT_CW_NO |
No CAN wake-up event detected. |
SBC_UJA_TRANS_EVNT_STAT_CW |
CAN wake-up event detected while the transceiver is in CAN Offline Mode. |
Definition at line 930 of file sbc_uja1169_driver.h.
Transceiver event status register,partial networking frame detection error (0x63).
Implements : sbc_trans_evnt_stat_pnfde_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_EVNT_STAT_PNFDE_NO |
No partial networking frame detection error detected. |
SBC_UJA_TRANS_EVNT_STAT_PNFDE |
Partial networking frame detection error detected. |
Definition at line 892 of file sbc_uja1169_driver.h.
Transceiver status register, CAN-bus silence status (0x22).
Implements : sbc_trans_stat_cbss_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_STAT_CBSS_ACT |
CAN-bus active (communication detected on bus) |
SBC_UJA_TRANS_STAT_CBSS_INACT |
CAN-bus inactive (for longer than t_to(silence)). |
Definition at line 562 of file sbc_uja1169_driver.h.
enum sbc_trans_stat_cfs_t |
Transceiver status register, CAN failure status (0x22).
Implements : sbc_trans_stat_cfs_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_STAT_CFS_NO_TXD |
No TXD dominant time-out event detected. |
SBC_UJA_TRANS_STAT_CFS_TXD |
CAN transmitter disabled due to a TXD dominant time-out event. |
Definition at line 586 of file sbc_uja1169_driver.h.
Transceiver status register, CAN oscillator status (0x22).
Implements : sbc_trans_stat_coscs_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_STAT_COSCS_NRUN |
CAN partial networking oscillator not running at target frequency. |
SBC_UJA_TRANS_STAT_COSCS_RUN |
CAN partial networking oscillator running at target. |
Definition at line 550 of file sbc_uja1169_driver.h.
Transceiver status register, CAN partial networking error (0x22).
Implements : sbc_trans_stat_cpnerr_t_Class
Definition at line 525 of file sbc_uja1169_driver.h.
Transceiver status register, CAN partial networking status (0x22).
Implements : sbc_trans_stat_cpns_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_STAT_CPNS_ERR |
CAN partial networking configuration error detected(PNCOK = 0). |
SBC_UJA_TRANS_STAT_CPNS_OK |
CAN partial networking configuration ok (PNCOK = 1). |
Definition at line 538 of file sbc_uja1169_driver.h.
enum sbc_trans_stat_cts_t |
Transceiver status register, CAN transceiver status (0x22).
Implements : sbc_trans_stat_cts_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_STAT_CTS_INACT |
CAN transceiver not in Active mode. |
SBC_UJA_TRANS_STAT_CTS_ACT |
CAN transceiver in Active mode. |
Definition at line 513 of file sbc_uja1169_driver.h.
enum sbc_trans_stat_vcs_t |
Transceiver status register, VCAN status (0x22).
Implements : sbc_trans_stat_vcs_t_Class
Enumerator | |
---|---|
SBC_UJA_TRANS_STAT_VCS_AB |
CAN supply voltage is above the 90 % threshold. |
SBC_UJA_TRANS_STAT_VCS_BE |
CAN supply voltage is below the 90 % threshold |
Definition at line 574 of file sbc_uja1169_driver.h.
enum sbc_wake_en_wpfe_t |
WAKE pin event capture enable register, WAKE pin falling-edge enable (0x4C).
Implements : sbc_wake_en_wpfe_t_Class
Enumerator | |
---|---|
SBC_UJA_WAKE_EN_WPFE_DIS |
Falling-edge detection on WAKE pin disabled. |
SBC_UJA_WAKE_EN_WPFE_EN |
Falling-edge detection on WAKE pin enabled. |
Definition at line 738 of file sbc_uja1169_driver.h.
enum sbc_wake_en_wpre_t |
WAKE pin event capture enable register, WAKE pin rising-edge enable (0x4C).
Implements : sbc_wake_en_wpre_t_Class
Enumerator | |
---|---|
SBC_UJA_WAKE_EN_WPRE_DIS |
Rising-edge detection on WAKE pin disabled. |
SBC_UJA_WAKE_EN_WPRE_EN |
Rising-edge detection on WAKE pin enabled. |
Definition at line 726 of file sbc_uja1169_driver.h.
WAKE pin event status register, WAKE pin falling edge (0x64).
Implements : sbc_wake_evnt_stat_wpf_t_Class
Enumerator | |
---|---|
SBC_UJA_WAKE_EVNT_STAT_WPF_NO |
No falling edge detected on WAKE pin. |
SBC_UJA_WAKE_EVNT_STAT_WPF |
Falling edge detected on WAKE pin. |
Definition at line 954 of file sbc_uja1169_driver.h.
WAKE pin event status register, WAKE pin rising edge (0x64).
Implements : sbc_wake_evnt_stat_wpr_t_Class
Enumerator | |
---|---|
SBC_UJA_WAKE_EVNT_STAT_WPR_NO |
No rising edge detected on WAKE pin. |
SBC_UJA_WAKE_EVNT_STAT_WPR |
Rising edge detected on WAKE pin. |
Definition at line 942 of file sbc_uja1169_driver.h.
enum sbc_wake_stat_wpvs_t |
WAKE pin status register, WAKE pin status (0x4B).
Implements : sbc_wake_stat_wpvs_t_Class
Enumerator | |
---|---|
SBC_UJA_WAKE_STAT_WPVS_BE |
Voltage on WAKE pin below switching threshold (Vth(sw)). |
SBC_UJA_WAKE_STAT_WPVS_AB |
voltage on WAKE pin above switching threshold (Vth(sw)). |
Definition at line 714 of file sbc_uja1169_driver.h.
enum sbc_wtdog_ctr_nwp_t |
Watchdog control register, nominal watchdog period (0x00). Eight watchdog periods are supported, from 8 ms to 4096 ms. The watchdog period is programmed via bits NWP. The selected period is valid for both Window and Timeout modes. The default watchdog period is 128 ms. A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid write access to the Watchdog control register. If the watchdog mode or the watchdog period have changed as a result of the write access, the new values are immediately valid.
Implements : sbc_wtdog_ctr_nwp_t_Class
Definition at line 152 of file sbc_uja1169_driver.h.
enum sbc_wtdog_ctr_wmc_t |
Watchdog control register, watchdog mode control (0x00). The UJA1169 contains a watchdog that supports three operating modes: Window, Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a watchdog trigger event within a defined watchdog window triggers and resets the watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered and reset at any time within the watchdog period by a watchdog trigger. Watchdog time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous mode, the watchdog can be off or autonomously in Timeout mode, depending on the selected SBC mode. The watchdog mode is selected via bits WMC in the Watchdog control register. The SBC must be in Standby mode when the watchdog mode is changed.
Implements : sbc_wtdog_ctr_wmc_t_Class
Enumerator | |
---|---|
SBC_UJA_WTDOG_CTR_WMC_AUTO |
Autonomous mode. |
SBC_UJA_WTDOG_CTR_WMC_TIME |
Timeout mode. |
SBC_UJA_WTDOG_CTR_WMC_WIND |
Window mode (available only in SBC Normal mode). |
Definition at line 131 of file sbc_uja1169_driver.h.
Watchdog status register, forced Normal mode status (0x05).
Implements : sbc_wtdog_stat_fnms_t_Class
Enumerator | |
---|---|
SBC_UJA_WTDOG_STAT_FNMS_N_NORMAL |
SBC is not in Forced Normal mode. |
SBC_UJA_WTDOG_STAT_FNMS_NORMAL |
SBC is in Forced Normal mode. |
Definition at line 278 of file sbc_uja1169_driver.h.
Watchdog status register, Software Development mode status (0x05).
Implements : sbc_wtdog_stat_sdms_t_Class
Enumerator | |
---|---|
SBC_UJA_WTDOG_STAT_SDMS_N_NORMAL |
SBC is not in Software Development mode. |
SBC_UJA_WTDOG_STAT_SDMS_NORMAL |
SBC is in Software Development mode. |
Definition at line 290 of file sbc_uja1169_driver.h.
enum sbc_wtdog_stat_wds_t |
Watchdog status register, watchdog status (0x05).
Implements : sbc_wtdog_stat_wds_t_Class
Definition at line 302 of file sbc_uja1169_driver.h.