S32 SDK
QuadSPI Peripheral Access Layer

Detailed Description

Modules

 QuadSPI Register Masks
 

Data Structures

struct  QuadSPI_Type
 

Macros

#define QuadSPI_RBDR_COUNT   32u
 
#define QuadSPI_LUT_COUNT   64u
 
#define QuadSPI_INSTANCE_COUNT   (1u)
 
#define QuadSPI_BASE   (0x40076000u)
 
#define QuadSPI   ((QuadSPI_Type *)QuadSPI_BASE)
 
#define QuadSPI_BASE_ADDRS   { QuadSPI_BASE }
 
#define QuadSPI_BASE_PTRS   { QuadSPI }
 
#define QuadSPI_IRQS_ARR_COUNT   (1u)
 
#define QuadSPI_IRQS_CH_COUNT   (1u)
 
#define QuadSPI_IRQS   { QSPI_IRQn }
 

Typedefs

typedef struct QuadSPI_TypeQuadSPI_MemMapPtr
 

Macro Definition Documentation

#define QuadSPI   ((QuadSPI_Type *)QuadSPI_BASE)

Peripheral QuadSPI base pointer

Definition at line 9807 of file S32K148.h.

#define QuadSPI_BASE   (0x40076000u)

Peripheral QuadSPI base address

Definition at line 9805 of file S32K148.h.

#define QuadSPI_BASE_ADDRS   { QuadSPI_BASE }

Array initializer of QuadSPI peripheral base addresses

Definition at line 9809 of file S32K148.h.

#define QuadSPI_BASE_PTRS   { QuadSPI }

Array initializer of QuadSPI peripheral base pointers

Definition at line 9811 of file S32K148.h.

#define QuadSPI_INSTANCE_COUNT   (1u)

Number of instances of the QuadSPI module.

Definition at line 9800 of file S32K148.h.

#define QuadSPI_IRQS   { QSPI_IRQn }

Interrupt vectors for the QuadSPI peripheral type

Definition at line 9817 of file S32K148.h.

#define QuadSPI_IRQS_ARR_COUNT   (1u)

Number of interrupt vector arrays for the QuadSPI module.

Definition at line 9813 of file S32K148.h.

#define QuadSPI_IRQS_CH_COUNT   (1u)

Number of interrupt channels for the QuadSPI module.

Definition at line 9815 of file S32K148.h.

#define QuadSPI_LUT_COUNT   64u

Definition at line 9752 of file S32K148.h.

#define QuadSPI_RBDR_COUNT   32u

QuadSPI - Size of Registers Arrays

Definition at line 9751 of file S32K148.h.

Typedef Documentation

typedef struct QuadSPI_Type * QuadSPI_MemMapPtr