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S32 SDK
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Modules | |
S32_NVIC Register Masks | |
Data Structures | |
struct | S32_NVIC_Type |
Macros | |
#define | S32_NVIC_ISER_COUNT 4u |
#define | S32_NVIC_ICER_COUNT 4u |
#define | S32_NVIC_ISPR_COUNT 4u |
#define | S32_NVIC_ICPR_COUNT 4u |
#define | S32_NVIC_IABR_COUNT 4u |
#define | S32_NVIC_IP_COUNT 123u |
#define | S32_NVIC_INSTANCE_COUNT (1u) |
#define | S32_NVIC_BASE (0xE000E100u) |
#define | S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE) |
#define | S32_NVIC_BASE_ADDRS { S32_NVIC_BASE } |
#define | S32_NVIC_BASE_PTRS { S32_NVIC } |
#define | S32_NVIC_IRQS_ARR_COUNT (1u) |
#define | S32_NVIC_IRQS_CH_COUNT (1u) |
#define | S32_NVIC_IRQS { SWI_IRQn } |
Typedefs | |
typedef struct S32_NVIC_Type * | S32_NVIC_MemMapPtr |
#define S32_NVIC ((S32_NVIC_Type *)S32_NVIC_BASE) |
#define S32_NVIC_BASE (0xE000E100u) |
#define S32_NVIC_BASE_ADDRS { S32_NVIC_BASE } |
#define S32_NVIC_BASE_PTRS { S32_NVIC } |
#define S32_NVIC_INSTANCE_COUNT (1u) |
#define S32_NVIC_IRQS { SWI_IRQn } |
#define S32_NVIC_IRQS_ARR_COUNT (1u) |
#define S32_NVIC_IRQS_CH_COUNT (1u) |
#define S32_NVIC_ISER_COUNT 4u |
typedef struct S32_NVIC_Type * S32_NVIC_MemMapPtr |