19 #include "quadspi_hw_access.h"
31 #define QSPI_TX_MIN_BUF_FILL 4U
33 #define QSPI_TIMEOUT_WRAP 0xFFFFFFFFU
36 #define QSPI_OP_READ 0U
37 #define QSPI_OP_READ_INT 1U
38 #define QSPI_OP_WRITE 2U
41 #define QSPI_ERR_FLAGS_MASK (QuadSPI_FR_TBUF_MASK | \
42 QuadSPI_FR_ILLINE_MASK | \
43 QuadSPI_FR_RBOF_MASK | \
44 QuadSPI_FR_IPAEF_MASK | \
45 QuadSPI_FR_IPIEF_MASK | \
46 QuadSPI_FR_IPGEF_MASK)
75 static bool QSPI_DRV_Timeout(uint32_t startTime, uint32_t timeout)
81 if (currentTime >= startTime)
83 retVal = ((currentTime - startTime) > timeout)?
true:
false;
88 retVal = ((QSPI_TIMEOUT_WRAP - startTime + currentTime) > timeout)?
true:
false;
107 *((uint32_t *)(state->data)) = value;
110 else if (state->roData)
113 if (*((uint32_t *)(state->roData)) != value)
122 if (value != 0xFFFFFFFFU)
144 dataSize = state->size;
148 for (cnt = 0U; cnt < dataSize; cnt++)
150 *state->data = (uint8_t)(value & 0xFFU);
155 else if (state->roData)
158 for (cnt = 0U; cnt < dataSize; cnt++)
160 if (*(state->roData) != (value & 0xFFU))
171 if (~value & ((1U << (dataSize * 8U)) - 1U))
192 while ((QSPI_DRV_GetTxWatermarkAvailable(baseAddr)) && (state->size > 0U))
194 if (state->size < 4U)
198 for (cnt = 0U; cnt < state->size; cnt++)
200 data += (*(state->roData) << (8U * cnt));
207 data = *(uint32_t *)(state->roData);
212 QSPI_DRV_WriteTxData(baseAddr, data);
227 if (baseAddr->
FR & QSPI_ERR_FLAGS_MASK)
230 baseAddr->
FR = QSPI_ERR_FLAGS_MASK;
245 static inline void QSPI_DRV_PadTxBuf(
QuadSPI_Type *baseAddr)
249 bufFill = QSPI_DRV_GetTxBufFill(baseAddr);
250 while (bufFill < QSPI_TX_MIN_BUF_FILL)
252 QSPI_DRV_WriteTxData(baseAddr, 0xFFFFFFFFUL);
267 QSPI_DRV_Enable(baseAddr);
269 QSPI_DRV_SwResetOn(baseAddr);
271 QSPI_DRV_Disable(baseAddr);
273 QSPI_DRV_SwResetOff(baseAddr);
287 uint8_t option = QSPI_MCR_SCLKCFG_INPUT_EN;
292 option |= QSPI_MCR_SCLKCFG_CLK_SRC;
297 option |= QSPI_MCR_SCLKCFG_EXT_DQS;
299 QSPI_DRV_SetChipOptions(baseAddr, option);
309 static void QSPI_DRV_IRQHandler(uint32_t instance)
317 baseAddr = g_qspiBase[instance];
318 state = g_qspiStatePtr[instance];
320 if (state->operation == QSPI_OP_READ_INT)
323 size = state->size >> 2;
324 for (cnt = 0; cnt < size; cnt++)
326 status = QSPI_DRV_ProcessData(baseAddr->
RBDR[cnt], state);
335 status = QSPI_DRV_ProcessLastData(baseAddr->
RBDR[size], state);
339 state->status = status;
347 if ((state->callback != NULL) && (state->operation == QSPI_OP_WRITE))
349 state->callback(instance, state->callbackParam);
354 #if (QuadSPI_INSTANCE_COUNT > 0U)
361 void QSPI_IRQHandler(
void)
363 QSPI_DRV_IRQHandler(0);
380 baseAddr = g_qspiBase[state->instance];
388 QSPI_DRV_DisableDmaReq(baseAddr);
391 if ((state->callback != NULL) && (state->operation != QSPI_OP_WRITE))
393 state->callback(state->instance, state->callbackParam);
404 static void QSPI_DRV_ConfigDmaRx(uint32_t instance,
qspi_state_t * state)
408 baseAddr = g_qspiBase[instance];
415 QSPI_DRV_GetRxDataAddr(baseAddr),
416 (uint32_t)(state->data),
418 4, state->size >> 2,
true);
429 QSPI_DRV_EnableRxDmaReq(baseAddr);
439 static void QSPI_DRV_ConfigDmaTx(uint32_t instance,
qspi_state_t * state)
443 baseAddr = g_qspiBase[instance];
450 (uint32_t)(state->roData),
451 QSPI_DRV_GetTxDataAddr(baseAddr),
453 4, state->size >> 2,
true);
464 QSPI_DRV_EnableTxDmaReq(baseAddr);
491 baseAddr = g_qspiBase[instance];
492 g_qspiStatePtr[instance] = state;
495 state->dmaSupport = userConfigPtr->
dmaSupport;
496 state->dmaChannel = userConfigPtr->
dmaChannel;
497 state->callback = userConfigPtr->
callback;
499 state->instance = instance;
503 QSPI_DRV_SwReset(baseAddr);
506 QSPI_DRV_SetMemMap(baseAddr, userConfigPtr->
side, userConfigPtr->
memSize);
509 QSPI_DRV_SetCsHoldTime(baseAddr, userConfigPtr->
csHoldTime);
510 QSPI_DRV_SetCsSetupTime(baseAddr, userConfigPtr->
csSetupTime);
514 QSPI_DRV_SetEndianess(baseAddr, userConfigPtr->
endianess);
515 QSPI_DRV_SetRxBufReadout(baseAddr, QSPI_RX_READOUT_IP);
517 QSPI_DRV_SetTxWatermark(baseAddr, 2U);
518 QSPI_DRV_SetRxWatermark(baseAddr, 1U);
529 QSPI_DDR_Disable(baseAddr);
532 QSPI_DQS_Disable(baseAddr);
536 QSPI_DQS_Enable(baseAddr);
543 QSPI_DDR_Enable(baseAddr);
544 QSPI_DQS_Enable(baseAddr);
548 QSPI_DRV_ConfigureChipOptions(baseAddr, userConfigPtr);
554 QSPI_DRV_Enable(baseAddr);
572 baseAddr = g_qspiBase[instance];
575 QSPI_DRV_Disable(baseAddr);
580 g_qspiStatePtr[instance] = NULL;
598 baseAddr = g_qspiBase[instance];
601 QSPI_DRV_SetAhbBuf1(baseAddr, config->
sizes[1U], config->
masters[1U]);
602 QSPI_DRV_SetAhbBuf2(baseAddr, config->
sizes[2U], config->
masters[2U]);
624 baseAddr = g_qspiBase[instance];
625 state = g_qspiStatePtr[instance];
628 QSPI_DRV_IpTrigger(baseAddr, lut, 1U);
635 while ((status ==
STATUS_BUSY) && !QSPI_DRV_Timeout(startTime, timeout));
655 const uint8_t * dataCmp,
667 baseAddr = g_qspiBase[instance];
668 state = g_qspiStatePtr[instance];
670 state->operation = QSPI_OP_READ;
672 state->data = dataRead;
674 state->roData = dataCmp;
684 QSPI_DRV_ConfigDmaRx(instance, state);
689 state->operation = QSPI_OP_READ_INT;
693 QSPI_DRV_SetIpAddr(baseAddr, addr);
695 QSPI_DRV_IpTrigger(baseAddr, lut, (uint16_t)size);
700 while (QSPI_DRV_GetBusyStatus(baseAddr) || QSPI_DRV_GetRxBufFill(baseAddr))
702 if (QSPI_DRV_GetRxDataEvent(baseAddr))
707 if (state->size >= 4)
709 status = QSPI_DRV_ProcessData(baseAddr->
RBDR[0U], state);
713 status = QSPI_DRV_ProcessLastData(baseAddr->
RBDR[0U], state);
716 QSPI_DRV_RxPop(baseAddr);
718 if (QSPI_DRV_Timeout(startTime, timeout))
725 QSPI_DRV_ClearRxBuf(baseAddr);
727 errors = QSPI_DRV_ErrorCheck(baseAddr);
759 baseAddr = g_qspiBase[instance];
760 state = g_qspiStatePtr[instance];
762 state->operation = QSPI_OP_WRITE;
764 state->roData = data;
768 QSPI_DRV_SetIpAddr(baseAddr, addr);
770 QSPI_DRV_ClearTxBuf(baseAddr);
771 QSPI_DRV_FillTxBuf(baseAddr, state);
773 QSPI_DRV_PadTxBuf(baseAddr);
785 QSPI_DRV_ConfigDmaTx(instance, state);
789 QSPI_DRV_IpTrigger(baseAddr, lut, (uint16_t)size);
794 while (QSPI_DRV_GetBusyStatus(baseAddr))
797 QSPI_DRV_FillTxBuf(baseAddr, state);
798 if (QSPI_DRV_Timeout(startTime, timeout))
805 errors = QSPI_DRV_ErrorCheck(baseAddr);
831 baseAddr = g_qspiBase[instance];
832 state = g_qspiStatePtr[instance];
836 QSPI_DRV_SetIpAddr(baseAddr, addr);
838 QSPI_DRV_IpTrigger(baseAddr, lut, 1U);
857 baseAddr = g_qspiBase[instance];
858 if (QSPI_DRV_GetBusyStatus(baseAddr))
863 return QSPI_DRV_ErrorCheck(baseAddr);
883 userConfigPtr->
memSize = 0x7FFFFFU;
uint8_t masters[QSPI_AHB_BUFFERS]
status_t QSPI_DRV_IpRead(uint32_t instance, uint8_t lut, uint32_t addr, uint8_t *dataRead, const uint8_t *dataCmp, uint32_t size, qspi_transfer_type_t transferType, uint32_t timeout)
Launches an IP read command.
qspi_endianess_t endianess
__I uint32_t RBDR[QuadSPI_RBDR_COUNT]
#define QuadSPI_FR_TFF_MASK
qspi_sample_delay_t sampleDelay
#define FEATURE_QSPI_DMA_RX_REQ
List of DMA Rx requests.
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
status_t QSPI_DRV_IpWrite(uint32_t instance, uint8_t lut, uint32_t addr, uint8_t *data, uint32_t size, qspi_transfer_type_t transferType, uint32_t timeout)
Launches an IP write command.
qspi_transfer_type_t
Driver type Implements : qspi_transfer_type_t_Class.
uint32_t OSIF_GetMilliseconds(void)
Returns the number of miliseconds elapsed since starting the internal timer or starting the scheduler...
uint16_t sizes[QSPI_AHB_BUFFERS]
qspi_clock_src_t clock_src
IRQn_Type
Defines the Interrupt Numbers definitions.
status_t EDMA_DRV_SetChannelRequest(uint8_t channel, uint8_t req)
Configures the DMA request for the eDMA channel.
status_t QSPI_DRV_Deinit(uint32_t instance)
De-initialize the qspi driver.
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
edma_chn_status_t
Channel status for eDMA channel.
qspi_date_rate_t dataRate
status_t QSPI_DRV_IpErase(uint32_t instance, uint8_t lut, uint32_t addr)
Launches an IP erase command.
#define QuadSPI_INSTANCE_COUNT
Driver configuration structure.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t QSPI_DRV_AhbSetup(uint32_t instance, const qspi_ahb_config_t *config)
Sets up AHB accesses to the serial flash.
#define FEATURE_QSPI_DMA_TX_REQ
List of DMA Tx requests.
status_t QSPI_DRV_IpGetStatus(uint32_t instance)
Checks the status of the currently running IP command.
status_t QSPI_DRV_IpCommand(uint32_t instance, uint8_t lut, uint32_t timeout)
Launches a simple IP command.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
qspi_read_mode_t readMode
Driver internal context structure.
qspi_sample_phase_t clockPhase
#define QuadSPI_RSER_TFIE_MASK
AHB configuration structure.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
status_t QSPI_DRV_GetDefaultConfig(qspi_user_config_t *userConfigPtr)
Returns default configuration structure for QuadSPI.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
QuadSPI_Type *const g_qspiBase[]
Table of base addresses for QuadSPI instances.
status_t QSPI_DRV_Init(uint32_t instance, const qspi_user_config_t *userConfigPtr, qspi_state_t *state)
Initializes the qspi driver.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
#define QuadSPI_BASE_PTRS