S32 SDK
S32K144_features.h
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1 /*
2  * Copyright (c) 2015 Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
18 
57 #if !defined(S32K144_FEATURES_H)
58 #define S32K144_FEATURES_H
59 
60 /* ERRATA sections*/
61 
62 /* @brief ARM Errata 838869: Store immediate overlapping exception return operation might vector to
63  * incorrect interrupt. */
64 #define ERRATA_E9005
65 
66 /* @brief ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
67  * short ISRs are used. */
68 #define ERRATA_E6940
69 
70 /* @brief E10655: When using LPSPI in master mode and the SR[MBF] bit is read as a one, then, the
71  * flag is set. If it is read as a zero, it must be read second time and this second read will be
72  * the correct state of the bit.​ */
73 #define ERRATA_E10655
74 
75 /* @brief E10792: LPI2C: Slave Transmit Data Flag may incorrectly read as one when TXCFG is zero.
76  * Interrupts for transfer data should be enabled after the address valid event is detected and
77  * disabled at the end of the transfer. */
78 #define ERRATA_E10792
79 
80 /* @brief Errata workaround: System clock status register may be a erroneous status during the system clock switch.
81  * Read system clock source twice. */
82 #define ERRATA_E10777
83 
84 /* @brief E10856: FTM: Safe state is not removed from channel outputs after fault condition
85  * ends if SWOCTRL is being used to control the pin */
86 #define ERRATA_E10856
87 
88 /* PCC module features */
89 
90 /* @brief Has InUse feature (register bit PCC[INUSE]). */
91 #define FEATURE_PCC_HAS_IN_USE_FEATURE (0)
92 
93 /* PORT module features */
95 #define FEATURE_PINS_DRIVER_USING_PORT (1)
96 /* @brief Has control lock (register bit PCR[LK]). */
97 #define FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
98 /* @brief Has open drain control (register bit PCR[ODE]). */
99 #define FEATURE_PINS_HAS_OPEN_DRAIN (0)
100 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */
101 #define FEATURE_PORT_HAS_DIGITAL_FILTER (1)
102 /* @brief Has DMA request (register bit field PCR[IRQC] values). */
103 #define FEATURE_PORT_HAS_DMA_REQUEST (1)
104 /* @brief Has pull resistor selection available. */
105 #define FEATURE_PINS_HAS_PULL_SELECTION (1)
106 /* @brief Has slew rate control (register bit PCR[SRE]). */
107 #define FEATURE_PINS_HAS_SLEW_RATE (0)
108 /* @brief Has passive filter (register bit field PCR[PFE]). */
109 #define FEATURE_PORT_HAS_PASSIVE_FILTER (1)
110 /* @brief Has drive strength (register bit PCR[DSE]). */
111 #define FEATURE_PINS_HAS_DRIVE_STRENGTH (1)
112 /* @brief Has drive strength control bits*/
113 #define FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL (0)
114 
115 /* SOC module features */
116 
117 /* @brief PORT availability on the SoC. */
118 #define FEATURE_SOC_PORT_COUNT (5)
119 
120 #define FEATURE_SOC_SCG_COUNT (1)
121 /* @brief Slow IRC low range clock frequency. */
122 #define FEATURE_SCG_SIRC_LOW_RANGE_FREQ (2000000U)
123 /* @brief Slow IRC high range clock frequency. */
124 #define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ (8000000U)
125 
126 /* @brief Fast IRC trimmed clock frequency(48MHz). */
127 #define FEATURE_SCG_FIRC_FREQ0 (48000000U)
128 /* @brief Fast IRC trimmed clock frequency(52MHz). */
129 #define FEATURE_SCG_FIRC_FREQ1 (52000000U)
130 /* @brief Fast IRC trimmed clock frequency(56MHz). */
131 #define FEATURE_SCG_FIRC_FREQ2 (56000000U)
132 /* @brief Fast IRC trimmed clock frequency(60MHz). */
133 #define FEATURE_SCG_FIRC_FREQ3 (60000000U)
134 
135 /* FLASH module features */
136 
137 /* @brief Is of type FTFA. */
138 #define FEATURE_FLS_IS_FTFA (0u)
139 /* @brief Is of type FTFC. */
140 #define FEATURE_FLS_IS_FTFC (1u)
141 /* @brief Is of type FTFE. */
142 #define FEATURE_FLS_IS_FTFE (0u)
143 /* @brief Is of type FTFL. */
144 #define FEATURE_FLS_IS_FTFL (0u)
145 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
146 #define FEATURE_FLS_HAS_FLEX_RAM_FLAGS (1u)
147 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
148 #define FEATURE_FLS_HAS_PF_SWAPPING_STATUS_FLAG (0u)
149 /* @brief Has EEPROM region protection (register FEPROT). */
150 #define FEATURE_FLS_HAS_EEROM_REGION_PROTECTION (1u)
151 /* @brief Has data flash region protection (register FDPROT). */
152 #define FEATURE_FLS_HAS_DATA_FLS_REGION_PROTECTION (1u)
153 /* @brief P-Flash block count. */
154 #define FEATURE_FLS_PF_BLOCK_COUNT (1u)
155 /* @brief P-Flash block size. */
156 #define FEATURE_FLS_PF_BLOCK_SIZE (524288u)
157 /* @brief P-Flash sector size. */
158 #define FEATURE_FLS_PF_BLOCK_SECTOR_SIZE (4096u)
159 /* @brief P-Flash write unit size. */
160 #define FEATURE_FLS_PF_BLOCK_WRITE_UNIT_SIZE (8u)
161 /* @brief P-Flash block swap feature. */
162 #define FEATURE_FLS_HAS_PF_BLOCK_SWAP (0u)
163 /* @brief Has FlexNVM memory. */
164 #define FEATURE_FLS_HAS_FLEX_NVM (1u)
165 /* @brief FlexNVM block count. */
166 #define FEATURE_FLS_DF_BLOCK_COUNT (1u)
167 /* @brief FlexNVM block size. */
168 #define FEATURE_FLS_DF_BLOCK_SIZE (65536u)
169 /* @brief FlexNVM sector size. */
170 #define FEATURE_FLS_DF_BLOCK_SECTOR_SIZE (2048u)
171 /* @brief FlexNVM write unit size. */
172 #define FEATURE_FLS_DF_BLOCK_WRITE_UNIT_SIZE (8u)
173 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
174 #define FEATURE_FLS_DF_START_ADDRESS (0x10000000u)
175 /* @brief Has FlexRAM memory. */
176 #define FEATURE_FLS_HAS_FLEX_RAM (1u)
177 /* @brief FlexRAM size. */
178 #define FEATURE_FLS_FLEX_RAM_SIZE (4096u)
179 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
180 #define FEATURE_FLS_FLEX_RAM_START_ADDRESS (0x14000000u)
181 /* @brief Has 0x00 Read 1s Block command. */
182 #define FEATURE_FLS_HAS_READ_1S_BLOCK_CMD (1u)
183 /* @brief Has 0x01 Read 1s Section command. */
184 #define FEATURE_FLS_HAS_READ_1S_SECTION_CMD (1u)
185 /* @brief Has 0x02 Program Check command. */
186 #define FEATURE_FLS_HAS_PROGRAM_CHECK_CMD (1u)
187 /* @brief Has 0x03 Read Resource command. */
188 #define FEATURE_FLS_HAS_READ_RESOURCE_CMD (0u)
189 /* @brief Has 0x06 Program Longword command. */
190 #define FEATURE_FLS_HAS_PROGRAM_LONGWORD_CMD (0u)
191 /* @brief Has 0x07 Program Phrase command. */
192 #define FEATURE_FLS_HAS_PROGRAM_PHRASE_CMD (1u)
193 /* @brief Has 0x08 Erase Flash Block command. */
194 #define FEATURE_FLS_HAS_ERASE_BLOCK_CMD (1u)
195 /* @brief Has 0x09 Erase Flash Sector command. */
196 #define FEATURE_FLS_HAS_ERASE_SECTOR_CMD (1u)
197 /* @brief Has 0x0B Program Section command. */
198 #define FEATURE_FLS_HAS_PROGRAM_SECTION_CMD (1u)
199 /* @brief Has 0x40 Read 1s All Blocks command. */
200 #define FEATURE_FLS_HAS_READ_1S_ALL_BLOCKS_CMD (1u)
201 /* @brief Has 0x41 Read Once command. */
202 #define FEATURE_FLS_HAS_READ_ONCE_CMD (1u)
203 /* @brief Has 0x43 Program Once command. */
204 #define FEATURE_FLS_HAS_PROGRAM_ONCE_CMD (1u)
205 /* @brief Has 0x44 Erase All Blocks command. */
206 #define FEATURE_FLS_HAS_ERASE_ALL_CMD (1u)
207 /* @brief Has 0x45 Verify Backdoor Access Key command. */
208 #define FEATURE_FLS_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1u)
209 /* @brief Has 0x46 Swap Control command. */
210 #define FEATURE_FLS_HAS_SWAP_CONTROL_CMD (0u)
211 /* @brief Has 0x49 Erase All Blocks unsecure command. */
212 #define FEATURE_FLS_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1u)
213 /* @brief Has 0x80 Program Partition command. */
214 #define FEATURE_FLS_HAS_PROGRAM_PARTITION_CMD (1u)
215 /* @brief Has 0x81 Set FlexRAM Function command. */
216 #define FEATURE_FLS_HAS_SET_FLEXRAM_FUNCTION_CMD (1u)
217 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
218 #define FEATURE_FLS_PF_BLOCK_CMD_ADDRESS_ALIGMENT (16u)
219 /* @brief P-Flash Erase sector command address alignment. */
220 #define FEATURE_FLS_PF_SECTOR_CMD_ADDRESS_ALIGMENT (16u)
221 /* @brief P-Flash Program/Verify section command address alignment. */
222 #define FEATURE_FLS_PF_SECTION_CMD_ADDRESS_ALIGMENT (16u)
223 /* @brief P-Flash Read resource command address alignment. */
224 #define FEATURE_FLS_PF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
225 /* @brief P-Flash Program check command address alignment. */
226 #define FEATURE_FLS_PF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
227 /* @brief P-Flash Program check command address alignment. */
228 #define FEATURE_FLS_PF_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0u)
229 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
230 #define FEATURE_FLS_DF_BLOCK_CMD_ADDRESS_ALIGMENT (8u)
231 /* @brief FlexNVM Erase sector command address alignment. */
232 #define FEATURE_FLS_DF_SECTOR_CMD_ADDRESS_ALIGMENT (8u)
233 /* @brief FlexNVM Program/Verify section command address alignment. */
234 #define FEATURE_FLS_DF_SECTION_CMD_ADDRESS_ALIGMENT (8u)
235 /* @brief FlexNVM Read resource command address alignment. */
236 #define FEATURE_FLS_DF_RESOURCE_CMD_ADDRESS_ALIGMENT (8u)
237 /* @brief FlexNVM Program check command address alignment. */
238 #define FEATURE_FLS_DF_CHECK_CMD_ADDRESS_ALIGMENT (4u)
239 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
240 #define FEATURE_FLS_DF_SIZE_0000 (0x00010000u)
241 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
242 #define FEATURE_FLS_DF_SIZE_0001 (0xFFFFFFFFu)
243 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
244 #define FEATURE_FLS_DF_SIZE_0010 (0xFFFFFFFFu)
245 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
246 #define FEATURE_FLS_DF_SIZE_0011 (0x00008000u)
247 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
248 #define FEATURE_FLS_DF_SIZE_0100 (0x00000000u)
249 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
250 #define FEATURE_FLS_DF_SIZE_0101 (0xFFFFFFFFu)
251 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
252 #define FEATURE_FLS_DF_SIZE_0110 (0xFFFFFFFFu)
253 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
254 #define FEATURE_FLS_DF_SIZE_0111 (0xFFFFFFFFu)
255 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
256 #define FEATURE_FLS_DF_SIZE_1000 (0x00000000u)
257 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
258 #define FEATURE_FLS_DF_SIZE_1001 (0xFFFFFFFFu)
259 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
260 #define FEATURE_FLS_DF_SIZE_1010 (0x00004000u)
261 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
262 #define FEATURE_FLS_DF_SIZE_1011 (0x00008000u)
263 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
264 #define FEATURE_FLS_DF_SIZE_1100 (0x00010000u)
265 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
266 #define FEATURE_FLS_DF_SIZE_1101 (0xFFFFFFFFu)
267 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
268 #define FEATURE_FLS_DF_SIZE_1110 (0xFFFFFFFFu)
269 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
270 #define FEATURE_FLS_DF_SIZE_1111 (0x00010000u)
271 /* @brief Emulated EEPROM size code 0000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
272 #define FEATURE_FLS_EE_SIZE_0000 (0xFFFFu)
273 /* @brief Emulated EEPROM size code 0001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
274 #define FEATURE_FLS_EE_SIZE_0001 (0xFFFFu)
275 /* @brief Emulated EEPROM size code 0010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
276 #define FEATURE_FLS_EE_SIZE_0010 (0x1000u)
277 /* @brief Emulated EEPROM size code 0011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
278 #define FEATURE_FLS_EE_SIZE_0011 (0x0800u)
279 /* @brief Emulated EEPROM size code 0100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
280 #define FEATURE_FLS_EE_SIZE_0100 (0x0400u)
281 /* @brief Emulated EEPROM size code 0101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
282 #define FEATURE_FLS_EE_SIZE_0101 (0x0200u)
283 /* @brief Emulated EEPROM size code 0110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
284 #define FEATURE_FLS_EE_SIZE_0110 (0x0100u)
285 /* @brief Emulated EEPROM size code 0111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
286 #define FEATURE_FLS_EE_SIZE_0111 (0x0080u)
287 /* @brief Emulated EEPROM size code 1000 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
288 #define FEATURE_FLS_EE_SIZE_1000 (0x0040u)
289 /* @brief Emulated EEPROM size code 1001 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
290 #define FEATURE_FLS_EE_SIZE_1001 (0x0020u)
291 /* @brief Emulated EEPROM size code 1010 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
292 #define FEATURE_FLS_EE_SIZE_1010 (0xFFFFu)
293 /* @brief Emulated EEPROM size code 1011 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
294 #define FEATURE_FLS_EE_SIZE_1011 (0xFFFFu)
295 /* @brief Emulated EEPROM size code 1100 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
296 #define FEATURE_FLS_EE_SIZE_1100 (0xFFFFu)
297 /* @brief Emulated EEPROM size code 1101 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
298 #define FEATURE_FLS_EE_SIZE_1101 (0xFFFFu)
299 /* @brief Emulated EEPROM size code 1110 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
300 #define FEATURE_FLS_EE_SIZE_1110 (0xFFFFu)
301 /* @brief Emulated EEPROM size code 1111 mapping to emulated EEPROM size in bytes (0xFFFF = reserved). */
302 #define FEATURE_FLS_EE_SIZE_1111 (0x0000u)
303 
304 /* CAN module features */
305 
306 /* @brief Frames available in Rx FIFO flag shift */
307 #define FEATURE_CAN_RXFIFO_FRAME_AVAILABLE (5U)
308 /* @brief Rx FIFO warning flag shift */
309 #define FEATURE_CAN_RXFIFO_WARNING (6U)
310 /* @brief Rx FIFO overflow flag shift */
311 #define FEATURE_CAN_RXFIFO_OVERFLOW (7U)
312 /* @brief Has Flexible Data Rate for CAN0 */
313 #define FEATURE_CAN0_HAS_FD (1)
314 /* @brief Has Flexible Data Rate for CAN1 */
315 #define FEATURE_CAN1_HAS_FD (0)
316 /* @brief Has Flexible Data Rate for CAN2 */
317 #define FEATURE_CAN2_HAS_FD (0)
318 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN0 */
319 #define FEATURE_CAN0_MAX_MB_NUM (32U)
320 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN1 */
321 #define FEATURE_CAN1_MAX_MB_NUM (16U)
322 /* @brief Maximum number of Message Buffers supported for payload size 8 for CAN2 */
323 #define FEATURE_CAN2_MAX_MB_NUM (16U)
324 /* @brief Has PE clock source select (bit field CAN_CTRL1[CLKSRC]). */
325 #define FEATURE_CAN_HAS_PE_CLKSRC_SELECT (1)
326 /* @brief Has DMA enable (bit field MCR[DMA]). */
327 #define FEATURE_CAN_HAS_DMA_ENABLE (1)
328 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
329 #define FEATURE_CAN_MAX_MB_NUM (32U)
330 /* @brief Maximum number of Message Buffers supported for payload size 8 for any of the CAN instances */
331 #define FEATURE_CAN_MAX_MB_NUM_ARRAY { FEATURE_CAN0_MAX_MB_NUM, \
332  FEATURE_CAN1_MAX_MB_NUM, \
333  FEATURE_CAN2_MAX_MB_NUM }
334 /* @brief Has Pretending Networking mode */
335 #define FEATURE_CAN_HAS_PRETENDED_NETWORKING (1)
336 /* @brief Has Stuff Bit Count Enable Bit */
337 #define FEATURE_CAN_HAS_STFCNTEN_ENABLE (0)
338 /* @brief Has ISO CAN FD Enable Bit */
339 #define FEATURE_CAN_HAS_ISOCANFDEN_ENABLE (1)
340 /* @brief Has Message Buffer Data Size Region 1 */
341 #define FEATURE_CAN_HAS_MBDSR1 (0)
342 /* @brief Has Message Buffer Data Size Region 2 */
343 #define FEATURE_CAN_HAS_MBDSR2 (0)
344 /* @brief DMA hardware requests for all FlexCAN instances */
345 #define FEATURE_CAN_EDMA_REQUESTS { EDMA_REQ_FLEXCAN0, \
346  EDMA_REQ_FLEXCAN1, \
347  EDMA_REQ_FLEXCAN2 }
348 
349 
350 /* @brief Maximum number of Message Buffers IRQs */
351 #define FEATURE_CAN_MB_IRQS_MAX_COUNT (2U)
352 /* @brief Message Buffers IRQs */
353 #define FEATURE_CAN_MB_IRQS { CAN_ORed_0_15_MB_IRQS, \
354  CAN_ORed_16_31_MB_IRQS }
355 /* @brief Has Wake Up Irq channels (CAN_Wake_Up_IRQS_CH_COUNT > 0u) */
356 #define FEATURE_CAN_HAS_WAKE_UP_IRQ (1)
357 
358 #if FEATURE_CAN_HAS_PE_CLKSRC_SELECT
359 
360 #define FEATURE_CAN_PE_CLK_NUM 2U
361 /* @brief FlexCAN clock source */
362 typedef enum {
366 /* @brief Clock names for FlexCAN PE clock */
367 #define FLEXCAN_PE_CLOCK_NAMES { FLEXCAN_CLK_SOURCE_SOSCDIV2, FLEXCAN_CLK_SOURCE_SYS }
368 #endif
369 /* @brief Has Self Wake Up mode */
370 #define FEATURE_CAN_HAS_SELF_WAKE_UP (0)
371 
372 /* LPUART module features */
373 
374 /* @brief Has extended data register ED. */
375 #define FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
376 /* @brief Hardware flow control (RTS, CTS) is supported. */
377 #define FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
378 /* @brief Baud rate oversampling is available. */
379 #define FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
380 /* @brief Baud rate oversampling is available. */
381 #define FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
382 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
383 #define FEATURE_LPUART_FIFO_SIZE (4U)
384 /* @brief Supports two match addresses to filter incoming frames. */
385 #define FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
386 /* @brief Has transmitter/receiver DMA enable bits. */
387 #define FEATURE_LPUART_HAS_DMA_ENABLE (1)
388 /* @brief Flag clearance mask for STAT register. */
389 #define FEATURE_LPUART_STAT_REG_FLAGS_MASK (0xC01FC000U)
390 /* @brief Flag clearance mask for FIFO register. */
391 #define FEATURE_LPUART_FIFO_REG_FLAGS_MASK (0x00030000U)
392 /* @brief Default oversampling ratio. */
393 #define FEATURE_LPUART_DEFAULT_OSR (0x0FUL)
394 /* @brief Default baud rate modulo divisor. */
395 #define FEATURE_LPUART_DEFAULT_SBR (0x04UL)
396 /* @brief Clock names for LPUART. */
397 #define LPUART_CLOCK_NAMES {LPUART0_CLK, LPUART1_CLK, LPUART2_CLK}
398 
399 /* FlexIO module features */
400 
401 /* @brief Define the maximum number of shifters for any FlexIO instance. */
402 #define FEATURE_FLEXIO_MAX_SHIFTER_COUNT (4U)
403 /* @brief Define DMA request names for Flexio. */
404 #define FEATURE_FLEXIO_DMA_REQ_0 EDMA_REQ_FLEXIO_SHIFTER0
405 #define FEATURE_FLEXIO_DMA_REQ_1 EDMA_REQ_FLEXIO_SHIFTER1
406 #define FEATURE_FLEXIO_DMA_REQ_2 EDMA_REQ_FLEXIO_SHIFTER2
407 #define FEATURE_FLEXIO_DMA_REQ_3 EDMA_REQ_FLEXIO_SHIFTER3
408 
409 /* LPSPI module features */
410 
411 /* @brief DMA instance used for LPSPI module */
412 #define LPSPI_DMA_INSTANCE 0U
413 
414 /* LPI2C module features */
415 
416 /* @brief DMA instance used for LPI2C module */
417 #define LPI2C_DMA_INSTANCE 0U
418 
419 /* @brief EDMA requests for LPI2C module. */
420 #define LPI2C_EDMA_REQ {{(uint8_t)EDMA_REQ_LPI2C0_TX, (uint8_t)EDMA_REQ_LPI2C0_RX}}
421 /* @brief PCC clocks for LPI2C module. */
422 #define LPI2C_PCC_CLOCKS {LPI2C0_CLK}
423 
424 /* PDB module features */
425 
426 /* @brief Define the count of supporting ADC channels per each PDB. */
427 #define FEATURE_PDB_ADC_CHANNEL_COUNT (2U)
428 /* @brief Define the count of supporting ADC pre-trigger for each channel. */
429 #define FEATURE_PDB_ADC_PRE_CHANNEL_COUNT (8U)
430 /* @brief Define the count of supporting Pulse-Out outputs per each PDB. */
431 #define FEATURE_PDB_PODLY_COUNT (1U)
432 
433 /* Interrupt module features */
434 
435 /* @brief Lowest interrupt request number. */
436 #define FEATURE_INTERRUPT_IRQ_MIN (NonMaskableInt_IRQn)
437 /* @brief Highest interrupt request number. */
438 #define FEATURE_INTERRUPT_IRQ_MAX (FTM3_Ovf_Reload_IRQn)
439 
440 #define FEATURE_NVIC_PRIO_BITS (4U)
441 /* @brief Has software interrupt. */
442 #define FEATURE_INTERRUPT_HAS_SOFTWARE_IRQ (0u)
443 /* @brief Has pending interrupt state. */
444 #define FEATURE_INTERRUPT_HAS_PENDING_STATE (1u)
445 /* @brief Has active interrupt state. */
446 #define FEATURE_INTERRUPT_HAS_ACTIVE_STATE (1u)
447 
448 
449 /* System Control Block module features */
450 
451 /* @brief VECTKEY value so that AIRCR register write is not ignored. */
452 #define FEATURE_SCB_VECTKEY (0x05FAU)
453 
454 
455 /* SMC module features */
456 
457 /* @brief Has stop option (register bit STOPCTRL[STOPO]). */
458 #define FEATURE_SMC_HAS_STOPO (1)
459 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
460 #define FEATURE_SMC_HAS_PSTOPO (0)
461 /* @brief Has WAIT and VLPW options. */
462 #define FEATURE_SMC_HAS_WAIT_VLPW (0)
463 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
464 #define FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
465 
466 
467 /* MPU module features */
468 
469 /* @brief Specifies hardware revision level. */
470 #define FEATURE_MPU_HARDWARE_REVISION_LEVEL (1U)
471 /* @brief Has process identifier support. */
472 #define FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1U)
473 /* @brief Specifies total number of bus masters. */
474 #define FEATURE_MPU_MASTER_COUNT (3U)
475 /* @brief Specifies maximum number of masters which have separated
476 privilege rights for user and supervisor mode accesses (e.g. master0~3 in S32K14x).
477 */
478 #define FEATURE_MPU_MAX_LOW_MASTER_NUMBER (3U)
479 /* @brief Specifies maximum number of masters which have only
480 read and write permissions (e.g. master4~7 in S32K14x).
481 */
482 #define FEATURE_MPU_MAX_HIGH_MASTER_NUMBER (7U)
483 
484 /* @brief Specifies number of set access control right bits for
485  masters which have separated privilege rights for user and
486  supervisor mode accesses (e.g. master0~3 in S32K14x).
487 */
488 #define FEATURE_MPU_LOW_MASTER_CONTROL_WIDTH (6U)
489 /* @brief Specifies number of set access control right bits for
490  masters which have only read and write permissions(e.g. master4~7 in S32K14x).
491 */
492 #define FEATURE_MPU_HIGH_MASTER_CONTROL_WIDTH (2U)
493 
494 /* @brief The MPU Logical Bus Master Number for core bus master. */
495 #define FEATURE_MPU_MASTER_CORE (0U)
496 /* @brief The MPU Logical Bus Master Number for Debugger master. */
497 #define FEATURE_MPU_MASTER_DEBUGGER (1U)
498 /* @brief The MPU Logical Bus Master Number for DMA master. */
499 #define FEATURE_MPU_MASTER_DMA (2U)
500 /* @brief Specifies master number. */
501 #define FEATURE_MPU_MASTER \
502 { \
503  FEATURE_MPU_MASTER_CORE, \
504  FEATURE_MPU_MASTER_DEBUGGER, \
505  FEATURE_MPU_MASTER_DMA, \
506 }
507 
508 /* @brief Specifies total number of slave ports. */
509 #define FEATURE_MPU_SLAVE_COUNT (4U)
510 /* @brief The MPU Slave Port Assignment for Flash Controller and boot ROM. */
511 #define FEATURE_MPU_SLAVE_FLASH_BOOTROM (0U)
512 /* @brief The MPU Slave Port Assignment for SRAM back door. */
513 #define FEATURE_MPU_SLAVE_SRAM_BACKDOOR (1U)
514 /* @brief The MPU Slave Port Assignment for SRAM_L front door. */
515 #define FEATURE_MPU_SLAVE_SRAM_L_FRONTDOOR (2U)
516 /* @brief The MPU Slave Port Assignment for SRAM_U front door. */
517 #define FEATURE_MPU_SLAVE_SRAM_U_FRONTDOOR (3U)
518 /* @brief The MPU Slave Port mask. */
519 #define FEATURE_MPU_SLAVE_MASK (0xF0000000U)
520 #define FEATURE_MPU_SLAVE_SHIFT (28u)
521 #define FEATURE_MPU_SLAVE_WIDTH (4u)
522 #define FEATURE_MPU_SLAVE(x) (((uint32_t)(((uint32_t)(x))<<FEATURE_MPU_SLAVE_SHIFT))&FEATURE_MPU_SLAVE_MASK)
523 
524 /* WDOG module features */
525 
526 /* @brief The 32-bit value used for unlocking the WDOG. */
527 #define FEATURE_WDOG_UNLOCK_VALUE (0xD928C520U)
528 /* @brief The 32-bit value used for resetting the WDOG counter. */
529 #define FEATURE_WDOG_TRIGGER_VALUE (0xB480A602U)
530 /* @brief The reset value of the timeout register. */
531 #define FEATURE_WDOG_TO_RESET_VALUE (0x400U)
532 /* @brief The value minimum of the timeout register. */
533 #define FEATURE_WDOG_MINIMUM_TIMEOUT_VALUE (0x0U)
534 /* @brief The reset value of the window register. */
535 #define FEATURE_WDOG_WIN_RESET_VALUE (0x0U)
536 /* @brief The mask of the reserved bit in the CS register. */
537 #define FEATURE_WDOG_CS_RESERVED_MASK (0x2000U)
538 /* @brief The value used to set WDOG source clock from LPO. */
539 #define FEATURE_WDOG_CLK_FROM_LPO (0x1UL)
540 /* @brief The first 16-bit value used for unlocking the WDOG. */
541 #define FEATURE_WDOG_UNLOCK16_FIRST_VALUE (0xC520U)
542 /* @brief The second 16-bit value used for unlocking the WDOG. */
543 #define FEATURE_WDOG_UNLOCK16_SECOND_VALUE (0xD928U)
544 /* @brief The first 16-bit value used for resetting the WDOG counter. */
545 #define FEATURE_WDOG_TRIGGER16_FIRST_VALUE (0xA602U)
546 /* @brief The second 16-bit value used for resetting the WDOG counter. */
547 #define FEATURE_WDOG_TRIGGER16_SECOND_VALUE (0xB480U)
548 
549 /* CRC module features */
550 
551 /* @brief CRC module use for S32K1xx. */
552 #define FEATURE_CRC_DRIVER_S32K1xx (1)
553 /* Default CRC bit width */
554 #define CRC_DEFAULT_WIDTH CRC_BITS_16
555 /* Default CRC read transpose */
556 #define CRC_DEFAULT_READ_TRANSPOSE CRC_TRANSPOSE_NONE
557 /* Default polynomial 0x1021U */
558 #define CRC_DEFAULT_POLYNOMIAL (0x1021U)
559 
560 /* EDMA module features */
561 
562 /* @brief Number of EDMA channels. */
563 #define FEATURE_EDMA_MODULE_CHANNELS (16U)
564 /* @brief Number of EDMA channel interrupt lines. */
565 #define FEATURE_CHANNEL_INTERRUPT_LINES (16U)
566 /* @brief Number of EDMA error interrupt lines. */
567 #define FEATURE_ERROR_INTERRUPT_LINES (1U)
568 /* @brief eDMA module has error interrupt. */
569 #define FEATURE_EDMA_HAS_ERROR_IRQ
570 /* @brief eDMA module has separate interrupt lines for each channel. */
571 #define FEATURE_EDMA_SEPARATE_IRQ_LINES_PER_CHN
572 /* @brief Conversion from channel index to DCHPRI index. */
573 #define FEATURE_EDMA_CHN_TO_DCHPRI_INDEX(x) ((x) ^ 3U)
574 /* @brief eDMA channel groups count. */
575 #define FEATURE_EDMA_CHANNEL_GROUP_COUNT (1U)
576 /* @brief Number of eDMA channels with asynchronous request capability. */
577 #define FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16U)
578 /* @brief Clock names for eDMA. */
579 #define EDMA_CLOCK_NAMES {SIM_DMA_CLK}
580 
581 /* DMAMUX module features */
582 
583 /* @brief Number of DMA channels. */
584 #define FEATURE_DMAMUX_MODULE_CHANNELS (16U)
585 /* @brief Has the periodic trigger capability */
586 #define FEATURE_DMAMUX_HAS_TRIG (1)
587 /* @brief Conversion from request source to the actual DMAMUX channel */
588 #define FEATURE_DMAMUX_REQ_SRC_TO_CHN(x) (x)
589 /* @brief Mapping between request source and DMAMUX instance */
590 #define FEATURE_DMAMUX_REQ_SRC_TO_INSTANCE(x) (0U)
591 /* @brief Conversion from eDMA channel index to DMAMUX channel. */
592 #define FEATURE_DMAMUX_CHN_FOR_EDMA_CHN(x) (x)
593 /* @brief Conversion from DMAMUX channel DMAMUX register index. */
594 #define FEATURE_DMAMUX_CHN_REG_INDEX(x) (x)
595 /* @brief Clock names for DMAMUX. */
596 #define DMAMUX_CLOCK_NAMES {DMAMUX0_CLK}
597 
605 typedef enum {
660 
661 /* LPI2C module features */
662 
663 /* @brief Disable high-speed and ultra-fast operating modes for S32K14x. */
664 #define LPI2C_HAS_FAST_PLUS_MODE (0U)
665 #define LPI2C_HAS_HIGH_SPEED_MODE (0U)
666 #define LPI2C_HAS_ULTRA_FAST_MODE (0U)
667 
668 /* FTM module features */
669 /* @brief Number of PWM channels */
670 #define FEATURE_FTM_CHANNEL_COUNT (8U)
671 /* @brief Number of fault channels */
672 #define FTM_FEATURE_FAULT_CHANNELS (4U)
673 /* @brief Width of control channel */
674 #define FTM_FEATURE_COMBINE_CHAN_CTRL_WIDTH (8U)
675 /* @brief Output channel offset */
676 #define FTM_FEATURE_OUTPUT_CHANNEL_OFFSET (16U)
677 /* @brief Max counter value */
678 #define FTM_FEATURE_CNT_MAX_VALUE_U32 (0x0000FFFFU)
679 /* @brief Input capture for single shot */
680 #define FTM_FEATURE_INPUT_CAPTURE_SINGLE_SHOT (2U)
681 /* @brief Dithering has supported on the generated PWM signals */
682 #define FEATURE_FTM_HAS_SUPPORTED_DITHERING (0U)
683 
684 /* EWM module features */
685 
686 /* @brief First byte of the EWM Service key */
687 #define FEATURE_EWM_KEY_FIRST_BYTE (0xB4U)
688 /* @brief Second byte of the EWM Service key */
689 #define FEATURE_EWM_KEY_SECOND_BYTE (0x2CU)
690 /* @brief EWM Compare High register maximum value */
691 #define FEATURE_EWM_CMPH_MAX_VALUE (0xFEU)
692 /* @brief EWM Compare Low register minimum value */
693 #define FEATURE_EWM_CMPL_MIN_VALUE (0x00U)
694 
695 /* CLOCK names */
696 
698 typedef enum {
699 
700  /* Main clocks */
701  CORE_CLK = 0u,
702  BUS_CLK = 1u,
703  SLOW_CLK = 2u,
704  CLKOUT_CLK = 3u,
706  /* Other internal clocks used by peripherals. */
707  SIRC_CLK = 4u,
708  FIRC_CLK = 5u,
709  SOSC_CLK = 6u,
710  SPLL_CLK = 7u,
714  SIRCDIV1_CLK = 10u,
715  SIRCDIV2_CLK = 11u,
716  FIRCDIV1_CLK = 12u,
717  FIRCDIV2_CLK = 13u,
718  SOSCDIV1_CLK = 14u,
719  SOSCDIV2_CLK = 15u,
720  SPLLDIV1_CLK = 16u,
721  SPLLDIV2_CLK = 17u,
725  /* SIM clocks */
732  SIM_LPO_CLK = 27u,
736  SIM_EIM_CLK = 31u,
737  SIM_ERM_CLK = 32u,
738  SIM_DMA_CLK = 33u,
739  SIM_MPU_CLK = 34u,
740  SIM_MSCM_CLK = 35u,
743  /* PCC clocks */
744  CMP0_CLK = 41u,
745  CRC0_CLK = 42u,
746  DMAMUX0_CLK = 43u,
747  EWM0_CLK = 44u,
748  PORTA_CLK = 45u,
749  PORTB_CLK = 46u,
750  PORTC_CLK = 47u,
751  PORTD_CLK = 48u,
752  PORTE_CLK = 49u,
753  RTC0_CLK = 50u,
755  FlexCAN0_CLK = 52u,
756  FlexCAN1_CLK = 53u,
757  FlexCAN2_CLK = 54u,
758  PDB0_CLK = 55u,
759  PDB1_CLK = 56u,
761  FTFC0_CLK = 58u,
763  FTM0_CLK = 60u,
764  FTM1_CLK = 61u,
765  FTM2_CLK = 62u,
766  FTM3_CLK = 63u,
768  ADC0_CLK = 65u,
769  ADC1_CLK = 66u,
770  FLEXIO0_CLK = 67u,
771  LPI2C0_CLK = 68u,
772  LPIT0_CLK = 69u,
773  LPSPI0_CLK = 70u,
774  LPSPI1_CLK = 71u,
775  LPSPI2_CLK = 72u,
776  LPTMR0_CLK = 73u,
777  LPUART0_CLK = 74u,
778  LPUART1_CLK = 75u,
779  LPUART2_CLK = 76u,
783 } clock_names_t;
784 
785 #define PCC_INVALID_INDEX 0
786 
792 #define PCC_CLOCK_NAME_MAPPINGS \
793 { \
794 PCC_INVALID_INDEX, \
795 PCC_INVALID_INDEX, \
796 PCC_INVALID_INDEX, \
797 PCC_INVALID_INDEX, \
798 PCC_INVALID_INDEX, \
799 PCC_INVALID_INDEX, \
800 PCC_INVALID_INDEX, \
801 PCC_INVALID_INDEX, \
802 PCC_INVALID_INDEX, \
803 PCC_INVALID_INDEX, \
804 PCC_INVALID_INDEX, \
805 PCC_INVALID_INDEX, \
806 PCC_INVALID_INDEX, \
807 PCC_INVALID_INDEX, \
808 PCC_INVALID_INDEX, \
809 PCC_INVALID_INDEX, \
810 PCC_INVALID_INDEX, \
811 PCC_INVALID_INDEX, \
812 PCC_INVALID_INDEX, \
813 PCC_INVALID_INDEX, \
814 PCC_INVALID_INDEX, \
815 PCC_INVALID_INDEX, \
816 PCC_INVALID_INDEX, \
817 PCC_INVALID_INDEX, \
818 PCC_INVALID_INDEX, \
819 PCC_INVALID_INDEX, \
820 PCC_INVALID_INDEX, \
821 PCC_INVALID_INDEX, \
822 PCC_INVALID_INDEX, \
823 PCC_INVALID_INDEX, \
824 PCC_INVALID_INDEX, \
825 PCC_INVALID_INDEX, \
826 PCC_INVALID_INDEX, \
827 PCC_INVALID_INDEX, \
828 PCC_INVALID_INDEX, \
829 PCC_INVALID_INDEX, \
830 PCC_INVALID_INDEX, \
831 PCC_INVALID_INDEX, \
832 PCC_INVALID_INDEX, \
833 PCC_INVALID_INDEX, \
834 PCC_INVALID_INDEX, \
835 PCC_CMP0_INDEX, \
836 PCC_CRC_INDEX, \
837 PCC_DMAMUX_INDEX, \
838 PCC_EWM_INDEX, \
839 PCC_PORTA_INDEX, \
840 PCC_PORTB_INDEX, \
841 PCC_PORTC_INDEX, \
842 PCC_PORTD_INDEX, \
843 PCC_PORTE_INDEX, \
844 PCC_RTC_INDEX, \
845 PCC_INVALID_INDEX, \
846 PCC_FlexCAN0_INDEX, \
847 PCC_FlexCAN1_INDEX, \
848 PCC_FlexCAN2_INDEX, \
849 PCC_PDB0_INDEX, \
850 PCC_PDB1_INDEX, \
851 PCC_INVALID_INDEX, \
852 PCC_FTFC_INDEX, \
853 PCC_INVALID_INDEX, \
854 PCC_FTM0_INDEX, \
855 PCC_FTM1_INDEX, \
856 PCC_FTM2_INDEX, \
857 PCC_FTM3_INDEX, \
858 PCC_INVALID_INDEX, \
859 PCC_ADC0_INDEX, \
860 PCC_ADC1_INDEX, \
861 PCC_FlexIO_INDEX, \
862 PCC_LPI2C0_INDEX, \
863 PCC_LPIT_INDEX, \
864 PCC_LPSPI0_INDEX, \
865 PCC_LPSPI1_INDEX, \
866 PCC_LPSPI2_INDEX, \
867 PCC_LPTMR0_INDEX, \
868 PCC_LPUART0_INDEX, \
869 PCC_LPUART1_INDEX, \
870 PCC_LPUART2_INDEX, \
871 PCC_INVALID_INDEX, \
872 PCC_INVALID_INDEX, \
873 }
874 
878 #define NO_PERIPHERAL_FEATURE (0U) /* It's not a peripheral instance, there is no peripheral feature. */
879 #define HAS_CLOCK_GATING_IN_SIM (1U << 0U) /* Clock gating is implemented in SIM (it's not in PCC) */
880 #define HAS_MULTIPLIER (1U << 1U) /* Multiplier is implemented in PCC */
881 #define HAS_DIVIDER (1U << 2U) /* Divider is implemented in PCC */
882 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC1 (1U << 3U) /* Functional clock source is provided by the first asynchronous clock. */
883 #define HAS_PROTOCOL_CLOCK_FROM_ASYNC2 (1U << 4U) /* Functional clock source is provided by the second asynchronous clock. */
884 #define HAS_INT_CLOCK_FROM_BUS_CLOCK (1U << 5U) /* Interface clock is provided by the bus clock. */
885 #define HAS_INT_CLOCK_FROM_SYS_CLOCK (1U << 6U) /* Interface clock is provided by the sys clock. */
886 #define HAS_INT_CLOCK_FROM_SLOW_CLOCK (1U << 7U) /* Interface clock is provided by the slow clock. */
887 
892 #define PERIPHERAL_FEATURES \
893 { \
894 (NO_PERIPHERAL_FEATURE), \
895 (NO_PERIPHERAL_FEATURE), \
896 (NO_PERIPHERAL_FEATURE), \
897 (NO_PERIPHERAL_FEATURE), \
898 (NO_PERIPHERAL_FEATURE), \
899 (NO_PERIPHERAL_FEATURE), \
900 (NO_PERIPHERAL_FEATURE), \
901 (NO_PERIPHERAL_FEATURE), \
902 (NO_PERIPHERAL_FEATURE), \
903 (NO_PERIPHERAL_FEATURE), \
904 (NO_PERIPHERAL_FEATURE), \
905 (NO_PERIPHERAL_FEATURE), \
906 (NO_PERIPHERAL_FEATURE), \
907 (NO_PERIPHERAL_FEATURE), \
908 (NO_PERIPHERAL_FEATURE), \
909 (NO_PERIPHERAL_FEATURE), \
910 (NO_PERIPHERAL_FEATURE), \
911 (NO_PERIPHERAL_FEATURE), \
912 (NO_PERIPHERAL_FEATURE), \
913 (NO_PERIPHERAL_FEATURE), \
914 (NO_PERIPHERAL_FEATURE), \
915 (NO_PERIPHERAL_FEATURE), \
916 (NO_PERIPHERAL_FEATURE), \
917 (NO_PERIPHERAL_FEATURE), \
918 (NO_PERIPHERAL_FEATURE), \
919 (NO_PERIPHERAL_FEATURE), \
920 (NO_PERIPHERAL_FEATURE), \
921 (NO_PERIPHERAL_FEATURE), \
922 (NO_PERIPHERAL_FEATURE), \
923 (NO_PERIPHERAL_FEATURE), \
924 (NO_PERIPHERAL_FEATURE), \
925 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
926 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
927 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
928 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
929 (HAS_CLOCK_GATING_IN_SIM | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
930 (NO_PERIPHERAL_FEATURE), \
931 (NO_PERIPHERAL_FEATURE), \
932 (NO_PERIPHERAL_FEATURE), \
933 (NO_PERIPHERAL_FEATURE), \
934 (NO_PERIPHERAL_FEATURE), \
935 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
936 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
937 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
938 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
939 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
940 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
941 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
942 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
943 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
944 (HAS_INT_CLOCK_FROM_BUS_CLOCK), \
945 (NO_PERIPHERAL_FEATURE), \
946 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
947 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
948 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
949 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
950 (HAS_INT_CLOCK_FROM_SYS_CLOCK), \
951 (NO_PERIPHERAL_FEATURE), \
952 (HAS_INT_CLOCK_FROM_SLOW_CLOCK), \
953 (NO_PERIPHERAL_FEATURE), \
954 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
955 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
956 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
957 (HAS_PROTOCOL_CLOCK_FROM_ASYNC1 | HAS_INT_CLOCK_FROM_SYS_CLOCK), \
958 (NO_PERIPHERAL_FEATURE), \
959 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
960 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
961 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
962 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
963 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
964 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
965 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
966 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
967 (HAS_MULTIPLIER | HAS_DIVIDER | HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
968 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
969 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
970 (HAS_PROTOCOL_CLOCK_FROM_ASYNC2 | HAS_INT_CLOCK_FROM_BUS_CLOCK), \
971 (NO_PERIPHERAL_FEATURE), \
972 (NO_PERIPHERAL_FEATURE), \
973 }
974 
975 /* Time to wait for SIRC to stabilize (number of
976  * cycles when core runs at maximum speed - 112 MHz */
977 #define SIRC_STABILIZATION_TIMEOUT 26U;
978 
979 /* Time to wait for FIRC to stabilize (number of
980  * cycles when core runs at maximum speed - 112 MHz */
981 #define FIRC_STABILIZATION_TIMEOUT 10U;
982 
983 /* Time to wait for SOSC to stabilize (number of
984  * cycles when core runs at maximum speed - 112 MHz */
985 #define SOSC_STABILIZATION_TIMEOUT 3205000U;
986 
987 /* Time to wait for SPLL to stabilize (number of
988  * cycles when core runs at maximum speed - 112 MHz */
989 #define SPLL_STABILIZATION_TIMEOUT 1000U;
990 
1001 #define MAX_FREQ_VLPR 0U
1002 #define MAX_FREQ_RUN 1U
1003 #define MAX_FREQ_HSRUN 2U
1004 
1005 #define MAX_FREQ_SYS_CLK 0U
1006 #define MAX_FREQ_BUS_CLK 1U
1007 #define MAX_FREQ_SLOW_CLK 2U
1008 
1009 #define MAX_FREQ_MODES_NO 3U
1010 #define MAX_FREQ_CLK_NO 3U
1011 
1012 #define CLOCK_MAX_FREQUENCIES \
1013 {/* SYS_CLK BUS_CLK SLOW_CLK */ \
1014 { 4000000, 4000000, 1000000}, \
1015 { 80000000,40000000,26670000}, \
1016 {112000000,56000000,28000000}, \
1017 }
1018 
1019 
1030 #define TMP_SIRC_CLK 0U
1031 #define TMP_FIRC_CLK 1U
1032 #define TMP_SOSC_CLK 2U
1033 #define TMP_SPLL_CLK 3U
1034 
1035 #define TMP_SYS_DIV 0U
1036 #define TMP_BUS_DIV 1U
1037 #define TMP_SLOW_DIV 2U
1038 
1039 #define TMP_SYS_CLK_NO 4U
1040 #define TMP_SYS_DIV_NO 3U
1041 
1042 #define TMP_SYSTEM_CLOCK_CONFIGS \
1043 { /* SYS_CLK BUS_CLK SLOW_CLK */ \
1044 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_1}, \
1045 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_4}, \
1046 { SCG_SYSTEM_CLOCK_DIV_BY_1, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
1047 { SCG_SYSTEM_CLOCK_DIV_BY_3, SCG_SYSTEM_CLOCK_DIV_BY_2, SCG_SYSTEM_CLOCK_DIV_BY_2}, \
1048 }
1049 
1050 /* Do not use the old names of the renamed symbols */
1051 /* #define DO_NOT_USE_DEPRECATED_SYMBOLS */
1052 
1058 #if !defined(DO_NOT_USE_DEPRECATED_SYMBOLS)
1059 #define CORE_CLOCK CORE_CLK
1060 #define BUS_CLOCK BUS_CLK
1061 #define SLOW_CLOCK SLOW_CLK
1062 #define CLKOUT_CLOCK CLKOUT_CLK
1063 #define SIRC_CLOCK SIRC_CLK
1064 #define FIRC_CLOCK FIRC_CLK
1065 #define SOSC_CLOCK SOSC_CLK
1066 #define SPLL_CLOCK SPLL_CLK
1067 #define RTC_CLKIN_CLOCK RTC_CLKIN_CLK
1068 #define SCG_CLKOUT_CLOCK SCG_CLKOUT_CLK
1069 #define SIM_RTCCLK_CLOCK SIM_RTCCLK_CLK
1070 #define SIM_LPO_CLOCK SIM_LPO_CLK
1071 #define SIM_LPO_1K_CLOCK SIM_LPO_1K_CLK
1072 #define SIM_LPO_32K_CLOCK SIM_LPO_32K_CLK
1073 #define SIM_LPO_128K_CLOCK SIM_LPO_128K_CLK
1074 #define SIM_EIM_CLOCK SIM_EIM_CLK
1075 #define SIM_ERM_CLOCK SIM_ERM_CLK
1076 #define SIM_DMA_CLOCK SIM_DMA_CLK
1077 #define SIM_MPU_CLOCK SIM_MPU_CLK
1078 #define SIM_MSCM_CLOCK SIM_MSCM_CLK
1079 #define PCC_DMAMUX0_CLOCK DMAMUX0_CLK
1080 #define PCC_CRC0_CLOCK CRC0_CLK
1081 #define PCC_RTC0_CLOCK RTC0_CLK
1082 #define PCC_PORTA_CLOCK PORTA_CLK
1083 #define PCC_PORTB_CLOCK PORTB_CLK
1084 #define PCC_PORTC_CLOCK PORTC_CLK
1085 #define PCC_PORTD_CLOCK PORTD_CLK
1086 #define PCC_PORTE_CLOCK PORTE_CLK
1087 #define PCC_EWM0_CLOCK EWM0_CLK
1088 #define PCC_CMP0_CLOCK CMP0_CLK
1089 #define PCC_FlexCAN0_CLOCK FlexCAN0_CLK
1090 #define PCC_FlexCAN1_CLOCK FlexCAN1_CLK
1091 #define PCC_FlexCAN2_CLOCK FlexCAN2_CLK
1092 #define PCC_PDB1_CLOCK PDB1_CLK
1093 #define PCC_PDB0_CLOCK PDB0_CLK
1094 #define PCC_FTFC0_CLOCK FTFC0_CLK
1095 #define PCC_FTM0_CLOCK FTM0_CLK
1096 #define PCC_FTM1_CLOCK FTM1_CLK
1097 #define PCC_FTM2_CLOCK FTM2_CLK
1098 #define PCC_FTM3_CLOCK FTM3_CLK
1099 #define PCC_ADC1_CLOCK ADC1_CLK
1100 #define PCC_LPSPI0_CLOCK LPSPI0_CLK
1101 #define PCC_LPSPI1_CLOCK LPSPI1_CLK
1102 #define PCC_LPSPI2_CLOCK LPSPI2_CLK
1103 #define PCC_LPIT0_CLOCK LPIT0_CLK
1104 #define PCC_ADC0_CLOCK ADC0_CLK
1105 #define PCC_LPTMR0_CLOCK LPTMR0_CLK
1106 #define PCC_FLEXIO0_CLOCK FLEXIO0_CLK
1107 #define PCC_LPI2C0_CLOCK LPI2C0_CLK
1108 #define PCC_LPUART0_CLOCK LPUART0_CLK
1109 #define PCC_LPUART1_CLOCK LPUART1_CLK
1110 #define PCC_LPUART2_CLOCK LPUART2_CLK
1111 #endif /* !DO_NOT_USE_DEPRECATED_SYMBOLS */
1112 
1113 
1114 /* CSEc module features */
1115 
1118 #define FEATURE_CSEC_PAGE_LENGTH_OFFSET (0xEU)
1119 
1121 #define FEATURE_CSEC_MESSAGE_LENGTH_OFFSET (0xCU)
1122 
1124 #define FEATURE_CSEC_MAC_LENGTH_OFFSET (0x8U)
1125 
1127 #define FEATURE_CSEC_BOOT_SIZE_OFFSET (0x1CU)
1128 
1130 #define FEATURE_CSEC_BOOT_FLAVOR_OFFSET (0x1BU)
1131 
1133 #define FEATURE_CSEC_FLASH_START_ADDRESS_OFFSET (0x10U)
1134 
1136 #define FEATURE_CSEC_VERIFICATION_STATUS_OFFSET (0x14U)
1137 
1138 #define FEATURE_CSEC_ERROR_BITS_OFFSET (0x4U)
1139 
1141 #define FEATURE_CSEC_SREG_OFFSET (0x2FU)
1142 
1144 #define FEATURE_CSEC_PAGE_0_OFFSET (0x0U)
1145 
1146 #define FEATURE_CSEC_PAGE_1_OFFSET (0x10U)
1147 
1148 #define FEATURE_CSEC_PAGE_2_OFFSET (0x20U)
1149 
1150 #define FEATURE_CSEC_PAGE_3_OFFSET (0x30U)
1151 
1152 #define FEATURE_CSEC_PAGE_4_OFFSET (0x40U)
1153 
1154 #define FEATURE_CSEC_PAGE_5_OFFSET (0x50U)
1155 
1156 #define FEATURE_CSEC_PAGE_6_OFFSET (0x60U)
1157 
1158 #define FEATURE_CSEC_PAGE_7_OFFSET (0x70U)
1159 
1160 
1161 /* ADC module features */
1162 
1165 #define FEATURE_ADC_HAS_EXTRA_NUM_REGS (0)
1166 
1170 #define FEATURE_ADC_MAX_NUM_EXT_CHANS (16)
1171 
1173 #if FEATURE_ADC_HAS_EXTRA_NUM_REGS
1174 #define ADC_CTRL_CHANS_COUNT ADC_aSC1_COUNT
1175 #else
1176 #define ADC_CTRL_CHANS_COUNT ADC_SC1_COUNT
1177 #endif /* FEATURE_ADC_HAS_EXTRA_NUM_REGS */
1178 
1180 #define ADC_DEFAULT_SAMPLE_TIME (0x0CU)
1181 
1182 #define ADC_DEFAULT_USER_GAIN (0x04U)
1183 
1184 /* MSCM module features */
1185 
1186 /* @brief Has interrupt router control registers (IRSPRCn). */
1187 #define FEATURE_MSCM_HAS_INTERRUPT_ROUTER (0)
1188 /* @brief Has directed CPU interrupt routerregisters (IRCPxxx). */
1189 #define FEATURE_MSCM_HAS_CPU_INTERRUPT_ROUTER (0)
1190 
1191 /* OSIF module features */
1192 
1193 #define FEATURE_OSIF_USE_SYSTICK (1)
1194 #define FEATURE_OSIF_FREERTOS_ISR_CONTEXT_METHOD (1) /* Cortex M device */
1195 
1196 /* TRGMUX module features */
1197 
1198 #define FEATURE_TRGMUX_HAS_EXTENDED_NUM_TRIGS (0)
1199 
1200 /* LPSPI module features */
1201 /* @brief Initial value for state structure */
1202 #define FEATURE_LPSPI_STATE_STRUCTURES_NULL {NULL, NULL, NULL}
1203 
1204 #endif /* S32K144_FEATURES_H */
1205 
1206 /*******************************************************************************
1207  * EOF
1208  ******************************************************************************/
dma_request_source_t
Structure for the DMA hardware request.
flexcan_clk_source_t
clock_names_t
Clock names.