50 uint8_t hwChannel = 0U;
51 uint8_t fltChannel = 0U;
52 uint8_t chnlPairNum = 0U;
53 uint8_t channelId = 0U;
60 FTM_DRV_SetClockSource(ftmBase, FTM_CLOCK_SOURCE_NONE);
62 FTM_DRV_ClearTimerOverflow(ftmBase);
64 FTM_DRV_SetWriteProtectionCmd(ftmBase,
false);
72 chnlPairNum = (uint8_t)(channelId >> 1U);
73 FTM_DRV_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum,
false);
75 FTM_DRV_SetChnEdgeLevel(ftmBase, channelId, 2U);
77 FTM_DRV_SetChnMSnBAMode(ftmBase, channelId, 3U);
79 FTM_DRV_EnablePwmChannelOutputs(ftmBase, channelId);
81 FTM_DRV_SetDualChnFaultCmd(ftmBase, chnlPairNum, ((param->
faultConfig)->faultMode != FTM_FAULT_CONTROL_DISABLED) ?
true :
false);
83 FTM_DRV_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum,
true);
84 FTM_DRV_SetDualChnCombineCmd(ftmBase, chnlPairNum,
false);
85 FTM_DRV_SetDualChnMofCombineCmd(ftmBase, chnlPairNum,
false);
94 chnlPairNum = (uint8_t)(channelId >> 1U);
95 FTM_DRV_SetDualEdgeCaptureCmd(ftmBase, chnlPairNum,
false);
97 FTM_DRV_SetChnEdgeLevel(ftmBase, channelId, 2U);
99 FTM_DRV_SetChnMSnBAMode(ftmBase, channelId, 3U);
102 FTM_DRV_EnablePwmChannelOutputs(ftmBase, channelId);
106 FTM_DRV_EnablePwmChannelOutputs(ftmBase, (uint8_t)(channelId + 1U));
108 FTM_DRV_SetChnEdgeLevel(ftmBase, (uint8_t)(channelId + 1U), 2U);
114 FTM_DRV_DisablePwmChannelOutputs(ftmBase, (uint8_t)(channelId + 1U));
118 FTM_DRV_SetDualChnFaultCmd(ftmBase, chnlPairNum, ((param->
faultConfig)->faultMode != FTM_FAULT_CONTROL_DISABLED) ?
true :
false);
120 FTM_DRV_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum,
true);
122 FTM_DRV_SetDualChnCombineCmd(ftmBase, chnlPairNum,
true);
136 if ((param->
faultConfig)->faultMode != FTM_FAULT_CONTROL_DISABLED)
139 FTM_DRV_SetPwmFaultBehavior(ftmBase, ((param->
faultConfig)->pwmOutputStateOnFault) ?
true :
false);
141 FTM_DRV_SetFaultInputFilterVal(ftmBase, ((param->
faultConfig)->faultFilterValue));
144 if (
true == (param->
faultConfig)->ftmFaultChannelParam[fltChannel].faultChannelEnabled)
147 FTM_DRV_SetFaultInputCmd(ftmBase, fltChannel,
true);
149 FTM_DRV_SetFaultInputFilterCmd(ftmBase,
151 ((param->
faultConfig)->ftmFaultChannelParam[fltChannel].faultFilterEnabled) ?
true :
false);
153 FTM_DRV_SetChnFaultInputPolarityCmd(ftmBase, fltChannel,
154 ((param->
faultConfig)->ftmFaultChannelParam[fltChannel].ftmFaultPinPolarity));
159 if (
true == ((param->
faultConfig)->pwmFaultInterrupt))
161 FTM_DRV_SetFaultInt(ftmBase,
true);
165 FTM_DRV_SetFaultControlMode(ftmBase, (param->
faultConfig)->faultMode);
173 FTM_DRV_SetCounterInitVal(ftmBase, 0U);
179 FTM_DRV_SetMod(ftmBase, (uint16_t)(state->
ftmPeriod >> 1U));
183 FTM_DRV_SetMod(ftmBase, (uint16_t)(state->
ftmPeriod - 1U));
215 FTM_DRV_Enable(ftmBase,
true);
216 FTM_DRV_SetPwmSyncMode(ftmBase,
true);
250 FTM_DRV_SetClockSource(ftmBase, FTM_CLOCK_SOURCE_NONE);
253 chnlPairNum = (uint8_t)(channel >> 1U);
255 FTM_DRV_SetChnCountVal(ftmBase, channel, 0U);
256 FTM_DRV_SetChnEdgeLevel(ftmBase, channel, 0U);
257 FTM_DRV_SetChnMSnBAMode(ftmBase, channel, 0U);
258 FTM_DRV_SetCpwms(ftmBase,
false);
260 FTM_DRV_SetChnOutputPolarityCmd(ftmBase, channel, FTM_POLARITY_LOW);
261 FTM_DRV_DisablePwmChannelOutputs(ftmBase, channel);
263 FTM_DRV_SetDualChnPwmSyncCmd(ftmBase, chnlPairNum,
false);
265 FTM_DRV_SetDualChnMofCombineCmd(ftmBase, chnlPairNum,
false);
266 FTM_DRV_SetDualChnCombineCmd(ftmBase, chnlPairNum,
false);
267 FTM_DRV_SetDualChnDeadtimeCmd(ftmBase, chnlPairNum,
false);
268 FTM_DRV_SetDualChnFaultCmd(ftmBase, chnlPairNum,
false);
272 FTM_DRV_SetExtDeadtimeValue(ftmBase, 0U);
273 FTM_DRV_SetDeadtimePrescale(ftmBase, FTM_DEADTIME_DIVID_BY_1);
274 FTM_DRV_SetDeadtimeCount(ftmBase, 0U);
276 FTM_DRV_ClearFaultControl(ftmBase);
278 FTM_DRV_SetFaultInt(ftmBase,
false);
280 FTM_DRV_SetFaultControlMode(ftmBase, FTM_FAULT_CONTROL_DISABLED);
282 FTM_DRV_SetMod(ftmBase, 0U);
283 FTM_DRV_SetCounter(ftmBase, 0U);
310 bool softwareTrigger)
314 uint16_t hwFirstEdge = 0U;
315 uint16_t hwSecondEdge = 0U;
316 uint16_t ftmPeriod = 0U;
317 uint8_t chnlPairNum = (uint8_t)(channel >> 1U);
327 ftmPeriod = (uint16_t)(ftmPeriod << 1U);
331 ftmPeriod = (uint16_t)(ftmPeriod + 1U);
354 hwFirstEdge = (uint16_t)(hwFirstEdge + 1U);
366 hwFirstEdge = firstEdge;
367 hwSecondEdge = secondEdge;
379 if (
true == FTM_DRV_GetDualChnMofCombineCmd(ftmBase, chnlPairNum))
384 FTM_DRV_SetChnCountVal(ftmBase, (uint8_t)(chnlPairNum * 2U), hwFirstEdge);
389 FTM_DRV_SetChnCountVal(ftmBase, (uint8_t)(chnlPairNum * 2U), hwFirstEdge);
393 FTM_DRV_SetChnCountVal(ftmBase, (uint8_t)((chnlPairNum * 2U) + 1U), hwSecondEdge);
400 FTM_DRV_SetChnCountVal(ftmBase, channel, (uint16_t)(hwFirstEdge >> 1U));
404 FTM_DRV_SetChnCountVal(ftmBase, channel, hwFirstEdge);
412 FTM_DRV_SetSoftwareTriggerCmd(ftmBase,
true);
440 bool softwareTrigger)
444 uint32_t ftmPeriod = 0U;
452 ftmPeriod = newValue;
456 if (newValue <= state->ftmSourceClockFrequency)
474 ftmPeriod = (ftmPeriod >> 1U);
478 ftmPeriod = (ftmPeriod - 1U);
481 FTM_DRV_SetMod(ftmBase, (uint16_t)(ftmPeriod));
485 FTM_DRV_SetSoftwareTriggerCmd(ftmBase,
true);
504 uint8_t numberOfChannels,
505 const uint8_t * channels,
506 const uint16_t * duty,
507 bool softwareTrigger)
514 for (i = 0U; i < numberOfChannels; i++)
516 ((ftmBase)->CONTROLS[channels[i]].CnV) = duty[i];
527 #if FEATURE_FTM_HAS_SUPPORTED_DITHERING
537 status_t FTM_DRV_UpdatePwmPeriodDither(uint32_t instance,
538 uint8_t newModFracVal,
539 bool softwareTrigger)
541 DEV_ASSERT((instance == FTM1_IDX) || (instance == FTM2_IDX));
545 FTM_DRV_SetModFracVal(ftmBase, newModFracVal);
549 FTM_DRV_SetSoftwareTriggerCmd(ftmBase,
true);
566 status_t FTM_DRV_UpdatePwmEdgeChannelDither(uint32_t instance,
568 uint8_t newMatchFracVal,
569 bool softwareTrigger)
571 DEV_ASSERT((instance == FTM1_IDX) || (instance == FTM2_IDX));
576 FTM_DRV_SetChnMatchFracVal(ftmBase, channel, newMatchFracVal);
580 FTM_DRV_SetSoftwareTriggerCmd(ftmBase,
true);
600 void FTM_PWM_DRV_IrqHandler(uint32_t instance,
601 uint32_t chnOutCtrlVal)
608 faultDetection =
true;
610 FTM_DRV_SetOutmaskReg(ftmBase, chnOutCtrlVal);
614 FTM_DRV_ClearTimerOverflow(ftmBase);
617 else if (faultDetection ==
true)
620 FTM_DRV_SetAllChnSoftwareCtrlCmd(ftmBase, 0x00U);
621 FTM_DRV_SetAllChnSoftwareCtrlVal(ftmBase, 0x00U);
623 uint8_t u8chnOutCtrlVal = (uint8_t)(chnOutCtrlVal & 0xFFu);
624 FTM_DRV_SetAllChnSoftwareCtrlCmd(ftmBase, u8chnOutCtrlVal);
625 FTM_DRV_SetAllChnSoftwareCtrlVal(ftmBase, u8chnOutCtrlVal);
627 FTM_DRV_SetOutmaskReg(ftmBase, 0x00U);
629 faultDetection =
false;
631 FTM_DRV_ClearTimerOverflow(ftmBase);
status_t FTM_DRV_DeinitPwm(uint32_t instance)
Stops all PWM channels .
FlexTimer state structure of the driver.
FTM_Type *const g_ftmBase[FTM_INSTANCE_COUNT]
Table of base addresses for FTM instances.
#define FTM_DUTY_TO_TICKS_SHIFT
Shift value which converts duty to ticks.
static bool FTM_DRV_GetCpwms(const FTM_Type *ftmBase)
Gets the FTM count direction bit.
ftm_state_t * ftmStatePtr[FTM_INSTANCE_COUNT]
Pointer to runtime state structure.
const ftm_combined_ch_param_t * pwmCombinedChannelConfig
status_t FTM_DRV_UpdatePwmPeriod(uint32_t instance, ftm_pwm_update_option_t typeOfUpdate, uint32_t newValue, bool softwareTrigger)
This function will update the new period in the frequency or in the counter value into mode register ...
static void FTM_DRV_ClearFaultsIsr(FTM_Type *const ftmBase)
Clears all fault interrupt flags that are active.
ftm_deadtime_ps_t deadTimePrescaler
uint8_t nNumCombinedPwmChannels
#define FEATURE_FTM_CHANNEL_COUNT
static void FTM_DRV_SetInitChnOutputCmd(FTM_Type *const ftmBase, bool enable)
Initializes the channels output.
static bool FTM_DRV_GetDualChnCombineCmd(const FTM_Type *ftmBase, uint8_t chnlPairNum)
Verify if an channels pair is used in combine mode or not.
#define FTM_MAX_DUTY_CYCLE
Maximum value for PWM duty cycle.
uint16_t FTM_DRV_ConvertFreqToPeriodTicks(uint32_t instance, uint32_t freqencyHz)
This function is used to covert the given frequency to period in ticks.
static uint8_t FTM_DRV_GetClockSource(const FTM_Type *ftmBase)
Reads the FTM clock source.
ftm_clock_source_t ftmClockSource
const ftm_pwm_fault_param_t * faultConfig
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t FTM_DRV_FastUpdatePwmChannels(uint32_t instance, uint8_t numberOfChannels, const uint8_t *channels, const uint16_t *duty, bool softwareTrigger)
This function will update the duty cycle of PWM output for multiple channels.
#define FTM_INSTANCE_COUNT
uint16_t uDutyCyclePercent
bool enableSecondChannelOutput
uint8_t nNumIndependentPwmChannels
FlexTimer driver PWM parameters.
#define FTM_FEATURE_FAULT_CHANNELS
bool enableExternalTrigger
ftm_polarity_t mainChannelPolarity
bool enableExternalTriggerOnNextChn
ftm_config_mode_t ftmMode
ftm_second_channel_polarity_t secondChannelPolarity
const ftm_independent_ch_param_t * pwmIndependentChannelConfig
static uint16_t FTM_DRV_GetMod(const FTM_Type *ftmBase)
Returns the FTM peripheral counter modulo value.
status_t FTM_DRV_UpdatePwmChannel(uint32_t instance, uint8_t channel, ftm_pwm_update_option_t typeOfUpdate, uint16_t firstEdge, uint16_t secondEdge, bool softwareTrigger)
This function updates the waveform output in PWM mode (duty cycle and phase).
ftm_pwm_update_option_t
FlexTimer Configure type of PWM update in the duty cycle or in ticks.
static bool FTM_DRV_GetDetectedFaultInput(const FTM_Type *ftmBase)
Gets the FTM detected fault input.
bool enableExternalTrigger
status_t FTM_DRV_InitPwm(uint32_t instance, const ftm_pwm_param_t *param)
Configures the duty cycle and frequency and starts outputting the PWM on all channels configured in p...
#define FTM_SYNC_SWSYNC_MASK
bool enableModifiedCombine