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S32 SDK
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Go to the source code of this file.
Data Structures | |
struct | sbc_wtdog_ctr_t |
Watchdog control register structure. Watchdog configuration structure. More... | |
struct | sbc_sbc_t |
SBC configuration control register structure. Two operating modes have a major impact on the operation of the watchdog: Forced Normal mode and Software Development mode (Software Development mode is provided for test and development purposes only and is not a dedicated SBC operating mode; the UJA1169 can be in any functional operating mode with Software Development mode enabled). These modes are enabled and disabled via bits FNMC and SDMC respectively in the SBC configuration control register. Note that this register is located in the non-volatile memory area. The watchdog is disabled in Forced Normal mode (FNM). In Software Development mode (SDM), the watchdog can be disabled or activated for test and software debugging purposes. More... | |
struct | sbc_start_up_t |
Start-up control register structure. This structure contains settings of RSTN output reset pulse width and V2/VEXT start-up control. More... | |
struct | sbc_regulator_t |
Regulator control register structure. This structure set power distribution control, V2/VEXT configuration, set V1 reset threshold. More... | |
struct | sbc_supply_evnt_t |
Supply event capture enable register structure. This structure enables or disables detection of V2/VEXT overvoltage, undervoltage and V1 undervoltage enable. More... | |
struct | sbc_sys_evnt_t |
System event capture enable register structure. This structure enables or disables overtemperature warning, SPI failure enable. More... | |
struct | sbc_can_ctr_t |
CAN control register structure. This structure configure CAN peripheral behavior. More... | |
struct | sbc_trans_evnt_t |
Transceiver event capture enable register structure. Can bus silence, Can failure and Can wake-up settings. More... | |
struct | sbc_frame_t |
Frame control register structure. The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via bit IDE in the Frame control register. More... | |
struct | sbc_can_conf_t |
CAN configuration group structure. This structure configure CAN peripheral behavior. More... | |
struct | sbc_wake_t |
WAKE pin event capture enable register structure. Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register. A wake-up event is triggered by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that do not use the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND. More... | |
struct | sbc_regulator_ctr_t |
Regulator control register group. This structure is group of regulator settings. More... | |
struct | sbc_int_config_t |
Init configuration structure. This structure is used for initialization of sbc. More... | |
struct | sbc_factories_conf_t |
Factory configuration structure. It contains Start-up control register and SBC configuration control register. This is non-volatile memory with limited write access. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP; Bit NVMPS in the MTPNV status register indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow; performing a factory reset also increments the counter). This counter is provided for information purposes only; reprogramming will not be rejected when it reaches its maximum value. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: pin RSTN is held LOW, CANH is pulled up to VBAT, CANL is pulled down to GND After the factory preset values have been restored, the SBC performs a system reset and enters Forced normal Mode. Since the CAN-bus is clamped dominant, pin RXDC is forced LOW. Pin RXD is forced HIGH during the factory preset restore process (td(MTPNV)). A falling edge on RXD caused by bit PO being set after power-on indicates that the factory preset process has been completed. Note that the write counter, WRCNTS, in the MTPNV status register is incremented every time the factory presets are restored. More... | |
struct | sbc_main_status_t |
Main status register structure. The Main status register can be accessed to monitor the status of the overtemperature warning flag and to determine whether the UJA1169 has entered Normal mode after initial power-up. It also indicates the source of the most recent reset event. More... | |
struct | sbc_wtdog_status_t |
Watchdog status register structure. Information on the status of the watchdog is available from the Watchdog status register. This register also indicates whether Forced Normal and Software Development modes are active. More... | |
struct | sbc_supply_status_t |
Supply voltage status register structure. V2/VEXT and V1 undervoltage and overvoltage status. More... | |
struct | sbc_trans_stat_t |
Transceiver status register structure. There are stored CAN transceiver statuses. More... | |
struct | sbc_gl_evnt_stat_t |
Global event status register. The microcontroller can monitor events via the event status registers. An extra status register, the Global event status register, is provided to help speed up software polling routines. By polling the Global event status register, the microcontroller can quickly determine the type of event captured (system, supply, transceiver or WAKE pin) and then query the relevant event status register. More... | |
struct | sbc_sys_evnt_stat_t |
System event status register. Wake-up and interrupt event diagnosis in the UJA1169 is intended to provide the microcontroller with information on the status of a range of features and functions. This information is stored in the event status registers and is signaled on pin RXD, if enabled. More... | |
struct | sbc_sup_evnt_stat_t |
Supply event status register. More... | |
struct | sbc_trans_evnt_stat_t |
Transceiver event status register. More... | |
struct | sbc_wake_evnt_stat_t |
WAKE pin event status register. More... | |
struct | sbc_evn_capt_t |
Event capture registers structure. This structure contains Global event status, System event status, Supply event status, Transceiver event status, WAKE pin event status. More... | |
struct | sbc_mtpnv_stat_t |
MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP). Bit NVMPS in the MTPNV status register indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow; performing a factory reset also increments the counter). This counter is provided for information purposes only; reprogramming will not be rejected when it reaches its maximum value. More... | |
struct | sbc_status_group_t |
Status group structure. All statuses of SBC are stored in this structure. More... | |
Macros | |
#define | SBC_UJA_TIMEOUT 1000U |
#define | SBC_UJA_COUNT_ID_REG 4U |
#define | SBC_UJA_COUNT_MASK 4U |
#define | SBC_UJA_COUNT_DMASK 8U |
Typedefs | |
typedef uint8_t | sbc_fail_safe_rcc_t |
Fail-safe control register, reset counter control (0x02). incremented every time the SBC enters Reset mode while FNMC = 0; RCC overflows from 11 to 00; default at power-on is 00. More... | |
typedef uint8_t | sbc_identifier_t |
ID registers, identifier format (0x27 to 0x2A). A valid WUF identifier is defined and stored in the ID registers. An ID mask can be defined to allow a group of identifiers to be recognized as valid by an individual node. More... | |
typedef uint8_t | sbc_identif_mask_t |
ID mask registers (0x2B to 0x2E). The identifier mask is defined in the ID mask registers, where a 1 means dont care. More... | |
typedef uint8_t | sbc_frame_ctr_dlc_t |
Frame control register, number of data bytes expected in a CAN frame (0x2F). More... | |
typedef uint8_t | sbc_data_mask_t |
Data mask registers. The data field indicates the nodes to be woken up. Within the data field, groups of nodes can be predefined and associated with bits in a data mask. By comparing the incoming data field with the data mask, multiple groups of nodes can be woken up simultaneously with a single wake-up message. More... | |
typedef uint8_t | sbc_mtpnv_stat_wrcnts_t |
MTPNV status register, write counter status (0x70). 6-bits - contains the number of times the MTPNV cells were reprogrammed. More... | |
Enumerations | |
enum | sbc_register_t { SBC_UJA_WTDOG_CTR = 0x00U, SBC_UJA_MODE = 0x01U, SBC_UJA_FAIL_SAFE = 0x02U, SBC_UJA_MAIN = 0x03U, SBC_UJA_SYSTEM_EVNT = 0x04U, SBC_UJA_WTDOG_STAT = 0x05U, SBC_UJA_MEMORY_0 = 0x06U, SBC_UJA_MEMORY_1 = 0x07U, SBC_UJA_MEMORY_2 = 0x08U, SBC_UJA_MEMORY_3 = 0x09U, SBC_UJA_LOCK = 0x0AU, SBC_UJA_REGULATOR = 0x10U, SBC_UJA_SUPPLY_STAT = 0x1BU, SBC_UJA_SUPPLY_EVNT = 0x1CU, SBC_UJA_CAN = 0x20U, SBC_UJA_TRANS_STAT = 0x22U, SBC_UJA_TRANS_EVNT = 0x23U, SBC_UJA_DAT_RATE = 0x26U, SBC_UJA_IDENTIF_0 = 0x27U, SBC_UJA_IDENTIF_1 = 0x28U, SBC_UJA_IDENTIF_2 = 0x29U, SBC_UJA_IDENTIF_3 = 0x2AU, SBC_UJA_MASK_0 = 0x2BU, SBC_UJA_MASK_1 = 0x2CU, SBC_UJA_MASK_2 = 0x2DU, SBC_UJA_MASK_3 = 0x2EU, SBC_UJA_FRAME_CTR = 0x2FU, SBC_UJA_DAT_MASK_0 = 0x68U, SBC_UJA_DAT_MASK_1 = 0x69U, SBC_UJA_DAT_MASK_2 = 0x6AU, SBC_UJA_DAT_MASK_3 = 0x6BU, SBC_UJA_DAT_MASK_4 = 0x6CU, SBC_UJA_DAT_MASK_5 = 0x6DU, SBC_UJA_DAT_MASK_6 = 0x6EU, SBC_UJA_DAT_MASK_7 = 0x6FU, SBC_UJA_WAKE_STAT = 0x4BU, SBC_UJA_WAKE_EN = 0x4CU, SBC_UJA_GL_EVNT_STAT = 0x60U, SBC_UJA_SYS_EVNT_STAT = 0x61U, SBC_UJA_SUP_EVNT_STAT = 0x62U, SBC_UJA_TRANS_EVNT_STAT = 0x63U, SBC_UJA_WAKE_EVNT_STAT = 0x64U, SBC_UJA_MTPNV_STAT = 0x70U, SBC_UJA_START_UP = 0x73U, SBC_UJA_SBC = 0x74U, SBC_UJA_MTPNV_CRC = 0x75U, SBC_UJA_IDENTIF = 0x7EU } |
Register map. More... | |
enum | sbc_wtdog_ctr_wmc_t { SBC_UJA_WTDOG_CTR_WMC_AUTO = SBC_UJA_WTDOG_CTR_WMC_F(1U), SBC_UJA_WTDOG_CTR_WMC_TIME = SBC_UJA_WTDOG_CTR_WMC_F(2U), SBC_UJA_WTDOG_CTR_WMC_WIND = SBC_UJA_WTDOG_CTR_WMC_F(4U) } |
Watchdog control register, watchdog mode control (0x00). The UJA1169 contains a watchdog that supports three operating modes: Window, Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a watchdog trigger event within a defined watchdog window triggers and resets the watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered and reset at any time within the watchdog period by a watchdog trigger. Watchdog time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous mode, the watchdog can be off or autonomously in Timeout mode, depending on the selected SBC mode. The watchdog mode is selected via bits WMC in the Watchdog control register. The SBC must be in Standby mode when the watchdog mode is changed. More... | |
enum | sbc_wtdog_ctr_nwp_t { SBC_UJA_WTDOG_CTR_NWP_8 = 0x08U, SBC_UJA_WTDOG_CTR_NWP_16 = 0x01U, SBC_UJA_WTDOG_CTR_NWP_32 = 0x02U, SBC_UJA_WTDOG_CTR_NWP_64 = 0x0BU, SBC_UJA_WTDOG_CTR_NWP_128 = 0x04U, SBC_UJA_WTDOG_CTR_NWP_256 = 0x0DU, SBC_UJA_WTDOG_CTR_NWP_1024 = 0x0EU, SBC_UJA_WTDOG_CTR_NWP_4096 = 0x07U } |
Watchdog control register, nominal watchdog period (0x00). Eight watchdog periods are supported, from 8 ms to 4096 ms. The watchdog period is programmed via bits NWP. The selected period is valid for both Window and Timeout modes. The default watchdog period is 128 ms. A watchdog trigger event resets the watchdog timer. A watchdog trigger event is any valid write access to the Watchdog control register. If the watchdog mode or the watchdog period have changed as a result of the write access, the new values are immediately valid. More... | |
enum | sbc_mode_mc_t { SBC_UJA_MODE_MC_SLEEP = 0x01U, SBC_UJA_MODE_MC_STANDBY = 0x04U, SBC_UJA_MODE_MC_NORMAL = 0x07U } |
Mode control register, mode control (0x01) More... | |
enum | sbc_fail_safe_lhc_t { SBC_UJA_FAIL_SAFE_LHC_FLOAT = SBC_UJA_FAIL_SAFE_LHC_F(0U), SBC_UJA_FAIL_SAFE_LHC_LOW = SBC_UJA_FAIL_SAFE_LHC_F(1U) } |
Fail-safe control register, LIMP home control (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register. More... | |
enum | sbc_main_otws_t { SBC_UJA_MAIN_OTWS_BELOW = SBC_UJA_MAIN_OTWS_F(0U), SBC_UJA_MAIN_OTWS_ABOVE = SBC_UJA_MAIN_OTWS_F(1U) } |
Main status register, Overtemperature warning status (0x03). More... | |
enum | sbc_main_nms_t { SBC_UJA_MAIN_NMS_NORMAL = SBC_UJA_MAIN_NMS_F(0U), SBC_UJA_MAIN_NMS_PWR_UP = SBC_UJA_MAIN_NMS_F(1U) } |
Main status register, normal mode status (0x03). More... | |
enum | sbc_main_rss_t { SBC_UJA_MAIN_RSS_OFF_MODE = 0x00U, SBC_UJA_MAIN_RSS_CAN_WAKEUP = 0x01U, SBC_UJA_MAIN_RSS_SLP_WAKEUP = 0x04U, SBC_UJA_MAIN_RSS_OVF_SLP = 0x0CU, SBC_UJA_MAIN_RSS_DIAG_WAKEUP = 0x0DU, SBC_UJA_MAIN_RSS_WATCH_TRIG = 0x0EU, SBC_UJA_MAIN_RSS_WATCH_OVF = 0x0FU, SBC_UJA_MAIN_RSS_ILLEG_WATCH = 0x10U, SBC_UJA_MAIN_RSS_RSTN_PULDW = 0x11U, SBC_UJA_MAIN_RSS_LFT_OVERTM = 0x12U, SBC_UJA_MAIN_RSS_V1_UNDERV = 0x13U, SBC_UJA_MAIN_RSS_ILLEG_SLP = 0x14U, SBC_UJA_MAIN_RSS_WAKE_SLP = 0x16U } |
Main status register, Reset source status (0x03). More... | |
enum | sbc_sys_evnt_otwe_t { SBC_UJA_SYS_EVNT_OTWE_DIS = SBC_UJA_SYS_EVNT_OTWE_F(0U), SBC_UJA_SYS_EVNT_OTWE_EN = SBC_UJA_SYS_EVNT_OTWE_F(1U) } |
System event capture enable, overtemperature warning enable (0x04). More... | |
enum | sbc_sys_evnt_spife_t { SBC_UJA_SYS_EVNT_SPIFE_DIS = SBC_UJA_SYS_EVNT_SPIFE_F(0U), SBC_UJA_SYS_EVNT_SPIFE_EN = SBC_UJA_SYS_EVNT_SPIFE_F(1U) } |
System event capture enable, SPI failure enable (0x04). More... | |
enum | sbc_wtdog_stat_fnms_t { SBC_UJA_WTDOG_STAT_FNMS_N_NORMAL = SBC_UJA_WTDOG_STAT_FNMS_F(0U), SBC_UJA_WTDOG_STAT_FNMS_NORMAL = SBC_UJA_WTDOG_STAT_FNMS_F(1U) } |
Watchdog status register, forced Normal mode status (0x05). More... | |
enum | sbc_wtdog_stat_sdms_t { SBC_UJA_WTDOG_STAT_SDMS_N_NORMAL = SBC_UJA_WTDOG_STAT_SDMS_F(0U), SBC_UJA_WTDOG_STAT_SDMS_NORMAL = SBC_UJA_WTDOG_STAT_SDMS_F(1U) } |
Watchdog status register, Software Development mode status (0x05). More... | |
enum | sbc_wtdog_stat_wds_t { SBC_UJA_WTDOG_STAT_WDS_OFF = SBC_UJA_WTDOG_STAT_WDS_F(0U), SBC_UJA_WTDOG_STAT_WDS_FIH = SBC_UJA_WTDOG_STAT_WDS_F(1U), SBC_UJA_WTDOG_STAT_WDS_SEH = SBC_UJA_WTDOG_STAT_WDS_F(2U) } |
Watchdog status register, watchdog status (0x05). More... | |
enum | sbc_lock_t { LK0C = SBC_UJA_LOCK_LK0C_MASK, LK1C = SBC_UJA_LOCK_LK1C_MASK, LK2C = SBC_UJA_LOCK_LK2C_MASK, LK3C = SBC_UJA_LOCK_LK3C_MASK, LK4C = SBC_UJA_LOCK_LK4C_MASK, LK5C = SBC_UJA_LOCK_LK5C_MASK, LK6C = SBC_UJA_LOCK_LK6C_MASK, LKAC = SBC_UJA_LOCK_LKNC_MASK } |
Lock control(0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc. More... | |
enum | sbc_regulator_pdc_t { SBC_UJA_REGULATOR_PDC_HV = SBC_UJA_REGULATOR_PDC_F(0U), SBC_UJA_REGULATOR_PDC_LV = SBC_UJA_REGULATOR_PDC_F(1U) } |
Regulator control register, power distribution control (0x10). More... | |
enum | sbc_regulator_v2c_t { SBC_UJA_REGULATOR_V2C_OFF = SBC_UJA_REGULATOR_V2C_F(0U), SBC_UJA_REGULATOR_V2C_N = SBC_UJA_REGULATOR_V2C_F(1U), SBC_UJA_REGULATOR_V2C_N_S_R = SBC_UJA_REGULATOR_V2C_F(2U), SBC_UJA_REGULATOR_V2C_N_S_S_R = SBC_UJA_REGULATOR_V2C_F(3U) } |
Regulator control register, V2/VEXT configuration (0x10). More... | |
enum | sbc_regulator_v1rtc_t { SBC_UJA_REGULATOR_V1RTC_90 = SBC_UJA_REGULATOR_V1RTC_F(0U), SBC_UJA_REGULATOR_V1RTC_80 = SBC_UJA_REGULATOR_V1RTC_F(1U), SBC_UJA_REGULATOR_V1RTC_70 = SBC_UJA_REGULATOR_V1RTC_F(2U), SBC_UJA_REGULATOR_V1RTC_60 = SBC_UJA_REGULATOR_V1RTC_F(3U) } |
Regulator control register, set V1 reset threshold (0x10). More... | |
enum | sbc_supply_stat_v2s_t { SBC_UJA_SUPPLY_STAT_V2S_VOK = SBC_UJA_SUPPLY_STAT_V2S_F(0U), SBC_UJA_SUPPLY_STAT_V2S_VBE = SBC_UJA_SUPPLY_STAT_V2S_F(1U), SBC_UJA_SUPPLY_STAT_V2S_VAB = SBC_UJA_SUPPLY_STAT_V2S_F(2U), SBC_UJA_SUPPLY_STAT_V2S_DIS = SBC_UJA_SUPPLY_STAT_V2S_F(3U) } |
Supply voltage status register, V2/VEXT status (0x1B). More... | |
enum | sbc_supply_stat_v1s_t { SBC_UJA_SUPPLY_STAT_V1S_VAB = SBC_UJA_SUPPLY_STAT_V1S_F(0U), SBC_UJA_SUPPLY_STAT_V1S_VBE = SBC_UJA_SUPPLY_STAT_V1S_F(1U) } |
Supply voltage status register, V1 status (0x1B). More... | |
enum | sbc_supply_evnt_v2oe_t { SBC_UJA_SUPPLY_EVNT_V2OE_DIS = SBC_UJA_SUPPLY_EVNT_V2OE_F(0U), SBC_UJA_SUPPLY_EVNT_V2OE_EN = SBC_UJA_SUPPLY_EVNT_V2OE_F(1U) } |
Supply event capture enable register, V2/VEXT overvoltage enable (0x1C). More... | |
enum | sbc_supply_evnt_v2ue_t { SBC_UJA_SUPPLY_EVNT_V2UE_DIS = SBC_UJA_SUPPLY_EVNT_V2UE_F(0U), SBC_UJA_SUPPLY_EVNT_V2UE_EN = SBC_UJA_SUPPLY_EVNT_V2UE_F(1U) } |
Supply event capture enable register, V2/VEXT undervoltage enable (0x1C). More... | |
enum | sbc_supply_evnt_v1ue_t { SBC_UJA_SUPPLY_EVNT_V1UE_DIS = SBC_UJA_SUPPLY_EVNT_V1UE_F(0U), SBC_UJA_SUPPLY_EVNT_V1UE_EN = SBC_UJA_SUPPLY_EVNT_V1UE_F(1U) } |
Supply event capture enable register, V1 undervoltage enable (0x1C). More... | |
enum | sbc_can_cfdc_t { SBC_UJA_CAN_CFDC_DIS = SBC_UJA_CAN_CFDC_F(0U), SBC_UJA_CAN_CFDC_EN = SBC_UJA_CAN_CFDC_F(1U) } |
CAN control register, CAN FD control (0x20). More... | |
enum | sbc_can_pncok_t { SBC_UJA_CAN_PNCOK_DIS = SBC_UJA_CAN_PNCOK_F(0U), SBC_UJA_CAN_PNCOK_EN = SBC_UJA_CAN_PNCOK_F(1U) } |
CAN control register, CAN partial networking configuration OK (0x20). More... | |
enum | sbc_can_cpnc_t { SBC_UJA_CAN_CPNC_DIS = SBC_UJA_CAN_CPNC_F(0U), SBC_UJA_CAN_CPNC_EN = SBC_UJA_CAN_CPNC_F(1U) } |
CAN control register, CAN partial networking control (0x20). More... | |
enum | sbc_can_cmc_t { SBC_UJA_CAN_CMC_OFMODE = SBC_UJA_CAN_CMC_F(0U), SBC_UJA_CAN_CMC_ACMODE_DA = SBC_UJA_CAN_CMC_F(1U), SBC_UJA_CAN_CMC_ACMODE_DD = SBC_UJA_CAN_CMC_F(2U), SBC_UJA_CAN_CMC_LISTEN = SBC_UJA_CAN_CMC_F(3U) } |
CAN control register, CAN mode control (0x20). More... | |
enum | sbc_trans_stat_cts_t { SBC_UJA_TRANS_STAT_CTS_INACT = SBC_UJA_TRANS_STAT_CTS_F(0U), SBC_UJA_TRANS_STAT_CTS_ACT = SBC_UJA_TRANS_STAT_CTS_F(1U) } |
Transceiver status register, CAN transceiver status (0x22). More... | |
enum | sbc_trans_stat_cpnerr_t { SBC_UJA_TRANS_STAT_CPNERR_NO_DET = SBC_UJA_TRANS_STAT_CPNERR_F(0U), SBC_UJA_TRANS_STAT_CPNERR_DET = SBC_UJA_TRANS_STAT_CPNERR_F(1U) } |
Transceiver status register, CAN partial networking error (0x22). More... | |
enum | sbc_trans_stat_cpns_t { SBC_UJA_TRANS_STAT_CPNS_ERR = SBC_UJA_TRANS_STAT_CPNS_F(0U), SBC_UJA_TRANS_STAT_CPNS_OK = SBC_UJA_TRANS_STAT_CPNS_F(1U) } |
Transceiver status register, CAN partial networking status (0x22). More... | |
enum | sbc_trans_stat_coscs_t { SBC_UJA_TRANS_STAT_COSCS_NRUN = SBC_UJA_TRANS_STAT_COSCS_F(0U), SBC_UJA_TRANS_STAT_COSCS_RUN = SBC_UJA_TRANS_STAT_COSCS_F(1U) } |
Transceiver status register, CAN oscillator status (0x22). More... | |
enum | sbc_trans_stat_cbss_t { SBC_UJA_TRANS_STAT_CBSS_ACT = SBC_UJA_TRANS_STAT_CBSS_F(0U), SBC_UJA_TRANS_STAT_CBSS_INACT = SBC_UJA_TRANS_STAT_CBSS_F(1U) } |
Transceiver status register, CAN-bus silence status (0x22). More... | |
enum | sbc_trans_stat_vcs_t { SBC_UJA_TRANS_STAT_VCS_AB = SBC_UJA_TRANS_STAT_VCS_F(0U), SBC_UJA_TRANS_STAT_VCS_BE = SBC_UJA_TRANS_STAT_VCS_F(1U) } |
Transceiver status register, VCAN status (0x22). More... | |
enum | sbc_trans_stat_cfs_t { SBC_UJA_TRANS_STAT_CFS_NO_TXD = SBC_UJA_TRANS_STAT_CFS_F(0U), SBC_UJA_TRANS_STAT_CFS_TXD = SBC_UJA_TRANS_STAT_CFS_F(1U) } |
Transceiver status register, CAN failure status (0x22). More... | |
enum | sbc_trans_evnt_cbse_t { SBC_UJA_TRANS_EVNT_CBSE_DIS = SBC_UJA_TRANS_EVNT_CBSE_F(0U), SBC_UJA_TRANS_EVNT_CBSE_EN = SBC_UJA_TRANS_EVNT_CBSE_F(1U) } |
Transceiver event capture enable register, CAN-bus silence enable (0x23). More... | |
enum | sbc_trans_evnt_cfe_t { SBC_UJA_TRANS_EVNT_CFE_DIS = SBC_UJA_TRANS_EVNT_CFE_F(0U), SBC_UJA_TRANS_EVNT_CFE_EN = SBC_UJA_TRANS_EVNT_CFE_F(1U) } |
Transceiver event capture enable register, CAN failure enable (0x23). More... | |
enum | sbc_trans_evnt_cwe_t { SBC_UJA_TRANS_EVNT_CWE_DIS = SBC_UJA_TRANS_EVNT_CWE_F(0U), SBC_UJA_TRANS_EVNT_CWE_EN = SBC_UJA_TRANS_EVNT_CWE_F(1U) } |
Transceiver event capture enable register, CAN wake-up enable (0x23). More... | |
enum | sbc_dat_rate_t { SBC_UJA_DAT_RATE_CDR_50KB = SBC_UJA_DAT_RATE_CDR_F(0U), SBC_UJA_DAT_RATE_CDR_100KB = SBC_UJA_DAT_RATE_CDR_F(1U), SBC_UJA_DAT_RATE_CDR_125KB = SBC_UJA_DAT_RATE_CDR_F(2U), SBC_UJA_DAT_RATE_CDR_250KB = SBC_UJA_DAT_RATE_CDR_F(3U), SBC_UJA_DAT_RATE_CDR_500KB = SBC_UJA_DAT_RATE_CDR_F(5U), SBC_UJA_DAT_RATE_CDR_1000KB = SBC_UJA_DAT_RATE_CDR_F(7U) } |
Data rate register, CAN data rate selection (0x26). CAN partial networking configuration registers. Dedicated registers are provided for configuring CAN partial networking. More... | |
enum | sbc_frame_ctr_ide_t { SBC_UJA_FRAME_CTR_IDE_11B = SBC_UJA_FRAME_CTR_IDE_F(0U), SBC_UJA_FRAME_CTR_IDE_29B = SBC_UJA_FRAME_CTR_IDE_F(1U) } |
Frame control register, identifier format (0x2F). The wake-up frame format, standard (11-bit) or extended (29-bit) identifier, is selected via bit IDE in the Frame control register. More... | |
enum | sbc_frame_ctr_pndm_t { SBC_UJA_FRAME_CTR_PNDM_DCARE = SBC_UJA_FRAME_CTR_PNDM_F(0U), SBC_UJA_FRAME_CTR_PNDM_EVAL = SBC_UJA_FRAME_CTR_PNDM_F(1U) } |
Frame control register, partial networking data mask (0x2F). More... | |
enum | sbc_wake_stat_wpvs_t { SBC_UJA_WAKE_STAT_WPVS_BE = SBC_UJA_WAKE_STAT_WPVS_F(0U), SBC_UJA_WAKE_STAT_WPVS_AB = SBC_UJA_WAKE_STAT_WPVS_F(1U) } |
WAKE pin status register, WAKE pin status (0x4B). More... | |
enum | sbc_wake_en_wpre_t { SBC_UJA_WAKE_EN_WPRE_DIS = SBC_UJA_WAKE_EN_WPRE_F(0U), SBC_UJA_WAKE_EN_WPRE_EN = SBC_UJA_WAKE_EN_WPRE_F(1U) } |
WAKE pin event capture enable register, WAKE pin rising-edge enable (0x4C). More... | |
enum | sbc_wake_en_wpfe_t { SBC_UJA_WAKE_EN_WPFE_DIS = SBC_UJA_WAKE_EN_WPFE_F(0U), SBC_UJA_WAKE_EN_WPFE_EN = SBC_UJA_WAKE_EN_WPFE_F(1U) } |
WAKE pin event capture enable register, WAKE pin falling-edge enable (0x4C). More... | |
enum | sbc_gl_evnt_stat_wpe_t { SBC_UJA_GL_EVNT_STAT_WPE_NO = SBC_UJA_GL_EVNT_STAT_WPE_F(0U), SBC_UJA_GL_EVNT_STAT_WPE = SBC_UJA_GL_EVNT_STAT_WPE_F(1U) } |
Global event status register, WAKE pin event (0x60). More... | |
enum | sbc_gl_evnt_stat_trxe_t { SBC_UJA_GL_EVNT_STAT_TRXE_NO = SBC_UJA_GL_EVNT_STAT_TRXE_F(0U), SBC_UJA_GL_EVNT_STAT_TRXE = SBC_UJA_GL_EVNT_STAT_TRXE_F(1U) } |
Global event status register, transceiver event (0x60). More... | |
enum | sbc_gl_evnt_stat_supe_t { SBC_UJA_GL_EVNT_STAT_SUPE_NO = SBC_UJA_GL_EVNT_STAT_SUPE_F(0U), SBC_UJA_GL_EVNT_STAT_SUPE = SBC_UJA_GL_EVNT_STAT_SUPE_F(1U) } |
Global event status register, supply event (0x60). More... | |
enum | sbc_gl_evnt_stat_syse_t { SBC_UJA_GL_EVNT_STAT_SYSE_NO = SBC_UJA_GL_EVNT_STAT_SYSE_F(0U), SBC_UJA_GL_EVNT_STAT_SYSE = SBC_UJA_GL_EVNT_STAT_SYSE_F(1U) } |
Global event status register, system event (0x60). More... | |
enum | sbc_sys_evnt_stat_po_t { SBC_UJA_SYS_EVNT_STAT_PO_NO = SBC_UJA_SYS_EVNT_STAT_PO_F(0U), SBC_UJA_SYS_EVNT_STAT_PO = SBC_UJA_SYS_EVNT_STAT_PO_F(1U) } |
System event status register, power-on (0x61). More... | |
enum | sbc_sys_evnt_stat_otw_t { SBC_UJA_SYS_EVNT_STAT_OTW_NO = SBC_UJA_SYS_EVNT_STAT_OTW_F(0U), SBC_UJA_SYS_EVNT_STAT_OTW = SBC_UJA_SYS_EVNT_STAT_OTW_F(1U) } |
System event status register, overtemperature warning (0x61). More... | |
enum | sbc_sys_evnt_stat_spif_t { SBC_UJA_SYS_EVNT_STAT_SPIF_NO = SBC_UJA_SYS_EVNT_STAT_SPIF_F(0U), SBC_UJA_SYS_EVNT_STAT_SPIF = SBC_UJA_SYS_EVNT_STAT_SPIF_F(1U) } |
System event status register, SPI failure (0x61). More... | |
enum | sbc_sys_evnt_stat_wdf_t { SBC_UJA_SYS_EVNT_STAT_WDF_NO = SBC_UJA_SYS_EVNT_STAT_WDF_F(0U), SBC_UJA_SYS_EVNT_STAT_WDF = SBC_UJA_SYS_EVNT_STAT_WDF_F(1U) } |
System event status register, watchdog failure (0x61). More... | |
enum | sbc_sup_evnt_stat_v2o_t { SBC_UJA_SUP_EVNT_STAT_V2O_NO = SBC_UJA_SUP_EVNT_STAT_V2O_F(0U), SBC_UJA_SUP_EVNT_STAT_V2O = SBC_UJA_SUP_EVNT_STAT_V2O_F(1U) } |
Supply event status register, V2/VEXT overvoltage (0x62). More... | |
enum | sbc_sup_evnt_stat_v2u_t { SBC_UJA_SUP_EVNT_STAT_V2U_NO = SBC_UJA_SUP_EVNT_STAT_V2U_F(0U), SBC_UJA_SUP_EVNT_STAT_V2U = SBC_UJA_SUP_EVNT_STAT_V2U_F(1U) } |
Supply event status register, V2/VEXT undervoltage (0x62). More... | |
enum | sbc_sup_evnt_stat_v1u_t { SBC_UJA_SUP_EVNT_STAT_V1U_NO = SBC_UJA_SUP_EVNT_STAT_V1U_F(0U), SBC_UJA_SUP_EVNT_STAT_V1U = SBC_UJA_SUP_EVNT_STAT_V1U_F(1U) } |
Supply event status register, V1 undervoltage (0x62). More... | |
enum | sbc_trans_evnt_stat_pnfde_t { SBC_UJA_TRANS_EVNT_STAT_PNFDE_NO = SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(0U), SBC_UJA_TRANS_EVNT_STAT_PNFDE = SBC_UJA_TRANS_EVNT_STAT_PNFDE_F(1U) } |
Transceiver event status register,partial networking frame detection error (0x63). More... | |
enum | sbc_trans_evnt_stat_cbs_t { SBC_UJA_TRANS_EVNT_STAT_CBS_NO = SBC_UJA_TRANS_EVNT_STAT_CBS_F(0U), SBC_UJA_TRANS_EVNT_STAT_CBS = SBC_UJA_TRANS_EVNT_STAT_CBS_F(1U) } |
Transceiver event status register, CAN-bus status (0x63). More... | |
enum | sbc_trans_evnt_stat_cf_t { SBC_UJA_TRANS_EVNT_STAT_CF_NO = SBC_UJA_TRANS_EVNT_STAT_CF_F(0U), SBC_UJA_TRANS_EVNT_STAT_CF = SBC_UJA_TRANS_EVNT_STAT_CF_F(1U) } |
Transceiver event status register, CAN failure (0x63). More... | |
enum | sbc_trans_evnt_stat_cw_t { SBC_UJA_TRANS_EVNT_STAT_CW_NO = SBC_UJA_TRANS_EVNT_STAT_CW_F(0U), SBC_UJA_TRANS_EVNT_STAT_CW = SBC_UJA_TRANS_EVNT_STAT_CW_F(1U) } |
Transceiver event status register, CAN wake-up (0x63). More... | |
enum | sbc_wake_evnt_stat_wpr_t { SBC_UJA_WAKE_EVNT_STAT_WPR_NO = SBC_UJA_WAKE_EVNT_STAT_WPR_F(0U), SBC_UJA_WAKE_EVNT_STAT_WPR = SBC_UJA_WAKE_EVNT_STAT_WPR_F(1U) } |
WAKE pin event status register, WAKE pin rising edge (0x64). More... | |
enum | sbc_wake_evnt_stat_wpf_t { SBC_UJA_WAKE_EVNT_STAT_WPF_NO = SBC_UJA_WAKE_EVNT_STAT_WPF_F(0U), SBC_UJA_WAKE_EVNT_STAT_WPF = SBC_UJA_WAKE_EVNT_STAT_WPF_F(1U) } |
WAKE pin event status register, WAKE pin falling edge (0x64). More... | |
enum | sbc_mtpnv_stat_eccs_t { SBC_UJA_MTPNV_STAT_ECCS_NO = SBC_UJA_MTPNV_STAT_ECCS_F(0U), SBC_UJA_MTPNV_STAT_ECCS = SBC_UJA_MTPNV_STAT_ECCS_F(1U) } |
MTPNV status register, error correction code status (0x70). More... | |
enum | sbc_mtpnv_stat_nvmps_t { SBC_UJA_MTPNV_STAT_NVMPS_NO = SBC_UJA_MTPNV_STAT_NVMPS_F(0U), SBC_UJA_MTPNV_STAT_NVMPS = SBC_UJA_MTPNV_STAT_NVMPS_F(1U) } |
MTPNV status register, non-volatile memory programming status (0x70). More... | |
enum | sbc_start_up_rlc_t { SBC_UJA_START_UP_RLC_20_25p0 = SBC_UJA_START_UP_RLC_F(0U), SBC_UJA_START_UP_RLC_10_12p5 = SBC_UJA_START_UP_RLC_F(1U), SBC_UJA_START_UP_RLC_03p6_05 = SBC_UJA_START_UP_RLC_F(2U), SBC_UJA_START_UP_RLC_01_01p5 = SBC_UJA_START_UP_RLC_F(3U) } |
Start-up control register, RSTN output reset pulse width macros (0x73). More... | |
enum | sbc_start_up_v2suc_t { SBC_UJA_START_UP_V2SUC_00 = SBC_UJA_START_UP_V2SUC_F(0U), SBC_UJA_START_UP_V2SUC_11 = SBC_UJA_START_UP_V2SUC_F(1U) } |
Start-up control register, V2/VEXT start-up control (0x73). More... | |
enum | sbc_sbc_v1rtsuc_t { SBC_UJA_SBC_V1RTSUC_90 = SBC_UJA_SBC_V1RTSUC_F(0U), SBC_UJA_SBC_V1RTSUC_80 = SBC_UJA_SBC_V1RTSUC_F(1U), SBC_UJA_SBC_V1RTSUC_70 = SBC_UJA_SBC_V1RTSUC_F(2U), SBC_UJA_SBC_V1RTSUC_60 = SBC_UJA_SBC_V1RTSUC_F(3U) } |
SBC configuration control register, V1 undervoltage threshold (defined by bit V1RTC) at start-up (0x74). More... | |
enum | sbc_sbc_fnmc_t { SBC_UJA_SBC_FNMC_DIS = SBC_UJA_SBC_FNMC_F(0U), SBC_UJA_SBC_FNMC_EN = SBC_UJA_SBC_FNMC_F(1U) } |
SBC configuration control register, Forced Normal mode control (0x74). More... | |
enum | sbc_sbc_sdmc_t { SBC_UJA_SBC_SDMC_DIS = SBC_UJA_SBC_SDMC_F(0U), SBC_UJA_SBC_SDMC_EN = SBC_UJA_SBC_SDMC_F(1U) } |
SBC configuration control register, Software Development mode control (0x74). More... | |
enum | sbc_sbc_slpc_t { SBC_UJA_SBC_SLPC_AC = SBC_UJA_SBC_SLPC_F(0U), SBC_UJA_SBC_SLPC_IG = SBC_UJA_SBC_SLPC_F(1U) } |
SBC configuration control register, Sleep control (0x74). More... | |
Functions | |
status_t | SBC_Init (const sbc_int_config_t *const config, const uint32_t lpspiInstance) |
This function initializes all registers. It waits 10ms and then writes to all registers. More... | |
status_t | SBC_SetVreg (const sbc_regulator_ctr_t *const regulatorCtr) |
This function configures Regulator control registers. More... | |
status_t | SBC_GetVreg (sbc_regulator_ctr_t *const regulatorCtr) |
This function reads Regulator control registers. More... | |
status_t | SBC_SetWatchdog (const sbc_wtdog_ctr_t *const wtdog) |
This function configures Watchdog control register (0x00). More... | |
status_t | SBC_GetWatchdog (sbc_wtdog_ctr_t *const wtdog) |
This function reads Watchdog control register (0x00). More... | |
status_t | SBC_SetMode (const sbc_mode_mc_t mode) |
This function writes to Mode control register. (0x01). More... | |
status_t | SBC_GetMode (sbc_mode_mc_t *const mode) |
This function reads Mode control register. (0x01). More... | |
status_t | SBC_SetFailSafe (const sbc_fail_safe_lhc_t lhc, const sbc_fail_safe_rcc_t *const rcc) |
This function writes to Fail-safe control register (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register. The limp-home function and the reset counter are disabled in Forced Normal mode. The LIMP pin is floating, RCC remains unchanged and bit LHC = 0. RCC -reset counter control. incremented every time the SBC enters Reset mode while FNMC = 0; RCC overflows from 11 to 00; default at power-on is 00. For ignore settings of rcc use NULL pointer or otherwise send pointer to variable. More... | |
status_t | SBC_GetFailSafe (sbc_fail_safe_lhc_t *const lhc, sbc_fail_safe_rcc_t *const rcc) |
This function reads from Fail-safe control register (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register. The limp-home function and the reset counter are disabled in Forced Normal mode. The LIMP pin is floating, RCC remains unchanged and bit LHC = 0. More... | |
status_t | SBC_SetSystemEvents (const sbc_sys_evnt_t *const sysEvnt) |
This function writes System event capture enable register (0x04). This function enables or disables overtemperature warning, SPI failure enable. More... | |
status_t | SBC_GetSystemEvents (sbc_sys_evnt_t *const sysEvnt) |
This function reads System event capture enable register (0x04). This function reads content of overtemperature warning and SPI failure settings. More... | |
status_t | SBC_SetLock (const sbc_lock_t lockMask) |
This function writes to Lock control register (0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc. For SPI write disable set lock bit to 1. This is mask for set lock control register. More... | |
status_t | SBC_GetLock (sbc_lock_t *const lockMask) |
This function reads Lock control register (0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc. For SPI write disable set lock bit to 1. This is mask for set lock control register. More... | |
status_t | SBC_SetCanConfig (const sbc_can_conf_t *const can) |
This function configures CAN peripheral behavior. This function configures CAN peripheral behavior. This function configures several registers which configure CAN. It contains CAN control register, Transceiver event capture enable register, CAN data rate selection, ID registers, ID mask registers, Frame control register, Data mask 0 - 7 configuration. More... | |
status_t | SBC_GetCanConfig (sbc_can_conf_t *const can) |
This function reads CAN peripheral settings. This function configures CAN peripheral behavior. This function configures several registers which configure CAN. It contains CAN control register, Transceiver event capture enable register, CAN data rate selection, ID registers, ID mask registers, Frame control register, Data mask 0 - 7 configuration. More... | |
status_t | SBC_SetWakePin (const sbc_wake_t *const wakePin) |
This function writes to WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register. A wake-up event is triggered by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that do not use the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND. More... | |
status_t | SBC_GetWakePin (sbc_wake_t *const wakePin) |
This function reads WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register. A wake-up event is triggered by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that do not use the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND. More... | |
status_t | SBC_GetMainStatus (sbc_main_status_t *const mainStatus) |
This function reads Main status register. This function will clear R/W registers automatically after reading. More... | |
status_t | SBC_GetWatchdogStatus (sbc_wtdog_status_t *const watchdogStatus) |
This function reads Watchdog status register. This function will clear R/W registers automatically after reading. More... | |
status_t | SBC_GetSupplyStatus (sbc_supply_status_t *const supStatus) |
This functions reads Supply voltage status register. This function clear R/W status after reading writing 0 to register. It contains V2/VEXT status and V1 status. More... | |
status_t | SBC_GetCanStatus (sbc_trans_stat_t *const transStatus) |
This functions reads Transceiver status register. It contains CAN transceiver status, CAN partial networking error, CAN partial networking status, CAN oscillator status, CAN-bus silence status, VCAN status, CAN failure status. More... | |
status_t | SBC_GetWakeStatus (sbc_wake_stat_wpvs_t *const wakeStatus) |
This functions reads WAKE pin status register. This function reads switching threshold of voltage on WAKE pin. More... | |
status_t | SBC_GetEventsStatus (sbc_evn_capt_t *const events) |
This functions reads Event capture registers. This function reads switching threshold of voltage on WAKE pin. This functions reads global events statuses: Global event status, System event status, Supply event status, Transceiver event status, WAKE pin event status. More... | |
status_t | SBC_CleanEvents (const sbc_evn_capt_t *const events) |
This function clears Event capture registers. It contains Global event status, System event status, Supply event status, Transceiver event status, WAKE pin event status. This function write 1 to bit which should be delete. After an event source has been identified, the status flag should be cleared (set to 0) by writing 1 to the relevant status bit (writing 0 will have no effect). Write true value to appropriate enumeration. More... | |
status_t | SBC_GetAllStatus (sbc_status_group_t *const status) |
This function reads all statuses from SBC device. It reads all status registers: Main status and Watchdog status, Supply voltage status, Transceiver status, WAKE pin status, Event capture registers. More... | |
status_t | SBC_GetMtpnvStatus (sbc_mtpnv_stat_t *const mtpnv) |
This function reads MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP). Bit NVMPS in the MTPNV status register indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow; performing a factory reset also increments the counter). This counter is provided for information purposes only; reprogramming will not be rejected when it reaches its maximum value. More... | |
status_t | SBC_GetFactoriesSettings (sbc_factories_conf_t *const factoriesConf) |
This function reads Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode. More... | |
status_t | SBC_ChangeFactoriesSettings (const sbc_factories_conf_t *const newConf) |
This function sets Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode. Note for default settings see sbc_factories_conf_t comment. If the device has been programmed previously, the factory presets may need to be restored before reprogramming can begin. When the factory presets have been restored successfully, a system reset is generated automatically and UJA1169 switches back to Forced Normal mode. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: -pin RSTN is held LOW -CANH is pulled up to VBAT -CANL is pulled down to GND. More... | |
status_t | SBC_DataTransfer (const sbc_register_t regName, const uint8_t *const sendData, uint8_t *const receiveData) |
This function sends data over LSPI to SBC device. This function sends 8 bites to SBC device register according device address which is selected. This transfer uses 16bit LSPI. CS polarity - active low, clock phase on second edge. Clock polarity active high. More... | |
void | SBC_FeedWatchdog (void) |
This function refreshes watchdog period by writing byte to the SBC watchdog register. This function must be called periodically according Watchdog mode control and Nominal watchdog period settings. Note: Unxpected behaviour can happend if watchdog mode is set to timeout period and watchdog is triggered exactly at 50% of period. Be sure you trigger watchdog before 50% or above 50% of watchdog period. More... | |
status_t SBC_ChangeFactoriesSettings | ( | const sbc_factories_conf_t *const | newConf | ) |
This function sets Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode. Note for default settings see sbc_factories_conf_t comment. If the device has been programmed previously, the factory presets may need to be restored before reprogramming can begin. When the factory presets have been restored successfully, a system reset is generated automatically and UJA1169 switches back to Forced Normal mode. Factory preset values are restored if the following conditions apply continuously for at least td(MTPNV) during battery power-up: -pin RSTN is held LOW -CANH is pulled up to VBAT -CANL is pulled down to GND.
newConf | value of this variable will be write to Start-up control register and SBC configuration control register. |
Definition at line 1584 of file sbc_uja1169_driver.c.
status_t SBC_CleanEvents | ( | const sbc_evn_capt_t *const | events | ) |
This function clears Event capture registers. It contains Global event status, System event status, Supply event status, Transceiver event status, WAKE pin event status. This function write 1 to bit which should be delete. After an event source has been identified, the status flag should be cleared (set to 0) by writing 1 to the relevant status bit (writing 0 will have no effect). Write true value to appropriate enumeration.
events | variable for clear Event capture registers, set status to 1 for clear appropriate status. |
Definition at line 1342 of file sbc_uja1169_driver.c.
status_t SBC_DataTransfer | ( | const sbc_register_t | regName, |
const uint8_t *const | sendData, | ||
uint8_t *const | receiveData | ||
) |
This function sends data over LSPI to SBC device. This function sends 8 bites to SBC device register according device address which is selected. This transfer uses 16bit LSPI. CS polarity - active low, clock phase on second edge. Clock polarity active high.
regName | this is register name for access. |
sendData | pointer of 8 bits variable which contains data for writing to register of SBC device. Use NULL pointer for data reading. |
receiveData | pointer of 8 bits variable which contains data for reading from SBC device. Use NULL pointer for data writing. |
Definition at line 1630 of file sbc_uja1169_driver.c.
void SBC_FeedWatchdog | ( | void | ) |
This function refreshes watchdog period by writing byte to the SBC watchdog register. This function must be called periodically according Watchdog mode control and Nominal watchdog period settings. Note: Unxpected behaviour can happend if watchdog mode is set to timeout period and watchdog is triggered exactly at 50% of period. Be sure you trigger watchdog before 50% or above 50% of watchdog period.
Definition at line 418 of file sbc_uja1169_driver.c.
status_t SBC_GetAllStatus | ( | sbc_status_group_t *const | status | ) |
This function reads all statuses from SBC device. It reads all status registers: Main status and Watchdog status, Supply voltage status, Transceiver status, WAKE pin status, Event capture registers.
status | variable for storing all status registers. |
Definition at line 1410 of file sbc_uja1169_driver.c.
status_t SBC_GetCanConfig | ( | sbc_can_conf_t *const | can | ) |
This function reads CAN peripheral settings. This function configures CAN peripheral behavior. This function configures several registers which configure CAN. It contains CAN control register, Transceiver event capture enable register, CAN data rate selection, ID registers, ID mask registers, Frame control register, Data mask 0 - 7 configuration.
can | reads CAN peripheral settings from SBC device. |
Definition at line 877 of file sbc_uja1169_driver.c.
status_t SBC_GetCanStatus | ( | sbc_trans_stat_t *const | transStatus | ) |
This functions reads Transceiver status register. It contains CAN transceiver status, CAN partial networking error, CAN partial networking status, CAN oscillator status, CAN-bus silence status, VCAN status, CAN failure status.
transStatus | variable for storing Transceiver status. |
Definition at line 1147 of file sbc_uja1169_driver.c.
status_t SBC_GetEventsStatus | ( | sbc_evn_capt_t *const | events | ) |
This functions reads Event capture registers. This function reads switching threshold of voltage on WAKE pin. This functions reads global events statuses: Global event status, System event status, Supply event status, Transceiver event status, WAKE pin event status.
events | variable for storing Event capture registers. |
Definition at line 1225 of file sbc_uja1169_driver.c.
status_t SBC_GetFactoriesSettings | ( | sbc_factories_conf_t *const | factoriesConf | ) |
This function reads Start-up control register and SBC configuration control register. It is non-volatile memory with limited write access. The UJA1169 contains Multiple Time Programmable Non-Volatile (MTPNV) memory cells that allow some of the default device settings to be reconfigured. The MTPNV memory address range is from 0x73 to 0x74. NXP delivers the UJA1169 in so-called Forced Normal mode, also referred to as the factory preset configuration. In order to change the default settings, the device must be in Forced Normal mode with FNMC = 1 and NVMPS = 1. In Forced Normal mode, the watchdog is disabled, all regulators are on and the CAN transceiver is in Active mode.
factoriesConf | variable for storing Start-up control register and SBC configuration control register. |
Definition at line 1514 of file sbc_uja1169_driver.c.
status_t SBC_GetFailSafe | ( | sbc_fail_safe_lhc_t *const | lhc, |
sbc_fail_safe_rcc_t *const | rcc | ||
) |
This function reads from Fail-safe control register (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register. The limp-home function and the reset counter are disabled in Forced Normal mode. The LIMP pin is floating, RCC remains unchanged and bit LHC = 0.
lhc | Variable for reading of limp home control. |
rcc | Pointer to rcc. Use null pointer or wrong value for ignore parameter or empty for reading. |
Definition at line 616 of file sbc_uja1169_driver.c.
status_t SBC_GetLock | ( | sbc_lock_t *const | lockMask | ) |
This function reads Lock control register (0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc. For SPI write disable set lock bit to 1. This is mask for set lock control register.
lockMask | reads CAN peripheral settings from SBC device. SBC device bytes. |
Definition at line 775 of file sbc_uja1169_driver.c.
status_t SBC_GetMainStatus | ( | sbc_main_status_t *const | mainStatus | ) |
This function reads Main status register. This function will clear R/W registers automatically after reading.
mainStatus | variable for storing Status. |
Definition at line 1025 of file sbc_uja1169_driver.c.
status_t SBC_GetMode | ( | sbc_mode_mc_t *const | mode | ) |
This function reads Mode control register. (0x01).
Normal mode is the active operating mode. In this mode, all the hardware on the device is available and can be activated. Voltage regulator V1 is enabled to supply the microcontroller. Standby mode is the first-level power-saving mode of the UJA1169, offering reduced current consumption. The transceiver is unable to transmit or receive data in Standby mode. The SPI remains enabled and V1 is still active; the watchdog is active (in Timeout mode) if enabled. The behavior of V2/VEXT is determined by the SPI setting. Sleep mode is the second-level power-saving mode of the UJA1169. The difference between Sleep and Standby modes is that V1 is off in Sleep mode and temperature protection is inactive. Note event status are cleared before device move to sleep mode.
mode | variable for store device mode - Normal, StandBy, Sleep. |
Definition at line 512 of file sbc_uja1169_driver.c.
status_t SBC_GetMtpnvStatus | ( | sbc_mtpnv_stat_t *const | mtpnv | ) |
This function reads MTPNV status register. The MTPNV cells can be reprogrammed a maximum of 200 times (Ncy(W)MTP). Bit NVMPS in the MTPNV status register indicates whether the non-volatile cells can be reprogrammed. This register also contains a write counter, WRCNTS, that is incremented each time the MTPNV cells are reprogrammed (up to a maximum value of 111111; there is no overflow; performing a factory reset also increments the counter). This counter is provided for information purposes only; reprogramming will not be rejected when it reaches its maximum value.
mtpnv | variable for storing MTPNV status registers. |
Definition at line 1466 of file sbc_uja1169_driver.c.
status_t SBC_GetSupplyStatus | ( | sbc_supply_status_t *const | supStatus | ) |
This functions reads Supply voltage status register. This function clear R/W status after reading writing 0 to register. It contains V2/VEXT status and V1 status.
supStatus | variable for storing Supply voltage status. |
Definition at line 1105 of file sbc_uja1169_driver.c.
status_t SBC_GetSystemEvents | ( | sbc_sys_evnt_t *const | sysEvnt | ) |
This function reads System event capture enable register (0x04). This function reads content of overtemperature warning and SPI failure settings.
sysEvnt | system event capture enable register structure for storing result from SBC device. |
Definition at line 698 of file sbc_uja1169_driver.c.
status_t SBC_GetVreg | ( | sbc_regulator_ctr_t *const | regulatorCtr | ) |
This function reads Regulator control registers.
Regulator control (0x10), Supply event enable(0x1C).
regulator | regulator registers structure where device data will be stored. |
Definition at line 237 of file sbc_uja1169_driver.c.
status_t SBC_GetWakePin | ( | sbc_wake_t *const | wakePin | ) |
This function reads WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register. A wake-up event is triggered by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that do not use the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND.
wakePin | reads configuration to WAKE pin event capture enable register of SBC device. |
Definition at line 987 of file sbc_uja1169_driver.c.
status_t SBC_GetWakeStatus | ( | sbc_wake_stat_wpvs_t *const | wakeStatus | ) |
This functions reads WAKE pin status register. This function reads switching threshold of voltage on WAKE pin.
wakeStatus | variable for storing WAKE pin status. |
Definition at line 1188 of file sbc_uja1169_driver.c.
status_t SBC_GetWatchdog | ( | sbc_wtdog_ctr_t *const | wtdog | ) |
This function reads Watchdog control register (0x00).
This function reads Watchdog mode control, and nominal watchdog period.
The UJA1169 contains a watchdog that supports three operating modes: Window, Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a watchdog trigger event within a defined watchdog window triggers and resets the watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered and reset at any time within the watchdog period by a watchdog trigger. Watchdog time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous mode, the watchdog can be off or autonomously in Timeout mode, depending on the selected SBC mode.
wtdog | watchdog registers structure which will be read from device. |
Definition at line 375 of file sbc_uja1169_driver.c.
status_t SBC_GetWatchdogStatus | ( | sbc_wtdog_status_t *const | watchdogStatus | ) |
This function reads Watchdog status register. This function will clear R/W registers automatically after reading.
watchdogStatus | variable for storing Status. |
Definition at line 1063 of file sbc_uja1169_driver.c.
status_t SBC_Init | ( | const sbc_int_config_t *const | config, |
const uint32_t | lpspiInstance | ||
) |
This function initializes all registers. It waits 10ms and then writes to all registers.
config | structure which contains configuration of all registers. |
lpspiInstance | is instance of LPSPI device. |
Definition at line 109 of file sbc_uja1169_driver.c.
status_t SBC_SetCanConfig | ( | const sbc_can_conf_t *const | can | ) |
This function configures CAN peripheral behavior. This function configures CAN peripheral behavior. This function configures several registers which configure CAN. It contains CAN control register, Transceiver event capture enable register, CAN data rate selection, ID registers, ID mask registers, Frame control register, Data mask 0 - 7 configuration.
can | writes CAN peripheral settings to SBC device. |
Definition at line 818 of file sbc_uja1169_driver.c.
status_t SBC_SetFailSafe | ( | const sbc_fail_safe_lhc_t | lhc, |
const sbc_fail_safe_rcc_t *const | rcc | ||
) |
This function writes to Fail-safe control register (0x02). The dedicated LIMP pin can be used to enable so called limp home hardware in the event of a serious ECU failure. Detectable failure conditions include SBC overtemperature events, loss of watchdog service, short-circuits on pins RSTN or V1 and user-initiated or external reset events. The LIMP pin is a battery-robust, active-LOW, open-drain output. The LIMP pin can also be forced LOW by setting bit LHC in the Fail-safe control register. The limp-home function and the reset counter are disabled in Forced Normal mode. The LIMP pin is floating, RCC remains unchanged and bit LHC = 0. RCC -reset counter control. incremented every time the SBC enters Reset mode while FNMC = 0; RCC overflows from 11 to 00; default at power-on is 00. For ignore settings of rcc use NULL pointer or otherwise send pointer to variable.
lhc | Variable for set limp home control. |
rcc | Pointer to rcc. Use null pointer or wrong value for ignore parameter or set value 0x00 to 0x03. |
Definition at line 562 of file sbc_uja1169_driver.c.
status_t SBC_SetLock | ( | const sbc_lock_t | lockMask | ) |
This function writes to Lock control register (0x0A). Sections of the register address area can be write-protected to protect against unintended modifications. This facility only protects locked bits from being modified via the SPI and will not prevent the UJA1169 updating status registers etc. For SPI write disable set lock bit to 1. This is mask for set lock control register.
lockMask | writes Lock control mask for lock or unlock appropriate SBC device bytes. |
Definition at line 741 of file sbc_uja1169_driver.c.
status_t SBC_SetMode | ( | const sbc_mode_mc_t | mode | ) |
This function writes to Mode control register. (0x01).
Normal mode is the active operating mode. In this mode, all the hardware on the device is available and can be activated. Voltage regulator V1 is enabled to supply the microcontroller. Standby mode is the first-level power-saving mode of the UJA1169, offering reduced current consumption. The transceiver is unable to transmit or receive data in Standby mode. The SPI remains enabled and V1 is still active; the watchdog is active (in Timeout mode) if enabled. The behavior of V2/VEXT is determined by the SPI setting. Sleep mode is the second-level power-saving mode of the UJA1169. The difference between Sleep and Standby modes is that V1 is off in Sleep mode and temperature protection is inactive. Note event status are cleared before device move to sleep mode. At least one wake up event must be enabled before moving to sleep mode otherwise SBC will be reseted.
mode | device mode - Normal, StandBy, Sleep. |
Definition at line 449 of file sbc_uja1169_driver.c.
status_t SBC_SetSystemEvents | ( | const sbc_sys_evnt_t *const | sysEvnt | ) |
This function writes System event capture enable register (0x04). This function enables or disables overtemperature warning, SPI failure enable.
sysEvnt | system event capture enable register structure which will be written to device. |
Definition at line 664 of file sbc_uja1169_driver.c.
status_t SBC_SetVreg | ( | const sbc_regulator_ctr_t *const | regulatorCtr | ) |
This function configures Regulator control registers.
Regulator control (0x10), Supply status (0x1B), Supply event enable(0x1C).
regulatorCtr | regulator registers structure which will be written to device. |
Definition at line 193 of file sbc_uja1169_driver.c.
status_t SBC_SetWakePin | ( | const sbc_wake_t *const | wakePin | ) |
This function writes to WAKE pin event capture enable register (0x4C). Local wake-up is enabled via bits WPRE and WPFE in the WAKE pin event capture enable register. A wake-up event is triggered by a LOW-to-HIGH (ifWPRE = 1) and/or a HIGH-to-LOW (if WPFE = 1) transition on the WAKE pin. This arrangement allows for maximum flexibility when designing a local wake-up circuit. In applications that do not use the local wake-up facility, local wake-up should be disabled and the WAKE pin connected to GND.
wakePin | writes configuration to WAKE pin event capture enable register of SBC device. |
Definition at line 949 of file sbc_uja1169_driver.c.
status_t SBC_SetWatchdog | ( | const sbc_wtdog_ctr_t *const | wtdog | ) |
This function configures Watchdog control register (0x00).
This function selects Watchdog mode control, and nominal watchdog period.
The UJA1169 contains a watchdog that supports three operating modes: Window, Timeout and Autonomous. In Window mode (available only in SBC Normal mode), a watchdog trigger event within a defined watchdog window triggers and resets the watchdog timer. In Timeout mode, the watchdog runs continuously and can be triggered and reset at any time within the watchdog period by a watchdog trigger. Watchdog time-out mode can also be used for cyclic wake-up of the microcontroller. In Autonomous mode, the watchdog can be off or autonomously in Timeout mode, depending on the selected SBC mode. Note SBC mode will temporary set to StandBy while WatchDog configuration is changed.
wtdog | watchdog registers structure which will be written to device. |
Definition at line 299 of file sbc_uja1169_driver.c.