36 #if defined(FEATURE_PINS_DRIVER_USING_PORT)
41 typedef uint32_t pins_channel_type_t;
43 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
48 typedef uint16_t pins_channel_type_t;
69 #if FEATURE_PINS_HAS_PULL_SELECTION
76 PORT_INTERNAL_PULL_NOT_ENABLED = 0U,
77 PORT_INTERNAL_PULL_DOWN_ENABLED = 1U,
78 PORT_INTERNAL_PULL_UP_ENABLED = 2U
82 #if FEATURE_PINS_HAS_OPEN_DRAIN
89 PORT_OPEN_DRAIN_DISABLED = 0U,
90 PORT_OPEN_DRAIN_ENABLED = 1U
94 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
101 #if FEATURE_PINS_HAS_DRIVE_STRENGTH_CONTROL
102 PORT_STRENGTH_DISABLED = 0U,
103 PORT_LOW_DRIVE_STRENGTH = 1U,
104 PORT_STR1_DRIVE_STRENGTH = 1U,
105 PORT_STR2_DRIVE_STRENGTH = 2U,
106 PORT_STR3_DRIVE_STRENGTH = 3U,
107 PORT_STR4_DRIVE_STRENGTH = 4U,
108 PORT_STR5_DRIVE_STRENGTH = 5U,
109 PORT_STR6_DRIVE_STRENGTH = 6U,
110 PORT_STR7_DRIVE_STRENGTH = 7U,
111 PORT_HIGH_DRIVE_STRENGTH = 7U
113 PORT_LOW_DRIVE_STRENGTH = 0U,
114 PORT_HIGH_DRIVE_STRENGTH = 1U
116 } port_drive_strength_t;
119 #ifdef FEATURE_PINS_DRIVER_USING_PORT
126 PORT_PIN_DISABLED = 0U,
127 PORT_MUX_AS_GPIO = 1U,
142 PORT_DMA_INT_DISABLED = 0x0U,
143 #if FEATURE_PORT_HAS_DMA_REQUEST
144 PORT_DMA_RISING_EDGE = 0x1U,
145 PORT_DMA_FALLING_EDGE = 0x2U,
146 PORT_DMA_EITHER_EDGE = 0x3U,
148 PORT_INT_LOGIC_ZERO = 0x8U,
149 PORT_INT_RISING_EDGE = 0x9U,
150 PORT_INT_FALLING_EDGE = 0xAU,
151 PORT_INT_EITHER_EDGE = 0xBU,
152 PORT_INT_LOGIC_ONE = 0xCU
153 } port_interrupt_config_t;
155 #if FEATURE_PINS_HAS_SLEW_RATE
162 PORT_FAST_SLEW_RATE = 0U,
163 PORT_SLOW_SLEW_RATE = 1U
167 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
168 #if FEATURE_SIUL2_HAS_DDR_PAD
177 DDR_DDR3_MODE = 0x0U,
178 DDR_LPDDR2_MODE = 0x2U
191 DDR_MIN_DELAY = 0x0U,
192 DDR_50PS_DELAY = 0x1U,
193 DDR_100PS_DELAY = 0x2U,
194 DDR_150PS_DELAY = 0x3U
195 } port_ddr_trim_delay_t;
207 DDR_NO_CRPOINT = 0x0U,
208 DDR_MINUS_CRPOINT = 0x1U,
209 DDR_PLUS_CRPOINT = 0x2U,
210 DDR_DOUBLE_CRPOINT = 0x3U
211 } port_ddr_crpoint_t;
224 DDR_LEFT_TRIM = 0x1U,
225 DDR_RIGHT_TRIM = 0x2U
234 PORT_DDR_INPUT_CMOS = 0U,
235 PORT_DDR_INPUT_DIFFERENTIAL = 1U
244 PORT_STR0_ON_DIE_TERMINATION = 0U,
245 PORT_STR1_ON_DIE_TERMINATION = 1U,
246 PORT_STR2_ON_DIE_TERMINATION = 2U,
247 PORT_STR3_ON_DIE_TERMINATION = 3U,
248 PORT_STR4_ON_DIE_TERMINATION = 4U,
249 PORT_STR5_ON_DIE_TERMINATION = 5U,
250 PORT_STR6_ON_DIE_TERMINATION = 6U,
251 PORT_STR7_ON_DIE_TERMINATION = 7U
252 } port_on_die_termination_t;
262 port_ddr_type_t ddrSelection;
263 port_ddr_trim_delay_t trimmingDelay;
264 port_ddr_crpoint_t crosspointAdjustment;
265 port_ddr_trim_t trimmingAdjustment;
276 PORT_MUX_AS_GPIO = 0U,
286 PORT_MUX_ALT10 = 10U,
287 PORT_MUX_ALT11 = 11U,
288 PORT_MUX_ALT12 = 12U,
289 PORT_MUX_ALT13 = 13U,
290 PORT_MUX_ALT14 = 14U,
300 SIUL2_INT_DISABLE = 0x0U,
301 SIUL2_INT_RISING_EDGE = 0x1U,
302 SIUL2_INT_FALLING_EDGE = 0x2U,
303 SIUL2_INT_EITHER_EDGE = 0x3U
304 } suil2_interrupt_type_t;
306 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
313 SIUL2_INT_USING_INTERUPT = 0x0U,
314 SIUL2_INT_USING_DMA = 0x1U
315 } suil2_interrupt_dma_select_t;
325 suil2_interrupt_type_t intEdgeSel;
326 #if FEATURE_SIUL2_EXTERNAL_INT_SUPPORT_DMA
327 suil2_interrupt_dma_select_t intExeSel;
329 } suil2_interupt_config_t;
337 PORT_OUTPUT_BUFFER_DISABLED = 0U,
338 PORT_OUTPUT_BUFFER_ENABLED = 1U
339 } port_output_buffer_t;
347 PORT_INPUT_BUFFER_DISABLED = 0U,
348 PORT_INPUT_BUFFER_ENABLED = 1U
349 } port_input_buffer_t;
351 #if FEATURE_SIUL2_HAS_HYSTERESIS
358 PORT_HYSTERESYS_CMOS = 0U,
359 PORT_HYSTERESYS_SCHMITT = 1U,
360 PORT_HYSTERESYS_DISABLED = 0U,
361 PORT_HYSTERESYS_ENABLED = 1U
365 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
372 PORT_INVERT_OUTPUT_DISABLED = 0U,
373 PORT_INVERT_OUTPUT_ENABLED = 1U
374 } port_invert_output_t;
377 #if FEATURE_SIUL2_HAS_PULL_KEEPER
384 PORT_PULL_KEEP_DISABLED = 0U,
385 PORT_PULL_KEEP_ENABLED = 1U
394 PORT_KEEPER_ENABLED = 0U,
395 PORT_PULL_ENABLED = 1U
396 } port_pull_keeper_select_t;
404 PORT_PULL_DOWN_ENABLED = 0U,
405 PORT_PULL_UP_MEDIUM = 1U,
406 PORT_PULL_UP_HIGH = 2U,
407 PORT_PULL_UP_LOW = 3U
408 } port_pull_up_down_t;
412 #if FEATURE_SIUL2_HAS_ANALOG_PAD
419 PORT_ANALOG_PAD_CONTROL_DISABLED = 0U,
420 PORT_ANALOG_PAD_CONTROL_ENABLED = 1U
430 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 1U)
431 PORT_INPUT_MUX_ALT0 = 0U,
432 PORT_INPUT_MUX_ALT1 = 1U,
434 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 2U)
435 PORT_INPUT_MUX_ALT2 = 2U,
436 PORT_INPUT_MUX_ALT3 = 3U,
438 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 3U)
439 PORT_INPUT_MUX_ALT4 = 4U,
440 PORT_INPUT_MUX_ALT5 = 5U,
441 PORT_INPUT_MUX_ALT6 = 6U,
442 PORT_INPUT_MUX_ALT7 = 7U,
444 #if (FEATURE_SIUL2_INPUT_SOURCE_SELECT_WIDTH >= 4U)
445 PORT_INPUT_MUX_ALT8 = 8U,
446 PORT_INPUT_MUX_ALT9 = 9U,
447 PORT_INPUT_MUX_ALT10 = 10U,
448 PORT_INPUT_MUX_ALT11 = 11U,
449 PORT_INPUT_MUX_ALT12 = 12U,
450 PORT_INPUT_MUX_ALT13 = 13U,
451 PORT_INPUT_MUX_ALT14 = 14U,
452 PORT_INPUT_MUX_ALT15 = 15U,
454 PORT_INPUT_MUX_NO_INIT
463 PORT_SAFE_MODE_DISABLED = 0U,
465 PORT_SAFE_MODE_ENABLED = 1U
468 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
475 HALF_STRENGTH_WITH_SLEWRATE_CONTROL = 0u,
476 FULL_STRENGTH_WITH_SLEWRATE_CONTROL = 1u,
477 HALF_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 2u,
478 FULL_STRENGTH_WITHOUT_SLEWRATE_CONTROL = 3u
479 } port_slew_rate_control_t;
482 #if FEATURE_PINS_HAS_SLEW_RATE
489 PORT_LOW_SLEW_RATE = 0U,
490 PORT_MEDIUM_SLEW_RATE = 1U,
491 PORT_MEDIUM_SLEW_RATE2 = 2U,
492 PORT_HIGH_SLEW_RATE = 3U
506 #ifdef FEATURE_PINS_DRIVER_USING_PORT
508 #elif defined FEATURE_PINS_DRIVER_USING_SIUL2
512 #if FEATURE_PINS_HAS_PULL_SELECTION
513 port_pull_config_t pullConfig;
515 #if FEATURE_PINS_HAS_SLEW_RATE
516 port_slew_rate_t rateSelect;
518 #if FEATURE_PORT_HAS_PASSIVE_FILTER
521 #if FEATURE_PINS_HAS_OPEN_DRAIN
522 port_open_drain_t openDrain;
524 #if FEATURE_PINS_HAS_DRIVE_STRENGTH
525 port_drive_strength_t driveSelect;
528 #if FEATURE_PORT_HAS_PIN_CONTROL_LOCK
531 #ifdef FEATURE_PINS_DRIVER_USING_PORT
537 #ifdef FEATURE_PINS_DRIVER_USING_SIUL2
538 port_input_mux_t inputMux[FEATURE_SIUL2_INPUT_MUX_WIDTH];
539 uint32_t inputMuxReg[FEATURE_SIUL2_INPUT_MUX_WIDTH];
540 port_output_buffer_t outputBuffer;
541 port_input_buffer_t inputBuffer;
543 #if FEATURE_SIUL2_HAS_SAFE_MODE_CONTROL
544 port_safe_mode_t safeMode;
546 #if FEATURE_SIUL2_HAS_SLEW_RATE_CONTROL
547 port_slew_rate_control_t slewRateCtrlSel;
549 #if FEATURE_SIUL2_HAS_HYSTERESIS
550 port_hysteresis_t hysteresisSelect;
552 #if FEATURE_SIUL2_HAS_DDR_PAD
553 pin_ddr_config_t ddrConfiguration;
554 port_ddr_input_t inputMode;
555 port_on_die_termination_t odtSelect;
557 #if FEATURE_SIUL2_HAS_INVERT_DATA_OUTPUT
558 port_invert_output_t invertOutput;
560 #if FEATURE_SIUL2_HAS_PULL_KEEPER
561 port_pull_keep_t pullKeepEnable;
562 port_pull_keeper_select_t pullKeepSelect;
563 port_pull_up_down_t pullSelect;
565 #if FEATURE_SIUL2_HAS_ANALOG_PAD
566 port_analog_pad_t analogPadCtrlSel;
579 #if defined(__cplusplus)
596 #ifdef FEATURE_PINS_DRIVER_USING_PORT
597 #if FEATURE_PINS_HAS_PULL_SELECTION
607 void PINS_DRV_SetPullSel(
PORT_Type *
const base,
609 port_pull_config_t pullConfig);
622 void PINS_DRV_SetMuxModeSel(
PORT_Type *
const base,
635 void PINS_DRV_SetPinIntSel(
PORT_Type *
const base,
648 port_interrupt_config_t PINS_DRV_GetPinIntSel(
const PORT_Type *
const base,
659 void PINS_DRV_ClearPinIntFlagCmd(
PORT_Type *
const base,
670 uint32_t PINS_DRV_GetPortIntFlag(
const PORT_Type *
const base);
679 void PINS_DRV_ClearPortIntFlagCmd(
PORT_Type *
const base);
694 pins_channel_type_t PINS_DRV_GetPinsDirection(
const GPIO_Type *
const base);
709 void PINS_DRV_SetPinDirection(
GPIO_Type *
const base,
710 pins_channel_type_t pin,
727 void PINS_DRV_SetPinsDirection(
GPIO_Type *
const base,
728 pins_channel_type_t pins);
744 void PINS_DRV_SetPortInputDisable(
GPIO_Type *
const base,
745 pins_channel_type_t pins);
760 pins_channel_type_t PINS_DRV_GetPortInputDisable(
const GPIO_Type *
const base);
762 #elif defined(FEATURE_PINS_DRIVER_USING_SIUL2)
772 void PINS_DRV_SetPinIntSel(
PORT_Type *
const base,
774 suil2_interupt_config_t intConfig);
785 suil2_interupt_config_t PINS_DRV_GetPinIntSel(
const PORT_Type *
const base,
803 pins_channel_type_t pin,
818 pins_channel_type_t pins);
848 pins_channel_type_t pins);
864 pins_channel_type_t pins);
879 pins_channel_type_t pins);
897 #if defined(__cplusplus)
rtc_interrupt_config_t * intConfig
status_t PINS_DRV_Init(uint32_t pinCount, const pin_settings_config_t config[])
Initializes the pins with the given configuration structure.
pins_channel_type_t PINS_DRV_GetPinsOutput(const GPIO_Type *const base)
Get the current output from a port.
port_mux_t mux
Pin (C55: Out) mux selection.
void PINS_DRV_WritePin(GPIO_Type *const base, pins_channel_type_t pin, pins_level_type_t value)
Write a pin of a port with a given value.
void PINS_DRV_TogglePins(GPIO_Type *const base, pins_channel_type_t pins)
Toggle pins value.
void PINS_DRV_WritePins(GPIO_Type *const base, pins_channel_type_t pins)
Write all pins of a port.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
port_data_direction_t
Configures the port data direction Implements : port_data_direction_t_Class.
Defines the converter configuration.
void PINS_DRV_SetPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins with 'Set' value.
pins_channel_type_t PINS_DRV_ReadPins(const GPIO_Type *const base)
Read input pins.
port_data_direction_t direction
uint8_t pins_level_type_t
Type of a port levels representation. Implements : pins_level_type_t_Class.
void PINS_DRV_ClearPins(GPIO_Type *const base, pins_channel_type_t pins)
Write pins to 'Clear' value.