19 #include "enet_hw_access.h"
27 #define ENET_ROUNDED_UP_DIV(a, b) ((a) + (b) - 1) / (b)
28 #define ENET_NS_IN_SECOND (1000000000U)
30 #define ENET_ALL_INTERRUPTS_MASK (0xFFFFFFFFU)
32 #define ENET_BYTE_0_IN_ADDR_SHIFT (24U)
33 #define ENET_BYTE_1_IN_ADDR_SHIFT (16U)
34 #define ENET_BYTE_2_IN_ADDR_SHIFT (8U)
35 #define ENET_BYTE_3_IN_ADDR_SHIFT (0U)
36 #define ENET_BYTE_4_IN_ADDR_SHIFT (8U)
37 #define ENET_BYTE_5_IN_ADDR_SHIFT (0U)
39 #define ENET_BYTE_MASK (0xFFU)
54 #ifdef FEATURE_ENET_WAKEUP_IRQS
80 uint32_t crc = 0xFFFFFFFF;
83 for (i = 0; i < 6U; i++)
86 for (j = 0; j < 8U; j++)
90 crc = (crc >> 1U) ^ 0xEDB88320U;
169 base = s_enetBases[instance];
178 ENET_ConfigReceiveControl(base, config);
179 ENET_ConfigTransmitControl(base, config);
189 #ifdef FEATURE_ENET_WAKEUP_IRQS
193 ENET_EnableInterrupts(base, config->
interrupt);
203 g_enetState[instance] = state;
213 ENET_ActivateReceive(base);
231 base = s_enetBases[instance];
239 #ifdef FEATURE_ENET_WAKEUP_IRQS
264 enet_buffer_descriptor_t *bd;
273 if ((bd->control & ENET_BUFFDESCR_RX_EMPTY_MASK) != (uint16_t)0)
279 buff->
data = bd->buffer;
280 buff->
length = bd->length;
283 if ((bd->control & ENET_BUFFDESCR_RX_WRAP_MASK) != (uint16_t)0)
310 enet_buffer_descriptor_t *bd;
317 base = s_enetBases[instance];
321 if ((bd->control & ENET_BUFFDESCR_TX_READY_MASK) != (uint16_t)0)
328 bd->length = buff->
length;
329 bd->buffer = buff->
data;
330 bd->control |= (uint16_t)(ENET_BUFFDESCR_TX_READY_MASK | ENET_BUFFDESCR_TX_LAST_MASK);
333 ENET_ActivateTransmit(base);
336 if ((bd->control & ENET_BUFFDESCR_TX_WRAP_MASK) != (uint16_t)0)
361 enet_buffer_descriptor_t *bd;
368 bd = g_enetState[instance]->
txBdBase;
371 while ((bd->control & ENET_BUFFDESCR_TX_WRAP_MASK) == (uint16_t)0)
373 if (bd->buffer == buff->
data)
376 if ((bd->control & ENET_BUFFDESCR_TX_READY_MASK) != (uint16_t)0)
404 enet_buffer_descriptor_t *bd;
410 base = s_enetBases[instance];
415 DEV_ASSERT((bd->control & ENET_BUFFDESCR_RX_EMPTY_MASK) == (uint16_t)0);
417 bd->buffer = buff->
data;
420 bd->control &= ENET_BUFFDESCR_RX_WRAP_MASK;
421 bd->control |= ENET_BUFFDESCR_RX_EMPTY_MASK;
424 if ((bd->control & ENET_BUFFDESCR_RX_WRAP_MASK) != (uint16_t)0)
434 ENET_ActivateReceive(base);
445 bool miiPreambleDisabled)
448 uint32_t moduleClk, holdTime, miiSpeed;
453 base = s_enetBases[instance];
463 ENET_WriteManagementConfig(base, config);
480 uint32_t startTime, crtTime;
485 base = s_enetBases[instance];
488 ENET_WriteManagementFrame(base, phyAddr, phyReg, ENET_MMFR_OP_WRITE, data);
498 ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
503 while (crtTime < startTime + timeoutMs);
522 uint32_t startTime, crtTime;
527 base = s_enetBases[instance];
530 ENET_WriteManagementFrame(base, phyAddr, phyReg, ENET_MMFR_OP_READ, 0);
538 *data = ENET_ReadManagementFrameData(base);
541 ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
546 while (crtTime < startTime + timeoutMs);
566 base = s_enetBases[instance];
573 ENET_SetPhyAddrLower(base, address);
579 ENET_SetPhyAddrUpper(base, address);
598 base = s_enetBases[instance];
601 address = ENET_GetPhyAddrLower(base);
608 address = ENET_GetPhyAddrUpper(base);
631 base = s_enetBases[instance];
636 ENET_AddToIndividualHashTable(base, crc);
640 ENET_RemoveFromIndividualHashTable(base, crc);
662 base = s_enetBases[instance];
667 ENET_AddToGroupHashTable(base, crc);
671 ENET_RemoveFromGroupHashTable(base, crc);
690 base = s_enetBases[instance];
694 base->
GAUR = 0xFFFFFFFFU;
695 base->
GALR = 0xFFFFFFFFU;
718 base = s_enetBases[instance];
744 base = s_enetBases[instance];
775 base = s_enetBases[instance];
void ENET_DRV_GetMacAddr(uint8_t instance, uint8_t *macAddr)
Gets the physical address of the MAC.
#define FEATURE_ENET_COUNTERS_OFFSET_WORDS
The offset of the counters region relative to the base address, in words.
enet_state_t * g_enetState[ENET_INSTANCE_COUNT]
Pointers to ENET internal driver state for each instance.
Internal driver state structure Implements : enet_state_t_Class.
#define FEATURE_ENET_RX_IRQS
The reception interrupts.
#define ENET_INSTANCE_COUNT
#define ENET_MIBC_MIB_CLEAR_MASK
#define ENET_BYTE_0_IN_ADDR_SHIFT
void ENET_DRV_SetUnicastForward(uint8_t instance, uint8_t *macAddr, bool enable)
Enables/Disables forwarding of unicast traffic having a specific MAC address as destination.
Send/Receive buffer information for the user Implements : enet_buffer_t_Class.
#define ENET_BYTE_4_IN_ADDR_SHIFT
void ENET_DRV_GetDefaultConfig(enet_config_t *config)
Gets the default configuration structure.
void ENET_DRV_ConfigCounters(uint8_t instance, bool enable)
Enables/Disables the MIB counters.
status_t ENET_DRV_GetTransmitStatus(uint8_t instance, enet_buffer_t *buff)
Checks if the transmission of a buffer is complete.
Defines the ENET module configuration structure Implements : enet_config_t_Class. ...
uint32_t OSIF_GetMilliseconds(void)
Returns the number of miliseconds elapsed since starting the internal timer or starting the scheduler...
#define ENET_MSCR_MII_SPEED(x)
IRQn_Type
Defines the Interrupt Numbers definitions.
#define FEATURE_ENET_MDIO_MIN_HOLD_TIME_NS
Minimum hold time on the MDIO output, in nanoseconds.
void ENET_DRV_EnableMDIO(uint8_t instance, bool miiPreambleDisabled)
Enables the MDIO interface.
void ENET_DRV_Deinit(uint8_t instance)
Deinitializes the ENET module.
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
#define FEATURE_ENET_ERR_IRQS
The error interrupts.
#define ENET_MIN_BUFFERSIZE
ENET minimum buffer size.
enet_buffer_descriptor_t * rxBdCurrent
#define ENET_BUFF_IS_ALIGNED(x)
void ENET_DRV_ProvideRxBuff(uint8_t instance, enet_buffer_t *buff)
Provides a receive buffer to be used by the driver for reception.
enet_buffer_descriptor_t * rxBdAlloc
#define ENET_MSCR_DIS_PRE(x)
#define ENET_ECR_MAGICEN_MASK
#define FEATURE_ENET_TX_IRQS
The transmission interrupts.
#define ENET_ECR_SLEEP_MASK
#define ENET_EIR_MII_MASK
void ENET_DRV_SetMacAddr(uint8_t instance, uint8_t *macAddr)
Configures the physical address of the MAC.
static uint32_t ENET_DRV_ComputeCRC32(uint8_t *mac)
enet_counter_t
Statistics counters enumeration Implements : enet_counter_t_Class.
void ENET_DRV_SetMulticastForwardAll(uint8_t instance, bool enable)
Enables/Disables forwarding of the multicast traffic, irrespective of the destination MAC address...
status_t ENET_DRV_MDIOWrite(uint8_t instance, uint8_t phyAddr, uint8_t phyReg, uint16_t data, uint32_t timeoutMs)
Writes the selected register of the PHY.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
#define FEATURE_ENET_DEFAULT_PHY_IF
Default configuration for the PHY interface.
enet_mii_duplex_t miiDuplex
#define ENET_ROUNDED_UP_DIV(a, b)
Defines the ENET buffer descriptors ring configuration structure Implements : enet_buffer_config_t_Cl...
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
clock_names_t
Clock names.
#define ENET_BYTE_5_IN_ADDR_SHIFT
status_t ENET_DRV_SendFrame(uint8_t instance, enet_buffer_t *buff)
Sends an Ethernet frame.
#define ENET_MSCR_HOLDTIME(x)
enet_buffer_descriptor_t * rxRingAligned
enet_buffer_descriptor_t * txBdBase
enet_mii_speed_t miiSpeed
#define ENET_BYTE_2_IN_ADDR_SHIFT
static const IRQn_Type s_enetTxIrqId[]
ENET transmit IRQ number for each instance.
static const clock_names_t s_enetClkNames[]
Table to save ENET clock indexes in clock configuration.
uint8_t * rxBufferAligned
#define ENET_BUFF_ALIGN(x)
Definitions used for aligning the data buffers.
enet_buffer_descriptor_t * txRingAligned
enet_buffer_descriptor_t * rxBdBase
#define FEATURE_ENET_WAKE_IRQS
The wakeup interrupts.
#define FEATURE_ENET_CLOCK_NAMES
ENET peripheral clock names.
void ENET_DRV_SetMulticastForward(uint8_t instance, uint8_t *macAddr, bool enable)
Enables/Disables forwarding of multicast traffic having a specific MAC address as destination...
enet_buffer_descriptor_t * txBdCurrent
#define ENET_BUFFDESCR_IS_ALIGNED(x)
#define ENET_BYTE_1_IN_ADDR_SHIFT
static const IRQn_Type s_enetRxIrqId[]
ENET receive IRQ number for each instance.
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
#define ENET_FRAME_MAX_FRAMELEN
Defines the maximum Ethernet frame size.
#define ENET_NS_IN_SECOND
uint32_t ENET_DRV_GetCounter(uint8_t instance, enet_counter_t counter)
Gets statistics from the specified counter.
#define ENET_ALL_INTERRUPTS_MASK
void ENET_DRV_SetSleepMode(uint8_t instance, bool enable)
Sets the MAC in sleep mode or normal mode.
#define ENET_BYTE_3_IN_ADDR_SHIFT
status_t ENET_DRV_ReadFrame(uint8_t instance, enet_buffer_t *buff)
Reads a received Ethernet frame.
#define ENET_MIBC_MIB_DIS_MASK
#define FEATURE_ENET_MDC_MAX_FREQUENCY
The maximum supported frequency for MDC, in Hz.
status_t ENET_DRV_MDIORead(uint8_t instance, uint8_t phyAddr, uint8_t phyReg, uint16_t *data, uint32_t timeoutMs)
Reads the selected register of the PHY.
static const IRQn_Type s_enetErrIrqId[]
ENET error IRQ number for each instance.
void ENET_DRV_Init(uint8_t instance, enet_state_t *state, const enet_config_t *config, const enet_buffer_config_t *bufferConfig, uint8_t *macAddr)
Initializes the ENET module.