S32 SDK
spi_pal_mapping.h
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1 /*
2  * Copyright 2017 NXP
3  * All rights reserved.
4  *
5  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
6  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
7  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
8  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
9  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
10  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
11  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
12  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
13  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
14  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
15  * THE POSSIBILITY OF SUCH DAMAGE.
16  */
17 
18 #ifndef PAL_mapping_H
19 #define PAL_mapping_H
20 #include "device_registers.h"
21 /*
22  * Define the available instances for SPI functionality
23  */
24 #if (defined(CPU_S32K144HFT0VLLT) || defined(CPU_S32K144LFT0MLLT) || defined(CPU_S32K148))
25 /*
26  * @brief Define instances for S32K144 and S32K148 (LPSPI and FlexIO)
27  */
28 
29 typedef enum
30 {
34  SPI_OVER_FLEXIO0_INSTANCE = 3U, /* This is a virtual SPI instance over FlexIO */
35  SPI_OVER_FLEXIO1_INSTANCE = 4U, /* This is a virtual SPI instance over FlexIO */
37 
38 /* On S32K144 and S32K148 are available 5 instances which supports SPI */
39 #define NUMBER_OF_SPI_PAL_INSTANCES 5U
40 /* Defines the index limits for all SPIs */
41 #define LPSPI_HIGH_INDEX 2U
42 #define FLEXIO_SPI_LOW_INDEX 3U
43 #define FLEXIO_SPI_HIGH_INDEX 4U
44 #endif
45 
46 #if (defined(CPU_S32K142))
47 /*
48  * @brief Define instances for S32K142 (LPSPI and FlexIO)
49  */
50 
51 typedef enum
52 {
55  SPI_OVER_FLEXIO_0_INSTANCE = 2U, /* This is a virtual SPI instance over FlexIO */
56  SPI_OVER_FLEXIO_1_INSTANCE = 3U, /* This is a virtual SPI instance over FlexIO */
58 
59 /* On S32K144 and S32K148 are available 5 instances which supports SPI */
60 #define NUMBER_OF_SPI_PAL_INSTANCES 4U
61 /* Defines the index limits for all SPIs */
62 #define LPSPI_HIGH_INDEX 1U
63 #define FLEXIO_SPI_LOW_INDEX 2U
64 #define FLEXIO_SPI_HIGH_INDEX 3U
65 #endif
66 
67 #if (defined(CPU_MPC5748G))
68 /*
69  * @brief Define instances for MPC5748G (DSPI)
70  */
71 typedef enum
72 {
73  SPI_OVER_DSPI0_INSTANCE = 0U,
74  SPI_OVER_DSPI1_INSTANCE = 1U,
75  SPI_OVER_DSPI2_INSTANCE = 2U,
76  SPI_OVER_DSPI3_INSTANCE = 3U,
77  SPI_OVER_SPI0_INSTANCE = 4U,
78  SPI_OVER_SPI1_INSTANCE = 5U,
79  SPI_OVER_SPI2_INSTANCE = 6U,
80  SPI_OVER_SPI3_INSTANCE = 7U,
81  SPI_OVER_SPI4_INSTANCE = 8U,
82  SPI_OVER_SPI5_INSTANCE = 9U,
84 
85 /* On MPC5748G are available 10 instances which supports SPI */
86 #define NUMBER_OF_SPI_PAL_INSTANCES 10U
87 /* Defines the index limits for all SPIs */
88 #define DSPI_LOW_INDEX 0U
89 #define DSPI_HIGH_INDEX 9U
90 #endif
91 
92 #endif /* PAL_mapping_H */
spi_instance_t