S32 SDK
clock_S32K1xx.c
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1 /*
2  * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
3  * Copyright 2016-2017 NXP
4  * All rights reserved.
5  *
6  * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
7  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
8  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
9  * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
10  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
11  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
12  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
13  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
14  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
15  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
16  * THE POSSIBILITY OF SUCH DAMAGE.
17  */
47 #include "device_registers.h"
48 #include "sim_hw_access.h"
49 #include "scg_hw_access.h"
50 #include "pcc_hw_access.h"
51 #include "pmc_hw_access.h"
52 #include "smc_hw_access.h"
53 #include "clock_manager.h"
54 #include <stddef.h> /* This header is included for bool type */
55 /*
56  * README:
57  * This file provides these APIs:
58  * 1. APIs to get the frequency of output clocks in Reference Manual ->
59  * Chapter Clock Distribution -> Figure Clocking diagram.
60  * 2. APIs for IP modules listed in Reference Manual -> Chapter Clock Distribution
61  * -> Module clocks.
62  */
63 
64 /*******************************************************************************
65  * Definitions
66  ******************************************************************************/
67 /* This frequency values should be set by different boards. */
68 /* SIM */
69 uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]; /* TCLKx clocks */
70 
71 /* RTC */
72 uint32_t g_RtcClkInFreq; /* RTC CLKIN clock */
73 
74 /* SCG */
75 uint32_t g_xtal0ClkFreq; /* EXTAL0 clock */
76 
77 
78 /* @brief System PLL base multiplier value, it is the multiplier value when SCG_SPLLCFG[MULT]=0. */
79 #define SCG_SPLL_MULT_BASE 16U
80 
81 /*
82  * @brief System PLL base divider value, it is the PLL reference clock divider value when
83  * SCG_SPLLCFG[PREDIV]=0.
84  */
85 #define SCG_SPLL_PREDIV_BASE 1U
86 
87 /*
88  * @brief System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
89  * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
90  */
91 #define SCG_SPLL_REF_MIN 8000000U
92 
93 /*
94  * @brief System PLL reference clock after SCG_SPLLCFG[PREDIV] should be in the range of
95  * SCG_SPLL_REF_MIN to SCG_SPLL_REF_MAX.
96  */
97 #define SCG_SPLL_REF_MAX 32000000U
98 
99 /*
100  * @brief LPO 128K fixed clock frequency.
101  */
102 #define LPO_128K_FREQUENCY 128000UL
103 
104 /*
105  * @brief LPO 32K fixed clock frequency.
106  */
107 #define LPO_32K_FREQUENCY 32000UL
108 
109 /*
110  * @brief LPO 1K fixed clock frequency.
111  */
112 #define LPO_1K_FREQUENCY 1000UL
113 
114 /*
115  * @brief Running modes.
116  */
117 #define HIGH_SPEED_RUNNING_MODE (1UL << 7U)
118 #define RUN_SPEED_RUNNING_MODE (1UL << 0U)
119 #define VLPR_SPEED_RUNNING_MODE (1UL << 2U)
120 
127 
132 
137 typedef enum
138 {
144 
149 typedef enum
150 {
155 
160 typedef enum
161 {
168 
169 
170 /*******************************************************************************
171  * INTERNAL FUNCTIONS
172  ******************************************************************************/
173 
175  uint32_t * frequency);
176 
178  uint32_t * frequency);
179 
181  uint32_t * frequency);
182 
183 static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName,
184  scg_async_clock_type_t divider);
185 
187 
189 
190 static uint32_t CLOCK_SYS_GetSimClkOutFreq(void);
191 
192 static uint32_t CLOCK_SYS_GetScgClkOutFreq(void);
193 
194 static uint32_t CLOCK_SYS_GetSimRtcClkFreq(void);
195 
197 
199 
200 static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t * sircConfig);
201 
202 static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t * fircConfig);
203 
204 static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t * soscConfig);
205 
206 static status_t CLOCK_SYS_ConfigureSPLL(bool enable, const scg_spll_config_t * spllConfig);
207 
209 
211  scg_system_clock_config_t const * config);
212 
213 static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource,
215 
216 static uint32_t CLOCK_SYS_GetSircFreq(void);
217 
218 static uint32_t CLOCK_SYS_GetFircFreq(void);
219 
220 static uint32_t CLOCK_SYS_GetSysOscFreq(void);
221 
222 static uint32_t CLOCK_SYS_GetSysPllFreq(void);
223 
224 static uint32_t CLOCK_SYS_GetLpoFreq(void);
225 
227 
228 static void CLOCK_SYS_GetCurrentSysClkConfig(scg_system_clock_config_t * sysClockConfig);
229 
230 /*******************************************************************************
231  * Code
232  ******************************************************************************/
233 
234 
235 /*FUNCTION**********************************************************************
236  *
237  * Function Name : CLOCK_SYS_SetConfiguration
238  * Description : This function sets the system to target configuration, it
239  * only sets the clock modules registers for clock mode change, but not send
240  * notifications to drivers.
241  *
242  * Implements CLOCK_SYS_SetConfiguration_Activity
243  * END**************************************************************************/
245 {
246  status_t result;
247  DEV_ASSERT(config != NULL);
248 
249  /* Set SCG settings. */
250  result = CLOCK_SYS_SetScgConfiguration(&config->scgConfig);
251 
252  if (STATUS_SUCCESS == result)
253  {
254  /* Set PCC settings. */
255  CLOCK_SYS_SetPccConfiguration(&config->pccConfig);
256 
257  /* Set SIM settings. */
258  CLOCK_SYS_SetSimConfiguration(&config->simConfig);
259 
260  /* Set PMC settings. */
261  CLOCK_SYS_SetPmcConfiguration(&config->pmcConfig);
262  }
263 
264  return result;
265 }
266 
267 /*FUNCTION**********************************************************************
268  *
269  * Function Name : CLOCK_SYS_SetScgConfiguration
270  * Description : This function configures the SCG blocks
271  *
272  * Implements CLOCK_SYS_SetScgConfiguration_Activity
273  * END**************************************************************************/
275 {
276  status_t status = STATUS_SUCCESS;
277  DEV_ASSERT(scgConfig != NULL);
278 
279  if (scgConfig != NULL)
280  {
281  /* Configure a temporary system clock source: FIRC */
283 
284  if (status == STATUS_SUCCESS)
285  {
286  /* Configure clock sources from SCG */
287  status = CLOCK_SYS_ConfigureModulesFromScg(scgConfig);
288  }
289 
290  if (status == STATUS_SUCCESS)
291  {
292  /* Configure RTC. */
293  if (scgConfig->rtcConfig.initialize)
294  {
295  /* RTC Clock settings. */
297  }
298 
299  /* Configure SCG ClockOut. */
300  if (scgConfig->clockOutConfig.initialize)
301  {
302  /* ClockOut settings. */
303  SCG_SetClockoutSourceSel(SCG, (uint32_t)scgConfig->clockOutConfig.source);
304  }
305 
306  /* Configure SCG clock modes. */
307  if (scgConfig->clockModeConfig.initialize)
308  {
309  /* Configure SCG clock modes */
311  if (status == STATUS_SUCCESS)
312  {
314  }
315 
316  if (status == STATUS_SUCCESS)
317  {
319  }
320  }
321  }
322  }
323 
324  return status;
325 }
326 
327 /*FUNCTION**********************************************************************
328  *
329  * Function Name : CLOCK_SYS_SetPccConfiguration
330  * Description : This function configures the PCC block
331  *
332  * Implements CLOCK_SYS_SetPccConfiguration_Activity
333  * END**************************************************************************/
334 void CLOCK_SYS_SetPccConfiguration(const pcc_config_t * peripheralClockConfig)
335 {
336  DEV_ASSERT(peripheralClockConfig != NULL);
337 
338  uint32_t i;
339 
340  if ((peripheralClockConfig != NULL) && (peripheralClockConfig->peripheralClocks != NULL))
341  {
342  for (i = 0U; i < peripheralClockConfig->count; i++)
343  {
344  /* Disable the peripheral clock */
345  PCC_SetClockMode(PCC, peripheralClockConfig->peripheralClocks[i].clockName, false);
346 
347  /* Set peripheral clock control */
348  PCC_SetPeripheralClockControl(PCC,
349  peripheralClockConfig->peripheralClocks[i].clockName,
350  peripheralClockConfig->peripheralClocks[i].clkGate,
351  (uint32_t)peripheralClockConfig->peripheralClocks[i].clkSrc,
352  (uint32_t)peripheralClockConfig->peripheralClocks[i].divider,
353  (uint32_t)peripheralClockConfig->peripheralClocks[i].frac);
354  }
355  }
356 }
357 
358 /*FUNCTION**********************************************************************
359  *
360  * Function Name : CLOCK_SYS_SetSimConfiguration
361  * Description : This function configures the SIM block
362  *
363  * Implements CLOCK_SYS_SetSimConfiguration_Activity
364  * END**************************************************************************/
366 {
367  DEV_ASSERT(simClockConfig != NULL);
368  uint8_t i;
369 
370  /* ClockOut settings. */
371  if (simClockConfig->clockOutConfig.initialize)
372  {
373  SIM_SetClockout(SIM, simClockConfig->clockOutConfig.enable, simClockConfig->clockOutConfig.source, simClockConfig->clockOutConfig.divider);
374  }
375 
376  /* Low Power Clock settings from SIM. */
377  if (simClockConfig->lpoClockConfig.initialize)
378  {
379  SIM_SetLpoClocks(SIM,
380  simClockConfig->lpoClockConfig.enableLpo1k,
381  simClockConfig->lpoClockConfig.enableLpo32k,
382  simClockConfig->lpoClockConfig.sourceLpoClk,
383  simClockConfig->lpoClockConfig.sourceRtcClk);
384  }
385 
386  /* Platform Gate Clock settings. */
387  if (simClockConfig->platGateConfig.initialize)
388  {
389  SIM_SetMscmClockGate(SIM, simClockConfig->platGateConfig.enableMscm);
390  SIM_SetMpuClockGate(SIM, simClockConfig->platGateConfig.enableMpu);
391  SIM_SetDmaClockGate(SIM, simClockConfig->platGateConfig.enableDma);
392  SIM_SetErmClockGate(SIM, simClockConfig->platGateConfig.enableErm);
393  SIM_SetEimClockGate(SIM, simClockConfig->platGateConfig.enableEim);
394 #if defined (QuadSPI_INSTANCE_COUNT)
395  SIM_SetQspiIntRefClockGate(SIM, simClockConfig->qspiRefClkGating.enableQspiRefClk);
396 #endif
397  }
398 
399  /* TCLK Clock settings. */
400  if (simClockConfig->tclkConfig.initialize)
401  {
402  for (i = 0; i < NUMBER_OF_TCLK_INPUTS; i++)
403  {
404  if (i < NUMBER_OF_TCLK_INPUTS)
405  {
406  g_TClkFreq[i] = simClockConfig->tclkConfig.tclkFreq[i];
407  }
408  }
409  }
410 
411  /* Debug trace Clock settings. */
412  if (simClockConfig->traceClockConfig.initialize)
413  {
414  SIM_ClearTraceClockConfig(SIM);
415  SIM_SetTraceClockSource(SIM, simClockConfig->traceClockConfig.source);
416  SIM_SetTraceClockConfig(SIM,
417  simClockConfig->traceClockConfig.divEnable,
418  simClockConfig->traceClockConfig.divider,
419  simClockConfig->traceClockConfig.divFraction);
420  }
421 }
422 
423 /*FUNCTION**********************************************************************
424  *
425  * Function Name : CLOCK_SYS_SetPmcConfiguration
426  * Description : This function configures the PMC block
427  *
428  * Implements CLOCK_SYS_SetPmcConfiguration_Activity
429  * END**************************************************************************/
431 {
432  DEV_ASSERT(pmcConfig != NULL);
433 
434  /* Low Power Clock settings from PMC. */
435  if (pmcConfig->lpoClockConfig.initialize)
436  {
437  /* Enable/disable the low power oscillator. */
438  PMC_SetLpoMode(PMC, pmcConfig->lpoClockConfig.enable);
439 
440  /* Write trimming value. */
441  PMC_SetLpoTrimValue(PMC, pmcConfig->lpoClockConfig.trimValue);
442  }
443 }
444 
445 /*FUNCTION**********************************************************************
446  *
447  * Function Name : CLOCK_SYS_GetScgClockFreq
448  * Description : This function returns the frequency of a given clock from SCG
449  *
450  * END**************************************************************************/
452  uint32_t * frequency)
453 {
454  status_t returnCode = STATUS_SUCCESS;
455  uint32_t freq = 0U;
456 
457  switch (clockName)
458  {
459  /* Main clocks */
460  case CORE_CLOCK:
462  break;
463  case BUS_CLOCK:
465  break;
466  case SLOW_CLOCK:
468  break;
469  case CLKOUT_CLOCK:
471  break;
472 
473  /* Other internal clocks used by peripherals. */
474  case SIRC_CLOCK:
475  freq = CLOCK_SYS_GetSircFreq();
476  break;
477  case FIRC_CLOCK:
478  freq = CLOCK_SYS_GetFircFreq();
479  break;
480  case SOSC_CLOCK:
481  freq = CLOCK_SYS_GetSysOscFreq();
482  break;
483  case SPLL_CLOCK:
484  freq = CLOCK_SYS_GetSysPllFreq();
485  break;
486  case RTC_CLKIN_CLOCK:
487  freq = g_RtcClkInFreq;
488  break;
489  case SCG_CLKOUT_CLOCK:
491  break;
492  case SIRCDIV1_CLK:
494  break;
495  case SIRCDIV2_CLK:
497  break;
498  case FIRCDIV1_CLK:
500  break;
501  case FIRCDIV2_CLK:
503  break;
504  case SOSCDIV1_CLK:
506  break;
507  case SOSCDIV2_CLK:
509  break;
510  case SPLLDIV1_CLK:
512  break;
513  case SPLLDIV2_CLK:
515  break;
516  default:
517  returnCode = STATUS_UNSUPPORTED;
518  break;
519  }
520 
521  if (frequency != NULL)
522  {
523  *frequency = freq;
524  }
525 
526  return returnCode;
527 }
528 
529 /*FUNCTION**********************************************************************
530  *
531  * Function Name : CLOCK_SYS_GetSimClockFreq
532  * Description : This function returns the frequency of a given clock from SIM
533  *
534  * END**************************************************************************/
536  uint32_t * frequency)
537 {
538  status_t returnCode = STATUS_SUCCESS;
539  uint32_t clockPinSelect;
540  uint32_t freq = 0U;
541 
542  switch (clockName)
543  {
544  /* SIM clocks */
545  case SIM_FTM0_CLOCKSEL:
546  clockPinSelect = SIM_GetFtm0ExternalClkPinMode(SIM);
547  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
548  {
549  freq = g_TClkFreq[clockPinSelect];
550  }
551 
552  break;
553  case SIM_FTM1_CLOCKSEL:
554  clockPinSelect = SIM_GetFtm1ExternalClkPinMode(SIM);
555  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
556  {
557  freq = g_TClkFreq[clockPinSelect];
558  }
559 
560  break;
561  case SIM_FTM2_CLOCKSEL:
562  clockPinSelect = SIM_GetFtm2ExternalClkPinMode(SIM);
563  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
564  {
565  freq = g_TClkFreq[clockPinSelect];
566  }
567 
568  break;
569  case SIM_FTM3_CLOCKSEL:
570  clockPinSelect = SIM_GetFtm3ExternalClkPinMode(SIM);
571  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
572  {
573  freq = g_TClkFreq[clockPinSelect];
574  }
575 
576  break;
577 #if FTM_INSTANCE_COUNT > 4U
578  case SIM_FTM4_CLOCKSEL:
579  clockPinSelect = SIM_GetFtm4ExternalClkPinMode(SIM);
580  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
581  {
582  freq = g_TClkFreq[clockPinSelect];
583  }
584 
585  break;
586 #endif
587 #if FTM_INSTANCE_COUNT > 5U
588  case SIM_FTM5_CLOCKSEL:
589  clockPinSelect = SIM_GetFtm5ExternalClkPinMode(SIM);
590  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
591  {
592  freq = g_TClkFreq[clockPinSelect];
593  }
594 
595  break;
596 #endif
597 #if FTM_INSTANCE_COUNT > 6U
598  case SIM_FTM6_CLOCKSEL:
599  clockPinSelect = SIM_GetFtm6ExternalClkPinMode(SIM);
600  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
601  {
602  freq = g_TClkFreq[clockPinSelect];
603  }
604 
605  break;
606 #endif
607 #if FTM_INSTANCE_COUNT > 7U
608  case SIM_FTM7_CLOCKSEL:
609  clockPinSelect = SIM_GetFtm7ExternalClkPinMode(SIM);
610  if (clockPinSelect < NUMBER_OF_TCLK_INPUTS)
611  {
612  freq = g_TClkFreq[clockPinSelect];
613  }
614 
615  break;
616 #endif
617  case SIM_CLKOUTSELL:
619  break;
620  case SIM_RTCCLK_CLOCK:
622  break;
623  case SIM_LPO_CLOCK:
624  if (PMC_GetLpoMode(PMC))
625  {
626  freq = CLOCK_SYS_GetLpoFreq();
627  }
628 
629  break;
630  case SIM_LPO_1K_CLOCK:
631  if (PMC_GetLpoMode(PMC))
632  {
633  freq = SIM_GetLpo1KStatus(SIM) ? LPO_1K_FREQUENCY : 0UL;
634  }
635 
636  break;
637  case SIM_LPO_32K_CLOCK:
638  if (PMC_GetLpoMode(PMC))
639  {
640  freq = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
641  }
642 
643  break;
644  case SIM_LPO_128K_CLOCK:
645  if (PMC_GetLpoMode(PMC))
646  {
647  freq = LPO_128K_FREQUENCY;
648  }
649 
650  break;
651  case SIM_EIM_CLOCK:
652  if (!SIM_GetEimClockGate(SIM))
653  {
654  /* EIM is not clocked. */
655  returnCode = STATUS_MCU_GATED_OFF;
656  }
657 
658  break;
659  case SIM_ERM_CLOCK:
660  if (!SIM_GetErmClockGate(SIM))
661  {
662  /* ERM is not clocked. */
663  returnCode = STATUS_MCU_GATED_OFF;
664  }
665 
666  break;
667  case SIM_DMA_CLOCK:
668  if (!SIM_GetDmaClockGate(SIM))
669  {
670  /* DMA is not clocked. */
671  returnCode = STATUS_MCU_GATED_OFF;
672  }
673 
674  break;
675  case SIM_MPU_CLOCK:
676  if (!SIM_GetMpuClockGate(SIM))
677  {
678  /* MPU is not clocked. */
679  returnCode = STATUS_MCU_GATED_OFF;
680  }
681 
682  break;
683  case SIM_MSCM_CLOCK:
684  if (!SIM_GetMscmClockGate(SIM))
685  {
686  /* MSCM is not clocked. */
687  returnCode = STATUS_MCU_GATED_OFF;
688  }
689 
690  break;
691  default:
692  returnCode = STATUS_UNSUPPORTED;
693  break;
694  }
695 
696  if (frequency != NULL)
697  {
698  *frequency = freq;
699  }
700 
701  return returnCode;
702 }
703 
704 /*FUNCTION**********************************************************************
705  *
706  * Function Name : CLOCK_SYS_GetPccClockFreq
707  * Description : This function returns the clock frequency of peripheral functional clock.
708  * END**************************************************************************/
710  uint32_t * frequency)
711 {
712  status_t returnCode = STATUS_SUCCESS;
713  uint32_t freq = 0U;
714 
715  /* Invalid PCC clock names. */
716  if ((clockName <= SIM_END_OF_CLOCKS) ||
717  (clockName == PCC_END_OF_BUS_CLOCKS) ||
718  (clockName == PCC_END_OF_SYS_CLOCKS) ||
719  (clockName == PCC_END_OF_SLOW_CLOCKS) ||
720  (clockName == PCC_END_OF_ASYNCH_DIV1_CLOCKS) ||
721  (clockName == PCC_END_OF_ASYNCH_DIV2_CLOCKS))
722  {
723  returnCode = STATUS_UNSUPPORTED;
724  }
725  else if (PCC_GetClockMode(PCC, clockName) == false)
726  {
727  /* Module is not clocked. */
728  returnCode = STATUS_MCU_GATED_OFF;
729  }
730  else
731  {
732  if ((peripheralFeaturesList[clockName] & HAS_INT_CLOCK_FROM_BUS_CLOCK) != 0U)
733  {
734  /* Check whether BUS CLOCK is clocked. */
736  }
737  else if ((peripheralFeaturesList[clockName] & HAS_INT_CLOCK_FROM_SYS_CLOCK) != 0U)
738  {
739  /* Check whether SYS CLOCK is clocked. */
741  }
742  else if ((peripheralFeaturesList[clockName] & HAS_INT_CLOCK_FROM_SLOW_CLOCK) != 0U)
743  {
744  /* Check whether SLOW CLOCK is clocked. */
746  }
747  else
748  { /* It's an issue in peripheral features list, each peripheral must have one interface clock. */
749  DEV_ASSERT(false);
750  }
751 
752  if (returnCode == STATUS_SUCCESS)
753  {
754  /* Check whether peripheral has protocol clock (functional clock) */
756  {
758  {
759  /* Check whether the functional clock is clocked */
761  }
762 
764  {
765  /* Check whether the functional clock is clocked */
767  }
768 
769  if (freq == 0U)
770  {
771  returnCode = STATUS_MCU_GATED_OFF;
772  }
773 
774  }
775  }
776 
777 
778 
779  }
780 
781  /* If frequency reference is provided, write this value */
782  if (frequency != NULL)
783  {
784  *frequency = freq;
785  }
786 
787  return returnCode;
788 }
789 
790 /*FUNCTION**********************************************************************
791  *
792  * Function Name : CLOCK_SYS_GetFreq
793  * Description : This function returns the frequency of a given clock
794  *
795  * Implements CLOCK_SYS_GetFreq_Activity
796  * END**************************************************************************/
798  uint32_t * frequency)
799 {
800  status_t returnCode;
801 
802  /* Frequency of the clock name from SCG */
803  if (clockName < SCG_END_OF_CLOCKS)
804  {
805  returnCode = CLOCK_SYS_GetScgClockFreq(clockName, frequency);
806  }
807  /* Frequency of the clock name from SIM */
808  else if (clockName < SIM_END_OF_CLOCKS)
809  {
810  returnCode = CLOCK_SYS_GetSimClockFreq(clockName, frequency);
811  }
812  /* Frequency of the clock name from PCC */
813  else if (clockName < PCC_END_OF_CLOCKS)
814  {
815  returnCode = CLOCK_SYS_GetPccClockFreq(clockName, frequency);
816  }
817  /* Invalid clock name */
818  else
819  {
820  returnCode = STATUS_UNSUPPORTED;
821  }
822 
823  return returnCode;
824 }
825 
826 /*FUNCTION**********************************************************************
827  * Function Name : CLOCK_SYS_GetPeripheralClock
828  * Description : Internal function used by CLOCK_SYS_GetFreq function
829  * END**************************************************************************/
830 
831 static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName,
832  scg_async_clock_type_t divider)
833 {
834  uint32_t frequency = 0;
835  uint32_t fracValue = PCC_GetFracValueSel(PCC, clockName);
836  uint32_t divValue = PCC_GetDividerSel(PCC, clockName);
837 
838  /* Check division factor */
839  if (((uint32_t)fracValue) <= ((uint32_t)divValue))
840  {
841  /* Check clock gate */
842  if (PCC_GetClockMode(PCC, clockName))
843  {
844  /* Check clock source */
845  switch (PCC_GetClockSourceSel(PCC, clockName))
846  {
847  case (uint32_t)CLK_SRC_SOSC:
848  frequency = CLOCK_SYS_GetSysAsyncFreq(SOSC_CLOCK, divider);
849  break;
850  case (uint32_t)CLK_SRC_SIRC:
851  frequency = CLOCK_SYS_GetSysAsyncFreq(SIRC_CLOCK, divider);
852  break;
853  case (uint32_t)CLK_SRC_FIRC:
854  frequency = CLOCK_SYS_GetSysAsyncFreq(FIRC_CLOCK, divider);
855  break;
856  case (uint32_t)CLK_SRC_SPLL:
857  frequency = CLOCK_SYS_GetSysAsyncFreq(SPLL_CLOCK, divider);
858  break;
859  default:
860  frequency = 0;
861  break;
862  }
863 
864  frequency = frequency / (divValue + 1U);
865  frequency = frequency * (fracValue + 1U);
866  }
867  }
868 
869  return frequency;
870 }
871 
872 /*FUNCTION**********************************************************************
873  * Function Name : CLOCK_SYS_GetCurrentRunMode
874  * Description : Internal function used by CLOCK_SYS_SetScgConfiguration function
875  * END**************************************************************************/
877 {
879 
880  /* Get the current running mode */
881  switch (SMC_GetCurrentRunningMode(SMC))
882  {
883  /* High speed run mode */
886  break;
887  /* Run mode */
890  break;
891  /* Very low power run mode */
894  break;
895  /* This should never happen - core has to be in some run mode to execute code */
896  default:
898  break;
899  }
900 
901  return mode;
902 }
903 
904 /*FUNCTION**********************************************************************
905  * Function Name : CLOCK_SYS_TransitionSystemClock
906  * Description : Internal function used by CLOCK_SYS_ConfigureTemporarySystemClock and
907  * CLOCK_SYS_ConfigureModulesFromScg functions
908  * END**************************************************************************/
910 {
911  scg_system_clock_mode_t run_mode;
912  status_t retValue = STATUS_SUCCESS;
913  uint32_t timeout;
914 
915  /* Check destination clock */
916  DEV_ASSERT(to_clk != NULL);
918 
919  /* Get & Convert Run mode from SMC to SCG defines*/
920  run_mode = CLOCK_SYS_GetCurrentRunMode();
921 
922  /* Check the current mode */
924 
925  /* Update run mode configuration */
926  retValue = CLOCK_SYS_SetSystemClockConfig(run_mode, to_clk);
927 
928  if (retValue == STATUS_SUCCESS)
929  {
930  /* Wait for system clock to transition. */
931 #ifdef ERRATA_E10777
932  timeout = 10U;
933 #else
934  timeout = 1U;
935 #endif
936 
937  do
938  {
939  timeout--;
940  }
941  while ((SCG_GetCurrentSystemClockSource(SCG) != ((uint32_t)to_clk->src)) && (timeout > 0U));
942 
943  if (timeout == 0U)
944  {
945  retValue = STATUS_TIMEOUT;
946  }
947  }
948 
949  return retValue;
950 }
951 
952 /*FUNCTION**********************************************************************
953  * Function Name : CLOCK_SYS_GetSimClkOutFreq
954  * Description : Internal function used by CLOCK_SYS_GetFreq function
955  * END**************************************************************************/
956 static uint32_t CLOCK_SYS_GetSimClkOutFreq(void)
957 {
958  uint32_t frequency;
959 
960  if (SIM_GetClockoutStatus(SIM))
961  {
962  switch (SIM_GetClockoutSelectorValue(SIM))
963  {
964  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SCG_CLKOUT):
965  frequency = CLOCK_SYS_GetScgClkOutFreq();
966  break;
967  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SOSC_DIV2_CLK):
969  break;
970  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SIRC_DIV2_CLK):
972  break;
973  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_FIRC_DIV2_CLK):
975  break;
976  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_SPLL_DIV2_CLK):
978  break;
979  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_LPO_128K_CLK):
980  frequency = LPO_128K_FREQUENCY;
981  break;
982  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_LPO_CLK):
983  frequency = CLOCK_SYS_GetLpoFreq();
984  break;
985  case ((uint32_t)SIM_CLKOUT_SEL_SYSTEM_RTC_CLK):
986  frequency = CLOCK_SYS_GetSimRtcClkFreq();
987  break;
988  default:
989  /* Invalid SIM CLKOUT selection.*/
990  frequency = 0U;
991  break;
992  }
993 
994  /* Apply Divide Ratio */
995  frequency /= (SIM_GetClockoutDividerValue(SIM) + 1U);
996  }
997  else
998  {
999  /* Output disabled. */
1000  frequency = 0U;
1001  }
1002 
1003  return frequency;
1004 }
1005 
1006 /*FUNCTION**********************************************************************
1007  * Function Name : CLOCK_SYS_GetScgClkOutFreq
1008  * Description : Internal function used by CLOCK_SYS_GetFreq function
1009  * END**************************************************************************/
1010 static uint32_t CLOCK_SYS_GetScgClkOutFreq(void)
1011 {
1012  uint32_t frequency;
1013 
1014  switch (SCG_GetClockoutSourceSel(SCG))
1015  {
1016  case ((uint32_t)SCG_CLOCKOUT_SRC_SCG_SLOW):
1018  break;
1019  case ((uint32_t)SCG_CLOCKOUT_SRC_SOSC):
1020  frequency = CLOCK_SYS_GetSysOscFreq();
1021  break;
1022  case ((uint32_t)SCG_CLOCKOUT_SRC_SIRC):
1023  frequency = CLOCK_SYS_GetSircFreq();
1024  break;
1025  case ((uint32_t)SCG_CLOCKOUT_SRC_FIRC):
1026  frequency = CLOCK_SYS_GetFircFreq();
1027  break;
1028  case ((uint32_t)SCG_CLOCKOUT_SRC_SPLL):
1029  frequency = CLOCK_SYS_GetSysPllFreq();
1030  break;
1031  default:
1032  /* Invalid SCG CLKOUT selection.*/
1033  frequency = 0U;
1034  break;
1035  }
1036 
1037  return frequency;
1038 }
1039 
1040 /*FUNCTION**********************************************************************
1041  * Function Name : CLOCK_SYS_GetSimRtcClkFreq
1042  * Description : Internal function used by CLOCK_SYS_GetFreq function
1043  * END**************************************************************************/
1045 {
1046  uint32_t frequency;
1047 
1048  /* Check RTCCLK Select */
1049  switch (SIM_GetRtcClkSrc(SIM))
1050  {
1051  case ((uint32_t)SIM_RTCCLK_SEL_SOSCDIV1_CLK):
1053  break;
1054  case ((uint32_t)SIM_RTCCLK_SEL_LPO_32K):
1055  frequency = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
1056  break;
1057  case ((uint32_t)SIM_RTCCLK_SEL_RTC_CLKIN):
1058  frequency = g_RtcClkInFreq;
1059  break;
1060  case ((uint32_t)SIM_RTCCLK_SEL_FIRCDIV1_CLK):
1062  break;
1063  default:
1064  /* Invalid RTCCLK selection.*/
1065  frequency = 0U;
1066  break;
1067  }
1068 
1069  return frequency;
1070 }
1071 
1072 /*FUNCTION**********************************************************************
1073  * Function Name : CLOCK_SYS_ConfigureSIRC
1074  * Description : Configures SIRC module based on provided configuration.
1075  * END**************************************************************************/
1076 static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t * sircConfig)
1077 {
1078  status_t status = STATUS_SUCCESS;
1079  scg_sirc_config_t sircDefaultConfig;
1080  const scg_sirc_config_t * sircCfg;
1081  uint32_t timeout;
1082 
1083  if (sircConfig == NULL)
1084  {
1085  sircDefaultConfig.enableInStop = false;
1086  sircDefaultConfig.enableInLowPower = true;
1087  sircDefaultConfig.locked = false;
1088 
1089  sircDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
1090  sircDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
1091 
1092  sircDefaultConfig.range = SCG_SIRC_RANGE_HIGH;
1093 
1094  sircCfg = &sircDefaultConfig;
1095  }
1096  else
1097  {
1098  sircCfg = sircConfig;
1099  }
1100 
1101  /* If clock is used by system, return error. */
1102  if (SCG_GetSircSystemClockMode(SCG))
1103  {
1104  status = STATUS_BUSY;
1105  }
1106  /* Disable SIRC */
1107  else
1108  {
1109  /* Clear LK bit field */
1110  SCG_ClearSircLock(SCG);
1111 
1112  /* Disable monitor, disable clock and clear error. */
1113  SCG_ClearSircControl(SCG);
1114  }
1115 
1116  /* Configure SIRC. */
1117  if (enable && (status == STATUS_SUCCESS))
1118  {
1119  /* Now start to set up SIRC clock. */
1120  /* Step 1. Setup dividers. */
1121  SCG_SetSircAsyncConfig(SCG, sircCfg->div1, sircCfg->div2);
1122 
1123  /* Step 2. Set SIRC configuration: frequency range. */
1124  SCG_SetSircConfiguration(SCG, sircCfg->range);
1125 
1126  /* Step 3. Set SIRC control: enable clock, configure source in STOP and VLP modes, configure lock feature. */
1127  SCG_SetSircControl(SCG, sircCfg->enableInStop, sircCfg->enableInLowPower, sircCfg->locked);
1128 
1129  /* Wait for SIRC to initialize */
1130  timeout = SIRC_STABILIZATION_TIMEOUT;
1131  while ((CLOCK_SYS_GetSircFreq() == 0U) && (timeout > 0U))
1132  {
1133  timeout--;
1134  }
1135 
1136  if (timeout == 0U)
1137  {
1138  status = STATUS_TIMEOUT;
1139  }
1140  }
1141 
1142  return status;
1143 }
1144 
1145 /*FUNCTION**********************************************************************
1146  * Function Name : CLOCK_SYS_ConfigureFIRC
1147  * Description : Configures FIRC module based on provided configuration.
1148  * END**************************************************************************/
1149 static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t * fircConfig)
1150 {
1151  status_t status = STATUS_SUCCESS;
1152  scg_firc_config_t fircDefaultConfig;
1153  const scg_firc_config_t * fircCfg;
1154  uint32_t timeout;
1155 
1156  if (fircConfig == NULL)
1157  {
1158  fircDefaultConfig.enableInStop = false;
1159  fircDefaultConfig.enableInLowPower = false;
1160  fircDefaultConfig.regulator = true;
1161  fircDefaultConfig.locked = false;
1162 
1163  fircDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
1164  fircDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
1165 
1166  fircDefaultConfig.range = SCG_FIRC_RANGE_48M;
1167 
1168  fircCfg = &fircDefaultConfig;
1169  }
1170  else
1171  {
1172  fircCfg = fircConfig;
1173  }
1174 
1175  /* If clock is used by system, return error. */
1176  if (SCG_GetFircSystemClockMode(SCG))
1177  {
1178  status = STATUS_BUSY;
1179  }
1180  /* Disable FIRC */
1181  else
1182  {
1183  /* Clear LK bit field */
1184  SCG_ClearFircLock(SCG);
1185 
1186  /* Disable monitor, disable clock and clear error. */
1187  SCG_ClearFircControl(SCG);
1188  }
1189 
1190  /* Configure FIRC. */
1191  if (enable && (status == STATUS_SUCCESS))
1192  {
1193  /* Now start to set up FIRC clock. */
1194  /* Step 1. Setup dividers. */
1195  SCG_SetFircAsyncConfig(SCG, fircCfg->div1, fircCfg->div2);
1196 
1197  /* Step 2. Set FIRC configuration. */
1198  SCG_SetFircConfiguration(SCG, fircCfg->range);
1199 
1200  /* Step 3. Enable clock, config regulator and locking feature. */
1201  SCG_SetFircControl(SCG, fircCfg->regulator, fircCfg->locked);
1202 
1203  /* Wait for FIRC to initialize */
1204  timeout = FIRC_STABILIZATION_TIMEOUT;
1205  while ((CLOCK_SYS_GetFircFreq() == 0U) && (timeout > 0U))
1206  {
1207  timeout--;
1208  }
1209 
1210  if (timeout == 0U)
1211  {
1212  status = STATUS_TIMEOUT;
1213  }
1214  }
1215 
1216  return status;
1217 }
1218 
1219 /*FUNCTION**********************************************************************
1220  * Function Name : CLOCK_SYS_ConfigureSOSC
1221  * Description : Configures SOSC module based on provided configuration.
1222  * END**************************************************************************/
1223 static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t * soscConfig)
1224 {
1225  status_t status = STATUS_SUCCESS;
1226  scg_sosc_config_t soscDefaultConfig;
1227  const scg_sosc_config_t * soscCfg;
1228  uint32_t timeout;
1229 
1230  if (soscConfig == NULL)
1231  {
1232  soscDefaultConfig.enableInStop = false;
1233  soscDefaultConfig.enableInLowPower = false;
1234 
1235  soscDefaultConfig.monitorMode = SCG_SOSC_MONITOR_DISABLE;
1236  soscDefaultConfig.locked = false;
1237 
1238  soscDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
1239  soscDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
1240 
1241  soscDefaultConfig.extRef = SCG_SOSC_REF_EXT;
1242  soscDefaultConfig.gain = SCG_SOSC_GAIN_LOW;
1243  soscDefaultConfig.range = SCG_SOSC_RANGE_LOW;
1244 
1245  soscCfg = &soscDefaultConfig;
1246  }
1247  else
1248  {
1249  soscCfg = soscConfig;
1250  }
1251 
1252  /* If clock is used by system, return error. */
1253  if (SCG_GetSoscSystemClockMode(SCG))
1254  {
1255  status = STATUS_BUSY;
1256  }
1257  /* Disable SOSC */
1258  else
1259  {
1260  /* Clear LK bit field */
1261  SCG_ClearSoscLock(SCG);
1262 
1263  /* Disable monitor, disable clock and clear error. */
1264  SCG_ClearSoscControl(SCG);
1265 
1266  g_xtal0ClkFreq = 0U;
1267  }
1268 
1269  /* Configure SOSC. */
1270  if (enable && (status == STATUS_SUCCESS))
1271  {
1272  /* Now start to set up OSC clock. */
1273  /* Step 1. Setup dividers. */
1274  SCG_SetSoscAsyncConfig(SCG, soscCfg->div1, soscCfg->div2);
1275 
1276  /* Step 2. Set OSC configuration. */
1277  SCG_SetSoscConfiguration(SCG, soscCfg->range, soscCfg->gain, soscCfg->extRef);
1278 
1279  /* Step 3. Enable clock, configure monitor, lock register. */
1280  switch (soscCfg->monitorMode)
1281  {
1283  {
1284  SCG_SetSoscControl(SCG, false, false, soscCfg->locked);
1285  }
1286  break;
1287  case SCG_SOSC_MONITOR_INT:
1288  {
1289  SCG_SetSoscControl(SCG, true, false, soscCfg->locked);
1290  }
1291  break;
1293  {
1294  SCG_SetSoscControl(SCG, true, true, soscCfg->locked);
1295  }
1296  break;
1297  default:
1298  /* Invalid monitor mode */
1299  DEV_ASSERT(false);
1300  break;
1301  }
1302 
1303  g_xtal0ClkFreq = soscCfg->freq;
1304 
1305  /* Wait for System OSC to initialize */
1306  timeout = SOSC_STABILIZATION_TIMEOUT;
1307  while ((CLOCK_SYS_GetSysOscFreq() == 0U) && (timeout > 0U))
1308  {
1309  timeout--;
1310  }
1311 
1312  if (timeout == 0U)
1313  {
1314  status = STATUS_TIMEOUT;
1315  }
1316  }
1317 
1318  return status;
1319 }
1320 
1321 /*FUNCTION**********************************************************************
1322  * Function Name : CLOCK_SYS_ConfigureSPLL
1323  * Description : Configures SPLL module based on provided configuration.
1324  * END**************************************************************************/
1325 static status_t CLOCK_SYS_ConfigureSPLL(bool enable, const scg_spll_config_t * spllConfig)
1326 {
1327  status_t status = STATUS_SUCCESS;
1328  scg_spll_config_t spllDefaultConfig;
1329  const scg_spll_config_t * spllCfg;
1330  uint32_t srcFreq, timeout;
1331 
1332  if (spllConfig == NULL)
1333  {
1334  spllDefaultConfig.enableInStop = false;
1335  spllDefaultConfig.monitorMode = SCG_SPLL_MONITOR_DISABLE;
1336  spllDefaultConfig.locked = false;
1337 
1338  spllDefaultConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
1339  spllDefaultConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
1340 
1341  spllDefaultConfig.prediv = 0;
1342  spllDefaultConfig.mult = 0;
1343  spllDefaultConfig.src = 0;
1344 
1345  spllCfg = &spllDefaultConfig;
1346  }
1347  else
1348  {
1349  spllCfg = spllConfig;
1350  }
1351 
1352  /* If clock is used by system, return error. */
1353  if (SCG_GetSpllSystemClockMode(SCG))
1354  {
1355  status = STATUS_BUSY;
1356  }
1357  /* Disable the SPLL. */
1358  else
1359  {
1360  /* Clear LK bit field */
1361  SCG_ClearSpllLock(SCG);
1362 
1363  /* Disable monitor, disable clock and clear error. */
1364  SCG_ClearSpllControl(SCG);
1365  }
1366 
1367  /* Configure SPLL. */
1368  if (enable && (status == STATUS_SUCCESS))
1369  {
1370  /* Get clock source frequency. */
1371  srcFreq = CLOCK_SYS_GetSysOscFreq();
1372  DEV_ASSERT(srcFreq != 0U);
1373 
1374  /* Pre-divider checking. */
1375  srcFreq /= (((uint32_t)spllCfg->prediv) + SCG_SPLL_PREDIV_BASE);
1376  DEV_ASSERT((srcFreq >= SCG_SPLL_REF_MIN) && (srcFreq <= SCG_SPLL_REF_MAX));
1377 
1378  /* Now start to set up PLL clock. */
1379  SCG_SetSpllAsyncConfig(SCG, spllCfg->div1, spllCfg->div2);
1380 
1381  /* Step 2. Set PLL configuration. */
1382  SCG_SetSpllConfiguration(SCG, spllCfg->prediv, spllCfg->mult);
1383 
1384  /* Step 3. Enable clock, configure monitor, lock register. */
1385  switch (spllCfg->monitorMode)
1386  {
1388  {
1389  SCG_SetSpllControl(SCG, false, false, spllCfg->locked);
1390  }
1391  break;
1392  case SCG_SOSC_MONITOR_INT:
1393  {
1394  SCG_SetSpllControl(SCG, true, false, spllCfg->locked);
1395  }
1396  break;
1398  {
1399  SCG_SetSpllControl(SCG, true, true, spllCfg->locked);
1400  }
1401  break;
1402  default:
1403  /* Invalid monitor mode */
1404  DEV_ASSERT(false);
1405  break;
1406  }
1407 
1408  /* Wait for System PLL to initialize */
1409  timeout = SPLL_STABILIZATION_TIMEOUT;
1410  while ((CLOCK_SYS_GetSysPllFreq() == 0U) && (timeout > 0U))
1411  {
1412  timeout--;
1413  }
1414 
1415  if (timeout == 0U)
1416  {
1417  status = STATUS_TIMEOUT;
1418  }
1419  }
1420 
1421  return status;
1422 }
1423 
1424 /*FUNCTION**********************************************************************
1425  * Function Name : CLOCK_SYS_ConfigureTemporarySystemClock
1426  * Description : Configures and transitions to a temporary system clock source: FIRC
1427  * END**************************************************************************/
1429 {
1430  status_t status = STATUS_SUCCESS;
1431  scg_system_clock_config_t sysClockConfig;
1433 
1434  /* If the current system clock source is not FIRC:
1435  * 1. Enable FIRC (if it's not enabled)
1436  * 2. Switch to FIRC.
1437  */
1438  if (SCG_GetCurrentSystemClockSource(SCG) != ((uint32_t)SCG_SYSTEM_CLOCK_SRC_FIRC))
1439  {
1440  /* If FIRC is not on, then FIRC is configured
1441  * with the default configuration */
1442  if (CLOCK_SYS_GetFircFreq() == 0UL)
1443  {
1444  status = CLOCK_SYS_ConfigureFIRC(true, NULL);
1445  }
1446 
1447  /* FIRC is enabled, transition the system clock source to FIRC. */
1448  if (status == STATUS_SUCCESS)
1449  {
1450  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
1451  sysClockConfig.divCore = tmpSysClk[TMP_FIRC_CLK][TMP_SYS_DIV];
1452  sysClockConfig.divBus = tmpSysClk[TMP_FIRC_CLK][TMP_BUS_DIV];
1453  sysClockConfig.divSlow = tmpSysClk[TMP_FIRC_CLK][TMP_SLOW_DIV];
1454  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1455  }
1456  }
1457 
1458  return status;
1459 }
1460 
1461 /*FUNCTION**********************************************************************
1462  * Function Name : CLOCK_SYS_ConfigureModulesFromScg
1463  * Description : Configures all modules from SCG (SIRC, FIRC, SOSC and SPLL)
1464  * END**************************************************************************/
1466 {
1467  status_t status = STATUS_SUCCESS;
1468  scg_system_clock_config_t sysClockConfig;
1469  const scg_system_clock_config_t * nextSysClockConfig;
1471 
1472  /* Configure all clock sources that are different from the
1473  * current system clock source FIRC (SIRC, SOSC, SPLL). */
1474  status = CLOCK_SYS_ConfigureSIRC(scgConfig->sircConfig.initialize, &scgConfig->sircConfig);
1475  if (status == STATUS_SUCCESS)
1476  {
1477  status = CLOCK_SYS_ConfigureSOSC(scgConfig->soscConfig.initialize, &scgConfig->soscConfig);
1478  if (status == STATUS_SUCCESS)
1479  {
1480  status = CLOCK_SYS_ConfigureSPLL(scgConfig->spllConfig.initialize,&scgConfig->spllConfig);
1481  }
1482  }
1483 
1484  /* Get the next system clock source */
1485  switch (CLOCK_SYS_GetCurrentRunMode())
1486  {
1488  {
1489  nextSysClockConfig = &scgConfig->clockModeConfig.rccrConfig;
1490  }
1491  break;
1493  {
1494  nextSysClockConfig = &scgConfig->clockModeConfig.vccrConfig;
1495  }
1496  break;
1498  {
1499  nextSysClockConfig = &scgConfig->clockModeConfig.hccrConfig;
1500  }
1501  break;
1502  default:
1503  DEV_ASSERT(false);
1504  nextSysClockConfig = NULL;
1505  break;
1506  }
1507 
1508  if (status == STATUS_SUCCESS)
1509  {
1510  /* The current system clock source is FIRC.
1511  * Verify whether the next system clock source is FIRC. */
1512  if (nextSysClockConfig->src == SCG_SYSTEM_CLOCK_SRC_FIRC)
1513  {
1514  /* If they are the same, search for a temporary system clock source
1515  * (use one of the following sources: SPLL, SOSC, SIRC)
1516  * Assume that a temporary clock is not found status = ERROR. */
1517  status = STATUS_ERROR;
1518 
1519  /* SPLL is enabled */
1520  if (scgConfig->spllConfig.initialize /* && (status == STATUS_ERROR) */)
1521  {
1522  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
1523  sysClockConfig.divCore = tmpSysClk[TMP_SPLL_CLK][TMP_SYS_DIV];
1524  sysClockConfig.divBus = tmpSysClk[TMP_SPLL_CLK][TMP_BUS_DIV];
1525  sysClockConfig.divSlow = tmpSysClk[TMP_SPLL_CLK][TMP_SLOW_DIV];
1526  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1527  }
1528 
1529  /* SOSC is enabled and SPLL configuration for system clock source is not valid */
1530  if (scgConfig->soscConfig.initialize && (status == STATUS_ERROR))
1531  {
1532  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
1533  sysClockConfig.divCore = tmpSysClk[TMP_SOSC_CLK][TMP_SYS_DIV];
1534  sysClockConfig.divBus = tmpSysClk[TMP_SOSC_CLK][TMP_BUS_DIV];
1535  sysClockConfig.divSlow = tmpSysClk[TMP_SOSC_CLK][TMP_SLOW_DIV];
1536  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1537  }
1538 
1539  /* SIRC is enabled and SOSC configuration for system clock source is not valid */
1540  if (scgConfig->sircConfig.initialize && (status == STATUS_ERROR))
1541  {
1542  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
1543  sysClockConfig.divCore = tmpSysClk[TMP_SIRC_CLK][TMP_SYS_DIV];
1544  sysClockConfig.divBus = tmpSysClk[TMP_SIRC_CLK][TMP_BUS_DIV];
1545  sysClockConfig.divSlow = tmpSysClk[TMP_SIRC_CLK][TMP_SLOW_DIV];
1546  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1547  }
1548 
1549  /* Transitioned to a temporary system clock source. */
1550  if (status == STATUS_SUCCESS)
1551  {
1552  /* Configure the remaining clock source (FIRC). */
1553  status = CLOCK_SYS_ConfigureFIRC(scgConfig->fircConfig.initialize, &scgConfig->fircConfig);
1554 
1555  if (status == STATUS_SUCCESS)
1556  {
1557  /* Transition to the next system clock source. */
1558  sysClockConfig.src = nextSysClockConfig->src;
1559  sysClockConfig.divCore = nextSysClockConfig->divCore;
1560  sysClockConfig.divBus = nextSysClockConfig->divBus;
1561  sysClockConfig.divSlow = nextSysClockConfig->divSlow;
1562  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1563  }
1564  }
1565  }
1566  else
1567  { /* Transition to the next system clock source. */
1568  sysClockConfig.src = nextSysClockConfig->src;
1569  sysClockConfig.divCore = nextSysClockConfig->divCore;
1570  sysClockConfig.divBus = nextSysClockConfig->divBus;
1571  sysClockConfig.divSlow = nextSysClockConfig->divSlow;
1572  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1573 
1574  if (status == STATUS_SUCCESS)
1575  {
1576  /* Configure the remaining clock source (FIRC) */
1577  status = CLOCK_SYS_ConfigureFIRC(scgConfig->fircConfig.initialize, &scgConfig->fircConfig);
1578  }
1579  }
1580  }
1581 
1582  return status;
1583 }
1584 
1585 /*FUNCTION**********************************************************************
1586  * Function Name : CLOCK_SYS_GetSystemClockFreq
1587  * Description : This function gets the SCG system clock frequency, these
1588  * clocks are used for core, platform, external and bus clock domains.
1589  * END**************************************************************************/
1591 {
1592  uint32_t freq;
1593 
1594 
1596 
1597  switch (SCG_GetCurrentSystemClockSource(SCG))
1598  {
1599  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_OSC):
1600  freq = CLOCK_SYS_GetSysOscFreq();
1601  break;
1602  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SIRC):
1603  freq = CLOCK_SYS_GetSircFreq();
1604  break;
1605  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_FIRC):
1606  freq = CLOCK_SYS_GetFircFreq();
1607  break;
1608  case ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_PLL):
1609  freq = CLOCK_SYS_GetSysPllFreq();
1610  break;
1611  default:
1612  freq = 0U;
1613  break;
1614  }
1615 
1616  freq /= (SCG_GetCurrentCoreClockDividerRatio(SCG) + 1U);
1617 
1618  switch (type)
1619  {
1620  case SCG_SYSTEM_CLOCK_CORE:
1621  /* Intentionally left blank */
1622  break;
1623  case SCG_SYSTEM_CLOCK_BUS:
1624  freq /= (SCG_GetCurrentBusClockDividerRatio(SCG) + 1U);
1625  break;
1626  case SCG_SYSTEM_CLOCK_SLOW:
1627  freq /= (SCG_GetCurrentSlowClockDividerRatio(SCG) + 1U);
1628  break;
1629  default:
1630  freq = 0U;
1631  break;
1632  }
1633 
1634  return freq;
1635 }
1636 
1637 /*FUNCTION**********************************************************************
1638  * Function Name : CLOCK_SYS_SetSystemClockConfig
1639  * Description : This function sets the system configuration for the specified mode.
1640  * END**************************************************************************/
1642  scg_system_clock_config_t const * config)
1643 {
1644  status_t status = STATUS_SUCCESS;
1645  uint32_t srcFreq = 0U;
1646 
1647  /* The maximum clock frequencies in all power modes */
1648  static const uint32_t maxClocksFreq[MAX_FREQ_MODES_NO][MAX_FREQ_CLK_NO] = CLOCK_MAX_FREQUENCIES;
1649  uint32_t maxFreqRunMode = 0U;
1650  const uint32_t sysFreqMul = ((uint32_t)config->divCore) + 1UL;
1651  const uint32_t busFreqMul = (((uint32_t)config->divCore) + 1UL) * (((uint32_t)config->divBus) + 1UL);
1652  const uint32_t slowFreqMul = (((uint32_t)config->divCore) + 1UL) * (((uint32_t)config->divSlow) + 1UL);
1653 
1654 
1656 
1657  switch (config->src)
1658  {
1660  srcFreq = CLOCK_SYS_GetSysOscFreq();
1661  break;
1663  srcFreq = CLOCK_SYS_GetSircFreq();
1664  break;
1666  srcFreq = CLOCK_SYS_GetFircFreq();
1667  break;
1669  srcFreq = CLOCK_SYS_GetSysPllFreq();
1670  break;
1671  default:
1672  srcFreq = 0U;
1673  break;
1674  }
1675 
1676  switch (mode)
1677  {
1679  maxFreqRunMode = MAX_FREQ_RUN;
1680  break;
1683  maxFreqRunMode = MAX_FREQ_VLPR;
1684  break;
1686  maxFreqRunMode = MAX_FREQ_HSRUN;
1687  break;
1688  default:
1689  /* Invalid mode */
1690  DEV_ASSERT(false);
1691  break;
1692  }
1693 
1694  /* Verify the frequencies of sys, bus and slow clocks. */
1695  if ((srcFreq > (sysFreqMul * maxClocksFreq[maxFreqRunMode][MAX_FREQ_SYS_CLK])) || /* Sys(core) clock */
1696  (srcFreq > (busFreqMul * maxClocksFreq[maxFreqRunMode][MAX_FREQ_BUS_CLK])) || /* Bus clock */
1697  (srcFreq > (slowFreqMul * maxClocksFreq[maxFreqRunMode][MAX_FREQ_SLOW_CLK]))) /* Slow clock */
1698  {
1699  /* Configuration for the next system clock source is not valid. */
1700  status = STATUS_ERROR;
1701  }
1702 
1703  if (status == STATUS_SUCCESS)
1704  {
1705  switch (mode)
1706  {
1708  SCG_SetRunClockControl(SCG, (uint32_t)config->src, (uint32_t)config->divCore, (uint32_t)config->divBus, (uint32_t)config->divSlow);
1709  break;
1712  SCG_SetVlprClockControl(SCG, (uint32_t)config->src, (uint32_t)config->divCore, (uint32_t)config->divBus, (uint32_t)config->divSlow);
1713  break;
1715  SCG_SetHsrunClockControl(SCG, (uint32_t)config->src, (uint32_t)config->divCore, (uint32_t)config->divBus, (uint32_t)config->divSlow);
1716  break;
1717  default:
1718  /* Invalid mode */
1719  DEV_ASSERT(false);
1720  break;
1721  }
1722  }
1723 
1724  return status;
1725 }
1726 
1727 /*FUNCTION**********************************************************************
1728  * Function Name : CLOCK_SYS_GetSysAsyncFreq
1729  * Description : Gets SCG asynchronous clock frequency from a clock source.
1730  * END**************************************************************************/
1731 static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource,
1733 {
1734  uint32_t freq, div = 0U;
1735 
1736  switch (type)
1737  {
1738  case SCG_ASYNC_CLOCK_DIV1:
1739  {
1740  switch (clockSource)
1741  {
1742  case FIRC_CLOCK:
1743  {
1744  freq = CLOCK_SYS_GetFircFreq();
1745  div = SCG_GetFircFirstAsyncDivider(SCG);
1746  }
1747  break;
1748  case SIRC_CLOCK:
1749  {
1750  freq = CLOCK_SYS_GetSircFreq();
1751  div = SCG_GetSircFirstAsyncDivider(SCG);
1752  }
1753  break;
1754  case SOSC_CLOCK:
1755  {
1756  freq = CLOCK_SYS_GetSysOscFreq();
1757  div = SCG_GetSoscFirstAsyncDivider(SCG);
1758  }
1759  break;
1760  case SPLL_CLOCK:
1761  {
1762  freq = CLOCK_SYS_GetSysPllFreq();
1763  div = SCG_GetSpllFirstAsyncDivider(SCG);
1764  }
1765  break;
1766  default:
1767  {
1768  /* Invalid clock source type */
1769  freq = 0U;
1770  DEV_ASSERT(false);
1771  }
1772  break;
1773  }
1774  }
1775  break;
1776  case SCG_ASYNC_CLOCK_DIV2:
1777  {
1778  switch (clockSource)
1779  {
1780  case FIRC_CLOCK:
1781  {
1782  freq = CLOCK_SYS_GetFircFreq();
1783  div = SCG_GetFircSecondAsyncDivider(SCG);
1784  }
1785  break;
1786  case SIRC_CLOCK:
1787  {
1788  freq = CLOCK_SYS_GetSircFreq();
1789  div = SCG_GetSircSecondAsyncDivider(SCG);
1790  }
1791  break;
1792  case SOSC_CLOCK:
1793  {
1794  freq = CLOCK_SYS_GetSysOscFreq();
1795  div = SCG_GetSoscSecondAsyncDivider(SCG);
1796  }
1797  break;
1798  case SPLL_CLOCK:
1799  {
1800  freq = CLOCK_SYS_GetSysPllFreq();
1801  div = SCG_GetSpllSecondAsyncDivider(SCG);
1802  }
1803  break;
1804  default:
1805  {
1806  /* Invalid clock source type */
1807  freq = 0U;
1808  DEV_ASSERT(false);
1809  }
1810  break;
1811  }
1812  }
1813  break;
1814  default:
1815  /* Invalid async clock source */
1816  freq = 0U;
1817  DEV_ASSERT(false);
1818  break;
1819  }
1820 
1821 
1822  if (div != 0U)
1823  {
1824  freq = (freq >> (div - 1U));
1825  }
1826  else /* Output disabled. */
1827  {
1828  freq = 0U;
1829  }
1830 
1831  return freq;
1832 }
1833 
1834 /*FUNCTION**********************************************************************
1835  * Function Name : CLOCK_SYS_GetSysOscFreq
1836  * Description : Gets SCG System OSC clock frequency (SYSOSC).
1837  * END**************************************************************************/
1838 static uint32_t CLOCK_SYS_GetSysOscFreq(void)
1839 {
1840  uint32_t retValue;
1841  if (SCG_GetSoscStatus(SCG)) /* System OSC clock is valid. */
1842  {
1843  retValue = g_xtal0ClkFreq;
1844  }
1845  else
1846  {
1847  retValue = 0U;
1848  }
1849 
1850  return retValue;
1851 }
1852 
1853 /*FUNCTION**********************************************************************
1854  * Function Name : CLOCK_SYS_GetSircFreq
1855  * Description : Gets SCG Slow IRC clock frequency (SIRC).
1856  * END**************************************************************************/
1857 static uint32_t CLOCK_SYS_GetSircFreq(void)
1858 {
1859  uint32_t retValue;
1860 
1861  if (SCG_GetSircStatus(SCG)) /* SIRC is valid. */
1862  {
1863  retValue = (SCG_GetSircRange(SCG) != 0U) ? FEATURE_SCG_SIRC_HIGH_RANGE_FREQ : FEATURE_SCG_SIRC_LOW_RANGE_FREQ;
1864  }
1865  else
1866  {
1867  retValue = 0U;
1868  }
1869 
1870  return retValue;
1871 }
1872 
1873 /*FUNCTION**********************************************************************
1874  * Function Name : CLOCK_SYS_GetFircFreq
1875  * Description : Gets SCG Fast IRC clock frequency (FIRC).
1876  * END**************************************************************************/
1877 static uint32_t CLOCK_SYS_GetFircFreq(void)
1878 {
1879  uint32_t retValue;
1880 
1881  static const uint32_t fircFreq[] = {
1883  };
1884 
1885  if (SCG_GetFircStatus(SCG)) /* FIRC is valid. */
1886  {
1887  retValue = fircFreq[SCG_GetFircRange(SCG)];
1888  }
1889  else
1890  {
1891  retValue = 0U;
1892  }
1893 
1894  return retValue;
1895 }
1896 
1897 /*FUNCTION**********************************************************************
1898  * Function Name : CLOCK_SYS_GetSysPllFreq
1899  * Description : Gets SCG System PLL clock frequency (SYSPLL).
1900  * END**************************************************************************/
1901 static uint32_t CLOCK_SYS_GetSysPllFreq(void)
1902 {
1903  uint32_t freq, retValue;
1904 
1905  if (SCG_GetSpllStatus(SCG)) /* System PLL is valid. */
1906  {
1907  /* Get System OSC. frequency. */
1908  freq = CLOCK_SYS_GetSysOscFreq();
1909 
1910  if (freq != 0U) /* If source is valid. */
1911  {
1912  freq /= (SCG_GetSpllPredivider(SCG) + SCG_SPLL_PREDIV_BASE); /* Pre-divider. */
1913  freq *= (SCG_GetSpllMultiplier(SCG) + SCG_SPLL_MULT_BASE); /* Multiplier. */
1914  freq = freq >> 1U; /* Divide VCO by 2. */
1915  }
1916 
1917  retValue = freq;
1918  }
1919  else
1920  {
1921  retValue = 0U;
1922  }
1923 
1924  return retValue;
1925 }
1926 
1927 /*FUNCTION**********************************************************************
1928  * Function Name : CLOCK_SYS_GetLpoFreq
1929  * Description : Gets SIM LPO clock frequency (LPO).
1930  * END**************************************************************************/
1931 static uint32_t CLOCK_SYS_GetLpoFreq(void)
1932 {
1933  uint32_t freq = 0U;
1934 
1935  switch (SIM_GetLpoClkSelectorValue(SIM))
1936  {
1937  case 0U: /* SIM_LPO_CLK_SEL_LPO_128K */
1938  freq = LPO_128K_FREQUENCY;
1939  break;
1940  case 1U: /* SIM_LPO_CLK_SEL_NO_CLOCK: */
1941  freq = 0U;
1942  break;
1943  case 2U: /* SIM_LPO_CLK_SEL_LPO_32K: */
1944  freq = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
1945  break;
1946  case 3U: /* SIM_LPO_CLK_SEL_LPO_1K: */
1947  freq = SIM_GetLpo32KStatus(SIM) ? LPO_32K_FREQUENCY : 0UL;
1948  break;
1949  default:
1950  /* Invalid LPOCLKSEL selection.*/
1951  DEV_ASSERT(false);
1952  break;
1953  }
1954 
1955  return freq;
1956 }
1957 
1958 /*FUNCTION**********************************************************************
1959  * Function Name : CLOCK_SYS_TransitionToTmpSysClk
1960  * Description : Transition to a temporary system clock
1961  * END**************************************************************************/
1963 {
1964  scg_system_clock_config_t sysClockConfig;
1965 
1967 
1968  status_t status = STATUS_ERROR;
1969 
1970  /* SPLL is functional, and is not the current system clock source */
1971  if ((CLOCK_SYS_GetSysPllFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SYS_PLL) /* && (status == STATUS_ERROR) */)
1972  {
1973  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
1974  sysClockConfig.divCore = tmpSysClk[TMP_SPLL_CLK][TMP_SYS_DIV];
1975  sysClockConfig.divBus = tmpSysClk[TMP_SPLL_CLK][TMP_BUS_DIV];
1976  sysClockConfig.divSlow = tmpSysClk[TMP_SPLL_CLK][TMP_SLOW_DIV];
1977  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1978  }
1979 
1980  /* FIRC is functional, it is not the current system clock source, no valid source has been found yet. */
1981  if ((CLOCK_SYS_GetFircFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_FIRC) && (status != STATUS_SUCCESS))
1982  {
1983  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
1984  sysClockConfig.divCore = tmpSysClk[TMP_FIRC_CLK][TMP_SYS_DIV];
1985  sysClockConfig.divBus = tmpSysClk[TMP_FIRC_CLK][TMP_BUS_DIV];
1986  sysClockConfig.divSlow = tmpSysClk[TMP_FIRC_CLK][TMP_SLOW_DIV];
1987  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1988  }
1989 
1990 
1991  /* SOSC is functional, it is not the current system clock source, no valid source has been found yet. */
1992  if ((CLOCK_SYS_GetSysOscFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SYS_OSC) && (status != STATUS_SUCCESS))
1993  {
1994  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
1995  sysClockConfig.divCore = tmpSysClk[TMP_SOSC_CLK][TMP_SYS_DIV];
1996  sysClockConfig.divBus = tmpSysClk[TMP_SOSC_CLK][TMP_BUS_DIV];
1997  sysClockConfig.divSlow = tmpSysClk[TMP_SOSC_CLK][TMP_SLOW_DIV];
1998  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
1999  }
2000 
2001  /* SIRC is functional, it is not the current system clock source, no valid source has been found yet. */
2002  if ((CLOCK_SYS_GetSircFreq() != 0U) && (currentSysClkSrc != SCG_SYSTEM_CLOCK_SRC_SIRC) && (status != STATUS_SUCCESS))
2003  {
2004  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
2005  sysClockConfig.divCore = tmpSysClk[TMP_SIRC_CLK][TMP_SYS_DIV];
2006  sysClockConfig.divBus = tmpSysClk[TMP_SIRC_CLK][TMP_BUS_DIV];
2007  sysClockConfig.divSlow = tmpSysClk[TMP_SIRC_CLK][TMP_SLOW_DIV];
2008  status = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2009  }
2010 
2011  return status;
2012 }
2013 
2014 /*FUNCTION**********************************************************************
2015  * Function Name : CLOCK_SYS_TransitionToTmpSysClk
2016  * Description : Transition to a temporary system clock
2017  * END**************************************************************************/
2019 {
2021  static const scg_system_clock_div_t sysClkDivMappings[((uint32_t) SCG_SYSTEM_CLOCK_DIV_BY_16)+ 1U] = {
2030 
2031  /* Save the current system clock source configuration */
2032  sysClockConfig->src = sysClkSrcMappings[SCG_GetCurrentSystemClockSource(SCG)];
2033  sysClockConfig->divBus = sysClkDivMappings[SCG_GetCurrentBusClockDividerRatio(SCG)];
2034  sysClockConfig->divCore = sysClkDivMappings[SCG_GetCurrentCoreClockDividerRatio(SCG)];
2035  sysClockConfig->divSlow = sysClkDivMappings[SCG_GetCurrentSlowClockDividerRatio(SCG)];
2036 }
2037 
2038 /*FUNCTION**********************************************************************
2039  *
2040  * Function Name : CLOCK_DRV_EnablePeripheralClock
2041  * Description : This function enables a peripheral clock
2042  *
2043  * Implements CLOCK_DRV_EnablePeripheralClock_Activity
2044  * END**************************************************************************/
2046  const periph_clk_config_t * periphClkConfig)
2047 {
2048  uint32_t source, divider, multiplier;
2049  periph_clk_config_t defaultPeriphClkCfg;
2050  const periph_clk_config_t * periphClkCfg;
2051 
2052  /* Configuration is not provided, a default one will be used. */
2053  if (periphClkConfig == NULL)
2054  {
2055  defaultPeriphClkCfg.source = FIRC_CLK_SRC;
2056  defaultPeriphClkCfg.divider = DO_NOT_DIVIDE;
2057  defaultPeriphClkCfg.multiplier = DO_NOT_MULTIPLY;
2058  periphClkCfg = &defaultPeriphClkCfg;
2059  }
2060  else
2061  {
2062  periphClkCfg = periphClkConfig;
2063  }
2064 
2065  /* Check that clock gating is configurable from PCC */
2066  if ((peripheralFeaturesList[clockName] & HAS_CLOCK_GATING_IN_SIM) == 0U)
2067  {
2068  /* Check that protocol clock is supported by the peripheral corresponding to the clock name */
2070  ((uint32_t) periphClkCfg->source) : 0U;
2071 
2072  /* Check that multiplier clock is supported. */
2073  multiplier = ((peripheralFeaturesList[clockName] & HAS_MULTIPLIER) != 0U) ?
2074  ((uint32_t) periphClkCfg->multiplier) : 0U;
2075 
2076  /* Check that divider clock is supported. */
2077  divider = ((peripheralFeaturesList[clockName] & HAS_DIVIDER) != 0U) ?
2078  ((uint32_t) periphClkCfg->divider) : 0U;
2079 
2080  /* Disable the peripheral clock */
2081  PCC_SetClockMode(PCC, clockName, false);
2082 
2083  /* Set peripheral clock control */
2084  PCC_SetPeripheralClockControl(PCC, clockName, true, source, divider, multiplier);
2085  }
2086  else
2087  {
2088  switch (clockName)
2089  {
2090  case SIM_MSCM_CLOCK:
2091  SIM_SetMscmClockGate(SIM, true);
2092  break;
2093 
2094  case SIM_MPU_CLOCK:
2095  SIM_SetMpuClockGate(SIM, true);
2096  break;
2097 
2098  case SIM_DMA_CLOCK:
2099  SIM_SetDmaClockGate(SIM, true);
2100  break;
2101 
2102  case SIM_ERM_CLOCK:
2103  SIM_SetErmClockGate(SIM, true);
2104  break;
2105 
2106  case SIM_EIM_CLOCK:
2107  SIM_SetEimClockGate(SIM, true);
2108  break;
2109  default:
2110  /* Invalid clock name */
2111  DEV_ASSERT(false);
2112  break;
2113  }
2114  }
2115 }
2116 
2117 /*FUNCTION**********************************************************************
2118  *
2119  * Function Name : CLOCK_DRV_DisablePeripheralClock
2120  * Description : This function disables a peripheral clock
2121  *
2122  * Implements CLOCK_DRV_DisablePeripheralClock_Activity
2123  * END**************************************************************************/
2125 {
2126  /* Check that clock gating is configurable from PCC */
2127  if ((peripheralFeaturesList[clockName] & HAS_CLOCK_GATING_IN_SIM) == 0U)
2128  {
2129  /* Disable the peripheral clock from PCC */
2130  PCC_SetClockMode(PCC, clockName, false);
2131  }
2132  /* Clock gating is implemented in PCC */
2133  else
2134  {
2135  switch (clockName)
2136  {
2137  case SIM_MSCM_CLOCK:
2138  SIM_SetMscmClockGate(SIM, false);
2139  break;
2140 
2141  case SIM_MPU_CLOCK:
2142  SIM_SetMpuClockGate(SIM, false);
2143  break;
2144 
2145  case SIM_DMA_CLOCK:
2146  SIM_SetDmaClockGate(SIM, false);
2147  break;
2148 
2149  case SIM_ERM_CLOCK:
2150  SIM_SetErmClockGate(SIM, false);
2151  break;
2152 
2153  case SIM_EIM_CLOCK:
2154  SIM_SetEimClockGate(SIM, false);
2155  break;
2156  default:
2157  /* Invalid clock name */
2158  DEV_ASSERT(false);
2159  break;
2160  }
2161  }
2162 }
2163 
2164 /*FUNCTION**********************************************************************
2165  *
2166  * Function Name : CLOCK_DRV_SetSystemClock
2167  * Description : This function configures the system clocks (core, bus and flash clocks).
2168  *
2169  * Implements CLOCK_DRV_SetSystemClock_Activity
2170  * END**************************************************************************/
2172  const sys_clk_config_t * sysClkConfig)
2173 {
2174  status_t retCode = STATUS_SUCCESS;
2175 
2176  scg_system_clock_mode_t sysClockMode, currentSysClockMode = CLOCK_SYS_GetCurrentRunMode();
2177  scg_system_clock_config_t sysClockConfig;
2178 
2182 
2183  /* The power mode is not provided, the current one will be used by default. */
2184  if (mode == NULL)
2185  {
2186  sysClockMode = currentSysClockMode;
2187  }
2188  else
2189  {
2190  switch (*mode)
2191  {
2192  /* High speed run mode */
2193  case HSRUN_MODE:
2194  sysClockMode = SCG_SYSTEM_CLOCK_MODE_HSRUN;
2195  break;
2196  /* Run mode */
2197  case RUN_MODE:
2198  sysClockMode = SCG_SYSTEM_CLOCK_MODE_RUN;
2199  break;
2200  /* Very low power run mode */
2201  case VLPR_MODE:
2202  sysClockMode = SCG_SYSTEM_CLOCK_MODE_VLPR;
2203  break;
2204  /* This should never happen - input power mode is invalid */
2205  default:
2206  sysClockMode = SCG_SYSTEM_CLOCK_MODE_NONE;
2207  DEV_ASSERT(false);
2208  break;
2209  }
2210  }
2211 
2212  /* System clock configuration is not provided, a default one will be used. */
2213  if (sysClkConfig == NULL)
2214  {
2215  /* Find a valid clock source. */
2216  if (CLOCK_SYS_GetFircFreq() != 0U)
2217  {
2218  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_FIRC;
2219  sysClockConfig.divCore = defSysClk[TMP_FIRC_CLK][TMP_SYS_DIV];
2220  sysClockConfig.divBus = defSysClk[TMP_FIRC_CLK][TMP_BUS_DIV];
2221  sysClockConfig.divSlow = defSysClk[TMP_FIRC_CLK][TMP_SLOW_DIV];
2222  }
2223  else if (CLOCK_SYS_GetSysPllFreq() != 0U)
2224  {
2225  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_PLL;
2226  sysClockConfig.divCore = defSysClk[TMP_SPLL_CLK][TMP_SYS_DIV];
2227  sysClockConfig.divBus = defSysClk[TMP_SPLL_CLK][TMP_BUS_DIV];
2228  sysClockConfig.divSlow = defSysClk[TMP_SPLL_CLK][TMP_SLOW_DIV];
2229  }
2230  else if (CLOCK_SYS_GetSysOscFreq() != 0U)
2231  {
2232  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SYS_OSC;
2233  sysClockConfig.divCore = defSysClk[TMP_SOSC_CLK][TMP_SYS_DIV];
2234  sysClockConfig.divBus = defSysClk[TMP_SOSC_CLK][TMP_BUS_DIV];
2235  sysClockConfig.divSlow = defSysClk[TMP_SOSC_CLK][TMP_SLOW_DIV];
2236  }
2237  else if (CLOCK_SYS_GetSircFreq() != 0U)
2238  {
2239  sysClockConfig.src = SCG_SYSTEM_CLOCK_SRC_SIRC;
2240  sysClockConfig.divCore = defSysClk[TMP_SIRC_CLK][TMP_SYS_DIV];
2241  sysClockConfig.divBus = defSysClk[TMP_SIRC_CLK][TMP_BUS_DIV];
2242  sysClockConfig.divSlow = defSysClk[TMP_SIRC_CLK][TMP_SLOW_DIV];
2243  }
2244  else
2245  {
2246  /* Can't reach this point, at least one clock source is functional.
2247  * This code is written to avoid MISRA 15.7 (no 'else' at end of 'if ... else if' chain) */
2248  DEV_ASSERT(false);
2249  }
2250  }
2251  else
2252  {
2253  /* The system clock source from input configuration structure must be valid. */
2254  DEV_ASSERT((CLOCK_SYS_GetSircFreq() != 0U) || (sysClkConfig->src != SYS_CLK_SIRC));
2255  DEV_ASSERT((CLOCK_SYS_GetFircFreq() != 0U) || (sysClkConfig->src != SYS_CLK_FIRC));
2256  DEV_ASSERT((CLOCK_SYS_GetSysOscFreq() != 0U) || (sysClkConfig->src != SYS_CLK_SOSC));
2257  DEV_ASSERT((CLOCK_SYS_GetSysPllFreq() != 0U) || (sysClkConfig->src != SYS_CLK_SPLL));
2258 
2259  sysClockConfig.src = sysClkSrcMappings[sysClkConfig->src];
2260  sysClockConfig.divCore = sysClkDivMappings[sysClkConfig->core];
2261  sysClockConfig.divBus = sysClkDivMappings[sysClkConfig->bus];
2262  sysClockConfig.divSlow = sysClkDivMappings[sysClkConfig->slow];
2263  }
2264 
2265  /* System clock is configured in the current mode,
2266  * set configuration and wait until the system clock is changed. */
2267  if (sysClockMode == currentSysClockMode)
2268  {
2269  retCode = CLOCK_SYS_TransitionSystemClock(&sysClockConfig);
2270  }
2271  /* System clock is not configured in the current mode, just set configuration. */
2272  else
2273  {
2274  retCode = CLOCK_SYS_SetSystemClockConfig(sysClockMode,&sysClockConfig);
2275  }
2276  return retCode;
2277 }
2278 
2279 /*FUNCTION**********************************************************************
2280  *
2281  * Function Name : CLOCK_DRV_SetSirc
2282  * Description : This function configures SIRC clock source
2283  *
2284  * Implements CLOCK_DRV_SetSirc_Activity
2285  * END**************************************************************************/
2287  const sirc_config_t * sircConfig)
2288 {
2289  status_t retCode = STATUS_SUCCESS;
2290  scg_sirc_config_t scgSircConfig;
2291  bool revertTmpSysClkTransition = false;
2292  scg_system_clock_config_t currentSysClockConfig;
2293 
2294  static const scg_sirc_range_t sircRangeMappings[(uint32_t)SIRC_RANGES_MAX] = {SCG_SIRC_RANGE_LOW,SCG_SIRC_RANGE_HIGH};
2295 
2296  /* Check whether the current system clock source is SIRC */
2297  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SIRC))
2298  {
2299  if (enable == false)
2300  {
2301  /* Can't disable SIRC, it's used as system clock source */
2302  retCode = STATUS_ERROR;
2303  }
2304  else
2305  {
2306  /* Save the current system clock source configuration */
2307  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
2308 
2309  /* Transition to a temporary system clock source */
2311 
2312  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
2313  }
2314  }
2315 
2316  if (retCode == STATUS_SUCCESS)
2317  {
2318  if (sircConfig == NULL)
2319  {
2320  retCode = CLOCK_SYS_ConfigureSIRC(enable, NULL);
2321  }
2322  else
2323  {
2324  /* Check VLP modes */
2325  if (((((uint32_t)sircConfig->modes) & ((uint32_t)VLPR_MODE)) != 0U) || ((((uint32_t)sircConfig->modes) & ((uint32_t)VLPS_MODE)) != 0U))
2326  {
2327  scgSircConfig.enableInLowPower = true;
2328  }
2329  else
2330  {
2331  scgSircConfig.enableInLowPower = false;
2332  }
2333 
2334  /* Check STOP mode. */
2335  if (((((uint32_t)sircConfig->modes) & ((uint32_t)STOP_MODE)) != 0U))
2336  {
2337  scgSircConfig.enableInStop = true;
2338  }
2339  else
2340  {
2341  scgSircConfig.enableInStop = false;
2342  }
2343 
2344  scgSircConfig.locked = false;
2345 
2346  scgSircConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2347  scgSircConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2348 
2349  scgSircConfig.range = sircRangeMappings[sircConfig->range];
2350 
2351  retCode = CLOCK_SYS_ConfigureSIRC(enable, &scgSircConfig);
2352  }
2353 
2354  /* If system clock source was SIRC and SIRC has been set successfully,
2355  * then transition back to SIRC */
2356  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
2357  {
2358  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
2359  }
2360  }
2361 
2362  return retCode;
2363 }
2364 
2365 /*FUNCTION**********************************************************************
2366  *
2367  * Function Name : CLOCK_DRV_SetFirc
2368  * Description : This function configures FIRC clock source
2369  *
2370  * Implements CLOCK_DRV_SetFirc_Activity
2371  * END**************************************************************************/
2373  const firc_config_t * fircConfig)
2374 {
2375  status_t retCode = STATUS_SUCCESS;
2376  scg_firc_config_t scgFircConfig;
2377  bool revertTmpSysClkTransition = false;
2378  scg_system_clock_config_t currentSysClockConfig;
2379 
2381 
2382  /* Check whether the current system clock source is FIRC */
2383  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_FIRC))
2384  {
2385  if (enable == false)
2386  {
2387  /* Can't disable FIRC, it's used as system clock source. */
2388  retCode = STATUS_ERROR;
2389  }
2390  else
2391  {
2392  /* Save the current system clock source configuration. */
2393  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
2394 
2395  /* Transition to a temporary system clock source. */
2397 
2398  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
2399  }
2400  }
2401 
2402  if (retCode == STATUS_SUCCESS)
2403  {
2404  if (fircConfig == NULL)
2405  {
2406  retCode = CLOCK_SYS_ConfigureFIRC(enable, NULL);
2407  }
2408  else
2409  {
2410  /* Check VLP modes */
2411  if (((((uint32_t)fircConfig->modes) & ((uint32_t)VLPR_MODE)) != 0U) || ((((uint32_t)fircConfig->modes) & ((uint32_t)VLPS_MODE)) != 0U))
2412  {
2413  scgFircConfig.enableInLowPower = true;
2414  }
2415  else
2416  {
2417  scgFircConfig.enableInLowPower = false;
2418  }
2419 
2420  /* Check STOP mode. */
2421  if (((((uint32_t)fircConfig->modes) & ((uint32_t)STOP_MODE)) != 0U))
2422  {
2423  scgFircConfig.enableInStop = true;
2424  }
2425  else
2426  {
2427  scgFircConfig.enableInStop = false;
2428  }
2429 
2430  scgFircConfig.locked = false;
2431 
2432  scgFircConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2433  scgFircConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2434 
2435  scgFircConfig.range = fircRangeMappings[fircConfig->range];
2436  scgFircConfig.regulator = fircConfig->regulator;
2437 
2438  retCode = CLOCK_SYS_ConfigureFIRC(enable, &scgFircConfig);
2439  }
2440 
2441  /* If system clock source was FIRC and FIRC has been set successfully,
2442  * then transition back to FIRC */
2443  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
2444  {
2445  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
2446  }
2447  }
2448 
2449  return retCode;
2450 }
2451 
2452 /*FUNCTION**********************************************************************
2453  *
2454  * Function Name : CLOCK_DRV_SetSosc
2455  * Description : This function configures SOSC clock source
2456  *
2457  * Implements CLOCK_DRV_SetSosc_Activity
2458  * END**************************************************************************/
2460  const sosc_config_t * soscConfig)
2461 {
2462  status_t retCode = STATUS_SUCCESS;
2463  scg_sosc_config_t scgSoscConfig;
2464  bool revertTmpSysClkTransition = false;
2465  scg_system_clock_config_t currentSysClockConfig;
2466 
2467  static const scg_sosc_range_t soscRangeMappings[(uint32_t)SOSC_RANGES_MAX] = {SCG_SOSC_RANGE_LOW, SCG_SOSC_RANGE_MID, SCG_SOSC_RANGE_HIGH};
2468  static const scg_sosc_ext_ref_t soscRefMappings[(uint32_t)SOSC_REFS_MAX] = {SCG_SOSC_REF_EXT, SCG_SOSC_REF_OSC};
2469 
2470  /* Check whether the current system clock source is SOSC */
2471  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_OSC))
2472  {
2473  if (enable == false)
2474  {
2475  /* Can't disable SOSC, it's used as system clock source. */
2476  retCode = STATUS_ERROR;
2477  }
2478  else
2479  {
2480  /* Save the current system clock source configuration. */
2481  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
2482 
2483  /* Transition to a temporary system clock source. */
2485 
2486  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
2487  }
2488  }
2489 
2490  if (retCode == STATUS_SUCCESS)
2491  {
2492  if (soscConfig == NULL)
2493  {
2494  retCode = CLOCK_SYS_ConfigureSOSC(enable, NULL);
2495  }
2496  else
2497  {
2498  /* Check VLP modes */
2499  if (((((uint32_t)soscConfig->modes) & ((uint32_t)VLPR_MODE)) != 0U) || ((((uint32_t)soscConfig->modes) & ((uint32_t)VLPS_MODE)) != 0U))
2500  {
2501  scgSoscConfig.enableInLowPower = true;
2502  }
2503  else
2504  {
2505  scgSoscConfig.enableInLowPower = false;
2506  }
2507 
2508  /* Check STOP mode. */
2509  if (((((uint32_t)soscConfig->modes) & ((uint32_t)STOP_MODE)) != 0U))
2510  {
2511  scgSoscConfig.enableInStop = true;
2512  }
2513  else
2514  {
2515  scgSoscConfig.enableInStop = false;
2516  }
2517 
2518  scgSoscConfig.freq = soscConfig->freq;
2519 
2520  scgSoscConfig.monitorMode = SCG_SOSC_MONITOR_DISABLE;
2521  scgSoscConfig.locked = false;
2522 
2523  scgSoscConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2524  scgSoscConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2525 
2526  scgSoscConfig.extRef = soscRefMappings[soscConfig->ref];
2527  scgSoscConfig.gain = SCG_SOSC_GAIN_LOW;
2528  scgSoscConfig.range = soscRangeMappings[soscConfig->range];
2529 
2530  retCode = CLOCK_SYS_ConfigureSOSC(enable, &scgSoscConfig);
2531  }
2532 
2533  /* If system clock source was SOSC and SOSC has been set successfully,
2534  * then transition back to SOSC */
2535  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
2536  {
2537  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
2538  }
2539  }
2540 
2541  return retCode;
2542 }
2543 
2544 /*FUNCTION**********************************************************************
2545  *
2546  * Function Name : CLOCK_DRV_SetSpll
2547  * Description : This function configures SPLL clock source
2548  *
2549  * Implements CLOCK_DRV_SetSpll_Activity
2550  * END**************************************************************************/
2552  const spll_config_t * spllConfig)
2553 {
2554  status_t retCode = STATUS_SUCCESS;
2555  scg_spll_config_t scgSpllConfig;
2556  bool revertTmpSysClkTransition = false;
2557  scg_system_clock_config_t currentSysClockConfig;
2558 
2559  /* Check whether the current system clock source is SPLL */
2560  if (SCG_GetCurrentSystemClockSource(SCG) == ((uint32_t)SCG_SYSTEM_CLOCK_SRC_SYS_PLL))
2561  {
2562  if (enable == false)
2563  {
2564  /* Can't disable SPLL, it's used as system clock source. */
2565  retCode = STATUS_ERROR;
2566  }
2567  else
2568  {
2569  /* Save the current system clock source configuration. */
2570  CLOCK_SYS_GetCurrentSysClkConfig(&currentSysClockConfig);
2571 
2572  /* Transition to a temporary system clock source. */
2573  retCode = CLOCK_SYS_TransitionToTmpSysClk(SCG_SYSTEM_CLOCK_SRC_SYS_PLL);
2574 
2575  revertTmpSysClkTransition = (retCode == STATUS_SUCCESS) ? true : false;
2576  }
2577  }
2578 
2579  if (retCode == STATUS_SUCCESS)
2580  {
2581  if (spllConfig == NULL)
2582  {
2583  retCode = CLOCK_SYS_ConfigureSPLL(enable, NULL);
2584  }
2585  else
2586  {
2587  /* Check STOP mode. */
2588  if (((((uint32_t)spllConfig->modes) & ((uint32_t)STOP_MODE)) != 0U))
2589  {
2590  scgSpllConfig.enableInStop = true;
2591  }
2592  else
2593  {
2594  scgSpllConfig.enableInStop = false;
2595  }
2596 
2597  scgSpllConfig.monitorMode = SCG_SPLL_MONITOR_DISABLE;
2598  scgSpllConfig.locked = false;
2599 
2600  scgSpllConfig.div1 = SCG_ASYNC_CLOCK_DIV_BY_1;
2601  scgSpllConfig.div2 = SCG_ASYNC_CLOCK_DIV_BY_1;
2602 
2603  scgSpllConfig.mult = (uint8_t) spllConfig->mult;
2604  scgSpllConfig.prediv = (uint8_t) spllConfig->prediv;
2605 
2606  retCode = CLOCK_SYS_ConfigureSPLL(enable, &scgSpllConfig);
2607  }
2608 
2609  /* If system clock source was SPLL and SPLL has been set successfully,
2610  * then transition back to SPLL */
2611  if ((retCode == STATUS_SUCCESS) && (revertTmpSysClkTransition == true))
2612  {
2613  retCode = CLOCK_SYS_TransitionSystemClock(&currentSysClockConfig);
2614  }
2615  }
2616 
2617  return retCode;
2618 }
2619 
2620 /*FUNCTION**********************************************************************
2621  *
2622  * Function Name : CLOCK_DRV_SetLpo
2623  * Description : This function configures LPO clock source
2624  *
2625  * Implements CLOCK_DRV_SetLpo_Activity
2626  * END**************************************************************************/
2628 {
2629  if (enable)
2630  {
2631  SIM_SetLpoClocks(SIM,true,true,SIM_LPO_CLK_SEL_LPO_128K,SIM_RTCCLK_SEL_SOSCDIV1_CLK);
2632  PMC_SetLpoMode(PMC, true);
2633  }
2634  else
2635  {
2636  PMC_SetLpoMode(PMC, false);
2637  }
2638 
2639  return STATUS_SUCCESS;
2640 }
2641 
2642 /*******************************************************************************
2643  * EOF
2644  ******************************************************************************/
static scg_system_clock_mode_t CLOCK_SYS_GetCurrentRunMode(void)
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC2
sys_clk_src_t src
#define SCG_SPLL_REF_MIN
Definition: clock_S32K1xx.c:91
scg_async_clock_div_t div1
#define CORE_CLOCK
#define SMC
Definition: S32K142.h:10991
scg_async_clock_div_t div2
pwr_modes_t modes
#define SOSC_STABILIZATION_TIMEOUT
scg_async_clock_div_t div1
sim_tclk_config_t tclkConfig
#define MAX_FREQ_RUN
static status_t CLOCK_SYS_TransitionToTmpSysClk(scg_system_clock_src_t currentSysClkSrc)
status_t CLOCK_DRV_SetSystemClock(const pwr_modes_t *mode, const sys_clk_config_t *sysClkConfig)
Configures the system clocks.
static status_t CLOCK_SYS_SetSystemClockConfig(scg_system_clock_mode_t mode, scg_system_clock_config_t const *config)
#define VLPR_SPEED_RUNNING_MODE
scg_async_clock_div_t div2
#define SIM_EIM_CLOCK
pwr_modes_t modes
scg_rtc_config_t rtcConfig
pwr_modes_t
Power mode. Implements pwr_modes_t_Class.
static status_t CLOCK_SYS_ConfigureSPLL(bool enable, const scg_spll_config_t *spllConfig)
#define TMP_SYSTEM_CLOCK_CONFIGS
pwr_modes_t modes
#define HAS_PROTOCOL_CLOCK_FROM_ASYNC1
scg_async_clock_type_t
SCG asynchronous clock type. Implements scg_async_clock_type_t_Class.
uint32_t g_TClkFreq[NUMBER_OF_TCLK_INPUTS]
Definition: clock_S32K1xx.c:69
#define TMP_SYS_DIV_NO
#define TMP_FIRC_CLK
#define TMP_SYS_CLK_NO
#define HAS_MULTIPLIER
#define MAX_FREQ_CLK_NO
scg_system_clock_type_t
SCG system clock type. Implements scg_system_clock_type_t_Class.
SCG configure structure. Implements scg_config_t_Class.
#define SIM
Definition: S32K142.h:10664
scg_firc_range_t range
scg_system_clock_config_t vccrConfig
sys_clk_div_t slow
#define LPO_128K_FREQUENCY
sirc_range_t range
#define HAS_INT_CLOCK_FROM_SLOW_CLOCK
scg_sirc_range_t range
uint32_t rtcClkInFreq
scg_spll_monitor_mode_t monitorMode
scg_async_clock_div_t div2
peripheral_clock_source_t clkSrc
peripheral instance clock configuration. Implements periph_clk_config_t_Class
SIM configure structure. Implements sim_clock_config_t_Class.
scg_firc_range_t
SCG fast IRC clock frequency range. Implements scg_firc_range_t_Class.
uint32_t tclkFreq[NUMBER_OF_TCLK_INPUTS]
void CLOCK_DRV_EnablePeripheralClock(clock_names_t clockName, const periph_clk_config_t *periphClkConfig)
Enables peripheral clock.
static uint32_t CLOCK_SYS_GetPeripheralClock(clock_names_t clockName, scg_async_clock_type_t divider)
scg_firc_config_t fircConfig
#define SOSC_CLOCK
sim_clkout_div_t divider
scg_sosc_config_t soscConfig
#define PMC
Definition: S32K142.h:8372
#define CLKOUT_CLOCK
#define FIRC_STABILIZATION_TIMEOUT
scg_system_clock_mode_t
SCG system clock modes. Implements scg_system_clock_mode_t_Class.
#define LPO_32K_FREQUENCY
scg_sosc_ext_ref_t extRef
spll_clock_mul_t mult
#define MAX_FREQ_HSRUN
periph_div_t divider
sim_trace_clock_config_t traceClockConfig
static uint32_t CLOCK_SYS_GetSimClkOutFreq(void)
#define SPLL_STABILIZATION_TIMEOUT
#define HIGH_SPEED_RUNNING_MODE
uint32_t g_RtcClkInFreq
Definition: clock_S32K1xx.c:72
sim_rtc_clk_sel_src_t sourceRtcClk
static status_t CLOCK_SYS_ConfigureSOSC(bool enable, const scg_sosc_config_t *soscConfig)
peripheral_clock_config_t * peripheralClocks
#define DEV_ASSERT(x)
Definition: devassert.h:77
#define HAS_INT_CLOCK_FROM_BUS_CLOCK
SCG system PLL configuration. Implements scg_spll_config_t_Class.
#define MAX_FREQ_VLPR
Maximum frequencies of core, bus and flash clocks. Each entry represents the maximum frequency of SYS...
sys_clk_div_t core
SCG slow IRC clock configuration. Implements scg_sirc_config_t_Class.
#define BUS_CLOCK
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
sim_plat_gate_config_t platGateConfig
#define TMP_SYS_DIV
static uint32_t CLOCK_SYS_GetSystemClockFreq(scg_system_clock_type_t type)
clock_names_t
Clock names.
static uint32_t CLOCK_SYS_GetSysPllFreq(void)
status_t CLOCK_SYS_SetConfiguration(clock_manager_user_config_t const *config)
Set system clock configuration.
#define SIRC_STABILIZATION_TIMEOUT
status_t CLOCK_DRV_SetSirc(bool enable, const sirc_config_t *sircConfig)
This function enables or disables SIRC clock source.
#define TMP_SOSC_CLK
#define SIM_LPO_CLOCK
#define SLOW_CLOCK
static status_t CLOCK_SYS_TransitionSystemClock(const scg_system_clock_config_t *to_clk)
scg_clockout_config_t clockOutConfig
#define PCC
Definition: S32K142.h:8069
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
void CLOCK_DRV_DisablePeripheralClock(clock_names_t clockName)
Disables peripheral clock.
#define SCG_SPLL_PREDIV_BASE
Definition: clock_S32K1xx.c:85
sim_clkout_src_t source
scg_system_clock_div_t
SCG system clock divider value. Implements scg_system_clock_div_t_Class.
#define SIM_DMA_CLOCK
scg_spll_config_t spllConfig
scg_clockout_src_t source
pwr_modes_t modes
#define SPLL_CLOCK
#define HAS_DIVIDER
status_t CLOCK_DRV_SetLpo(bool enable)
This function enables or disables LPO clock source.
scg_clock_mode_config_t clockModeConfig
#define SIM_LPO_32K_CLOCK
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
Definition: status.h:44
scg_sirc_config_t sircConfig
#define MAX_FREQ_BUS_CLK
scg_sosc_gain_t gain
pmc_lpo_clock_config_t lpoClockConfig
scg_async_clock_div_t div1
spll_clock_div_t prediv
static status_t CLOCK_SYS_GetSimClockFreq(clock_names_t clockName, uint32_t *frequency)
SCG system clock configuration. Implements scg_system_clock_config_t_Class.
#define SIM_RTCCLK_CLOCK
#define TMP_BUS_DIV
#define FEATURE_SCG_FIRC_FREQ2
#define FEATURE_SCG_SIRC_LOW_RANGE_FREQ
#define SIM_MPU_CLOCK
scg_sirc_range_t
SCG slow IRC clock frequency range. Implements scg_sirc_range_t_Class.
#define SIRC_CLOCK
sosc_range_t range
status_t CLOCK_DRV_SetSpll(bool enable, const spll_config_t *spllConfig)
This function enables or disables SPLL clock source.
const uint16_t clockNameMappings[]
Clock name mappings Constant array storing the mappings between clock names and peripheral clock cont...
#define SCG_SPLL_REF_MAX
Definition: clock_S32K1xx.c:97
scg_system_clock_div_t divCore
#define SCG_SPLL_MULT_BASE
Definition: clock_S32K1xx.c:79
#define SIM_LPO_128K_CLOCK
scg_async_clock_div_t div2
#define CLOCK_MAX_FREQUENCIES
#define MAX_FREQ_SYS_CLK
#define SIM_ERM_CLOCK
#define FEATURE_SCG_SIRC_HIGH_RANGE_FREQ
scg_system_clock_div_t divSlow
scg_sosc_range_t
SCG OSC frequency range select Implements scg_sosc_range_t_Class.
sim_clock_out_config_t clockOutConfig
#define SCG_CLKOUT_CLOCK
status_t CLOCK_SYS_SetScgConfiguration(const scg_config_t *scgConfig)
Configures SCG module.
#define NUMBER_OF_TCLK_INPUTS
Definition: clock_S32K1xx.h:49
#define SIM_LPO_1K_CLOCK
static uint32_t CLOCK_SYS_GetSircFreq(void)
scg_async_clock_div_t div1
static status_t CLOCK_SYS_ConfigureFIRC(bool enable, const scg_firc_config_t *fircConfig)
static status_t CLOCK_SYS_GetPccClockFreq(clock_names_t clockName, uint32_t *frequency)
#define MAX_FREQ_MODES_NO
#define SCG
Definition: S32K142.h:10323
uint32_t count
scg_sosc_range_t range
status_t CLOCK_DRV_SetFirc(bool enable, const firc_config_t *fircConfig)
This function enables or disables FIRC clock source.
periph_clk_src_t source
#define TMP_SLOW_DIV
void CLOCK_SYS_SetSimConfiguration(const sim_clock_config_t *simClockConfig)
Configures SIM module.
sim_qspi_ref_clk_gating_t qspiRefClkGating
#define HAS_INT_CLOCK_FROM_SYS_CLOCK
scg_sosc_monitor_mode_t monitorMode
SCG slow IRC clock configuration. Implements sirc_config_t_Class.
#define TMP_SPLL_CLK
peripheral_clock_divider_t divider
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
#define PCC_CLOCK_NAME_MAPPINGS
PCC clock name mappings Mappings between clock names and peripheral clock control indexes...
sim_lpo_clock_config_t lpoClockConfig
static status_t CLOCK_SYS_ConfigureTemporarySystemClock(void)
static status_t CLOCK_SYS_ConfigureModulesFromScg(const scg_config_t *scgConfig)
#define FEATURE_SCG_FIRC_FREQ1
#define RUN_SPEED_RUNNING_MODE
static status_t CLOCK_SYS_GetScgClockFreq(clock_names_t clockName, uint32_t *frequency)
sim_lpoclk_sel_src_t sourceLpoClk
PMC configure structure.
sosc_ref_t ref
#define FEATURE_SCG_FIRC_FREQ3
uint32_t g_xtal0ClkFreq
Definition: clock_S32K1xx.c:75
void CLOCK_SYS_SetPccConfiguration(const pcc_config_t *peripheralClockConfig)
Configures PCC module.
static status_t CLOCK_SYS_ConfigureSIRC(bool enable, const scg_sirc_config_t *sircConfig)
void CLOCK_SYS_SetPmcConfiguration(const pmc_config_t *pmcConfig)
Configures PMC module.
scg_system_clock_src_t
SCG system clock source. Implements scg_system_clock_src_t_Class.
const uint8_t peripheralFeaturesList[]
Peripheral features list Constant array storing the mappings between clock names of the peripherals a...
SCG system OSC configuration. Implements scg_sosc_config_t_Class.
#define PERIPHERAL_FEATURES
Peripheral features. List of features for each clock name. If a clock name is not a peripheral...
clock_trace_src_t source
SCG fast IRC clock configuration. Implements scg_firc_config_t_Class.
scg_system_clock_config_t rccrConfig
static uint32_t CLOCK_SYS_GetScgClkOutFreq(void)
scg_system_clock_src_t src
#define HAS_CLOCK_GATING_IN_SIM
sys_clk_div_t bus
#define MAX_FREQ_SLOW_CLK
#define FIRC_CLOCK
static uint32_t CLOCK_SYS_GetSysAsyncFreq(clock_names_t clockSource, scg_async_clock_type_t type)
Clock configuration structure. Implements clock_manager_user_config_t_Class.
Definition: clock_manager.h:73
static uint32_t CLOCK_SYS_GetSysOscFreq(void)
peripheral_clock_frac_t frac
#define FEATURE_SCG_FIRC_FREQ0
scg_sosc_ext_ref_t
SCG OSC external reference clock select. Implements scg_sosc_ext_ref_t_Class.
#define RTC_CLKIN_CLOCK
#define TMP_SIRC_CLK
Temporary system clock source configurations. Each line represents the SYS(CORE), BUS and SLOW(FLASH)...
firc_range_t range
status_t CLOCK_DRV_SetSosc(bool enable, const sosc_config_t *soscConfig)
This function enables or disables SOSC clock source.
static uint32_t CLOCK_SYS_GetLpoFreq(void)
static uint32_t CLOCK_SYS_GetFircFreq(void)
static uint32_t CLOCK_SYS_GetSimRtcClkFreq(void)
scg_system_clock_config_t hccrConfig
periph_mul_t multiplier
#define LPO_1K_FREQUENCY
static void CLOCK_SYS_GetCurrentSysClkConfig(scg_system_clock_config_t *sysClockConfig)
#define SIM_MSCM_CLOCK
scg_system_clock_div_t divBus
system clock configuration. Implements sys_clk_config_t_Class
PCC configuration. Implements pcc_config_t_Class.