20 #include "flexio_hw_access.h"
100 #define DIVIDER_MIN_VALUE 1U
101 #define DIVIDER_MAX_VALUE 0xFFU
105 #define TX_SHIFTER(x) (x)
106 #define RX_SHIFTER(x) (uint8_t)((x) + 1U)
107 #define SCK_TIMER(x) (x)
108 #define WS_TIMER(x) (uint8_t)((x) + 1U)
120 static uint8_t FLEXIO_I2S_DRV_ComputeByteWidth(uint8_t bitsWidth)
128 else if (bitsWidth <= 16U)
155 tmpDiv = ((inputClock + baudRate) / (2U * baudRate)) - 1U;
157 if (tmpDiv < DIVIDER_MIN_VALUE)
159 tmpDiv = DIVIDER_MIN_VALUE;
161 if (tmpDiv > DIVIDER_MAX_VALUE)
163 tmpDiv = DIVIDER_MAX_VALUE;
166 *divider = (uint16_t)tmpDiv;
183 uint8_t resourceIndex;
186 resourceIndex = master->flexioCommon.resourceIndex;
189 FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(master, userConfigPtr->
baudRate, ÷r, inputClock);
193 FLEXIO_SetShifterConfig(baseAddr,
194 TX_SHIFTER(resourceIndex),
195 FLEXIO_SHIFTER_START_BIT_DISABLED_SH,
196 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
197 FLEXIO_SHIFTER_SOURCE_PIN);
198 FLEXIO_SetShifterControl(baseAddr,
199 TX_SHIFTER(resourceIndex),
200 FLEXIO_SHIFTER_MODE_DISABLED,
201 userConfigPtr->
txPin,
202 FLEXIO_PIN_POLARITY_HIGH,
203 FLEXIO_PIN_CONFIG_DISABLED,
204 SCK_TIMER(resourceIndex),
205 FLEXIO_TIMER_POLARITY_POSEDGE);
208 FLEXIO_SetShifterConfig(baseAddr,
209 RX_SHIFTER(resourceIndex),
210 FLEXIO_SHIFTER_START_BIT_DISABLED,
211 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
212 FLEXIO_SHIFTER_SOURCE_PIN);
213 FLEXIO_SetShifterControl(baseAddr,
214 RX_SHIFTER(resourceIndex),
215 FLEXIO_SHIFTER_MODE_DISABLED,
216 userConfigPtr->
rxPin,
217 FLEXIO_PIN_POLARITY_HIGH,
218 FLEXIO_PIN_CONFIG_DISABLED,
219 SCK_TIMER(resourceIndex),
220 FLEXIO_TIMER_POLARITY_NEGEDGE);
223 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)((((bits << 1U) - 1U) << 8U) + divider));
224 FLEXIO_SetTimerConfig(baseAddr,
225 SCK_TIMER(resourceIndex),
226 FLEXIO_TIMER_START_BIT_ENABLED,
227 FLEXIO_TIMER_STOP_BIT_DISABLED,
228 FLEXIO_TIMER_ENABLE_TRG_HIGH,
229 FLEXIO_TIMER_DISABLE_NEVER,
230 FLEXIO_TIMER_RESET_NEVER,
231 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
232 FLEXIO_TIMER_INITOUT_ONE);
233 FLEXIO_SetTimerControl(baseAddr,
234 SCK_TIMER(resourceIndex),
235 (uint8_t)((TX_SHIFTER(resourceIndex) << 2U) + 1U),
236 FLEXIO_TRIGGER_POLARITY_LOW,
237 FLEXIO_TRIGGER_SOURCE_INTERNAL,
239 FLEXIO_PIN_POLARITY_LOW,
240 FLEXIO_PIN_CONFIG_OUTPUT,
241 FLEXIO_TIMER_MODE_DISABLED);
245 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)((bits * ((divider + 1U) * 2U)) - 1U));
246 FLEXIO_SetTimerConfig(baseAddr,
247 WS_TIMER(resourceIndex),
248 FLEXIO_TIMER_START_BIT_DISABLED,
249 FLEXIO_TIMER_STOP_BIT_DISABLED,
250 FLEXIO_TIMER_ENABLE_TIM_ENABLE,
251 FLEXIO_TIMER_DISABLE_NEVER,
252 FLEXIO_TIMER_RESET_NEVER,
253 FLEXIO_TIMER_DECREMENT_CLK_SHIFT_TMR,
254 FLEXIO_TIMER_INITOUT_ONE);
255 FLEXIO_SetTimerControl(baseAddr,
256 WS_TIMER(resourceIndex),
258 FLEXIO_TRIGGER_POLARITY_HIGH,
259 FLEXIO_TRIGGER_SOURCE_EXTERNAL,
260 userConfigPtr->
wsPin,
261 FLEXIO_PIN_POLARITY_LOW,
262 FLEXIO_PIN_CONFIG_OUTPUT,
263 FLEXIO_TIMER_MODE_DISABLED);
278 uint8_t resourceIndex;
281 resourceIndex = slave->flexioCommon.resourceIndex;
286 FLEXIO_SetShifterConfig(baseAddr,
287 TX_SHIFTER(resourceIndex),
288 FLEXIO_SHIFTER_START_BIT_DISABLED,
289 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
290 FLEXIO_SHIFTER_SOURCE_PIN);
291 FLEXIO_SetShifterControl(baseAddr,
292 TX_SHIFTER(resourceIndex),
293 FLEXIO_SHIFTER_MODE_DISABLED,
294 userConfigPtr->
txPin,
295 FLEXIO_PIN_POLARITY_HIGH,
296 FLEXIO_PIN_CONFIG_DISABLED,
297 WS_TIMER(resourceIndex),
298 FLEXIO_TIMER_POLARITY_POSEDGE);
301 FLEXIO_SetShifterConfig(baseAddr,
302 RX_SHIFTER(resourceIndex),
303 FLEXIO_SHIFTER_START_BIT_DISABLED,
304 FLEXIO_SHIFTER_STOP_BIT_DISABLED,
305 FLEXIO_SHIFTER_SOURCE_PIN);
306 FLEXIO_SetShifterControl(baseAddr,
307 RX_SHIFTER(resourceIndex),
308 FLEXIO_SHIFTER_MODE_DISABLED,
309 userConfigPtr->
rxPin,
310 FLEXIO_PIN_POLARITY_HIGH,
311 FLEXIO_PIN_CONFIG_DISABLED,
312 WS_TIMER(resourceIndex),
313 FLEXIO_TIMER_POLARITY_NEGEDGE);
316 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)((bits << 2U) - 3U));
317 FLEXIO_SetTimerConfig(baseAddr,
318 SCK_TIMER(resourceIndex),
319 FLEXIO_TIMER_START_BIT_DISABLED,
320 FLEXIO_TIMER_STOP_BIT_DISABLED,
321 FLEXIO_TIMER_ENABLE_PIN_POSEDGE,
322 FLEXIO_TIMER_DISABLE_TIM_CMP,
323 FLEXIO_TIMER_RESET_NEVER,
324 FLEXIO_TIMER_DECREMENT_TRG_SHIFT_TRG,
325 FLEXIO_TIMER_INITOUT_ONE);
326 FLEXIO_SetTimerControl(baseAddr,
327 SCK_TIMER(resourceIndex),
328 (uint8_t)(userConfigPtr->
sckPin << 1U),
329 FLEXIO_TRIGGER_POLARITY_LOW,
330 FLEXIO_TRIGGER_SOURCE_INTERNAL,
331 userConfigPtr->
wsPin,
332 FLEXIO_PIN_POLARITY_LOW,
333 FLEXIO_PIN_CONFIG_DISABLED,
334 FLEXIO_TIMER_MODE_DISABLED);
337 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)((bits << 1U) - 1U));
338 FLEXIO_SetTimerConfig(baseAddr,
339 WS_TIMER(resourceIndex),
340 FLEXIO_TIMER_START_BIT_DISABLED,
341 FLEXIO_TIMER_STOP_BIT_DISABLED,
342 FLEXIO_TIMER_ENABLE_PIN_POSEDGE_TRG_HIGH,
343 FLEXIO_TIMER_DISABLE_TIM_CMP_TRG_LOW,
344 FLEXIO_TIMER_RESET_NEVER,
345 FLEXIO_TIMER_DECREMENT_PIN_SHIFT_PIN,
346 FLEXIO_TIMER_INITOUT_ONE);
347 FLEXIO_SetTimerControl(baseAddr,
348 WS_TIMER(resourceIndex),
349 (uint8_t)((SCK_TIMER(resourceIndex) << 2U) + 3U),
350 FLEXIO_TRIGGER_POLARITY_HIGH,
351 FLEXIO_TRIGGER_SOURCE_INTERNAL,
353 FLEXIO_PIN_POLARITY_LOW,
354 FLEXIO_PIN_CONFIG_DISABLED,
355 FLEXIO_TIMER_MODE_DISABLED);
368 uint8_t resourceIndex;
371 resourceIndex = master->flexioCommon.resourceIndex;
374 switch (master->driverType)
378 FLEXIO_SetShifterInterrupt(baseAddr,
379 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
381 FLEXIO_SetShifterErrorInterrupt(baseAddr,
382 (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
393 FLEXIO_SetShifterDMARequest(baseAddr, (uint8_t)((1U << TX_SHIFTER(resourceIndex)) | (1U << RX_SHIFTER(resourceIndex))),
false);
400 master->driverIdle =
true;
401 master->txData = NULL;
402 master->rxData = NULL;
403 master->txRemainingBytes = 0U;
404 master->rxRemainingBytes = 0U;
407 if (master->blocking ==
true)
423 uint8_t resourceIndex;
425 resourceIndex = master->flexioCommon.resourceIndex;
429 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_TRANSMIT);
430 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_RECEIVE);
433 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_8BIT_BAUD);
437 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
439 FLEXIO_SetTimerMode(baseAddr, WS_TIMER(resourceIndex), FLEXIO_TIMER_MODE_16BIT);
452 uint8_t resourceIndex;
454 resourceIndex = master->flexioCommon.resourceIndex;
458 FLEXIO_SetShifterMode(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
459 FLEXIO_SetShifterMode(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_MODE_DISABLED);
460 FLEXIO_SetTimerMode(baseAddr, SCK_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
461 FLEXIO_SetTimerMode(baseAddr, WS_TIMER(resourceIndex), FLEXIO_TIMER_MODE_DISABLED);
463 FLEXIO_SetShifterPinConfig(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_PIN_CONFIG_DISABLED);
466 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
467 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
469 FLEXIO_ClearShifterStatus(baseAddr, RX_SHIFTER(resourceIndex));
472 FLEXIO_I2S_DRV_MasterEndTransfer(master);
486 switch (master->driverType)
490 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
497 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
505 master->blocking =
false;
510 FLEXIO_I2S_DRV_MasterStopTransfer(master);
513 return master->status;
527 uint8_t resourceIndex;
530 resourceIndex = master->flexioCommon.resourceIndex;
533 data = FLEXIO_ReadShifterBuffer(baseAddr, RX_SHIFTER(resourceIndex), FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
535 if (master->rxRemainingBytes > 0U)
537 if (master->rxData != NULL)
539 switch (master->byteWidth)
542 *(uint8_t *)master->rxData = (uint8_t)data;
545 *(uint16_t *)master->rxData = (uint16_t)data;
548 *(uint32_t *)master->rxData = (uint32_t)data;
552 master->rxData = &master->rxData[master->byteWidth];
555 master->rxRemainingBytes -= (uint32_t)(master->byteWidth);
574 uint8_t resourceIndex;
577 resourceIndex = master->flexioCommon.resourceIndex;
579 if (master->txRemainingBytes == 0U)
586 switch (master->byteWidth)
589 data = (uint32_t)(*(
const uint8_t *)master->txData);
592 data = (uint32_t)(*(
const uint16_t *)master->txData);
595 data = (uint32_t)(*(
const uint32_t *)master->txData);
598 master->txData = &master->txData[master->byteWidth];
599 master->txRemainingBytes -= (uint32_t)(master->byteWidth);
603 data <<= 32U - (uint32_t)(master->bitsWidth);
604 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), data, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
616 static void FLEXIO_I2S_DRV_MasterCheckStatus(
void *stateStruct)
619 uint8_t resourceIndex;
626 resourceIndex = master->flexioCommon.resourceIndex;
629 if (master->txData != NULL)
631 if(FLEXIO_GetShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex)))
634 FLEXIO_ClearShifterErrorStatus(baseAddr, TX_SHIFTER(resourceIndex));
638 if (master->rxData != NULL)
640 if (FLEXIO_GetShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex)))
643 FLEXIO_ClearShifterErrorStatus(baseAddr, RX_SHIFTER(resourceIndex));
648 if (FLEXIO_GetShifterStatus(baseAddr, RX_SHIFTER(resourceIndex)))
650 FLEXIO_I2S_DRV_ReadData(master);
651 if ((master->rxData != NULL) && (master->rxRemainingBytes == 0U))
654 if (master->callback != NULL)
661 if (master->txData != NULL)
663 if (FLEXIO_GetShifterStatus(baseAddr, TX_SHIFTER(resourceIndex)))
665 FLEXIO_I2S_DRV_WriteData(master);
666 if (master->txRemainingBytes == 0U)
669 if (master->callback != NULL)
673 if (master->txRemainingBytes == 0U)
679 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
680 FLEXIO_SetShifterErrorInterrupt(baseAddr, (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
false);
682 FLEXIO_SetShifterInterrupt(baseAddr, (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
true);
684 master->txData = NULL;
691 if (master->rxRemainingBytes == 0U)
699 FLEXIO_I2S_DRV_MasterStopTransfer(master);
701 if (master->callback != NULL)
715 static void FLEXIO_I2S_DRV_MasterEndDmaTxTransfer(
void *stateStruct,
edma_chn_status_t status)
726 if (master->callback != NULL)
730 if (master->txRemainingBytes == 0U)
733 master->txData = NULL;
739 dmaChn = master->txDMAChannel;
743 master->txRemainingBytes = 0U;
756 static void FLEXIO_I2S_DRV_MasterEndDmaRxTransfer(
void *stateStruct,
edma_chn_status_t status)
768 if ((master->rxData != NULL) && (master->callback != NULL))
772 if (master->rxRemainingBytes == 0U)
777 FLEXIO_I2S_DRV_MasterStopTransfer(master);
779 if (master->callback != NULL)
788 dmaChn = master->rxDMAChannel;
789 if (master->rxData != NULL)
791 addr = (uint32_t)(master->rxData);
796 addr = (uint32_t)(&(master->dummyDmaData));
801 master->rxRemainingBytes = 0U;
821 shifter = TX_SHIFTER(master->flexioCommon.resourceIndex);
822 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter])) + (
sizeof(uint32_t) - master->byteWidth);
840 shifter = RX_SHIFTER(master->flexioCommon.resourceIndex);
841 addr = (uint32_t)(&(baseAddr->
SHIFTBUFBIS[shifter]));
854 uint8_t resourceIndex;
857 uint8_t requestMask = 0U;
864 resourceIndex = master->flexioCommon.resourceIndex;
867 if (master->txData != NULL)
872 (uint32_t)(master->txData),
873 FLEXIO_I2S_DRV_MasterComputeTxRegAddr(master),
874 dmaTransferSize[master->byteWidth - 1U],
876 master->txRemainingBytes / master->byteWidth,
879 master->txRemainingBytes = 0U;
887 requestMask = (uint8_t)(1U << TX_SHIFTER(resourceIndex));
890 if (master->rxData != NULL)
892 addr = (uint32_t)(master->rxData);
897 addr = (uint32_t)(&(master->dummyDmaData));
902 FLEXIO_I2S_DRV_MasterComputeRxRegAddr(master),
904 dmaTransferSize[master->byteWidth - 1U],
906 master->rxRemainingBytes / master->byteWidth,
908 if (master->rxData == NULL)
914 master->rxRemainingBytes = 0U;
922 requestMask |= (uint8_t)(1U << RX_SHIFTER(resourceIndex));
925 FLEXIO_SetShifterDMARequest(baseAddr, requestMask,
true);
963 master->flexioCommon.resourceCount = 2U;
978 master->driverType = userConfigPtr->
driverType;
979 master->bitsWidth = userConfigPtr->
bitsWidth;
980 master->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(userConfigPtr->
bitsWidth);
981 master->driverIdle =
true;
982 master->callback = userConfigPtr->
callback;
984 master->blocking =
false;
985 master->txData = NULL;
986 master->txRemainingBytes = 0U;
987 master->rxData = NULL;
988 master->rxRemainingBytes = 0U;
989 master->master =
true;
993 FLEXIO_I2S_DRV_MasterConfigure(master, userConfigPtr, inputClock);
996 switch (master->driverType)
999 master->flexioCommon.isr = FLEXIO_I2S_DRV_MasterCheckStatus;
1009 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(master->flexioCommon.resourceIndex)];
1010 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(master->flexioCommon.resourceIndex)];
1061 uint32_t inputClock;
1063 uint8_t resourceIndex;
1069 (bitsWidth != 8U) && (bitsWidth != 16U) && (bitsWidth != 32U)
1072 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1073 resourceIndex = master->flexioCommon.resourceIndex;
1083 FLEXIO_I2S_DRV_MasterComputeBaudRateDivider(master, baudRate, ÷r, inputClock);
1086 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)(((((uint16_t)bitsWidth << 1U) - 1U) << 8U) + divider));
1088 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)((bitsWidth * ((divider + 1U) * 2U)) - 1U));
1090 master->bitsWidth = bitsWidth;
1091 master->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(bitsWidth);
1108 uint32_t inputClock;
1112 uint8_t resourceIndex;
1116 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1117 resourceIndex = master->flexioCommon.resourceIndex;
1125 timerCmp = FLEXIO_GetTimerCompare(baseAddr, SCK_TIMER(resourceIndex));
1126 divider = (uint16_t)(timerCmp & 0x00FFU);
1129 *baudRate = (inputClock + (uint32_t)divider + 1U) / (2U * ((uint32_t)divider + 1U));
1145 const uint8_t * txBuff,
1149 uint8_t resourceIndex;
1155 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1156 resourceIndex = master->flexioCommon.resourceIndex;
1161 master->txData = txBuff;
1162 master->txRemainingBytes = txSize;
1164 master->rxRemainingBytes = txSize;
1165 master->rxData = NULL;
1167 master->driverIdle =
false;
1170 FLEXIO_SetShifterPinConfig(baseAddr, TX_SHIFTER(resourceIndex), FLEXIO_PIN_CONFIG_OUTPUT);
1172 FLEXIO_I2S_DRV_MasterEnableTransfer(master);
1174 switch (master->driverType)
1178 FLEXIO_SetShifterInterrupt(baseAddr,
1179 (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
1181 FLEXIO_SetShifterErrorInterrupt(baseAddr,
1182 (uint8_t)(1U << TX_SHIFTER(resourceIndex)),
1187 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1190 FLEXIO_I2S_DRV_MasterStartDmaTransfer(master);
1209 const uint8_t * txBuff,
1218 master->blocking =
true;
1225 master->blocking =
false;
1230 return FLEXIO_I2S_DRV_MasterWaitTransferEnd(master, timeout);
1246 uint8_t resourceIndex;
1252 baseAddr =
g_flexioBase[master->flexioCommon.instance];
1253 resourceIndex = master->flexioCommon.resourceIndex;
1258 master->rxData = rxBuff;
1259 master->rxRemainingBytes = rxSize;
1260 master->txData = NULL;
1261 master->txRemainingBytes = 0U;
1263 master->driverIdle =
false;
1266 FLEXIO_I2S_DRV_MasterEnableTransfer(master);
1269 switch (master->driverType)
1273 FLEXIO_SetShifterInterrupt(baseAddr,
1274 (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
1276 FLEXIO_SetShifterErrorInterrupt(baseAddr,
1277 (uint8_t)(1U << RX_SHIFTER(resourceIndex)),
1282 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1285 FLEXIO_I2S_DRV_MasterStartDmaTransfer(master);
1294 FLEXIO_WriteShifterBuffer(baseAddr, TX_SHIFTER(resourceIndex), 0x0, FLEXIO_SHIFTER_RW_MODE_BIT_SWAP);
1317 master->blocking =
true;
1324 master->blocking =
false;
1329 return FLEXIO_I2S_DRV_MasterWaitTransferEnd(master, timeout);
1345 FLEXIO_I2S_DRV_MasterStopTransfer(master);
1365 FLEXIO_I2S_DRV_MasterCheckStatus(master);
1368 if (bytesRemaining != NULL)
1372 *bytesRemaining = master->rxRemainingBytes;
1375 if (!master->driverIdle)
1381 return master->status;
1401 master->rxData = rxBuff;
1402 master->rxRemainingBytes = rxSize;
1416 const uint8_t * txBuff,
1423 master->txData = txBuff;
1424 master->txRemainingBytes = txSize;
1426 master->rxRemainingBytes += txSize;
1454 slave->flexioCommon.resourceCount = 2U;
1468 slave->driverType = userConfigPtr->
driverType;
1469 slave->bitsWidth = userConfigPtr->
bitsWidth;
1470 slave->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(userConfigPtr->
bitsWidth);
1471 slave->driverIdle =
true;
1472 slave->callback = userConfigPtr->
callback;
1474 slave->blocking =
false;
1475 slave->txData = NULL;
1476 slave->txRemainingBytes = 0U;
1477 slave->rxData = NULL;
1478 slave->rxRemainingBytes = 0U;
1479 slave->master =
false;
1483 FLEXIO_I2S_DRV_SlaveConfigure(slave, userConfigPtr);
1486 switch (slave->driverType)
1489 slave->flexioCommon.isr = FLEXIO_I2S_DRV_MasterCheckStatus;
1499 dmaReqTx =
g_flexioDMASrc[instance][TX_SHIFTER(slave->flexioCommon.resourceIndex)];
1500 dmaReqRx =
g_flexioDMASrc[instance][RX_SHIFTER(slave->flexioCommon.resourceIndex)];
1525 uint8_t resourceIndex;
1531 (bitsWidth != 8U) && (bitsWidth != 16U) && (bitsWidth != 32U)
1535 resourceIndex = slave->flexioCommon.resourceIndex;
1540 slave->bitsWidth = bitsWidth;
1541 slave->byteWidth = FLEXIO_I2S_DRV_ComputeByteWidth(bitsWidth);
1544 FLEXIO_SetTimerCompare(baseAddr, SCK_TIMER(resourceIndex), (uint16_t)(((uint16_t)bitsWidth << 2U) - 3U));
1546 FLEXIO_SetTimerCompare(baseAddr, WS_TIMER(resourceIndex), (uint16_t)(((uint16_t)bitsWidth << 1U) - 1U));
status_t FLEXIO_I2S_DRV_MasterReceiveDataBlocking(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterReceiveData(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2S bus.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
status_t FLEXIO_I2S_DRV_MasterSetTxBuffer(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
FLEXIO_Type *const g_flexioBase[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
#define FLEXIO_INSTANCE_COUNT
status_t FLEXIO_I2S_DRV_MasterSendData(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2S bus.
void EDMA_DRV_SetDestOffset(uint8_t channel, int16_t offset)
Configures the destination address signed offset for the eDMA channel.
Master internal context structure.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
Slave configuration structure.
status_t EDMA_DRV_SetChannelRequest(uint8_t channel, uint8_t req)
Configures the DMA request for the eDMA channel.
status_t FLEXIO_DRV_DeinitDriver(const flexio_common_state_t *driver)
status_t FLEXIO_I2S_DRV_MasterDeinit(flexio_i2s_master_state_t *master)
De-initialize the FLEXIO_I2S master mode driver.
status_t FLEXIO_I2S_DRV_SlaveInit(uint32_t instance, const flexio_i2s_slave_user_config_t *userConfigPtr, flexio_i2s_slave_state_t *slave)
Initialize the FLEXIO_I2S slave mode driver.
edma_chn_status_t
Channel status for eDMA channel.
__IO uint32_t SHIFTBUFBIS[FLEXIO_SHIFTBUFBIS_COUNT]
edma_transfer_size_t
eDMA transfer configuration Implements : edma_transfer_size_t_Class
flexio_callback_t callback
void EDMA_DRV_SetSrcAddr(uint8_t channel, uint32_t address)
Configures the source address for the eDMA channel.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
status_t FLEXIO_I2S_DRV_MasterSendDataBlocking(flexio_i2s_master_state_t *master, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2S bus.
status_t FLEXIO_I2S_DRV_MasterSetConfig(flexio_i2s_master_state_t *master, uint32_t baudRate, uint8_t bitsWidth)
Set the baud rate and bit width for any subsequent I2S communication.
status_t FLEXIO_I2S_DRV_MasterGetStatus(flexio_i2s_master_state_t *master, uint32_t *bytesRemaining)
Get the status of the current non-blocking I2S master transaction.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
const uint8_t g_flexioDMASrc[FLEXIO_INSTANCE_COUNT][FEATURE_FLEXIO_MAX_SHIFTER_COUNT]
void EDMA_DRV_SetMajorLoopIterationCount(uint8_t channel, uint32_t majorLoopCount)
Configures the number of major loop iterations.
void EDMA_DRV_SetDestAddr(uint8_t channel, uint32_t address)
Configures the destination address for the eDMA channel.
flexio_driver_type_t driverType
status_t FLEXIO_DRV_InitDriver(uint32_t instance, flexio_common_state_t *driver)
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
status_t FLEXIO_I2S_DRV_MasterInit(uint32_t instance, const flexio_i2s_master_user_config_t *userConfigPtr, flexio_i2s_master_state_t *master)
Initialize the FLEXIO_I2S master mode driver.
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
flexio_driver_type_t driverType
flexio_device_state_t * g_flexioDeviceStatePtr[FLEXIO_INSTANCE_COUNT]
status_t FLEXIO_I2S_DRV_MasterSetRxBuffer(flexio_i2s_master_state_t *master, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
Master configuration structure.
void(* edma_callback_t)(void *parameter, edma_chn_status_t status)
Definition for the eDMA channel callback function.
status_t FLEXIO_I2S_DRV_MasterGetBaudRate(flexio_i2s_master_state_t *master, uint32_t *baudRate)
Get the currently configured baud rate.
status_t FLEXIO_I2S_DRV_MasterTransferAbort(flexio_i2s_master_state_t *master)
Aborts a non-blocking I2S master transaction.
const clock_names_t g_flexioClock[FLEXIO_INSTANCE_COUNT]
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
flexio_callback_t callback
status_t FLEXIO_I2S_DRV_SlaveSetConfig(flexio_i2s_slave_state_t *slave, uint8_t bitsWidth)
Set the bit width for any subsequent I2S communication.