91 #include "lpi2c_hw_access.h"
101 #define CLKHI_MIN_VALUE 1U
102 #define CLKLO_MIN_VALUE 3U
103 #define CLKHI_MAX_VALUE (((1U << LPI2C_MCCR0_CLKHI_WIDTH) - 1U) >> 1U)
104 #define CLKLO_MAX_VALUE (CLKHI_MAX_VALUE << 1U)
105 #define DATAVD_MIN_VALUE 1U
106 #define SETHOLD_MIN_VALUE 2U
133 } lpi2c_transfer_direction_t;
146 uint32_t i2cDataRegAddr;
147 uint8_t *bufferTransfer;
148 uint32_t transferSize;
149 lpi2c_transfer_direction_t transferDirection;
169 return (master->cmdQueue.writeIdx == master->cmdQueue.readIdx);
183 master->cmdQueue.readIdx = 0U;
184 master->cmdQueue.writeIdx = 0U;
196 lpi2c_master_command_t cmd,
202 uint16_t txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
203 uint16_t txFIFOSize = LPI2C_Get_MasterTxFIFOSize(baseAddr);
206 if (txFIFOCount < txFIFOSize)
208 LPI2C_Cmd_MasterTransmit(baseAddr, cmd, data);
213 DEV_ASSERT(master->cmdQueue.writeIdx < LPI2C_MASTER_CMD_QUEUE_SIZE);
215 master->cmdQueue.cmd[master->cmdQueue.writeIdx] = cmd;
216 master->cmdQueue.data[master->cmdQueue.writeIdx] = data;
217 master->cmdQueue.writeIdx++;
233 uint16_t txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
234 uint16_t txFifoSize = LPI2C_Get_MasterTxFIFOSize(baseAddr);
238 LPI2C_Cmd_MasterTransmit(baseAddr,
239 master->cmdQueue.cmd[master->cmdQueue.readIdx],
240 master->cmdQueue.data[master->cmdQueue.readIdx]);
241 master->cmdQueue.readIdx++;
243 txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
266 lpi2c_master_command_t startCommand;
271 #if(LPI2C_HAS_HIGH_SPEED_MODE)
272 if ((master->operatingMode == LPI2C_HIGHSPEED_MODE) && (master->highSpeedInProgress ==
false))
276 master->highSpeedInProgress =
true;
279 if (master->highSpeedInProgress ==
true)
282 startCommand = LPI2C_MASTER_COMMAND_START_HS;
288 startCommand = LPI2C_MASTER_COMMAND_START;
291 if (master->is10bitAddr)
295 addrByte = (uint8_t)(0xF0U + ((master->slaveAddress >> 7U) & 0x6U) + (uint8_t)0U);
298 addrByte = (uint8_t)(master->slaveAddress & 0xFFU);
304 addrByte = (uint8_t)(0xF0U + ((master->slaveAddress >> 7U) & 0x6U) + (uint8_t)1U);
312 addrByte = (uint8_t)((master->slaveAddress << 1U) + (uint8_t)receive);
330 uint16_t txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
331 uint16_t txFifoSize = LPI2C_Get_MasterTxFIFOSize(baseAddr);
336 while ((master->txSize > 0U) && (txFIFOCount < txFifoSize))
338 LPI2C_Cmd_MasterTransmit(baseAddr, LPI2C_MASTER_COMMAND_TRANSMIT, master->txBuff[0U]);
342 txFIFOCount = LPI2C_Get_MasterTxFIFOCount(baseAddr);
363 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
364 LPI2C_MASTER_ARBITRATION_LOST_INT |
365 LPI2C_MASTER_NACK_DETECT_INT |
366 LPI2C_MASTER_TRANSMIT_DATA_INT |
367 LPI2C_MASTER_RECEIVE_DATA_INT,
370 if (resetFIFO ==
true)
373 LPI2C_Reset_MasterTxFIFOCmd(baseAddr);
374 LPI2C_Reset_MasterRxFIFOCmd(baseAddr);
378 if (sendStop ==
true)
380 LPI2C_Cmd_MasterTransmit(baseAddr, LPI2C_MASTER_COMMAND_STOP, 0U);
381 #if(LPI2C_HAS_HIGH_SPEED_MODE)
382 master->highSpeedInProgress =
false;
389 if (master->rxSize != (uint16_t)0)
391 (void)LPI2C_Set_MasterRxDMA(baseAddr,
false);
395 (void)LPI2C_Set_MasterTxDMA(baseAddr,
false);
399 master->txBuff = NULL;
401 master->rxBuff = NULL;
403 master->i2cIdle =
true;
421 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
422 LPI2C_SLAVE_FIFO_ERROR_INT |
423 LPI2C_SLAVE_STOP_DETECT_INT |
424 LPI2C_SLAVE_REPEATED_START_INT |
425 LPI2C_SLAVE_ADDRESS_VALID_INT |
426 LPI2C_SLAVE_RECEIVE_DATA_INT |
427 LPI2C_SLAVE_TRANSMIT_DATA_INT,
433 if (slave->rxSize != (uint16_t)0)
435 (void)LPI2C_Set_SlaveRxDMA(baseAddr,
false);
439 (void)LPI2C_Set_SlaveTxDMA(baseAddr,
false);
444 LPI2C_Set_SlaveEnable(baseAddr,
false);
446 slave->isTransferInProgress =
false;
447 slave->rxBuff = NULL;
449 slave->txBuff = NULL;
465 baseAddr = g_lpi2cBase[instance];
466 master = g_lpi2cMasterStatePtr[instance];
469 #if(LPI2C_HAS_ULTRA_FAST_MODE)
470 if (operatingMode == LPI2C_ULTRAFAST_MODE)
472 LPI2C_Set_MasterPinConfig(baseAddr, LPI2C_CFG_2PIN_OUTPUT_ONLY);
473 LPI2C_Set_MasterNACKConfig(baseAddr, LPI2C_NACK_IGNORE);
478 LPI2C_Set_MasterPinConfig(baseAddr, LPI2C_CFG_2PIN_OPEN_DRAIN);
479 LPI2C_Set_MasterNACKConfig(baseAddr, LPI2C_NACK_RECEIVE);
482 master->operatingMode = operatingMode;
497 baseAddr = g_lpi2cBase[instance];
498 slave = g_lpi2cSlaveStatePtr[instance];
501 #if(LPI2C_HAS_ULTRA_FAST_MODE)
502 if (operatingMode == LPI2C_ULTRAFAST_MODE)
504 LPI2C_Set_SlaveIgnoreNACK(baseAddr, LPI2C_SLAVE_NACK_CONTINUE_TRANSFER);
505 LPI2C_Set_SlaveTransmitNACK(baseAddr, LPI2C_SLAVE_TRANSMIT_NACK);
507 LPI2C_Set_SlaveACKStall(baseAddr,
false);
508 LPI2C_Set_SlaveTXDStall(baseAddr,
false);
509 LPI2C_Set_SlaveRXStall(baseAddr,
false);
510 LPI2C_Set_SlaveAddrStall(baseAddr,
false);
515 LPI2C_Set_SlaveIgnoreNACK(baseAddr, LPI2C_SLAVE_NACK_END_TRANSFER);
516 LPI2C_Set_SlaveTransmitNACK(baseAddr, LPI2C_SLAVE_TRANSMIT_ACK);
518 LPI2C_Set_SlaveACKStall(baseAddr,
false);
519 LPI2C_Set_SlaveTXDStall(baseAddr,
true);
520 LPI2C_Set_SlaveRXStall(baseAddr,
true);
521 LPI2C_Set_SlaveAddrStall(baseAddr,
true);
524 #if(LPI2C_HAS_HIGH_SPEED_MODE)
525 if (operatingMode == LPI2C_HIGHSPEED_MODE)
528 LPI2C_Set_SlaveHighSpeedModeDetect(baseAddr,
true);
534 LPI2C_Set_SlaveHighSpeedModeDetect(baseAddr,
false);
537 slave->operatingMode = operatingMode;
550 if (dmaTransParams->transferDirection == LPI2C_TX_REQ)
555 (uint32_t)dmaTransParams->transferSize,
false);
562 (uint32_t)dmaTransParams->transferSize,
false);
578 bool receive =
false;
580 dmaTransParams.dmaChannel = master->dmaChannel;
581 if (master->txSize > 0U)
584 uint32_t txBytes = LPI2C_Get_MasterTxFIFOSize(baseAddr);
585 if (txBytes > master->txSize)
587 txBytes = master->txSize;
589 LPI2C_Set_MasterTxFIFOWatermark(baseAddr, (uint16_t)(txBytes - 1U));
592 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
MTDR));
593 dmaTransParams.bufferTransfer = (uint8_t *)master->txBuff;
594 dmaTransParams.transferDirection = LPI2C_TX_REQ;
595 dmaTransParams.transferSize = master->txSize;
601 LPI2C_Set_MasterRxFIFOWatermark(baseAddr, 0U);
606 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
MRDR));
607 dmaTransParams.bufferTransfer = master->rxBuff;
608 dmaTransParams.transferDirection = LPI2C_RX_REQ;
609 dmaTransParams.transferSize = master->rxSize;
626 if (master->txSize > (uint32_t)0U)
628 (void)LPI2C_Set_MasterTxDMA(baseAddr,
true);
633 (void)LPI2C_Set_MasterRxDMA(baseAddr,
true);
650 if (slave->txSize > (uint32_t)0U)
652 dmaTransParams.dmaChannel = slave->dmaChannel;
654 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
STDR));
655 dmaTransParams.bufferTransfer = (uint8_t*)slave->txBuff;
656 dmaTransParams.transferDirection = LPI2C_TX_REQ;
657 dmaTransParams.transferSize = slave->txSize;
661 dmaTransParams.dmaChannel = slave->dmaChannel;
663 dmaTransParams.i2cDataRegAddr = (uint32_t)(&(baseAddr->
SRDR));
664 dmaTransParams.bufferTransfer = slave->rxBuff;
665 dmaTransParams.transferDirection = LPI2C_RX_REQ;
666 dmaTransParams.transferSize = slave->rxSize;
677 if (slave->txSize > (uint32_t)0U)
679 (void)LPI2C_Set_SlaveTxDMA(baseAddr,
true);
683 (void)LPI2C_Set_SlaveRxDMA(baseAddr,
true);
703 uint32_t instance = (uint32_t)parameter;
705 baseAddr = g_lpi2cBase[instance];
706 master = g_lpi2cMasterStatePtr[instance];
711 if (master->blocking ==
true)
732 baseAddr = g_lpi2cBase[instance];
733 master = g_lpi2cMasterStatePtr[instance];
736 osifError =
OSIF_SemaWait(&(master->idleSemaphore), timeout);
745 master->blocking =
false;
746 return master->status;
762 baseAddr = g_lpi2cBase[instance];
763 slave = g_lpi2cSlaveStatePtr[instance];
775 slave->blocking =
false;
776 return slave->status;
794 else if (master->txBuff != NULL)
797 if (master->txSize == 0U)
803 if (master->blocking ==
true)
810 if (master->masterCallback != NULL)
824 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_TRANSMIT_DATA_INT,
false);
841 while ((LPI2C_Get_MasterRxFIFOCount(baseAddr) > 0U) && (master->rxSize > 0U))
843 master->rxBuff[0U] = LPI2C_Get_MasterRxData(baseAddr);
847 if (master->rxSize == 0U)
853 if (master->blocking ==
true)
860 if (master->masterCallback != NULL)
865 else if (master->rxSize <= LPI2C_Get_MasterRxFIFOWatermark(baseAddr))
868 LPI2C_Set_MasterRxFIFOWatermark(baseAddr, (uint16_t)(master->rxSize - 1U));
885 uint16_t receivedAddr;
887 receivedAddr = LPI2C_Get_SlaveReceivedAddr(baseAddr);
888 if ((receivedAddr & 1U) != (uint16_t)0U)
891 if ((slave->slaveCallback != NULL) && slave->slaveListening)
896 #if defined(ERRATA_E10792)
899 LPI2C_Set_SlaveInt(g_lpi2cBase[instance], LPI2C_SLAVE_TRANSMIT_DATA_INT,
true);
903 slave->txUnderrunWarning =
false;
914 if ((slave->slaveCallback != NULL) && slave->slaveListening)
937 if (slave->txUnderrunWarning ==
true)
943 if (slave->txSize == 0U)
946 if (slave->slaveCallback != NULL)
952 if (slave->txSize == 0U)
960 slave->txUnderrunWarning =
true;
961 LPI2C_Transmit_SlaveData(baseAddr, (uint8_t)0xFFU);
965 LPI2C_Transmit_SlaveData(baseAddr, slave->txBuff[0U]);
980 if (slave->rxSize == 0U)
983 if (slave->slaveCallback != NULL)
989 if (slave->rxSize == 0U)
993 (void)LPI2C_Get_SlaveData(baseAddr);
997 slave->rxBuff[0U] = LPI2C_Get_SlaveData(baseAddr);
1022 uint32_t inputClock;
1030 DEV_ASSERT(g_lpi2cMasterStatePtr[instance] == NULL);
1037 baseAddr = g_lpi2cBase[instance];
1038 g_lpi2cMasterStatePtr[instance] = master;
1041 master->rxBuff = NULL;
1042 master->rxSize = 0U;
1043 master->txBuff = NULL;
1044 master->txSize = 0U;
1046 master->i2cIdle =
true;
1051 master->dmaChannel = userConfigPtr->
dmaChannel;
1054 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1055 master->masterCode = userConfigPtr->masterCode;
1056 master->highSpeedInProgress =
false;
1058 master->blocking =
false;
1070 LPI2C_Init(baseAddr);
1074 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1075 baudRate.baudRateHS = userConfigPtr->baudRateHS;
1083 LPI2C_Set_MasterEnable(baseAddr,
true);
1105 baseAddr = g_lpi2cBase[instance];
1106 master = g_lpi2cMasterStatePtr[instance];
1112 g_lpi2cMasterStatePtr[instance] = NULL;
1115 LPI2C_Set_MasterEnable(baseAddr,
false);
1139 uint32_t inputClock;
1143 baseAddr = g_lpi2cBase[instance];
1144 master = g_lpi2cMasterStatePtr[instance];
1155 prescaler = LPI2C_Get_MasterPrescaler(baseAddr);
1156 clkHi =LPI2C_Get_MasterClockHighPeriod(baseAddr);
1157 clkLo = LPI2C_Get_MasterClockLowPeriod(baseAddr);
1159 baudRate->
baudRate = inputClock / (((uint32_t)1U << prescaler) * (clkLo + clkHi + (uint32_t)2U));
1161 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1162 if (master->operatingMode == LPI2C_HIGHSPEED_MODE)
1164 clkHi =LPI2C_Get_MasterClockHighPeriodHS(baseAddr);
1165 clkLo = LPI2C_Get_MasterClockLowPeriodHS(baseAddr);
1167 baudRate->baudRateHS = inputClock / (((uint32_t)1U << prescaler) * (clkLo + clkHi + (uint32_t)2U));
1190 uint32_t inputClock;
1191 uint32_t minPrescaler;
1201 baseAddr = g_lpi2cBase[instance];
1202 master = g_lpi2cMasterStatePtr[instance];
1214 LPI2C_Set_MasterEnable(baseAddr,
false);
1221 minPrescaler = ((inputClock - 1U) / (baudRate.
baudRate * (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U))) + (uint32_t)1U;
1222 for (prescaler = 0U; prescaler < 7U; prescaler++)
1224 if (((uint32_t)1U << prescaler) >= minPrescaler)
1231 clkTotal = (inputClock + ((baudRate.
baudRate << prescaler) >> 1U)) / (baudRate.
baudRate << prescaler);
1232 if (clkTotal > (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U))
1234 clkTotal = (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U);
1249 clkHi = (clkTotal - 2U) / 3U;
1250 clkLo = clkTotal - 2U - clkHi;
1253 if (clkHi < CLKHI_MIN_VALUE)
1255 clkHi = CLKHI_MIN_VALUE;
1257 if (clkLo < CLKLO_MIN_VALUE)
1259 clkLo = CLKLO_MIN_VALUE;
1264 dataVd = clkHi >> 1U;
1265 if (setHold < SETHOLD_MIN_VALUE)
1267 setHold = SETHOLD_MIN_VALUE;
1269 if (dataVd < DATAVD_MIN_VALUE)
1271 dataVd = DATAVD_MIN_VALUE;
1275 LPI2C_Set_MasterPrescaler(baseAddr, (lpi2c_master_prescaler_t)prescaler);
1276 LPI2C_Set_MasterDataValidDelay(baseAddr, (uint8_t)dataVd);
1277 LPI2C_Set_MasterSetupHoldDelay(baseAddr, (uint8_t)setHold);
1278 LPI2C_Set_MasterClockHighPeriod(baseAddr, (uint8_t)clkHi);
1279 LPI2C_Set_MasterClockLowPeriod(baseAddr, (uint8_t)clkLo);
1281 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1282 if (operatingMode == LPI2C_HIGHSPEED_MODE)
1286 clkTotal = (inputClock + ((baudRate.baudRateHS << prescaler) >> 1U)) / (baudRate.baudRateHS << prescaler);
1287 if (clkTotal > (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U))
1289 clkTotal = (CLKHI_MAX_VALUE + CLKLO_MAX_VALUE + 2U);
1292 clkHi = (clkTotal - 2U) / 3U;
1293 clkLo = clkTotal - 2U - clkHi;
1294 if (clkHi < CLKHI_MIN_VALUE)
1296 clkHi = CLKHI_MIN_VALUE;
1298 if (clkLo < CLKLO_MIN_VALUE)
1300 clkLo = CLKLO_MIN_VALUE;
1305 dataVd = clkHi >> 1U;
1306 if (setHold < SETHOLD_MIN_VALUE)
1308 setHold = SETHOLD_MIN_VALUE;
1310 if (dataVd < DATAVD_MIN_VALUE)
1312 dataVd = DATAVD_MIN_VALUE;
1316 LPI2C_Set_MasterDataValidDelayHS(baseAddr, (uint8_t)dataVd);
1317 LPI2C_Set_MasterSetupHoldDelayHS(baseAddr, (uint8_t)setHold);
1318 LPI2C_Set_MasterClockHighPeriodHS(baseAddr, (uint8_t)clkHi);
1319 LPI2C_Set_MasterClockLowPeriodHS(baseAddr, (uint8_t)clkLo);
1327 LPI2C_Set_MasterEnable(baseAddr,
true);
1347 master = g_lpi2cMasterStatePtr[instance];
1350 master->slaveAddress = address;
1351 master->is10bitAddr = is10bitAddr;
1363 const uint8_t * txBuff,
1374 baseAddr = g_lpi2cBase[instance];
1375 master = g_lpi2cMasterStatePtr[instance];
1382 master->txBuff = txBuff;
1383 master->txSize = txSize;
1384 master->sendStop = sendStop;
1385 master->i2cIdle =
false;
1390 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1391 LPI2C_MASTER_ARBITRATION_LOST_INT |
1392 LPI2C_MASTER_NACK_DETECT_INT,
1406 LPI2C_Set_MasterTxFIFOWatermark(baseAddr, 0U);
1409 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1410 if (master->operatingMode == LPI2C_ULTRAFAST_MODE)
1413 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1414 LPI2C_MASTER_ARBITRATION_LOST_INT |
1415 LPI2C_MASTER_TRANSMIT_DATA_INT,
1421 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1422 LPI2C_MASTER_ARBITRATION_LOST_INT |
1423 LPI2C_MASTER_NACK_DETECT_INT |
1424 LPI2C_MASTER_TRANSMIT_DATA_INT,
1441 const uint8_t * txBuff,
1456 master->blocking =
true;
1461 master->blocking =
false;
1484 baseAddr = g_lpi2cBase[instance];
1485 master = g_lpi2cMasterStatePtr[instance];
1490 if (master->rxBuff != NULL)
1527 baseAddr = g_lpi2cBase[instance];
1528 master = g_lpi2cMasterStatePtr[instance];
1534 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1535 if (master->operatingMode == LPI2C_ULTRAFAST_MODE)
1543 master->rxSize = rxSize;
1544 master->i2cIdle =
false;
1545 master->sendStop = sendStop;
1546 master->rxBuff = rxBuff;
1551 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1552 LPI2C_MASTER_ARBITRATION_LOST_INT |
1553 LPI2C_MASTER_NACK_DETECT_INT,
1566 rxBytes = LPI2C_Get_MasterRxFIFOSize(baseAddr);
1567 if (rxBytes > rxSize)
1569 rxBytes = (uint8_t)rxSize;
1571 LPI2C_Set_MasterRxFIFOWatermark(baseAddr, (uint16_t)(rxBytes - 1U));
1577 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1578 LPI2C_MASTER_ARBITRATION_LOST_INT |
1579 LPI2C_MASTER_NACK_DETECT_INT |
1580 LPI2C_MASTER_TRANSMIT_DATA_INT |
1581 LPI2C_MASTER_RECEIVE_DATA_INT,
1586 LPI2C_Set_MasterInt(baseAddr, LPI2C_MASTER_FIFO_ERROR_INT |
1587 LPI2C_MASTER_ARBITRATION_LOST_INT |
1588 LPI2C_MASTER_NACK_DETECT_INT |
1589 LPI2C_MASTER_RECEIVE_DATA_INT,
1621 master->blocking =
true;
1626 master->blocking =
false;
1647 uint32_t *bytesRemaining)
1654 baseAddr = g_lpi2cBase[instance];
1655 master = g_lpi2cMasterStatePtr[instance];
1660 if (master->txSize > 0U)
1664 *bytesRemaining = master->txSize + LPI2C_Get_MasterTxFIFOCount(baseAddr);
1666 else if (master->rxSize > 0U)
1670 *bytesRemaining = master->rxSize - LPI2C_Get_MasterRxFIFOCount(baseAddr);
1674 *bytesRemaining = 0U;
1678 return master->status;
1695 baseAddr = g_lpi2cBase[instance];
1696 master = g_lpi2cMasterStatePtr[instance];
1700 if (LPI2C_Get_MasterTransmitDataRequestEvent(baseAddr))
1705 if (LPI2C_Get_MasterReceiveDataReadyEvent(baseAddr))
1710 if (LPI2C_Get_MasterFIFOErrorEvent(baseAddr))
1713 LPI2C_Clear_MasterFIFOErrorEvent(baseAddr);
1715 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1717 master->highSpeedInProgress =
false;
1726 if (master->blocking ==
true)
1731 if (master->masterCallback != NULL)
1737 if (LPI2C_Get_MasterArbitrationLostEvent(baseAddr))
1740 LPI2C_Clear_MasterArbitrationLostEvent(baseAddr);
1747 if (master->blocking ==
true)
1754 if (master->masterCallback != NULL)
1760 if (LPI2C_Get_MasterNACKDetectEvent(baseAddr))
1763 LPI2C_Clear_MasterNACKDetectEvent(baseAddr);
1765 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1767 if (master->operatingMode != LPI2C_ULTRAFAST_MODE)
1771 if (master->blocking ==
true)
1776 #if(LPI2C_HAS_HIGH_SPEED_MODE)
1778 master->highSpeedInProgress =
false;
1786 if (master->masterCallback != NULL)
1790 #if(LPI2C_HAS_ULTRA_FAST_MODE)
1810 uint32_t inputClock;
1816 DEV_ASSERT(g_lpi2cSlaveStatePtr[instance] == NULL);
1826 baseAddr = g_lpi2cBase[instance];
1827 g_lpi2cSlaveStatePtr[instance] = slave;
1834 slave->txBuff = NULL;
1835 slave->rxBuff = NULL;
1840 slave->dmaChannel = userConfigPtr->
dmaChannel;
1841 slave->isTransferInProgress =
false;
1842 slave->blocking =
false;
1852 LPI2C_Init(baseAddr);
1855 LPI2C_Set_SlaveAddr0(baseAddr, userConfigPtr->
slaveAddress);
1858 LPI2C_Set_SlaveAddrConfig(baseAddr, LPI2C_SLAVE_ADDR_MATCH_0_10BIT);
1862 LPI2C_Set_SlaveAddrConfig(baseAddr, LPI2C_SLAVE_ADDR_MATCH_0_7BIT);
1873 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
1874 LPI2C_SLAVE_FIFO_ERROR_INT |
1875 LPI2C_SLAVE_STOP_DETECT_INT |
1876 LPI2C_SLAVE_REPEATED_START_INT |
1877 LPI2C_SLAVE_ADDRESS_VALID_INT,
1883 #if defined(ERRATA_E10792)
1884 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
1885 LPI2C_SLAVE_FIFO_ERROR_INT |
1886 LPI2C_SLAVE_STOP_DETECT_INT |
1887 LPI2C_SLAVE_REPEATED_START_INT |
1888 LPI2C_SLAVE_ADDRESS_VALID_INT |
1889 LPI2C_SLAVE_RECEIVE_DATA_INT,
1893 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
1894 LPI2C_SLAVE_FIFO_ERROR_INT |
1895 LPI2C_SLAVE_STOP_DETECT_INT |
1896 LPI2C_SLAVE_REPEATED_START_INT |
1897 LPI2C_SLAVE_ADDRESS_VALID_INT |
1898 LPI2C_SLAVE_RECEIVE_DATA_INT |
1899 LPI2C_SLAVE_TRANSMIT_DATA_INT,
1907 LPI2C_Set_SlaveEnable(baseAddr,
true);
1929 baseAddr = g_lpi2cBase[instance];
1936 if ((slave->transferType ==
LPI2C_USING_DMA) && slave->slaveListening)
1939 (void)LPI2C_Set_SlaveRxDMA(baseAddr,
false);
1940 (void)LPI2C_Set_SlaveTxDMA(baseAddr,
false);
1943 g_lpi2cSlaveStatePtr[instance] = NULL;
1946 LPI2C_Set_SlaveEnable(baseAddr,
false);
1963 const uint8_t * txBuff,
1972 slave = g_lpi2cSlaveStatePtr[instance];
1975 slave->txBuff = txBuff;
1976 slave->txSize = txSize;
1999 slave = g_lpi2cSlaveStatePtr[instance];
2002 slave->rxBuff = rxBuff;
2003 slave->rxSize = rxSize;
2017 const uint8_t * txBuff,
2028 baseAddr = g_lpi2cBase[instance];
2029 slave = g_lpi2cSlaveStatePtr[instance];
2036 DEV_ASSERT(slave->isTransferInProgress ==
false);
2038 slave->txBuff = txBuff;
2039 slave->txSize = txSize;
2045 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2046 LPI2C_SLAVE_FIFO_ERROR_INT |
2047 LPI2C_SLAVE_STOP_DETECT_INT |
2048 LPI2C_SLAVE_REPEATED_START_INT |
2049 LPI2C_SLAVE_ADDRESS_VALID_INT,
2053 LPI2C_Set_SlaveEnable(baseAddr,
true);
2055 slave->isTransferInProgress =
true;
2062 #if defined(ERRATA_E10792)
2064 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2065 LPI2C_SLAVE_FIFO_ERROR_INT |
2066 LPI2C_SLAVE_STOP_DETECT_INT |
2067 LPI2C_SLAVE_REPEATED_START_INT |
2068 LPI2C_SLAVE_ADDRESS_VALID_INT,
2072 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2073 LPI2C_SLAVE_FIFO_ERROR_INT |
2074 LPI2C_SLAVE_STOP_DETECT_INT |
2075 LPI2C_SLAVE_REPEATED_START_INT |
2076 LPI2C_SLAVE_ADDRESS_VALID_INT |
2077 LPI2C_SLAVE_TRANSMIT_DATA_INT,
2083 LPI2C_Set_SlaveEnable(baseAddr,
true);
2085 slave->isTransferInProgress =
true;
2100 const uint8_t * txBuff,
2114 slave->blocking =
true;
2145 baseAddr = g_lpi2cBase[instance];
2146 slave = g_lpi2cSlaveStatePtr[instance];
2153 DEV_ASSERT(slave->isTransferInProgress ==
false);
2155 slave->rxBuff = rxBuff;
2156 slave->rxSize = rxSize;
2162 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2163 LPI2C_SLAVE_FIFO_ERROR_INT |
2164 LPI2C_SLAVE_STOP_DETECT_INT |
2165 LPI2C_SLAVE_REPEATED_START_INT |
2166 LPI2C_SLAVE_ADDRESS_VALID_INT,
2170 LPI2C_Set_SlaveEnable(baseAddr,
true);
2172 slave->isTransferInProgress =
true;
2178 slave->isTransferInProgress =
true;
2181 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_BIT_ERROR_INT |
2182 LPI2C_SLAVE_FIFO_ERROR_INT |
2183 LPI2C_SLAVE_STOP_DETECT_INT |
2184 LPI2C_SLAVE_REPEATED_START_INT |
2185 LPI2C_SLAVE_ADDRESS_VALID_INT |
2186 LPI2C_SLAVE_RECEIVE_DATA_INT,
2190 LPI2C_Set_SlaveEnable(baseAddr,
true);
2219 slave->blocking =
true;
2244 uint32_t *bytesRemaining)
2250 slave = g_lpi2cSlaveStatePtr[instance];
2255 if (slave->txSize > 0U)
2258 *bytesRemaining = slave->txSize;
2260 else if (slave->rxSize > 0U)
2263 *bytesRemaining = slave->rxSize;
2267 *bytesRemaining = 0U;
2271 return slave->status;
2289 baseAddr = g_lpi2cBase[instance];
2290 slave = g_lpi2cSlaveStatePtr[instance];
2293 if (!slave->slaveListening)
2295 DEV_ASSERT(slave->isTransferInProgress ==
true);
2315 bool stopDetect =
false, repeatStartDetect =
false;
2319 baseAddr = g_lpi2cBase[instance];
2320 slave = g_lpi2cSlaveStatePtr[instance];
2324 if (LPI2C_Get_SlaveAddressValidEvent(baseAddr))
2329 if (LPI2C_Get_SlaveTransmitDataEvent(baseAddr))
2331 if (LPI2C_Get_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT))
2337 if (LPI2C_Get_SlaveReceiveDataEvent(baseAddr))
2339 if (LPI2C_Get_SlaveInt(baseAddr, LPI2C_SLAVE_RECEIVE_DATA_INT))
2345 stopDetect = LPI2C_Get_SlaveSTOPDetectEvent(baseAddr);
2346 repeatStartDetect = LPI2C_Get_SlaveRepeatedStartEvent(baseAddr);
2347 if ((stopDetect ==
true) || (repeatStartDetect ==
true))
2350 LPI2C_Clear_SlaveSTOPDetectEvent(baseAddr);
2351 LPI2C_Clear_SlaveRepeatedStartEvent(baseAddr);
2353 #if defined(ERRATA_E10792)
2355 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT,
false);
2369 if (!slave->slaveListening)
2374 if (slave->blocking ==
true)
2380 if(slave->slaveCallback != NULL)
2386 if (LPI2C_Get_SlaveBitErrorEvent(baseAddr))
2389 LPI2C_Clear_SlaveBitErrorEvent(baseAddr);
2391 #if defined(ERRATA_E10792)
2393 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT,
false);
2400 if (!slave->slaveListening){
2405 if (slave->blocking ==
true)
2411 if(slave->slaveCallback != NULL)
2417 if (LPI2C_Get_SlaveFIFOErrorEvent(baseAddr))
2422 LPI2C_Clear_SlaveFIFOErrorEvent(baseAddr);
2424 #if defined(ERRATA_E10792)
2426 LPI2C_Set_SlaveInt(baseAddr, LPI2C_SLAVE_TRANSMIT_DATA_INT,
false);
2433 if (!slave->slaveListening)
2438 if (slave->blocking ==
true)
2444 if(slave->slaveCallback != NULL)
static void LPI2C_DRV_SlaveSetOperatingMode(uint32_t instance, lpi2c_mode_t operatingMode)
status_t LPI2C_DRV_SlaveGetTransferStatus(uint32_t instance, uint32_t *bytesRemaining)
Return the current status of the I2C slave transfer.
static void LPI2C_DRV_MasterEndTransfer(LPI2C_Type *baseAddr, lpi2c_master_state_t *master, bool sendStop, bool resetFIFO)
lpi2c_mode_t operatingMode
lpi2c_slave_callback_t slaveCallback
status_t LPI2C_DRV_MasterGetTransferStatus(uint32_t instance, uint32_t *bytesRemaining)
Return the current status of the I2C master transfer.
status_t OSIF_SemaDestroy(const semaphore_t *const pSem)
Destroys a previously created semaphore.
static void LPI2C_DRV_MasterHandleTransmitDataRequest(uint32_t instance, LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
status_t LPI2C_DRV_MasterAbortTransferData(uint32_t instance)
Abort a non-blocking I2C Master transmission or reception.
edma_transfer_type_t
A type for the DMA transfer. Implements : edma_transfer_type_t_Class.
static void LPI2C_DRV_MasterQueueCmd(LPI2C_Type *baseAddr, lpi2c_master_state_t *master, lpi2c_master_command_t cmd, uint8_t data)
static bool LPI2C_DRV_MasterCmdQueueEmpty(const lpi2c_master_state_t *master)
static status_t LPI2C_DRV_SlaveWaitTransferEnd(uint32_t instance, uint32_t timeout)
lpi2c_transfer_type_t transferType
static void LPI2C_DRV_MasterQueueData(LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
static void LPI2C_DRV_SlaveStartDmaTransfer(uint32_t instance)
status_t EDMA_DRV_StopChannel(uint8_t channel)
Stops the eDMA channel.
lpi2c_master_callback_t masterCallback
static void LPI2C_DRV_SlaveHandleTransmitDataEvent(uint32_t instance, LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)
status_t LPI2C_DRV_SlaveReceiveData(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize)
Perform a non-blocking receive transaction on the I2C bus.
static void LPI2C_DRV_SlaveHandleAddressValidEvent(uint32_t instance, const LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)
static void LPI2C_DRV_MasterSendQueuedCmd(LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
status_t LPI2C_DRV_SlaveSendDataBlocking(uint32_t instance, const uint8_t *txBuff, uint32_t txSize, uint32_t timeout)
Perform a blocking send transaction on the I2C bus.
status_t OSIF_SemaCreate(semaphore_t *const pSem, const uint8_t initValue)
Creates a semaphore with a given value.
static void LPI2C_DRV_MasterCompleteDMATransfer(void *parameter, edma_chn_status_t status)
status_t EDMA_DRV_SetChannelRequest(uint8_t channel, uint8_t req)
Configures the DMA request for the eDMA channel.
lpi2c_transfer_type_t transferType
lpi2c_mode_t
I2C operating modes Implements : lpi2c_mode_t_Class.
void EDMA_DRV_DisableRequestsOnTransferComplete(uint8_t channel, bool disable)
Disables/Enables the DMA request after the major loop completes for the TCD.
void LPI2C_DRV_MasterSetSlaveAddr(uint32_t instance, const uint16_t address, const bool is10bitAddr)
Set the slave address for any subsequent I2C communication.
#define LPI2C_MASTER_IRQS
status_t LPI2C_DRV_SlaveSetRxBuffer(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize)
Provide a buffer for receiving data.
static void LPI2C_DRV_ConfigureDmaTransfer(uint32_t instance, const lpi2c_dma_transfer_params_t *dmaTransParams)
void INT_SYS_DisableIRQ(IRQn_Type irqNumber)
Disables an interrupt for a given IRQ number.
void EDMA_DRV_SetSrcLastAddrAdjustment(uint8_t channel, int32_t adjust)
Configures the source address last adjustment.
void LPI2C_DRV_MasterGetBaudRate(uint32_t instance, lpi2c_baud_rate_params_t *baudRate)
Get the currently configured baud rate.
status_t LPI2C_DRV_MasterReceiveDataBlocking(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize, bool sendStop, uint32_t timeout)
Perform a blocking receive transaction on the I2C bus.
static void LPI2C_DRV_MasterHandleReceiveDataReadyEvent(uint32_t instance, LPI2C_Type *baseAddr, lpi2c_master_state_t *master)
status_t LPI2C_DRV_MasterSendData(uint32_t instance, const uint8_t *txBuff, uint32_t txSize, bool sendStop)
Perform a non-blocking send transaction on the I2C bus.
static void LPI2C_DRV_MasterResetQueue(lpi2c_master_state_t *master)
status_t LPI2C_DRV_SlaveSetTxBuffer(uint32_t instance, const uint8_t *txBuff, uint32_t txSize)
Provide a buffer for transmitting data.
edma_chn_status_t
Channel status for eDMA channel.
clock_names_t
Clock names.
Slave configuration structure.
Slave internal context structure.
static void LPI2C_DRV_MasterStartDmaTransfer(uint32_t instance)
status_t LPI2C_DRV_SlaveSendData(uint32_t instance, const uint8_t *txBuff, uint32_t txSize)
Perform a non-blocking send transaction on the I2C bus.
status_t LPI2C_DRV_SlaveAbortTransferData(uint32_t instance)
Abort a non-blocking I2C Master transmission or reception.
status_t CLOCK_SYS_GetFreq(clock_names_t clockName, uint32_t *frequency)
Gets the clock frequency for a specific clock name.
static void LPI2C_DRV_MasterSendAddress(LPI2C_Type *baseAddr, lpi2c_master_state_t *master, bool receive)
void LPI2C_DRV_MasterIRQHandler(uint32_t instance)
Handle master operation when I2C interrupt occurs.
status_t
Status return codes. Common error codes will be a unified enumeration (C enum) that will contain all ...
status_t LPI2C_DRV_MasterInit(uint32_t instance, const lpi2c_master_user_config_t *userConfigPtr, lpi2c_master_state_t *master)
Initialize the LPI2C master mode driver.
status_t LPI2C_DRV_MasterDeinit(uint32_t instance)
De-initialize the LPI2C master mode driver.
void LPI2C_DRV_SlaveIRQHandler(uint32_t instance)
Handle slave operation when I2C interrupt occurs.
Master configuration structure.
status_t OSIF_SemaWait(semaphore_t *const pSem, const uint32_t timeout)
Decrement a semaphore with timeout.
status_t EDMA_DRV_StartChannel(uint8_t channel)
Starts an eDMA channel.
static void LPI2C_DRV_SlaveHandleReceiveDataEvent(uint32_t instance, const LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)
status_t LPI2C_DRV_SlaveDeinit(uint32_t instance)
De-initialize the I2C slave mode driver.
static status_t LPI2C_DRV_MasterWaitTransferEnd(uint32_t instance, uint32_t timeout)
status_t OSIF_SemaPost(semaphore_t *const pSem)
Increment a semaphore.
lpi2c_mode_t operatingMode
void INT_SYS_EnableIRQ(IRQn_Type irqNumber)
Enables an interrupt for a given IRQ number.
void LPI2C_DRV_MasterSetBaudRate(uint32_t instance, const lpi2c_mode_t operatingMode, const lpi2c_baud_rate_params_t baudRate)
Set the baud rate for any subsequent I2C communication.
lpi2c_dma_transfer_params_t
Master internal context structure.
status_t LPI2C_DRV_MasterReceiveData(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize, bool sendStop)
Perform a non-blocking receive transaction on the I2C bus.
status_t LPI2C_DRV_SlaveReceiveDataBlocking(uint32_t instance, uint8_t *rxBuff, uint32_t rxSize, uint32_t timeout)
Perform a blocking receive transaction on the I2C bus.
status_t LPI2C_DRV_SlaveInit(uint32_t instance, const lpi2c_slave_user_config_t *userConfigPtr, lpi2c_slave_state_t *slave)
Initialize the I2C slave mode driver.
static void LPI2C_DRV_MasterSetOperatingMode(uint32_t instance, lpi2c_mode_t operatingMode)
status_t LPI2C_DRV_MasterSendDataBlocking(uint32_t instance, const uint8_t *txBuff, uint32_t txSize, bool sendStop, uint32_t timeout)
Perform a blocking send transaction on the I2C bus.
status_t EDMA_DRV_ConfigMultiBlockTransfer(uint8_t channel, edma_transfer_type_t type, uint32_t srcAddr, uint32_t destAddr, edma_transfer_size_t transferSize, uint32_t blockSize, uint32_t blockCount, bool disableReqOnCompletion)
Configures a multiple block data transfer with DMA.
status_t EDMA_DRV_InstallCallback(uint8_t channel, edma_callback_t callback, void *parameter)
Registers the callback function and the parameter for eDMA channel.
#define LPI2C_INSTANCE_COUNT
IRQn_Type
Defines the Interrupt Numbers definitions.
static void LPI2C_DRV_SlaveEndTransfer(LPI2C_Type *baseAddr, lpi2c_slave_state_t *slave)