SAMV71 Xplained Ultra Software Package 1.4

instance_usart0.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2014, Atmel Corporation                                        */
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00011 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
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00029 
00030 #ifndef _SAMV71_USART0_INSTANCE_
00031 #define _SAMV71_USART0_INSTANCE_
00032 
00033 /* ========== Register definition for USART0 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_USART0_CR                        (0x40024000U) /**< \brief (USART0) Control Register */
00036   #define REG_USART0_MR                        (0x40024004U) /**< \brief (USART0) Mode Register */
00037   #define REG_USART0_IER                       (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
00038   #define REG_USART0_IDR                       (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
00039   #define REG_USART0_IMR                       (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
00040   #define REG_USART0_CSR                       (0x40024014U) /**< \brief (USART0) Channel Status Register */
00041   #define REG_USART0_RHR                       (0x40024018U) /**< \brief (USART0) Receive Holding Register */
00042   #define REG_USART0_THR                       (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
00043   #define REG_USART0_BRGR                      (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
00044   #define REG_USART0_RTOR                      (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
00045   #define REG_USART0_TTGR                      (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
00046   #define REG_USART0_MAN                       (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
00047   #define REG_USART0_LINMR                     (0x40024054U) /**< \brief (USART0) LIN Mode Register */
00048   #define REG_USART0_LINIR                     (0x40024058U) /**< \brief (USART0) LIN Identifier Register */
00049   #define REG_USART0_LINBRR                    (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
00050   #define REG_USART0_LONMR                     (0x40024060U) /**< \brief (USART0) LON Mode Register */
00051   #define REG_USART0_LONPR                     (0x40024064U) /**< \brief (USART0) LON Preamble Register */
00052   #define REG_USART0_LONDL                     (0x40024068U) /**< \brief (USART0) LON Data Length Register */
00053   #define REG_USART0_LONL2HDR                  (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
00054   #define REG_USART0_LONBL                     (0x40024070U) /**< \brief (USART0) LON Backlog Register */
00055   #define REG_USART0_LONB1TX                   (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
00056   #define REG_USART0_LONB1RX                   (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
00057   #define REG_USART0_LONPRIO                   (0x4002407CU) /**< \brief (USART0) LON Priority Register */
00058   #define REG_USART0_IDTTX                     (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
00059   #define REG_USART0_IDTRX                     (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
00060   #define REG_USART0_ICDIFF                    (0x40024088U) /**< \brief (USART0) IC DIFF Register */
00061   #define REG_USART0_WPMR                      (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
00062   #define REG_USART0_WPSR                      (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
00063 #else
00064   #define REG_USART0_CR       (*(__O  uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */
00065   #define REG_USART0_MR       (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */
00066   #define REG_USART0_IER      (*(__O  uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */
00067   #define REG_USART0_IDR      (*(__O  uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */
00068   #define REG_USART0_IMR      (*(__I  uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */
00069   #define REG_USART0_CSR      (*(__I  uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */
00070   #define REG_USART0_RHR      (*(__I  uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */
00071   #define REG_USART0_THR      (*(__O  uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */
00072   #define REG_USART0_BRGR     (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */
00073   #define REG_USART0_RTOR     (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */
00074   #define REG_USART0_TTGR     (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */
00075   #define REG_USART0_MAN      (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */
00076   #define REG_USART0_LINMR    (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */
00077   #define REG_USART0_LINIR    (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */
00078   #define REG_USART0_LINBRR   (*(__I  uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */
00079   #define REG_USART0_LONMR    (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */
00080   #define REG_USART0_LONPR    (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */
00081   #define REG_USART0_LONDL    (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */
00082   #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */
00083   #define REG_USART0_LONBL    (*(__I  uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */
00084   #define REG_USART0_LONB1TX  (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */
00085   #define REG_USART0_LONB1RX  (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */
00086   #define REG_USART0_LONPRIO  (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */
00087   #define REG_USART0_IDTTX    (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */
00088   #define REG_USART0_IDTRX    (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */
00089   #define REG_USART0_ICDIFF   (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */
00090   #define REG_USART0_WPMR     (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */
00091   #define REG_USART0_WPSR     (*(__I  uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */
00092 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00093 
00094 #endif /* _SAMV71_USART0_INSTANCE_ */
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