SAMV71 Xplained Ultra Software Package 1.4

instance_spi1.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
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00005 /* Copyright (c) 2014, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_SPI1_INSTANCE_
00031 #define _SAMV71_SPI1_INSTANCE_
00032 
00033 /* ========== Register definition for SPI1 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_SPI1_CR                    (0x40058000U) /**< \brief (SPI1) Control Register */
00036   #define REG_SPI1_MR                    (0x40058004U) /**< \brief (SPI1) Mode Register */
00037   #define REG_SPI1_RDR                   (0x40058008U) /**< \brief (SPI1) Receive Data Register */
00038   #define REG_SPI1_TDR                   (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
00039   #define REG_SPI1_SR                    (0x40058010U) /**< \brief (SPI1) Status Register */
00040   #define REG_SPI1_IER                   (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
00041   #define REG_SPI1_IDR                   (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
00042   #define REG_SPI1_IMR                   (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
00043   #define REG_SPI1_CSR                   (0x40058030U) /**< \brief (SPI1) Chip Select Register */
00044   #define REG_SPI1_WPMR                  (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
00045   #define REG_SPI1_WPSR                  (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
00046 #else
00047   #define REG_SPI1_CR   (*(__O  uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */
00048   #define REG_SPI1_MR   (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */
00049   #define REG_SPI1_RDR  (*(__I  uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */
00050   #define REG_SPI1_TDR  (*(__O  uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */
00051   #define REG_SPI1_SR   (*(__I  uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */
00052   #define REG_SPI1_IER  (*(__O  uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */
00053   #define REG_SPI1_IDR  (*(__O  uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */
00054   #define REG_SPI1_IMR  (*(__I  uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */
00055   #define REG_SPI1_CSR  (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */
00056   #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */
00057   #define REG_SPI1_WPSR (*(__I  uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */
00058 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00059 
00060 #endif /* _SAMV71_SPI1_INSTANCE_ */
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