Data Structures | |
struct | Twi |
Twi hardware registers. More... | |
Defines | |
#define | TWI_CR_START (0x1u << 0) |
(TWI_CR) Send a START Condition | |
#define | TWI_CR_STOP (0x1u << 1) |
(TWI_CR) Send a STOP Condition | |
#define | TWI_CR_MSEN (0x1u << 2) |
(TWI_CR) TWI Master Mode Enabled | |
#define | TWI_CR_MSDIS (0x1u << 3) |
(TWI_CR) TWI Master Mode Disabled | |
#define | TWI_CR_SVEN (0x1u << 4) |
(TWI_CR) TWI Slave Mode Enabled | |
#define | TWI_CR_SVDIS (0x1u << 5) |
(TWI_CR) TWI Slave Mode Disabled | |
#define | TWI_CR_QUICK (0x1u << 6) |
(TWI_CR) SMBUS Quick Command | |
#define | TWI_CR_SWRST (0x1u << 7) |
(TWI_CR) Software Reset | |
#define | TWI_MMR_IADRSZ_Pos 8 |
#define | TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) |
(TWI_MMR) Internal Device Address Size | |
#define | TWI_MMR_IADRSZ_NONE (0x0u << 8) |
(TWI_MMR) No internal device address | |
#define | TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) |
(TWI_MMR) One-byte internal device address | |
#define | TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) |
(TWI_MMR) Two-byte internal device address | |
#define | TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) |
(TWI_MMR) Three-byte internal device address | |
#define | TWI_MMR_MREAD (0x1u << 12) |
(TWI_MMR) Master Read Direction | |
#define | TWI_MMR_DADR_Pos 16 |
#define | TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) |
(TWI_MMR) Device Address | |
#define | TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) |
#define | TWI_SMR_SADR_Pos 16 |
#define | TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) |
(TWI_SMR) Slave Address | |
#define | TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) |
#define | TWI_IADR_IADR_Pos 0 |
#define | TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) |
(TWI_IADR) Internal Address | |
#define | TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) |
#define | TWI_CWGR_CLDIV_Pos 0 |
#define | TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) |
(TWI_CWGR) Clock Low Divider | |
#define | TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) |
#define | TWI_CWGR_CHDIV_Pos 8 |
#define | TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) |
(TWI_CWGR) Clock High Divider | |
#define | TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) |
#define | TWI_CWGR_CKDIV_Pos 16 |
#define | TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) |
(TWI_CWGR) Clock Divider | |
#define | TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) |
#define | TWI_CWGR_HOLD_Pos 24 |
#define | TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) |
(TWI_CWGR) TWD Hold Time versus TWCK falling | |
#define | TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos))) |
#define | TWI_SR_TXCOMP (0x1u << 0) |
(TWI_SR) Transmission Completed (automatically set / reset) | |
#define | TWI_SR_RXRDY (0x1u << 1) |
(TWI_SR) Receive Holding Register Ready (automatically set / reset) | |
#define | TWI_SR_TXRDY (0x1u << 2) |
(TWI_SR) Transmit Holding Register Ready (automatically set / reset) | |
#define | TWI_SR_SVREAD (0x1u << 3) |
(TWI_SR) Slave Read (automatically set / reset) | |
#define | TWI_SR_SVACC (0x1u << 4) |
(TWI_SR) Slave Access (automatically set / reset) | |
#define | TWI_SR_GACC (0x1u << 5) |
(TWI_SR) General Call Access (clear on read) | |
#define | TWI_SR_OVRE (0x1u << 6) |
(TWI_SR) Overrun Error (clear on read) | |
#define | TWI_SR_NACK (0x1u << 8) |
(TWI_SR) Not Acknowledged (clear on read) | |
#define | TWI_SR_ARBLST (0x1u << 9) |
(TWI_SR) Arbitration Lost (clear on read) | |
#define | TWI_SR_SCLWS (0x1u << 10) |
(TWI_SR) Clock Wait State (automatically set / reset) | |
#define | TWI_SR_EOSACC (0x1u << 11) |
(TWI_SR) End Of Slave Access (clear on read) | |
#define | TWI_IER_TXCOMP (0x1u << 0) |
(TWI_IER) Transmission Completed Interrupt Enable | |
#define | TWI_IER_RXRDY (0x1u << 1) |
(TWI_IER) Receive Holding Register Ready Interrupt Enable | |
#define | TWI_IER_TXRDY (0x1u << 2) |
(TWI_IER) Transmit Holding Register Ready Interrupt Enable | |
#define | TWI_IER_SVACC (0x1u << 4) |
(TWI_IER) Slave Access Interrupt Enable | |
#define | TWI_IER_GACC (0x1u << 5) |
(TWI_IER) General Call Access Interrupt Enable | |
#define | TWI_IER_OVRE (0x1u << 6) |
(TWI_IER) Overrun Error Interrupt Enable | |
#define | TWI_IER_NACK (0x1u << 8) |
(TWI_IER) Not Acknowledge Interrupt Enable | |
#define | TWI_IER_ARBLST (0x1u << 9) |
(TWI_IER) Arbitration Lost Interrupt Enable | |
#define | TWI_IER_SCL_WS (0x1u << 10) |
(TWI_IER) Clock Wait State Interrupt Enable | |
#define | TWI_IER_EOSACC (0x1u << 11) |
(TWI_IER) End Of Slave Access Interrupt Enable | |
#define | TWI_IDR_TXCOMP (0x1u << 0) |
(TWI_IDR) Transmission Completed Interrupt Disable | |
#define | TWI_IDR_RXRDY (0x1u << 1) |
(TWI_IDR) Receive Holding Register Ready Interrupt Disable | |
#define | TWI_IDR_TXRDY (0x1u << 2) |
(TWI_IDR) Transmit Holding Register Ready Interrupt Disable | |
#define | TWI_IDR_SVACC (0x1u << 4) |
(TWI_IDR) Slave Access Interrupt Disable | |
#define | TWI_IDR_GACC (0x1u << 5) |
(TWI_IDR) General Call Access Interrupt Disable | |
#define | TWI_IDR_OVRE (0x1u << 6) |
(TWI_IDR) Overrun Error Interrupt Disable | |
#define | TWI_IDR_NACK (0x1u << 8) |
(TWI_IDR) Not Acknowledge Interrupt Disable | |
#define | TWI_IDR_ARBLST (0x1u << 9) |
(TWI_IDR) Arbitration Lost Interrupt Disable | |
#define | TWI_IDR_SCL_WS (0x1u << 10) |
(TWI_IDR) Clock Wait State Interrupt Disable | |
#define | TWI_IDR_EOSACC (0x1u << 11) |
(TWI_IDR) End Of Slave Access Interrupt Disable | |
#define | TWI_IMR_TXCOMP (0x1u << 0) |
(TWI_IMR) Transmission Completed Interrupt Mask | |
#define | TWI_IMR_RXRDY (0x1u << 1) |
(TWI_IMR) Receive Holding Register Ready Interrupt Mask | |
#define | TWI_IMR_TXRDY (0x1u << 2) |
(TWI_IMR) Transmit Holding Register Ready Interrupt Mask | |
#define | TWI_IMR_SVACC (0x1u << 4) |
(TWI_IMR) Slave Access Interrupt Mask | |
#define | TWI_IMR_GACC (0x1u << 5) |
(TWI_IMR) General Call Access Interrupt Mask | |
#define | TWI_IMR_OVRE (0x1u << 6) |
(TWI_IMR) Overrun Error Interrupt Mask | |
#define | TWI_IMR_NACK (0x1u << 8) |
(TWI_IMR) Not Acknowledge Interrupt Mask | |
#define | TWI_IMR_ARBLST (0x1u << 9) |
(TWI_IMR) Arbitration Lost Interrupt Mask | |
#define | TWI_IMR_SCL_WS (0x1u << 10) |
(TWI_IMR) Clock Wait State Interrupt Mask | |
#define | TWI_IMR_EOSACC (0x1u << 11) |
(TWI_IMR) End Of Slave Access Interrupt Mask | |
#define | TWI_RHR_RXDATA_Pos 0 |
#define | TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) |
(TWI_RHR) Master or Slave Receive Holding Data | |
#define | TWI_THR_TXDATA_Pos 0 |
#define | TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) |
(TWI_THR) Master or Slave Transmit Holding Data | |
#define | TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) |
#define | TWI_WPMR_WPEN (0x1u << 0) |
(TWI_WPMR) Write Protection Enable | |
#define | TWI_WPMR_WPKEY_Pos 8 |
#define | TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) |
(TWI_WPMR) Write Protection Key | |
#define | TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) |
(TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 | |
#define | TWI_WPSR_WPVS (0x1u << 0) |
(TWI_WPSR) Write Protection Violation Status | |
#define | TWI_WPSR_WPVSRC_Pos 8 |
#define | TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) |
(TWI_WPSR) Write Protection Violation Source |
SOFTWARE API DEFINITION FOR Two-wire Interface