SAMV71 Xplained Ultra Software Package 1.4

exceptions.c

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2014, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /**
00031  * \file
00032  * This file contains the default exception handlers.
00033  *
00034  * \note
00035  * The exception handler has weak aliases.
00036  * As they are weak aliases, any function with the same name will override
00037  * this definition.
00038  */
00039 
00040 /*----------------------------------------------------------------------------
00041  *        Headers
00042  *----------------------------------------------------------------------------*/
00043 
00044 #include "chip.h"
00045 
00046 /*----------------------------------------------------------------------------
00047  *        Exported functions
00048  *----------------------------------------------------------------------------*/
00049 
00050 /**
00051  * \brief Default NMI interrupt handler.
00052  */
00053 void NMI_Handler( void )
00054 {
00055     while ( 1 ) ;
00056 }
00057 
00058 /**
00059  * \brief This function back trace the stack to give exact address where fault 
00060  happened
00061 **/
00062 #if (TRACE_LEVEL > 4) 
00063 __STATIC_INLINE uint32_t StackUnwind(void)
00064 {
00065     uint32_t Fault_Add;
00066 
00067 #if defined (__CC_ARM)
00068     uint32_t temp;
00069     __ASM("mrs temp, msp ");
00070     __ASM{ ldr Fault_Add, [temp,#28]}
00071 #else
00072     __ASM("mrs r0, msp ");
00073     __ASM("ldr %0, [r0,#28]" : "=r" (Fault_Add));
00074 #endif
00075     return Fault_Add;
00076 }
00077 #endif
00078 
00079 /**
00080  * \brief If Other Faults are enabled then HardFault error will look for those 
00081  *  errors to give more detail about fault
00082 **/
00083 static void HardFault_reason(void)
00084 {
00085     uint32_t CFSRValue; 
00086     TRACE_DEBUG("In Hard Fault Handler\n\r");
00087     TRACE_DEBUG("SCB->HFSR = 0x%08x\n\r", SCB->HFSR);
00088 
00089     if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk)) {
00090         TRACE_DEBUG("Debug Event Hard Fault\n\r");
00091         TRACE_DEBUG("SCB->DFSR = 0x%08x\n", SCB->DFSR );
00092     }
00093 
00094     if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk)) {
00095         TRACE_DEBUG("Fault was due to vector table read on \
00096             exception processing\n\r");
00097     }
00098     // Forced HardFault
00099     if ((SCB->HFSR & SCB_HFSR_FORCED_Msk)) {
00100         TRACE_DEBUG("Forced Hard Fault\n\r");
00101         TRACE_DEBUG("SCB->CFSR = 0x%08x\n\r", SCB->CFSR );
00102         // Usage Fault
00103         if((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk)) 
00104         {
00105             CFSRValue = SCB->CFSR;
00106             TRACE_DEBUG("Usage fault: ");
00107             CFSRValue >>= SCB_CFSR_USGFAULTSR_Pos;
00108             if((CFSRValue & (1 << 9))) {
00109                 TRACE_DEBUG("Divide by zero\n\r");
00110             }
00111             if((CFSRValue & (1 << 8))) {
00112                 TRACE_DEBUG("Unaligned access error\n\r");
00113             }
00114             if((CFSRValue & (1 << 3))) {
00115                 TRACE_DEBUG("Coprocessor access error\n\r");
00116             }
00117             if((CFSRValue & (1 << 2))) {
00118                 TRACE_DEBUG("Integrity check error on EXC_RETURN\n\r");
00119             }
00120         }
00121         // Bus Fault
00122         if((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk)) {
00123             CFSRValue = SCB->CFSR;
00124             TRACE_DEBUG("Bus fault: ");
00125             CFSRValue >>= SCB_CFSR_BUSFAULTSR_Pos;
00126 
00127             if((CFSRValue & (1 << 7)) && (CFSRValue & (1 << 1))) {
00128                 TRACE_DEBUG("Precise data access error. Bus Fault Address \
00129                     Register is: %x \n\r", SCB->BFAR );
00130             }
00131             if((CFSRValue & (1 << 4))) {
00132                 TRACE_DEBUG("Bus fault has occurred on exception entry\n\r");
00133             }
00134             if((CFSRValue & (1 << 3))) {
00135                 TRACE_DEBUG("bus fault has occurred on exception return\n\r");
00136             }
00137             if((CFSRValue & (1 << 2))) {
00138                 TRACE_DEBUG("Imprecise data access error\n\r");
00139             }
00140 
00141             if((CFSRValue & (1 << 0))) {
00142                 TRACE_DEBUG("This bit indicates a bus fault on an instruction \
00143                     pre-fetch. \n\r");
00144             }
00145         }
00146     }
00147     // MemoryFault
00148     if((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk)) {
00149         CFSRValue = SCB->CFSR;
00150         TRACE_DEBUG("Memory fault: ");
00151         CFSRValue >>= SCB_CFSR_MEMFAULTSR_Pos;
00152         if((CFSRValue & (1 << 9)) != 0) {
00153             TRACE_DEBUG("Divide by zero\n\r");
00154         }
00155     }
00156     __ISB();
00157     __DMB();
00158     __ASM volatile("BKPT #01");
00159 }
00160 /**
00161  * \brief Default HardFault interrupt handler.
00162  */
00163 
00164 void HardFault_Handler( void )
00165 {
00166     TRACE_DEBUG("\n\rHardFault at address 0X%x\n\r", StackUnwind());
00167     __ISB();
00168     __DMB();
00169     HardFault_reason();
00170 }
00171 
00172 #ifndef MPU_EXAMPLE_FEATURE
00173 /**
00174  * \brief Default MemManage interrupt handler.
00175  */
00176 void MemManage_Handler( void )
00177 {
00178     TRACE_DEBUG("\n\rMemoryMemFault (MPU fault) at address 0X%x\n\r",
00179         StackUnwind());
00180     __ISB();
00181     __DMB();
00182     __ASM volatile("BKPT #01");
00183 }
00184 #endif
00185 
00186 /**
00187  * \brief Default BusFault interrupt handler.
00188  */
00189 void BusFault_Handler( void )
00190 {
00191     __ASM("nop");
00192     __ASM("nop");
00193     TRACE_DEBUG("\n\rBus Fault at address 0X%x\n\r", StackUnwind());
00194 
00195     __ISB();
00196     __DMB();
00197     __ASM volatile("BKPT #01");
00198 }
00199 
00200 /**
00201  * \brief Default UsageFault interrupt handler.
00202  */
00203 void UsageFault_Handler( void )
00204 {
00205     TRACE_DEBUG("\r\nUsage fault at address 0X%x", StackUnwind());
00206 
00207     __ISB();
00208     __DMB();
00209     __ASM volatile("BKPT #01");  
00210 }
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