SAMV71 Xplained Ultra Software Package 1.4

usbhs.h

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License 
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2010, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /** \file */
00031 
00032 #ifndef USBHS_H
00033 #define USBHS_H
00034 /** addtogroup usbd_hal
00035  *@{
00036  */
00037 
00038 #define  USB_DEVICE_HS_SUPPORT
00039 
00040 //! Control endpoint size
00041 #define  USB_DEVICE_EP_CTRL_SIZE       64
00042 
00043 /** Indicates chip has an UDP High Speed. */
00044 #define CHIP_USB_UDP
00045 
00046 /** Indicates chip has an internal pull-up. */
00047 #define CHIP_USB_PULLUP_INTERNAL
00048 
00049 /** Number of USB endpoints */
00050 #define CHIP_USB_NUMENDPOINTS   10
00051 
00052 /** Endpoints max packet size */
00053 #define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \
00054    ((ep == 0) ? 64 : 1024)
00055 
00056 /** Endpoints Number of Bank */
00057 #define CHIP_USB_ENDPOINTS_BANKS(ep)            ((ep==0)?1:((ep<=2)?3:2))
00058      
00059      
00060 #define CHIP_USB_ENDPOINTS_HBW(ep)               ((((ep)>=1) &&((ep)<=2))?true:false)
00061 
00062 /** Endpoints DMA support */
00063 #define CHIP_USB_ENDPOINTS_DMA(ep)              ((((ep)>=1)&&((ep)<=7))?true:false)
00064     
00065 /** Max size of the FMA FIFO */
00066 #define DMA_MAX_FIFO_SIZE     (65536/1)
00067 /** fifo space size in DW */
00068 #define EPT_VIRTUAL_SIZE      16384     
00069          
00070      
00071      //! @name USBHS Host IP properties
00072 //!
00073 //! @{
00074 //! Get maximal number of endpoints
00075 #define uhd_get_pipe_max_nbr()                (9)
00076 #define USBHS_EPT_NUM                        (uhd_get_pipe_max_nbr()+1)
00077   //! Get maximal number of banks of endpoints
00078 #define uhd_get_pipe_bank_max_nbr(ep)         ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2))
00079   //! Get maximal size of endpoint (3X, 1024/64)
00080 #define uhd_get_pipe_size_max(ep)             (((ep) == 0) ? 64 : 1024)
00081   //! Get DMA support of endpoints
00082 #define Is_uhd_pipe_dma_supported(ep)         ((((ep) >= 1) && ((ep) <= 6)) ? true : false)
00083   //! Get High Band Width support of endpoints
00084 #define Is_uhd_pipe_high_bw_supported(ep)     (((ep) >= 2) ? true : false)
00085 //! @}
00086 
00087 typedef enum
00088 {
00089   HOST_MODE= 0,
00090   DEVICE_MODE=1
00091 }USB_Mode_t;
00092 
00093 //! Maximum transfer size on USB DMA
00094 #define UHD_PIPE_MAX_TRANS 0x8000
00095 
00096 /**
00097 =================================  
00098         USBHS_CTRL 
00099 =================================
00100 **/
00101 
00102 /**
00103  * \brief Freeze or unfreeze USB clock
00104  * \param pUsbhs   Pointer to an USBHS instance.
00105  * \param Enable Enable or disable
00106  */
00107 __STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs)
00108 {
00109     pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
00110 }
00111 
00112 /**
00113  * \brief Freeze or unfreeze USB clock
00114  * \param pUsbhs   Pointer to an USBHS instance.
00115  * \param Enable Enable or disable
00116  */
00117 __STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs)
00118 {
00119   pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK);
00120 }
00121 /**
00122  * \brief Freeze or unfreeze USB clock
00123  * \param pUsbhs   Pointer to an USBHS instance.
00124  * \param Enable Enable or disable
00125  */
00126 __STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable)
00127 {
00128       
00129     if(!Enable) {
00130         pUsbhs->USBHS_CTRL |= (1<<8);
00131     } else {
00132         pUsbhs->USBHS_CTRL &= ~((uint32_t)(1<<8));
00133     }
00134 }
00135 
00136 /**
00137  * \brief Enables or disables USB 
00138  * \param pUsbhs   Pointer to an USBHS instance.
00139  * \param Enable Enable or disable
00140  */
00141 
00142 __STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable)
00143 {
00144     if(Enable) {
00145         pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE;
00146     } else {
00147         pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE);
00148     }
00149 }
00150 
00151 
00152 /**
00153  * \brief Device or Host Mode
00154  * \param pUsbhs   Pointer to an USBHS instance.
00155  * \param Mode   Device or Host Mode
00156  */
00157 
00158 __STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode)
00159 {
00160     if(Mode) {
00161         pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE;
00162     } else {
00163         pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE);
00164     }
00165 }
00166 
00167 /********************* USBHS_SR  *****************/
00168 
00169 /**
00170  * \brief Check if clock is usable or not
00171  * \param pUsbhs   Pointer to an USBHS instance.
00172  * \return 1 if USB clock is usable
00173  */
00174 
00175 __STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs)
00176 { 
00177     return (( pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14);
00178 }
00179 
00180 
00181 /**
00182  * \brief Raise interrupt for endpoint.
00183  * \param pUsbhs   Pointer to an USBHS instance.
00184  * \return USB status
00185  */
00186 
00187 __STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs)
00188 {   
00189     return (pUsbhs->USBHS_SR);   
00190 }
00191 
00192 /**
00193  * \brief Enable or disable USB address
00194  * \param pUsbhs   Pointer to an USBHS instance.
00195  * \return USB speed status
00196  */
00197 
00198 __STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs)
00199 {
00200     return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) );
00201 }
00202 
00203 
00204 /**
00205  * \brief Enable or disable USB address
00206  * \param pUsbhs   Pointer to an USBHS instance.
00207  * \return USB speed status
00208  */
00209 
00210 __STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs)
00211 {
00212   return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ? true:false;
00213 }
00214 
00215 
00216 /**
00217  * \brief Enable or disable USB address
00218  * \param pUsbhs   Pointer to an USBHS instance.
00219  * \return USB speed status
00220  */
00221 
00222 __STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs)
00223 {
00224     return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ? true:false;
00225 }
00226 
00227 /**
00228  * \brief Enable or disable USB address
00229  * \param pUsbhs   Pointer to an USBHS instance.
00230  * \return USB speed status
00231  */
00232 
00233 __STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs)
00234 {
00235     return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ? true:false;
00236 }
00237 /********************* USBHS_SCR  *****************/
00238 
00239 /**
00240  * \brief Raise interrupt for endpoint.
00241  * \param pUsbhs   Pointer to an USBHS instance.
00242  * \param AckType Interrupt Acknowledge type
00243  */
00244 
00245 __STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType)
00246 {
00247     pUsbhs->USBHS_SCR |= AckType;
00248 }
00249 
00250 /********************* USBHS_SFR  *****************/
00251 
00252 /**
00253  * \brief Raise interrupt for endpoint.
00254  * \param pUsbhs   Pointer to an USBHS instance.
00255  * \param SetStatus Set USB status
00256  */
00257 
00258 __STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus)
00259 {
00260     pUsbhs->USBHS_SFR |= SetStatus;
00261 }
00262 
00263 
00264  /*--------------------------------------------------------
00265  * =========== USB Device functions ======================
00266  *---------------------------------------------------------*/
00267 
00268 /**
00269  * \brief Enable or disable USB address
00270  * \param pUsbhs   Pointer to an USBHS instance.
00271  * \param SetStatus Set USB status
00272  */
00273 
00274 __STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable)
00275 {
00276     if(Enable) {
00277         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
00278     } else {
00279         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN);
00280     }
00281 }
00282 
00283 /**
00284  * \brief Configure USB address and enable or disable it
00285  * \param pUsbhs   Pointer to an USBHS instance.
00286  * \param Addr   USB device status
00287  */
00288 
00289 __STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr)
00290 {
00291     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr);
00292     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
00293 }
00294 
00295 /**
00296  * \brief Get USB address
00297  * \param pUsbhs   Pointer to an USBHS instance.
00298  */
00299 
00300 __STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs)
00301 {
00302     return ( pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk);
00303 }
00304 
00305 /**
00306  * \brief Attach or detach USB.
00307  * \param pUsbhs   Pointer to an USBHS instance.
00308  * \param Enable Attachs or detach USB device
00309  */
00310 
00311 __STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable)
00312 {
00313     if(Enable) {
00314         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
00315     } else {
00316         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH);
00317     }
00318   
00319 }
00320 
00321 /**
00322  * \brief Force Low Speed mode
00323  * \param pUsbhs   Pointer to an USBHS instance.
00324  * \param Enable Enables the Full speed
00325  */
00326 
00327 __STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable)
00328 {
00329     if(Enable) {
00330         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS;
00331     } else {
00332         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS);
00333     }
00334 }
00335 
00336 /**
00337  * \brief Disable/Enables High Speed mode
00338  * \param pUsbhs   Pointer to an USBHS instance.
00339  * \param Enable Enables/disable option
00340  */
00341 
00342 __STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable)
00343 {
00344     uint32_t cfg = pUsbhs->USBHS_DEVCTRL;
00345     cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk);
00346     if(Enable) {
00347         pUsbhs->USBHS_DEVCTRL |= cfg;
00348     } else {
00349         pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS);
00350     }
00351   
00352 }
00353 
00354 /**
00355  * \brief Set Remote WakeUp mode
00356  * \param pUsbhs   Pointer to an USBHS instance.
00357  */
00358 
00359 __STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs)
00360 {
00361     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
00362 }
00363 
00364 /**
00365  * \brief Disable/Enables Test mode
00366  * \param pUsbhs   Pointer to an USBHS instance.
00367  * \param mode Enables/disable option
00368  */
00369 
00370 __STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode)
00371 {
00372     pUsbhs->USBHS_DEVCTRL |= mode;
00373 }
00374 
00375 
00376 /**
00377  * \brief Disable/Enables HS Test mode
00378  * \param pUsbhs   Pointer to an USBHS instance.
00379  */
00380 
00381 __STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs)
00382 {
00383     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED;
00384 }
00385 
00386 /**
00387  * \brief Read status for an interrupt
00388  * \param pUsbhs   Pointer to an USBHS instance.
00389  * \param IntType Interrupt type
00390  */
00391 
00392 __STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType)
00393 {   
00394     return (pUsbhs->USBHS_DEVISR & IntType);    
00395 }
00396 
00397 /**
00398  * \brief Read status for an Endpoint
00399  * \param pUsbhs   Pointer to an USBHS instance.
00400  * \param EpNum  Endpoint
00401  */
00402 
00403 __STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum)
00404 {   
00405     return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_PEP_0 << EpNum) );    
00406 }
00407 
00408 /**
00409  * \brief Read status for a DMA Endpoint
00410  * \param pUsbhs   Pointer to an USBHS instance.
00411  * \param DmaNum  DMA Endpoint
00412  */
00413 __STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum)
00414 {   
00415     return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_DMA_1 << DmaNum) );
00416 }
00417 
00418 /**
00419  * \brief Acknowledge interrupt for endpoint.
00420  * \param pUsbhs   Pointer to an USBHS instance.
00421  * \param IntType Interrupt Type
00422  */
00423 
00424 __STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType)
00425 {   
00426     pUsbhs->USBHS_DEVICR |=  IntType;
00427 }
00428 
00429 /**
00430  * \brief Raise interrupt for endpoint.
00431  * \param pUsbhs   Pointer to an USBHS instance.
00432  * \param IntType Interrupt Type
00433  */
00434 
00435 
00436 __STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType)
00437 {   
00438     pUsbhs->USBHS_DEVIFR |=  IntType;
00439 }
00440 
00441 /**
00442  * \brief Raise DMA interrupt for endpoint.
00443  * \param pUsbhs   Pointer to an USBHS instance.
00444  * \param IntType Interrupt Type
00445  */
00446 __STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma)
00447 {   
00448     assert(Dma< USBHSDEVDMA_NUMBER);
00449     pUsbhs->USBHS_DEVIFR |=  ( USBHS_DEVIFR_DMA_1 << Dma );
00450 }
00451 
00452 /**
00453  * \brief check for interrupt of endpoint.
00454  * \param pUsbhs   Pointer to an USBHS instance.
00455  * \param IntType Interrupt Type
00456  */
00457 
00458 __STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType)
00459 {
00460     return (pUsbhs->USBHS_DEVIMR &  IntType);
00461 }
00462 
00463 /**
00464  * \brief Check if endpoint's interrupt is enabled for a given endpoint number
00465  * \param pUsbhs   Pointer to an USBHS instance.
00466  * \param EpNum Endpoint number
00467  */
00468 
00469 __STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum)
00470 {
00471     return (pUsbhs->USBHS_DEVIMR &  (USBHS_DEVIMR_PEP_0 << EpNum ));
00472 }
00473 
00474 
00475 /**
00476  * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint 
00477  * DMA number
00478  * \param pUsbhs   Pointer to an USBHS instance.
00479  * \param DmaNum Endpoint's DMA number
00480  */
00481 
00482 __STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum)
00483 {
00484     return (pUsbhs->USBHS_DEVIMR &  (USBHS_DEVIMR_DMA_1 << DmaNum));
00485 }
00486 
00487 
00488 /**
00489  * \brief Enables Interrupt
00490  * \param pUsbhs   Pointer to an USBHS instance.
00491  * \param IntType Interrupt Type
00492  */
00493 __STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType)
00494 {   
00495     pUsbhs->USBHS_DEVIER |=  IntType;
00496 }
00497 
00498 /**
00499  * \brief Enables interrupt for a given endpoint.
00500  * \param pUsbhs   Pointer to an USBHS instance.
00501  * \param DmaNum Endpoint's DMA number
00502  */
00503 __STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum)
00504 {   
00505     pUsbhs->USBHS_DEVIER |=  (USBHS_DEVIER_PEP_0 << EpNum);
00506 }
00507 
00508 /**
00509  * \brief Enables DMA interrupt for a given endpoint.
00510  * \param pUsbhs   Pointer to an USBHS instance.
00511  * \param DmaEp  Endpoint's DMA interrupt number
00512  */
00513 
00514 __STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp)
00515 {   
00516     assert(DmaEp< USBHSDEVDMA_NUMBER);
00517     pUsbhs->USBHS_DEVIER |=  (USBHS_DEVIER_DMA_1 << DmaEp);
00518 }
00519   
00520  /**
00521  * \brief Disables interrupt for endpoint.
00522  * \param pUsbhs   Pointer to an USBHS instance.
00523  * \param IntType Int type
00524  */  
00525 
00526 __STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType)
00527 {   
00528     pUsbhs->USBHS_DEVIDR |=  IntType;
00529 }
00530 
00531  /**
00532  * \brief Disables interrupt for endpoint.
00533  * \param pUsbhs  Pointer to an USBHS instance.
00534  * \param Ep    Endpoint number
00535  */ 
00536 
00537 __STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep)
00538 {   
00539     pUsbhs->USBHS_DEVIDR |=  (USBHS_DEVIDR_PEP_0 << Ep);    
00540 }
00541 
00542  /**
00543  * \brief Disables DMA interrupt for endpoint.
00544  * \param pUsbhs  Pointer to an USBHS instance.
00545  * \param DmaEp Endpoint's DMA number
00546  */
00547 __STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp)
00548 {   
00549     assert(DmaEp< USBHSDEVDMA_NUMBER);
00550     pUsbhs->USBHS_DEVIDR |=  (USBHS_DEVIDR_DMA_1 << DmaEp);
00551 }
00552 
00553 
00554  /**
00555  * \brief Enables or disables endpoint.
00556  * \param pUsbhs  Pointer to an USBHS instance.
00557  * \param Enable Enable/disable endpoint
00558  */
00559 
00560 __STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
00561 {
00562     if(Enable) {
00563         pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep);
00564     } else {
00565         pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep);
00566     }
00567     
00568 }
00569 
00570 
00571  /**
00572  * \brief Rests Endpoint
00573  * \param pUsbhs  Pointer to an USBHS instance.
00574  * \param Ep    Endpoint Number
00575  */
00576 
00577 __STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep)
00578 {
00579     pUsbhs->USBHS_DEVEPT |=  (USBHS_DEVEPT_EPRST0 << Ep);
00580    //pUsbhs->USBHS_DEVEPT &=  ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep);
00581 }
00582 
00583  /**
00584  * \brief Checks if Endpoint is enable
00585  * \param pUsbhs  Pointer to an USBHS instance.
00586  * \param Ep    Endpoint Number
00587  */
00588 
00589 __STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep)
00590 {
00591     return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep) );
00592 }
00593 
00594  /**
00595  * \brief Get MicrFrame number
00596  * \param pUsbhs  Pointer to an USBHS instance.
00597  * \retruns Micro frame number
00598  */
00599 __STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs)
00600 {
00601     return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk);    
00602 }
00603 
00604 
00605  /**
00606  * \brief Get Frame number
00607  * \param pUsbhs  Pointer to an USBHS instance.
00608  * \retruns frame number
00609  */
00610 __STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs)
00611 {
00612     return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk) 
00613             >> USBHS_DEVFNUM_FNUM_Pos); 
00614 }
00615 
00616  /**
00617  * \brief Get Frame number CRC error
00618  * \param pUsbhs  Pointer to an USBHS instance.
00619  * \retruns Frame number error status
00620  */
00621 __STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs)
00622 {
00623     return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15);
00624 }
00625 
00626  /*-----------------------------------------
00627  * =========== USB Device's Endpoint functions ========
00628  *------------------------------------------*/
00629 
00630 /**
00631  * Set Endpoints configuration
00632  * Bank size, type and direction
00633  */
00634 __STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep,
00635         const uint8_t Type, const uint8_t Dir, 
00636         const uint8_t Size, const uint8_t Bank)
00637 {  
00638     
00639     pUsbhs->USBHS_DEVEPTCFG[Ep] |= 
00640         ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk);
00641     pUsbhs->USBHS_DEVEPTCFG[Ep] |= 
00642         ((Dir << 8 ) & USBHS_DEVEPTCFG_EPDIR);
00643     pUsbhs->USBHS_DEVEPTCFG[Ep] |= 
00644         (( (Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk);
00645     pUsbhs->USBHS_DEVEPTCFG[Ep] |= 
00646         (( (Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk);
00647 }
00648 
00649 
00650 /**
00651  * Enable or disable Auto switch of banks
00652  */
00653 __STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
00654 {
00655     if(Enable) {
00656         pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_AUTOSW;
00657     } else {
00658         pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW);
00659     }
00660 }
00661 
00662 
00663 /**
00664  * Allocate Endpoint memory
00665  */
00666 __STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep)
00667 {
00668     pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_ALLOC;
00669 }
00670 
00671 
00672 /**
00673  * Free allocated Endpoint memory
00674  */
00675 __STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep)
00676 {
00677     pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC);
00678 }
00679 
00680 
00681 /**
00682  * Get Endpoint configuration
00683  */
00684 __STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep,
00685                                                 uint32_t IntType)
00686 {  
00687     return ((pUsbhs->USBHS_DEVEPTCFG[Ep] ) & IntType);
00688 }
00689 
00690 /**
00691  * Get Endpoint Type
00692  */
00693 __STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep)
00694 {  
00695     return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk) 
00696             >> USBHS_DEVEPTCFG_EPTYPE_Pos);
00697 }
00698 
00699 /**
00700  * Get Endpoint Size
00701  */
00702 __STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep)
00703 {  
00704     return ( 8 << ( (pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk)
00705             >> USBHS_DEVEPTCFG_EPSIZE_Pos) );
00706 }
00707 
00708 
00709 /**
00710  * Sets ISO endpoint's Number of Transfer for High Speed
00711  */
00712 __STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep, 
00713         uint8_t nbTrans)
00714 {  
00715     pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans) ;
00716 }
00717 
00718 /**
00719  * Check for interrupt types enabled for a given endpoint
00720  */
00721 __STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep,
00722         uint32_t EpIntType)
00723 {  
00724     return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType);
00725 }
00726 
00727 
00728 /**
00729  * Enables an interrupt type for a given endpoint
00730  */
00731 __STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep, 
00732         uint32_t EpInt)
00733 {
00734     pUsbhs->USBHS_DEVEPTIER[Ep] |=  EpInt;
00735 }
00736 
00737 /**
00738  * Enables an interrupt type for a given endpoint
00739  */
00740 __STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep)
00741 {   
00742     return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK);
00743 }
00744 
00745 /**
00746  * Enables an interrupt type for a given endpoint
00747  */
00748 __STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep)
00749 {
00750     pUsbhs->USBHS_DEVEPTIER[Ep] =  USBHS_DEVEPTIER_KILLBKS;
00751 }
00752 /**
00753  * Disables an interrupt type for a given endpoint
00754  */
00755 __STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep, 
00756         uint32_t EpInt)
00757 {
00758     pUsbhs->USBHS_DEVEPTIDR[Ep] |=  EpInt;
00759 }
00760 
00761 /**
00762  * Clears register/acknowledge for a given endpoint
00763  */
00764 __STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
00765 {
00766     pUsbhs->USBHS_DEVEPTICR[Ep] |=  EpInt;
00767 }
00768 
00769 /**
00770  * Sets/Raise register for a given endpoint
00771  */
00772 __STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
00773 {   
00774     pUsbhs->USBHS_DEVEPTIFR[Ep] |=  EpInt;    
00775 }
00776 
00777 /**
00778  * Gets interrupt status for a given EP
00779  */
00780 __STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep, 
00781         uint32_t EpInt)
00782 {
00783     return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt);
00784 }
00785 
00786 /**
00787  * Check if given endpoint's bank is free
00788  */
00789 __STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep)
00790 {
00791     if( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)) {
00792         return false;
00793     } else {
00794         return true;
00795     }
00796 }
00797 
00798 /**
00799  * Read endpoint's bank number in use
00800  */
00801 __STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep)
00802 {
00803     return ( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk) 
00804         >> USBHS_DEVEPTISR_NBUSYBK_Pos);
00805 }
00806 
00807 
00808 /**
00809  * Read endpoint's bank number in use
00810  */
00811 __STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep)
00812 {
00813     return (uint16_t)( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk)
00814         >> USBHS_DEVEPTISR_BYCT_Pos);
00815 }
00816 
00817  /*--------------------------------------------------------
00818  * =========== USB Device's Ep's DMA functions =========
00819  *---------------------------------------------------------*/
00820 
00821  /**
00822  * \brief Sets DMA next descriptor address
00823  * \param pUsbDma  USBHS device DMA instance
00824  * \param Desc NDA address
00825  */ 
00826 __STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc)
00827 {
00828     pUsbDma->USBHS_DEVDMANXTDSC = Desc;
00829 }
00830 
00831  /**
00832  * \brief Gets DMA next descriptor address
00833  * \param pUsbDma  USBHS device DMA instance
00834  * \return Next DMA descriptor
00835  */ 
00836 __STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma)
00837 {
00838     return (pUsbDma->USBHS_DEVDMANXTDSC);
00839 }
00840 
00841  /**
00842  * \brief Sets USBHS's DMA Buffer addresse
00843  * \param pUsbDma  USBHS device DMA instance
00844  * \param Addr  DMA's buffer Addrs
00845  */ 
00846 __STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr)
00847 {
00848     pUsbDma->USBHS_DEVDMAADDRESS = Addr;
00849 }
00850 
00851 
00852  /**
00853  * \brief Gets USBHS's DMA Buffer addresse
00854  * \param pUsbDma  USBHS device DMA instance
00855  * \return DMA addrs
00856  */ 
00857 __STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma)
00858 {
00859     return (pUsbDma->USBHS_DEVDMAADDRESS);
00860 }
00861 
00862  /**
00863  * \brief Setup the USBHS DMA
00864  * \param pUsbDma  USBHS device DMA instance
00865  * \param Cfg  DMA's configuration
00866  */ 
00867 __STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg)
00868 {
00869     pUsbDma->USBHS_DEVDMACONTROL |= Cfg;
00870 }
00871 
00872  /**
00873  * \brief Get DMA configuration
00874  * \param pUsbDma  USBHS device DMA instance
00875  * \return DMA control setup
00876  */ 
00877 __STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma)
00878 {
00879     return (pUsbDma->USBHS_DEVDMACONTROL);
00880 }
00881 
00882 
00883  /**
00884  * \brief Set DMA status
00885  * \param pUsbDma  USBHS device DMA instance
00886  * \Status Set DMA status
00887  */ 
00888 __STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status)
00889 {
00890     pUsbDma->USBHS_DEVDMASTATUS = Status;
00891 }
00892 
00893 
00894  /**
00895  * \brief Get Dma Status
00896  * \param pUsbDma  USBHS device DMA instance
00897  * \return Dma status
00898  */ 
00899 __STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma)
00900 {
00901     return (pUsbDma->USBHS_DEVDMASTATUS);
00902 }
00903 
00904 
00905  /**
00906  * \brief Get DMA buffer's count
00907  * \param pUsbDma  USBHS device DMA instance
00908  * \return Buffer count
00909  */ 
00910 __STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma)
00911 {
00912     return ( (pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk)
00913         >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
00914 }
00915 
00916 
00917  /*--------------------------------------------------------
00918  * =========== USB Host Functions  ========================
00919  *---------------------------------------------------------*/
00920 
00921 /** Number of USB endpoints */
00922 #define CHIP_USB_NUMPIPE            10
00923 /** Number of USB endpoints */
00924 #define CHIP_USB_DMA_NUMPIPE        7
00925 
00926 /** Endpoints max paxcket size */
00927 #define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \
00928    ((ep == 0) ? 64 : 1024)
00929 
00930 /** Endpoints Number of Bank */
00931 #define CHIP_USB_PIPE_BANKS(ep)                 ((ep==0)?1:((ep<=2)?3:2))
00932      
00933      
00934 #define CHIP_USB_PIPE_HBW(ep)                   ((((ep)>=1) &&((ep)<=2))?true:false)
00935 
00936 /** Endpoints DMA support */
00937 #define CHIP_USB_PIPE_DMA(ep)                   ((((ep)>=1)&&((ep)<=7))?true:false)
00938 
00939  /**
00940  * \brief Sets USB host's speed to Normal , it sets to HS from FS
00941  * \param pUsbhs  USBHS host instance
00942  */ 
00943 __STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs)
00944 {
00945     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00946     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL;
00947 }
00948 
00949  /**
00950  * \brief Sets USB host's speed to Low speed
00951  * \param pUsbhs  USBHS host instance
00952  */ 
00953 __STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs)
00954 {
00955     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00956     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER;
00957 }
00958 
00959  /**
00960  * \brief Sets USB host's speed to forced Full speed
00961  * \param pUsbhs  USBHS host instance
00962  */ 
00963 __STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs)
00964 {
00965     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00966     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS;
00967 }
00968 
00969  /**
00970  * \brief Sets USB host sends reste signal on USB Bus
00971  * \param pUsbhs  USBHS host instance
00972  */ 
00973 __STATIC_INLINE void USBHS_Reset(void)
00974 {
00975    USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET;
00976 }
00977 
00978  /**
00979  * \brief Sets USB host sends reste signal on USB Bus
00980  * \param pUsbhs  USBHS host instance
00981  */ 
00982 __STATIC_INLINE void USBHS_StopReset(void)
00983 {
00984    USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET;
00985 }
00986 
00987  /**
00988  * \brief Sets USB host send Resume on USB bus
00989  * \param pUsbhs  USBHS host instance
00990  */ 
00991 __STATIC_INLINE void USBHS_Resume(void)
00992 {
00993    USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME;
00994 }
00995 
00996  /**
00997  * \brief Sets USB host Enable the Generation of  Start of Frame
00998  * \param pUsbhs  USBHS host instance
00999  */ 
01000 __STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs)
01001 {
01002    pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE;
01003 }
01004 
01005  /**
01006  * \brief Sets USB host Enable the Generation of  Start of Frame
01007  * \param pUsbhs  USBHS host instance
01008  */ 
01009 __STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs)
01010 {
01011     return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8;
01012 }
01013  /**
01014  * \brief Sets USB host disable the Generation of  Start of Frame
01015  * \param pUsbhs  USBHS host instance
01016  */ 
01017 __STATIC_INLINE void USBHS_DisableSOF(void)
01018 {
01019    USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE;
01020 }
01021 
01022  /**
01023  * \brief Gets USB host interrupt status
01024  * \param pUsbhs  USBHS host instance
01025  */ 
01026 __STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType)
01027 {
01028    return (pUsbhs->USBHS_HSTISR & IntType);
01029 }
01030 
01031 
01032 /**
01033  * \brief Gets USB host interrupt status
01034  * \param pUsbhs  USBHS host instance
01035  */ 
01036 __STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01037 {
01038    assert( PipeInt < CHIP_USB_NUMPIPE);
01039    return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_PEP_0 << PipeInt) );
01040 }
01041 
01042 
01043 /**
01044  * \brief Gets USB host interrupt status
01045  * \param pUsbhs  USBHS host instance
01046  */ 
01047 __STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01048 {
01049     assert( PipeInt);
01050     assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01051     return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_DMA_1 << PipeInt) );
01052 }
01053 
01054 /**
01055  * \brief Gets USB host interrupt status
01056  * \param pUsbhs  USBHS host instance
01057  */ 
01058 __STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType)
01059 {
01060     pUsbhs->USBHS_HSTICR = IntType;
01061 }
01062 
01063 /**
01064  * \brief Gets USB host interrupt status
01065  * \param pUsbhs  USBHS host instance
01066  */ 
01067 __STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType)
01068 {
01069     pUsbhs->USBHS_HSTIFR = IntType;
01070 }
01071 
01072 /**
01073  * \brief Gets USB host interrupt status
01074  * \param pUsbhs  USBHS host instance
01075  */ 
01076 __STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01077 {
01078     assert( PipeInt);
01079     assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01080     pUsbhs->USBHS_HSTIFR =  (USBHS_HSTIFR_DMA_1 << PipeInt) ;
01081 }
01082 
01083 /*** Interrupt Mask ****/
01084 /**
01085  * \brief Gets USB host interrupt status
01086  * \param pUsbhs  USBHS host instance
01087  */ 
01088 __STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType)
01089 {
01090     return (pUsbhs->USBHS_HSTIMR & IntType) ;
01091 }
01092 
01093 /**
01094  * \brief Gets USB host interrupt status
01095  * \param pUsbhs  USBHS host instance
01096  */ 
01097 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01098 {
01099     assert( PipeInt < CHIP_USB_NUMPIPE);
01100     return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt) );
01101 }
01102 
01103 /**
01104  * \brief Gets USB host interrupt status
01105  * \param pUsbhs  USBHS host instance
01106  */ 
01107 __STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01108 {
01109     assert( PipeInt);
01110     assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01111     return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt) );
01112 }
01113 
01114 /*** Interrupt Disable ****/
01115 /**
01116  * \brief Gets USB host interrupt status
01117  * \param pUsbhs  USBHS host instance
01118  */ 
01119 __STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType)
01120 {
01121     pUsbhs->USBHS_HSTIDR = IntType ;
01122 }
01123 
01124 /**
01125  * \brief Gets USB host interrupt status
01126  * \param pUsbhs  USBHS host instance
01127  */ 
01128 __STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
01129 {
01130     assert( PipeInt < CHIP_USB_NUMPIPE);
01131     pUsbhs->USBHS_HSTIDR  = (USBHS_HSTIDR_PEP_0 << PipeInt);
01132 }
01133 
01134 /**
01135  * \brief Gets USB host interrupt status
01136  * \param pUsbhs  USBHS host instance
01137  */ 
01138 __STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
01139 {
01140     assert( PipeInt);
01141     assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01142     pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt) ;
01143 }
01144 
01145 /*** Interrupt Enable ****/
01146 
01147 /**
01148  * \brief Gets USB host interrupt status
01149  * \param pUsbhs  USBHS host instance
01150  */ 
01151 __STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType)
01152 {
01153     pUsbhs->USBHS_HSTIER = IntType ;
01154 }
01155 
01156 /**
01157  * \brief Gets USB host interrupt status
01158  * \param pUsbhs  USBHS host instance
01159  */ 
01160 __STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01161 {
01162      assert( PipeInt < CHIP_USB_NUMPIPE);
01163      pUsbhs->USBHS_HSTIER =(USBHS_HSTIER_PEP_0 << PipeInt) ;
01164 }
01165 
01166 /**
01167  * \brief Gets USB host interrupt status
01168  * \param pUsbhs  USBHS host instance
01169  */ 
01170 __STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01171 {
01172     assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01173     pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt);
01174 }
01175 
01176 /**
01177  * \brief Gets USB host interrupt status
01178  * \param pUsbhs  USBHS host instance
01179  */ 
01180 __STATIC_INLINE uint16_t USBHS_HostGetSOF(void)
01181 {
01182    return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >> USBHS_HSTFNUM_FNUM_Pos);
01183 }
01184 
01185 /**
01186  * \brief Gets USB host interrupt status
01187  * \param pUsbhs  USBHS host instance
01188  */ 
01189 __STATIC_INLINE uint16_t USBHS_HostGetFramePos(void)
01190 {
01191    return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >> USBHS_HSTFNUM_FLENHIGH_Pos);
01192 }
01193 
01194 
01195 /**
01196  * \brief Gets USB host interrupt status
01197  * \param pUsbhs  USBHS host instance
01198  */ 
01199 __STATIC_INLINE uint16_t USBHS_HostGetMSOF(void)
01200 {
01201    return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >> USBHS_HSTFNUM_MFNUM_Pos);
01202 }
01203 
01204 __STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Addr)
01205 {
01206   assert( Pipe < CHIP_USB_NUMPIPE);
01207   if (Pipe <4)
01208   {
01209     pUsbhs->USBHS_HSTADDR1 |= (Addr << (8*Pipe));
01210   }
01211   else if( (Pipe <8) && (Pipe >=4))
01212   {
01213     pUsbhs->USBHS_HSTADDR2 |= (Addr << (8* (Pipe -4)));
01214   }
01215   else
01216   {
01217     pUsbhs->USBHS_HSTADDR3 |= (Addr << (8*(Pipe -8)));
01218   }
01219   
01220 }
01221 
01222 __STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe)
01223 {
01224   assert( Pipe < CHIP_USB_NUMPIPE);
01225   if (Pipe <4)
01226   {
01227     return ( pUsbhs->USBHS_HSTADDR1 >>  (8*Pipe)) ;
01228   }
01229   else if( (Pipe <8) && (Pipe >=4))
01230   {
01231     return (pUsbhs->USBHS_HSTADDR2  >>  (8*(Pipe -4)));
01232   }
01233   else
01234   {
01235     return (pUsbhs->USBHS_HSTADDR3  >> (8*(Pipe -8)));
01236   }
01237   
01238 }
01239 
01240 /**
01241  * \brief Gets USB host interrupt status
01242  * \param pUsbhs  USBHS host instance
01243  */ 
01244 __STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
01245 {
01246     assert( Pipe < CHIP_USB_NUMPIPE);
01247     pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe);
01248 }
01249 
01250 /**
01251  * \brief Gets USB host interrupt status
01252  * \param pUsbhs  USBHS host instance
01253  */ 
01254 __STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe)
01255 {
01256     assert( Pipe < CHIP_USB_NUMPIPE);
01257     pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe);
01258 }
01259 
01260 /**
01261  * \brief Gets USB host interrupt status
01262  * \param pUsbhs  USBHS host instance
01263  */ 
01264 __STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
01265 {
01266     assert( Pipe < CHIP_USB_NUMPIPE);
01267     return (pUsbhs->USBHS_HSTPIP &(USBHS_HSTPIP_PEN0 << Pipe));
01268 }
01269 /**
01270  * \brief Gets USB host interrupt status
01271  * \param pUsbhs  USBHS host instance
01272  */ 
01273 __STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe)
01274 {
01275     assert( Pipe < CHIP_USB_NUMPIPE);
01276     pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe);
01277     pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe);
01278 }
01279 
01280 /**
01281  * \brief Gets USB host interrupt status
01282  * \param pUsbhs  USBHS host instance
01283  */ 
01284 __STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, uint8_t pipeEpNum, uint8_t PipeIntFreq)
01285 {
01286     assert( Pipe < CHIP_USB_NUMPIPE);
01287     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= ( pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) |  USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq));
01288 }
01289 
01290 /**
01291  * \brief Gets USB host interrupt status
01292  * \param pUsbhs  USBHS host instance
01293  */ 
01294 __STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe)
01295 {
01296   pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC;
01297   
01298 }
01299 
01300 /**
01301  * \brief Gets USB host interrupt status
01302  * \param pUsbhs  USBHS host instance
01303  */ 
01304 __STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe)
01305 {
01306   pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC;
01307   
01308 }
01309 
01310 
01311 /**
01312  * \brief Gets USB host interrupt status
01313  * \param pUsbhs  USBHS host instance
01314  */ 
01315 __STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe)
01316 {
01317     return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >> USBHS_HSTPIPCFG_PSIZE_Pos)) ;
01318   
01319 }
01320 
01321      /**
01322  * \brief Gets USB host interrupt status
01323  * \param pUsbhs  USBHS host instance
01324  */ 
01325 __STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, uint32_t Token)
01326 {
01327     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk;
01328     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token;
01329   
01330 }
01331 
01332 
01333 /**
01334  * \brief Gets USB host interrupt status
01335  * \param pUsbhs  USBHS host instance
01336  */ 
01337 __STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe)
01338 {
01339     return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk) ;
01340   
01341 }
01342 
01343 
01344 /**
01345  * \brief Gets USB host interrupt status
01346  * \param pUsbhs  USBHS host instance
01347  */ 
01348 __STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, uint8_t PipeType)
01349 {
01350     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk ;
01351     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType ;
01352   
01353 }
01354 
01355 /**
01356  * \brief Gets USB host interrupt status
01357  * \param pUsbhs  USBHS host instance
01358  */ 
01359 __STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe )
01360 {
01361     return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk) ;
01362   
01363 }
01364 
01365 __STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe)
01366 {
01367   
01368    if( USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN)
01369    {
01370      return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80);
01371    }
01372    else
01373    {
01374      return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00) ;
01375    }  
01376 }
01377 
01378 
01379 
01380 /**
01381  * \brief Gets USB host interrupt status
01382  * \param pUsbhs  USBHS host instance
01383  */ 
01384 __STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
01385 {
01386   pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW;  
01387 }
01388 
01389 /**
01390  * \brief Gets USB host interrupt status
01391  * \param pUsbhs  USBHS host instance
01392  */ 
01393 __STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
01394 {
01395   pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW;  
01396 }
01397 
01398 /**
01399  * \brief Gets USB host interrupt status
01400  * \param pUsbhs  USBHS host instance
01401  */ 
01402 __STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Freq)
01403 {
01404   pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq);  
01405 }
01406 
01407 
01408 /**
01409  * \brief Gets USB host interrupt status
01410  * \param pUsbhs  USBHS host instance
01411  */ 
01412 __STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe)
01413 {
01414   pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN;  
01415 }
01416 
01417 
01418 /**
01419  * \brief Gets USB host interrupt status
01420  * \param pUsbhs  USBHS host instance
01421  */ 
01422 __STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe)
01423 {
01424     return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >> USBHS_HSTPIPISR_DTSEQ_Pos ) ;  
01425 }
01426 
01427 
01428 /**
01429  * \brief Gets USB host interrupt status
01430  * \param pUsbhs  USBHS host instance
01431  */ 
01432 __STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe)
01433 {
01434     return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >> USBHS_HSTPIPISR_NBUSYBK_Pos ) ;  
01435 }
01436 
01437 
01438 /**
01439  * \brief Gets USB host interrupt status
01440  * \param pUsbhs  USBHS host instance
01441  */ 
01442 __STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe)
01443 {
01444     return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >> USBHS_HSTPIPISR_CURRBK_Pos ) ;  
01445 }
01446 
01447 
01448 /**
01449  * \brief Gets USB host interrupt status
01450  * \param pUsbhs  USBHS host instance
01451  */ 
01452 __STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe)
01453 {
01454     return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >> USBHS_HSTPIPISR_PBYCT_Pos ) ;  
01455 }
01456 
01457 /**
01458  * \brief Gets USB host interrupt status
01459  * \param pUsbhs  USBHS host instance
01460  */ 
01461 __STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe)
01462 {
01463     return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK);  
01464 }
01465 
01466 /**
01467  * \brief Gets USB host interrupt status
01468  * \param pUsbhs  USBHS host instance
01469  */ 
01470 __STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01471 {
01472     return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType);  
01473 }
01474 
01475 /**
01476  * \brief Gets USB host interrupt status
01477  * \param pUsbhs  USBHS host instance
01478  */ 
01479 __STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01480 {
01481     pUsbhs->USBHS_HSTPIPICR[Pipe] = intType;  
01482 }
01483 
01484 /**
01485  * \brief Gets USB host interrupt status
01486  * \param pUsbhs  USBHS host instance
01487  */ 
01488 __STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01489 {
01490     pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType;  
01491 }
01492 
01493 /**
01494  * \brief Gets USB host interrupt status
01495  * \param pUsbhs  USBHS host instance
01496  */ 
01497 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01498 {
01499     return ( pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType);  
01500 }
01501 
01502 /**
01503  * \brief Gets USB host interrupt status
01504  * \param pUsbhs  USBHS host instance
01505  */ 
01506 __STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01507 {
01508     pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType;  
01509 }
01510 
01511 /**
01512  * \brief Gets USB host interrupt status
01513  * \param pUsbhs  USBHS host instance
01514  */ 
01515 __STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01516 {
01517     pUsbhs->USBHS_HSTPIPIER[Pipe] = intType;  
01518 }
01519 
01520 /**
01521  * \brief Gets USB host interrupt status
01522  * \param pUsbhs  USBHS host instance
01523  */ 
01524 __STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe)
01525 {
01526     pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE;  
01527 }
01528 
01529 /**
01530  * \brief Gets USB host interrupt status
01531  * \param pUsbhs  USBHS host instance
01532  */ 
01533 __STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe)
01534 {
01535     pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE;  
01536 }
01537 
01538 /**
01539  * \brief Gets USB host interrupt status
01540  * \param pUsbhs  USBHS host instance
01541  */ 
01542 __STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe)
01543 {
01544     return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8); 
01545 }
01546 
01547 /**
01548  * \brief Gets USB host interrupt status
01549  * \param pUsbhs  USBHS host instance
01550  */ 
01551 __STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq)
01552 {
01553     pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq-1);  
01554 }
01555 
01556 
01557 /**
01558  * \brief Gets USB host interrupt status
01559  * \param pUsbhs  USBHS host instance
01560  */ 
01561 __STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01562 {
01563     pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err;  
01564 }
01565 
01566 /**
01567  * \brief Gets USB host interrupt status
01568  * \param pUsbhs  USBHS host instance
01569  */ 
01570 __STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01571 {
01572     return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err);  
01573 }
01574 
01575 
01576 /**
01577  * \brief Gets USB host interrupt status
01578  * \param pUsbhs  USBHS host instance
01579  */ 
01580 __STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01581 {
01582     pUsbhs->USBHS_HSTPIPERR[Pipe] = Err;  
01583 }
01584 
01585 
01586 __STATIC_INLINE  uint8_t USBHS_GetInterruptPipeNum(void)
01587 {
01588     uint32_t status = USBHS->USBHS_HSTISR;
01589     uint32_t mask = USBHS->USBHS_HSTIMR;
01590     return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM));
01591 }
01592 
01593 static inline uint8_t USBHS_GetInterruptPipeDmaNum(void)
01594 {
01595     uint32_t status = USBHS->USBHS_HSTISR;
01596     uint32_t mask = USBHS->USBHS_HSTIMR;
01597     return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM-1))) + 1);
01598 }
01599  /*--------------------------------------------------------
01600  * =========== USB Host's pipe DMA functions =========
01601  *---------------------------------------------------------*/
01602 
01603  /**
01604  * \brief Sets DMA next descriptor address
01605  * \param pUsbDma  USBHS device DMA instance
01606  * \param Desc NDA addrs
01607  */ 
01608 __STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc)
01609 {
01610   pUsbDma->USBHS_HSTDMANXTDSC = Desc;
01611 }
01612 
01613  /**
01614  * \brief Gets DMA next descriptor address
01615  * \param pUsbDma  USBHS device DMA instance
01616  * \return Next DMA descriptor
01617  */ 
01618 __STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma)
01619 {
01620    return (pUsbDma->USBHS_HSTDMANXTDSC);
01621 }
01622 
01623  /**
01624  * \brief Sets USBHS's DMA Buffer addresse
01625  * \param pUsbDma  USBHS device DMA instance
01626  * \param Addr  DMA's buffer Addrs
01627  */ 
01628 __STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, uint32_t Addr)
01629 {
01630   pUsbDma->USBHS_HSTDMAADDRESS = Addr;
01631 }
01632 
01633 
01634  /**
01635  * \brief Gets USBHS's DMA Buffer addresse
01636  * \param pUsbDma  USBHS device DMA instance
01637  * \return DMA addrs
01638  */ 
01639 __STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma)
01640 {
01641    return (pUsbDma->USBHS_HSTDMAADDRESS);
01642 }
01643 
01644  /**
01645  * \brief Setup the USBHS DMA
01646  * \param pUsbDma  USBHS device DMA instance
01647  * \param Cfg  DMA's configuration
01648  */ 
01649 __STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg)
01650 {
01651   pUsbDma->USBHS_HSTDMACONTROL |= Cfg;
01652 }
01653 
01654  /**
01655  * \brief Get DMA configuration
01656  * \param pUsbDma  USBHS device DMA instance
01657  * \return DMA control setup
01658  */ 
01659 __STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma)
01660 {
01661    return (pUsbDma->USBHS_HSTDMACONTROL);
01662 }
01663 
01664 
01665  /**
01666  * \brief Set DMA status
01667  * \param pUsbDma  USBHS device DMA instance
01668  * \Status Set DMA status
01669  */ 
01670 __STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, uint32_t Status)
01671 {
01672   pUsbDma->USBHS_HSTDMASTATUS = Status;
01673 }
01674 
01675 
01676  /**
01677  * \brief Get Dma Status
01678  * \param pUsbDma  USBHS device DMA instance
01679  * \return Dma status
01680  */ 
01681 __STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma)
01682 {
01683    return (pUsbDma->USBHS_HSTDMASTATUS);
01684 }
01685 
01686 /**@}*/
01687 #endif /* #ifndef USBHS_H */
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