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00082 #ifndef _GMAC_H
00083 #define _GMAC_H
00084
00085
00086
00087
00088 #include "chip.h"
00089
00090 #include <stdint.h>
00091
00092 #ifdef __cplusplus
00093 extern "C" {
00094 #endif
00095
00096
00097
00098
00099
00100
00101
00102 #define NUM_GMAC_QUEUES 3
00103
00104
00105 #define GMAC_DUPLEX_HALF 0
00106 #define GMAC_DUPLEX_FULL 1
00107
00108
00109 #define GMAC_SPEED_10M 0
00110 #define GMAC_SPEED_100M 1
00111 #define GMAC_SPEED_1000M 2
00112
00113
00114
00115
00116
00117
00118
00119
00120 #define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC)
00121 #define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask
00122
00123
00124 #define GMAC_RX_OWNERSHIP_BIT (1u << 0)
00125 #define GMAC_RX_WRAP_BIT (1u << 1)
00126 #define GMAC_RX_SOF_BIT (1u << 14)
00127 #define GMAC_RX_EOF_BIT (1u << 15)
00128
00129
00130 #define GMAC_TX_LAST_BUFFER_BIT (1u << 15)
00131 #define GMAC_TX_WRAP_BIT (1u << 30)
00132 #define GMAC_TX_USED_BIT (1u << 31)
00133 #define GMAC_TX_RLE_BIT (1u << 29) /// Retry Limit Exceeded
00134 #define GMAC_TX_UND_BIT (1u << 28) /// Tx Buffer Under-run
00135 #define GMAC_TX_ERR_BIT (1u << 27) /// Exhausted in mid-frame
00136 #define GMAC_TX_ERR_BITS \
00137 (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
00138
00139
00140 #define GMAC_INT_RX_BITS \
00141 (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)
00142 #define GMAC_INT_TX_ERR_BITS \
00143 (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP)
00144 #define GMAC_INT_TX_BITS \
00145 (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)
00146
00147 #define GMAC_INT_RX_STATUS_BITS \
00148 (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR)
00149 #define GMAC_INT_TX_STATUS_ERR_BITS \
00150 (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP)
00151
00152
00153
00154
00155
00156
00157
00158 typedef enum {
00159 GMAC_QUE_0 = 0,
00160 GMAC_QUE_1 = 1,
00161 GMAC_QUE_2 = 2
00162 }gmacQueList_t;
00163
00164
00165 typedef struct _GmacRxDescriptor {
00166 union _GmacRxAddr {
00167 uint32_t val;
00168 struct _GmacRxAddrBM {
00169 uint32_t bOwnership:1,
00170
00171
00172 bWrap:1,
00173 addrDW:30;
00174 } bm;
00175 } addr;
00176 union _GmacRxStatus {
00177 uint32_t val;
00178 struct _GmacRxStatusBM {
00179 uint32_t len:12,
00180 offset:2,
00181
00182
00183 bSof:1,
00184 bEof:1,
00185 bCFI:1,
00186 vlanPriority:3,
00187 bPriorityDetected:1,
00188 bVlanDetected:1,
00189 bTypeIDMatch:1,
00190 bAddr4Match:1,
00191 bAddr3Match:1,
00192 bAddr2Match:1,
00193 bAddr1Match:1,
00194 reserved:1,
00195 bExtAddrMatch:1,
00196 bUniHashMatch:1,
00197 bMultiHashMatch:1,
00198 bBroadcastDetected:1;
00199
00200 } bm;
00201 } status;
00202 } sGmacRxDescriptor ;
00203
00204
00205 typedef struct _GmacTxDescriptor {
00206 uint32_t addr;
00207 union _GmacTxStatus {
00208 uint32_t val;
00209 struct _GmacTxStatusBM {
00210 uint32_t len:11,
00211 reserved:4,
00212 bLastBuffer:1,
00213 bNoCRC:1,
00214 reserved1:10,
00215 bExhausted:1,
00216 bUnderrun:1,
00217 bError:1,
00218 bWrap:1,
00219 bUsed:1;
00220
00221 } bm;
00222 } status;
00223 } sGmacTxDescriptor;
00224
00225
00226
00227
00228
00229
00230 extern uint8_t GMAC_IsIdle(Gmac *pGmac);
00231 extern void GMAC_PHYMaintain(Gmac *pGmac,
00232 uint8_t bPhyAddr,
00233 uint8_t bRegAddr,
00234 uint8_t bRW,
00235 uint16_t wData);
00236 extern uint16_t GMAC_PHYData(Gmac *pGmac);
00237 extern void GMAC_ClearStatistics(Gmac *pGmac);
00238 extern void GMAC_IncreaseStatistics(Gmac *pGmac);
00239 extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);
00240 extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck );
00241 extern void GMAC_EnableMdio(Gmac *pGmac );
00242 extern void GMAC_DisableMdio(Gmac *pGmac );
00243 extern void GMAC_EnableMII(Gmac *pGmac );
00244 extern void GMAC_EnableRMII(Gmac *pGmac );
00245 extern void GMAC_EnableGMII( Gmac *pGmac );
00246 extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);
00247 extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx);
00248 extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
00249 extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx);
00250 extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
00251 extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx);
00252 extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx);
00253 extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);
00254 extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);
00255 extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);
00256 extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);
00257 extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis);
00258 extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);
00259 extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);
00260 extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx);
00261 extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
00262 extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx);
00263 extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
00264 extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);
00265 extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);
00266 extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);
00267 extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB);
00268 extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);
00269 extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);
00270 extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx);
00271 extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx);
00272 extern uint32_t GMAC_GetConfigure(Gmac *pGmac);
00273 extern void GMAC_TransmissionStart(Gmac *pGmac);
00274 extern void GMAC_TransmissionHalt(Gmac *pGmac);
00275 extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);
00276
00277 void GMAC_ClearScreener1Reg (Gmac* pGmac, gmacQueList_t queueIdx);
00278
00279 void GMAC_WriteScreener1Reg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal);
00280
00281 void GMAC_ClearScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx);
00282
00283 void GMAC_WriteScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal);
00284
00285 void GMAC_WriteEthTypeReg (Gmac* pGmac, gmacQueList_t queueIdx, uint16_t etherType);
00286
00287 void GMAC_WriteCompareReg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, uint16_t c1Reg);
00288
00289 void GMAC_EnableCbsQueA(Gmac *pGmac);
00290
00291 void GMAC_DisableCbsQueA(Gmac *pGmac);
00292
00293 void GMAC_EnableCbsQueB(Gmac *pGmac);
00294
00295 void GMAC_DisableCbsQueB(Gmac *pGmac);
00296
00297 void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA);
00298
00299 void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB);
00300
00301 void GMAC_SetTsuTmrIncReg( Gmac *pGmac, uint32_t nanoSec);
00302
00303 uint16_t GMAC_GetPtpEvtMsgRxdMsbSec( Gmac *pGmac );
00304
00305 uint32_t GMAC_GetPtpEvtMsgRxdLsbSec( Gmac *pGmac );
00306
00307 uint32_t GMAC_GetPtpEvtMsgRxdNanoSec( Gmac *pGmac );
00308
00309 void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, uint32_t nanosec );
00310
00311 void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec);
00312
00313 void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31);
00314
00315 void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47);
00316
00317 uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac);
00318
00319 uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac);
00320
00321 uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac);
00322
00323 uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac);
00324
00325 uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac);
00326
00327 uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac);
00328
00329 uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac);
00330
00331 uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac);
00332
00333 #ifdef __cplusplus
00334 }
00335 #endif
00336
00337 #endif // #ifndef GMAC_H
00338