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00030 #include "samv71.h"
00031
00032
00033
00034 #ifdef __cplusplus
00035 extern "C" {
00036 #endif
00037
00038
00039
00040
00041
00042
00043 #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
00044 #ifdef MCK_123MHZ
00045
00046
00047 #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x28U) | \
00048 CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
00049
00050 #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK \
00051 | PMC_MCKR_MDIV_PCK_DIV2)
00052 #else
00053 #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) | \
00054 CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
00055
00056 #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK \
00057 | PMC_MCKR_MDIV_PCK_DIV2)
00058 #endif
00059
00060 uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
00061 #define USBCLK_DIV 10
00062
00063
00064
00065
00066
00067 void SystemInit( void )
00068 {
00069 uint32_t read_MOR;
00070
00071 EFC->EEFC_FMR = EEFC_FMR_FWS(5);
00072
00073
00074
00075
00076
00077
00078 read_MOR = PMC->CKGR_MOR;
00079
00080 read_MOR |= (CKGR_MOR_KEY_PASSWD |CKGR_MOR_XT32KFME);
00081 PMC->CKGR_MOR = read_MOR;
00082
00083
00084 if ( (SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST )
00085 {
00086 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
00087
00088 while( !(SUPC->SUPC_SR & SUPC_SR_OSCSEL) );
00089 }
00090
00091
00092 if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
00093 {
00094 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT
00095 | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
00096
00097 while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) )
00098 {
00099 }
00100 }
00101
00102
00103 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT
00104 | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
00105
00106 while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) )
00107 {
00108 }
00109
00110 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk)
00111 | PMC_MCKR_CSS_MAIN_CLK;
00112
00113 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
00114 {
00115 }
00116
00117
00118 PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
00119 while ( !(PMC->PMC_SR & PMC_SR_LOCKA) )
00120 {
00121 }
00122
00123
00124 PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
00125 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
00126 {
00127 }
00128
00129
00130 PMC->PMC_MCKR = SYS_BOARD_MCKR;
00131 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
00132 {
00133 }
00134
00135 SystemCoreClock = CHIP_FREQ_CPU_MAX;
00136 }
00137
00138 void SystemCoreClockUpdate( void )
00139 {
00140
00141 switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
00142 {
00143 case PMC_MCKR_CSS_SLOW_CLK:
00144 if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
00145 {
00146 SystemCoreClock = CHIP_FREQ_XTAL_32K;
00147 }
00148 else
00149 {
00150 SystemCoreClock = CHIP_FREQ_SLCK_RC;
00151 }
00152 break;
00153
00154 case PMC_MCKR_CSS_MAIN_CLK:
00155 if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
00156 {
00157 SystemCoreClock = CHIP_FREQ_XTAL_12M;
00158 }
00159 else
00160 {
00161 SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
00162
00163 switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
00164 {
00165 case CKGR_MOR_MOSCRCF_4_MHz:
00166 break;
00167
00168 case CKGR_MOR_MOSCRCF_8_MHz:
00169 SystemCoreClock *= 2U;
00170 break;
00171
00172 case CKGR_MOR_MOSCRCF_12_MHz:
00173 SystemCoreClock *= 3U;
00174 break;
00175
00176 default:
00177 break;
00178 }
00179 }
00180 break;
00181
00182 case PMC_MCKR_CSS_PLLA_CLK:
00183 if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
00184 {
00185 SystemCoreClock = CHIP_FREQ_XTAL_12M ;
00186 }
00187 else
00188 {
00189 SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
00190
00191 switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
00192 {
00193 case CKGR_MOR_MOSCRCF_4_MHz:
00194 break;
00195
00196 case CKGR_MOR_MOSCRCF_8_MHz:
00197 SystemCoreClock *= 2U;
00198 break;
00199
00200 case CKGR_MOR_MOSCRCF_12_MHz:
00201 SystemCoreClock *= 3U;
00202 break;
00203
00204 default:
00205 break;
00206 }
00207 }
00208
00209 if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
00210 == PMC_MCKR_CSS_PLLA_CLK )
00211 {
00212 SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk)
00213 >> CKGR_PLLAR_MULA_Pos) + 1U);
00214 SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk)
00215 >> CKGR_PLLAR_DIVA_Pos));
00216 }
00217 break;
00218
00219 default:
00220 break;
00221 }
00222
00223 if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
00224 {
00225 SystemCoreClock /= 3U;
00226 }
00227 else
00228 {
00229 SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk)
00230 >> PMC_MCKR_PRES_Pos);
00231 }
00232 }
00233
00234
00235
00236 void system_init_flash( uint32_t ul_clk )
00237 {
00238
00239 if ( ul_clk < CHIP_FREQ_FWS_0 )
00240 {
00241 EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
00242 }
00243 else
00244 {
00245 if (ul_clk < CHIP_FREQ_FWS_1)
00246 {
00247 EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
00248 }
00249 else
00250 {
00251 if (ul_clk < CHIP_FREQ_FWS_2)
00252 {
00253 EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
00254 }
00255 else
00256 {
00257 if ( ul_clk < CHIP_FREQ_FWS_3 )
00258 {
00259 EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
00260 }
00261 else
00262 {
00263 if ( ul_clk < CHIP_FREQ_FWS_4 )
00264 {
00265 EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
00266 }
00267 else
00268 {
00269 EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
00270 }
00271 }
00272 }
00273 }
00274 }
00275 }
00276
00277
00278
00279
00280
00281
00282
00283 void sysclk_enable_usb(void)
00284 {
00285
00286 PMC->PMC_SCDR = PMC_SCDR_USBCLK;
00287
00288
00289 PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF);
00290
00291 while( !(PMC->PMC_SR & PMC_SR_LOCKU) );
00292
00293
00294 PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1) );
00295
00296 PMC->PMC_SCER = PMC_SCER_USBCLK;
00297 }
00298
00299
00300
00301
00302
00303
00304
00305
00306
00307 void sysclk_disable_usb(void)
00308 {
00309
00310 PMC->PMC_SCDR = PMC_SCDR_USBCLK;
00311
00312
00313 PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF);
00314
00315 while( !(PMC->PMC_SR & PMC_SR_LOCKU) );
00316
00317
00318 PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1) );
00319
00320
00321 }
00322
00323
00324
00325
00326 #ifdef __cplusplus
00327 }
00328 #endif
00329
00330