SAMV71 Xplained Ultra Software Package 1.4

gmac.h

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License 
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2012, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /** \file */
00031 
00032 /** \addtogroup gmac_module
00033  * @{
00034  * Provides the interface to configure and use the GMAC peripheral.
00035  *
00036  * \section gmac_usage Usage
00037  * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls
00038  *   are also available, such as:
00039  *   - GMAC_SetSpeed(): Setup GMAC working clock.
00040  *   - GMAC_FullDuplexEnable(): Working in full duplex or not.
00041  *   - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF).
00042  *   - ...
00043  * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls
00044  *   can modify with:
00045  *   - GMAC_ReceiveEnable(): Enable/Disable Rx.
00046  *   - GMAC_TransmitEnable(): Enable/Disable Tx.
00047  *   - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving.
00048  *   - ...
00049  * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(),
00050  *   GMAC_GetItMask() and GMAC_GetItStatus().
00051  * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus()
00052  *   GMAC_ClearTxStatus() and GMAC_ClearRxStatus().
00053  * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(),
00054  *   GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define
00055  *   by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor.
00056  * - Manage PHY through GMAC is performed by
00057  *   - GMAC_ManagementEnable(): Enable/Disable PHY management.
00058  *   - GMAC_PHYMaintain(): Execute PHY management commands.
00059  *   - GMAC_PHYData(): Return PHY management data.
00060  *   - GMAC_IsIdle(): Check if PHY is idle.
00061  * - Setup GMAC parameters with following functions:
00062  *   - GMAC_SetHash(): Set Hash value.
00063  *   - GMAC_SetAddress(): Set MAC address.
00064  * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable()
00065  * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable()
00066  *
00067  * For more accurate information, please look at the GMAC section of the
00068  * Datasheet.
00069  *
00070  * \sa \ref gmacd_module
00071  *
00072  * Related files:\n
00073  * gmac.c\n
00074  * gmac.h.\n
00075  *
00076  *   \defgroup gmac_defines GMAC Defines
00077  *   \defgroup gmac_structs GMAC Data Structs
00078  *   \defgroup gmac_functions GMAC Functions
00079  */
00080 /**@}*/
00081 
00082 #ifndef _GMAC_H
00083 #define _GMAC_H
00084 
00085 /*----------------------------------------------------------------------------
00086  *        Headers
00087  *----------------------------------------------------------------------------*/
00088 #include "chip.h"
00089 
00090 #include <stdint.h>
00091 
00092 #ifdef __cplusplus
00093  extern "C" {
00094 #endif
00095 
00096 /*----------------------------------------------------------------------------
00097  *        Defines
00098  *----------------------------------------------------------------------------*/
00099 /** \addtogroup gmac_defines
00100         @{*/
00101 
00102 #define NUM_GMAC_QUEUES 3
00103 /// Board GMAC base address
00104 
00105 #define GMAC_DUPLEX_HALF 0
00106 #define GMAC_DUPLEX_FULL 1
00107 
00108 //
00109 #define GMAC_SPEED_10M      0
00110 #define GMAC_SPEED_100M     1
00111 #define GMAC_SPEED_1000M    2
00112    
00113 /*------------------------------------------------------------------------------
00114                             Definitions
00115 ------------------------------------------------------------------------------
00116 */
00117 /// The buffer addresses written into the descriptors must be aligned so the
00118 /// last few bits are zero.  These bits have special meaning for the GMAC
00119 /// peripheral and cannot be used as part of the address.
00120 #define GMAC_ADDRESS_MASK   ((unsigned int)0xFFFFFFFC)
00121 #define GMAC_LENGTH_FRAME   ((unsigned int)0x3FFF)    /// Length of frame mask
00122 
00123 // receive buffer descriptor bits
00124 #define GMAC_RX_OWNERSHIP_BIT   (1u <<  0)
00125 #define GMAC_RX_WRAP_BIT        (1u <<  1)
00126 #define GMAC_RX_SOF_BIT         (1u << 14)
00127 #define GMAC_RX_EOF_BIT         (1u << 15)
00128 
00129 // Transmit buffer descriptor bits
00130 #define GMAC_TX_LAST_BUFFER_BIT (1u << 15)
00131 #define GMAC_TX_WRAP_BIT        (1u << 30)
00132 #define GMAC_TX_USED_BIT        (1u << 31)
00133 #define GMAC_TX_RLE_BIT         (1u << 29) /// Retry Limit Exceeded
00134 #define GMAC_TX_UND_BIT         (1u << 28) /// Tx Buffer Under-run
00135 #define GMAC_TX_ERR_BIT         (1u << 27) /// Exhausted in mid-frame
00136 #define GMAC_TX_ERR_BITS  \
00137     (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT)
00138 
00139 // Interrupt bits
00140 #define GMAC_INT_RX_BITS  \
00141     (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR)
00142 #define GMAC_INT_TX_ERR_BITS  \
00143     (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP)
00144 #define GMAC_INT_TX_BITS  \
00145     (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP)
00146 // Interrupt Status bits
00147 #define GMAC_INT_RX_STATUS_BITS  \
00148     (GMAC_ISR_RCOMP | GMAC_ISR_RXUBR | GMAC_ISR_ROVR)
00149 #define GMAC_INT_TX_STATUS_ERR_BITS  \
00150     (GMAC_ISR_TUR | GMAC_ISR_RLEX | GMAC_ISR_TFC | GMAC_ISR_HRESP)
00151 /*----------------------------------------------------------------------------
00152  *        Types
00153  *----------------------------------------------------------------------------*/
00154 /** \addtogroup gmac_structs
00155         @{*/
00156    
00157 /* This is the list of GMAC queue */
00158 typedef enum  {
00159     GMAC_QUE_0 = 0,
00160     GMAC_QUE_1 = 1,
00161     GMAC_QUE_2 = 2
00162 }gmacQueList_t;
00163 
00164 /** Receive buffer descriptor struct */
00165 typedef struct _GmacRxDescriptor {
00166     union _GmacRxAddr {
00167         uint32_t val;
00168         struct _GmacRxAddrBM {
00169             uint32_t bOwnership:1,  /**< User clear, GMAC set this to one once
00170                                          it has successfully written a frame to
00171                                          memory */
00172                      bWrap:1,       /**< Marks last descriptor in receive buffer */
00173                      addrDW:30;     /**< Address in number of DW */
00174         } bm;
00175     } addr;                    /**< Address, Wrap & Ownership */
00176     union _GmacRxStatus {
00177         uint32_t val;
00178         struct _GmacRxStatusBM {
00179             uint32_t len:12,                /** Length of frame including FCS */
00180                      offset:2,              /** Receive buffer offset,
00181                                                 bits 13:12 of frame length for jumbo
00182                                                 frame */
00183                      bSof:1,                /** Start of frame */
00184                      bEof:1,                /** End of frame */
00185                      bCFI:1,                /** Concatenation Format Indicator */
00186                      vlanPriority:3,        /** VLAN priority (if VLAN detected) */
00187                      bPriorityDetected:1,   /** Priority tag detected */
00188                      bVlanDetected:1,       /**< VLAN tag detected */
00189                      bTypeIDMatch:1,        /**< Type ID match */
00190                      bAddr4Match:1,         /**< Address register 4 match */
00191                      bAddr3Match:1,         /**< Address register 3 match */
00192                      bAddr2Match:1,         /**< Address register 2 match */
00193                      bAddr1Match:1,         /**< Address register 1 match */
00194                      reserved:1,
00195                      bExtAddrMatch:1,       /**< External address match */
00196                      bUniHashMatch:1,       /**< Unicast hash match */
00197                      bMultiHashMatch:1,     /**< Multicast hash match */
00198                      bBroadcastDetected:1;  /**< Global all ones broadcast
00199                                                  address detected */
00200         } bm;
00201     } status;
00202 } sGmacRxDescriptor ;    /* GCC */
00203 
00204 /** Transmit buffer descriptor struct */
00205 typedef struct _GmacTxDescriptor {
00206     uint32_t addr;
00207     union _GmacTxStatus {
00208         uint32_t val;
00209         struct _GmacTxStatusBM {
00210             uint32_t len:11,        /**< Length of buffer */
00211                      reserved:4,
00212                      bLastBuffer:1, /**< Last buffer (in the current frame) */
00213                      bNoCRC:1,      /**< No CRC */
00214                      reserved1:10,
00215                      bExhausted:1,  /**< Buffer exhausted in mid frame */
00216                      bUnderrun:1,   /**< Transmit under run */
00217                      bError:1,      /**< Retry limit exceeded, error detected */
00218                      bWrap:1,       /**< Marks last descriptor in TD list */
00219                      bUsed:1;       /**< User clear, GMAC sets this once a frame
00220                                          has been successfully transmitted */
00221         } bm;
00222     } status;
00223 } sGmacTxDescriptor;     /* GCC */
00224 
00225 /**     @}*/
00226 
00227 //-----------------------------------------------------------------------------
00228 //         PHY Exported functions
00229 //-----------------------------------------------------------------------------
00230 extern uint8_t GMAC_IsIdle(Gmac *pGmac);
00231 extern void GMAC_PHYMaintain(Gmac      *pGmac,
00232                              uint8_t   bPhyAddr,
00233                              uint8_t   bRegAddr,
00234                              uint8_t   bRW,
00235                              uint16_t  wData);
00236 extern uint16_t GMAC_PHYData(Gmac *pGmac);
00237 extern void GMAC_ClearStatistics(Gmac *pGmac);
00238 extern void GMAC_IncreaseStatistics(Gmac *pGmac);
00239 extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis);
00240 extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck );
00241 extern void GMAC_EnableMdio(Gmac *pGmac );
00242 extern void GMAC_DisableMdio(Gmac *pGmac );
00243 extern void GMAC_EnableMII(Gmac *pGmac );
00244 extern void GMAC_EnableRMII(Gmac *pGmac );
00245 extern void GMAC_EnableGMII( Gmac *pGmac );
00246 extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex);
00247 extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx);
00248 extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
00249 extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx);
00250 extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources);
00251 extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx);
00252 extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx);
00253 extern uint32_t GMAC_GetTxStatus(Gmac *pGmac);
00254 extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus);
00255 extern uint32_t GMAC_GetRxStatus(Gmac *pGmac);
00256 extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus);
00257 extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis);
00258 extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis);
00259 extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac);
00260 extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx);
00261 extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
00262 extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx);
00263 extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx);
00264 extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR);
00265 extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac);
00266 extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr);
00267 extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB);
00268 extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac);
00269 extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg);
00270 extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx);
00271 extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx);
00272 extern uint32_t GMAC_GetConfigure(Gmac *pGmac);
00273 extern void GMAC_TransmissionStart(Gmac *pGmac);
00274 extern void GMAC_TransmissionHalt(Gmac *pGmac);
00275 extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed);
00276 
00277 void GMAC_ClearScreener1Reg (Gmac* pGmac, gmacQueList_t queueIdx);
00278 
00279 void GMAC_WriteScreener1Reg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal);
00280 
00281 void GMAC_ClearScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx);
00282 
00283 void GMAC_WriteScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal);
00284 
00285 void GMAC_WriteEthTypeReg (Gmac* pGmac, gmacQueList_t queueIdx,  uint16_t etherType);
00286 
00287 void GMAC_WriteCompareReg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, uint16_t c1Reg);
00288 
00289 void GMAC_EnableCbsQueA(Gmac *pGmac);
00290 
00291 void GMAC_DisableCbsQueA(Gmac *pGmac);
00292 
00293 void GMAC_EnableCbsQueB(Gmac *pGmac);
00294 
00295 void GMAC_DisableCbsQueB(Gmac *pGmac);
00296 
00297 void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA);
00298 
00299 void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB);
00300 
00301 void GMAC_SetTsuTmrIncReg( Gmac *pGmac, uint32_t nanoSec);
00302 
00303 uint16_t GMAC_GetPtpEvtMsgRxdMsbSec( Gmac *pGmac );
00304 
00305 uint32_t GMAC_GetPtpEvtMsgRxdLsbSec( Gmac *pGmac );
00306 
00307 uint32_t GMAC_GetPtpEvtMsgRxdNanoSec( Gmac *pGmac );
00308 
00309 void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, uint32_t nanosec );
00310 
00311 void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec);
00312 
00313 void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31);
00314 
00315 void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47);
00316 
00317 uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac);
00318 
00319 uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac);
00320 
00321 uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac);
00322 
00323 uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac);
00324 
00325 uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac);
00326 
00327 uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac);
00328 
00329 uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac);
00330 
00331 uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac);
00332 
00333 #ifdef __cplusplus
00334 }
00335 #endif
00336 
00337 #endif // #ifndef GMAC_H
00338 
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