Twi hardware registers. More...
#include <D:/git/git_canopus_1/softpack/samv7/libraries/libchip_samv7/include/samv7/component/component_twi.h>
Data Fields | |
__O uint32_t | TWI_CR |
(Twi Offset: 0x00) Control Register | |
__IO uint32_t | TWI_MMR |
(Twi Offset: 0x04) Master Mode Register | |
__IO uint32_t | TWI_SMR |
(Twi Offset: 0x08) Slave Mode Register | |
__IO uint32_t | TWI_IADR |
(Twi Offset: 0x0C) Internal Address Register | |
__IO uint32_t | TWI_CWGR |
(Twi Offset: 0x10) Clock Waveform Generator Register | |
__I uint32_t | Reserved1 [3] |
__I uint32_t | TWI_SR |
(Twi Offset: 0x20) Status Register | |
__O uint32_t | TWI_IER |
(Twi Offset: 0x24) Interrupt Enable Register | |
__O uint32_t | TWI_IDR |
(Twi Offset: 0x28) Interrupt Disable Register | |
__I uint32_t | TWI_IMR |
(Twi Offset: 0x2C) Interrupt Mask Register | |
__I uint32_t | TWI_RHR |
(Twi Offset: 0x30) Receive Holding Register | |
__O uint32_t | TWI_THR |
(Twi Offset: 0x34) Transmit Holding Register | |
__I uint32_t | Reserved2 [43] |
__IO uint32_t | TWI_WPMR |
(Twi Offset: 0xE4) Write Protection Mode Register | |
__I uint32_t | TWI_WPSR |
(Twi Offset: 0xE8) Write Protection Status Register |
Twi hardware registers.
Definition at line 41 of file component_twi.h.