SAMV71 Xplained Ultra Software Package 1.4

board_lowlevel.c

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2012, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00024  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /**
00031  * \file
00032  *
00033  * Provides the low-level initialization function that called on chip startup.
00034  */
00035 
00036 /*----------------------------------------------------------------------------
00037  *        Headers
00038  *----------------------------------------------------------------------------*/
00039 
00040 #include "board.h"
00041 
00042 
00043 #if defined(ENABLE_TCM) && defined(__GNUC__)
00044     extern char _itcm_lma, _sitcm, _eitcm;
00045 #endif
00046 
00047 
00048 /*----------------------------------------------------------------------------
00049  *        Exported functions
00050  *----------------------------------------------------------------------------*/
00051 /* Default memory map 
00052    Address range        Memory region      Memory type   Shareability  Cache policy
00053    0x00000000- 0x1FFFFFFF Code             Normal        Non-shareable  WT
00054    0x20000000- 0x3FFFFFFF SRAM             Normal        Non-shareable  WBWA
00055    0x40000000- 0x5FFFFFFF Peripheral       Device        Non-shareable  -
00056    0x60000000- 0x7FFFFFFF RAM              Normal        Non-shareable  WBWA
00057    0x80000000- 0x9FFFFFFF RAM              Normal        Non-shareable  WT
00058    0xA0000000- 0xBFFFFFFF Device           Device        Shareable
00059    0xC0000000- 0xDFFFFFFF Device           Device        Non Shareable
00060    0xE0000000- 0xFFFFFFFF System           -                  -
00061    */
00062 
00063 /**
00064  * \brief Set up a memory region.
00065  */
00066 void _SetupMemoryRegion( void )
00067 {
00068 
00069     uint32_t dwRegionBaseAddr;
00070     uint32_t dwRegionAttr;
00071     
00072     memory_barrier();
00073 
00074 /***************************************************
00075     ITCM memory region --- Normal 
00076     START_Addr:-  0x00000000UL
00077     END_Addr:-    0x00400000UL
00078 ****************************************************/
00079     dwRegionBaseAddr = 
00080         ITCM_START_ADDRESS |
00081         MPU_REGION_VALID |
00082         MPU_DEFAULT_ITCM_REGION;        // 1
00083 
00084     dwRegionAttr = 
00085         MPU_AP_PRIVILEGED_READ_WRITE | 
00086         MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
00087         MPU_REGION_ENABLE;
00088 
00089     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00090 
00091 /****************************************************
00092     Internal flash memory region --- Normal read-only 
00093     (update to Strongly ordered in write accesses)
00094     START_Addr:-  0x00400000UL
00095     END_Addr:-    0x00600000UL
00096 ******************************************************/
00097     
00098     dwRegionBaseAddr = 
00099         IFLASH_START_ADDRESS |
00100         MPU_REGION_VALID |
00101         MPU_DEFAULT_IFLASH_REGION;      //2
00102 
00103     dwRegionAttr = 
00104         MPU_AP_READONLY |
00105         INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
00106         MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
00107         MPU_REGION_ENABLE;
00108 
00109     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00110 
00111 /****************************************************
00112     DTCM memory region --- Normal
00113     START_Addr:-  0x20000000L
00114     END_Addr:-    0x20400000UL
00115 ******************************************************/
00116 
00117     /* DTCM memory region */
00118     dwRegionBaseAddr = 
00119         DTCM_START_ADDRESS |
00120         MPU_REGION_VALID |
00121         MPU_DEFAULT_DTCM_REGION;         //3
00122 
00123     dwRegionAttr = 
00124         MPU_AP_PRIVILEGED_READ_WRITE | 
00125         MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
00126         MPU_REGION_ENABLE;
00127 
00128     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00129 
00130 /****************************************************
00131     SRAM Cacheable memory region --- Normal
00132     START_Addr:-  0x20400000UL
00133     END_Addr:-    0x2043FFFFUL
00134 ******************************************************/
00135     /* SRAM memory  region */
00136     dwRegionBaseAddr = 
00137         SRAM_FIRST_START_ADDRESS |
00138         MPU_REGION_VALID |
00139         MPU_DEFAULT_SRAM_REGION_1;         //4
00140 
00141     dwRegionAttr = 
00142         MPU_AP_FULL_ACCESS    |
00143         INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
00144         MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS) 
00145         | MPU_REGION_ENABLE;
00146 
00147     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00148 
00149     
00150 /****************************************************
00151     Internal SRAM second partition memory region --- Normal 
00152     START_Addr:-  0x20440000UL
00153     END_Addr:-    0x2045FFFFUL
00154 ******************************************************/
00155     /* SRAM memory region */
00156     dwRegionBaseAddr = 
00157         SRAM_SECOND_START_ADDRESS |
00158         MPU_REGION_VALID |
00159         MPU_DEFAULT_SRAM_REGION_2;         //5
00160 
00161     dwRegionAttr = 
00162         MPU_AP_FULL_ACCESS    |
00163         INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) |
00164         MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
00165         MPU_REGION_ENABLE;
00166 
00167     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00168     
00169 #ifdef MPU_HAS_NOCACHE_REGION
00170     dwRegionBaseAddr =
00171         SRAM_NOCACHE_START_ADDRESS |
00172         MPU_REGION_VALID |
00173         MPU_NOCACHE_SRAM_REGION;          //11
00174 
00175     dwRegionAttr =
00176         MPU_AP_FULL_ACCESS    |
00177         INNER_OUTER_NORMAL_NOCACHE_TYPE( SHAREABLE ) |
00178         MPU_CalMPURegionSize(NOCACHE_SRAM_REGION_SIZE) |
00179         MPU_REGION_ENABLE;
00180 
00181     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00182 #endif
00183     
00184 /****************************************************
00185     Peripheral memory region --- DEVICE Shareable
00186     START_Addr:-  0x40000000UL
00187     END_Addr:-    0x5FFFFFFFUL
00188 ******************************************************/
00189     dwRegionBaseAddr = 
00190         PERIPHERALS_START_ADDRESS |
00191         MPU_REGION_VALID |
00192         MPU_PERIPHERALS_REGION;          //6
00193 
00194     dwRegionAttr = MPU_AP_FULL_ACCESS |
00195         MPU_REGION_EXECUTE_NEVER |
00196         SHAREABLE_DEVICE_TYPE |
00197         MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
00198         |MPU_REGION_ENABLE;
00199 
00200     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00201 
00202 
00203 /****************************************************
00204     External EBI memory  memory region --- Strongly Ordered
00205     START_Addr:-  0x60000000UL
00206     END_Addr:-    0x6FFFFFFFUL
00207 ******************************************************/
00208     dwRegionBaseAddr =
00209         EXT_EBI_START_ADDRESS |
00210         MPU_REGION_VALID |
00211         MPU_EXT_EBI_REGION;
00212 
00213     dwRegionAttr =
00214         MPU_AP_FULL_ACCESS |
00215         /* External memory Must be defined with 'Device' or 'Strongly Ordered'
00216         attribute for write accesses (AXI) */
00217         STRONGLY_ORDERED_SHAREABLE_TYPE |
00218         MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
00219         MPU_REGION_ENABLE;
00220 
00221     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00222 
00223 /****************************************************
00224     SDRAM Cacheable memory region --- Normal
00225     START_Addr:-  0x70000000UL
00226     END_Addr:-    0x7FFFFFFFUL
00227 ******************************************************/
00228     dwRegionBaseAddr = 
00229         SDRAM_START_ADDRESS |
00230         MPU_REGION_VALID |
00231         MPU_DEFAULT_SDRAM_REGION;        //7
00232 
00233     dwRegionAttr = 
00234         MPU_AP_FULL_ACCESS    |
00235         INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) |
00236         MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
00237         MPU_REGION_ENABLE;
00238 
00239     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00240 
00241 /****************************************************
00242     QSPI memory region --- Strongly ordered
00243     START_Addr:-  0x80000000UL
00244     END_Addr:-    0x9FFFFFFFUL
00245 ******************************************************/
00246     dwRegionBaseAddr = 
00247         QSPI_START_ADDRESS |
00248         MPU_REGION_VALID |
00249         MPU_QSPIMEM_REGION;              //8
00250 
00251     dwRegionAttr = 
00252         MPU_AP_FULL_ACCESS |
00253         STRONGLY_ORDERED_SHAREABLE_TYPE |
00254         MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
00255         MPU_REGION_ENABLE;
00256 
00257     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00258 
00259   
00260 /****************************************************
00261     USB RAM Memory region --- Device
00262     START_Addr:-  0xA0100000UL
00263     END_Addr:-    0xA01FFFFFUL
00264 ******************************************************/
00265     dwRegionBaseAddr = 
00266         USBHSRAM_START_ADDRESS |
00267         MPU_REGION_VALID |
00268         MPU_USBHSRAM_REGION;              //9
00269 
00270     dwRegionAttr = 
00271         MPU_AP_FULL_ACCESS |
00272         MPU_REGION_EXECUTE_NEVER |
00273         SHAREABLE_DEVICE_TYPE |
00274         MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
00275         MPU_REGION_ENABLE;
00276 
00277     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00278 
00279 
00280     /* Enable the memory management fault , Bus Fault, Usage Fault exception */
00281     SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
00282                     | SCB_SHCSR_USGFAULTENA_Msk);
00283 
00284     /* Enable the MPU region */
00285     MPU_Enable( MPU_ENABLE | MPU_PRIVDEFENA);
00286     
00287     memory_sync();
00288 }
00289 
00290 #ifdef ENABLE_TCM
00291 
00292 #if defined ( __ICCARM__ ) /* IAR Ewarm */
00293 #pragma section = "CSTACK"
00294 #pragma section = "CSTACK_DTCM"
00295     #define SRAM_STACK_BASE     (__section_begin("CSTACK"))
00296     #define DTCM_STACK_BASE     (__section_begin("CSTACK_DTCM"))
00297     #define SRAM_STACK_LIMIT    (__section_end("CSTACK"))
00298     #define DTCM_STACK_LIMIT    (__section_end("CSTACK_DTCM"))
00299 #elif defined (__CC_ARM)  /* MDK */
00300     extern uint32_t Image$$ARM_LIB_STACK$$Base;
00301     extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
00302     extern uint32_t Image$$DTCM_STACK$$Base;
00303     extern uint32_t Image$$DTCM_STACK$$ZI$$Limit;
00304     #define SRAM_STACK_BASE     (&Image$$ARM_LIB_STACK$$Base)
00305     #define DTCM_STACK_BASE     (&Image$$DTCM_STACK$$Base)
00306     #define SRAM_STACK_LIMIT    (&Image$$ARM_LIB_STACK$$ZI$$Limit)
00307     #define DTCM_STACK_LIMIT    (&Image$$DTCM_STACK$$ZI$$Limit)
00308 #elif defined (  __GNUC__  )  /* GCC */
00309     extern char _sdtcm_stack, _edtcm_stack, _sstack, _estack;
00310     #define SRAM_STACK_BASE     ((void *)(&_sstack))
00311     #define DTCM_STACK_BASE     ((void *)(&_sdtcm_stack))
00312     #define SRAM_STACK_LIMIT    ((void *)(&_estack))
00313     #define DTCM_STACK_LIMIT    ((void *)(&_edtcm_stack))
00314 #endif
00315 
00316 /** \brief  Change stack's location to DTCM
00317 
00318     The function changes the stack's location from SRAM to DTCM
00319  */
00320 void TCM_StackInit(void);
00321 void TCM_StackInit(void)
00322 {
00323     uint32_t offset = (uint32_t)SRAM_STACK_LIMIT - (uint32_t)DTCM_STACK_LIMIT;
00324     volatile char *dst = (volatile char *)DTCM_STACK_LIMIT;
00325     volatile char *src = (volatile char *)SRAM_STACK_LIMIT;
00326     /* copy stack data from SRAM to DTCM */
00327     while(src > (volatile char *)SRAM_STACK_BASE){
00328         *--dst = *--src;
00329     }
00330     __set_MSP(__get_MSP() - offset);
00331 }
00332 
00333 #endif
00334 
00335 
00336 /**
00337  * \brief Performs the low-level initialization of the chip.
00338  */
00339 extern WEAK void LowLevelInit( void )
00340 {
00341   
00342     SystemInit(); 
00343 #ifndef MPU_EXAMPLE_FEATURE
00344     _SetupMemoryRegion();
00345 #endif
00346 
00347 #if defined(FFT_DEMO) && ( defined(__GNUC__) || defined(__CC_ARM) )
00348     /* Enabling the FPU */
00349     SCB->CPACR |= 0x00F00000;
00350     __DSB();
00351     __ISB();
00352 #endif
00353 
00354 #if defined(ENABLE_TCM) && defined(__GNUC__)
00355     volatile char *dst = &_sitcm;
00356     volatile char *src = &_itcm_lma;
00357     /* copy code_TCM from flash to ITCM */
00358     while(dst < &_eitcm){
00359         *dst++ = *src++;
00360     }
00361 #endif
00362 }
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