SAMV71 Xplained Ultra Software Package 1.4

qspi.h

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License 
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2011, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 
00031 /**
00032  * \file
00033  *
00034  * Interface for Serial Peripheral Interface (SPI) controller.
00035  *
00036  */
00037 
00038 #ifndef _QSPI_
00039 #define _QSPI_
00040 /*----------------------------------------------------------------------------
00041  *        Macros
00042  *----------------------------------------------------------------------------*/
00043 
00044 /**
00045  *
00046  * Here are several macros which should be used when configuring a SPI
00047  * peripheral.
00048  *
00049  * \section qspi_configuration_macros SPI Configuration Macros
00050  * - \ref QSPI_PCS
00051  * - \ref QSPI_SCBR
00052  * - \ref QSPI_DLYBS
00053  * - \ref QSPI_DLYBCT
00054  */
00055 
00056 /** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
00057 #define QSPI_SCBR(baudrate, masterClock) \
00058         ((uint32_t) (masterClock / baudrate) << 8)
00059 
00060 /** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
00061 #define QSPI_DLYBS(delay, masterClock) \
00062         ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16)
00063 
00064 /** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
00065 #define QSPI_DLYBCT(delay, masterClock) \
00066         ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24)
00067 
00068 /*--------------------------------------------------------------------------- */
00069 
00070 #ifdef __cplusplus
00071  extern "C" {
00072 #endif
00073 
00074 /*----------------------------------------------------------------------------
00075  *        Exported functions
00076  *----------------------------------------------------------------------------*/
00077   
00078 /** \brief qspi access modes 
00079  */
00080 typedef enum{
00081      CmdAccess = 0,
00082      ReadAccess,
00083      WriteAccess
00084 }Access_t;
00085 
00086 /** \brief qspi modes SPI or QSPI
00087  */
00088 typedef enum{
00089     SpiMode = QSPI_MR_SMM_SPI,
00090     QspiMemMode = QSPI_MR_SMM_MEMORY
00091 }QspiMode_t;
00092 
00093 
00094 /** \brief qspi clock modes , regarding clock phase and clock polarity
00095  */
00096 typedef enum{
00097     ClockMode_00 = 0,
00098     ClockMode_10,
00099     ClockMode_01,
00100     ClockMode_11
00101 }QspiClockMode_t;
00102 
00103 
00104 /** \brief qspi status codes
00105  */
00106 typedef enum{
00107     QSPI_SUCCESS = 0,
00108     QSPI_BUSY,
00109     QSPI_BUSY_SENDING,
00110     QSPI_READ_ERROR,
00111     QSPI_WRITE_ERROR,
00112     QSPI_UNKNOWN_ERROR,
00113     QSPI_INIT_ERROR,
00114     QSPI_INPUT_ERROR,
00115     QSPI_TOTAL_ERROR
00116 }QspidStatus_t;
00117      
00118 
00119 /** \brief qspi status regiter bits
00120  */
00121 typedef enum {
00122     IsReceived    = QSPI_SR_RDRF,
00123     IsTxSent      = QSPI_SR_TDRE,
00124     IsTxEmpty     = QSPI_SR_TXEMPTY,
00125     IsOverrun     = QSPI_SR_OVRES,
00126     IsCsRise      = QSPI_SR_CSR,
00127     IsCsAsserted  = QSPI_SR_CSS,
00128     IsEofInst     = QSPI_SR_INSTRE,
00129     IsEnabled     = QSPI_SR_QSPIENS
00130 }QspiStatus_t;
00131 
00132 /** \brief qspi command structure
00133  */
00134 typedef struct {
00135     uint8_t       Instruction; 
00136     uint8_t       Option;  
00137 }QspiMemCmd_t;
00138 
00139 /** \brief qspi buffer structure
00140  */
00141 typedef struct {
00142     uint32_t      TxDataSize;     /* Tx buffer size */
00143     uint32_t      RxDataSize;     /* Rx buffer size */
00144     uint32_t      *pDataTx;       /* Tx buffer */
00145     uint32_t      *pDataRx;       /* Rx buffer */
00146 }QspiBuffer_t;
00147 
00148 
00149 /** \brief qspi frame structure for QSPI mode
00150  */
00151 typedef struct {
00152    union _QspiInstFrame {
00153         uint32_t val;
00154         struct _QspiInstFrameBM {
00155             uint32_t bwidth:3,          /** Width of QSPI Addr , inst data */
00156                      reserved0:1,        /** Reserved*/
00157                      bInstEn:1,         /** Enable Inst */
00158                      bAddrEn:1,         /** Enable Address */
00159                      bOptEn:1,          /** Enable Option */
00160                      bDataEn:1,         /** Enable Data */
00161                      bOptLen:2,         /** Option Length*/
00162                      bAddrLen:1,        /** Addrs Length*/
00163                      reserved1:1,        /** Option Length*/
00164                      bXfrType:2,        /** Transfer type*/
00165                      bContinuesRead:1,  /** Continoues read mode*/
00166                      reserved2:1,        /** Reserved*/
00167                      bDummyCycles:5,    /**< Unicast hash match */
00168                      reserved3:11;       /** Reserved*/
00169         } bm;
00170     } InstFrame;
00171   uint32_t       Addr;
00172 }QspiInstFrame_t;
00173 
00174 /** \brief qspi driver structure
00175  */
00176 typedef struct {
00177     uint8_t           qspiId;         /* QSPI ID */
00178     Qspi              *pQspiHw;       /* QSPI Hw instance */
00179     QspiMode_t        qspiMode;       /* Qspi mode: SPI or QSPI */
00180     QspiMemCmd_t      qspiCommand;    /* Qspi command structure*/
00181     QspiBuffer_t      qspiBuffer;     /* Qspi buffer*/
00182     QspiInstFrame_t   *pQspiFrame;    /* Qspi QSPI mode Fram register informations*/
00183 }Qspid_t;
00184 
00185 
00186 void QSPI_SwReset( Qspi *pQspi );
00187 
00188 void QSPI_Disable( Qspi *pQspi );
00189 
00190 void QSPI_Enable( Qspi *pQspi );
00191 
00192 QspidStatus_t QSPI_EndTransfer( Qspi *pQspi );
00193 
00194 uint32_t QSPI_GetStatus( Qspi *pQspi, const QspiStatus_t rStatus );
00195 
00196 void QSPI_ConfigureClock( Qspi *pQspi, QspiClockMode_t ClockMode, 
00197         uint32_t dwClockCfg );
00198   
00199 QspidStatus_t QSPI_SingleReadSPI( Qspid_t *pQspid, uint16_t* const pData );
00200      
00201 QspidStatus_t QSPI_MultiReadSPI( Qspid_t *pQspid, uint16_t* 
00202         const pData, uint32_t NumOfBytes );
00203        
00204 QspidStatus_t QSPI_SingleWriteSPI( Qspid_t *pQspid, uint16_t const *pData );
00205 
00206 QspidStatus_t QSPI_MultiWriteSPI( Qspid_t *pQspid, uint16_t const *pData ,
00207         uint32_t NumOfBytes );
00208 
00209 QspidStatus_t QSPI_EnableIt( Qspi *pQspi, uint32_t dwSources );
00210 
00211 QspidStatus_t QSPI_DisableIt( Qspi *pQspi, uint32_t dwSources );
00212   
00213 uint32_t QSPI_GetItMask( Qspi *pQspi );
00214      
00215 uint32_t QSPI_GetEnabledItStatus( Qspi *pQspi );
00216      
00217 QspidStatus_t QSPI_ConfigureInterface( Qspid_t *pQspid, QspiMode_t Mode, 
00218         uint32_t dwConfiguration );
00219 
00220 QspidStatus_t QSPI_SendCommand( Qspid_t *pQspi, uint8_t const KeepCfg);
00221      
00222 QspidStatus_t QSPI_SendCommandWithData( Qspid_t *pQspi, uint8_t const KeepCfg);
00223 
00224 QspidStatus_t QSPI_ReadCommand( Qspid_t *pQspi,  uint8_t const KeepCfg);
00225 
00226 QspidStatus_t QSPI_EnableMemAccess( Qspid_t *pQspi, uint8_t const KeepCfg,
00227         uint8_t ScrambleFlag);
00228 
00229 QspidStatus_t QSPI_ReadWriteMem( Qspid_t *pQspid, Access_t const ReadWrite);
00230 
00231 #ifdef __cplusplus
00232 }
00233 #endif
00234 
00235 #endif /* #ifndef _QSPI_ */
00236 
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