Data Fields | |
__IO uint32_t | PWM_CLK |
(Pwm Offset: 0x00) PWM Clock Register | |
__O uint32_t | PWM_ENA |
(Pwm Offset: 0x04) PWM Enable Register | |
__O uint32_t | PWM_DIS |
(Pwm Offset: 0x08) PWM Disable Register | |
__I uint32_t | PWM_SR |
(Pwm Offset: 0x0C) PWM Status Register | |
__O uint32_t | PWM_IER1 |
(Pwm Offset: 0x10) PWM Interrupt Enable Register 1 | |
__O uint32_t | PWM_IDR1 |
(Pwm Offset: 0x14) PWM Interrupt Disable Register 1 | |
__I uint32_t | PWM_IMR1 |
(Pwm Offset: 0x18) PWM Interrupt Mask Register 1 | |
__I uint32_t | PWM_ISR1 |
(Pwm Offset: 0x1C) PWM Interrupt Status Register 1 | |
__IO uint32_t | PWM_SCM |
(Pwm Offset: 0x20) PWM Sync Channels Mode Register | |
__O uint32_t | PWM_DMAR |
(Pwm Offset: 0x24) PWM DMA Register | |
__IO uint32_t | PWM_SCUC |
(Pwm Offset: 0x28) PWM Sync Channels Update Control Register | |
__IO uint32_t | PWM_SCUP |
(Pwm Offset: 0x2C) PWM Sync Channels Update Period Register | |
__O uint32_t | PWM_SCUPUPD |
(Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register | |
__O uint32_t | PWM_IER2 |
(Pwm Offset: 0x34) PWM Interrupt Enable Register 2 | |
__O uint32_t | PWM_IDR2 |
(Pwm Offset: 0x38) PWM Interrupt Disable Register 2 | |
__I uint32_t | PWM_IMR2 |
(Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 | |
__I uint32_t | PWM_ISR2 |
(Pwm Offset: 0x40) PWM Interrupt Status Register 2 | |
__IO uint32_t | PWM_OOV |
(Pwm Offset: 0x44) PWM Output Override Value Register | |
__IO uint32_t | PWM_OS |
(Pwm Offset: 0x48) PWM Output Selection Register | |
__O uint32_t | PWM_OSS |
(Pwm Offset: 0x4C) PWM Output Selection Set Register | |
__O uint32_t | PWM_OSC |
(Pwm Offset: 0x50) PWM Output Selection Clear Register | |
__O uint32_t | PWM_OSSUPD |
(Pwm Offset: 0x54) PWM Output Selection Set Update Register | |
__O uint32_t | PWM_OSCUPD |
(Pwm Offset: 0x58) PWM Output Selection Clear Update Register | |
__IO uint32_t | PWM_FMR |
(Pwm Offset: 0x5C) PWM Fault Mode Register | |
__I uint32_t | PWM_FSR |
(Pwm Offset: 0x60) PWM Fault Status Register | |
__O uint32_t | PWM_FCR |
(Pwm Offset: 0x64) PWM Fault Clear Register | |
__IO uint32_t | PWM_FPV1 |
(Pwm Offset: 0x68) PWM Fault Protection Value Register 1 | |
__IO uint32_t | PWM_FPE |
(Pwm Offset: 0x6C) PWM Fault Protection Enable Register | |
__I uint32_t | Reserved1 [3] |
__IO uint32_t | PWM_ELMR [8] |
(Pwm Offset: 0x7C) PWM Event Line 0 Mode Register | |
__I uint32_t | Reserved2 [1] |
__IO uint32_t | PWM_SSPR |
(Pwm Offset: 0xA0) PWM Spread Spectrum Register | |
__O uint32_t | PWM_SSPUP |
(Pwm Offset: 0xA4) PWM Spread Spectrum Update Register | |
__I uint32_t | Reserved3 [2] |
__IO uint32_t | PWM_SMMR |
(Pwm Offset: 0xB0) PWM Stepper Motor Mode Register | |
__I uint32_t | Reserved4 [3] |
__IO uint32_t | PWM_FPV2 |
(Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register | |
__I uint32_t | Reserved5 [8] |
__O uint32_t | PWM_WPCR |
(Pwm Offset: 0xE4) PWM Write Protection Control Register | |
__I uint32_t | PWM_WPSR |
(Pwm Offset: 0xE8) PWM Write Protection Status Register | |
__I uint32_t | Reserved6 [17] |
PwmCmp | PWM_CMP [PWMCMP_NUMBER] |
(Pwm Offset: 0x130) 0 .. 7 | |
__I uint32_t | Reserved7 [20] |
PwmCh_num | PWM_CH_NUM [PWMCH_NUM_NUMBER] |
(Pwm Offset: 0x200) ch_num = 0 .. 3 | |
__I uint32_t | Reserved8 [96] |
__O uint32_t | PWM_CMUPD0 |
(Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) | |
__I uint32_t | Reserved9 [7] |
__O uint32_t | PWM_CMUPD1 |
(Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) | |
__I uint32_t | Reserved10 [2] |
__IO uint32_t | PWM_ETRG1 |
(Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) | |
__IO uint32_t | PWM_LEBR1 |
(Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) | |
__I uint32_t | Reserved11 [3] |
__O uint32_t | PWM_CMUPD2 |
(Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) | |
__I uint32_t | Reserved12 [2] |
__IO uint32_t | PWM_ETRG2 |
(Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) | |
__IO uint32_t | PWM_LEBR2 |
(Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) | |
__I uint32_t | Reserved13 [3] |
__O uint32_t | PWM_CMUPD3 |
(Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) | |
__I uint32_t | Reserved14 [2] |
__IO uint32_t | PWM_ETRG3 |
(Pwm Offset: 0x46C) PWM External Trigger Register (trg_num = 3) | |
__IO uint32_t | PWM_LEBR3 |
(Pwm Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) | |
__I uint32_t | Reserved15 [6] |
__IO uint32_t | PWM_ETRG4 |
(Pwm Offset: 0x48C) PWM External Trigger Register (trg_num = 4) | |
__IO uint32_t | PWM_LEBR4 |
(Pwm Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) |
Definition at line 61 of file component_pwm.h.