00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAM_UOTGHS_COMPONENT_ 00031 #define _SAM_UOTGHS_COMPONENT_ 00032 00033 /* ============================================================================= */ 00034 /** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */ 00035 /* ============================================================================= */ 00036 /** \addtogroup SAM_UOTGHS USB On-The-Go Interface */ 00037 /*@{*/ 00038 00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00040 /** \brief UotghsDevdma hardware registers */ 00041 typedef struct { 00042 __IO uint32_t UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ 00043 __IO uint32_t UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */ 00044 __IO uint32_t UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */ 00045 __IO uint32_t UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */ 00046 } UotghsDevdma; 00047 /** \brief UotghsHstdma hardware registers */ 00048 typedef struct { 00049 __IO uint32_t UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ 00050 __IO uint32_t UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */ 00051 __IO uint32_t UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */ 00052 __IO uint32_t UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */ 00053 } UotghsHstdma; 00054 /** \brief Uotghs hardware registers */ 00055 #define UOTGHSDEVDMA_NUMBER 7 00056 #define UOTGHSHSTDMA_NUMBER 7 00057 typedef struct { 00058 __IO uint32_t UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */ 00059 __I uint32_t UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */ 00060 __O uint32_t UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */ 00061 __O uint32_t UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */ 00062 __I uint32_t UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */ 00063 __O uint32_t UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */ 00064 __O uint32_t UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */ 00065 __IO uint32_t UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */ 00066 __I uint32_t UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */ 00067 __I uint32_t Reserved1[55]; 00068 __IO uint32_t UOTGHS_DEVEPTCFG[12]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ 00069 __I uint32_t UOTGHS_DEVEPTISR[12]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */ 00070 __O uint32_t UOTGHS_DEVEPTICR[12]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ 00071 __O uint32_t UOTGHS_DEVEPTIFR[12]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */ 00072 __I uint32_t UOTGHS_DEVEPTIMR[12]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ 00073 __O uint32_t UOTGHS_DEVEPTIER[12]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ 00074 __O uint32_t UOTGHS_DEVEPTIDR[12]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ 00075 __I uint32_t Reserved2[48]; 00076 UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */ 00077 __I uint32_t Reserved3[32]; 00078 __IO uint32_t UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */ 00079 __I uint32_t UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */ 00080 __O uint32_t UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */ 00081 __O uint32_t UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */ 00082 __I uint32_t UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */ 00083 __O uint32_t UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */ 00084 __O uint32_t UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */ 00085 __IO uint32_t UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */ 00086 __IO uint32_t UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */ 00087 __IO uint32_t UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */ 00088 __IO uint32_t UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */ 00089 __IO uint32_t UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */ 00090 __I uint32_t Reserved4[52]; 00091 __IO uint32_t UOTGHS_HSTPIPCFG[12]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ 00092 __I uint32_t UOTGHS_HSTPIPISR[12]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */ 00093 __O uint32_t UOTGHS_HSTPIPICR[12]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */ 00094 __O uint32_t UOTGHS_HSTPIPIFR[12]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */ 00095 __I uint32_t UOTGHS_HSTPIPIMR[12]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ 00096 __O uint32_t UOTGHS_HSTPIPIER[12]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ 00097 __O uint32_t UOTGHS_HSTPIPIDR[12]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */ 00098 __IO uint32_t UOTGHS_HSTPIPINRQ[12]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ 00099 __IO uint32_t UOTGHS_HSTPIPERR[12]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */ 00100 __I uint32_t Reserved5[24]; 00101 UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */ 00102 __I uint32_t Reserved6[32]; 00103 __IO uint32_t UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */ 00104 __I uint32_t UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */ 00105 __O uint32_t UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */ 00106 __O uint32_t UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */ 00107 __IO uint32_t UOTGHS_TSTA1; /**< \brief (Uotghs Offset: 0x0810) General Test A1 Register */ 00108 __IO uint32_t UOTGHS_TSTA2; /**< \brief (Uotghs Offset: 0x0814) General Test A2 Register */ 00109 __I uint32_t UOTGHS_VERSION; /**< \brief (Uotghs Offset: 0x0818) General Version Register */ 00110 __I uint32_t UOTGHS_FEATURES; /**< \brief (Uotghs Offset: 0x081C) General Features Register */ 00111 __I uint32_t UOTGHS_ADDRSIZE; /**< \brief (Uotghs Offset: 0x0820) General APB Address Size Register */ 00112 __I uint32_t UOTGHS_IPNAME1; /**< \brief (Uotghs Offset: 0x0824) General Name Register 1 */ 00113 __I uint32_t UOTGHS_IPNAME2; /**< \brief (Uotghs Offset: 0x0828) General Name Register 2 */ 00114 __I uint32_t UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */ 00115 } Uotghs; 00116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00117 /* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */ 00118 #define UOTGHS_DEVCTRL_UADD_Pos 0 00119 #define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */ 00120 #define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos))) 00121 #define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */ 00122 #define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */ 00123 #define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */ 00124 #define UOTGHS_DEVCTRL_SPDCONF_Pos 10 00125 #define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */ 00126 #define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */ 00127 #define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */ 00128 #define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */ 00129 #define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */ 00130 #define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */ 00131 #define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */ 00132 #define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */ 00133 #define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */ 00134 #define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */ 00135 /* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ 00136 #define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */ 00137 #define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */ 00138 #define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */ 00139 #define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */ 00140 #define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */ 00141 #define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */ 00142 #define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */ 00143 #define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */ 00144 #define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */ 00145 #define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */ 00146 #define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */ 00147 #define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */ 00148 #define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */ 00149 #define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */ 00150 #define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */ 00151 #define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */ 00152 #define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */ 00153 #define UOTGHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVISR) Endpoint 10 Interrupt */ 00154 #define UOTGHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVISR) Endpoint 11 Interrupt */ 00155 #define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */ 00156 #define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */ 00157 #define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */ 00158 #define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */ 00159 #define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */ 00160 #define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */ 00161 #define UOTGHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVISR) DMA Channel 7 Interrupt */ 00162 /* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ 00163 #define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */ 00164 #define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */ 00165 #define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */ 00166 #define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */ 00167 #define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */ 00168 #define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */ 00169 #define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */ 00170 /* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ 00171 #define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */ 00172 #define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */ 00173 #define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */ 00174 #define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */ 00175 #define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */ 00176 #define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */ 00177 #define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */ 00178 #define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */ 00179 #define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */ 00180 #define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */ 00181 #define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */ 00182 #define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */ 00183 #define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */ 00184 #define UOTGHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIFR) DMA Channel 7 Interrupt Set */ 00185 /* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ 00186 #define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */ 00187 #define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */ 00188 #define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */ 00189 #define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */ 00190 #define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */ 00191 #define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */ 00192 #define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */ 00193 #define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */ 00194 #define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */ 00195 #define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */ 00196 #define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */ 00197 #define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */ 00198 #define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */ 00199 #define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */ 00200 #define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */ 00201 #define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */ 00202 #define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */ 00203 #define UOTGHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIMR) Endpoint 10 Interrupt Mask */ 00204 #define UOTGHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIMR) Endpoint 11 Interrupt Mask */ 00205 #define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */ 00206 #define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */ 00207 #define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */ 00208 #define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */ 00209 #define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */ 00210 #define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */ 00211 #define UOTGHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIMR) DMA Channel 7 Interrupt Mask */ 00212 /* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ 00213 #define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */ 00214 #define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */ 00215 #define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */ 00216 #define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */ 00217 #define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */ 00218 #define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */ 00219 #define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */ 00220 #define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */ 00221 #define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */ 00222 #define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */ 00223 #define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */ 00224 #define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */ 00225 #define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */ 00226 #define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */ 00227 #define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */ 00228 #define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */ 00229 #define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */ 00230 #define UOTGHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIDR) Endpoint 10 Interrupt Disable */ 00231 #define UOTGHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIDR) Endpoint 11 Interrupt Disable */ 00232 #define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */ 00233 #define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */ 00234 #define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */ 00235 #define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */ 00236 #define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */ 00237 #define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */ 00238 #define UOTGHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIDR) DMA Channel 7 Interrupt Disable */ 00239 /* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ 00240 #define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */ 00241 #define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */ 00242 #define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */ 00243 #define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */ 00244 #define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */ 00245 #define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */ 00246 #define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */ 00247 #define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */ 00248 #define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */ 00249 #define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */ 00250 #define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */ 00251 #define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */ 00252 #define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */ 00253 #define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */ 00254 #define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */ 00255 #define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */ 00256 #define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */ 00257 #define UOTGHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIER) Endpoint 10 Interrupt Enable */ 00258 #define UOTGHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIER) Endpoint 11 Interrupt Enable */ 00259 #define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */ 00260 #define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */ 00261 #define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */ 00262 #define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */ 00263 #define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */ 00264 #define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */ 00265 #define UOTGHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIER) DMA Channel 7 Interrupt Enable */ 00266 /* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */ 00267 #define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */ 00268 #define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */ 00269 #define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */ 00270 #define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */ 00271 #define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */ 00272 #define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */ 00273 #define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */ 00274 #define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */ 00275 #define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */ 00276 #define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */ 00277 #define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */ 00278 #define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */ 00279 #define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */ 00280 #define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */ 00281 #define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */ 00282 #define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */ 00283 #define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */ 00284 #define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */ 00285 /* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */ 00286 #define UOTGHS_DEVFNUM_MFNUM_Pos 0 00287 #define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */ 00288 #define UOTGHS_DEVFNUM_FNUM_Pos 3 00289 #define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */ 00290 #define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */ 00291 /* -------- UOTGHS_DEVEPTCFG[12] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ 00292 #define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Memory Allocate */ 00293 #define UOTGHS_DEVEPTCFG_EPBK_Pos 2 00294 #define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Banks */ 00295 #define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Single-bank endpoint */ 00296 #define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Double-bank endpoint */ 00297 #define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Triple-bank endpoint */ 00298 #define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4 00299 #define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Size */ 00300 #define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 8 bytes */ 00301 #define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 16 bytes */ 00302 #define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 32 bytes */ 00303 #define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 64 bytes */ 00304 #define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 128 bytes */ 00305 #define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 256 bytes */ 00306 #define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 512 bytes */ 00307 #define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 1024 bytes */ 00308 #define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Direction */ 00309 #define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is OUT. */ 00310 #define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is IN (nor for control endpoints). */ 00311 #define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[12]) Automatic Switch */ 00312 #define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11 00313 #define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Type */ 00314 #define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Control */ 00315 #define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Isochronous */ 00316 #define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Bulk */ 00317 #define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Interrupt */ 00318 #define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13 00319 #define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Number of transaction per microframe for isochronous endpoint */ 00320 #define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */ 00321 #define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) default value: one transaction per micro-frame. */ 00322 #define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */ 00323 #define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */ 00324 /* -------- UOTGHS_DEVEPTISR[12] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ 00325 #define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[12]) Transmitted IN Data Interrupt */ 00326 #define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[12]) Received OUT Data Interrupt */ 00327 #define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Received SETUP Interrupt */ 00328 #define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed OUT Interrupt */ 00329 #define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed IN Interrupt */ 00330 #define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[12]) Overflow Interrupt */ 00331 #define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) STALLed Interrupt */ 00332 #define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[12]) Short Packet Interrupt */ 00333 #define UOTGHS_DEVEPTISR_DTSEQ_Pos 8 00334 #define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Data Toggle Sequence */ 00335 #define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data0 toggle sequence */ 00336 #define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data1 toggle sequence */ 00337 #define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */ 00338 #define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */ 00339 #define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12 00340 #define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Number of Busy Banks */ 00341 #define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 0 busy bank (all banks free) */ 00342 #define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 1 busy bank */ 00343 #define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 2 busy banks */ 00344 #define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 3 busy banks */ 00345 #define UOTGHS_DEVEPTISR_CURRBK_Pos 14 00346 #define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Current Bank */ 00347 #define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank0 */ 00348 #define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank1 */ 00349 #define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank2 */ 00350 #define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[12]) Read-write Allowed */ 00351 #define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[12]) Control Direction */ 00352 #define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[12]) Configuration OK Status */ 00353 #define UOTGHS_DEVEPTISR_BYCT_Pos 20 00354 #define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Byte Count */ 00355 #define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Underflow Interrupt */ 00356 #define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Underflow Error Interrupt */ 00357 #define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Flush Interrupt */ 00358 #define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) CRC Error Interrupt */ 00359 #define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[12]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ 00360 /* -------- UOTGHS_DEVEPTICR[12] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ 00361 #define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[12]) Transmitted IN Data Interrupt Clear */ 00362 #define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[12]) Received OUT Data Interrupt Clear */ 00363 #define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Received SETUP Interrupt Clear */ 00364 #define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed OUT Interrupt Clear */ 00365 #define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed IN Interrupt Clear */ 00366 #define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[12]) Overflow Interrupt Clear */ 00367 #define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) STALLed Interrupt Clear */ 00368 #define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[12]) Short Packet Interrupt Clear */ 00369 #define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Underflow Interrupt Clear */ 00370 #define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) High bandwidth isochronous IN Underflow Error Interrupt Clear */ 00371 #define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */ 00372 #define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) CRC Error Interrupt Clear */ 00373 /* -------- UOTGHS_DEVEPTIFR[12] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ 00374 #define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[12]) Transmitted IN Data Interrupt Set */ 00375 #define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received OUT Data Interrupt Set */ 00376 #define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received SETUP Interrupt Set */ 00377 #define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed OUT Interrupt Set */ 00378 #define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed IN Interrupt Set */ 00379 #define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[12]) Overflow Interrupt Set */ 00380 #define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) STALLed Interrupt Set */ 00381 #define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[12]) Short Packet Interrupt Set */ 00382 #define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[12]) Number of Busy Banks Interrupt Set */ 00383 #define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Underflow Interrupt Set */ 00384 #define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) High bandwidth isochronous IN Underflow Error Interrupt Set */ 00385 #define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) High Bandwidth Isochronous IN Flush Interrupt Set */ 00386 #define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) CRC Error Interrupt Set */ 00387 /* -------- UOTGHS_DEVEPTIMR[12] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ 00388 #define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transmitted IN Data Interrupt */ 00389 #define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received OUT Data Interrupt */ 00390 #define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received SETUP Interrupt */ 00391 #define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed OUT Interrupt */ 00392 #define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed IN Interrupt */ 00393 #define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[12]) Overflow Interrupt */ 00394 #define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALLed Interrupt */ 00395 #define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[12]) Short Packet Interrupt */ 00396 #define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[12]) Number of Busy Banks Interrupt */ 00397 #define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[12]) Kill IN Bank */ 00398 #define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[12]) FIFO Control */ 00399 #define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[12]) Endpoint Interrupts Disable HDMA Request */ 00400 #define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[12]) NYET Token Disable */ 00401 #define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[12]) Reset Data Toggle */ 00402 #define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALL Request */ 00403 #define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Underflow Interrupt */ 00404 #define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Error Interrupt */ 00405 #define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Flush Interrupt */ 00406 #define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) CRC Error Interrupt */ 00407 #define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[12]) MData Interrupt */ 00408 #define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[12]) DataX Interrupt */ 00409 #define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transaction Error Interrupt */ 00410 /* -------- UOTGHS_DEVEPTIER[12] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ 00411 #define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[12]) Transmitted IN Data Interrupt Enable */ 00412 #define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[12]) Received OUT Data Interrupt Enable */ 00413 #define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Received SETUP Interrupt Enable */ 00414 #define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed OUT Interrupt Enable */ 00415 #define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed IN Interrupt Enable */ 00416 #define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[12]) Overflow Interrupt Enable */ 00417 #define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) STALLed Interrupt Enable */ 00418 #define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[12]) Short Packet Interrupt Enable */ 00419 #define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[12]) Number of Busy Banks Interrupt Enable */ 00420 #define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[12]) Kill IN Bank */ 00421 #define UOTGHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIER[12]) FIFO Control */ 00422 #define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[12]) Endpoint Interrupts Disable HDMA Request Enable */ 00423 #define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[12]) NYET Token Disable Enable */ 00424 #define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[12]) Reset Data Toggle Enable */ 00425 #define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[12]) STALL Request Enable */ 00426 #define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Underflow Interrupt Enable */ 00427 #define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Error Interrupt Enable */ 00428 #define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Flush Interrupt Enable */ 00429 #define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) CRC Error Interrupt Enable */ 00430 #define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[12]) MData Interrupt Enable */ 00431 #define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[12]) DataX Interrupt Enable */ 00432 #define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[12]) Transaction Error Interrupt Enable */ 00433 /* -------- UOTGHS_DEVEPTIDR[12] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ 00434 #define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transmitted IN Interrupt Clear */ 00435 #define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received OUT Data Interrupt Clear */ 00436 #define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received SETUP Interrupt Clear */ 00437 #define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed OUT Interrupt Clear */ 00438 #define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed IN Interrupt Clear */ 00439 #define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[12]) Overflow Interrupt Clear */ 00440 #define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALLed Interrupt Clear */ 00441 #define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[12]) Shortpacket Interrupt Clear */ 00442 #define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[12]) Number of Busy Banks Interrupt Clear */ 00443 #define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[12]) FIFO Control Clear */ 00444 #define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[12]) Endpoint Interrupts Disable HDMA Request Clear */ 00445 #define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[12]) NYET Token Disable Clear */ 00446 #define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALL Request Clear */ 00447 #define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Underflow Interrupt Clear */ 00448 #define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Error Interrupt Clear */ 00449 #define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */ 00450 #define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) CRC Error Interrupt Clear */ 00451 #define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[12]) MData Interrupt Clear */ 00452 #define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[12]) DataX Interrupt Clear */ 00453 #define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transaction Error Interrupt Clear */ 00454 /* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ 00455 #define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 00456 #define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */ 00457 #define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) 00458 /* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */ 00459 #define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 00460 #define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */ 00461 #define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos))) 00462 /* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */ 00463 #define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */ 00464 #define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ 00465 #define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */ 00466 #define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */ 00467 #define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ 00468 #define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ 00469 #define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ 00470 #define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */ 00471 #define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 00472 #define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ 00473 #define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) 00474 /* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */ 00475 #define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */ 00476 #define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */ 00477 #define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */ 00478 #define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */ 00479 #define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */ 00480 #define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 00481 #define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */ 00482 #define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos))) 00483 /* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */ 00484 #define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */ 00485 #define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */ 00486 #define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */ 00487 #define UOTGHS_HSTCTRL_SPDCONF_Pos 12 00488 #define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */ 00489 #define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */ 00490 #define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */ 00491 #define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */ 00492 #define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */ 00493 /* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ 00494 #define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */ 00495 #define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */ 00496 #define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */ 00497 #define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */ 00498 #define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */ 00499 #define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */ 00500 #define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */ 00501 #define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */ 00502 #define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */ 00503 #define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */ 00504 #define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */ 00505 #define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */ 00506 #define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */ 00507 #define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */ 00508 #define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */ 00509 #define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */ 00510 #define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */ 00511 #define UOTGHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTISR) Pipe 10 Interrupt */ 00512 #define UOTGHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTISR) Pipe 11 Interrupt */ 00513 #define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */ 00514 #define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */ 00515 #define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */ 00516 #define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */ 00517 #define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */ 00518 #define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */ 00519 #define UOTGHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTISR) DMA Channel 7 Interrupt */ 00520 /* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ 00521 #define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */ 00522 #define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */ 00523 #define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */ 00524 #define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */ 00525 #define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */ 00526 #define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */ 00527 #define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */ 00528 /* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ 00529 #define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */ 00530 #define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */ 00531 #define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */ 00532 #define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */ 00533 #define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */ 00534 #define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */ 00535 #define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */ 00536 #define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */ 00537 #define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */ 00538 #define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */ 00539 #define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */ 00540 #define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */ 00541 #define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */ 00542 #define UOTGHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIFR) DMA Channel 7 Interrupt Set */ 00543 /* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ 00544 #define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */ 00545 #define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */ 00546 #define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */ 00547 #define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ 00548 #define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */ 00549 #define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */ 00550 #define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */ 00551 #define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */ 00552 #define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */ 00553 #define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */ 00554 #define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */ 00555 #define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */ 00556 #define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */ 00557 #define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */ 00558 #define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */ 00559 #define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */ 00560 #define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */ 00561 #define UOTGHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIMR) Pipe 10 Interrupt Enable */ 00562 #define UOTGHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIMR) Pipe 11 Interrupt Enable */ 00563 #define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */ 00564 #define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */ 00565 #define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */ 00566 #define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */ 00567 #define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */ 00568 #define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */ 00569 #define UOTGHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIMR) DMA Channel 7 Interrupt Enable */ 00570 /* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ 00571 #define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */ 00572 #define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */ 00573 #define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */ 00574 #define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ 00575 #define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */ 00576 #define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */ 00577 #define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */ 00578 #define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */ 00579 #define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */ 00580 #define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */ 00581 #define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */ 00582 #define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */ 00583 #define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */ 00584 #define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */ 00585 #define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */ 00586 #define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */ 00587 #define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */ 00588 #define UOTGHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIDR) Pipe 10 Interrupt Disable */ 00589 #define UOTGHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIDR) Pipe 11 Interrupt Disable */ 00590 #define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */ 00591 #define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */ 00592 #define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */ 00593 #define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */ 00594 #define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */ 00595 #define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */ 00596 #define UOTGHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIDR) DMA Channel 7 Interrupt Disable */ 00597 /* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ 00598 #define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */ 00599 #define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */ 00600 #define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */ 00601 #define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */ 00602 #define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */ 00603 #define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */ 00604 #define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */ 00605 #define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */ 00606 #define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */ 00607 #define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */ 00608 #define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */ 00609 #define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */ 00610 #define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */ 00611 #define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */ 00612 #define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */ 00613 #define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */ 00614 #define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */ 00615 #define UOTGHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIER) Pipe 10 Interrupt Enable */ 00616 #define UOTGHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIER) Pipe 11 Interrupt Enable */ 00617 #define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */ 00618 #define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */ 00619 #define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */ 00620 #define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */ 00621 #define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */ 00622 #define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */ 00623 #define UOTGHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIER) DMA Channel 7 Interrupt Enable */ 00624 /* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */ 00625 #define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */ 00626 #define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */ 00627 #define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */ 00628 #define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */ 00629 #define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */ 00630 #define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */ 00631 #define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */ 00632 #define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */ 00633 #define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */ 00634 #define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */ 00635 #define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */ 00636 #define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */ 00637 #define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */ 00638 #define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */ 00639 #define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */ 00640 #define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */ 00641 #define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */ 00642 #define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */ 00643 /* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */ 00644 #define UOTGHS_HSTFNUM_MFNUM_Pos 0 00645 #define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */ 00646 #define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos))) 00647 #define UOTGHS_HSTFNUM_FNUM_Pos 3 00648 #define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */ 00649 #define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos))) 00650 #define UOTGHS_HSTFNUM_FLENHIGH_Pos 16 00651 #define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */ 00652 #define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos))) 00653 /* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */ 00654 #define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0 00655 #define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ 00656 #define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos))) 00657 #define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8 00658 #define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ 00659 #define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos))) 00660 #define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16 00661 #define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ 00662 #define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos))) 00663 #define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24 00664 #define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ 00665 #define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos))) 00666 /* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */ 00667 #define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0 00668 #define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ 00669 #define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos))) 00670 #define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8 00671 #define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ 00672 #define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos))) 00673 #define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16 00674 #define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ 00675 #define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos))) 00676 #define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24 00677 #define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ 00678 #define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos))) 00679 /* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */ 00680 #define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0 00681 #define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ 00682 #define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos))) 00683 #define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8 00684 #define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ 00685 #define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos))) 00686 /* -------- UOTGHS_HSTPIPCFG[12] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ 00687 #define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Memory Allocate */ 00688 #define UOTGHS_HSTPIPCFG_PBK_Pos 2 00689 #define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Banks */ 00690 #define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Single-bank pipe */ 00691 #define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Double-bank pipe */ 00692 #define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Triple-bank pipe */ 00693 #define UOTGHS_HSTPIPCFG_PSIZE_Pos 4 00694 #define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Size */ 00695 #define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 8 bytes */ 00696 #define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 16 bytes */ 00697 #define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 32 bytes */ 00698 #define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 64 bytes */ 00699 #define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 128 bytes */ 00700 #define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 256 bytes */ 00701 #define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 512 bytes */ 00702 #define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 1024 bytes */ 00703 #define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8 00704 #define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Token */ 00705 #define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) SETUP */ 00706 #define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) IN */ 00707 #define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) OUT */ 00708 #define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[12]) Automatic Switch */ 00709 #define UOTGHS_HSTPIPCFG_PTYPE_Pos 12 00710 #define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Type */ 00711 #define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Control */ 00712 #define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Isochronous */ 00713 #define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Bulk */ 00714 #define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Interrupt */ 00715 #define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16 00716 #define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Endpoint Number */ 00717 #define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos))) 00718 #define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24 00719 #define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Interrupt Request Frequency */ 00720 #define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos))) 00721 #define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[12]) Ping Enable */ 00722 #define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24 00723 #define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Binterval Parameter for the Bulk-Out/Ping Transaction */ 00724 #define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos))) 00725 /* -------- UOTGHS_HSTPIPISR[12] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ 00726 #define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[12]) Received IN Data Interrupt */ 00727 #define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted OUT Data Interrupt */ 00728 #define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted SETUP Interrupt */ 00729 #define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Error Interrupt */ 00730 #define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[12]) NAKed Interrupt */ 00731 #define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[12]) Overflow Interrupt */ 00732 #define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) Received STALLed Interrupt */ 00733 #define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[12]) Short Packet Interrupt */ 00734 #define UOTGHS_HSTPIPISR_DTSEQ_Pos 8 00735 #define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Data Toggle Sequence */ 00736 #define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data0 toggle sequence */ 00737 #define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data1 toggle sequence */ 00738 #define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12 00739 #define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Number of Busy Banks */ 00740 #define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 0 busy bank (all banks free) */ 00741 #define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 1 busy bank */ 00742 #define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 2 busy banks */ 00743 #define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 3 busy banks */ 00744 #define UOTGHS_HSTPIPISR_CURRBK_Pos 14 00745 #define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Current Bank */ 00746 #define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank0 */ 00747 #define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank1 */ 00748 #define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank2 */ 00749 #define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[12]) Read-write Allowed */ 00750 #define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[12]) Configuration OK Status */ 00751 #define UOTGHS_HSTPIPISR_PBYCT_Pos 20 00752 #define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Byte Count */ 00753 #define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Underflow Interrupt */ 00754 #define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) CRC Error Interrupt */ 00755 /* -------- UOTGHS_HSTPIPICR[12] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ 00756 #define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[12]) Received IN Data Interrupt Clear */ 00757 #define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted OUT Data Interrupt Clear */ 00758 #define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted SETUP Interrupt Clear */ 00759 #define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[12]) NAKed Interrupt Clear */ 00760 #define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[12]) Overflow Interrupt Clear */ 00761 #define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) Received STALLed Interrupt Clear */ 00762 #define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[12]) Short Packet Interrupt Clear */ 00763 #define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Underflow Interrupt Clear */ 00764 #define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) CRC Error Interrupt Clear */ 00765 /* -------- UOTGHS_HSTPIPIFR[12] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ 00766 #define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received IN Data Interrupt Set */ 00767 #define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted OUT Data Interrupt Set */ 00768 #define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted SETUP Interrupt Set */ 00769 #define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[12]) Pipe Error Interrupt Set */ 00770 #define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[12]) NAKed Interrupt Set */ 00771 #define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[12]) Overflow Interrupt Set */ 00772 #define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received STALLed Interrupt Set */ 00773 #define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[12]) Short Packet Interrupt Set */ 00774 #define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[12]) Number of Busy Banks Set */ 00775 #define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Underflow Interrupt Set */ 00776 #define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) CRC Error Interrupt Set */ 00777 /* -------- UOTGHS_HSTPIPIMR[12] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ 00778 #define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received IN Data Interrupt Enable */ 00779 #define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted OUT Data Interrupt Enable */ 00780 #define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted SETUP Interrupt Enable */ 00781 #define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Error Interrupt Enable */ 00782 #define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[12]) NAKed Interrupt Enable */ 00783 #define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[12]) Overflow Interrupt Enable */ 00784 #define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received STALLed Interrupt Enable */ 00785 #define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[12]) Short Packet Interrupt Enable */ 00786 #define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[12]) Number of Busy Banks Interrupt Enable */ 00787 #define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[12]) FIFO Control */ 00788 #define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Interrupts Disable HDMA Request Enable */ 00789 #define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Freeze */ 00790 #define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[12]) Reset Data Toggle */ 00791 #define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Underflow Interrupt Enable */ 00792 #define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) CRC Error Interrupt Enable */ 00793 /* -------- UOTGHS_HSTPIPIER[12] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ 00794 #define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[12]) Received IN Data Interrupt Enable */ 00795 #define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted OUT Data Interrupt Enable */ 00796 #define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted SETUP Interrupt Enable */ 00797 #define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Error Interrupt Enable */ 00798 #define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[12]) NAKed Interrupt Enable */ 00799 #define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[12]) Overflow Interrupt Enable */ 00800 #define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) Received STALLed Interrupt Enable */ 00801 #define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[12]) Short Packet Interrupt Enable */ 00802 #define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[12]) Number of Busy Banks Enable */ 00803 #define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Interrupts Disable HDMA Request Enable */ 00804 #define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Freeze Enable */ 00805 #define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[12]) Reset Data Toggle Enable */ 00806 #define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Underflow Interrupt Enable */ 00807 #define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) CRC Error Interrupt Enable */ 00808 /* -------- UOTGHS_HSTPIPIDR[12] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ 00809 #define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received IN Data Interrupt Disable */ 00810 #define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted OUT Data Interrupt Disable */ 00811 #define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted SETUP Interrupt Disable */ 00812 #define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Error Interrupt Disable */ 00813 #define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[12]) NAKed Interrupt Disable */ 00814 #define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[12]) Overflow Interrupt Disable */ 00815 #define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received STALLed Interrupt Disable */ 00816 #define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[12]) Short Packet Interrupt Disable */ 00817 #define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[12]) Number of Busy Banks Disable */ 00818 #define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[12]) FIFO Control Disable */ 00819 #define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Interrupts Disable HDMA Request Disable */ 00820 #define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Freeze Disable */ 00821 #define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Underflow Interrupt Disable */ 00822 #define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) CRC Error Interrupt Disable */ 00823 /* -------- UOTGHS_HSTPIPINRQ[12] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ 00824 #define UOTGHS_HSTPIPINRQ_INRQ_Pos 0 00825 #define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Number before Freeze */ 00826 #define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos))) 00827 #define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Mode */ 00828 /* -------- UOTGHS_HSTPIPERR[12] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ 00829 #define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[12]) Data Toggle Error */ 00830 #define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[12]) Data PID Error */ 00831 #define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[12]) PID Error */ 00832 #define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[12]) Time-Out Error */ 00833 #define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[12]) CRC16 Error */ 00834 #define UOTGHS_HSTPIPERR_COUNTER_Pos 5 00835 #define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[12]) Error Counter */ 00836 #define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos))) 00837 /* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ 00838 #define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 00839 #define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */ 00840 #define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) 00841 /* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */ 00842 #define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 00843 #define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */ 00844 #define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos))) 00845 /* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */ 00846 #define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */ 00847 #define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ 00848 #define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */ 00849 #define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */ 00850 #define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ 00851 #define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ 00852 #define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ 00853 #define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */ 00854 #define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 00855 #define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ 00856 #define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) 00857 /* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */ 00858 #define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */ 00859 #define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */ 00860 #define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */ 00861 #define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */ 00862 #define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */ 00863 #define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 00864 #define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */ 00865 #define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos))) 00866 /* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */ 00867 #define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */ 00868 #define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */ 00869 #define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */ 00870 #define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */ 00871 #define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */ 00872 #define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */ 00873 #define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */ 00874 #define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */ 00875 #define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */ 00876 #define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */ 00877 #define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */ 00878 #define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */ 00879 #define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */ 00880 #define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */ 00881 #define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */ 00882 #define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */ 00883 #define UOTGHS_CTRL_TIMVALUE_Pos 16 00884 #define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */ 00885 #define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos))) 00886 #define UOTGHS_CTRL_TIMPAGE_Pos 20 00887 #define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */ 00888 #define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos))) 00889 #define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */ 00890 #define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */ 00891 #define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */ 00892 #define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */ 00893 #define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */ 00894 #define UOTGHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */ 00895 #define UOTGHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */ 00896 /* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */ 00897 #define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */ 00898 #define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */ 00899 #define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */ 00900 #define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */ 00901 #define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */ 00902 #define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */ 00903 #define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */ 00904 #define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */ 00905 #define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */ 00906 #define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */ 00907 #define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */ 00908 #define UOTGHS_SR_SPEED_Pos 12 00909 #define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */ 00910 #define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */ 00911 #define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */ 00912 #define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */ 00913 #define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */ 00914 /* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */ 00915 #define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */ 00916 #define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */ 00917 #define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */ 00918 #define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */ 00919 #define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */ 00920 #define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */ 00921 #define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */ 00922 #define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */ 00923 #define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */ 00924 /* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */ 00925 #define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */ 00926 #define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */ 00927 #define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */ 00928 #define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */ 00929 #define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */ 00930 #define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */ 00931 #define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */ 00932 #define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */ 00933 #define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */ 00934 /* -------- UOTGHS_TSTA1 : (UOTGHS Offset: 0x0810) General Test A1 Register -------- */ 00935 #define UOTGHS_TSTA1_CounterA_Pos 0 00936 #define UOTGHS_TSTA1_CounterA_Msk (0x7fffu << UOTGHS_TSTA1_CounterA_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterA */ 00937 #define UOTGHS_TSTA1_CounterA(value) ((UOTGHS_TSTA1_CounterA_Msk & ((value) << UOTGHS_TSTA1_CounterA_Pos))) 00938 #define UOTGHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (UOTGHS_TSTA1) Load CounterA */ 00939 #define UOTGHS_TSTA1_CounterB_Pos 16 00940 #define UOTGHS_TSTA1_CounterB_Msk (0x3fu << UOTGHS_TSTA1_CounterB_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterB */ 00941 #define UOTGHS_TSTA1_CounterB(value) ((UOTGHS_TSTA1_CounterB_Msk & ((value) << UOTGHS_TSTA1_CounterB_Pos))) 00942 #define UOTGHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (UOTGHS_TSTA1) Load CounterB */ 00943 #define UOTGHS_TSTA1_SOFCntMa1_Pos 24 00944 #define UOTGHS_TSTA1_SOFCntMa1_Msk (0x7fu << UOTGHS_TSTA1_SOFCntMa1_Pos) /**< \brief (UOTGHS_TSTA1) SOF Counter Max */ 00945 #define UOTGHS_TSTA1_SOFCntMa1(value) ((UOTGHS_TSTA1_SOFCntMa1_Msk & ((value) << UOTGHS_TSTA1_SOFCntMa1_Pos))) 00946 #define UOTGHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (UOTGHS_TSTA1) Load SOF Counter */ 00947 /* -------- UOTGHS_TSTA2 : (UOTGHS Offset: 0x0814) General Test A2 Register -------- */ 00948 #define UOTGHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (UOTGHS_TSTA2) Full Detach Enable */ 00949 #define UOTGHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (UOTGHS_TSTA2) HS Serial Mode */ 00950 #define UOTGHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (UOTGHS_TSTA2) Loop-back Mode */ 00951 #define UOTGHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (UOTGHS_TSTA2) Disable Gated Clock */ 00952 #define UOTGHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (UOTGHS_TSTA2) Force SuspendM to 1 */ 00953 #define UOTGHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (UOTGHS_TSTA2) Bypass DPLL */ 00954 #define UOTGHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (UOTGHS_TSTA2) Host HS Disconnect Disable */ 00955 #define UOTGHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (UOTGHS_TSTA2) Force HS Reset to 50 ms */ 00956 #define UOTGHS_TSTA2_UTMIReset (0x1u << 8) /**< \brief (UOTGHS_TSTA2) UTMI Reset */ 00957 #define UOTGHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (UOTGHS_TSTA2) Remove Pull-up When TX */ 00958 /* -------- UOTGHS_VERSION : (UOTGHS Offset: 0x0818) General Version Register -------- */ 00959 #define UOTGHS_VERSION_VERSION_Pos 0 00960 #define UOTGHS_VERSION_VERSION_Msk (0xfffu << UOTGHS_VERSION_VERSION_Pos) /**< \brief (UOTGHS_VERSION) Version Number */ 00961 #define UOTGHS_VERSION_VARIANT_Pos 16 00962 #define UOTGHS_VERSION_VARIANT_Msk (0xfu << UOTGHS_VERSION_VARIANT_Pos) /**< \brief (UOTGHS_VERSION) Variant Number */ 00963 /* -------- UOTGHS_FEATURES : (UOTGHS Offset: 0x081C) General Features Register -------- */ 00964 #define UOTGHS_FEATURES_EPTNBRMAX_Pos 0 00965 #define UOTGHS_FEATURES_EPTNBRMAX_Msk (0xfu << UOTGHS_FEATURES_EPTNBRMAX_Pos) /**< \brief (UOTGHS_FEATURES) Maximal Number of Pipes/Endpoints */ 00966 #define UOTGHS_FEATURES_EPTNBRMAX_16_P_E (0x0u << 0) /**< \brief (UOTGHS_FEATURES) 16 pipes/endpoints */ 00967 #define UOTGHS_FEATURES_EPTNBRMAX_1_P_E (0x1u << 0) /**< \brief (UOTGHS_FEATURES) 1 pipe/endpoint */ 00968 #define UOTGHS_FEATURES_EPTNBRMAX_2_P_E (0x2u << 0) /**< \brief (UOTGHS_FEATURES) 2 pipes/endpoints */ 00969 #define UOTGHS_FEATURES_EPTNBRMAX_15_P_E (0xFu << 0) /**< \brief (UOTGHS_FEATURES) 15 pipes/endpoints */ 00970 #define UOTGHS_FEATURES_DMACHANNELNBR_Pos 4 00971 #define UOTGHS_FEATURES_DMACHANNELNBR_Msk (0x7u << UOTGHS_FEATURES_DMACHANNELNBR_Pos) /**< \brief (UOTGHS_FEATURES) Number of DMA Channels */ 00972 #define UOTGHS_FEATURES_DMACHANNELNBR_1_DMA_CH (0x1u << 4) /**< \brief (UOTGHS_FEATURES) 1 DMA channel */ 00973 #define UOTGHS_FEATURES_DMACHANNELNBR_2_DMA_CH (0x2u << 4) /**< \brief (UOTGHS_FEATURES) 2 DMA channels */ 00974 #define UOTGHS_FEATURES_DMACHANNELNBR_7_DMA_CH (0x7u << 4) /**< \brief (UOTGHS_FEATURES) 7 DMA channels */ 00975 #define UOTGHS_FEATURES_DMABUFFERSIZE (0x1u << 7) /**< \brief (UOTGHS_FEATURES) DMA Buffer Size */ 00976 #define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos 8 00977 #define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Msk (0xfu << UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos) /**< \brief (UOTGHS_FEATURES) DMA FIFO Depth in Words */ 00978 #define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_16_DMA_F_D (0x0u << 8) /**< \brief (UOTGHS_FEATURES) 16 DMA FIFO depth */ 00979 #define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_1_DMA_F_D (0x1u << 8) /**< \brief (UOTGHS_FEATURES) 1 DMA FIFO depth */ 00980 #define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_2_DMA_F_D (0x2u << 8) /**< \brief (UOTGHS_FEATURES) 2 DMA FIFO depth */ 00981 #define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_15_DMA_F_D (0xFu << 8) /**< \brief (UOTGHS_FEATURES) 15 DMA FIFO depth */ 00982 #define UOTGHS_FEATURES_FIFOMAXSIZE_Pos 12 00983 #define UOTGHS_FEATURES_FIFOMAXSIZE_Msk (0x7u << UOTGHS_FEATURES_FIFOMAXSIZE_Pos) /**< \brief (UOTGHS_FEATURES) Maximal FIFO Size */ 00984 #define UOTGHS_FEATURES_FIFOMAXSIZE_256_BYTE (0x0u << 12) /**< \brief (UOTGHS_FEATURES) < 256 bytes */ 00985 #define UOTGHS_FEATURES_FIFOMAXSIZE_512_BYTE (0x1u << 12) /**< \brief (UOTGHS_FEATURES) < 512 bytes */ 00986 #define UOTGHS_FEATURES_FIFOMAXSIZE_1024_BYTE (0x2u << 12) /**< \brief (UOTGHS_FEATURES) < 1024 bytes */ 00987 #define UOTGHS_FEATURES_FIFOMAXSIZE_2048_BYTE (0x3u << 12) /**< \brief (UOTGHS_FEATURES) < 2048 bytes */ 00988 #define UOTGHS_FEATURES_FIFOMAXSIZE_4096_BYTE (0x4u << 12) /**< \brief (UOTGHS_FEATURES) < 4096 bytes */ 00989 #define UOTGHS_FEATURES_FIFOMAXSIZE_8192_BYTE (0x5u << 12) /**< \brief (UOTGHS_FEATURES) < 8192 bytes */ 00990 #define UOTGHS_FEATURES_FIFOMAXSIZE_16384_BYTE (0x6u << 12) /**< \brief (UOTGHS_FEATURES) < 16384 bytes */ 00991 #define UOTGHS_FEATURES_FIFOMAXSIZE_P16384_BYTE (0x7u << 12) /**< \brief (UOTGHS_FEATURES) >= 16384 bytes */ 00992 #define UOTGHS_FEATURES_BYTEWRITEDPRAM (0x1u << 15) /**< \brief (UOTGHS_FEATURES) DPRAM Byte-Write Capability */ 00993 #define UOTGHS_FEATURES_DATABUS (0x1u << 16) /**< \brief (UOTGHS_FEATURES) Data Bus 16-8 */ 00994 #define UOTGHS_FEATURES_ENHBISO1 (0x1u << 17) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 1 */ 00995 #define UOTGHS_FEATURES_ENHBISO2 (0x1u << 18) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 2 */ 00996 #define UOTGHS_FEATURES_ENHBISO3 (0x1u << 19) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 3 */ 00997 #define UOTGHS_FEATURES_ENHBISO4 (0x1u << 20) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 4 */ 00998 #define UOTGHS_FEATURES_ENHBISO5 (0x1u << 21) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 5 */ 00999 #define UOTGHS_FEATURES_ENHBISO6 (0x1u << 22) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 6 */ 01000 #define UOTGHS_FEATURES_ENHBISO7 (0x1u << 23) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 7 */ 01001 /* -------- UOTGHS_ADDRSIZE : (UOTGHS Offset: 0x0820) General APB Address Size Register -------- */ 01002 #define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos 0 01003 #define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Msk (0xffffffffu << UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos) /**< \brief (UOTGHS_ADDRSIZE) IP APB Address Size */ 01004 /* -------- UOTGHS_IPNAME1 : (UOTGHS Offset: 0x0824) General Name Register 1 -------- */ 01005 #define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos 0 01006 #define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Msk (0xffffffffu << UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos) /**< \brief (UOTGHS_IPNAME1) IP Name Part One */ 01007 /* -------- UOTGHS_IPNAME2 : (UOTGHS Offset: 0x0828) General Name Register 2 -------- */ 01008 #define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos 0 01009 #define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Msk (0xffffffffu << UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos) /**< \brief (UOTGHS_IPNAME2) IP Name Part Two */ 01010 /* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */ 01011 #define UOTGHS_FSM_DRDSTATE_Pos 0 01012 #define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) Dual Role Device State */ 01013 #define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ 01014 #define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ 01015 #define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ 01016 #define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */ 01017 #define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */ 01018 #define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */ 01019 #define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ 01020 #define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ 01021 #define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ 01022 #define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */ 01023 #define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */ 01024 #define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ 01025 #define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */ 01026 #define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ 01027 #define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */ 01028 #define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ 01029 01030 /*@}*/ 01031 01032 01033 #endif /* _SAM_UOTGHS_COMPONENT_ */