SAMV71 Xplained Ultra Software Package 1.4

instance_pwm0.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2014, Atmel Corporation                                        */
00006 /*                                                                              */
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00008 /*                                                                              */
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00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_PWM0_INSTANCE_
00031 #define _SAMV71_PWM0_INSTANCE_
00032 
00033 /* ========== Register definition for PWM0 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_PWM0_CLK                       (0x40020000U) /**< \brief (PWM0) PWM Clock Register */
00036   #define REG_PWM0_ENA                       (0x40020004U) /**< \brief (PWM0) PWM Enable Register */
00037   #define REG_PWM0_DIS                       (0x40020008U) /**< \brief (PWM0) PWM Disable Register */
00038   #define REG_PWM0_SR                        (0x4002000CU) /**< \brief (PWM0) PWM Status Register */
00039   #define REG_PWM0_IER1                      (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
00040   #define REG_PWM0_IDR1                      (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
00041   #define REG_PWM0_IMR1                      (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
00042   #define REG_PWM0_ISR1                      (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
00043   #define REG_PWM0_SCM                       (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
00044   #define REG_PWM0_DMAR                      (0x40020024U) /**< \brief (PWM0) PWM DMA Register */
00045   #define REG_PWM0_SCUC                      (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
00046   #define REG_PWM0_SCUP                      (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
00047   #define REG_PWM0_SCUPUPD                   (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
00048   #define REG_PWM0_IER2                      (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
00049   #define REG_PWM0_IDR2                      (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
00050   #define REG_PWM0_IMR2                      (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
00051   #define REG_PWM0_ISR2                      (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
00052   #define REG_PWM0_OOV                       (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
00053   #define REG_PWM0_OS                        (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
00054   #define REG_PWM0_OSS                       (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
00055   #define REG_PWM0_OSC                       (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
00056   #define REG_PWM0_OSSUPD                    (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
00057   #define REG_PWM0_OSCUPD                    (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
00058   #define REG_PWM0_FMR                       (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
00059   #define REG_PWM0_FSR                       (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
00060   #define REG_PWM0_FCR                       (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
00061   #define REG_PWM0_FPV1                      (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
00062   #define REG_PWM0_FPE                       (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
00063   #define REG_PWM0_ELMR                      (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
00064   #define REG_PWM0_SSPR                      (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
00065   #define REG_PWM0_SSPUP                     (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
00066   #define REG_PWM0_SMMR                      (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
00067   #define REG_PWM0_FPV2                      (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
00068   #define REG_PWM0_WPCR                      (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
00069   #define REG_PWM0_WPSR                      (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
00070   #define REG_PWM0_CMPV0                     (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
00071   #define REG_PWM0_CMPVUPD0                  (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
00072   #define REG_PWM0_CMPM0                     (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
00073   #define REG_PWM0_CMPMUPD0                  (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
00074   #define REG_PWM0_CMPV1                     (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
00075   #define REG_PWM0_CMPVUPD1                  (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
00076   #define REG_PWM0_CMPM1                     (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
00077   #define REG_PWM0_CMPMUPD1                  (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
00078   #define REG_PWM0_CMPV2                     (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
00079   #define REG_PWM0_CMPVUPD2                  (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
00080   #define REG_PWM0_CMPM2                     (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
00081   #define REG_PWM0_CMPMUPD2                  (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
00082   #define REG_PWM0_CMPV3                     (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
00083   #define REG_PWM0_CMPVUPD3                  (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
00084   #define REG_PWM0_CMPM3                     (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
00085   #define REG_PWM0_CMPMUPD3                  (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
00086   #define REG_PWM0_CMPV4                     (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
00087   #define REG_PWM0_CMPVUPD4                  (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
00088   #define REG_PWM0_CMPM4                     (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
00089   #define REG_PWM0_CMPMUPD4                  (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
00090   #define REG_PWM0_CMPV5                     (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
00091   #define REG_PWM0_CMPVUPD5                  (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
00092   #define REG_PWM0_CMPM5                     (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
00093   #define REG_PWM0_CMPMUPD5                  (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
00094   #define REG_PWM0_CMPV6                     (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
00095   #define REG_PWM0_CMPVUPD6                  (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
00096   #define REG_PWM0_CMPM6                     (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
00097   #define REG_PWM0_CMPMUPD6                  (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
00098   #define REG_PWM0_CMPV7                     (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
00099   #define REG_PWM0_CMPVUPD7                  (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
00100   #define REG_PWM0_CMPM7                     (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
00101   #define REG_PWM0_CMPMUPD7                  (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
00102   #define REG_PWM0_CMR0                      (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
00103   #define REG_PWM0_CDTY0                     (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
00104   #define REG_PWM0_CDTYUPD0                  (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
00105   #define REG_PWM0_CPRD0                     (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
00106   #define REG_PWM0_CPRDUPD0                  (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
00107   #define REG_PWM0_CCNT0                     (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
00108   #define REG_PWM0_DT0                       (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
00109   #define REG_PWM0_DTUPD0                    (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
00110   #define REG_PWM0_CMR1                      (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
00111   #define REG_PWM0_CDTY1                     (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
00112   #define REG_PWM0_CDTYUPD1                  (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
00113   #define REG_PWM0_CPRD1                     (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
00114   #define REG_PWM0_CPRDUPD1                  (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
00115   #define REG_PWM0_CCNT1                     (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
00116   #define REG_PWM0_DT1                       (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
00117   #define REG_PWM0_DTUPD1                    (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
00118   #define REG_PWM0_CMR2                      (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
00119   #define REG_PWM0_CDTY2                     (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
00120   #define REG_PWM0_CDTYUPD2                  (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
00121   #define REG_PWM0_CPRD2                     (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
00122   #define REG_PWM0_CPRDUPD2                  (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
00123   #define REG_PWM0_CCNT2                     (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
00124   #define REG_PWM0_DT2                       (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
00125   #define REG_PWM0_DTUPD2                    (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
00126   #define REG_PWM0_CMR3                      (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
00127   #define REG_PWM0_CDTY3                     (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
00128   #define REG_PWM0_CDTYUPD3                  (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
00129   #define REG_PWM0_CPRD3                     (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
00130   #define REG_PWM0_CPRDUPD3                  (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
00131   #define REG_PWM0_CCNT3                     (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
00132   #define REG_PWM0_DT3                       (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
00133   #define REG_PWM0_DTUPD3                    (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
00134   #define REG_PWM0_CMUPD0                    (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
00135   #define REG_PWM0_CMUPD1                    (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
00136   #define REG_PWM0_ETRG1                     (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
00137   #define REG_PWM0_LEBR1                     (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
00138   #define REG_PWM0_CMUPD2                    (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
00139   #define REG_PWM0_ETRG2                     (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
00140   #define REG_PWM0_LEBR2                     (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
00141   #define REG_PWM0_CMUPD3                    (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
00142   #define REG_PWM0_ETRG3                     (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */
00143   #define REG_PWM0_LEBR3                     (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */
00144   #define REG_PWM0_ETRG4                     (0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */
00145   #define REG_PWM0_LEBR4                     (0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */
00146 #else
00147   #define REG_PWM0_CLK      (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */
00148   #define REG_PWM0_ENA      (*(__O  uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */
00149   #define REG_PWM0_DIS      (*(__O  uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */
00150   #define REG_PWM0_SR       (*(__I  uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */
00151   #define REG_PWM0_IER1     (*(__O  uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */
00152   #define REG_PWM0_IDR1     (*(__O  uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */
00153   #define REG_PWM0_IMR1     (*(__I  uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */
00154   #define REG_PWM0_ISR1     (*(__I  uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */
00155   #define REG_PWM0_SCM      (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */
00156   #define REG_PWM0_DMAR     (*(__O  uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */
00157   #define REG_PWM0_SCUC     (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */
00158   #define REG_PWM0_SCUP     (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */
00159   #define REG_PWM0_SCUPUPD  (*(__O  uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */
00160   #define REG_PWM0_IER2     (*(__O  uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */
00161   #define REG_PWM0_IDR2     (*(__O  uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */
00162   #define REG_PWM0_IMR2     (*(__I  uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */
00163   #define REG_PWM0_ISR2     (*(__I  uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */
00164   #define REG_PWM0_OOV      (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */
00165   #define REG_PWM0_OS       (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */
00166   #define REG_PWM0_OSS      (*(__O  uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */
00167   #define REG_PWM0_OSC      (*(__O  uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */
00168   #define REG_PWM0_OSSUPD   (*(__O  uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */
00169   #define REG_PWM0_OSCUPD   (*(__O  uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */
00170   #define REG_PWM0_FMR      (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */
00171   #define REG_PWM0_FSR      (*(__I  uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */
00172   #define REG_PWM0_FCR      (*(__O  uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */
00173   #define REG_PWM0_FPV1     (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */
00174   #define REG_PWM0_FPE      (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */
00175   #define REG_PWM0_ELMR     (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */
00176   #define REG_PWM0_SSPR     (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */
00177   #define REG_PWM0_SSPUP    (*(__O  uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */
00178   #define REG_PWM0_SMMR     (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */
00179   #define REG_PWM0_FPV2     (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */
00180   #define REG_PWM0_WPCR     (*(__O  uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */
00181   #define REG_PWM0_WPSR     (*(__I  uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */
00182   #define REG_PWM0_CMPV0    (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */
00183   #define REG_PWM0_CMPVUPD0 (*(__O  uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */
00184   #define REG_PWM0_CMPM0    (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */
00185   #define REG_PWM0_CMPMUPD0 (*(__O  uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */
00186   #define REG_PWM0_CMPV1    (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */
00187   #define REG_PWM0_CMPVUPD1 (*(__O  uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */
00188   #define REG_PWM0_CMPM1    (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */
00189   #define REG_PWM0_CMPMUPD1 (*(__O  uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */
00190   #define REG_PWM0_CMPV2    (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */
00191   #define REG_PWM0_CMPVUPD2 (*(__O  uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */
00192   #define REG_PWM0_CMPM2    (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */
00193   #define REG_PWM0_CMPMUPD2 (*(__O  uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */
00194   #define REG_PWM0_CMPV3    (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */
00195   #define REG_PWM0_CMPVUPD3 (*(__O  uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */
00196   #define REG_PWM0_CMPM3    (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */
00197   #define REG_PWM0_CMPMUPD3 (*(__O  uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */
00198   #define REG_PWM0_CMPV4    (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */
00199   #define REG_PWM0_CMPVUPD4 (*(__O  uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */
00200   #define REG_PWM0_CMPM4    (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */
00201   #define REG_PWM0_CMPMUPD4 (*(__O  uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */
00202   #define REG_PWM0_CMPV5    (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */
00203   #define REG_PWM0_CMPVUPD5 (*(__O  uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */
00204   #define REG_PWM0_CMPM5    (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */
00205   #define REG_PWM0_CMPMUPD5 (*(__O  uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */
00206   #define REG_PWM0_CMPV6    (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */
00207   #define REG_PWM0_CMPVUPD6 (*(__O  uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */
00208   #define REG_PWM0_CMPM6    (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */
00209   #define REG_PWM0_CMPMUPD6 (*(__O  uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */
00210   #define REG_PWM0_CMPV7    (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */
00211   #define REG_PWM0_CMPVUPD7 (*(__O  uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */
00212   #define REG_PWM0_CMPM7    (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */
00213   #define REG_PWM0_CMPMUPD7 (*(__O  uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */
00214   #define REG_PWM0_CMR0     (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */
00215   #define REG_PWM0_CDTY0    (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */
00216   #define REG_PWM0_CDTYUPD0 (*(__O  uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */
00217   #define REG_PWM0_CPRD0    (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */
00218   #define REG_PWM0_CPRDUPD0 (*(__O  uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */
00219   #define REG_PWM0_CCNT0    (*(__I  uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */
00220   #define REG_PWM0_DT0      (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */
00221   #define REG_PWM0_DTUPD0   (*(__O  uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */
00222   #define REG_PWM0_CMR1     (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */
00223   #define REG_PWM0_CDTY1    (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */
00224   #define REG_PWM0_CDTYUPD1 (*(__O  uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */
00225   #define REG_PWM0_CPRD1    (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */
00226   #define REG_PWM0_CPRDUPD1 (*(__O  uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */
00227   #define REG_PWM0_CCNT1    (*(__I  uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */
00228   #define REG_PWM0_DT1      (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */
00229   #define REG_PWM0_DTUPD1   (*(__O  uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */
00230   #define REG_PWM0_CMR2     (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */
00231   #define REG_PWM0_CDTY2    (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */
00232   #define REG_PWM0_CDTYUPD2 (*(__O  uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */
00233   #define REG_PWM0_CPRD2    (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */
00234   #define REG_PWM0_CPRDUPD2 (*(__O  uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */
00235   #define REG_PWM0_CCNT2    (*(__I  uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */
00236   #define REG_PWM0_DT2      (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */
00237   #define REG_PWM0_DTUPD2   (*(__O  uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */
00238   #define REG_PWM0_CMR3     (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */
00239   #define REG_PWM0_CDTY3    (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */
00240   #define REG_PWM0_CDTYUPD3 (*(__O  uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */
00241   #define REG_PWM0_CPRD3    (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */
00242   #define REG_PWM0_CPRDUPD3 (*(__O  uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */
00243   #define REG_PWM0_CCNT3    (*(__I  uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */
00244   #define REG_PWM0_DT3      (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */
00245   #define REG_PWM0_DTUPD3   (*(__O  uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */
00246   #define REG_PWM0_CMUPD0   (*(__O  uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
00247   #define REG_PWM0_CMUPD1   (*(__O  uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
00248   #define REG_PWM0_ETRG1    (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */
00249   #define REG_PWM0_LEBR1    (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
00250   #define REG_PWM0_CMUPD2   (*(__O  uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
00251   #define REG_PWM0_ETRG2    (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */
00252   #define REG_PWM0_LEBR2    (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
00253   #define REG_PWM0_CMUPD3   (*(__O  uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
00254   #define REG_PWM0_ETRG3    (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */
00255   #define REG_PWM0_LEBR3    (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */
00256   #define REG_PWM0_ETRG4    (*(__IO uint32_t*)0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */
00257   #define REG_PWM0_LEBR4    (*(__IO uint32_t*)0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */
00258 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00259 
00260 #endif /* _SAMV71_PWM0_INSTANCE_ */
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