SAMV71 Xplained Ultra Software Package 1.4

mpu.c

Go to the documentation of this file.
00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License 
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2014, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00024  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /** \file */
00031 
00032 /** 
00033  * \addtogroup mmu MMU Initialization
00034  *
00035  * \section Usage
00036  *
00037  * Translation Look-aside Buffers (TLBs) are an implementation technique that 
00038  * caches translations or translation table entries. TLBs avoid the requirement 
00039  * for every memory access to perform a translation table lookup. 
00040  * The ARM architecture does not specify the exact form of the TLB structures 
00041  * for any design. In a similar way to the requirements for caches, the 
00042  * architecture only defines certain principles for TLBs:
00043  * 
00044  * The MMU supports memory accesses based on memory sections or pages:
00045  * Super-sections Consist of 16MB blocks of memory. Support for Super sections 
00046  * is optional.
00047  * -# Sections Consist of 1MB blocks of memory.
00048  * -# Large pages Consist of 64KB blocks of memory.
00049  * -# Small pages Consist of 4KB blocks of memory.
00050  *
00051  * Access to a memory region is controlled by the access permission bits and 
00052  * the domain field in the TLB entry.
00053  * Memory region attributes
00054  * Each TLB entry has an associated set of memory region attributes. These 
00055  * control accesses to the caches,
00056  * how the write buffer is used, and if the memory region is Shareable and 
00057  * therefore must be kept coherent.
00058  *
00059  * Related files:\n
00060  * \ref mmu.c\n
00061  * \ref mmu.h \n
00062  */
00063 
00064 /*-------------------------------------------------------------------------- */
00065 /*         Headers                                                           */
00066 /*-------------------------------------------------------------------------- */
00067 #include <chip.h>
00068 
00069 /*----------------------------------------------------------------------------
00070  *        Exported functions
00071 
00072  *----------------------------------------------------------------------------*/
00073 /**
00074  * \brief Enables the MPU module.
00075  *
00076  * \param dwMPUEnable  Enable/Disable the memory region.
00077  */
00078 void MPU_Enable( uint32_t dwMPUEnable )
00079 {
00080     MPU->CTRL = dwMPUEnable ;
00081 }
00082 
00083 /**
00084  * \brief Set active memory region.
00085  *
00086  * \param dwRegionNum  The memory region to be active.
00087  */
00088 void MPU_SetRegionNum( uint32_t dwRegionNum )
00089 {
00090     MPU->RNR = dwRegionNum;
00091 }
00092 
00093 /**
00094  * \brief Disable the current active region.
00095  */
00096 extern void MPU_DisableRegion( void )
00097 {
00098     MPU->RASR &= 0xfffffffe;
00099 }
00100 
00101 /**
00102  * \brief Setup a memory region.
00103  *
00104  * \param dwRegionBaseAddr  Memory region base address.
00105  * \param dwRegionAttr  Memory region attributes.  
00106  */
00107 void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr )
00108 {
00109     MPU->RBAR = dwRegionBaseAddr;
00110     MPU->RASR = dwRegionAttr;
00111 }
00112 
00113 
00114 /**
00115  * \brief Calculate region size for the RASR.
00116  */
00117 uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes )
00118 {
00119     uint32_t dwRegionSize = 32;
00120     uint32_t dwReturnValue = 4;
00121 
00122     while( dwReturnValue < 31 ) {
00123         if( dwActualSizeInBytes <= dwRegionSize ) {
00124             break;
00125         } else {
00126             dwReturnValue++;
00127         }
00128         dwRegionSize <<= 1;
00129     }
00130 
00131     return ( dwReturnValue << 1 );
00132 }
00133 
00134 
00135 /**
00136  *  \brief Update MPU regions.
00137  *
00138  *  \return Unused (ANSI-C compatibility).
00139  */
00140 void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
00141         uint32_t dwRegionAttr)
00142 {
00143     
00144     /* Disable interrupt */
00145     __disable_irq();
00146 
00147     /* Clean up data and instruction buffer */
00148     __DSB();
00149     __ISB();
00150 
00151     /* Set active region */
00152     MPU_SetRegionNum(dwRegionNum);
00153 
00154     /* Disable region */
00155     MPU_DisableRegion();
00156 
00157     /* Update region attribute */
00158     MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr);
00159 
00160     /* Clean up data and instruction buffer to make the new region taking 
00161        effect at once */
00162     __DSB();
00163     __ISB();
00164 
00165     /* Enable the interrupt */
00166     __enable_irq();
00167 }
00168 
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Defines