00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_MCAN1_INSTANCE_ 00031 #define _SAMV71_MCAN1_INSTANCE_ 00032 00033 /* ========== Register definition for MCAN1 peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_MCAN1_CUST (0x40034008U) /**< \brief (MCAN1) Customer Register */ 00036 #define REG_MCAN1_FBTP (0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ 00037 #define REG_MCAN1_TEST (0x40034010U) /**< \brief (MCAN1) Test Register */ 00038 #define REG_MCAN1_RWD (0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ 00039 #define REG_MCAN1_CCCR (0x40034018U) /**< \brief (MCAN1) CC Control Register */ 00040 #define REG_MCAN1_BTP (0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ 00041 #define REG_MCAN1_TSCC (0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ 00042 #define REG_MCAN1_TSCV (0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ 00043 #define REG_MCAN1_TOCC (0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ 00044 #define REG_MCAN1_TOCV (0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ 00045 #define REG_MCAN1_ECR (0x40034040U) /**< \brief (MCAN1) Error Counter Register */ 00046 #define REG_MCAN1_PSR (0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ 00047 #define REG_MCAN1_IR (0x40034050U) /**< \brief (MCAN1) Interrupt Register */ 00048 #define REG_MCAN1_IE (0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ 00049 #define REG_MCAN1_ILS (0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ 00050 #define REG_MCAN1_ILE (0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ 00051 #define REG_MCAN1_GFC (0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ 00052 #define REG_MCAN1_SIDFC (0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ 00053 #define REG_MCAN1_XIDFC (0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ 00054 #define REG_MCAN1_XIDAM (0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ 00055 #define REG_MCAN1_HPMS (0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ 00056 #define REG_MCAN1_NDAT1 (0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ 00057 #define REG_MCAN1_NDAT2 (0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ 00058 #define REG_MCAN1_RXF0C (0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ 00059 #define REG_MCAN1_RXF0S (0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ 00060 #define REG_MCAN1_RXF0A (0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ 00061 #define REG_MCAN1_RXBC (0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ 00062 #define REG_MCAN1_RXF1C (0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ 00063 #define REG_MCAN1_RXF1S (0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ 00064 #define REG_MCAN1_RXF1A (0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ 00065 #define REG_MCAN1_RXESC (0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ 00066 #define REG_MCAN1_TXBC (0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ 00067 #define REG_MCAN1_TXFQS (0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ 00068 #define REG_MCAN1_TXESC (0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ 00069 #define REG_MCAN1_TXBRP (0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ 00070 #define REG_MCAN1_TXBAR (0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ 00071 #define REG_MCAN1_TXBCR (0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ 00072 #define REG_MCAN1_TXBTO (0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ 00073 #define REG_MCAN1_TXBCF (0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ 00074 #define REG_MCAN1_TXBTIE (0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ 00075 #define REG_MCAN1_TXBCIE (0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 00076 #define REG_MCAN1_TXEFC (0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ 00077 #define REG_MCAN1_TXEFS (0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ 00078 #define REG_MCAN1_TXEFA (0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ 00079 #else 00080 #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< \brief (MCAN1) Customer Register */ 00081 #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ 00082 #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< \brief (MCAN1) Test Register */ 00083 #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ 00084 #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< \brief (MCAN1) CC Control Register */ 00085 #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ 00086 #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ 00087 #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ 00088 #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ 00089 #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ 00090 #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< \brief (MCAN1) Error Counter Register */ 00091 #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ 00092 #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< \brief (MCAN1) Interrupt Register */ 00093 #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ 00094 #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ 00095 #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ 00096 #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ 00097 #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ 00098 #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ 00099 #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ 00100 #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ 00101 #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ 00102 #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ 00103 #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ 00104 #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ 00105 #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ 00106 #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ 00107 #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ 00108 #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ 00109 #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ 00110 #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ 00111 #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ 00112 #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ 00113 #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ 00114 #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ 00115 #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ 00116 #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ 00117 #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ 00118 #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ 00119 #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ 00120 #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 00121 #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ 00122 #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ 00123 #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ 00124 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00125 00126 #endif /* _SAMV71_MCAN1_INSTANCE_ */