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00031
00032 #ifndef USBHS_H
00033 #define USBHS_H
00034
00035
00036
00037
00038 #define USB_DEVICE_HS_SUPPORT
00039
00040
00041 #define USB_DEVICE_EP_CTRL_SIZE 64
00042
00043
00044 #define CHIP_USB_UDP
00045
00046
00047 #define CHIP_USB_PULLUP_INTERNAL
00048
00049
00050 #define CHIP_USB_NUMENDPOINTS 10
00051
00052
00053 #define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \
00054 ((ep == 0) ? 64 : 1024)
00055
00056
00057 #define CHIP_USB_ENDPOINTS_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2))
00058
00059
00060 #define CHIP_USB_ENDPOINTS_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false)
00061
00062
00063 #define CHIP_USB_ENDPOINTS_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false)
00064
00065
00066 #define DMA_MAX_FIFO_SIZE (65536/1)
00067
00068 #define EPT_VIRTUAL_SIZE 16384
00069
00070
00071
00072
00073
00074
00075 #define uhd_get_pipe_max_nbr() (9)
00076 #define USBHS_EPT_NUM (uhd_get_pipe_max_nbr()+1)
00077
00078 #define uhd_get_pipe_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2))
00079
00080 #define uhd_get_pipe_size_max(ep) (((ep) == 0) ? 64 : 1024)
00081
00082 #define Is_uhd_pipe_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 6)) ? true : false)
00083
00084 #define Is_uhd_pipe_high_bw_supported(ep) (((ep) >= 2) ? true : false)
00085
00086
00087 typedef enum
00088 {
00089 HOST_MODE= 0,
00090 DEVICE_MODE=1
00091 }USB_Mode_t;
00092
00093
00094 #define UHD_PIPE_MAX_TRANS 0x8000
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107 __STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs)
00108 {
00109 pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
00110 }
00111
00112
00113
00114
00115
00116
00117 __STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs)
00118 {
00119 pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK);
00120 }
00121
00122
00123
00124
00125
00126 __STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable)
00127 {
00128
00129 if(!Enable) {
00130 pUsbhs->USBHS_CTRL |= (1<<8);
00131 } else {
00132 pUsbhs->USBHS_CTRL &= ~((uint32_t)(1<<8));
00133 }
00134 }
00135
00136
00137
00138
00139
00140
00141
00142 __STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable)
00143 {
00144 if(Enable) {
00145 pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE;
00146 } else {
00147 pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE);
00148 }
00149 }
00150
00151
00152
00153
00154
00155
00156
00157
00158 __STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode)
00159 {
00160 if(Mode) {
00161 pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE;
00162 } else {
00163 pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE);
00164 }
00165 }
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175 __STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs)
00176 {
00177 return (( pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14);
00178 }
00179
00180
00181
00182
00183
00184
00185
00186
00187 __STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs)
00188 {
00189 return (pUsbhs->USBHS_SR);
00190 }
00191
00192
00193
00194
00195
00196
00197
00198 __STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs)
00199 {
00200 return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) );
00201 }
00202
00203
00204
00205
00206
00207
00208
00209
00210 __STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs)
00211 {
00212 return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ? true:false;
00213 }
00214
00215
00216
00217
00218
00219
00220
00221
00222 __STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs)
00223 {
00224 return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ? true:false;
00225 }
00226
00227
00228
00229
00230
00231
00232
00233 __STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs)
00234 {
00235 return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ? true:false;
00236 }
00237
00238
00239
00240
00241
00242
00243
00244
00245 __STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType)
00246 {
00247 pUsbhs->USBHS_SCR |= AckType;
00248 }
00249
00250
00251
00252
00253
00254
00255
00256
00257
00258 __STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus)
00259 {
00260 pUsbhs->USBHS_SFR |= SetStatus;
00261 }
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274 __STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable)
00275 {
00276 if(Enable) {
00277 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
00278 } else {
00279 pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN);
00280 }
00281 }
00282
00283
00284
00285
00286
00287
00288
00289 __STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr)
00290 {
00291 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr);
00292 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
00293 }
00294
00295
00296
00297
00298
00299
00300 __STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs)
00301 {
00302 return ( pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk);
00303 }
00304
00305
00306
00307
00308
00309
00310
00311 __STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable)
00312 {
00313 if(Enable) {
00314 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
00315 } else {
00316 pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH);
00317 }
00318
00319 }
00320
00321
00322
00323
00324
00325
00326
00327 __STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable)
00328 {
00329 if(Enable) {
00330 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS;
00331 } else {
00332 pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS);
00333 }
00334 }
00335
00336
00337
00338
00339
00340
00341
00342 __STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable)
00343 {
00344 uint32_t cfg = pUsbhs->USBHS_DEVCTRL;
00345 cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk);
00346 if(Enable) {
00347 pUsbhs->USBHS_DEVCTRL |= cfg;
00348 } else {
00349 pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS);
00350 }
00351
00352 }
00353
00354
00355
00356
00357
00358
00359 __STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs)
00360 {
00361 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
00362 }
00363
00364
00365
00366
00367
00368
00369
00370 __STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode)
00371 {
00372 pUsbhs->USBHS_DEVCTRL |= mode;
00373 }
00374
00375
00376
00377
00378
00379
00380
00381 __STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs)
00382 {
00383 pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED;
00384 }
00385
00386
00387
00388
00389
00390
00391
00392 __STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType)
00393 {
00394 return (pUsbhs->USBHS_DEVISR & IntType);
00395 }
00396
00397
00398
00399
00400
00401
00402
00403 __STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum)
00404 {
00405 return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_PEP_0 << EpNum) );
00406 }
00407
00408
00409
00410
00411
00412
00413 __STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum)
00414 {
00415 return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_DMA_1 << DmaNum) );
00416 }
00417
00418
00419
00420
00421
00422
00423
00424 __STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType)
00425 {
00426 pUsbhs->USBHS_DEVICR |= IntType;
00427 }
00428
00429
00430
00431
00432
00433
00434
00435
00436 __STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType)
00437 {
00438 pUsbhs->USBHS_DEVIFR |= IntType;
00439 }
00440
00441
00442
00443
00444
00445
00446 __STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma)
00447 {
00448 assert(Dma< USBHSDEVDMA_NUMBER);
00449 pUsbhs->USBHS_DEVIFR |= ( USBHS_DEVIFR_DMA_1 << Dma );
00450 }
00451
00452
00453
00454
00455
00456
00457
00458 __STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType)
00459 {
00460 return (pUsbhs->USBHS_DEVIMR & IntType);
00461 }
00462
00463
00464
00465
00466
00467
00468
00469 __STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum)
00470 {
00471 return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_PEP_0 << EpNum ));
00472 }
00473
00474
00475
00476
00477
00478
00479
00480
00481
00482 __STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum)
00483 {
00484 return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_DMA_1 << DmaNum));
00485 }
00486
00487
00488
00489
00490
00491
00492
00493 __STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType)
00494 {
00495 pUsbhs->USBHS_DEVIER |= IntType;
00496 }
00497
00498
00499
00500
00501
00502
00503 __STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum)
00504 {
00505 pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_PEP_0 << EpNum);
00506 }
00507
00508
00509
00510
00511
00512
00513
00514 __STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp)
00515 {
00516 assert(DmaEp< USBHSDEVDMA_NUMBER);
00517 pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_DMA_1 << DmaEp);
00518 }
00519
00520
00521
00522
00523
00524
00525
00526 __STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType)
00527 {
00528 pUsbhs->USBHS_DEVIDR |= IntType;
00529 }
00530
00531
00532
00533
00534
00535
00536
00537 __STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep)
00538 {
00539 pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_PEP_0 << Ep);
00540 }
00541
00542
00543
00544
00545
00546
00547 __STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp)
00548 {
00549 assert(DmaEp< USBHSDEVDMA_NUMBER);
00550 pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_DMA_1 << DmaEp);
00551 }
00552
00553
00554
00555
00556
00557
00558
00559
00560 __STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
00561 {
00562 if(Enable) {
00563 pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep);
00564 } else {
00565 pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep);
00566 }
00567
00568 }
00569
00570
00571
00572
00573
00574
00575
00576
00577 __STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep)
00578 {
00579 pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPRST0 << Ep);
00580
00581 }
00582
00583
00584
00585
00586
00587
00588
00589 __STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep)
00590 {
00591 return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep) );
00592 }
00593
00594
00595
00596
00597
00598
00599 __STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs)
00600 {
00601 return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk);
00602 }
00603
00604
00605
00606
00607
00608
00609
00610 __STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs)
00611 {
00612 return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk)
00613 >> USBHS_DEVFNUM_FNUM_Pos);
00614 }
00615
00616
00617
00618
00619
00620
00621 __STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs)
00622 {
00623 return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15);
00624 }
00625
00626
00627
00628
00629
00630
00631
00632
00633
00634 __STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep,
00635 const uint8_t Type, const uint8_t Dir,
00636 const uint8_t Size, const uint8_t Bank)
00637 {
00638
00639 pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00640 ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk);
00641 pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00642 ((Dir << 8 ) & USBHS_DEVEPTCFG_EPDIR);
00643 pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00644 (( (Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk);
00645 pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00646 (( (Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk);
00647 }
00648
00649
00650
00651
00652
00653 __STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
00654 {
00655 if(Enable) {
00656 pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_AUTOSW;
00657 } else {
00658 pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW);
00659 }
00660 }
00661
00662
00663
00664
00665
00666 __STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep)
00667 {
00668 pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_ALLOC;
00669 }
00670
00671
00672
00673
00674
00675 __STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep)
00676 {
00677 pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC);
00678 }
00679
00680
00681
00682
00683
00684 __STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep,
00685 uint32_t IntType)
00686 {
00687 return ((pUsbhs->USBHS_DEVEPTCFG[Ep] ) & IntType);
00688 }
00689
00690
00691
00692
00693 __STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep)
00694 {
00695 return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk)
00696 >> USBHS_DEVEPTCFG_EPTYPE_Pos);
00697 }
00698
00699
00700
00701
00702 __STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep)
00703 {
00704 return ( 8 << ( (pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk)
00705 >> USBHS_DEVEPTCFG_EPSIZE_Pos) );
00706 }
00707
00708
00709
00710
00711
00712 __STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep,
00713 uint8_t nbTrans)
00714 {
00715 pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans) ;
00716 }
00717
00718
00719
00720
00721 __STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep,
00722 uint32_t EpIntType)
00723 {
00724 return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType);
00725 }
00726
00727
00728
00729
00730
00731 __STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
00732 uint32_t EpInt)
00733 {
00734 pUsbhs->USBHS_DEVEPTIER[Ep] |= EpInt;
00735 }
00736
00737
00738
00739
00740 __STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep)
00741 {
00742 return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK);
00743 }
00744
00745
00746
00747
00748 __STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep)
00749 {
00750 pUsbhs->USBHS_DEVEPTIER[Ep] = USBHS_DEVEPTIER_KILLBKS;
00751 }
00752
00753
00754
00755 __STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
00756 uint32_t EpInt)
00757 {
00758 pUsbhs->USBHS_DEVEPTIDR[Ep] |= EpInt;
00759 }
00760
00761
00762
00763
00764 __STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
00765 {
00766 pUsbhs->USBHS_DEVEPTICR[Ep] |= EpInt;
00767 }
00768
00769
00770
00771
00772 __STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
00773 {
00774 pUsbhs->USBHS_DEVEPTIFR[Ep] |= EpInt;
00775 }
00776
00777
00778
00779
00780 __STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep,
00781 uint32_t EpInt)
00782 {
00783 return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt);
00784 }
00785
00786
00787
00788
00789 __STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep)
00790 {
00791 if( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)) {
00792 return false;
00793 } else {
00794 return true;
00795 }
00796 }
00797
00798
00799
00800
00801 __STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep)
00802 {
00803 return ( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)
00804 >> USBHS_DEVEPTISR_NBUSYBK_Pos);
00805 }
00806
00807
00808
00809
00810
00811 __STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep)
00812 {
00813 return (uint16_t)( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk)
00814 >> USBHS_DEVEPTISR_BYCT_Pos);
00815 }
00816
00817
00818
00819
00820
00821
00822
00823
00824
00825
00826 __STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc)
00827 {
00828 pUsbDma->USBHS_DEVDMANXTDSC = Desc;
00829 }
00830
00831
00832
00833
00834
00835
00836 __STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma)
00837 {
00838 return (pUsbDma->USBHS_DEVDMANXTDSC);
00839 }
00840
00841
00842
00843
00844
00845
00846 __STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr)
00847 {
00848 pUsbDma->USBHS_DEVDMAADDRESS = Addr;
00849 }
00850
00851
00852
00853
00854
00855
00856
00857 __STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma)
00858 {
00859 return (pUsbDma->USBHS_DEVDMAADDRESS);
00860 }
00861
00862
00863
00864
00865
00866
00867 __STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg)
00868 {
00869 pUsbDma->USBHS_DEVDMACONTROL |= Cfg;
00870 }
00871
00872
00873
00874
00875
00876
00877 __STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma)
00878 {
00879 return (pUsbDma->USBHS_DEVDMACONTROL);
00880 }
00881
00882
00883
00884
00885
00886
00887
00888 __STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status)
00889 {
00890 pUsbDma->USBHS_DEVDMASTATUS = Status;
00891 }
00892
00893
00894
00895
00896
00897
00898
00899 __STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma)
00900 {
00901 return (pUsbDma->USBHS_DEVDMASTATUS);
00902 }
00903
00904
00905
00906
00907
00908
00909
00910 __STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma)
00911 {
00912 return ( (pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk)
00913 >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
00914 }
00915
00916
00917
00918
00919
00920
00921
00922 #define CHIP_USB_NUMPIPE 10
00923
00924 #define CHIP_USB_DMA_NUMPIPE 7
00925
00926
00927 #define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \
00928 ((ep == 0) ? 64 : 1024)
00929
00930
00931 #define CHIP_USB_PIPE_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2))
00932
00933
00934 #define CHIP_USB_PIPE_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false)
00935
00936
00937 #define CHIP_USB_PIPE_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false)
00938
00939
00940
00941
00942
00943 __STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs)
00944 {
00945 pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00946 pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL;
00947 }
00948
00949
00950
00951
00952
00953 __STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs)
00954 {
00955 pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00956 pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER;
00957 }
00958
00959
00960
00961
00962
00963 __STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs)
00964 {
00965 pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00966 pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS;
00967 }
00968
00969
00970
00971
00972
00973 __STATIC_INLINE void USBHS_Reset(void)
00974 {
00975 USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET;
00976 }
00977
00978
00979
00980
00981
00982 __STATIC_INLINE void USBHS_StopReset(void)
00983 {
00984 USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET;
00985 }
00986
00987
00988
00989
00990
00991 __STATIC_INLINE void USBHS_Resume(void)
00992 {
00993 USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME;
00994 }
00995
00996
00997
00998
00999
01000 __STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs)
01001 {
01002 pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE;
01003 }
01004
01005
01006
01007
01008
01009 __STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs)
01010 {
01011 return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8;
01012 }
01013
01014
01015
01016
01017 __STATIC_INLINE void USBHS_DisableSOF(void)
01018 {
01019 USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE;
01020 }
01021
01022
01023
01024
01025
01026 __STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType)
01027 {
01028 return (pUsbhs->USBHS_HSTISR & IntType);
01029 }
01030
01031
01032
01033
01034
01035
01036 __STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01037 {
01038 assert( PipeInt < CHIP_USB_NUMPIPE);
01039 return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_PEP_0 << PipeInt) );
01040 }
01041
01042
01043
01044
01045
01046
01047 __STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01048 {
01049 assert( PipeInt);
01050 assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01051 return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_DMA_1 << PipeInt) );
01052 }
01053
01054
01055
01056
01057
01058 __STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType)
01059 {
01060 pUsbhs->USBHS_HSTICR = IntType;
01061 }
01062
01063
01064
01065
01066
01067 __STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType)
01068 {
01069 pUsbhs->USBHS_HSTIFR = IntType;
01070 }
01071
01072
01073
01074
01075
01076 __STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01077 {
01078 assert( PipeInt);
01079 assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01080 pUsbhs->USBHS_HSTIFR = (USBHS_HSTIFR_DMA_1 << PipeInt) ;
01081 }
01082
01083
01084
01085
01086
01087
01088 __STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType)
01089 {
01090 return (pUsbhs->USBHS_HSTIMR & IntType) ;
01091 }
01092
01093
01094
01095
01096
01097 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01098 {
01099 assert( PipeInt < CHIP_USB_NUMPIPE);
01100 return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt) );
01101 }
01102
01103
01104
01105
01106
01107 __STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01108 {
01109 assert( PipeInt);
01110 assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01111 return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt) );
01112 }
01113
01114
01115
01116
01117
01118
01119 __STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType)
01120 {
01121 pUsbhs->USBHS_HSTIDR = IntType ;
01122 }
01123
01124
01125
01126
01127
01128 __STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
01129 {
01130 assert( PipeInt < CHIP_USB_NUMPIPE);
01131 pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_PEP_0 << PipeInt);
01132 }
01133
01134
01135
01136
01137
01138 __STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
01139 {
01140 assert( PipeInt);
01141 assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01142 pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt) ;
01143 }
01144
01145
01146
01147
01148
01149
01150
01151 __STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType)
01152 {
01153 pUsbhs->USBHS_HSTIER = IntType ;
01154 }
01155
01156
01157
01158
01159
01160 __STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01161 {
01162 assert( PipeInt < CHIP_USB_NUMPIPE);
01163 pUsbhs->USBHS_HSTIER =(USBHS_HSTIER_PEP_0 << PipeInt) ;
01164 }
01165
01166
01167
01168
01169
01170 __STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01171 {
01172 assert( PipeInt < CHIP_USB_DMA_NUMPIPE);
01173 pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt);
01174 }
01175
01176
01177
01178
01179
01180 __STATIC_INLINE uint16_t USBHS_HostGetSOF(void)
01181 {
01182 return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >> USBHS_HSTFNUM_FNUM_Pos);
01183 }
01184
01185
01186
01187
01188
01189 __STATIC_INLINE uint16_t USBHS_HostGetFramePos(void)
01190 {
01191 return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >> USBHS_HSTFNUM_FLENHIGH_Pos);
01192 }
01193
01194
01195
01196
01197
01198
01199 __STATIC_INLINE uint16_t USBHS_HostGetMSOF(void)
01200 {
01201 return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >> USBHS_HSTFNUM_MFNUM_Pos);
01202 }
01203
01204 __STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Addr)
01205 {
01206 assert( Pipe < CHIP_USB_NUMPIPE);
01207 if (Pipe <4)
01208 {
01209 pUsbhs->USBHS_HSTADDR1 |= (Addr << (8*Pipe));
01210 }
01211 else if( (Pipe <8) && (Pipe >=4))
01212 {
01213 pUsbhs->USBHS_HSTADDR2 |= (Addr << (8* (Pipe -4)));
01214 }
01215 else
01216 {
01217 pUsbhs->USBHS_HSTADDR3 |= (Addr << (8*(Pipe -8)));
01218 }
01219
01220 }
01221
01222 __STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe)
01223 {
01224 assert( Pipe < CHIP_USB_NUMPIPE);
01225 if (Pipe <4)
01226 {
01227 return ( pUsbhs->USBHS_HSTADDR1 >> (8*Pipe)) ;
01228 }
01229 else if( (Pipe <8) && (Pipe >=4))
01230 {
01231 return (pUsbhs->USBHS_HSTADDR2 >> (8*(Pipe -4)));
01232 }
01233 else
01234 {
01235 return (pUsbhs->USBHS_HSTADDR3 >> (8*(Pipe -8)));
01236 }
01237
01238 }
01239
01240
01241
01242
01243
01244 __STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
01245 {
01246 assert( Pipe < CHIP_USB_NUMPIPE);
01247 pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe);
01248 }
01249
01250
01251
01252
01253
01254 __STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe)
01255 {
01256 assert( Pipe < CHIP_USB_NUMPIPE);
01257 pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe);
01258 }
01259
01260
01261
01262
01263
01264 __STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
01265 {
01266 assert( Pipe < CHIP_USB_NUMPIPE);
01267 return (pUsbhs->USBHS_HSTPIP &(USBHS_HSTPIP_PEN0 << Pipe));
01268 }
01269
01270
01271
01272
01273 __STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe)
01274 {
01275 assert( Pipe < CHIP_USB_NUMPIPE);
01276 pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe);
01277 pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe);
01278 }
01279
01280
01281
01282
01283
01284 __STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, uint8_t pipeEpNum, uint8_t PipeIntFreq)
01285 {
01286 assert( Pipe < CHIP_USB_NUMPIPE);
01287 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= ( pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) | USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq));
01288 }
01289
01290
01291
01292
01293
01294 __STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe)
01295 {
01296 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC;
01297
01298 }
01299
01300
01301
01302
01303
01304 __STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe)
01305 {
01306 pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC;
01307
01308 }
01309
01310
01311
01312
01313
01314
01315 __STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe)
01316 {
01317 return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >> USBHS_HSTPIPCFG_PSIZE_Pos)) ;
01318
01319 }
01320
01321
01322
01323
01324
01325 __STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, uint32_t Token)
01326 {
01327 pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk;
01328 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token;
01329
01330 }
01331
01332
01333
01334
01335
01336
01337 __STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe)
01338 {
01339 return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk) ;
01340
01341 }
01342
01343
01344
01345
01346
01347
01348 __STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, uint8_t PipeType)
01349 {
01350 pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk ;
01351 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType ;
01352
01353 }
01354
01355
01356
01357
01358
01359 __STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe )
01360 {
01361 return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk) ;
01362
01363 }
01364
01365 __STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe)
01366 {
01367
01368 if( USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN)
01369 {
01370 return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80);
01371 }
01372 else
01373 {
01374 return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00) ;
01375 }
01376 }
01377
01378
01379
01380
01381
01382
01383
01384 __STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
01385 {
01386 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW;
01387 }
01388
01389
01390
01391
01392
01393 __STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
01394 {
01395 pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW;
01396 }
01397
01398
01399
01400
01401
01402 __STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Freq)
01403 {
01404 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq);
01405 }
01406
01407
01408
01409
01410
01411
01412 __STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe)
01413 {
01414 pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN;
01415 }
01416
01417
01418
01419
01420
01421
01422 __STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe)
01423 {
01424 return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >> USBHS_HSTPIPISR_DTSEQ_Pos ) ;
01425 }
01426
01427
01428
01429
01430
01431
01432 __STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe)
01433 {
01434 return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >> USBHS_HSTPIPISR_NBUSYBK_Pos ) ;
01435 }
01436
01437
01438
01439
01440
01441
01442 __STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe)
01443 {
01444 return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >> USBHS_HSTPIPISR_CURRBK_Pos ) ;
01445 }
01446
01447
01448
01449
01450
01451
01452 __STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe)
01453 {
01454 return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >> USBHS_HSTPIPISR_PBYCT_Pos ) ;
01455 }
01456
01457
01458
01459
01460
01461 __STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe)
01462 {
01463 return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK);
01464 }
01465
01466
01467
01468
01469
01470 __STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01471 {
01472 return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType);
01473 }
01474
01475
01476
01477
01478
01479 __STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01480 {
01481 pUsbhs->USBHS_HSTPIPICR[Pipe] = intType;
01482 }
01483
01484
01485
01486
01487
01488 __STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01489 {
01490 pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType;
01491 }
01492
01493
01494
01495
01496
01497 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01498 {
01499 return ( pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType);
01500 }
01501
01502
01503
01504
01505
01506 __STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01507 {
01508 pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType;
01509 }
01510
01511
01512
01513
01514
01515 __STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType)
01516 {
01517 pUsbhs->USBHS_HSTPIPIER[Pipe] = intType;
01518 }
01519
01520
01521
01522
01523
01524 __STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe)
01525 {
01526 pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE;
01527 }
01528
01529
01530
01531
01532
01533 __STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe)
01534 {
01535 pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE;
01536 }
01537
01538
01539
01540
01541
01542 __STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe)
01543 {
01544 return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8);
01545 }
01546
01547
01548
01549
01550
01551 __STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq)
01552 {
01553 pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq-1);
01554 }
01555
01556
01557
01558
01559
01560
01561 __STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01562 {
01563 pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err;
01564 }
01565
01566
01567
01568
01569
01570 __STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01571 {
01572 return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err);
01573 }
01574
01575
01576
01577
01578
01579
01580 __STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01581 {
01582 pUsbhs->USBHS_HSTPIPERR[Pipe] = Err;
01583 }
01584
01585
01586 __STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void)
01587 {
01588 uint32_t status = USBHS->USBHS_HSTISR;
01589 uint32_t mask = USBHS->USBHS_HSTIMR;
01590 return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM));
01591 }
01592
01593 static inline uint8_t USBHS_GetInterruptPipeDmaNum(void)
01594 {
01595 uint32_t status = USBHS->USBHS_HSTISR;
01596 uint32_t mask = USBHS->USBHS_HSTIMR;
01597 return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM-1))) + 1);
01598 }
01599
01600
01601
01602
01603
01604
01605
01606
01607
01608 __STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc)
01609 {
01610 pUsbDma->USBHS_HSTDMANXTDSC = Desc;
01611 }
01612
01613
01614
01615
01616
01617
01618 __STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma)
01619 {
01620 return (pUsbDma->USBHS_HSTDMANXTDSC);
01621 }
01622
01623
01624
01625
01626
01627
01628 __STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, uint32_t Addr)
01629 {
01630 pUsbDma->USBHS_HSTDMAADDRESS = Addr;
01631 }
01632
01633
01634
01635
01636
01637
01638
01639 __STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma)
01640 {
01641 return (pUsbDma->USBHS_HSTDMAADDRESS);
01642 }
01643
01644
01645
01646
01647
01648
01649 __STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg)
01650 {
01651 pUsbDma->USBHS_HSTDMACONTROL |= Cfg;
01652 }
01653
01654
01655
01656
01657
01658
01659 __STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma)
01660 {
01661 return (pUsbDma->USBHS_HSTDMACONTROL);
01662 }
01663
01664
01665
01666
01667
01668
01669
01670 __STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, uint32_t Status)
01671 {
01672 pUsbDma->USBHS_HSTDMASTATUS = Status;
01673 }
01674
01675
01676
01677
01678
01679
01680
01681 __STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma)
01682 {
01683 return (pUsbDma->USBHS_HSTDMASTATUS);
01684 }
01685
01686
01687 #endif