SAMV71 Xplained Ultra Software Package 1.4

instance_pwm1.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2014, Atmel Corporation                                        */
00006 /*                                                                              */
00007 /* All rights reserved.                                                         */
00008 /*                                                                              */
00009 /* Redistribution and use in source and binary forms, with or without           */
00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
00018 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
00028 /* ---------------------------------------------------------------------------- */
00029 
00030 #ifndef _SAMV71_PWM1_INSTANCE_
00031 #define _SAMV71_PWM1_INSTANCE_
00032 
00033 /* ========== Register definition for PWM1 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_PWM1_CLK                       (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */
00036   #define REG_PWM1_ENA                       (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */
00037   #define REG_PWM1_DIS                       (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */
00038   #define REG_PWM1_SR                        (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */
00039   #define REG_PWM1_IER1                      (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */
00040   #define REG_PWM1_IDR1                      (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */
00041   #define REG_PWM1_IMR1                      (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */
00042   #define REG_PWM1_ISR1                      (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */
00043   #define REG_PWM1_SCM                       (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */
00044   #define REG_PWM1_DMAR                      (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */
00045   #define REG_PWM1_SCUC                      (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */
00046   #define REG_PWM1_SCUP                      (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */
00047   #define REG_PWM1_SCUPUPD                   (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */
00048   #define REG_PWM1_IER2                      (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */
00049   #define REG_PWM1_IDR2                      (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */
00050   #define REG_PWM1_IMR2                      (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */
00051   #define REG_PWM1_ISR2                      (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */
00052   #define REG_PWM1_OOV                       (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */
00053   #define REG_PWM1_OS                        (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */
00054   #define REG_PWM1_OSS                       (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */
00055   #define REG_PWM1_OSC                       (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */
00056   #define REG_PWM1_OSSUPD                    (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */
00057   #define REG_PWM1_OSCUPD                    (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */
00058   #define REG_PWM1_FMR                       (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */
00059   #define REG_PWM1_FSR                       (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */
00060   #define REG_PWM1_FCR                       (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */
00061   #define REG_PWM1_FPV1                      (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */
00062   #define REG_PWM1_FPE                       (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */
00063   #define REG_PWM1_ELMR                      (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */
00064   #define REG_PWM1_SSPR                      (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */
00065   #define REG_PWM1_SSPUP                     (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */
00066   #define REG_PWM1_SMMR                      (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */
00067   #define REG_PWM1_FPV2                      (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */
00068   #define REG_PWM1_WPCR                      (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */
00069   #define REG_PWM1_WPSR                      (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */
00070   #define REG_PWM1_CMPV0                     (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */
00071   #define REG_PWM1_CMPVUPD0                  (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */
00072   #define REG_PWM1_CMPM0                     (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */
00073   #define REG_PWM1_CMPMUPD0                  (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */
00074   #define REG_PWM1_CMPV1                     (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */
00075   #define REG_PWM1_CMPVUPD1                  (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */
00076   #define REG_PWM1_CMPM1                     (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */
00077   #define REG_PWM1_CMPMUPD1                  (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */
00078   #define REG_PWM1_CMPV2                     (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */
00079   #define REG_PWM1_CMPVUPD2                  (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */
00080   #define REG_PWM1_CMPM2                     (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */
00081   #define REG_PWM1_CMPMUPD2                  (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */
00082   #define REG_PWM1_CMPV3                     (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */
00083   #define REG_PWM1_CMPVUPD3                  (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */
00084   #define REG_PWM1_CMPM3                     (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */
00085   #define REG_PWM1_CMPMUPD3                  (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */
00086   #define REG_PWM1_CMPV4                     (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */
00087   #define REG_PWM1_CMPVUPD4                  (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */
00088   #define REG_PWM1_CMPM4                     (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */
00089   #define REG_PWM1_CMPMUPD4                  (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */
00090   #define REG_PWM1_CMPV5                     (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */
00091   #define REG_PWM1_CMPVUPD5                  (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */
00092   #define REG_PWM1_CMPM5                     (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */
00093   #define REG_PWM1_CMPMUPD5                  (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */
00094   #define REG_PWM1_CMPV6                     (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */
00095   #define REG_PWM1_CMPVUPD6                  (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */
00096   #define REG_PWM1_CMPM6                     (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */
00097   #define REG_PWM1_CMPMUPD6                  (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */
00098   #define REG_PWM1_CMPV7                     (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */
00099   #define REG_PWM1_CMPVUPD7                  (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */
00100   #define REG_PWM1_CMPM7                     (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */
00101   #define REG_PWM1_CMPMUPD7                  (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */
00102   #define REG_PWM1_CMR0                      (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */
00103   #define REG_PWM1_CDTY0                     (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */
00104   #define REG_PWM1_CDTYUPD0                  (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */
00105   #define REG_PWM1_CPRD0                     (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */
00106   #define REG_PWM1_CPRDUPD0                  (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */
00107   #define REG_PWM1_CCNT0                     (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */
00108   #define REG_PWM1_DT0                       (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */
00109   #define REG_PWM1_DTUPD0                    (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */
00110   #define REG_PWM1_CMR1                      (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */
00111   #define REG_PWM1_CDTY1                     (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */
00112   #define REG_PWM1_CDTYUPD1                  (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */
00113   #define REG_PWM1_CPRD1                     (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */
00114   #define REG_PWM1_CPRDUPD1                  (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */
00115   #define REG_PWM1_CCNT1                     (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */
00116   #define REG_PWM1_DT1                       (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */
00117   #define REG_PWM1_DTUPD1                    (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */
00118   #define REG_PWM1_CMR2                      (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */
00119   #define REG_PWM1_CDTY2                     (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */
00120   #define REG_PWM1_CDTYUPD2                  (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */
00121   #define REG_PWM1_CPRD2                     (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */
00122   #define REG_PWM1_CPRDUPD2                  (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */
00123   #define REG_PWM1_CCNT2                     (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */
00124   #define REG_PWM1_DT2                       (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */
00125   #define REG_PWM1_DTUPD2                    (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */
00126   #define REG_PWM1_CMR3                      (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */
00127   #define REG_PWM1_CDTY3                     (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */
00128   #define REG_PWM1_CDTYUPD3                  (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */
00129   #define REG_PWM1_CPRD3                     (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */
00130   #define REG_PWM1_CPRDUPD3                  (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */
00131   #define REG_PWM1_CCNT3                     (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */
00132   #define REG_PWM1_DT3                       (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */
00133   #define REG_PWM1_DTUPD3                    (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */
00134   #define REG_PWM1_CMUPD0                    (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
00135   #define REG_PWM1_CMUPD1                    (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
00136   #define REG_PWM1_ETRG1                     (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */
00137   #define REG_PWM1_LEBR1                     (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
00138   #define REG_PWM1_CMUPD2                    (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
00139   #define REG_PWM1_ETRG2                     (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */
00140   #define REG_PWM1_LEBR2                     (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
00141   #define REG_PWM1_CMUPD3                    (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
00142   #define REG_PWM1_ETRG3                     (0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */
00143   #define REG_PWM1_LEBR3                     (0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */
00144   #define REG_PWM1_ETRG4                     (0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */
00145   #define REG_PWM1_LEBR4                     (0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */
00146 #else
00147   #define REG_PWM1_CLK      (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */
00148   #define REG_PWM1_ENA      (*(__O  uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */
00149   #define REG_PWM1_DIS      (*(__O  uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */
00150   #define REG_PWM1_SR       (*(__I  uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */
00151   #define REG_PWM1_IER1     (*(__O  uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */
00152   #define REG_PWM1_IDR1     (*(__O  uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */
00153   #define REG_PWM1_IMR1     (*(__I  uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */
00154   #define REG_PWM1_ISR1     (*(__I  uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */
00155   #define REG_PWM1_SCM      (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */
00156   #define REG_PWM1_DMAR     (*(__O  uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */
00157   #define REG_PWM1_SCUC     (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */
00158   #define REG_PWM1_SCUP     (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */
00159   #define REG_PWM1_SCUPUPD  (*(__O  uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */
00160   #define REG_PWM1_IER2     (*(__O  uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */
00161   #define REG_PWM1_IDR2     (*(__O  uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */
00162   #define REG_PWM1_IMR2     (*(__I  uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */
00163   #define REG_PWM1_ISR2     (*(__I  uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */
00164   #define REG_PWM1_OOV      (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */
00165   #define REG_PWM1_OS       (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */
00166   #define REG_PWM1_OSS      (*(__O  uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */
00167   #define REG_PWM1_OSC      (*(__O  uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */
00168   #define REG_PWM1_OSSUPD   (*(__O  uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */
00169   #define REG_PWM1_OSCUPD   (*(__O  uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */
00170   #define REG_PWM1_FMR      (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */
00171   #define REG_PWM1_FSR      (*(__I  uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */
00172   #define REG_PWM1_FCR      (*(__O  uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */
00173   #define REG_PWM1_FPV1     (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */
00174   #define REG_PWM1_FPE      (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */
00175   #define REG_PWM1_ELMR     (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */
00176   #define REG_PWM1_SSPR     (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */
00177   #define REG_PWM1_SSPUP    (*(__O  uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */
00178   #define REG_PWM1_SMMR     (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */
00179   #define REG_PWM1_FPV2     (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */
00180   #define REG_PWM1_WPCR     (*(__O  uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */
00181   #define REG_PWM1_WPSR     (*(__I  uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */
00182   #define REG_PWM1_CMPV0    (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */
00183   #define REG_PWM1_CMPVUPD0 (*(__O  uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */
00184   #define REG_PWM1_CMPM0    (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */
00185   #define REG_PWM1_CMPMUPD0 (*(__O  uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */
00186   #define REG_PWM1_CMPV1    (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */
00187   #define REG_PWM1_CMPVUPD1 (*(__O  uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */
00188   #define REG_PWM1_CMPM1    (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */
00189   #define REG_PWM1_CMPMUPD1 (*(__O  uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */
00190   #define REG_PWM1_CMPV2    (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */
00191   #define REG_PWM1_CMPVUPD2 (*(__O  uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */
00192   #define REG_PWM1_CMPM2    (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */
00193   #define REG_PWM1_CMPMUPD2 (*(__O  uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */
00194   #define REG_PWM1_CMPV3    (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */
00195   #define REG_PWM1_CMPVUPD3 (*(__O  uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */
00196   #define REG_PWM1_CMPM3    (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */
00197   #define REG_PWM1_CMPMUPD3 (*(__O  uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */
00198   #define REG_PWM1_CMPV4    (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */
00199   #define REG_PWM1_CMPVUPD4 (*(__O  uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */
00200   #define REG_PWM1_CMPM4    (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */
00201   #define REG_PWM1_CMPMUPD4 (*(__O  uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */
00202   #define REG_PWM1_CMPV5    (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */
00203   #define REG_PWM1_CMPVUPD5 (*(__O  uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */
00204   #define REG_PWM1_CMPM5    (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */
00205   #define REG_PWM1_CMPMUPD5 (*(__O  uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */
00206   #define REG_PWM1_CMPV6    (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */
00207   #define REG_PWM1_CMPVUPD6 (*(__O  uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */
00208   #define REG_PWM1_CMPM6    (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */
00209   #define REG_PWM1_CMPMUPD6 (*(__O  uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */
00210   #define REG_PWM1_CMPV7    (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */
00211   #define REG_PWM1_CMPVUPD7 (*(__O  uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */
00212   #define REG_PWM1_CMPM7    (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */
00213   #define REG_PWM1_CMPMUPD7 (*(__O  uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */
00214   #define REG_PWM1_CMR0     (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */
00215   #define REG_PWM1_CDTY0    (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */
00216   #define REG_PWM1_CDTYUPD0 (*(__O  uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */
00217   #define REG_PWM1_CPRD0    (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */
00218   #define REG_PWM1_CPRDUPD0 (*(__O  uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */
00219   #define REG_PWM1_CCNT0    (*(__I  uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */
00220   #define REG_PWM1_DT0      (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */
00221   #define REG_PWM1_DTUPD0   (*(__O  uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */
00222   #define REG_PWM1_CMR1     (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */
00223   #define REG_PWM1_CDTY1    (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */
00224   #define REG_PWM1_CDTYUPD1 (*(__O  uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */
00225   #define REG_PWM1_CPRD1    (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */
00226   #define REG_PWM1_CPRDUPD1 (*(__O  uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */
00227   #define REG_PWM1_CCNT1    (*(__I  uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */
00228   #define REG_PWM1_DT1      (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */
00229   #define REG_PWM1_DTUPD1   (*(__O  uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */
00230   #define REG_PWM1_CMR2     (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */
00231   #define REG_PWM1_CDTY2    (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */
00232   #define REG_PWM1_CDTYUPD2 (*(__O  uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */
00233   #define REG_PWM1_CPRD2    (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */
00234   #define REG_PWM1_CPRDUPD2 (*(__O  uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */
00235   #define REG_PWM1_CCNT2    (*(__I  uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */
00236   #define REG_PWM1_DT2      (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */
00237   #define REG_PWM1_DTUPD2   (*(__O  uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */
00238   #define REG_PWM1_CMR3     (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */
00239   #define REG_PWM1_CDTY3    (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */
00240   #define REG_PWM1_CDTYUPD3 (*(__O  uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */
00241   #define REG_PWM1_CPRD3    (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */
00242   #define REG_PWM1_CPRDUPD3 (*(__O  uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */
00243   #define REG_PWM1_CCNT3    (*(__I  uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */
00244   #define REG_PWM1_DT3      (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */
00245   #define REG_PWM1_DTUPD3   (*(__O  uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */
00246   #define REG_PWM1_CMUPD0   (*(__O  uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
00247   #define REG_PWM1_CMUPD1   (*(__O  uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
00248   #define REG_PWM1_ETRG1    (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */
00249   #define REG_PWM1_LEBR1    (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
00250   #define REG_PWM1_CMUPD2   (*(__O  uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
00251   #define REG_PWM1_ETRG2    (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */
00252   #define REG_PWM1_LEBR2    (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
00253   #define REG_PWM1_CMUPD3   (*(__O  uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
00254   #define REG_PWM1_ETRG3    (*(__IO uint32_t*)0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */
00255   #define REG_PWM1_LEBR3    (*(__IO uint32_t*)0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */
00256   #define REG_PWM1_ETRG4    (*(__IO uint32_t*)0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */
00257   #define REG_PWM1_LEBR4    (*(__IO uint32_t*)0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */
00258 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00259 
00260 #endif /* _SAMV71_PWM1_INSTANCE_ */
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Defines