SAMV71 Xplained Ultra Software Package 1.4

instance_tc0.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2014, Atmel Corporation                                        */
00006 /*                                                                              */
00007 /* All rights reserved.                                                         */
00008 /*                                                                              */
00009 /* Redistribution and use in source and binary forms, with or without           */
00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
00018 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
00028 /* ---------------------------------------------------------------------------- */
00029 
00030 #ifndef _SAMV71_TC0_INSTANCE_
00031 #define _SAMV71_TC0_INSTANCE_
00032 
00033 /* ========== Register definition for TC0 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_TC0_CCR0                   (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
00036   #define REG_TC0_CMR0                   (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
00037   #define REG_TC0_SMMR0                  (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
00038   #define REG_TC0_RAB0                   (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */
00039   #define REG_TC0_CV0                    (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */
00040   #define REG_TC0_RA0                    (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */
00041   #define REG_TC0_RB0                    (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */
00042   #define REG_TC0_RC0                    (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */
00043   #define REG_TC0_SR0                    (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */
00044   #define REG_TC0_IER0                   (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
00045   #define REG_TC0_IDR0                   (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
00046   #define REG_TC0_IMR0                   (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
00047   #define REG_TC0_EMR0                   (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
00048   #define REG_TC0_CCR1                   (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
00049   #define REG_TC0_CMR1                   (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
00050   #define REG_TC0_SMMR1                  (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
00051   #define REG_TC0_RAB1                   (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */
00052   #define REG_TC0_CV1                    (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */
00053   #define REG_TC0_RA1                    (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */
00054   #define REG_TC0_RB1                    (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */
00055   #define REG_TC0_RC1                    (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */
00056   #define REG_TC0_SR1                    (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */
00057   #define REG_TC0_IER1                   (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
00058   #define REG_TC0_IDR1                   (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
00059   #define REG_TC0_IMR1                   (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
00060   #define REG_TC0_EMR1                   (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
00061   #define REG_TC0_CCR2                   (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
00062   #define REG_TC0_CMR2                   (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
00063   #define REG_TC0_SMMR2                  (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
00064   #define REG_TC0_RAB2                   (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */
00065   #define REG_TC0_CV2                    (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */
00066   #define REG_TC0_RA2                    (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */
00067   #define REG_TC0_RB2                    (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */
00068   #define REG_TC0_RC2                    (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */
00069   #define REG_TC0_SR2                    (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */
00070   #define REG_TC0_IER2                   (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
00071   #define REG_TC0_IDR2                   (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
00072   #define REG_TC0_IMR2                   (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
00073   #define REG_TC0_EMR2                   (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
00074   #define REG_TC0_BCR                    (0x4000C0C0U) /**< \brief (TC0) Block Control Register */
00075   #define REG_TC0_BMR                    (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */
00076   #define REG_TC0_QIER                   (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
00077   #define REG_TC0_QIDR                   (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
00078   #define REG_TC0_QIMR                   (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
00079   #define REG_TC0_QISR                   (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
00080   #define REG_TC0_FMR                    (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */
00081   #define REG_TC0_WPMR                   (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */
00082 #else
00083   #define REG_TC0_CCR0  (*(__O  uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
00084   #define REG_TC0_CMR0  (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
00085   #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
00086   #define REG_TC0_RAB0  (*(__I  uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */
00087   #define REG_TC0_CV0   (*(__I  uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */
00088   #define REG_TC0_RA0   (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */
00089   #define REG_TC0_RB0   (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */
00090   #define REG_TC0_RC0   (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */
00091   #define REG_TC0_SR0   (*(__I  uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */
00092   #define REG_TC0_IER0  (*(__O  uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
00093   #define REG_TC0_IDR0  (*(__O  uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
00094   #define REG_TC0_IMR0  (*(__I  uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
00095   #define REG_TC0_EMR0  (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
00096   #define REG_TC0_CCR1  (*(__O  uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
00097   #define REG_TC0_CMR1  (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
00098   #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
00099   #define REG_TC0_RAB1  (*(__I  uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */
00100   #define REG_TC0_CV1   (*(__I  uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */
00101   #define REG_TC0_RA1   (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */
00102   #define REG_TC0_RB1   (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */
00103   #define REG_TC0_RC1   (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */
00104   #define REG_TC0_SR1   (*(__I  uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */
00105   #define REG_TC0_IER1  (*(__O  uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
00106   #define REG_TC0_IDR1  (*(__O  uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
00107   #define REG_TC0_IMR1  (*(__I  uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
00108   #define REG_TC0_EMR1  (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
00109   #define REG_TC0_CCR2  (*(__O  uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
00110   #define REG_TC0_CMR2  (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
00111   #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
00112   #define REG_TC0_RAB2  (*(__I  uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */
00113   #define REG_TC0_CV2   (*(__I  uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */
00114   #define REG_TC0_RA2   (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */
00115   #define REG_TC0_RB2   (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */
00116   #define REG_TC0_RC2   (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */
00117   #define REG_TC0_SR2   (*(__I  uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */
00118   #define REG_TC0_IER2  (*(__O  uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
00119   #define REG_TC0_IDR2  (*(__O  uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
00120   #define REG_TC0_IMR2  (*(__I  uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
00121   #define REG_TC0_EMR2  (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
00122   #define REG_TC0_BCR   (*(__O  uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */
00123   #define REG_TC0_BMR   (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */
00124   #define REG_TC0_QIER  (*(__O  uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
00125   #define REG_TC0_QIDR  (*(__O  uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
00126   #define REG_TC0_QIMR  (*(__I  uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
00127   #define REG_TC0_QISR  (*(__I  uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
00128   #define REG_TC0_FMR   (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */
00129   #define REG_TC0_WPMR  (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */
00130 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00131 
00132 #endif /* _SAMV71_TC0_INSTANCE_ */
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Defines