SAMV71 Xplained Ultra Software Package 1.4

startup_sam.c

00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2011, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00024  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 
00031 #include "samv71.h"
00032 
00033 typedef void (*intfunc) (void);
00034 typedef union { intfunc __fun; void * __ptr; } intvec_elem;
00035 
00036 void __iar_program_start(void);
00037 int __low_level_init(void);
00038 
00039 /* Default empty handler */
00040 void Dummy_Handler(void);
00041 
00042 /* Cortex-M4 core handlers */
00043 #pragma weak NMI_Handler=Dummy_Handler
00044 #pragma weak HardFault_Handler=Dummy_Handler
00045 #pragma weak MemManage_Handler=Dummy_Handler
00046 #pragma weak BusFault_Handler=Dummy_Handler
00047 #pragma weak UsageFault_Handler=Dummy_Handler
00048 #pragma weak SVC_Handler=Dummy_Handler
00049 #pragma weak DebugMon_Handler=Dummy_Handler
00050 #pragma weak PendSV_Handler=Dummy_Handler
00051 #pragma weak SysTick_Handler=Dummy_Handler
00052 
00053 /* Peripherals handlers */
00054 #pragma weak SUPC_Handler=Dummy_Handler
00055 #pragma weak RSTC_Handler=Dummy_Handler
00056 #pragma weak RTC_Handler=Dummy_Handler
00057 #pragma weak RTT_Handler=Dummy_Handler
00058 #pragma weak WDT_Handler=Dummy_Handler
00059 #pragma weak PMC_Handler=Dummy_Handler
00060 #pragma weak EFC_Handler=Dummy_Handler
00061 #pragma weak UART0_Handler=Dummy_Handler
00062 #pragma weak UART1_Handler=Dummy_Handler
00063 #pragma weak PIOA_Handler=Dummy_Handler
00064 #pragma weak PIOB_Handler=Dummy_Handler
00065 
00066 #ifdef _SAMV71_PIOC_INSTANCE_
00067 #pragma weak PIOC_Handler=Dummy_Handler
00068 #endif /* _SAMV71_PIOC_INSTANCE_ */
00069 
00070 #pragma weak USART0_Handler=Dummy_Handler
00071 #pragma weak USART1_Handler=Dummy_Handler
00072 #pragma weak USART2_Handler=Dummy_Handler
00073 #pragma weak PIOD_Handler=Dummy_Handler
00074 
00075 #ifdef _SAMV71_PIOE_INSTANCE_
00076 #pragma weak PIOE_Handler=Dummy_Handler
00077 #endif /* _SAMV71_PIOE_INSTANCE_ */
00078 
00079 #ifdef _SAMV71_HSMCI_INSTANCE_
00080 #pragma weak HSMCI_Handler=Dummy_Handler
00081 #endif /* _SAMV71_HSMCI_INSTANCE_ */
00082 
00083 #pragma weak TWIHS0_Handler=Dummy_Handler
00084 #pragma weak TWIHS1_Handler=Dummy_Handler
00085 #pragma weak SPI0_Handler=Dummy_Handler
00086 #pragma weak SSC_Handler=Dummy_Handler
00087 #pragma weak TC0_Handler=Dummy_Handler
00088 #pragma weak TC1_Handler=Dummy_Handler
00089 #pragma weak TC2_Handler=Dummy_Handler
00090 
00091 #ifdef _SAMV71_TC1_INSTANCE_
00092 #pragma weak TC3_Handler=Dummy_Handler
00093 #endif /* _SAMV71_TC1_INSTANCE_ */
00094 #ifdef _SAMV71_TC1_INSTANCE_
00095 #pragma weak TC4_Handler=Dummy_Handler
00096 #endif /* _SAMV71_TC1_INSTANCE_ */
00097 #ifdef _SAMV71_TC1_INSTANCE_
00098 #pragma weak TC5_Handler=Dummy_Handler
00099 #endif /* _SAMV71_TC1_INSTANCE_ */
00100 
00101 #pragma weak AFEC0_Handler=Dummy_Handler
00102 
00103 #ifdef _SAMV71_DACC_INSTANCE_
00104 #pragma weak DACC_Handler=Dummy_Handler
00105 #endif /* _SAMV71_DACC_INSTANCE_ */
00106 
00107 #pragma weak PWM0_Handler=Dummy_Handler
00108 #pragma weak ICM_Handler=Dummy_Handler
00109 #pragma weak ACC_Handler=Dummy_Handler
00110 #pragma weak USBHS_Handler=Dummy_Handler
00111 #pragma weak MCAN0_Handler=Dummy_Handler
00112 #pragma weak MCAN0_Line1_Handler=Dummy_Handler
00113 #pragma weak MCAN1_Handler=Dummy_Handler
00114 #pragma weak MCAN1_Line1_Handler=Dummy_Handler
00115 #pragma weak GMAC_Handler=Dummy_Handler
00116 #pragma weak GMACQ1_Handler=Dummy_Handler
00117 #pragma weak GMACQ2_Handler=Dummy_Handler
00118 #pragma weak AFEC1_Handler=Dummy_Handler
00119 
00120 #ifdef _SAMV71_TWIHS2_INSTANCE_
00121 #pragma weak TWIHS2_Handler=Dummy_Handler
00122 #endif /* _SAMV71_TWI2_INSTANCE_ */
00123 
00124 #pragma weak SPI1_Handler=Dummy_Handler
00125 #pragma weak QSPI_Handler=Dummy_Handler
00126 #pragma weak UART2_Handler=Dummy_Handler
00127 #pragma weak UART3_Handler=Dummy_Handler
00128 #pragma weak UART4_Handler=Dummy_Handler
00129 
00130 #ifdef _SAMV71_TC2_INSTANCE_
00131 #pragma weak TC6_Handler=Dummy_Handler
00132 #endif /* _SAMV71_TC2_INSTANCE_ */
00133 
00134 #ifdef _SAMV71_TC2_INSTANCE_
00135 #pragma weak TC7_Handler=Dummy_Handler
00136 #endif /* _SAMV71_TC2_INSTANCE_ */
00137 
00138 #ifdef _SAMV71_TC2_INSTANCE_
00139 #pragma weak TC8_Handler=Dummy_Handler
00140 #endif /* _SAMV71_TC2_INSTANCE_ */
00141 
00142 #pragma weak TC9_Handler=Dummy_Handler
00143 #pragma weak TC10_Handler=Dummy_Handler
00144 #pragma weak TC11_Handler=Dummy_Handler
00145 #pragma weak MLB_Handler=Dummy_Handler
00146 #pragma weak AES_Handler=Dummy_Handler
00147 #pragma weak TRNG_Handler=Dummy_Handler
00148 #pragma weak XDMAC_Handler=Dummy_Handler
00149 #pragma weak ISI_Handler=Dummy_Handler
00150 #pragma weak PWM1_Handler=Dummy_Handler
00151 #pragma weak FPU_Handler=Dummy_Handler
00152 
00153 #ifdef _SAMV71_SDRAMC_INSTANCE_
00154 #pragma weak SDRAMC_Handler=Dummy_Handler
00155 #endif /* _SAMV71_SDRAMC_INSTANCE_ */
00156 
00157 #pragma weak RSWDT_Handler=Dummy_Handler
00158 #pragma weak CCF_Handler=Dummy_Handler
00159 #pragma weak CCW_Handler=Dummy_Handler
00160 
00161 /* Exception Table */
00162 #pragma language = extended
00163 #pragma segment = "CSTACK"
00164 
00165 /* The name "__vector_table" has special meaning for C-SPY: */
00166 /* it is where the SP start value is found, and the NVIC vector */
00167 /* table register (VTOR) is initialized to this address if != 0 */
00168 
00169 #pragma section = ".intvec"
00170 #pragma location = ".intvec"
00171 const intvec_elem __vector_table[] =
00172 {
00173     { .__ptr = __sfe( "CSTACK" ) },
00174     __iar_program_start,
00175     NMI_Handler,
00176     HardFault_Handler,
00177     MemManage_Handler,
00178     BusFault_Handler,
00179     UsageFault_Handler,
00180     (0UL), (0UL), (0UL), (0UL),          /* Reserved */
00181     SVC_Handler,
00182     DebugMon_Handler,
00183     (0UL),          /* Reserved */
00184     PendSV_Handler,
00185     SysTick_Handler,
00186 
00187     SUPC_Handler,   /* 0  Supply Controller */
00188     RSTC_Handler,   /* 1  Reset Controller */
00189     RTC_Handler,    /* 2  Real Time Clock */
00190     RTT_Handler,    /* 3  Real Time Timer */
00191     WDT_Handler,    /* 4  Watchdog Timer 0 */
00192     PMC_Handler,    /* 5  Power Management Controller */
00193     EFC_Handler,    /* 6  Enhanced Embedded Flash Controller */
00194     UART0_Handler,  /* 7  UART 0 */
00195     UART1_Handler,  /* 8  UART 1 */
00196     (0UL),          /* 9  Reserved */
00197     PIOA_Handler,   /* 10 Parallel I/O Controller A */
00198     PIOB_Handler,   /* 11 Parallel I/O Controller B */
00199     PIOC_Handler,   /* 12 Parallel I/O Controller C */
00200     USART0_Handler, /* 13 USART 0 */
00201     USART1_Handler, /* 14 USART 1 */
00202     USART2_Handler, /* 15 USART 2 */
00203     PIOD_Handler,   /* 16 Parallel I/O Controller D */
00204     PIOE_Handler,   /* 17 Parallel I/O Controller E */    
00205     HSMCI_Handler,  /* 18 Multimedia Card Interface */
00206     TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */
00207     TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */
00208     SPI0_Handler,   /* 21 Serial Peripheral Interface 0 */
00209     SSC_Handler,    /* 22 Synchronous Serial Controller */
00210     TC0_Handler,    /* 23 Timer/Counter 0 */
00211     TC1_Handler,    /* 24 Timer/Counter 1 */
00212     TC2_Handler,    /* 25 Timer/Counter 2 */
00213     TC3_Handler,    /* 26 Timer/Counter 3 */
00214     TC4_Handler,    /* 27 Timer/Counter 4 */
00215     TC5_Handler,    /* 28 Timer/Counter 5 */
00216     AFEC0_Handler,  /* 29 Analog Front End 0 */
00217     DACC_Handler,   /* 30 Digital To Analog Converter */
00218     PWM0_Handler,   /* 31 Pulse Width Modulation 0 */
00219     ICM_Handler,    /* 32 Integrity Check Monitor */
00220     ACC_Handler,    /* 33 Analog Comparator */
00221     USBHS_Handler,  /* 34 USB Host / Device Controller */
00222     MCAN0_Handler,  /* 35 CAN Controller 0 */
00223     MCAN0_Line1_Handler,  /* 36 CAN Controller 0 - Line 1 */
00224     MCAN1_Handler,  /* 37 CAN Controller 1 */
00225     MCAN1_Line1_Handler,  /* 38 CAN Controller 1 - Line 1 */
00226     GMAC_Handler,   /* 39 Ethernet MAC */
00227     AFEC1_Handler,  /* 40 Analog Front End 1 */
00228     TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */
00229     SPI1_Handler,   /* 42 Serial Peripheral Interface 1 */
00230     QSPI_Handler,   /* 43 Quad I/O Serial Peripheral Interface */
00231     UART2_Handler,  /* 44 UART 2 */
00232     UART3_Handler,  /* 45 UART 3 */
00233     UART4_Handler,  /* 46 UART 4 */
00234     TC6_Handler,    /* 47 Timer/Counter 6 */
00235     TC7_Handler,    /* 48 Timer/Counter 7 */
00236     TC8_Handler,    /* 49 Timer/Counter 8 */
00237     TC9_Handler,    /* 50 Timer/Counter 9 */
00238     TC10_Handler,   /* 51 Timer/Counter 10 */
00239     TC11_Handler,   /* 52 Timer/Counter 11 */
00240     MLB_Handler,    /* 53 MediaLB */
00241     (0UL),          /* 54 Reserved */
00242     (0UL),          /* 55 Reserved */
00243     AES_Handler,    /* 56 AES */
00244     TRNG_Handler,   /* 57 True Random Generator */
00245     XDMAC_Handler,  /* 58 DMA */
00246     ISI_Handler,    /* 59 Camera Interface */
00247     PWM1_Handler,   /* 60 Pulse Width Modulation 1 */
00248     (0UL),          /* 61 Reserved */
00249     SDRAMC_Handler, /* 62 SDRAM Controller */
00250     RSWDT_Handler,   /* 63 Watchdog Timer 1 */
00251   
00252 };
00253 
00254 void LowLevelInit(void);
00255 
00256 #ifdef ENABLE_TCM 
00257 /** \brief  TCM memory enable
00258 
00259     The function enables TCM memories
00260  */
00261 __STATIC_INLINE void TCM_Enable(void) 
00262 {
00263 
00264     __DSB();
00265     __ISB();
00266     SCB->ITCMCR = (SCB_ITCMCR_EN_Msk  | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk);
00267     SCB->DTCMCR = ( SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk);
00268     __DSB();
00269     __ISB();
00270 }
00271 #endif
00272 
00273 /** \brief  TCM memory Disable
00274 
00275     The function enables TCM memories
00276  */
00277 __STATIC_INLINE void TCM_Disable(void) 
00278 {
00279 
00280     __DSB();
00281     __ISB();
00282     SCB->ITCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk;
00283     SCB->DTCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk;
00284     __DSB();
00285     __ISB();
00286 }
00287 /**------------------------------------------------------------------------------
00288  * This is the code that gets called on processor reset. To initialize the
00289  * device.
00290  *------------------------------------------------------------------------------*/
00291 int __low_level_init(void)
00292 {
00293   
00294   uint32_t *pSrc = __section_begin(".intvec");    
00295   SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
00296       
00297 #ifdef ENABLE_TCM 
00298 #ifndef FFT_DEMO
00299   // 32 Kb
00300     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
00301 #else
00302     // 128 Kb
00303     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
00304 #endif
00305     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
00306 
00307     TCM_Enable();
00308 #else
00309     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
00310     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
00311     
00312     TCM_Disable();
00313 #endif
00314   LowLevelInit();
00315   return 1; /* if return 0, the data sections will not be initialized */
00316 }
00317 
00318 
00319 /**
00320  * \brief Default interrupt handler for unused IRQs.
00321  */
00322 void Dummy_Handler(void)
00323 {
00324         while (1) {
00325         }
00326 }
00327 
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