SAMV71 Xplained Ultra Software Package 1.5

instance_usart1.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_USART1_INSTANCE_
00031 #define _SAMV71_USART1_INSTANCE_
00032 
00033 /* ========== Register definition for USART1 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_USART1_CR                        (0x40028000U) /**< \brief (USART1) Control Register */
00036   #define REG_USART1_MR                        (0x40028004U) /**< \brief (USART1) Mode Register */
00037   #define REG_USART1_IER                       (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
00038   #define REG_USART1_IDR                       (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
00039   #define REG_USART1_IMR                       (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
00040   #define REG_USART1_CSR                       (0x40028014U) /**< \brief (USART1) Channel Status Register */
00041   #define REG_USART1_RHR                       (0x40028018U) /**< \brief (USART1) Receive Holding Register */
00042   #define REG_USART1_THR                       (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
00043   #define REG_USART1_BRGR                      (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
00044   #define REG_USART1_RTOR                      (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
00045   #define REG_USART1_TTGR                      (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
00046   #define REG_USART1_FIDI                      (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
00047   #define REG_USART1_NER                       (0x40028044U) /**< \brief (USART1) Number of Errors Register */
00048   #define REG_USART1_IF                        (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
00049   #define REG_USART1_MAN                       (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
00050   #define REG_USART1_LINMR                     (0x40028054U) /**< \brief (USART1) LIN Mode Register */
00051   #define REG_USART1_LINIR                     (0x40028058U) /**< \brief (USART1) LIN Identifier Register */
00052   #define REG_USART1_LINBRR                    (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
00053   #define REG_USART1_LONMR                     (0x40028060U) /**< \brief (USART1) LON Mode Register */
00054   #define REG_USART1_LONPR                     (0x40028064U) /**< \brief (USART1) LON Preamble Register */
00055   #define REG_USART1_LONDL                     (0x40028068U) /**< \brief (USART1) LON Data Length Register */
00056   #define REG_USART1_LONL2HDR                  (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
00057   #define REG_USART1_LONBL                     (0x40028070U) /**< \brief (USART1) LON Backlog Register */
00058   #define REG_USART1_LONB1TX                   (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
00059   #define REG_USART1_LONB1RX                   (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
00060   #define REG_USART1_LONPRIO                   (0x4002807CU) /**< \brief (USART1) LON Priority Register */
00061   #define REG_USART1_IDTTX                     (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
00062   #define REG_USART1_IDTRX                     (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
00063   #define REG_USART1_ICDIFF                    (0x40028088U) /**< \brief (USART1) IC DIFF Register */
00064   #define REG_USART1_WPMR                      (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
00065   #define REG_USART1_WPSR                      (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
00066   #define REG_USART1_VERSION                   (0x400280FCU) /**< \brief (USART1) Version Register */
00067 #else
00068   #define REG_USART1_CR       (*(__O  uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */
00069   #define REG_USART1_MR       (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */
00070   #define REG_USART1_IER      (*(__O  uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */
00071   #define REG_USART1_IDR      (*(__O  uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */
00072   #define REG_USART1_IMR      (*(__I  uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */
00073   #define REG_USART1_CSR      (*(__I  uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */
00074   #define REG_USART1_RHR      (*(__I  uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */
00075   #define REG_USART1_THR      (*(__O  uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */
00076   #define REG_USART1_BRGR     (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */
00077   #define REG_USART1_RTOR     (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */
00078   #define REG_USART1_TTGR     (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */
00079   #define REG_USART1_FIDI     (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */
00080   #define REG_USART1_NER      (*(__I  uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */
00081   #define REG_USART1_IF       (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */
00082   #define REG_USART1_MAN      (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */
00083   #define REG_USART1_LINMR    (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */
00084   #define REG_USART1_LINIR    (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */
00085   #define REG_USART1_LINBRR   (*(__I  uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */
00086   #define REG_USART1_LONMR    (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */
00087   #define REG_USART1_LONPR    (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */
00088   #define REG_USART1_LONDL    (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */
00089   #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */
00090   #define REG_USART1_LONBL    (*(__I  uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */
00091   #define REG_USART1_LONB1TX  (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */
00092   #define REG_USART1_LONB1RX  (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */
00093   #define REG_USART1_LONPRIO  (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */
00094   #define REG_USART1_IDTTX    (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */
00095   #define REG_USART1_IDTRX    (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */
00096   #define REG_USART1_ICDIFF   (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */
00097   #define REG_USART1_WPMR     (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */
00098   #define REG_USART1_WPSR     (*(__I  uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */
00099   #define REG_USART1_VERSION  (*(__I  uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */
00100 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00101 
00102 #endif /* _SAMV71_USART1_INSTANCE_ */
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