SAMV71 Xplained Ultra Software Package 1.5

xdmad.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _XDMAD_H
00031 #define _XDMAD_H
00032 
00033 
00034 /*----------------------------------------------------------------------------
00035  *        Includes
00036  *----------------------------------------------------------------------------*/
00037 
00038 #include "chip.h"
00039 #include <assert.h>
00040 
00041 
00042 /** \addtogroup dmad_defines DMA Driver Defines
00043         @{*/
00044 /*----------------------------------------------------------------------------
00045  *        Consts
00046  *----------------------------------------------------------------------------*/
00047 #define XDMAD_TRANSFER_MEMORY  0xFF   /**< DMA transfer from or to memory */
00048 #define XDMAD_ALLOC_FAILED     0xFFFF /**< Channel allocate failed */
00049 
00050 #define XDMAD_TRANSFER_TX      0
00051 #define XDMAD_TRANSFER_RX      1
00052 
00053 /* XDMA_MBR_UBC */
00054 #define XDMA_UBC_NDE (0x1u << 24)
00055 #define   XDMA_UBC_NDE_FETCH_DIS (0x0u << 24)
00056 #define   XDMA_UBC_NDE_FETCH_EN  (0x1u << 24)
00057 #define XDMA_UBC_NSEN (0x1u << 25)
00058 #define   XDMA_UBC_NSEN_UNCHANGED (0x0u << 25)
00059 #define   XDMA_UBC_NSEN_UPDATED (0x1u << 25)
00060 #define XDMA_UBC_NDEN (0x1u << 26)
00061 #define   XDMA_UBC_NDEN_UNCHANGED (0x0u << 26)
00062 #define   XDMA_UBC_NDEN_UPDATED (0x1u << 26)
00063 #define XDMA_UBC_NVIEW_Pos 27
00064 #define    XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos)
00065 #define    XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos)
00066 #define    XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos)
00067 #define    XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos)
00068 #define    XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos)
00069 
00070 /*----------------------------------------------------------------------------
00071  *        MACRO
00072  *----------------------------------------------------------------------------*/
00073 
00074 /**     @}*/
00075 
00076 /*----------------------------------------------------------------------------
00077  *        Types
00078  *----------------------------------------------------------------------------*/
00079 /** \addtogroup dmad_structs DMA Driver Structs
00080         @{*/
00081 
00082 /** DMA status or return code */
00083 typedef enum _XdmadStatus {
00084     XDMAD_OK = 0,        /**< Operation is successful */
00085     XDMAD_PARTIAL_DONE,
00086     XDMAD_DONE,
00087     XDMAD_BUSY,          /**< Channel occupied or transfer not finished */
00088     XDMAD_ERROR,         /**< Operation failed */
00089     XDMAD_CANCELED       /**< Operation cancelled */
00090 } eXdmadStatus, eXdmadRC;
00091 
00092 /** DMA state for channel */
00093 typedef enum _XdmadState {
00094     XDMAD_STATE_FREE = 0,      /**< Free channel */
00095     XDMAD_STATE_ALLOCATED,     /**< Allocated to some peripheral */
00096     XDMAD_STATE_START,         /**< DMA started */
00097     XDMAD_STATE_IN_XFR,        /**< DMA in transferring */
00098     XDMAD_STATE_DONE,          /**< DMA transfer done */
00099     XDMAD_STATE_HALTED,        /**< DMA transfer stopped */
00100 } eXdmadState;
00101 
00102 /** DMA Programming state for channel */
00103 typedef enum _XdmadProgState {
00104     XDMAD_SINGLE = 0,
00105     XDMAD_MULTI,
00106     XDMAD_LLI,
00107 } eXdmadProgState;
00108 
00109 /** DMA transfer callback */
00110 typedef void (*XdmadTransferCallback)(uint32_t Channel, void *pArg);
00111 
00112 /** DMA driver channel */
00113 typedef struct _XdmadChannel {
00114     XdmadTransferCallback fCallback; /**< Callback */
00115     void *pArg;                     /**< Callback argument */
00116     uint8_t bIrqOwner;              /**< Uses DMA handler or external one */
00117     uint8_t bSrcPeriphID;           /**< HW ID for source */
00118     uint8_t bDstPeriphID;           /**< HW ID for destination */
00119     uint8_t bSrcTxIfID;             /**< DMA Tx Interface ID for source */
00120     uint8_t bSrcRxIfID;             /**< DMA Rx Interface ID for source */
00121     uint8_t bDstTxIfID;             /**< DMA Tx Interface ID for destination */
00122     uint8_t bDstRxIfID;             /**< DMA Rx Interface ID for destination */
00123     volatile uint8_t state;         /**< DMA channel state */
00124 } sXdmadChannel;
00125 
00126 /** DMA driver instance */
00127 typedef struct _Xdmad {
00128     Xdmac *pXdmacs;
00129     sXdmadChannel XdmaChannels[XDMACCHID_NUMBER];
00130     uint8_t  numControllers;
00131     uint8_t  numChannels;
00132     uint8_t  pollingMode;
00133     uint8_t  pollingTimeout;
00134     uint8_t  xdmaMutex;
00135 } sXdmad;
00136 
00137 typedef struct _XdmadCfg {
00138     /** Microblock Control Member. */
00139     uint32_t mbr_ubc;
00140     /** Source Address Member. */
00141     uint32_t mbr_sa;
00142     /** Destination Address Member. */
00143     uint32_t mbr_da;
00144     /** Configuration Register. */
00145     uint32_t mbr_cfg;
00146     /** Block Control Member. */
00147     uint32_t mbr_bc;
00148     /** Data Stride Member. */
00149     uint32_t mbr_ds;
00150     /** Source Microblock Stride Member. */
00151     uint32_t mbr_sus;
00152     /** Destination Microblock Stride Member. */
00153     uint32_t mbr_dus;
00154 } sXdmadCfg;
00155 
00156 /** \brief Structure for storing parameters for DMA view0 that can be
00157  * performed by the DMA Master transfer.*/
00158 typedef struct _LinkedListDescriporView0 {
00159     /** Next Descriptor Address number. */
00160     uint32_t mbr_nda;
00161     /** Microblock Control Member. */
00162     uint32_t mbr_ubc;
00163     /** Transfer Address Member. */
00164     uint32_t mbr_ta;
00165 } LinkedListDescriporView0;
00166 
00167 /** \brief Structure for storing parameters for DMA view1 that can be
00168  * performed by the DMA Master transfer.*/
00169 typedef struct _LinkedListDescriporView1 {
00170     /** Next Descriptor Address number. */
00171     uint32_t mbr_nda;
00172     /** Microblock Control Member. */
00173     uint32_t mbr_ubc;
00174     /** Source Address Member. */
00175     uint32_t mbr_sa;
00176     /** Destination Address Member. */
00177     uint32_t mbr_da;
00178 } LinkedListDescriporView1;
00179 
00180 /** \brief Structure for storing parameters for DMA view2 that can be
00181  * performed by the DMA Master transfer.*/
00182 typedef struct _LinkedListDescriporView2 {
00183     /** Next Descriptor Address number. */
00184     uint32_t mbr_nda;
00185     /** Microblock Control Member. */
00186     uint32_t mbr_ubc;
00187     /** Source Address Member. */
00188     uint32_t mbr_sa;
00189     /** Destination Address Member. */
00190     uint32_t mbr_da;
00191     /** Configuration Register. */
00192     uint32_t mbr_cfg;
00193 } LinkedListDescriporView2;
00194 
00195 /** \brief Structure for storing parameters for DMA view3 that can be
00196  * performed by the DMA Master transfer.*/
00197 typedef struct _LinkedListDescriporView3 {
00198     /** Next Descriptor Address number. */
00199     uint32_t mbr_nda;
00200     /** Microblock Control Member. */
00201     uint32_t mbr_ubc;
00202     /** Source Address Member. */
00203     uint32_t mbr_sa;
00204     /** Destination Address Member. */
00205     uint32_t mbr_da;
00206     /** Configuration Register. */
00207     uint32_t mbr_cfg;
00208     /** Block Control Member. */
00209     uint32_t mbr_bc;
00210     /** Data Stride Member. */
00211     uint32_t mbr_ds;
00212     /** Source Microblock Stride Member. */
00213     uint32_t mbr_sus;
00214     /** Destination Microblock Stride Member. */
00215     uint32_t mbr_dus;
00216 } LinkedListDescriporView3;
00217 
00218 /**     @}*/
00219 
00220 /*----------------------------------------------------------------------------
00221  *        Exported functions
00222  *----------------------------------------------------------------------------*/
00223 /** \addtogroup dmad_functions DMA Driver Functions
00224         @{*/
00225 extern void XDMAD_Initialize(sXdmad *pXdmad,
00226                               uint8_t bPollingMode);
00227 
00228 extern void XDMAD_Handler(sXdmad *pDmad);
00229 
00230 extern uint32_t XDMAD_AllocateChannel(sXdmad *pXdmad,
00231                                        uint8_t bSrcID, uint8_t bDstID);
00232 extern eXdmadRC XDMAD_FreeChannel(sXdmad *pXdmad, uint32_t dwChannel);
00233 
00234 extern eXdmadRC XDMAD_ConfigureTransfer(sXdmad *pXdmad,
00235         uint32_t dwChannel,
00236         sXdmadCfg *pXdmaParam,
00237         uint32_t dwXdmaDescCfg,
00238         uint32_t dwXdmaDescAddr,
00239         uint32_t dwXdmaIntEn);
00240 
00241 extern eXdmadRC XDMAD_PrepareChannel(sXdmad *pXdmad, uint32_t dwChannel);
00242 
00243 extern eXdmadRC XDMAD_IsTransferDone(sXdmad *pXdmad, uint32_t dwChannel);
00244 
00245 extern eXdmadRC XDMAD_StartTransfer(sXdmad *pXdmad, uint32_t dwChannel);
00246 
00247 extern eXdmadRC XDMAD_SetCallback(sXdmad *pXdmad,
00248                                    uint32_t dwChannel,
00249                                    XdmadTransferCallback fCallback,
00250                                    void *pArg);
00251 
00252 extern eXdmadRC XDMAD_StopTransfer(sXdmad *pXdmad, uint32_t dwChannel);
00253 /**     @}*/
00254 /**@}*/
00255 #endif //#ifndef _XDMAD_H
00256 
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