SAMV71 Xplained Ultra Software Package 1.5

instance_tc3.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_TC3_INSTANCE_
00031 #define _SAMV71_TC3_INSTANCE_
00032 
00033 /* ========== Register definition for TC3 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_TC3_CCR0                   (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */
00036   #define REG_TC3_CMR0                   (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */
00037   #define REG_TC3_SMMR0                  (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */
00038   #define REG_TC3_RAB0                   (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */
00039   #define REG_TC3_CV0                    (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */
00040   #define REG_TC3_RA0                    (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */
00041   #define REG_TC3_RB0                    (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */
00042   #define REG_TC3_RC0                    (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */
00043   #define REG_TC3_SR0                    (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */
00044   #define REG_TC3_IER0                   (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */
00045   #define REG_TC3_IDR0                   (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */
00046   #define REG_TC3_IMR0                   (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */
00047   #define REG_TC3_EMR0                   (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */
00048   #define REG_TC3_CCR1                   (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */
00049   #define REG_TC3_CMR1                   (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */
00050   #define REG_TC3_SMMR1                  (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */
00051   #define REG_TC3_RAB1                   (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */
00052   #define REG_TC3_CV1                    (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */
00053   #define REG_TC3_RA1                    (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */
00054   #define REG_TC3_RB1                    (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */
00055   #define REG_TC3_RC1                    (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */
00056   #define REG_TC3_SR1                    (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */
00057   #define REG_TC3_IER1                   (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */
00058   #define REG_TC3_IDR1                   (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */
00059   #define REG_TC3_IMR1                   (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */
00060   #define REG_TC3_EMR1                   (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */
00061   #define REG_TC3_CCR2                   (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */
00062   #define REG_TC3_CMR2                   (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */
00063   #define REG_TC3_SMMR2                  (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */
00064   #define REG_TC3_RAB2                   (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */
00065   #define REG_TC3_CV2                    (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */
00066   #define REG_TC3_RA2                    (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */
00067   #define REG_TC3_RB2                    (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */
00068   #define REG_TC3_RC2                    (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */
00069   #define REG_TC3_SR2                    (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */
00070   #define REG_TC3_IER2                   (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */
00071   #define REG_TC3_IDR2                   (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */
00072   #define REG_TC3_IMR2                   (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */
00073   #define REG_TC3_EMR2                   (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */
00074   #define REG_TC3_BCR                    (0x400540C0U) /**< \brief (TC3) Block Control Register */
00075   #define REG_TC3_BMR                    (0x400540C4U) /**< \brief (TC3) Block Mode Register */
00076   #define REG_TC3_QIER                   (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */
00077   #define REG_TC3_QIDR                   (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */
00078   #define REG_TC3_QIMR                   (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */
00079   #define REG_TC3_QISR                   (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */
00080   #define REG_TC3_FMR                    (0x400540D8U) /**< \brief (TC3) Fault Mode Register */
00081   #define REG_TC3_WPMR                   (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */
00082   #define REG_TC3_VER                    (0x400540FCU) /**< \brief (TC3) Version Register */
00083 #else
00084   #define REG_TC3_CCR0  (*(__O  uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */
00085   #define REG_TC3_CMR0  (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */
00086   #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */
00087   #define REG_TC3_RAB0  (*(__I  uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */
00088   #define REG_TC3_CV0   (*(__I  uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */
00089   #define REG_TC3_RA0   (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */
00090   #define REG_TC3_RB0   (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */
00091   #define REG_TC3_RC0   (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */
00092   #define REG_TC3_SR0   (*(__I  uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */
00093   #define REG_TC3_IER0  (*(__O  uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */
00094   #define REG_TC3_IDR0  (*(__O  uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */
00095   #define REG_TC3_IMR0  (*(__I  uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */
00096   #define REG_TC3_EMR0  (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */
00097   #define REG_TC3_CCR1  (*(__O  uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */
00098   #define REG_TC3_CMR1  (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */
00099   #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */
00100   #define REG_TC3_RAB1  (*(__I  uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */
00101   #define REG_TC3_CV1   (*(__I  uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */
00102   #define REG_TC3_RA1   (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */
00103   #define REG_TC3_RB1   (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */
00104   #define REG_TC3_RC1   (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */
00105   #define REG_TC3_SR1   (*(__I  uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */
00106   #define REG_TC3_IER1  (*(__O  uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */
00107   #define REG_TC3_IDR1  (*(__O  uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */
00108   #define REG_TC3_IMR1  (*(__I  uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */
00109   #define REG_TC3_EMR1  (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */
00110   #define REG_TC3_CCR2  (*(__O  uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */
00111   #define REG_TC3_CMR2  (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */
00112   #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */
00113   #define REG_TC3_RAB2  (*(__I  uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */
00114   #define REG_TC3_CV2   (*(__I  uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */
00115   #define REG_TC3_RA2   (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */
00116   #define REG_TC3_RB2   (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */
00117   #define REG_TC3_RC2   (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */
00118   #define REG_TC3_SR2   (*(__I  uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */
00119   #define REG_TC3_IER2  (*(__O  uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */
00120   #define REG_TC3_IDR2  (*(__O  uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */
00121   #define REG_TC3_IMR2  (*(__I  uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */
00122   #define REG_TC3_EMR2  (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */
00123   #define REG_TC3_BCR   (*(__O  uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */
00124   #define REG_TC3_BMR   (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */
00125   #define REG_TC3_QIER  (*(__O  uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */
00126   #define REG_TC3_QIDR  (*(__O  uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */
00127   #define REG_TC3_QIMR  (*(__I  uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */
00128   #define REG_TC3_QISR  (*(__I  uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */
00129   #define REG_TC3_FMR   (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */
00130   #define REG_TC3_WPMR  (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */
00131   #define REG_TC3_VER   (*(__I  uint32_t*)0x400540FCU) /**< \brief (TC3) Version Register */
00132 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00133 
00134 #endif /* _SAMV71_TC3_INSTANCE_ */
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