SAMV71 Xplained Ultra Software Package 1.5

usbhs.h

Go to the documentation of this file.
00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2015, Atmel Corporation                                        */
00006 /*                                                                              */
00007 /* All rights reserved.                                                         */
00008 /*                                                                              */
00009 /* Redistribution and use in source and binary forms, with or without           */
00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
00018 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,  */
00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
00028 /* ---------------------------------------------------------------------------- */
00029 
00030 /** \file */
00031 
00032 #ifndef USBHS_H
00033 #define USBHS_H
00034 /** addtogroup usbd_hal
00035  *@{
00036  */
00037 
00038 #define  USB_DEVICE_HS_SUPPORT
00039 
00040 //! Control endpoint size
00041 #define  USB_DEVICE_EP_CTRL_SIZE       64
00042 
00043 /** Indicates chip has an UDP High Speed. */
00044 #define CHIP_USB_UDP
00045 
00046 /** Indicates chip has an internal pull-up. */
00047 #define CHIP_USB_PULLUP_INTERNAL
00048 
00049 /** Number of USB endpoints */
00050 #define CHIP_USB_NUMENDPOINTS   10
00051 
00052 /** Endpoints max packet size */
00053 #define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \
00054     ((ep == 0) ? 64 : 1024)
00055 
00056 /** Endpoints Number of Bank */
00057 #define CHIP_USB_ENDPOINTS_BANKS(ep)            ((ep==0)?1:((ep<=2)?3:2))
00058 
00059 
00060 #define CHIP_USB_ENDPOINTS_HBW(ep)               ((((ep)>=1) &&((ep)<=2))?true:false)
00061 
00062 /** Endpoints DMA support */
00063 #define CHIP_USB_ENDPOINTS_DMA(ep)              ((((ep)>=1)&&((ep)<=7))?true:false)
00064 
00065 /** Max size of the FMA FIFO */
00066 #define DMA_MAX_FIFO_SIZE     (65536/1)
00067 /** fifo space size in DW */
00068 #define EPT_VIRTUAL_SIZE      8192
00069 
00070 
00071 //! @name USBHS Host IP properties
00072 //!
00073 //! @{
00074 //! Get maximal number of endpoints
00075 #define uhd_get_pipe_max_nbr()                (9)
00076 #define USBHS_EPT_NUM                        (uhd_get_pipe_max_nbr()+1)
00077 //! Get maximal number of banks of endpoints
00078 #define uhd_get_pipe_bank_max_nbr(ep)         ((ep == 0) ? 1 : ((ep <= 2) ? 3 : 2))
00079 //! Get maximal size of endpoint (3X, 1024/64)
00080 #define uhd_get_pipe_size_max(ep)             (((ep) == 0) ? 64 : 1024)
00081 //! Get DMA support of endpoints
00082 #define Is_uhd_pipe_dma_supported(ep)         ((((ep) >= 1) && ((ep) <= 7)) ? true : false)
00083 //! Get High Band Width support of endpoints
00084 #define Is_uhd_pipe_high_bw_supported(ep)     (((ep) >= 2) ? true : false)
00085 //! @}
00086 
00087 typedef enum {
00088     HOST_MODE = 0,
00089     DEVICE_MODE = 1
00090 } USB_Mode_t;
00091 
00092 //! Maximum transfer size on USB DMA
00093 #define UHD_PIPE_MAX_TRANS 0x8000
00094 
00095 /**
00096 =================================
00097         USBHS_CTRL
00098 =================================
00099 **/
00100 
00101 /**
00102  * \brief Freeze or unfreeze USB clock
00103  * \param pUsbhs   Pointer to an USBHS instance.
00104  * \param Enable Enable or disable
00105  */
00106 __STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs)
00107 {
00108     pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
00109 }
00110 
00111 /**
00112  * \brief Freeze or unfreeze USB clock
00113  * \param pUsbhs   Pointer to an USBHS instance.
00114  * \param Enable Enable or disable
00115  */
00116 __STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs)
00117 {
00118     pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK);
00119 }
00120 /**
00121  * \brief Freeze or unfreeze USB clock
00122  * \param pUsbhs   Pointer to an USBHS instance.
00123  * \param Enable Enable or disable
00124  */
00125 __STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable)
00126 {
00127 
00128     if (!Enable)
00129         pUsbhs->USBHS_CTRL |= (1 << 8);
00130     else
00131         pUsbhs->USBHS_CTRL &= ~((uint32_t)(1 << 8));
00132 }
00133 
00134 /**
00135  * \brief Enables or disables USB
00136  * \param pUsbhs   Pointer to an USBHS instance.
00137  * \param Enable Enable or disable
00138  */
00139 
00140 __STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable)
00141 {
00142     if (Enable)
00143         pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE;
00144     else
00145         pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE);
00146 }
00147 
00148 
00149 /**
00150  * \brief Device or Host Mode
00151  * \param pUsbhs   Pointer to an USBHS instance.
00152  * \param Mode   Device or Host Mode
00153  */
00154 
00155 __STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode)
00156 {
00157     if (Mode)
00158         pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE;
00159     else
00160         pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE);
00161 }
00162 
00163 /********************* USBHS_SR  *****************/
00164 
00165 /**
00166  * \brief Check if clock is usable or not
00167  * \param pUsbhs   Pointer to an USBHS instance.
00168  * \return 1 if USB clock is usable
00169  */
00170 
00171 __STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs)
00172 {
00173     return ((pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14);
00174 }
00175 
00176 
00177 /**
00178  * \brief Raise interrupt for endpoint.
00179  * \param pUsbhs   Pointer to an USBHS instance.
00180  * \return USB status
00181  */
00182 
00183 __STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs)
00184 {
00185     return (pUsbhs->USBHS_SR);
00186 }
00187 
00188 /**
00189  * \brief Enable or disable USB address
00190  * \param pUsbhs   Pointer to an USBHS instance.
00191  * \return USB speed status
00192  */
00193 
00194 __STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs)
00195 {
00196     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk));
00197 }
00198 
00199 
00200 /**
00201  * \brief Enable or disable USB address
00202  * \param pUsbhs   Pointer to an USBHS instance.
00203  * \return USB speed status
00204  */
00205 
00206 __STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs)
00207 {
00208     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ?
00209            true : false;
00210 }
00211 
00212 
00213 /**
00214  * \brief Enable or disable USB address
00215  * \param pUsbhs   Pointer to an USBHS instance.
00216  * \return USB speed status
00217  */
00218 
00219 __STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs)
00220 {
00221     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ?
00222            true : false;
00223 }
00224 
00225 /**
00226  * \brief Enable or disable USB address
00227  * \param pUsbhs   Pointer to an USBHS instance.
00228  * \return USB speed status
00229  */
00230 
00231 __STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs)
00232 {
00233     return ((pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ?
00234            true : false;
00235 }
00236 /********************* USBHS_SCR  *****************/
00237 
00238 /**
00239  * \brief Raise interrupt for endpoint.
00240  * \param pUsbhs   Pointer to an USBHS instance.
00241  * \param AckType Interrupt Acknowledge type
00242  */
00243 
00244 __STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType)
00245 {
00246     pUsbhs->USBHS_SCR |= AckType;
00247 }
00248 
00249 /********************* USBHS_SFR  *****************/
00250 
00251 /**
00252  * \brief Raise interrupt for endpoint.
00253  * \param pUsbhs   Pointer to an USBHS instance.
00254  * \param SetStatus Set USB status
00255  */
00256 
00257 __STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus)
00258 {
00259     pUsbhs->USBHS_SFR |= SetStatus;
00260 }
00261 
00262 
00263 /*--------------------------------------------------------
00264 * =========== USB Device functions ======================
00265 *---------------------------------------------------------*/
00266 
00267 /**
00268  * \brief Enable or disable USB address
00269  * \param pUsbhs   Pointer to an USBHS instance.
00270  * \param SetStatus Set USB status
00271  */
00272 
00273 __STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable)
00274 {
00275     if (Enable)
00276         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
00277     else
00278         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN);
00279 }
00280 
00281 /**
00282  * \brief Configure USB address and enable or disable it
00283  * \param pUsbhs   Pointer to an USBHS instance.
00284  * \param Addr   USB device status
00285  */
00286 
00287 __STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr)
00288 {
00289     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr);
00290     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN;
00291 }
00292 
00293 /**
00294  * \brief Get USB address
00295  * \param pUsbhs   Pointer to an USBHS instance.
00296  */
00297 
00298 __STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs)
00299 {
00300     return (pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk);
00301 }
00302 
00303 /**
00304  * \brief Attach or detach USB.
00305  * \param pUsbhs   Pointer to an USBHS instance.
00306  * \param Enable Attachs or detach USB device
00307  */
00308 
00309 __STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable)
00310 {
00311     if (Enable)
00312         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH;
00313     else
00314         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH);
00315 
00316 }
00317 
00318 /**
00319  * \brief Force Low Speed mode
00320  * \param pUsbhs   Pointer to an USBHS instance.
00321  * \param Enable Enables the Full speed
00322  */
00323 
00324 __STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable)
00325 {
00326     if (Enable)
00327         pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS;
00328     else
00329         pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS);
00330 }
00331 
00332 /**
00333  * \brief Disable/Enables High Speed mode
00334  * \param pUsbhs   Pointer to an USBHS instance.
00335  * \param Enable Enables/disable option
00336  */
00337 
00338 __STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable)
00339 {
00340     uint32_t cfg = pUsbhs->USBHS_DEVCTRL;
00341     cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk);
00342 
00343     if (Enable)
00344         pUsbhs->USBHS_DEVCTRL |= cfg;
00345     else
00346         pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS);
00347 
00348 }
00349 
00350 /**
00351  * \brief Set Remote WakeUp mode
00352  * \param pUsbhs   Pointer to an USBHS instance.
00353  */
00354 
00355 __STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs)
00356 {
00357     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP;
00358 }
00359 
00360 /**
00361  * \brief Disable/Enables Test mode
00362  * \param pUsbhs   Pointer to an USBHS instance.
00363  * \param mode Enables/disable option
00364  */
00365 
00366 __STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode)
00367 {
00368     pUsbhs->USBHS_DEVCTRL |= mode;
00369 }
00370 
00371 
00372 /**
00373  * \brief Disable/Enables HS Test mode
00374  * \param pUsbhs   Pointer to an USBHS instance.
00375  */
00376 
00377 __STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs)
00378 {
00379     pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED;
00380 }
00381 
00382 /**
00383  * \brief Read status for an interrupt
00384  * \param pUsbhs   Pointer to an USBHS instance.
00385  * \param IntType Interrupt type
00386  */
00387 
00388 __STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType)
00389 {
00390     return (pUsbhs->USBHS_DEVISR & IntType);
00391 }
00392 
00393 /**
00394  * \brief Read status for an Endpoint
00395  * \param pUsbhs   Pointer to an USBHS instance.
00396  * \param EpNum  Endpoint
00397  */
00398 
00399 __STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum)
00400 {
00401     return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_PEP_0 << EpNum));
00402 }
00403 
00404 /**
00405  * \brief Read status for a DMA Endpoint
00406  * \param pUsbhs   Pointer to an USBHS instance.
00407  * \param DmaNum  DMA Endpoint
00408  */
00409 __STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum)
00410 {
00411     return (pUsbhs->USBHS_DEVISR & (USBHS_DEVISR_DMA_1 << DmaNum));
00412 }
00413 
00414 /**
00415  * \brief Acknowledge interrupt for endpoint.
00416  * \param pUsbhs   Pointer to an USBHS instance.
00417  * \param IntType Interrupt Type
00418  */
00419 
00420 __STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType)
00421 {
00422     pUsbhs->USBHS_DEVICR |=  IntType;
00423 }
00424 
00425 /**
00426  * \brief Raise interrupt for endpoint.
00427  * \param pUsbhs   Pointer to an USBHS instance.
00428  * \param IntType Interrupt Type
00429  */
00430 
00431 
00432 __STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType)
00433 {
00434     pUsbhs->USBHS_DEVIFR |=  IntType;
00435 }
00436 
00437 /**
00438  * \brief Raise DMA interrupt for endpoint.
00439  * \param pUsbhs   Pointer to an USBHS instance.
00440  * \param IntType Interrupt Type
00441  */
00442 __STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma)
00443 {
00444     assert(Dma < USBHSDEVDMA_NUMBER);
00445     pUsbhs->USBHS_DEVIFR |=  (USBHS_DEVIFR_DMA_1 << Dma);
00446 }
00447 
00448 /**
00449  * \brief check for interrupt of endpoint.
00450  * \param pUsbhs   Pointer to an USBHS instance.
00451  * \param IntType Interrupt Type
00452  */
00453 
00454 __STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType)
00455 {
00456     return (pUsbhs->USBHS_DEVIMR &  IntType);
00457 }
00458 
00459 /**
00460  * \brief Check if endpoint's interrupt is enabled for a given endpoint number
00461  * \param pUsbhs   Pointer to an USBHS instance.
00462  * \param EpNum Endpoint number
00463  */
00464 
00465 __STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum)
00466 {
00467     return (pUsbhs->USBHS_DEVIMR &  (USBHS_DEVIMR_PEP_0 << EpNum));
00468 }
00469 
00470 
00471 /**
00472  * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint
00473  * DMA number
00474  * \param pUsbhs   Pointer to an USBHS instance.
00475  * \param DmaNum Endpoint's DMA number
00476  */
00477 
00478 __STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum)
00479 {
00480     return (pUsbhs->USBHS_DEVIMR &  (USBHS_DEVIMR_DMA_1 << DmaNum));
00481 }
00482 
00483 
00484 /**
00485  * \brief Enables Interrupt
00486  * \param pUsbhs   Pointer to an USBHS instance.
00487  * \param IntType Interrupt Type
00488  */
00489 __STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType)
00490 {
00491     pUsbhs->USBHS_DEVIER |=  IntType;
00492 }
00493 
00494 /**
00495  * \brief Enables interrupt for a given endpoint.
00496  * \param pUsbhs   Pointer to an USBHS instance.
00497  * \param DmaNum Endpoint's DMA number
00498  */
00499 __STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum)
00500 {
00501     pUsbhs->USBHS_DEVIER |=  (USBHS_DEVIER_PEP_0 << EpNum);
00502 }
00503 
00504 /**
00505  * \brief Enables DMA interrupt for a given endpoint.
00506  * \param pUsbhs   Pointer to an USBHS instance.
00507  * \param DmaEp  Endpoint's DMA interrupt number
00508  */
00509 
00510 __STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp)
00511 {
00512     assert(DmaEp < USBHSDEVDMA_NUMBER);
00513     pUsbhs->USBHS_DEVIER |=  (USBHS_DEVIER_DMA_1 << DmaEp);
00514 }
00515 
00516 /**
00517 * \brief Disables interrupt for endpoint.
00518 * \param pUsbhs   Pointer to an USBHS instance.
00519 * \param IntType Int type
00520 */
00521 
00522 __STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType)
00523 {
00524     pUsbhs->USBHS_DEVIDR |=  IntType;
00525 }
00526 
00527 /**
00528 * \brief Disables interrupt for endpoint.
00529 * \param pUsbhs  Pointer to an USBHS instance.
00530 * \param Ep    Endpoint number
00531 */
00532 
00533 __STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep)
00534 {
00535     pUsbhs->USBHS_DEVIDR |=  (USBHS_DEVIDR_PEP_0 << Ep);
00536 }
00537 
00538 /**
00539 * \brief Disables DMA interrupt for endpoint.
00540 * \param pUsbhs  Pointer to an USBHS instance.
00541 * \param DmaEp Endpoint's DMA number
00542 */
00543 __STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp)
00544 {
00545     assert(DmaEp < USBHSDEVDMA_NUMBER);
00546     pUsbhs->USBHS_DEVIDR |=  (USBHS_DEVIDR_DMA_1 << DmaEp);
00547 }
00548 
00549 
00550 /**
00551 * \brief Enables or disables endpoint.
00552 * \param pUsbhs  Pointer to an USBHS instance.
00553 * \param Enable Enable/disable endpoint
00554 */
00555 
00556 __STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable)
00557 {
00558     if (Enable)
00559         pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep);
00560     else
00561         pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep);
00562 
00563 }
00564 
00565 
00566 /**
00567 * \brief Rests Endpoint
00568 * \param pUsbhs  Pointer to an USBHS instance.
00569 * \param Ep    Endpoint Number
00570 */
00571 
00572 __STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep)
00573 {
00574     pUsbhs->USBHS_DEVEPT |=  (USBHS_DEVEPT_EPRST0 << Ep);
00575     pUsbhs->USBHS_DEVEPT &=  ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep);
00576 }
00577 
00578 /**
00579 * \brief Checks if Endpoint is enable
00580 * \param pUsbhs  Pointer to an USBHS instance.
00581 * \param Ep    Endpoint Number
00582 */
00583 
00584 __STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep)
00585 {
00586     return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep));
00587 }
00588 
00589 /**
00590 * \brief Get MicrFrame number
00591 * \param pUsbhs  Pointer to an USBHS instance.
00592 * \retruns Micro frame number
00593 */
00594 __STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs)
00595 {
00596     return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk);
00597 }
00598 
00599 
00600 /**
00601 * \brief Get Frame number
00602 * \param pUsbhs  Pointer to an USBHS instance.
00603 * \retruns frame number
00604 */
00605 __STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs)
00606 {
00607     return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk)
00608              >> USBHS_DEVFNUM_FNUM_Pos);
00609 }
00610 
00611 /**
00612 * \brief Get Frame number CRC error
00613 * \param pUsbhs  Pointer to an USBHS instance.
00614 * \retruns Frame number error status
00615 */
00616 __STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs)
00617 {
00618     return ((pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15);
00619 }
00620 
00621 /*-----------------------------------------
00622 * =========== USB Device's Endpoint functions ========
00623 *------------------------------------------*/
00624 
00625 /**
00626  * Set Endpoints configuration
00627  * Bank size, type and direction
00628  */
00629 __STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep,
00630                                         const uint8_t Type, const uint8_t Dir,
00631                                         const uint8_t Size, const uint8_t Bank)
00632 {
00633 
00634     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00635         ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk);
00636     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00637         ((Dir << 8) & USBHS_DEVEPTCFG_EPDIR);
00638     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00639         (((Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk);
00640     pUsbhs->USBHS_DEVEPTCFG[Ep] |=
00641         (((Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk);
00642 }
00643 
00644 
00645 /**
00646  * Enable or disable Auto switch of banks
00647  */
00648 __STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep,
00649         uint8_t Enable)
00650 {
00651     if (Enable)
00652         pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_AUTOSW;
00653     else
00654         pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW);
00655 }
00656 
00657 
00658 /**
00659  * Allocate Endpoint memory
00660  */
00661 __STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep)
00662 {
00663     pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_ALLOC;
00664 }
00665 
00666 
00667 /**
00668  * Free allocated Endpoint memory
00669  */
00670 __STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep)
00671 {
00672     pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC);
00673 }
00674 
00675 
00676 /**
00677  * Get Endpoint configuration
00678  */
00679 __STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep,
00680         uint32_t IntType)
00681 {
00682     return ((pUsbhs->USBHS_DEVEPTCFG[Ep]) & IntType);
00683 }
00684 
00685 /**
00686  * Get Endpoint Type
00687  */
00688 __STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep)
00689 {
00690     return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk)
00691             >> USBHS_DEVEPTCFG_EPTYPE_Pos);
00692 }
00693 
00694 /**
00695  * Get Endpoint Size
00696  */
00697 __STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep)
00698 {
00699     return (8 << ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk)
00700                     >> USBHS_DEVEPTCFG_EPSIZE_Pos));
00701 }
00702 
00703 
00704 /**
00705  * Sets ISO endpoint's Number of Transfer for High Speed
00706  */
00707 __STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep,
00708                                        uint8_t nbTrans)
00709 {
00710     pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans);
00711 }
00712 
00713 /**
00714  * Check for interrupt types enabled for a given endpoint
00715  */
00716 __STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep,
00717         uint32_t EpIntType)
00718 {
00719     return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType);
00720 }
00721 
00722 
00723 /**
00724  * Enables an interrupt type for a given endpoint
00725  */
00726 __STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
00727         uint32_t EpInt)
00728 {
00729     pUsbhs->USBHS_DEVEPTIER[Ep] |=  EpInt;
00730 }
00731 
00732 /**
00733  * Enables an interrupt type for a given endpoint
00734  */
00735 __STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep)
00736 {
00737     return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK);
00738 }
00739 
00740 /**
00741  * Enables an interrupt type for a given endpoint
00742  */
00743 __STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep)
00744 {
00745     pUsbhs->USBHS_DEVEPTIER[Ep] =  USBHS_DEVEPTIER_KILLBKS;
00746 }
00747 /**
00748  * Disables an interrupt type for a given endpoint
00749  */
00750 __STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep,
00751         uint32_t EpInt)
00752 {
00753     pUsbhs->USBHS_DEVEPTIDR[Ep] |=  EpInt;
00754 }
00755 
00756 /**
00757  * Clears register/acknowledge for a given endpoint
00758  */
00759 __STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep,
00760         uint32_t EpInt)
00761 {
00762     pUsbhs->USBHS_DEVEPTICR[Ep] |=  EpInt;
00763 }
00764 
00765 /**
00766  * Sets/Raise register for a given endpoint
00767  */
00768 __STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt)
00769 {
00770     pUsbhs->USBHS_DEVEPTIFR[Ep] |=  EpInt;
00771 }
00772 
00773 /**
00774  * Gets interrupt status for a given EP
00775  */
00776 __STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep,
00777         uint32_t EpInt)
00778 {
00779     return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt);
00780 }
00781 
00782 /**
00783  * Check if given endpoint's bank is free
00784  */
00785 __STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep)
00786 {
00787     if ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk))
00788         return false;
00789     else
00790         return true;
00791 }
00792 
00793 /**
00794  * Read endpoint's bank number in use
00795  */
00796 __STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep)
00797 {
00798     return ((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)
00799              >> USBHS_DEVEPTISR_NBUSYBK_Pos);
00800 }
00801 
00802 
00803 /**
00804  * Read endpoint's byte count of the FIFO
00805  */
00806 __STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep)
00807 {
00808     return (uint16_t)((pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk)
00809                        >> USBHS_DEVEPTISR_BYCT_Pos);
00810 }
00811 
00812 /*--------------------------------------------------------
00813 * =========== USB Device's Ep's DMA functions =========
00814 *---------------------------------------------------------*/
00815 
00816 /**
00817 * \brief Sets DMA next descriptor address
00818 * \param pUsbDma  USBHS device DMA instance
00819 * \param Desc NDA address
00820 */
00821 __STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc)
00822 {
00823     pUsbDma->USBHS_DEVDMANXTDSC = Desc;
00824 }
00825 
00826 /**
00827 * \brief Gets DMA next descriptor address
00828 * \param pUsbDma  USBHS device DMA instance
00829 * \return Next DMA descriptor
00830 */
00831 __STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma)
00832 {
00833     return (pUsbDma->USBHS_DEVDMANXTDSC);
00834 }
00835 
00836 /**
00837 * \brief Sets USBHS's DMA Buffer addresse
00838 * \param pUsbDma  USBHS device DMA instance
00839 * \param Addr  DMA's buffer Addrs
00840 */
00841 __STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr)
00842 {
00843     pUsbDma->USBHS_DEVDMAADDRESS = Addr;
00844 }
00845 
00846 
00847 /**
00848 * \brief Gets USBHS's DMA Buffer addresse
00849 * \param pUsbDma  USBHS device DMA instance
00850 * \return DMA addrs
00851 */
00852 __STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma)
00853 {
00854     return (pUsbDma->USBHS_DEVDMAADDRESS);
00855 }
00856 
00857 /**
00858 * \brief Setup the USBHS DMA
00859 * \param pUsbDma  USBHS device DMA instance
00860 * \param Cfg  DMA's configuration
00861 */
00862 __STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg)
00863 {
00864     pUsbDma->USBHS_DEVDMACONTROL |= Cfg;
00865 }
00866 
00867 /**
00868 * \brief Get DMA configuration
00869 * \param pUsbDma  USBHS device DMA instance
00870 * \return DMA control setup
00871 */
00872 __STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma)
00873 {
00874     return (pUsbDma->USBHS_DEVDMACONTROL);
00875 }
00876 
00877 
00878 /**
00879 * \brief Set DMA status
00880 * \param pUsbDma  USBHS device DMA instance
00881 * \Status Set DMA status
00882 */
00883 __STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status)
00884 {
00885     pUsbDma->USBHS_DEVDMASTATUS = Status;
00886 }
00887 
00888 
00889 /**
00890 * \brief Get Dma Status
00891 * \param pUsbDma  USBHS device DMA instance
00892 * \return Dma status
00893 */
00894 __STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma)
00895 {
00896     return (pUsbDma->USBHS_DEVDMASTATUS);
00897 }
00898 
00899 
00900 /**
00901 * \brief Get DMA buffer's count
00902 * \param pUsbDma  USBHS device DMA instance
00903 * \return Buffer count
00904 */
00905 __STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma)
00906 {
00907     return ((pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk)
00908              >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
00909 }
00910 
00911 
00912 /*--------------------------------------------------------
00913 * =========== USB Host Functions  ========================
00914 *---------------------------------------------------------*/
00915 
00916 /** Number of USB endpoints */
00917 #define CHIP_USB_NUMPIPE            10
00918 /** Number of USB endpoints */
00919 #define CHIP_USB_DMA_NUMPIPE        7
00920 
00921 /** Endpoints max paxcket size */
00922 #define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \
00923     ((ep == 0) ? 64 : 1024)
00924 
00925 /** Endpoints Number of Bank */
00926 #define CHIP_USB_PIPE_BANKS(ep)                 ((ep==0)?1:((ep<=2)?3:2))
00927 
00928 
00929 #define CHIP_USB_PIPE_HBW(ep)                   ((((ep)>=1) &&((ep)<=2))?true:false)
00930 
00931 /** Endpoints DMA support */
00932 #define CHIP_USB_PIPE_DMA(ep)                   ((((ep)>=1)&&((ep)<=7))?true:false)
00933 
00934 /**
00935 * \brief Sets USB host's speed to Normal , it sets to HS from FS
00936 * \param pUsbhs  USBHS host instance
00937 */
00938 __STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs)
00939 {
00940     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00941     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL;
00942 }
00943 
00944 /**
00945 * \brief Sets USB host's speed to Low speed
00946 * \param pUsbhs  USBHS host instance
00947 */
00948 __STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs)
00949 {
00950     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00951     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER;
00952 }
00953 
00954 /**
00955 * \brief Sets USB host's speed to forced Full speed
00956 * \param pUsbhs  USBHS host instance
00957 */
00958 __STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs)
00959 {
00960     pUsbhs->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SPDCONF_Msk;
00961     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS;
00962 }
00963 
00964 /**
00965 * \brief Sets USB host sends reste signal on USB Bus
00966 * \param pUsbhs  USBHS host instance
00967 */
00968 __STATIC_INLINE void USBHS_Reset(void)
00969 {
00970     USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET;
00971 }
00972 
00973 /**
00974 * \brief Sets USB host sends reste signal on USB Bus
00975 * \param pUsbhs  USBHS host instance
00976 */
00977 __STATIC_INLINE void USBHS_StopReset(void)
00978 {
00979     USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET;
00980 }
00981 
00982 /**
00983 * \brief Sets USB host send Resume on USB bus
00984 * \param pUsbhs  USBHS host instance
00985 */
00986 __STATIC_INLINE void USBHS_Resume(void)
00987 {
00988     USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME;
00989 }
00990 
00991 /**
00992 * \brief Sets USB host Enable the Generation of  Start of Frame
00993 * \param pUsbhs  USBHS host instance
00994 */
00995 __STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs)
00996 {
00997     pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE;
00998 }
00999 
01000 /**
01001 * \brief Sets USB host Enable the Generation of  Start of Frame
01002 * \param pUsbhs  USBHS host instance
01003 */
01004 __STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs)
01005 {
01006     return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8;
01007 }
01008 /**
01009 * \brief Sets USB host disable the Generation of  Start of Frame
01010 * \param pUsbhs  USBHS host instance
01011 */
01012 __STATIC_INLINE void USBHS_DisableSOF(void)
01013 {
01014     USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE;
01015 }
01016 
01017 /**
01018 * \brief Gets USB host interrupt status
01019 * \param pUsbhs  USBHS host instance
01020 */
01021 __STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType)
01022 {
01023     return (pUsbhs->USBHS_HSTISR & IntType);
01024 }
01025 
01026 
01027 /**
01028  * \brief Gets USB host interrupt status
01029  * \param pUsbhs  USBHS host instance
01030  */
01031 __STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01032 {
01033     assert(PipeInt < CHIP_USB_NUMPIPE);
01034     return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_PEP_0 << PipeInt));
01035 }
01036 
01037 
01038 /**
01039  * \brief Gets USB host interrupt status
01040  * \param pUsbhs  USBHS host instance
01041  */
01042 __STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs,
01043         uint8_t PipeInt)
01044 {
01045     assert(PipeInt);
01046     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
01047     return (pUsbhs->USBHS_HSTISR & (USBHS_HSTISR_DMA_1 << PipeInt));
01048 }
01049 
01050 /**
01051  * \brief Gets USB host interrupt status
01052  * \param pUsbhs  USBHS host instance
01053  */
01054 __STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType)
01055 {
01056     pUsbhs->USBHS_HSTICR = IntType;
01057 }
01058 
01059 /**
01060  * \brief Gets USB host interrupt status
01061  * \param pUsbhs  USBHS host instance
01062  */
01063 __STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType)
01064 {
01065     pUsbhs->USBHS_HSTIFR = IntType;
01066 }
01067 
01068 /**
01069  * \brief Gets USB host interrupt status
01070  * \param pUsbhs  USBHS host instance
01071  */
01072 __STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt)
01073 {
01074     assert(PipeInt);
01075     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
01076     pUsbhs->USBHS_HSTIFR =  (USBHS_HSTIFR_DMA_1 << PipeInt);
01077 }
01078 
01079 /*** Interrupt Mask ****/
01080 /**
01081  * \brief Gets USB host interrupt status
01082  * \param pUsbhs  USBHS host instance
01083  */
01084 __STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType)
01085 {
01086     return (pUsbhs->USBHS_HSTIMR & IntType);
01087 }
01088 
01089 /**
01090  * \brief Gets USB host interrupt status
01091  * \param pUsbhs  USBHS host instance
01092  */
01093 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs,
01094         uint8_t PipeInt)
01095 {
01096     assert(PipeInt < CHIP_USB_NUMPIPE);
01097     return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt));
01098 }
01099 
01100 /**
01101  * \brief Gets USB host interrupt status
01102  * \param pUsbhs  USBHS host instance
01103  */
01104 __STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs,
01105         uint8_t PipeInt)
01106 {
01107     assert(PipeInt);
01108     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
01109     return (pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt));
01110 }
01111 
01112 /*** Interrupt Disable ****/
01113 /**
01114  * \brief Gets USB host interrupt status
01115  * \param pUsbhs  USBHS host instance
01116  */
01117 __STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType)
01118 {
01119     pUsbhs->USBHS_HSTIDR = IntType;
01120 }
01121 
01122 /**
01123  * \brief Gets USB host interrupt status
01124  * \param pUsbhs  USBHS host instance
01125  */
01126 __STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
01127 {
01128     assert(PipeInt < CHIP_USB_NUMPIPE);
01129     pUsbhs->USBHS_HSTIDR  = (USBHS_HSTIDR_PEP_0 << PipeInt);
01130 }
01131 
01132 /**
01133  * \brief Gets USB host interrupt status
01134  * \param pUsbhs  USBHS host instance
01135  */
01136 __STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt)
01137 {
01138     assert(PipeInt);
01139     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
01140     pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt);
01141 }
01142 
01143 /*** Interrupt Enable ****/
01144 
01145 /**
01146  * \brief Gets USB host interrupt status
01147  * \param pUsbhs  USBHS host instance
01148  */
01149 __STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint32_t IntType)
01150 {
01151     pUsbhs->USBHS_HSTIER = IntType;
01152 }
01153 
01154 /**
01155  * \brief Gets USB host interrupt status
01156  * \param pUsbhs  USBHS host instance
01157  */
01158 __STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01159 {
01160     assert(PipeInt < CHIP_USB_NUMPIPE);
01161     pUsbhs->USBHS_HSTIER = (USBHS_HSTIER_PEP_0 << PipeInt);
01162 }
01163 
01164 /**
01165  * \brief Gets USB host interrupt status
01166  * \param pUsbhs  USBHS host instance
01167  */
01168 __STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt)
01169 {
01170     assert(PipeInt < CHIP_USB_DMA_NUMPIPE);
01171     pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt);
01172 }
01173 
01174 /**
01175  * \brief Gets USB host interrupt status
01176  * \param pUsbhs  USBHS host instance
01177  */
01178 __STATIC_INLINE uint16_t USBHS_HostGetSOF(void)
01179 {
01180     return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >>
01181              USBHS_HSTFNUM_FNUM_Pos);
01182 }
01183 
01184 /**
01185  * \brief Gets USB host interrupt status
01186  * \param pUsbhs  USBHS host instance
01187  */
01188 __STATIC_INLINE uint16_t USBHS_HostGetFramePos(void)
01189 {
01190     return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FLENHIGH_Msk) >>
01191              USBHS_HSTFNUM_FLENHIGH_Pos);
01192 }
01193 
01194 
01195 /**
01196  * \brief Gets USB host interrupt status
01197  * \param pUsbhs  USBHS host instance
01198  */
01199 __STATIC_INLINE uint16_t USBHS_HostGetMSOF(void)
01200 {
01201     return ((USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >>
01202              USBHS_HSTFNUM_MFNUM_Pos);
01203 }
01204 
01205 __STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe,
01206                                        uint8_t Addr)
01207 {
01208     assert(Pipe < CHIP_USB_NUMPIPE);
01209 
01210     if (Pipe < 4)
01211         pUsbhs->USBHS_HSTADDR1 |= (Addr << (8 * Pipe));
01212     else if ((Pipe < 8) && (Pipe >= 4))
01213         pUsbhs->USBHS_HSTADDR2 |= (Addr << (8 * (Pipe - 4)));
01214     else
01215         pUsbhs->USBHS_HSTADDR3 |= (Addr << (8 * (Pipe - 8)));
01216 
01217 }
01218 
01219 __STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe)
01220 {
01221     assert(Pipe < CHIP_USB_NUMPIPE);
01222 
01223     if (Pipe < 4)
01224         return (pUsbhs->USBHS_HSTADDR1 >>  (8 * Pipe));
01225     else if ((Pipe < 8) && (Pipe >= 4))
01226         return (pUsbhs->USBHS_HSTADDR2  >>  (8 * (Pipe - 4)));
01227     else
01228         return (pUsbhs->USBHS_HSTADDR3  >> (8 * (Pipe - 8)));
01229 
01230 }
01231 
01232 /**
01233  * \brief Gets USB host interrupt status
01234  * \param pUsbhs  USBHS host instance
01235  */
01236 __STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
01237 {
01238     assert(Pipe < CHIP_USB_NUMPIPE);
01239     pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe);
01240 }
01241 
01242 /**
01243  * \brief Gets USB host interrupt status
01244  * \param pUsbhs  USBHS host instance
01245  */
01246 __STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe)
01247 {
01248     assert(Pipe < CHIP_USB_NUMPIPE);
01249     pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe);
01250 }
01251 
01252 /**
01253  * \brief Gets USB host interrupt status
01254  * \param pUsbhs  USBHS host instance
01255  */
01256 __STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe)
01257 {
01258     assert(Pipe < CHIP_USB_NUMPIPE);
01259     return (pUsbhs->USBHS_HSTPIP & (USBHS_HSTPIP_PEN0 << Pipe));
01260 }
01261 /**
01262  * \brief Gets USB host interrupt status
01263  * \param pUsbhs  USBHS host instance
01264  */
01265 __STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe)
01266 {
01267     assert(Pipe < CHIP_USB_NUMPIPE);
01268     pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe);
01269     pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe);
01270 }
01271 
01272 /**
01273  * \brief Gets USB host interrupt status
01274  * \param pUsbhs  USBHS host instance
01275  */
01276 __STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe,
01277         uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken,
01278         uint8_t pipeEpNum, uint8_t PipeIntFreq)
01279 {
01280     assert(Pipe < CHIP_USB_NUMPIPE);
01281     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= (pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(
01282                                            pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) |
01283                                        USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq));
01284 }
01285 
01286 /**
01287  * \brief Gets USB host interrupt status
01288  * \param pUsbhs  USBHS host instance
01289  */
01290 __STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe)
01291 {
01292     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC;
01293 
01294 }
01295 
01296 /**
01297  * \brief Gets USB host interrupt status
01298  * \param pUsbhs  USBHS host instance
01299  */
01300 __STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe)
01301 {
01302     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC;
01303 
01304 }
01305 
01306 
01307 /**
01308  * \brief Gets USB host interrupt status
01309  * \param pUsbhs  USBHS host instance
01310  */
01311 __STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe)
01312 {
01313     return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >>
01314                   USBHS_HSTPIPCFG_PSIZE_Pos));
01315 
01316 }
01317 
01318 /**
01319 * \brief Gets USB host interrupt status
01320 * \param pUsbhs  USBHS host instance
01321 */
01322 __STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe,
01323                                         uint32_t Token)
01324 {
01325     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk;
01326     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token;
01327 
01328 }
01329 
01330 
01331 /**
01332  * \brief Gets USB host interrupt status
01333  * \param pUsbhs  USBHS host instance
01334  */
01335 __STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe)
01336 {
01337     return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk);
01338 
01339 }
01340 
01341 
01342 /**
01343  * \brief Gets USB host interrupt status
01344  * \param pUsbhs  USBHS host instance
01345  */
01346 __STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe,
01347         uint8_t PipeType)
01348 {
01349     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk;
01350     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType;
01351 
01352 }
01353 
01354 /**
01355  * \brief Gets USB host interrupt status
01356  * \param pUsbhs  USBHS host instance
01357  */
01358 __STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe)
01359 {
01360     return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk);
01361 
01362 }
01363 
01364 __STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe)
01365 {
01366 
01367     if (USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN)
01368         return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >>
01369                   USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80);
01370     else
01371         return (((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >>
01372                   USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00);
01373 }
01374 
01375 
01376 
01377 /**
01378  * \brief Gets USB host interrupt status
01379  * \param pUsbhs  USBHS host instance
01380  */
01381 __STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
01382 {
01383     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW;
01384 }
01385 
01386 /**
01387  * \brief Gets USB host interrupt status
01388  * \param pUsbhs  USBHS host instance
01389  */
01390 __STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe)
01391 {
01392     pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW;
01393 }
01394 
01395 /**
01396  * \brief Gets USB host interrupt status
01397  * \param pUsbhs  USBHS host instance
01398  */
01399 __STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe,
01400         uint8_t Freq)
01401 {
01402     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq);
01403 }
01404 
01405 
01406 /**
01407  * \brief Gets USB host interrupt status
01408  * \param pUsbhs  USBHS host instance
01409  */
01410 __STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe)
01411 {
01412     pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN;
01413 }
01414 
01415 
01416 /**
01417  * \brief Gets USB host interrupt status
01418  * \param pUsbhs  USBHS host instance
01419  */
01420 __STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe)
01421 {
01422     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >>
01423              USBHS_HSTPIPISR_DTSEQ_Pos);
01424 }
01425 
01426 
01427 /**
01428  * \brief Gets USB host interrupt status
01429  * \param pUsbhs  USBHS host instance
01430  */
01431 __STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe)
01432 {
01433     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >>
01434              USBHS_HSTPIPISR_NBUSYBK_Pos);
01435 }
01436 
01437 
01438 /**
01439  * \brief Gets USB host interrupt status
01440  * \param pUsbhs  USBHS host instance
01441  */
01442 __STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe)
01443 {
01444     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >>
01445              USBHS_HSTPIPISR_CURRBK_Pos);
01446 }
01447 
01448 
01449 /**
01450  * \brief Gets USB host interrupt status
01451  * \param pUsbhs  USBHS host instance
01452  */
01453 __STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe)
01454 {
01455     return ((pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >>
01456              USBHS_HSTPIPISR_PBYCT_Pos);
01457 }
01458 
01459 /**
01460  * \brief Gets USB host interrupt status
01461  * \param pUsbhs  USBHS host instance
01462  */
01463 __STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe)
01464 {
01465     return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK);
01466 }
01467 
01468 /**
01469  * \brief Gets USB host interrupt status
01470  * \param pUsbhs  USBHS host instance
01471  */
01472 __STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe,
01473         uint32_t intType)
01474 {
01475     return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType);
01476 }
01477 
01478 /**
01479  * \brief Gets USB host interrupt status
01480  * \param pUsbhs  USBHS host instance
01481  */
01482 __STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
01483         uint32_t intType)
01484 {
01485     pUsbhs->USBHS_HSTPIPICR[Pipe] = intType;
01486 }
01487 
01488 /**
01489  * \brief Gets USB host interrupt status
01490  * \param pUsbhs  USBHS host instance
01491  */
01492 __STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
01493         uint32_t intType)
01494 {
01495     pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType;
01496 }
01497 
01498 /**
01499  * \brief Gets USB host interrupt status
01500  * \param pUsbhs  USBHS host instance
01501  */
01502 __STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs,
01503         uint8_t Pipe, uint32_t intType)
01504 {
01505     return (pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType);
01506 }
01507 
01508 /**
01509  * \brief Gets USB host interrupt status
01510  * \param pUsbhs  USBHS host instance
01511  */
01512 __STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
01513         uint32_t intType)
01514 {
01515     pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType;
01516 }
01517 
01518 /**
01519  * \brief Gets USB host interrupt status
01520  * \param pUsbhs  USBHS host instance
01521  */
01522 __STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe,
01523         uint32_t intType)
01524 {
01525     pUsbhs->USBHS_HSTPIPIER[Pipe] = intType;
01526 }
01527 
01528 /**
01529  * \brief Gets USB host interrupt status
01530  * \param pUsbhs  USBHS host instance
01531  */
01532 __STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe)
01533 {
01534     pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE;
01535 }
01536 
01537 /**
01538  * \brief Gets USB host interrupt status
01539  * \param pUsbhs  USBHS host instance
01540  */
01541 __STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe)
01542 {
01543     pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE;
01544 }
01545 
01546 /**
01547  * \brief Gets USB host interrupt status
01548  * \param pUsbhs  USBHS host instance
01549  */
01550 __STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe)
01551 {
01552     return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8);
01553 }
01554 
01555 /**
01556  * \brief Gets USB host interrupt status
01557  * \param pUsbhs  USBHS host instance
01558  */
01559 __STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq)
01560 {
01561     pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq - 1);
01562 }
01563 
01564 
01565 /**
01566  * \brief Gets USB host interrupt status
01567  * \param pUsbhs  USBHS host instance
01568  */
01569 __STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err)
01570 {
01571     pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err;
01572 }
01573 
01574 /**
01575  * \brief Gets USB host interrupt status
01576  * \param pUsbhs  USBHS host instance
01577  */
01578 __STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe,
01579         uint8_t Err)
01580 {
01581     return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err);
01582 }
01583 
01584 
01585 /**
01586  * \brief Gets USB host interrupt status
01587  * \param pUsbhs  USBHS host instance
01588  */
01589 __STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe,
01590                                         uint8_t Err)
01591 {
01592     pUsbhs->USBHS_HSTPIPERR[Pipe] = Err;
01593 }
01594 
01595 
01596 __STATIC_INLINE  uint8_t USBHS_GetInterruptPipeNum(void)
01597 {
01598     uint32_t status = USBHS->USBHS_HSTISR;
01599     uint32_t mask = USBHS->USBHS_HSTIMR;
01600     return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM));
01601 }
01602 
01603 static inline uint8_t USBHS_GetInterruptPipeDmaNum(void)
01604 {
01605     uint32_t status = USBHS->USBHS_HSTISR;
01606     uint32_t mask = USBHS->USBHS_HSTIMR;
01607     return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM - 1))) + 1);
01608 }
01609 /*--------------------------------------------------------
01610 * =========== USB Host's pipe DMA functions =========
01611 *---------------------------------------------------------*/
01612 
01613 /**
01614 * \brief Sets DMA next descriptor address
01615 * \param pUsbDma  USBHS device DMA instance
01616 * \param Desc NDA addrs
01617 */
01618 __STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc)
01619 {
01620     pUsbDma->USBHS_HSTDMANXTDSC = Desc;
01621 }
01622 
01623 /**
01624 * \brief Gets DMA next descriptor address
01625 * \param pUsbDma  USBHS device DMA instance
01626 * \return Next DMA descriptor
01627 */
01628 __STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma)
01629 {
01630     return (pUsbDma->USBHS_HSTDMANXTDSC);
01631 }
01632 
01633 /**
01634 * \brief Sets USBHS's DMA Buffer addresse
01635 * \param pUsbDma  USBHS device DMA instance
01636 * \param Addr  DMA's buffer Addrs
01637 */
01638 __STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma,
01639         uint32_t Addr)
01640 {
01641     pUsbDma->USBHS_HSTDMAADDRESS = Addr;
01642 }
01643 
01644 
01645 /**
01646 * \brief Gets USBHS's DMA Buffer addresse
01647 * \param pUsbDma  USBHS device DMA instance
01648 * \return DMA addrs
01649 */
01650 __STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma)
01651 {
01652     return (pUsbDma->USBHS_HSTDMAADDRESS);
01653 }
01654 
01655 /**
01656 * \brief Setup the USBHS DMA
01657 * \param pUsbDma  USBHS device DMA instance
01658 * \param Cfg  DMA's configuration
01659 */
01660 __STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg)
01661 {
01662     pUsbDma->USBHS_HSTDMACONTROL |= Cfg;
01663 }
01664 
01665 /**
01666 * \brief Get DMA configuration
01667 * \param pUsbDma  USBHS device DMA instance
01668 * \return DMA control setup
01669 */
01670 __STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma)
01671 {
01672     return (pUsbDma->USBHS_HSTDMACONTROL);
01673 }
01674 
01675 
01676 /**
01677 * \brief Set DMA status
01678 * \param pUsbDma  USBHS device DMA instance
01679 * \Status Set DMA status
01680 */
01681 __STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma,
01682         uint32_t Status)
01683 {
01684     pUsbDma->USBHS_HSTDMASTATUS = Status;
01685 }
01686 
01687 
01688 /**
01689 * \brief Get Dma Status
01690 * \param pUsbDma  USBHS device DMA instance
01691 * \return Dma status
01692 */
01693 __STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma)
01694 {
01695     return (pUsbDma->USBHS_HSTDMASTATUS);
01696 }
01697 
01698 /**@}*/
01699 #endif /* #ifndef USBHS_H */
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Defines