00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049 #include "chip.h"
00050
00051
00052
00053
00054
00055
00056
00057
00058 #define DMA_QSPI_LLI 2
00059
00060
00061
00062
00063
00064
00065
00066
00067
00068
00069
00070 static void QSPID_Spi_Cb(uint32_t channel, QspiDma_t *pArg)
00071 {
00072 Qspi *pQspiHw = pArg->Qspid.pQspiHw;
00073
00074 if (channel != pArg->RxChNum)
00075 return;
00076
00077
00078 ReleaseMutex(pArg->progress);
00079 QSPI_EndTransfer(pQspiHw);
00080 SCB_InvalidateDCache_by_Addr((uint32_t *)pArg->Qspid.qspiBuffer.pDataRx,
00081 pArg->Qspid.qspiBuffer.RxDataSize);
00082 memory_sync();
00083 }
00084
00085
00086
00087
00088
00089
00090
00091
00092 static void QSPID_qspiTx_Cb(uint32_t channel, QspiDma_t *pArg)
00093 {
00094 Qspi *pQspiHw = pArg->Qspid.pQspiHw;
00095
00096 if (channel != pArg->TxChNum)
00097 return;
00098
00099
00100 ReleaseMutex(pArg->progress);
00101 QSPI_EndTransfer(pQspiHw);
00102
00103 while (!QSPI_GetStatus(pArg->Qspid.pQspiHw, IsEofInst));
00104
00105 memory_sync();
00106 }
00107
00108
00109
00110
00111
00112
00113
00114
00115 static void QSPID_qspiRx_Cb(uint32_t channel, QspiDma_t *pArg)
00116 {
00117 Qspi *pQspiHw = pArg->Qspid.pQspiHw;
00118
00119 if (channel != pArg->RxChNum)
00120 return;
00121
00122
00123 ReleaseMutex(pArg->progress);
00124 QSPI_EndTransfer(pQspiHw);
00125
00126 while (!QSPI_GetStatus(pArg->Qspid.pQspiHw, IsEofInst));
00127
00128 SCB_InvalidateDCache_by_Addr((uint32_t *)pArg->Qspid.qspiBuffer.pDataRx,
00129 pArg->Qspid.qspiBuffer.RxDataSize);
00130 memory_sync();
00131 }
00132
00133
00134
00135
00136
00137
00138
00139
00140
00141
00142
00143 static uint8_t QSPID_configureQpsiDma(QspiDma_t *pQspidma, uint32_t Addr,
00144 QspiBuffer_t *pBuffer, Access_t const ReadWrite)
00145 {
00146 sXdmadCfg xdmadCfg, xdmadRxCfg, xdmadTxCfg;
00147 uint8_t chanNum;
00148 uint8_t qspi_id = pQspidma->Qspid.qspiId;
00149 Qspi *pQspiHw = pQspidma->Qspid.pQspiHw;
00150 uint32_t xdmaCndc, xdmaInt, BurstSize, ChannelWidth;
00151
00152
00153
00154
00155 if (pQspidma->Qspid.qspiMode == QSPI_MR_SMM_SPI) {
00156
00157
00158 xdmadTxCfg.mbr_sa = (uint32_t)pBuffer->pDataTx;
00159 xdmadTxCfg.mbr_da = (uint32_t)&pQspiHw->QSPI_TDR;
00160 xdmadTxCfg.mbr_ubc = (pBuffer->TxDataSize);
00161
00162 xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
00163 XDMAC_CC_MBSIZE_SINGLE |
00164 XDMAC_CC_DSYNC_MEM2PER |
00165 XDMAC_CC_CSIZE_CHK_1 |
00166 XDMAC_CC_DWIDTH_BYTE |
00167 XDMAC_CC_SIF_AHB_IF0 |
00168 XDMAC_CC_DIF_AHB_IF1 |
00169 XDMAC_CC_SAM_INCREMENTED_AM |
00170 XDMAC_CC_DAM_FIXED_AM |
00171 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber
00172 (qspi_id, XDMAD_TRANSFER_TX));
00173
00174 xdmadTxCfg.mbr_bc = 0;
00175 xdmadTxCfg.mbr_sus = 0;
00176 xdmadTxCfg.mbr_dus = 0;
00177
00178
00179
00180 xdmadRxCfg.mbr_da = (uint32_t)pBuffer->pDataRx;
00181 xdmadRxCfg.mbr_sa = (uint32_t)&pQspiHw->QSPI_RDR;
00182 xdmadRxCfg.mbr_ubc = (pBuffer->RxDataSize);
00183 xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
00184 XDMAC_CC_MBSIZE_SINGLE |
00185 XDMAC_CC_DSYNC_PER2MEM |
00186 XDMAC_CC_CSIZE_CHK_1 |
00187 XDMAC_CC_DWIDTH_BYTE |
00188 XDMAC_CC_SIF_AHB_IF1 |
00189 XDMAC_CC_DIF_AHB_IF0 |
00190 XDMAC_CC_SAM_FIXED_AM |
00191 XDMAC_CC_DAM_INCREMENTED_AM |
00192 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber
00193 (qspi_id, XDMAD_TRANSFER_RX));
00194
00195 xdmadRxCfg.mbr_bc = 0;
00196 xdmadRxCfg.mbr_sus = 0;
00197 xdmadRxCfg.mbr_dus = 0;
00198 xdmaCndc = 0;
00199
00200 xdmaInt = (XDMAC_CIE_BIE |
00201 XDMAC_CIE_RBIE |
00202 XDMAC_CIE_WBIE |
00203 XDMAC_CIE_ROIE);
00204
00205 memory_barrier();
00206
00207 if (XDMAD_ConfigureTransfer
00208 (pQspidma->pXdmad, pQspidma->RxChNum, &xdmadRxCfg, xdmaCndc, 0, xdmaInt))
00209 return QSPID_ERROR;
00210
00211 if (XDMAD_ConfigureTransfer
00212 (pQspidma->pXdmad, pQspidma->TxChNum, &xdmadTxCfg, xdmaCndc, 0, xdmaInt))
00213 return QSPID_ERROR;
00214
00215 return 0;
00216
00217 } else {
00218 if (ReadWrite == WriteAccess) {
00219 xdmadCfg.mbr_sa = (uint32_t)pBuffer->pDataTx;
00220 xdmadCfg.mbr_da = (uint32_t)(QSPIMEM_ADDR | Addr);
00221 xdmadCfg.mbr_ubc = (pBuffer->TxDataSize);
00222 chanNum = pQspidma->TxChNum;
00223 ChannelWidth = XDMAC_CC_DWIDTH_BYTE;
00224 BurstSize = XDMAC_CC_MBSIZE_SIXTEEN;
00225 } else if (ReadWrite == ReadAccess) {
00226 xdmadCfg.mbr_da = (uint32_t)pBuffer->pDataRx;
00227 xdmadCfg.mbr_sa = (uint32_t)(QSPIMEM_ADDR | Addr);
00228 xdmadCfg.mbr_ubc = ((pBuffer->RxDataSize >> 2));
00229 chanNum = pQspidma->RxChNum;
00230 ChannelWidth = XDMAC_CC_DWIDTH_WORD;
00231 BurstSize = XDMAC_CC_MBSIZE_SIXTEEN;
00232 } else {
00233 TRACE_ERROR(" QSPI error \n\r");
00234 return 1;
00235 }
00236
00237 xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN |
00238 XDMAC_CC_MEMSET_NORMAL_MODE |
00239 BurstSize |
00240 ChannelWidth |
00241 XDMAC_CC_SIF_AHB_IF1 |
00242 XDMAC_CC_DIF_AHB_IF1 |
00243 XDMAC_CC_SAM_INCREMENTED_AM |
00244 XDMAC_CC_DAM_INCREMENTED_AM;
00245
00246 xdmadCfg.mbr_bc = 0;
00247 xdmadCfg.mbr_sus = 0;
00248 xdmadCfg.mbr_dus = 0;
00249
00250 xdmaCndc = 0;
00251
00252
00253
00254 xdmaInt = (XDMAC_CIE_BIE |
00255 XDMAC_CIE_RBIE |
00256 XDMAC_CIE_WBIE |
00257 XDMAC_CIE_ROIE);
00258
00259 memory_barrier();
00260
00261 if (XDMAD_ConfigureTransfer(pQspidma->pXdmad, chanNum, &xdmadCfg, xdmaCndc, 0,
00262 xdmaInt))
00263 return QSPID_ERROR;
00264
00265 return 0;
00266 }
00267 }
00268
00269
00270
00271
00272
00273
00274
00275
00276
00277
00278
00279
00280
00281 uint32_t QSPID_Configure(QspiDma_t *pQspidma, QspiMode_t Mode,
00282 uint32_t dwConf, sXdmad *pXdmad)
00283 {
00284
00285
00286 QSPI_ConfigureInterface(&pQspidma->Qspid, Mode, dwConf);
00287
00288 pQspidma->Qspid.qspiCommand.Instruction = 0;
00289 pQspidma->Qspid.qspiCommand.Option = 0;
00290
00291 pQspidma->RxChNum = QSPID_CH_NOT_ENABLED;
00292 pQspidma->TxChNum = QSPID_CH_NOT_ENABLED;
00293
00294 pQspidma->pXdmad = pXdmad;
00295
00296
00297 XDMAD_Initialize(pQspidma->pXdmad, 0);
00298
00299
00300 NVIC_ClearPendingIRQ(XDMAC_IRQn);
00301 NVIC_SetPriority(XDMAC_IRQn , 1);
00302 NVIC_EnableIRQ(XDMAC_IRQn);
00303
00304
00305 return QSPI_SUCCESS;
00306 }
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316
00317
00318
00319
00320 uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma)
00321 {
00322 static uint16_t DmaChannel;
00323
00324
00325 if (pQspidma->RxChNum != QSPID_CH_NOT_ENABLED)
00326 return QSPID_ERROR_LOCK;
00327
00328
00329 DmaChannel = XDMAD_AllocateChannel(
00330 pQspidma->pXdmad, XDMAD_TRANSFER_MEMORY, XDMAD_TRANSFER_MEMORY);
00331
00332 if (DmaChannel == XDMAD_ALLOC_FAILED)
00333 return QSPID_ERROR;
00334
00335 pQspidma->RxChNum = DmaChannel;
00336
00337 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum,
00338 (XdmadTransferCallback)QSPID_qspiRx_Cb, pQspidma);
00339
00340 if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->RxChNum))
00341 return QSPID_ERROR;
00342
00343 return 0;
00344 }
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354
00355
00356
00357 uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma)
00358 {
00359 static uint16_t DmaChannel;
00360
00361
00362 if (pQspidma->TxChNum != QSPID_CH_NOT_ENABLED)
00363 return QSPID_ERROR_LOCK;
00364
00365
00366 DmaChannel = XDMAD_AllocateChannel(pQspidma->pXdmad,
00367 XDMAD_TRANSFER_MEMORY, XDMAD_TRANSFER_MEMORY);
00368
00369 if (DmaChannel == XDMAD_ALLOC_FAILED)
00370 return QSPID_ERROR;
00371
00372 pQspidma->TxChNum = DmaChannel;
00373
00374 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum,
00375 (XdmadTransferCallback)QSPID_qspiTx_Cb, pQspidma);
00376
00377 if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->TxChNum))
00378 return QSPID_ERROR;
00379
00380 return 0;
00381 }
00382
00383
00384
00385
00386
00387
00388
00389
00390
00391
00392
00393
00394 uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma)
00395 {
00396 static uint16_t DmaChannel;
00397
00398
00399 if (pQspidma->RxChNum != QSPID_CH_NOT_ENABLED)
00400 return QSPID_ERROR_LOCK;
00401
00402
00403 if (pQspidma->TxChNum != QSPID_CH_NOT_ENABLED)
00404 return QSPID_ERROR_LOCK;
00405
00406
00407 DmaChannel = XDMAD_AllocateChannel
00408 (pQspidma->pXdmad, pQspidma->Qspid.qspiId, XDMAD_TRANSFER_MEMORY);
00409
00410 if (DmaChannel == XDMAD_ALLOC_FAILED)
00411 return QSPID_ERROR;
00412
00413 pQspidma->RxChNum = DmaChannel;
00414
00415
00416 DmaChannel = XDMAD_AllocateChannel(pQspidma->pXdmad,
00417 XDMAD_TRANSFER_MEMORY, pQspidma->Qspid.qspiId);
00418
00419 if (DmaChannel == XDMAD_ALLOC_FAILED)
00420 return QSPID_ERROR;
00421
00422 pQspidma->TxChNum = DmaChannel;
00423
00424
00425 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum,
00426 (XdmadTransferCallback)QSPID_Spi_Cb, pQspidma);
00427
00428 if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->RxChNum))
00429 return QSPID_ERROR;
00430
00431
00432 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, NULL, NULL);
00433
00434 if (XDMAD_PrepareChannel(pQspidma->pXdmad, pQspidma->TxChNum))
00435 return QSPID_ERROR;
00436
00437 return 0;
00438 }
00439
00440
00441
00442
00443
00444
00445
00446
00447
00448
00449
00450
00451 uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma)
00452 {
00453
00454 XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->RxChNum);
00455 XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->RxChNum);
00456
00457 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, NULL, NULL);
00458
00459
00460
00461 XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->RxChNum);
00462
00463 pQspidma->RxChNum = QSPID_CH_NOT_ENABLED;
00464
00465 return 0;
00466 }
00467
00468
00469
00470
00471
00472
00473
00474
00475
00476
00477
00478
00479
00480 uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma)
00481 {
00482
00483 XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->TxChNum);
00484 XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->TxChNum);
00485
00486 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, NULL, NULL);
00487
00488
00489 XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->TxChNum);
00490
00491 pQspidma->TxChNum = QSPID_CH_NOT_ENABLED;
00492
00493 return 0;
00494 }
00495
00496
00497
00498
00499
00500
00501
00502
00503
00504
00505
00506
00507 uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma)
00508 {
00509
00510 XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->RxChNum);
00511
00512 XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->RxChNum);
00513 XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->TxChNum);
00514
00515 XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, NULL, NULL);
00516
00517
00518 XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->RxChNum);
00519
00520 XDMAD_FreeChannel(pQspidma->pXdmad, pQspidma->TxChNum);
00521
00522 pQspidma->RxChNum = QSPID_CH_NOT_ENABLED;
00523 pQspidma->TxChNum = QSPID_CH_NOT_ENABLED;
00524
00525 return 0;
00526 }
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538 uint32_t QSPID_ReadWriteQSPI(QspiDma_t *pQspidma, Access_t const ReadWrite)
00539 {
00540 QspiBuffer_t *pBuffer = &pQspidma->Qspid.qspiBuffer;
00541 uint8_t chanNum;
00542 uint32_t semTimer = 0x7FF;
00543
00544
00545
00546 if (pQspidma->progress)
00547 return QSPID_ERROR_LOCK;
00548
00549 LockMutex(pQspidma->progress, semTimer);
00550
00551 if (QSPID_configureQpsiDma
00552 (pQspidma, pQspidma->Qspid.pQspiFrame->Addr, pBuffer, ReadWrite))
00553 return QSPID_ERROR_LOCK;
00554
00555 if (ReadWrite == WriteAccess) {
00556 chanNum = pQspidma->TxChNum;
00557 SCB_CleanDCache_by_Addr((uint32_t *)pBuffer->pDataTx, pBuffer->TxDataSize);
00558 } else if (ReadWrite == ReadAccess)
00559 chanNum = pQspidma->RxChNum;
00560 else
00561 TRACE_ERROR("%s QSPI Access Error\n\r", __FUNCTION__);
00562
00563
00564 if (XDMAD_StartTransfer(pQspidma->pXdmad, chanNum))
00565 return QSPID_ERROR_LOCK;
00566
00567 return 0;
00568 }
00569
00570
00571
00572
00573
00574
00575
00576
00577
00578
00579
00580 uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite)
00581 {
00582 QspiBuffer_t *pBuffer = &pQspidma->Qspid.qspiBuffer;
00583 uint32_t semTimer = 0x7FF;
00584
00585 assert(pBuffer->pDataRx);
00586 assert(pBuffer->pDataTx);
00587
00588
00589 if (pQspidma->progress)
00590
00591 return QSPID_ERROR_LOCK;
00592
00593 LockMutex(pQspidma->progress, semTimer);
00594
00595 if (QSPID_configureQpsiDma
00596 (pQspidma, pQspidma->Qspid.pQspiFrame->Addr, pBuffer, ReadWrite))
00597 return QSPID_ERROR_LOCK;
00598
00599 SCB_CleanDCache_by_Addr((uint32_t *)pBuffer->pDataTx, pBuffer->TxDataSize);
00600
00601
00602 if (XDMAD_StartTransfer(pQspidma->pXdmad, pQspidma->RxChNum))
00603 return QSPID_ERROR_LOCK;
00604
00605 if (XDMAD_StartTransfer(pQspidma->pXdmad, pQspidma->TxChNum))
00606 return QSPID_ERROR_LOCK;
00607
00608 return 0;
00609 }
00610
00611
00612
00613
00614
00615
00616
00617 uint32_t QSPID_IsBusy(volatile uint8_t *QspiSemaphore)
00618 {
00619 if (Is_LockFree(QspiSemaphore))
00620 return 1;
00621 else
00622 return 0;
00623 }