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00030 #ifndef _MPU_H_
00031 #define _MPU_H_
00032
00033
00034
00035
00036 #define ARM_MODE_USR 0x10
00037
00038 #define PRIVILEGE_MODE 0
00039 #define USER_MODE 1
00040
00041 #define MPU_DEFAULT_ITCM_REGION (1)
00042 #define MPU_DEFAULT_IFLASH_REGION (2)
00043 #define MPU_DEFAULT_DTCM_REGION (3)
00044 #define MPU_DEFAULT_SRAM_REGION_1 (4)
00045 #define MPU_DEFAULT_SRAM_REGION_2 (5)
00046 #define MPU_PERIPHERALS_REGION (6)
00047 #define MPU_EXT_EBI_REGION (7)
00048 #define MPU_DEFAULT_SDRAM_REGION (8)
00049 #define MPU_QSPIMEM_REGION (9)
00050 #define MPU_USBHSRAM_REGION (10)
00051 #if defined MPU_HAS_NOCACHE_REGION
00052 #define MPU_NOCACHE_SRAM_REGION (11)
00053 #endif
00054
00055 #define MPU_REGION_VALID (0x10)
00056 #define MPU_REGION_ENABLE (0x01)
00057 #define MPU_REGION_DISABLE (0x0)
00058
00059 #define MPU_ENABLE (0x1 << MPU_CTRL_ENABLE_Pos)
00060 #define MPU_HFNMIENA (0x1 << MPU_CTRL_HFNMIENA_Pos)
00061 #define MPU_PRIVDEFENA (0x1 << MPU_CTRL_PRIVDEFENA_Pos)
00062
00063
00064 #define MPU_REGION_BUFFERABLE (0x01 << MPU_RASR_B_Pos)
00065 #define MPU_REGION_CACHEABLE (0x01 << MPU_RASR_C_Pos)
00066 #define MPU_REGION_SHAREABLE (0x01 << MPU_RASR_S_Pos)
00067
00068 #define MPU_REGION_EXECUTE_NEVER (0x01 << MPU_RASR_XN_Pos)
00069
00070 #define MPU_AP_NO_ACCESS (0x00 << MPU_RASR_AP_Pos)
00071 #define MPU_AP_PRIVILEGED_READ_WRITE (0x01 << MPU_RASR_AP_Pos)
00072 #define MPU_AP_UNPRIVILEGED_READONLY (0x02 << MPU_RASR_AP_Pos)
00073 #define MPU_AP_FULL_ACCESS (0x03 << MPU_RASR_AP_Pos)
00074 #define MPU_AP_RES (0x04 << MPU_RASR_AP_Pos)
00075 #define MPU_AP_PRIVILEGED_READONLY (0x05 << MPU_RASR_AP_Pos)
00076 #define MPU_AP_READONLY (0x06 << MPU_RASR_AP_Pos)
00077 #define MPU_AP_READONLY2 (0x07 << MPU_RASR_AP_Pos)
00078
00079 #define MPU_TEX_B000 (0x01 << MPU_RASR_TEX_Pos)
00080 #define MPU_TEX_B001 (0x01 << MPU_RASR_TEX_Pos)
00081 #define MPU_TEX_B010 (0x01 << MPU_RASR_TEX_Pos)
00082 #define MPU_TEX_B011 (0x01 << MPU_RASR_TEX_Pos)
00083 #define MPU_TEX_B100 (0x01 << MPU_RASR_TEX_Pos)
00084 #define MPU_TEX_B101 (0x01 << MPU_RASR_TEX_Pos)
00085 #define MPU_TEX_B110 (0x01 << MPU_RASR_TEX_Pos)
00086 #define MPU_TEX_B111 (0x01 << MPU_RASR_TEX_Pos)
00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101 #define ITCM_START_ADDRESS 0x00000000UL
00102 #define ITCM_END_ADDRESS 0x003FFFFFUL
00103 #define IFLASH_START_ADDRESS 0x00400000UL
00104 #define IFLASH_END_ADDRESS 0x005FFFFFUL
00105
00106
00107 #define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS)
00108 #define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF)
00109
00110 #define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1)
00111 #define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS)
00112
00113
00114 #define DTCM_START_ADDRESS 0x20000000UL
00115 #define DTCM_END_ADDRESS 0x203FFFFFUL
00116
00117
00118
00119
00120 #define SRAM_START_ADDRESS 0x20400000UL
00121 #define SRAM_END_ADDRESS 0x2045FFFFUL
00122
00123 #if defined MPU_HAS_NOCACHE_REGION
00124 #define NOCACHE_SRAM_REGION_SIZE 0x1000
00125 #endif
00126
00127
00128 #define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
00129 #define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
00130
00131 #if defined MPU_HAS_NOCACHE_REGION
00132 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
00133 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
00134 #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
00135 #define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
00136 #else
00137 #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
00138 #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
00139 #endif
00140
00141 #define PERIPHERALS_START_ADDRESS 0x40000000UL
00142 #define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
00143
00144
00145 #define EXT_EBI_START_ADDRESS 0x60000000UL
00146 #define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL
00147
00148
00149 #define SDRAM_START_ADDRESS 0x70000000UL
00150 #define SDRAM_END_ADDRESS 0x7FFFFFFFUL
00151
00152
00153 #define QSPI_START_ADDRESS 0x80000000UL
00154 #define QSPI_END_ADDRESS 0x9FFFFFFFUL
00155
00156
00157 #define USBHSRAM_START_ADDRESS 0xA0100000UL
00158 #define USBHSRAM_END_ADDRESS 0xA01FFFFFUL
00159
00160
00161
00162
00163 void MPU_Enable(uint32_t dwMPUEnable);
00164 void MPU_SetRegion(uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr);
00165 void MPU_SetRegionNum(uint32_t dwRegionNum);
00166 void MPU_DisableRegion(void);
00167 uint32_t MPU_CalMPURegionSize(uint32_t dwActualSizeInBytes);
00168 void MPU_UpdateRegions(uint32_t dwRegionNum, uint32_t dwRegionBaseAddr,
00169 uint32_t dwRegionAttr);
00170
00171 #endif
00172