SAMV71 Xplained Ultra Software Package 1.5

instance_spi0.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_SPI0_INSTANCE_
00031 #define _SAMV71_SPI0_INSTANCE_
00032 
00033 /* ========== Register definition for SPI0 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_SPI0_CR                       (0x40008000U) /**< \brief (SPI0) Control Register */
00036   #define REG_SPI0_MR                       (0x40008004U) /**< \brief (SPI0) Mode Register */
00037   #define REG_SPI0_RDR                      (0x40008008U) /**< \brief (SPI0) Receive Data Register */
00038   #define REG_SPI0_TDR                      (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
00039   #define REG_SPI0_SR                       (0x40008010U) /**< \brief (SPI0) Status Register */
00040   #define REG_SPI0_IER                      (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
00041   #define REG_SPI0_IDR                      (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
00042   #define REG_SPI0_IMR                      (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
00043   #define REG_SPI0_CSR                      (0x40008030U) /**< \brief (SPI0) Chip Select Register */
00044   #define REG_SPI0_WPMR                     (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */
00045   #define REG_SPI0_WPSR                     (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
00046   #define REG_SPI0_VERSION                  (0x400080FCU) /**< \brief (SPI0) Version Register */
00047 #else
00048   #define REG_SPI0_CR      (*(__O  uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */
00049   #define REG_SPI0_MR      (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */
00050   #define REG_SPI0_RDR     (*(__I  uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */
00051   #define REG_SPI0_TDR     (*(__O  uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */
00052   #define REG_SPI0_SR      (*(__I  uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */
00053   #define REG_SPI0_IER     (*(__O  uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */
00054   #define REG_SPI0_IDR     (*(__O  uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */
00055   #define REG_SPI0_IMR     (*(__I  uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */
00056   #define REG_SPI0_CSR     (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register */
00057   #define REG_SPI0_WPMR    (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */
00058   #define REG_SPI0_WPSR    (*(__I  uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */
00059   #define REG_SPI0_VERSION (*(__I  uint32_t*)0x400080FCU) /**< \brief (SPI0) Version Register */
00060 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00061 
00062 #endif /* _SAMV71_SPI0_INSTANCE_ */
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