00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_MLB_INSTANCE_ 00031 #define _SAMV71_MLB_INSTANCE_ 00032 00033 /* ========== Register definition for MLB peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_MLB_MLBC0 (0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ 00036 #define REG_MLB_MS0 (0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ 00037 #define REG_MLB_MS1 (0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ 00038 #define REG_MLB_MSS (0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ 00039 #define REG_MLB_MSD (0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ 00040 #define REG_MLB_MIEN (0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ 00041 #define REG_MLB_MLBC1 (0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ 00042 #define REG_MLB_HCTL (0x40068080U) /**< \brief (MLB) HBI Control Register */ 00043 #define REG_MLB_HCMR (0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ 00044 #define REG_MLB_HCER (0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ 00045 #define REG_MLB_HCBR (0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ 00046 #define REG_MLB_MDAT (0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ 00047 #define REG_MLB_MDWE (0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ 00048 #define REG_MLB_MCTL (0x400680E0U) /**< \brief (MLB) MIF Control Register */ 00049 #define REG_MLB_MADR (0x400680E4U) /**< \brief (MLB) MIF Address Register */ 00050 #define REG_MLB_ACTL (0x400683C0U) /**< \brief (MLB) AHB Control Register */ 00051 #define REG_MLB_ACSR (0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ 00052 #define REG_MLB_ACMR (0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ 00053 #else 00054 #define REG_MLB_MLBC0 (*(__IO uint32_t*)0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ 00055 #define REG_MLB_MS0 (*(__IO uint32_t*)0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ 00056 #define REG_MLB_MS1 (*(__IO uint32_t*)0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ 00057 #define REG_MLB_MSS (*(__IO uint32_t*)0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ 00058 #define REG_MLB_MSD (*(__I uint32_t*)0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ 00059 #define REG_MLB_MIEN (*(__IO uint32_t*)0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ 00060 #define REG_MLB_MLBC1 (*(__IO uint32_t*)0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ 00061 #define REG_MLB_HCTL (*(__IO uint32_t*)0x40068080U) /**< \brief (MLB) HBI Control Register */ 00062 #define REG_MLB_HCMR (*(__IO uint32_t*)0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ 00063 #define REG_MLB_HCER (*(__I uint32_t*)0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ 00064 #define REG_MLB_HCBR (*(__I uint32_t*)0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ 00065 #define REG_MLB_MDAT (*(__IO uint32_t*)0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ 00066 #define REG_MLB_MDWE (*(__IO uint32_t*)0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ 00067 #define REG_MLB_MCTL (*(__IO uint32_t*)0x400680E0U) /**< \brief (MLB) MIF Control Register */ 00068 #define REG_MLB_MADR (*(__IO uint32_t*)0x400680E4U) /**< \brief (MLB) MIF Address Register */ 00069 #define REG_MLB_ACTL (*(__IO uint32_t*)0x400683C0U) /**< \brief (MLB) AHB Control Register */ 00070 #define REG_MLB_ACSR (*(__IO uint32_t*)0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ 00071 #define REG_MLB_ACMR (*(__IO uint32_t*)0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ 00072 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00073 00074 #endif /* _SAMV71_MLB_INSTANCE_ */