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00030 #ifndef _SAMV71_GMAC_COMPONENT_
00031 #define _SAMV71_GMAC_COMPONENT_
00032
00033
00034
00035
00036
00037
00038
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040
00041 typedef struct {
00042 __IO uint32_t GMAC_SAB;
00043 __IO uint32_t GMAC_SAT;
00044 } GmacSa;
00045
00046
00047 typedef struct {
00048 __IO uint32_t GMAC_ST2COM0;
00049 __IO uint32_t GMAC_ST2COM1;
00050 } GmacSt2Compare;
00051
00052
00053 #define GMACSA_NUMBER 4
00054 #define GMACST2COMPARE_NUMBER 24
00055 typedef struct {
00056 __IO uint32_t GMAC_NCR;
00057 __IO uint32_t GMAC_NCFGR;
00058 __I uint32_t GMAC_NSR;
00059 __IO uint32_t GMAC_UR;
00060 __IO uint32_t GMAC_DCFGR;
00061 __IO uint32_t GMAC_TSR;
00062 __IO uint32_t GMAC_RBQB;
00063 __IO uint32_t GMAC_TBQB;
00064 __IO uint32_t GMAC_RSR;
00065 __I uint32_t GMAC_ISR;
00066 __O uint32_t GMAC_IER;
00067 __O uint32_t GMAC_IDR;
00068 __IO uint32_t GMAC_IMR;
00069 __IO uint32_t GMAC_MAN;
00070 __I uint32_t GMAC_RPQ;
00071 __IO uint32_t GMAC_TPQ;
00072 __IO uint32_t GMAC_TPSF;
00073 __IO uint32_t GMAC_RPSF;
00074 __IO uint32_t GMAC_RJFML;
00075 __I uint32_t Reserved1[13];
00076 __IO uint32_t GMAC_HRB;
00077 __IO uint32_t GMAC_HRT;
00078 GmacSa GMAC_SA[GMACSA_NUMBER];
00079 __IO uint32_t GMAC_TIDM1;
00080 __IO uint32_t GMAC_TIDM2;
00081 __IO uint32_t GMAC_TIDM3;
00082 __IO uint32_t GMAC_TIDM4;
00083 __IO uint32_t GMAC_WOL;
00084 __IO uint32_t GMAC_IPGS;
00085 __IO uint32_t GMAC_SVLAN;
00086 __IO uint32_t GMAC_TPFCP;
00087 __IO uint32_t GMAC_SAMB1;
00088 __IO uint32_t GMAC_SAMT1;
00089 __I uint32_t Reserved2[3];
00090 __IO uint32_t GMAC_NSC;
00091 __IO uint32_t GMAC_SCL;
00092 __IO uint32_t GMAC_SCH;
00093 __I uint32_t GMAC_EFTSH;
00094 __I uint32_t GMAC_EFRSH;
00095 __I uint32_t GMAC_PEFTSH;
00096 __I uint32_t GMAC_PEFRSH;
00097 __I uint32_t Reserved3[1];
00098 __I uint32_t GMAC_MID;
00099 __I uint32_t GMAC_OTLO;
00100 __I uint32_t GMAC_OTHI;
00101 __I uint32_t GMAC_FT;
00102 __I uint32_t GMAC_BCFT;
00103 __I uint32_t GMAC_MFT;
00104 __I uint32_t GMAC_PFT;
00105 __I uint32_t GMAC_BFT64;
00106 __I uint32_t GMAC_TBFT127;
00107 __I uint32_t GMAC_TBFT255;
00108 __I uint32_t GMAC_TBFT511;
00109 __I uint32_t GMAC_TBFT1023;
00110 __I uint32_t GMAC_TBFT1518;
00111 __I uint32_t GMAC_GTBFT1518;
00112 __I uint32_t GMAC_TUR;
00113 __I uint32_t GMAC_SCF;
00114 __I uint32_t GMAC_MCF;
00115 __I uint32_t GMAC_EC;
00116 __I uint32_t GMAC_LC;
00117 __I uint32_t GMAC_DTF;
00118 __I uint32_t GMAC_CSE;
00119 __I uint32_t GMAC_ORLO;
00120 __I uint32_t GMAC_ORHI;
00121 __I uint32_t GMAC_FR;
00122 __I uint32_t GMAC_BCFR;
00123 __I uint32_t GMAC_MFR;
00124 __I uint32_t GMAC_PFR;
00125 __I uint32_t GMAC_BFR64;
00126 __I uint32_t GMAC_TBFR127;
00127 __I uint32_t GMAC_TBFR255;
00128 __I uint32_t GMAC_TBFR511;
00129 __I uint32_t GMAC_TBFR1023;
00130 __I uint32_t GMAC_TBFR1518;
00131 __I uint32_t GMAC_TMXBFR;
00132 __I uint32_t GMAC_UFR;
00133 __I uint32_t GMAC_OFR;
00134 __I uint32_t GMAC_JR;
00135 __I uint32_t GMAC_FCSE;
00136 __I uint32_t GMAC_LFFE;
00137 __I uint32_t GMAC_RSE;
00138 __I uint32_t GMAC_AE;
00139 __I uint32_t GMAC_RRE;
00140 __I uint32_t GMAC_ROE;
00141 __I uint32_t GMAC_IHCE;
00142 __I uint32_t GMAC_TCE;
00143 __I uint32_t GMAC_UCE;
00144 __I uint32_t Reserved4[2];
00145 __IO uint32_t GMAC_TISUBN;
00146 __IO uint32_t GMAC_TSH;
00147 __I uint32_t Reserved5[3];
00148 __IO uint32_t GMAC_TSL;
00149 __IO uint32_t GMAC_TN;
00150 __O uint32_t GMAC_TA;
00151 __IO uint32_t GMAC_TI;
00152 __I uint32_t GMAC_EFTSL;
00153 __I uint32_t GMAC_EFTN;
00154 __I uint32_t GMAC_EFRSL;
00155 __I uint32_t GMAC_EFRN;
00156 __I uint32_t GMAC_PEFTSL;
00157 __I uint32_t GMAC_PEFTN;
00158 __I uint32_t GMAC_PEFRSL;
00159 __I uint32_t GMAC_PEFRN;
00160 __I uint32_t Reserved6[128];
00161 __I uint32_t GMAC_ISRPQ[2];
00162 __I uint32_t Reserved7[14];
00163 __IO uint32_t GMAC_TBQBAPQ[2];
00164 __I uint32_t Reserved8[14];
00165 __IO uint32_t GMAC_RBQBAPQ[2];
00166 __I uint32_t Reserved9[6];
00167 __IO uint32_t GMAC_RBSRPQ[2];
00168 __I uint32_t Reserved10[5];
00169 __IO uint32_t GMAC_CBSCR;
00170 __IO uint32_t GMAC_CBSISQA;
00171 __IO uint32_t GMAC_CBSISQB;
00172 __I uint32_t Reserved11[14];
00173 __IO uint32_t GMAC_ST1RPQ[4];
00174 __I uint32_t Reserved12[12];
00175 __IO uint32_t GMAC_ST2RPQ[8];
00176 __I uint32_t Reserved13[12];
00177 __I uint32_t Reserved14[28];
00178 __O uint32_t GMAC_IERPQ[2];
00179 __I uint32_t Reserved15[6];
00180 __O uint32_t GMAC_IDRPQ[2];
00181 __I uint32_t Reserved16[6];
00182 __IO uint32_t GMAC_IMRPQ[2];
00183 __I uint32_t Reserved17[38];
00184 __IO uint32_t GMAC_ST2ER[4];
00185 __I uint32_t Reserved18[4];
00186 __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];
00187 } Gmac;
00188 #endif
00189
00190 #define GMAC_NCR_LBL (0x1u << 1)
00191 #define GMAC_NCR_RXEN (0x1u << 2)
00192 #define GMAC_NCR_TXEN (0x1u << 3)
00193 #define GMAC_NCR_MPE (0x1u << 4)
00194 #define GMAC_NCR_CLRSTAT (0x1u << 5)
00195 #define GMAC_NCR_INCSTAT (0x1u << 6)
00196 #define GMAC_NCR_WESTAT (0x1u << 7)
00197 #define GMAC_NCR_BP (0x1u << 8)
00198 #define GMAC_NCR_TSTART (0x1u << 9)
00199 #define GMAC_NCR_THALT (0x1u << 10)
00200 #define GMAC_NCR_TXPF (0x1u << 11)
00201 #define GMAC_NCR_TXZQPF (0x1u << 12)
00202 #define GMAC_NCR_SRTSM (0x1u << 15)
00203 #define GMAC_NCR_ENPBPR (0x1u << 16)
00204 #define GMAC_NCR_TXPBPF (0x1u << 17)
00205 #define GMAC_NCR_FNP (0x1u << 18)
00206
00207 #define GMAC_NCFGR_SPD (0x1u << 0)
00208 #define GMAC_NCFGR_FD (0x1u << 1)
00209 #define GMAC_NCFGR_DNVLAN (0x1u << 2)
00210 #define GMAC_NCFGR_JFRAME (0x1u << 3)
00211 #define GMAC_NCFGR_CAF (0x1u << 4)
00212 #define GMAC_NCFGR_NBC (0x1u << 5)
00213 #define GMAC_NCFGR_MTIHEN (0x1u << 6)
00214 #define GMAC_NCFGR_UNIHEN (0x1u << 7)
00215 #define GMAC_NCFGR_MAXFS (0x1u << 8)
00216 #define GMAC_NCFGR_RTY (0x1u << 12)
00217 #define GMAC_NCFGR_PEN (0x1u << 13)
00218 #define GMAC_NCFGR_RXBUFO_Pos 14
00219 #define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos)
00220 #define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos)))
00221 #define GMAC_NCFGR_LFERD (0x1u << 16)
00222 #define GMAC_NCFGR_RFCS (0x1u << 17)
00223 #define GMAC_NCFGR_CLK_Pos 18
00224 #define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos)
00225 #define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos)))
00226 #define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18)
00227 #define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18)
00228 #define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18)
00229 #define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18)
00230 #define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18)
00231 #define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18)
00232 #define GMAC_NCFGR_DBW_Pos 21
00233 #define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos)
00234 #define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos)))
00235 #define GMAC_NCFGR_DCPF (0x1u << 23)
00236 #define GMAC_NCFGR_RXCOEN (0x1u << 24)
00237 #define GMAC_NCFGR_EFRHD (0x1u << 25)
00238 #define GMAC_NCFGR_IRXFCS (0x1u << 26)
00239 #define GMAC_NCFGR_IPGSEN (0x1u << 28)
00240 #define GMAC_NCFGR_RXBP (0x1u << 29)
00241 #define GMAC_NCFGR_IRXER (0x1u << 30)
00242
00243 #define GMAC_NSR_MDIO (0x1u << 1)
00244 #define GMAC_NSR_IDLE (0x1u << 2)
00245
00246 #define GMAC_UR_RMII (0x1u << 0)
00247
00248 #define GMAC_DCFGR_FBLDO_Pos 0
00249 #define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos)
00250 #define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos)))
00251 #define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0)
00252 #define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0)
00253 #define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0)
00254 #define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0)
00255 #define GMAC_DCFGR_ESMA (0x1u << 6)
00256 #define GMAC_DCFGR_ESPA (0x1u << 7)
00257 #define GMAC_DCFGR_RXBMS_Pos 8
00258 #define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos)
00259 #define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos)))
00260 #define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8)
00261 #define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8)
00262 #define GMAC_DCFGR_RXBMS_HALF (0x2u << 8)
00263 #define GMAC_DCFGR_RXBMS_FULL (0x3u << 8)
00264 #define GMAC_DCFGR_TXPBMS (0x1u << 10)
00265 #define GMAC_DCFGR_TXCOEN (0x1u << 11)
00266 #define GMAC_DCFGR_DRBS_Pos 16
00267 #define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos)
00268 #define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos)))
00269 #define GMAC_DCFGR_DDRP (0x1u << 24)
00270
00271 #define GMAC_TSR_UBR (0x1u << 0)
00272 #define GMAC_TSR_COL (0x1u << 1)
00273 #define GMAC_TSR_RLE (0x1u << 2)
00274 #define GMAC_TSR_TXGO (0x1u << 3)
00275 #define GMAC_TSR_TFC (0x1u << 4)
00276 #define GMAC_TSR_TXCOMP (0x1u << 5)
00277 #define GMAC_TSR_HRESP (0x1u << 8)
00278
00279 #define GMAC_RBQB_ADDR_Pos 2
00280 #define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos)
00281 #define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos)))
00282
00283 #define GMAC_TBQB_ADDR_Pos 2
00284 #define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos)
00285 #define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos)))
00286
00287 #define GMAC_RSR_BNA (0x1u << 0)
00288 #define GMAC_RSR_REC (0x1u << 1)
00289 #define GMAC_RSR_RXOVR (0x1u << 2)
00290 #define GMAC_RSR_HNO (0x1u << 3)
00291
00292 #define GMAC_ISR_MFS (0x1u << 0)
00293 #define GMAC_ISR_RCOMP (0x1u << 1)
00294 #define GMAC_ISR_RXUBR (0x1u << 2)
00295 #define GMAC_ISR_TXUBR (0x1u << 3)
00296 #define GMAC_ISR_TUR (0x1u << 4)
00297 #define GMAC_ISR_RLEX (0x1u << 5)
00298 #define GMAC_ISR_TFC (0x1u << 6)
00299 #define GMAC_ISR_TCOMP (0x1u << 7)
00300 #define GMAC_ISR_ROVR (0x1u << 10)
00301 #define GMAC_ISR_HRESP (0x1u << 11)
00302 #define GMAC_ISR_PFNZ (0x1u << 12)
00303 #define GMAC_ISR_PTZ (0x1u << 13)
00304 #define GMAC_ISR_PFTR (0x1u << 14)
00305 #define GMAC_ISR_DRQFR (0x1u << 18)
00306 #define GMAC_ISR_SFR (0x1u << 19)
00307 #define GMAC_ISR_DRQFT (0x1u << 20)
00308 #define GMAC_ISR_SFT (0x1u << 21)
00309 #define GMAC_ISR_PDRQFR (0x1u << 22)
00310 #define GMAC_ISR_PDRSFR (0x1u << 23)
00311 #define GMAC_ISR_PDRQFT (0x1u << 24)
00312 #define GMAC_ISR_PDRSFT (0x1u << 25)
00313 #define GMAC_ISR_SRI (0x1u << 26)
00314 #define GMAC_ISR_WOL (0x1u << 28)
00315 #define GMAC_ISR_TSU (0x1u << 29)
00316
00317 #define GMAC_IER_MFS (0x1u << 0)
00318 #define GMAC_IER_RCOMP (0x1u << 1)
00319 #define GMAC_IER_RXUBR (0x1u << 2)
00320 #define GMAC_IER_TXUBR (0x1u << 3)
00321 #define GMAC_IER_TUR (0x1u << 4)
00322 #define GMAC_IER_RLEX (0x1u << 5)
00323 #define GMAC_IER_TFC (0x1u << 6)
00324 #define GMAC_IER_TCOMP (0x1u << 7)
00325 #define GMAC_IER_ROVR (0x1u << 10)
00326 #define GMAC_IER_HRESP (0x1u << 11)
00327 #define GMAC_IER_PFNZ (0x1u << 12)
00328 #define GMAC_IER_PTZ (0x1u << 13)
00329 #define GMAC_IER_PFTR (0x1u << 14)
00330 #define GMAC_IER_EXINT (0x1u << 15)
00331 #define GMAC_IER_DRQFR (0x1u << 18)
00332 #define GMAC_IER_SFR (0x1u << 19)
00333 #define GMAC_IER_DRQFT (0x1u << 20)
00334 #define GMAC_IER_SFT (0x1u << 21)
00335 #define GMAC_IER_PDRQFR (0x1u << 22)
00336 #define GMAC_IER_PDRSFR (0x1u << 23)
00337 #define GMAC_IER_PDRQFT (0x1u << 24)
00338 #define GMAC_IER_PDRSFT (0x1u << 25)
00339 #define GMAC_IER_SRI (0x1u << 26)
00340 #define GMAC_IER_WOL (0x1u << 28)
00341
00342 #define GMAC_IDR_MFS (0x1u << 0)
00343 #define GMAC_IDR_RCOMP (0x1u << 1)
00344 #define GMAC_IDR_RXUBR (0x1u << 2)
00345 #define GMAC_IDR_TXUBR (0x1u << 3)
00346 #define GMAC_IDR_TUR (0x1u << 4)
00347 #define GMAC_IDR_RLEX (0x1u << 5)
00348 #define GMAC_IDR_TFC (0x1u << 6)
00349 #define GMAC_IDR_TCOMP (0x1u << 7)
00350 #define GMAC_IDR_ROVR (0x1u << 10)
00351 #define GMAC_IDR_HRESP (0x1u << 11)
00352 #define GMAC_IDR_PFNZ (0x1u << 12)
00353 #define GMAC_IDR_PTZ (0x1u << 13)
00354 #define GMAC_IDR_PFTR (0x1u << 14)
00355 #define GMAC_IDR_EXINT (0x1u << 15)
00356 #define GMAC_IDR_DRQFR (0x1u << 18)
00357 #define GMAC_IDR_SFR (0x1u << 19)
00358 #define GMAC_IDR_DRQFT (0x1u << 20)
00359 #define GMAC_IDR_SFT (0x1u << 21)
00360 #define GMAC_IDR_PDRQFR (0x1u << 22)
00361 #define GMAC_IDR_PDRSFR (0x1u << 23)
00362 #define GMAC_IDR_PDRQFT (0x1u << 24)
00363 #define GMAC_IDR_PDRSFT (0x1u << 25)
00364 #define GMAC_IDR_SRI (0x1u << 26)
00365 #define GMAC_IDR_WOL (0x1u << 28)
00366
00367 #define GMAC_IMR_MFS (0x1u << 0)
00368 #define GMAC_IMR_RCOMP (0x1u << 1)
00369 #define GMAC_IMR_RXUBR (0x1u << 2)
00370 #define GMAC_IMR_TXUBR (0x1u << 3)
00371 #define GMAC_IMR_TUR (0x1u << 4)
00372 #define GMAC_IMR_RLEX (0x1u << 5)
00373 #define GMAC_IMR_TFC (0x1u << 6)
00374 #define GMAC_IMR_TCOMP (0x1u << 7)
00375 #define GMAC_IMR_ROVR (0x1u << 10)
00376 #define GMAC_IMR_HRESP (0x1u << 11)
00377 #define GMAC_IMR_PFNZ (0x1u << 12)
00378 #define GMAC_IMR_PTZ (0x1u << 13)
00379 #define GMAC_IMR_PFTR (0x1u << 14)
00380 #define GMAC_IMR_EXINT (0x1u << 15)
00381 #define GMAC_IMR_DRQFR (0x1u << 18)
00382 #define GMAC_IMR_SFR (0x1u << 19)
00383 #define GMAC_IMR_DRQFT (0x1u << 20)
00384 #define GMAC_IMR_SFT (0x1u << 21)
00385 #define GMAC_IMR_PDRQFR (0x1u << 22)
00386 #define GMAC_IMR_PDRSFR (0x1u << 23)
00387 #define GMAC_IMR_PDRQFT (0x1u << 24)
00388 #define GMAC_IMR_PDRSFT (0x1u << 25)
00389
00390 #define GMAC_MAN_DATA_Pos 0
00391 #define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos)
00392 #define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos)))
00393 #define GMAC_MAN_WTN_Pos 16
00394 #define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos)
00395 #define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos)))
00396 #define GMAC_MAN_REGA_Pos 18
00397 #define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos)
00398 #define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos)))
00399 #define GMAC_MAN_PHYA_Pos 23
00400 #define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos)
00401 #define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos)))
00402 #define GMAC_MAN_OP_Pos 28
00403 #define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos)
00404 #define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos)))
00405 #define GMAC_MAN_CLTTO (0x1u << 30)
00406 #define GMAC_MAN_WZO (0x1u << 31)
00407
00408 #define GMAC_RPQ_RPQ_Pos 0
00409 #define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos)
00410
00411 #define GMAC_TPQ_TPQ_Pos 0
00412 #define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos)
00413 #define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos)))
00414
00415 #define GMAC_TPSF_TPB1ADR_Pos 0
00416 #define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos)
00417 #define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos)))
00418 #define GMAC_TPSF_ENTXP (0x1u << 31)
00419
00420 #define GMAC_RPSF_RPB1ADR_Pos 0
00421 #define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos)
00422 #define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos)))
00423 #define GMAC_RPSF_ENRXP (0x1u << 31)
00424
00425 #define GMAC_RJFML_FML_Pos 0
00426 #define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos)
00427 #define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos)))
00428
00429 #define GMAC_HRB_ADDR_Pos 0
00430 #define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos)
00431 #define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos)))
00432
00433 #define GMAC_HRT_ADDR_Pos 0
00434 #define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos)
00435 #define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos)))
00436
00437 #define GMAC_SAB_ADDR_Pos 0
00438 #define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos)
00439 #define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos)))
00440
00441 #define GMAC_SAT_ADDR_Pos 0
00442 #define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos)
00443 #define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos)))
00444
00445 #define GMAC_TIDM1_TID_Pos 0
00446 #define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos)
00447 #define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos)))
00448 #define GMAC_TIDM1_ENID1 (0x1u << 31)
00449
00450 #define GMAC_TIDM2_TID_Pos 0
00451 #define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos)
00452 #define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos)))
00453 #define GMAC_TIDM2_ENID2 (0x1u << 31)
00454
00455 #define GMAC_TIDM3_TID_Pos 0
00456 #define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos)
00457 #define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos)))
00458 #define GMAC_TIDM3_ENID3 (0x1u << 31)
00459
00460 #define GMAC_TIDM4_TID_Pos 0
00461 #define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos)
00462 #define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos)))
00463 #define GMAC_TIDM4_ENID4 (0x1u << 31)
00464
00465 #define GMAC_WOL_IP_Pos 0
00466 #define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos)
00467 #define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos)))
00468 #define GMAC_WOL_MAG (0x1u << 16)
00469 #define GMAC_WOL_ARP (0x1u << 17)
00470 #define GMAC_WOL_SA1 (0x1u << 18)
00471 #define GMAC_WOL_MTI (0x1u << 19)
00472
00473 #define GMAC_IPGS_FL_Pos 0
00474 #define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos)
00475 #define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos)))
00476
00477 #define GMAC_SVLAN_VLAN_TYPE_Pos 0
00478 #define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos)
00479 #define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos)))
00480 #define GMAC_SVLAN_ESVLAN (0x1u << 31)
00481
00482 #define GMAC_TPFCP_PEV_Pos 0
00483 #define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos)
00484 #define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos)))
00485 #define GMAC_TPFCP_PQ_Pos 8
00486 #define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos)
00487 #define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos)))
00488
00489 #define GMAC_SAMB1_ADDR_Pos 0
00490 #define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos)
00491 #define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos)))
00492
00493 #define GMAC_SAMT1_ADDR_Pos 0
00494 #define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos)
00495 #define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos)))
00496
00497 #define GMAC_NSC_NANOSEC_Pos 0
00498 #define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos)
00499 #define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos)))
00500
00501 #define GMAC_SCL_SEC_Pos 0
00502 #define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos)
00503 #define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos)))
00504
00505 #define GMAC_SCH_SEC_Pos 0
00506 #define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos)
00507 #define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos)))
00508
00509 #define GMAC_EFTSH_RUD_Pos 0
00510 #define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos)
00511
00512 #define GMAC_EFRSH_RUD_Pos 0
00513 #define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos)
00514
00515 #define GMAC_PEFTSH_RUD_Pos 0
00516 #define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos)
00517
00518 #define GMAC_PEFRSH_RUD_Pos 0
00519 #define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos)
00520
00521 #define GMAC_MID_MREV_Pos 0
00522 #define GMAC_MID_MREV_Msk (0xffffu << GMAC_MID_MREV_Pos)
00523 #define GMAC_MID_MID_Pos 16
00524 #define GMAC_MID_MID_Msk (0xffffu << GMAC_MID_MID_Pos)
00525
00526 #define GMAC_OTLO_TXO_Pos 0
00527 #define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos)
00528
00529 #define GMAC_OTHI_TXO_Pos 0
00530 #define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos)
00531
00532 #define GMAC_FT_FTX_Pos 0
00533 #define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos)
00534
00535 #define GMAC_BCFT_BFTX_Pos 0
00536 #define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos)
00537
00538 #define GMAC_MFT_MFTX_Pos 0
00539 #define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos)
00540
00541 #define GMAC_PFT_PFTX_Pos 0
00542 #define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos)
00543
00544 #define GMAC_BFT64_NFTX_Pos 0
00545 #define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos)
00546
00547 #define GMAC_TBFT127_NFTX_Pos 0
00548 #define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos)
00549
00550 #define GMAC_TBFT255_NFTX_Pos 0
00551 #define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos)
00552
00553 #define GMAC_TBFT511_NFTX_Pos 0
00554 #define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos)
00555
00556 #define GMAC_TBFT1023_NFTX_Pos 0
00557 #define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos)
00558
00559 #define GMAC_TBFT1518_NFTX_Pos 0
00560 #define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos)
00561
00562 #define GMAC_GTBFT1518_NFTX_Pos 0
00563 #define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos)
00564
00565 #define GMAC_TUR_TXUNR_Pos 0
00566 #define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos)
00567
00568 #define GMAC_SCF_SCOL_Pos 0
00569 #define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos)
00570
00571 #define GMAC_MCF_MCOL_Pos 0
00572 #define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos)
00573
00574 #define GMAC_EC_XCOL_Pos 0
00575 #define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos)
00576
00577 #define GMAC_LC_LCOL_Pos 0
00578 #define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos)
00579
00580 #define GMAC_DTF_DEFT_Pos 0
00581 #define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos)
00582
00583 #define GMAC_CSE_CSR_Pos 0
00584 #define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos)
00585
00586 #define GMAC_ORLO_RXO_Pos 0
00587 #define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos)
00588
00589 #define GMAC_ORHI_RXO_Pos 0
00590 #define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos)
00591
00592 #define GMAC_FR_FRX_Pos 0
00593 #define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos)
00594
00595 #define GMAC_BCFR_BFRX_Pos 0
00596 #define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos)
00597
00598 #define GMAC_MFR_MFRX_Pos 0
00599 #define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos)
00600
00601 #define GMAC_PFR_PFRX_Pos 0
00602 #define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos)
00603
00604 #define GMAC_BFR64_NFRX_Pos 0
00605 #define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos)
00606
00607 #define GMAC_TBFR127_NFRX_Pos 0
00608 #define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos)
00609
00610 #define GMAC_TBFR255_NFRX_Pos 0
00611 #define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos)
00612
00613 #define GMAC_TBFR511_NFRX_Pos 0
00614 #define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos)
00615
00616 #define GMAC_TBFR1023_NFRX_Pos 0
00617 #define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos)
00618
00619 #define GMAC_TBFR1518_NFRX_Pos 0
00620 #define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos)
00621
00622 #define GMAC_TMXBFR_NFRX_Pos 0
00623 #define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos)
00624
00625 #define GMAC_UFR_UFRX_Pos 0
00626 #define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos)
00627
00628 #define GMAC_OFR_OFRX_Pos 0
00629 #define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos)
00630
00631 #define GMAC_JR_JRX_Pos 0
00632 #define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos)
00633
00634 #define GMAC_FCSE_FCKR_Pos 0
00635 #define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos)
00636
00637 #define GMAC_LFFE_LFER_Pos 0
00638 #define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos)
00639
00640 #define GMAC_RSE_RXSE_Pos 0
00641 #define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos)
00642
00643 #define GMAC_AE_AER_Pos 0
00644 #define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos)
00645
00646 #define GMAC_RRE_RXRER_Pos 0
00647 #define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos)
00648
00649 #define GMAC_ROE_RXOVR_Pos 0
00650 #define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos)
00651
00652 #define GMAC_IHCE_HCKER_Pos 0
00653 #define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos)
00654
00655 #define GMAC_TCE_TCKER_Pos 0
00656 #define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos)
00657
00658 #define GMAC_UCE_UCKER_Pos 0
00659 #define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos)
00660
00661 #define GMAC_TISUBN_LSBTIR_Pos 0
00662 #define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos)
00663 #define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos)))
00664
00665 #define GMAC_TSH_TCS_Pos 0
00666 #define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos)
00667 #define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos)))
00668
00669 #define GMAC_TSL_TCS_Pos 0
00670 #define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos)
00671 #define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos)))
00672
00673 #define GMAC_TN_TNS_Pos 0
00674 #define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos)
00675 #define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos)))
00676
00677 #define GMAC_TA_ITDT_Pos 0
00678 #define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos)
00679 #define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos)))
00680 #define GMAC_TA_ADJ (0x1u << 31)
00681
00682 #define GMAC_TI_CNS_Pos 0
00683 #define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos)
00684 #define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos)))
00685 #define GMAC_TI_ACNS_Pos 8
00686 #define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos)
00687 #define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos)))
00688 #define GMAC_TI_NIT_Pos 16
00689 #define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos)
00690 #define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos)))
00691
00692 #define GMAC_EFTSL_RUD_Pos 0
00693 #define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos)
00694
00695 #define GMAC_EFTN_RUD_Pos 0
00696 #define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos)
00697
00698 #define GMAC_EFRSL_RUD_Pos 0
00699 #define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos)
00700
00701 #define GMAC_EFRN_RUD_Pos 0
00702 #define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos)
00703
00704 #define GMAC_PEFTSL_RUD_Pos 0
00705 #define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos)
00706
00707 #define GMAC_PEFTN_RUD_Pos 0
00708 #define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos)
00709
00710 #define GMAC_PEFRSL_RUD_Pos 0
00711 #define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos)
00712
00713 #define GMAC_PEFRN_RUD_Pos 0
00714 #define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos)
00715
00716 #define GMAC_ISRPQ_RCOMP (0x1u << 1)
00717 #define GMAC_ISRPQ_RXUBR (0x1u << 2)
00718 #define GMAC_ISRPQ_RLEX (0x1u << 5)
00719 #define GMAC_ISRPQ_TFC (0x1u << 6)
00720 #define GMAC_ISRPQ_TCOMP (0x1u << 7)
00721 #define GMAC_ISRPQ_ROVR (0x1u << 10)
00722 #define GMAC_ISRPQ_HRESP (0x1u << 11)
00723
00724 #define GMAC_TBQBAPQ_TXBQBA_Pos 2
00725 #define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fffffffu << GMAC_TBQBAPQ_TXBQBA_Pos)
00726 #define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos)))
00727
00728 #define GMAC_RBQBAPQ_RXBQBA_Pos 2
00729 #define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fffffffu << GMAC_RBQBAPQ_RXBQBA_Pos)
00730 #define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos)))
00731
00732 #define GMAC_RBSRPQ_RBS_Pos 0
00733 #define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos)
00734 #define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos)))
00735
00736 #define GMAC_CBSCR_QBE (0x1u << 0)
00737 #define GMAC_CBSCR_QAE (0x1u << 1)
00738
00739 #define GMAC_CBSISQA_IS_Pos 0
00740 #define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos)
00741 #define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos)))
00742
00743 #define GMAC_CBSISQB_IS_Pos 0
00744 #define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos)
00745 #define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos)))
00746
00747 #define GMAC_ST1RPQ_QNB_Pos 0
00748 #define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos)
00749 #define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos)))
00750 #define GMAC_ST1RPQ_DSTCM_Pos 4
00751 #define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos)
00752 #define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos)))
00753 #define GMAC_ST1RPQ_UDPM_Pos 12
00754 #define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos)
00755 #define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos)))
00756 #define GMAC_ST1RPQ_DSTCE (0x1u << 28)
00757 #define GMAC_ST1RPQ_UDPE (0x1u << 29)
00758
00759 #define GMAC_ST2RPQ_QNB_Pos 0
00760 #define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos)
00761 #define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos)))
00762 #define GMAC_ST2RPQ_VLANP_Pos 4
00763 #define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos)
00764 #define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos)))
00765 #define GMAC_ST2RPQ_VLANE (0x1u << 8)
00766 #define GMAC_ST2RPQ_I2ETH_Pos 9
00767 #define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos)
00768 #define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos)))
00769 #define GMAC_ST2RPQ_ETHE (0x1u << 12)
00770 #define GMAC_ST2RPQ_COMPA_Pos 13
00771 #define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos)
00772 #define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos)))
00773 #define GMAC_ST2RPQ_COMPAE (0x1u << 18)
00774 #define GMAC_ST2RPQ_COMPB_Pos 19
00775 #define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos)
00776 #define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos)))
00777 #define GMAC_ST2RPQ_COMPBE (0x1u << 24)
00778 #define GMAC_ST2RPQ_COMPC_Pos 25
00779 #define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos)
00780 #define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos)))
00781 #define GMAC_ST2RPQ_COMPCE (0x1u << 30)
00782
00783 #define GMAC_IERPQ_RCOMP (0x1u << 1)
00784 #define GMAC_IERPQ_RXUBR (0x1u << 2)
00785 #define GMAC_IERPQ_RLEX (0x1u << 5)
00786 #define GMAC_IERPQ_TFC (0x1u << 6)
00787 #define GMAC_IERPQ_TCOMP (0x1u << 7)
00788 #define GMAC_IERPQ_ROVR (0x1u << 10)
00789 #define GMAC_IERPQ_HRESP (0x1u << 11)
00790
00791 #define GMAC_IDRPQ_RCOMP (0x1u << 1)
00792 #define GMAC_IDRPQ_RXUBR (0x1u << 2)
00793 #define GMAC_IDRPQ_RLEX (0x1u << 5)
00794 #define GMAC_IDRPQ_TFC (0x1u << 6)
00795 #define GMAC_IDRPQ_TCOMP (0x1u << 7)
00796 #define GMAC_IDRPQ_ROVR (0x1u << 10)
00797 #define GMAC_IDRPQ_HRESP (0x1u << 11)
00798
00799 #define GMAC_IMRPQ_RCOMP (0x1u << 1)
00800 #define GMAC_IMRPQ_RXUBR (0x1u << 2)
00801 #define GMAC_IMRPQ_RLEX (0x1u << 5)
00802 #define GMAC_IMRPQ_AHB (0x1u << 6)
00803 #define GMAC_IMRPQ_TCOMP (0x1u << 7)
00804 #define GMAC_IMRPQ_ROVR (0x1u << 10)
00805 #define GMAC_IMRPQ_HRESP (0x1u << 11)
00806
00807 #define GMAC_ST2ER_COMPVAL_Pos 0
00808 #define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos)
00809 #define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos)))
00810
00811 #define GMAC_ST2CW00_MASKVAL_Pos 0
00812 #define GMAC_ST2CW00_MASKVAL_Msk (0xffffu << GMAC_ST2CW00_MASKVAL_Pos)
00813 #define GMAC_ST2CW00_MASKVAL(value) ((GMAC_ST2CW00_MASKVAL_Msk & ((value) << GMAC_ST2CW00_MASKVAL_Pos)))
00814 #define GMAC_ST2CW00_COMPVAL_Pos 16
00815 #define GMAC_ST2CW00_COMPVAL_Msk (0xffffu << GMAC_ST2CW00_COMPVAL_Pos)
00816 #define GMAC_ST2CW00_COMPVAL(value) ((GMAC_ST2CW00_COMPVAL_Msk & ((value) << GMAC_ST2CW00_COMPVAL_Pos)))
00817
00818 #define GMAC_ST2CW10_OFFSVAL_Pos 0
00819 #define GMAC_ST2CW10_OFFSVAL_Msk (0x7fu << GMAC_ST2CW10_OFFSVAL_Pos)
00820 #define GMAC_ST2CW10_OFFSVAL(value) ((GMAC_ST2CW10_OFFSVAL_Msk & ((value) << GMAC_ST2CW10_OFFSVAL_Pos)))
00821 #define GMAC_ST2CW10_OFFSSTRT_Pos 7
00822 #define GMAC_ST2CW10_OFFSSTRT_Msk (0x3u << GMAC_ST2CW10_OFFSSTRT_Pos)
00823 #define GMAC_ST2CW10_OFFSSTRT(value) ((GMAC_ST2CW10_OFFSSTRT_Msk & ((value) << GMAC_ST2CW10_OFFSSTRT_Pos)))
00824 #define GMAC_ST2CW10_OFFSSTRT_FRAMESTART (0x0u << 7)
00825 #define GMAC_ST2CW10_OFFSSTRT_ETHERTYPE (0x1u << 7)
00826 #define GMAC_ST2CW10_OFFSSTRT_IP (0x2u << 7)
00827 #define GMAC_ST2CW10_OFFSSTRT_TCP_UDP (0x3u << 7)
00828
00829 #define GMAC_ST2CW01_MASKVAL_Pos 0
00830 #define GMAC_ST2CW01_MASKVAL_Msk (0xffffu << GMAC_ST2CW01_MASKVAL_Pos)
00831 #define GMAC_ST2CW01_MASKVAL(value) ((GMAC_ST2CW01_MASKVAL_Msk & ((value) << GMAC_ST2CW01_MASKVAL_Pos)))
00832 #define GMAC_ST2CW01_COMPVAL_Pos 16
00833 #define GMAC_ST2CW01_COMPVAL_Msk (0xffffu << GMAC_ST2CW01_COMPVAL_Pos)
00834 #define GMAC_ST2CW01_COMPVAL(value) ((GMAC_ST2CW01_COMPVAL_Msk & ((value) << GMAC_ST2CW01_COMPVAL_Pos)))
00835
00836 #define GMAC_ST2CW11_OFFSVAL_Pos 0
00837 #define GMAC_ST2CW11_OFFSVAL_Msk (0x7fu << GMAC_ST2CW11_OFFSVAL_Pos)
00838 #define GMAC_ST2CW11_OFFSVAL(value) ((GMAC_ST2CW11_OFFSVAL_Msk & ((value) << GMAC_ST2CW11_OFFSVAL_Pos)))
00839 #define GMAC_ST2CW11_OFFSSTRT_Pos 7
00840 #define GMAC_ST2CW11_OFFSSTRT_Msk (0x3u << GMAC_ST2CW11_OFFSSTRT_Pos)
00841 #define GMAC_ST2CW11_OFFSSTRT(value) ((GMAC_ST2CW11_OFFSSTRT_Msk & ((value) << GMAC_ST2CW11_OFFSSTRT_Pos)))
00842 #define GMAC_ST2CW11_OFFSSTRT_FRAMESTART (0x0u << 7)
00843 #define GMAC_ST2CW11_OFFSSTRT_ETHERTYPE (0x1u << 7)
00844 #define GMAC_ST2CW11_OFFSSTRT_IP (0x2u << 7)
00845 #define GMAC_ST2CW11_OFFSSTRT_TCP_UDP (0x3u << 7)
00846
00847 #define GMAC_ST2CW02_MASKVAL_Pos 0
00848 #define GMAC_ST2CW02_MASKVAL_Msk (0xffffu << GMAC_ST2CW02_MASKVAL_Pos)
00849 #define GMAC_ST2CW02_MASKVAL(value) ((GMAC_ST2CW02_MASKVAL_Msk & ((value) << GMAC_ST2CW02_MASKVAL_Pos)))
00850 #define GMAC_ST2CW02_COMPVAL_Pos 16
00851 #define GMAC_ST2CW02_COMPVAL_Msk (0xffffu << GMAC_ST2CW02_COMPVAL_Pos)
00852 #define GMAC_ST2CW02_COMPVAL(value) ((GMAC_ST2CW02_COMPVAL_Msk & ((value) << GMAC_ST2CW02_COMPVAL_Pos)))
00853
00854 #define GMAC_ST2CW12_OFFSVAL_Pos 0
00855 #define GMAC_ST2CW12_OFFSVAL_Msk (0x7fu << GMAC_ST2CW12_OFFSVAL_Pos)
00856 #define GMAC_ST2CW12_OFFSVAL(value) ((GMAC_ST2CW12_OFFSVAL_Msk & ((value) << GMAC_ST2CW12_OFFSVAL_Pos)))
00857 #define GMAC_ST2CW12_OFFSSTRT_Pos 7
00858 #define GMAC_ST2CW12_OFFSSTRT_Msk (0x3u << GMAC_ST2CW12_OFFSSTRT_Pos)
00859 #define GMAC_ST2CW12_OFFSSTRT(value) ((GMAC_ST2CW12_OFFSSTRT_Msk & ((value) << GMAC_ST2CW12_OFFSSTRT_Pos)))
00860 #define GMAC_ST2CW12_OFFSSTRT_FRAMESTART (0x0u << 7)
00861 #define GMAC_ST2CW12_OFFSSTRT_ETHERTYPE (0x1u << 7)
00862 #define GMAC_ST2CW12_OFFSSTRT_IP (0x2u << 7)
00863 #define GMAC_ST2CW12_OFFSSTRT_TCP_UDP (0x3u << 7)
00864
00865 #define GMAC_ST2CW03_MASKVAL_Pos 0
00866 #define GMAC_ST2CW03_MASKVAL_Msk (0xffffu << GMAC_ST2CW03_MASKVAL_Pos)
00867 #define GMAC_ST2CW03_MASKVAL(value) ((GMAC_ST2CW03_MASKVAL_Msk & ((value) << GMAC_ST2CW03_MASKVAL_Pos)))
00868 #define GMAC_ST2CW03_COMPVAL_Pos 16
00869 #define GMAC_ST2CW03_COMPVAL_Msk (0xffffu << GMAC_ST2CW03_COMPVAL_Pos)
00870 #define GMAC_ST2CW03_COMPVAL(value) ((GMAC_ST2CW03_COMPVAL_Msk & ((value) << GMAC_ST2CW03_COMPVAL_Pos)))
00871
00872 #define GMAC_ST2CW13_OFFSVAL_Pos 0
00873 #define GMAC_ST2CW13_OFFSVAL_Msk (0x7fu << GMAC_ST2CW13_OFFSVAL_Pos)
00874 #define GMAC_ST2CW13_OFFSVAL(value) ((GMAC_ST2CW13_OFFSVAL_Msk & ((value) << GMAC_ST2CW13_OFFSVAL_Pos)))
00875 #define GMAC_ST2CW13_OFFSSTRT_Pos 7
00876 #define GMAC_ST2CW13_OFFSSTRT_Msk (0x3u << GMAC_ST2CW13_OFFSSTRT_Pos)
00877 #define GMAC_ST2CW13_OFFSSTRT(value) ((GMAC_ST2CW13_OFFSSTRT_Msk & ((value) << GMAC_ST2CW13_OFFSSTRT_Pos)))
00878 #define GMAC_ST2CW13_OFFSSTRT_FRAMESTART (0x0u << 7)
00879 #define GMAC_ST2CW13_OFFSSTRT_ETHERTYPE (0x1u << 7)
00880 #define GMAC_ST2CW13_OFFSSTRT_IP (0x2u << 7)
00881 #define GMAC_ST2CW13_OFFSSTRT_TCP_UDP (0x3u << 7)
00882
00883 #define GMAC_ST2CW04_MASKVAL_Pos 0
00884 #define GMAC_ST2CW04_MASKVAL_Msk (0xffffu << GMAC_ST2CW04_MASKVAL_Pos)
00885 #define GMAC_ST2CW04_MASKVAL(value) ((GMAC_ST2CW04_MASKVAL_Msk & ((value) << GMAC_ST2CW04_MASKVAL_Pos)))
00886 #define GMAC_ST2CW04_COMPVAL_Pos 16
00887 #define GMAC_ST2CW04_COMPVAL_Msk (0xffffu << GMAC_ST2CW04_COMPVAL_Pos)
00888 #define GMAC_ST2CW04_COMPVAL(value) ((GMAC_ST2CW04_COMPVAL_Msk & ((value) << GMAC_ST2CW04_COMPVAL_Pos)))
00889
00890 #define GMAC_ST2CW14_OFFSVAL_Pos 0
00891 #define GMAC_ST2CW14_OFFSVAL_Msk (0x7fu << GMAC_ST2CW14_OFFSVAL_Pos)
00892 #define GMAC_ST2CW14_OFFSVAL(value) ((GMAC_ST2CW14_OFFSVAL_Msk & ((value) << GMAC_ST2CW14_OFFSVAL_Pos)))
00893 #define GMAC_ST2CW14_OFFSSTRT_Pos 7
00894 #define GMAC_ST2CW14_OFFSSTRT_Msk (0x3u << GMAC_ST2CW14_OFFSSTRT_Pos)
00895 #define GMAC_ST2CW14_OFFSSTRT(value) ((GMAC_ST2CW14_OFFSSTRT_Msk & ((value) << GMAC_ST2CW14_OFFSSTRT_Pos)))
00896 #define GMAC_ST2CW14_OFFSSTRT_FRAMESTART (0x0u << 7)
00897 #define GMAC_ST2CW14_OFFSSTRT_ETHERTYPE (0x1u << 7)
00898 #define GMAC_ST2CW14_OFFSSTRT_IP (0x2u << 7)
00899 #define GMAC_ST2CW14_OFFSSTRT_TCP_UDP (0x3u << 7)
00900
00901 #define GMAC_ST2CW05_MASKVAL_Pos 0
00902 #define GMAC_ST2CW05_MASKVAL_Msk (0xffffu << GMAC_ST2CW05_MASKVAL_Pos)
00903 #define GMAC_ST2CW05_MASKVAL(value) ((GMAC_ST2CW05_MASKVAL_Msk & ((value) << GMAC_ST2CW05_MASKVAL_Pos)))
00904 #define GMAC_ST2CW05_COMPVAL_Pos 16
00905 #define GMAC_ST2CW05_COMPVAL_Msk (0xffffu << GMAC_ST2CW05_COMPVAL_Pos)
00906 #define GMAC_ST2CW05_COMPVAL(value) ((GMAC_ST2CW05_COMPVAL_Msk & ((value) << GMAC_ST2CW05_COMPVAL_Pos)))
00907
00908 #define GMAC_ST2CW15_OFFSVAL_Pos 0
00909 #define GMAC_ST2CW15_OFFSVAL_Msk (0x7fu << GMAC_ST2CW15_OFFSVAL_Pos)
00910 #define GMAC_ST2CW15_OFFSVAL(value) ((GMAC_ST2CW15_OFFSVAL_Msk & ((value) << GMAC_ST2CW15_OFFSVAL_Pos)))
00911 #define GMAC_ST2CW15_OFFSSTRT_Pos 7
00912 #define GMAC_ST2CW15_OFFSSTRT_Msk (0x3u << GMAC_ST2CW15_OFFSSTRT_Pos)
00913 #define GMAC_ST2CW15_OFFSSTRT(value) ((GMAC_ST2CW15_OFFSSTRT_Msk & ((value) << GMAC_ST2CW15_OFFSSTRT_Pos)))
00914 #define GMAC_ST2CW15_OFFSSTRT_FRAMESTART (0x0u << 7)
00915 #define GMAC_ST2CW15_OFFSSTRT_ETHERTYPE (0x1u << 7)
00916 #define GMAC_ST2CW15_OFFSSTRT_IP (0x2u << 7)
00917 #define GMAC_ST2CW15_OFFSSTRT_TCP_UDP (0x3u << 7)
00918
00919 #define GMAC_ST2CW06_MASKVAL_Pos 0
00920 #define GMAC_ST2CW06_MASKVAL_Msk (0xffffu << GMAC_ST2CW06_MASKVAL_Pos)
00921 #define GMAC_ST2CW06_MASKVAL(value) ((GMAC_ST2CW06_MASKVAL_Msk & ((value) << GMAC_ST2CW06_MASKVAL_Pos)))
00922 #define GMAC_ST2CW06_COMPVAL_Pos 16
00923 #define GMAC_ST2CW06_COMPVAL_Msk (0xffffu << GMAC_ST2CW06_COMPVAL_Pos)
00924 #define GMAC_ST2CW06_COMPVAL(value) ((GMAC_ST2CW06_COMPVAL_Msk & ((value) << GMAC_ST2CW06_COMPVAL_Pos)))
00925
00926 #define GMAC_ST2CW16_OFFSVAL_Pos 0
00927 #define GMAC_ST2CW16_OFFSVAL_Msk (0x7fu << GMAC_ST2CW16_OFFSVAL_Pos)
00928 #define GMAC_ST2CW16_OFFSVAL(value) ((GMAC_ST2CW16_OFFSVAL_Msk & ((value) << GMAC_ST2CW16_OFFSVAL_Pos)))
00929 #define GMAC_ST2CW16_OFFSSTRT_Pos 7
00930 #define GMAC_ST2CW16_OFFSSTRT_Msk (0x3u << GMAC_ST2CW16_OFFSSTRT_Pos)
00931 #define GMAC_ST2CW16_OFFSSTRT(value) ((GMAC_ST2CW16_OFFSSTRT_Msk & ((value) << GMAC_ST2CW16_OFFSSTRT_Pos)))
00932 #define GMAC_ST2CW16_OFFSSTRT_FRAMESTART (0x0u << 7)
00933 #define GMAC_ST2CW16_OFFSSTRT_ETHERTYPE (0x1u << 7)
00934 #define GMAC_ST2CW16_OFFSSTRT_IP (0x2u << 7)
00935 #define GMAC_ST2CW16_OFFSSTRT_TCP_UDP (0x3u << 7)
00936
00937 #define GMAC_ST2CW07_MASKVAL_Pos 0
00938 #define GMAC_ST2CW07_MASKVAL_Msk (0xffffu << GMAC_ST2CW07_MASKVAL_Pos)
00939 #define GMAC_ST2CW07_MASKVAL(value) ((GMAC_ST2CW07_MASKVAL_Msk & ((value) << GMAC_ST2CW07_MASKVAL_Pos)))
00940 #define GMAC_ST2CW07_COMPVAL_Pos 16
00941 #define GMAC_ST2CW07_COMPVAL_Msk (0xffffu << GMAC_ST2CW07_COMPVAL_Pos)
00942 #define GMAC_ST2CW07_COMPVAL(value) ((GMAC_ST2CW07_COMPVAL_Msk & ((value) << GMAC_ST2CW07_COMPVAL_Pos)))
00943
00944 #define GMAC_ST2CW17_OFFSVAL_Pos 0
00945 #define GMAC_ST2CW17_OFFSVAL_Msk (0x7fu << GMAC_ST2CW17_OFFSVAL_Pos)
00946 #define GMAC_ST2CW17_OFFSVAL(value) ((GMAC_ST2CW17_OFFSVAL_Msk & ((value) << GMAC_ST2CW17_OFFSVAL_Pos)))
00947 #define GMAC_ST2CW17_OFFSSTRT_Pos 7
00948 #define GMAC_ST2CW17_OFFSSTRT_Msk (0x3u << GMAC_ST2CW17_OFFSSTRT_Pos)
00949 #define GMAC_ST2CW17_OFFSSTRT(value) ((GMAC_ST2CW17_OFFSSTRT_Msk & ((value) << GMAC_ST2CW17_OFFSSTRT_Pos)))
00950 #define GMAC_ST2CW17_OFFSSTRT_FRAMESTART (0x0u << 7)
00951 #define GMAC_ST2CW17_OFFSSTRT_ETHERTYPE (0x1u << 7)
00952 #define GMAC_ST2CW17_OFFSSTRT_IP (0x2u << 7)
00953 #define GMAC_ST2CW17_OFFSSTRT_TCP_UDP (0x3u << 7)
00954
00955 #define GMAC_ST2CW08_MASKVAL_Pos 0
00956 #define GMAC_ST2CW08_MASKVAL_Msk (0xffffu << GMAC_ST2CW08_MASKVAL_Pos)
00957 #define GMAC_ST2CW08_MASKVAL(value) ((GMAC_ST2CW08_MASKVAL_Msk & ((value) << GMAC_ST2CW08_MASKVAL_Pos)))
00958 #define GMAC_ST2CW08_COMPVAL_Pos 16
00959 #define GMAC_ST2CW08_COMPVAL_Msk (0xffffu << GMAC_ST2CW08_COMPVAL_Pos)
00960 #define GMAC_ST2CW08_COMPVAL(value) ((GMAC_ST2CW08_COMPVAL_Msk & ((value) << GMAC_ST2CW08_COMPVAL_Pos)))
00961
00962 #define GMAC_ST2CW18_OFFSVAL_Pos 0
00963 #define GMAC_ST2CW18_OFFSVAL_Msk (0x7fu << GMAC_ST2CW18_OFFSVAL_Pos)
00964 #define GMAC_ST2CW18_OFFSVAL(value) ((GMAC_ST2CW18_OFFSVAL_Msk & ((value) << GMAC_ST2CW18_OFFSVAL_Pos)))
00965 #define GMAC_ST2CW18_OFFSSTRT_Pos 7
00966 #define GMAC_ST2CW18_OFFSSTRT_Msk (0x3u << GMAC_ST2CW18_OFFSSTRT_Pos)
00967 #define GMAC_ST2CW18_OFFSSTRT(value) ((GMAC_ST2CW18_OFFSSTRT_Msk & ((value) << GMAC_ST2CW18_OFFSSTRT_Pos)))
00968 #define GMAC_ST2CW18_OFFSSTRT_FRAMESTART (0x0u << 7)
00969 #define GMAC_ST2CW18_OFFSSTRT_ETHERTYPE (0x1u << 7)
00970 #define GMAC_ST2CW18_OFFSSTRT_IP (0x2u << 7)
00971 #define GMAC_ST2CW18_OFFSSTRT_TCP_UDP (0x3u << 7)
00972
00973 #define GMAC_ST2CW09_MASKVAL_Pos 0
00974 #define GMAC_ST2CW09_MASKVAL_Msk (0xffffu << GMAC_ST2CW09_MASKVAL_Pos)
00975 #define GMAC_ST2CW09_MASKVAL(value) ((GMAC_ST2CW09_MASKVAL_Msk & ((value) << GMAC_ST2CW09_MASKVAL_Pos)))
00976 #define GMAC_ST2CW09_COMPVAL_Pos 16
00977 #define GMAC_ST2CW09_COMPVAL_Msk (0xffffu << GMAC_ST2CW09_COMPVAL_Pos)
00978 #define GMAC_ST2CW09_COMPVAL(value) ((GMAC_ST2CW09_COMPVAL_Msk & ((value) << GMAC_ST2CW09_COMPVAL_Pos)))
00979
00980 #define GMAC_ST2CW19_OFFSVAL_Pos 0
00981 #define GMAC_ST2CW19_OFFSVAL_Msk (0x7fu << GMAC_ST2CW19_OFFSVAL_Pos)
00982 #define GMAC_ST2CW19_OFFSVAL(value) ((GMAC_ST2CW19_OFFSVAL_Msk & ((value) << GMAC_ST2CW19_OFFSVAL_Pos)))
00983 #define GMAC_ST2CW19_OFFSSTRT_Pos 7
00984 #define GMAC_ST2CW19_OFFSSTRT_Msk (0x3u << GMAC_ST2CW19_OFFSSTRT_Pos)
00985 #define GMAC_ST2CW19_OFFSSTRT(value) ((GMAC_ST2CW19_OFFSSTRT_Msk & ((value) << GMAC_ST2CW19_OFFSSTRT_Pos)))
00986 #define GMAC_ST2CW19_OFFSSTRT_FRAMESTART (0x0u << 7)
00987 #define GMAC_ST2CW19_OFFSSTRT_ETHERTYPE (0x1u << 7)
00988 #define GMAC_ST2CW19_OFFSSTRT_IP (0x2u << 7)
00989 #define GMAC_ST2CW19_OFFSSTRT_TCP_UDP (0x3u << 7)
00990
00991 #define GMAC_ST2CW010_MASKVAL_Pos 0
00992 #define GMAC_ST2CW010_MASKVAL_Msk (0xffffu << GMAC_ST2CW010_MASKVAL_Pos)
00993 #define GMAC_ST2CW010_MASKVAL(value) ((GMAC_ST2CW010_MASKVAL_Msk & ((value) << GMAC_ST2CW010_MASKVAL_Pos)))
00994 #define GMAC_ST2CW010_COMPVAL_Pos 16
00995 #define GMAC_ST2CW010_COMPVAL_Msk (0xffffu << GMAC_ST2CW010_COMPVAL_Pos)
00996 #define GMAC_ST2CW010_COMPVAL(value) ((GMAC_ST2CW010_COMPVAL_Msk & ((value) << GMAC_ST2CW010_COMPVAL_Pos)))
00997
00998 #define GMAC_ST2CW110_OFFSVAL_Pos 0
00999 #define GMAC_ST2CW110_OFFSVAL_Msk (0x7fu << GMAC_ST2CW110_OFFSVAL_Pos)
01000 #define GMAC_ST2CW110_OFFSVAL(value) ((GMAC_ST2CW110_OFFSVAL_Msk & ((value) << GMAC_ST2CW110_OFFSVAL_Pos)))
01001 #define GMAC_ST2CW110_OFFSSTRT_Pos 7
01002 #define GMAC_ST2CW110_OFFSSTRT_Msk (0x3u << GMAC_ST2CW110_OFFSSTRT_Pos)
01003 #define GMAC_ST2CW110_OFFSSTRT(value) ((GMAC_ST2CW110_OFFSSTRT_Msk & ((value) << GMAC_ST2CW110_OFFSSTRT_Pos)))
01004 #define GMAC_ST2CW110_OFFSSTRT_FRAMESTART (0x0u << 7)
01005 #define GMAC_ST2CW110_OFFSSTRT_ETHERTYPE (0x1u << 7)
01006 #define GMAC_ST2CW110_OFFSSTRT_IP (0x2u << 7)
01007 #define GMAC_ST2CW110_OFFSSTRT_TCP_UDP (0x3u << 7)
01008
01009 #define GMAC_ST2CW011_MASKVAL_Pos 0
01010 #define GMAC_ST2CW011_MASKVAL_Msk (0xffffu << GMAC_ST2CW011_MASKVAL_Pos)
01011 #define GMAC_ST2CW011_MASKVAL(value) ((GMAC_ST2CW011_MASKVAL_Msk & ((value) << GMAC_ST2CW011_MASKVAL_Pos)))
01012 #define GMAC_ST2CW011_COMPVAL_Pos 16
01013 #define GMAC_ST2CW011_COMPVAL_Msk (0xffffu << GMAC_ST2CW011_COMPVAL_Pos)
01014 #define GMAC_ST2CW011_COMPVAL(value) ((GMAC_ST2CW011_COMPVAL_Msk & ((value) << GMAC_ST2CW011_COMPVAL_Pos)))
01015
01016 #define GMAC_ST2CW111_OFFSVAL_Pos 0
01017 #define GMAC_ST2CW111_OFFSVAL_Msk (0x7fu << GMAC_ST2CW111_OFFSVAL_Pos)
01018 #define GMAC_ST2CW111_OFFSVAL(value) ((GMAC_ST2CW111_OFFSVAL_Msk & ((value) << GMAC_ST2CW111_OFFSVAL_Pos)))
01019 #define GMAC_ST2CW111_OFFSSTRT_Pos 7
01020 #define GMAC_ST2CW111_OFFSSTRT_Msk (0x3u << GMAC_ST2CW111_OFFSSTRT_Pos)
01021 #define GMAC_ST2CW111_OFFSSTRT(value) ((GMAC_ST2CW111_OFFSSTRT_Msk & ((value) << GMAC_ST2CW111_OFFSSTRT_Pos)))
01022 #define GMAC_ST2CW111_OFFSSTRT_FRAMESTART (0x0u << 7)
01023 #define GMAC_ST2CW111_OFFSSTRT_ETHERTYPE (0x1u << 7)
01024 #define GMAC_ST2CW111_OFFSSTRT_IP (0x2u << 7)
01025 #define GMAC_ST2CW111_OFFSSTRT_TCP_UDP (0x3u << 7)
01026
01027 #define GMAC_ST2CW012_MASKVAL_Pos 0
01028 #define GMAC_ST2CW012_MASKVAL_Msk (0xffffu << GMAC_ST2CW012_MASKVAL_Pos)
01029 #define GMAC_ST2CW012_MASKVAL(value) ((GMAC_ST2CW012_MASKVAL_Msk & ((value) << GMAC_ST2CW012_MASKVAL_Pos)))
01030 #define GMAC_ST2CW012_COMPVAL_Pos 16
01031 #define GMAC_ST2CW012_COMPVAL_Msk (0xffffu << GMAC_ST2CW012_COMPVAL_Pos)
01032 #define GMAC_ST2CW012_COMPVAL(value) ((GMAC_ST2CW012_COMPVAL_Msk & ((value) << GMAC_ST2CW012_COMPVAL_Pos)))
01033
01034 #define GMAC_ST2CW112_OFFSVAL_Pos 0
01035 #define GMAC_ST2CW112_OFFSVAL_Msk (0x7fu << GMAC_ST2CW112_OFFSVAL_Pos)
01036 #define GMAC_ST2CW112_OFFSVAL(value) ((GMAC_ST2CW112_OFFSVAL_Msk & ((value) << GMAC_ST2CW112_OFFSVAL_Pos)))
01037 #define GMAC_ST2CW112_OFFSSTRT_Pos 7
01038 #define GMAC_ST2CW112_OFFSSTRT_Msk (0x3u << GMAC_ST2CW112_OFFSSTRT_Pos)
01039 #define GMAC_ST2CW112_OFFSSTRT(value) ((GMAC_ST2CW112_OFFSSTRT_Msk & ((value) << GMAC_ST2CW112_OFFSSTRT_Pos)))
01040 #define GMAC_ST2CW112_OFFSSTRT_FRAMESTART (0x0u << 7)
01041 #define GMAC_ST2CW112_OFFSSTRT_ETHERTYPE (0x1u << 7)
01042 #define GMAC_ST2CW112_OFFSSTRT_IP (0x2u << 7)
01043 #define GMAC_ST2CW112_OFFSSTRT_TCP_UDP (0x3u << 7)
01044
01045 #define GMAC_ST2CW013_MASKVAL_Pos 0
01046 #define GMAC_ST2CW013_MASKVAL_Msk (0xffffu << GMAC_ST2CW013_MASKVAL_Pos)
01047 #define GMAC_ST2CW013_MASKVAL(value) ((GMAC_ST2CW013_MASKVAL_Msk & ((value) << GMAC_ST2CW013_MASKVAL_Pos)))
01048 #define GMAC_ST2CW013_COMPVAL_Pos 16
01049 #define GMAC_ST2CW013_COMPVAL_Msk (0xffffu << GMAC_ST2CW013_COMPVAL_Pos)
01050 #define GMAC_ST2CW013_COMPVAL(value) ((GMAC_ST2CW013_COMPVAL_Msk & ((value) << GMAC_ST2CW013_COMPVAL_Pos)))
01051
01052 #define GMAC_ST2CW113_OFFSVAL_Pos 0
01053 #define GMAC_ST2CW113_OFFSVAL_Msk (0x7fu << GMAC_ST2CW113_OFFSVAL_Pos)
01054 #define GMAC_ST2CW113_OFFSVAL(value) ((GMAC_ST2CW113_OFFSVAL_Msk & ((value) << GMAC_ST2CW113_OFFSVAL_Pos)))
01055 #define GMAC_ST2CW113_OFFSSTRT_Pos 7
01056 #define GMAC_ST2CW113_OFFSSTRT_Msk (0x3u << GMAC_ST2CW113_OFFSSTRT_Pos)
01057 #define GMAC_ST2CW113_OFFSSTRT(value) ((GMAC_ST2CW113_OFFSSTRT_Msk & ((value) << GMAC_ST2CW113_OFFSSTRT_Pos)))
01058 #define GMAC_ST2CW113_OFFSSTRT_FRAMESTART (0x0u << 7)
01059 #define GMAC_ST2CW113_OFFSSTRT_ETHERTYPE (0x1u << 7)
01060 #define GMAC_ST2CW113_OFFSSTRT_IP (0x2u << 7)
01061 #define GMAC_ST2CW113_OFFSSTRT_TCP_UDP (0x3u << 7)
01062
01063 #define GMAC_ST2CW014_MASKVAL_Pos 0
01064 #define GMAC_ST2CW014_MASKVAL_Msk (0xffffu << GMAC_ST2CW014_MASKVAL_Pos)
01065 #define GMAC_ST2CW014_MASKVAL(value) ((GMAC_ST2CW014_MASKVAL_Msk & ((value) << GMAC_ST2CW014_MASKVAL_Pos)))
01066 #define GMAC_ST2CW014_COMPVAL_Pos 16
01067 #define GMAC_ST2CW014_COMPVAL_Msk (0xffffu << GMAC_ST2CW014_COMPVAL_Pos)
01068 #define GMAC_ST2CW014_COMPVAL(value) ((GMAC_ST2CW014_COMPVAL_Msk & ((value) << GMAC_ST2CW014_COMPVAL_Pos)))
01069
01070 #define GMAC_ST2CW114_OFFSVAL_Pos 0
01071 #define GMAC_ST2CW114_OFFSVAL_Msk (0x7fu << GMAC_ST2CW114_OFFSVAL_Pos)
01072 #define GMAC_ST2CW114_OFFSVAL(value) ((GMAC_ST2CW114_OFFSVAL_Msk & ((value) << GMAC_ST2CW114_OFFSVAL_Pos)))
01073 #define GMAC_ST2CW114_OFFSSTRT_Pos 7
01074 #define GMAC_ST2CW114_OFFSSTRT_Msk (0x3u << GMAC_ST2CW114_OFFSSTRT_Pos)
01075 #define GMAC_ST2CW114_OFFSSTRT(value) ((GMAC_ST2CW114_OFFSSTRT_Msk & ((value) << GMAC_ST2CW114_OFFSSTRT_Pos)))
01076 #define GMAC_ST2CW114_OFFSSTRT_FRAMESTART (0x0u << 7)
01077 #define GMAC_ST2CW114_OFFSSTRT_ETHERTYPE (0x1u << 7)
01078 #define GMAC_ST2CW114_OFFSSTRT_IP (0x2u << 7)
01079 #define GMAC_ST2CW114_OFFSSTRT_TCP_UDP (0x3u << 7)
01080
01081 #define GMAC_ST2CW015_MASKVAL_Pos 0
01082 #define GMAC_ST2CW015_MASKVAL_Msk (0xffffu << GMAC_ST2CW015_MASKVAL_Pos)
01083 #define GMAC_ST2CW015_MASKVAL(value) ((GMAC_ST2CW015_MASKVAL_Msk & ((value) << GMAC_ST2CW015_MASKVAL_Pos)))
01084 #define GMAC_ST2CW015_COMPVAL_Pos 16
01085 #define GMAC_ST2CW015_COMPVAL_Msk (0xffffu << GMAC_ST2CW015_COMPVAL_Pos)
01086 #define GMAC_ST2CW015_COMPVAL(value) ((GMAC_ST2CW015_COMPVAL_Msk & ((value) << GMAC_ST2CW015_COMPVAL_Pos)))
01087
01088 #define GMAC_ST2CW115_OFFSVAL_Pos 0
01089 #define GMAC_ST2CW115_OFFSVAL_Msk (0x7fu << GMAC_ST2CW115_OFFSVAL_Pos)
01090 #define GMAC_ST2CW115_OFFSVAL(value) ((GMAC_ST2CW115_OFFSVAL_Msk & ((value) << GMAC_ST2CW115_OFFSVAL_Pos)))
01091 #define GMAC_ST2CW115_OFFSSTRT_Pos 7
01092 #define GMAC_ST2CW115_OFFSSTRT_Msk (0x3u << GMAC_ST2CW115_OFFSSTRT_Pos)
01093 #define GMAC_ST2CW115_OFFSSTRT(value) ((GMAC_ST2CW115_OFFSSTRT_Msk & ((value) << GMAC_ST2CW115_OFFSSTRT_Pos)))
01094 #define GMAC_ST2CW115_OFFSSTRT_FRAMESTART (0x0u << 7)
01095 #define GMAC_ST2CW115_OFFSSTRT_ETHERTYPE (0x1u << 7)
01096 #define GMAC_ST2CW115_OFFSSTRT_IP (0x2u << 7)
01097 #define GMAC_ST2CW115_OFFSSTRT_TCP_UDP (0x3u << 7)
01098
01099 #define GMAC_ST2CW016_MASKVAL_Pos 0
01100 #define GMAC_ST2CW016_MASKVAL_Msk (0xffffu << GMAC_ST2CW016_MASKVAL_Pos)
01101 #define GMAC_ST2CW016_MASKVAL(value) ((GMAC_ST2CW016_MASKVAL_Msk & ((value) << GMAC_ST2CW016_MASKVAL_Pos)))
01102 #define GMAC_ST2CW016_COMPVAL_Pos 16
01103 #define GMAC_ST2CW016_COMPVAL_Msk (0xffffu << GMAC_ST2CW016_COMPVAL_Pos)
01104 #define GMAC_ST2CW016_COMPVAL(value) ((GMAC_ST2CW016_COMPVAL_Msk & ((value) << GMAC_ST2CW016_COMPVAL_Pos)))
01105
01106 #define GMAC_ST2CW116_OFFSVAL_Pos 0
01107 #define GMAC_ST2CW116_OFFSVAL_Msk (0x7fu << GMAC_ST2CW116_OFFSVAL_Pos)
01108 #define GMAC_ST2CW116_OFFSVAL(value) ((GMAC_ST2CW116_OFFSVAL_Msk & ((value) << GMAC_ST2CW116_OFFSVAL_Pos)))
01109 #define GMAC_ST2CW116_OFFSSTRT_Pos 7
01110 #define GMAC_ST2CW116_OFFSSTRT_Msk (0x3u << GMAC_ST2CW116_OFFSSTRT_Pos)
01111 #define GMAC_ST2CW116_OFFSSTRT(value) ((GMAC_ST2CW116_OFFSSTRT_Msk & ((value) << GMAC_ST2CW116_OFFSSTRT_Pos)))
01112 #define GMAC_ST2CW116_OFFSSTRT_FRAMESTART (0x0u << 7)
01113 #define GMAC_ST2CW116_OFFSSTRT_ETHERTYPE (0x1u << 7)
01114 #define GMAC_ST2CW116_OFFSSTRT_IP (0x2u << 7)
01115 #define GMAC_ST2CW116_OFFSSTRT_TCP_UDP (0x3u << 7)
01116
01117 #define GMAC_ST2CW017_MASKVAL_Pos 0
01118 #define GMAC_ST2CW017_MASKVAL_Msk (0xffffu << GMAC_ST2CW017_MASKVAL_Pos)
01119 #define GMAC_ST2CW017_MASKVAL(value) ((GMAC_ST2CW017_MASKVAL_Msk & ((value) << GMAC_ST2CW017_MASKVAL_Pos)))
01120 #define GMAC_ST2CW017_COMPVAL_Pos 16
01121 #define GMAC_ST2CW017_COMPVAL_Msk (0xffffu << GMAC_ST2CW017_COMPVAL_Pos)
01122 #define GMAC_ST2CW017_COMPVAL(value) ((GMAC_ST2CW017_COMPVAL_Msk & ((value) << GMAC_ST2CW017_COMPVAL_Pos)))
01123
01124 #define GMAC_ST2CW117_OFFSVAL_Pos 0
01125 #define GMAC_ST2CW117_OFFSVAL_Msk (0x7fu << GMAC_ST2CW117_OFFSVAL_Pos)
01126 #define GMAC_ST2CW117_OFFSVAL(value) ((GMAC_ST2CW117_OFFSVAL_Msk & ((value) << GMAC_ST2CW117_OFFSVAL_Pos)))
01127 #define GMAC_ST2CW117_OFFSSTRT_Pos 7
01128 #define GMAC_ST2CW117_OFFSSTRT_Msk (0x3u << GMAC_ST2CW117_OFFSSTRT_Pos)
01129 #define GMAC_ST2CW117_OFFSSTRT(value) ((GMAC_ST2CW117_OFFSSTRT_Msk & ((value) << GMAC_ST2CW117_OFFSSTRT_Pos)))
01130 #define GMAC_ST2CW117_OFFSSTRT_FRAMESTART (0x0u << 7)
01131 #define GMAC_ST2CW117_OFFSSTRT_ETHERTYPE (0x1u << 7)
01132 #define GMAC_ST2CW117_OFFSSTRT_IP (0x2u << 7)
01133 #define GMAC_ST2CW117_OFFSSTRT_TCP_UDP (0x3u << 7)
01134
01135 #define GMAC_ST2CW018_MASKVAL_Pos 0
01136 #define GMAC_ST2CW018_MASKVAL_Msk (0xffffu << GMAC_ST2CW018_MASKVAL_Pos)
01137 #define GMAC_ST2CW018_MASKVAL(value) ((GMAC_ST2CW018_MASKVAL_Msk & ((value) << GMAC_ST2CW018_MASKVAL_Pos)))
01138 #define GMAC_ST2CW018_COMPVAL_Pos 16
01139 #define GMAC_ST2CW018_COMPVAL_Msk (0xffffu << GMAC_ST2CW018_COMPVAL_Pos)
01140 #define GMAC_ST2CW018_COMPVAL(value) ((GMAC_ST2CW018_COMPVAL_Msk & ((value) << GMAC_ST2CW018_COMPVAL_Pos)))
01141
01142 #define GMAC_ST2CW118_OFFSVAL_Pos 0
01143 #define GMAC_ST2CW118_OFFSVAL_Msk (0x7fu << GMAC_ST2CW118_OFFSVAL_Pos)
01144 #define GMAC_ST2CW118_OFFSVAL(value) ((GMAC_ST2CW118_OFFSVAL_Msk & ((value) << GMAC_ST2CW118_OFFSVAL_Pos)))
01145 #define GMAC_ST2CW118_OFFSSTRT_Pos 7
01146 #define GMAC_ST2CW118_OFFSSTRT_Msk (0x3u << GMAC_ST2CW118_OFFSSTRT_Pos)
01147 #define GMAC_ST2CW118_OFFSSTRT(value) ((GMAC_ST2CW118_OFFSSTRT_Msk & ((value) << GMAC_ST2CW118_OFFSSTRT_Pos)))
01148 #define GMAC_ST2CW118_OFFSSTRT_FRAMESTART (0x0u << 7)
01149 #define GMAC_ST2CW118_OFFSSTRT_ETHERTYPE (0x1u << 7)
01150 #define GMAC_ST2CW118_OFFSSTRT_IP (0x2u << 7)
01151 #define GMAC_ST2CW118_OFFSSTRT_TCP_UDP (0x3u << 7)
01152
01153 #define GMAC_ST2CW019_MASKVAL_Pos 0
01154 #define GMAC_ST2CW019_MASKVAL_Msk (0xffffu << GMAC_ST2CW019_MASKVAL_Pos)
01155 #define GMAC_ST2CW019_MASKVAL(value) ((GMAC_ST2CW019_MASKVAL_Msk & ((value) << GMAC_ST2CW019_MASKVAL_Pos)))
01156 #define GMAC_ST2CW019_COMPVAL_Pos 16
01157 #define GMAC_ST2CW019_COMPVAL_Msk (0xffffu << GMAC_ST2CW019_COMPVAL_Pos)
01158 #define GMAC_ST2CW019_COMPVAL(value) ((GMAC_ST2CW019_COMPVAL_Msk & ((value) << GMAC_ST2CW019_COMPVAL_Pos)))
01159
01160 #define GMAC_ST2CW119_OFFSVAL_Pos 0
01161 #define GMAC_ST2CW119_OFFSVAL_Msk (0x7fu << GMAC_ST2CW119_OFFSVAL_Pos)
01162 #define GMAC_ST2CW119_OFFSVAL(value) ((GMAC_ST2CW119_OFFSVAL_Msk & ((value) << GMAC_ST2CW119_OFFSVAL_Pos)))
01163 #define GMAC_ST2CW119_OFFSSTRT_Pos 7
01164 #define GMAC_ST2CW119_OFFSSTRT_Msk (0x3u << GMAC_ST2CW119_OFFSSTRT_Pos)
01165 #define GMAC_ST2CW119_OFFSSTRT(value) ((GMAC_ST2CW119_OFFSSTRT_Msk & ((value) << GMAC_ST2CW119_OFFSSTRT_Pos)))
01166 #define GMAC_ST2CW119_OFFSSTRT_FRAMESTART (0x0u << 7)
01167 #define GMAC_ST2CW119_OFFSSTRT_ETHERTYPE (0x1u << 7)
01168 #define GMAC_ST2CW119_OFFSSTRT_IP (0x2u << 7)
01169 #define GMAC_ST2CW119_OFFSSTRT_TCP_UDP (0x3u << 7)
01170
01171 #define GMAC_ST2CW020_MASKVAL_Pos 0
01172 #define GMAC_ST2CW020_MASKVAL_Msk (0xffffu << GMAC_ST2CW020_MASKVAL_Pos)
01173 #define GMAC_ST2CW020_MASKVAL(value) ((GMAC_ST2CW020_MASKVAL_Msk & ((value) << GMAC_ST2CW020_MASKVAL_Pos)))
01174 #define GMAC_ST2CW020_COMPVAL_Pos 16
01175 #define GMAC_ST2CW020_COMPVAL_Msk (0xffffu << GMAC_ST2CW020_COMPVAL_Pos)
01176 #define GMAC_ST2CW020_COMPVAL(value) ((GMAC_ST2CW020_COMPVAL_Msk & ((value) << GMAC_ST2CW020_COMPVAL_Pos)))
01177
01178 #define GMAC_ST2CW120_OFFSVAL_Pos 0
01179 #define GMAC_ST2CW120_OFFSVAL_Msk (0x7fu << GMAC_ST2CW120_OFFSVAL_Pos)
01180 #define GMAC_ST2CW120_OFFSVAL(value) ((GMAC_ST2CW120_OFFSVAL_Msk & ((value) << GMAC_ST2CW120_OFFSVAL_Pos)))
01181 #define GMAC_ST2CW120_OFFSSTRT_Pos 7
01182 #define GMAC_ST2CW120_OFFSSTRT_Msk (0x3u << GMAC_ST2CW120_OFFSSTRT_Pos)
01183 #define GMAC_ST2CW120_OFFSSTRT(value) ((GMAC_ST2CW120_OFFSSTRT_Msk & ((value) << GMAC_ST2CW120_OFFSSTRT_Pos)))
01184 #define GMAC_ST2CW120_OFFSSTRT_FRAMESTART (0x0u << 7)
01185 #define GMAC_ST2CW120_OFFSSTRT_ETHERTYPE (0x1u << 7)
01186 #define GMAC_ST2CW120_OFFSSTRT_IP (0x2u << 7)
01187 #define GMAC_ST2CW120_OFFSSTRT_TCP_UDP (0x3u << 7)
01188
01189 #define GMAC_ST2CW021_MASKVAL_Pos 0
01190 #define GMAC_ST2CW021_MASKVAL_Msk (0xffffu << GMAC_ST2CW021_MASKVAL_Pos)
01191 #define GMAC_ST2CW021_MASKVAL(value) ((GMAC_ST2CW021_MASKVAL_Msk & ((value) << GMAC_ST2CW021_MASKVAL_Pos)))
01192 #define GMAC_ST2CW021_COMPVAL_Pos 16
01193 #define GMAC_ST2CW021_COMPVAL_Msk (0xffffu << GMAC_ST2CW021_COMPVAL_Pos)
01194 #define GMAC_ST2CW021_COMPVAL(value) ((GMAC_ST2CW021_COMPVAL_Msk & ((value) << GMAC_ST2CW021_COMPVAL_Pos)))
01195
01196 #define GMAC_ST2CW121_OFFSVAL_Pos 0
01197 #define GMAC_ST2CW121_OFFSVAL_Msk (0x7fu << GMAC_ST2CW121_OFFSVAL_Pos)
01198 #define GMAC_ST2CW121_OFFSVAL(value) ((GMAC_ST2CW121_OFFSVAL_Msk & ((value) << GMAC_ST2CW121_OFFSVAL_Pos)))
01199 #define GMAC_ST2CW121_OFFSSTRT_Pos 7
01200 #define GMAC_ST2CW121_OFFSSTRT_Msk (0x3u << GMAC_ST2CW121_OFFSSTRT_Pos)
01201 #define GMAC_ST2CW121_OFFSSTRT(value) ((GMAC_ST2CW121_OFFSSTRT_Msk & ((value) << GMAC_ST2CW121_OFFSSTRT_Pos)))
01202 #define GMAC_ST2CW121_OFFSSTRT_FRAMESTART (0x0u << 7)
01203 #define GMAC_ST2CW121_OFFSSTRT_ETHERTYPE (0x1u << 7)
01204 #define GMAC_ST2CW121_OFFSSTRT_IP (0x2u << 7)
01205 #define GMAC_ST2CW121_OFFSSTRT_TCP_UDP (0x3u << 7)
01206
01207 #define GMAC_ST2CW022_MASKVAL_Pos 0
01208 #define GMAC_ST2CW022_MASKVAL_Msk (0xffffu << GMAC_ST2CW022_MASKVAL_Pos)
01209 #define GMAC_ST2CW022_MASKVAL(value) ((GMAC_ST2CW022_MASKVAL_Msk & ((value) << GMAC_ST2CW022_MASKVAL_Pos)))
01210 #define GMAC_ST2CW022_COMPVAL_Pos 16
01211 #define GMAC_ST2CW022_COMPVAL_Msk (0xffffu << GMAC_ST2CW022_COMPVAL_Pos)
01212 #define GMAC_ST2CW022_COMPVAL(value) ((GMAC_ST2CW022_COMPVAL_Msk & ((value) << GMAC_ST2CW022_COMPVAL_Pos)))
01213
01214 #define GMAC_ST2CW122_OFFSVAL_Pos 0
01215 #define GMAC_ST2CW122_OFFSVAL_Msk (0x7fu << GMAC_ST2CW122_OFFSVAL_Pos)
01216 #define GMAC_ST2CW122_OFFSVAL(value) ((GMAC_ST2CW122_OFFSVAL_Msk & ((value) << GMAC_ST2CW122_OFFSVAL_Pos)))
01217 #define GMAC_ST2CW122_OFFSSTRT_Pos 7
01218 #define GMAC_ST2CW122_OFFSSTRT_Msk (0x3u << GMAC_ST2CW122_OFFSSTRT_Pos)
01219 #define GMAC_ST2CW122_OFFSSTRT(value) ((GMAC_ST2CW122_OFFSSTRT_Msk & ((value) << GMAC_ST2CW122_OFFSSTRT_Pos)))
01220 #define GMAC_ST2CW122_OFFSSTRT_FRAMESTART (0x0u << 7)
01221 #define GMAC_ST2CW122_OFFSSTRT_ETHERTYPE (0x1u << 7)
01222 #define GMAC_ST2CW122_OFFSSTRT_IP (0x2u << 7)
01223 #define GMAC_ST2CW122_OFFSSTRT_TCP_UDP (0x3u << 7)
01224
01225 #define GMAC_ST2CW023_MASKVAL_Pos 0
01226 #define GMAC_ST2CW023_MASKVAL_Msk (0xffffu << GMAC_ST2CW023_MASKVAL_Pos)
01227 #define GMAC_ST2CW023_MASKVAL(value) ((GMAC_ST2CW023_MASKVAL_Msk & ((value) << GMAC_ST2CW023_MASKVAL_Pos)))
01228 #define GMAC_ST2CW023_COMPVAL_Pos 16
01229 #define GMAC_ST2CW023_COMPVAL_Msk (0xffffu << GMAC_ST2CW023_COMPVAL_Pos)
01230 #define GMAC_ST2CW023_COMPVAL(value) ((GMAC_ST2CW023_COMPVAL_Msk & ((value) << GMAC_ST2CW023_COMPVAL_Pos)))
01231
01232 #define GMAC_ST2CW123_OFFSVAL_Pos 0
01233 #define GMAC_ST2CW123_OFFSVAL_Msk (0x7fu << GMAC_ST2CW123_OFFSVAL_Pos)
01234 #define GMAC_ST2CW123_OFFSVAL(value) ((GMAC_ST2CW123_OFFSVAL_Msk & ((value) << GMAC_ST2CW123_OFFSVAL_Pos)))
01235 #define GMAC_ST2CW123_OFFSSTRT_Pos 7
01236 #define GMAC_ST2CW123_OFFSSTRT_Msk (0x3u << GMAC_ST2CW123_OFFSSTRT_Pos)
01237 #define GMAC_ST2CW123_OFFSSTRT(value) ((GMAC_ST2CW123_OFFSSTRT_Msk & ((value) << GMAC_ST2CW123_OFFSSTRT_Pos)))
01238 #define GMAC_ST2CW123_OFFSSTRT_FRAMESTART (0x0u << 7)
01239 #define GMAC_ST2CW123_OFFSSTRT_ETHERTYPE (0x1u << 7)
01240 #define GMAC_ST2CW123_OFFSSTRT_IP (0x2u << 7)
01241 #define GMAC_ST2CW123_OFFSSTRT_TCP_UDP (0x3u << 7)
01242
01243
01244
01245
01246 #endif