SAMV71 Xplained Ultra Software Package 1.5

instance_twihs1.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_TWIHS1_INSTANCE_
00031 #define _SAMV71_TWIHS1_INSTANCE_
00032 
00033 /* ========== Register definition for TWIHS1 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_TWIHS1_CR                     (0x4001C000U) /**< \brief (TWIHS1) Control Register */
00036   #define REG_TWIHS1_MMR                    (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
00037   #define REG_TWIHS1_SMR                    (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
00038   #define REG_TWIHS1_IADR                   (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
00039   #define REG_TWIHS1_CWGR                   (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
00040   #define REG_TWIHS1_SR                     (0x4001C020U) /**< \brief (TWIHS1) Status Register */
00041   #define REG_TWIHS1_IER                    (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
00042   #define REG_TWIHS1_IDR                    (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
00043   #define REG_TWIHS1_IMR                    (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
00044   #define REG_TWIHS1_RHR                    (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
00045   #define REG_TWIHS1_THR                    (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
00046   #define REG_TWIHS1_SMBTR                  (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
00047   #define REG_TWIHS1_FILTR                  (0x4001C044U) /**< \brief (TWIHS1) Filter Register */
00048   #define REG_TWIHS1_SWMR                   (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
00049   #define REG_TWIHS1_DR                     (0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */
00050   #define REG_TWIHS1_WPMR                   (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
00051   #define REG_TWIHS1_WPSR                   (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
00052   #define REG_TWIHS1_VER                    (0x4001C0FCU) /**< \brief (TWIHS1) Version Register */
00053 #else
00054   #define REG_TWIHS1_CR    (*(__O  uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */
00055   #define REG_TWIHS1_MMR   (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */
00056   #define REG_TWIHS1_SMR   (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */
00057   #define REG_TWIHS1_IADR  (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */
00058   #define REG_TWIHS1_CWGR  (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */
00059   #define REG_TWIHS1_SR    (*(__I  uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */
00060   #define REG_TWIHS1_IER   (*(__O  uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */
00061   #define REG_TWIHS1_IDR   (*(__O  uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */
00062   #define REG_TWIHS1_IMR   (*(__I  uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */
00063   #define REG_TWIHS1_RHR   (*(__I  uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */
00064   #define REG_TWIHS1_THR   (*(__O  uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */
00065   #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */
00066   #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */
00067   #define REG_TWIHS1_SWMR  (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */
00068   #define REG_TWIHS1_DR    (*(__I  uint32_t*)0x4001C0D0U) /**< \brief (TWIHS1) Debug Register */
00069   #define REG_TWIHS1_WPMR  (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */
00070   #define REG_TWIHS1_WPSR  (*(__I  uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */
00071   #define REG_TWIHS1_VER   (*(__I  uint32_t*)0x4001C0FCU) /**< \brief (TWIHS1) Version Register */
00072 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00073 
00074 #endif /* _SAMV71_TWIHS1_INSTANCE_ */
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