00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_AFEC1_INSTANCE_ 00031 #define _SAMV71_AFEC1_INSTANCE_ 00032 00033 /* ========== Register definition for AFEC1 peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ 00036 #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ 00037 #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ 00038 #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ 00039 #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ 00040 #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ 00041 #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ 00042 #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ 00043 #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ 00044 #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ 00045 #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ 00046 #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ 00047 #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ 00048 #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ 00049 #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ 00050 #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ 00051 #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ 00052 #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ 00053 #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ 00054 #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ 00055 #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ 00056 #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ 00057 #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ 00058 #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ 00059 #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ 00060 #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ 00061 #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ 00062 #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ 00063 #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ 00064 #define REG_AFEC1_VERSION (0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */ 00065 #else 00066 #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ 00067 #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ 00068 #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ 00069 #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ 00070 #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ 00071 #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ 00072 #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ 00073 #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ 00074 #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ 00075 #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ 00076 #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ 00077 #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ 00078 #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ 00079 #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ 00080 #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ 00081 #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ 00082 #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ 00083 #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ 00084 #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ 00085 #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ 00086 #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ 00087 #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ 00088 #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ 00089 #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ 00090 #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ 00091 #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ 00092 #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ 00093 #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ 00094 #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ 00095 #define REG_AFEC1_VERSION (*(__I uint32_t*)0x400640FCU) /**< \brief (AFEC1) AFEC Version Register */ 00096 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00097 00098 #endif /* _SAMV71_AFEC1_INSTANCE_ */