00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_USBHS_INSTANCE_ 00031 #define _SAMV71_USBHS_INSTANCE_ 00032 00033 /* ========== Register definition for USBHS peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */ 00036 #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ 00037 #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ 00038 #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ 00039 #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ 00040 #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ 00041 #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ 00042 #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ 00043 #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ 00044 #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ 00045 #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ 00046 #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ 00047 #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ 00048 #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ 00049 #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ 00050 #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ 00051 #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ 00052 #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ 00053 #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ 00054 #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ 00055 #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ 00056 #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ 00057 #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ 00058 #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ 00059 #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ 00060 #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ 00061 #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ 00062 #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ 00063 #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ 00064 #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ 00065 #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ 00066 #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ 00067 #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ 00068 #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ 00069 #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ 00070 #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ 00071 #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ 00072 #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ 00073 #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ 00074 #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ 00075 #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ 00076 #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ 00077 #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ 00078 #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ 00079 #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */ 00080 #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ 00081 #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ 00082 #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ 00083 #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ 00084 #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ 00085 #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ 00086 #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ 00087 #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ 00088 #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ 00089 #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ 00090 #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ 00091 #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ 00092 #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ 00093 #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ 00094 #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ 00095 #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ 00096 #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ 00097 #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ 00098 #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ 00099 #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ 00100 #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ 00101 #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ 00102 #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ 00103 #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ 00104 #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ 00105 #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ 00106 #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ 00107 #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ 00108 #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ 00109 #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ 00110 #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ 00111 #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ 00112 #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ 00113 #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ 00114 #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ 00115 #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ 00116 #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ 00117 #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ 00118 #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ 00119 #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ 00120 #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ 00121 #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ 00122 #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ 00123 #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ 00124 #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ 00125 #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ 00126 #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ 00127 #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ 00128 #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */ 00129 #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */ 00130 #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */ 00131 #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */ 00132 #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */ 00133 #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */ 00134 #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */ 00135 #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ 00136 #else 00137 #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */ 00138 #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ 00139 #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ 00140 #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ 00141 #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ 00142 #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ 00143 #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ 00144 #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ 00145 #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ 00146 #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ 00147 #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ 00148 #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ 00149 #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ 00150 #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ 00151 #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ 00152 #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ 00153 #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ 00154 #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ 00155 #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ 00156 #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ 00157 #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ 00158 #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ 00159 #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ 00160 #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ 00161 #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ 00162 #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ 00163 #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ 00164 #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ 00165 #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ 00166 #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ 00167 #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ 00168 #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ 00169 #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ 00170 #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ 00171 #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ 00172 #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ 00173 #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ 00174 #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ 00175 #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ 00176 #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ 00177 #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ 00178 #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ 00179 #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ 00180 #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ 00181 #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */ 00182 #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ 00183 #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ 00184 #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ 00185 #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ 00186 #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ 00187 #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ 00188 #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ 00189 #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ 00190 #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ 00191 #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ 00192 #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ 00193 #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ 00194 #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ 00195 #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ 00196 #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ 00197 #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ 00198 #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ 00199 #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ 00200 #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ 00201 #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ 00202 #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ 00203 #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ 00204 #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ 00205 #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ 00206 #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ 00207 #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ 00208 #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ 00209 #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ 00210 #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ 00211 #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ 00212 #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ 00213 #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ 00214 #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ 00215 #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ 00216 #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ 00217 #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ 00218 #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ 00219 #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ 00220 #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ 00221 #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ 00222 #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ 00223 #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ 00224 #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ 00225 #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ 00226 #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ 00227 #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ 00228 #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ 00229 #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ 00230 #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */ 00231 #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */ 00232 #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */ 00233 #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */ 00234 #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */ 00235 #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */ 00236 #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */ 00237 #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ 00238 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00239 00240 #endif /* _SAMV71_USBHS_INSTANCE_ */