Go to the documentation of this file.00001
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00044 #include "chip.h"
00045
00046
00047
00048
00049
00050
00051
00052
00053 void NMI_Handler(void)
00054 {
00055 printf("\r\n-E- Enter NMI_Handler!");
00056
00057 while (1);
00058 }
00059
00060
00061
00062
00063
00064 __STATIC_INLINE uint32_t StackUnwind(void)
00065 {
00066 uint32_t Fault_Add;
00067
00068 #if defined (__CC_ARM)
00069 uint32_t temp;
00070 __ASM("mrs temp, msp ");
00071 __ASM{ ldr Fault_Add, [temp, #28]}
00072 #else
00073 __ASM("mrs r0, msp ");
00074 __ASM("ldr %0, [r0,#28]" : "=r" (Fault_Add));
00075 #endif
00076 return Fault_Add;
00077 }
00078
00079
00080
00081
00082
00083 static void HardFault_reason(void)
00084 {
00085 uint32_t CFSRValue;
00086 TRACE_DEBUG("In Hard Fault Handler\n\r");
00087 TRACE_DEBUG("SCB->HFSR = 0x%08x\n\r", SCB->HFSR);
00088
00089 if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk)) {
00090 TRACE_DEBUG("Debug Event Hard Fault\n\r");
00091 TRACE_DEBUG("SCB->DFSR = 0x%08x\n", SCB->DFSR);
00092 }
00093
00094 if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk)) {
00095 TRACE_DEBUG("Fault was due to vector table read on \
00096 exception processing\n\r");
00097 }
00098
00099
00100 if ((SCB->HFSR & SCB_HFSR_FORCED_Msk)) {
00101 TRACE_DEBUG("Forced Hard Fault\n\r");
00102 TRACE_DEBUG("SCB->CFSR = 0x%08x\n\r", SCB->CFSR);
00103
00104
00105 if ((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk)) {
00106 CFSRValue = SCB->CFSR;
00107 TRACE_DEBUG("Usage fault: ");
00108 CFSRValue >>= SCB_CFSR_USGFAULTSR_Pos;
00109
00110 if ((CFSRValue & (1 << 9)))
00111 TRACE_DEBUG("Divide by zero\n\r");
00112
00113 if ((CFSRValue & (1 << 8)))
00114 TRACE_DEBUG("Unaligned access error\n\r");
00115
00116 if ((CFSRValue & (1 << 3)))
00117 TRACE_DEBUG("Coprocessor access error\n\r");
00118
00119 if ((CFSRValue & (1 << 2)))
00120 TRACE_DEBUG("Integrity check error on EXC_RETURN\n\r");
00121 }
00122
00123
00124 if ((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk)) {
00125 CFSRValue = SCB->CFSR;
00126 TRACE_DEBUG("Bus fault: ");
00127 CFSRValue >>= SCB_CFSR_BUSFAULTSR_Pos;
00128
00129 if ((CFSRValue & (1 << 7)) && (CFSRValue & (1 << 1))) {
00130 TRACE_DEBUG("Precise data access error. Bus Fault Address \
00131 Register is: %x \n\r", SCB->BFAR);
00132 }
00133
00134 if ((CFSRValue & (1 << 4)))
00135 TRACE_DEBUG("Bus fault has occurred on exception entry\n\r");
00136
00137 if ((CFSRValue & (1 << 3)))
00138 TRACE_DEBUG("bus fault has occurred on exception return\n\r");
00139
00140 if ((CFSRValue & (1 << 2)))
00141 TRACE_DEBUG("Imprecise data access error\n\r");
00142
00143 if ((CFSRValue & (1 << 0))) {
00144 TRACE_DEBUG("This bit indicates a bus fault on an instruction \
00145 pre-fetch. \n\r");
00146 }
00147 }
00148 }
00149
00150
00151 if ((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk)) {
00152 CFSRValue = SCB->CFSR;
00153 TRACE_DEBUG("Memory fault: ");
00154 CFSRValue >>= SCB_CFSR_MEMFAULTSR_Pos;
00155
00156 if ((CFSRValue & (1 << 9)) != 0)
00157 TRACE_DEBUG("Divide by zero\n\r");
00158 }
00159
00160 __ISB();
00161 __DMB();
00162 __ASM volatile("BKPT #01");
00163 }
00164
00165
00166
00167
00168 void HardFault_Handler(void)
00169 {
00170 printf("\n\rHardFault at address 0X%x\n\r", (int)StackUnwind());
00171 __ISB();
00172 __DMB();
00173 HardFault_reason();
00174 }
00175
00176 #ifndef MPU_EXAMPLE_FEATURE
00177
00178
00179
00180 void MemManage_Handler(void)
00181 {
00182 printf("\n\rMemoryMemFault (MPU fault) at address 0X%x\n\r",
00183 (int)StackUnwind());
00184 __ISB();
00185 __DMB();
00186 __ASM volatile("BKPT #01");
00187 }
00188 #endif
00189
00190
00191
00192
00193 void BusFault_Handler(void)
00194 {
00195 __ASM("nop");
00196 __ASM("nop");
00197 printf("\n\rBus Fault at address 0X%x\n\r", (int)StackUnwind());
00198
00199 __ISB();
00200 __DMB();
00201 __ASM volatile("BKPT #01");
00202 }
00203
00204
00205
00206
00207 void UsageFault_Handler(void)
00208 {
00209 printf("\r\nUsage fault at address 0X%x", (int)StackUnwind());
00210
00211 __ISB();
00212 __DMB();
00213 __ASM volatile("BKPT #01");
00214 }