SAMV71 Xplained Ultra Software Package 1.5

main.c

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00029 
00030 /**
00031  *  \page aes Advanced Encryption Standard Example
00032  *
00033  *  \section Purpose
00034  *  This application demonstrates the Advanced Encryption Standard (AES)
00035  *  peripheral integrated in some of SAMV7 micro-controllers family. It encrypts
00036  *  and decrypts several test values in Electronic CodeBook (ECB) and Cipher Block
00037  *  Chaining (CBC),OBC,OFB,TRC modes and checks them against the known answers.
00038  *
00039  * \section Requirements
00040  *
00041  *  This package can be used with SAMV71 Xplained Ultra board or SAME70 Xplained board.
00042  *
00043  *  \section Description
00044  * This example shows how to configure AES in encryption and decryption mode.
00045  * In encryption mode, it encrypts plain text with one of ECB, CBC, OFB ,CFB and
00046  * CTR mode. Programmable key mode with processing using with or without DMA
00047  * support.
00048  * In decryption mode, it decrypts cipher data generate from encryption mode and
00049  * get the known plain value.
00050  *
00051  *  \section Usage
00052  *
00053  *  -# Build the program and download it inside the board.
00054  *     Please refer to the Getting Started with SAM V71/E70 Microcontrollers.pdf
00055  *  -# On the computer, open and configure a terminal application
00056  *     (e.g. HyperTerminal on Microsoft Windows) with these settings:
00057  *    - 115200 baud rate
00058  *    - 8 bits of data
00059  *    - No parity
00060  *    - 1 stop bit
00061  *    - No flow control
00062  *  -# In the terminal window, the
00063  *     following text should appear (values depend on the board and chip used):
00064  *     \code
00065  *      -- AES Example xxx --
00066  *      -- SAMxxxxx-xx
00067  *      -- Compiled: xxx xx xxxx xx:xx:xx --
00068  *      -- Menu Choices for this example--
00069  *      \endcode
00070  *  -# Input command according to the menu.
00071  *
00072  *  \section References
00073  *  - aes/main.c
00074  *  - aes.c
00075  *  - aes.h */
00076 
00077 /** \file
00078  *
00079  *  This file contains all the specific code for the AES
00080  */
00081 
00082 /*----------------------------------------------------------------------------
00083  *        Headers
00084  *----------------------------------------------------------------------------*/
00085 #include <board.h>
00086 #include <string.h>
00087 /*----------------------------------------------------------------------------
00088  *        Local definitions
00089  *----------------------------------------------------------------------------*/
00090 #define DATA_LEN_INBYTE   640
00091 #define DATA_LEN_INWORD (DATA_LEN_INBYTE/4)
00092 #define DATA_LEN_INDWORD (DATA_LEN_INBYTE/8)
00093 
00094 #define AES_VECTOR_0     0x11223344
00095 #define AES_VECTOR_1     0x55667788
00096 #define AES_VECTOR_2     0x11112222
00097 #define AES_VECTOR_3     0x33334444
00098 
00099 #define AES_KEY_0       0x01234567
00100 #define AES_KEY_1       0x89ABCDEF
00101 #define AES_KEY_2       0x76543210
00102 #define AES_KEY_3       0xFEDCBA98
00103 #define AES_KEY_4       0x55AA55AA
00104 #define AES_KEY_5       0xAA55AA55
00105 #define AES_KEY_6       0x0000FFFF
00106 #define AES_KEY_7       0xFFFF0000
00107 
00108 /*----------------------------------------------------------------------------
00109  *        Local variables
00110  *----------------------------------------------------------------------------*/
00111 const uint32_t aes_keys[8] = {AES_KEY_0, AES_KEY_1, AES_KEY_2, AES_KEY_3,
00112                                 AES_KEY_4, AES_KEY_5, AES_KEY_6, AES_KEY_7
00113                                 };
00114 const uint32_t aes_vectors[4] = { AES_VECTOR_0,
00115                                 AES_VECTOR_1,
00116                                 AES_VECTOR_2,
00117                                 AES_VECTOR_3
00118                                 };
00119 
00120 COMPILER_ALIGNED(32) static uint32_t bufPlaint[DATA_LEN_INWORD];
00121 COMPILER_ALIGNED(32) static uint32_t bufCipher[DATA_LEN_INWORD];
00122 COMPILER_ALIGNED(32) static uint32_t bufOut[DATA_LEN_INWORD];
00123 
00124 const char plaintext[DATA_LEN_INBYTE] = "\
00125   The Advanced Encryption Standard (AES) is compliant with the A\
00126 merican FIPS (Federal Information Processing Standard) Publicati\
00127 on 197 specification. AES supports all five confidentiality mode\
00128 s of operation for symmetrical key block cipher algorithms (ECB,\
00129 CBC,OFB, CFB and CTR), as specified in the NIST Special Publicat\
00130 ion 80038A. It is compatible with all these modes via Peripheral\
00131  DMA Controller channels, minimizing processor intervention for \
00132 large buffer transfers.The 128-bit/192-bit/256-bit key is stored\
00133 in four/six/eight 32-bit registers (AES_KEYWRx) which are all wr\
00134 ite-only .......................................................";
00135 
00136 static uint32_t operationMode, startMode, keyMode, keylength;
00137 static uint32_t desDone;
00138 /** Global DMA driver instance for all DMA transfers in application. */
00139 static sXdmad xdmad;
00140 static sXdmadCfg xdmadCfg;
00141 static uint32_t dmaWriteChannel, dmaReadChannel;
00142 COMPILER_ALIGNED(32) static LinkedListDescriporView1
00143 dmaWriteLinkList[DATA_LEN_INWORD];
00144 COMPILER_ALIGNED(32) static LinkedListDescriporView1
00145 dmaReadLinkList[DATA_LEN_INWORD];
00146 
00147 /*----------------------------------------------------------------------------
00148  *        Local functions
00149  *----------------------------------------------------------------------------*/
00150 /**
00151  * \brief Display main menu.
00152  */
00153 static void _displayMenu(void)
00154 {
00155     uint8_t ucChar[5];
00156     printf("\n\rAES Menu :\n\r");
00157     printf("Press [0|1|2|3|4] to set Operation Mode \n\r");
00158     ucChar[0] = (operationMode == AES_MR_OPMOD_ECB) ? 'X' : ' ';
00159     ucChar[1] = (operationMode == AES_MR_OPMOD_CBC) ? 'X' : ' ';
00160     ucChar[2] = (operationMode == AES_MR_OPMOD_OFB) ? 'X' : ' ';
00161     ucChar[3] = (operationMode == AES_MR_OPMOD_CFB) ? 'X' : ' ';
00162     ucChar[4] = (operationMode == AES_MR_OPMOD_CTR) ? 'X' : ' ';
00163     printf("   0: ECB[%c] 1: CBC[%c] 2: OFB[%c] 3: CFB[%c] 4: CTR[%c] \n\r",
00164             ucChar[0], ucChar[1], ucChar[2], ucChar[3], ucChar[4]);
00165     printf("Press [5|6|7| set key size\n\r");
00166     ucChar[0] = (keyMode == AES_MR_KEYSIZE_AES128) ? 'X' : ' ';
00167     ucChar[1] = (keyMode == AES_MR_KEYSIZE_AES192) ? 'X' : ' ';
00168     ucChar[2] = (keyMode == AES_MR_KEYSIZE_AES256) ? 'X' : ' ';
00169     printf("    5: key 128-bits[%c] 6: key 192-bits[%c] 7: key 256-bits[%c]\n\r",
00170             ucChar[0], ucChar[1], ucChar[2]);
00171     printf("Press [m|a|d] to set Start Mode \n\r");
00172     ucChar[0] = (startMode == AES_MR_SMOD_MANUAL_START) ? 'X' : ' ';
00173     ucChar[1] = (startMode == AES_MR_SMOD_AUTO_START) ? 'X' : ' ';
00174     ucChar[2] = (startMode == AES_MR_SMOD_IDATAR0_START) ? 'X' : ' ';
00175     printf("   m: MANUAL_START[%c] a: AUTO_START[%c] d: DMA[%c]\n\r",
00176             ucChar[0], ucChar[1], ucChar[2]);
00177     printf("   p: Begin the encryption/decryption process \n\r");
00178     printf("   h: Display this menu\n\r");
00179     printf("\n\r");
00180 }
00181 
00182 /**
00183  * \brief xDMA handler.
00184  */
00185 void XDMAC_Handler(void)
00186 {
00187     XDMAD_Handler(&xdmad);
00188 }
00189 
00190 /**
00191  * \brief xDMA initialization.
00192  */
00193 
00194 static void _xdma_init(void)
00195 {
00196     /* Initialize XDMA driver instance with polling mode */
00197     XDMAD_Initialize(&xdmad, 1);
00198 
00199     /* Allocate a XDMA channel, Write accesses into AES_IDATARx */
00200     dmaWriteChannel = XDMAD_AllocateChannel(&xdmad, XDMAD_TRANSFER_MEMORY, ID_AES);
00201 
00202     if (dmaWriteChannel == XDMAD_ALLOC_FAILED)
00203         printf("-E- Can't allocate XDMA channel\n\r");
00204 
00205     XDMAD_PrepareChannel(&xdmad, dmaWriteChannel );
00206 
00207     /* Allocate a XDMA channel, Read accesses into AES_ODATARx */
00208     dmaReadChannel = XDMAD_AllocateChannel(&xdmad, ID_AES, XDMAD_TRANSFER_MEMORY);
00209 
00210     if (dmaReadChannel == XDMAD_ALLOC_FAILED)
00211         printf("-E- Can't allocate XDMA channel\n\r");
00212 
00213     XDMAD_PrepareChannel(&xdmad, dmaReadChannel );
00214 }
00215 
00216 /**
00217  * \brief Configure xDMA write linker list for AES transfer.
00218  */
00219 static void _xdma_configure_write(uint32_t *buf, uint32_t len)
00220 {
00221     uint32_t i;
00222     uint32_t xdmaCndc;
00223 
00224     for (i = 0; i < len; i++) {
00225         dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1
00226                                         | ((i == len - 1) ? 0 : XDMA_UBC_NDE_FETCH_EN)
00227                                         | XDMA_UBC_NDEN_UPDATED
00228                                         | 4;
00229         dmaWriteLinkList[i].mbr_sa = (uint32_t)&buf[i * 4];
00230         dmaWriteLinkList[i].mbr_da = (uint32_t)&(AES->AES_IDATAR[0]);
00231 
00232         if (i == len - 1) dmaWriteLinkList[i].mbr_nda = 0;
00233         else dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[ i + 1 ];
00234     }
00235 
00236     xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN
00237                         | XDMAC_CC_MBSIZE_SINGLE
00238                         | XDMAC_CC_DSYNC_MEM2PER
00239                         | XDMAC_CC_CSIZE_CHK_4
00240                         | XDMAC_CC_DWIDTH_WORD
00241                         | XDMAC_CC_SIF_AHB_IF1
00242                         | XDMAC_CC_DIF_AHB_IF1
00243                         | XDMAC_CC_SAM_INCREMENTED_AM
00244                         | XDMAC_CC_DAM_FIXED_AM
00245                         | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_AES, XDMAD_TRANSFER_TX));
00246 
00247     xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1
00248                 | XDMAC_CNDC_NDE_DSCR_FETCH_EN
00249                 | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED
00250                 | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED;
00251 
00252     SCB_CleanDCache_by_Addr((uint32_t *)dmaWriteLinkList, sizeof(dmaWriteLinkList));
00253 
00254     XDMAD_ConfigureTransfer(&xdmad, dmaWriteChannel, &xdmadCfg, xdmaCndc,
00255                                 (uint32_t)&dmaWriteLinkList[0], XDMAC_CIE_LIE);
00256 }
00257 
00258 /**
00259  * \brief Configure xDMA read linker list for AES transfer.
00260  */
00261 static void _xdma_configure_read(uint32_t *buf, uint32_t len)
00262 {
00263     uint32_t i;
00264     uint32_t xdmaCndc;
00265 
00266     for (i = 0; i < len; i++) {
00267         dmaReadLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1
00268                                     | ((i == len - 1) ? 0 : XDMA_UBC_NDE_FETCH_EN)
00269                                     | XDMA_UBC_NDEN_UPDATED
00270                                     | 4;
00271         dmaReadLinkList[i].mbr_sa  = (uint32_t) & (AES->AES_ODATAR[0]);
00272         dmaReadLinkList[i].mbr_da = (uint32_t)&buf[i * 4];
00273 
00274         if (i == len - 1) dmaReadLinkList[i].mbr_nda = 0;
00275         else
00276             dmaReadLinkList[i].mbr_nda = (uint32_t)&dmaReadLinkList[ i + 1 ];
00277     }
00278 
00279     xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN
00280                         | XDMAC_CC_MBSIZE_SINGLE
00281                         | XDMAC_CC_DSYNC_PER2MEM
00282                         | XDMAC_CC_CSIZE_CHK_4
00283                         | XDMAC_CC_DWIDTH_WORD
00284                         | XDMAC_CC_SIF_AHB_IF1
00285                         | XDMAC_CC_DIF_AHB_IF1
00286                         | XDMAC_CC_SAM_FIXED_AM
00287                         | XDMAC_CC_DAM_INCREMENTED_AM
00288                         | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ID_AES, XDMAD_TRANSFER_RX));
00289     xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1
00290                 | XDMAC_CNDC_NDE_DSCR_FETCH_EN
00291                 | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED
00292                 | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED;
00293 
00294     SCB_CleanDCache_by_Addr((uint32_t *)dmaReadLinkList, sizeof(dmaReadLinkList));
00295     XDMAD_ConfigureTransfer(&xdmad, dmaReadChannel, &xdmadCfg, xdmaCndc,
00296                                 (uint32_t)&dmaReadLinkList[0], XDMAC_CIE_LIE);
00297 }
00298 
00299 /**
00300  * \brief AES interrupt hander.
00301  */
00302 void AES_Handler(void)
00303 {
00304     if ((AES_GetStatus() & AES_ISR_DATRDY) == AES_ISR_DATRDY) {
00305         /* Disable AES interrupt */
00306         AES_DisableIt(AES_IER_DATRDY);
00307         desDone = 1;
00308     }
00309 }
00310 
00311 static void _startAES(void)
00312 {
00313     char *p;
00314     uint32_t i;
00315     uint32_t loop = DATA_LEN_INWORD;
00316     /* A software triggered hardware reset of the AES interface is performed */
00317     AES_SoftReset();
00318     /* Configure and enable interrupt on RC compare */
00319     NVIC_ClearPendingIRQ(AES_IRQn);
00320     NVIC_EnableIRQ(AES_IRQn);
00321 
00322     if (startMode == AES_MR_SMOD_IDATAR0_START) {
00323         _xdma_init();
00324         loop = 1;
00325     }
00326 
00327     memcpy((char *)bufPlaint, plaintext, DATA_LEN_INBYTE);
00328 
00329     for (i = 0; i < DATA_LEN_INWORD; i++) {
00330         bufCipher[i] = 0xffffffff;
00331         bufOut[i]  = 0xffffffff;
00332     }
00333 
00334     for (i = 0; i < loop; i += 4) {
00335         /* Encrypts data */
00336         desDone = 0;
00337         /* Enable AES interrupt */
00338         AES_EnableIt(AES_IER_DATRDY);
00339 
00340         AES_Configure(AES_MR_CIPHER_ENCRYPT
00341                         | keyMode
00342                         | startMode
00343                         | operationMode
00344                         );
00345         /* Write the 128-bit/192-bit/256-bit key(s) in the Key Registers
00346                 (AES_KEYxWRx)*/
00347         AES_WriteKey(aes_keys, keylength);
00348 
00349         /* The Initialization Vector Registers concern all modes except ECB. */
00350         if (operationMode != AES_MR_OPMOD_ECB)
00351             AES_SetVector(aes_vectors);
00352 
00353         if (startMode != AES_MR_SMOD_IDATAR0_START) {
00354             /* Write the data to be encrypted in the authorized Input Data
00355                 Registers */
00356             AES_SetInput(&bufPlaint[i]);
00357 
00358             if (startMode == AES_MR_SMOD_MANUAL_START)
00359                 /* Set the START bit in the AES Control register AES_CR to
00360                     begin the encryption process. */
00361                 AES_Start();
00362 
00363             while (!desDone);
00364 
00365             AES_GetOutput(&bufCipher[i]);
00366         } else {
00367             AES_SetDataLen(DATA_LEN_INBYTE);
00368             _xdma_configure_write(bufPlaint, DATA_LEN_INWORD / 4);
00369             _xdma_configure_read(bufCipher, DATA_LEN_INWORD / 4);
00370             SCB_CleanDCache_by_Addr((uint32_t *)bufPlaint, DATA_LEN_INBYTE);
00371             XDMAD_StartTransfer(&xdmad, dmaWriteChannel);
00372             XDMAD_StartTransfer(&xdmad, dmaReadChannel );
00373 
00374             while (XDMAD_IsTransferDone(&xdmad, dmaReadChannel));
00375 
00376             SCB_InvalidateDCache_by_Addr((uint32_t *)bufCipher, DATA_LEN_INBYTE);
00377         }
00378 
00379         /* Decrypts data */
00380         desDone = 0;
00381         /* Enable AES interrupt */
00382         AES_EnableIt(AES_IER_DATRDY);
00383         AES_Configure(AES_MR_CIPHER_DECRYPT
00384                         | keyMode
00385                         | startMode
00386                         | operationMode);
00387         /* Write the 128-bit/192-bit/256-bit key(s) in the Key Registers
00388             (AES_KEYxWRx)*/
00389         AES_WriteKey(aes_keys, keylength);
00390 
00391         /* The Initialization Vector Registers concern all modes except ECB. */
00392         if (operationMode != AES_MR_OPMOD_ECB)
00393             AES_SetVector(aes_vectors);
00394 
00395         if (startMode != AES_MR_SMOD_IDATAR0_START) {
00396             /* Write the data to be decrypted in the authorized Input Data
00397                 Registers */
00398             AES_SetInput(&bufCipher[i]);
00399 
00400             if (startMode == AES_MR_SMOD_MANUAL_START)
00401                 /* Set the START bit in the AES Control register AES_CR to
00402                 begin the decryption process. */
00403                 AES_Start();
00404 
00405             while (!desDone);
00406 
00407             AES_GetOutput(&bufOut[i]);
00408         } else {
00409             XDMAD_FreeChannel(&xdmad, dmaWriteChannel);
00410             XDMAD_FreeChannel(&xdmad, dmaReadChannel);
00411             _xdma_init();
00412             AES_SetDataLen(DATA_LEN_INBYTE);
00413             _xdma_configure_write(bufCipher, DATA_LEN_INWORD / 4);
00414             _xdma_configure_read(bufOut, DATA_LEN_INWORD / 4);
00415             SCB_CleanDCache_by_Addr((uint32_t *)bufCipher, DATA_LEN_INBYTE);
00416             XDMAD_StartTransfer(&xdmad, dmaWriteChannel);
00417             XDMAD_StartTransfer(&xdmad, dmaReadChannel);
00418 
00419             while (XDMAD_IsTransferDone(&xdmad, dmaReadChannel));
00420 
00421             SCB_InvalidateDCache_by_Addr((uint32_t *)bufOut, DATA_LEN_INBYTE);
00422         }
00423     }
00424 
00425     p = (char *)bufOut;
00426     printf("Dump plain text after AES decryption ...\n\r");
00427 
00428     for (i = 0; i < DATA_LEN_INBYTE; i++)
00429         printf("%c", *p++);
00430 
00431     XDMAD_FreeChannel(&xdmad, dmaWriteChannel);
00432     XDMAD_FreeChannel(&xdmad, dmaReadChannel);
00433 }
00434 
00435 /*----------------------------------------------------------------------------
00436  *        Exported functions
00437  *----------------------------------------------------------------------------*/
00438 
00439 /**
00440  *  \brief AES Application entry point.
00441  *
00442  *  \return Unused (ANSI-C compatibility).
00443  *  \callgraph
00444  */
00445 int main(void)
00446 {
00447     uint32_t key;
00448     /* Disable watchdog */
00449     WDT_Disable(WDT);
00450 
00451     /* Enable I and D cache */
00452     SCB_EnableICache();
00453     SCB_EnableDCache();
00454 
00455     /* Output example information */
00456     printf("-- AES Example %s --\n\r", SOFTPACK_VERSION );
00457     printf("-- %s\n\r", BOARD_NAME);
00458     printf("-- Compiled: %s %s With %s--\n\r", __DATE__, __TIME__ ,
00459             COMPILER_NAME);
00460 
00461     /* Enable AES peripheral clock */
00462     PMC_EnablePeripheral(ID_AES);
00463 
00464     /* Configure and enable interrupt on XDMA */
00465     NVIC_ClearPendingIRQ(XDMAC_IRQn);
00466     NVIC_SetPriority(XDMAC_IRQn, 1);
00467     NVIC_EnableIRQ(XDMAC_IRQn);
00468 
00469     /* Display menu */
00470     _displayMenu();
00471     operationMode = AES_MR_OPMOD_ECB;
00472     startMode = AES_MR_SMOD_MANUAL_START;
00473 
00474     //printf("bufPlaint-0x%x  0x%x\n\r",bufPlaint,sizeof(bufPlaint));
00475     keyMode = 0;
00476 
00477     for (; ;) {
00478         key = DBG_GetChar();
00479 
00480         switch (key) {
00481         case '5':
00482         case '6':
00483         case '7':
00484             keyMode = ((key - '5') << AES_MR_KEYSIZE_Pos );
00485             _displayMenu();
00486             keylength = (keyMode == AES_MR_KEYSIZE_AES128) ? 16 : \
00487                         ((keyMode == AES_MR_KEYSIZE_AES192) ? 24 : 32);
00488             break;
00489 
00490         case '0':
00491         case '1':
00492         case '2':
00493         case '3':
00494         case '4':
00495             operationMode = ((key - '0') << AES_MR_OPMOD_Pos );
00496             _displayMenu();
00497             break;
00498 
00499         case 'm':
00500         case 'M':
00501             startMode = AES_MR_SMOD_MANUAL_START; _displayMenu();
00502             break;
00503 
00504         case 'a':
00505         case 'A':
00506             startMode = AES_MR_SMOD_AUTO_START; _displayMenu();
00507             break;
00508 
00509         case 'd':
00510         case 'D':
00511             startMode = AES_MR_SMOD_IDATAR0_START; _displayMenu();
00512             break;
00513 
00514         case 'h':
00515         case 'H':
00516             _displayMenu();
00517             break;
00518 
00519         case 'p':
00520         case 'P':
00521             _startAES();
00522             break;
00523         }
00524     }
00525 }
00526 
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