SAMV71 Xplained Ultra Software Package 1.5

gmii.h

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00002 /*                  Atmel Microcontroller Software Support                      */
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00029 
00030 #ifndef _GMII_DEFINE_H
00031 #define _GMII_DEFINE_H
00032 
00033 
00034 /*---------------------------------------------------------------------------
00035  *         Definitions
00036  *---------------------------------------------------------------------------*/
00037 
00038 //IEEE defined Registers
00039 #define GMII_BMCR        0x0   // Basic Mode Control Register
00040 #define GMII_BMSR        0x1   // Basic Mode Status Register
00041 #define GMII_PHYID1R     0x2   // PHY Identifier Register 1
00042 #define GMII_PHYID2R     0x3   // PHY Identifier Register 2
00043 #define GMII_ANAR        0x4   // Auto_Negotiation Advertisement Register
00044 #define GMII_ANLPAR      0x5   // Auto_negotiation Link Partner Ability Register
00045 #define GMII_ANER        0x6   // Auto-negotiation Expansion Register
00046 #define GMII_ANNPR       0x7   // Auto-negotiation Next Page Register
00047 #define GMII_ANLPNPAR    0x8   // Auto_negotiation Link Partner Next Page Ability Register
00048 #define GMII_AFEC0R      0x11  // AFE Control 0 Register
00049 #define GMII_AFEC3R      0x14  // AFE Control 3 Register
00050 #define GMII_RXERCR      0x15  // RXER Counter Register
00051 #define GMII_OMSSR       0x17  // Operation Mode Strap Status Register
00052 #define GMII_ECR         0x18  // Expanded Control Register
00053 #define GMII_ICSR        0x1B  // Interrupt Control/Status Register
00054 #define GMII_FC          0x1C  // Function Control
00055 #define GMII_LCSR        0x1D  // LinkMDŽ Control/Status Register
00056 #define GMII_PC1R        0x1E  // PHY Control 1 Register
00057 #define GMII_PC2R        0x1F  // PHY Control 2 Register
00058 
00059 // PHY ID Identifier Register
00060 #define GMII_LSB_MASK           0x0U
00061 // definitions: MII_PHYID1
00062 #define GMII_OUI_MSB            0x0022
00063 // definitions: MII_PHYID2
00064 #define GMII_OUI_LSB            0x1572          // KSZ8061 PHY Id2
00065 
00066 // Basic Mode Control Register (BMCR)
00067 // Bit definitions: MII_BMCR
00068 #define GMII_RESET             (1 << 15) // 1= Software Reset; 0=Normal Operation
00069 #define GMII_LOOPBACK          (1 << 14) // 1=loopback Enabled; 0=Normal Operation
00070 #define GMII_SPEED_SELECT_LSB  (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps
00071 #define GMII_AUTONEG           (1 << 12) // Auto-negotiation Enable
00072 #define GMII_POWER_DOWN        (1 << 11) // 1=Power down 0=Normal operation
00073 #define GMII_ISOLATE           (1 << 10) // 1 = Isolates 0 = Normal operation
00074 #define GMII_RESTART_AUTONEG   (1 << 9)  // 1 = Restart auto-negotiation 0 = Normal operation
00075 #define GMII_DUPLEX_MODE       (1 << 8)  // 1 = Full duplex operation 0 = Normal operation
00076 //      Reserved                7        // Read as 0, ignore on write
00077 #define GMII_SPEED_SELECT_MSB  (1 << 6)  // 
00078 //      Reserved                5 to 0   // Read as 0, ignore on write
00079 
00080 
00081 // Basic Mode Status Register (BMSR)
00082 // Bit definitions: MII_BMSR
00083 #define GMII_100BASE_T4        (1 << 15) // 100BASE-T4 Capable
00084 #define GMII_100BASE_TX_FD     (1 << 14) // 100BASE-TX Full Duplex Capable
00085 #define GMII_100BASE_T4_HD     (1 << 13) // 100BASE-TX Half Duplex Capable
00086 #define GMII_10BASE_T_FD       (1 << 12) // 10BASE-T Full Duplex Capable
00087 #define GMII_10BASE_T_HD       (1 << 11) // 10BASE-T Half Duplex Capable
00088 //      Reserved                10 to 9  // Read as 0, ignore on write
00089 #define GMII_EXTEND_STATUS     (1 << 8)  // 1 = Extend Status Information In Reg 15
00090 //      Reserved                7
00091 #define GMII_MF_PREAMB_SUPPR   (1 << 6)  // MII Frame Preamble Suppression
00092 #define GMII_AUTONEG_COMP      (1 << 5)  // Auto-negotiation Complete
00093 #define GMII_REMOTE_FAULT      (1 << 4)  // Remote Fault
00094 #define GMII_AUTONEG_ABILITY   (1 << 3)  // Auto Configuration Ability
00095 #define GMII_LINK_STATUS       (1 << 2)  // Link Status
00096 #define GMII_JABBER_DETECT     (1 << 1)  // Jabber Detect
00097 #define GMII_EXTEND_CAPAB      (1 << 0)  // Extended Capability
00098 
00099 // Auto-negotiation Advertisement Register (ANAR)
00100 // Auto-negotiation Link Partner Ability Register (ANLPAR)
00101 // Bit definitions: MII_ANAR, MII_ANLPAR
00102 #define GMII_NP               (1 << 15) // Next page Indication
00103 //      Reserved               7
00104 #define GMII_RF               (1 << 13) // Remote Fault
00105 //      Reserved               12       // Write as 0, ignore on read
00106 #define GMII_PAUSE_MASK       (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner)
00107                                         // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device)
00108 #define GMII_T4               (1 << 9)  // 100BASE-T4 Support
00109 #define GMII_TX_FDX           (1 << 8)  // 100BASE-TX Full Duplex Support
00110 #define GMII_TX_HDX           (1 << 7)  // 100BASE-TX Support
00111 #define GMII_10_FDX           (1 << 6)  // 10BASE-T Full Duplex Support
00112 #define GMII_10_HDX           (1 << 5)  // 10BASE-T Support
00113 //      Selector                 4 to 0   // Protocol Selection Bits
00114 #define GMII_AN_IEEE_802_3      0x00001
00115 
00116 #endif // #ifndef _MII_DEFINE_H
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