SAMV71 Xplained Ultra Software Package 1.5

instance_usart2.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_USART2_INSTANCE_
00031 #define _SAMV71_USART2_INSTANCE_
00032 
00033 /* ========== Register definition for USART2 peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_USART2_CR                        (0x4002C000U) /**< \brief (USART2) Control Register */
00036   #define REG_USART2_MR                        (0x4002C004U) /**< \brief (USART2) Mode Register */
00037   #define REG_USART2_IER                       (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
00038   #define REG_USART2_IDR                       (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
00039   #define REG_USART2_IMR                       (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
00040   #define REG_USART2_CSR                       (0x4002C014U) /**< \brief (USART2) Channel Status Register */
00041   #define REG_USART2_RHR                       (0x4002C018U) /**< \brief (USART2) Receive Holding Register */
00042   #define REG_USART2_THR                       (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
00043   #define REG_USART2_BRGR                      (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
00044   #define REG_USART2_RTOR                      (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
00045   #define REG_USART2_TTGR                      (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
00046   #define REG_USART2_FIDI                      (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
00047   #define REG_USART2_NER                       (0x4002C044U) /**< \brief (USART2) Number of Errors Register */
00048   #define REG_USART2_IF                        (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
00049   #define REG_USART2_MAN                       (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
00050   #define REG_USART2_LINMR                     (0x4002C054U) /**< \brief (USART2) LIN Mode Register */
00051   #define REG_USART2_LINIR                     (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
00052   #define REG_USART2_LINBRR                    (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
00053   #define REG_USART2_LONMR                     (0x4002C060U) /**< \brief (USART2) LON Mode Register */
00054   #define REG_USART2_LONPR                     (0x4002C064U) /**< \brief (USART2) LON Preamble Register */
00055   #define REG_USART2_LONDL                     (0x4002C068U) /**< \brief (USART2) LON Data Length Register */
00056   #define REG_USART2_LONL2HDR                  (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
00057   #define REG_USART2_LONBL                     (0x4002C070U) /**< \brief (USART2) LON Backlog Register */
00058   #define REG_USART2_LONB1TX                   (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
00059   #define REG_USART2_LONB1RX                   (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
00060   #define REG_USART2_LONPRIO                   (0x4002C07CU) /**< \brief (USART2) LON Priority Register */
00061   #define REG_USART2_IDTTX                     (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
00062   #define REG_USART2_IDTRX                     (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
00063   #define REG_USART2_ICDIFF                    (0x4002C088U) /**< \brief (USART2) IC DIFF Register */
00064   #define REG_USART2_WPMR                      (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
00065   #define REG_USART2_WPSR                      (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
00066   #define REG_USART2_VERSION                   (0x4002C0FCU) /**< \brief (USART2) Version Register */
00067 #else
00068   #define REG_USART2_CR       (*(__O  uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */
00069   #define REG_USART2_MR       (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */
00070   #define REG_USART2_IER      (*(__O  uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
00071   #define REG_USART2_IDR      (*(__O  uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
00072   #define REG_USART2_IMR      (*(__I  uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
00073   #define REG_USART2_CSR      (*(__I  uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
00074   #define REG_USART2_RHR      (*(__I  uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */
00075   #define REG_USART2_THR      (*(__O  uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */
00076   #define REG_USART2_BRGR     (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
00077   #define REG_USART2_RTOR     (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
00078   #define REG_USART2_TTGR     (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
00079   #define REG_USART2_FIDI     (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
00080   #define REG_USART2_NER      (*(__I  uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */
00081   #define REG_USART2_IF       (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
00082   #define REG_USART2_MAN      (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */
00083   #define REG_USART2_LINMR    (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */
00084   #define REG_USART2_LINIR    (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */
00085   #define REG_USART2_LINBRR   (*(__I  uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */
00086   #define REG_USART2_LONMR    (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */
00087   #define REG_USART2_LONPR    (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */
00088   #define REG_USART2_LONDL    (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */
00089   #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */
00090   #define REG_USART2_LONBL    (*(__I  uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */
00091   #define REG_USART2_LONB1TX  (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */
00092   #define REG_USART2_LONB1RX  (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */
00093   #define REG_USART2_LONPRIO  (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */
00094   #define REG_USART2_IDTTX    (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */
00095   #define REG_USART2_IDTRX    (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */
00096   #define REG_USART2_ICDIFF   (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */
00097   #define REG_USART2_WPMR     (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */
00098   #define REG_USART2_WPSR     (*(__I  uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */
00099   #define REG_USART2_VERSION  (*(__I  uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */
00100 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00101 
00102 #endif /* _SAMV71_USART2_INSTANCE_ */
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