SAMV71 Xplained Ultra Software Package 1.5

component_acc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_ACC_COMPONENT_
00031 #define _SAMV71_ACC_COMPONENT_
00032 
00033 /* ============================================================================= */
00034 /**  SOFTWARE API DEFINITION FOR Analog Comparator Controller */
00035 /* ============================================================================= */
00036 /** \addtogroup SAMV71_ACC Analog Comparator Controller */
00037 /*@{*/
00038 
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040 /** \brief Acc hardware registers */
00041 typedef struct {
00042   __O  uint32_t ACC_CR;        /**< \brief (Acc Offset: 0x00) Control Register */
00043   __IO uint32_t ACC_MR;        /**< \brief (Acc Offset: 0x04) Mode Register */
00044   __I  uint32_t Reserved1[7];
00045   __O  uint32_t ACC_IER;       /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */
00046   __O  uint32_t ACC_IDR;       /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */
00047   __I  uint32_t ACC_IMR;       /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */
00048   __I  uint32_t ACC_ISR;       /**< \brief (Acc Offset: 0x30) Interrupt Status Register */
00049   __I  uint32_t Reserved2[24];
00050   __IO uint32_t ACC_ACR;       /**< \brief (Acc Offset: 0x94) Analog Control Register */
00051   __I  uint32_t Reserved3[19];
00052   __IO uint32_t ACC_WPMR;      /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */
00053   __I  uint32_t ACC_WPSR;      /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */
00054   __I  uint32_t Reserved4[4];
00055   __I  uint32_t ACC_VER;       /**< \brief (Acc Offset: 0xFC) Version Register */
00056 } Acc;
00057 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00058 /* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */
00059 #define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */
00060 /* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */
00061 #define ACC_MR_SELMINUS_Pos 0
00062 #define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */
00063 #define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)))
00064 #define   ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */
00065 #define   ACC_MR_SELMINUS_VREFP (0x1u << 0) /**< \brief (ACC_MR) Select VREFP */
00066 #define   ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */
00067 #define   ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */
00068 #define   ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */
00069 #define   ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */
00070 #define   ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */
00071 #define   ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */
00072 #define ACC_MR_SELPLUS_Pos 4
00073 #define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */
00074 #define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)))
00075 #define   ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */
00076 #define   ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */
00077 #define   ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */
00078 #define   ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */
00079 #define   ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */
00080 #define   ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */
00081 #define   ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */
00082 #define   ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */
00083 #define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */
00084 #define   ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */
00085 #define   ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */
00086 #define ACC_MR_EDGETYP_Pos 9
00087 #define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */
00088 #define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)))
00089 #define   ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */
00090 #define   ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */
00091 #define   ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */
00092 #define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */
00093 #define   ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */
00094 #define   ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */
00095 #define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */
00096 #define   ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */
00097 #define   ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */
00098 #define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */
00099 #define   ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */
00100 #define   ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */
00101 /* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */
00102 #define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */
00103 /* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */
00104 #define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */
00105 /* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */
00106 #define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */
00107 /* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */
00108 #define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */
00109 #define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */
00110 #define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */
00111 /* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */
00112 #define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */
00113 #define   ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */
00114 #define   ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */
00115 #define ACC_ACR_HYST_Pos 1
00116 #define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */
00117 #define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)))
00118 /* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */
00119 #define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */
00120 #define ACC_WPMR_WPKEY_Pos 8
00121 #define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */
00122 #define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)))
00123 #define   ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */
00124 /* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */
00125 #define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */
00126 /* -------- ACC_VER : (ACC Offset: 0xFC) Version Register -------- */
00127 #define ACC_VER_VERSION_Pos 0
00128 #define ACC_VER_VERSION_Msk (0xfffu << ACC_VER_VERSION_Pos) /**< \brief (ACC_VER) Version of the Hardware Module */
00129 #define ACC_VER_MFN_Pos 16
00130 #define ACC_VER_MFN_Msk (0x7u << ACC_VER_MFN_Pos) /**< \brief (ACC_VER) Metal Fix Number */
00131 
00132 /*@}*/
00133 
00134 
00135 #endif /* _SAMV71_ACC_COMPONENT_ */
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