00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_DACC_INSTANCE_ 00031 #define _SAMV71_DACC_INSTANCE_ 00032 00033 /* ========== Register definition for DACC peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */ 00036 #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */ 00037 #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */ 00038 #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */ 00039 #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */ 00040 #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */ 00041 #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */ 00042 #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ 00043 #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ 00044 #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ 00045 #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */ 00046 #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */ 00047 #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode Register */ 00048 #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status Register */ 00049 #define REG_DACC_VERSION (0x400400FCU) /**< \brief (DACC) Version Register */ 00050 #else 00051 #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */ 00052 #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */ 00053 #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */ 00054 #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */ 00055 #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */ 00056 #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */ 00057 #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */ 00058 #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ 00059 #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ 00060 #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ 00061 #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */ 00062 #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */ 00063 #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode Register */ 00064 #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status Register */ 00065 #define REG_DACC_VERSION (*(__I uint32_t*)0x400400FCU) /**< \brief (DACC) Version Register */ 00066 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00067 00068 #endif /* _SAMV71_DACC_INSTANCE_ */