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Data Structures | |
struct | DeviceVectors |
Defines | |
#define | __CM7_REV 0x0000 |
Configuration of the Cortex-M7 Processor and Core Peripherals. | |
#define | __MPU_PRESENT 1 |
#define | __NVIC_PRIO_BITS 3 |
#define | __FPU_PRESENT 1 |
#define | __FPU_DP 1 |
#define | __ICACHE_PRESENT 1 |
#define | __DCACHE_PRESENT 1 |
#define | __DTCM_PRESENT 1 |
#define | __ITCM_PRESENT 1 |
#define | __Vendor_SysTickConfig 0 |
Enumerations | |
enum | IRQn_Type { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, PIOC_IRQn = 12, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27, TC5_IRQn = 28, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47, TC7_IRQn = 48, TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, SDRAMC_IRQn = 62, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, PIOC_IRQn = 12, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27, TC5_IRQn = 28, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN1_IRQn = 37, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47, TC7_IRQn = 48, TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, SDRAMC_IRQn = 62, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, SUPC_IRQn = 0, RSTC_IRQn = 1, RTC_IRQn = 2, RTT_IRQn = 3, WDT_IRQn = 4, PMC_IRQn = 5, EFC_IRQn = 6, UART0_IRQn = 7, UART1_IRQn = 8, PIOA_IRQn = 10, PIOB_IRQn = 11, PIOC_IRQn = 12, USART0_IRQn = 13, USART1_IRQn = 14, USART2_IRQn = 15, PIOD_IRQn = 16, PIOE_IRQn = 17, HSMCI_IRQn = 18, TWIHS0_IRQn = 19, TWIHS1_IRQn = 20, SPI0_IRQn = 21, SSC_IRQn = 22, TC0_IRQn = 23, TC1_IRQn = 24, TC2_IRQn = 25, TC3_IRQn = 26, TC4_IRQn = 27, TC5_IRQn = 28, AFEC0_IRQn = 29, DACC_IRQn = 30, PWM0_IRQn = 31, ICM_IRQn = 32, ACC_IRQn = 33, USBHS_IRQn = 34, MCAN0_IRQn = 35, MCAN0_LINE1_IRQn = 36, MCAN1_IRQn = 37, MCAN1_LINE1_IRQn = 38, GMAC_IRQn = 39, AFEC1_IRQn = 40, TWIHS2_IRQn = 41, SPI1_IRQn = 42, QSPI_IRQn = 43, UART2_IRQn = 44, UART3_IRQn = 45, UART4_IRQn = 46, TC6_IRQn = 47, TC7_IRQn = 48, TC8_IRQn = 49, TC9_IRQn = 50, TC10_IRQn = 51, TC11_IRQn = 52, MLB_IRQn = 53, AES_IRQn = 56, TRNG_IRQn = 57, XDMAC_IRQn = 58, ISI_IRQn = 59, PWM1_IRQn = 60, SDRAMC_IRQn = 62, RSWDT_IRQn = 63, PERIPH_COUNT_IRQn = 64 } |
Functions | |
void | Reset_Handler (void) |
void | NMI_Handler (void) |
Default NMI interrupt handler. | |
void | HardFault_Handler (void) |
Default HardFault interrupt handler. | |
void | MemManage_Handler (void) |
Default MemManage interrupt handler. There is a weak handler by default and if the MPU feature is enabled, it must be implemented with the actual handler. | |
void | BusFault_Handler (void) |
Default BusFault interrupt handler. | |
void | UsageFault_Handler (void) |
Default UsageFault interrupt handler. | |
void | SVC_Handler (void) |
Default SVC interrupt handler. | |
void | DebugMon_Handler (void) |
void | PendSV_Handler (void) |
void | SysTick_Handler (void) |
Handler for System Tick interrupt. | |
void | ACC_Handler (void) |
void | AES_Handler (void) |
AES interrupt hander. | |
void | AFEC0_Handler (void) |
void | AFEC1_Handler (void) |
void | DACC_Handler (void) |
void | EFC_Handler (void) |
void | GMAC_Handler (void) |
void | HSMCI_Handler (void) |
void | ICM_Handler (void) |
ICM interrupt hander. | |
void | ISI_Handler (void) |
ISI interrupt handler. | |
void | MCAN0_Handler (void) |
void | MCAN1_Handler (void) |
void | MLB_Handler (void) |
void | PIOA_Handler (void) |
Parallel IO Controller A interrupt handler PIOA interrupt handler for NVIC interrupt table. | |
void | PIOB_Handler (void) |
Parallel IO Controller B interrupt handler PIOB interrupt handler for NVIC interrupt table. | |
void | PIOD_Handler (void) |
Parallel IO Controller D interrupt handler PIOD interrupt handler for NVIC interrupt table. | |
void | PMC_Handler (void) |
void | PWM0_Handler (void) |
void | PWM1_Handler (void) |
void | QSPI_Handler (void) |
void | RSTC_Handler (void) |
void | RSWDT_Handler (void) |
void | RTC_Handler (void) |
Interrupt handler for the RTC. Refreshes the display. | |
void | RTT_Handler (void) |
Interrupt handler for the RTT. | |
void | SPI0_Handler (void) |
void | SPI1_Handler (void) |
void | SSC_Handler (void) |
void | SUPC_Handler (void) |
void | TC0_Handler (void) |
void | TC1_Handler (void) |
void | TC2_Handler (void) |
void | TC9_Handler (void) |
void | TC10_Handler (void) |
void | TC11_Handler (void) |
void | TRNG_Handler (void) |
TRNG interrupt handler. | |
void | TWIHS0_Handler (void) |
TWI interrupt handler. Forwards the interrupt to the TWI driver handler. | |
void | TWIHS1_Handler (void) |
void | UART0_Handler (void) |
void | UART1_Handler (void) |
void | UART2_Handler (void) |
void | UART3_Handler (void) |
void | UART4_Handler (void) |
void | USART0_Handler (void) |
void | USART1_Handler (void) |
USART ISR for wakeup from sleep mode. | |
void | USART2_Handler (void) |
void | USBHS_Handler (void) |
void | WDT_Handler (void) |
Handler for watchdog interrupt. | |
void | XDMAC_Handler (void) |
xDMA interrupt handler. |
#define __CM7_REV 0x0000 |
Configuration of the Cortex-M7 Processor and Core Peripherals.
SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number)
Definition at line 278 of file samv71j19.h.
#define __DCACHE_PRESENT 1 |
SAMV71J19 does provide a Data Cache
Definition at line 284 of file samv71j19.h.
#define __DTCM_PRESENT 1 |
SAMV71J19 does provide a Data TCM
Definition at line 285 of file samv71j19.h.
#define __FPU_DP 1 |
SAMV71J19 Double precision FPU
Definition at line 282 of file samv71j19.h.
#define __FPU_PRESENT 1 |
SAMV71J19 does provide a FPU
Definition at line 281 of file samv71j19.h.
#define __ICACHE_PRESENT 1 |
SAMV71J19 does provide an Instruction Cache
Definition at line 283 of file samv71j19.h.
#define __ITCM_PRESENT 1 |
SAMV71J19 does provide an Instruction TCM
Definition at line 286 of file samv71j19.h.
#define __MPU_PRESENT 1 |
SAMV71J19 does provide a MPU
Definition at line 279 of file samv71j19.h.
#define __NVIC_PRIO_BITS 3 |
SAMV71J19 uses 3 Bits for the Priority Levels
Definition at line 280 of file samv71j19.h.
#define __Vendor_SysTickConfig 0 |
Set to 1 if different SysTick Config is used
Definition at line 287 of file samv71j19.h.
enum IRQn_Type |
< Interrupt Number Definition
Definition at line 57 of file samv71j19.h.
void HSMCI_Handler | ( | void | ) |
void Reset_Handler | ( | void | ) |
------------------------------------------------------------------------------ This is the code that gets called on processor reset. To initialize the device. -----------------------------------------------------------------------------
Definition at line 275 of file startup_sam.c.
void RTT_Handler | ( | void | ) |
void SysTick_Handler | ( | void | ) |
Handler for System Tick interrupt.
Process System Tick Event Increments the time-stamp counter.
Definition at line 65 of file timetick.c.
void TC0_Handler | ( | void | ) |
void USBHS_Handler | ( | void | ) |
USBD (UDP) interrupt handler Manages device resume, suspend, end of bus reset. Forwards endpoint events to the appropriate handler.
Definition at line 1006 of file USBD_HAL.c.
void XDMAC_Handler | ( | void | ) |