SAMV71 Xplained Ultra Software Package 1.5

instance_matrix.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2015, Atmel Corporation                                        */
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00011 /*                                                                              */
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00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_MATRIX_INSTANCE_
00031 #define _SAMV71_MATRIX_INSTANCE_
00032 
00033 /* ========== Register definition for MATRIX peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_MATRIX_MCFG                     (0x40088000U) /**< \brief (MATRIX) Master Configuration Register */
00036   #define REG_MATRIX_SCFG                     (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
00037   #define REG_MATRIX_PRAS0                    (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
00038   #define REG_MATRIX_PRBS0                    (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
00039   #define REG_MATRIX_PRAS1                    (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
00040   #define REG_MATRIX_PRBS1                    (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
00041   #define REG_MATRIX_PRAS2                    (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
00042   #define REG_MATRIX_PRBS2                    (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
00043   #define REG_MATRIX_PRAS3                    (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
00044   #define REG_MATRIX_PRBS3                    (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
00045   #define REG_MATRIX_PRAS4                    (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
00046   #define REG_MATRIX_PRBS4                    (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
00047   #define REG_MATRIX_PRAS5                    (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
00048   #define REG_MATRIX_PRBS5                    (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
00049   #define REG_MATRIX_PRAS6                    (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
00050   #define REG_MATRIX_PRBS6                    (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
00051   #define REG_MATRIX_PRAS7                    (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
00052   #define REG_MATRIX_PRBS7                    (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
00053   #define REG_MATRIX_PRAS8                    (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
00054   #define REG_MATRIX_PRBS8                    (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
00055   #define REG_MATRIX_MRCR                     (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
00056   #define REG_CCFG_CAN0                       (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */
00057   #define REG_CCFG_SYSIO                      (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */
00058   #define REG_CCFG_SMCNFCS                    (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
00059   #define REG_MATRIX_WPMR                     (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
00060   #define REG_MATRIX_WPSR                     (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
00061   #define REG_MATRIX_VERSION                  (0x400881FCU) /**< \brief (MATRIX) Version Register */
00062 #else
00063   #define REG_MATRIX_MCFG    (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register */
00064   #define REG_MATRIX_SCFG    (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */
00065   #define REG_MATRIX_PRAS0   (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
00066   #define REG_MATRIX_PRBS0   (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
00067   #define REG_MATRIX_PRAS1   (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
00068   #define REG_MATRIX_PRBS1   (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
00069   #define REG_MATRIX_PRAS2   (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
00070   #define REG_MATRIX_PRBS2   (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
00071   #define REG_MATRIX_PRAS3   (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
00072   #define REG_MATRIX_PRBS3   (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
00073   #define REG_MATRIX_PRAS4   (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
00074   #define REG_MATRIX_PRBS4   (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
00075   #define REG_MATRIX_PRAS5   (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
00076   #define REG_MATRIX_PRBS5   (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
00077   #define REG_MATRIX_PRAS6   (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
00078   #define REG_MATRIX_PRBS6   (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
00079   #define REG_MATRIX_PRAS7   (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
00080   #define REG_MATRIX_PRBS7   (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
00081   #define REG_MATRIX_PRAS8   (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
00082   #define REG_MATRIX_PRBS8   (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
00083   #define REG_MATRIX_MRCR    (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */
00084   #define REG_CCFG_CAN0      (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */
00085   #define REG_CCFG_SYSIO     (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */
00086   #define REG_CCFG_SMCNFCS   (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */
00087   #define REG_MATRIX_WPMR    (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */
00088   #define REG_MATRIX_WPSR    (*(__I  uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */
00089   #define REG_MATRIX_VERSION (*(__I  uint32_t*)0x400881FCU) /**< \brief (MATRIX) Version Register */
00090 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00091 
00092 #endif /* _SAMV71_MATRIX_INSTANCE_ */
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