00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_TC1_INSTANCE_ 00031 #define _SAMV71_TC1_INSTANCE_ 00032 00033 /* ========== Register definition for TC1 peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ 00036 #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ 00037 #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ 00038 #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ 00039 #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ 00040 #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ 00041 #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ 00042 #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ 00043 #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ 00044 #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ 00045 #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ 00046 #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ 00047 #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ 00048 #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ 00049 #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ 00050 #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ 00051 #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ 00052 #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ 00053 #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ 00054 #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ 00055 #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ 00056 #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ 00057 #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ 00058 #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ 00059 #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ 00060 #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ 00061 #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ 00062 #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ 00063 #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ 00064 #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ 00065 #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ 00066 #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ 00067 #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ 00068 #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ 00069 #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ 00070 #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ 00071 #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ 00072 #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ 00073 #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ 00074 #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */ 00075 #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */ 00076 #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ 00077 #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ 00078 #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ 00079 #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ 00080 #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */ 00081 #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ 00082 #define REG_TC1_VER (0x400100FCU) /**< \brief (TC1) Version Register */ 00083 #else 00084 #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ 00085 #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ 00086 #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ 00087 #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ 00088 #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ 00089 #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ 00090 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ 00091 #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ 00092 #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ 00093 #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ 00094 #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ 00095 #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ 00096 #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ 00097 #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ 00098 #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ 00099 #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ 00100 #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ 00101 #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ 00102 #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ 00103 #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ 00104 #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ 00105 #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ 00106 #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ 00107 #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ 00108 #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ 00109 #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ 00110 #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ 00111 #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ 00112 #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ 00113 #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ 00114 #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ 00115 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ 00116 #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ 00117 #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ 00118 #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ 00119 #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ 00120 #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ 00121 #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ 00122 #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ 00123 #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */ 00124 #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */ 00125 #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ 00126 #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ 00127 #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ 00128 #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ 00129 #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */ 00130 #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ 00131 #define REG_TC1_VER (*(__I uint32_t*)0x400100FCU) /**< \brief (TC1) Version Register */ 00132 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00133 00134 #endif /* _SAMV71_TC1_INSTANCE_ */