SAMV71 Xplained Ultra Software Package 1.5

startup_sam.c

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2015, Atmel Corporation                                        */
00006 /*                                                                              */
00007 /* All rights reserved.                                                         */
00008 /*                                                                              */
00009 /* Redistribution and use in source and binary forms, with or without           */
00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
00012 /* - Redistributions of source code must retain the above copyright notice,     */
00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
00018 /* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR   */
00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE   */
00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,      */
00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    */
00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING         */
00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                           */
00028 /* ---------------------------------------------------------------------------- */
00029 
00030 #include "samv71.h"
00031 #include <stdio.h>
00032 
00033 typedef void (*intfunc) (void);
00034 typedef union { intfunc __fun; void *__ptr; } intvec_elem;
00035 
00036 extern int Image$$ARM_LIB_STACK$$ZI$$Limit;
00037 extern int Image$$Vector_region$$Base;
00038 extern int Image$$Vector_region$$Limit;
00039 
00040 extern void __main(void);
00041 __INLINE void Reset_Handler(void);
00042 
00043 int __low_level_init(void);
00044 /* Default empty handler */
00045 void Dummy_Handler(void);
00046 
00047 #pragma weak NMI_Handler=Dummy_Handler
00048 #pragma weak HardFault_Handler=Dummy_Handler
00049 #pragma weak MemManage_Handler=Dummy_Handler
00050 #pragma weak BusFault_Handler=Dummy_Handler
00051 #pragma weak UsageFault_Handler=Dummy_Handler
00052 #pragma weak SVC_Handler=Dummy_Handler
00053 #pragma weak DebugMon_Handler=Dummy_Handler
00054 #pragma weak PendSV_Handler=Dummy_Handler
00055 #pragma weak SysTick_Handler=Dummy_Handler
00056 
00057 /* Peripherals handlers */
00058 #pragma weak SUPC_Handler=Dummy_Handler
00059 #pragma weak RSTC_Handler=Dummy_Handler
00060 #pragma weak RTC_Handler=Dummy_Handler
00061 #pragma weak RTT_Handler=Dummy_Handler
00062 #pragma weak WDT_Handler=Dummy_Handler
00063 #pragma weak PMC_Handler=Dummy_Handler
00064 #pragma weak EFC_Handler=Dummy_Handler
00065 #pragma weak UART0_Handler=Dummy_Handler
00066 #pragma weak UART1_Handler=Dummy_Handler
00067 #pragma weak PIOA_Handler=Dummy_Handler
00068 #pragma weak PIOB_Handler=Dummy_Handler
00069 #ifdef _SAMV71_PIOC_INSTANCE_
00070     #pragma weak PIOC_Handler=Dummy_Handler
00071 #endif /* _SAM_PIOC_INSTANCE_ */
00072 #pragma weak USART0_Handler=Dummy_Handler
00073 #pragma weak USART1_Handler=Dummy_Handler
00074 #pragma weak USART2_Handler=Dummy_Handler
00075 #pragma weak PIOD_Handler=Dummy_Handler
00076 #ifdef _SAMV71_PIOE_INSTANCE_
00077     #pragma weak PIOE_Handler=Dummy_Handler
00078 #endif /* _SAM_PIOE_INSTANCE_ */
00079 #ifdef _SAMV71_HSMCI_INSTANCE_
00080     #pragma weak HSMCI_Handler=Dummy_Handler
00081 #endif /* _SAM_HSMCI_INSTANCE_ */
00082 #pragma weak TWIHS0_Handler=Dummy_Handler
00083 #pragma weak TWIHS1_Handler=Dummy_Handler
00084 #pragma weak SPI0_Handler=Dummy_Handler
00085 #pragma weak SSC_Handler=Dummy_Handler
00086 #pragma weak TC0_Handler=Dummy_Handler
00087 #pragma weak TC1_Handler=Dummy_Handler
00088 #pragma weak TC2_Handler=Dummy_Handler
00089 #ifdef _SAMV71_TC1_INSTANCE_
00090     #pragma weak TC3_Handler=Dummy_Handler
00091 #endif /* _SAM_TC1_INSTANCE_ */
00092 #ifdef _SAMV71_TC1_INSTANCE_
00093     #pragma weak TC4_Handler=Dummy_Handler
00094 #endif /* _SAM_TC1_INSTANCE_ */
00095 #ifdef _SAMV71_TC1_INSTANCE_
00096     #pragma weak TC5_Handler=Dummy_Handler
00097 #endif /* _SAM_TC1_INSTANCE_ */
00098 #pragma weak AFEC0_Handler=Dummy_Handler
00099 #ifdef _SAMV71_DACC_INSTANCE_
00100     #pragma weak DACC_Handler=Dummy_Handler
00101 #endif /* _SAM_DACC_INSTANCE_ */
00102 #pragma weak PWM0_Handler=Dummy_Handler
00103 #pragma weak ICM_Handler=Dummy_Handler
00104 #pragma weak ACC_Handler=Dummy_Handler
00105 #pragma weak USBHS_Handler=Dummy_Handler
00106 #pragma weak MCAN0_Handler=Dummy_Handler
00107 #pragma weak MCAN0_Line1_Handler=Dummy_Handler
00108 #pragma weak MCAN1_Handler=Dummy_Handler
00109 #pragma weak MCAN1_Line1_Handler=Dummy_Handler
00110 #pragma weak GMAC_Handler=Dummy_Handler
00111 #pragma weak GMACQ1_Handler=Dummy_Handler
00112 #pragma weak GMACQ2_Handler=Dummy_Handler
00113 #pragma weak AFEC1_Handler=Dummy_Handler
00114 #ifdef _SAMV71_TWIHS2_INSTANCE_
00115     #pragma weak TWIHS2_Handler=Dummy_Handler
00116 #endif /* _SAM_TWI2_INSTANCE_ */
00117 #pragma weak SPI1_Handler=Dummy_Handler
00118 #pragma weak QSPI_Handler=Dummy_Handler
00119 #pragma weak UART2_Handler=Dummy_Handler
00120 #pragma weak UART3_Handler=Dummy_Handler
00121 #pragma weak UART4_Handler=Dummy_Handler
00122 #ifdef _SAMV71_TC2_INSTANCE_
00123     #pragma weak TC6_Handler=Dummy_Handler
00124 #endif /* _SAM_TC2_INSTANCE_ */
00125 #ifdef _SAMV71_TC2_INSTANCE_
00126     #pragma weak TC7_Handler=Dummy_Handler
00127 #endif /* _SAM_TC2_INSTANCE_ */
00128 #ifdef _SAMV71_TC2_INSTANCE_
00129     #pragma weak TC8_Handler=Dummy_Handler
00130 #endif /* _SAM_TC2_INSTANCE_ */
00131 #pragma weak TC9_Handler=Dummy_Handler
00132 #pragma weak TC10_Handler=Dummy_Handler
00133 #pragma weak TC11_Handler=Dummy_Handler
00134 #pragma weak MLB_Handler=Dummy_Handler
00135 #pragma weak AES_Handler=Dummy_Handler
00136 #pragma weak TRNG_Handler=Dummy_Handler
00137 #pragma weak XDMAC_Handler=Dummy_Handler
00138 #pragma weak ISI_Handler=Dummy_Handler
00139 #pragma weak PWM1_Handler=Dummy_Handler
00140 #pragma weak FPU_Handler=Dummy_Handler
00141 #ifdef _SAMV71_SDRAMC_INSTANCE_
00142     #pragma weak SDRAMC_Handler=Dummy_Handler
00143 #endif /* _SAM_SDRAMC_INSTANCE_ */
00144 #pragma weak RSWDT_Handler=Dummy_Handler
00145 #pragma weak CCF_Handler=Dummy_Handler
00146 #pragma weak CCW_Handler=Dummy_Handler
00147 
00148 
00149 /* The name "__vector_table" has special meaning for C-SPY: */
00150 /* it is where the SP start value is found, and the NVIC vector */
00151 /* table register (VTOR) is initialized to this address if != 0 */
00152 #pragma arm section rodata = "vectors"
00153 
00154 const intvec_elem __vector_table[] = {
00155     (intfunc) &Image$$ARM_LIB_STACK$$ZI$$Limit,
00156     Reset_Handler,
00157     NMI_Handler,
00158     HardFault_Handler,
00159     MemManage_Handler,
00160     BusFault_Handler,
00161     UsageFault_Handler,
00162     (0UL), (0UL), (0UL), (0UL),          /* Reserved */
00163     SVC_Handler,
00164     DebugMon_Handler,
00165     (0UL),          /* Reserved */
00166     PendSV_Handler,
00167     SysTick_Handler,
00168 
00169     SUPC_Handler,   /* 0  Supply Controller */
00170     RSTC_Handler,   /* 1  Reset Controller */
00171     RTC_Handler,    /* 2  Real Time Clock */
00172     RTT_Handler,    /* 3  Real Time Timer */
00173     WDT_Handler,    /* 4  Watchdog Timer 0 */
00174     PMC_Handler,    /* 5  Power Management Controller */
00175     EFC_Handler,    /* 6  Enhanced Embedded Flash Controller */
00176     UART0_Handler,  /* 7  UART 0 */
00177     UART1_Handler,  /* 8  UART 1 */
00178     (0UL),          /* 9  Reserved */
00179     PIOA_Handler,   /* 10 Parallel I/O Controller A */
00180     PIOB_Handler,   /* 11 Parallel I/O Controller B */
00181     PIOC_Handler,   /* 12 Parallel I/O Controller C */
00182     USART0_Handler, /* 13 USART 0 */
00183     USART1_Handler, /* 14 USART 1 */
00184     USART2_Handler, /* 15 USART 2 */
00185     PIOD_Handler,   /* 16 Parallel I/O Controller D */
00186     PIOE_Handler,   /* 17 Parallel I/O Controller E */
00187     HSMCI_Handler,  /* 18 Multimedia Card Interface */
00188     TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */
00189     TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */
00190     SPI0_Handler,   /* 21 Serial Peripheral Interface 0 */
00191     SSC_Handler,    /* 22 Synchronous Serial Controller */
00192     TC0_Handler,    /* 23 Timer/Counter 0 */
00193     TC1_Handler,    /* 24 Timer/Counter 1 */
00194     TC2_Handler,    /* 25 Timer/Counter 2 */
00195     TC3_Handler,    /* 26 Timer/Counter 3 */
00196     TC4_Handler,    /* 27 Timer/Counter 4 */
00197     TC5_Handler,    /* 28 Timer/Counter 5 */
00198     AFEC0_Handler,  /* 29 Analog Front End 0 */
00199     DACC_Handler,   /* 30 Digital To Analog Converter */
00200     PWM0_Handler,   /* 31 Pulse Width Modulation 0 */
00201     ICM_Handler,    /* 32 Integrity Check Monitor */
00202     ACC_Handler,    /* 33 Analog Comparator */
00203     USBHS_Handler,  /* 34 USB Host / Device Controller */
00204     MCAN0_Handler,   /* 35 CAN Controller 0 */
00205     MCAN0_Line1_Handler, /* 36 CAN Controller 0 - Line 1 */
00206     MCAN1_Handler,  /* 37 CAN Controller 1 */
00207     MCAN1_Line1_Handler,  /* 38 CAN Controller 1 - Line 1 */
00208     GMAC_Handler,   /* 39 Ethernet MAC */
00209     AFEC1_Handler,  /* 40 Analog Front End 1 */
00210     TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */
00211     SPI1_Handler,   /* 42 Serial Peripheral Interface 1 */
00212     QSPI_Handler,   /* 43 Quad I/O Serial Peripheral Interface */
00213     UART2_Handler,  /* 44 UART 2 */
00214     UART3_Handler,  /* 45 UART 3 */
00215     UART4_Handler,  /* 46 UART 4 */
00216     TC6_Handler,    /* 47 Timer/Counter 6 */
00217     TC7_Handler,    /* 48 Timer/Counter 7 */
00218     TC8_Handler,    /* 49 Timer/Counter 8 */
00219     TC9_Handler,    /* 50 Timer/Counter 9 */
00220     TC10_Handler,   /* 51 Timer/Counter 10 */
00221     TC11_Handler,   /* 52 Timer/Counter 11 */
00222     MLB_Handler,    /* 53 MediaLB */
00223     (0UL),          /* 54 Reserved */
00224     (0UL),          /* 55 Reserved */
00225     AES_Handler,    /* 56 AES */
00226     TRNG_Handler,   /* 57 True Random Generator */
00227     XDMAC_Handler,  /* 58 DMA */
00228     ISI_Handler,    /* 59 Camera Interface */
00229     PWM1_Handler,   /* 60 Pulse Width Modulation 1 */
00230     (0UL),          /* 61 Reserved */
00231     SDRAMC_Handler, /* 62 SDRAM Controller */
00232     RSWDT_Handler,  /* 63 Watchdog Timer 1 */
00233 };
00234 #pragma arm section
00235 
00236 
00237 void LowLevelInit(void);
00238 
00239 #ifdef ENABLE_TCM
00240 /** \brief  TCM memory enable
00241 
00242     The function enables TCM memories
00243  */
00244 __STATIC_INLINE void TCM_Enable(void)
00245 {
00246 
00247     __DSB();
00248     __ISB();
00249     SCB->ITCMCR = (SCB_ITCMCR_EN_Msk  | SCB_ITCMCR_RMW_Msk | SCB_ITCMCR_RETEN_Msk);
00250     SCB->DTCMCR = (SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk | SCB_DTCMCR_RETEN_Msk);
00251     __DSB();
00252     __ISB();
00253 }
00254 #endif
00255 
00256 /** \brief  TCM memory Disable
00257 
00258     The function enables TCM memories
00259  */
00260 __STATIC_INLINE void TCM_Disable(void)
00261 {
00262 
00263     __DSB();
00264     __ISB();
00265     SCB->ITCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk;
00266     SCB->DTCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk;
00267     __DSB();
00268     __ISB();
00269 }
00270 
00271 /**------------------------------------------------------------------------------
00272  * This is the code that gets called on processor reset. To initialize the
00273  * device.
00274  *-----------------------------------------------------------------------------*/
00275 void Reset_Handler(void)
00276 {
00277     uint32_t *pSrc = (uint32_t *)&Image$$Vector_region$$Base;
00278 
00279 #ifdef ENABLE_TCM
00280 #ifndef FFT_DEMO
00281     // 32 Kb
00282     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
00283 #else
00284     // 128 Kb
00285     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(8));
00286 #endif
00287     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB | EEFC_FCR_FARG(7));
00288 
00289     TCM_Enable();
00290 #else
00291     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(8));
00292     EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(7));
00293 
00294     TCM_Disable();
00295 #endif
00296 
00297     /* Low level Initialize */
00298     LowLevelInit();
00299     SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
00300 
00301     /* Branch to main function */
00302     __main();
00303 
00304     /* Infinite loop */
00305     while (1);
00306 }
00307 
00308 /**
00309  * \brief Default interrupt handler for unused IRQs.
00310  */
00311 void Dummy_Handler(void)
00312 {
00313     printf("\r\n-E- Enter Dummy_Handler!");
00314 
00315     while (1) {
00316     }
00317 }
00318 
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