SAMV71 Xplained Ultra Software Package 1.5

samv71j20.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2015, Atmel Corporation                                        */
00006 /*                                                                              */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71J20_
00031 #define _SAMV71J20_
00032 
00033 /** \addtogroup SAMV71J20_definitions SAMV71J20 definitions
00034   This file defines all structures and symbols for SAMV71J20:
00035     - registers and bitfields
00036     - peripheral base address
00037     - peripheral ID
00038     - PIO definitions
00039 */
00040 /*@{*/
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00047 #include <stdint.h>
00048 #endif
00049 
00050 /* ************************************************************************** */
00051 /*   CMSIS DEFINITIONS FOR SAMV71J20 */
00052 /* ************************************************************************** */
00053 /** \addtogroup SAMV71J20_cmsis CMSIS Definitions */
00054 /*@{*/
00055 
00056 /**< Interrupt Number Definition */
00057 typedef enum IRQn
00058 {
00059 /******  Cortex-M7 Processor Exceptions Numbers ******************************/
00060   NonMaskableInt_IRQn   = -14, /**<  2 Non Maskable Interrupt                */
00061   HardFault_IRQn        = -13, /**<  3 HardFault Interrupt                   */
00062   MemoryManagement_IRQn = -12, /**<  4 Cortex-M7 Memory Management Interrupt */
00063   BusFault_IRQn         = -11, /**<  5 Cortex-M7 Bus Fault Interrupt         */
00064   UsageFault_IRQn       = -10, /**<  6 Cortex-M7 Usage Fault Interrupt       */
00065   SVCall_IRQn           = -5,  /**< 11 Cortex-M7 SV Call Interrupt           */
00066   DebugMonitor_IRQn     = -4,  /**< 12 Cortex-M7 Debug Monitor Interrupt     */
00067   PendSV_IRQn           = -2,  /**< 14 Cortex-M7 Pend SV Interrupt           */
00068   SysTick_IRQn          = -1,  /**< 15 Cortex-M7 System Tick Interrupt       */
00069 /******  SAMV71J20 specific Interrupt Numbers *********************************/
00070 
00071   SUPC_IRQn            =  0, /**<  0 SAMV71J20 Supply Controller (SUPC) */
00072   RSTC_IRQn            =  1, /**<  1 SAMV71J20 Reset Controller (RSTC) */
00073   RTC_IRQn             =  2, /**<  2 SAMV71J20 Real Time Clock (RTC) */
00074   RTT_IRQn             =  3, /**<  3 SAMV71J20 Real Time Timer (RTT) */
00075   WDT_IRQn             =  4, /**<  4 SAMV71J20 Watchdog Timer (WDT) */
00076   PMC_IRQn             =  5, /**<  5 SAMV71J20 Power Management Controller (PMC) */
00077   EFC_IRQn             =  6, /**<  6 SAMV71J20 Enhanced Embedded Flash Controller (EFC) */
00078   UART0_IRQn           =  7, /**<  7 SAMV71J20 UART 0 (UART0) */
00079   UART1_IRQn           =  8, /**<  8 SAMV71J20 UART 1 (UART1) */
00080   PIOA_IRQn            = 10, /**< 10 SAMV71J20 Parallel I/O Controller A (PIOA) */
00081   PIOB_IRQn            = 11, /**< 11 SAMV71J20 Parallel I/O Controller B (PIOB) */
00082   USART0_IRQn          = 13, /**< 13 SAMV71J20 USART 0 (USART0) */
00083   USART1_IRQn          = 14, /**< 14 SAMV71J20 USART 1 (USART1) */
00084   USART2_IRQn          = 15, /**< 15 SAMV71J20 USART 2 (USART2) */
00085   PIOD_IRQn            = 16, /**< 16 SAMV71J20 Parallel I/O Controller D (PIOD) */
00086   HSMCI_IRQn           = 18, /**< 18 SAMV71J20 Multimedia Card Interface (HSMCI) */
00087   TWIHS0_IRQn          = 19, /**< 19 SAMV71J20 Two Wire Interface 0 HS (TWIHS0) */
00088   TWIHS1_IRQn          = 20, /**< 20 SAMV71J20 Two Wire Interface 1 HS (TWIHS1) */
00089   SPI0_IRQn            = 21, /**< 21 SAMV71J20 Serial Peripheral Interface 0 (SPI0) */
00090   SSC_IRQn             = 22, /**< 22 SAMV71J20 Synchronous Serial Controller (SSC) */
00091   TC0_IRQn             = 23, /**< 23 SAMV71J20 Timer/Counter 0 (TC0) */
00092   TC1_IRQn             = 24, /**< 24 SAMV71J20 Timer/Counter 1 (TC1) */
00093   TC2_IRQn             = 25, /**< 25 SAMV71J20 Timer/Counter 2 (TC2) */
00094   AFEC0_IRQn           = 29, /**< 29 SAMV71J20 Analog Front End 0 (AFEC0) */
00095   DACC_IRQn            = 30, /**< 30 SAMV71J20 Digital To Analog Converter (DACC) */
00096   PWM0_IRQn            = 31, /**< 31 SAMV71J20 Pulse Width Modulation 0 (PWM0) */
00097   ICM_IRQn             = 32, /**< 32 SAMV71J20 Integrity Check Monitor (ICM) */
00098   ACC_IRQn             = 33, /**< 33 SAMV71J20 Analog Comparator (ACC) */
00099   USBHS_IRQn           = 34, /**< 34 SAMV71J20 USB Host / Device Controller (USBHS) */
00100   MCAN0_IRQn           = 35, /**< 35 SAMV71J20 MCAN Controller 0 (MCAN0) */
00101   MCAN1_IRQn           = 37, /**< 37 SAMV71J20 MCAN Controller 1 (MCAN1) */
00102   GMAC_IRQn            = 39, /**< 39 SAMV71J20 Ethernet MAC (GMAC) */
00103   AFEC1_IRQn           = 40, /**< 40 SAMV71J20 Analog Front End 1 (AFEC1) */
00104   SPI1_IRQn            = 42, /**< 42 SAMV71J20 Serial Peripheral Interface 1 (SPI1) */
00105   QSPI_IRQn            = 43, /**< 43 SAMV71J20 Quad I/O Serial Peripheral Interface (QSPI) */
00106   UART2_IRQn           = 44, /**< 44 SAMV71J20 UART 2 (UART2) */
00107   UART3_IRQn           = 45, /**< 45 SAMV71J20 UART 3 (UART3) */
00108   UART4_IRQn           = 46, /**< 46 SAMV71J20 UART 4 (UART4) */
00109   TC9_IRQn             = 50, /**< 50 SAMV71J20 Timer/Counter 9 (TC9) */
00110   TC10_IRQn            = 51, /**< 51 SAMV71J20 Timer/Counter 10 (TC10) */
00111   TC11_IRQn            = 52, /**< 52 SAMV71J20 Timer/Counter 11 (TC11) */
00112   MLB_IRQn             = 53, /**< 53 SAMV71J20 MediaLB (MLB) */
00113   AES_IRQn             = 56, /**< 56 SAMV71J20 AES (AES) */
00114   TRNG_IRQn            = 57, /**< 57 SAMV71J20 True Random Generator (TRNG) */
00115   XDMAC_IRQn           = 58, /**< 58 SAMV71J20 DMA (XDMAC) */
00116   ISI_IRQn             = 59, /**< 59 SAMV71J20 Camera Interface (ISI) */
00117   PWM1_IRQn            = 60, /**< 60 SAMV71J20 Pulse Width Modulation 1 (PWM1) */
00118   RSWDT_IRQn           = 63, /**< 63 SAMV71J20 Reinforced Secure Watchdog Timer (RSWDT) */
00119 
00120   PERIPH_COUNT_IRQn    = 64  /**< Number of peripheral IDs */
00121 } IRQn_Type;
00122 
00123 typedef struct _DeviceVectors
00124 {
00125   /* Stack pointer */
00126   void* pvStack;
00127 
00128   /* Cortex-M handlers */
00129   void* pfnReset_Handler;
00130   void* pfnNMI_Handler;
00131   void* pfnHardFault_Handler;
00132   void* pfnMemManage_Handler;
00133   void* pfnBusFault_Handler;
00134   void* pfnUsageFault_Handler;
00135   void* pfnReserved1_Handler;
00136   void* pfnReserved2_Handler;
00137   void* pfnReserved3_Handler;
00138   void* pfnReserved4_Handler;
00139   void* pfnSVC_Handler;
00140   void* pfnDebugMon_Handler;
00141   void* pfnReserved5_Handler;
00142   void* pfnPendSV_Handler;
00143   void* pfnSysTick_Handler;
00144 
00145   /* Peripheral handlers */
00146   void* pfnSUPC_Handler;   /*  0 Supply Controller */
00147   void* pfnRSTC_Handler;   /*  1 Reset Controller */
00148   void* pfnRTC_Handler;    /*  2 Real Time Clock */
00149   void* pfnRTT_Handler;    /*  3 Real Time Timer */
00150   void* pfnWDT_Handler;    /*  4 Watchdog Timer */
00151   void* pfnPMC_Handler;    /*  5 Power Management Controller */
00152   void* pfnEFC_Handler;    /*  6 Enhanced Embedded Flash Controller */
00153   void* pfnUART0_Handler;  /*  7 UART 0 */
00154   void* pfnUART1_Handler;  /*  8 UART 1 */
00155   void* pvReserved9;
00156   void* pfnPIOA_Handler;   /* 10 Parallel I/O Controller A */
00157   void* pfnPIOB_Handler;   /* 11 Parallel I/O Controller B */
00158   void* pvReserved12;
00159   void* pfnUSART0_Handler; /* 13 USART 0 */
00160   void* pfnUSART1_Handler; /* 14 USART 1 */
00161   void* pfnUSART2_Handler; /* 15 USART 2 */
00162   void* pfnPIOD_Handler;   /* 16 Parallel I/O Controller D */
00163   void* pvReserved17;
00164   void* pfnHSMCI_Handler;  /* 18 Multimedia Card Interface */
00165   void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */
00166   void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */
00167   void* pfnSPI0_Handler;   /* 21 Serial Peripheral Interface 0 */
00168   void* pfnSSC_Handler;    /* 22 Synchronous Serial Controller */
00169   void* pfnTC0_Handler;    /* 23 Timer/Counter 0 */
00170   void* pfnTC1_Handler;    /* 24 Timer/Counter 1 */
00171   void* pfnTC2_Handler;    /* 25 Timer/Counter 2 */
00172   void* pvReserved26;
00173   void* pvReserved27;
00174   void* pvReserved28;
00175   void* pfnAFEC0_Handler;  /* 29 Analog Front End 0 */
00176   void* pfnDACC_Handler;   /* 30 Digital To Analog Converter */
00177   void* pfnPWM0_Handler;   /* 31 Pulse Width Modulation 0 */
00178   void* pfnICM_Handler;    /* 32 Integrity Check Monitor */
00179   void* pfnACC_Handler;    /* 33 Analog Comparator */
00180   void* pfnUSBHS_Handler;  /* 34 USB Host / Device Controller */
00181   void* pfnMCAN0_Handler;  /* 35 MCAN Controller 0 */
00182   void* pvReserved36;
00183   void* pfnMCAN1_Handler;  /* 37 MCAN Controller 1 */
00184   void* pvReserved38;
00185   void* pfnGMAC_Handler;   /* 39 Ethernet MAC */
00186   void* pfnAFEC1_Handler;  /* 40 Analog Front End 1 */
00187   void* pvReserved41;
00188   void* pfnSPI1_Handler;   /* 42 Serial Peripheral Interface 1 */
00189   void* pfnQSPI_Handler;   /* 43 Quad I/O Serial Peripheral Interface */
00190   void* pfnUART2_Handler;  /* 44 UART 2 */
00191   void* pfnUART3_Handler;  /* 45 UART 3 */
00192   void* pfnUART4_Handler;  /* 46 UART 4 */
00193   void* pvReserved47;
00194   void* pvReserved48;
00195   void* pvReserved49;
00196   void* pfnTC9_Handler;    /* 50 Timer/Counter 9 */
00197   void* pfnTC10_Handler;   /* 51 Timer/Counter 10 */
00198   void* pfnTC11_Handler;   /* 52 Timer/Counter 11 */
00199   void* pfnMLB_Handler;    /* 53 MediaLB */
00200   void* pvReserved54;
00201   void* pvReserved55;
00202   void* pfnAES_Handler;    /* 56 AES */
00203   void* pfnTRNG_Handler;   /* 57 True Random Generator */
00204   void* pfnXDMAC_Handler;  /* 58 DMA */
00205   void* pfnISI_Handler;    /* 59 Camera Interface */
00206   void* pfnPWM1_Handler;   /* 60 Pulse Width Modulation 1 */
00207   void* pvReserved61;
00208   void* pvReserved62;
00209   void* pfnRSWDT_Handler;  /* 63 Reinforced Secure Watchdog Timer */
00210 } DeviceVectors;
00211 
00212 /* Cortex-M7 core handlers */
00213 void Reset_Handler      ( void );
00214 void NMI_Handler        ( void );
00215 void HardFault_Handler  ( void );
00216 void MemManage_Handler  ( void );
00217 void BusFault_Handler   ( void );
00218 void UsageFault_Handler ( void );
00219 void SVC_Handler        ( void );
00220 void DebugMon_Handler   ( void );
00221 void PendSV_Handler     ( void );
00222 void SysTick_Handler    ( void );
00223 
00224 /* Peripherals handlers */
00225 void ACC_Handler        ( void );
00226 void AES_Handler        ( void );
00227 void AFEC0_Handler      ( void );
00228 void AFEC1_Handler      ( void );
00229 void DACC_Handler       ( void );
00230 void EFC_Handler        ( void );
00231 void GMAC_Handler       ( void );
00232 void HSMCI_Handler      ( void );
00233 void ICM_Handler        ( void );
00234 void ISI_Handler        ( void );
00235 void MCAN0_Handler      ( void );
00236 void MCAN1_Handler      ( void );
00237 void MLB_Handler        ( void );
00238 void PIOA_Handler       ( void );
00239 void PIOB_Handler       ( void );
00240 void PIOD_Handler       ( void );
00241 void PMC_Handler        ( void );
00242 void PWM0_Handler       ( void );
00243 void PWM1_Handler       ( void );
00244 void QSPI_Handler       ( void );
00245 void RSTC_Handler       ( void );
00246 void RSWDT_Handler      ( void );
00247 void RTC_Handler        ( void );
00248 void RTT_Handler        ( void );
00249 void SPI0_Handler       ( void );
00250 void SPI1_Handler       ( void );
00251 void SSC_Handler        ( void );
00252 void SUPC_Handler       ( void );
00253 void TC0_Handler        ( void );
00254 void TC1_Handler        ( void );
00255 void TC2_Handler        ( void );
00256 void TC9_Handler        ( void );
00257 void TC10_Handler       ( void );
00258 void TC11_Handler       ( void );
00259 void TRNG_Handler       ( void );
00260 void TWIHS0_Handler     ( void );
00261 void TWIHS1_Handler     ( void );
00262 void UART0_Handler      ( void );
00263 void UART1_Handler      ( void );
00264 void UART2_Handler      ( void );
00265 void UART3_Handler      ( void );
00266 void UART4_Handler      ( void );
00267 void USART0_Handler     ( void );
00268 void USART1_Handler     ( void );
00269 void USART2_Handler     ( void );
00270 void USBHS_Handler      ( void );
00271 void WDT_Handler        ( void );
00272 void XDMAC_Handler      ( void );
00273 
00274 /**
00275  * \brief Configuration of the Cortex-M7 Processor and Core Peripherals
00276  */
00277 
00278 #define __CM7_REV              0x0000 /**< SAMV71J20 core revision number ([15:8] revision number, [7:0] patch number) */
00279 #define __MPU_PRESENT          1      /**< SAMV71J20 does provide a MPU */
00280 #define __NVIC_PRIO_BITS       3      /**< SAMV71J20 uses 3 Bits for the Priority Levels */
00281 #define __FPU_PRESENT          1      /**< SAMV71J20 does provide a FPU                */
00282 #define __FPU_DP               1      /**< SAMV71J20 Double precision FPU              */
00283 #define __ICACHE_PRESENT       1      /**< SAMV71J20 does provide an Instruction Cache */
00284 #define __DCACHE_PRESENT       1      /**< SAMV71J20 does provide a Data Cache         */
00285 #define __DTCM_PRESENT         1      /**< SAMV71J20 does provide a Data TCM           */
00286 #define __ITCM_PRESENT         1      /**< SAMV71J20 does provide an Instruction TCM   */
00287 #define __Vendor_SysTickConfig 0      /**< Set to 1 if different SysTick Config is used */
00288 
00289 /*
00290  * \brief CMSIS includes
00291  */
00292 
00293 #include <core_cm7.h>
00294 #if !defined DONT_USE_CMSIS_INIT
00295 #include "system_samv71.h"
00296 #endif /* DONT_USE_CMSIS_INIT */
00297 
00298 /*@}*/
00299 
00300 /* ************************************************************************** */
00301 /**  SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J20 */
00302 /* ************************************************************************** */
00303 /** \addtogroup SAMV71J20_api Peripheral Software API */
00304 /*@{*/
00305 
00306 #include "component/component_acc.h"
00307 #include "component/component_aes.h"
00308 #include "component/component_afec.h"
00309 #include "component/component_chipid.h"
00310 #include "component/component_dacc.h"
00311 #include "component/component_efc.h"
00312 #include "component/component_gmac.h"
00313 #include "component/component_gpbr.h"
00314 #include "component/component_hsmci.h"
00315 #include "component/component_icm.h"
00316 #include "component/component_isi.h"
00317 #include "component/component_matrix.h"
00318 #include "component/component_mcan.h"
00319 #include "component/component_mlb.h"
00320 #include "component/component_pio.h"
00321 #include "component/component_pmc.h"
00322 #include "component/component_pwm.h"
00323 #include "component/component_qspi.h"
00324 #include "component/component_rstc.h"
00325 #include "component/component_rswdt.h"
00326 #include "component/component_rtc.h"
00327 #include "component/component_rtt.h"
00328 #include "component/component_spi.h"
00329 #include "component/component_ssc.h"
00330 #include "component/component_supc.h"
00331 #include "component/component_tc.h"
00332 #include "component/component_trng.h"
00333 #include "component/component_twihs.h"
00334 #include "component/component_uart.h"
00335 #include "component/component_usart.h"
00336 #include "component/component_usbhs.h"
00337 #include "component/component_utmi.h"
00338 #include "component/component_wdt.h"
00339 #include "component/component_xdmac.h"
00340 /*@}*/
00341 
00342 /* ************************************************************************** */
00343 /*   REGISTER ACCESS DEFINITIONS FOR SAMV71J20 */
00344 /* ************************************************************************** */
00345 /** \addtogroup SAMV71J20_reg Registers Access Definitions */
00346 /*@{*/
00347 
00348 #include "instance/instance_hsmci.h"
00349 #include "instance/instance_ssc.h"
00350 #include "instance/instance_spi0.h"
00351 #include "instance/instance_tc0.h"
00352 #include "instance/instance_twihs0.h"
00353 #include "instance/instance_twihs1.h"
00354 #include "instance/instance_pwm0.h"
00355 #include "instance/instance_usart0.h"
00356 #include "instance/instance_usart1.h"
00357 #include "instance/instance_usart2.h"
00358 #include "instance/instance_mcan0.h"
00359 #include "instance/instance_mcan1.h"
00360 #include "instance/instance_usbhs.h"
00361 #include "instance/instance_afec0.h"
00362 #include "instance/instance_dacc.h"
00363 #include "instance/instance_acc.h"
00364 #include "instance/instance_icm.h"
00365 #include "instance/instance_isi.h"
00366 #include "instance/instance_gmac.h"
00367 #include "instance/instance_tc3.h"
00368 #include "instance/instance_spi1.h"
00369 #include "instance/instance_pwm1.h"
00370 #include "instance/instance_afec1.h"
00371 #include "instance/instance_mlb.h"
00372 #include "instance/instance_aes.h"
00373 #include "instance/instance_trng.h"
00374 #include "instance/instance_xdmac.h"
00375 #include "instance/instance_qspi.h"
00376 #include "instance/instance_matrix.h"
00377 #include "instance/instance_utmi.h"
00378 #include "instance/instance_pmc.h"
00379 #include "instance/instance_uart0.h"
00380 #include "instance/instance_chipid.h"
00381 #include "instance/instance_uart1.h"
00382 #include "instance/instance_efc.h"
00383 #include "instance/instance_pioa.h"
00384 #include "instance/instance_piob.h"
00385 #include "instance/instance_piod.h"
00386 #include "instance/instance_rstc.h"
00387 #include "instance/instance_supc.h"
00388 #include "instance/instance_rtt.h"
00389 #include "instance/instance_wdt.h"
00390 #include "instance/instance_rtc.h"
00391 #include "instance/instance_gpbr.h"
00392 #include "instance/instance_rswdt.h"
00393 #include "instance/instance_uart2.h"
00394 #include "instance/instance_uart3.h"
00395 #include "instance/instance_uart4.h"
00396 /*@}*/
00397 
00398 /* ************************************************************************** */
00399 /*   PERIPHERAL ID DEFINITIONS FOR SAMV71J20 */
00400 /* ************************************************************************** */
00401 /** \addtogroup SAMV71J20_id Peripheral Ids Definitions */
00402 /*@{*/
00403 
00404 #define ID_SUPC   ( 0) /**< \brief Supply Controller (SUPC) */
00405 #define ID_RSTC   ( 1) /**< \brief Reset Controller (RSTC) */
00406 #define ID_RTC    ( 2) /**< \brief Real Time Clock (RTC) */
00407 #define ID_RTT    ( 3) /**< \brief Real Time Timer (RTT) */
00408 #define ID_WDT    ( 4) /**< \brief Watchdog Timer (WDT) */
00409 #define ID_PMC    ( 5) /**< \brief Power Management Controller (PMC) */
00410 #define ID_EFC    ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */
00411 #define ID_UART0  ( 7) /**< \brief UART 0 (UART0) */
00412 #define ID_UART1  ( 8) /**< \brief UART 1 (UART1) */
00413 #define ID_PIOA   (10) /**< \brief Parallel I/O Controller A (PIOA) */
00414 #define ID_PIOB   (11) /**< \brief Parallel I/O Controller B (PIOB) */
00415 #define ID_USART0 (13) /**< \brief USART 0 (USART0) */
00416 #define ID_USART1 (14) /**< \brief USART 1 (USART1) */
00417 #define ID_USART2 (15) /**< \brief USART 2 (USART2) */
00418 #define ID_PIOD   (16) /**< \brief Parallel I/O Controller D (PIOD) */
00419 #define ID_HSMCI  (18) /**< \brief Multimedia Card Interface (HSMCI) */
00420 #define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */
00421 #define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */
00422 #define ID_SPI0   (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */
00423 #define ID_SSC    (22) /**< \brief Synchronous Serial Controller (SSC) */
00424 #define ID_TC0    (23) /**< \brief Timer/Counter 0 (TC0) */
00425 #define ID_TC1    (24) /**< \brief Timer/Counter 1 (TC1) */
00426 #define ID_TC2    (25) /**< \brief Timer/Counter 2 (TC2) */
00427 #define ID_AFEC0  (29) /**< \brief Analog Front End 0 (AFEC0) */
00428 #define ID_DACC   (30) /**< \brief Digital To Analog Converter (DACC) */
00429 #define ID_PWM0   (31) /**< \brief Pulse Width Modulation 0 (PWM0) */
00430 #define ID_ICM    (32) /**< \brief Integrity Check Monitor (ICM) */
00431 #define ID_ACC    (33) /**< \brief Analog Comparator (ACC) */
00432 #define ID_USBHS  (34) /**< \brief USB Host / Device Controller (USBHS) */
00433 #define ID_MCAN0  (35) /**< \brief MCAN Controller 0 (MCAN0) */
00434 #define ID_MCAN1  (37) /**< \brief MCAN Controller 1 (MCAN1) */
00435 #define ID_GMAC   (39) /**< \brief Ethernet MAC (GMAC) */
00436 #define ID_AFEC1  (40) /**< \brief Analog Front End 1 (AFEC1) */
00437 #define ID_SPI1   (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */
00438 #define ID_QSPI   (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */
00439 #define ID_UART2  (44) /**< \brief UART 2 (UART2) */
00440 #define ID_UART3  (45) /**< \brief UART 3 (UART3) */
00441 #define ID_UART4  (46) /**< \brief UART 4 (UART4) */
00442 #define ID_TC9    (50) /**< \brief Timer/Counter 9 (TC9) */
00443 #define ID_TC10   (51) /**< \brief Timer/Counter 10 (TC10) */
00444 #define ID_TC11   (52) /**< \brief Timer/Counter 11 (TC11) */
00445 #define ID_MLB    (53) /**< \brief MediaLB (MLB) */
00446 #define ID_AES    (56) /**< \brief AES (AES) */
00447 #define ID_TRNG   (57) /**< \brief True Random Generator (TRNG) */
00448 #define ID_XDMAC  (58) /**< \brief DMA (XDMAC) */
00449 #define ID_ISI    (59) /**< \brief Camera Interface (ISI) */
00450 #define ID_PWM1   (60) /**< \brief Pulse Width Modulation 1 (PWM1) */
00451 #define ID_RSWDT  (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */
00452 
00453 #define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */
00454 /*@}*/
00455 
00456 /* ************************************************************************** */
00457 /*   BASE ADDRESS DEFINITIONS FOR SAMV71J20 */
00458 /* ************************************************************************** */
00459 /** \addtogroup SAMV71J20_base Peripheral Base Address Definitions */
00460 /*@{*/
00461 
00462 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00463 #define HSMCI  (0x40000000U) /**< \brief (HSMCI ) Base Address */
00464 #define SSC    (0x40004000U) /**< \brief (SSC   ) Base Address */
00465 #define SPI0   (0x40008000U) /**< \brief (SPI0  ) Base Address */
00466 #define TC0    (0x4000C000U) /**< \brief (TC0   ) Base Address */
00467 #define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */
00468 #define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */
00469 #define PWM0   (0x40020000U) /**< \brief (PWM0  ) Base Address */
00470 #define USART0 (0x40024000U) /**< \brief (USART0) Base Address */
00471 #define USART1 (0x40028000U) /**< \brief (USART1) Base Address */
00472 #define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */
00473 #define MCAN0  (0x40030000U) /**< \brief (MCAN0 ) Base Address */
00474 #define MCAN1  (0x40034000U) /**< \brief (MCAN1 ) Base Address */
00475 #define USBHS  (0x40038000U) /**< \brief (USBHS ) Base Address */
00476 #define AFEC0  (0x4003C000U) /**< \brief (AFEC0 ) Base Address */
00477 #define DACC   (0x40040000U) /**< \brief (DACC  ) Base Address */
00478 #define ACC    (0x40044000U) /**< \brief (ACC   ) Base Address */
00479 #define ICM    (0x40048000U) /**< \brief (ICM   ) Base Address */
00480 #define ISI    (0x4004C000U) /**< \brief (ISI   ) Base Address */
00481 #define GMAC   (0x40050000U) /**< \brief (GMAC  ) Base Address */
00482 #define TC3    (0x40054000U) /**< \brief (TC3   ) Base Address */
00483 #define SPI1   (0x40058000U) /**< \brief (SPI1  ) Base Address */
00484 #define PWM1   (0x4005C000U) /**< \brief (PWM1  ) Base Address */
00485 #define AFEC1  (0x40064000U) /**< \brief (AFEC1 ) Base Address */
00486 #define MLB    (0x40068000U) /**< \brief (MLB   ) Base Address */
00487 #define AES    (0x4006C000U) /**< \brief (AES   ) Base Address */
00488 #define TRNG   (0x40070000U) /**< \brief (TRNG  ) Base Address */
00489 #define XDMAC  (0x40078000U) /**< \brief (XDMAC ) Base Address */
00490 #define QSPI   (0x4007C000U) /**< \brief (QSPI  ) Base Address */
00491 #define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */
00492 #define UTMI   (0x400E0400U) /**< \brief (UTMI  ) Base Address */
00493 #define PMC    (0x400E0600U) /**< \brief (PMC   ) Base Address */
00494 #define UART0  (0x400E0800U) /**< \brief (UART0 ) Base Address */
00495 #define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */
00496 #define UART1  (0x400E0A00U) /**< \brief (UART1 ) Base Address */
00497 #define EFC    (0x400E0C00U) /**< \brief (EFC   ) Base Address */
00498 #define PIOA   (0x400E0E00U) /**< \brief (PIOA  ) Base Address */
00499 #define PIOB   (0x400E1000U) /**< \brief (PIOB  ) Base Address */
00500 #define PIOD   (0x400E1400U) /**< \brief (PIOD  ) Base Address */
00501 #define RSTC   (0x400E1800U) /**< \brief (RSTC  ) Base Address */
00502 #define SUPC   (0x400E1810U) /**< \brief (SUPC  ) Base Address */
00503 #define RTT    (0x400E1830U) /**< \brief (RTT   ) Base Address */
00504 #define WDT    (0x400E1850U) /**< \brief (WDT   ) Base Address */
00505 #define RTC    (0x400E1860U) /**< \brief (RTC   ) Base Address */
00506 #define GPBR   (0x400E1890U) /**< \brief (GPBR  ) Base Address */
00507 #define RSWDT  (0x400E1900U) /**< \brief (RSWDT ) Base Address */
00508 #define UART2  (0x400E1A00U) /**< \brief (UART2 ) Base Address */
00509 #define UART3  (0x400E1C00U) /**< \brief (UART3 ) Base Address */
00510 #define UART4  (0x400E1E00U) /**< \brief (UART4 ) Base Address */
00511 #else
00512 #define HSMCI  ((Hsmci  *)0x40000000U) /**< \brief (HSMCI ) Base Address */
00513 #define SSC    ((Ssc    *)0x40004000U) /**< \brief (SSC   ) Base Address */
00514 #define SPI0   ((Spi    *)0x40008000U) /**< \brief (SPI0  ) Base Address */
00515 #define TC0    ((Tc     *)0x4000C000U) /**< \brief (TC0   ) Base Address */
00516 #define TWIHS0 ((Twihs  *)0x40018000U) /**< \brief (TWIHS0) Base Address */
00517 #define TWIHS1 ((Twihs  *)0x4001C000U) /**< \brief (TWIHS1) Base Address */
00518 #define PWM0   ((Pwm    *)0x40020000U) /**< \brief (PWM0  ) Base Address */
00519 #define USART0 ((Usart  *)0x40024000U) /**< \brief (USART0) Base Address */
00520 #define USART1 ((Usart  *)0x40028000U) /**< \brief (USART1) Base Address */
00521 #define USART2 ((Usart  *)0x4002C000U) /**< \brief (USART2) Base Address */
00522 #define MCAN0  ((Mcan   *)0x40030000U) /**< \brief (MCAN0 ) Base Address */
00523 #define MCAN1  ((Mcan   *)0x40034000U) /**< \brief (MCAN1 ) Base Address */
00524 #define USBHS  ((Usbhs  *)0x40038000U) /**< \brief (USBHS ) Base Address */
00525 #define AFEC0  ((Afec   *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */
00526 #define DACC   ((Dacc   *)0x40040000U) /**< \brief (DACC  ) Base Address */
00527 #define ACC    ((Acc    *)0x40044000U) /**< \brief (ACC   ) Base Address */
00528 #define ICM    ((Icm    *)0x40048000U) /**< \brief (ICM   ) Base Address */
00529 #define ISI    ((Isi    *)0x4004C000U) /**< \brief (ISI   ) Base Address */
00530 #define GMAC   ((Gmac   *)0x40050000U) /**< \brief (GMAC  ) Base Address */
00531 #define TC3    ((Tc     *)0x40054000U) /**< \brief (TC3   ) Base Address */
00532 #define SPI1   ((Spi    *)0x40058000U) /**< \brief (SPI1  ) Base Address */
00533 #define PWM1   ((Pwm    *)0x4005C000U) /**< \brief (PWM1  ) Base Address */
00534 #define AFEC1  ((Afec   *)0x40064000U) /**< \brief (AFEC1 ) Base Address */
00535 #define MLB    ((Mlb    *)0x40068000U) /**< \brief (MLB   ) Base Address */
00536 #define AES    ((Aes    *)0x4006C000U) /**< \brief (AES   ) Base Address */
00537 #define TRNG   ((Trng   *)0x40070000U) /**< \brief (TRNG  ) Base Address */
00538 #define XDMAC  ((Xdmac  *)0x40078000U) /**< \brief (XDMAC ) Base Address */
00539 #define QSPI   ((Qspi   *)0x4007C000U) /**< \brief (QSPI  ) Base Address */
00540 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */
00541 #define UTMI   ((Utmi   *)0x400E0400U) /**< \brief (UTMI  ) Base Address */
00542 #define PMC    ((Pmc    *)0x400E0600U) /**< \brief (PMC   ) Base Address */
00543 #define UART0  ((Uart   *)0x400E0800U) /**< \brief (UART0 ) Base Address */
00544 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */
00545 #define UART1  ((Uart   *)0x400E0A00U) /**< \brief (UART1 ) Base Address */
00546 #define EFC    ((Efc    *)0x400E0C00U) /**< \brief (EFC   ) Base Address */
00547 #define PIOA   ((Pio    *)0x400E0E00U) /**< \brief (PIOA  ) Base Address */
00548 #define PIOB   ((Pio    *)0x400E1000U) /**< \brief (PIOB  ) Base Address */
00549 #define PIOD   ((Pio    *)0x400E1400U) /**< \brief (PIOD  ) Base Address */
00550 #define RSTC   ((Rstc   *)0x400E1800U) /**< \brief (RSTC  ) Base Address */
00551 #define SUPC   ((Supc   *)0x400E1810U) /**< \brief (SUPC  ) Base Address */
00552 #define RTT    ((Rtt    *)0x400E1830U) /**< \brief (RTT   ) Base Address */
00553 #define WDT    ((Wdt    *)0x400E1850U) /**< \brief (WDT   ) Base Address */
00554 #define RTC    ((Rtc    *)0x400E1860U) /**< \brief (RTC   ) Base Address */
00555 #define GPBR   ((Gpbr   *)0x400E1890U) /**< \brief (GPBR  ) Base Address */
00556 #define RSWDT  ((Rswdt  *)0x400E1900U) /**< \brief (RSWDT ) Base Address */
00557 #define UART2  ((Uart   *)0x400E1A00U) /**< \brief (UART2 ) Base Address */
00558 #define UART3  ((Uart   *)0x400E1C00U) /**< \brief (UART3 ) Base Address */
00559 #define UART4  ((Uart   *)0x400E1E00U) /**< \brief (UART4 ) Base Address */
00560 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00561 /*@}*/
00562 
00563 /* ************************************************************************** */
00564 /*   PIO DEFINITIONS FOR SAMV71J20 */
00565 /* ************************************************************************** */
00566 /** \addtogroup SAMV71J20_pio Peripheral Pio Definitions */
00567 /*@{*/
00568 
00569 #include "pio/pio_samv71j20.h"
00570 /*@}*/
00571 
00572 /* ************************************************************************** */
00573 /*   MEMORY MAPPING DEFINITIONS FOR SAMV71J20 */
00574 /* ************************************************************************** */
00575 
00576 #define IFLASH_SIZE             (0x100000u)
00577 #define IFLASH_PAGE_SIZE        (512u)
00578 #define IFLASH_LOCK_REGION_SIZE (8192u)
00579 #define IFLASH_NB_OF_PAGES      (2048u)
00580 #define IFLASH_NB_OF_LOCK_BITS  (64u)
00581 #define IRAM_SIZE               (0x60000u)
00582 
00583 #define QSPIMEM_ADDR  (0x80000000u) /**< QSPI Memory base address */
00584 #define AXIMX_ADDR    (0xA0000000u) /**< AXI Bus Matrix base address */
00585 #define ITCM_ADDR     (0x00000000u) /**< Instruction Tightly Coupled Memory base address */
00586 #define IFLASH_ADDR   (0x00400000u) /**< Internal Flash base address */
00587 #define IROM_ADDR     (0x00800000u) /**< Internal ROM base address */
00588 #define DTCM_ADDR     (0x20000000u) /**< Data Tightly Coupled Memory base address */
00589 #define IRAM_ADDR     (0x20400000u) /**< Internal RAM base address */
00590 #define EBI_CS0_ADDR  (0x60000000u) /**< EBI Chip Select 0 base address */
00591 #define EBI_CS1_ADDR  (0x61000000u) /**< EBI Chip Select 1 base address */
00592 #define EBI_CS2_ADDR  (0x62000000u) /**< EBI Chip Select 2 base address */
00593 #define EBI_CS3_ADDR  (0x63000000u) /**< EBI Chip Select 3 base address */
00594 #define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */
00595 
00596 /* ************************************************************************** */
00597 /*   MISCELLANEOUS DEFINITIONS FOR SAMV71J20 */
00598 /* ************************************************************************** */
00599 
00600 #define CHIP_JTAGID (0x05B3D03FUL)
00601 #define CHIP_CIDR   (0xA1220C00UL)
00602 #define CHIP_EXID   (0x00000000UL)
00603 
00604 /* ************************************************************************** */
00605 /*   ELECTRICAL DEFINITIONS FOR SAMV71J20 */
00606 /* ************************************************************************** */
00607 
00608 /* %ATMEL_ELECTRICAL% */
00609 
00610 /* Device characteristics */
00611 #define CHIP_FREQ_SLCK_RC_MIN           (20000UL)
00612 #define CHIP_FREQ_SLCK_RC               (32000UL)
00613 #define CHIP_FREQ_SLCK_RC_MAX           (44000UL)
00614 #define CHIP_FREQ_MAINCK_RC_4MHZ        (4000000UL)
00615 #define CHIP_FREQ_MAINCK_RC_8MHZ        (8000000UL)
00616 #define CHIP_FREQ_MAINCK_RC_12MHZ       (12000000UL)
00617 #define CHIP_FREQ_CPU_MAX               (120000000UL)
00618 #define CHIP_FREQ_XTAL_32K              (32768UL)
00619 #define CHIP_FREQ_XTAL_12M              (12000000UL)
00620 
00621 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */
00622 #define CHIP_FREQ_FWS_0                 (20000000UL)  /**< \brief Maximum operating frequency when FWS is 0 */
00623 #define CHIP_FREQ_FWS_1                 (40000000UL)  /**< \brief Maximum operating frequency when FWS is 1 */
00624 #define CHIP_FREQ_FWS_2                 (60000000UL)  /**< \brief Maximum operating frequency when FWS is 2 */
00625 #define CHIP_FREQ_FWS_3                 (80000000UL)  /**< \brief Maximum operating frequency when FWS is 3 */
00626 #define CHIP_FREQ_FWS_4                 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */
00627 #define CHIP_FREQ_FWS_5                 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */
00628 
00629 #ifdef __cplusplus
00630 }
00631 #endif
00632 
00633 /*@}*/
00634 
00635 #endif /* _SAMV71J20_ */
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