SAMV71 Xplained Ultra Software Package 1.5

gmac.c

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00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2015, Atmel Corporation                                        */
00006 /*                                                                              */
00007 /* All rights reserved.                                                         */
00008 /*                                                                              */
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00010 /* modification, are permitted provided that the following condition is met:    */
00011 /*                                                                              */
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00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
00015 /* Atmel's name may not be used to endorse or promote products derived from     */
00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
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00028 /* ---------------------------------------------------------------------------- */
00029 
00030 /** \file */
00031 
00032 /*----------------------------------------------------------------------------
00033  *        Headers
00034  *----------------------------------------------------------------------------*/
00035 
00036 #include "chip.h"
00037 #include <stdio.h>
00038 #include <string.h>
00039 #include <assert.h>
00040 
00041 
00042 
00043 /*----------------------------------------------------------------------------
00044  *        Internal functions
00045  *----------------------------------------------------------------------------*/
00046 /*----------------------------------------------------------------------------
00047  *        Exported functions
00048  *----------------------------------------------------------------------------*/
00049 
00050 /**
00051  * Return 1 if PHY is idle
00052  */
00053 uint8_t GMAC_IsIdle(Gmac *pGmac)
00054 {
00055     return ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) > 0);
00056 }
00057 
00058 
00059 /**
00060  * Execute PHY maintenance command
00061  */
00062 void GMAC_PHYMaintain(Gmac      *pGmac,
00063                       uint8_t   bPhyAddr,
00064                       uint8_t   bRegAddr,
00065                       uint8_t   bRW,
00066                       uint16_t  wData)
00067 {
00068     /* Wait until bus idle */
00069     while ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);
00070 
00071     /* Write maintain register */
00072     pGmac->GMAC_MAN = (~GMAC_MAN_WZO & GMAC_MAN_CLTTO)
00073                       | (GMAC_MAN_OP(bRW ? 0x2 : 0x1))
00074                       | GMAC_MAN_WTN(0x02)
00075                       | GMAC_MAN_PHYA(bPhyAddr)
00076                       | GMAC_MAN_REGA(bRegAddr)
00077                       | GMAC_MAN_DATA(wData);
00078 }
00079 
00080 /**
00081  * Return PHY maintenance data returned
00082  */
00083 uint16_t GMAC_PHYData(Gmac *pGmac)
00084 {
00085     /* Wait until bus idle */
00086     while ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);
00087 
00088     /* Return data */
00089     return (uint16_t)(pGmac->GMAC_MAN & GMAC_MAN_DATA_Msk);
00090 }
00091 
00092 /**
00093  *  \brief Set MDC clock according to current board clock. Per 802.3, MDC should
00094  *  be less then 2.5MHz.
00095  *  \param pGmac Pointer to an Gmac instance.
00096  *  \param mck Mdc clock
00097  *  \return 1 if successfully, 0 if MDC clock not found.
00098  */
00099 uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck)
00100 {
00101     uint32_t clock_dividor;
00102     pGmac->GMAC_NCR &=  ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00103 
00104     if (mck <= 20000000) {
00105         clock_dividor = GMAC_NCFGR_CLK_MCK_8;          // MDC clock = MCK/8
00106     } else if (mck <= 40000000) {
00107         clock_dividor = GMAC_NCFGR_CLK_MCK_16;         // MDC clock = MCK/16
00108     } else if (mck <= 80000000) {
00109         clock_dividor = GMAC_NCFGR_CLK_MCK_32;         // MDC clock = MCK/32
00110     } else if (mck <= 160000000) {
00111         clock_dividor = GMAC_NCFGR_CLK_MCK_64;         // MDC clock = MCK/64
00112     } else if (mck <= 240000000) {
00113         clock_dividor = GMAC_NCFGR_CLK_MCK_96;         // MDC clock = MCK/96
00114     } else {
00115         TRACE_ERROR("E: No valid MDC clock.\n\r");
00116         return 0;
00117     }
00118 
00119     pGmac->GMAC_NCFGR = (pGmac->GMAC_NCFGR & (~GMAC_NCFGR_CLK_Msk)) | clock_dividor;
00120     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00121     return 1;
00122 }
00123 
00124 /**
00125  *  \brief Enable MDI with PHY
00126  *  \param pGmac Pointer to an Gmac instance.
00127  */
00128 void GMAC_EnableMdio(Gmac *pGmac)
00129 {
00130     pGmac->GMAC_NCR &=  ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00131     pGmac->GMAC_NCR |= GMAC_NCR_MPE;
00132     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00133 }
00134 
00135 /**
00136  *  \brief Enable MDI with PHY
00137  *  \param pGmac Pointer to an Gmac instance.
00138  */
00139 void GMAC_DisableMdio(Gmac *pGmac)
00140 {
00141     pGmac->GMAC_NCR &=  ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00142     pGmac->GMAC_NCR &= ~GMAC_NCR_MPE;
00143     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00144 }
00145 
00146 /**
00147  *  \brief Enable MII mode for GMAC, called once after auto negotiate
00148  *  \param pGmac Pointer to an Gmac instance.
00149  */
00150 void GMAC_EnableMII(Gmac *pGmac)
00151 {
00152     pGmac->GMAC_NCR &=  ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00153     pGmac->GMAC_UR &= ~GMAC_UR_RMII;
00154     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00155 }
00156 
00157 /**
00158  *  \brief Enable GMII mode for GMAC, called once after auto negotiate
00159  *  \param pGmac Pointer to an Gmac instance.
00160  */
00161 void GMAC_EnableGMII(Gmac *pGmac)
00162 {
00163     pGmac->GMAC_NCR &=  ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00164     /* RGMII disable */
00165     pGmac->GMAC_UR &= ~GMAC_UR_RMII;
00166     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00167 }
00168 
00169 #define GMAC_NCFGR_GBE (0x1u << 10)
00170 /**
00171  *  \brief Enable RGMII mode for GMAC, called once after auto negotiate
00172  *  \param pGmac Pointer to an Gmac instance.
00173  *  \param duplex: 1 full duplex 0 half duplex
00174  *  \param speed:   0 10M 1 100M
00175  */
00176 void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed)
00177 {
00178     pGmac->GMAC_NCR &=  ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00179 
00180     if (duplex == GMAC_DUPLEX_HALF)
00181         pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD;
00182     else
00183         pGmac->GMAC_NCFGR |= GMAC_NCFGR_FD;
00184 
00185 
00186     if (speed == GMAC_SPEED_10M)
00187         pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD;
00188     else if (speed == GMAC_SPEED_100M)
00189         pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;
00190     else
00191         pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;
00192 
00193     /* RGMII enable */
00194     pGmac->GMAC_UR = 0;
00195     pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE;
00196     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00197     return;
00198 }
00199 
00200 /**
00201  *  \brief Setup the GMAC for the link : speed 100M/10M and Full/Half duplex
00202  *  \param pGmac Pointer to an Gmac instance.
00203  *  \param speed        Link speed, 0 for 10M, 1 for 100M
00204  *  \param fullduplex   1 for Full Duplex mode
00205  */
00206 void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex)
00207 {
00208     uint32_t ncfgr;
00209     ncfgr = pGmac->GMAC_NCFGR;
00210     ncfgr &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD);
00211 
00212     if (speed)
00213         ncfgr |= GMAC_NCFGR_SPD;
00214 
00215     if (fullduplex)
00216         ncfgr |= GMAC_NCFGR_FD;
00217 
00218     pGmac->GMAC_NCFGR = ncfgr;
00219     pGmac->GMAC_NCR |=  (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00220 }
00221 
00222 /**
00223  *  \brief set local loop back
00224  *  \param pGmac Pointer to an Gmac instance.
00225  */
00226 uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac)
00227 {
00228     pGmac->GMAC_NCR |= GMAC_NCR_LBL;
00229     return 0;
00230 }
00231 
00232 /**
00233  * Return interrupt mask.
00234  */
00235 uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx)
00236 {
00237     if (!queueIdx)
00238         return pGmac->GMAC_IMR;
00239     else
00240         return pGmac->GMAC_IMRPQ[queueIdx - 1];
00241 }
00242 
00243 
00244 /**
00245  * Return transmit status
00246  */
00247 uint32_t GMAC_GetTxStatus(Gmac *pGmac)
00248 {
00249     return pGmac->GMAC_TSR;
00250 }
00251 
00252 /**
00253  * Clear transmit status
00254  */
00255 void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus)
00256 {
00257     pGmac->GMAC_TSR = dwStatus;
00258 }
00259 
00260 /**
00261  * Return receive status
00262  */
00263 uint32_t GMAC_GetRxStatus(Gmac *pGmac)
00264 {
00265     return pGmac->GMAC_RSR;
00266 }
00267 
00268 /**
00269  * Clear receive status
00270  */
00271 void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus)
00272 {
00273     pGmac->GMAC_RSR = dwStatus;
00274 }
00275 
00276 
00277 /**
00278  * Enable/Disable GMAC receive.
00279  */
00280 void GMAC_ReceiveEnable(Gmac *pGmac, uint8_t bEnaDis)
00281 {
00282     if (bEnaDis) pGmac->GMAC_NCR |=  GMAC_NCR_RXEN;
00283     else         pGmac->GMAC_NCR &= ~GMAC_NCR_RXEN;
00284 }
00285 
00286 /**
00287  * Enable/Disable GMAC transmit.
00288  */
00289 void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis)
00290 {
00291     if (bEnaDis) pGmac->GMAC_NCR |=  GMAC_NCR_TXEN;
00292     else         pGmac->GMAC_NCR &= ~GMAC_NCR_TXEN;
00293 }
00294 
00295 
00296 /**
00297  * Set Rx Queue
00298  */
00299 void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx)
00300 {
00301     if (!queueIdx)
00302         pGmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & dwAddr;
00303     else
00304         pGmac->GMAC_RBQBAPQ[queueIdx - 1] = GMAC_RBQB_ADDR_Msk & dwAddr;
00305 }
00306 
00307 /**
00308  * Get Rx Queue Address
00309  */
00310 uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx)
00311 {
00312     if (!queueIdx)
00313         return pGmac->GMAC_RBQB;
00314     else
00315         return pGmac->GMAC_RBQBAPQ[queueIdx - 1];
00316 }
00317 
00318 /**
00319  * Set Tx Queue
00320  */
00321 void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx)
00322 {
00323     if (!queueIdx)
00324         pGmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & dwAddr;
00325     else
00326         pGmac->GMAC_TBQBAPQ[queueIdx - 1] = GMAC_TBQB_ADDR_Msk & dwAddr;
00327 }
00328 
00329 /**
00330  * Get Tx Queue
00331  */
00332 uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx)
00333 {
00334     if (!queueIdx)
00335         return pGmac->GMAC_TBQB;
00336     else
00337         return pGmac->GMAC_TBQBAPQ[queueIdx - 1];
00338 }
00339 
00340 
00341 /**
00342  * Write control value
00343  */
00344 void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR)
00345 {
00346     pGmac->GMAC_NCR = bmNCR;
00347 }
00348 
00349 
00350 /**
00351  * Get control value
00352  */
00353 uint32_t GMAC_GetNetworkControl(Gmac *pGmac)
00354 {
00355     return pGmac->GMAC_NCR;
00356 }
00357 
00358 /**
00359  * Enable interrupt(s).
00360  */
00361 void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx)
00362 {
00363     if (!queueIdx)
00364         pGmac->GMAC_IER = dwSources;
00365     else
00366         pGmac->GMAC_IERPQ[queueIdx - 1] = dwSources;
00367 }
00368 
00369 /**
00370  * Disable interrupt(s).
00371  */
00372 void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources)
00373 {
00374     pGmac->GMAC_IDR = dwSources;
00375     pGmac->GMAC_IDRPQ[0] = dwSources;
00376     pGmac->GMAC_IDRPQ[1] = dwSources;
00377 }
00378 
00379 /**
00380  * Disable interrupt(s).
00381  */
00382 void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources)
00383 {
00384     pGmac->GMAC_IER = dwSources;
00385     pGmac->GMAC_IERPQ[0] = dwSources;
00386     pGmac->GMAC_IERPQ[1] = dwSources;
00387 }
00388 
00389 /**
00390  * Disable interrupt(s).
00391  */
00392 void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx)
00393 {
00394     if (!queueIdx)
00395         pGmac->GMAC_IDR = dwSources;
00396     else
00397         pGmac->GMAC_IDRPQ[queueIdx - 1] = dwSources;
00398 }
00399 
00400 /**
00401  * Return interrupt status.
00402  */
00403 uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx)
00404 {
00405     if (!queueIdx)
00406         return pGmac->GMAC_ISR;
00407     else
00408         return pGmac->GMAC_ISRPQ[queueIdx - 1];
00409 }
00410 
00411 
00412 /**
00413  * Set MAC Address
00414  */
00415 void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr)
00416 {
00417     pGmac->GMAC_SA[bIndex].GMAC_SAB = (pMacAddr[3] << 24)
00418                                       | (pMacAddr[2] << 16)
00419                                       | (pMacAddr[1] <<  8)
00420                                       | (pMacAddr[0])
00421                                      ;
00422     pGmac->GMAC_SA[bIndex].GMAC_SAT = (pMacAddr[5] <<  8)
00423                                       | (pMacAddr[4])
00424                                      ;
00425 }
00426 
00427 /**
00428  * Set MAC Address via 2 DW
00429  */
00430 void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT,
00431                        uint32_t dwMacB)
00432 {
00433     pGmac->GMAC_SA[bIndex].GMAC_SAB = dwMacB;
00434     pGmac->GMAC_SA[bIndex].GMAC_SAT = dwMacT;
00435 }
00436 
00437 /**
00438  * Set MAC Address via int64
00439  */
00440 void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac)
00441 {
00442     pGmac->GMAC_SA[bIndex].GMAC_SAB = (uint32_t)ddwMac;
00443     pGmac->GMAC_SA[bIndex].GMAC_SAT = (uint32_t)(ddwMac > 32);
00444 }
00445 
00446 
00447 /**
00448  * Clear all statistics registers
00449  */
00450 void GMAC_ClearStatistics(Gmac *pGmac)
00451 {
00452     pGmac->GMAC_NCR |=  GMAC_NCR_CLRSTAT;
00453 }
00454 
00455 /**
00456  * Increase all statistics registers
00457  */
00458 void GMAC_IncreaseStatistics(Gmac *pGmac)
00459 {
00460     pGmac->GMAC_NCR |=  GMAC_NCR_INCSTAT;
00461 }
00462 
00463 /**
00464  * Enable/Disable statistics registers writing.
00465  */
00466 void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis)
00467 {
00468     if (bEnaDis) pGmac->GMAC_NCR |=  GMAC_NCR_WESTAT;
00469     else         pGmac->GMAC_NCR &= ~GMAC_NCR_WESTAT;
00470 }
00471 
00472 
00473 /**
00474  * Setup network configuration register
00475  */
00476 void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg)
00477 {
00478     pGmac->GMAC_NCFGR = dwCfg;
00479 }
00480 
00481 
00482 /**
00483  * Setup DMA configuration register
00484  */
00485 void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx)
00486 {
00487     if (!queueIdx)
00488         pGmac->GMAC_DCFGR = dwDmaCfg;
00489     else
00490         pGmac->GMAC_RBSRPQ[queueIdx - 1] = dwDmaCfg;
00491 }
00492 
00493 /**
00494  * Return DMA configuration register
00495  */
00496 uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx)
00497 {
00498     if (!queueIdx)
00499         return pGmac->GMAC_DCFGR;
00500     else
00501         return pGmac->GMAC_RBSRPQ[queueIdx - 1];;
00502 }
00503 
00504 /**
00505  * Return network configuration.
00506  */
00507 uint32_t GMAC_GetConfigure(Gmac *pGmac)
00508 {
00509     return pGmac->GMAC_NCFGR;
00510 }
00511 
00512 
00513 /**
00514  * Start transmission
00515  */
00516 void GMAC_TransmissionStart(Gmac *pGmac)
00517 {
00518     pGmac->GMAC_NCR |= GMAC_NCR_TSTART;
00519 }
00520 
00521 /**
00522  * Halt transmission
00523  */
00524 void GMAC_TransmissionHalt(Gmac *pGmac)
00525 {
00526     pGmac->GMAC_NCR |= GMAC_NCR_THALT;
00527 }
00528 
00529 
00530 /* Screener Register configurations */
00531 void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx)
00532 {
00533     pGmac->GMAC_ST1RPQ[queueIdx] = 0u;
00534 }
00535 
00536 void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx,
00537                             uint32_t regVal)
00538 {
00539     pGmac->GMAC_ST1RPQ[queueIdx] = regVal;
00540 }
00541 
00542 void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx)
00543 {
00544     pGmac->GMAC_ST2RPQ[queueIdx] = 0u;
00545 }
00546 
00547 void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx,
00548                              uint32_t regVal)
00549 {
00550     pGmac->GMAC_ST2RPQ[queueIdx] = regVal;
00551 }
00552 
00553 void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx,
00554                            uint16_t etherType)
00555 {
00556     pGmac->GMAC_ST2ER[queueIdx] = (uint32_t)etherType;
00557 }
00558 
00559 void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg,
00560                           uint16_t c1Reg)
00561 {
00562     pGmac->GMAC_ST2COMP[queueIdx].GMAC_ST2COM0 = c0Reg;
00563     pGmac->GMAC_ST2COMP[queueIdx].GMAC_ST2COM1 = (uint32_t)c1Reg;
00564     memory_barrier();
00565 }
00566 
00567 /* CBS queue control APIs */
00568 void GMAC_EnableCbsQueA(Gmac *pGmac)
00569 {
00570     pGmac->GMAC_CBSCR |= GMAC_CBSCR_QAE;
00571 }
00572 
00573 void GMAC_DisableCbsQueA(Gmac *pGmac)
00574 {
00575     pGmac->GMAC_CBSCR &= ~GMAC_CBSCR_QAE;
00576 }
00577 
00578 void GMAC_EnableCbsQueB(Gmac *pGmac)
00579 {
00580     pGmac->GMAC_CBSCR |= GMAC_CBSCR_QBE;
00581 }
00582 
00583 void GMAC_DisableCbsQueB(Gmac *pGmac)
00584 {
00585     pGmac->GMAC_CBSCR &= ~GMAC_CBSCR_QBE;
00586 }
00587 
00588 
00589 void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA)
00590 {
00591     /* 10/100 speeds use a 4-bit interface */
00592     pGmac->GMAC_CBSISQA = idleSlopeA > 2u;
00593 }
00594 
00595 void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB)
00596 {
00597     /* 10/100 speeds use a 4-bit interface */
00598     pGmac->GMAC_CBSISQB = idleSlopeB > 2u;
00599 }
00600 
00601 void GMAC_SetTsuTmrIncReg(Gmac *pGmac, uint32_t nanoSec)
00602 {
00603     pGmac->GMAC_TI = nanoSec;
00604 }
00605 
00606 uint16_t GMAC_GetPtpEvtMsgRxdMsbSec(Gmac *pGmac)
00607 {
00608     return (uint16_t)(pGmac->GMAC_EFRSH & GMAC_EFRSH_RUD_Msk);
00609 }
00610 
00611 uint32_t GMAC_GetPtpEvtMsgRxdLsbSec(Gmac *pGmac)
00612 {
00613     return (pGmac->GMAC_EFRSL & GMAC_EFRSL_RUD_Msk);
00614 }
00615 
00616 uint32_t GMAC_GetPtpEvtMsgRxdNanoSec(Gmac *pGmac)
00617 {
00618     return (pGmac->GMAC_EFRN & GMAC_EFRN_RUD_Msk);
00619 }
00620 
00621 void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31,
00622                         uint32_t nanosec)
00623 {
00624     pGmac->GMAC_SCH = seconds47;
00625     pGmac->GMAC_SCL = seconds31;
00626     pGmac->GMAC_NSC = nanosec;
00627     memory_barrier();
00628 }
00629 
00630 
00631 void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec)
00632 {
00633     pGmac->GMAC_NSC = nanosec;
00634 }
00635 
00636 void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31)
00637 {
00638     pGmac->GMAC_SCL = seconds31;
00639 }
00640 
00641 void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47)
00642 {
00643     pGmac->GMAC_SCH = seconds47;
00644 }
00645 
00646 
00647 uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac)
00648 {
00649     return pGmac->GMAC_EFRSL;
00650 }
00651 
00652 uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac)
00653 {
00654     return pGmac->GMAC_EFRN;
00655 }
00656 
00657 uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac)
00658 {
00659     return pGmac->GMAC_PEFRSL;
00660 }
00661 
00662 uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac)
00663 {
00664     return pGmac->GMAC_PEFRN;
00665 }
00666 
00667 uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac)
00668 {
00669     return pGmac->GMAC_EFTSL;
00670 }
00671 
00672 uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac)
00673 {
00674     return pGmac->GMAC_EFTN;
00675 }
00676 
00677 uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac)
00678 {
00679     return pGmac->GMAC_PEFTSL;
00680 }
00681 
00682 uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac)
00683 {
00684     return pGmac->GMAC_PEFTN;
00685 }
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