00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_TC_COMPONENT_ 00031 #define _SAMV71_TC_COMPONENT_ 00032 00033 /* ============================================================================= */ 00034 /** SOFTWARE API DEFINITION FOR Timer Counter */ 00035 /* ============================================================================= */ 00036 /** \addtogroup SAMV71_TC Timer Counter */ 00037 /*@{*/ 00038 00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00040 /** \brief TcChannel hardware registers */ 00041 typedef struct { 00042 __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ 00043 __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ 00044 __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ 00045 __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ 00046 __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ 00047 __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ 00048 __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ 00049 __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ 00050 __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ 00051 __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ 00052 __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ 00053 __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ 00054 __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ 00055 __I uint32_t Reserved1[3]; 00056 } TcChannel; 00057 /** \brief Tc hardware registers */ 00058 #define TCCHANNEL_NUMBER 3 00059 typedef struct { 00060 TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ 00061 __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ 00062 __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ 00063 __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ 00064 __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ 00065 __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ 00066 __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ 00067 __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ 00068 __I uint32_t Reserved1[2]; 00069 __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ 00070 __I uint32_t Reserved2[5]; 00071 __I uint32_t TC_VER; /**< \brief (Tc Offset: 0xFC) Version Register */ 00072 } Tc; 00073 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00074 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ 00075 #define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ 00076 #define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ 00077 #define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ 00078 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ 00079 #define TC_CMR_TCCLKS_Pos 0 00080 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ 00081 #define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) 00082 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ 00083 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ 00084 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ 00085 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ 00086 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ 00087 #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ 00088 #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ 00089 #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ 00090 #define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ 00091 #define TC_CMR_BURST_Pos 4 00092 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ 00093 #define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) 00094 #define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ 00095 #define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ 00096 #define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ 00097 #define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ 00098 #define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ 00099 #define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ 00100 #define TC_CMR_ETRGEDG_Pos 8 00101 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ 00102 #define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) 00103 #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ 00104 #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ 00105 #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ 00106 #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ 00107 #define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ 00108 #define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ 00109 #define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ 00110 #define TC_CMR_LDRA_Pos 16 00111 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ 00112 #define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) 00113 #define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ 00114 #define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ 00115 #define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ 00116 #define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ 00117 #define TC_CMR_LDRB_Pos 18 00118 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ 00119 #define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) 00120 #define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ 00121 #define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ 00122 #define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ 00123 #define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ 00124 #define TC_CMR_SBSMPLR_Pos 20 00125 #define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ 00126 #define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) 00127 #define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ 00128 #define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ 00129 #define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ 00130 #define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ 00131 #define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ 00132 #define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ 00133 #define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ 00134 #define TC_CMR_EEVTEDG_Pos 8 00135 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ 00136 #define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) 00137 #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ 00138 #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ 00139 #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ 00140 #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ 00141 #define TC_CMR_EEVT_Pos 10 00142 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ 00143 #define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) 00144 #define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ 00145 #define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ 00146 #define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ 00147 #define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ 00148 #define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ 00149 #define TC_CMR_WAVSEL_Pos 13 00150 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ 00151 #define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) 00152 #define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ 00153 #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ 00154 #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ 00155 #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ 00156 #define TC_CMR_ACPA_Pos 16 00157 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ 00158 #define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) 00159 #define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ 00160 #define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ 00161 #define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ 00162 #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ 00163 #define TC_CMR_ACPC_Pos 18 00164 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ 00165 #define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) 00166 #define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ 00167 #define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ 00168 #define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ 00169 #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ 00170 #define TC_CMR_AEEVT_Pos 20 00171 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ 00172 #define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) 00173 #define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ 00174 #define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ 00175 #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ 00176 #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ 00177 #define TC_CMR_ASWTRG_Pos 22 00178 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ 00179 #define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) 00180 #define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ 00181 #define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ 00182 #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ 00183 #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ 00184 #define TC_CMR_BCPB_Pos 24 00185 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ 00186 #define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) 00187 #define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ 00188 #define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ 00189 #define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ 00190 #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ 00191 #define TC_CMR_BCPC_Pos 26 00192 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ 00193 #define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) 00194 #define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ 00195 #define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ 00196 #define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ 00197 #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ 00198 #define TC_CMR_BEEVT_Pos 28 00199 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ 00200 #define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) 00201 #define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ 00202 #define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ 00203 #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ 00204 #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ 00205 #define TC_CMR_BSWTRG_Pos 30 00206 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ 00207 #define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) 00208 #define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ 00209 #define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ 00210 #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ 00211 #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ 00212 /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ 00213 #define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ 00214 #define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ 00215 /* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ 00216 #define TC_RAB_RAB_Pos 0 00217 #define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ 00218 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ 00219 #define TC_CV_CV_Pos 0 00220 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ 00221 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */ 00222 #define TC_RA_RA_Pos 0 00223 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ 00224 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) 00225 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */ 00226 #define TC_RB_RB_Pos 0 00227 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ 00228 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) 00229 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */ 00230 #define TC_RC_RC_Pos 0 00231 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ 00232 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) 00233 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ 00234 #define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ 00235 #define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ 00236 #define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ 00237 #define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ 00238 #define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ 00239 #define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ 00240 #define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ 00241 #define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ 00242 #define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ 00243 #define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ 00244 #define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ 00245 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ 00246 #define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ 00247 #define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ 00248 #define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ 00249 #define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ 00250 #define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ 00251 #define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ 00252 #define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ 00253 #define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ 00254 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ 00255 #define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ 00256 #define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ 00257 #define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ 00258 #define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ 00259 #define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ 00260 #define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ 00261 #define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ 00262 #define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ 00263 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ 00264 #define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ 00265 #define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ 00266 #define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ 00267 #define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ 00268 #define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ 00269 #define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ 00270 #define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ 00271 #define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ 00272 /* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ 00273 #define TC_EMR_TRIGSRCA_Pos 0 00274 #define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ 00275 #define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) 00276 #define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ 00277 #define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ 00278 #define TC_EMR_TRIGSRCB_Pos 4 00279 #define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ 00280 #define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) 00281 #define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ 00282 #define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). */ 00283 #define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ 00284 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ 00285 #define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ 00286 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ 00287 #define TC_BMR_TC0XC0S_Pos 0 00288 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ 00289 #define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) 00290 #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ 00291 #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ 00292 #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ 00293 #define TC_BMR_TC1XC1S_Pos 2 00294 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ 00295 #define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) 00296 #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ 00297 #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ 00298 #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ 00299 #define TC_BMR_TC2XC2S_Pos 4 00300 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ 00301 #define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) 00302 #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ 00303 #define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ 00304 #define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ 00305 #define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ 00306 #define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ 00307 #define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ 00308 #define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ 00309 #define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ 00310 #define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ 00311 #define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ 00312 #define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ 00313 #define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ 00314 #define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ 00315 #define TC_BMR_MAXFILT_Pos 20 00316 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ 00317 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) 00318 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ 00319 #define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ 00320 #define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ 00321 #define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ 00322 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ 00323 #define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ 00324 #define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ 00325 #define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ 00326 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ 00327 #define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ 00328 #define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ 00329 #define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ 00330 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ 00331 #define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ 00332 #define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ 00333 #define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ 00334 #define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ 00335 /* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ 00336 #define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ 00337 #define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ 00338 /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ 00339 #define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ 00340 #define TC_WPMR_WPKEY_Pos 8 00341 #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ 00342 #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) 00343 #define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 00344 /* -------- TC_VER : (TC Offset: 0xFC) Version Register -------- */ 00345 #define TC_VER_VERSION_Pos 0 00346 #define TC_VER_VERSION_Msk (0xfffu << TC_VER_VERSION_Pos) /**< \brief (TC_VER) Version of the Hardware Module */ 00347 #define TC_VER_MFN_Pos 16 00348 #define TC_VER_MFN_Msk (0x7u << TC_VER_MFN_Pos) /**< \brief (TC_VER) Metal Fix Number */ 00349 00350 /*@}*/ 00351 00352 00353 #endif /* _SAMV71_TC_COMPONENT_ */