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00059 #include "chip.h"
00060
00061
00062
00063
00064
00065
00066 #define USE_SPI_DMA
00067
00068
00069 #define DMA_SPI_LLI 2
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081 static uint32_t spiDmaTxChannel;
00082 static uint32_t spiDmaRxChannel;
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094 static void SPID_Rx_Cb(uint32_t channel, Spid *pArg)
00095 {
00096 SpidCmd *pSpidCmd = pArg->pCurrentCommand;
00097 Spi *pSpiHw = pArg->pSpiHw;
00098
00099 if (channel != spiDmaRxChannel)
00100 return;
00101
00102
00103 SPI_Disable (pSpiHw);
00104 TRACE_INFO("SPI Rx DMA Callback has been called %d bytes received\n\r",
00105 pArg->pCurrentCommand->RxSize);
00106
00107 NVIC_ClearPendingIRQ(XDMAC_IRQn);
00108 NVIC_DisableIRQ(XDMAC_IRQn);
00109
00110
00111 PMC_DisablePeripheral (pArg->spiId);
00112
00113
00114 SPI_ReleaseCS(pSpiHw);
00115
00116
00117 XDMAD_FreeChannel(pArg->pXdmad, spiDmaRxChannel);
00118 XDMAD_FreeChannel(pArg->pXdmad, spiDmaTxChannel);
00119 SCB_InvalidateDCache_by_Addr((uint32_t *)pArg->pCurrentCommand->pRxBuff,
00120 pArg->pCurrentCommand->RxSize);
00121
00122 pArg->semaphore++;
00123
00124 printf(" %s\n\r", pArg->pCurrentCommand->pRxBuff);
00125
00126
00127 if (pSpidCmd && pSpidCmd->callback) {
00128
00129 pSpidCmd->callback(0, pSpidCmd->pArgument);
00130 }
00131 }
00132
00133
00134
00135
00136
00137
00138
00139 static uint8_t _spid_configureDmaChannels(Spid *pSpid)
00140 {
00141
00142 XDMAD_Initialize(pSpid->pXdmad, 0);
00143
00144 XDMAD_FreeChannel(pSpid->pXdmad, spiDmaTxChannel);
00145 XDMAD_FreeChannel(pSpid->pXdmad, spiDmaRxChannel);
00146
00147
00148 spiDmaTxChannel = XDMAD_AllocateChannel(pSpid->pXdmad,
00149 XDMAD_TRANSFER_MEMORY, pSpid->spiId);
00150
00151 if (spiDmaTxChannel == XDMAD_ALLOC_FAILED)
00152 return SPID_ERROR;
00153
00154
00155 spiDmaRxChannel =
00156 XDMAD_AllocateChannel(pSpid->pXdmad, pSpid->spiId, XDMAD_TRANSFER_MEMORY);
00157
00158 if (spiDmaRxChannel == XDMAD_ALLOC_FAILED)
00159 return SPID_ERROR;
00160
00161
00162 XDMAD_SetCallback(pSpid->pXdmad, spiDmaRxChannel,
00163 (XdmadTransferCallback)SPID_Rx_Cb, pSpid);
00164
00165 if (XDMAD_PrepareChannel(pSpid->pXdmad, spiDmaRxChannel))
00166 return SPID_ERROR;
00167
00168
00169 XDMAD_SetCallback(pSpid->pXdmad, spiDmaTxChannel, NULL, NULL);
00170
00171 if (XDMAD_PrepareChannel(pSpid->pXdmad, spiDmaTxChannel))
00172 return SPID_ERROR;
00173
00174 return 0;
00175 }
00176
00177
00178
00179
00180
00181
00182
00183
00184 static uint8_t _spid_configureLinkList(Spi *pSpiHw, void *pXdmad,
00185 SpidCmd *pCommand)
00186 {
00187 sXdmadCfg xdmadRxCfg, xdmadTxCfg;
00188 uint32_t xdmaCndc, xdmaInt;
00189 uint32_t spiId;
00190
00191 if ((unsigned int)pSpiHw == (unsigned int)SPI0) spiId = ID_SPI0;
00192
00193 if ((unsigned int)pSpiHw == (unsigned int)SPI1) spiId = ID_SPI1;
00194
00195
00196
00197 xdmadTxCfg.mbr_sa = (uint32_t)pCommand->pTxBuff;
00198
00199 xdmadTxCfg.mbr_da = (uint32_t)&pSpiHw->SPI_TDR;
00200
00201 xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
00202 XDMA_UBC_NDE_FETCH_DIS |
00203 XDMA_UBC_NSEN_UPDATED | pCommand->TxSize;
00204
00205 xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
00206 XDMAC_CC_MBSIZE_SINGLE |
00207 XDMAC_CC_DSYNC_MEM2PER |
00208 XDMAC_CC_CSIZE_CHK_1 |
00209 XDMAC_CC_DWIDTH_BYTE |
00210 XDMAC_CC_SIF_AHB_IF1 |
00211 XDMAC_CC_DIF_AHB_IF1 |
00212 XDMAC_CC_SAM_INCREMENTED_AM |
00213 XDMAC_CC_DAM_FIXED_AM |
00214 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(spiId, XDMAD_TRANSFER_TX));
00215
00216
00217 xdmadTxCfg.mbr_bc = 0;
00218 xdmadTxCfg.mbr_sus = 0;
00219 xdmadTxCfg.mbr_dus = 0;
00220
00221
00222
00223 xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
00224 XDMA_UBC_NDE_FETCH_DIS |
00225 XDMA_UBC_NDEN_UPDATED | pCommand->RxSize;
00226
00227 xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;
00228
00229 xdmadRxCfg.mbr_sa = (uint32_t)&pSpiHw->SPI_RDR;
00230 xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
00231 XDMAC_CC_MBSIZE_SINGLE |
00232 XDMAC_CC_DSYNC_PER2MEM |
00233 XDMAC_CC_CSIZE_CHK_1 |
00234 XDMAC_CC_DWIDTH_BYTE |
00235 XDMAC_CC_SIF_AHB_IF1 |
00236 XDMAC_CC_DIF_AHB_IF1 |
00237 XDMAC_CC_SAM_FIXED_AM |
00238 XDMAC_CC_DAM_INCREMENTED_AM |
00239 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(spiId, XDMAD_TRANSFER_RX));
00240
00241
00242 xdmadRxCfg.mbr_bc = 0;
00243 xdmadRxCfg.mbr_sus = 0;
00244 xdmadRxCfg.mbr_dus = 0;
00245
00246 xdmaCndc = 0;
00247
00248
00249 xdmaInt = (XDMAC_CIE_BIE |
00250 XDMAC_CIE_DIE |
00251 XDMAC_CIE_FIE |
00252 XDMAC_CIE_RBIE |
00253 XDMAC_CIE_WBIE |
00254 XDMAC_CIE_ROIE);
00255
00256 if (XDMAD_ConfigureTransfer(pXdmad, spiDmaRxChannel, &xdmadRxCfg, xdmaCndc, 0,
00257 xdmaInt))
00258 return SPID_ERROR;
00259
00260 if (XDMAD_ConfigureTransfer(pXdmad, spiDmaTxChannel, &xdmadTxCfg, xdmaCndc, 0,
00261 xdmaInt))
00262 return SPID_ERROR;
00263
00264 return 0;
00265 }
00266
00267
00268
00269
00270
00271
00272
00273
00274
00275
00276
00277
00278
00279
00280
00281
00282 uint32_t SPID_Configure(Spid *pSpid ,
00283 Spi *pSpiHw ,
00284 uint8_t spiId,
00285 uint32_t spiMode,
00286 sXdmad *pXdmad)
00287 {
00288
00289 pSpid->pSpiHw = pSpiHw;
00290 pSpid->spiId = spiId;
00291 pSpid->semaphore = 1;
00292 pSpid->pCurrentCommand = 0;
00293 pSpid->pXdmad = pXdmad;
00294
00295
00296
00297 SPI_Configure (pSpiHw, pSpid->spiId, spiMode);
00298
00299 return 0;
00300 }
00301
00302
00303
00304
00305
00306
00307
00308
00309 void SPID_ConfigureCS(Spid *pSpid,
00310 uint32_t dwCS,
00311 uint32_t dwCsr)
00312 {
00313 Spi *pSpiHw = pSpid->pSpiHw;
00314
00315
00316 PMC_EnablePeripheral (pSpid->spiId);
00317
00318 SPI_ConfigureNPCS(pSpiHw, dwCS, dwCsr);
00319
00320
00321 PMC_DisablePeripheral (pSpid->spiId);
00322
00323 }
00324
00325
00326
00327
00328
00329
00330
00331
00332
00333
00334
00335 uint32_t SPID_SendCommand(Spid *pSpid, SpidCmd *pCommand)
00336 {
00337 Spi *pSpiHw = pSpid->pSpiHw;
00338
00339
00340 if (pSpid->semaphore == 0)
00341 return SPID_ERROR_LOCK;
00342
00343 pSpid->semaphore--;
00344
00345
00346 PMC_EnablePeripheral (pSpid->spiId);
00347
00348
00349 SPI_ChipSelect (pSpiHw, 1 << pCommand->spiCs);
00350
00351
00352 pSpid->pCurrentCommand = pCommand;
00353
00354
00355 if (_spid_configureDmaChannels(pSpid))
00356 return SPID_ERROR_LOCK;
00357
00358
00359 NVIC_ClearPendingIRQ(XDMAC_IRQn);
00360 NVIC_SetPriority(XDMAC_IRQn , 1);
00361 NVIC_EnableIRQ(XDMAC_IRQn);
00362
00363
00364 if (_spid_configureLinkList(pSpiHw, pSpid->pXdmad, pCommand))
00365 return SPID_ERROR_LOCK;
00366
00367
00368 SPI_Enable (pSpiHw);
00369 SCB_CleanDCache_by_Addr((uint32_t *)pCommand->pTxBuff, pCommand->TxSize);
00370
00371
00372 if (XDMAD_StartTransfer(pSpid->pXdmad, spiDmaRxChannel))
00373 return SPID_ERROR_LOCK;
00374
00375 if (XDMAD_StartTransfer(pSpid->pXdmad, spiDmaTxChannel))
00376 return SPID_ERROR_LOCK;
00377
00378 return 0;
00379 }
00380
00381
00382
00383
00384
00385
00386
00387 uint32_t SPID_IsBusy(const Spid *pSpid)
00388 {
00389 if (pSpid->semaphore == 0)
00390 return 1;
00391 else
00392 return 0;
00393 }