SAMV71 Xplained Ultra Software Package 1.5

board_lowlevel.c

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00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2015, Atmel Corporation                                        */
00006 /*                                                                              */
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00011 /*                                                                              */
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00028 /* ---------------------------------------------------------------------------- */
00029 
00030 /**
00031  * \file
00032  *
00033  * Provides the low-level initialization function that called on chip startup.
00034  */
00035 
00036 /*----------------------------------------------------------------------------
00037  *        Headers
00038  *----------------------------------------------------------------------------*/
00039 
00040 #include "board.h"
00041 
00042 
00043 #if defined(ENABLE_TCM) && defined(__GNUC__)
00044     extern char _itcm_lma, _sitcm, _eitcm;
00045 #endif
00046 
00047 
00048 /*----------------------------------------------------------------------------
00049  *        Exported functions
00050  *----------------------------------------------------------------------------*/
00051 /* Default memory map
00052    NO. Address range          Memory region    Memory type     Shareable?    Cache policy
00053    1   0x00000000- 0x1FFFFFFF Code             Normal
00054        0x00000000- 0x003FFFFF ITCM
00055        0x00400000- 0x005FFFFF Internal flash   Normal          Not shareable   WB
00056    2   0x20000000- 0x3FFFFFFF SRAM             Normal
00057        0x20000000- 0x203FFFFF DTCM
00058        0x20400000- 0x2043FFFF First Partition  Normal          Not shareable   WB
00059  if MPU_HAS_NOCACHE_REGION is defined
00060        0x20440000- 0x2045EFFF Second Partition Normal          Not shareable   WB
00061        0x2045F000- 0x2045FFFF Nocache SRAM     Normal          Shareable
00062  if MPU_HAS_NOCACHE_REGION is NOT defined
00063        0x20440000- 0x2045FFFF Second Partition Normal          Not shareable   WB
00064    3   0x40000000- 0x5FFFFFFF Peripheral       Device          Shareable
00065    4   0x60000000- 0x7FFFFFFF RAM
00066        0x60000000- 0x6FFFFFFF External EBI  Strongly-ordered   Shareable
00067        0x70000000- 0x7FFFFFFF SDRAM            Normal          Shareable       WBWA
00068    5   0x80000000- 0x9FFFFFFF QSPI          Strongly-ordered   Shareable
00069    6   0xA0100000- 0xA01FFFFF USBHS RAM        Device          Shareable
00070    7   0xE0000000- 0xFFFFFFFF System           -                  -
00071    */
00072 
00073 /**
00074  * \brief Set up a memory region.
00075  */
00076 void _SetupMemoryRegion(void)
00077 {
00078 
00079     uint32_t dwRegionBaseAddr;
00080     uint32_t dwRegionAttr;
00081 
00082     memory_barrier();
00083 
00084     /***************************************************
00085         ITCM memory region --- Normal
00086         START_Addr:-  0x00000000UL
00087         END_Addr:-    0x003FFFFFUL
00088     ****************************************************/
00089     dwRegionBaseAddr =
00090         ITCM_START_ADDRESS |
00091         MPU_REGION_VALID |
00092         MPU_DEFAULT_ITCM_REGION;        // 1
00093 
00094     dwRegionAttr =
00095         MPU_AP_PRIVILEGED_READ_WRITE |
00096         MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) |
00097         MPU_REGION_ENABLE;
00098 
00099     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00100 
00101     /****************************************************
00102         Internal flash memory region --- Normal read-only
00103         (update to Strongly ordered in write accesses)
00104         START_Addr:-  0x00400000UL
00105         END_Addr:-    0x005FFFFFUL
00106     ******************************************************/
00107 
00108     dwRegionBaseAddr =
00109         IFLASH_START_ADDRESS |
00110         MPU_REGION_VALID |
00111         MPU_DEFAULT_IFLASH_REGION;      //2
00112 
00113     dwRegionAttr =
00114         MPU_AP_READONLY |
00115         INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
00116         MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) |
00117         MPU_REGION_ENABLE;
00118 
00119     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00120 
00121     /****************************************************
00122         DTCM memory region --- Normal
00123         START_Addr:-  0x20000000L
00124         END_Addr:-    0x203FFFFFUL
00125     ******************************************************/
00126 
00127     /* DTCM memory region */
00128     dwRegionBaseAddr =
00129         DTCM_START_ADDRESS |
00130         MPU_REGION_VALID |
00131         MPU_DEFAULT_DTCM_REGION;         //3
00132 
00133     dwRegionAttr =
00134         MPU_AP_PRIVILEGED_READ_WRITE |
00135         MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) |
00136         MPU_REGION_ENABLE;
00137 
00138     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00139 
00140     /****************************************************
00141         SRAM Cacheable memory region --- Normal
00142         START_Addr:-  0x20400000UL
00143         END_Addr:-    0x2043FFFFUL
00144     ******************************************************/
00145     /* SRAM memory  region */
00146     dwRegionBaseAddr =
00147         SRAM_FIRST_START_ADDRESS |
00148         MPU_REGION_VALID |
00149         MPU_DEFAULT_SRAM_REGION_1;         //4
00150 
00151     dwRegionAttr =
00152         MPU_AP_FULL_ACCESS    |
00153         INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
00154         MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS)
00155         | MPU_REGION_ENABLE;
00156 
00157     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00158 
00159 
00160     /****************************************************
00161         Internal SRAM second partition memory region --- Normal
00162         START_Addr:-  0x20440000UL
00163         END_Addr:-    0x2045FFFFUL
00164     ******************************************************/
00165     /* SRAM memory region */
00166     dwRegionBaseAddr =
00167         SRAM_SECOND_START_ADDRESS |
00168         MPU_REGION_VALID |
00169         MPU_DEFAULT_SRAM_REGION_2;         //5
00170 
00171     dwRegionAttr =
00172         MPU_AP_FULL_ACCESS    |
00173         INNER_NORMAL_WB_NWA_TYPE(NON_SHAREABLE) |
00174         MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) |
00175         MPU_REGION_ENABLE;
00176 
00177     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00178 
00179 #ifdef MPU_HAS_NOCACHE_REGION
00180     dwRegionBaseAddr =
00181         SRAM_NOCACHE_START_ADDRESS |
00182         MPU_REGION_VALID |
00183         MPU_NOCACHE_SRAM_REGION;          //11
00184 
00185     dwRegionAttr =
00186         MPU_AP_FULL_ACCESS    |
00187         INNER_OUTER_NORMAL_NOCACHE_TYPE(SHAREABLE) |
00188         MPU_CalMPURegionSize(NOCACHE_SRAM_REGION_SIZE) |
00189         MPU_REGION_ENABLE;
00190 
00191     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00192 #endif
00193 
00194     /****************************************************
00195         Peripheral memory region --- DEVICE Shareable
00196         START_Addr:-  0x40000000UL
00197         END_Addr:-    0x5FFFFFFFUL
00198     ******************************************************/
00199     dwRegionBaseAddr =
00200         PERIPHERALS_START_ADDRESS |
00201         MPU_REGION_VALID |
00202         MPU_PERIPHERALS_REGION;          //6
00203 
00204     dwRegionAttr = MPU_AP_FULL_ACCESS |
00205                    MPU_REGION_EXECUTE_NEVER |
00206                    SHAREABLE_DEVICE_TYPE |
00207                    MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS)
00208                    | MPU_REGION_ENABLE;
00209 
00210     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00211 
00212 
00213     /****************************************************
00214         External EBI memory  memory region --- Strongly Ordered
00215         START_Addr:-  0x60000000UL
00216         END_Addr:-    0x6FFFFFFFUL
00217     ******************************************************/
00218     dwRegionBaseAddr =
00219         EXT_EBI_START_ADDRESS |
00220         MPU_REGION_VALID |
00221         MPU_EXT_EBI_REGION;
00222 
00223     dwRegionAttr =
00224         MPU_AP_FULL_ACCESS |
00225         /* External memory Must be defined with 'Device' or 'Strongly Ordered'
00226         attribute for write accesses (AXI) */
00227         STRONGLY_ORDERED_SHAREABLE_TYPE |
00228         MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) |
00229         MPU_REGION_ENABLE;
00230 
00231     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00232 
00233     /****************************************************
00234         SDRAM Cacheable memory region --- Normal
00235         START_Addr:-  0x70000000UL
00236         END_Addr:-    0x7FFFFFFFUL
00237     ******************************************************/
00238     dwRegionBaseAddr =
00239         SDRAM_START_ADDRESS |
00240         MPU_REGION_VALID |
00241         MPU_DEFAULT_SDRAM_REGION;        //7
00242 
00243     dwRegionAttr =
00244         MPU_AP_FULL_ACCESS    |
00245         INNER_NORMAL_WB_RWA_TYPE(SHAREABLE) |
00246         MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) |
00247         MPU_REGION_ENABLE;
00248 
00249     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00250 
00251     /****************************************************
00252         QSPI memory region --- Strongly ordered
00253         START_Addr:-  0x80000000UL
00254         END_Addr:-    0x9FFFFFFFUL
00255     ******************************************************/
00256     dwRegionBaseAddr =
00257         QSPI_START_ADDRESS |
00258         MPU_REGION_VALID |
00259         MPU_QSPIMEM_REGION;              //8
00260 
00261     dwRegionAttr =
00262         MPU_AP_FULL_ACCESS |
00263         STRONGLY_ORDERED_SHAREABLE_TYPE |
00264         MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) |
00265         MPU_REGION_ENABLE;
00266 
00267     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00268 
00269 
00270     /****************************************************
00271         USB RAM Memory region --- Device
00272         START_Addr:-  0xA0100000UL
00273         END_Addr:-    0xA01FFFFFUL
00274     ******************************************************/
00275     dwRegionBaseAddr =
00276         USBHSRAM_START_ADDRESS |
00277         MPU_REGION_VALID |
00278         MPU_USBHSRAM_REGION;              //9
00279 
00280     dwRegionAttr =
00281         MPU_AP_FULL_ACCESS |
00282         MPU_REGION_EXECUTE_NEVER |
00283         SHAREABLE_DEVICE_TYPE |
00284         MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) |
00285         MPU_REGION_ENABLE;
00286 
00287     MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr);
00288 
00289 
00290     /* Enable the memory management fault , Bus Fault, Usage Fault exception */
00291     SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
00292                    | SCB_SHCSR_USGFAULTENA_Msk);
00293 
00294     /* Enable the MPU region */
00295     MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA);
00296 
00297     memory_sync();
00298 }
00299 
00300 #ifdef ENABLE_TCM
00301 
00302 #if defined (__ICCARM__) /* IAR Ewarm */
00303     #pragma section = "CSTACK"
00304     #pragma section = "CSTACK_DTCM"
00305     #define SRAM_STACK_BASE     (__section_begin("CSTACK"))
00306     #define DTCM_STACK_BASE     (__section_begin("CSTACK_DTCM"))
00307     #define SRAM_STACK_LIMIT    (__section_end("CSTACK"))
00308     #define DTCM_STACK_LIMIT    (__section_end("CSTACK_DTCM"))
00309 #elif defined (__CC_ARM)  /* MDK */
00310     extern uint32_t Image$$ARM_LIB_STACK$$Base;
00311     extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
00312     extern uint32_t Image$$DTCM_STACK$$Base;
00313     extern uint32_t Image$$DTCM_STACK$$ZI$$Limit;
00314     #define SRAM_STACK_BASE     (&Image$$ARM_LIB_STACK$$Base)
00315     #define DTCM_STACK_BASE     (&Image$$DTCM_STACK$$Base)
00316     #define SRAM_STACK_LIMIT    (&Image$$ARM_LIB_STACK$$ZI$$Limit)
00317     #define DTCM_STACK_LIMIT    (&Image$$DTCM_STACK$$ZI$$Limit)
00318 #elif defined (__GNUC__)  /* GCC */
00319     extern char _sdtcm_stack, _edtcm_stack, _sstack, _estack;
00320     #define SRAM_STACK_BASE     ((void *)(&_sstack))
00321     #define DTCM_STACK_BASE     ((void *)(&_sdtcm_stack))
00322     #define SRAM_STACK_LIMIT    ((void *)(&_estack))
00323     #define DTCM_STACK_LIMIT    ((void *)(&_edtcm_stack))
00324 #endif
00325 
00326 /** \brief  Change stack's location to DTCM
00327 
00328     The function changes the stack's location from SRAM to DTCM
00329  */
00330 void TCM_StackInit(void);
00331 void TCM_StackInit(void)
00332 {
00333     uint32_t offset = (uint32_t)SRAM_STACK_LIMIT - (uint32_t)DTCM_STACK_LIMIT;
00334     volatile char *dst = (volatile char *)DTCM_STACK_LIMIT;
00335     volatile char *src = (volatile char *)SRAM_STACK_LIMIT;
00336 
00337     /* copy stack data from SRAM to DTCM */
00338     while (src > (volatile char *)SRAM_STACK_BASE)
00339         *--dst = *--src;
00340 
00341     __set_MSP(__get_MSP() - offset);
00342 }
00343 
00344 #endif
00345 
00346 
00347 /**
00348  * \brief Performs the low-level initialization of the chip.
00349  */
00350 extern WEAK void LowLevelInit(void)
00351 {
00352 
00353     SystemInit();
00354 #ifndef MPU_EXAMPLE_FEATURE
00355     _SetupMemoryRegion();
00356 #endif
00357 
00358 #if defined(FFT_DEMO) && (defined(__GNUC__) || defined(__CC_ARM))
00359     /* Enabling the FPU */
00360     SCB->CPACR |= 0x00F00000;
00361     __DSB();
00362     __ISB();
00363 #endif
00364 
00365 #if defined(ENABLE_TCM) && defined(__GNUC__)
00366     volatile char *dst = &_sitcm;
00367     volatile char *src = &_itcm_lma;
00368 
00369     /* copy code_TCM from flash to ITCM */
00370     while (dst < &_eitcm)
00371         *dst++ = *src++;
00372 
00373 #endif
00374 }
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