00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2015, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 /** 00031 * \file 00032 * 00033 * Implementation of memories configuration on board. 00034 * 00035 */ 00036 00037 /*---------------------------------------------------------------------------- 00038 * Headers 00039 *----------------------------------------------------------------------------*/ 00040 #include "board.h" 00041 00042 /*---------------------------------------------------------------------------- 00043 * Exported functions 00044 *----------------------------------------------------------------------------*/ 00045 00046 #define SDRAM_BA0 (1 << 20) 00047 #define SDRAM_BA1 (1 << 21) 00048 00049 00050 uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size) 00051 { 00052 uint32_t i; 00053 uint32_t ret = 1; 00054 uint32_t *ptr32 = (uint32_t *) baseAddr; 00055 uint16_t *ptr16 = (uint16_t *) baseAddr; 00056 uint8_t *ptr8 = (uint8_t *) baseAddr; 00057 /* Test for 55AA55AA/AA55AA55 pattern */ 00058 printf(" Test for 55AA55AA/AA55AA55 pattern ... \n\r"); 00059 00060 for (i = 0; i < size; i ++) { 00061 if (i & 1) 00062 ptr32[i] = 0x55AA55AA; 00063 else 00064 ptr32[i] = 0xAA55AA55; 00065 00066 memory_barrier() 00067 } 00068 00069 for (i = 0; i < size; i++) { 00070 if (i & 1) { 00071 if (ptr32[i] != 0x55AA55AA) { 00072 printf("-E- Expected:%x, read %x @ %x \n\r" , 00073 0xAA55AA55, (unsigned)ptr32[i], (unsigned)(baseAddr + i)); 00074 ret = 0; 00075 00076 } 00077 } else { 00078 if (ptr32[i] != 0xAA55AA55) { 00079 printf("-E- Expected:%x, read %x @ %x \n\r" , 00080 0xAA55AA55 , (unsigned)ptr32[i], (unsigned)(baseAddr + i)); 00081 ret = 0; 00082 } 00083 } 00084 } 00085 00086 if (!ret) return ret; 00087 00088 printf(" Test for BYTE accessing... \n\r"); 00089 00090 /* Test for BYTE accessing */ 00091 for (i = 0; i < size; i ++) 00092 ptr8[i] = (uint8_t)(i & 0xFF); 00093 00094 for (i = 0; i < size; i++) { 00095 if (ptr8[i] != (uint8_t)(i & 0xFF)) { 00096 printf("-E- Expected:%x, read %x @ %x \n\r" , 00097 (unsigned)(i & 0xFF), ptr8[i], (unsigned)(baseAddr + i)); 00098 ret = 0; 00099 } 00100 } 00101 00102 if (!ret) return ret; 00103 00104 printf(" Test for WORD accessing... \n\r"); 00105 00106 /* Test for WORD accessing */ 00107 for (i = 0; i < size / 2; i ++) 00108 ptr16[i] = (uint16_t)(i & 0xFFFF); 00109 00110 for (i = 0; i < size / 2; i++) { 00111 if (ptr16[i] != (uint16_t)(i & 0xFFFF)) { 00112 printf("-E- Expected:%x, read %x @ %x \n\r" , 00113 (unsigned)(i & 0xFFFF), ptr16[i], (unsigned)(baseAddr + i)); 00114 ret = 0; 00115 } 00116 } 00117 00118 if (!ret) return ret; 00119 00120 printf(" Test for DWORD accessing... \n\r"); 00121 00122 /* Test for DWORD accessing */ 00123 for (i = 0; i < size / 4; i ++) { 00124 ptr32[i] = (uint32_t)(i & 0xFFFFFFFF); 00125 memory_barrier() 00126 } 00127 00128 for (i = 0; i < size / 4; i++) { 00129 if (ptr32[i] != (uint32_t)(i & 0xFFFFFFFF)) { 00130 printf("-E- Expected:%x, read %x @ %x \n\r" , 00131 (unsigned)(i & 0xFFFFFFFF), (unsigned)ptr32[i], (unsigned)(baseAddr + i)); 00132 ret = 0; 00133 } 00134 } 00135 00136 return ret; 00137 } 00138 00139 00140 /** 00141 * \brief Configures the EBI for SDRAM (IS42S16100E-7B) access. 00142 */ 00143 00144 00145 void BOARD_ConfigureSdram(void) 00146 { 00147 const Pin pinsSdram[] = {BOARD_SDRAM_PINS}; 00148 volatile uint32_t i; 00149 volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR; 00150 00151 /* Configure PIO */ 00152 PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram)); 00153 PMC_EnablePeripheral(ID_SDRAMC); 00154 MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN; 00155 00156 /* 1. SDRAM features must be set in the configuration register: 00157 asynchronous timings (TRC, TRAS, etc.), number of columns, rows, 00158 CAS latency, and the data bus width. */ 00159 SDRAMC->SDRAMC_CR = 00160 SDRAMC_CR_NC_COL8 // 8 column bits 00161 | SDRAMC_CR_NR_ROW11 // 12 row bits (4K) 00162 | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 3 00163 | SDRAMC_CR_NB_BANK2 // 2 banks 00164 | SDRAMC_CR_DBW // 16 bit 00165 | SDRAMC_CR_TWR(5) 00166 | SDRAMC_CR_TRC_TRFC(13) // 63ns min 00167 | SDRAMC_CR_TRP(5) // Command period (PRE to ACT) 21 ns min 00168 | SDRAMC_CR_TRCD( 00169 5) // Active Command to read/Write Command delay time 21ns min 00170 | SDRAMC_CR_TRAS(9) // Command period (ACT to PRE) 42ns min 00171 | SDRAMC_CR_TXSR(15U); // Exit self-refresh to active time 70ns Min 00172 00173 /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive 00174 strength (DS) and partial array self refresh (PASR) must be set in the 00175 Low Power Register. */ 00176 00177 /* 3. The SDRAM memory type must be set in the Memory Device Register.*/ 00178 SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM; 00179 00180 /* 4. A minimum pause of 200 ¦Ěs is provided to precede any signal toggle.*/ 00181 for (i = 0; i < 100000; i++); 00182 00183 /* 5. (1)A NOP command is issued to the SDRAM devices. The application must 00184 set Mode to 1 in the Mode Register and perform a write access to 00185 any SDRAM address.*/ 00186 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP; 00187 *pSdram = 0; 00188 00189 for (i = 0; i < 100000; i++); 00190 00191 /* 6. An All Banks Precharge command is issued to the SDRAM devices. 00192 The application must set Mode to 2 in the Mode Register and perform a write 00193 access to any SDRAM address. */ 00194 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE; 00195 *pSdram = 0; 00196 00197 for (i = 0; i < 100000; i++); 00198 00199 /* 7. Eight auto-refresh (CBR) cycles are provided. The application must 00200 set the Mode to 4 in the Mode Register and perform a write access to any 00201 SDRAM location eight times.*/ 00202 for (i = 0; i < 8; i++) { 00203 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00204 *pSdram = 0; 00205 } 00206 00207 for (i = 0; i < 100000; i++); 00208 00209 /*8. A Mode Register set (MRS) cycle is issued to program the parameters of 00210 the SDRAM devices, in particular CAS latency and burst length. The 00211 application must set Mode to 3 in the Mode Register and perform a write 00212 access to the SDRAM. The write address must be chosen so that BA[1:0] 00213 are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 00214 4 banks) bank address, the SDRAM write access should be done at the address 00215 0x70000000.*/ 00216 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG; 00217 *pSdram = 0; 00218 00219 for (i = 0; i < 100000; i++); 00220 00221 /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) 00222 cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The 00223 application must set Mode to 5 in the Mode Register and perform a write 00224 access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] 00225 are set to 1. 00226 For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank 00227 address the SDRAM write access should be done at the address 0x70800000 or 00228 0x70400000. */ 00229 //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG; 00230 // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0; 00231 00232 /* 10. The application must go into Normal Mode, setting Mode to 0 in the 00233 Mode Register and performing a write access at any location in the SDRAM. */ 00234 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL; 00235 *pSdram = 0; 00236 00237 for (i = 0; i < 100000; i++); 00238 00239 /* 11. Write the refresh rate into the count field in the SDRAMC Refresh 00240 Timer register. (Refresh rate = delay between refresh cycles). 00241 The SDRAM device requires a refresh every 15.625 ¦Ěs or 7.81 ¦Ěs. 00242 With a 100 MHz frequency, the Refresh Timer Counter Register must be set 00243 with the value 1562(15.625 ¦Ěs x 100 MHz) or 781(7.81 ¦Ěs x 100 MHz). */ 00244 // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ¦Ěs 00245 /* ((32 x 10(^-3))/2048) x150 x (10^6) */ 00246 SDRAMC->SDRAMC_TR = 1562; 00247 SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL; 00248 /* After initialization, the SDRAM devices are fully functional. */ 00249 }