00001 /* ---------------------------------------------------------------------------- 00002 * SAM Software Package License 00003 * ---------------------------------------------------------------------------- 00004 * Copyright (c) 2014, Atmel Corporation 00005 * 00006 * All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without 00009 * modification, are permitted provided that the following conditions are met: 00010 * 00011 * - Redistributions of source code must retain the above copyright notice, 00012 * this list of conditions and the disclaimer below. 00013 * 00014 * Atmel's name may not be used to endorse or promote products derived from 00015 * this software without specific prior written permission. 00016 * 00017 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 00018 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00019 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 00020 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 00021 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00022 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 00023 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 00024 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 00025 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 00026 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00027 * ---------------------------------------------------------------------------- 00028 */ 00029 00030 /** \addtogroup sdram_module 00031 * The SDRAMC driver provides the Interface to configure the SDRAM Controller 00032 * (SDRAMC). 00033 * \section Usage 00034 * <ul> 00035 * <li> Configure SDRAM using SDRAMC_Configure().</li> 00036 00037 * </ul> 00038 * For more accurate information, please look at the SDRAMC section of the 00039 * Datasheet. 00040 * Related files :\n 00041 * \ref sdramc.c\n 00042 * \ref sdramc.h.\n 00043 */ 00044 00045 /** 00046 * \file 00047 * 00048 * \section Purpose 00049 * 00050 * Interface for configuring and using SDRAM Controller (SDRAMC). 00051 * 00052 */ 00053 00054 /** 00055 * \file 00056 * 00057 * Implementation of memories configuration on board. 00058 * 00059 */ 00060 /*---------------------------------------------------------------------------- 00061 * Headers 00062 *----------------------------------------------------------------------------*/ 00063 #include "chip.h" 00064 00065 /*---------------------------------------------------------------------------- 00066 * Local functions 00067 *----------------------------------------------------------------------------*/ 00068 /** 00069 * \brief Calculate the sdram controller config register value. 00070 * \param pMemory Pointer to the sdram structure. 00071 * \return Configure register value. 00072 */ 00073 static uint32_t SDRAMC_compute_CR_value( SSdramc_Memory* pMemory ) 00074 { 00075 uint32_t dw=0 ; 00076 00077 dw |= pMemory->cfg.dwColumnBits ; 00078 dw |= pMemory->cfg.dwRowBits ; 00079 dw |= pMemory->cfg.dwBanks ; //NB, number of banks 00080 dw |= pMemory->cfg.dwCAS ; //CAS, CAS latency 00081 dw |= pMemory->cfg.dwDataBusWidth ; //DBW, data bus width 00082 dw |= SDRAMC_CR_TWR( pMemory->cfg.dwWriteRecoveryDelay ) ; 00083 //TWR, Write Recovery Delay 00084 dw |= SDRAMC_CR_TRC_TRFC( pMemory->cfg.dwRowCycleDelay_RowRefreshCycle ) ; 00085 //TRC_TRFC,Row Cycle Delay and Row Refresh Cycle 00086 dw |= SDRAMC_CR_TRP( pMemory->cfg.dwRowPrechargeDelay ) ; 00087 //TRP, Row Precharge Delay 00088 dw |= SDRAMC_CR_TRCD( pMemory->cfg.dwRowColumnDelay ) ; 00089 //TRCD, Row to Column Delay 00090 dw |= SDRAMC_CR_TRAS( pMemory->cfg.dwActivePrechargeDelay ) ; 00091 //TRAS, Active to Precharge Delay 00092 dw |= SDRAMC_CR_TXSR( pMemory->cfg.dwExitSelfRefreshActiveDelay ) ; 00093 //TXSR, Exit Self Refresh to Active Delay 00094 return dw ; 00095 } 00096 00097 /*---------------------------------------------------------------------------- 00098 * Exported functions 00099 *----------------------------------------------------------------------------*/ 00100 /** 00101 * \brief Configure and initialize the SDRAM controller. 00102 * \param pMemory Pointer to the sdram structure. 00103 * \param dwClockFrequency SDRAM clock frequency. 00104 */ 00105 extern void SDRAMC_Configure( SSdramc_Memory* pMemory, uint32_t dwClockFrequency ) 00106 { 00107 volatile uint32_t dw ; 00108 00109 /* SDRAM hardware init */ 00110 /* Enable peripheral clock */ 00111 PMC_EnablePeripheral( ID_SMC ) ; 00112 00113 /* SDRAM device configure */ 00114 /* Step 1. */ 00115 /* Program the features of SDRAM device into the Configuration Register.*/ 00116 SDRAMC->SDRAMC_CR = SDRAMC_compute_CR_value( pMemory ) ; 00117 00118 /* Step 2. */ 00119 /* For low-power SDRAM, temperature-compensated self refresh (TCSR), 00120 drive strength (DS) and partial array self refresh (PASR) must be set 00121 in the Low-power Register.*/ 00122 SDRAMC->SDRAMC_LPR = 0; 00123 00124 /* Step 3. */ 00125 /* Program the memory device type into the Memory Device Register */ 00126 SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM; 00127 00128 /* Step 4 */ 00129 /* A minimum pause of 200 ¦Ěs is provided to precede any signal toggle. 00130 (6 core cycles per iteration) */ 00131 for ( dw = 0; dw < ((dwClockFrequency/1000000)*200/6) ; dw++ ) ; 00132 00133 /* Step 5. */ 00134 /* A NOP command is issued to the SDR-SDRAM. Program NOP command into 00135 Mode Register, the application must set Mode to 1 in the Mode Register. 00136 Perform a write access to any SDR-SDRAM address to acknowledge this command. 00137 Now the clock which drives SDR-SDRAM device is enabled.*/ 00138 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP; 00139 *(uint16_t *)(EBI_SDRAMC_ADDR) = 0; 00140 00141 /* Step 6. */ 00142 /* An all banks precharge command is issued to the SDR-SDRAM. Program all 00143 banks precharge command into Mode Register, the application must set Mode to 00144 2 in the Mode Register . Perform a write access to any SDRSDRAM address to 00145 acknowledge this command. */ 00146 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE; 00147 *(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0; 00148 00149 /* add some delays after precharge */ 00150 for ( dw = 0; dw < ((dwClockFrequency/1000000)*200/6) ; dw++ ); 00151 00152 /* Step 7. */ 00153 /* Eight auto-refresh (CBR) cycles are provided. Program the auto refresh 00154 command (CBR) into Mode Register, the application must set Mode to 4 in 00155 the Mode Register. Once in the idle state, eight AUTO REFRESH cycles must 00156 be performed. */ 00157 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00158 *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x1; 00159 00160 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00161 *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x2; 00162 00163 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00164 *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x3; 00165 00166 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00167 *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x4; 00168 00169 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00170 *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x5; 00171 00172 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00173 *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x6; 00174 00175 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00176 *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x7; 00177 00178 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; 00179 *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x8; 00180 00181 /* Step 8. */ 00182 /* A Mode Register set (MRS) cycle is issued to program the parameters of 00183 the SDRAM devices, in particular CAS latency and burst length. */ 00184 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG; 00185 *(uint16_t *)(EBI_SDRAMC_ADDR + 0x22) = 0xcafe; 00186 00187 /* Step 9. */ 00188 /* For low-power SDR-SDRAM initialization, an Extended Mode Register set 00189 (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). 00190 The write address must be chosen so that BA[1] is set to 1 and BA[0] is set 00191 to 0 */ 00192 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG; 00193 *((uint16_t *)(EBI_SDRAMC_ADDR + (1 << pMemory->cfg.dwBK1))) = 0; 00194 00195 /* Step 10. */ 00196 /* The application must go into Normal Mode, setting Mode to 0 in the Mode 00197 Register and perform a write access at any location in the SDRAM to 00198 acknowledge this command. */ 00199 SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL; 00200 *(uint16_t *)(EBI_SDRAMC_ADDR ) = 0x0; 00201 00202 /* Step 11. */ 00203 /* Write the refresh rate into the count field in the SDRAMC Refresh 00204 Timer register. Set Refresh timer 15.625 us*/ 00205 dw=dwClockFrequency/1000u ; 00206 dw*=15625u ; 00207 dw/=1000000u ; 00208 SDRAMC->SDRAMC_TR = SDRAMC_TR_COUNT( dw ) ; 00209 } 00210