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00030 #ifndef _SAMV71_ICM_COMPONENT_
00031 #define _SAMV71_ICM_COMPONENT_
00032
00033
00034
00035
00036
00037
00038
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040
00041 typedef struct {
00042 __IO uint32_t ICM_CFG;
00043 __O uint32_t ICM_CTRL;
00044 __O uint32_t ICM_SR;
00045 __I uint32_t Reserved1[1];
00046 __O uint32_t ICM_IER;
00047 __O uint32_t ICM_IDR;
00048 __I uint32_t ICM_IMR;
00049 __I uint32_t ICM_ISR;
00050 __I uint32_t ICM_UASR;
00051 __I uint32_t Reserved2[3];
00052 __IO uint32_t ICM_DSCR;
00053 __IO uint32_t ICM_HASH;
00054 __O uint32_t ICM_UIHVAL[8];
00055 } Icm;
00056 #endif
00057
00058 #define ICM_CFG_WBDIS (0x1u << 0)
00059 #define ICM_CFG_EOMDIS (0x1u << 1)
00060 #define ICM_CFG_SLBDIS (0x1u << 2)
00061 #define ICM_CFG_BBC_Pos 4
00062 #define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos)
00063 #define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)))
00064 #define ICM_CFG_ASCD (0x1u << 8)
00065 #define ICM_CFG_DUALBUFF (0x1u << 9)
00066 #define ICM_CFG_UIHASH (0x1u << 12)
00067 #define ICM_CFG_UALGO_Pos 13
00068 #define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos)
00069 #define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)))
00070 #define ICM_CFG_UALGO_SHA1 (0x0u << 13)
00071 #define ICM_CFG_UALGO_SHA256 (0x1u << 13)
00072 #define ICM_CFG_UALGO_SHA224 (0x4u << 13)
00073 #define ICM_CFG_HAPROT_Pos 16
00074 #define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos)
00075 #define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)))
00076 #define ICM_CFG_DAPROT_Pos 24
00077 #define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos)
00078 #define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)))
00079
00080 #define ICM_CTRL_ENABLE (0x1u << 0)
00081 #define ICM_CTRL_DISABLE (0x1u << 1)
00082 #define ICM_CTRL_SWRST (0x1u << 2)
00083 #define ICM_CTRL_REHASH_Pos 4
00084 #define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos)
00085 #define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)))
00086 #define ICM_CTRL_RMDIS_Pos 8
00087 #define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos)
00088 #define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)))
00089 #define ICM_CTRL_RMEN_Pos 12
00090 #define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos)
00091 #define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)))
00092
00093 #define ICM_SR_ENABLE (0x1u << 0)
00094 #define ICM_SR_RAWRMDIS_Pos 8
00095 #define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos)
00096 #define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)))
00097 #define ICM_SR_RMDIS_Pos 12
00098 #define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos)
00099 #define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)))
00100
00101 #define ICM_IER_RHC_Pos 0
00102 #define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos)
00103 #define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)))
00104 #define ICM_IER_RDM_Pos 4
00105 #define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos)
00106 #define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)))
00107 #define ICM_IER_RBE_Pos 8
00108 #define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos)
00109 #define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)))
00110 #define ICM_IER_RWC_Pos 12
00111 #define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos)
00112 #define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)))
00113 #define ICM_IER_REC_Pos 16
00114 #define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos)
00115 #define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)))
00116 #define ICM_IER_RSU_Pos 20
00117 #define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos)
00118 #define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)))
00119 #define ICM_IER_URAD (0x1u << 24)
00120
00121 #define ICM_IDR_RHC_Pos 0
00122 #define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos)
00123 #define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)))
00124 #define ICM_IDR_RDM_Pos 4
00125 #define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos)
00126 #define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)))
00127 #define ICM_IDR_RBE_Pos 8
00128 #define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos)
00129 #define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)))
00130 #define ICM_IDR_RWC_Pos 12
00131 #define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos)
00132 #define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)))
00133 #define ICM_IDR_REC_Pos 16
00134 #define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos)
00135 #define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)))
00136 #define ICM_IDR_RSU_Pos 20
00137 #define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos)
00138 #define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)))
00139 #define ICM_IDR_URAD (0x1u << 24)
00140
00141 #define ICM_IMR_RHC_Pos 0
00142 #define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos)
00143 #define ICM_IMR_RDM_Pos 4
00144 #define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos)
00145 #define ICM_IMR_RBE_Pos 8
00146 #define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos)
00147 #define ICM_IMR_RWC_Pos 12
00148 #define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos)
00149 #define ICM_IMR_REC_Pos 16
00150 #define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos)
00151 #define ICM_IMR_RSU_Pos 20
00152 #define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos)
00153 #define ICM_IMR_URAD (0x1u << 24)
00154
00155 #define ICM_ISR_RHC_Pos 0
00156 #define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos)
00157 #define ICM_ISR_RDM_Pos 4
00158 #define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos)
00159 #define ICM_ISR_RBE_Pos 8
00160 #define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos)
00161 #define ICM_ISR_RWC_Pos 12
00162 #define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos)
00163 #define ICM_ISR_REC_Pos 16
00164 #define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos)
00165 #define ICM_ISR_RSU_Pos 20
00166 #define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos)
00167 #define ICM_ISR_URAD (0x1u << 24)
00168
00169 #define ICM_UASR_URAT_Pos 0
00170 #define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos)
00171 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0)
00172 #define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0)
00173 #define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0)
00174 #define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0)
00175 #define ICM_UASR_URAT_READ_ACCESS (0x4u << 0)
00176
00177 #define ICM_DSCR_DASA_Pos 6
00178 #define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos)
00179 #define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)))
00180
00181 #define ICM_HASH_HASA_Pos 7
00182 #define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos)
00183 #define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)))
00184
00185 #define ICM_UIHVAL_VAL_Pos 0
00186 #define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos)
00187 #define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)))
00188
00189
00190
00191
00192 #endif