Go to the documentation of this file.00001
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00039 #include "chip.h"
00040 #include <assert.h>
00041
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00054
00055 extern void HSMCI_Enable(Hsmci* pRMci)
00056 {
00057 pRMci->HSMCI_CR = HSMCI_CR_MCIEN;
00058 }
00059
00060
00061
00062
00063
00064
00065 extern void HSMCI_Disable(Hsmci* pRMci)
00066 {
00067 pRMci->HSMCI_CR = HSMCI_CR_MCIDIS;
00068
00069 }
00070
00071
00072
00073
00074
00075
00076
00077
00078 extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup)
00079 {
00080 if (bBackup) {
00081 uint32_t mr = pRMci->HSMCI_MR;
00082 uint32_t dtor = pRMci->HSMCI_DTOR;
00083 uint32_t sdcr = pRMci->HSMCI_SDCR;
00084 uint32_t cstor = pRMci->HSMCI_CSTOR;
00085 uint32_t dma = pRMci->HSMCI_DMA;
00086 uint32_t cfg = pRMci->HSMCI_CFG;
00087
00088 pRMci->HSMCI_CR = HSMCI_CR_SWRST;
00089
00090 pRMci->HSMCI_MR = mr;
00091 pRMci->HSMCI_DTOR = dtor;
00092 pRMci->HSMCI_SDCR = sdcr;
00093 pRMci->HSMCI_CSTOR = cstor;
00094 pRMci->HSMCI_DMA = dma;
00095 pRMci->HSMCI_CFG = cfg;
00096 } else {
00097 pRMci->HSMCI_CR = HSMCI_CR_SWRST;
00098 }
00099 }
00100
00101
00102
00103
00104
00105
00106 extern void HSMCI_Select(Hsmci *pRMci, uint8_t bSlot, uint8_t bBusWidth)
00107 {
00108 uint32_t dwSdcr;
00109 dwSdcr = (HSMCI_SDCR_SDCSEL_Msk & bSlot);
00110 switch(bBusWidth) {
00111 case 1:
00112 pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1;
00113 break;
00114 case 4:
00115 pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4;
00116 break;
00117 case 8:
00118 pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8;
00119 break;
00120 }
00121 }
00122
00123
00124
00125
00126
00127
00128 extern void HSMCI_SetSlot(Hsmci *pRMci, uint8_t bSlot)
00129 {
00130 uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCSEL_Msk;
00131 pRMci->HSMCI_SDCR = dwSdcr | (HSMCI_SDCR_SDCSEL_Msk & bSlot);
00132 }
00133
00134
00135
00136
00137
00138
00139 extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth)
00140 {
00141 uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk;
00142 switch(bBusWidth) {
00143 case 1:
00144 pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1;
00145 break;
00146 case 4:
00147 pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4;
00148 break;
00149 case 8:
00150 pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8;
00151 break;
00152 }
00153 }
00154
00155
00156
00157
00158
00159
00160
00161 extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci)
00162 {
00163 switch(pRMci->HSMCI_SDCR & HSMCI_SDCR_SDCBUS_Msk) {
00164 case HSMCI_SDCR_SDCBUS_1: return 1;
00165 case HSMCI_SDCR_SDCBUS_4: return 4;
00166 case HSMCI_SDCR_SDCBUS_8: return 8;
00167 }
00168 return 0;
00169 }
00170
00171
00172
00173
00174
00175
00176
00177 extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode)
00178 {
00179 pRMci->HSMCI_MR = dwMode;
00180
00181 }
00182
00183
00184
00185
00186
00187 extern uint32_t HSMCI_GetMode(Hsmci * pRMci)
00188 {
00189 return pRMci->HSMCI_MR;
00190 }
00191
00192
00193
00194
00195
00196
00197
00198
00199 extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof)
00200 {
00201 uint32_t mr = pRMci->HSMCI_MR;
00202 pRMci->HSMCI_MR = (mr & (~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF)))
00203 | (bRdProof ? HSMCI_MR_RDPROOF : 0)
00204 | (bWrProof ? HSMCI_MR_WRPROOF : 0)
00205 ;
00206 }
00207
00208
00209
00210
00211
00212
00213
00214 extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv)
00215 {
00216 if (bPadv) {
00217 pRMci->HSMCI_MR |= HSMCI_MR_PADV;
00218 } else {
00219 pRMci->HSMCI_MR &= ~HSMCI_MR_PADV;
00220 }
00221 }
00222
00223
00224
00225
00226
00227
00228
00229 extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn)
00230 {
00231 if (bFByteEn) {
00232 pRMci->HSMCI_MR |= HSMCI_MR_FBYTE;
00233 } else {
00234 pRMci->HSMCI_MR &= ~HSMCI_MR_FBYTE;
00235 }
00236 }
00237
00238
00239
00240
00241
00242
00243
00244 extern uint8_t HSMCI_IsFByteEnabled(Hsmci *pRMci)
00245 {
00246 return ((pRMci->HSMCI_MR & HSMCI_MR_FBYTE) > 0);
00247 }
00248
00249
00250
00251
00252
00253
00254
00255
00256 extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv)
00257 {
00258 uint32_t mr = pRMci->HSMCI_MR;
00259 uint32_t clkdiv ,clkodd;
00260 clkdiv = bClkDiv - 2 ;
00261 clkodd = (bClkDiv & 1)? HSMCI_MR_CLKODD: 0;
00262 clkdiv = clkdiv >> 1;
00263
00264 pRMci->HSMCI_MR = (mr & ~(HSMCI_MR_CLKDIV_Msk | HSMCI_MR_PWSDIV_Msk))
00265 | HSMCI_MR_CLKDIV(clkdiv)
00266 | HSMCI_MR_PWSDIV(bPwsDiv)
00267 | clkodd
00268 ;
00269 }
00270
00271
00272
00273
00274
00275
00276
00277 extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources)
00278 {
00279 pRMci->HSMCI_IER = dwSources;
00280 }
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00287
00288 extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources)
00289 {
00290 pRMci->HSMCI_IDR = dwSources;
00291 }
00292
00293
00294
00295
00296
00297
00298
00299 extern uint32_t HSMCI_GetItMask(Hsmci *pRMci)
00300 {
00301 return (pRMci->HSMCI_IMR) ;
00302 }
00303
00304
00305
00306
00307
00308
00309
00310
00311 extern void HSMCI_ConfigureTransfer(Hsmci *pRMci,
00312 uint16_t wBlkLen,
00313 uint16_t wCnt)
00314 {
00315 pRMci->HSMCI_BLKR = (wBlkLen << 16) | wCnt;
00316 }
00317
00318
00319
00320
00321
00322
00323
00324
00325
00326 extern void HSMCI_SetBlockLen(Hsmci *pRMci, uint16_t wBlkSize)
00327 {
00328 pRMci->HSMCI_BLKR = wBlkSize << 16;
00329 }
00330
00331
00332
00333
00334
00335
00336
00337 extern void HSMCI_SetBlockCount(Hsmci *pRMci, uint16_t wBlkCnt)
00338 {
00339 pRMci->HSMCI_BLKR |= wBlkCnt;
00340 }
00341
00342
00343
00344
00345
00346
00347
00348 extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure)
00349 {
00350 pRMci->HSMCI_CSTOR = dwConfigure;
00351 }
00352
00353
00354
00355
00356
00357
00358
00359 extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure)
00360 {
00361 pRMci->HSMCI_DTOR = dwConfigure;
00362 }
00363
00364
00365
00366
00367
00368
00369
00370
00371 extern void HSMCI_SendCmd(Hsmci *pRMci, uint32_t dwCmd, uint32_t dwArg)
00372 {
00373 pRMci->HSMCI_ARGR = dwArg;
00374 pRMci->HSMCI_CMDR = dwCmd;
00375 }
00376
00377
00378
00379
00380
00381
00382
00383
00384 extern uint32_t HSMCI_GetResponse(Hsmci *pRMci)
00385 {
00386 return pRMci->HSMCI_RSPR[0];
00387 }
00388
00389
00390
00391
00392
00393
00394
00395 extern uint32_t HSMCI_Read(Hsmci *pRMci)
00396 {
00397 return pRMci->HSMCI_RDR;
00398 }
00399
00400
00401
00402
00403
00404
00405
00406
00407 extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize)
00408 {
00409 volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO);
00410 register uint32_t c4, c1;
00411
00412 if (dwSize == 0)
00413 return;
00414
00415 c4 = dwSize >> 2;
00416 c1 = dwSize & 0x3;
00417
00418 for(;c4;c4 --) {
00419 *pdwData ++ = *pFIFO ++;
00420 *pdwData ++ = *pFIFO ++;
00421 *pdwData ++ = *pFIFO ++;
00422 *pdwData ++ = *pFIFO ++;
00423 }
00424 for(;c1;c1 --) {
00425 *pdwData ++ = *pFIFO ++;
00426 }
00427 }
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00434
00435 extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData)
00436 {
00437 pRMci->HSMCI_TDR = dwData;
00438 }
00439
00440
00441
00442
00443
00444
00445
00446
00447 extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize)
00448 {
00449 volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO);
00450 register uint32_t c4, c1;
00451
00452 if (dwSize == 0)
00453 return;
00454
00455 c4 = dwSize >> 2;
00456 c1 = dwSize & 0x3;
00457
00458 for(;c4;c4 --) {
00459 *pFIFO ++ = *pdwData ++;
00460 *pFIFO ++ = *pdwData ++;
00461 *pFIFO ++ = *pdwData ++;
00462 *pFIFO ++ = *pdwData ++;
00463 }
00464 for(;c1;c1 --) {
00465 *pFIFO ++ = *pdwData ++;
00466 }
00467 }
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00474
00475 extern uint32_t HSMCI_GetStatus(Hsmci *pRMci)
00476 {
00477 return pRMci->HSMCI_SR;
00478 }
00479
00480
00481
00482
00483
00484
00485
00486 extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure)
00487 {
00488 pRMci->HSMCI_DMA = dwConfigure;
00489 }
00490
00491
00492
00493
00494
00495
00496
00497 extern void HSMCI_EnableDma(Hsmci *pRMci, uint8_t bEnable)
00498 {
00499 if (bEnable) {
00500 pRMci->HSMCI_DMA |= HSMCI_DMA_DMAEN ;
00501 } else {
00502 pRMci->HSMCI_DMA &= ~HSMCI_DMA_DMAEN;
00503 }
00504 }
00505
00506
00507
00508
00509
00510
00511
00512 extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure)
00513 {
00514 pRMci->HSMCI_CFG = dwConfigure;
00515 }
00516
00517
00518
00519
00520
00521
00522
00523 extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable)
00524 {
00525 if (bHsEnable) {
00526 pRMci->HSMCI_CFG |= HSMCI_CFG_HSMODE;
00527 } else {
00528 pRMci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE;
00529 }
00530 }
00531
00532
00533
00534
00535
00536
00537 extern uint8_t HSMCI_IsHsEnabled(Hsmci * pRMci)
00538 {
00539 return ((pRMci->HSMCI_CFG & HSMCI_CFG_HSMODE) > 0);
00540 }
00541
00542
00543
00544
00545
00546
00547
00548 extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure)
00549 {
00550 pRMci->HSMCI_WPMR = dwConfigure;
00551 }
00552
00553
00554
00555
00556
00557
00558
00559 extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci)
00560 {
00561 return pRMci->HSMCI_WPSR;
00562 }
00563
00564
00565