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00030 #ifndef _YUV_H_
00031 #define _YUV_H_
00032
00033
00034
00035
00036
00037
00038
00039 #define OV_I2C_SENSOR_ADDRESS (0x42u >> 1)
00040
00041
00042
00043
00044 #define OV7740_GAIN (0x00u)
00045
00046
00047 #define OV7740_BLUE_GAIN (0x01u)
00048
00049
00050 #define OV7740_RED_GAIN (0x02u)
00051
00052
00053 #define OV7740_GREEN_GAIN (0x03u)
00054
00055
00056 #define OV7740_REG04 (0x04u)
00057
00058
00059 #define OV7740_BLUE_AVG (0x05u)
00060
00061
00062 #define OV7740_GREEN_AVG (0x06u)
00063
00064
00065 #define OV7740_RED_AVG (0x07u)
00066
00067
00068 #define OV7740_PIDH (0x0au)
00069 #define OV7740_PIDH_DEFAULT (0x77u << 0)
00070
00071
00072 #define OV7740_PIDL (0x0bu)
00073 #define OV7740_PIDL_DEFAULT (0x40u << 0)
00074
00075
00076 #define OV7740_REG0C (0x0c)
00077 #define OV7740_REG0C_MAX_EXPOSURE_Pos (1)
00078
00079 #define OV7740_REG0C_MAX_EXPOSURE_Msk (0x3u << OV7740_REG0C_MAX_EXPOSURE_Pos)
00080 #define OV7740_REG0C_MAX_EXPOSURE(value) \
00081 ((OV7740_REG0C_MAX_EXPOSURE_Msk & ((value) << OV7740_REG0C_MAX_EXPOSURE_Pos)))
00082
00083 #define OV7740_REG0C_BYTE_SWAP_Msk (0x1u << 3)
00084
00085 #define OV7740_REG0C_BYTE_SWAP_DISABLE (0x0u << 3)
00086
00087 #define OV7740_REG0C_BYTE_SWAP_ENABLE (0x1u << 3)
00088
00089 #define OV7740_REG0C_YUV_SWAP_Msk (0x1u << 4)
00090
00091 #define OV7740_REG0C_YUV_SWAP_DISABLE (0x0u << 4)
00092
00093 #define OV7740_REG0C_YUV_SWAP_ENABLE (0x1u << 4)
00094
00095 #define OV7740_REG0C_MIRROR_ENABLE (0x1u << 6)
00096
00097 #define OV7740_REG0C_FLIP_ENABLE (0x1u << 7)
00098
00099
00100 #define OV7740_REG0D (0x0du)
00101
00102
00103
00104 #define OV7740_REG0E (0x0eu)
00105 #define OV7740_REG0E_OUTPUT_Pos (0)
00106
00107 #define OV7740_REG0E_OUTPUT_Msk (0x3u << OV7740_REG0E_OUTPUT_Pos)
00108
00109 #define OV7740_REG0E_OUTPUT_1X (0x0u << OV7740_REG0E_OUTPUT_Pos)
00110
00111 #define OV7740_REG0E_OUTPUT_2X (0x1u << OV7740_REG0E_OUTPUT_Pos)
00112
00113 #define OV7740_REG0E_OUTPUT_3X (0x2u << OV7740_REG0E_OUTPUT_Pos)
00114
00115 #define OV7740_REG0E_OUTPUT_4X (0x3u << OV7740_REG0E_OUTPUT_Pos)
00116
00117 #define OV7740_REG0E_SLEEP_MODE (0x1u << 3)
00118 #define OV7740_REG0E_BLC_Pos (5)
00119
00120 #define OV7740_REG0E_BLC_Msk (0x3u << OV7740_REG0E_BLC_Pos)
00121
00122 #define OV7740_REG0E_BLC_BOTH0 (0x0u << OV7740_REG0E_BLC_Pos)
00123
00124 #define OV7740_REG0E_BLC_RED (0x1u << OV7740_REG0E_BLC_Pos)
00125
00126 #define OV7740_REG0E_BLC_BLUE (0x2u << OV7740_REG0E_BLC_Pos)
00127
00128 #define OV7740_REG0E_BLC_BOTH (0x3u << OV7740_REG0E_BLC_Pos)
00129
00130 #define OV7740_REG0E_BLC_LINE_Msk (0x1u << 7)
00131
00132 #define OV7740_REG0E_BLC_LINE_ELECTRICAL (0x0u << 7)
00133
00134 #define OV7740_REG0E_BLC_LINE_OPTICAL (0x1u << 7)
00135
00136
00137 #define OV7740_HAEC (0x0fu)
00138
00139
00140 #define OV7740_AEC (0x10u)
00141
00142
00143
00144 #define OV7740_CLK (0x11u)
00145 #define OV7740_CLK_DIVIDER_Pos (0)
00146
00147 #define OV7740_CLK_DIVIDER_Msk (0x3fu << OV7740_CLK_DIVIDER_Pos)
00148 #define OV7740_CLK_DIVIDER(value) \
00149 ((OV7740_CLK_DIVIDER_Msk & ((value) << OV7740_CLK_DIVIDER_Pos)))
00150 #define OV7740_CLK_PLL_Pos (6)
00151
00152 #define OV7740_CLK_PLL_Msk (0x3u << OV7740_CLK_PLL_Pos)
00153 #define OV7740_CLK_PLL(value) \
00154 ((OV7740_CLK_PLL_Msk & ((value) << OV7740_CLK_PLL_Pos)))
00155
00156 #define FRAME_RATE_60 0x00
00157 #define FRAME_RATE_30 0x01
00158 #define FRAME_RATE_20 0x02
00159 #define FRAME_RATE_15 0x03
00160 #define FRAME_RATE_10 0x05
00161 #define FRAME_RATE_7 0x07
00162 #define PLL_DIV_DEFAULT 0x40
00163 #define FRAME_RATE_7_MCK_132 0x0A
00164 #define PLL_DIV_7_MCK_132 0xC0
00165
00166
00167 #define OV7740_REG12 (0x12u)
00168 #define OV7740_REG12_RAW_RGB (0x1u << 0)
00169 #define OV7740_REG12_SENSOR_RAW (0x1u << 4)
00170 #define OV7740_REG12_CC656_MODE (0x1u << 5)
00171 #define OV7740_REG12_VSKIP (0x1u << 6)
00172 #define OV7740_REG12_RESET (0x1u << 7)
00173
00174
00175 #define OV7740_REG13 (0x13u)
00176
00177 #define OV7740_REG13_EXPOSURE_Msk (0x01u << 0)
00178 #define OV7740_REG13_EXPOSURE_MANUAL (0x0u << 0)
00179 #define OV7740_REG13_EXPOSURE_AUTO (0x1u << 0)
00180
00181 #define OV7740_REG13_WBAL_Msk (0x1u << 1)
00182 #define OV7740_REG13_WBAL_MANUAL (0x0u << 1)
00183 #define OV7740_REG13_WBAL_AUTO (0x1u << 1)
00184
00185 #define OV7740_REG13_AGC_Msk (0x1u << 2)
00186 #define OV7740_REG13_AGC_MANUAL (0x0u << 2)
00187 #define OV7740_REG13_AGC_AUTO (0x1u << 2)
00188
00189 #define OV7740_REG13_LAEC_Msk (0x1u << 3)
00190 #define OV7740_REG13_LAEC_DISABLE (0x0u << 3)
00191 #define OV7740_REG13_LAEC_ENABLE (0x1u << 3)
00192
00193 #define OV7740_REG13_BANDING_OPT_Msk (0x1u << 4)
00194
00195
00196 #define OV7740_REG13_BANDING_OPT_LIMITED (0x0u << 4)
00197
00198
00199 #define OV7740_REG13_BANDING_OPT_ENABLE (0x1u << 4)
00200
00201 #define OV7740_REG13_BANDING_Mask (0x1u << 5)
00202 #define OV7740_REG13_BANDING_DISABLE (0x0u << 5)
00203 #define OV7740_REG13_BANDING_ENABLE (0x1u << 5)
00204
00205 #define OV7740_REG13_FRAME_DROP_Mask (0x1u << 6)
00206 #define OV7740_REG13_FRAME_DROP_DISABLE (0x0u << 6)
00207 #define OV7740_REG13_FRAME_DROP_ENABLE (0x1u << 6)
00208
00209 #define OV7740_REG13_AEC_Mask (0x1u << 7)
00210
00211 #define OV7740_REG13_AEC_NORMAL (0x0u << 7)
00212
00213 #define OV7740_REG13_AEC_FASTER (0x1u << 7)
00214
00215
00216 #define OV7740_REG14 (0x14u)
00217
00218
00219 #define OV7740_REG15 (0x15u)
00220 #define OV7740_REG15_GAIN_Pos (0)
00221
00222 #define OV7740_REG15_GAIN_Msk (0x3u << OV7740_REG15_GAIN_Pos)
00223 #define OV7740_REG15_GAIN(value) \
00224 ((OV7740_REG15_GAIN_Msk & ((value) << OV7740_REG15_GAIN_Pos)))
00225
00226 #define OV7740_REG15_NIGHT_Mask (0x3u << 2)
00227
00228 #define OV7740_REG15_NIGHT_2X_GAIN (0x0u << 2)
00229
00230 #define OV7740_REG15_NIGHT_4X_GAIN (0x1u << 2)
00231
00232 #define OV7740_REG15_NIGHT_8X_GAIN (0x2u << 2)
00233
00234 #define OV7740_REG15_NIGHT_16X_GAIN (0x3u << 2)
00235
00236 #define OV7740_REG15_CEIL_Mask (0x3u << 4)
00237
00238 #define OV7740_REG15_CEIL_0 (0x0u << 4)
00239
00240 #define OV7740_REG15_CEIL_1 (0x1u << 4)
00241
00242 #define OV7740_REG15_CEIL_2 (0x2u << 4)
00243
00244 #define OV7740_REG15_CEIL_3 (0x3u << 4)
00245
00246 #define OV7740_REG15_CEIL_7 (0x7u << 4)
00247
00248 #define OV7740_REG15_ENABLE_NIGHT (0x1u << 7)
00249
00250
00251 #define OV7740_REG16 (0x16u)
00252
00253
00254
00255
00256
00257 #define OV7740_AHSTART (0x17u)
00258
00259
00260
00261
00262
00263 #define OV7740_AHSIZE (0x18u)
00264
00265
00266
00267
00268
00269 #define OV7740_AVSTART (0x19u)
00270
00271
00272
00273
00274
00275 #define OV7740_AVSIZE (0x1au)
00276
00277
00278 #define OV7740_PIXEL_SHIFT (0x1bu)
00279
00280
00281 #define OV7740_MIDH (0x1cu)
00282 #define OV7740_MIDH_DEFAULT (0x7fu << 0)
00283
00284
00285 #define OV7740_MIDL (0x1du)
00286 #define OV7740_MIDL_DEFAULT (0xa2u << 0)
00287
00288
00289 #define OV7740_REG1E (0x1eu)
00290
00291
00292 #define OV7740_REG1F (0x1fu)
00293
00294
00295 #define OV7740_REG1E (0x1eu)
00296
00297
00298 #define OV7740_REG20 (0x20u)
00299
00300
00301 #define OV7740_REG21 (0x21u)
00302
00303
00304
00305
00306 #define OV7740_WPT (0x24u)
00307
00308
00309
00310
00311
00312 #define OV7740_BPT (0x25u)
00313
00314
00315 #define OV7740_VPT (0x26u)
00316
00317
00318 #define OV7740_REG27 (0x27u)
00319
00320 #define OV7740_REG27_BLACKSUN (0x1u << 7)
00321
00322
00323 #define OV7740_REG28 (0x28u)
00324
00325 #define OV7740_REG28_VSYNC_Msk (0x1u << 1)
00326
00327 #define OV7740_REG28_VSYNC_POSITIVE (0x1u << 0)
00328
00329 #define OV7740_REG28_VSYNC_NEGATIVE (0x1u << 1)
00330
00331 #define OV7740_REG28_VSYNC_OUTPUT_Msk (0x1u << 3)
00332
00333 #define OV7740_REG28_VSYNC_OUTPUT_STILL (0x0u << 3)
00334
00335 #define OV7740_REG28_VSYNC_OUTPUT_NONE (0x1u << 3)
00336
00337 #define OV7740_REG28_HREF_Msk (0x1u << 4)
00338
00339 #define OV7740_REG28_HREF_POSITIVE (0x0u << 4)
00340
00341 #define OV7740_REG28_HREF_NEGATIVE (0x1u << 4)
00342
00343 #define OV7740_REG28_HSYNC_Msk (0x1u << 5)
00344
00345 #define OV7740_REG28_HSYNC_POSITIVE (0x0u << 5)
00346
00347 #define OV7740_REG28_HSYNC_NEGATIVE (0x1u << 5)
00348
00349 #define OV7740_REG28_HREF_OUTPUT_Msk (0x1u << 6)
00350
00351 #define OV7740_REG28_HREF_OUTPUT_HREF (0x0u << 6)
00352
00353 #define OV7740_REG28_HREF_OUTPUT_HSYNC (0x1u << 6)
00354
00355 #define OV7740_REG28_OUTPUT_REVERSE (0x1u << 7)
00356
00357
00358 #define OV7740_REG65 (0x65u)
00359
00360 #define OV7740_REG65_BIT_SWAP_Msk (0x1u << 3)
00361
00362 #define OV7740_REG65_BIT_SWAP_NORMAL (0x0u << 3)
00363
00364 #define OV7740_REG65_BIT_SWAP_REVERSE (0x1u << 3)
00365
00366
00367 #define OV7740_YUV422CTRL (0xd9u)
00368
00369 #define OV7740_YUV422CTRL_CNV_OPT_Msk (0x1u << 0)
00370
00371 #define OV7740_YUV422CTRL_CNV_OPT_AVERAGE (0x0u << 0)
00372
00373 #define OV7740_YUV422CTRL_CNV_OPT_DROP (0x1u << 0)
00374
00375
00376 #define OV7740_YUV422CTRL_V_FIRST_Msk (0x1u << 1)
00377
00378 #define OV7740_YUV422CTRL_V_FIRST_YUYV (0x0u << 1)
00379
00380
00381
00382 #define OV7740_YUV422CTRL_V_FIRST_YVYU (0x1u << 1)
00383
00384
00385
00386 #endif // #ifndef _YUV_H_
00387