00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_DACC_COMPONENT_ 00031 #define _SAMV71_DACC_COMPONENT_ 00032 00033 /* ============================================================================= */ 00034 /** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ 00035 /* ============================================================================= */ 00036 /** \addtogroup SAMV71_DACC Digital-to-Analog Converter Controller */ 00037 /*@{*/ 00038 00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00040 /** \brief Dacc hardware registers */ 00041 typedef struct { 00042 __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ 00043 __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ 00044 __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ 00045 __I uint32_t Reserved1[1]; 00046 __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ 00047 __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ 00048 __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ 00049 __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ 00050 __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ 00051 __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ 00052 __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ 00053 __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ 00054 __I uint32_t Reserved2[24]; 00055 __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ 00056 __I uint32_t Reserved3[19]; 00057 __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */ 00058 __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */ 00059 } Dacc; 00060 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00061 /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ 00062 #define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ 00063 /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ 00064 #define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ 00065 #define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */ 00066 #define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */ 00067 #define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ 00068 #define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */ 00069 #define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */ 00070 #define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ 00071 #define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */ 00072 #define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */ 00073 #define DACC_MR_REFRESH_Pos 8 00074 #define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ 00075 #define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) 00076 #define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ 00077 #define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */ 00078 #define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */ 00079 #define DACC_MR_PRESCALER_Pos 24 00080 #define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ 00081 #define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) 00082 /* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ 00083 #define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ 00084 #define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ 00085 #define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ 00086 #define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ 00087 #define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ 00088 #define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ 00089 #define DACC_TRIGR_TRGSEL0_Pos 4 00090 #define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ 00091 #define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) 00092 #define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ 00093 #define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ 00094 #define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ 00095 #define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ 00096 #define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ 00097 #define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ 00098 #define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ 00099 #define DACC_TRIGR_TRGSEL1_Pos 8 00100 #define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ 00101 #define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) 00102 #define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ 00103 #define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ 00104 #define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ 00105 #define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ 00106 #define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ 00107 #define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ 00108 #define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ 00109 #define DACC_TRIGR_OSR0_Pos 16 00110 #define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ 00111 #define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) 00112 #define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ 00113 #define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ 00114 #define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ 00115 #define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ 00116 #define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ 00117 #define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ 00118 #define DACC_TRIGR_OSR1_Pos 20 00119 #define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ 00120 #define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) 00121 #define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ 00122 #define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ 00123 #define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ 00124 #define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ 00125 #define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ 00126 #define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ 00127 /* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ 00128 #define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ 00129 #define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ 00130 /* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ 00131 #define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ 00132 #define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ 00133 /* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ 00134 #define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ 00135 #define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ 00136 #define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */ 00137 #define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */ 00138 /* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ 00139 #define DACC_CDR_DATA0_Pos 0 00140 #define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ 00141 #define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) 00142 #define DACC_CDR_DATA1_Pos 16 00143 #define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ 00144 #define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) 00145 /* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ 00146 #define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ 00147 #define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ 00148 #define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ 00149 #define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ 00150 #define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */ 00151 #define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */ 00152 #define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */ 00153 #define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */ 00154 /* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ 00155 #define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ 00156 #define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ 00157 #define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ 00158 #define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ 00159 #define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */ 00160 #define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */ 00161 #define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */ 00162 #define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */ 00163 /* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ 00164 #define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ 00165 #define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ 00166 #define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ 00167 #define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ 00168 #define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */ 00169 #define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */ 00170 #define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */ 00171 #define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */ 00172 /* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ 00173 #define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ 00174 #define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ 00175 #define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ 00176 #define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ 00177 #define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */ 00178 #define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */ 00179 #define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */ 00180 #define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */ 00181 /* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ 00182 #define DACC_ACR_IBCTLCH0_Pos 0 00183 #define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ 00184 #define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) 00185 #define DACC_ACR_IBCTLCH1_Pos 2 00186 #define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ 00187 #define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) 00188 /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */ 00189 #define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ 00190 #define DACC_WPMR_WPKEY_Pos 8 00191 #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ 00192 #define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) 00193 #define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ 00194 /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */ 00195 #define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ 00196 #define DACC_WPSR_WPVSRC_Pos 8 00197 #define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ 00198 00199 /*@}*/ 00200 00201 00202 #endif /* _SAMV71_DACC_COMPONENT_ */