00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_PMC_INSTANCE_ 00031 #define _SAMV71_PMC_INSTANCE_ 00032 00033 /* ========== Register definition for PMC peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ 00036 #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ 00037 #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ 00038 #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ 00039 #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ 00040 #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ 00041 #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ 00042 #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ 00043 #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ 00044 #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ 00045 #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ 00046 #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ 00047 #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ 00048 #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ 00049 #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ 00050 #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ 00051 #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ 00052 #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ 00053 #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ 00054 #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ 00055 #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ 00056 #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ 00057 #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ 00058 #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ 00059 #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ 00060 #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ 00061 #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ 00062 #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ 00063 #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ 00064 #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ 00065 #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ 00066 #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ 00067 #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ 00068 #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ 00069 #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ 00070 #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ 00071 #else 00072 #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ 00073 #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ 00074 #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ 00075 #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ 00076 #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ 00077 #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ 00078 #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ 00079 #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ 00080 #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ 00081 #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */ 00082 #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ 00083 #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ 00084 #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ 00085 #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ 00086 #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ 00087 #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */ 00088 #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ 00089 #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ 00090 #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ 00091 #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ 00092 #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ 00093 #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ 00094 #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ 00095 #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ 00096 #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ 00097 #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ 00098 #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ 00099 #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ 00100 #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ 00101 #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ 00102 #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ 00103 #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ 00104 #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ 00105 #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ 00106 #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ 00107 #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ 00108 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00109 00110 #endif /* _SAMV71_PMC_INSTANCE_ */