00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036
00037
00038
00039
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059 #include "chip.h"
00060
00061
00062
00063
00064
00065
00066 #define USE_SPI_DMA
00067
00068
00069 #define DMA_SPI_LLI 2
00070
00071
00072
00073
00074
00075
00076
00077
00078
00079
00080
00081 static uint32_t spiDmaTxChannel;
00082 static uint32_t spiDmaRxChannel;
00083
00084
00085
00086
00087
00088
00089
00090
00091
00092
00093
00094 static void SPID_Rx_Cb(uint32_t channel, Spid* pArg)
00095 {
00096 SpidCmd *pSpidCmd = pArg->pCurrentCommand;
00097 Spi *pSpiHw = pArg->pSpiHw;
00098 if (channel != spiDmaRxChannel)
00099 return;
00100
00101
00102 SPI_Disable ( pSpiHw );
00103 TRACE_INFO("SPI Rx DMA Callback has been called %d bytes received\n\r",
00104 pArg->pCurrentCommand->RxSize);
00105
00106 NVIC_ClearPendingIRQ(XDMAC_IRQn);
00107 NVIC_DisableIRQ(XDMAC_IRQn);
00108
00109
00110 PMC_DisablePeripheral ( pArg->spiId );
00111
00112
00113 SPI_ReleaseCS(pSpiHw);
00114
00115
00116 XDMAD_FreeChannel(pArg->pXdmad, spiDmaRxChannel);
00117 XDMAD_FreeChannel(pArg->pXdmad, spiDmaTxChannel);
00118 SCB_CleanInvalidateDCache();
00119
00120 pArg->semaphore++;
00121
00122 printf(" %s\n\r",pArg->pCurrentCommand->pRxBuff);
00123
00124
00125 if (pSpidCmd && pSpidCmd->callback) {
00126
00127 pSpidCmd->callback(0, pSpidCmd->pArgument);
00128 }
00129 }
00130
00131
00132
00133
00134
00135
00136
00137 static uint8_t _spid_configureDmaChannels( Spid* pSpid )
00138 {
00139
00140 XDMAD_Initialize( pSpid->pXdmad, 0 );
00141
00142 XDMAD_FreeChannel( pSpid->pXdmad, spiDmaTxChannel);
00143 XDMAD_FreeChannel( pSpid->pXdmad, spiDmaRxChannel);
00144
00145
00146 spiDmaTxChannel = XDMAD_AllocateChannel( pSpid->pXdmad,
00147 XDMAD_TRANSFER_MEMORY, pSpid->spiId);
00148 if ( spiDmaTxChannel == XDMAD_ALLOC_FAILED ) {
00149 return SPID_ERROR;
00150 }
00151
00152 spiDmaRxChannel =
00153 XDMAD_AllocateChannel( pSpid->pXdmad, pSpid->spiId, XDMAD_TRANSFER_MEMORY);
00154 if ( spiDmaRxChannel == XDMAD_ALLOC_FAILED ) {
00155 return SPID_ERROR;
00156 }
00157
00158
00159 XDMAD_SetCallback(pSpid->pXdmad, spiDmaRxChannel,
00160 (XdmadTransferCallback)SPID_Rx_Cb, pSpid);
00161 if (XDMAD_PrepareChannel( pSpid->pXdmad, spiDmaRxChannel ))
00162 return SPID_ERROR;
00163
00164
00165 XDMAD_SetCallback(pSpid->pXdmad, spiDmaTxChannel, NULL, NULL);
00166 if ( XDMAD_PrepareChannel( pSpid->pXdmad, spiDmaTxChannel ))
00167 return SPID_ERROR;
00168 return 0;
00169 }
00170
00171
00172
00173
00174
00175
00176
00177
00178 static uint8_t _spid_configureLinkList(Spi *pSpiHw, void *pXdmad, SpidCmd *pCommand)
00179 {
00180 sXdmadCfg xdmadRxCfg,xdmadTxCfg;
00181 uint32_t xdmaCndc, xdmaInt;
00182 uint32_t spiId;
00183 if ((unsigned int)pSpiHw == (unsigned int)SPI0 ) spiId = ID_SPI0;
00184 if ((unsigned int)pSpiHw == (unsigned int)SPI1 ) spiId = ID_SPI1;
00185
00186
00187
00188 xdmadTxCfg.mbr_sa = (uint32_t)pCommand->pTxBuff;
00189
00190 xdmadTxCfg.mbr_da = (uint32_t)&pSpiHw->SPI_TDR;
00191
00192 xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
00193 XDMA_UBC_NDE_FETCH_DIS|
00194 XDMA_UBC_NSEN_UPDATED | pCommand->TxSize;
00195
00196 xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
00197 XDMAC_CC_MBSIZE_SINGLE |
00198 XDMAC_CC_DSYNC_MEM2PER |
00199 XDMAC_CC_CSIZE_CHK_1 |
00200 XDMAC_CC_DWIDTH_BYTE|
00201 XDMAC_CC_SIF_AHB_IF0 |
00202 XDMAC_CC_DIF_AHB_IF1 |
00203 XDMAC_CC_SAM_INCREMENTED_AM |
00204 XDMAC_CC_DAM_FIXED_AM |
00205 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( spiId, XDMAD_TRANSFER_TX ));
00206
00207
00208 xdmadTxCfg.mbr_bc = 0;
00209 xdmadTxCfg.mbr_sus = 0;
00210 xdmadTxCfg.mbr_dus =0;
00211
00212
00213
00214 xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 |
00215 XDMA_UBC_NDE_FETCH_DIS|
00216 XDMA_UBC_NDEN_UPDATED | pCommand->RxSize;
00217
00218 xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff;
00219
00220 xdmadRxCfg.mbr_sa = (uint32_t)&pSpiHw->SPI_RDR;
00221 xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN |
00222 XDMAC_CC_MBSIZE_SINGLE |
00223 XDMAC_CC_DSYNC_PER2MEM |
00224 XDMAC_CC_CSIZE_CHK_1 |
00225 XDMAC_CC_DWIDTH_BYTE|
00226 XDMAC_CC_SIF_AHB_IF1 |
00227 XDMAC_CC_DIF_AHB_IF0 |
00228 XDMAC_CC_SAM_FIXED_AM |
00229 XDMAC_CC_DAM_INCREMENTED_AM |
00230 XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( spiId, XDMAD_TRANSFER_RX ));
00231
00232
00233 xdmadRxCfg.mbr_bc = 0;
00234 xdmadRxCfg.mbr_sus = 0;
00235 xdmadRxCfg.mbr_dus =0;
00236
00237 xdmaCndc = 0;
00238
00239
00240 xdmaInt = (XDMAC_CIE_BIE |
00241 XDMAC_CIE_DIE |
00242 XDMAC_CIE_FIE |
00243 XDMAC_CIE_RBIE |
00244 XDMAC_CIE_WBIE |
00245 XDMAC_CIE_ROIE);
00246
00247 if (XDMAD_ConfigureTransfer( pXdmad, spiDmaRxChannel, &xdmadRxCfg, xdmaCndc, 0, xdmaInt))
00248 return SPID_ERROR;
00249
00250 if (XDMAD_ConfigureTransfer( pXdmad, spiDmaTxChannel, &xdmadTxCfg, xdmaCndc, 0, xdmaInt))
00251 return SPID_ERROR;
00252 return 0;
00253 }
00254
00255
00256
00257
00258
00259
00260
00261
00262
00263
00264
00265
00266
00267
00268
00269
00270 uint32_t SPID_Configure( Spid *pSpid ,
00271 Spi *pSpiHw ,
00272 uint8_t spiId,
00273 uint32_t spiMode,
00274 sXdmad *pXdmad )
00275 {
00276
00277 pSpid->pSpiHw = pSpiHw;
00278 pSpid->spiId = spiId;
00279 pSpid->semaphore = 1;
00280 pSpid->pCurrentCommand = 0;
00281 pSpid->pXdmad = pXdmad;
00282
00283
00284
00285 SPI_Configure ( pSpiHw, pSpid->spiId, spiMode );
00286
00287 return 0;
00288 }
00289
00290
00291
00292
00293
00294
00295
00296
00297 void SPID_ConfigureCS( Spid *pSpid,
00298 uint32_t dwCS,
00299 uint32_t dwCsr)
00300 {
00301 Spi *pSpiHw = pSpid->pSpiHw;
00302
00303
00304 PMC_EnablePeripheral (pSpid->spiId );
00305
00306 SPI_ConfigureNPCS( pSpiHw, dwCS, dwCsr );
00307
00308
00309 PMC_DisablePeripheral (pSpid->spiId );
00310
00311 }
00312
00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323 uint32_t SPID_SendCommand( Spid *pSpid, SpidCmd *pCommand)
00324 {
00325 Spi *pSpiHw = pSpid->pSpiHw;
00326
00327
00328 if (pSpid->semaphore == 0) {
00329 return SPID_ERROR_LOCK;
00330 }
00331 pSpid->semaphore--;
00332
00333
00334 PMC_EnablePeripheral (pSpid->spiId );
00335
00336
00337 SPI_ChipSelect (pSpiHw, 1 << pCommand->spiCs);
00338
00339
00340 pSpid->pCurrentCommand = pCommand;
00341
00342
00343 if (_spid_configureDmaChannels(pSpid) )
00344 return SPID_ERROR_LOCK;
00345
00346
00347 NVIC_ClearPendingIRQ(XDMAC_IRQn);
00348 NVIC_SetPriority( XDMAC_IRQn ,1);
00349 NVIC_EnableIRQ(XDMAC_IRQn);
00350
00351
00352 if (_spid_configureLinkList(pSpiHw, pSpid->pXdmad, pCommand))
00353 return SPID_ERROR_LOCK;
00354
00355
00356 SPI_Enable (pSpiHw );
00357 SCB_CleanInvalidateDCache();
00358
00359 if (XDMAD_StartTransfer( pSpid->pXdmad, spiDmaRxChannel ))
00360 return SPID_ERROR_LOCK;
00361 if (XDMAD_StartTransfer( pSpid->pXdmad, spiDmaTxChannel ))
00362 return SPID_ERROR_LOCK;
00363
00364 return 0;
00365 }
00366
00367
00368
00369
00370
00371
00372
00373 uint32_t SPID_IsBusy(const Spid *pSpid)
00374 {
00375 if (pSpid->semaphore == 0) {
00376 return 1;
00377 } else {
00378 return 0;
00379 }
00380 }