00001 /* ---------------------------------------------------------------------------- 00002 * SAM Software Package License 00003 * ---------------------------------------------------------------------------- 00004 * Copyright (c) 2011, Atmel Corporation 00005 * 00006 * All rights reserved. 00007 * 00008 * Redistribution and use in source and binary forms, with or without 00009 * modification, are permitted provided that the following conditions are met: 00010 * 00011 * - Redistributions of source code must retain the above copyright notice, 00012 * this list of conditions and the disclaimer below. 00013 * 00014 * Atmel's name may not be used to endorse or promote products derived from 00015 * this software without specific prior written permission. 00016 * 00017 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 00018 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00019 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 00020 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 00021 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00022 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 00023 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 00024 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 00025 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 00026 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00027 * ---------------------------------------------------------------------------- 00028 */ 00029 00030 /** \file */ 00031 /*--------------------------------------------------------------------------- 00032 * Headers 00033 *---------------------------------------------------------------------------*/ 00034 00035 #include <chip.h> 00036 00037 00038 /*--------------------------------------------------------------------------- 00039 * Exported functions 00040 *---------------------------------------------------------------------------*/ 00041 00042 /** 00043 * Configure the mode of the RSTC peripheral. 00044 * The configuration is computed by the lib (RSTC_RMR_*). 00045 * \param mr Desired mode configuration. 00046 */ 00047 void RSTC_ConfigureMode(uint32_t mr) 00048 { 00049 Rstc *pHw = RSTC; 00050 mr &= ~RSTC_MR_KEY_Msk; 00051 pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; 00052 } 00053 00054 /** 00055 * Enable/Disable the detection of a low level on the pin NRST as User Reset 00056 * \param enable 1 to enable & 0 to disable. 00057 */ 00058 void RSTC_SetUserResetEnable(uint8_t enable) 00059 { 00060 Rstc *pHw = RSTC; 00061 uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk); 00062 if (enable) { 00063 mr |= RSTC_MR_URSTEN; 00064 } else { 00065 mr &= ~RSTC_MR_URSTEN; 00066 } 00067 pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; 00068 } 00069 00070 /** 00071 * Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST). 00072 * \param enable 1 to enable & 0 to disable. 00073 */ 00074 void RSTC_SetUserResetInterruptEnable(uint8_t enable) 00075 { 00076 Rstc *pHw = RSTC; 00077 uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk); 00078 if (enable) { 00079 mr |= RSTC_MR_URSTIEN; 00080 } else { 00081 mr &= ~RSTC_MR_URSTIEN; 00082 } 00083 pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; 00084 } 00085 00086 /** 00087 * Setup the external reset length. The length is asserted during a time of 00088 * pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s. 00089 * \param powl Power length defined. 00090 */ 00091 void RSTC_SetExtResetLength(uint8_t powl) 00092 { 00093 Rstc *pHw = RSTC; 00094 uint32_t mr = pHw->RSTC_MR; 00095 mr &= ~(RSTC_MR_KEY_Msk | RSTC_MR_ERSTL_Msk); 00096 mr |= RSTC_MR_ERSTL(powl); 00097 pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; 00098 } 00099 00100 00101 /** 00102 * Resets the processor. 00103 */ 00104 void RSTC_ProcessorReset(void) 00105 { 00106 Rstc *pHw = RSTC; 00107 pHw->RSTC_CR = RSTC_CR_PROCRST | RSTC_CR_KEY_PASSWD; 00108 } 00109 00110 00111 /** 00112 * Asserts the NRST pin for external resets. 00113 */ 00114 void RSTC_ExtReset(void) 00115 { 00116 Rstc *pHw = RSTC; 00117 pHw->RSTC_CR = RSTC_CR_EXTRST | RSTC_CR_KEY_PASSWD; 00118 } 00119 00120 /** 00121 * Return NRST pin level ( 1 or 0 ). 00122 */ 00123 uint8_t RSTC_GetNrstLevel(void) 00124 { 00125 Rstc *pHw = RSTC; 00126 return ((pHw->RSTC_SR & RSTC_SR_NRSTL) > 0); 00127 } 00128 00129 /** 00130 * Returns 1 if at least one high-to-low transition of NRST (User Reset) has 00131 * been detected since the last read of RSTC_RSR. 00132 */ 00133 uint8_t RSTC_IsUserResetDetected(void) 00134 { 00135 Rstc *pHw = RSTC; 00136 if (pHw->RSTC_SR & RSTC_SR_URSTS) { 00137 return 1; 00138 } 00139 return 0; 00140 } 00141 00142 /** 00143 * Return 1 if a software reset command is being performed by the reset 00144 * controller. The reset controller is busy. 00145 */ 00146 uint8_t RSTC_IsBusy(void) 00147 { 00148 Rstc *pHw = RSTC; 00149 if (pHw->RSTC_SR & RSTC_SR_SRCMP) { 00150 return 1; 00151 } 00152 return 0; 00153 } 00154 00155 /** 00156 * Get the status 00157 */ 00158 uint32_t RSTC_GetStatus(void) 00159 { 00160 Rstc *pHw = RSTC; 00161 return (pHw->RSTC_SR); 00162 } 00163