SAMV71 Xplained Ultra Software Package 1.3

SAMV71Q20 definitions

Collaboration diagram for SAMV71Q20 definitions:

Modules

 CMSIS Definitions
 Peripheral Software API
 Registers Access Definitions
 Peripheral Ids Definitions
 Peripheral Base Address Definitions
 Peripheral Pio Definitions

Defines

#define IFLASH_SIZE   (0x100000u)
#define IFLASH_PAGE_SIZE   (512u)
#define IFLASH_LOCK_REGION_SIZE   (16384u)
#define IFLASH_NB_OF_PAGES   (2048u)
#define IFLASH_NB_OF_LOCK_BITS   (64u)
#define IRAM_SIZE   (0x60000u)
#define QSPIMEM_ADDR   (0x80000000u)
#define AXIMX_ADDR   (0xA0000000u)
#define ITCM_ADDR   (0x00000000u)
#define IFLASH_ADDR   (0x00400000u)
#define IROM_ADDR   (0x00800000u)
#define DTCM_ADDR   (0x20000000u)
#define IRAM_ADDR   (0x20400000u)
#define EBI_CS0_ADDR   (0x60000000u)
#define EBI_CS1_ADDR   (0x61000000u)
#define EBI_CS2_ADDR   (0x62000000u)
#define EBI_CS3_ADDR   (0x63000000u)
#define SDRAM_CS_ADDR   (0x70000000u)
#define CHIP_JTAGID   (0x05B3D03FUL)
#define CHIP_CIDR   (0xA1220C00UL)
#define CHIP_EXID   (0x00000002UL)
#define CHIP_FREQ_SLCK_RC_MIN   (20000UL)
#define CHIP_FREQ_SLCK_RC   (32000UL)
#define CHIP_FREQ_SLCK_RC_MAX   (44000UL)
#define CHIP_FREQ_MAINCK_RC_4MHZ   (4000000UL)
#define CHIP_FREQ_MAINCK_RC_8MHZ   (8000000UL)
#define CHIP_FREQ_MAINCK_RC_12MHZ   (12000000UL)
#define CHIP_FREQ_CPU_MAX   (300000000UL)
#define CHIP_FREQ_XTAL_32K   (32768UL)
#define CHIP_FREQ_XTAL_12M   (12000000UL)
#define CHIP_FREQ_FWS_0   (26000000UL)
 Maximum operating frequency when FWS is 0.
#define CHIP_FREQ_FWS_1   (52000000UL)
 Maximum operating frequency when FWS is 1.
#define CHIP_FREQ_FWS_2   (78000000UL)
 Maximum operating frequency when FWS is 2.
#define CHIP_FREQ_FWS_3   (104000000UL)
 Maximum operating frequency when FWS is 3.
#define CHIP_FREQ_FWS_4   (131000000UL)
 Maximum operating frequency when FWS is 4.
#define CHIP_FREQ_FWS_5   (150000000UL)
 Maximum operating frequency when FWS is 5.

Detailed Description

This file defines all structures and symbols for SAMV71Q20:


Define Documentation

#define AXIMX_ADDR   (0xA0000000u)

AXI Bus Matrix base address

Definition at line 642 of file samv71q20.h.

#define DTCM_ADDR   (0x20000000u)

Data Tightly Coupled Memory base address

Definition at line 646 of file samv71q20.h.

#define EBI_CS0_ADDR   (0x60000000u)

EBI Chip Select 0 base address

Definition at line 648 of file samv71q20.h.

#define EBI_CS1_ADDR   (0x61000000u)

EBI Chip Select 1 base address

Definition at line 649 of file samv71q20.h.

#define EBI_CS2_ADDR   (0x62000000u)

EBI Chip Select 2 base address

Definition at line 650 of file samv71q20.h.

#define EBI_CS3_ADDR   (0x63000000u)

EBI Chip Select 3 base address

Definition at line 651 of file samv71q20.h.

#define IFLASH_ADDR   (0x00400000u)

Internal Flash base address

Definition at line 644 of file samv71q20.h.

#define IRAM_ADDR   (0x20400000u)

Internal RAM base address

Definition at line 647 of file samv71q20.h.

#define IROM_ADDR   (0x00800000u)

Internal ROM base address

Definition at line 645 of file samv71q20.h.

#define ITCM_ADDR   (0x00000000u)

Instruction Tightly Coupled Memory base address

Definition at line 643 of file samv71q20.h.

#define QSPIMEM_ADDR   (0x80000000u)

QSPI Memory base address

Definition at line 641 of file samv71q20.h.

#define SDRAM_CS_ADDR   (0x70000000u)

SDRAM Chip Select base address

Definition at line 652 of file samv71q20.h.

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