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00030 #include "samv71.h"
00031
00032
00033
00034 #ifdef __cplusplus
00035 extern "C" {
00036 #endif
00037
00038
00039
00040
00041
00042
00043 #define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U))
00044 #define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) | \
00045 CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U))
00046
00047 #define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK \
00048 | PMC_MCKR_MDIV_PCK_DIV2)
00049
00050 uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
00051 #define USBCLK_DIV 10
00052
00053
00054
00055
00056
00057 void SystemInit( void )
00058 {
00059 uint32_t read_MOR;
00060
00061 EFC->EEFC_FMR = EEFC_FMR_FWS(5);
00062
00063
00064
00065
00066
00067
00068 read_MOR = PMC->CKGR_MOR;
00069
00070 read_MOR |= (CKGR_MOR_KEY_PASSWD |CKGR_MOR_XT32KFME);
00071 PMC->CKGR_MOR = read_MOR;
00072
00073
00074 if ( (SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST )
00075 {
00076 SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL;
00077
00078 while( !(SUPC->SUPC_SR & SUPC_SR_OSCSEL) );
00079 }
00080
00081
00082 if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) )
00083 {
00084 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT
00085 | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
00086
00087 while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) )
00088 {
00089 }
00090 }
00091
00092
00093 PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT
00094 | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
00095
00096 while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) )
00097 {
00098 }
00099
00100 PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk)
00101 | PMC_MCKR_CSS_MAIN_CLK;
00102
00103 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
00104 {
00105 }
00106
00107
00108 PMC->CKGR_PLLAR = SYS_BOARD_PLLAR;
00109 while ( !(PMC->PMC_SR & PMC_SR_LOCKA) )
00110 {
00111 }
00112
00113
00114 PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK;
00115 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
00116 {
00117 }
00118
00119
00120 PMC->PMC_MCKR = SYS_BOARD_MCKR;
00121 while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) )
00122 {
00123 }
00124
00125 SystemCoreClock = CHIP_FREQ_CPU_MAX;
00126 }
00127
00128 void SystemCoreClockUpdate( void )
00129 {
00130
00131 switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
00132 {
00133 case PMC_MCKR_CSS_SLOW_CLK:
00134 if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL )
00135 {
00136 SystemCoreClock = CHIP_FREQ_XTAL_32K;
00137 }
00138 else
00139 {
00140 SystemCoreClock = CHIP_FREQ_SLCK_RC;
00141 }
00142 break;
00143
00144 case PMC_MCKR_CSS_MAIN_CLK:
00145 if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
00146 {
00147 SystemCoreClock = CHIP_FREQ_XTAL_12M;
00148 }
00149 else
00150 {
00151 SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
00152
00153 switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
00154 {
00155 case CKGR_MOR_MOSCRCF_4_MHz:
00156 break;
00157
00158 case CKGR_MOR_MOSCRCF_8_MHz:
00159 SystemCoreClock *= 2U;
00160 break;
00161
00162 case CKGR_MOR_MOSCRCF_12_MHz:
00163 SystemCoreClock *= 3U;
00164 break;
00165
00166 default:
00167 break;
00168 }
00169 }
00170 break;
00171
00172 case PMC_MCKR_CSS_PLLA_CLK:
00173 if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL )
00174 {
00175 SystemCoreClock = CHIP_FREQ_XTAL_12M ;
00176 }
00177 else
00178 {
00179 SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ;
00180
00181 switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk )
00182 {
00183 case CKGR_MOR_MOSCRCF_4_MHz:
00184 break;
00185
00186 case CKGR_MOR_MOSCRCF_8_MHz:
00187 SystemCoreClock *= 2U;
00188 break;
00189
00190 case CKGR_MOR_MOSCRCF_12_MHz:
00191 SystemCoreClock *= 3U;
00192 break;
00193
00194 default:
00195 break;
00196 }
00197 }
00198
00199 if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk)
00200 == PMC_MCKR_CSS_PLLA_CLK )
00201 {
00202 SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk)
00203 >> CKGR_PLLAR_MULA_Pos) + 1U);
00204 SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk)
00205 >> CKGR_PLLAR_DIVA_Pos));
00206 }
00207 break;
00208
00209 default:
00210 break;
00211 }
00212
00213 if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 )
00214 {
00215 SystemCoreClock /= 3U;
00216 }
00217 else
00218 {
00219 SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk)
00220 >> PMC_MCKR_PRES_Pos);
00221 }
00222 }
00223
00224
00225
00226 void system_init_flash( uint32_t ul_clk )
00227 {
00228
00229 if ( ul_clk < CHIP_FREQ_FWS_0 )
00230 {
00231 EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE;
00232 }
00233 else
00234 {
00235 if (ul_clk < CHIP_FREQ_FWS_1)
00236 {
00237 EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE;
00238 }
00239 else
00240 {
00241 if (ul_clk < CHIP_FREQ_FWS_2)
00242 {
00243 EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE;
00244 }
00245 else
00246 {
00247 if ( ul_clk < CHIP_FREQ_FWS_3 )
00248 {
00249 EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE;
00250 }
00251 else
00252 {
00253 if ( ul_clk < CHIP_FREQ_FWS_4 )
00254 {
00255 EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE;
00256 }
00257 else
00258 {
00259 EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE;
00260 }
00261 }
00262 }
00263 }
00264 }
00265 }
00266
00267
00268
00269
00270
00271
00272
00273 void sysclk_enable_usb(void)
00274 {
00275
00276 PMC->PMC_SCDR = PMC_SCDR_USBCLK;
00277
00278
00279 PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF);
00280
00281 while( !(PMC->PMC_SR & PMC_SR_LOCKU) );
00282
00283
00284 PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1) );
00285
00286 PMC->PMC_SCER = PMC_SCER_USBCLK;
00287 }
00288
00289
00290
00291
00292
00293
00294
00295
00296
00297 void sysclk_disable_usb(void)
00298 {
00299
00300 PMC->PMC_SCDR = PMC_SCDR_USBCLK;
00301
00302
00303 PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF);
00304
00305 while( !(PMC->PMC_SR & PMC_SR_LOCKU) );
00306
00307
00308 PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1) );
00309
00310
00311 }
00312
00313
00314
00315
00316 #ifdef __cplusplus
00317 }
00318 #endif
00319
00320