SAMV71 Xplained Ultra Software Package 1.3

chip.h

00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2014, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00024  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 #ifndef SAMS7_CHIP_H
00031 #define SAMS7_CHIP_H
00032 
00033 #include "compiler.h"
00034  
00035    
00036 /*************************************************
00037  *      Memory type and its attribute 
00038  *************************************************/
00039 #define SHAREABLE       1
00040 #define NON_SHAREABLE   0
00041  /*********************************************************************************************************************************************************************
00042  *   Memory Type Definition                          Memory TEX attribute            C attribute                     B attribute                     S attribute  
00043  **********************************************************************************************************************************************************************/
00044    
00045 #define STRONGLY_ORDERED_SHAREABLE_TYPE      (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ))     // DO not care //
00046 #define SHAREABLE_DEVICE_TYPE                (( 0x00 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( ENABLE  << MPU_RASR_B_Pos ))     // DO not care //
00047 #define INNER_OUTER_NORMAL_WT_NWA_TYPE(x)   (( 0x00 << MPU_RASR_TEX_Pos ) | ( ENABLE  << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
00048 #define INNER_OUTER_NORMAL_WB_NWA_TYPE(x)   (( 0x00 << MPU_RASR_TEX_Pos ) | ( ENABLE  << MPU_RASR_C_Pos ) | ( ENABLE  << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
00049 #define INNER_OUTER_NORMAL_NOCACHE_TYPE(x)  (( 0x01 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
00050 #define INNER_OUTER_NORMAL_WB_RWA_TYPE(x)   (( 0x01 << MPU_RASR_TEX_Pos ) | ( ENABLE  << MPU_RASR_C_Pos ) | ( ENABLE  << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
00051 #define NON_SHAREABLE_DEVICE_TYPE            (( 0x02 << MPU_RASR_TEX_Pos ) | ( DISABLE << MPU_RASR_C_Pos ) | ( DISABLE << MPU_RASR_B_Pos ))     // DO not care //
00052 
00053  /*  Normal memory attributes with outer capability rules to Non_Cacable */
00054    
00055 #define INNER_NORMAL_NOCACHE_TYPE(x)  (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE  << MPU_RASR_C_Pos ) | ( DISABLE  << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
00056 #define INNER_NORMAL_WB_RWA_TYPE(x)   (( 0x04 << MPU_RASR_TEX_Pos ) | ( DISABLE  << MPU_RASR_C_Pos ) | ( ENABLE  << MPU_RASR_B_Pos )  | ( x << MPU_RASR_S_Pos ))
00057 #define INNER_NORMAL_WT_NWA_TYPE(x)   (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE  << MPU_RASR_C_Pos )  | ( DISABLE  << MPU_RASR_B_Pos ) | ( x << MPU_RASR_S_Pos ))
00058 #define INNER_NORMAL_WB_NWA_TYPE(x)   (( 0x04 << MPU_RASR_TEX_Pos ) | ( ENABLE  << MPU_RASR_C_Pos )  | ( ENABLE  << MPU_RASR_B_Pos )  | ( x << MPU_RASR_S_Pos ))
00059 
00060 /* SCB Interrupt Control State Register Definitions */
00061 #ifndef SCB_VTOR_TBLBASE_Pos
00062 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
00063 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
00064 #endif
00065 
00066 
00067 /*
00068  * Peripherals
00069  */
00070 #include "include/acc.h"
00071 #include "include/aes.h"
00072 #include "include/afec.h"
00073 #include "include/efc.h"
00074 #include "include/pio.h"
00075 #include "include/pio_it.h"
00076 #include "include/efc.h"
00077 #include "include/rstc.h"
00078 #include "include/mpu.h"
00079 #include "include/gmac.h"
00080 #include "include/gmacd.h"
00081 #include "include/video.h"
00082 #include "include/icm.h"
00083 #include "include/isi.h"
00084 #include "include/exceptions.h"
00085 #include "include/pio_capture.h"
00086 #include "include/rtc.h"
00087 #include "include/rtt.h"
00088 #include "include/tc.h"
00089 #include "include/timetick.h"
00090 #include "include/twi.h"
00091 #include "include/flashd.h"
00092 #include "include/pmc.h"
00093 #include "include/pwmc.h"
00094 #include "include/mcan.h"
00095 #include "include/supc.h"
00096 #include "include/usart.h"
00097 #include "include/uart.h"
00098 #include "include/isi.h"
00099 #include "include/hsmci.h"
00100 #include "include/ssc.h"
00101 #include "include/twi.h"
00102 #include "include/trng.h"
00103 #include "include/wdt.h"
00104 #include "include/spi.h"
00105 #include "include/qspi.h"
00106 #include "include/trace.h"
00107 #include "include/xdmac.h"
00108 #include "include/xdma_hardware_interface.h"
00109 #include "include/xdmad.h"
00110 #include "include/mcid.h"
00111 #include "include/twid.h"
00112 #include "include/spi_dma.h"
00113 #include "include/qspi_dma.h"
00114 #include "include/uart_dma.h"
00115 #include "include/usart_dma.h"
00116 #include "include/twid.h"
00117 #include "include/afe_dma.h"
00118 #include "include/dac_dma.h"
00119 #include "include/usbhs.h"
00120 
00121 #define ENABLE_PERIPHERAL(dwId)         PMC_EnablePeripheral( dwId )
00122 #define DISABLE_PERIPHERAL(dwId)        PMC_DisablePeripheral( dwId )
00123       
00124 #endif /* SAMS7_CHIP_H */
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