00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030 #ifndef _SAMV71_SMC_COMPONENT_
00031 #define _SAMV71_SMC_COMPONENT_
00032
00033
00034
00035
00036
00037
00038
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040
00041 typedef struct {
00042 __IO uint32_t SMC_SETUP;
00043 __IO uint32_t SMC_PULSE;
00044 __IO uint32_t SMC_CYCLE;
00045 __IO uint32_t SMC_MODE;
00046 } SmcCs_number;
00047
00048 #define SMCCS_NUMBER_NUMBER 4
00049 typedef struct {
00050 SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER];
00051 __I uint32_t Reserved1[16];
00052 __IO uint32_t SMC_OCMS;
00053 __O uint32_t SMC_KEY1;
00054 __O uint32_t SMC_KEY2;
00055 __I uint32_t Reserved2[22];
00056 __IO uint32_t SMC_WPMR;
00057 __I uint32_t SMC_WPSR;
00058 } Smc;
00059 #endif
00060
00061 #define SMC_SETUP_NWE_SETUP_Pos 0
00062 #define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos)
00063 #define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)))
00064 #define SMC_SETUP_NCS_WR_SETUP_Pos 8
00065 #define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos)
00066 #define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)))
00067 #define SMC_SETUP_NRD_SETUP_Pos 16
00068 #define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos)
00069 #define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)))
00070 #define SMC_SETUP_NCS_RD_SETUP_Pos 24
00071 #define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos)
00072 #define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)))
00073
00074 #define SMC_PULSE_NWE_PULSE_Pos 0
00075 #define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos)
00076 #define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)))
00077 #define SMC_PULSE_NCS_WR_PULSE_Pos 8
00078 #define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos)
00079 #define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)))
00080 #define SMC_PULSE_NRD_PULSE_Pos 16
00081 #define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos)
00082 #define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)))
00083 #define SMC_PULSE_NCS_RD_PULSE_Pos 24
00084 #define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos)
00085 #define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)))
00086
00087 #define SMC_CYCLE_NWE_CYCLE_Pos 0
00088 #define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos)
00089 #define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)))
00090 #define SMC_CYCLE_NRD_CYCLE_Pos 16
00091 #define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos)
00092 #define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)))
00093
00094 #define SMC_MODE_READ_MODE (0x1u << 0)
00095 #define SMC_MODE_WRITE_MODE (0x1u << 1)
00096 #define SMC_MODE_EXNW_MODE_Pos 4
00097 #define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos)
00098 #define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)))
00099 #define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4)
00100 #define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4)
00101 #define SMC_MODE_EXNW_MODE_READY (0x3u << 4)
00102 #define SMC_MODE_BAT (0x1u << 8)
00103 #define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8)
00104 #define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8)
00105 #define SMC_MODE_DBW (0x1u << 12)
00106 #define SMC_MODE_DBW_8_BIT (0x0u << 12)
00107 #define SMC_MODE_DBW_16_BIT (0x1u << 12)
00108 #define SMC_MODE_TDF_CYCLES_Pos 16
00109 #define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos)
00110 #define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)))
00111 #define SMC_MODE_TDF_MODE (0x1u << 20)
00112 #define SMC_MODE_PMEN (0x1u << 24)
00113 #define SMC_MODE_PS_Pos 28
00114 #define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos)
00115 #define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)))
00116 #define SMC_MODE_PS_4_BYTE (0x0u << 28)
00117 #define SMC_MODE_PS_8_BYTE (0x1u << 28)
00118 #define SMC_MODE_PS_16_BYTE (0x2u << 28)
00119 #define SMC_MODE_PS_32_BYTE (0x3u << 28)
00120
00121 #define SMC_OCMS_SMSE (0x1u << 0)
00122
00123 #define SMC_KEY1_KEY1_Pos 0
00124 #define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos)
00125 #define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)))
00126
00127 #define SMC_KEY2_KEY2_Pos 0
00128 #define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos)
00129 #define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)))
00130
00131 #define SMC_WPMR_WPEN (0x1u << 0)
00132 #define SMC_WPMR_WPKEY_Pos 8
00133 #define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos)
00134 #define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)))
00135 #define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8)
00136
00137 #define SMC_WPSR_WPVS (0x1u << 0)
00138 #define SMC_WPSR_WPVSRC_Pos 8
00139 #define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos)
00140
00141
00142
00143
00144 #endif