00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_ISI_COMPONENT_ 00031 #define _SAMV71_ISI_COMPONENT_ 00032 00033 /* ============================================================================= */ 00034 /** SOFTWARE API DEFINITION FOR Image Sensor Interface */ 00035 /* ============================================================================= */ 00036 /** \addtogroup SAMV71_ISI Image Sensor Interface */ 00037 /*@{*/ 00038 00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00040 /** \brief Isi hardware registers */ 00041 typedef struct { 00042 __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ 00043 __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ 00044 __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ 00045 __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ 00046 __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 00047 __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 00048 __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 00049 __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 00050 __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 00051 __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ 00052 __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ 00053 __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ 00054 __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ 00055 __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ 00056 __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ 00057 __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ 00058 __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ 00059 __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ 00060 __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ 00061 __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ 00062 __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ 00063 __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ 00064 __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ 00065 __I uint32_t Reserved1[34]; 00066 __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ 00067 __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ 00068 } Isi; 00069 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00070 /* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ 00071 #define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ 00072 #define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ 00073 #define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ 00074 #define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ 00075 #define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ 00076 #define ISI_CFG1_FRATE_Pos 8 00077 #define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ 00078 #define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) 00079 #define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ 00080 #define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ 00081 #define ISI_CFG1_THMASK_Pos 13 00082 #define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ 00083 #define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) 00084 #define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ 00085 #define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ 00086 #define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ 00087 #define ISI_CFG1_SLD_Pos 16 00088 #define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ 00089 #define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) 00090 #define ISI_CFG1_SFD_Pos 24 00091 #define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ 00092 #define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) 00093 /* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ 00094 #define ISI_CFG2_IM_VSIZE_Pos 0 00095 #define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ 00096 #define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) 00097 #define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ 00098 #define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ 00099 #define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ 00100 #define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ 00101 #define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ 00102 #define ISI_CFG2_IM_HSIZE_Pos 16 00103 #define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ 00104 #define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) 00105 #define ISI_CFG2_YCC_SWAP_Pos 28 00106 #define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ 00107 #define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) 00108 #define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ 00109 #define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ 00110 #define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ 00111 #define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ 00112 #define ISI_CFG2_RGB_CFG_Pos 30 00113 #define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ 00114 #define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) 00115 #define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ 00116 #define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ 00117 #define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ 00118 #define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ 00119 /* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ 00120 #define ISI_PSIZE_PREV_VSIZE_Pos 0 00121 #define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ 00122 #define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) 00123 #define ISI_PSIZE_PREV_HSIZE_Pos 16 00124 #define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ 00125 #define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) 00126 /* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ 00127 #define ISI_PDECF_DEC_FACTOR_Pos 0 00128 #define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ 00129 #define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) 00130 /* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ 00131 #define ISI_Y2R_SET0_C0_Pos 0 00132 #define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ 00133 #define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) 00134 #define ISI_Y2R_SET0_C1_Pos 8 00135 #define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ 00136 #define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) 00137 #define ISI_Y2R_SET0_C2_Pos 16 00138 #define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ 00139 #define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) 00140 #define ISI_Y2R_SET0_C3_Pos 24 00141 #define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ 00142 #define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) 00143 /* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ 00144 #define ISI_Y2R_SET1_C4_Pos 0 00145 #define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ 00146 #define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) 00147 #define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ 00148 #define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ 00149 #define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ 00150 /* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ 00151 #define ISI_R2Y_SET0_C0_Pos 0 00152 #define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ 00153 #define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) 00154 #define ISI_R2Y_SET0_C1_Pos 8 00155 #define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ 00156 #define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) 00157 #define ISI_R2Y_SET0_C2_Pos 16 00158 #define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ 00159 #define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) 00160 #define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ 00161 /* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ 00162 #define ISI_R2Y_SET1_C3_Pos 0 00163 #define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ 00164 #define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) 00165 #define ISI_R2Y_SET1_C4_Pos 8 00166 #define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ 00167 #define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) 00168 #define ISI_R2Y_SET1_C5_Pos 16 00169 #define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ 00170 #define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) 00171 #define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ 00172 /* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ 00173 #define ISI_R2Y_SET2_C6_Pos 0 00174 #define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ 00175 #define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) 00176 #define ISI_R2Y_SET2_C7_Pos 8 00177 #define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ 00178 #define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) 00179 #define ISI_R2Y_SET2_C8_Pos 16 00180 #define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ 00181 #define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) 00182 #define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ 00183 /* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ 00184 #define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ 00185 #define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ 00186 #define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ 00187 #define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ 00188 /* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ 00189 #define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ 00190 #define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ 00191 #define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ 00192 #define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ 00193 #define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ 00194 #define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ 00195 #define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ 00196 #define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ 00197 #define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ 00198 #define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ 00199 #define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ 00200 #define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ 00201 /* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ 00202 #define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ 00203 #define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ 00204 #define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ 00205 #define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ 00206 #define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ 00207 #define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ 00208 #define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ 00209 #define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ 00210 #define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ 00211 /* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ 00212 #define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ 00213 #define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ 00214 #define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ 00215 #define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ 00216 #define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ 00217 #define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ 00218 #define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ 00219 #define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ 00220 #define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ 00221 /* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ 00222 #define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ 00223 #define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ 00224 #define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ 00225 #define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ 00226 #define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ 00227 #define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ 00228 #define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ 00229 #define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ 00230 #define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ 00231 /* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ 00232 #define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ 00233 #define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ 00234 /* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ 00235 #define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ 00236 #define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ 00237 /* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ 00238 #define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ 00239 #define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ 00240 /* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ 00241 #define ISI_DMA_P_ADDR_P_ADDR_Pos 2 00242 #define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ 00243 #define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) 00244 /* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ 00245 #define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ 00246 #define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ 00247 #define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ 00248 #define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ 00249 /* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ 00250 #define ISI_DMA_P_DSCR_P_DSCR_Pos 2 00251 #define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ 00252 #define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) 00253 /* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ 00254 #define ISI_DMA_C_ADDR_C_ADDR_Pos 2 00255 #define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ 00256 #define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) 00257 /* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ 00258 #define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ 00259 #define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ 00260 #define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ 00261 #define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ 00262 /* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ 00263 #define ISI_DMA_C_DSCR_C_DSCR_Pos 2 00264 #define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ 00265 #define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) 00266 /* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ 00267 #define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ 00268 #define ISI_WPMR_WPKEY_Pos 8 00269 #define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ 00270 #define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) 00271 #define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 00272 /* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ 00273 #define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ 00274 #define ISI_WPSR_WPVSRC_Pos 8 00275 #define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ 00276 00277 /*@}*/ 00278 00279 00280 #endif /* _SAMV71_ISI_COMPONENT_ */