SAMV71 Xplained Ultra Software Package 1.3

component_mlb.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
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00005 /* Copyright (c) 2014, Atmel Corporation                                        */
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00011 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_MLB_COMPONENT_
00031 #define _SAMV71_MLB_COMPONENT_
00032 
00033 /* ============================================================================= */
00034 /**  SOFTWARE API DEFINITION FOR Media LB */
00035 /* ============================================================================= */
00036 /** \addtogroup SAMV71_MLB Media LB */
00037 /*@{*/
00038 
00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00040 /** \brief Mlb hardware registers */
00041 typedef struct {
00042   __IO uint32_t MLB_MLBC0;       /**< \brief (Mlb Offset: 0x000) MediaLB Control 0 Register */
00043   __I  uint32_t Reserved1[2];
00044   __IO uint32_t MLB_MS0;         /**< \brief (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register */
00045   __I  uint32_t Reserved2[1];
00046   __IO uint32_t MLB_MS1;         /**< \brief (Mlb Offset: 0x014) MediaLB Channel Status1 Register */
00047   __I  uint32_t Reserved3[2];
00048   __IO uint32_t MLB_MSS;         /**< \brief (Mlb Offset: 0x020) MediaLB System Status Register */
00049   __I  uint32_t MLB_MSD;         /**< \brief (Mlb Offset: 0x024) MediaLB System Data Register */
00050   __I  uint32_t Reserved4[1];
00051   __IO uint32_t MLB_MIEN;        /**< \brief (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register */
00052   __I  uint32_t Reserved5[3];
00053   __IO uint32_t MLB_MLBC1;       /**< \brief (Mlb Offset: 0x03C) MediaLB Control 1 Register */
00054   __I  uint32_t Reserved6[1];
00055   __I  uint32_t Reserved7[15];
00056   __IO uint32_t MLB_HCTL;        /**< \brief (Mlb Offset: 0x080) HBI Control Register */
00057   __I  uint32_t Reserved8[1];
00058   __IO uint32_t MLB_HCMR[2];     /**< \brief (Mlb Offset: 0x088) HBI Channel Mask 0 Register */
00059   __I  uint32_t MLB_HCER[2];     /**< \brief (Mlb Offset: 0x090) HBI Channel Error 0 Register */
00060   __I  uint32_t MLB_HCBR[2];     /**< \brief (Mlb Offset: 0x098) HBI Channel Busy 0 Register */
00061   __I  uint32_t Reserved9[8];
00062   __IO uint32_t MLB_MDAT[4];     /**< \brief (Mlb Offset: 0x0C0) MIF Data 0 Register */
00063   __IO uint32_t MLB_MDWE[4];     /**< \brief (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register */
00064   __IO uint32_t MLB_MCTL;        /**< \brief (Mlb Offset: 0x0E0) MIF Control Register */
00065   __IO uint32_t MLB_MADR;        /**< \brief (Mlb Offset: 0x0E4) MIF Address Register */
00066   __I  uint32_t Reserved10[182];
00067   __IO uint32_t MLB_ACTL;        /**< \brief (Mlb Offset: 0x3C0) AHB Control Register */
00068   __I  uint32_t Reserved11[3];
00069   __IO uint32_t MLB_ACSR[2];     /**< \brief (Mlb Offset: 0x3D0) AHB Channel Status 0 Register */
00070   __IO uint32_t MLB_ACMR[2];     /**< \brief (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register */
00071 } Mlb;
00072 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00073 /* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */
00074 #define MLB_MLBC0_MLBEN (0x1u << 0) /**< \brief (MLB_MLBC0) MediaLB Enable */
00075 #define MLB_MLBC0_MLBCLK_Pos 2
00076 #define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos) /**< \brief (MLB_MLBC0) MLB_CLK (MediaLB clock) speed select */
00077 #define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos)))
00078 #define   MLB_MLBC0_MLBCLK_256_FS (0x0u << 2) /**< \brief (MLB_MLBC0) 256xFs (for MLBPEN = 0) */
00079 #define   MLB_MLBC0_MLBCLK_512_FS (0x1u << 2) /**< \brief (MLB_MLBC0) 512xFs (for MLBPEN = 0) */
00080 #define   MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2) /**< \brief (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */
00081 #define MLB_MLBC0_ZERO (0x1u << 5) /**< \brief (MLB_MLBC0) Must be Written to 0 */
00082 #define MLB_MLBC0_MLBLK (0x1u << 7) /**< \brief (MLB_MLBC0) MediaLB Lock Status (read-only) */
00083 #define MLB_MLBC0_ASYRETRY (0x1u << 12) /**< \brief (MLB_MLBC0) Asynchronous Tx Packet Retry */
00084 #define MLB_MLBC0_CTLRETRY (0x1u << 14) /**< \brief (MLB_MLBC0) Control Tx Packet Retry */
00085 #define MLB_MLBC0_FCNT_Pos 15
00086 #define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos) /**< \brief (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels */
00087 #define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos)))
00088 #define   MLB_MLBC0_FCNT_1_FRAME (0x0u << 15) /**< \brief (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */
00089 #define   MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15) /**< \brief (MLB_MLBC0) 2 frames per sub-buffer */
00090 #define   MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15) /**< \brief (MLB_MLBC0) 4 frames per sub-buffer */
00091 #define   MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15) /**< \brief (MLB_MLBC0) 8 frames per sub-buffer */
00092 #define   MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15) /**< \brief (MLB_MLBC0) 16 frames per sub-buffer */
00093 #define   MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15) /**< \brief (MLB_MLBC0) 32 frames per sub-buffer */
00094 #define   MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15) /**< \brief (MLB_MLBC0) 64 frames per sub-buffer */
00095 /* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */
00096 #define MLB_MS0_MCS_Pos 0
00097 #define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos) /**< \brief (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) */
00098 #define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos)))
00099 /* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */
00100 #define MLB_MS1_MCS_Pos 0
00101 #define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos) /**< \brief (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) */
00102 #define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos)))
00103 /* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */
00104 #define MLB_MSS_RSTSYSCMD (0x1u << 0) /**< \brief (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) */
00105 #define MLB_MSS_LKSYSCMD (0x1u << 1) /**< \brief (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */
00106 #define MLB_MSS_ULKSYSCMD (0x1u << 2) /**< \brief (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */
00107 #define MLB_MSS_CSSYSCMD (0x1u << 3) /**< \brief (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */
00108 #define MLB_MSS_SWSYSCMD (0x1u << 4) /**< \brief (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) */
00109 #define MLB_MSS_SERVREQ (0x1u << 5) /**< \brief (MLB_MSS) Service Request Enabled */
00110 /* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */
00111 #define MLB_MSD_SD0_Pos 0
00112 #define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos) /**< \brief (MLB_MSD) System Data (Byte 0) */
00113 #define MLB_MSD_SD1_Pos 8
00114 #define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos) /**< \brief (MLB_MSD) System Data (Byte 1) */
00115 #define MLB_MSD_SD2_Pos 16
00116 #define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos) /**< \brief (MLB_MSD) System Data (Byte 2) */
00117 #define MLB_MSD_SD3_Pos 24
00118 #define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos) /**< \brief (MLB_MSD) System Data (Byte 3) */
00119 /* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */
00120 #define MLB_MIEN_ISOC_PE (0x1u << 0) /**< \brief (MLB_MIEN) Isochronous Rx Protocol Error Enable */
00121 #define MLB_MIEN_ISOC_BUFO (0x1u << 1) /**< \brief (MLB_MIEN) Isochronous Rx Buffer Overflow Enable */
00122 #define MLB_MIEN_SYNC_PE (0x1u << 16) /**< \brief (MLB_MIEN) Synchronous Protocol Error Enable */
00123 #define MLB_MIEN_ARX_DONE (0x1u << 17) /**< \brief (MLB_MIEN) Asynchronous Rx Done Enable */
00124 #define MLB_MIEN_ARX_PE (0x1u << 18) /**< \brief (MLB_MIEN) Asynchronous Rx Protocol Error Enable */
00125 #define MLB_MIEN_ARX_BREAK (0x1u << 19) /**< \brief (MLB_MIEN) Asynchronous Rx Break Enable */
00126 #define MLB_MIEN_ATX_DONE (0x1u << 20) /**< \brief (MLB_MIEN) Asynchronous Tx Packet Done Enable */
00127 #define MLB_MIEN_ATX_PE (0x1u << 21) /**< \brief (MLB_MIEN) Asynchronous Tx Protocol Error Enable */
00128 #define MLB_MIEN_ATX_BREAK (0x1u << 22) /**< \brief (MLB_MIEN) Asynchronous Tx Break Enable */
00129 #define MLB_MIEN_CRX_DONE (0x1u << 24) /**< \brief (MLB_MIEN) Control Rx Packet Done Enable */
00130 #define MLB_MIEN_CRX_PE (0x1u << 25) /**< \brief (MLB_MIEN) Control Rx Protocol Error Enable */
00131 #define MLB_MIEN_CRX_BREAK (0x1u << 26) /**< \brief (MLB_MIEN) Control Rx Break Enable */
00132 #define MLB_MIEN_CTX_DONE (0x1u << 27) /**< \brief (MLB_MIEN) Control Tx Packet Done Enable */
00133 #define MLB_MIEN_CTX_PE (0x1u << 28) /**< \brief (MLB_MIEN) Control Tx Protocol Error Enable */
00134 #define MLB_MIEN_CTX_BREAK (0x1u << 29) /**< \brief (MLB_MIEN) Control Tx Break Enable */
00135 /* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */
00136 #define MLB_MLBC1_LOCK (0x1u << 6) /**< \brief (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) */
00137 #define MLB_MLBC1_CLKM (0x1u << 7) /**< \brief (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) */
00138 #define MLB_MLBC1_NDA_Pos 8
00139 #define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos) /**< \brief (MLB_MLBC1) Node Device Address */
00140 #define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos)))
00141 /* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */
00142 #define MLB_HCTL_RST0 (0x1u << 0) /**< \brief (MLB_HCTL) Address Generation Unit 0 Software Reset */
00143 #define MLB_HCTL_RST1 (0x1u << 1) /**< \brief (MLB_HCTL) Address Generation Unit 1 Software Reset */
00144 #define MLB_HCTL_EN (0x1u << 15) /**< \brief (MLB_HCTL) HBI Enable */
00145 /* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */
00146 #define MLB_HCMR_CHM_Pos 0
00147 #define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos) /**< \brief (MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0] */
00148 #define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos)))
00149 /* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */
00150 #define MLB_HCER_CERR_Pos 0
00151 #define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos) /**< \brief (MLB_HCER[2]) Bitwise Channel Error Bit [31:0] */
00152 /* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */
00153 #define MLB_HCBR_CHB_Pos 0
00154 #define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos) /**< \brief (MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0] */
00155 /* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */
00156 #define MLB_MDAT_DATA_Pos 0
00157 #define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos) /**< \brief (MLB_MDAT[4]) CRT or DBR Data */
00158 #define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos)))
00159 /* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */
00160 #define MLB_MDWE_MASK_Pos 0
00161 #define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos) /**< \brief (MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0] */
00162 #define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos)))
00163 /* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */
00164 #define MLB_MCTL_XCMP (0x1u << 0) /**< \brief (MLB_MCTL) Transfer Complete (Write 0 to Clear) */
00165 /* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */
00166 #define MLB_MADR_ADDR_Pos 0
00167 #define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos) /**< \brief (MLB_MADR) CTR or DBR Address */
00168 #define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos)))
00169 #define MLB_MADR_TB (0x1u << 30) /**< \brief (MLB_MADR) Target Location Bit */
00170 #define   MLB_MADR_TB_CTR (0x0u << 30) /**< \brief (MLB_MADR) Selects CTR */
00171 #define   MLB_MADR_TB_DBR (0x1u << 30) /**< \brief (MLB_MADR) Selects DBR */
00172 #define MLB_MADR_WNR (0x1u << 31) /**< \brief (MLB_MADR) Write-Not-Read Selection */
00173 /* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */
00174 #define MLB_ACTL_SCE (0x1u << 0) /**< \brief (MLB_ACTL) Software Clear Enable */
00175 #define MLB_ACTL_SMX (0x1u << 1) /**< \brief (MLB_ACTL) AHB Interrupt Mux Enable */
00176 #define MLB_ACTL_DMA_MODE (0x1u << 2) /**< \brief (MLB_ACTL) DMA Mode */
00177 #define MLB_ACTL_MPB (0x1u << 4) /**< \brief (MLB_ACTL) DMA Packet Buffering Mode */
00178 #define   MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4) /**< \brief (MLB_ACTL) Single-packet mode */
00179 #define   MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4) /**< \brief (MLB_ACTL) Multiple-packet mode */
00180 /* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */
00181 #define MLB_ACSR_CHS_Pos 0
00182 #define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos) /**< \brief (MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */
00183 #define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos)))
00184 /* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */
00185 #define MLB_ACMR_CHM_Pos 0
00186 #define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos) /**< \brief (MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0 */
00187 #define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos)))
00188 
00189 /*@}*/
00190 
00191 
00192 #endif /* _SAMV71_MLB_COMPONENT_ */
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