SAMV71 Xplained Ultra Software Package 1.3

ov_7740.h

00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License 
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2013, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00024  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 #ifndef _YUV_H_
00031 #define _YUV_H_
00032 
00033 /*---------------------------------------------------------------------------
00034  *         Headers
00035  *---------------------------------------------------------------------------*/
00036 
00037 
00038 /** Slave address of OMNIVISION chip. */
00039 #define OV_I2C_SENSOR_ADDRESS          (0x42u >> 1)   /* OV7740 -> 0x42 */
00040 
00041 
00042 /** Register definitions. */
00043 /* -------- OV7740_GAIN : (Address: 0x00) AGC Gain Control LSBs -------- */
00044 #define OV7740_GAIN                    (0x00u)
00045 
00046 /* -------- OV7740_BGAIN : (Address: 0x01) AWB - Blue channel gain setting -- */
00047 #define OV7740_BLUE_GAIN               (0x01u)
00048 
00049 /* -------- OV7740_RGAIN : (Address: 0x02) AWB - Red channel gain setting --- */
00050 #define OV7740_RED_GAIN                (0x02u)
00051 
00052 /* -------- OV7740_GGAIN : (Address: 0x03) AWB - Green channel gain setting - */
00053 #define OV7740_GREEN_GAIN              (0x03u)
00054 
00055 /* -------- OV7740_REG04 : (Address: 0x04) Analog setting -------- */
00056 #define OV7740_REG04                   (0x04u)
00057 
00058 /* -------- OV7740_BAVG : (Address: 0x05) B Channel Average -------- */
00059 #define OV7740_BLUE_AVG                (0x05u)
00060 
00061 /* -------- OV7740_GAVG : (Address: 0x06) G Channel Average -------- */
00062 #define OV7740_GREEN_AVG               (0x06u)
00063 
00064 /* -------- OV7740_RAVG : (Address: 0x07) R Channel Average -------- */
00065 #define OV7740_RED_AVG                 (0x07u)
00066 
00067 /* -------- OV7740_PIDH : (Address: 0x0a) Product ID number MSB -------- */
00068 #define OV7740_PIDH                    (0x0au)
00069 #define OV7740_PIDH_DEFAULT            (0x77u << 0)
00070 
00071 /* -------- OV7740_PIDL : (Address: 0x0b) Product ID number LSB -------- */
00072 #define OV7740_PIDL                    (0x0bu)
00073 #define OV7740_PIDL_DEFAULT            (0x40u << 0)
00074 
00075 /* -------- OV7740_REG0C : (Address: 0x0b) -------- */
00076 #define OV7740_REG0C                   (0x0c)
00077 #define OV7740_REG0C_MAX_EXPOSURE_Pos    (1)
00078  /**< \brief (OV7740_REG0C) Max exposure = frame length - limit x 2 */
00079 #define OV7740_REG0C_MAX_EXPOSURE_Msk    (0x3u << OV7740_REG0C_MAX_EXPOSURE_Pos)
00080 #define OV7740_REG0C_MAX_EXPOSURE(value) \
00081 ((OV7740_REG0C_MAX_EXPOSURE_Msk & ((value) << OV7740_REG0C_MAX_EXPOSURE_Pos)))
00082 /**< \brief (OV7740_REG0C) High 8-bit MSB and LSB swap */
00083 #define OV7740_REG0C_BYTE_SWAP_Msk       (0x1u << 3) 
00084 /**< \brief (OV7740_REG0C) output Y9,Y8...Y3,Y2,Y1,Y0 */
00085 #define OV7740_REG0C_BYTE_SWAP_DISABLE   (0x0u << 3) 
00086 /**< \brief (OV7740_REG0C) output Y3,Y2...Y8,Y9,Y1,Y0 */
00087 #define OV7740_REG0C_BYTE_SWAP_ENABLE    (0x1u << 3) 
00088 /**< \brief (OV7740_REG0C) YUV output, Y <-> UV swap */
00089 #define OV7740_REG0C_YUV_SWAP_Msk        (0x1u << 4) 
00090 /**< \brief (OV7740_REG0C) output YUYVYUYV */
00091 #define OV7740_REG0C_YUV_SWAP_DISABLE    (0x0u << 4) 
00092 /**< \brief (OV7740_REG0C) output UYVYUYVY */
00093 #define OV7740_REG0C_YUV_SWAP_ENABLE     (0x1u << 4) 
00094 /**< \brief (OV7740_REG0C) Mirror enable */
00095 #define OV7740_REG0C_MIRROR_ENABLE       (0x1u << 6) 
00096 /**< \brief (OV7740_REG0C) Flip enable */
00097 #define OV7740_REG0C_FLIP_ENABLE         (0x1u << 7) 
00098 
00099 /* -------- OV7740_REG0D : (Address: 0x0d) Analog setting -------- */
00100 #define OV7740_REG0D                   (0x0du)
00101 
00102 /* -------- OV7740_REG0E : (Address: 0x0e) Analog setting -------- */
00103 /* default value: OV7740_REG0E_BLC_BOTH|OV7740_REG0E_BLC_OPTICAL */
00104 #define OV7740_REG0E                   (0x0eu)
00105 #define OV7740_REG0E_OUTPUT_Pos          (0)
00106 /**< \brief (OV7740_REG0E) Output driving capability */
00107 #define OV7740_REG0E_OUTPUT_Msk          (0x3u << OV7740_REG0E_OUTPUT_Pos)
00108 /**< \brief (OV7740_REG0E) 1x */
00109 #define OV7740_REG0E_OUTPUT_1X           (0x0u << OV7740_REG0E_OUTPUT_Pos)
00110 /**< \brief (OV7740_REG0E) 2x */
00111 #define OV7740_REG0E_OUTPUT_2X           (0x1u << OV7740_REG0E_OUTPUT_Pos)
00112 /**< \brief (OV7740_REG0E) 3x */
00113 #define OV7740_REG0E_OUTPUT_3X           (0x2u << OV7740_REG0E_OUTPUT_Pos)
00114 /**< \brief (OV7740_REG0E) 4x */
00115 #define OV7740_REG0E_OUTPUT_4X          (0x3u << OV7740_REG0E_OUTPUT_Pos)
00116 /**< \brief (OV7740_REG0E) Sleep mode */
00117 #define OV7740_REG0E_SLEEP_MODE          (0x1u << 3) 
00118 #define OV7740_REG0E_BLC_Pos             (5)
00119 /**< \brief (OV7740_REG0E) BLC line selection */
00120 #define OV7740_REG0E_BLC_Msk             (0x3u << OV7740_REG0E_BLC_Pos)
00121 /**< \brief (OV7740_REG0E) Select both blue line and red line as BLC line. */
00122 #define OV7740_REG0E_BLC_BOTH0           (0x0u << OV7740_REG0E_BLC_Pos)
00123 /**< \brief (OV7740_REG0E) Select red line as BLC line. */
00124 #define OV7740_REG0E_BLC_RED             (0x1u << OV7740_REG0E_BLC_Pos)
00125 /**< \brief (OV7740_REG0E) Select blue line as BLC line. */
00126 #define OV7740_REG0E_BLC_BLUE            (0x2u << OV7740_REG0E_BLC_Pos)
00127 /**< \brief (OV7740_REG0E) Select both blue line and red line as BLC line. */
00128 #define OV7740_REG0E_BLC_BOTH            (0x3u << OV7740_REG0E_BLC_Pos)
00129 /**< \brief (OV7740_REG0E) BLC line selection */
00130 #define OV7740_REG0E_BLC_LINE_Msk        (0x1u << 7)
00131 /**< \brief (OV7740_REG0E) Electrical BLC */
00132 #define OV7740_REG0E_BLC_LINE_ELECTRICAL (0x0u << 7)
00133 /**< \brief (OV7740_REG0E) Optical BLC */
00134 #define OV7740_REG0E_BLC_LINE_OPTICAL    (0x1u << 7)
00135 
00136 /* ----- OV7740_HAEC : (Address: 0x0f) Automatic exposure control bit [15:8] - */
00137 #define OV7740_HAEC                    (0x0fu)
00138 
00139 /* -------- OV7740_AEC : (Address: 0x10) Automatic exposure control bit [7:0]- */
00140 #define OV7740_AEC                     (0x10u)
00141 
00142 /* -------- OV7740_CLK : (Address: 0x11) Clock settings -------- */
00143 /**< \brief (OV7740_CLK) sysclk=XVCLK1 x PLLDIV / [(CLK[5:0]+1) x2 xPreDiv] */
00144 #define OV7740_CLK                     (0x11u) 
00145 #define OV7740_CLK_DIVIDER_Pos           (0)
00146 /**< \brief (OV7740_CLK) Clock divider */
00147 #define OV7740_CLK_DIVIDER_Msk           (0x3fu << OV7740_CLK_DIVIDER_Pos) 
00148 #define OV7740_CLK_DIVIDER(value) \
00149         ((OV7740_CLK_DIVIDER_Msk & ((value) << OV7740_CLK_DIVIDER_Pos)))
00150 #define OV7740_CLK_PLL_Pos               (6)
00151 /**< \brief (OV7740_CLK) PLL setting - Changing this value is not recommended */
00152 #define OV7740_CLK_PLL_Msk               (0x3u << OV7740_CLK_PLL_Pos) 
00153 #define OV7740_CLK_PLL(value) \
00154         ((OV7740_CLK_PLL_Msk & ((value) << OV7740_CLK_PLL_Pos)))
00155 
00156 #define FRAME_RATE_60           0x00
00157 #define FRAME_RATE_30           0x01
00158 #define FRAME_RATE_20           0x02
00159 #define FRAME_RATE_15           0x03
00160 #define FRAME_RATE_10           0x05
00161 #define FRAME_RATE_7            0x07
00162 #define PLL_DIV_DEFAULT         0x40
00163 #define FRAME_RATE_7_MCK_132    0x0A
00164 #define PLL_DIV_7_MCK_132       0xC0
00165 
00166 /* -------- OV7740_REG12 : (Address: 0x12) -------- */
00167 #define OV7740_REG12                   (0x12u)
00168 #define OV7740_REG12_RAW_RGB             (0x1u << 0)
00169 #define OV7740_REG12_SENSOR_RAW          (0x1u << 4)
00170 #define OV7740_REG12_CC656_MODE          (0x1u << 5)
00171 #define OV7740_REG12_VSKIP               (0x1u << 6)
00172 #define OV7740_REG12_RESET               (0x1u << 7)
00173 
00174 /* -------- OV7740_REG13 : (Address: 0x13) -------- */
00175 #define OV7740_REG13                   (0x13u)
00176 /**< \brief (OV7740_REG13) Exposure auto/manual control selection */
00177 #define OV7740_REG13_EXPOSURE_Msk        (0x01u << 0) 
00178 #define OV7740_REG13_EXPOSURE_MANUAL     (0x0u << 0)
00179 #define OV7740_REG13_EXPOSURE_AUTO       (0x1u << 0)
00180 /**< \brief (OV7740_REG13) Auto white balance control selection */
00181 #define OV7740_REG13_WBAL_Msk            (0x1u << 1) 
00182 #define OV7740_REG13_WBAL_MANUAL         (0x0u << 1)
00183 #define OV7740_REG13_WBAL_AUTO           (0x1u << 1)
00184 /**< \brief (OV7740_REG13) AGC auto/manual control selection */
00185 #define OV7740_REG13_AGC_Msk             (0x1u << 2) 
00186 #define OV7740_REG13_AGC_MANUAL          (0x0u << 2)
00187 #define OV7740_REG13_AGC_AUTO            (0x1u << 2)
00188 /**< \brief (OV7740_REG13) LAEC enable */
00189 #define OV7740_REG13_LAEC_Msk            (0x1u << 3) 
00190 #define OV7740_REG13_LAEC_DISABLE        (0x0u << 3)
00191 #define OV7740_REG13_LAEC_ENABLE         (0x1u << 3)
00192  /**< \brief (OV7740_REG13) Banding option */
00193 #define OV7740_REG13_BANDING_OPT_Msk     (0x1u << 4)
00194 /**< \brief (OV7740_REG13) Minimum exposure is limited to 1/120 or 1/100 second 
00195  when banding filter is enabled */
00196 #define OV7740_REG13_BANDING_OPT_LIMITED (0x0u << 4)
00197 /**< \brief (OV7740_REG13) Minimum exposure is allowed to be less than 1/120 or
00198  1/100 second when banding filter is enabled */
00199 #define OV7740_REG13_BANDING_OPT_ENABLE  (0x1u << 4)
00200 /**< \brief (OV7740_REG13) Banding enable */
00201 #define OV7740_REG13_BANDING_Mask        (0x1u << 5) 
00202 #define OV7740_REG13_BANDING_DISABLE     (0x0u << 5)
00203 #define OV7740_REG13_BANDING_ENABLE      (0x1u << 5)
00204 /**< \brief (OV7740_REG13) Enable frame drop function */
00205 #define OV7740_REG13_FRAME_DROP_Mask     (0x1u << 6) 
00206 #define OV7740_REG13_FRAME_DROP_DISABLE  (0x0u << 6)
00207 #define OV7740_REG13_FRAME_DROP_ENABLE   (0x1u << 6)
00208 /**< \brief (OV7740_REG13) AEC speed selection */
00209 #define OV7740_REG13_AEC_Mask            (0x1u << 7)
00210 /**< \brief (OV7740_REG13) Normal */
00211 #define OV7740_REG13_AEC_NORMAL          (0x0u << 7)
00212 /**< \brief (OV7740_REG13) Faster AEC correction */
00213 #define OV7740_REG13_AEC_FASTER          (0x1u << 7) 
00214 
00215 /* -------- OV7740_REG14 : (Address: 0x14) -------- */
00216 #define OV7740_REG14                   (0x14u)
00217 
00218 /* -------- OV7740_REG15 : (Address: 0x15) -------- */
00219 #define OV7740_REG15                   (0x15u)
00220 #define OV7740_REG15_GAIN_Pos          (0)
00221 /**< \brief (OV7740_REG15) AGC MSBs (digital gain) (LSBs in GAIN[7:0]) */
00222 #define OV7740_REG15_GAIN_Msk          (0x3u << OV7740_REG15_GAIN_Pos) 
00223 #define OV7740_REG15_GAIN(value) \
00224         ((OV7740_REG15_GAIN_Msk & ((value) << OV7740_REG15_GAIN_Pos)))
00225 /**< \brief (OV7740_REG15) Night mode triggering point */
00226 #define OV7740_REG15_NIGHT_Mask        (0x3u << 2) 
00227 /**< \brief (OV7740_REG15) 2x gain */
00228 #define OV7740_REG15_NIGHT_2X_GAIN     (0x0u << 2) 
00229 /**< \brief (OV7740_REG15) 4x gain */
00230 #define OV7740_REG15_NIGHT_4X_GAIN     (0x1u << 2) 
00231 /**< \brief (OV7740_REG15) 8x gain */
00232 #define OV7740_REG15_NIGHT_8X_GAIN     (0x2u << 2)
00233 /**< \brief (OV7740_REG15) 16x gain */
00234 #define OV7740_REG15_NIGHT_16X_GAIN    (0x3u << 2)
00235 /**< \brief (OV7740_REG15) Ceiling of inserting frames */
00236 #define OV7740_REG15_CEIL_Mask         (0x3u << 4)
00237 /**< \brief (OV7740_REG15) Up to 0 frames */
00238 #define OV7740_REG15_CEIL_0            (0x0u << 4)
00239 /**< \brief (OV7740_REG15) Up to 1 frames */
00240 #define OV7740_REG15_CEIL_1            (0x1u << 4)
00241 /**< \brief (OV7740_REG15) Up to 2 frames */
00242 #define OV7740_REG15_CEIL_2            (0x2u << 4)
00243 /**< \brief (OV7740_REG15) Up to 3 frames */
00244 #define OV7740_REG15_CEIL_3            (0x3u << 4)
00245 /**< \brief (OV7740_REG15) Up to 7 frames */
00246 #define OV7740_REG15_CEIL_7            (0x7u << 4)
00247 /**< \brief (OV7740_REG15) Enable inserting frames in night mode */
00248 #define OV7740_REG15_ENABLE_NIGHT      (0x1u << 7)  
00249 
00250 /*   OV7740_REG16 : (Address: 0x16)   */
00251 #define OV7740_REG16                   (0x16u)
00252 
00253 /*
00254  * OV7740_AHSTART : (Address: 0x17) Sensor Horizontal output start point
00255  * 8 MSBs (LSBs in REG16[1:0])
00256  */
00257 #define OV7740_AHSTART                 (0x17u)
00258 
00259 /* 
00260  * OV7740_AHSIZE : (Address: 0x18) Sensor Horizontal output size 8 MSBs 
00261  * (LSBs in REG16[4:3])
00262  */
00263 #define OV7740_AHSIZE                  (0x18u)
00264 
00265 /* 
00266  * OV7740_AVSTART : (Address: 0x19) Sensor Vertical output start point 8 MSBs 
00267  * (LSBs in REG16[2])
00268  */
00269 #define OV7740_AVSTART                 (0x19u)
00270 
00271 /* 
00272  * OV7740_AVSIZE : (Address: 0x1a) Sensor Vertical output size 8 MSBs 
00273  * (LSBs in REG16[5])
00274  */
00275 #define OV7740_AVSIZE                  (0x1au)
00276 
00277 /* -------- OV7740_PIXEL_SHIFT : (Address: 0x1b) Pixel shift -------- */
00278 #define OV7740_PIXEL_SHIFT             (0x1bu)
00279 
00280 /* -------- OV7740_MIDH : (Address: 0x1c) Manufacturer ID Byte - High ------- */
00281 #define OV7740_MIDH                    (0x1cu)
00282 #define OV7740_MIDH_DEFAULT              (0x7fu << 0)
00283 
00284 /* -------- OV7740_MIDL : (Address: 0x1d) Manufacturer ID Byte - Low -------- */
00285 #define OV7740_MIDL                    (0x1du)
00286 #define OV7740_MIDL_DEFAULT              (0xa2u << 0)
00287 
00288 /* -------- OV7740_REG1E : (Address: 0x1e) -------- */
00289 #define OV7740_REG1E                   (0x1eu)
00290 
00291 /* -------- OV7740_REG1F : (Address: 0x1f) -------- */
00292 #define OV7740_REG1F                   (0x1fu)
00293 
00294 /* -------- OV7740_REG1E : (Address: 0x1e) -------- */
00295 #define OV7740_REG1E                   (0x1eu)
00296 
00297 /* -------- OV7740_REG20 : (Address: 0x20) -------- */
00298 #define OV7740_REG20                   (0x20u)
00299 
00300 /* -------- OV7740_REG21 : (Address: 0x21) -------- */
00301 #define OV7740_REG21                   (0x21u)
00302 
00303 /*  OV7740_REG21 : (Address: 0x24) Luminance signal high range for AEC/AGC 
00304  * operation.
00305  */
00306 #define OV7740_WPT                     (0x24u)
00307 
00308 /*
00309  * OV7740_REG21 : (Address: 0x25) Luminance signal low range for AEC/AGC 
00310  * operation 
00311  */
00312 #define OV7740_BPT                     (0x25u)
00313 
00314 /* ---  OV7740_VPT : (Address: 0x26) effective only in AEG/AGC fast mode ---- */
00315 #define OV7740_VPT                     (0x26u)
00316 
00317 /* -------- OV7740_REG27 : (Address: 0x27) -------- */
00318 #define OV7740_REG27                   (0x27u)
00319 /**< \brief (OV7740_REG27) Black sun cancellation enable */
00320 #define OV7740_REG27_BLACKSUN            (0x1u << 7) 
00321 
00322 /* -------- OV7740_REG28 : (Address: 0x28) -------- */
00323 #define OV7740_REG28                   (0x28u)
00324 /**< \brief (OV7740_REG28) VSYNC polarity */
00325 #define OV7740_REG28_VSYNC_Msk           (0x1u << 1)
00326 /**< \brief (OV7740_REG28) Positive */
00327 #define OV7740_REG28_VSYNC_POSITIVE      (0x1u << 0)
00328 /**< \brief (OV7740_REG28) Negative */
00329 #define OV7740_REG28_VSYNC_NEGATIVE      (0x1u << 1)
00330 /**< \brief (OV7740_REG28) No VSYNC output option */
00331 #define OV7740_REG28_VSYNC_OUTPUT_Msk    (0x1u << 3)
00332 /**< \brief (OV7740_REG28) Still output VSYNC when frame drop */
00333 #define OV7740_REG28_VSYNC_OUTPUT_STILL  (0x0u << 3)
00334 /**< \brief (OV7740_REG28) No VSYNC output when frame drop */
00335 #define OV7740_REG28_VSYNC_OUTPUT_NONE   (0x1u << 3)
00336 /**< \brief (OV7740_REG28) HREF polarity */
00337 #define OV7740_REG28_HREF_Msk            (0x1u << 4)
00338 /**< \brief (OV7740_REG28) Output positive HREF */
00339 #define OV7740_REG28_HREF_POSITIVE       (0x0u << 4)
00340  /**< \brief (OV7740_REG28) Output negative HREF for data valid */
00341 #define OV7740_REG28_HREF_NEGATIVE       (0x1u << 4)
00342 /**< \brief (OV7740_REG28) HSYNC polarity */
00343 #define OV7740_REG28_HSYNC_Msk           (0x1u << 5)
00344 /**< \brief (OV7740_REG28) Positive */
00345 #define OV7740_REG28_HSYNC_POSITIVE      (0x0u << 5)
00346 /**< \brief (OV7740_REG28) Negative */
00347 #define OV7740_REG28_HSYNC_NEGATIVE      (0x1u << 5)
00348 /**< \brief (OV7740_REG28) HREF pin output swap */
00349 #define OV7740_REG28_HREF_OUTPUT_Msk     (0x1u << 6)
00350 /**< \brief (OV7740_REG28) HREF */
00351 #define OV7740_REG28_HREF_OUTPUT_HREF    (0x0u << 6)
00352 /**< \brief (OV7740_REG28) HSYNC */
00353 #define OV7740_REG28_HREF_OUTPUT_HSYNC   (0x1u << 6)
00354 /**< \brief (OV7740_REG28) Output data bit reverse option */
00355 #define OV7740_REG28_OUTPUT_REVERSE      (0x1u << 7) 
00356 
00357 /* -------- OV7740_REG65 : (Address: 0x65) -------- */
00358 #define OV7740_REG65                  (0x65u)
00359 /**< \brief (OV7740_REG65) Output data bit swap option */
00360 #define OV7740_REG65_BIT_SWAP_Msk       (0x1u << 3)
00361  /**< \brief (OV7740_REG65) Output DATA[9:0] */
00362 #define OV7740_REG65_BIT_SWAP_NORMAL    (0x0u << 3)
00363 /**< \brief (OV7740_REG65) Output DATA[0:9] */
00364 #define OV7740_REG65_BIT_SWAP_REVERSE   (0x1u << 3) 
00365 
00366 /* -------- OV7740_YUV422CTRL : (Address: 0xd9) -------- */
00367 #define OV7740_YUV422CTRL             (0xd9u)
00368  /**< \brief (OV7740_YUV422CTRL) cnv_opt */
00369 #define OV7740_YUV422CTRL_CNV_OPT_Msk   (0x1u << 0)
00370 /**< \brief (OV7740_YUV422CTRL) Average mode */
00371 #define OV7740_YUV422CTRL_CNV_OPT_AVERAGE (0x0u << 0)
00372 /**< \brief (OV7740_YUV422CTRL) Drop mode */
00373 #define OV7740_YUV422CTRL_CNV_OPT_DROP    (0x1u << 0)
00374 
00375 /**< \brief (OV7740_YUV422CTRL) v_first */
00376 #define OV7740_YUV422CTRL_V_FIRST_Msk   (0x1u << 1)
00377 /**< \brief (OV7740_YUV422CTRL) Output line will be YUYV... */
00378 #define OV7740_YUV422CTRL_V_FIRST_YUYV  (0x0u << 1)
00379 /**< \brief (OV7740_YUV422CTRL) Output line will be YVYU... (it will affect 
00380 definition of U/V in SDE. If it is set, all registers in SDE about U/V must be 
00381 swapped */
00382 #define OV7740_YUV422CTRL_V_FIRST_YVYU  (0x1u << 1) 
00383 
00384 
00385 
00386 #endif // #ifndef _YUV_H_
00387 
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