00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_UART_COMPONENT_ 00031 #define _SAMV71_UART_COMPONENT_ 00032 00033 /* ============================================================================= */ 00034 /** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ 00035 /* ============================================================================= */ 00036 /** \addtogroup SAMV71_UART Universal Asynchronous Receiver Transmitter */ 00037 /*@{*/ 00038 00039 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00040 /** \brief Uart hardware registers */ 00041 typedef struct { 00042 __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ 00043 __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ 00044 __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ 00045 __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ 00046 __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ 00047 __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ 00048 __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ 00049 __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ 00050 __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ 00051 __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ 00052 __I uint32_t Reserved1[47]; 00053 __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ 00054 } Uart; 00055 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00056 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ 00057 #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ 00058 #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ 00059 #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ 00060 #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ 00061 #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ 00062 #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ 00063 #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ 00064 #define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ 00065 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ 00066 #define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ 00067 #define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ 00068 #define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ 00069 #define UART_MR_PAR_Pos 9 00070 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ 00071 #define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) 00072 #define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ 00073 #define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ 00074 #define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ 00075 #define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ 00076 #define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ 00077 #define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ 00078 #define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ 00079 #define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ 00080 #define UART_MR_CHMODE_Pos 14 00081 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ 00082 #define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) 00083 #define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ 00084 #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ 00085 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ 00086 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ 00087 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ 00088 #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ 00089 #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ 00090 #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ 00091 #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ 00092 #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ 00093 #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ 00094 #define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ 00095 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ 00096 #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ 00097 #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ 00098 #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ 00099 #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ 00100 #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ 00101 #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ 00102 #define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ 00103 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ 00104 #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ 00105 #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ 00106 #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ 00107 #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ 00108 #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ 00109 #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ 00110 #define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ 00111 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ 00112 #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ 00113 #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ 00114 #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ 00115 #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ 00116 #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ 00117 #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ 00118 #define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ 00119 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ 00120 #define UART_RHR_RXCHR_Pos 0 00121 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ 00122 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ 00123 #define UART_THR_TXCHR_Pos 0 00124 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ 00125 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) 00126 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ 00127 #define UART_BRGR_CD_Pos 0 00128 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ 00129 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) 00130 /* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ 00131 #define UART_CMPR_VAL1_Pos 0 00132 #define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ 00133 #define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) 00134 #define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ 00135 #define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ 00136 #define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ 00137 #define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ 00138 #define UART_CMPR_VAL2_Pos 16 00139 #define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ 00140 #define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) 00141 /* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ 00142 #define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ 00143 #define UART_WPMR_WPKEY_Pos 8 00144 #define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ 00145 #define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) 00146 #define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ 00147 00148 /*@}*/ 00149 00150 00151 #endif /* _SAMV71_UART_COMPONENT_ */