SAMV71 Xplained Ultra Software Package 1.3

s25fl1.h

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License 
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2013, Atmel Corporation
00005  *
00006  * All rights reserved.
00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
00018  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
00021  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
00023  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
00024  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
00025  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /**
00031  * \file
00032  *
00033  * Interface for the S25fl1 Serial Flash driver.
00034  *
00035  */
00036 
00037 #ifndef S25FL1_H
00038 #define S25FL1_H
00039 #define USE_QSPI_DMA
00040 /*----------------------------------------------------------------------------
00041  *        Macros
00042  *----------------------------------------------------------------------------*/
00043 
00044 #define Size(pAt25)            ((pAt25)->pDesc->size)
00045 #define PageSize(pAt25)        ((pAt25)->pDesc->pageSize)
00046 #define BlockSize(pAt25)       ((pAt25)->pDesc->blockSize)
00047 #define Name(pAt25)            ((pAt25)->pDesc->name)
00048 #define ManId(pAt25)           (((pAt25)->pDesc->jedecId) & 0xFF)
00049 #define PageNumber(pAt25)      (Size(pAt25) / PageSize(pAt25))
00050 #define BlockNumber(pAt25)     (Size(pAt25) / BlockSize(pAt25))
00051 #define PagePerBlock(pAt25)    (BlockSize(pAt25) / PageSize(pAt25))
00052 #define BlockEraseCmd(pAt25)   ((pAt25)->pDesc->blockEraseCmd)
00053 
00054 /*----------------------------------------------------------------------------
00055  *        Local definitions
00056  *----------------------------------------------------------------------------*/
00057 
00058 /** Device is protected, operation cannot be carried out. */
00059 #define ERROR_PROTECTED        1
00060 /** Device is busy executing a command. */
00061 #define ERROR_BUSY             2
00062 /** There was a problem while trying to program page data. */
00063 #define ERROR_PROGRAM          3
00064 /** There was an SPI communication error. */
00065 #define ERROR_SPI              4
00066 
00067 /** Device ready/busy status bit. */
00068 #define STATUS_RDYBSY          (1 << 0)
00069 /** Device is ready. */
00070 #define STATUS_RDYBSY_READY    (0 << 0)
00071 /** Device is busy with internal operations. */
00072 #define STATUS_RDYBSY_BUSY     (1 << 0)
00073 /** Write enable latch status bit. */
00074 #define STATUS_WEL             (1 << 1)
00075 /** Device is not write enabled. */
00076 #define STATUS_WEL_DISABLED    (0 << 1)
00077 /** Device is write enabled. */
00078 #define STATUS_WEL_ENABLED     (1 << 1)
00079 /** Software protection status bit-field. */
00080 #define STATUS_SWP             (3 << 2)
00081 /** All sectors are software protected. */
00082 #define STATUS_SWP_PROTALL     (3 << 2)
00083 /** Some sectors are software protected. */
00084 #define STATUS_SWP_PROTSOME    (1 << 2)
00085 /** No sector is software protected. */
00086 #define STATUS_SWP_PROTNONE    (0 << 2)
00087 /** Write protect pin status bit. */
00088 #define STATUS_WPP             (1 << 4)
00089 /** Write protect signal is not asserted. */
00090 #define STATUS_WPP_NOTASSERTED (0 << 4)
00091 /** Write protect signal is asserted. */
00092 #define STATUS_WPP_ASSERTED    (1 << 4)
00093 /** Erase/program error bit. */
00094 #define STATUS_EPE             (1 << 5)
00095 /** Erase or program operation was successful. */
00096 #define STATUS_EPE_SUCCESS     (0 << 5)
00097 /** Erase or program error detected. */
00098 #define STATUS_EPE_ERROR       (1 << 5)
00099 /** Sector protection registers locked bit. */
00100 #define STATUS_SPRL            (1 << 7)
00101 /** Sector protection registers are unlocked. */
00102 #define STATUS_SPRL_UNLOCKED   (0 << 7)
00103 /** Sector protection registers are locked. */
00104 #define STATUS_SPRL_LOCKED     (1 << 7)
00105    
00106 /** Quad enable bit */
00107 #define STATUS_QUAD_ENABLE     (1 << 1)
00108    /** Quad enable bit */
00109 #define STATUS_WRAP_ENABLE     (0 << 4)
00110    
00111    /** Latency control bits */
00112 #define STATUS_LATENCY_CTRL    (0xF << 0)   
00113    
00114 #define STATUS_WRAP_BYTE       (1 << 5)
00115    
00116 #define BLOCK_PROTECT_Msk      (7 << 2)
00117    
00118 #define TOP_BTM_PROTECT_Msk    (1 << 5)
00119    
00120 #define SEC_PROTECT_Msk        (1 << 6)   
00121    
00122 #define CHIP_PROTECT_Msk       (0x1F << 2)    
00123 
00124 /** Read array command code. */
00125 #define READ_ARRAY             0x0B
00126 /** Read array (low frequency) command code. */
00127 #define READ_ARRAY_LF          0x03
00128 /** Fast Read array  command code. */
00129 #define READ_ARRAY_DUAL        0x3B
00130 /** Fast Read array  command code. */
00131 #define READ_ARRAY_QUAD        0x6B   
00132 /** Fast Read array  command code. */
00133 #define READ_ARRAY_DUAL_IO     0xBB
00134 /** Fast Read array  command code. */
00135 #define READ_ARRAY_QUAD_IO     0xEB   
00136 /** Block erase command code (4K block). */
00137 #define BLOCK_ERASE_4K         0x20
00138 /** Block erase command code (32K block). */
00139 #define BLOCK_ERASE_32K        0x52
00140 /** Block erase command code (64K block). */
00141 #define BLOCK_ERASE_64K        0xD8
00142 /** Chip erase command code 1. */
00143 #define CHIP_ERASE_1           0x60
00144 /** Chip erase command code 2. */
00145 #define CHIP_ERASE_2           0xC7
00146 /** Byte/page program command code. */
00147 #define BYTE_PAGE_PROGRAM      0x02
00148 /** Sequential program mode command code 1. */
00149 #define SEQUENTIAL_PROGRAM_1   0xAD
00150 /** Sequential program mode command code 2. */
00151 #define SEQUENTIAL_PROGRAM_2   0xAF
00152 /** Write enable command code. */
00153 #define WRITE_ENABLE           0x06
00154 /** Write disable command code. */
00155 #define WRITE_DISABLE          0x04
00156 /** Protect sector command code. */
00157 #define PROTECT_SECTOR         0x36
00158 /** Unprotected sector command code. */
00159 #define UNPROTECT_SECTOR       0x39
00160 /** Read sector protection registers command code. */
00161 #define READ_SECTOR_PROT       0x3C
00162 /** Read status register command code. */
00163 #define READ_STATUS_1          0x05
00164    /** Read status register command code. */
00165 #define READ_STATUS_2          0x35
00166    /** Read status register command code. */
00167 #define READ_STATUS_3          0x33
00168 /** Write status register command code. */
00169 #define WRITE_STATUS           0x01
00170 /** Read manufacturer and device ID command code. */
00171 #define READ_JEDEC_ID          0x9F
00172 /** Deep power-down command code. */
00173 #define DEEP_PDOWN             0xB9
00174 /** Resume from deep power-down command code. */
00175 #define RES_DEEP_PDOWN         0xAB
00176 /** Resume from deep power-down command code. */
00177 #define SOFT_RESET_ENABLE      0x66
00178 /** Resume from deep power-down command code. */
00179 #define SOFT_RESET             0x99
00180 /** Resume from deep power-down command code. */
00181 #define WRAP_ENABLE            0x77
00182 /** Continuous Read Mode Reset command code. */
00183 #define CONT_MODE_RESET        0xFF
00184 
00185 /** SPI Flash Manufacturer JEDEC ID */
00186 #define ATMEL_SPI_FLASH             0x1F
00187 #define ST_SPI_FLASH                0x20
00188 #define WINBOND_SPI_FLASH           0xEF
00189 #define MACRONIX_SPI_FLASH          0xC2
00190 #define SST_SPI_FLASH               0xBF
00191 
00192 /*----------------------------------------------------------------------------
00193  *        Exported functions
00194  *----------------------------------------------------------------------------*/
00195 
00196 uint32_t S25FL1D_ReadJedecId(void);
00197 
00198 void S25FL1D_InitFlashInterface(uint8_t Mode);
00199 
00200 void S25FL1D_SoftReset(void);
00201 
00202 void S25FL1D_ContReadModeReset(void);
00203 unsigned char S25FL1D_Unprotect(void);
00204 
00205 unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size);
00206 
00207 void S25FL1D_QuadMode(uint8_t Enable);
00208 
00209 void S25FL1D_EnableWrap(uint8_t ByetAlign);
00210 
00211 void S25FL1D_SetReadLatencyControl(uint8_t Latency);
00212 
00213 unsigned char S25FL1D_EraseChip(void);
00214 
00215 unsigned char S25FL1D_EraseSector( unsigned int address);
00216 
00217 unsigned char S25FL1D_Erase64KBlock(  unsigned int address);
00218 
00219 unsigned char S25FL1D_Write(
00220                 uint32_t *pData,
00221                 uint32_t size,
00222                 uint32_t address,
00223                 uint8_t Secure);
00224 
00225 extern unsigned char S25FL1D_Read(
00226                 uint32_t *pData,
00227                 uint32_t size,
00228                 uint32_t address);
00229 
00230 extern unsigned char S25FL1D_ReadDual(
00231                 uint32_t *pData,
00232                 uint32_t size,
00233                 uint32_t address);
00234 
00235 extern unsigned char S25FL1D_ReadQuad(
00236                 uint32_t *pData,
00237                 uint32_t size,
00238                 uint32_t address);
00239 
00240 extern unsigned char S25FL1D_ReadDualIO(
00241                 uint32_t *pData,
00242                 uint32_t size,
00243                 uint32_t address,
00244                 uint8_t ContMode,
00245                 uint8_t Secure);
00246 
00247 extern unsigned char S25FL1D_ReadQuadIO(
00248                 uint32_t *pData,
00249                 uint32_t size,
00250                 uint32_t address,
00251                 uint8_t ContMode,
00252                 uint8_t Secure);
00253 
00254 #endif // #ifndef S25FL1_H
00255 
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