SAMV71 Xplained Ultra Software Package 1.3

instance_smc.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2014, Atmel Corporation                                        */
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00011 /*                                                                              */
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00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
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00029 
00030 #ifndef _SAMV71_SMC_INSTANCE_
00031 #define _SAMV71_SMC_INSTANCE_
00032 
00033 /* ========== Register definition for SMC peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_SMC_SETUP0                  (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
00036   #define REG_SMC_PULSE0                  (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
00037   #define REG_SMC_CYCLE0                  (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
00038   #define REG_SMC_MODE0                   (0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
00039   #define REG_SMC_SETUP1                  (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
00040   #define REG_SMC_PULSE1                  (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
00041   #define REG_SMC_CYCLE1                  (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
00042   #define REG_SMC_MODE1                   (0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
00043   #define REG_SMC_SETUP2                  (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
00044   #define REG_SMC_PULSE2                  (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
00045   #define REG_SMC_CYCLE2                  (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
00046   #define REG_SMC_MODE2                   (0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
00047   #define REG_SMC_SETUP3                  (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
00048   #define REG_SMC_PULSE3                  (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
00049   #define REG_SMC_CYCLE3                  (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
00050   #define REG_SMC_MODE3                   (0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
00051   #define REG_SMC_OCMS                    (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */
00052   #define REG_SMC_KEY1                    (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
00053   #define REG_SMC_KEY2                    (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
00054   #define REG_SMC_WPMR                    (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */
00055   #define REG_SMC_WPSR                    (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */
00056 #else
00057   #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
00058   #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
00059   #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
00060   #define REG_SMC_MODE0  (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */
00061   #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
00062   #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
00063   #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
00064   #define REG_SMC_MODE1  (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */
00065   #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
00066   #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
00067   #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
00068   #define REG_SMC_MODE2  (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */
00069   #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
00070   #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
00071   #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
00072   #define REG_SMC_MODE3  (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */
00073   #define REG_SMC_OCMS   (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */
00074   #define REG_SMC_KEY1   (*(__O  uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
00075   #define REG_SMC_KEY2   (*(__O  uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
00076   #define REG_SMC_WPMR   (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */
00077   #define REG_SMC_WPSR   (*(__I  uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */
00078 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00079 
00080 #endif /* _SAMV71_SMC_INSTANCE_ */
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