00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_ISI_INSTANCE_ 00031 #define _SAMV71_ISI_INSTANCE_ 00032 00033 /* ========== Register definition for ISI peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ 00036 #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ 00037 #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ 00038 #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ 00039 #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 00040 #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 00041 #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 00042 #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 00043 #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 00044 #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */ 00045 #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */ 00046 #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ 00047 #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ 00048 #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ 00049 #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ 00050 #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ 00051 #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ 00052 #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ 00053 #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ 00054 #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ 00055 #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ 00056 #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ 00057 #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ 00058 #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ 00059 #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ 00060 #else 00061 #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ 00062 #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ 00063 #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ 00064 #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ 00065 #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ 00066 #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ 00067 #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ 00068 #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ 00069 #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ 00070 #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */ 00071 #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */ 00072 #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ 00073 #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ 00074 #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ 00075 #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ 00076 #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ 00077 #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ 00078 #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ 00079 #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ 00080 #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ 00081 #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ 00082 #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ 00083 #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ 00084 #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ 00085 #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ 00086 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00087 00088 #endif /* _SAMV71_ISI_INSTANCE_ */