SAMV71 Xplained Ultra Software Package 1.3

board_memories.c

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00001 /* ----------------------------------------------------------------------------
00002  *         SAM Software Package License
00003  * ----------------------------------------------------------------------------
00004  * Copyright (c) 2012, Atmel Corporation
00005  *
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00007  *
00008  * Redistribution and use in source and binary forms, with or without
00009  * modification, are permitted provided that the following conditions are met:
00010  *
00011  * - Redistributions of source code must retain the above copyright notice,
00012  * this list of conditions and the disclaimer below.
00013  *
00014  * Atmel's name may not be used to endorse or promote products derived from
00015  * this software without specific prior written permission.
00016  *
00017  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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00019  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
00020  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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00022  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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00026  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00027  * ----------------------------------------------------------------------------
00028  */
00029 
00030 /**
00031  * \file
00032  *
00033  * Implementation of memories configuration on board.
00034  *
00035  */
00036 
00037 /*----------------------------------------------------------------------------
00038  *        Headers
00039  *----------------------------------------------------------------------------*/
00040 #include "board.h"
00041 
00042 /*----------------------------------------------------------------------------
00043  *        Exported functions
00044  *----------------------------------------------------------------------------*/
00045 
00046 #define SDRAM_BA0 (1 << 20)
00047 #define SDRAM_BA1 (1 << 21)
00048 
00049 
00050 uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size)
00051 {
00052     uint32_t i;
00053     uint32_t ret = 1;
00054     uint32_t *ptr32 = (uint32_t *) baseAddr;
00055     uint16_t *ptr16 = (uint16_t *) baseAddr;
00056     uint8_t *ptr8 = (uint8_t *) baseAddr;
00057     /* Test for 55AA55AA/AA55AA55 pattern */
00058     printf(" Test for 55AA55AA/AA55AA55 pattern ... \n\r");
00059     for (i = 0; i < size ; i ++) {
00060         if (i & 1) {
00061             ptr32[i] = 0x55AA55AA ;
00062         } else {
00063             ptr32[i] = 0xAA55AA55 ;
00064         }
00065         memory_barrier() 
00066     }
00067     for (i = 0; i <  size ; i++) {
00068         if (i & 1) {
00069             if (ptr32[i] != 0x55AA55AA ) {
00070                 printf("-E- Expected:%x, read %x @ %x \n\r" ,
00071                     0xAA55AA55, (unsigned)ptr32[i], (unsigned)(baseAddr + i));
00072                 ret = 0;
00073                 
00074             }
00075         } else {
00076             if (ptr32[i] != 0xAA55AA55 ) {
00077                 printf("-E- Expected:%x, read %x @ %x \n\r" ,
00078                         0xAA55AA55 , (unsigned)ptr32[i], (unsigned)(baseAddr + i));
00079                 ret = 0;
00080             }
00081         }
00082     }
00083     if (!ret) return ret;
00084     printf(" Test for BYTE accessing... \n\r");
00085     /* Test for BYTE accessing */
00086     for (i = 0; i < size ; i ++) {
00087         ptr8[i] = (uint8_t)( i & 0xFF) ;
00088     }
00089     
00090     for (i = 0; i <  size ; i++) {
00091         if (ptr8[i] != (uint8_t)(i & 0xFF))  {
00092             printf("-E- Expected:%x, read %x @ %x \n\r" ,
00093                 (unsigned)(i & 0xFF), ptr8[i],(unsigned)(baseAddr + i));
00094             ret = 0;
00095         }
00096     }
00097     if (!ret) return ret;
00098     
00099     printf(" Test for WORD accessing... \n\r");
00100     /* Test for WORD accessing */
00101     for (i = 0; i < size / 2 ; i ++) {
00102         ptr16[i] = (uint16_t)( i & 0xFFFF) ;
00103     }
00104     
00105     for (i = 0; i <  size / 2 ; i++) {
00106         if (ptr16[i] != (uint16_t)(i & 0xFFFF))  {
00107             printf("-E- Expected:%x, read %x @ %x \n\r" ,
00108                 (unsigned)(i & 0xFFFF), ptr16[i],(unsigned)(baseAddr + i));
00109             ret = 0;
00110         }
00111     }
00112     if (!ret) return ret;
00113     printf(" Test for DWORD accessing... \n\r");
00114     /* Test for DWORD accessing */
00115     for (i = 0; i < size / 4 ; i ++) {
00116         ptr32[i] = (uint32_t)( i & 0xFFFFFFFF) ;
00117         memory_barrier() 
00118     }
00119     
00120     for (i = 0; i <  size / 4 ; i++) {
00121         if (ptr32[i] != (uint32_t)(i & 0xFFFFFFFF))  {
00122             printf("-E- Expected:%x, read %x @ %x \n\r" ,
00123                 (unsigned)(i & 0xFFFFFFFF), (unsigned)ptr32[i], (unsigned)(baseAddr + i));
00124             ret = 0;
00125         }
00126     }
00127     return ret;
00128 }
00129 
00130 
00131 /**
00132  * \brief Configures the EBI for SDRAM (IS42S16100E-7B) access.
00133  */
00134 
00135 
00136 void BOARD_ConfigureSdram( void )
00137 {
00138     const Pin pinsSdram[] = {BOARD_SDRAM_PINS};
00139     volatile uint32_t i;
00140     volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR;
00141 
00142     /* Configure PIO */
00143     PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram));
00144     PMC_EnablePeripheral(ID_SDRAMC);
00145     MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN;
00146 
00147     /* 1. SDRAM features must be set in the configuration register: 
00148     asynchronous timings (TRC, TRAS, etc.), number of columns, rows, 
00149     CAS latency, and the data bus width. */
00150     SDRAMC->SDRAMC_CR = 
00151           SDRAMC_CR_NC_COL8      // 8 column bits 
00152         | SDRAMC_CR_NR_ROW11     // 12 row bits (4K)
00153         | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 3
00154         | SDRAMC_CR_NB_BANK2     // 2 banks
00155         | SDRAMC_CR_DBW          // 16 bit
00156         | SDRAMC_CR_TWR(4)
00157         | SDRAMC_CR_TRC_TRFC(11) // 63ns   min
00158         | SDRAMC_CR_TRP(5)       // Command period (PRE to ACT) 21 ns min
00159         | SDRAMC_CR_TRCD(5)      // Active Command to read/Write Command delay time 21ns min 
00160         | SDRAMC_CR_TRAS(8)      // Command period (ACT to PRE)  42ns min 
00161         | SDRAMC_CR_TXSR(13U);   // Exit self-refresh to active time  70ns Min
00162 
00163     /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive
00164     strength (DS) and partial array self refresh (PASR) must be set in the
00165     Low Power Register. */
00166 
00167     /* 3. The SDRAM memory type must be set in the Memory Device Register.*/
00168     SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM;
00169 
00170     /* 4. A minimum pause of 200 ¦Ěs is provided to precede any signal toggle.*/
00171     for (i = 0; i < 100000; i++);
00172 
00173     /* 5. (1)A NOP command is issued to the SDRAM devices. The application must
00174     set Mode to 1 in the Mode Register and perform a write access to
00175     any SDRAM address.*/
00176     SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP;
00177     *pSdram = 0;
00178     for (i = 0; i < 100000; i++);
00179     /* 6. An All Banks Precharge command is issued to the SDRAM devices.
00180     The application must set Mode to 2 in the Mode Register and perform a write
00181     access to any SDRAM address. */
00182     SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE;
00183     *pSdram = 0;
00184     for (i = 0; i < 100000; i++);
00185     /* 7. Eight auto-refresh (CBR) cycles are provided. The application must
00186     set the Mode to 4 in the Mode Register and perform a write access to any
00187     SDRAM location eight times.*/
00188     for (i = 0 ; i< 8; i++) {
00189         SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH;
00190         *pSdram = 0;
00191     }
00192     for (i = 0; i < 100000; i++);
00193     /*8. A Mode Register set (MRS) cycle is issued to program the parameters of
00194     the SDRAM devices, in particular CAS latency and burst length. The 
00195     application must set Mode to 3 in the Mode Register and perform a write
00196     access to the SDRAM. The write address must be chosen so that BA[1:0] 
00197     are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns,
00198     4 banks) bank address, the SDRAM write access should be done at the address
00199     0x70000000.*/
00200     SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG;
00201     *pSdram = 0;
00202 
00203     for (i = 0; i < 100000; i++);
00204     /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) 
00205     cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The 
00206     application must set Mode to 5 in the Mode Register and perform a write 
00207     access to the SDRAM. The write address must be chosen so that BA[1] or BA[0]
00208     are set to 1.
00209     For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank
00210     address the SDRAM write access should be done at the address 0x70800000 or 
00211     0x70400000. */
00212     //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG;
00213     // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0;
00214 
00215     /* 10. The application must go into Normal Mode, setting Mode to 0 in the
00216     Mode Register and performing a write access at any location in the SDRAM. */
00217     SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL;
00218     *pSdram = 0;
00219     for (i = 0; i < 100000; i++);
00220     /* 11. Write the refresh rate into the count field in the SDRAMC Refresh
00221     Timer register. (Refresh rate = delay between refresh cycles). 
00222     The SDRAM device requires a refresh every 15.625 ¦Ěs or 7.81 ¦Ěs.
00223     With a 100 MHz frequency, the Refresh Timer Counter Register must be set
00224     with the value 1562(15.625 ¦Ěs x 100 MHz) or 781(7.81 ¦Ěs x 100 MHz). */
00225     // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ¦Ěs
00226     /* ((32 x 10(^-3))/2048) x150 x (10^6) */
00227     SDRAMC->SDRAMC_TR = 2343; ;
00228     SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL;
00229     /* After initialization, the SDRAM devices are fully functional. */
00230 }
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