SAMV71 Xplained Ultra Software Package 1.3

instance_pioe.h

00001 /* ---------------------------------------------------------------------------- */
00002 /*                  Atmel Microcontroller Software Support                      */
00003 /*                       SAM Software Package License                           */
00004 /* ---------------------------------------------------------------------------- */
00005 /* Copyright (c) 2014, Atmel Corporation                                        */
00006 /*                                                                              */
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00011 /*                                                                              */
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00013 /* this list of conditions and the disclaimer below.                            */
00014 /*                                                                              */
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00016 /* this software without specific prior written permission.                     */
00017 /*                                                                              */
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00028 /* ---------------------------------------------------------------------------- */
00029 
00030 #ifndef _SAMV71_PIOE_INSTANCE_
00031 #define _SAMV71_PIOE_INSTANCE_
00032 
00033 /* ========== Register definition for PIOE peripheral ========== */
00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
00035   #define REG_PIOE_PER                      (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
00036   #define REG_PIOE_PDR                      (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
00037   #define REG_PIOE_PSR                      (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
00038   #define REG_PIOE_OER                      (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
00039   #define REG_PIOE_ODR                      (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
00040   #define REG_PIOE_OSR                      (0x400E1618U) /**< \brief (PIOE) Output Status Register */
00041   #define REG_PIOE_IFER                     (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
00042   #define REG_PIOE_IFDR                     (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
00043   #define REG_PIOE_IFSR                     (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
00044   #define REG_PIOE_SODR                     (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
00045   #define REG_PIOE_CODR                     (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
00046   #define REG_PIOE_ODSR                     (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
00047   #define REG_PIOE_PDSR                     (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
00048   #define REG_PIOE_IER                      (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
00049   #define REG_PIOE_IDR                      (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
00050   #define REG_PIOE_IMR                      (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
00051   #define REG_PIOE_ISR                      (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
00052   #define REG_PIOE_MDER                     (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
00053   #define REG_PIOE_MDDR                     (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
00054   #define REG_PIOE_MDSR                     (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
00055   #define REG_PIOE_PUDR                     (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
00056   #define REG_PIOE_PUER                     (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
00057   #define REG_PIOE_PUSR                     (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
00058   #define REG_PIOE_ABCDSR                   (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
00059   #define REG_PIOE_IFSCDR                   (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
00060   #define REG_PIOE_IFSCER                   (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
00061   #define REG_PIOE_IFSCSR                   (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
00062   #define REG_PIOE_SCDR                     (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
00063   #define REG_PIOE_PPDDR                    (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
00064   #define REG_PIOE_PPDER                    (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
00065   #define REG_PIOE_PPDSR                    (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
00066   #define REG_PIOE_OWER                     (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
00067   #define REG_PIOE_OWDR                     (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
00068   #define REG_PIOE_OWSR                     (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
00069   #define REG_PIOE_AIMER                    (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
00070   #define REG_PIOE_AIMDR                    (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */
00071   #define REG_PIOE_AIMMR                    (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
00072   #define REG_PIOE_ESR                      (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
00073   #define REG_PIOE_LSR                      (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
00074   #define REG_PIOE_ELSR                     (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
00075   #define REG_PIOE_FELLSR                   (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */
00076   #define REG_PIOE_REHLSR                   (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */
00077   #define REG_PIOE_FRLHSR                   (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
00078   #define REG_PIOE_LOCKSR                   (0x400E16E0U) /**< \brief (PIOE) Lock Status */
00079   #define REG_PIOE_WPMR                     (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */
00080   #define REG_PIOE_WPSR                     (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */
00081   #define REG_PIOE_SCHMITT                  (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
00082   #define REG_PIOE_KER                      (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */
00083   #define REG_PIOE_KRCR                     (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */
00084   #define REG_PIOE_KDR                      (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */
00085   #define REG_PIOE_KIER                     (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */
00086   #define REG_PIOE_KIDR                     (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */
00087   #define REG_PIOE_KIMR                     (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */
00088   #define REG_PIOE_KSR                      (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */
00089   #define REG_PIOE_KKPR                     (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */
00090   #define REG_PIOE_KKRR                     (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */
00091   #define REG_PIOE_PCMR                     (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
00092   #define REG_PIOE_PCIER                    (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
00093   #define REG_PIOE_PCIDR                    (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
00094   #define REG_PIOE_PCIMR                    (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
00095   #define REG_PIOE_PCISR                    (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
00096   #define REG_PIOE_PCRHR                    (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
00097 #else
00098   #define REG_PIOE_PER     (*(__O  uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
00099   #define REG_PIOE_PDR     (*(__O  uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
00100   #define REG_PIOE_PSR     (*(__I  uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
00101   #define REG_PIOE_OER     (*(__O  uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
00102   #define REG_PIOE_ODR     (*(__O  uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
00103   #define REG_PIOE_OSR     (*(__I  uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
00104   #define REG_PIOE_IFER    (*(__O  uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
00105   #define REG_PIOE_IFDR    (*(__O  uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
00106   #define REG_PIOE_IFSR    (*(__I  uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
00107   #define REG_PIOE_SODR    (*(__O  uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
00108   #define REG_PIOE_CODR    (*(__O  uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
00109   #define REG_PIOE_ODSR    (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
00110   #define REG_PIOE_PDSR    (*(__I  uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
00111   #define REG_PIOE_IER     (*(__O  uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
00112   #define REG_PIOE_IDR     (*(__O  uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
00113   #define REG_PIOE_IMR     (*(__I  uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
00114   #define REG_PIOE_ISR     (*(__I  uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
00115   #define REG_PIOE_MDER    (*(__O  uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
00116   #define REG_PIOE_MDDR    (*(__O  uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
00117   #define REG_PIOE_MDSR    (*(__I  uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
00118   #define REG_PIOE_PUDR    (*(__O  uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
00119   #define REG_PIOE_PUER    (*(__O  uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
00120   #define REG_PIOE_PUSR    (*(__I  uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
00121   #define REG_PIOE_ABCDSR  (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
00122   #define REG_PIOE_IFSCDR  (*(__O  uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
00123   #define REG_PIOE_IFSCER  (*(__O  uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
00124   #define REG_PIOE_IFSCSR  (*(__I  uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
00125   #define REG_PIOE_SCDR    (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
00126   #define REG_PIOE_PPDDR   (*(__O  uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
00127   #define REG_PIOE_PPDER   (*(__O  uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
00128   #define REG_PIOE_PPDSR   (*(__I  uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
00129   #define REG_PIOE_OWER    (*(__O  uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
00130   #define REG_PIOE_OWDR    (*(__O  uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
00131   #define REG_PIOE_OWSR    (*(__I  uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
00132   #define REG_PIOE_AIMER   (*(__O  uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
00133   #define REG_PIOE_AIMDR   (*(__O  uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */
00134   #define REG_PIOE_AIMMR   (*(__I  uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
00135   #define REG_PIOE_ESR     (*(__O  uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
00136   #define REG_PIOE_LSR     (*(__O  uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
00137   #define REG_PIOE_ELSR    (*(__I  uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
00138   #define REG_PIOE_FELLSR  (*(__O  uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */
00139   #define REG_PIOE_REHLSR  (*(__O  uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */
00140   #define REG_PIOE_FRLHSR  (*(__I  uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
00141   #define REG_PIOE_LOCKSR  (*(__I  uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
00142   #define REG_PIOE_WPMR    (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */
00143   #define REG_PIOE_WPSR    (*(__I  uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */
00144   #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
00145   #define REG_PIOE_KER     (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */
00146   #define REG_PIOE_KRCR    (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */
00147   #define REG_PIOE_KDR     (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */
00148   #define REG_PIOE_KIER    (*(__O  uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */
00149   #define REG_PIOE_KIDR    (*(__O  uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */
00150   #define REG_PIOE_KIMR    (*(__I  uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */
00151   #define REG_PIOE_KSR     (*(__I  uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */
00152   #define REG_PIOE_KKPR    (*(__I  uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */
00153   #define REG_PIOE_KKRR    (*(__I  uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */
00154   #define REG_PIOE_PCMR    (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
00155   #define REG_PIOE_PCIER   (*(__O  uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
00156   #define REG_PIOE_PCIDR   (*(__O  uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
00157   #define REG_PIOE_PCIMR   (*(__I  uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
00158   #define REG_PIOE_PCISR   (*(__I  uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
00159   #define REG_PIOE_PCRHR   (*(__I  uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
00160 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
00161 
00162 #endif /* _SAMV71_PIOE_INSTANCE_ */
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