00001 /* ---------------------------------------------------------------------------- */ 00002 /* Atmel Microcontroller Software Support */ 00003 /* SAM Software Package License */ 00004 /* ---------------------------------------------------------------------------- */ 00005 /* Copyright (c) 2014, Atmel Corporation */ 00006 /* */ 00007 /* All rights reserved. */ 00008 /* */ 00009 /* Redistribution and use in source and binary forms, with or without */ 00010 /* modification, are permitted provided that the following condition is met: */ 00011 /* */ 00012 /* - Redistributions of source code must retain the above copyright notice, */ 00013 /* this list of conditions and the disclaimer below. */ 00014 /* */ 00015 /* Atmel's name may not be used to endorse or promote products derived from */ 00016 /* this software without specific prior written permission. */ 00017 /* */ 00018 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00019 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00020 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00021 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00022 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00023 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00024 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00025 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00026 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00027 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00028 /* ---------------------------------------------------------------------------- */ 00029 00030 #ifndef _SAMV71_QSPI_INSTANCE_ 00031 #define _SAMV71_QSPI_INSTANCE_ 00032 00033 /* ========== Register definition for QSPI peripheral ========== */ 00034 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 00035 #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */ 00036 #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */ 00037 #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */ 00038 #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ 00039 #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */ 00040 #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ 00041 #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ 00042 #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ 00043 #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ 00044 #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ 00045 #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ 00046 #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ 00047 #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ 00048 #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ 00049 #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ 00050 #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ 00051 #else 00052 #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */ 00053 #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */ 00054 #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */ 00055 #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ 00056 #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */ 00057 #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ 00058 #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ 00059 #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ 00060 #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ 00061 #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ 00062 #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ 00063 #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ 00064 #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ 00065 #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ 00066 #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ 00067 #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ 00068 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 00069 00070 #endif /* _SAMV71_QSPI_INSTANCE_ */