Data Fields | |
__IO uint32_t | UOTGHS_DEVCTRL |
(Uotghs Offset: 0x0000) Device General Control Register | |
__I uint32_t | UOTGHS_DEVISR |
(Uotghs Offset: 0x0004) Device Global Interrupt Status Register | |
__O uint32_t | UOTGHS_DEVICR |
(Uotghs Offset: 0x0008) Device Global Interrupt Clear Register | |
__O uint32_t | UOTGHS_DEVIFR |
(Uotghs Offset: 0x000C) Device Global Interrupt Set Register | |
__I uint32_t | UOTGHS_DEVIMR |
(Uotghs Offset: 0x0010) Device Global Interrupt Mask Register | |
__O uint32_t | UOTGHS_DEVIDR |
(Uotghs Offset: 0x0014) Device Global Interrupt Disable Register | |
__O uint32_t | UOTGHS_DEVIER |
(Uotghs Offset: 0x0018) Device Global Interrupt Enable Register | |
__IO uint32_t | UOTGHS_DEVEPT |
(Uotghs Offset: 0x001C) Device Endpoint Register | |
__I uint32_t | UOTGHS_DEVFNUM |
(Uotghs Offset: 0x0020) Device Frame Number Register | |
__I uint32_t | Reserved1 [55] |
__IO uint32_t | UOTGHS_DEVEPTCFG [12] |
(Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) | |
__I uint32_t | UOTGHS_DEVEPTISR [12] |
(Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) | |
__O uint32_t | UOTGHS_DEVEPTICR [12] |
(Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) | |
__O uint32_t | UOTGHS_DEVEPTIFR [12] |
(Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) | |
__I uint32_t | UOTGHS_DEVEPTIMR [12] |
(Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) | |
__O uint32_t | UOTGHS_DEVEPTIER [12] |
(Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) | |
__O uint32_t | UOTGHS_DEVEPTIDR [12] |
(Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) | |
__I uint32_t | Reserved2 [48] |
UotghsDevdma | UOTGHS_DEVDMA [UOTGHSDEVDMA_NUMBER] |
(Uotghs Offset: 0x310) n = 1 .. 7 | |
__I uint32_t | Reserved3 [32] |
__IO uint32_t | UOTGHS_HSTCTRL |
(Uotghs Offset: 0x0400) Host General Control Register | |
__I uint32_t | UOTGHS_HSTISR |
(Uotghs Offset: 0x0404) Host Global Interrupt Status Register | |
__O uint32_t | UOTGHS_HSTICR |
(Uotghs Offset: 0x0408) Host Global Interrupt Clear Register | |
__O uint32_t | UOTGHS_HSTIFR |
(Uotghs Offset: 0x040C) Host Global Interrupt Set Register | |
__I uint32_t | UOTGHS_HSTIMR |
(Uotghs Offset: 0x0410) Host Global Interrupt Mask Register | |
__O uint32_t | UOTGHS_HSTIDR |
(Uotghs Offset: 0x0414) Host Global Interrupt Disable Register | |
__O uint32_t | UOTGHS_HSTIER |
(Uotghs Offset: 0x0418) Host Global Interrupt Enable Register | |
__IO uint32_t | UOTGHS_HSTPIP |
(Uotghs Offset: 0x0041C) Host Pipe Register | |
__IO uint32_t | UOTGHS_HSTFNUM |
(Uotghs Offset: 0x0420) Host Frame Number Register | |
__IO uint32_t | UOTGHS_HSTADDR1 |
(Uotghs Offset: 0x0424) Host Address 1 Register | |
__IO uint32_t | UOTGHS_HSTADDR2 |
(Uotghs Offset: 0x0428) Host Address 2 Register | |
__IO uint32_t | UOTGHS_HSTADDR3 |
(Uotghs Offset: 0x042C) Host Address 3 Register | |
__I uint32_t | Reserved4 [52] |
__IO uint32_t | UOTGHS_HSTPIPCFG [12] |
(Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) | |
__I uint32_t | UOTGHS_HSTPIPISR [12] |
(Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) | |
__O uint32_t | UOTGHS_HSTPIPICR [12] |
(Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) | |
__O uint32_t | UOTGHS_HSTPIPIFR [12] |
(Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) | |
__I uint32_t | UOTGHS_HSTPIPIMR [12] |
(Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) | |
__O uint32_t | UOTGHS_HSTPIPIER [12] |
(Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) | |
__O uint32_t | UOTGHS_HSTPIPIDR [12] |
(Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) | |
__IO uint32_t | UOTGHS_HSTPIPINRQ [12] |
(Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) | |
__IO uint32_t | UOTGHS_HSTPIPERR [12] |
(Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) | |
__I uint32_t | Reserved5 [24] |
UotghsHstdma | UOTGHS_HSTDMA [UOTGHSHSTDMA_NUMBER] |
(Uotghs Offset: 0x710) n = 1 .. 7 | |
__I uint32_t | Reserved6 [32] |
__IO uint32_t | UOTGHS_CTRL |
(Uotghs Offset: 0x0800) General Control Register | |
__I uint32_t | UOTGHS_SR |
(Uotghs Offset: 0x0804) General Status Register | |
__O uint32_t | UOTGHS_SCR |
(Uotghs Offset: 0x0808) General Status Clear Register | |
__O uint32_t | UOTGHS_SFR |
(Uotghs Offset: 0x080C) General Status Set Register | |
__IO uint32_t | UOTGHS_TSTA1 |
(Uotghs Offset: 0x0810) General Test A1 Register | |
__IO uint32_t | UOTGHS_TSTA2 |
(Uotghs Offset: 0x0814) General Test A2 Register | |
__I uint32_t | UOTGHS_VERSION |
(Uotghs Offset: 0x0818) General Version Register | |
__I uint32_t | UOTGHS_FEATURES |
(Uotghs Offset: 0x081C) General Features Register | |
__I uint32_t | UOTGHS_ADDRSIZE |
(Uotghs Offset: 0x0820) General APB Address Size Register | |
__I uint32_t | UOTGHS_IPNAME1 |
(Uotghs Offset: 0x0824) General Name Register 1 | |
__I uint32_t | UOTGHS_IPNAME2 |
(Uotghs Offset: 0x0828) General Name Register 2 | |
__I uint32_t | UOTGHS_FSM |
(Uotghs Offset: 0x082C) General Finite State Machine Register |
Definition at line 57 of file component_uotghs.h.