00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036 #include "chip.h"
00037 #include <stdio.h>
00038 #include <string.h>
00039 #include <assert.h>
00040
00041
00042
00043
00044
00045
00046
00047
00048
00049
00050
00051
00052
00053 uint8_t GMAC_IsIdle(Gmac *pGmac)
00054 {
00055 return ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) > 0);
00056 }
00057
00058
00059
00060
00061
00062 void GMAC_PHYMaintain(Gmac *pGmac,
00063 uint8_t bPhyAddr,
00064 uint8_t bRegAddr,
00065 uint8_t bRW,
00066 uint16_t wData)
00067 {
00068
00069 while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);
00070
00071 pGmac->GMAC_MAN = (~GMAC_MAN_WZO & GMAC_MAN_CLTTO)
00072 | (GMAC_MAN_OP(bRW ? 0x2 : 0x1))
00073 | GMAC_MAN_WTN(0x02)
00074 | GMAC_MAN_PHYA(bPhyAddr)
00075 | GMAC_MAN_REGA(bRegAddr)
00076 | GMAC_MAN_DATA(wData) ;
00077 }
00078
00079
00080
00081
00082 uint16_t GMAC_PHYData(Gmac *pGmac)
00083 {
00084
00085 while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0);
00086
00087 return (uint16_t)(pGmac->GMAC_MAN & GMAC_MAN_DATA_Msk);
00088 }
00089
00090
00091
00092
00093
00094
00095
00096
00097 uint8_t GMAC_SetMdcClock( Gmac *pGmac, uint32_t mck )
00098 {
00099 uint32_t clock_dividor;
00100 pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00101 if (mck <= 20000000) {
00102 clock_dividor = GMAC_NCFGR_CLK_MCK_8;
00103 } else if (mck <= 40000000) {
00104 clock_dividor = GMAC_NCFGR_CLK_MCK_16;
00105 } else if (mck <= 80000000) {
00106 clock_dividor = GMAC_NCFGR_CLK_MCK_32;
00107 } else if (mck <= 160000000) {
00108 clock_dividor = GMAC_NCFGR_CLK_MCK_64;
00109 } else if (mck <= 240000000) {
00110 clock_dividor = GMAC_NCFGR_CLK_MCK_96;
00111 } else {
00112 TRACE_ERROR("E: No valid MDC clock.\n\r");
00113 return 0;
00114 }
00115 pGmac->GMAC_NCFGR = (pGmac->GMAC_NCFGR & (~GMAC_NCFGR_CLK_Msk)) | clock_dividor;
00116 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00117 return 1;
00118 }
00119
00120
00121
00122
00123
00124 void GMAC_EnableMdio( Gmac *pGmac )
00125 {
00126 pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00127 pGmac->GMAC_NCR |= GMAC_NCR_MPE;
00128 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00129 }
00130
00131
00132
00133
00134
00135 void GMAC_DisableMdio( Gmac *pGmac )
00136 {
00137 pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00138 pGmac->GMAC_NCR &= ~GMAC_NCR_MPE;
00139 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00140 }
00141
00142
00143
00144
00145
00146 void GMAC_EnableMII( Gmac *pGmac )
00147 {
00148 pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00149 pGmac->GMAC_UR &= ~GMAC_UR_RMII;
00150 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00151 }
00152
00153
00154
00155
00156
00157 void GMAC_EnableGMII( Gmac *pGmac )
00158 {
00159 pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00160
00161 pGmac->GMAC_UR &= ~GMAC_UR_RMII;
00162 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00163 }
00164
00165 #define GMAC_NCFGR_GBE (0x1u << 10)
00166
00167
00168
00169
00170
00171
00172 void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed)
00173 {
00174 pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00175 if (duplex == GMAC_DUPLEX_HALF) {
00176 pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD;
00177 } else {
00178 pGmac->GMAC_NCFGR |= GMAC_NCFGR_FD;
00179 }
00180
00181
00182 if (speed == GMAC_SPEED_10M) {
00183 pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD;
00184 } else if(speed == GMAC_SPEED_100M) {
00185 pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;
00186 } else {
00187 pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD;
00188 }
00189
00190
00191 pGmac->GMAC_UR = 0;
00192 pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE;
00193 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00194 return;
00195 }
00196
00197
00198
00199
00200
00201
00202
00203 void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex)
00204 {
00205 uint32_t ncfgr;
00206 ncfgr = pGmac->GMAC_NCFGR;
00207 ncfgr &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD);
00208 if (speed) {
00209 ncfgr |= GMAC_NCFGR_SPD;
00210 }
00211 if (fullduplex) {
00212 ncfgr |= GMAC_NCFGR_FD;
00213 }
00214 pGmac->GMAC_NCFGR = ncfgr;
00215 pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN);
00216 }
00217
00218
00219
00220
00221
00222 uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac)
00223 {
00224 pGmac->GMAC_NCR |= GMAC_NCR_LBL;
00225 return 0;
00226 }
00227
00228
00229
00230
00231 uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx)
00232 {
00233 if(!queueIdx) {
00234 return pGmac->GMAC_IMR;
00235 } else {
00236 return pGmac->GMAC_IMRPQ[queueIdx -1];
00237 }
00238 }
00239
00240
00241
00242
00243
00244 uint32_t GMAC_GetTxStatus(Gmac *pGmac)
00245 {
00246 return pGmac->GMAC_TSR;
00247 }
00248
00249
00250
00251
00252 void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus)
00253 {
00254 pGmac->GMAC_TSR = dwStatus;
00255 }
00256
00257
00258
00259
00260 uint32_t GMAC_GetRxStatus(Gmac *pGmac)
00261 {
00262 return pGmac->GMAC_RSR;
00263 }
00264
00265
00266
00267
00268 void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus)
00269 {
00270 pGmac->GMAC_RSR = dwStatus;
00271 }
00272
00273
00274
00275
00276
00277 void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis)
00278 {
00279 if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_RXEN;
00280 else pGmac->GMAC_NCR &= ~GMAC_NCR_RXEN;
00281 }
00282
00283
00284
00285
00286 void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis)
00287 {
00288 if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_TXEN;
00289 else pGmac->GMAC_NCR &= ~GMAC_NCR_TXEN;
00290 }
00291
00292
00293
00294
00295
00296 void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx)
00297 {
00298 if(!queueIdx) {
00299 pGmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & dwAddr;
00300 } else {
00301 pGmac->GMAC_RBQBAPQ[queueIdx - 1] = GMAC_RBQB_ADDR_Msk & dwAddr;
00302 }
00303 }
00304
00305
00306
00307
00308 uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx)
00309 {
00310 if(!queueIdx) {
00311 return pGmac->GMAC_RBQB;
00312 } else {
00313 return pGmac->GMAC_RBQBAPQ[queueIdx - 1];
00314 }
00315 }
00316
00317
00318
00319
00320 void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx)
00321 {
00322 if(!queueIdx) {
00323 pGmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & dwAddr;
00324 } else {
00325 pGmac->GMAC_TBQBAPQ[queueIdx - 1] = GMAC_TBQB_ADDR_Msk & dwAddr;
00326 }
00327 }
00328
00329
00330
00331
00332 uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx)
00333 {
00334 if(!queueIdx) {
00335 return pGmac->GMAC_TBQB;
00336 } else {
00337 return pGmac->GMAC_TBQBAPQ[queueIdx - 1];
00338 }
00339 }
00340
00341
00342
00343
00344
00345 void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR)
00346 {
00347 pGmac->GMAC_NCR = bmNCR;
00348 }
00349
00350
00351
00352
00353
00354 uint32_t GMAC_GetNetworkControl(Gmac *pGmac)
00355 {
00356 return pGmac->GMAC_NCR;
00357 }
00358
00359
00360
00361
00362 void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx)
00363 {
00364 if(!queueIdx) {
00365 pGmac->GMAC_IER = dwSources;
00366 } else {
00367 pGmac->GMAC_IERPQ[queueIdx-1] = dwSources;
00368 }
00369 }
00370
00371
00372
00373
00374 void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources)
00375 {
00376 pGmac->GMAC_IDR = dwSources;
00377 pGmac->GMAC_IDRPQ[0] = dwSources;
00378 pGmac->GMAC_IDRPQ[1] = dwSources;
00379 }
00380
00381
00382
00383
00384 void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources)
00385 {
00386 pGmac->GMAC_IER = dwSources;
00387 pGmac->GMAC_IERPQ[0] = dwSources;
00388 pGmac->GMAC_IERPQ[1] = dwSources;
00389 }
00390
00391
00392
00393
00394 void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx)
00395 {
00396 if(!queueIdx) {
00397 pGmac->GMAC_IDR = dwSources;
00398 } else {
00399 pGmac->GMAC_IDRPQ[queueIdx-1] = dwSources;
00400 }
00401 }
00402
00403
00404
00405
00406 uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx)
00407 {
00408 if(!queueIdx) {
00409 return pGmac->GMAC_ISR;
00410 } else {
00411 return pGmac->GMAC_ISRPQ[queueIdx-1];
00412 }
00413 }
00414
00415
00416
00417
00418
00419 void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr)
00420 {
00421 pGmac->GMAC_SA[bIndex].GMAC_SAB = (pMacAddr[3] << 24)
00422 | (pMacAddr[2] << 16)
00423 | (pMacAddr[1] << 8)
00424 | (pMacAddr[0] )
00425 ;
00426 pGmac->GMAC_SA[bIndex].GMAC_SAT = (pMacAddr[5] << 8)
00427 | (pMacAddr[4] )
00428 ;
00429 }
00430
00431
00432
00433
00434 void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB)
00435 {
00436 pGmac->GMAC_SA[bIndex].GMAC_SAB = dwMacB;
00437 pGmac->GMAC_SA[bIndex].GMAC_SAT = dwMacT;
00438 }
00439
00440
00441
00442
00443 void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac)
00444 {
00445 pGmac->GMAC_SA[bIndex].GMAC_SAB = (uint32_t)ddwMac;
00446 pGmac->GMAC_SA[bIndex].GMAC_SAT = (uint32_t)(ddwMac >32);
00447 }
00448
00449
00450
00451
00452
00453 void GMAC_ClearStatistics(Gmac *pGmac)
00454 {
00455 pGmac->GMAC_NCR |= GMAC_NCR_CLRSTAT;
00456 }
00457
00458
00459
00460
00461 void GMAC_IncreaseStatistics(Gmac *pGmac)
00462 {
00463 pGmac->GMAC_NCR |= GMAC_NCR_INCSTAT;
00464 }
00465
00466
00467
00468
00469 void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis)
00470 {
00471 if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_WESTAT;
00472 else pGmac->GMAC_NCR &= ~GMAC_NCR_WESTAT;
00473 }
00474
00475
00476
00477
00478
00479 void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg)
00480 {
00481 pGmac->GMAC_NCFGR = dwCfg;
00482 }
00483
00484
00485
00486
00487
00488 void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx)
00489 {
00490 if(!queueIdx) {
00491 pGmac->GMAC_DCFGR = dwDmaCfg;
00492 } else {
00493 pGmac->GMAC_RBSRPQ[queueIdx-1] = dwDmaCfg;
00494 }
00495 }
00496
00497
00498
00499
00500 uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx)
00501 {
00502 if(!queueIdx) {
00503 return pGmac->GMAC_DCFGR;
00504 } else {
00505 return pGmac->GMAC_RBSRPQ[queueIdx-1];
00506 };
00507 }
00508
00509
00510
00511
00512 uint32_t GMAC_GetConfigure(Gmac *pGmac)
00513 {
00514 return pGmac->GMAC_NCFGR;
00515 }
00516
00517
00518
00519
00520
00521 void GMAC_TransmissionStart(Gmac *pGmac)
00522 {
00523 pGmac->GMAC_NCR |= GMAC_NCR_TSTART;
00524 }
00525
00526
00527
00528
00529 void GMAC_TransmissionHalt(Gmac *pGmac)
00530 {
00531 pGmac->GMAC_NCR |= GMAC_NCR_THALT;
00532 }
00533
00534
00535
00536 void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx)
00537 {
00538 pGmac->GMAC_ST1RPQ[queueIdx] = 0u;
00539 }
00540
00541 void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t regVal)
00542 {
00543 pGmac->GMAC_ST1RPQ[queueIdx] = regVal;
00544 }
00545
00546 void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx)
00547 {
00548 pGmac->GMAC_ST2RPQ[queueIdx] = 0u;
00549 }
00550
00551 void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx, uint32_t regVal)
00552 {
00553 pGmac->GMAC_ST2RPQ[queueIdx] = regVal;
00554 }
00555
00556 void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx, uint16_t etherType)
00557 {
00558 pGmac->GMAC_ST2ER[queueIdx] = (uint32_t)etherType;
00559 }
00560
00561 void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg,
00562 uint16_t c1Reg)
00563 {
00564 pGmac->GMAC_ST2COMP[queueIdx].GMAC_ST2COM0 = c0Reg;
00565 pGmac->GMAC_ST2COMP[queueIdx].GMAC_ST2COM1 = (uint32_t)c1Reg;
00566 memory_barrier();
00567 }
00568
00569
00570 void GMAC_EnableCbsQueA(Gmac *pGmac)
00571 {
00572 pGmac->GMAC_CBSCR |= GMAC_CBSCR_QAE;
00573 }
00574
00575 void GMAC_DisableCbsQueA(Gmac *pGmac)
00576 {
00577 pGmac->GMAC_CBSCR &= ~GMAC_CBSCR_QAE;
00578 }
00579
00580 void GMAC_EnableCbsQueB(Gmac *pGmac)
00581 {
00582 pGmac->GMAC_CBSCR |= GMAC_CBSCR_QBE;
00583 }
00584
00585 void GMAC_DisableCbsQueB(Gmac *pGmac)
00586 {
00587 pGmac->GMAC_CBSCR &= ~GMAC_CBSCR_QBE;
00588 }
00589
00590
00591 void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA)
00592 {
00593
00594 pGmac->GMAC_CBSISQA = idleSlopeA >2u;
00595 }
00596
00597 void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB)
00598 {
00599
00600 pGmac->GMAC_CBSISQB = idleSlopeB >2u;
00601 }
00602
00603 void GMAC_SetTsuTmrIncReg( Gmac *pGmac, uint32_t nanoSec)
00604 {
00605 pGmac->GMAC_TI = nanoSec;
00606 }
00607
00608 uint16_t GMAC_GetPtpEvtMsgRxdMsbSec( Gmac *pGmac )
00609 {
00610 return (uint16_t)(pGmac->GMAC_EFRSH & GMAC_EFRSH_RUD_Msk);
00611 }
00612
00613 uint32_t GMAC_GetPtpEvtMsgRxdLsbSec( Gmac *pGmac )
00614 {
00615 return (pGmac->GMAC_EFRSL & GMAC_EFRSL_RUD_Msk);
00616 }
00617
00618 uint32_t GMAC_GetPtpEvtMsgRxdNanoSec( Gmac *pGmac )
00619 {
00620 return (pGmac->GMAC_EFRN & GMAC_EFRN_RUD_Msk);
00621 }
00622
00623 void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31,
00624 uint32_t nanosec )
00625 {
00626 pGmac->GMAC_SCH = seconds47;
00627 pGmac->GMAC_SCL = seconds31;
00628 pGmac->GMAC_NSC = nanosec;
00629 memory_barrier();
00630 }
00631
00632
00633 void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec)
00634 {
00635 pGmac->GMAC_NSC = nanosec;
00636 }
00637
00638 void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31)
00639 {
00640 pGmac->GMAC_SCL = seconds31;
00641 }
00642
00643 void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47)
00644 {
00645 pGmac->GMAC_SCH = seconds47;
00646 }
00647
00648
00649 uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac)
00650 {
00651 return pGmac->GMAC_EFRSL;
00652 }
00653
00654 uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac)
00655 {
00656 return pGmac->GMAC_EFRN;
00657 }
00658
00659 uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac)
00660 {
00661 return pGmac->GMAC_PEFRSL;
00662 }
00663
00664 uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac)
00665 {
00666 return pGmac->GMAC_PEFRN;
00667 }
00668
00669 uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac)
00670 {
00671 return pGmac->GMAC_EFTSL;
00672 }
00673
00674 uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac)
00675 {
00676 return pGmac->GMAC_EFTN;
00677 }
00678
00679 uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac)
00680 {
00681 return pGmac->GMAC_PEFTSL;
00682 }
00683
00684 uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac)
00685 {
00686 return pGmac->GMAC_PEFTN;
00687 }