Data Structures | |
struct | Wdt |
Wdt hardware registers. More... | |
Defines | |
#define | WDT_CR_WDRSTT (0x1u << 0) |
(WDT_CR) Watchdog Restart | |
#define | WDT_CR_KEY_Pos 24 |
#define | WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) |
(WDT_CR) Password | |
#define | WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) |
#define | WDT_CR_KEY_PASSWD (0xA5u << 24) |
(WDT_CR) Writing any other value in this field aborts the write operation. | |
#define | WDT_MR_WDV_Pos 0 |
#define | WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) |
(WDT_MR) Watchdog Counter Value | |
#define | WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) |
#define | WDT_MR_WDFIEN (0x1u << 12) |
(WDT_MR) Watchdog Fault Interrupt Enable | |
#define | WDT_MR_WDRSTEN (0x1u << 13) |
(WDT_MR) Watchdog Reset Enable | |
#define | WDT_MR_WDDIS (0x1u << 15) |
(WDT_MR) Watchdog Disable | |
#define | WDT_MR_WDD_Pos 16 |
#define | WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) |
(WDT_MR) Watchdog Delta Value | |
#define | WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) |
#define | WDT_MR_WDDBGHLT (0x1u << 28) |
(WDT_MR) Watchdog Debug Halt | |
#define | WDT_MR_WDIDLEHLT (0x1u << 29) |
(WDT_MR) Watchdog Idle Halt | |
#define | WDT_SR_WDUNF (0x1u << 0) |
(WDT_SR) Watchdog Underflow (cleared on read) | |
#define | WDT_SR_WDERR (0x1u << 1) |
(WDT_SR) Watchdog Error (cleared on read) |
SOFTWARE API DEFINITION FOR Watchdog Timer