created by :

generated by : yoesha01

generated from : /home/hw/yoesha01/P4/cc_7/cc312_cerberus/env/src/regs/XL/regdb_iot.xlsx

IDesignSpec rev : idsbatch v 4.12.19.1

XML Revision :

chip : CryptoCell

LEGEND
RO : Read Only
WO : Write Only
RW : Read/Write
RW1: Read/Write once
W1 : Write once
RWC: Read/Write change (Register value changes internally)
RC : Read Change (Readable, register valus changes)
WM : Write Modify (Write triggers an internal FSM)

INDEX
1.1	block: PKA	0x000000000
1.1.1	reg: MEMORY_MAP0	0x000000000
1.1.2	reg: MEMORY_MAP1	0x000000004
1.1.3	reg: MEMORY_MAP2	0x000000008
1.1.4	reg: MEMORY_MAP3	0x00000000C
1.1.5	reg: MEMORY_MAP4	0x000000010
1.1.6	reg: MEMORY_MAP5	0x000000014
1.1.7	reg: MEMORY_MAP6	0x000000018
1.1.8	reg: MEMORY_MAP7	0x00000001C
1.1.9	reg: MEMORY_MAP8	0x000000020
1.1.10	reg: MEMORY_MAP9	0x000000024
1.1.11	reg: MEMORY_MAP10	0x000000028
1.1.12	reg: MEMORY_MAP11	0x00000002C
1.1.13	reg: MEMORY_MAP12	0x000000030
1.1.14	reg: MEMORY_MAP13	0x000000034
1.1.15	reg: MEMORY_MAP14	0x000000038
1.1.16	reg: MEMORY_MAP15	0x00000003C
1.1.17	reg: MEMORY_MAP16	0x000000040
1.1.18	reg: MEMORY_MAP17	0x000000044
1.1.19	reg: MEMORY_MAP18	0x000000048
1.1.20	reg: MEMORY_MAP19	0x00000004C
1.1.21	reg: MEMORY_MAP20	0x000000050
1.1.22	reg: MEMORY_MAP21	0x000000054
1.1.23	reg: MEMORY_MAP22	0x000000058
1.1.24	reg: MEMORY_MAP23	0x00000005C
1.1.25	reg: MEMORY_MAP24	0x000000060
1.1.26	reg: MEMORY_MAP25	0x000000064
1.1.27	reg: MEMORY_MAP26	0x000000068
1.1.28	reg: MEMORY_MAP27	0x00000006C
1.1.29	reg: MEMORY_MAP28	0x000000070
1.1.30	reg: MEMORY_MAP29	0x000000074
1.1.31	reg: MEMORY_MAP30	0x000000078
1.1.32	reg: MEMORY_MAP31	0x00000007C
1.1.33	reg: OPCODE	0x000000080
1.1.34	reg: N_NP_T0_T1_ADDR	0x000000084
1.1.35	reg: PKA_STATUS	0x000000088
1.1.36	reg: PKA_SW_RESET	0x00000008C
1.1.37	reg: PKA_L0	0x000000090
1.1.38	reg: PKA_L1	0x000000094
1.1.39	reg: PKA_L2	0x000000098
1.1.40	reg: PKA_L3	0x00000009C
1.1.41	reg: PKA_L4	0x0000000A0
1.1.42	reg: PKA_L5	0x0000000A4
1.1.43	reg: PKA_L6	0x0000000A8
1.1.44	reg: PKA_L7	0x0000000AC
1.1.45	reg: PKA_PIPE_RDY	0x0000000B0
1.1.46	reg: PKA_DONE	0x0000000B4
1.1.47	reg: PKA_MON_SELECT	0x0000000B8
1.1.48	reg: PKA_VERSION	0x0000000C4
1.1.49	reg: PKA_MON_READ	0x0000000D0
1.1.50	reg: PKA_SRAM_ADDR	0x0000000D4
1.1.51	reg: PKA_SRAM_WDATA	0x0000000D8
1.1.52	reg: PKA_SRAM_RDATA	0x0000000DC
1.1.53	reg: PKA_SRAM_WR_CLR	0x0000000E0
1.1.54	reg: PKA_SRAM_RADDR	0x0000000E4
1.1.55	reg: PKA_WORD_ACCESS	0x0000000F0
1.1.56	reg: PKA_BUFF_ADDR	0x0000000F8
1.2	block: RNG	0x000000100
1.2.1	reg: RNG_IMR	0x000000100
1.2.2	reg: RNG_ISR	0x000000104
1.2.3	reg: RNG_ICR	0x000000108
1.2.4	reg: TRNG_CONFIG	0x00000010C
1.2.5	reg: TRNG_VALID	0x000000110
1.2.6	reg: EHR_DATA_0	0x000000114
1.2.7	reg: EHR_DATA_1	0x000000118
1.2.8	reg: EHR_DATA_2	0x00000011C
1.2.9	reg: EHR_DATA_3	0x000000120
1.2.10	reg: EHR_DATA_4	0x000000124
1.2.11	reg: EHR_DATA_5	0x000000128
1.2.12	reg: RND_SOURCE_ENABLE	0x00000012C
1.2.13	reg: SAMPLE_CNT1	0x000000130
1.2.14	reg: AUTOCORR_STATISTIC	0x000000134
1.2.15	reg: TRNG_DEBUG_CONTROL	0x000000138
1.2.16	reg: RNG_SW_RESET	0x000000140
1.2.17	reg: RNG_DEBUG_EN_INPUT	0x0000001B4
1.2.18	reg: RNG_BUSY	0x0000001B8
1.2.19	reg: RST_BITS_COUNTER	0x0000001BC
1.2.20	reg: RNG_VERSION	0x0000001C0
1.2.21	reg: RNG_CLK_ENABLE	0x0000001C4
1.2.22	reg: RNG_DMA_ENABLE	0x0000001C8
1.2.23	reg: RNG_DMA_SRC_MASK	0x0000001CC
1.2.24	reg: RNG_DMA_SRAM_ADDR	0x0000001D0
1.2.25	reg: RNG_DMA_SAMPLES_NUM	0x0000001D4
1.2.26	reg: RNG_WATCHDOG_VAL	0x0000001D8
1.2.27	reg: RNG_DMA_STATUS	0x0000001DC
1.3	block: CHACHA	0x000000380
1.3.1	reg: CHACHA_CONTROL_REG	0x000000380
1.3.2	reg: CHACHA_VERSION	0x000000384
1.3.3	reg: CHACHA_KEY0	0x000000388
1.3.4	reg: CHACHA_KEY1	0x00000038C
1.3.5	reg: CHACHA_KEY2	0x000000390
1.3.6	reg: CHACHA_KEY3	0x000000394
1.3.7	reg: CHACHA_KEY4	0x000000398
1.3.8	reg: CHACHA_KEY5	0x00000039C
1.3.9	reg: CHACHA_KEY6	0x0000003A0
1.3.10	reg: CHACHA_KEY7	0x0000003A4
1.3.11	reg: CHACHA_IV_0	0x0000003A8
1.3.12	reg: CHACHA_IV_1	0x0000003AC
1.3.13	reg: CHACHA_BUSY	0x0000003B0
1.3.14	reg: CHACHA_HW_FLAGS	0x0000003B4
1.3.15	reg: CHACHA_BLOCK_CNT_LSB	0x0000003B8
1.3.16	reg: CHACHA_BLOCK_CNT_MSB	0x0000003BC
1.3.17	reg: CHACHA_SW_RESET	0x0000003C0
1.3.18	reg: CHACHA_FOR_POLY_KEY0	0x0000003C4
1.3.19	reg: CHACHA_FOR_POLY_KEY1	0x0000003C8
1.3.20	reg: CHACHA_FOR_POLY_KEY2	0x0000003CC
1.3.21	reg: CHACHA_FOR_POLY_KEY3	0x0000003D0
1.3.22	reg: CHACHA_FOR_POLY_KEY4	0x0000003D4
1.3.23	reg: CHACHA_FOR_POLY_KEY5	0x0000003D8
1.3.24	reg: CHACHA_FOR_POLY_KEY6	0x0000003DC
1.3.25	reg: CHACHA_FOR_POLY_KEY7	0x0000003E0
1.3.26	reg: CHACHA_BYTE_WORD_ORDER_CNTL_REG	0x0000003E4
1.3.27	reg: CHACHA_DEBUG_REG	0x0000003E8
1.4	block: AES	0x000000400
1.4.1	reg: AES_KEY_0_0	0x000000400
1.4.2	reg: AES_KEY_0_1	0x000000404
1.4.3	reg: AES_KEY_0_2	0x000000408
1.4.4	reg: AES_KEY_0_3	0x00000040C
1.4.5	reg: AES_KEY_0_4	0x000000410
1.4.6	reg: AES_KEY_0_5	0x000000414
1.4.7	reg: AES_KEY_0_6	0x000000418
1.4.8	reg: AES_KEY_0_7	0x00000041C
1.4.9	reg: AES_KEY_1_0	0x000000420
1.4.10	reg: AES_KEY_1_1	0x000000424
1.4.11	reg: AES_KEY_1_2	0x000000428
1.4.12	reg: AES_KEY_1_3	0x00000042C
1.4.13	reg: AES_KEY_1_4	0x000000430
1.4.14	reg: AES_KEY_1_5	0x000000434
1.4.15	reg: AES_KEY_1_6	0x000000438
1.4.16	reg: AES_KEY_1_7	0x00000043C
1.4.17	reg: AES_IV_0_0	0x000000440
1.4.18	reg: AES_IV_0_1	0x000000444
1.4.19	reg: AES_IV_0_2	0x000000448
1.4.20	reg: AES_IV_0_3	0x00000044C
1.4.21	reg: AES_IV_1_0	0x000000450
1.4.22	reg: AES_IV_1_1	0x000000454
1.4.23	reg: AES_IV_1_2	0x000000458
1.4.24	reg: AES_IV_1_3	0x00000045C
1.4.25	reg: AES_CTR_0_0	0x000000460
1.4.26	reg: AES_CTR_0_1	0x000000464
1.4.27	reg: AES_CTR_0_2	0x000000468
1.4.28	reg: AES_CTR_0_3	0x00000046C
1.4.29	reg: AES_BUSY	0x000000470
1.4.30	reg: AES_SK	0x000000478
1.4.31	reg: AES_CMAC_INIT	0x00000047C
1.4.32	reg: AES_SK1	0x0000004B4
1.4.33	reg: AES_REMAINING_BYTES	0x0000004BC
1.4.34	reg: AES_CONTROL	0x0000004C0
1.4.35	reg: AES_HW_FLAGS	0x0000004C8
1.4.36	reg: AES_CTR_NO_INCREMENT	0x0000004D8
1.4.37	reg: AES_DFA_IS_ON	0x0000004F0
1.4.38	reg: AES_DFA_ERR_STATUS	0x0000004F8
1.4.39	reg: AES_CMAC_SIZE0_KICK	0x000000524
1.5	block: HASH	0x000000640
1.5.1	reg: HASH_H0	0x000000640
1.5.2	reg: HASH_H1	0x000000644
1.5.3	reg: HASH_H2	0x000000648
1.5.4	reg: HASH_H3	0x00000064C
1.5.5	reg: HASH_H4	0x000000650
1.5.6	reg: HASH_H5	0x000000654
1.5.7	reg: HASH_H6	0x000000658
1.5.8	reg: HASH_H7	0x00000065C
1.5.9	reg: HASH_H8	0x000000660
1.5.10	reg: AUTO_HW_PADDING	0x000000684
1.5.11	reg: HASH_XOR_DIN	0x000000688
1.5.12	reg: LOAD_INIT_STATE	0x000000694
1.5.13	reg: HASH_SEL_AES_MAC	0x0000006A4
1.5.14	reg: HASH_VERSION	0x0000007B0
1.5.15	reg: HASH_CONTROL	0x0000007C0
1.5.16	reg: HASH_PAD_EN	0x0000007C4
1.5.17	reg: HASH_PAD_CFG	0x0000007C8
1.5.18	reg: HASH_CUR_LEN_0	0x0000007CC
1.5.19	reg: HASH_CUR_LEN_1	0x0000007D0
1.5.20	reg: HASH_PARAM	0x0000007DC
1.5.21	reg: HASH_AES_SW_RESET	0x0000007E4
1.5.22	reg: HASH_ENDIANESS	0x0000007E8
1.6	block: MISC	0x000000800
1.6.1	reg: AES_CLK_ENABLE	0x000000810
1.6.2	reg: HASH_CLK_ENABLE	0x000000818
1.6.3	reg: PKA_CLK_ENABLE	0x00000081C
1.6.4	reg: DMA_CLK_ENABLE	0x000000820
1.6.5	reg: CLK_STATUS	0x000000824
1.6.6	reg: CHACHA_CLK_ENABLE	0x000000858
1.7	block: CC_CTL	0x000000900
1.7.1	reg: CRYPTO_CTL	0x000000900
1.7.2	reg: CRYPTO_BUSY	0x000000910
1.7.3	reg: HASH_BUSY	0x00000091C
1.7.4	reg: CONTEXT_ID	0x000000930
1.8	block: GHASH	0x000000960
1.8.1	reg: GHASH_SUBKEY_0_0	0x000000960
1.8.2	reg: GHASH_SUBKEY_0_1	0x000000964
1.8.3	reg: GHASH_SUBKEY_0_2	0x000000968
1.8.4	reg: GHASH_SUBKEY_0_3	0x00000096C
1.8.5	reg: GHASH_IV_0_0	0x000000970
1.8.6	reg: GHASH_IV_0_1	0x000000974
1.8.7	reg: GHASH_IV_0_2	0x000000978
1.8.8	reg: GHASH_IV_0_3	0x00000097C
1.8.9	reg: GHASH_BUSY	0x000000980
1.8.10	reg: GHASH_INIT	0x000000984
1.9	block: HOST_RGF	0x000000A00
1.9.1	reg: HOST_RGF_IRR	0x000000A00
1.9.2	reg: HOST_RGF_IMR	0x000000A04
1.9.3	reg: HOST_RGF_ICR	0x000000A08
1.9.4	reg: HOST_RGF_ENDIAN	0x000000A0C
1.9.5	reg: HOST_RGF_SIGNATURE	0x000000A24
1.9.6	reg: HOST_BOOT	0x000000A28
1.9.7	reg: HOST_CRYPTOKEY_SEL	0x000000A38
1.9.8	reg: HOST_CORE_CLK_GATING_ENABLE	0x000000A78
1.9.9	reg: HOST_CC_IS_IDLE	0x000000A7C
1.9.10	reg: HOST_POWERDOWN	0x000000A80
1.9.11	reg: HOST_REMOVE_GHASH_ENGINE	0x000000A84
1.9.12	reg: HOST_REMOVE_CHACHA_ENGINE	0x000000A88
1.10	block: AHB	0x000000B00
1.10.1	reg: AHBM_SINGLES	0x000000B00
1.10.2	reg: AHBM_HPROT	0x000000B04
1.10.3	reg: AHBM_HMASTLOCK	0x000000B08
1.10.4	reg: AHBM_HNONSEC	0x000000B0C
1.11	block: DIN	0x000000C00
1.11.1	reg: DIN_BUFFER	0x000000C00
1.11.2	reg: DIN_MEM_DMA_BUSY	0x000000C20
1.11.3	reg: SRC_LLI_WORD0	0x000000C28
1.11.4	reg: SRC_LLI_WORD1	0x000000C2C
1.11.5	reg: SRAM_SRC_ADDR	0x000000C30
1.11.6	reg: DIN_SRAM_BYTES_LEN	0x000000C34
1.11.7	reg: DIN_SRAM_DMA_BUSY	0x000000C38
1.11.8	reg: DIN_SRAM_ENDIANNESS	0x000000C3C
1.11.9	reg: DIN_CPU_DATA_SIZE	0x000000C48
1.11.10	reg: FIFO_IN_EMPTY	0x000000C50
1.11.11	reg: DIN_FIFO_RST_PNTR	0x000000C58
1.12	block: DOUT	0x000000D00
1.12.1	reg: DOUT_BUFFER	0x000000D00
1.12.2	reg: DOUT_MEM_DMA_BUSY	0x000000D20
1.12.3	reg: DST_LLI_WORD0	0x000000D28
1.12.4	reg: DST_LLI_WORD1	0x000000D2C
1.12.5	reg: SRAM_DEST_ADDR	0x000000D30
1.12.6	reg: DOUT_SRAM_BYTES_LEN	0x000000D34
1.12.7	reg: DOUT_SRAM_DMA_BUSY	0x000000D38
1.12.8	reg: DOUT_SRAM_ENDIANNESS	0x000000D3C
1.12.9	reg: READ_ALIGN_LAST	0x000000D44
1.12.10	reg: DOUT_FIFO_EMPTY	0x000000D50
1.13	block: HOST_SRAM	0x000000F00
1.13.1	reg: SRAM_DATA	0x000000F00
1.13.2	reg: SRAM_ADDR	0x000000F04
1.13.3	reg: SRAM_DATA_READY	0x000000F08
1.14	block: ID_REGISTERS	0x000000F10
1.14.1	reg: PERIPHERAL_ID_4	0x000000FD0
1.14.2	reg: PIDRESERVED0	0x000000FD4
1.14.3	reg: PIDRESERVED1	0x000000FD8
1.14.4	reg: PIDRESERVED2	0x000000FDC
1.14.5	reg: PERIPHERAL_ID_0	0x000000FE0
1.14.6	reg: PERIPHERAL_ID_1	0x000000FE4
1.14.7	reg: PERIPHERAL_ID_2	0x000000FE8
1.14.8	reg: PERIPHERAL_ID_3	0x000000FEC
1.14.9	reg: COMPONENT_ID_0	0x000000FF0
1.14.10	reg: COMPONENT_ID_1	0x000000FF4
1.14.11	reg: COMPONENT_ID_2	0x000000FF8
1.14.12	reg: COMPONENT_ID_3	0x000000FFC
1.15	block: AO	0x000001E00
1.15.1	reg: HOST_DCU_EN0	0x000001E00
1.15.2	reg: HOST_DCU_EN1	0x000001E04
1.15.3	reg: HOST_DCU_EN2	0x000001E08
1.15.4	reg: HOST_DCU_EN3	0x000001E0C
1.15.5	reg: HOST_DCU_LOCK0	0x000001E10
1.15.6	reg: HOST_DCU_LOCK1	0x000001E14
1.15.7	reg: HOST_DCU_LOCK2	0x000001E18
1.15.8	reg: HOST_DCU_LOCK3	0x000001E1C
1.15.9	reg: AO_ICV_DCU_RESTRICTION_MASK0	0x000001E20
1.15.10	reg: AO_ICV_DCU_RESTRICTION_MASK1	0x000001E24
1.15.11	reg: AO_ICV_DCU_RESTRICTION_MASK2	0x000001E28
1.15.12	reg: AO_ICV_DCU_RESTRICTION_MASK3	0x000001E2C
1.15.13	reg: AO_CC_SEC_DEBUG_RESET	0x000001E30
1.15.14	reg: HOST_AO_LOCK_BITS	0x000001E34
1.15.15	reg: AO_APB_FILTERING	0x000001E38
1.15.16	reg: AO_CC_GPPC	0x000001E3C
1.15.17	reg: HOST_RGF_CC_SW_RST	0x000001E40
1.16	block: NVM	0x000001F00
1.16.1	reg: AIB_FUSE_PROG_COMPLETED	0x000001F04
1.16.2	reg: NVM_DEBUG_STATUS	0x000001F08
1.16.3	reg: LCS_IS_VALID	0x000001F0C
1.16.4	reg: NVM_IS_IDLE	0x000001F10
1.16.5	reg: LCS_REG	0x000001F14
1.16.6	reg: HOST_SHADOW_KDR_REG	0x000001F18
1.16.7	reg: HOST_SHADOW_KCP_REG	0x000001F1C
1.16.8	reg: HOST_SHADOW_KCE_REG	0x000001F20
1.16.9	reg: HOST_SHADOW_KPICV_REG	0x000001F24
1.16.10	reg: HOST_SHADOW_KCEICV_REG	0x000001F28
1.16.11	reg: OTP_ADDR_WIDTH_DEF	0x000001F2C
1.17	block: ENV_CC_MEMORIES	0x060004000
1.17.1	reg: ENV_FUSE_READY	0x060004000
1.17.2	reg: ENV_PERF_RAM_MASTER	0x0600040EC
1.17.3	reg: ENV_PERF_RAM_ADDR_HIGH4	0x0600040F0
1.17.4	reg: ENV_FUSES_RAM	0x0600043EC
1.18	block: FPGA_ENV_REGS	0x060005000
1.18.1	reg: ENV_FPGA_PKA_DEBUG_MODE	0x060005024
1.18.2	reg: ENV_FPGA_SCAN_MODE	0x060005030
1.18.3	reg: ENV_FPGA_CC_ALLOW_SCAN	0x060005034
1.18.4	reg: ENV_FPGA_CC_HOST_INT	0x0600050A0
1.18.5	reg: ENV_FPGA_CC_PUB_HOST_INT	0x0600050A4
1.18.6	reg: ENV_FPGA_CC_RST_N	0x0600050A8
1.18.7	reg: ENV_FPGA_RST_OVERRIDE	0x0600050AC
1.18.8	reg: ENV_FPGA_CC_POR_N_ADDR	0x0600050E0
1.18.9	reg: ENV_FPGA_CC_COLD_RST	0x0600050FC
1.18.10	reg: ENV_FPGA_DUMMY_ADDR	0x060005108
1.18.11	reg: ENV_FPGA_COUNTER_CLR	0x060005118
1.18.12	reg: ENV_FPGA_COUNTER_RD	0x06000511C
1.18.13	reg: ENV_FPGA_RNG_DEBUG_ENABLE	0x060005430
1.18.14	reg: ENV_FPGA_CC_LCS	0x06000543C
1.18.15	reg: ENV_FPGA_CC_IS_CM_DM_SECURE_RMA	0x060005440
1.18.16	reg: ENV_FPGA_DCU_EN	0x060005444
1.18.17	reg: ENV_FPGA_CC_LCS_IS_VALID	0x060005448
1.18.18	reg: ENV_FPGA_POWER_DOWN	0x060005478
1.18.19	reg: ENV_FPGA_DCU_H_EN	0x060005484
1.18.20	reg: ENV_FPGA_VERSION	0x060005488
1.18.21	reg: ENV_FPGA_ROSC_WRITE	0x06000548C
1.18.22	reg: ENV_FPGA_ROSC_ADDR	0x060005490
1.18.23	reg: ENV_FPGA_RESET_SESSION_KEY	0x060005494
1.18.24	reg: ENV_FPGA_SESSION_KEY_0	0x0600054A0
1.18.25	reg: ENV_FPGA_SESSION_KEY_1	0x0600054A4
1.18.26	reg: ENV_FPGA_SESSION_KEY_2	0x0600054A8
1.18.27	reg: ENV_FPGA_SESSION_KEY_3	0x0600054AC
1.18.28	reg: ENV_FPGA_SESSION_KEY_VALID	0x0600054B0
1.18.29	reg: ENV_FPGA_SPIDEN	0x0600054D0
1.18.30	reg: ENV_FPGA_AXIM_USER_PARAMS	0x060005600
1.18.31	reg: ENV_FPGA_SECURITY_MODE_OVERRIDE	0x060005604
1.18.32	reg: ENV_FPGA_SRAM_ENABLE	0x060005608
1.18.33	reg: ENV_FPGA_APB_FIPS_ADDR	0x060005650
1.18.34	reg: ENV_FPGA_APB_FIPS_VAL	0x060005654
1.18.35	reg: ENV_FPGA_APB_FIPS_MASK	0x060005658
1.18.36	reg: ENV_FPGA_APB_FIPS_CNT	0x06000565C
1.18.37	reg: ENV_FPGA_APB_FIPS_NEW_ADDR	0x060005660
1.18.38	reg: ENV_FPGA_APB_FIPS_NEW_VAL	0x060005664
1.18.39	reg: ENV_FPGA_APB_PPROT_OVERRIDE	0x060005668
1.18.40	reg: ENV_FPGA_APBP_FIPS_ADDR	0x060005670
1.18.41	reg: ENV_FPGA_APBP_FIPS_VAL	0x060005674
1.18.42	reg: ENV_FPGA_APBP_FIPS_MASK	0x060005678
1.18.43	reg: ENV_FPGA_APBP_FIPS_CNT	0x06000567C
1.18.44	reg: ENV_FPGA_APBP_FIPS_NEW_ADDR	0x060005680
1.18.45	reg: ENV_FPGA_APBP_FIPS_NEW_VAL	0x060005684
1.18.46	reg: ENV_FPGA_AO_CC_GPPC	0x060005700
1.19	block: ENV_PERF_RAM_BASE	0x060006000
1.19.1	reg: ENV_PERF_RAM_BASE	0x060006000

1 : Chip: CryptoCell

0x000000000

Blocks:
PKA
RNG
CHACHA
AES
HASH
MISC
CC_CTL
GHASH
HOST_RGF
AHB
DIN
DOUT
HOST_SRAM
ID_REGISTERS
AO
NVM
ENV_CC_MEMORIES
FPGA_ENV_REGS
ENV_PERF_RAM_BASE

1.1 : Block: PKA

0x000000000

1.1.1 : Reg : MEMORY_MAP0 : 0x000000000
reg sep address : reg host address :
This register maps the virtual register R0 to a physical address in memory.

MEMORY_MAP0

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP0	rw	0x0	Contains the physical address in memory to map the R0 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.2 : Reg : MEMORY_MAP1 : 0x000000004
reg sep address : reg host address :
This register maps the virtual register R1 to a physical address in memory.

MEMORY_MAP1

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP1	rw	0x0	Contains the physical address in memory to map the R1 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.3 : Reg : MEMORY_MAP2 : 0x000000008
reg sep address : reg host address :
This register maps the virtual register R2 to a physical address in memory.

MEMORY_MAP2

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP2	rw	0x0	Contains the physical address in memory to map the R2 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.4 : Reg : MEMORY_MAP3 : 0x00000000C
reg sep address : reg host address :
This register maps the virtual register R3 to a physical address in memory.

MEMORY_MAP3

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP3	rw	0x0	Contains the physical address in memory to map the R3 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.5 : Reg : MEMORY_MAP4 : 0x000000010
reg sep address : reg host address :
This register maps the virtual register R4 to a physical address in memory.

MEMORY_MAP4

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP4	rw	0x0	Contains the physical address in memory to map the R4 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.6 : Reg : MEMORY_MAP5 : 0x000000014
reg sep address : reg host address :
This register maps the virtual register R5 to a physical address in memory.

MEMORY_MAP5

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP5	rw	0x0	Contains the physical address in memory to map the R5 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.7 : Reg : MEMORY_MAP6 : 0x000000018
reg sep address : reg host address :
This register maps the virtual register R6 to a physical address in memory.

MEMORY_MAP6

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP6	rw	0x0	Contains the physical address in memory to map the R6 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.8 : Reg : MEMORY_MAP7 : 0x00000001C
reg sep address : reg host address :
This register maps the virtual register R7 to a physical address in memory.

MEMORY_MAP7

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP7	rw	0x0	Contains the physical address in memory to map the R7 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.9 : Reg : MEMORY_MAP8 : 0x000000020
reg sep address : reg host address :
This register maps the virtual register R8 to a physical address in memory.

MEMORY_MAP8

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP8	rw	0x0	Contains the physical address in memory to map the R8 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.10 : Reg : MEMORY_MAP9 : 0x000000024
reg sep address : reg host address :
This register maps the virtual register R9 to a physical address in memory.

MEMORY_MAP9

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP9	rw	0x0	Contains the physical address in memory to map the R9 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.11 : Reg : MEMORY_MAP10 : 0x000000028
reg sep address : reg host address :
This register maps the virtual register R10 to a physical address in memory.

MEMORY_MAP10

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP10	rw	0x0	Contains the physical address in memory to map the R10 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.12 : Reg : MEMORY_MAP11 : 0x00000002C
reg sep address : reg host address :
This register maps the virtual register R11 to a physical address in memory.

MEMORY_MAP11

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP11	rw	0x0	Contains the physical address in memory to map the R11 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.13 : Reg : MEMORY_MAP12 : 0x000000030
reg sep address : reg host address :
This register maps the virtual register R12 to a physical address in memory.

MEMORY_MAP12

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP12	rw	0x0	Contains the physical address in memory to map the R12 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.14 : Reg : MEMORY_MAP13 : 0x000000034
reg sep address : reg host address :
This register maps the virtual register R13 to a physical address in memory.

MEMORY_MAP13

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP13	rw	0x0	Contains the physical address in memory to map the R13 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.15 : Reg : MEMORY_MAP14 : 0x000000038
reg sep address : reg host address :
This register maps the virtual register R14 to a physical address in memory.

MEMORY_MAP14

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP14	rw	0x0	Contains the physical address in memory to map the R14 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.16 : Reg : MEMORY_MAP15 : 0x00000003C
reg sep address : reg host address :
This register maps the virtual register R15 to a physical address in memory.

MEMORY_MAP15

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP15	rw	0x0	Contains the physical address in memory to map the R15 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.17 : Reg : MEMORY_MAP16 : 0x000000040
reg sep address : reg host address :
This register maps the virtual register R16 to a physical address in memory.

MEMORY_MAP16

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP16	rw	0x0	Contains the physical address in memory to map the R16 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.18 : Reg : MEMORY_MAP17 : 0x000000044
reg sep address : reg host address :
This register maps the virtual register R17 to a physical address in memory.

MEMORY_MAP17

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP17	rw	0x0	Contains the physical address in memory to map the R17 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.19 : Reg : MEMORY_MAP18 : 0x000000048
reg sep address : reg host address :
This register maps the virtual register R18 to a physical address in memory.

MEMORY_MAP18

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP18	rw	0x0	Contains the physical address in memory to map the R18 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.20 : Reg : MEMORY_MAP19 : 0x00000004C
reg sep address : reg host address :
This register maps the virtual register R19 to a physical address in memory.

MEMORY_MAP19

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP19	rw	0x0	Contains the physical address in memory to map the R19 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.21 : Reg : MEMORY_MAP20 : 0x000000050
reg sep address : reg host address :
This register maps the virtual register R20 to a physical address in memory.

MEMORY_MAP20

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP20	rw	0x0	Contains the physical address in memory to map the R20 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.22 : Reg : MEMORY_MAP21 : 0x000000054
reg sep address : reg host address :
This register maps the virtual register R21 to a physical address in memory.

MEMORY_MAP21

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP21	rw	0x0	Contains the physical address in memory to map the R21 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.23 : Reg : MEMORY_MAP22 : 0x000000058
reg sep address : reg host address :
This register maps the virtual register R22 to a physical address in memory.

MEMORY_MAP22

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP22	rw	0x0	Contains the physical address in memory to map the R22 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.24 : Reg : MEMORY_MAP23 : 0x00000005C
reg sep address : reg host address :
This register maps the virtual register R23 to a physical address in memory.

MEMORY_MAP23

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP23	rw	0x0	Contains the physical address in memory to map the R23 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.25 : Reg : MEMORY_MAP24 : 0x000000060
reg sep address : reg host address :
This register maps the virtual register R24 to a physical address in memory.

MEMORY_MAP24

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP24	rw	0x0	Contains the physical address in memory to map the R24 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.26 : Reg : MEMORY_MAP25 : 0x000000064
reg sep address : reg host address :
This register maps the virtual register R25 to a physical address in memory.

MEMORY_MAP25

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP25	rw	0x0	Contains the physical address in memory to map the R25 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.27 : Reg : MEMORY_MAP26 : 0x000000068
reg sep address : reg host address :
This register maps the virtual register R26 to a physical address in memory.

MEMORY_MAP26

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP26	rw	0x0	Contains the physical address in memory to map the R26 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.28 : Reg : MEMORY_MAP27 : 0x00000006C
reg sep address : reg host address :
This register maps the virtual register R27 to a physical address in memory.

MEMORY_MAP27

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP27	rw	0x0	Contains the physical address in memory to map the R27 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.29 : Reg : MEMORY_MAP28 : 0x000000070
reg sep address : reg host address :
This register maps the virtual register R28 to a physical address in memory.

MEMORY_MAP28

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP28	rw	0x0	Contains the physical address in memory to map the R28 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.30 : Reg : MEMORY_MAP29 : 0x000000074
reg sep address : reg host address :
This register maps the virtual register R29 to a physical address in memory.

MEMORY_MAP29

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP29	rw	0x0	Contains the physical address in memory to map the R29 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.31 : Reg : MEMORY_MAP30 : 0x000000078
reg sep address : reg host address :
This register maps the virtual register R30 to a physical address in memory.

MEMORY_MAP30

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP30	rw	0x0	Contains the physical address in memory to map the R30 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.32 : Reg : MEMORY_MAP31 : 0x00000007C
reg sep address : reg host address :
This register maps the virtual register R31 to a physical address in memory.

MEMORY_MAP31

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
10:1	MEMORY_MAP31	rw	0x0	Contains the physical address in memory to map the R31 register to.
31:11	RESERVED1	rw	0x0	Reserved

1.1.33 : Reg : OPCODE : 0x000000080
reg sep address : reg host address :
This register holds the PKA's OPCODE.

OPCODE

bits	Field name	permission	default	Description
5:0	TAG	rw	0x0	Holds the opreation's tag or the operand C virtual address.
11:6	REG_R	rw	0x0	Result register virtual address 0-15.
17:12	REG_B	rw	0x0	Operand B virtual address 0-15.
23:18	REG_A	rw	0x0	Operand A virtual address 0-15.
26:24	LEN	rw	0x0	The length of the operation. The value serves as a pointer to PKA length register, for example, if the value is 0, PKA_L0 holds the size of the operation.
31:27	OPCODE	rw	0x0	Defines the PKA operation: @0x4 - Add,Inc @0x5 - Sub,Dec,Neg @0x6 - ModAdd,ModInc @0x7 - ModSub,ModDec,ModNeg @0x8 - AND,TST0,CLR0 @0x9 - OR,COPY,SET0 @0xa - XOR,FLIP0,INVERT,COMPARE @0xc - SHR0 @0xd - SHR1 @0xe - SHL0 @0xf - SHL1 @0x10 - MulLow @0x11 - ModMul @0x12 - ModMulN @0x13 - ModExp @0x14 - Division @0x15 - Div @0x16 - ModDiv @0x00 - Terminate

1.1.34 : Reg : N_NP_T0_T1_ADDR : 0x000000084
reg sep address : reg host address :
This register maps N_NP_T0_T1 to a virtual address.

N_NP_T0_T1_ADDR

bits	Field name	permission	default	Description
4:0	N_VIRTUAL_ADDR	rw	0x0	Virtual address of register N.
9:5	NP_VIRTUAL_ADDR	rw	0x1	Virtual address of register NP.
14:10	T0_VIRTUAL_ADDR	rw	0x	Virtual address of temporary register number 0
19:15	T1_VIRTUAL_ADDR	rw	0x	Virtual address of temporary register number 1
31:20	Reserved	rw	0x0	Reserved

1.1.35 : Reg : PKA_STATUS : 0x000000088
reg sep address : reg host address :
This register holds the PKA pipe status.

PKA_STATUS

bits	Field name	permission	default	Description
3:0	ALU_MSB_4BITS	ro	0x0	The most significant 4-bits of the operand updated in shift operation.
7:4	ALU_LSB_4BITS	ro	0x0	The least significant 4-bits of the operand updated in shift operation.
8:8	ALU_SIGN_OUT	ro	0x0	Indicates the last operation's sign (MSB).
9:9	ALU_CARRY	ro	0x0	Holds the carry of the last ALU operation.
10:10	ALU_CARRY_MOD	ro	0x0	holds the carry of the last Modular operation.
11:11	ALU_SUB_IS_ZERO	ro	0x0	Indicates the last subtraction operation's sign .
12:12	ALU_OUT_ZERO	ro	0x1	Indicates if the result of ALU OUT is zero.
13:13	ALU_MODOVRFLW	ro	0x0	Modular overflow flag.
14:14	DIV_BY_ZERO	ro	0x0	Indication if the division is done by zero.
15:15	MODINV_OF_ZERO	ro	0x0	Indicates the Modular inverse of zero.
20:16	OPCODE	ro	0x0	Opcode of the last operation
31:21	RESERVED	ro	0x0	Reserved

1.1.36 : Reg : PKA_SW_RESET : 0x00000008C
reg sep address : reg host address :
Writing to this register triggers a software reset of the PKA.

PKA_SW_RESET

bits	Field name	permission	default	Description
0:0	PKA_SW_RESET	wo	0x0	The reset mechanism takes about four PKA clock cycles until the reset line is deasserted
31:1	RESERVED	wo	0x0	Reserved

1.1.37 : Reg : PKA_L0 : 0x000000090
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L0

bits	Field name	permission	default	Description
12:0	PKA_L0	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.38 : Reg : PKA_L1 : 0x000000094
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L1

bits	Field name	permission	default	Description
12:0	PKA_L1	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.39 : Reg : PKA_L2 : 0x000000098
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L2

bits	Field name	permission	default	Description
12:0	PKA_L2	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.40 : Reg : PKA_L3 : 0x00000009C
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L3

bits	Field name	permission	default	Description
12:0	PKA_L3	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.41 : Reg : PKA_L4 : 0x0000000A0
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L4

bits	Field name	permission	default	Description
12:0	PKA_L4	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.42 : Reg : PKA_L5 : 0x0000000A4
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L5

bits	Field name	permission	default	Description
12:0	PKA_L5	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.43 : Reg : PKA_L6 : 0x0000000A8
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L6

bits	Field name	permission	default	Description
12:0	PKA_L6	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.44 : Reg : PKA_L7 : 0x0000000AC
reg sep address : reg host address :
This register holds one of the optional size of the operation.

PKA_L7

bits	Field name	permission	default	Description
12:0	PKA_L7	rw	0x0	Size of the operation in bytes.
31:13	RESERVED	rw	0x0	Reserved

1.1.45 : Reg : PKA_PIPE_RDY : 0x0000000B0
reg sep address : reg host address :
This register indicates whether the PKA pipe is ready to receive a new OPCODE.

PKA_PIPE_RDY

bits	Field name	permission	default	Description
0:0	PKA_PIPE_RDY	ro	0x1	Indication whether PKA pipe is ready for new OPCODE.
31:1	RESERVED	ro	0x0	Reserved

1.1.46 : Reg : PKA_DONE : 0x0000000B4
reg sep address : reg host address :
This register indicates whether PKA operation is completed.

PKA_DONE

bits	Field name	permission	default	Description
0:0	PKA_DONE	ro	0x1	Indicates if PKA operation is completed, and pipe is empty.
31:1	RESERVED	ro	0x0	Reserved

1.1.47 : Reg : PKA_MON_SELECT : 0x0000000B8
reg sep address : reg host address :
This register defines which PKA FSM monitor is being output.

PKA_MON_SELECT

bits	Field name	permission	default	Description
3:0	PKA_MON_SELECT	rw	0x0	Defines which PKA FSM monitor is being output.
31:4	RESERVED	rw	0x0	Reserved

1.1.48 : Reg : PKA_VERSION : 0x0000000C4
reg sep address : reg host address :
This register holds the pka version

PKA_VERSION

bits	Field name	permission	default	Description
31:0	PKA_VERSION	ro	0x	This is the PKA version

1.1.49 : Reg : PKA_MON_READ : 0x0000000D0
reg sep address : reg host address :
The PKA monitor bus register.

PKA_MON_READ

bits	Field name	permission	default	Description
31:0	PKA_MON_READ	ro	0x0	This is the PKA monitor bus register output

1.1.50 : Reg : PKA_SRAM_ADDR : 0x0000000D4
reg sep address : reg host address :
first address given to PKA SRAM for write transactions.

PKA_SRAM_ADDR

bits	Field name	permission	default	Description
31:0	PKA_SRAM_ADDR	wo	0x0	PKA SRAM write starting address

1.1.51 : Reg : PKA_SRAM_WDATA : 0x0000000D8
reg sep address : reg host address :
Write data to PKA SRAM.

PKA_SRAM_WDATA

bits	Field name	permission	default	Description
31:0	PKA_SRAM_WDATA	wo	0x0	32 bit write to PKA SRAM: triggers the SRAM write DMA address automatically incremented

1.1.52 : Reg : PKA_SRAM_RDATA : 0x0000000DC
reg sep address : reg host address :
Read data from PKA SRAM.

PKA_SRAM_RDATA

bits	Field name	permission	default	Description
31:0	PKA_SRAM_RDATA	r/wc	0x0	32 bit read from PKA SRAM: read - triggers the SRAM read DMA address automatically incremented

1.1.53 : Reg : PKA_SRAM_WR_CLR : 0x0000000E0
reg sep address : reg host address :
Write buffer clean.

PKA_SRAM_WR_CLR

bits	Field name	permission	default	Description
31:0	PKA_SRAM_WR_CLR	wo	0x0	Clear the write buffer.

1.1.54 : Reg : PKA_SRAM_RADDR : 0x0000000E4
reg sep address : reg host address :
first address given to PKA SRAM for read transactions.

PKA_SRAM_RADDR

bits	Field name	permission	default	Description
31:0	PKA_SRAM_RADDR	wo	0x0	PKA SRAM read starting address

1.1.55 : Reg : PKA_WORD_ACCESS : 0x0000000F0
reg sep address : reg host address :
This register holds the data written to PKA memory using the wop opcode.

PKA_WORD_ACCESS

bits	Field name	permission	default	Description
31:0	PKA_WORD_ACCESS	wo	0x0	32 bit read/write data.

1.1.56 : Reg : PKA_BUFF_ADDR : 0x0000000F8
reg sep address : reg host address :
This register maps the virtual buffer registers to a physical address in memory.

PKA_BUFF_ADDR

bits	Field name	permission	default	Description
11:0	PKA_BUF_ADDR	wo	0x0	Contains the physical address in memory to map the buffer registers.
31:12	RESEREVED1	wo	0x0	Reserved

(top of block)

1.2 : Block: RNG

0x000000100

1.2.1 : Reg : RNG_IMR : 0x000000100
reg sep address : reg host address :
Interrupt masking register.
Consists of {prng_imr trng_imr} bit[31-16] - PRNG_IMR bit[15-0] - TRNG_IMR
(Ws - PRNG bit exists only if PRNG_EXISTS flag)

RNG_IMR

bits	Field name	permission	default	Description
0:0	EHR_VALID_INT_MASK	rw	0x1	1'b1 - masks the EHR interrupt. No interrupt is generated. See RNG_ISR for explanation on this interrupt.
1:1	AUTOCORR_ERR_INT_MASK	rw	0x1	1'b1 - masks the autocorrelation interrupt. No interrupt is generated. See RNG_ISR for explanation on this interrupt.
2:2	CRNGT_ERR_INT_MASK	rw	0x1	1'b1 - masks the CRNGT error interrupt. No interrupt is generated. See RNG_ISR for explanation on this interrupt.
3:3	VN_ERR_INT_MASK	rw	0x1	1'b1 - masks the Von-Neumann error interrupt. No interrupt is generated. See RNG_ISR for explanation on this interrupt.
4:4	WATCHDOG_INT_MASK	rw	0x1	1'b1 - masks the watchdog interrupt. No interrupt is generated. See RNG_ISR for explanation on this interrupt.
5:5	RNG_DMA_DONE_INT	rw	0x1	1'b1 - masks the RNG DMA completion interrupt. No interrupt is generated. See RNG_ISR for explanation on this interrupt.
31:6	RESERVED	rw	0x0	Reserved

1.2.2 : Reg : RNG_ISR : 0x000000104
reg sep address : reg host address :
Status register.
If corresponding RNG_IMR bit is unmasked, an interrupt is generated.
Consists of trng_isr and prng_isr bit[15-0] - TRNG bit[31-16] - PRNG

RNG_ISR

bits	Field name	permission	default	Description
0:0	EHR_VALID	ro	0x0	1'b1 indicates that 192 bits have been collected in the TRNG and are ready to be read.
1:1	AUTOCORR_ERR	ro	0x0	1'b1 indicates Autocorrelation test failed four times in a row. When it set ,TRNG ceases to function until next reset.
2:2	CRNGT_ERR	ro	0x0	1'b1 indicates CRNGT in the TRNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal.
3:3	VN_ERR	ro	0x0	1'b1 indicates Von Neumann error. Error in von Neumann occurs if 32 consecutive collected bits are identical, ZERO, or ONE.
4:4	RESERVED0	ro	0x0	Reserved
5:5	RNG_DMA_DONE	ro	0x0	1'b1 indicates RNG DMA to SRAM is completed.
15:6	RESERVED1	ro	0x0	Reserved
16:16	RESEEDING_DONE	ro	0x0	1'b1 indicates completion of reseeding algorithm with no errors.
17:17	INSTANTIATION_DONE	ro	0x0	1'b1 indicates completion of instantiation algorithm with no errors.
18:18	FINAL_UPDATE_DONE	ro	0x0	1'b1 indicates completion of final update algorithm.
19:19	OUTPUT_READY	ro	0x0	1'b1 indicates that the result of PRNG is valid and ready to be read. The result can be read from the RNG_READOUT register.
20:20	RESEED_CNTR_FULL	ro	0x0	1'b1 indicates that the reseed counter has reached 2^48, requiring to run the reseed algorithm before generating new random numbers.
21:21	RESEED_CNTR_TOP_40	ro	0x0	1'b1 indicates that the top 40 bits of the reseed counter are set (that is the reseed counter is larger than 2^48-2^8). This is a recommendation for running the reseed algorithm before the counter reaches its max value.
22:22	PRNG_CRNGT_ERR	ro	0x0	1'b1 indicates CRNGT in the PRNG test failed. Failure occurs when two consecutive results of AES are equal
23:23	REQ_SIZE	ro	0x0	1'b1 indicates that the request size counter (which represents how many generations of random bits in the PRNG have been produced) has reached 2^12, thus requiring a working state update before generating new random numbers.
24:24	KAT_ERR	ro	0x0	1'b1 indicates that one of the KAT (Known Answer Tests) tests has failed. When set, the entire engine ceases to function.
26:25	WHICH_KAT_ERR	ro	0x0	When the KAT_ERR bit is set, these bits represent which Known Answer Test had failed: @2'b00 - first test of instantiation @2'b01 - second test of instantiation @2'b10 - first test of reseeding @2'b11 - second test of reseeding
31:27	RESERVED	ro	0x0	Reserved

1.2.3 : Reg : RNG_ICR : 0x000000108
reg sep address : reg host address :
Interrupt/status bit clear Register. Consists of trng_icr and prng_icr bit[15-0] - TRNG bit[31-16] - PRNG

RNG_ICR

bits	Field name	permission	default	Description
0:0	EHR_VALID	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
1:1	AUTOCORR_ERR	wo	0x0	Cannot be cleared by SW! Only RNG reset clears this bit.
2:2	CRNGT_ERR	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
3:3	VN_ERR	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
4:4	RNG_WATCHDOG	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
5:5	RNG_DMA_DONE	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
15:6	RESERVED0	wo	0x0	Reserved
16:16	RESEEDING_DONE	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
17:17	INSTANTIATION_DONE	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
18:18	FINAL_UPDATE_DONE	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
19:19	OUTPUT_READY	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
20:20	RESEED_CNTR_FULL	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
21:21	RESEED_CNTR_TOP_40	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
22:22	PRNG_CRNGT_ERR	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
23:23	REQ_SIZE	wo	0x0	Writing value 1'b1 - clears corresponding bit in RNG_ISR
24:24	KAT_ERR	wo	0x0	Cannot be cleared by SW! Only RNG reset clears this bit.
26:25	WHICH_KAT_ERR	wo	0x0	Cannot be cleared by SW! Only RNG reset clears this bit.
31:27	RESERVED1	wo	0x0	Reserved

1.2.4 : Reg : TRNG_CONFIG : 0x00000010C
reg sep address : reg host address :
This register handles TRNG configuration

TRNG_CONFIG

bits	Field name	permission	default	Description
1:0	RND_SRC_SEL	rw	0x0	Defines the length of the oscillator ring (= the number of inverters) out of four possible selections.
2:2	SOP_SEL	rw	0x0	Secure Output Port selection: @1'b1 - sop_data port reflects TRNG output (EHR_DATA). @1'b0 - sop_data port reflects PRNG output (RNG_READOUT). NOTE: Secure output is used for direct connection of the RNG block outputs to an engine input key. If CryptoCell does not include a HW PRNG - this field should be set to 1.
31:3	RESERVED	rw	0x0	Reserved

1.2.5 : Reg : TRNG_VALID : 0x000000110
reg sep address : reg host address :
This register indicates that the TRNG data is valid.

TRNG_VALID

bits	Field name	permission	default	Description
0:0	EHR_VALID	ro	0x0	1'b1 indicates that collection of bits in the TRNG is completed, and data can be read from the EHR_DATA register.
31:1	RESERVED	ro	0x0	Reserved

1.2.6 : Reg : EHR_DATA_0 : 0x000000114
reg sep address : reg host address :
This register contains the data collected in the TRNG[31_0].
NOTE: can only be set while in debug mode (rng_debug_enable input is set).

EHR_DATA_0

bits	Field name	permission	default	Description
31:0	EHR_DATA	ro	0x0	Contains the data collected in the TRNG[31_0] . NOTE: can only be set while in debug mode (rng_debug_enable input is set).

1.2.7 : Reg : EHR_DATA_1 : 0x000000118
reg sep address : reg host address :
This register contains the data collected in the TRNG[63_32].
NOTE: can only be set while in debug mode (rng_debug_enable input is set).

EHR_DATA_1

bits	Field name	permission	default	Description
31:0	EHR_DATA	ro	0x0	Contains the data collected in the TRNG[63_32]. NOTE: can only be set while in debug mode (rng_debug_enable input is set).

1.2.8 : Reg : EHR_DATA_2 : 0x00000011C
reg sep address : reg host address :
This register contains the data collected in the TRNG[95_64].
NOTE: can only be set while in debug mode (rng_debug_enable input is set).

EHR_DATA_2

bits	Field name	permission	default	Description
31:0	EHR_DATA	ro	0x0	Contains the data collected in the TRNG[95_64]. NOTE: can only be set while in debug mode (rng_debug_enable input is set).

1.2.9 : Reg : EHR_DATA_3 : 0x000000120
reg sep address : reg host address :
This register contains the data collected in the TRNG[127_96].
NOTE: can only be set while in debug mode (rng_debug_enable input is set).

EHR_DATA_3

bits	Field name	permission	default	Description
31:0	EHR_DATA	ro	0x0	Contains the data collected in the TRNG[127_96]. NOTE: can only be set while in debug mode (rng_debug_enable input is set).

1.2.10 : Reg : EHR_DATA_4 : 0x000000124
reg sep address : reg host address :
This register contains the data collected in the TRNG[159_128].
NOTE: can only be set while in debug mode (rng_debug_enable input is set).

EHR_DATA_4

bits	Field name	permission	default	Description
31:0	EHR_DATA	ro	0x0	Contains the data collected in the TRNG[159_128]. NOTE: can only be set while in debug mode (rng_debug_enable input is set).

1.2.11 : Reg : EHR_DATA_5 : 0x000000128
reg sep address : reg host address :
This register contains the data collected in the TRNG[191_160].
NOTE: can only be set while in debug mode (rng_debug_enable input is set).

EHR_DATA_5

bits	Field name	permission	default	Description
31:0	EHR_DATA	ro	0x0	Contains the data collected in the TRNG[191_160]. NOTE: can only be set while in debug mode (rng_debug_enable input is set).

1.2.12 : Reg : RND_SOURCE_ENABLE : 0x00000012C
reg sep address : reg host address :
This register holds the enable signal for the random source.

RND_SOURCE_ENABLE

bits	Field name	permission	default	Description
0:0	RND_SRC_EN	rw	0x0	Enable signal for the random source.
31:1	RESERVED	rw	0x0	Reserved

1.2.13 : Reg : SAMPLE_CNT1 : 0x000000130
reg sep address : reg host address :
Counts clocks between sampling of random bit.

SAMPLE_CNT1

bits	Field name	permission	default	Description
31:0	SAMPLE_CNTR1	rw	0x	Sets the number of rng_clk cycles between two consecutive ring oscillator samples. NOTE: If the Von-Neumann is bypassed, the minimum value for sample counter must not be less than decimal seventeen.

1.2.14 : Reg : AUTOCORR_STATISTIC : 0x000000134
reg sep address : reg host address :
Statistics about autocorrelation test activations.

AUTOCORR_STATISTIC

bits	Field name	permission	default	Description
13:0	AUTOCORR_TRYS	r/wc	0x0	Count each time an autocorrelation test starts. Any write to the register resets the counter. Stops collecting statistics if one of the counters has reached the limit.
21:14	AUTOCORR_FAILS	r/wc	0x0	Count each time an autocorrelation test fails. Any write to the register resets the counter. Stops collecting statistics if one of the counters has reached the limit.
31:22	RESERVED	r/wc	0x0	Reserved

1.2.15 : Reg : TRNG_DEBUG_CONTROL : 0x000000138
reg sep address : reg host address :
This register is used to debug the TRNG

TRNG_DEBUG_CONTROL

bits	Field name	permission	default	Description
0:0	RESERVED0	rw	0x0	Reserved
1:1	VNC_BYPASS	rw	0x0	When this bit is set, the Von-Neumann balancer is bypassed (including the 32 consecutive bits test). NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, this bit can be set while not in debug mode.
2:2	TRNG_CRNGT_BYPASS	rw	0x0	When this bit is set, the CRNGT test in the TRNG is bypassed. NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, this bit can be set while not in debug mode.
3:3	AUTO_CORRELATE_BYPASS	rw	0x0	When this bit is set, the autocorrelation test in the TRNG module is bypassed. NOTE: Can only be set while in debug mode. If TRNG_TESTS_BYPASS_EN HW flag is defined, this bit can be set while not in debug mode.
31:4	RESERVED1	rw	0x0	Reserved

1.2.16 : Reg : RNG_SW_RESET : 0x000000140
reg sep address : reg host address :
Generate SW reset solely to RNG block.

RNG_SW_RESET

bits	Field name	permission	default	Description
0:0	RNG_SW_RESET	r/wc	0x0	Any value written (1'b0 or 1'b1) causes a reset cycle to the TRNG block. The reset mechanism takes about four RNG clock cycles until the reset line is de-asserted.
31:1	RESERVED	r/wc	0x0	Reserved

1.2.17 : Reg : RNG_DEBUG_EN_INPUT : 0x0000001B4
reg sep address : reg host address :
Defines the RNG in debug mode

RNG_DEBUG_EN_INPUT

bits	Field name	permission	default	Description
0:0	RNG_DEBUG_EN	ro	0x0	Reflects the rng_debug_enable input port
31:1	RESERVED	ro	0x0	Reserved

1.2.18 : Reg : RNG_BUSY : 0x0000001B8
reg sep address : reg host address :
RNG busy indication

RNG_BUSY

bits	Field name	permission	default	Description
0:0	RNG_BUSY	ro	0x0	Reflects rng_busy output port which Consists of trng_busy and prng_busy.
1:1	TRNG_BUSY	ro	0x0	Reflects trng_busy.
2:2	PRNG_BUSY	ro	0x0	Reflects prng_busy.
31:3	RESERVED	ro	0x0	Reserved

1.2.19 : Reg : RST_BITS_COUNTER : 0x0000001BC
reg sep address : reg host address :
Resets the counter of collected bits in the TRNG

RST_BITS_COUNTER

bits	Field name	permission	default	Description
0:0	RST_BITS_COUNTER	wo	0x0	Writing any value to this address resets the bits counter and trng valid registers. RND_SORCE_ENABLE register must be unset in order for reset to take place.
31:1	RESERVED	wo	0x0	Reserved

1.2.20 : Reg : RNG_VERSION : 0x0000001C0
reg sep address : reg host address :
This register holds the RNG version

RNG_VERSION

bits	Field name	permission	default	Description
0:0	EHR_WIDTH_192	ro	0x1	@1'b0 - 128 bit EHR @1'b1 - 192 bit EHR
1:1	CRNGT_EXISTS	ro	0x1	@1'b0 - does not exist @1'b1 - exists
2:2	AUTOCORR_EXISTS	ro	0x1	@1'b0 - does not exist @1'b1 - exists
3:3	TRNG_TESTS_BYPASS_EN	ro	0x1	@1'b0 - trng tests bypass not enabled @1'b1 - trng tests bypass enabled
4:4	PRNG_EXISTS	ro	0x0	@1'b0 - does not exist @1'b1 - exists
5:5	KAT_EXISTS	ro	0x0	@1'b0 - does not exist @1'b1 - exists
6:6	RESEEDING_EXISTS	ro	0x0	@1'b0 - does not exist @1'b1 - exists
7:7	RNG_USE_5_SBOXES	ro	0x0	@1'b0 - 20 SBOX AES @1'b1 - 5 SBOX AES
31:8	RESERVED	ro	0x0	Reserved

1.2.21 : Reg : RNG_CLK_ENABLE : 0x0000001C4
reg sep address : reg host address :
Writing to this register enables/disables the RNG clock.

RNG_CLK_ENABLE

bits	Field name	permission	default	Description
0:0	EN	wo	0x0	Writing value 1'b1 enables RNG clock.
31:1	RESERVED	wo	0x0	Reserved

1.2.22 : Reg : RNG_DMA_ENABLE : 0x0000001C8
reg sep address : reg host address :
Writing to this register enables/disables the RNG DMA.

RNG_DMA_ENABLE

bits	Field name	permission	default	Description
0:0	EN	r/wc	0x0	Writing value 1'b1 enables RNG DMA to SRAM. The Value is cleared when DMA completes its operation.
31:1	RESERVED	r/wc	0x0	Reserved

1.2.23 : Reg : RNG_DMA_SRC_MASK : 0x0000001CC
reg sep address : reg host address :
This register defines which ring-oscillator length should be used when using the RNG DMA.

RNG_DMA_SRC_MASK

bits	Field name	permission	default	Description
0:0	EN_SRC_SEL0	rw	0x0	Writing value 1'b1 enables SRC_SEL 0.
1:1	EN_SRC_SEL1	rw	0x0	Writing value 1'b1 enables SRC_SEL 1.
2:2	EN_SRC_SEL2	rw	0x0	Writing value 1'b1 enables SRC_SEL 2.
3:3	EN_SRC_SEL3	rw	0x0	Writing value 1'b1 enables SRC_SEL 3.
31:4	RESERVED	rw	0x0	Reserved

1.2.24 : Reg : RNG_DMA_SRAM_ADDR : 0x0000001D0
reg sep address : reg host address :
This register defines the start address of the DMA for the TRNG data.

RNG_DMA_SRAM_ADDR

bits	Field name	permission	default	Description
10:0	RNG_SRAM_DMA_ADDR	rw	0x0	Defines the start address of the DMA for the TRNG data.
31:11	RESERVED	rw	0x0	Reserved

1.2.25 : Reg : RNG_DMA_SAMPLES_NUM : 0x0000001D4
reg sep address : reg host address :
This register defines the number of 192-bits samples that the DMA collects per RNG configuration.

RNG_DMA_SAMPLES_NUM

bits	Field name	permission	default	Description
7:0	RNG_SAMPLES_NUM	rw	0x0	Defines the number of 192-bits samples that the DMA collects per RNG configuration.
31:8	RESERVED	rw	0x0	Reserved

1.2.26 : Reg : RNG_WATCHDOG_VAL : 0x0000001D8
reg sep address : reg host address :
This register defines the maximum number of clock cycles per TRNG collection of 192 samples. If the number of cycles for a collection exceeds this threshold, TRNG signals an interrupt.

RNG_WATCHDOG_VAL

bits	Field name	permission	default	Description
31:0	RNG_WATCHDOG_VAL	rw	0x0	Defines the maximum number of clock cycles per TRNG collection of 192 samples. If the number of cycles for a collection exceeds this threshold, TRNG signals an interrupt.

1.2.27 : Reg : RNG_DMA_STATUS : 0x0000001DC
reg sep address : reg host address :
This register holds the RNG DMA status.

RNG_DMA_STATUS

bits	Field name	permission	default	Description
0:0	RNG_DMA_BUSY	ro	0x0	Indicates whether DMA is busy.
2:1	DMA_SRC_SEL	ro	0x0	The active ring oscillator length using by DMA
10:3	NUM_OF_SAMPLES	ro	0x0	Number of samples already collected in the current ring oscillator chain length.
31:11	RESERVED	ro	0x0	Reserved

(top of block)

1.3 : Block: CHACHA

0x000000380

1.3.1 : Reg : CHACHA_CONTROL_REG : 0x000000380
reg sep address : reg host address :
CHACHA general configuration.

CHACHA_CONTROL_REG

bits	Field name	permission	default	Description
0:0	CHACHA_OR_SALSA	r/wc	0x0	Core: @1'b0 - ChaCha mode. @1'b1 - Salsa mode.
1:1	INIT_FROM_HOST	r/wc	0x0	Start init for new Message: @1'b0 - disable. @1'b1 - enable.
2:2	CALC_KEY_FOR_POLY1305	r/wc	0x0	Only if ChaCha core: @1'b0 - disable. @1'b1 - enable.
3:3	KEY_LEN	r/wc	0x0	For All Core: @1'b0 - 256 bit. @1'b1 - 128 bit.
5:4	NUM_OF_ROUNDS	r/wc	0x0	The core of ChaCha is a hash function which based on rotation operations. The hash function consist in application of 20 rounds (default value). In additional, ChaCha have two variants (they work exactly as the original algorithm): ChaCha20/8 and ChaCha20/12 (using 8 and 12 rounds). Default value 00 @00 - 20 rounds @01 - 12 rounds @10 - 8 rounds @11 - N/A
8:6	RESERVED	r/wc	0x0	Reserved
9:9	RESET_BLOCK_CNT	r/wc	0x0	For new message
10:10	USE_IV_96BIT	r/wc	0x0	If use 96bit IV
31:11	RESERVED1	r/wc	0x0	Reserved1

1.3.2 : Reg : CHACHA_VERSION : 0x000000384
reg sep address : reg host address :
CHACHA Version

CHACHA_VERSION

bits	Field name	permission	default	Description
31:0	CHACHA_VERSION	ro	0x1

1.3.3 : Reg : CHACHA_KEY0 : 0x000000388
reg sep address : reg host address :
bits 255:224 of CHACHA Key

CHACHA_KEY0

bits	Field name	permission	default	Description
31:0	CHACHA_KEY0	wo	0x0	bits 255:224 of CHACHA Key

1.3.4 : Reg : CHACHA_KEY1 : 0x00000038C
reg sep address : reg host address :
bits 223:192 of CHACHA Key

CHACHA_KEY1

bits	Field name	permission	default	Description
31:0	CHACHA_KEY1	wo	0x0	bits 223:192 of CHACHA Key

1.3.5 : Reg : CHACHA_KEY2 : 0x000000390
reg sep address : reg host address :
bits191:160 of CHACHA Key

CHACHA_KEY2

bits	Field name	permission	default	Description
31:0	CHACHA_KEY2	wo	0x0	bits191:160 of CHACHA Key

1.3.6 : Reg : CHACHA_KEY3 : 0x000000394
reg sep address : reg host address :
bits159:128 of CHACHA Key

CHACHA_KEY3

bits	Field name	permission	default	Description
31:0	CHACHA_KEY3	wo	0x0	bits 159:128 of CHACHA Key

1.3.7 : Reg : CHACHA_KEY4 : 0x000000398
reg sep address : reg host address :
bits 127:96 of CHACHA Key

CHACHA_KEY4

bits	Field name	permission	default	Description
31:0	CHACHA_KEY4	wo	0x0	bits 127:96 of CHACHA Key

1.3.8 : Reg : CHACHA_KEY5 : 0x00000039C
reg sep address : reg host address :
bits 95:64 of CHACHA Key

CHACHA_KEY5

bits	Field name	permission	default	Description
31:0	CHACHA_KEY5	wo	0x0	bits 95:64 of CHACHA Key

1.3.9 : Reg : CHACHA_KEY6 : 0x0000003A0
reg sep address : reg host address :
bits 63:32 of CHACHA Key

CHACHA_KEY6

bits	Field name	permission	default	Description
31:0	CHACHA_KEY6	wo	0x0	bits 63:32 of CHACHA Key

1.3.10 : Reg : CHACHA_KEY7 : 0x0000003A4
reg sep address : reg host address :
bits 31:0 of CHACHA Key

CHACHA_KEY7

bits	Field name	permission	default	Description
31:0	CHACHA_KEY7	wo	0x0	bits 31:0 of CHACHA Key

1.3.11 : Reg : CHACHA_IV_0 : 0x0000003A8
reg sep address : reg host address :
bits 31:0 of CHACHA_IV0 register

CHACHA_IV_0

bits	Field name	permission	default	Description
31:0	CHACHA_IV_0	rw	0x0	bits 31:0 of CHACHA_IV0 register

1.3.12 : Reg : CHACHA_IV_1 : 0x0000003AC
reg sep address : reg host address :
bits 31:0 of CHACHA_IV1 register

CHACHA_IV_1

bits	Field name	permission	default	Description
31:0	CHACHA_IV_1	rw	0x0	bits 31:0 of CHACHA_IV1 register

1.3.13 : Reg : CHACHA_BUSY : 0x0000003B0
reg sep address : reg host address :
This register is set when the CHACHA/SALSA core is active

CHACHA_BUSY

bits	Field name	permission	default	Description
0:0	CHACHA_BUSY	ro	0x0	CHACHA_BUSY Register. this register is set when the CHACHA/SALSA core is active
31:1	RESERVED	ro	0x0	Reserved

1.3.14 : Reg : CHACHA_HW_FLAGS : 0x0000003B4
reg sep address : reg host address :
This register holds the pre-synthesis HW flag configuration of the CHACHA/SALSA engine

CHACHA_HW_FLAGS

bits	Field name	permission	default	Description
0:0	CHACHA_EXISTS	ro	0x1	If this flag is set, the Salsa/ChaCha engine include ChaCha implementation: @1'b0 - disable. @1'b1 - enable.
1:1	SALSA_EXISTS	ro	0x0	If this flag is set, the Salsa/ChaCha engine include Salsa implementation: @1'b0 - disable. @1'b1 - enable.
2:2	FAST_CHACHA	ro	0x0	If this flag is set, the next matrix calculated when the current one is written to data output path (same flag for Salsa core): @1'b0 - disable. @1'b1 - enable.
31:3	RESERVED	ro	0x0	Reserved

1.3.15 : Reg : CHACHA_BLOCK_CNT_LSB : 0x0000003B8
reg sep address : reg host address :
The two first words (n) in the last row of the cipher matrix are the block counter. At the end of each block (512b), the block_cnt for the next block is written by HW to the block_cnt_lsb and block_cnt_msb registers. Need reset block counter , if start new message.

CHACHA_BLOCK_CNT_LSB

bits	Field name	permission	default	Description
31:0	CHACHA_BLOCK_CNT_LSB	rw	0x0	bits 31:0 of CHACHA_BLOCK_CNT_LSB register. This register holds the chacha block counter bits 31:0

1.3.16 : Reg : CHACHA_BLOCK_CNT_MSB : 0x0000003BC
reg sep address : reg host address :
The two first words (n) in the last row of the cipher matrix are the block counter. At the end of each block (512b), the block_cnt for the next block is written by HW to the block_cnt_lsb and block_cnt_msb registers. Need reset block counter , if start new message.

CHACHA_BLOCK_CNT_MSB

bits	Field name	permission	default	Description
31:0	CHACHA_BLOCK_CNT_MSB	rw	0x0	bits 31:0 of CHACHA_BLOCK_CNT_MSB register. This register holds the chacha block counter bits 63:32

1.3.17 : Reg : CHACHA_SW_RESET : 0x0000003C0
reg sep address : reg host address :
Resets CHACHA/SALSA engine.

CHACHA_SW_RESET

bits	Field name	permission	default	Description
0:0	CHACH_SW_RESET	wo	0x0	Writing to this address resets the only FSM of CHACHA engine. The reset takes 4 CORE_CLK cycles.
31:1	RESERVED	wo	0x0	Reserved

1.3.18 : Reg : CHACHA_FOR_POLY_KEY0 : 0x0000003C4
reg sep address : reg host address :
bits 255:224 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY0

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY0	ro	0x0	bits 255:224 of CHACHA_FOR_POLY_KEY

1.3.19 : Reg : CHACHA_FOR_POLY_KEY1 : 0x0000003C8
reg sep address : reg host address :
bits 223:192 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY1

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY1	ro	0x0	bits 223:192 of CHACHA_FOR_POLY_KEY

1.3.20 : Reg : CHACHA_FOR_POLY_KEY2 : 0x0000003CC
reg sep address : reg host address :
bits191:160 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY2

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY2	ro	0x0	bits191:160 of CHACHA_FOR_POLY_KEY

1.3.21 : Reg : CHACHA_FOR_POLY_KEY3 : 0x0000003D0
reg sep address : reg host address :
bits159:128 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY3

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY3	ro	0x0	bits 159:128 of CHACHA_FOR_POLY_KEY

1.3.22 : Reg : CHACHA_FOR_POLY_KEY4 : 0x0000003D4
reg sep address : reg host address :
bits 127:96 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY4

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY4	ro	0x0	bits 127:96 of CHACHA_FOR_POLY_KEY

1.3.23 : Reg : CHACHA_FOR_POLY_KEY5 : 0x0000003D8
reg sep address : reg host address :
bits 95:64 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY5

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY5	ro	0x0	bits 95:64 of CHACHA_FOR_POLY_KEY

1.3.24 : Reg : CHACHA_FOR_POLY_KEY6 : 0x0000003DC
reg sep address : reg host address :
bits 63:32 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY6

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY6	ro	0x0	bits 63:32 of CHACHA_FOR_POLY_KEY

1.3.25 : Reg : CHACHA_FOR_POLY_KEY7 : 0x0000003E0
reg sep address : reg host address :
bits 31:0 of CHACHA_FOR_POLY_KEY

CHACHA_FOR_POLY_KEY7

bits	Field name	permission	default	Description
31:0	CHACHA_FOR_POLY_KEY7	ro	0x0	bits 31:0 of CHACHA_FOR_POLY_KEY

1.3.26 : Reg : CHACHA_BYTE_WORD_ORDER_CNTL_REG : 0x0000003E4
reg sep address : reg host address :
CHACHA/SALSA DATA ORDER configuration.

CHACHA_BYTE_WORD_ORDER_CNTL_REG

bits	Field name	permission	default	Description
0:0	CHACHA_DIN_WORD_ORDER	rw	0x0	Change the words order of the input data. @1'b0 - disable. @1'b1 - enable. (reverse each word in 128 bit input ( w0->w3, w1->w2, w2->w1,w3-w0))
1:1	CHACHA_DIN_BYTE_ORDER	rw	0x0	Change the byte order of the input data. @1'b0 - disable. @1'b1 - enable. (reverse each byte in each word input (b0->b3, b1->b2, b2->b1,b3->b0))
2:2	CHACHA_CORE_MATRIX_LBE_ORDER	rw	0x0	Change the quarter of a matrix order in core @1'b0 - disable. @1'b1 - enable. (reverse each quarter of a matrix (m[0-127]->m[384-511], m[128-255]->m[256-383], m[256-383]->m[128-255], m[384-511]->m[0-127]))
3:3	CHACHA_DOUT_WORD_ORDER	rw	0x0	Change the words order of the output data. @1'b0 - disable. @1'b1 - enable. (reverse each word in 128 bit output ( w0->w3, w1->w2, w2->w1,w3-w0))
4:4	CHACHA_DOUT_BYTE_ORDER	rw	0x0	Change the byte order of the output data. @1'b0 - disable. @1'b1 - enable. (reverse each byte in each word output (b0->b3, b1->b2, b2->b1,b3->b0))
31:5	RESERVED	rw	0x0	Reserved

1.3.27 : Reg : CHACHA_DEBUG_REG : 0x0000003E8
reg sep address : reg host address :
This register is used to debug the CHACHA engine

CHACHA_DEBUG_REG

bits	Field name	permission	default	Description
1:0	CHACHA_DEBUG_FSM_STATE	ro	0x0	CHACHA_DEBUG_FSM_STATE @0x0 - IDLE_STATE @0x1 - INIT_STATE @0x2 - ROUNDS_STATE @0x3 - FINAL_STATE
31:2	RESERVED	ro	0x0	Reserved

(top of block)

1.4 : Block: AES

0x000000400

1.4.1 : Reg : AES_KEY_0_0 : 0x000000400
reg sep address : reg host address :
bits 31:0 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_0

bits	Field name	permission	default	Description
31:0	AES_KEY_0_0	wo	0x0	bits 31:0 of AES Key0.

1.4.2 : Reg : AES_KEY_0_1 : 0x000000404
reg sep address : reg host address :
bits 63:32 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_1

bits	Field name	permission	default	Description
31:0	AES_KEY_0_1	wo	0x0	bits 63:32 of AES Key0.

1.4.3 : Reg : AES_KEY_0_2 : 0x000000408
reg sep address : reg host address :
bits 95:64 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_2

bits	Field name	permission	default	Description
31:0	AES_KEY_0_2	wo	0x0	bits 95:64 of AES Key0.

1.4.4 : Reg : AES_KEY_0_3 : 0x00000040C
reg sep address : reg host address :
bits 127:96 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_3

bits	Field name	permission	default	Description
31:0	AES_KEY_0_3	wo	0x0	bits 127:96 of AES Key0.

1.4.5 : Reg : AES_KEY_0_4 : 0x000000410
reg sep address : reg host address :
bits 159:128 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_4

bits	Field name	permission	default	Description
31:0	AES_KEY_0_4	wo	0x0	bits 159:128 of AES Key0 .

1.4.6 : Reg : AES_KEY_0_5 : 0x000000414
reg sep address : reg host address :
bits 191:160 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_5

bits	Field name	permission	default	Description
31:0	AES_KEY_0_5	wo	0x0	bits 191:160 of AES Key0.

1.4.7 : Reg : AES_KEY_0_6 : 0x000000418
reg sep address : reg host address :
bits 223:192 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_6

bits	Field name	permission	default	Description
31:0	AES_KEY_0_6	wo	0x0	bits 223:192 of AES Key0.

1.4.8 : Reg : AES_KEY_0_7 : 0x00000041C
reg sep address : reg host address :
bits 255:224 of AES Key0 (used as the AES key in non-tunneling operations, and as the first tunnel stage key in tunneling operations).

AES_KEY_0_7

bits	Field name	permission	default	Description
31:0	AES_KEY_0_7	wo	0x0	bits 255:224 of AES Key0.

1.4.9 : Reg : AES_KEY_1_0 : 0x000000420
reg sep address : reg host address :
bits 31:0 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_0

bits	Field name	permission	default	Description
31:0	AES_KEY_1_0	wo	0x0	bits 31:0 of AES Key1.

1.4.10 : Reg : AES_KEY_1_1 : 0x000000424
reg sep address : reg host address :
bits 63:32 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_1

bits	Field name	permission	default	Description
31:0	AES_KEY_1_1	wo	0x0	bits 63:32 of AES Key1.

1.4.11 : Reg : AES_KEY_1_2 : 0x000000428
reg sep address : reg host address :
bits 95:64 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_2

bits	Field name	permission	default	Description
31:0	AES_KEY_1_2	wo	0x0	bits 95:64 of AES Key1.

1.4.12 : Reg : AES_KEY_1_3 : 0x00000042C
reg sep address : reg host address :
bits 127:96 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_3

bits	Field name	permission	default	Description
31:0	AES_KEY_1_3	wo	0x0	bits 127:96 of AES Key1.

1.4.13 : Reg : AES_KEY_1_4 : 0x000000430
reg sep address : reg host address :
bits 159:128 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_4

bits	Field name	permission	default	Description
31:0	AES_KEY_1_4	wo	0x0	bits 159:128 of AES Key1.

1.4.14 : Reg : AES_KEY_1_5 : 0x000000434
reg sep address : reg host address :
bits 191:160 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_5

bits	Field name	permission	default	Description
31:0	AES_KEY_1_5	wo	0x0	bits 191:160 of AES Key1.

1.4.15 : Reg : AES_KEY_1_6 : 0x000000438
reg sep address : reg host address :
bits 223:192 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_6

bits	Field name	permission	default	Description
31:0	AES_KEY_1_6	wo	0x0	bits 223:192 of AES Key1.

1.4.16 : Reg : AES_KEY_1_7 : 0x00000043C
reg sep address : reg host address :
bits 255:224 of AES Key1 (used as the second AES tunnel stage key in tunneling operations).

AES_KEY_1_7

bits	Field name	permission	default	Description
31:0	AES_KEY_1_7	wo	0x0	bits 255:224 of AES Key1.

1.4.17 : Reg : AES_IV_0_0 : 0x000000440
reg sep address : reg host address :
bits 31:0 of AES_IV0 register.
AES IV0 is used as the AES IV (Initialization Value) register in non-tunneling operations,
and as the first tunnel stage IV register in tunneling operations.
The IV register should be loaded according to the AES mode:
in AES CBC/CBC-MAC - the AES IV register should be loaded with the IV (initialization vector).
in XTS-AES - the AES IV register should be loaded with the 'T' value (unless the HW T calculation mode is active, in which the 'T' value is calculated by the HW).

AES_IV_0_0

bits	Field name	permission	default	Description
31:0	AES_IV_0_0	r/wc	0x0	bits 31:0 of AES_IV0 register. For the description of AES_IV0, see the AES_IV_0_0 register description

1.4.18 : Reg : AES_IV_0_1 : 0x000000444
reg sep address : reg host address :
bits 63:32 of AES_IV0 128b register.
For the description of AES_IV0, see the AES_IV_0_0 register description

AES_IV_0_1

bits	Field name	permission	default	Description
31:0	AES_IV_0_1	r/wc	0x0	bits 63:32 of AES_IV0 register. For the description of AES_IV0, see the AES_IV_0_0 register description

1.4.19 : Reg : AES_IV_0_2 : 0x000000448
reg sep address : reg host address :
bits 95:64 of AES_IV0 128b register.
For the description of AES_IV0, see the AES_IV_0_0 register description

AES_IV_0_2

bits	Field name	permission	default	Description
31:0	AES_IV_0_2	r/wc	0x0	bits 95:64 of AES_IV0 register. For the description of AES_IV0, see the AES_IV_0_0 register description

1.4.20 : Reg : AES_IV_0_3 : 0x00000044C
reg sep address : reg host address :
bits 127:96 of AES_IV0 128b register.
For the description of AES_IV0, see the AES_IV_0_0 register description

AES_IV_0_3

bits	Field name	permission	default	Description
31:0	AES_IV_0_3	r/wc	0x0	bits 127:96 of AES_IV0 register. For the description of AES_IV0, see the AES_IV_0_0 register description

1.4.21 : Reg : AES_IV_1_0 : 0x000000450
reg sep address : reg host address :
bits 31:0 of AES_IV1 128b register.
AES IV1 is used as the AES IV (Initialization Value) register as the second tunnel stage IV register in tunneling operations.
The IV register should be loaded according to the AES mode:
in AES CBC/CBC-MAC - the AES IV register should be loaded with the IV (initialization vector).
in XTS-AES - the AES IV register should be loaded with the 'T' value (unless the HW T calculation mode is active, in which the 'T' value is calculated by the HW.

AES_IV_1_0

bits	Field name	permission	default	Description
31:0	AES_IV_1_0	r/wc	0x0	bits 31:0 of AES_IV1 register. For the description of AES_IV1, see the AES_IV_1_0 register description

1.4.22 : Reg : AES_IV_1_1 : 0x000000454
reg sep address : reg host address :
bits 63:32 of AES_IV1 128b register.
For the description of AES_IV1, see the AES_IV_1_0 register description

AES_IV_1_1

bits	Field name	permission	default	Description
31:0	AES_IV_1_1	r/wc	0x0	bits 63:32 of AES_IV1 register. For the description of AES_IV1, see the AES_IV_1_0 register description

1.4.23 : Reg : AES_IV_1_2 : 0x000000458
reg sep address : reg host address :
bits 95:64 of AES_IV1 128b register.
For the description of AES_IV1, see the AES_IV_1_0 register description

AES_IV_1_2

bits	Field name	permission	default	Description
31:0	AES_IV_1_2	r/wc	0x0	bits 95:64 of AES_IV1 register. For the description of AES_IV1, see the AES_IV_1_0 register description

1.4.24 : Reg : AES_IV_1_3 : 0x00000045C
reg sep address : reg host address :
bits 127:96 of AES_IV1 128b register.
For the description of AES_IV1, see the AES_IV_1_0 register description

AES_IV_1_3

bits	Field name	permission	default	Description
31:0	AES_IV_1_3	r/wc	0x0	bits 127:96 of AES_IV1 register. For the description of AES_IV1, see the AES_IV_1_0 register description

1.4.25 : Reg : AES_CTR_0_0 : 0x000000460
reg sep address : reg host address :
bits 31:0 of AES_CTR0 128b register.
AES CTR0 is used as the AES CTR (counter) register in non-tunneling operations, and as the first tunnel stage CTR register in tunneling operations.
The CTR register should be loaded according to the AES mode:
in AES CTR/GCTR - the AES CTR register should be loaded with the counter value.
in XTS-AES - the AES CTR register should be loaded with the 'i' value (in order to calculate the T value from it, if HW T calculation is supported).

AES_CTR_0_0

bits	Field name	permission	default	Description
31:0	AES_CTR_0_0	r/wc	0x0	bits 31:0 of AES_CTR0 register. For the description of AES_CTR0, see the AES_CTR_0_0 register description

1.4.26 : Reg : AES_CTR_0_1 : 0x000000464
reg sep address : reg host address :
bits 63:32 of AES_CTR0 128b register.
For the description of AES_CTR0, see the AES_CTR_0_0 register description.

AES_CTR_0_1

bits	Field name	permission	default	Description
31:0	AES_CTR_0_1	r/wc	0x0	bits 63:32 of AES_CTR0 register. For the description of AES_CTR0, see the AES_CTR_0_0 register description

1.4.27 : Reg : AES_CTR_0_2 : 0x000000468
reg sep address : reg host address :
bits 95:64 of AES_CTR0 128b register.
For the description of AES_CTR0, see the AES_CTR_0_0 register description.

AES_CTR_0_2

bits	Field name	permission	default	Description
31:0	AES_CTR_0_2	r/wc	0x0	bits 95:64 of AES_CTR0 register. For the description of AES_CTR0, see the AES_CTR_0_0 register description

1.4.28 : Reg : AES_CTR_0_3 : 0x00000046C
reg sep address : reg host address :
bits 127:96 of AES_CTR0 128b register.
For the description of AES_CTR0, see the AES_CTR_0_0 register description.

AES_CTR_0_3

bits	Field name	permission	default	Description
31:0	AES_CTR_0_3	r/wc	0x0	bits 127:96 of AES_CTR0 register. For the description of AES_CTR0, see the AES_CTR_0_0 register description

1.4.29 : Reg : AES_BUSY : 0x000000470
reg sep address : reg host address :
This register is set when the AES core is active

AES_BUSY

bits	Field name	permission	default	Description
0:0	AES_BUSY	ro	0x0	AES_BUSY Register. this register is set when the AES core is active
31:1	RESERVED	ro	0x0	31'b0

1.4.30 : Reg : AES_SK : 0x000000478
reg sep address : reg host address :
writing to this address causes sampling of the HW key to the AES_KEY0 register

AES_SK

bits	Field name	permission	default	Description
0:0	AES_SK	wm	0x0	writing to this address causes sampling of the HW key to the AES_KEY0 register
31:1	RESERVED	wm	0x0	Reserved

1.4.31 : Reg : AES_CMAC_INIT : 0x00000047C
reg sep address : reg host address :
Writing to this address triggers the AES engine generating of K1 and K2 for AES CMAC operations.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

AES_CMAC_INIT

bits	Field name	permission	default	Description
0:0	AES_CMAC_INIT	wo	0x0	Writing to this address starts the generating of K1 and K2 for AES CMAC operations
31:1	RESERVED	wo	0x0	Reserved

1.4.32 : Reg : AES_SK1 : 0x0000004B4
reg sep address : reg host address :
writing to this address causes sampling of the HW key to the AES_KEY1 register

AES_SK1

bits	Field name	permission	default	Description
0:0	AES_SK1	wm	0x0	writing to this address causes sampling of the HW key to the AES_KEY1 register
31:1	RESERVED	wm	0x0	Reserved

1.4.33 : Reg : AES_REMAINING_BYTES : 0x0000004BC
reg sep address : reg host address :
This register should be set with the amount of remaining bytes until the end of the current AES operation. The AES engine counts down from this value to determine the last / one before last blocks in AES CMAC, XTS AES and AES CCM.

AES_REMAINING_BYTES

bits	Field name	permission	default	Description
31:0	AES_REMAINING_BYTES	r/wc	0x0	This register should be set with the amount of remaining bytes until the end of the current AES operation. The AES engine counts down from this value to determine the last / one before last blocks in AES CMAC, XTS AES and AES CCM.

1.4.34 : Reg : AES_CONTROL : 0x0000004C0
reg sep address : reg host address :
This register holds the configuration of the AES engine
Note: This is a special register, affected by internal logic. Test result of this register is NA.

AES_CONTROL

bits	Field name	permission	default	Description
0:0	DEC_KEY0	rw	0x0	This field determines whether the AES performs Decrypt/Encrypt operations, in non-tunneling operations: @0 - Encrypt @1 - Decrypt
1:1	MODE0_IS_CBC_CTS	rw	0x0	If MODE_KEY0 is set to 3'b001 (CBC), and this field is set - the mode is CBC-CTS. In addition, If MODE_KEY0 is set to 3'b010 (CTR), and this field is set - the mode is GCTR.
4:2	MODE_KEY0	rw	0x0	This field determines the AES mode in non tunneling operations, and the AES mode of the first stage in tunneling operations: @000 - ECB @001 - CBC @010 - CTR @011 - CBC MAC @100 - XEX/XTS @101 - XCBC-MAC @110 -OFB @111 - CMAC
7:5	MODE_KEY1	rw	0x0	This field determines the AES mode of the second stage operation in tunneling operations: @000 - ECB @001 - CBC @010 - CTR @011 - CBC MAC @100 - XEX/XTS @101 - XCBC-MAC @110 -OFB @111 - CMAC
8:8	CBC_IS_ESSIV	rw	0x0	If MODE_KEY0 is set to 3'b001 (CBC), and this field is set - the mode is CBC-with ESSIV.
9:9	RESERVED0	rw	0x0	Reserved
10:10	AES_TUNNEL_IS_ON	rw	0x0	This field determines whether the AES performs dual-tunnel operations or standard non-tunneling operations: @0 - standard non-tunneling operations @1 - tunneling operations.
11:11	CBC_IS_BITLOCKER	rw	0x0	If MODE_KEY0 is set to 3'b001 (CBC), and this field is set - the mode isBITLOCKER.
13:12	NK_KEY0	rw	0x0	This field determines the AES Key length in non tunneling operations, and the AES key length of the first stage in tunneling operations: @00 - 128 bits key @01 - 192 bits key @10 - 256 bits key @11 - N/A
15:14	NK_KEY1	rw	0x0	This field determines the AES key length of the second stage operation in tunneling operations: @00 - 128 bits key @01 - 192 bits key @10 - 256 bits key @11 - N/A
21:16	RESERVED2	rw	0x0	Reserved
22:22	AES_TUNNEL1_DECRYPT	rw	0x0	This field determines whether the second tunnel stage performs encrypt or decrypt operation : @0 - the second tunnel stage performs encrypt operations. @1 - the second tunnel stage performs decrypt operations.
23:23	AES_TUN_B1_USES_PADDED_DATA_IN	rw	0x0	This field determines, for tunneling operations, the data that is fed to the second tunneling stage: @0 - the output of the first block (standard tunneling operation). @1- data_in after padding rather than the output of the first block.
24:24	AES_TUNNEL0_ENCRYPT	rw	0x0	This field determines whether the first tunnel stage performs encrypt or decrypt operation : @0 - the first tunnel stage performs decrypt operations. @1 - the first tunnel stage performs encrypt operations.
25:25	AES_OUTPUT_MID_TUNNEL_DATA	rw	0x0	This fields determines whether the AES output is the result of the first or second tunneling stage: @0 - The AES engine outputs the result of the second tunnel stage (standard tunneling). @1 - The AES engine outputs the result of the first tunnel stage.
26:26	AES_TUNNEL_B1_PAD_EN	rw	0x0	This field determines whether the input data to the second tunnel stage is padded with zeroes (according to the remaining_bytes value) or not: @0 - The data input to the second tunnel block is not padded with zeros. @1 - The data input to the second tunnel block is padded with zeros.
27:27	RESERVED3	rw	0x0	Reserved
28:28	AES_OUT_MID_TUN_TO_HASH	rw	0x0	This field determines for AES-TO-HASH-AND-DOUT tunneling operations, whether the AES outputs to the HASH the result of the first or the second tunneling stage: @0 - The AES engine writes to the hash the result of the second tunnel stage. @1 - The AES engine writes to the hash the result of the first tunnel stage.
29:29	AES_XOR_CRYPTOKEY	rw	0x0	This field determines the value that is written to AES_KEY0, when AES_SK is kicked: @0 - The value that is written to AES_KEY0 is the value of the HW cryptokey, as is. @1 - The value that is written to AES_KEY0 is the value of the HW cryptokey xored with the current value of AES_KEY0.
30:30	RESERVED4	rw	0x0	Reserved
31:31	DIRECT_ACCESS	rw	0x0	Using direct access and not the din-dout interface

1.4.35 : Reg : AES_HW_FLAGS : 0x0000004C8
reg sep address : reg host address :
This register holds the pre-synthesis HW flag configuration of the AES engine

AES_HW_FLAGS

bits	Field name	permission	default	Description
0:0	SUPPORT_256_192_KEY	ro	0x1	the SUPPORT_256_192_KEY flag
1:1	AES_LARGE_RKEK	ro	0x1	the AES_LARGE_RKEK flag
2:2	DPA_CNTRMSR_EXIST	ro	0x0	the DPA_CNTRMSR_EXIST flag
3:3	CTR_EXIST	ro	0x1	the CTR_EXIST flag
4:4	ONLY_ENCRYPT	ro	0x0	the ONLY_ENCRYPT flag
5:5	USE_SBOX_TABLE	ro	0x0	the USE_SBOX_TABLE flag
7:6	RESERVED0	ro	0x0	Reserved
8:8	USE_5_SBOXES	ro	0x1	the USE_5_SBOXES flag
9:9	AES_SUPPORT_PREV_IV	ro	0x0	the AES_SUPPORT_PREV_IV flag
10:10	aes_tunnel_exists	ro	0x1	the aes_tunnel_exists flag
11:11	SECOND_REGS_SET_EXIST	ro	0x1	the SECOND_REGS_SET_EXIST flag
12:12	DFA_CNTRMSR_EXIST	ro	0x1	the DFA_CNTRMSR_EXIST flag
31:13	RESERVED1	ro	0x0	Reserved

1.4.36 : Reg : AES_CTR_NO_INCREMENT : 0x0000004D8
reg sep address : reg host address :
This register enables the AES CTR no increment mode (in which the counter mode is not incremented between 2 blocks)

AES_CTR_NO_INCREMENT

bits	Field name	permission	default	Description
0:0	AES_CTR_NO_INCREMENT	rw	0x0	This field enables the AES CTR "no increment" mode (in which the counter mode is not incremented between 2 blocks)
31:1	RESERVED	rw	0x0	Reserved

1.4.37 : Reg : AES_DFA_IS_ON : 0x0000004F0
reg sep address : reg host address :
This register disable/enable the AES dfa.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

AES_DFA_IS_ON

bits	Field name	permission	default	Description
0:0	AES_DFA_IS_ON	r/wc	0x0	writing to this register turns the DFA counter-measures on. this register exists only if DFA countermeasures are supported
31:1	RESERVED	r/wc	0x0	Reserved

1.4.38 : Reg : AES_DFA_ERR_STATUS : 0x0000004F8
reg sep address : reg host address :
dfa error status register.

AES_DFA_ERR_STATUS

bits	Field name	permission	default	Description
0:0	AES_DFA_ERR_STATUS	ro	0x0	after a DFA violation this register is set and the AES block is disabled) until the next reset. this register only exists if DFA countermeasures is are supported
31:1	RESERVED	ro	0x0	Reserved

1.4.39 : Reg : AES_CMAC_SIZE0_KICK : 0x000000524
reg sep address : reg host address :
writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV0 register.

AES_CMAC_SIZE0_KICK

bits	Field name	permission	default	Description
0:0	AES_CMAC_SIZE0_KICK	wm	0x0	writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV0 register.
31:1	RESERVED	wm	0x0	Reserved

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1.5 : Block: HASH

0x000000640

1.5.1 : Reg : HASH_H0 : 0x000000640
reg sep address : reg host address :
H0 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512

HASH_H0

bits	Field name	permission	default	Description
31:0	HASH_H0	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.2 : Reg : HASH_H1 : 0x000000644
reg sep address : reg host address :
H1 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512

HASH_H1

bits	Field name	permission	default	Description
31:0	HASH_H1	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.3 : Reg : HASH_H2 : 0x000000648
reg sep address : reg host address :
H2 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512

HASH_H2

bits	Field name	permission	default	Description
31:0	HASH_H2	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.4 : Reg : HASH_H3 : 0x00000064C
reg sep address : reg host address :
H3 data. can only be written in the following HASH_CONTROL modes: MD5 SHA1 SHA224 SHA256 SHA384 SHA512

HASH_H3

bits	Field name	permission	default	Description
31:0	HASH_H3	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.5 : Reg : HASH_H4 : 0x000000650
reg sep address : reg host address :
H4 data. can only be written in the following HASH_CONTROL modes: SHA1 SHA224 SHA256 SHA384 SHA512

HASH_H4

bits	Field name	permission	default	Description
31:0	HASH_H4	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.6 : Reg : HASH_H5 : 0x000000654
reg sep address : reg host address :
H5 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512

HASH_H5

bits	Field name	permission	default	Description
31:0	HASH_H5	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.7 : Reg : HASH_H6 : 0x000000658
reg sep address : reg host address :
H6 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512

HASH_H6

bits	Field name	permission	default	Description
31:0	HASH_H6	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.8 : Reg : HASH_H7 : 0x00000065C
reg sep address : reg host address :
H7 data. can only be written in the following HASH_CONTROL modes: SHA224 SHA256 SHA384 SHA512

HASH_H7

bits	Field name	permission	default	Description
31:0	HASH_H7	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.9 : Reg : HASH_H8 : 0x000000660
reg sep address : reg host address :
H8 data. can only be written in the following HASH_CONTROL modes: SHA384 SHA512

HASH_H8

bits	Field name	permission	default	Description
31:0	HASH_H8	r/wc	0x0	1) Write initial Hash value. 2) Read final Hash value - result.

1.5.10 : Reg : AUTO_HW_PADDING : 0x000000684
reg sep address : reg host address :
HW padding automatically activated by engine. For the special case of ZERO bytes data vector this register should not be used! instead use HASH_PAD_CFG

AUTO_HW_PADDING

bits	Field name	permission	default	Description
0:0	EN	wo	0x0	1'b1 - Enable Automatic HW padding (No need for SW intervention by writing PAD_CFG). Note: Not supported for 0 bytes ! Note: Disable this register when HASH op is done
31:1	RESERVED	wo	0x0	Reserved

1.5.11 : Reg : HASH_XOR_DIN : 0x000000688
reg sep address : reg host address :
This register is always xored with the input to the hash engine,it should be '0' if xored is not reqiured .

HASH_XOR_DIN

bits	Field name	permission	default	Description
31:0	HASH_XOR_DATA	rw	0x0	This register holds the value to be xor-ed with hash input data.

1.5.12 : Reg : LOAD_INIT_STATE : 0x000000694
reg sep address : reg host address :
Indication to HASH that the following data is to be loaded into initial value registers in HASH(H0:H15) or IV to AES MAC

LOAD_INIT_STATE

bits	Field name	permission	default	Description
0:0	LOAD	wo	0x0	Load data to initial state registers. digest/iv for hash/aes_mac. When done loading data this bit should be reset
31:1	RESERVED	wo	0x0	Reserved

1.5.13 : Reg : HASH_SEL_AES_MAC : 0x0000006A4
reg sep address : reg host address :
select the AES MAC module rather than the hash module

HASH_SEL_AES_MAC

bits	Field name	permission	default	Description
0:0	HASH_SEL_AES_MAC	wo	0x0	@1'b0 - select the hash module @1'b1 - select the AES mac module
1:1	GHASH_SEL	wo	0x0	@1'b0 - select the hash module @1'b1 - select the ghash module
31:2	RESERVED	wo	0x0	Reserved

1.5.14 : Reg : HASH_VERSION : 0x0000007B0
reg sep address : reg host address :
HASH VERSION Register

HASH_VERSION

bits	Field name	permission	default	Description
7:0	FIXES	ro	0x0
11:8	MINOR_VERSION_NUMBER	ro	0x0	minor version number
15:12	MAJOR_VERSION_NUMBER	ro	0x0	major version number
31:16	RESERVED	ro	0x0	Reserved

1.5.15 : Reg : HASH_CONTROL : 0x0000007C0
reg sep address : reg host address :
HASH_CONTROL Register. selects which HASH mode to run

HASH_CONTROL

bits	Field name	permission	default	Description
1:0	MODE_0_1	rw	0x0	bits 1:0 of the HASH mode field. The hash mode field possible values are: @4'b0000 - MD5 if present @4'b0001 - SHA-1 @4'b0010 - SHA-256 @4'b1010 - SHA-224
2:2	RESERVED0	rw	0x0	Reserved
3:3	MODE_3	rw	0x0	bit 3 of the HASH mode field. The hash mode field possible values are:4'b0000 - MD5 if present 4'b0001 - SHA-1 4'b0010 - SHA-256 4'b1010 - SHA-224
31:4	RESERVED1	rw	0x0	Reserved

1.5.16 : Reg : HASH_PAD_EN : 0x0000007C4
reg sep address : reg host address :
This register enables the hash hw padding .

HASH_PAD_EN

bits	Field name	permission	default	Description
0:0	EN	rw	0x1	1 - Enable generation of padding by HW Pad block. 0 - Disable generation of padding by HW Pad block.
31:1	RESERVED	rw	0x0	Reserved

1.5.17 : Reg : HASH_PAD_CFG : 0x0000007C8
reg sep address : reg host address :
HASH_PAD_CFG Register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HASH_PAD_CFG

bits	Field name	permission	default	Description
1:0	RESERVED0	rw	0x0	Reserved
2:2	DO_PAD	rw	0x0	Enable Padding generation. must be reset upon completion of padding.
31:3	RESERVED1	rw	0x0	Reserved

1.5.18 : Reg : HASH_CUR_LEN_0 : 0x0000007CC
reg sep address : reg host address :
This register hold the length of current hash operation bit 31:0.

HASH_CUR_LEN_0

bits	Field name	permission	default	Description
31:0	Length	rw	0x0	Represent the current length of valid bits where digest need to be computed In Bytes.

1.5.19 : Reg : HASH_CUR_LEN_1 : 0x0000007D0
reg sep address : reg host address :
This register hold the length of current hash operation bit 63:32.

HASH_CUR_LEN_1

bits	Field name	permission	default	Description
31:0	Length	rw	0x0	Represent the current length of valid bits where digest need to be computed In Bytes.

1.5.20 : Reg : HASH_PARAM : 0x0000007DC
reg sep address : reg host address :
HASH_PARAM Register.

HASH_PARAM

bits	Field name	permission	default	Description
3:0	CW	ro	0x1	Indicates the number of concurrent words the hash is using to compute signature. 1 - One concurrent w(t). 2 - Two concurrent w(t).
7:4	CH	ro	0x0	Indicate if Hi adders are present for each Hi value or 1 adder is shared for all Hi. 0 - One Hi value is updated at a time 1 - All Hi values are updated at the same time.
11:8	DW	ro	0x0	Determine the granularity of word size. 0 - 32 bit word data. 1 - 64 bit word data.
12:12	SHA_512_EXISTS	ro	0x0	Indicate if SHA-512 is present in the design. By default SHA-1 and SHA-256 are present. 0 - SHA-1 and SHA-256 are present only 1 - SHA-1 and all SHA-2 are present (SHA-256 SHA-512).
13:13	PAD_EXISTS	ro	0x1	Indicate if pad block is present in the design. 0 - pad function is not supported by hardware. 1 - pad function is supported by hardware.
14:14	MD5_EXISTS	ro	0x0	Indicate if MD5 is present in HW
15:15	HMAC_EXISTS	ro	0x0	Indicate if HMAC logic is present in the design
16:16	SHA_256_EXISTS	ro	0x1	Indicate if SHA-256 is present in the design
17:17	HASH_COMPARE_EXISTS	ro	0x0	Indicate if COMPARE digest logic is present in the design
18:18	DUMP_HASH_TO_DOUT_EXISTS	ro	0x0	Indicate if HASH to dout is present in the design
31:19	RESERVED	ro	0x0	Reserved

1.5.21 : Reg : HASH_AES_SW_RESET : 0x0000007E4
reg sep address : reg host address :
HASH_AES_SW_RESET Register.

HASH_AES_SW_RESET

bits	Field name	permission	default	Description
0:0	HASH_AES_SW_RESET	wo	0x0	Hash receive reset internally.
31:1	RESERVED	wo	0x0	Reserved

1.5.22 : Reg : HASH_ENDIANESS : 0x0000007E8
reg sep address : reg host address :
This register hold the HASH_ENDIANESS configuration.

HASH_ENDIANESS

bits	Field name	permission	default	Description
0:0	ENDIAN	rw	0x1	The default value is little-endian. The data and generation of padding can be swapped to be big-endian.
31:1	RESERVED	rw	0x0	Reserved

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1.6 : Block: MISC

0x000000800

1.6.1 : Reg : AES_CLK_ENABLE : 0x000000810
reg sep address : reg host address :
The AES clock enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

AES_CLK_ENABLE

bits	Field name	permission	default	Description
0:0	EN	rw	0x0	@1'b1 - the AES clock is enabled. @1'b0 - the AES clock is disabled.
31:1	RESERVED	rw	0x0	Reserved

1.6.2 : Reg : HASH_CLK_ENABLE : 0x000000818
reg sep address : reg host address :
The HASH clock enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HASH_CLK_ENABLE

bits	Field name	permission	default	Description
0:0	EN	rw	0x0	@1'b1 - the HASH clock is enabled. @1'b0 - the HASH clock is disabled.
31:1	RESERVED	rw	0x0	Reserved

1.6.3 : Reg : PKA_CLK_ENABLE : 0x00000081C
reg sep address : reg host address :
The PKA clock enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

PKA_CLK_ENABLE

bits	Field name	permission	default	Description
0:0	EN	rw	0x0	@1'b1 - the PKA clock is enabled. @1'b0 - the PKA clock is disabled.
31:1	RESERVED	rw	0x0	Reserved

1.6.4 : Reg : DMA_CLK_ENABLE : 0x000000820
reg sep address : reg host address :
DMA_CLK enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

DMA_CLK_ENABLE

bits	Field name	permission	default	Description
0:0	EN	rw	0x0	@1'b1 - the DMA clock is enabled. @1'b0 - the DMA clock is disabled.
31:1	RESERVED	rw	0x0	Reserved

1.6.5 : Reg : CLK_STATUS : 0x000000824
reg sep address : reg host address :
The CryptoCell clocks' status register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

CLK_STATUS

bits	Field name	permission	default	Description
0:0	AES_CLK_STATUS	ro	0x0	@1'b1 - the AES clock is enabled. @1'b0 - the AES clock is disabled.
1:1	RESERVED	ro	0x0	@1'b1 - the DES clock is enabled. @1'b0 - the DES clock is disabled.
2:2	HASH_CLK_STATUS	ro	0x0	@1'b1 - the HASH clock is enabled. @1'b0 - the HASH clock is disabled.
3:3	PKA_CLK_STATUS	ro	0x0	@1'b1 - the PKA clock is enabled. @1'b0 - the PKA clock is disabled.
6:4	RESERVED0	ro	0x0	Reserved
7:7	CHACHA_CLK_STATUS	ro	0x0	@1'b1 - the CHACHA clock is enabled. @1'b0 - the CHACHA clock is disabled.
8:8	DMA_CLK_STATUS	ro	0x1	@1'b1 - the DMA clock is enabled. @1'b0 - the DMA clock is disabled.
31:9	RESERVED1	ro	0x0	Reserved

1.6.6 : Reg : CHACHA_CLK_ENABLE : 0x000000858
reg sep address : reg host address :
CHACHA /SALSA clock enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

CHACHA_CLK_ENABLE

bits	Field name	permission	default	Description
0:0	EN	wo	0x0	@1'b1 - the CHACHA / SALSA clock is enabled. @1'b0 - the CHACHA / SALSA clock is disabled.
31:1	RESERVED	wo	0x0	Reserved

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1.7 : Block: CC_CTL

0x000000900

1.7.1 : Reg : CRYPTO_CTL : 0x000000900
reg sep address : reg host address :
Defines the cryptographic flow.

CRYPTO_CTL

bits	Field name	permission	default	Description
4:0	MODE	wo	0x0	Determines the active cryptographic engine: @5'b0000 - BYPASS @5'b0001 - AES @5'b0010 - AES_TO_HASH @5'b0011 - AES_AND_HASH @5'b0100 - DES @5'b0101 - DES_TO_HASH @5'b0110 - DES_AND_HASH @5'b0111 - HASH @5'b1001 - AES_MAC_AND_BYPASS @5'b1010 - AES_TO_HASH_AND_DOUT @5'b1011 - Reserved @5'b1000 - Reserved
31:5	RESERVED	wo	0x0	Reserved

1.7.2 : Reg : CRYPTO_BUSY : 0x000000910
reg sep address : reg host address :
This register is set when the cryptographic core is busy.

CRYPTO_BUSY

bits	Field name	permission	default	Description
0:0	CRYPTO_BUSY	ro	0x0	@1'b0 - Ready @1'b1 - Busy Asserted when AES_BUSY or DES_BUSY or HASH_BUSY are asserted or when the DIN FIFO is not empty.
31:1	RESERVED	ro	0x0	Reserved

1.7.3 : Reg : HASH_BUSY : 0x00000091C
reg sep address : reg host address :
This register is set when the Hash engine is busy.

HASH_BUSY

bits	Field name	permission	default	Description
0:0	HASH_BUSY	ro	0x0	@1'b0 - Ready @1'b1 - Busy Asserted when hash engine is busy.
31:1	RESERVED	ro	0x0	Reserved

1.7.4 : Reg : CONTEXT_ID : 0x000000930
reg sep address : reg host address :
A general RD/WR register. For Firmware use.

CONTEXT_ID

bits	Field name	permission	default	Description
7:0	CONTEXT_ID	rw	0x0	Context ID
31:8	RESERVED	rw	0x0	Reserved

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1.8 : Block: GHASH

0x000000960

1.8.1 : Reg : GHASH_SUBKEY_0_0 : 0x000000960
reg sep address : reg host address :
Bits 31:0 of GHASH Key0 (used as the GHASH module key).

GHASH_SUBKEY_0_0

bits	Field name	permission	default	Description
31:0	GHASH_SUBKEY_0_0	wo	0x0	Bits 31:0 of GHASH Key0.

1.8.2 : Reg : GHASH_SUBKEY_0_1 : 0x000000964
reg sep address : reg host address :
Bits 63:32 of GHASH Key0 (used as the GHASH module key).

GHASH_SUBKEY_0_1

bits	Field name	permission	default	Description
31:0	GHASH_SUBKEY_0_1	wo	0x0	Bits 63:32 of GHASH Key0.

1.8.3 : Reg : GHASH_SUBKEY_0_2 : 0x000000968
reg sep address : reg host address :
Bits 95:64 of GHASH Key0 (used as the GHASH module key).

GHASH_SUBKEY_0_2

bits	Field name	permission	default	Description
31:0	GHASH_SUBKEY_0_2	wo	0x0	Bits 95:64 of GHASH Key0.

1.8.4 : Reg : GHASH_SUBKEY_0_3 : 0x00000096C
reg sep address : reg host address :
Bits 127:96 of GHASH Key0 (used as the GHASH module key).

GHASH_SUBKEY_0_3

bits	Field name	permission	default	Description
31:0	GHASH_SUBKEY_0_3	wo	0x0	Bits 127:96 of GHASH Key0.

1.8.5 : Reg : GHASH_IV_0_0 : 0x000000970
reg sep address : reg host address :
Bits 31:0 of GHASH_IV0 register.
GHASH IV0 is used as the GHASH IV (Initialization Value) register.

GHASH_IV_0_0

bits	Field name	permission	default	Description
31:0	GHASH_IV_0_0	r/wc	0x0	Bits 31:0 of GHASH_IV0 register of the GHASH module. For the description of GHASH_IV0, see the GHASH_0_0 register description

1.8.6 : Reg : GHASH_IV_0_1 : 0x000000974
reg sep address : reg host address :
Bits 63:32 of GHASH_IV0 register.
GHASH IV0 is used as the GHASH IV (Initialization Value) register.

GHASH_IV_0_1

bits	Field name	permission	default	Description
31:0	GHASH_IV_0_1	r/wc	0x0	Bits 63:32 of GHASH_IV0 register of the GHASH module. For the description of GHASH_IV0, see the GHASH_0_0 register description

1.8.7 : Reg : GHASH_IV_0_2 : 0x000000978
reg sep address : reg host address :
Bits 95:64 of GHASH_IV0 register.
GHASH IV0 is used as the GHASH IV (Initialization Value) register.

GHASH_IV_0_2

bits	Field name	permission	default	Description
31:0	GHASH_IV_0_2	r/wc	0x0	Bits 95:64 of GHASH_IV0 register of the GHASH module. For the description of GHASH_IV0, see the GHASH_0_0 register description

1.8.8 : Reg : GHASH_IV_0_3 : 0x00000097C
reg sep address : reg host address :
Bits 127:96 of GHASH_IV0 register.
GHASH IV0 is used as the GHASH IV (Initialization Value) register.

GHASH_IV_0_3

bits	Field name	permission	default	Description
31:0	GHASH_IV_0_3	r/wc	0x0	Bits 127:96 of GHASH_IV0 register of the GHASH module. For the description of GHASH_IV0, see the GHASH_0_0 register description

1.8.9 : Reg : GHASH_BUSY : 0x000000980
reg sep address : reg host address :
The GHASH module GHASH_BUSY Register. This register is set when the GHASH core is active.

GHASH_BUSY

bits	Field name	permission	default	Description
0:0	GHASH_BUSY	ro	0x0	GHASH_BUSY Register. this register is set when the GHASH core is active
31:1	RESERVED	ro	0x0	Reserved

1.8.10 : Reg : GHASH_INIT : 0x000000984
reg sep address : reg host address :
Writing to this address sets the GHASH engine to be ready to a new GHASH operation.

GHASH_INIT

bits	Field name	permission	default	Description
0:0	GHASH_INIT	wo	0x0	Writing to this address sets the GHASH engine to be ready to a new GHASH operation.
31:1	RESERVED	wo	0x0	Reserved

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1.9 : Block: HOST_RGF

0x000000A00

1.9.1 : Reg : HOST_RGF_IRR : 0x000000A00
reg sep address : reg host address :
The Interrupt Request register. Each bit of this register holds the interrupt status of a single interrupt source.

HOST_RGF_IRR

bits	Field name	permission	default	Description
3:0	unused0	ro	0x0	Reserved
4:4	SRAM_TO_DIN_INT	ro	0x0	The SRAM to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered to DIN buffer from SRAM.
5:5	DOUT_TO_SRAM_INT	ro	0x0	The DOUT to SRAM DMA done interrupt status. This interrupt is asserted when all data was delivered to SRAM buffer from DOUT.
6:6	MEM_TO_DIN_INT	ro	0x0	The memory to DIN DMA done interrupt status. This interrupt is asserted when all data was delivered to DIN buffer from memory.
7:7	DOUT_TO_MEM_INT	ro	0x0	The DOUT to memory DMA done interrupt status. This interrupt is asserted when all data was delivered to memory buffer from DOUT.
8:8	AHB_ERR_INT	ro	0x0	The AXI error interrupt status.
9:9	PKA_EXP_INT	ro	0x0	The PKA end of operation interrupt status.
10:10	RNG_INT	ro	0x0	The RNG interrupt status.
11:11	SYM_DMA_COMPLETED	ro	0x0	The GPR interrupt status.
31:12	RESERVED2	ro	0x0	Reserved

1.9.2 : Reg : HOST_RGF_IMR : 0x000000A04
reg sep address : reg host address :
The Interrupt Mask register. Each bit of this register holds the mask of a single interrupt source.

HOST_RGF_IMR

bits	Field name	permission	default	Description
3:0	unused0	rw	0x	Reserved
4:4	SRAM_TO_DIN_MASK	rw	0x1	The SRAM to DIN DMA done interrupt mask.
5:5	DOUT_TO_SRAM_MASK	rw	0x1	The DOUT to SRAM DMA done interrupt mask.
6:6	MEM_TO_DIN_MASK	rw	0x1	The memory to DIN DMA done interrupt mask.
7:7	DOUT_TO_MEM_MASK	rw	0x1	The DOUT to memory DMA done interrupt mask.
8:8	AXI_ERR_MASK	rw	0x1	The AXI error interrupt mask.
9:9	PKA_EXP_MASK	rw	0x1	The PKA end of operation interrupt mask.
10:10	RNG_INT_MASK	rw	0x1	The RNG interrupt mask.
11:11	SYM_DMA_COMPLETED_MASK	rw	0x1	The GPR interrupt mask.
31:12	RESERVED0	rw	0x0	Reserved

1.9.3 : Reg : HOST_RGF_ICR : 0x000000A08
reg sep address : reg host address :
Interrupt Clear Register.

HOST_RGF_ICR

bits	Field name	permission	default	Description
3:0	RESERVED0	wo	0x0	Reserved
4:4	SRAM_TO_DIN_CLEAR	wo	0x0	The SRAM to DIN DMA done interrupt clear.
5:5	DOUT_TO_SRAM_CLEAR	wo	0x0	The DOUT to SRAM DMA done interrupt clear.
6:6	MEM_TO_DIN_CLEAR	wo	0x0	The memory to DIN DMA done interrupt clear.
7:7	DOUT_TO_MEM_CLEAR	wo	0x0	The DOUT to memory DMA done interrupt clear.
8:8	AXI_ERR_CLEAR	wo	0x0	The AXI error interrupt clear.
9:9	PKA_EXP_CLEAR	wo	0x0	The PKA end of operation interrupt clear.
10:10	RNG_INT_CLEAR	wo	0x0	The RNG interrupt clear.
11:11	SYM_DMA_COMPLETED_CLEAR	wo	0x0	The GPR interrupt clear.
31:12	RESERVED2	wo	0x0	Reserved

1.9.4 : Reg : HOST_RGF_ENDIAN : 0x000000A0C
reg sep address : reg host address :
This register defines the endianness of the Host-accessible registers.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_RGF_ENDIAN

bits	Field name	permission	default	Description
2:0	RESERVED0	rw1	0x0	Reserved
3:3	DOUT_WR_BG	rw1	0x0	DOUT write endianness: @1'b0 - little endian @1'b1 - big endian
6:4	RESERVED1	rw1	0x0	Reserved
7:7	DIN_RD_BG	rw1	0x0	DIN write endianness: @1'b0 - little endian @1'b1 - big endian
10:8	RESERVED2	rw1	0x0	Reserved
11:11	DOUT_WR_WBG	rw1	0x0	DOUT write word endianness: @1'b0 - little endian @1'b1 - big endian
14:12	RESERVED3	rw1	0x0	Reserved
15:15	DIN_RD_WBG	rw1	0x0	DIN write word endianness: @1'b0 - little endian @1'b1 - big endian
31:16	RESERVED4	rw1	0x0	Reserved

1.9.5 : Reg : HOST_RGF_SIGNATURE : 0x000000A24
reg sep address : reg host address :
This register holds the CryptoCell product signature.

HOST_RGF_SIGNATURE

bits	Field name	permission	default	Description
31:0	HOST_SIGNATURE	ro	0x	Identification “signature”: always returns a fixed value, used by Host driver to verify CryptoCell presence at this address.

1.9.6 : Reg : HOST_BOOT : 0x000000A28
reg sep address : reg host address :
This register holds the values of CryptoCell's pre-synthesis flags

HOST_BOOT

bits	Field name	permission	default	Description
0:0	SYNTHESIS_CONFIG	ro	0x0	POWER_GATING_EXISTS_LOCAL
1:1	LARGE_RKEK_LOCAL	ro	0x1	LARGE_RKEK_LOCAL
2:2	HASH_IN_FUSES_LOCAL	ro	0x1	HASH_IN_FUSES_LOCAL
3:3	EXT_MEM_SECURED_LOCAL	ro	0x1	EXT_MEM_SECURED_LOCAL
4:4	Reserved	ro	0x0	Reserved
5:5	RKEK_ECC_EXISTS_LOCAL_N	ro	0x1	RKEK_ECC_EXISTS_LOCAL_N
8:6	SRAM_SIZE_LOCAL	ro	0x0	SRAM_SIZE_LOCAL
9:9	DSCRPTR_EXISTS_LOCAL	ro	0x0	DSCRPTR_EXISTS_LOCAL
10:10	PAU_EXISTS_LOCAL	ro	0x0	PAU_EXISTS_LOCAL
11:11	RNG_EXISTS_LOCAL	ro	0x1	RNG_EXISTS_LOCAL
12:12	PKA_EXISTS_LOCAL	ro	0x1	PKA_EXISTS_LOCAL
13:13	RC4_EXISTS_LOCAL	ro	0x0	RC4_EXISTS_LOCAL
14:14	SHA_512_PRSNT_LOCAL	ro	0x0	SHA_512_PRSNT_LOCAL
15:15	SHA_256_PRSNT_LOCAL	ro	0x1	SHA_256_PRSNT_LOCAL
16:16	MD5_PRSNT_LOCAL	ro	0x0	MD5_PRSNT_LOCAL
17:17	HASH_EXISTS_LOCAL	ro	0x1	HASH_EXISTS_LOCAL
18:18	C2_EXISTS_LOCAL	ro	0x0	C2_EXISTS_LOCAL
19:19	DES_EXISTS_LOCAL	ro	0x0	DES_EXISTS_LOCAL
20:20	AES_XCBC_MAC_EXISTS_LOCAL	ro	0x0	AES_XCBC_MAC_EXISTS_LOCAL
21:21	AES_CMAC_EXISTS_LOCAL	ro	0x1	AES_CMAC_EXISTS_LOCAL
22:22	AES_CCM_EXISTS_LOCAL	ro	0x1	AES_CCM_EXISTS_LOCAL
23:23	AES_XEX_HW_T_CALC_LOCAL	ro	0x0	AES_XEX_HW_T_CALC_LOCAL
24:24	AES_XEX_EXISTS_LOCAL	ro	0x0	AES_XEX_EXISTS_LOCAL
25:25	CTR_EXISTS_LOCAL	ro	0x1	CTR_EXISTS_LOCAL
26:26	AES_DIN_BYTE_RESOLUTION_LOCAL	ro	0x1	AES_DIN_BYTE_RESOLUTION_LOCAL
27:27	TUNNELING_ENB_LOCAL	ro	0x1	TUNNELING_ENB_LOCAL
28:28	SUPPORT_256_192_KEY_LOCAL	ro	0x1	SUPPORT_256_192_KEY_LOCAL
29:29	ONLY_ENCRYPT_LOCAL	ro	0x0	ONLY_ENCRYPT_LOCAL
30:30	AES_EXISTS_LOCAL	ro	0x1	AES_EXISTS_LOCAL
31:31	RESERVED	ro	0x0	Reserved

1.9.7 : Reg : HOST_CRYPTOKEY_SEL : 0x000000A38
reg sep address : reg host address :
AES hardware key select.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_CRYPTOKEY_SEL

bits	Field name	permission	default	Description
2:0	SEL_CRYPTO_KEY	rw	0x0	Select the source of the HW key that is used by the AES engine: @3'h0 - RKEK @3'h1 -the Krtl. @3'h2 - the provision key KCP. @3'h3 - the code encryption key KCE. @3'h4 - the KPICV, The ICV provisioning key . @3'h5 - the code encryption key KCEICV NOTE: When "kprtl_lock" is set - kprtl will be masked (trying to load it will load zeros to the AES key register. When "kcertl_lock" is set - kcertl will be masked (trying to load it will load zeros to the AES key register. When scan_mode is asserted – all the RTL keys (Krtll) will be masked.
31:3	RESERVED	rw	0x0	Reserved

1.9.8 : Reg : HOST_CORE_CLK_GATING_ENABLE : 0x000000A78
reg sep address : reg host address :
This register enables the core clk gating by masking/enabling the cc_idle_state output signal.

HOST_CORE_CLK_GATING_ENABLE

bits	Field name	permission	default	Description
0:0	HOST_CORE_CLK_GATING_ENABLE	rw	0x0	Enable the core clk gating,
31:1	RESERVED	rw	0x0	Reserved Note: This is a special register, this registers

1.9.9 : Reg : HOST_CC_IS_IDLE : 0x000000A7C
reg sep address : reg host address :
This register holds the idle indication of CC . Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_CC_IS_IDLE

bits	Field name	permission	default	Description
0:0	HOST_CC_IS_IDLE	ro	0x0	Read if CC is idle.
1:1	HOST_CC_IS_IDLE_EVENT	ro	0x0	The event that indicates that CC is idle.
2:2	SYM_IS_BUSY	ro	0x0	symetric flow is busy
3:3	AHB_IS_IDLE	ro	0x0	ahb stste machine is idle
4:4	NVM_ARB_IS_IDLE	ro	0x0	nvm arbiter is idle
5:5	NVM_IS_IDLE	ro	0x0	nvm is idle
6:6	FATAL_WR	ro	0x0	fatal write
7:7	RNG_IS_IDLE	ro	0x0	rng is idle
8:8	PKA_IS_IDLE	ro	0x0	pka is idle
9:9	CRYPTO_IS_IDLE	ro	0x0	crypto flow is done
31:10	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.9.10 : Reg : HOST_POWERDOWN : 0x000000A80
reg sep address : reg host address :
This register start the power-down sequence.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_POWERDOWN

bits	Field name	permission	default	Description
0:0	HOST_POWERDOWN	rw	0x0	Power down enable register.
31:1	RESERVED	rw	0x0	Reserved Note: This is a special register, this registers

1.9.11 : Reg : HOST_REMOVE_GHASH_ENGINE : 0x000000A84
reg sep address : reg host address :
These inputs are to be statically tied to 0 or 1 by the customers. When such an input is set, the matching engines inputs are tied to zero and its outputs are disconnected, so that the engine will be entirely removed by Synthesis

HOST_REMOVE_GHASH_ENGINE

bits	Field name	permission	default	Description
0:0	HOST_REMOVE_GHASH_ENGINE	ro	0x0	Read the Remove_chacha_engine input
31:1	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.9.12 : Reg : HOST_REMOVE_CHACHA_ENGINE : 0x000000A88
reg sep address : reg host address :
These inputs are to be statically tied to 0 or 1 by the customers. When such an input is set, the matching engines inputs are tied to zero and its outputs are disconnected, so that the engine will be entirely removed by Synthesis

HOST_REMOVE_CHACHA_ENGINE

bits	Field name	permission	default	Description
0:0	HOST_REMOVE_CHACHA_ENGINE	ro	0x0	Read the Remove_ghash_engine input
31:1	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

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1.10 : Block: AHB

0x000000B00

1.10.1 : Reg : AHBM_SINGLES : 0x000000B00
reg sep address : reg host address :
This register forces the ahb transactions to be always singles.

AHBM_SINGLES

bits	Field name	permission	default	Description
0:0	AHB_SINGLES	rw	0x0	Force ahb singles
31:1	RESERVED	rw	0x0	Reserved

1.10.2 : Reg : AHBM_HPROT : 0x000000B04
reg sep address : reg host address :
This register holds the ahb prot value

AHBM_HPROT

bits	Field name	permission	default	Description
3:0	AHB_PROT	rw	0x0	The ahb prot value
31:4	RESERVED	rw	0x0	Reserved

1.10.3 : Reg : AHBM_HMASTLOCK : 0x000000B08
reg sep address : reg host address :
This register holds ahb hmastlock value

AHBM_HMASTLOCK

bits	Field name	permission	default	Description
0:0	AHB_HMASTLOCK	rw	0x0	The hmastlock value.
31:1	RESERVED	rw	0x0	Reserved

1.10.4 : Reg : AHBM_HNONSEC : 0x000000B0C
reg sep address : reg host address :
This register holds ahb hnonsec value

AHBM_HNONSEC

bits	Field name	permission	default	Description
0:0	AHB_WRITE_HNONSEC	rw	0x0	The hnonsec value for write transaction.
1:1	AHB_READ_HNONSEC	rw	0x0	The hnonsec value for read transaction.
31:2	RESERVED	rw	0x0	Reserved

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1.11 : Block: DIN

0x000000C00

1.11.1 : Reg : DIN_BUFFER : 0x000000C00
reg sep address : reg host address :
This address can be used by the CPU to write data directly to the DIN buffer to be sent to engines.

DIN_BUFFER

bits	Field name	permission	default	Description
31:0	DIN_BUFFER_DATA	wo	0x0	This register is mapped into 8 addresses in order to enable a CPU burst.

1.11.2 : Reg : DIN_MEM_DMA_BUSY : 0x000000C20
reg sep address : reg host address :
Indicates whether memory (AXI) source DMA (DIN) is busy.

DIN_MEM_DMA_BUSY

bits	Field name	permission	default	Description
0:0	DIN_MEM_DMA_BUSY	ro	0x0	DIN memory DMA busy: @1'b1 - busy @1'b0 - not busy
31:1	RESERVED	ro	0x0	Reserved

1.11.3 : Reg : SRC_LLI_WORD0 : 0x000000C28
reg sep address : reg host address :
This register is used in direct LLI mode - holds the location of the data source in the memory (AXI).

SRC_LLI_WORD0

bits	Field name	permission	default	Description
31:0	SRC_LLI_WORD0	wo	0x0	Source address within memory.

1.11.4 : Reg : SRC_LLI_WORD1 : 0x000000C2C
reg sep address : reg host address :
This register is used in direct LLI mode - holds the number of bytes to be read from the memory (AXI). Writing to this register triggers the DMA.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

SRC_LLI_WORD1

bits	Field name	permission	default	Description
29:0	BYTES_NUM	wo	0x0	Total number of bytes to read using DMA in this entry
30:30	FIRST	wo	0x0	1'b1 - Indicates the first LLI entry
31:31	LAST	wo	0x0	1'b1 - Indicates the last LLI entry

1.11.5 : Reg : SRAM_SRC_ADDR : 0x000000C30
reg sep address : reg host address :
Location of data (start address) to be read from SRAM.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

SRAM_SRC_ADDR

bits	Field name	permission	default	Description
31:0	SRAM_SOURCE	rw	0x0	SRAM source base address of data

1.11.6 : Reg : DIN_SRAM_BYTES_LEN : 0x000000C34
reg sep address : reg host address :
This register holds the size of the data (in bytes) to be read from the SRAM.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

DIN_SRAM_BYTES_LEN

bits	Field name	permission	default	Description
31:0	BYTES_LEN	r/wc	0x0	Size of data to read from SRAM (bytes). This is the trigger to the SRAM SRC DMA.

1.11.7 : Reg : DIN_SRAM_DMA_BUSY : 0x000000C38
reg sep address : reg host address :
This register holds the status of the SRAM DMA DIN.

DIN_SRAM_DMA_BUSY

bits	Field name	permission	default	Description
0:0	BUSY	ro	0x0	DIN SRAM DMA busy: @1'b1 - busy @1'b0 - not busy
31:1	RESERVED	ro	0x0	Reserved

1.11.8 : Reg : DIN_SRAM_ENDIANNESS : 0x000000C3C
reg sep address : reg host address :
This register defines the endianness of the DIN interface to SRAM.

DIN_SRAM_ENDIANNESS

bits	Field name	permission	default	Description
0:0	SRAM_DIN_ENDIANNESS	rw	0x0	Defines the endianness of DIN interface to SRAM: @1'b1 - big-endianness @1'b0 - little endianness
31:1	RESERVED	rw	0x0	Reserved

1.11.9 : Reg : DIN_CPU_DATA_SIZE : 0x000000C48
reg sep address : reg host address :
This register hold the number of bytes to be transmited using external DMA
Note: This is a special register, affected by internal logic. Test result of this register is NA.

DIN_CPU_DATA_SIZE

bits	Field name	permission	default	Description
15:0	CPU_DIN_SIZE	wo	0x0	When using external DMA, the size of transmited data in bytes should be written to this register.
31:16	RESERVED	wo	0x0	Reserved

1.11.10 : Reg : FIFO_IN_EMPTY : 0x000000C50
reg sep address : reg host address :
DIN FIFO empty indication

FIFO_IN_EMPTY

bits	Field name	permission	default	Description
0:0	EMPTY	ro	0x1	1'b1 - FIFO empty
31:1	RESERVED	ro	0x0	Reserved

1.11.11 : Reg : DIN_FIFO_RST_PNTR : 0x000000C58
reg sep address : reg host address :
Writing to this register resets the DIN_FIFO pointers.

DIN_FIFO_RST_PNTR

bits	Field name	permission	default	Description
0:0	RST	wo	0x0	Writing any value to this address resets the DIN_FIFO pointers.
31:1	RESERVED	wo	0x0	Reserved

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1.12 : Block: DOUT

0x000000D00

1.12.1 : Reg : DOUT_BUFFER : 0x000000D00
reg sep address : reg host address :
Cryptographic result - CPU can directly access it.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

DOUT_BUFFER

bits	Field name	permission	default	Description
31:0	DOUT_BUFFER_DATA	ro	0x0	This address can be used by the CPU to read data directly from the DOUT buffer.

1.12.2 : Reg : DOUT_MEM_DMA_BUSY : 0x000000D20
reg sep address : reg host address :
DOUT memory DMA busy - Indicates that memory (AXI) destination DMA (DOUT) is busy,

DOUT_MEM_DMA_BUSY

bits	Field name	permission	default	Description
0:0	DOUT_MEM_DMA_BUSY	ro	0x0	DOUT memory DMA busy: @1'b1 - busy @1'b0 - not busy
31:1	RESERVED	ro	0x0	Reserved

1.12.3 : Reg : DST_LLI_WORD0 : 0x000000D28
reg sep address : reg host address :
This register is used in direct LLI mode - holds the location of the data destination in the memory (AXI)

DST_LLI_WORD0

bits	Field name	permission	default	Description
31:0	DST_LLI_WORD0	wo	0x0	Destination address within memory

1.12.4 : Reg : DST_LLI_WORD1 : 0x000000D2C
reg sep address : reg host address :
This register is used in direct LLI mode - holds the number of bytes to be written to the memory (AXI).
Note: This is a special register, affected by internal logic. Test result of this register is NA.

DST_LLI_WORD1

bits	Field name	permission	default	Description
29:0	BYTES_NUM	r/wc	0x0	Total byte number to be written by DMA in this entry
30:30	FIRST	r/wc	0x0	1'b1 - Indicates the first LLI entry
31:31	LAST	r/wc	0x0	1'b1 - Indicates the last LLI entry

1.12.5 : Reg : SRAM_DEST_ADDR : 0x000000D30
reg sep address : reg host address :
Location of result to be sent to in SRAM
Note: This is a special register, affected by internal logic. Test result of this register is NA.

SRAM_DEST_ADDR

bits	Field name	permission	default	Description
31:0	SRAM_DEST	rw	0x0	SRAM destination base address for data.

1.12.6 : Reg : DOUT_SRAM_BYTES_LEN : 0x000000D34
reg sep address : reg host address :
This register holds the size of the data (in bytes) to be written to the SRAM.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

DOUT_SRAM_BYTES_LEN

bits	Field name	permission	default	Description
31:0	BYTES_LEN	r/wc	0x0	Size of data to write to SRAM (bytes). This is the trigger to the SRAM DST DMA.

1.12.7 : Reg : DOUT_SRAM_DMA_BUSY : 0x000000D38
reg sep address : reg host address :
This register holds the status of the SRAM DMA DOUT.

DOUT_SRAM_DMA_BUSY

bits	Field name	permission	default	Description
0:0	BUSY	ro	0x0	@1'b0 - all data was written to SRAM. @1'b1 - DOUT SRAM DMA busy.
31:1	RESERVED	ro	0x0	Reserved

1.12.8 : Reg : DOUT_SRAM_ENDIANNESS : 0x000000D3C
reg sep address : reg host address :
This register defines the endianness of the DOUT interface from SRAM.

DOUT_SRAM_ENDIANNESS

bits	Field name	permission	default	Description
0:0	DOUT_SRAM_ENDIANNESS	rw	0x0	Defines the endianness of DOUT interface from SRAM: @1'b1 - big-endianness @1'b0 - little endianness
31:1	RESERVED	rw	0x0	Reserved

1.12.9 : Reg : READ_ALIGN_LAST : 0x000000D44
reg sep address : reg host address :
Indication that the next read from the CPU is the last one. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding).

READ_ALIGN_LAST

bits	Field name	permission	default	Description
0:0	LAST	wo	0x0	1'b1 - Flush the read aligner content (used for reading the last data).
31:1	RESERVED	wo	0x0	Reserved

1.12.10 : Reg : DOUT_FIFO_EMPTY : 0x000000D50
reg sep address : reg host address :
DOUT_FIFO_EMPTY Register.

DOUT_FIFO_EMPTY

bits	Field name	permission	default	Description
0:0	DOUT_FIFO_EMPTY	ro	0x1	@1'b0 - DOUT FIFO is not empty @1'b1 - DOUT FIFO is empty
31:1	RESERVED	ro	0x0	Reserved

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1.13 : Block: HOST_SRAM

0x000000F00

1.13.1 : Reg : SRAM_DATA : 0x000000F00
reg sep address : reg host address :
READ WRITE DATA FROM SRAM
Note: This is a special register, affected by internal logic. Test result of this register is NA.

SRAM_DATA

bits	Field name	permission	default	Description
31:0	SRAM_DATA	rw	0x0	32 bit write or read from SRAM: read - triggers the SRAM read DMA address automatically incremented write - triggers the SRAM write DMA address automatically incremented

1.13.2 : Reg : SRAM_ADDR : 0x000000F04
reg sep address : reg host address :
first address given to SRAM DMA for read/write transactions from SRAM

SRAM_ADDR

bits	Field name	permission	default	Description
14:0	SRAM_ADDR	wo	0x0	SRAM starting address
31:15	RESERVED	wo	0x0	17'b0

1.13.3 : Reg : SRAM_DATA_READY : 0x000000F08
reg sep address : reg host address :
The SRAM content is ready for read in SRAM_DATA.

SRAM_DATA_READY

bits	Field name	permission	default	Description
0:0	SRAM_READY	ro	0x1	SRAM content is ready for read in SRAM_DATA.
31:1	RESERVED	ro	0x0	Reserved

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1.14 : Block: ID_REGISTERS

0x000000F10

1.14.1 : Reg : PERIPHERAL_ID_4 : 0x000000FD0
reg sep address : reg host address :

PERIPHERAL_ID_4

bits	Field name	permission	default	Description
3:0	DES_2_JEP106	ro	0x	Continuation Code. 0x4 for ARM products.
31:4	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.2 : Reg : PIDRESERVED0 : 0x000000FD4
reg sep address : reg host address :

PIDRESERVED0

bits	Field name	permission	default	Description
31:0	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.3 : Reg : PIDRESERVED1 : 0x000000FD8
reg sep address : reg host address :

PIDRESERVED1

bits	Field name	permission	default	Description
31:0	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.4 : Reg : PIDRESERVED2 : 0x000000FDC
reg sep address : reg host address :

PIDRESERVED2

bits	Field name	permission	default	Description
31:0	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.5 : Reg : PERIPHERAL_ID_0 : 0x000000FE0
reg sep address : reg host address :

PERIPHERAL_ID_0

bits	Field name	permission	default	Description
7:0	PART_0	ro	0x	Identification register part number, bits[7:0]
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.6 : Reg : PERIPHERAL_ID_1 : 0x000000FE4
reg sep address : reg host address :

PERIPHERAL_ID_1

bits	Field name	permission	default	Description
3:0	PART_1	ro	0x0	Identification register part number, bits[11:8]
7:4	DES_0_JEP106	ro	0x3	identification code, bits[3:0]. 0x3B for ARM products.
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.7 : Reg : PERIPHERAL_ID_2 : 0x000000FE8
reg sep address : reg host address :

PERIPHERAL_ID_2

bits	Field name	permission	default	Description
2:0	DES_1_JEP106	ro	0x	identification code, bits[6:4]. 0x3B for ARM products.
3	JEDEC	ro	0x1	constant 0x1. Indicates that a JEDEC assigned value is used.
7:4	REVISION	ro	0x0	starts at zero and increments for every new IP release.
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.8 : Reg : PERIPHERAL_ID_3 : 0x000000FEC
reg sep address : reg host address :

PERIPHERAL_ID_3

bits	Field name	permission	default	Description
3:0	CMOD	ro	0x0	Customer Modified, normally zero, but if a partner applies any changes themselves, they must change this value.
7:4	REVAND	ro	0x0	starts at zero for every Revision, and increments if metal fixes are applied between 2 IP releases.
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.9 : Reg : COMPONENT_ID_0 : 0x000000FF0
reg sep address : reg host address :

COMPONENT_ID_0

bits	Field name	permission	default	Description
7:0	PRMBL_0	ro	0x	constant 0xD
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.10 : Reg : COMPONENT_ID_1 : 0x000000FF4
reg sep address : reg host address :

COMPONENT_ID_1

bits	Field name	permission	default	Description
3:0	PRMBL_1	ro	0x0	constant 0x0
7:4	CLASS	ro	0x	component type 0 0xF for Cryptocell
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.11 : Reg : COMPONENT_ID_2 : 0x000000FF8
reg sep address : reg host address :

COMPONENT_ID_2

bits	Field name	permission	default	Description
7:0	PRMBL_2	ro	0x	constant 0x5
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

1.14.12 : Reg : COMPONENT_ID_3 : 0x000000FFC
reg sep address : reg host address :

COMPONENT_ID_3

bits	Field name	permission	default	Description
7:0	PRMBL_3	ro	0x	constant 0xB1
31:8	RESERVED	ro	0x0	Reserved Note: This is a special register, this registers

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1.15 : Block: AO

0x000001E00

1.15.1 : Reg : HOST_DCU_EN0 : 0x000001E00
reg sep address : reg host address :
The DCU [31:0] enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_EN0

bits	Field name	permission	default	Description
31:0	HOST_DCU_EN0	rw	0x0	Debug Control Unit (DCU) Enable bits.

1.15.2 : Reg : HOST_DCU_EN1 : 0x000001E04
reg sep address : reg host address :
The DCU [63:32] enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_EN1

bits	Field name	permission	default	Description
31:0	HOST_DCU_EN1	rw	0x0	Debug Control Unit (DCU) Enable bits.

1.15.3 : Reg : HOST_DCU_EN2 : 0x000001E08
reg sep address : reg host address :
The DCU [95:64] enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_EN2

bits	Field name	permission	default	Description
31:0	HOST_DCU_EN2	rw	0x0	Debug Control Unit (DCU) Enable bits.

1.15.4 : Reg : HOST_DCU_EN3 : 0x000001E0C
reg sep address : reg host address : 1E0C
The DCU [1271:96] enable register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_EN3

bits	Field name	permission	default	Description
31:0	HOST_DCU_EN3	rw	0x0	Debug Control Unit (DCU) Enable bits.

1.15.5 : Reg : HOST_DCU_LOCK0 : 0x000001E10
reg sep address : reg host address :
The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_LOCK0

bits	Field name	permission	default	Description
31:0	HOST_DCU_LOCK0	rw	0x0	DCU_lock [31:0] register (a dedicated lock register per DCU bit).

1.15.6 : Reg : HOST_DCU_LOCK1 : 0x000001E14
reg sep address : reg host address :
The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_LOCK1

bits	Field name	permission	default	Description
31:0	HOST_DCU_LOCK1	rw	0x0	DCU_lock [63:32] register (a dedicated lock register per DCU bit).

1.15.7 : Reg : HOST_DCU_LOCK2 : 0x000001E18
reg sep address : reg host address :
The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_LOCK2

bits	Field name	permission	default	Description
31:0	HOST_DCU_LOCK2	rw	0x0	DCU_lock [95:64] register (a dedicated lock register per DCU bit).

1.15.8 : Reg : HOST_DCU_LOCK3 : 0x000001E1C
reg sep address : reg host address :
The DCU lock register.Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_DCU_LOCK3

bits	Field name	permission	default	Description
31:0	HOST_DCU_LOCK3	rw	0x0	DCU_lock [127:96] register (a dedicated lock register per DCU bit).

1.15.9 : Reg : AO_ICV_DCU_RESTRICTION_MASK0 : 0x000001E20
reg sep address : reg host address :
The DCU lock register.

AO_ICV_DCU_RESTRICTION_MASK0

bits	Field name	permission	default	Description
31:0	AO_ICV_DCU_RESTRICTION_MASK0	ro	0x	AO_ICV_DCU_RESTRICTION_MASK [31:0] parameter, that will be a customer modifiable.

1.15.10 : Reg : AO_ICV_DCU_RESTRICTION_MASK1 : 0x000001E24
reg sep address : reg host address :
The "ICV_DCU_restriction_mask" parameter is read by FW during the secure debug verification to prevent OEM from setting specific DCUs that protect ICV secrets

AO_ICV_DCU_RESTRICTION_MASK1

bits	Field name	permission	default	Description
31:0	AO_ICV_DCU_RESTRICTION_MASK1	ro	0x	AO_ICV_DCU_RESTRICTION_MASK [63:32] parameter, that will be a customer modifiable.

1.15.11 : Reg : AO_ICV_DCU_RESTRICTION_MASK2 : 0x000001E28
reg sep address : reg host address :
The "ICV_DCU_restriction_mask" parameter is read by FW during the secure debug verification to prevent OEM from setting specific DCUs that protect ICV secrets

AO_ICV_DCU_RESTRICTION_MASK2

bits	Field name	permission	default	Description
31:0	AO_ICV_DCU_RESTRICTION_MASK2	ro	0x0	AO_ICV_DCU_RESTRICTION_MASK [95:64] parameter, that will be a customer modifiable.

1.15.12 : Reg : AO_ICV_DCU_RESTRICTION_MASK3 : 0x000001E2C
reg sep address : reg host address :
The "ICV_DCU_restriction_mask" parameter is read by FW during the secure debug verification to prevent OEM from setting specific DCUs that protect ICV secrets

AO_ICV_DCU_RESTRICTION_MASK3

bits	Field name	permission	default	Description
31:0	AO_ICV_DCU_RESTRICTION_MASK3	ro	0x0	AO_ICV_DCU_RESTRICTION_MASK [127:96] parameter, that will be a customer modifiable.

1.15.13 : Reg : AO_CC_SEC_DEBUG_RESET : 0x000001E30
reg sep address : reg host address :
The reset-upon-debug indication

AO_CC_SEC_DEBUG_RESET

bits	Field name	permission	default	Description
0:0	AO_CC_SEC_DEBUG_RESET	ro	0x0	For resets Cerberus, and prevents loading the HW keys after that reset
31:1	RESERVED	ro	0x0	Reserved

1.15.14 : Reg : HOST_AO_LOCK_BITS : 0x000001E34
reg sep address : reg host address :
These masks will define, per LCS, which DCU bits will be tied to zero, even if the Host tries to set them. Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_AO_LOCK_BITS

bits	Field name	permission	default	Description
0:0	HOST_FATAL_ERR	rw	0x0	When the "FATAL_ERROR" register is asserted - HW keys will not be copied from OTP
1:1	HOST_KPICV_LOCK	rw	0x0	When this FW controlled register is set, the Kpicv HW key is masked (to zero).
2:2	HOST_KCEICV_LOCK	rw	0x0	When this FW controlled register is set, the Kceicv HW key is masked (to zero).
3:3	HOST_KCP_LOCK	rw	0x0	When this FW controlled register is set, the Kcp HW key is masked (to zero).
4:4	HOST_KCE_LOCK	rw	0x0	When this FW controlled register is set, the Kce HW key is masked (to zero).
5:5	HOST_ICV_RMA_LOCK	rw	0x0	The ICV_RMA_LOCK register is set-once (per POR).
6:6	RESET_UPON_DEBUG_DISABLE	rw	0x0	The RESET_UPON_DEBUG_DISABLE register is set-once (per POR).
7:7	HOST_FORCE_DFA_ENABLE	rw	0x1	When this FW controlled register is set, the AES DFA countermeasures are enabled/disabled (regardless of the AES_DFA_IS_ON register value).
8:8	HOST_DFA_ENABLE_LOCK	rw	0x0	When this FW control is set, the DFA_ENABLE register can't be written until the next POR. The DFA_ENABLE_LOCK register is set-once (per POR).
31:9	RESERVED	rw	0x0	Reserved

1.15.15 : Reg : AO_APB_FILTERING : 0x000001E38
reg sep address : reg host address :
This register holds the AO_APB_FILTERING data. Note: This is a special register, affected by internal logic. Test result of this register is NA.

AO_APB_FILTERING

bits	Field name	permission	default	Description
0:0	ONLY_SEC_ACCESS_ALLOW	rw	0x1	when this FW controlled register is set, the APB slave accepts only secure accesses
1:1	ONLY_SEC_ACCESS_ALLOW_LOCK	rw	0x0	when this FW controlled register is set, the ONLY_SEC_ACCESS_ALLOWED register can't be modified (until the next POR).
2:2	ONLY_PRIV_ACCESS_ALLOW	rw	0x1	when this FW controlled register is set, the APB slave accepts only privileged accesses
3:3	ONLY_PRIV_ACCESS_ALLOW_LOCK	rw	0x0	when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLOWED register can't be modified (until the next POR)
4:4	APBC_ONLY_SEC_ACCESS_ALLOW	rw	0x1	when this FW controlled register is set, the APB-C slave accepts only secure accesses
5:5	APBC_ONLY_SEC_ACCESS_ALLOW_LOCK	rw	0x0	when this FW controlled register is set, the APBC_ONLY_SEC_ACCESS_ALLOWED register can't be modified (until the next POR).
6:6	APBC_ONLY_PRIV_ACCESS_ALLOW	rw	0x1	when this FW controlled register is set, the APB-C slave accepts only privileged accesses
7:7	APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK	rw	0x0	when this FW controlled register is set, the APBC_ONLY_PRIV_ACCESS_ALLOWED register can't be modified (until the next POR)
8:8	APBC_ONLY_INST_ACCESS_ALLOW	rw	0x0	when this FW controlled register is set, the APB-C slave accepts only instruction accesses
9:9	APBC_ONLY_INST_ACCESS_ALLOW_LOCK	rw	0x0	when this FW controlled register is set, the APBC_ONLY_INST_ACCESS_ALLOWED register can't be modified (until the next POR)
31:10	RESERVED	rw	0x0	Reserved

1.15.16 : Reg : AO_CC_GPPC : 0x000001E3C
reg sep address : reg host address :
holds the AO_CC_GPPC value from AO
Note: This is a special register, affected by internal logic. Test result of this register is NA.

AO_CC_GPPC

bits	Field name	permission	default	Description
7:0	AO_CC_GPPC	ro	0x0	The AO_CC_GPPC value
31:8	RESERVED	ro	0x0	reserved

1.15.17 : Reg : HOST_RGF_CC_SW_RST : 0x000001E40
reg sep address : reg host address :
Writing to this register generates a general reset to CryptoCell. This reset takes about 4 core clock cycles.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

HOST_RGF_CC_SW_RST

bits	Field name	permission	default	Description
0:0	HOST_RGF_CC_SW_RST	wo	0x0	Writing '1' to this field generates a general reset to CryptoCell.
31:1	RESERVED	wo	0x0	Reserved

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1.16 : Block: NVM

0x000001F00

1.16.1 : Reg : AIB_FUSE_PROG_COMPLETED : 0x000001F04
reg sep address : reg host address :
This register reflects the fuse_aib_prog_completed input, which indicates that the fuse programming was completed.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

AIB_FUSE_PROG_COMPLETED

bits	Field name	permission	default	Description
0:0	AIB_FUSE_PROG_COMPLETED	ro	0x0	Indicates if the fuse programming operation has been completed.
31:1	RESERVED	ro	0x0	Reserved

1.16.2 : Reg : NVM_DEBUG_STATUS : 0x000001F08
reg sep address : reg host address :
AIB debug status register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

NVM_DEBUG_STATUS

bits	Field name	permission	default	Description
0:0	RESERVED0	ro	0x0	Reserved
3:1	NVM_SM	ro	0x0	Main nvm fsm 3'b000 - IDLE 3'b001 - READ_DUMMY 3'b010 - READ_MAN_FLAG 3'b011 - READ_OEM_FLAG 3'b100 - READ_GPPC 3'b101 - DECODE 3'b110 - OTP_LCS_VALID 3'b111 - LCS_IS_VALID
31:4	RESERVED1	ro	0x0	Reserved

1.16.3 : Reg : LCS_IS_VALID : 0x000001F0C
reg sep address : reg host address :
Indicates that the LCS register holds a valid value.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

LCS_IS_VALID

bits	Field name	permission	default	Description
0:0	LCS_IS_VALID_REG	ro	0x0	Indicates whether LCS is valid.
31:1	RESERVED	ro	0x0	Reserved

1.16.4 : Reg : NVM_IS_IDLE : 0x000001F10
reg sep address : reg host address :
Indicates that the LCS register holds a valid value.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

NVM_IS_IDLE

bits	Field name	permission	default	Description
0:0	NVM_IS_IDLE_REG	ro	0x0	Indicates whether the NVM manager finishes its operation, calculates the LCS, reads the HW keys, compares the number of zeros and clears the keys
31:1	RESERVED	ro	0x0	Reserved

1.16.5 : Reg : LCS_REG : 0x000001F14
reg sep address : reg host address :
The lifecycle state register.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

LCS_REG

bits	Field name	permission	default	Description
2:0	LCS_REG	ro	0x	Indicates the LCS (Lifecycle State) value. 3'b000 - CM 3'b001 - DM 3'b101 - SE 3'b111 - RMA
7:3	RESERVED0	ro	0x0	Reserved
8:8	ERROR_KDR_ZERO_CNT	ro	0x0	Indication that the number of zeroes in the loaded KDR is not equal to the value set in the manufacture flag.
9:9	ERROR_PROV_ZERO_CNT	ro	0x0	Indication that the number of zeroes in the loaded KCP is not equal to the value set in the OEM flag.
10:10	ERROR_KCE_ZERO_CNT	ro	0x0	Indication that the number of zeroes in the loaded KCE is not equal to the value set in the OEM flag.
11:11	ERROR_KPICV_ZERO_CNT	ro	0x0	Indication that the number of zeroes in the loaded KPICV is not equal to the value set in the manufacture flag.
12:12	ERROR_KCEICV_ZERO_CNT	ro	0x0	Indication that the number of zeroes in the loaded KCEICV is not equal to the value set in the manufacture flag.
31:13	RESERVED1	ro	0x0	Reserved

1.16.6 : Reg : HOST_SHADOW_KDR_REG : 0x000001F18
reg sep address : reg host address :
This register interface is used to update the RKEK(KDR) registers when the device is in CM or DM mode , it is Write-once (per warm boot) in RMA LCS, The RKEK is updated by shifting .

HOST_SHADOW_KDR_REG

bits	Field name	permission	default	Description
0:0	HOST_SHADOW_KDR_REG	wo	0x0	This field is used to update the KDR registers when the device is in CM , DM or RMA mode, The KDR is updated by shifting .
31:1	RESERVED	wo	0x0	Reserved

1.16.7 : Reg : HOST_SHADOW_KCP_REG : 0x000001F1C
reg sep address : reg host address :
This register interface is used to update the KCP registers when the device is in CM or DM mode, The KCP is updated by shifting

HOST_SHADOW_KCP_REG

bits	Field name	permission	default	Description
0:0	HOST_SHADOW_KCP_REG	wo	0x0	This field is used to update the KCP registers when the device is in CM or DM mode, The KCP is updated by shifting
31:1	RESERVED	wo	0x0	Reserved

1.16.8 : Reg : HOST_SHADOW_KCE_REG : 0x000001F20
reg sep address : reg host address :
This register interface is used to update the KCE registers when the device is in CM or DM mode, The KCE is updated by shifting

HOST_SHADOW_KCE_REG

bits	Field name	permission	default	Description
0:0	HOST_SHADOW_KCE_REG	wo	0x0	This field is used to update the KCE registers when the device is in CM or DM mode, The KCE is updated by shifting
31:1	RESERVED	wo	0x0	Reserved

1.16.9 : Reg : HOST_SHADOW_KPICV_REG : 0x000001F24
reg sep address : reg host address :
This register interface is used to update the KPICV registers when the device is in CM or DM mode, The KPICV is updated by shifting

HOST_SHADOW_KPICV_REG

bits	Field name	permission	default	Description
0:0	HOST_SHADOW_KPICV_REG	wo	0x0	This field is used to update the KPICV registers when the device is in CM or DM mode, The KPICV is updated by shifting
31:1	RESERVED	wo	0x0	Reserved

1.16.10 : Reg : HOST_SHADOW_KCEICV_REG : 0x000001F28
reg sep address : reg host address :
This register interface is used to update the KCEICV registers when the device is in CM or DM mode, The KCEICV is updated by shifting

HOST_SHADOW_KCEICV_REG

bits	Field name	permission	default	Description
0:0	HOST_SHADOW_KCEICV_REG	wo	0x0	This field is used to update the KCEICV registers when the device is in CM or DM mode, The KCEICV is updated by shifting
31:1	RESERVED	wo	0x0	Reserved

1.16.11 : Reg : OTP_ADDR_WIDTH_DEF : 0x000001F2C
reg sep address : reg host address :
OTP_ADDR_WIDTH parameter, that will define the integrated OTP address width (address in words). The supported sizes are 6 (for 2 Kbits),7,8,9,11 (for 64 Kbits). The default value in the provided RTL will be 6.
Note: This is a special register, affected by internal logic. Test result of this register is NA.

OTP_ADDR_WIDTH_DEF

bits	Field name	permission	default	Description
3:0	OTP_ADDR_WIDTH_DEF	ro	0x	Holds the OTP_ADDR_WIDTH_DEF value.
31:4	RESERVED	ro	0x0	Reserved

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1.17 : Block: ENV_CC_MEMORIES

0x060004000

1.17.1 : Reg : ENV_FUSE_READY : 0x060004000
reg sep address : reg host address :
keep FUSE ready de-asserted (used in Discretix internal DSM tests only)
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FUSE_READY

bits	Field name	permission	default	Description
0:0	FUSE_READY	wo	0x0	1'0 - FUSE ready kept low , 1'1 - FUSE ready released
31:1	RESERVED	wo	0x0	31'b0

1.17.2 : Reg : ENV_PERF_RAM_MASTER : 0x0600040EC
reg sep address : reg host address :
selects who's the Performance RAM master
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_PERF_RAM_MASTER

bits	Field name	permission	default	Description
0:0	PERF_RAM_MASTER	wo	0x0	1'b0 - sw_monitor_sni0er, 1'b1 - HOST
31:1	RESERVED	wo	0x0	selects who's the Performance RAM master

1.17.3 : Reg : ENV_PERF_RAM_ADDR_HIGH4 : 0x0600040F0
reg sep address : reg host address :
4 bits to concat with ENV_PERF_RAM_BASE[11]
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_PERF_RAM_ADDR_HIGH4

bits	Field name	permission	default	Description
1:0	ADDR_HIGH_4	wo	0x0	4 bits to concatenate: perf ram address = {ENV_PERF_RAM_ADDR_HIGH[3:0] ENV_PERF_RAM_BASE[11:2]}
31:2	RESERVED	wo	0x0	4 bits to concat with ENV_PERF_RAM_BASE[11

1.17.4 : Reg : ENV_FUSES_RAM : 0x0600043EC
reg sep address : reg host address :
Using this address the HOST gains access to the aib_slave_model (fuses). (Actually there are 256 words hidden here.)
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FUSES_RAM

bits	Field name	permission	default	Description
31:0	FUSE_VAL	r/wc	0x0	Fuse value

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1.18 : Block: FPGA_ENV_REGS

0x060005000

1.18.1 : Reg : ENV_FPGA_PKA_DEBUG_MODE : 0x060005024
reg sep address : reg host address :
Drive PKA debug mode
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_PKA_DEBUG_MODE

bits	Field name	permission	default	Description
0:0	PKA_DEBUG_MODE	rw	0x0	1'b1 - PKA in debug mode
31:1	RESERVED	rw	0x0	0

1.18.2 : Reg : ENV_FPGA_SCAN_MODE : 0x060005030
reg sep address : reg host address :
CryptoCell scan_mode input
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SCAN_MODE

bits	Field name	permission	default	Description
0:0	SCAN_MODE	wo	0x0	when Scan mode is set RKEKs are reset
31:1	RESERVED	wo	0x0	0

1.18.3 : Reg : ENV_FPGA_CC_ALLOW_SCAN : 0x060005034
reg sep address : reg host address :
CryptoCell allow_scan output
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_ALLOW_SCAN

bits	Field name	permission	default	Description
0:0	CC_ALLOW_SCAN	ro	0x1	When low scan can not be performed. Reset value is: 1'b1
31:1	RESERVED	ro	0x0	0

1.18.4 : Reg : ENV_FPGA_CC_HOST_INT : 0x0600050A0
reg sep address : reg host address :
CryptoCell interrupt value
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_HOST_INT

bits	Field name	permission	default	Description
0:0	CC_HOST_INT	ro	0x0	CryptoCell interrupt to Host Active High
31:1	RESERVED	ro	0x0	0

1.18.5 : Reg : ENV_FPGA_CC_PUB_HOST_INT : 0x0600050A4
reg sep address : reg host address :
CryptoCell public host interrupt value
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_PUB_HOST_INT

bits	Field name	permission	default	Description
0:0	CC_PUB_HOST_INT	ro	0x0	CryptoCell interrupt to public Host Active High
31:1	RESERVED	ro	0x0	0

1.18.6 : Reg : ENV_FPGA_CC_RST_N : 0x0600050A8
reg sep address : reg host address :
generate reset cycle towards CryptoCell
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_RST_N

bits	Field name	permission	default	Description
0:0	CC_RST_N	wo	0x0	1'b1 - generate reset cycle towards CryptoCell
31:1	RESERVED	wo	0x0	generate reset cycle towards CryptoCell

1.18.7 : Reg : ENV_FPGA_RST_OVERRIDE : 0x0600050AC
reg sep address : reg host address :
Force high all reset lines in CryptoCell
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_RST_OVERRIDE

bits	Field name	permission	default	Description
0:0	RST_OVERRIDE	wo	0x0	1'b1 - doesn't permit SW_RST or SYS_RST to CryptoCell or any engine
31:1	RESERVED	wo	0x0	Force high all reset lines in CryptoCell Note: This is a special register, affected by internal logic. Test result of this register is NA.

1.18.8 : Reg : ENV_FPGA_CC_POR_N_ADDR : 0x0600050E0
reg sep address : reg host address :
CryptoCell power ON
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_POR_N_ADDR

bits	Field name	permission	default	Description
0:0	CC_POR_N_ADDR	wo	0x1	Active low. When asserted indicates that the entire system is powered on and not only the CryptoCell. If there's no potential powering down of the CryptoCell in the SoC this input must be connected to the SYS_RST_n input
31:1	RESERVED	wo	0x0	CryptoCell power ON

1.18.9 : Reg : ENV_FPGA_CC_COLD_RST : 0x0600050FC
reg sep address : reg host address :
CryptoCell cold reset
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_COLD_RST

bits	Field name	permission	default	Description
0:0	ENV_CC_COLD_RST	wo	0x0	CryptoCell cold reset assertion
31:1	RESERVED	wo	0x0	CryptoCell cold reset

1.18.10 : Reg : ENV_FPGA_DUMMY_ADDR : 0x060005108
reg sep address : reg host address :
dummy environment register
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_DUMMY_ADDR

bits	Field name	permission	default	Description
31:0	ENV_DUMMY_ADDR	rw	0x0	0

1.18.11 : Reg : ENV_FPGA_COUNTER_CLR : 0x060005118
reg sep address : reg host address :
clear and start the SW counter
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_COUNTER_CLR

bits	Field name	permission	default	Description
0:0	COUNTER_CLR	wo	0x0	1'b1 - clear/start counter
31:1	RESERVED	wo	0x0	clear and start the SW counter

1.18.12 : Reg : ENV_FPGA_COUNTER_RD : 0x06000511C
reg sep address : reg host address :
clear and start the SW counter
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_COUNTER_RD

bits	Field name	permission	default	Description
31:0	COUNTER_VAL	ro	0x0	SW counter value

1.18.13 : Reg : ENV_FPGA_RNG_DEBUG_ENABLE : 0x060005430
reg sep address : reg host address :
set RNG debug port
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_RNG_DEBUG_ENABLE

bits	Field name	permission	default	Description
0:0	DEBUG_EN	wo	0x0	1'b1 - RNG debug port asserted
31:1	RESERVED	wo	0x0	31'b0

1.18.14 : Reg : ENV_FPGA_CC_LCS : 0x06000543C
reg sep address : reg host address :
LCS register value
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_LCS

bits	Field name	permission	default	Description
7:0	LCS	ro	0x0	LCS data
31:8	RESERVED	ro	0x0	24'b0

1.18.15 : Reg : ENV_FPGA_CC_IS_CM_DM_SECURE_RMA : 0x060005440
reg sep address : reg host address :
read the lcs states if it is CM DM SECURED or RMA
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_IS_CM_DM_SECURE_RMA

bits	Field name	permission	default	Description
0:0	IS_CM	ro	0x0	1'b1 - lcs state is CM 1'b0 - not
1:1	IS_DM	ro	0x0	1'b1 - lcs state is DM 1'b0 - not
2:2	IS_SECURE	ro	0x0	1'b1 - lcs state is SECURE 1'b0 - not
3:3	IS_RMA	ro	0x0	1'b1 - lcs state is RMA 1'b0 - not
31:4	RESERVED	ro	0x0	28'b0

1.18.16 : Reg : ENV_FPGA_DCU_EN : 0x060005444
reg sep address : reg host address :
read the lcs states if it is CM DM SECURED or RMA
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_DCU_EN

bits	Field name	permission	default	Description
31:0	DCU_EN	ro	0x0	Every bit in this sets of bits sets the matching dcu_en signal to a single dcu.

1.18.17 : Reg : ENV_FPGA_CC_LCS_IS_VALID : 0x060005448
reg sep address : reg host address :
boot process finished reading LCS from NVM and write it to LCS register
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_CC_LCS_IS_VALID

bits	Field name	permission	default	Description
0:0	LCS_IS_VALID	ro	0x0	LCS data is valid
31:1	RESERVED	ro	0x0	31'b0

1.18.18 : Reg : ENV_FPGA_POWER_DOWN : 0x060005478
reg sep address : reg host address :
ENV_POWER_DOWN change bus to X's in DX simulations ONLY !
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_POWER_DOWN

bits	Field name	permission	default	Description
31:0	ENV_POWER_DOWN	wo	0x0	write pulse of power down indication. Used for Internal DX simulations ONLY !

1.18.19 : Reg : ENV_FPGA_DCU_H_EN : 0x060005484
reg sep address : reg host address :
read the lcs states if it is CM DM SECURED or RMA
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_DCU_H_EN

bits	Field name	permission	default	Description
31:0	DCU_EN	ro	0x0	Every bit in this sets of bits sets the matching dcu_en signal to a single dcu.

1.18.20 : Reg : ENV_FPGA_VERSION : 0x060005488
reg sep address : reg host address :
version of FPGA
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_VERSION

bits	Field name	permission	default	Description
31:0	FPGA_VERSION	ro	0x0	Define the FPGA version.

1.18.21 : Reg : ENV_FPGA_ROSC_WRITE : 0x06000548C
reg sep address : reg host address :
ROSC write select
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_ROSC_WRITE

bits	Field name	permission	default	Description
0:0	ROSC_PSEL	wo	0x0	rosc psel
31:1	RESERVED	wo	0x0	31'b0

1.18.22 : Reg : ENV_FPGA_ROSC_ADDR : 0x060005490
reg sep address : reg host address :
ROSC ADDRRESS
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_ROSC_ADDR

bits	Field name	permission	default	Description
7:0	ROSC_ADDR	wo	0x0	rosc address
31:8	RESERVED	wo	0x0	24'b0

1.18.23 : Reg : ENV_FPGA_RESET_SESSION_KEY : 0x060005494
reg sep address : reg host address :
Reset the session key
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_RESET_SESSION_KEY

bits	Field name	permission	default	Description
0:0	RESET_SESSION_KEY	wo	0x0	async reset for the session key - (fpga env only)
31:1	RESERVED	wo	0x0	31'b0

1.18.24 : Reg : ENV_FPGA_SESSION_KEY_0 : 0x0600054A0
reg sep address : reg host address :
Session key 0
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SESSION_KEY_0

bits	Field name	permission	default	Description
31:0	SESSION_KEY_0	wo	0x0	Session key 0

1.18.25 : Reg : ENV_FPGA_SESSION_KEY_1 : 0x0600054A4
reg sep address : reg host address :
Session key 0
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SESSION_KEY_1

bits	Field name	permission	default	Description
31:0	SESSION_KEY_1	wo	0x0	Session key 1

1.18.26 : Reg : ENV_FPGA_SESSION_KEY_2 : 0x0600054A8
reg sep address : reg host address :
Session key 1
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SESSION_KEY_2

bits	Field name	permission	default	Description
31:0	SESSION_KEY_2	wo	0x0	Session key 2

1.18.27 : Reg : ENV_FPGA_SESSION_KEY_3 : 0x0600054AC
reg sep address : reg host address :
Session key 1
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SESSION_KEY_3

bits	Field name	permission	default	Description
31:0	SESSION_KEY_3	wo	0x0	Session key 3

1.18.28 : Reg : ENV_FPGA_SESSION_KEY_VALID : 0x0600054B0
reg sep address : reg host address :
Session key valid
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SESSION_KEY_VALID

bits	Field name	permission	default	Description
0:0	SESSION_KEY_VALID	wo	0x0	Session key valid
31:1	RESERVED	wo	0x0	reserved

1.18.29 : Reg : ENV_FPGA_SPIDEN : 0x0600054D0
reg sep address : reg host address :
spiden override
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SPIDEN

bits	Field name	permission	default	Description
0:0	SPIDEN	rw	0x0	spiden value
31:1	RESERVED	rw	0x0	reserved

1.18.30 : Reg : ENV_FPGA_AXIM_USER_PARAMS : 0x060005600
reg sep address : reg host address :
axim master cache coherency configuration override
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_AXIM_USER_PARAMS

bits	Field name	permission	default	Description
4:0	ARUSER	rw	0x0	aruser override value
9:5	AWUSER	rw	0x0	awuser override value
31:10	RESERVED	rw	0x0	reserved

1.18.31 : Reg : ENV_FPGA_SECURITY_MODE_OVERRIDE : 0x060005604
reg sep address : reg host address :
axim master prot override
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SECURITY_MODE_OVERRIDE

bits	Field name	permission	default	Description
0:0	AWPROT_NS_BIT	rw	0x0	AWPROT override value
1:1	AWPROT_NS_OVERRIDE	rw	0x0	AWPROT override enable
2:2	ARPROT_NS_BIT	rw	0x0	ARPROT override value
3:3	ARPROT_NS_OVERRIDE	rw	0x0	ARPROT override enable
31:4	RESERVED	rw	0x0	reserved

1.18.32 : Reg : ENV_FPGA_SRAM_ENABLE : 0x060005608
reg sep address : reg host address :
SRAM enable
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_SRAM_ENABLE

bits	Field name	permission	default	Description
0:0	SRAM_ENABLE	wo	0x0	sram enable bit
31:1	RESERVED	wo	0x0	reserved

1.18.33 : Reg : ENV_FPGA_APB_FIPS_ADDR : 0x060005650
reg sep address : reg host address :
the secure host register offset for fips access match
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_FIPS_ADDR

bits	Field name	permission	default	Description
11:0	FIPS_ADDR	wo	0x0	SECURE HOST FIPS register offset
31:12	RESERVED	wo	0x0	reserved

1.18.34 : Reg : ENV_FPGA_APB_FIPS_VAL : 0x060005654
reg sep address : reg host address :
the secure host write data for fips access match
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_FIPS_VAL

bits	Field name	permission	default	Description
31:0	FIPS_DATA	wo	0x0	SECURE HOST FIPS data

1.18.35 : Reg : ENV_FPGA_APB_FIPS_MASK : 0x060005658
reg sep address : reg host address :
the secure host write data mask for fips access match
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_FIPS_MASK

bits	Field name	permission	default	Description
31:0	FIPS_MASK	wo	0x0	SECURE HOST FIPS data mask

1.18.36 : Reg : ENV_FPGA_APB_FIPS_CNT : 0x06000565C
reg sep address : reg host address :
the secure host fips access counter thershold
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_FIPS_CNT

bits	Field name	permission	default	Description
31:0	FIPS_CNT	wo	0x0	SECURE HOST FIPS CNT

1.18.37 : Reg : ENV_FPGA_APB_FIPS_NEW_ADDR : 0x060005660
reg sep address : reg host address :
the secure host register offset of the new register after FIPS cnt reached
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_FIPS_NEW_ADDR

bits	Field name	permission	default	Description
11:0	FIPS_NEW_ADDR	wo	0x0	SECURE HOST FIPS NEW register offset
31:12	RESERVED	wo	0x0	reserved

1.18.38 : Reg : ENV_FPGA_APB_FIPS_NEW_VAL : 0x060005664
reg sep address : reg host address :
the secure host new write data after fips cnt reached
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_FIPS_NEW_VAL

bits	Field name	permission	default	Description
31:0	FIPS_DATA	wo	0x0	SECURE HOST FIPS NEW data

1.18.39 : Reg : ENV_FPGA_APB_PPROT_OVERRIDE : 0x060005668
reg sep address : reg host address :
apbs pprot override
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APB_PPROT_OVERRIDE

bits	Field name	permission	default	Description
2:0	PPROT_OVERRIDE_VAL	rw	0x0	PPROT override value
3:3	PPROT_OVERRIDE_CNTL	rw	0x0	PPROT override control ;1 = ovveride
31:4	RESERVED	rw	0x0	ARPROT override value

1.18.40 : Reg : ENV_FPGA_APBP_FIPS_ADDR : 0x060005670
reg sep address : reg host address :
the public host register offset for fips access match
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APBP_FIPS_ADDR

bits	Field name	permission	default	Description
11:0	FIPS_ADDR	wo	0x0	PUBLIC HOST FIPS register offset
31:12	RESERVED	wo	0x0	reserved

1.18.41 : Reg : ENV_FPGA_APBP_FIPS_VAL : 0x060005674
reg sep address : reg host address :
the public host write data for fips access match
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APBP_FIPS_VAL

bits	Field name	permission	default	Description
31:0	FIPS_DATA	wo	0x0	PUBLIC HOST FIPS data

1.18.42 : Reg : ENV_FPGA_APBP_FIPS_MASK : 0x060005678
reg sep address : reg host address :
the public host write data mask for fips access match
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APBP_FIPS_MASK

bits	Field name	permission	default	Description
31:0	FIPS_MASK	wo	0x0	PUBLIC HOST FIPS data mask

1.18.43 : Reg : ENV_FPGA_APBP_FIPS_CNT : 0x06000567C
reg sep address : reg host address :
the public host fips access counter thershold
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APBP_FIPS_CNT

bits	Field name	permission	default	Description
31:0	FIPS_CNT	wo	0x0	PUBLIC HOST FIPS CNT

1.18.44 : Reg : ENV_FPGA_APBP_FIPS_NEW_ADDR : 0x060005680
reg sep address : reg host address :
the public host register offset of the new register after FIPS cnt reached
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APBP_FIPS_NEW_ADDR

bits	Field name	permission	default	Description
11:0	FIPS_NEW_ADDR	wo	0x0	PUBLIC HOST FIPS NEW register offset
31:12	RESERVED	wo	0x0	reserved

1.18.45 : Reg : ENV_FPGA_APBP_FIPS_NEW_VAL : 0x060005684
reg sep address : reg host address :
the public host new write data after fips cnt reached
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_APBP_FIPS_NEW_VAL

bits	Field name	permission	default	Description
31:0	FIPS_DATA	wo	0x0	PUBLIC HOST FIPS NEW data

1.18.46 : Reg : ENV_FPGA_AO_CC_GPPC : 0x060005700
reg sep address : reg host address :
holds the AO_CC_GPPC value from AO
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_FPGA_AO_CC_GPPC

bits	Field name	permission	default	Description
7:0	AO_CC_GPPC	ro	0x0	AO_CC_GPPC
31:8	RESERVED	ro	0x0	reserved

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1.19 : Block: ENV_PERF_RAM_BASE

0x060006000

1.19.1 : Reg : ENV_PERF_RAM_BASE : 0x060006000
reg sep address : reg host address :
Performance RAM base address Data read from performance RAM
Note: This is a special register, affected by internal logic. Test result of this register is NA.

ENV_PERF_RAM_BASE

bits	Field name	permission	default	Description
31:0	PERF_RAM_D	ro	0x0	Data read from performance RAM

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