12 #if defined(__ICCARM__)
14 #pragma required=tfm_core_svc_handler
27 __attribute__((naked))
36 __attribute__((naked))
37 static int32_t tfm_spm_request(int32_t request_type)
50 __attribute__((naked))
58 __attribute__((naked))
66 __attribute__((naked))
85 actual_signal_mask = psa_wait_internal(signal_mask, timeout);
86 if ((actual_signal_mask & signal_mask) != 0) {
87 return actual_signal_mask;
93 __attribute__((naked))
101 #if defined(__ARM_ARCH_8_1M_MAIN__) || defined(__ARM_ARCH_8M_MAIN__)
102 __attribute__((section(
"SFN"), naked))
106 "PUSH {r4-r12, lr} \n"
118 "POP {r4-r12, pc} \n"
124 __attribute__((section(
"SFN"), naked))
126 uint32_t irq_signal, uint32_t irq_line)
130 "PUSH {r4-r12, lr} \n"
149 "POP {r4-r12, pc} \n"
154 #elif defined(__ARM_ARCH_8M_BASE__)
155 __attribute__((section(
"SFN"), naked))
193 __attribute__((section(
"SFN"), naked))
195 uint32_t irq_signal, uint32_t irq_line)
199 "PUSH {r4-r7, lr} \n"
239 #if defined(__ARM_ARCH_8_1M_MAIN__) || \
240 defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8M_BASE__)
249 VECTKEY = (~AIRCR & SCB_AIRCR_VECTKEYSTAT_Msk);
250 scb->AIRCR = SCB_AIRCR_PRIS_Msk |
252 (AIRCR & ~SCB_AIRCR_VECTKEY_Msk);
254 #ifndef __ARM_ARCH_8M_BASE__
255 NVIC_SetPriority(MemoryManagement_IRQn, 0);
256 NVIC_SetPriority(BusFault_IRQn, 0);
257 NVIC_SetPriority(SecureFault_IRQn, 0);
264 NVIC_SetPriority(SVCall_IRQn, 0);
265 NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
268 #error Function based model works on V8M series only.
273 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
278 #if defined (__FPU_USED) && (__FPU_USED == 1U)
280 SCB->CPACR |= (3U << 10U*2U)
283 #if defined(__ARM_ARCH_8_1M_MAIN__) || defined(__ARM_ARCH_8M_MAIN__)
288 FPU->FPCCR |= FPU_FPCCR_TS_Msk
289 | FPU_FPCCR_CLRONRET_Msk
290 | FPU_FPCCR_CLRONRETS_Msk;
294 #if defined(__ARM_ARCH_8_1M_MAIN__) || defined(__ARM_ARCH_8M_MAIN__)
299 SCB->NSACR |= SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk;
304 #if defined(__ARM_ARCH_8M_BASE__) || defined(__ARM_ARCH_8_1M_MAIN__) || defined(__ARM_ARCH_8M_MAIN__)
308 #if !defined(__ICCARM__)
322 "LDR r0, =0xFEF5EDA5 \n"
329 "BL tfm_core_svc_handler \n"
343 #elif defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_7M__) || \
344 defined(__ARM_ARCH_7EM__)
358 "BL tfm_core_svc_handler \n"
371 __ASM
volatile(
"b .");
381 __ASM
volatile(
"b .");
391 __ASM
volatile(
"b .");
401 __ASM
volatile(
"b .");
void tfm_disable_irq(psa_signal_t irq_signal)
void jump_to_ns_code(void)
Jump to non-secure code.
void psa_eoi(psa_signal_t irq_signal)
Inform the SPM that an interrupt has been handled (end of interrupt).
void BusFault_Handler(void)
void MemManage_Handler(void)
void HardFault_Handler(void)
int32_t tfm_core_sfn_request(const struct tfm_sfn_req_s *desc_ptr)
int32_t tfm_spm_request_reset_vote(void)
Request a vote from SPM on a system reset.
void tfm_arch_set_secure_exception_priorities(void)
void tfm_core_panic(void)
void tfm_enable_irq(psa_signal_t irq_signal)
void priv_irq_handler_main(uint32_t partition_id, uint32_t unpriv_handler, uint32_t irq_signal, uint32_t irq_line)
int32_t tfm_core_get_caller_client_id(int32_t *caller_client_id)
void tfm_arch_configure_coprocessors(void)
Configure coprocessors.
uint32_t tfm_core_svc_handler(uint32_t *svc_args, uint32_t lr, uint32_t *msp)
psa_signal_t psa_wait(psa_signal_t signal_mask, uint32_t timeout)
Return the Secure Partition interrupt signals that have been asserted from a subset of signals provid...
void SecureFault_Handler(void)