00001
00034 #include "em_ebi.h"
00035 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
00036 #include "em_assert.h"
00037 #include "em_bitband.h"
00038
00039
00044
00050
00061 void EBI_Init(const EBI_Init_TypeDef *ebiInit)
00062 {
00063 uint32_t ctrl = EBI->CTRL;
00064
00065 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00066
00067 ctrl |= EBI_CTRL_ITS;
00068
00069
00070 EBI_BankPolaritySet(ebiInit->banks, ebiLineARDY, ebiInit->ardyPolarity);
00071
00072 EBI_BankPolaritySet(ebiInit->banks, ebiLineALE, ebiInit->alePolarity);
00073
00074 EBI_BankPolaritySet(ebiInit->banks, ebiLineWE, ebiInit->wePolarity);
00075
00076 EBI_BankPolaritySet(ebiInit->banks, ebiLineRE, ebiInit->rePolarity);
00077
00078 EBI_BankPolaritySet(ebiInit->banks, ebiLineCS, ebiInit->csPolarity);
00079
00080 EBI_BankPolaritySet(ebiInit->banks, ebiLineBL, ebiInit->blPolarity);
00081 #else
00082
00083 EBI_PolaritySet(ebiLineARDY, ebiInit->ardyPolarity);
00084
00085 EBI_PolaritySet(ebiLineALE, ebiInit->alePolarity);
00086
00087 EBI_PolaritySet(ebiLineWE, ebiInit->wePolarity);
00088
00089 EBI_PolaritySet(ebiLineRE, ebiInit->rePolarity);
00090
00091 EBI_PolaritySet(ebiLineCS, ebiInit->csPolarity);
00092 #endif
00093
00094
00095 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00096 if (ebiInit->banks & EBI_BANK0)
00097 {
00098 ctrl &= ~(_EBI_CTRL_MODE_MASK|
00099 _EBI_CTRL_ARDYEN_MASK|
00100 _EBI_CTRL_ARDYTODIS_MASK|
00101 _EBI_CTRL_BL_MASK|
00102 _EBI_CTRL_NOIDLE_MASK|
00103 _EBI_CTRL_BANK0EN_MASK);
00104 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE_SHIFT);
00105 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
00106 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
00107 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL_SHIFT);
00108 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE_SHIFT);
00109 if ( ebiInit->enable)
00110 {
00111 ctrl |= EBI_CTRL_BANK0EN;
00112 }
00113 }
00114 if (ebiInit->banks & EBI_BANK1)
00115 {
00116 ctrl &= ~(_EBI_CTRL_BL1_MASK|
00117 _EBI_CTRL_MODE1_MASK|
00118 _EBI_CTRL_ARDY1EN_MASK|
00119 _EBI_CTRL_ARDYTO1DIS_MASK|
00120 _EBI_CTRL_NOIDLE1_MASK|
00121 _EBI_CTRL_BANK1EN_MASK);
00122 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE1_SHIFT);
00123 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY1EN_SHIFT);
00124 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO1DIS_SHIFT);
00125 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL1_SHIFT);
00126 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE1_SHIFT);
00127 if ( ebiInit->enable)
00128 {
00129 ctrl |= EBI_CTRL_BANK1EN;
00130 }
00131 }
00132 if (ebiInit->banks & EBI_BANK2)
00133 {
00134 ctrl &= ~(_EBI_CTRL_BL2_MASK|
00135 _EBI_CTRL_MODE2_MASK|
00136 _EBI_CTRL_ARDY2EN_MASK|
00137 _EBI_CTRL_ARDYTO2DIS_MASK|
00138 _EBI_CTRL_NOIDLE2_MASK|
00139 _EBI_CTRL_BANK2EN_MASK);
00140 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE2_SHIFT);
00141 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY2EN_SHIFT);
00142 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO2DIS_SHIFT);
00143 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL2_SHIFT);
00144 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE2_SHIFT);
00145 if ( ebiInit->enable)
00146 {
00147 ctrl |= EBI_CTRL_BANK2EN;
00148 }
00149 }
00150 if (ebiInit->banks & EBI_BANK3)
00151 {
00152 ctrl &= ~(_EBI_CTRL_BL3_MASK|
00153 _EBI_CTRL_MODE3_MASK|
00154 _EBI_CTRL_ARDY3EN_MASK|
00155 _EBI_CTRL_ARDYTO3DIS_MASK|
00156 _EBI_CTRL_NOIDLE3_MASK|
00157 _EBI_CTRL_BANK3EN_MASK);
00158 ctrl |= (ebiInit->mode << _EBI_CTRL_MODE3_SHIFT);
00159 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDY3EN_SHIFT);
00160 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTO3DIS_SHIFT);
00161 ctrl |= (ebiInit->blEnable << _EBI_CTRL_BL3_SHIFT);
00162 ctrl |= (ebiInit->noIdle << _EBI_CTRL_NOIDLE3_SHIFT);
00163 if ( ebiInit->enable)
00164 {
00165 ctrl |= EBI_CTRL_BANK3EN;
00166 }
00167 }
00168 #else
00169 ctrl &= ~(_EBI_CTRL_MODE_MASK|
00170 _EBI_CTRL_ARDYEN_MASK|
00171 _EBI_CTRL_ARDYTODIS_MASK|
00172 _EBI_CTRL_BANK0EN_MASK|
00173 _EBI_CTRL_BANK1EN_MASK|
00174 _EBI_CTRL_BANK2EN_MASK|
00175 _EBI_CTRL_BANK3EN_MASK);
00176 if ( ebiInit->enable)
00177 {
00178 if ( ebiInit->banks & EBI_BANK0 )
00179 {
00180 ctrl |= EBI_CTRL_BANK0EN;
00181 }
00182 if ( ebiInit->banks & EBI_BANK1 )
00183 {
00184 ctrl |= EBI_CTRL_BANK1EN;
00185 }
00186 if ( ebiInit->banks & EBI_BANK2 )
00187 {
00188 ctrl |= EBI_CTRL_BANK2EN;
00189 }
00190 if ( ebiInit->banks & EBI_BANK3 )
00191 {
00192 ctrl |= EBI_CTRL_BANK3EN;
00193 }
00194 }
00195 ctrl |= ebiInit->mode;
00196 ctrl |= (ebiInit->ardyEnable << _EBI_CTRL_ARDYEN_SHIFT);
00197 ctrl |= (ebiInit->ardyDisableTimeout << _EBI_CTRL_ARDYTODIS_SHIFT);
00198 #endif
00199
00200
00201 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00202 EBI_BankReadTimingSet(ebiInit->banks,
00203 ebiInit->readSetupCycles,
00204 ebiInit->readStrobeCycles,
00205 ebiInit->readHoldCycles);
00206 EBI_BankReadTimingConfig(ebiInit->banks,
00207 ebiInit->readPageMode,
00208 ebiInit->readPrefetch,
00209 ebiInit->readHalfRE);
00210 EBI_BankWriteTimingSet(ebiInit->banks,
00211 ebiInit->writeSetupCycles,
00212 ebiInit->writeStrobeCycles,
00213 ebiInit->writeHoldCycles);
00214 EBI_BankWriteTimingConfig(ebiInit->banks,
00215 ebiInit->writeBufferDisable,
00216 ebiInit->writeHalfWE);
00217 EBI_BankAddressTimingSet(ebiInit->banks,
00218 ebiInit->addrSetupCycles,
00219 ebiInit->addrHoldCycles);
00220 EBI_BankAddressTimingConfig(ebiInit->banks,
00221 ebiInit->addrHalfALE);
00222 #else
00223 EBI_ReadTimingSet(ebiInit->readSetupCycles,
00224 ebiInit->readStrobeCycles,
00225 ebiInit->readHoldCycles);
00226 EBI_WriteTimingSet(ebiInit->writeSetupCycles,
00227 ebiInit->writeStrobeCycles,
00228 ebiInit->writeHoldCycles);
00229 EBI_AddressTimingSet(ebiInit->addrSetupCycles,
00230 ebiInit->addrHoldCycles);
00231 #endif
00232
00233
00234 EBI->CTRL = ctrl;
00235
00236
00237 switch (ebiInit->mode)
00238 {
00239 case ebiModeD16A16ALE:
00240 case ebiModeD8A24ALE:
00241
00242 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 1);
00243 break;
00244 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00245 case ebiModeD16:
00246 #endif
00247 case ebiModeD8A8:
00248
00249 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_ALEPEN_SHIFT, 0);
00250 break;
00251 }
00252 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00253
00254 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_ALB_MASK) | ebiInit->aLow;
00255 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_APEN_MASK) | ebiInit->aHigh;
00256
00257 EBI->ROUTE = (EBI->ROUTE & ~_EBI_ROUTE_LOCATION_MASK) | ebiInit->location;
00258
00259
00260 if(ctrl & (_EBI_CTRL_BL_MASK|_EBI_CTRL_BL1_MASK|_EBI_CTRL_BL2_MASK|_EBI_CTRL_BL3_MASK))
00261 {
00262 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_BLPEN_SHIFT, ebiInit->blEnable);
00263 }
00264 #endif
00265
00266 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_EBIPEN_SHIFT, 1);
00267
00268
00269 EBI_ChipSelectEnable(ebiInit->csLines, true);
00270 }
00271
00272
00273
00277 void EBI_Disable(void)
00278 {
00279
00280 EBI->ROUTE = _EBI_ROUTE_RESETVALUE;
00281
00282 EBI->CTRL = _EBI_CTRL_RESETVALUE;
00283 }
00284
00285
00286
00296 void EBI_BankEnable(uint32_t banks, bool enable)
00297 {
00298 if (banks & EBI_BANK0)
00299 {
00300 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK0EN_SHIFT, enable);
00301 }
00302 if (banks & EBI_BANK1)
00303 {
00304 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK1EN_SHIFT, enable);
00305 }
00306 if (banks & EBI_BANK2)
00307 {
00308 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK2EN_SHIFT, enable);
00309 }
00310 if (banks & EBI_BANK3)
00311 {
00312 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BANK3EN_SHIFT, enable);
00313 }
00314 }
00315
00316
00317
00327 uint32_t EBI_BankAddress(uint32_t bank)
00328 {
00329 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00330 if(EBI->CTRL & EBI_CTRL_ALTMAP)
00331 {
00332 switch (bank)
00333 {
00334 case EBI_BANK0:
00335 return(EBI_MEM_BASE);
00336
00337 case EBI_BANK1:
00338 return(EBI_MEM_BASE + 0x10000000UL);
00339
00340 case EBI_BANK2:
00341 return(EBI_MEM_BASE + 0x20000000UL);
00342
00343 case EBI_BANK3:
00344 return(EBI_MEM_BASE + 0x30000000UL);
00345
00346 default:
00347 EFM_ASSERT(0);
00348 break;
00349 }
00350 }
00351 #endif
00352 switch (bank)
00353 {
00354 case EBI_BANK0:
00355 return(EBI_MEM_BASE);
00356
00357 case EBI_BANK1:
00358 return(EBI_MEM_BASE + 0x04000000UL);
00359
00360 case EBI_BANK2:
00361 return(EBI_MEM_BASE + 0x08000000UL);
00362
00363 case EBI_BANK3:
00364 return(EBI_MEM_BASE + 0x0C000000UL);
00365
00366 default:
00367 EFM_ASSERT(0);
00368 break;
00369 }
00370 return 0;
00371 }
00372
00373
00374
00384 void EBI_ChipSelectEnable(uint32_t cs, bool enable)
00385 {
00386 if (cs & EBI_CS0)
00387 {
00388 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS0PEN_SHIFT, enable);
00389 }
00390 if (cs & EBI_CS1)
00391 {
00392 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS1PEN_SHIFT, enable);
00393 }
00394 if (cs & EBI_CS2)
00395 {
00396 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS2PEN_SHIFT, enable);
00397 }
00398 if (cs & EBI_CS3)
00399 {
00400 BITBAND_Peripheral(&(EBI->ROUTE), _EBI_ROUTE_CS3PEN_SHIFT, enable);
00401 }
00402 }
00403
00404
00405
00415 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
00416 {
00417 switch (line)
00418 {
00419 case ebiLineARDY:
00420 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
00421 break;
00422 case ebiLineALE:
00423 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_ALEPOL_SHIFT, polarity);
00424 break;
00425 case ebiLineWE:
00426 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_WEPOL_SHIFT, polarity);
00427 break;
00428 case ebiLineRE:
00429 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_REPOL_SHIFT, polarity);
00430 break;
00431 case ebiLineCS:
00432 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_CSPOL_SHIFT, polarity);
00433 break;
00434 #if defined (_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00435 case ebiLineBL:
00436 BITBAND_Peripheral(&(EBI->POLARITY), _EBI_POLARITY_BLPOL_SHIFT, polarity);
00437 break;
00438 case ebiLineTFTVSync:
00439 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
00440 break;
00441 case ebiLineTFTHSync:
00442 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
00443 break;
00444 case ebiLineTFTDataEn:
00445 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
00446 break;
00447 case ebiLineTFTDClk:
00448 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
00449 break;
00450 case ebiLineTFTCS:
00451 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
00452 break;
00453 #endif
00454 default:
00455 EFM_ASSERT(0);
00456 break;
00457 }
00458 }
00459
00460
00461
00475 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles)
00476 {
00477 uint32_t readTiming;
00478
00479
00480 EFM_ASSERT(setupCycles < 4);
00481 EFM_ASSERT(strobeCycles < 16);
00482 EFM_ASSERT(holdCycles < 4);
00483
00484
00485 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
00486 (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
00487 (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
00488
00489
00490 EBI->RDTIMING = (EBI->RDTIMING &
00491 ~(_EBI_RDTIMING_RDSETUP_MASK |
00492 _EBI_RDTIMING_RDSTRB_MASK |
00493 _EBI_RDTIMING_RDHOLD_MASK)) | readTiming;
00494 }
00495
00496
00497
00510 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles)
00511 {
00512 uint32_t writeTiming;
00513
00514
00515 EFM_ASSERT(setupCycles < 4);
00516 EFM_ASSERT(strobeCycles < 16);
00517 EFM_ASSERT(holdCycles < 4);
00518
00519
00520 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
00521 (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
00522 (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
00523
00524 EBI->WRTIMING = (EBI->WRTIMING &
00525 ~(_EBI_WRTIMING_WRSETUP_MASK |
00526 _EBI_WRTIMING_WRSTRB_MASK |
00527 _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming;
00528 }
00529
00530
00531
00542 void EBI_AddressTimingSet(int setupCycles, int holdCycles)
00543 {
00544 uint32_t addressLatchTiming;
00545
00546
00547 EFM_ASSERT(setupCycles < 4);
00548 EFM_ASSERT(holdCycles < 4);
00549
00550
00551 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
00552 (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
00553
00554 EBI->ADDRTIMING = (EBI->ADDRTIMING &
00555 ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
00556 _EBI_ADDRTIMING_ADDRHOLD_MASK)) | addressLatchTiming;
00557 }
00558
00559 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00560
00567 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit)
00568 {
00569 uint32_t ctrl;
00570
00571
00572 EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset);
00573
00574
00575 EBI_TFTSizeSet(ebiTFTInit->hsize,
00576 ebiTFTInit->vsize);
00577 EBI_TFTHPorchSet(ebiTFTInit->hPorchFront,
00578 ebiTFTInit->hPorchBack,
00579 ebiTFTInit->hPulseWidth);
00580 EBI_TFTVPorchSet(ebiTFTInit->vPorchFront,
00581 ebiTFTInit->vPorchBack,
00582 ebiTFTInit->vPulseWidth);
00583
00584
00585 EBI_TFTTimingSet(ebiTFTInit->dclkPeriod,
00586 ebiTFTInit->startPosition,
00587 ebiTFTInit->setupCycles,
00588 ebiTFTInit->holdCycles);
00589
00590
00591 EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity);
00592 EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity);
00593 EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity);
00594 EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity);
00595 EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity);
00596
00597
00598 ctrl =
00599 (uint32_t)(ebiTFTInit->bank) |
00600 (uint32_t)(ebiTFTInit->width) |
00601 (uint32_t)(ebiTFTInit->colSrc) |
00602 (uint32_t)(ebiTFTInit->interleave) |
00603 (uint32_t)(ebiTFTInit->fbTrigger) |
00604 (uint32_t)(ebiTFTInit->shiftDClk == true ? (1 << _EBI_TFTCTRL_SHIFTDCLKEN_SHIFT) : 0) |
00605 (uint32_t)(ebiTFTInit->maskBlend) |
00606 (uint32_t)(ebiTFTInit->driveMode);
00607
00608 EBI->TFTCTRL = ctrl;
00609
00610
00611 if (ebiTFTInit->driveMode != ebiTFTDDModeDisabled)
00612 {
00613 EBI->ROUTE |= (EBI_ROUTE_TFTPEN);
00614 }
00615 }
00616
00617
00618
00627 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical)
00628 {
00629 EFM_ASSERT((horizontal-1) < 1024);
00630 EFM_ASSERT((vertical-1) < 1024);
00631
00632 EBI->TFTSIZE = ((horizontal-1) << _EBI_TFTSIZE_HSZ_SHIFT) |
00633 ((vertical-1) << _EBI_TFTSIZE_VSZ_SHIFT);
00634 }
00635
00636
00647 void EBI_TFTHPorchSet(int front, int back, int pulseWidth)
00648 {
00649 EFM_ASSERT(front < 256);
00650 EFM_ASSERT(back < 256);
00651 EFM_ASSERT((pulseWidth-1) < 128);
00652
00653 EBI->TFTHPORCH = (front << _EBI_TFTHPORCH_HFPORCH_SHIFT) |
00654 (back << _EBI_TFTHPORCH_HBPORCH_SHIFT) |
00655 ((pulseWidth-1) << _EBI_TFTHPORCH_HSYNC_SHIFT);
00656 }
00657
00658
00659
00670 void EBI_TFTVPorchSet(int front, int back, int pulseWidth)
00671 {
00672 EFM_ASSERT(front < 256);
00673 EFM_ASSERT(back < 256);
00674 EFM_ASSERT((pulseWidth-1) < 128);
00675
00676 EBI->TFTVPORCH = (front << _EBI_TFTVPORCH_VFPORCH_SHIFT) |
00677 (back << _EBI_TFTVPORCH_VBPORCH_SHIFT) |
00678 ((pulseWidth-1) << _EBI_TFTVPORCH_VSYNC_SHIFT);
00679 }
00680
00681
00682
00698 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold)
00699 {
00700 EFM_ASSERT(dclkPeriod < 2048);
00701 EFM_ASSERT(start < 2048);
00702 EFM_ASSERT(setup < 4);
00703 EFM_ASSERT(hold < 4);
00704
00705 EBI->TFTTIMING = (dclkPeriod << _EBI_TFTTIMING_DCLKPERIOD_SHIFT) |
00706 (start << _EBI_TFTTIMING_TFTSTART_SHIFT) |
00707 (setup << _EBI_TFTTIMING_TFTSETUP_SHIFT) |
00708 (hold << _EBI_TFTTIMING_TFTHOLD_SHIFT);
00709 }
00710 #endif
00711
00712 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
00713
00729 void EBI_BankReadTimingConfig(uint32_t banks, bool pageMode, bool prefetch, bool halfRE)
00730 {
00731
00732 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
00733
00734
00735 if( banks & EBI_BANK0 )
00736 {
00737 BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
00738 BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
00739 BITBAND_Peripheral(&EBI->RDTIMING, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
00740 }
00741 if( banks & EBI_BANK1 )
00742 {
00743 BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
00744 BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
00745 BITBAND_Peripheral(&EBI->RDTIMING1, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
00746 }
00747 if( banks & EBI_BANK2 )
00748 {
00749 BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
00750 BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
00751 BITBAND_Peripheral(&EBI->RDTIMING2, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
00752 }
00753 if( banks & EBI_BANK3 )
00754 {
00755 BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PAGEMODE_SHIFT, pageMode);
00756 BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_PREFETCH_SHIFT, prefetch);
00757 BITBAND_Peripheral(&EBI->RDTIMING3, _EBI_RDTIMING_HALFRE_SHIFT, halfRE);
00758 }
00759 }
00760
00761
00778 void EBI_BankReadTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
00779 {
00780 uint32_t readTiming;
00781
00782
00783 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
00784
00785
00786 EFM_ASSERT(setupCycles < 4);
00787 EFM_ASSERT(strobeCycles < 64);
00788 EFM_ASSERT(holdCycles < 4);
00789
00790
00791 readTiming = (setupCycles << _EBI_RDTIMING_RDSETUP_SHIFT) |
00792 (strobeCycles << _EBI_RDTIMING_RDSTRB_SHIFT) |
00793 (holdCycles << _EBI_RDTIMING_RDHOLD_SHIFT);
00794
00795 if (banks & EBI_BANK0)
00796 {
00797 EBI->RDTIMING = (EBI->RDTIMING &
00798 ~(_EBI_RDTIMING_RDSETUP_MASK |
00799 _EBI_RDTIMING_RDSTRB_MASK |
00800 _EBI_RDTIMING_RDHOLD_MASK)) | readTiming;
00801 }
00802 if (banks & EBI_BANK1)
00803 {
00804 EBI->RDTIMING1 = (EBI->RDTIMING1 &
00805 ~(_EBI_RDTIMING1_RDSETUP_MASK |
00806 _EBI_RDTIMING1_RDSTRB_MASK |
00807 _EBI_RDTIMING1_RDHOLD_MASK)) | readTiming;
00808 }
00809 if (banks & EBI_BANK2)
00810 {
00811 EBI->RDTIMING2 = (EBI->RDTIMING2 &
00812 ~(_EBI_RDTIMING2_RDSETUP_MASK |
00813 _EBI_RDTIMING2_RDSTRB_MASK |
00814 _EBI_RDTIMING2_RDHOLD_MASK)) | readTiming;
00815 }
00816 if (banks & EBI_BANK3)
00817 {
00818 EBI->RDTIMING3 = (EBI->RDTIMING3 &
00819 ~(_EBI_RDTIMING3_RDSETUP_MASK |
00820 _EBI_RDTIMING3_RDSTRB_MASK |
00821 _EBI_RDTIMING3_RDHOLD_MASK)) | readTiming;
00822 }
00823 }
00824
00825
00826
00839 void EBI_BankWriteTimingConfig(uint32_t banks, bool writeBufDisable, bool halfWE)
00840 {
00841
00842 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
00843
00844
00845 if( banks & EBI_BANK0 )
00846 {
00847 BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
00848 BITBAND_Peripheral(&EBI->WRTIMING, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
00849 }
00850 if( banks & EBI_BANK1 )
00851 {
00852 BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
00853 BITBAND_Peripheral(&EBI->WRTIMING1, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
00854 }
00855 if( banks & EBI_BANK2 )
00856 {
00857 BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
00858 BITBAND_Peripheral(&EBI->WRTIMING2, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
00859 }
00860 if( banks & EBI_BANK3 )
00861 {
00862 BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_WBUFDIS_SHIFT, writeBufDisable);
00863 BITBAND_Peripheral(&EBI->WRTIMING3, _EBI_WRTIMING_HALFWE_SHIFT, halfWE);
00864 }
00865 }
00866
00867
00868
00884 void EBI_BankWriteTimingSet(uint32_t banks, int setupCycles, int strobeCycles, int holdCycles)
00885 {
00886 uint32_t writeTiming;
00887
00888
00889 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
00890
00891
00892 EFM_ASSERT(setupCycles < 4);
00893 EFM_ASSERT(strobeCycles < 64);
00894 EFM_ASSERT(holdCycles < 4);
00895
00896
00897 writeTiming = (setupCycles << _EBI_WRTIMING_WRSETUP_SHIFT) |
00898 (strobeCycles << _EBI_WRTIMING_WRSTRB_SHIFT) |
00899 (holdCycles << _EBI_WRTIMING_WRHOLD_SHIFT);
00900
00901 if (banks & EBI_BANK0)
00902 {
00903 EBI->WRTIMING = (EBI->WRTIMING &
00904 ~(_EBI_WRTIMING_WRSETUP_MASK |
00905 _EBI_WRTIMING_WRSTRB_MASK |
00906 _EBI_WRTIMING_WRHOLD_MASK)) | writeTiming;
00907 }
00908 if (banks & EBI_BANK1)
00909 {
00910 EBI->WRTIMING1 = (EBI->WRTIMING1 &
00911 ~(_EBI_WRTIMING1_WRSETUP_MASK |
00912 _EBI_WRTIMING1_WRSTRB_MASK |
00913 _EBI_WRTIMING1_WRHOLD_MASK)) | writeTiming;
00914 }
00915 if (banks & EBI_BANK2)
00916 {
00917 EBI->WRTIMING2 = (EBI->WRTIMING2 &
00918 ~(_EBI_WRTIMING2_WRSETUP_MASK |
00919 _EBI_WRTIMING2_WRSTRB_MASK |
00920 _EBI_WRTIMING2_WRHOLD_MASK)) | writeTiming;
00921 }
00922 if (banks & EBI_BANK3)
00923 {
00924 EBI->WRTIMING3 = (EBI->WRTIMING3 &
00925 ~(_EBI_WRTIMING3_WRSETUP_MASK |
00926 _EBI_WRTIMING3_WRSTRB_MASK |
00927 _EBI_WRTIMING3_WRHOLD_MASK)) | writeTiming;
00928 }
00929 }
00930
00931
00932
00942 void EBI_BankAddressTimingConfig(uint32_t banks, bool halfALE)
00943 {
00944
00945 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
00946
00947 if( banks & EBI_BANK0 )
00948 {
00949 BITBAND_Peripheral(&EBI->ADDRTIMING, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
00950 }
00951 if( banks & EBI_BANK1 )
00952 {
00953 BITBAND_Peripheral(&EBI->ADDRTIMING1, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
00954 }
00955 if( banks & EBI_BANK2 )
00956 {
00957 BITBAND_Peripheral(&EBI->ADDRTIMING2, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
00958 }
00959 if( banks & EBI_BANK3 )
00960 {
00961 BITBAND_Peripheral(&EBI->ADDRTIMING3, _EBI_ADDRTIMING_HALFALE_SHIFT, halfALE);
00962 }
00963 }
00964
00965
00966
00980 void EBI_BankAddressTimingSet(uint32_t banks, int setupCycles, int holdCycles)
00981 {
00982 uint32_t addressLatchTiming;
00983
00984
00985 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
00986
00987
00988 EFM_ASSERT(setupCycles < 4);
00989 EFM_ASSERT(holdCycles < 4);
00990
00991
00992 addressLatchTiming = (setupCycles << _EBI_ADDRTIMING_ADDRSETUP_SHIFT) |
00993 (holdCycles << _EBI_ADDRTIMING_ADDRHOLD_SHIFT);
00994
00995 if (banks & EBI_BANK0)
00996 {
00997 EBI->ADDRTIMING = (EBI->ADDRTIMING &
00998 ~(_EBI_ADDRTIMING_ADDRSETUP_MASK |
00999 _EBI_ADDRTIMING_ADDRHOLD_MASK)) | addressLatchTiming;
01000 }
01001 if (banks & EBI_BANK1)
01002 {
01003 EBI->ADDRTIMING1 = (EBI->ADDRTIMING1 &
01004 ~(_EBI_ADDRTIMING1_ADDRSETUP_MASK |
01005 _EBI_ADDRTIMING1_ADDRHOLD_MASK)) | addressLatchTiming;
01006 }
01007 if (banks & EBI_BANK2)
01008 {
01009 EBI->ADDRTIMING2 = (EBI->ADDRTIMING2 &
01010 ~(_EBI_ADDRTIMING2_ADDRSETUP_MASK |
01011 _EBI_ADDRTIMING2_ADDRHOLD_MASK)) | addressLatchTiming;
01012 }
01013 if (banks & EBI_BANK3)
01014 {
01015 EBI->ADDRTIMING3 = (EBI->ADDRTIMING3 &
01016 ~(_EBI_ADDRTIMING3_ADDRSETUP_MASK |
01017 _EBI_ADDRTIMING3_ADDRHOLD_MASK)) | addressLatchTiming;
01018 }
01019 }
01020
01021
01022
01036 void EBI_BankPolaritySet(uint32_t banks, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity)
01037 {
01038 uint32_t bankSet = 0;
01039 volatile uint32_t *polRegister = 0;
01040
01041
01042 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
01043
01044 while (banks)
01045 {
01046 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
01047 if (banks & EBI_BANK0)
01048 {
01049 polRegister = &EBI->POLARITY;
01050 bankSet = EBI_BANK0;
01051 }
01052 if (banks & EBI_BANK1)
01053 {
01054 polRegister = &EBI->POLARITY1;
01055 bankSet = EBI_BANK1;
01056 }
01057 if (banks & EBI_BANK2)
01058 {
01059 polRegister = &EBI->POLARITY2;
01060 bankSet = EBI_BANK2;
01061 }
01062 if (banks & EBI_BANK3)
01063 {
01064 polRegister = &EBI->POLARITY3;
01065 bankSet = EBI_BANK3;
01066 }
01067 #else
01068 polRegister = &EBI->POLARITY;
01069 banks = 0;
01070 #endif
01071
01072
01073 switch (line)
01074 {
01075 case ebiLineARDY:
01076 BITBAND_Peripheral(polRegister, _EBI_POLARITY_ARDYPOL_SHIFT, polarity);
01077 break;
01078 case ebiLineALE:
01079 BITBAND_Peripheral(polRegister, _EBI_POLARITY_ALEPOL_SHIFT, polarity);
01080 break;
01081 case ebiLineWE:
01082 BITBAND_Peripheral(polRegister, _EBI_POLARITY_WEPOL_SHIFT, polarity);
01083 break;
01084 case ebiLineRE:
01085 BITBAND_Peripheral(polRegister, _EBI_POLARITY_REPOL_SHIFT, polarity);
01086 break;
01087 case ebiLineCS:
01088 BITBAND_Peripheral(polRegister, _EBI_POLARITY_CSPOL_SHIFT, polarity);
01089 break;
01090 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
01091 case ebiLineBL:
01092 BITBAND_Peripheral(polRegister, _EBI_POLARITY_BLPOL_SHIFT, polarity);
01093 break;
01094 case ebiLineTFTVSync:
01095 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_VSYNCPOL_SHIFT, polarity);
01096 break;
01097 case ebiLineTFTHSync:
01098 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_HSYNCPOL_SHIFT, polarity);
01099 break;
01100 case ebiLineTFTDataEn:
01101 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DATAENPOL_SHIFT, polarity);
01102 break;
01103 case ebiLineTFTDClk:
01104 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_DCLKPOL_SHIFT, polarity);
01105 break;
01106 case ebiLineTFTCS:
01107 BITBAND_Peripheral(&(EBI->TFTPOLARITY), _EBI_TFTPOLARITY_CSPOL_SHIFT, polarity);
01108 break;
01109 #endif
01110 default:
01111 EFM_ASSERT(0);
01112 break;
01113 }
01114 banks = banks & (~bankSet);
01115 }
01116 }
01117
01118
01119
01130 void EBI_BankByteLaneEnable(uint32_t banks, bool enable)
01131 {
01132
01133 EFM_ASSERT((banks & ~(EBI_BANK0 | EBI_BANK1 | EBI_BANK2 | EBI_BANK3)) == 0);
01134
01135
01136 if (banks & EBI_BANK0)
01137 {
01138 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL_SHIFT, enable);
01139 }
01140 if (banks & EBI_BANK1)
01141 {
01142 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL1_SHIFT, enable);
01143 }
01144 if (banks & EBI_BANK2)
01145 {
01146 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL2_SHIFT, enable);
01147 }
01148 if (banks & EBI_BANK3)
01149 {
01150 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_BL3_SHIFT, enable);
01151 }
01152 }
01153
01154
01155
01163 void EBI_AltMapEnable(bool enable)
01164 {
01165 BITBAND_Peripheral(&(EBI->CTRL), _EBI_CTRL_ALTMAP_SHIFT, enable);
01166 }
01167
01168 #endif
01169
01173 #endif