Revision History
Capabilities
This driver supports Asynchronous mode.
Instances
Hardware resource relating to driver instance is shown in the table below:
Driver Instance | Hardware Resource |
Driver_USART1 | USART1 |
Driver_USART2 | USART2 |
Driver_USART3 | USART3 |
Driver_USART4 | UART4 |
Driver_USART5 | UART5 |
Driver_USART6 | USART6 |
Driver_USART7 | UART7 |
Driver_USART8 | UART8 |
Driver_USART9 | UART9 |
Driver_USART10 | USART10 |
Driver_USART11 | USART11 |
Driver_USART12 | UART12 |
Driver_USART13 | LPUART1 |
- Note
- The CMSIS Driver:USART (API):USART component in the Manage Run-Time Environment dialog adds multiple C source files to the project.
The interface selection in STM32CubeMX selects the actual implementation that is compiled: IrDA, SmartCard, UART or USART.
Limitations
STM32 HAL limitations:
- Rx Timeout event disables further reception
- No callback available for Rx Idle event
- Stop bits 0.5 and 1.5 are not supported
- Manual control of modem lines is not supported
- Break character is handled as framing error
Configuration
STM32CubeMX
The USART driver requires:
- UART/USART peripheral clock
- UART/USART peripheral configured as Asynchronous
- optional Hardware Flow Control
- UART/USART TX, Rx and optional Hardware flow Control pins
- optional DMA configuration for transfers
NUCLEO-H563ZI Board Configuration
These settings are relevant for this board, for different board please refer to the board schematic for proper configuration.
Link to NUCLEO-H563ZI board schematic.
STM32CubeMX
Required peripherals for the NUCLEO-H563ZI board are listed in the table below:
Peripheral | Mode | Description |
USART2 | Asynchronous | USART2 Controller |
PD5 | Alternate Function Push Pull | USART2 TX Pin |
PD6 | Alternate Function Push Pull | USART2 RX Pin |
- Note
- All settings have to be configured as described in the procedure below. Important settings, typically the ones different from default, are emphasized in bold.
Pinout & Configuration tab
- In the Pinout view window click on a pin and select it's functionality:
Pin | Functionality |
PD5 | USART2_TX |
PD6 | USART2_RX |
Under Categories: Connectivity select USART2:
Mode:
- Mode: Asynchronous
- Hardware Flow Control (RS232): Disable
- Hardware Flow Control (RS485): unchecked
- Software NSS Management: unchecked
Configuration:
- Parameter Settings: not used
- User Constants: not used
- NVIC Settings: configured in later step (under Category: System Core: NVIC)
- DMA Settings: configured in later step (under Category: System Core: GPDMA1)
- GPIO Settings:
Pin Name | Signal on Pin | Pin Context.. | Pin Priv.. | GPIO output.. | GPIO mode | GPIO Pull-up/Pull.. | Maximum out.. | Fast Mode | User Label |
PD5 | USART2_TX | n/a | n/a | n/a | Alternate Function Push Pull | No pull-up and no.. | Low | n/a | . |
PD6 | USART2_RX | n/a | n/a | n/a | Alternate Function Push Pull | No pull-up and no.. | Low | n/a | . |
Under Categories: System Core select GPDMA1:
Mode:
- Channel 0 - 2 Words Internal FIFO: Standard Request Mode
- Channel 1 - 2 Words Internal FIFO: Standard Request Mode
Configuration:
- All Channels: not used
- Security:
- CH1:
- Enable Channel as Privileged: NON PRIVILEGED
- CH0:
- Enable Channel as Privileged: NON PRIVILEGED
- CH0:
- Circular configuration:
- Request Configuration:
- Request: USART2_TX
- DMA Handle in IP Structure: hdmatx
- Block HW request protocol: Single/Burst Level
- Channel configuration:
- Priority: Low
- Transaction Mode: Normal
- Direction: Memory to Peripheral
- Source Data Setting:
- Source Address Increment After Transfer: Enabled
- Data Width: Byte
- Burst Length: 1
- Allocated Port for Transfer: Port 0
- Destination Data Setting:
- Destination Address Increment After Transfer: Disabled
- Data Width: Byte
- Burst Length: 1
- Allocated Port for Transfer: Port 0
- Data Handling:
- Data Handling Configuration: Disable
- Trigger:
- Trigger Configuration: Disable
- Transfer Event Configuration:
- Transfer Event Generation: The TC (and the HT) ...
- CH1:
- Circular configuration:
- Request Configuration:
- Request: USART2_RX
- DMA Handle in IP Structure: hdmarx
- Block HW request protocol: Single/Burst Level
- Channel configuration:
- Priority: Low
- Transaction Mode: Normal
- Direction: Peripheral to Memory
- Source Data Setting:
- Source Address Increment After Transfer: Disabled
- Data Width: Byte
- Burst Length: 1
- Allocated Port for Transfer: Port 1
- Destination Data Setting:
- Destination Address Increment After Transfer: Enabled
- Data Width: Byte
- Burst Length: 1
- Allocated Port for Transfer: Port 1
- Data Handling:
- Data Handling Configuration: Disable
- Trigger:
- Trigger Configuration: Disable
- Transfer Event Configuration:
- Transfer Event Generation: The TC (and the HT) ...
- User Constants: not used
Under Categories: System Core select NVIC:
Configuration:
- NVIC:
NVIC Interrupt Table | Enabled | Preemption Priority | Sub Priority |
GPDMA1 Channel 0 global interrupt | checked | 0 | 0 |
GPDMA1 Channel 1 global interrupt | checked | 0 | 0 |
USART2 global interrupt | checked | 0 | 0 |
- Code generation:
Enabled interrupt table | Select for.. | Generate Enable in.. | Generate IRQ h.. | Call HAL handler |
GPDMA1 Channel 0 global interrupt | unchecked | checked | checked | checked |
GPDMA1 Channel 1 global interrupt | unchecked | checked | checked | checked |
USART2 global interrupt | unchecked | checked | checked | checked |
Clock Configuration tab
- Configure To USART2 (MHz): 250
Project Manager tab
Under Advanced Settings:
Generated Function Calls:
Generate Code | Function Name | Peripheral Inst.. | Do not generate .. | Visibility (Static) |
checked | MX_USART2_UART_Init | USART2 | checked | checked |
Generate Code
Generate source code by clicking on the GENERATE CODE button on the toolbar.
Validation
Results of the CMSIS-Driver Validation for this driver can be found in the USART_TestReport.txt file.