STM32Cube  Version 1.2.0
Create Projects for STM32H5 Series with STM32Cube HAL and STM32CubeMX
SPI

Revision History

  • Version 1.0
    • Initial release

Capabilities

This driver supports Master and Slave modes.

Instances

Hardware resource relating to driver instance is shown in the table below:

Driver Instance Hardware Resource
Driver_SPI1 SPI1
Driver_SPI2 SPI2
Driver_SPI3 SPI3
Driver_SPI4 SPI4
Driver_SPI5 SPI5
Driver_SPI6 SPI6

Limitations

Hardware limitations:

  • Number of items to send, receive or transmit for SPI4/SPI5/SPI6 is limited to 1023

STM32 HAL limitations:

  • Number of items to send, receive or transmit is limited to 65535
  • Mode Fault and Data Lost events can be detected only when reception is active
  • Settings changes using Control function activate upon send/receive/transfer operation start
Note
If SPI driver is used in IRQ mode, ensure that it has higher priority then any IRQ routine requiring longer processing time, because such IRQ routine can prevent SPI IRQ routine to correctly handle reception thus fail to receive all data correctly or fail to generate ARM_SPI_EVENT_TRANSFER_COMPLETE event.
The previous limitation can also be avoided by using SPI driver in DMA mode.

Configuration

STM32CubeMX

The SPI driver requires:

  • SPI peripheral clock
  • SPI peripheral configured as Full-Duplex Master/Slave
  • SPI MISO, MOSI, SCK and NSS pins
  • optional DMA configuration for transfers

NUCLEO-H563ZI Board Configuration

These settings are relevant for this board, for different board please refer to the board schematic for proper configuration.

Link to NUCLEO-H563ZI board schematic.

STM32CubeMX

Required peripherals for the NUCLEO-H563ZI board are listed in the table below:

Peripheral Mode Description
SPI1 Full-Duplex Master SPI1 Controller
PD10 Alternate Function Push Pull SPI1 NSS Pin
PA15 Alternate Function Push Pull SPI1 SCK Pin
PG9 Alternate Function Push Pull SPI1 MISO Pin
PB5 Alternate Function Push Pull SPI1 MOSI Pin
Note
All settings have to be configured as described in the procedure below. Important settings, typically the ones different from default, are emphasized in bold.

Pinout & Configuration tab

  1. In the Pinout view window click on a pin and select it's functionality:
    Pin Functionality
    PD10 SPI1_NSS
    PA5 SPI1_SCK
    PG9 SPI1_MISO
    PB5 SPI1_MOSI

  2. Under Categories: Connectivity select SPI1:

    Mode:

    • Mode: Full-Duplex Master
    • Hardware NSS Signal: Hardware NSS Output Signal
    • Hardware RDY Signal: Disable

    Configuration:

    • Parameter Settings: not used
    • User Constants: not used
    • NVIC Settings: configured in later step (under Category: System Core: NVIC)
    • DMA Settings: configured in later step (under Category: System Core: GPDMA1)
    • GPIO Settings:
      Pin Name Signal on Pin Pin Context.. Pin Priv.. GPIO output.. GPIO mode GPIO Pull-up/Pull.. Maximum out.. Fast Mode User Label
      PD10 SPI1_NSS n/a n/a n/a Alternate Function Push Pull No pull-up and no.. Medium n/a .
      PA5 SPI1_SCK n/a n/a n/a Alternate Function Push Pull No pull-up and no.. Medium n/a .
      PG9 SPI1_MISO n/a n/a n/a Alternate Function Push Pull No pull-up and no.. Medium n/a .
      PB5 SPI1_MOSI n/a n/a n/a Alternate Function Push Pull No pull-up and no.. Medium n/a .

  3. Under Categories: System Core select GPDMA1:

    Mode:

    • Channel 0 - 2 Words Internal FIFO: Standard Request Mode
    • Channel 1 - 2 Words Internal FIFO: Standard Request Mode

    Configuration:

    • All Channels: not used
    • Security:
      • CH1:
        • Enable Channel as Privileged: NON PRIVILEGED
      • CH0:
        • Enable Channel as Privileged: NON PRIVILEGED
    • CH0:
      • Circular configuration:
        • Circular Mode: Disable
      • Request Configuration:
        • Request: SPI1_TX
        • DMA Handle in IP Structure: hdmatx
        • Block HW request protocol: Single/Burst Level
      • Channel configuration:
        • Priority: Low
        • Transaction Mode: Normal
        • Direction: Memory to Peripheral
      • Source Data Setting:
        • Source Address Increment After Transfer: Enabled
        • Data Width: Byte
        • Burst Length: 1
        • Allocated Port for Transfer: Port 0
      • Destination Data Setting:
        • Destination Address Increment After Transfer: Disabled
        • Data Width: Byte
        • Burst Length: 1
        • Allocated Port for Transfer: Port 0
      • Data Handling:
        • Data Handling Configuration: Disable
      • Trigger:
        • Trigger Configuration: Disable
      • Transfer Event Configuration:
        • Transfer Event Generation: The TC (and the HT) ...
    • CH1:
      • Circular configuration:
        • Circular Mode: Disable
      • Request Configuration:
        • Request: SPI1_RX
        • DMA Handle in IP Structure: hdmarx
        • Block HW request protocol: Single/Burst Level
      • Channel configuration:
        • Priority: Low
        • Transaction Mode: Normal
        • Direction: Peripheral to Memory
      • Source Data Setting:
        • Source Address Increment After Transfer: Disabled
        • Data Width: Byte
        • Burst Length: 1
        • Allocated Port for Transfer: Port 1
      • Destination Data Setting:
        • Destination Address Increment After Transfer: Enabled
        • Data Width: Byte
        • Burst Length: 1
        • Allocated Port for Transfer: Port 1
      • Data Handling:
        • Data Handling Configuration: Disable
      • Trigger:
        • Trigger Configuration: Disable
      • Transfer Event Configuration:
        • Transfer Event Generation: The TC (and the HT) ...
    • User Constants: not used

  4. Under Categories: System Core select NVIC:

    Configuration:

    • NVIC:
      NVIC Interrupt Table Enabled Preemption Priority Sub Priority
      GPDMA1 Channel 0 global interrupt checked 0 0
      GPDMA1 Channel 1 global interrupt checked 0 0
      SPI1 global interrupt checked 0 0
    • Code generation:
      Enabled interrupt table Select for.. Generate Enable in.. Generate IRQ h.. Call HAL handler
      GPDMA1 Channel 0 global interrupt unchecked checked checked checked
      GPDMA1 Channel 1 global interrupt unchecked checked checked checked
      SPI1 global interrupt unchecked checked checked checked

Clock Configuration tab

  1. Configure To SPI1 (MHz): 250

Project Manager tab

  1. Under Advanced Settings:

    Generated Function Calls:

    Generate Code Function Name Peripheral Inst.. Do not generate .. Visibility (Static)
    checked MX_SPI1_Init SPI1 checked checked


    Note
    If you use HAL based driver in parallel with the CMSIS Driver (for different instances) and if the HAL_SPI_RegisterCallback function is called then select ENABLE under Register Callback for the SPI peripheral.

Generate Code

Generate source code by clicking on the GENERATE CODE button on the toolbar.

Validation

Results of the CMSIS-Driver Validation for this driver can be found in the SPI_TestReport.txt file.